-o -name '.*.d' -o -name '.*.tmp' -o -name '*.mod.c' \
-o -name '*.symtypes' -o -name 'modules.order' \
-o -name modules.builtin -o -name '.tmp_*.o.*' \
+ -o -name 'dsdt.aml' -o -name 'dsdt.asl.tmp' -o -name 'dsdt.c' \
-o -name '*.gcno' \) -type f -print | xargs rm -f
# mrproper - Delete all generated files, including .config
CONFIG_CMD_ECHO echo arguments
CONFIG_CMD_EDITENV edit env variable
CONFIG_CMD_EEPROM * EEPROM read/write support
+ CONFIG_CMD_EEPROM_LAYOUT* EEPROM layout aware commands
CONFIG_CMD_ELF * bootelf, bootvx
CONFIG_CMD_ENV_CALLBACK * display details about env callbacks
CONFIG_CMD_ENV_FLAGS * display details about env flags
CONFIG_CMD_RUN run command in env variable
CONFIG_CMD_SANDBOX * sb command to access sandbox features
CONFIG_CMD_SAVES * save S record dump
- CONFIG_CMD_SCSI * SCSI Support
+ CONFIG_SCSI * SCSI Support
CONFIG_CMD_SDRAM * print SDRAM configuration information
(requires CONFIG_CMD_I2C)
CONFIG_CMD_SETGETDCR Support for DCR Register access
CONFIG_MTD_PARTITIONS Memory Technology Device partition table.
If IDE or SCSI support is enabled (CONFIG_CMD_IDE or
- CONFIG_CMD_SCSI) you must configure support for at
+ CONFIG_SCSI) you must configure support for at
least one non-MTD partition type as well.
- IDE Reset method:
consider that a completely unreadable NAND block is bad,
and thus should be skipped silently.
+ CONFIG_SPL_ABORT_ON_RAW_IMAGE
+ When defined, SPL will proceed to another boot method
+ if the image it has loaded does not have a signature.
+
CONFIG_SPL_RELOC_STACK
Adress of the start of the stack SPL will use after
relocation. If unspecified, this is equal to
{
int *c;
- if ((c = (int *)va_arg(ap, u_int32_t)) == NULL)
+ if ((c = (int *)va_arg(ap, uintptr_t)) == NULL)
return API_EINVAL;
*c = getc();
{
int *t;
- if ((t = (int *)va_arg(ap, u_int32_t)) == NULL)
+ if ((t = (int *)va_arg(ap, uintptr_t)) == NULL)
return API_EINVAL;
*t = tstc();
{
char *c;
- if ((c = (char *)va_arg(ap, u_int32_t)) == NULL)
+ if ((c = (char *)va_arg(ap, uintptr_t)) == NULL)
return API_EINVAL;
putc(*c);
{
char *s;
- if ((s = (char *)va_arg(ap, u_int32_t)) == NULL)
+ if ((s = (char *)va_arg(ap, uintptr_t)) == NULL)
return API_EINVAL;
puts(s);
{
struct sys_info *si;
- si = (struct sys_info *)va_arg(ap, u_int32_t);
+ si = (struct sys_info *)va_arg(ap, uintptr_t);
if (si == NULL)
return API_ENOMEM;
{
unsigned long *d;
- if ((d = (unsigned long *)va_arg(ap, u_int32_t)) == NULL)
+ if ((d = (unsigned long *)va_arg(ap, unsigned long)) == NULL)
return API_EINVAL;
udelay(*d);
{
unsigned long *base, *cur;
- cur = (unsigned long *)va_arg(ap, u_int32_t);
+ cur = (unsigned long *)va_arg(ap, unsigned long);
if (cur == NULL)
return API_EINVAL;
- base = (unsigned long *)va_arg(ap, u_int32_t);
+ base = (unsigned long *)va_arg(ap, unsigned long);
if (base == NULL)
return API_EINVAL;
struct device_info *di;
/* arg is ptr to the device_info struct we are going to fill out */
- di = (struct device_info *)va_arg(ap, u_int32_t);
+ di = (struct device_info *)va_arg(ap, uintptr_t);
if (di == NULL)
return API_EINVAL;
int err = 0;
/* arg is ptr to the device_info struct */
- di = (struct device_info *)va_arg(ap, u_int32_t);
+ di = (struct device_info *)va_arg(ap, uintptr_t);
if (di == NULL)
return API_EINVAL;
int err = 0;
/* arg is ptr to the device_info struct */
- di = (struct device_info *)va_arg(ap, u_int32_t);
+ di = (struct device_info *)va_arg(ap, uintptr_t);
if (di == NULL)
return API_EINVAL;
int err = 0;
/* 1. arg is ptr to the device_info struct */
- di = (struct device_info *)va_arg(ap, u_int32_t);
+ di = (struct device_info *)va_arg(ap, uintptr_t);
if (di == NULL)
return API_EINVAL;
return API_ENODEV;
/* 2. arg is ptr to buffer from where to get data to write */
- buf = (void *)va_arg(ap, u_int32_t);
+ buf = (void *)va_arg(ap, uintptr_t);
if (buf == NULL)
return API_EINVAL;
/* 3. arg is length of buffer */
- len = (int *)va_arg(ap, u_int32_t);
+ len = (int *)va_arg(ap, uintptr_t);
if (len == NULL)
return API_EINVAL;
if (*len <= 0)
int *len_net, *act_len_net;
/* 1. arg is ptr to the device_info struct */
- di = (struct device_info *)va_arg(ap, u_int32_t);
+ di = (struct device_info *)va_arg(ap, uintptr_t);
if (di == NULL)
return API_EINVAL;
return API_ENODEV;
/* 2. arg is ptr to buffer from where to put the read data */
- buf = (void *)va_arg(ap, u_int32_t);
+ buf = (void *)va_arg(ap, uintptr_t);
if (buf == NULL)
return API_EINVAL;
if (di->type & DEV_TYP_STOR) {
/* 3. arg - ptr to var with # of blocks to read */
- len_stor = (lbasize_t *)va_arg(ap, u_int32_t);
+ len_stor = (lbasize_t *)va_arg(ap, uintptr_t);
if (!len_stor)
return API_EINVAL;
if (*len_stor <= 0)
return API_EINVAL;
/* 4. arg - ptr to var with start block */
- start = (lbastart_t *)va_arg(ap, u_int32_t);
+ start = (lbastart_t *)va_arg(ap, uintptr_t);
/* 5. arg - ptr to var where to put the len actually read */
- act_len_stor = (lbasize_t *)va_arg(ap, u_int32_t);
+ act_len_stor = (lbasize_t *)va_arg(ap, uintptr_t);
if (!act_len_stor)
return API_EINVAL;
} else if (di->type & DEV_TYP_NET) {
/* 3. arg points to the var with length of packet to read */
- len_net = (int *)va_arg(ap, u_int32_t);
+ len_net = (int *)va_arg(ap, uintptr_t);
if (!len_net)
return API_EINVAL;
if (*len_net <= 0)
return API_EINVAL;
/* 4. - ptr to var where to put the len actually read */
- act_len_net = (int *)va_arg(ap, u_int32_t);
+ act_len_net = (int *)va_arg(ap, uintptr_t);
if (!act_len_net)
return API_EINVAL;
{
char *name, **value;
- if ((name = (char *)va_arg(ap, u_int32_t)) == NULL)
+ if ((name = (char *)va_arg(ap, uintptr_t)) == NULL)
return API_EINVAL;
- if ((value = (char **)va_arg(ap, u_int32_t)) == NULL)
+ if ((value = (char **)va_arg(ap, uintptr_t)) == NULL)
return API_EINVAL;
*value = getenv(name);
{
char *name, *value;
- if ((name = (char *)va_arg(ap, u_int32_t)) == NULL)
+ if ((name = (char *)va_arg(ap, uintptr_t)) == NULL)
return API_EINVAL;
- if ((value = (char *)va_arg(ap, u_int32_t)) == NULL)
+ if ((value = (char *)va_arg(ap, uintptr_t)) == NULL)
return API_EINVAL;
setenv(name, value);
int i, n;
char *last, **next;
- last = (char *)va_arg(ap, u_int32_t);
+ last = (char *)va_arg(ap, unsigned long);
- if ((next = (char **)va_arg(ap, u_int32_t)) == NULL)
+ if ((next = (char **)va_arg(ap, uintptr_t)) == NULL)
return API_EINVAL;
if (last == NULL)
}
setenv_hex("api_address", (unsigned long)sig);
- debugf("API sig @ 0x%08x\n", sig);
+ debugf("API sig @ 0x%lX\n", (unsigned long)sig);
memcpy(sig->magic, API_SIG_MAGIC, 8);
sig->version = API_SIG_VERSION;
sig->syscall = &syscall;
sig->checksum = 0;
sig->checksum = crc32(0, (unsigned char *)sig,
sizeof(struct api_signature));
- debugf("syscall entry: 0x%08x\n", sig->syscall);
+ debugf("syscall entry: 0x%lX\n", (unsigned long)sig->syscall);
}
void platform_set_mr(struct sys_info *si, unsigned long start, unsigned long size,
specs[ENUM_SATA].type = DEV_TYP_STOR | DT_STOR_SATA;
specs[ENUM_SATA].name = "sata";
#endif
-#if defined(CONFIG_CMD_SCSI)
+#if defined(CONFIG_SCSI)
specs[ENUM_SCSI].max_dev = CONFIG_SYS_SCSI_MAX_DEVICE;
specs[ENUM_SCSI].enum_started = 0;
specs[ENUM_SCSI].enum_ended = 0;
select DM
select OF_CONTROL
select DM_SERIAL
+ select SUPPORT_SPL
config TEGRA
bool "NVIDIA Tegra"
switch (spl_boot_device()) {
case BOOT_DEVICE_MMC1:
#ifdef CONFIG_SPL_FAT_SUPPORT
- return MMCSD_MODE_FAT;
+ return MMCSD_MODE_FS;
#else
return MMCSD_MODE_RAW;
#endif
PLL_ENET_MAIN_250M_CLK, PLL_AUDIO_MAIN_CLK}
},
{AHB_CLK_ROOT, CCM_AHB_CHANNEL,
- {OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_DRAM_MAIN_533M_CLK,
+ {OSC_24M_CLK, PLL_SYS_PFD2_270M_CLK, PLL_DRAM_MAIN_533M_CLK,
PLL_SYS_PFD0_392M_CLK, PLL_ENET_MAIN_125M_CLK, PLL_USB_MAIN_480M_CLK,
PLL_AUDIO_MAIN_CLK, PLL_VIDEO_MAIN_CLK}
},
flush_dcache_range((ulong)level0_table,
(ulong)level0_table + gd->arch.tlb_size);
-#ifdef CONFIG_SYS_DPAA_FMAN
- flush_dcache_all();
-#endif
/* point TTBR to the new table */
set_ttbr_tcr_mair(el, (u64)level0_table, LAYERSCAPE_TCR_FINAL,
MEMORY_ATTRIBUTES);
#ifdef CONFIG_MP
#include <asm/arch/mp.h>
#endif
+#include <fsl_sec.h>
+#include <asm/arch-fsl-layerscape/soc.h>
int fdt_fixup_phy_connection(void *blob, int offset, phy_interface_t phyc)
{
void ft_cpu_setup(void *blob, bd_t *bd)
{
+#ifdef CONFIG_FSL_LSCH2
+ struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ unsigned int svr = in_be32(&gur->svr);
+
+ /* delete crypto node if not on an E-processor */
+ if (!IS_E_PROCESSOR(svr))
+ fdt_fixup_crypto_node(blob, 0);
+#if CONFIG_SYS_FSL_SEC_COMPAT >= 4
+ else {
+ ccsr_sec_t __iomem *sec;
+
+ sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
+ fdt_fixup_crypto_node(blob, sec_in32(&sec->secvid_ms));
+ }
+#endif
+#endif
+
#ifdef CONFIG_MP
ft_fixup_cpu(blob);
#endif
#include <asm/io.h>
#include <asm/global_data.h>
#include <asm/arch-fsl-layerscape/config.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr.h>
#ifdef CONFIG_CHAIN_OF_TRUST
#include <fsl_validate.h>
#endif
#endif
}
+static void erratum_a008850_early(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008850
+ /* part 1 of 2 */
+ struct ccsr_cci400 __iomem *cci = (void *)CONFIG_SYS_CCI400_ADDR;
+ struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
+
+ /* disables propagation of barrier transactions to DDRC from CCI400 */
+ out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
+
+ /* disable the re-ordering in DDRC */
+ ddr_out32(&ddr->eor, DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS);
+#endif
+}
+
+void erratum_a008850_post(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008850
+ /* part 2 of 2 */
+ struct ccsr_cci400 __iomem *cci = (void *)CONFIG_SYS_CCI400_ADDR;
+ struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
+ u32 tmp;
+
+ /* enable propagation of barrier transactions to DDRC from CCI400 */
+ out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
+
+ /* enable the re-ordering in DDRC */
+ tmp = ddr_in32(&ddr->eor);
+ tmp &= ~(DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS);
+ ddr_out32(&ddr->eor, tmp);
+#endif
+}
+
void fsl_lsch2_early_init_f(void)
{
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
/* Erratum */
+ erratum_a008850_early(); /* part 1 of 2 */
erratum_a009929();
erratum_a009660();
}
switch (spl_boot_device()) {
case BOOT_DEVICE_MMC1:
#ifdef CONFIG_SPL_FAT_SUPPORT
- return MMCSD_MODE_FAT;
+ return MMCSD_MODE_FS;
#else
return MMCSD_MODE_RAW;
#endif
memset((void *)gd, 0, sizeof(gd_t));
#ifdef CONFIG_LS2080A
arch_cpu_init();
-#endif
-#ifdef CONFIG_FSL_IFC
- init_early_memctl_regs();
#endif
board_early_init_f();
timer_init();
#endif
#endif
-#ifndef CONFIG_ARMV8_MULTIENTRY
+#ifdef CONFIG_ARMV8_MULTIENTRY
branch_if_master x0, x1, 2f
/*
obj-y += cpu.o
obj-$(CONFIG_MP) += mp.o
obj-y += slcr.o
+obj-$(CONFIG_SPL_BUILD) += spl.o
--- /dev/null
+/*
+ * Copyright 2015 - 2016 Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <debug_uart.h>
+#include <spl.h>
+
+#include <asm/io.h>
+#include <asm/spl.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/sys_proto.h>
+
+void board_init_f(ulong dummy)
+{
+ psu_init();
+ board_early_init_r();
+
+#ifdef CONFIG_DEBUG_UART
+ /* Uart debug for sure */
+ debug_uart_init();
+ puts("Debug uart enabled\n"); /* or printch() */
+#endif
+ /* Delay is required for clocks to be propagated */
+ udelay(1000000);
+
+ /* Clear the BSS */
+ memset(__bss_start, 0, __bss_end - __bss_start);
+
+ /* No need to call timer init - it is empty for ZynqMP */
+ board_init_r(NULL, 0);
+}
+
+#ifdef CONFIG_SPL_BOARD_INIT
+void spl_board_init(void)
+{
+ preloader_console_init();
+ board_init();
+}
+#endif
+
+u32 spl_boot_device(void)
+{
+ u32 reg = 0;
+ u8 bootmode;
+
+ reg = readl(&crlapb_base->boot_mode);
+ bootmode = reg & BOOT_MODES_MASK;
+
+ switch (bootmode) {
+ case JTAG_MODE:
+ return BOOT_DEVICE_RAM;
+#ifdef CONFIG_SPL_MMC_SUPPORT
+ case EMMC_MODE:
+ case SD_MODE:
+ case SD_MODE1:
+ return BOOT_DEVICE_MMC1;
+#endif
+ default:
+ printf("Invalid Boot Mode:0x%x\n", bootmode);
+ break;
+ }
+
+ return 0;
+}
+
+u32 spl_boot_mode(void)
+{
+ switch (spl_boot_device()) {
+ case BOOT_DEVICE_RAM:
+ return 0;
+ case BOOT_DEVICE_MMC1:
+ return MMCSD_MODE_FS;
+ default:
+ puts("spl: error: unsupported device\n");
+ hang();
+ }
+}
+
+__weak void psu_init(void)
+{
+ /*
+ * This function is overridden by the one in
+ * board/xilinx/zynqmp/(platform)/psu_init_gpl.c, if it exists.
+ */
+}
+
+#ifdef CONFIG_SPL_OS_BOOT
+int spl_start_uboot(void)
+{
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+ /* Just empty function now - can't decide what to choose */
+ debug("%s: %s\n", __func__, name);
+
+ return 0;
+}
+#endif
active_slave = <0>;
cpts_clock_mult = <0x80000000>;
cpts_clock_shift = <29>;
+ syscon = <&scm_conf>;
ranges;
davinci_mdio: mdio@4a101000 {
ti,irqs-safe-map = <0>;
};
- mac: ethernet@4a100000 {
+ mac: ethernet@48484000 {
compatible = "ti,cpsw";
ti,hwmods = "gmac";
clocks = <&dpll_gmac_ck>, <&gmac_gmii_ref_clk_div>;
active_slave = <0>;
cpts_clock_mult = <0x80000000>;
cpts_clock_shift = <29>;
+ syscon = <&scm_conf>;
reg = <0x48484000 0x1000
0x48485200 0x2E00>;
#address-cells = <1>;
};
soft-spi {
- compatible = "u-boot,soft-spi";
- cs-gpio = <&gpy4 3 0>;
- sclk-gpio = <&gpy3 1 0>;
- mosi-gpio = <&gpy3 3 0>;
- miso-gpio = <&gpy3 0 0>;
+ compatible = "spi-gpio";
+ cs-gpios = <&gpy4 3 0>;
+ gpio-sck = <&gpy3 1 0>;
+ gpio-mosi = <&gpy3 3 0>;
+ gpio-miso = <&gpy3 0 0>;
spi-delay-us = <1>;
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,vf610-qspi";
#address-cells = <1>;
#size-cells = <0>;
- reg = <0x1550000 0x10000>,
- <0x40000000 0x4000000>;
+ reg = <0x0 0x1550000 0x0 0x10000>,
+ <0x0 0x40000000 0x0 0x4000000>;
+ reg-names = "QuadSPI", "QuadSPI-memory";
num-cs = <2>;
big-endian;
status = "disabled";
nvidia,panel = <&lcd_panel>;
};
};
-
- dc@54240000 {
- status = "disabled";
- };
};
/* This is not used in U-Boot, but is expected to be in kernel .dts */
slcr: slcr@f8000000 {
#address-cells = <1>;
#size-cells = <1>;
- compatible = "xlnx,zynq-slcr", "syscon", "simple-bus";
+ compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd";
reg = <0xF8000000 0x1000>;
ranges;
clkc: clkc@100 {
compatible = "arm,gic-400", "arm,cortex-a15-gic";
#interrupt-cells = <3>;
reg = <0x0 0xf9010000 0x10000>,
- <0x0 0xf902f000 0x2000>,
+ <0x0 0xf9020000 0x20000>,
<0x0 0xf9040000 0x20000>,
- <0x0 0xf906f000 0x2000>;
+ <0x0 0xf9060000 0x20000>;
interrupt-controller;
interrupt-parent = <&gic>;
interrupts = <1 9 0xf04>;
amba: amba {
compatible = "simple-bus";
+ u-boot,dm-pre-reloc;
#address-cells = <2>;
#size-cells = <1>;
ranges = <0 0 0 0 0xffffffff>;
};
sdhci0: sdhci@ff160000 {
+ u-boot,dm-pre-reloc;
compatible = "arasan,sdhci-8.9a";
status = "disabled";
interrupt-parent = <&gic>;
};
sdhci1: sdhci@ff170000 {
+ u-boot,dm-pre-reloc;
compatible = "arasan,sdhci-8.9a";
status = "disabled";
interrupt-parent = <&gic>;
};
uart0: serial@ff000000 {
+ u-boot,dm-pre-reloc;
compatible = "cdns,uart-r1p12", "xlnx,xuartps";
status = "disabled";
interrupt-parent = <&gic>;
};
uart1: serial@ff010000 {
+ u-boot,dm-pre-reloc;
compatible = "cdns,uart-r1p12", "xlnx,xuartps";
status = "disabled";
interrupt-parent = <&gic>;
{
switch (imxtype) {
case MXC_CPU_MX7S:
- return "7SOLO"; /* Single-core version of the mx7 */
+ return "7S"; /* Single-core version of the mx7 */
case MXC_CPU_MX7D:
return "7D"; /* Dual-core version of the mx7 */
case MXC_CPU_MX6QP:
#define CONFIG_SYS_FSL_ERRATUM_A008751
#define CONFIG_SYS_FSL_ERRATUM_A009635
#define CONFIG_SYS_FSL_ERRATUM_A009663
+#define CONFIG_SYS_FSL_ERRATUM_A009801
#define CONFIG_SYS_FSL_ERRATUM_A009803
#define CONFIG_SYS_FSL_ERRATUM_A009942
+#define CONFIG_SYS_FSL_ERRATUM_A010165
/* ARM A57 CORE ERRATA */
#define CONFIG_ARM_ERRATA_826974
#define CONFIG_ARM_ERRATA_829520
#define CONFIG_ARM_ERRATA_833471
+#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
#elif defined(CONFIG_LS1043A)
#define CONFIG_MAX_CPUS 4
#define CONFIG_SYS_CACHELINE_SIZE 64
#define GICD_BASE 0x01401000
#define GICC_BASE 0x01402000
+#define CONFIG_SYS_FSL_ERRATUM_A008850
#define CONFIG_SYS_FSL_ERRATUM_A009663
#define CONFIG_SYS_FSL_ERRATUM_A009929
#define CONFIG_SYS_FSL_ERRATUM_A009942
#define CONFIG_SYS_FSL_ERRATUM_A009660
+#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
#else
#error SoC not defined
#endif
#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000)
#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000)
#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000)
-#define CONFIG_SYS_FSL_SEC_ADDR (CONFIG_SYS_IMMR + 0x700000)
-#define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_IMMR + 0x710000)
#define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0xe90000)
#define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0xe80200)
#define CONFIG_SYS_FSL_FM1_DTSEC1_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET)
+#define CONFIG_SYS_FSL_SEC_OFFSET 0x700000ull
+#define CONFIG_SYS_FSL_JR0_OFFSET 0x710000ull
+#define CONFIG_SYS_FSL_SEC_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET)
+#define CONFIG_SYS_FSL_JR0_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET)
+
/* Device Configuration and Pin Control */
struct ccsr_gur {
u32 porsr1; /* POR status 1 */
#define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0x00e80200)
/* SEC */
-#define CONFIG_SYS_FSL_SEC_ADDR (CONFIG_SYS_IMMR + 0x07000000)
-#define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_IMMR + 0x07010000)
+#define CONFIG_SYS_FSL_SEC_OFFSET 0x07000000ull
+#define CONFIG_SYS_FSL_JR0_OFFSET 0x07010000ull
+#define CONFIG_SYS_FSL_SEC_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET)
+#define CONFIG_SYS_FSL_JR0_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET)
/* Security Monitor */
#define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0x00e90000)
(CONFIG_SYS_IMMR + CONFIG_SYS_LS102XA_USB1_OFFSET)
#define CONFIG_SYS_FSL_SEC_OFFSET 0x00700000
+#define CONFIG_SYS_FSL_JR0_OFFSET 0x00710000
#define CONFIG_SYS_LS102XA_USB1_OFFSET 0x07600000
#define CONFIG_SYS_TSEC1_OFFSET 0x01d10000
#define CONFIG_SYS_TSEC2_OFFSET 0x01d50000
/* SATA */
#define AHCI_BASE_ADDR (CONFIG_SYS_IMMR + 0x02200000)
#define CONFIG_BOARD_LATE_INIT
-#define CONFIG_CMD_SCSI
+#define CONFIG_SCSI
#define CONFIG_LIBATA
#define CONFIG_SCSI_AHCI
#define CONFIG_SCSI_AHCI_PLAT
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#define CONFIG_SYS_FSL_ERRATUM_A008378
#define CONFIG_SYS_FSL_ERRATUM_A009663
+#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
#else
#error SoC not defined
#endif
#define CAAM_BASE_ADDR (ATZ2_BASE_ADDR)
#define ARM_BASE_ADDR (ATZ2_BASE_ADDR + 0x40000)
-#define CONFIG_SYS_FSL_SEC_ADDR CAAM_BASE_ADDR
-#define CONFIG_SYS_FSL_JR0_ADDR (CAAM_BASE_ADDR + 0x1000)
+#define CONFIG_SYS_FSL_SEC_OFFSET 0
+#define CONFIG_SYS_FSL_SEC_ADDR (CAAM_BASE_ADDR + \
+ CONFIG_SYS_FSL_SEC_OFFSET)
+#define CONFIG_SYS_FSL_JR0_OFFSET 0x1000
+#define CONFIG_SYS_FSL_JR0_ADDR (CAAM_BASE_ADDR + \
+ CONFIG_SYS_FSL_JR0_OFFSET)
+#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
#define USB_PL301_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000)
#define USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000)
MX6_PAD_SD1_DAT3__USDHC1_DAT3 = IOMUX_PAD(0x0548, 0x0240, 0, 0x0000, 0, 0),
MX6_PAD_SD1_DAT4__USDHC1_DAT4 = IOMUX_PAD(0x054C, 0x0244, 0, 0x0000, 0, 0),
MX6_PAD_SD1_DAT5__USDHC1_DAT5 = IOMUX_PAD(0x0550, 0x0248, 0, 0x0000, 0, 0),
+ MX6_PAD_SD1_DAT5__GPIO_5_9 = IOMUX_PAD(0x0550, 0x0248, 5, 0x0000, 0, 0),
MX6_PAD_SD1_DAT6__USDHC1_DAT6 = IOMUX_PAD(0x0554, 0x024C, 0, 0x0000, 0, 0),
MX6_PAD_SD1_DAT7__USDHC1_DAT7 = IOMUX_PAD(0x0558, 0x0250, 0, 0x0000, 0, 0),
MX6_PAD_KEY_ROW7__GPIO_4_7 = IOMUX_PAD(0x04B0, 0x01A8, 5, 0x0000, 0, 0),
#define FEC_QUIRK_ENET_MAC
#define SNVS_LPGPR 0x68
-
-#define CONFIG_SYS_FSL_SEC_ADDR (CAAM_IPS_BASE_ADDR)
-#define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_FSL_SEC_ADDR + 0x1000)
-
+#define CONFIG_SYS_FSL_SEC_OFFSET 0
+#define CONFIG_SYS_FSL_SEC_ADDR (CAAM_IPS_BASE_ADDR + \
+ CONFIG_SYS_FSL_SEC_OFFSET)
+#define CONFIG_SYS_FSL_JR0_OFFSET 0x1000
+#define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_FSL_SEC_ADDR + \
+ CONFIG_SYS_FSL_JR0_OFFSET)
+#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
#include <asm/imx-common/regs-lcdif.h>
#include <asm/types.h>
MX7D_PAD_LCD_DATA23__GPIO3_IO28 = IOMUX_PAD(0x0394, 0x0124, 5, 0x0000, 0, 0),
MX7D_PAD_LCD_DATA23__I2C4_SDA = IOMUX_PAD(0x0394, 0x0124, IOMUX_CONFIG_SION | 6, 0x05F0, 1, 0),
- MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX = IOMUX_PAD(0x0398, 0x0128, 0, 0x0000, 0, 0),
+ MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX = IOMUX_PAD(0x0398, 0x0128, 0, 0x06F4, 0, 0),
MX7D_PAD_UART1_RX_DATA__UART1_DTE_TX = IOMUX_PAD(0x0398, 0x0128, 0, 0x0000, 0, 0),
MX7D_PAD_UART1_RX_DATA__I2C1_SCL = IOMUX_PAD(0x0398, 0x0128, IOMUX_CONFIG_SION | 1, 0x0000, 0, 0),
MX7D_PAD_UART1_TX_DATA__GPIO4_IO1 = IOMUX_PAD(0x039C, 0x012C, 5, 0x0000, 0, 0),
MX7D_PAD_UART1_TX_DATA__ENET1_MDC = IOMUX_PAD(0x039C, 0x012C, 6, 0x0000, 0, 0),
- MX7D_PAD_UART2_RX_DATA__UART2_DCE_RX = IOMUX_PAD(0x03A0, 0x0130, 0, 0x0000, 0, 0),
+ MX7D_PAD_UART2_RX_DATA__UART2_DCE_RX = IOMUX_PAD(0x03A0, 0x0130, 0, 0x06FC, 2, 0),
MX7D_PAD_UART2_RX_DATA__UART2_DTE_TX = IOMUX_PAD(0x03A0, 0x0130, 0, 0x0000, 0, 0),
MX7D_PAD_UART2_RX_DATA__I2C2_SCL = IOMUX_PAD(0x03A0, 0x0130, IOMUX_CONFIG_SION | 1, 0x0000, 0, 0),
MX7D_PAD_UART2_TX_DATA__UART2_DCE_TX = IOMUX_PAD(0x03A4, 0x0134, 0, 0x0000, 0, 0),
- MX7D_PAD_UART2_TX_DATA__UART2_DTE_RX = IOMUX_PAD(0x03A4, 0x0134, 0, 0x0000, 0, 0),
+ MX7D_PAD_UART2_TX_DATA__UART2_DTE_RX = IOMUX_PAD(0x03A4, 0x0134, 0, 0x06FC, 3, 0),
MX7D_PAD_UART2_TX_DATA__I2C2_SDA = IOMUX_PAD(0x03A4, 0x0134, IOMUX_CONFIG_SION | 1, 0x05E0, 0, 0),
MX7D_PAD_UART2_TX_DATA__SAI3_RX_DATA0 = IOMUX_PAD(0x03A4, 0x0134, 2, 0x06C8, 0, 0),
MX7D_PAD_UART2_TX_DATA__ECSPI1_RDY = IOMUX_PAD(0x03A4, 0x0134, 3, 0x0000, 0, 0),
MX7D_PAD_UART3_TX_DATA__GPIO4_IO5 = IOMUX_PAD(0x03AC, 0x013C, 5, 0x0000, 0, 0),
MX7D_PAD_UART3_TX_DATA__SD2_LCTL = IOMUX_PAD(0x03AC, 0x013C, 6, 0x0000, 0, 0),
- MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS = IOMUX_PAD(0x03B0, 0x0140, 0, 0x0000, 0, 0),
+ MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS = IOMUX_PAD(0x03B0, 0x0140, 0, 0x0700, 2, 0),
MX7D_PAD_UART3_RTS_B__UART3_DTE_CTS = IOMUX_PAD(0x03B0, 0x0140, 0, 0x0000, 0, 0),
MX7D_PAD_UART3_RTS_B__USB_OTG2_OC = IOMUX_PAD(0x03B0, 0x0140, 1, 0x0000, 0, 0),
#define CPSW_BASE 0x48484000
#define CPSW_MDIO_BASE 0x48485000
+/* gmii_sel register defines */
+#define GMII1_SEL_MII 0x0
+#define GMII1_SEL_RMII 0x1
+#define GMII1_SEL_RGMII 0x2
+#define GMII2_SEL_MII (GMII1_SEL_MII << 4)
+#define GMII2_SEL_RMII (GMII1_SEL_RMII << 4)
+#define GMII2_SEL_RGMII (GMII1_SEL_RGMII << 4)
+
+#define MII_MODE_ENABLE (GMII1_SEL_MII | GMII2_SEL_MII)
+#define RMII_MODE_ENABLE (GMII1_SEL_RMII | GMII2_SEL_RMII)
+#define RGMII_MODE_ENABLE (GMII1_SEL_RGMII | GMII2_SEL_RGMII)
+
#endif /* _CPU_H */
unsigned int zynqmp_get_silicon_version(void);
+void psu_init(void);
+
#endif /* _ASM_ARCH_SYS_PROTO_H */
select CPU_ARM926EJS
select SUPPORT_SPL
+config TARGET_SAMA5D2_PTC
+ bool "SAMA5D2 PTC board"
+ select CPU_V7
+ select SUPPORT_SPL
+
config TARGET_SAMA5D2_XPLAINED
bool "SAMA5D2 Xplained board"
select CPU_V7
source "board/atmel/at91sam9n12ek/Kconfig"
source "board/atmel/at91sam9rlek/Kconfig"
source "board/atmel/at91sam9x5ek/Kconfig"
+source "board/atmel/sama5d2_ptc/Kconfig"
source "board/atmel/sama5d2_xplained/Kconfig"
source "board/atmel/sama5d3_xplained/Kconfig"
source "board/atmel/sama5d3xek/Kconfig"
obj-$(CONFIG_AT91SAM9M10G45) += mpddrc.o spl_at91.o
obj-$(CONFIG_AT91SAM9N12) += mpddrc.o spl_at91.o
obj-$(CONFIG_AT91SAM9X5) += mpddrc.o spl_at91.o
-obj-$(CONFIG_SAMA5D2) += mpddrc.o spl_atmel.o matrix.o atmel_sfr.o
+obj-$(CONFIG_SAMA5D2) += bootparams_atmel.o mpddrc.o spl_atmel.o matrix.o atmel_sfr.o
obj-$(CONFIG_SAMA5D3) += mpddrc.o spl_atmel.o
obj-$(CONFIG_SAMA5D4) += mpddrc.o spl_atmel.o matrix.o atmel_sfr.o
obj-y += spl.o
if (div > 0xff)
return -EINVAL;
+ if (clk_source == GCK_CSS_UPLL_CLK) {
+ if (at91_upll_clk_enable())
+ return -ENODEV;
+ }
+
writel(id, &pmc->pcr);
regval = readl(&pmc->pcr);
regval &= ~AT91_PMC_PCR_GCKCSS;
case AT91_PMC_PCR_GCKCSS_PLLA_CLK:
freq = gd->arch.plla_rate_hz;
break;
+ case AT91_PMC_PCR_GCKCSS_UPLL_CLK:
+ freq = AT91_UTMI_PLL_CLK_FREQ;
+ break;
+ case AT91_PMC_PCR_GCKCSS_MCK_CLK:
+ freq = gd->arch.mck_rate_hz;
+ break;
default:
printf("Improper GCK clock source selection!\n");
freq = 0;
--- /dev/null
+/*
+ * Atmel SAMA5Dx boot parameter handling
+ *
+ * Copyright (c) 2016 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <asm/system.h>
+#include <linux/linkage.h>
+
+ENTRY(save_boot_params)
+ ldr r0, =bootrom_stash
+ str r4, [r0, #0]
+ b save_boot_params_ret
+ENDPROC(save_boot_params)
#define GCK_CSS_MCK_CLK 4
#define GCK_CSS_AUDIO_CLK 5
+#define AT91_UTMI_PLL_CLK_FREQ 480000000
+
static inline unsigned long get_cpu_clk_rate(void)
{
DECLARE_GLOBAL_DATA_PTR;
#define ATMEL_SFR_DDRCFG_FDQIEN 0x00010000
#define ATMEL_SFR_DDRCFG_FDQSIEN 0x00020000
+/* Bit field in EBICFG */
+#define AT91_SFR_EBICFG_DRIVE0 (0x3 << 0)
+#define AT91_SFR_EBICFG_DRIVE0_LOW (0x0 << 0)
+#define AT91_SFR_EBICFG_DRIVE0_MEDIUM (0x2 << 0)
+#define AT91_SFR_EBICFG_DRIVE0_HIGH (0x3 << 0)
+#define AT91_SFR_EBICFG_PULL0 (0x3 << 2)
+#define AT91_SFR_EBICFG_PULL0_UP (0x0 << 2)
+#define AT91_SFR_EBICFG_PULL0_NONE (0x1 << 2)
+#define AT91_SFR_EBICFG_PULL0_DOWN (0x3 << 2)
+#define AT91_SFR_EBICFG_SCH0 (0x1 << 4)
+#define AT91_SFR_EBICFG_SCH0_OFF (0x0 << 4)
+#define AT91_SFR_EBICFG_SCH0_ON (0x1 << 4)
+#define AT91_SFR_EBICFG_DRIVE1 (0x3 << 8)
+#define AT91_SFR_EBICFG_DRIVE1_LOW (0x0 << 8)
+#define AT91_SFR_EBICFG_DRIVE1_MEDIUM (0x2 << 8)
+#define AT91_SFR_EBICFG_DRIVE1_HIGH (0x3 << 8)
+#define AT91_SFR_EBICFG_PULL1 (0x3 << 10)
+#define AT91_SFR_EBICFG_PULL1_UP (0x0 << 10)
+#define AT91_SFR_EBICFG_PULL1_NONE (0x1 << 10)
+#define AT91_SFR_EBICFG_PULL1_DOWN (0x3 << 10)
+#define AT91_SFR_EBICFG_SCH1 (0x1 << 12)
+#define AT91_SFR_EBICFG_SCH1_OFF (0x0 << 12)
+#define AT91_SFR_EBICFG_SCH1_ON (0x1 << 12)
+
/* Bit field in AICREDIR */
#define ATMEL_SFR_AICREDIR_NSAIC 0x00000001
/*
* Address Memory Space
*/
+#define ATMEL_BASE_CS0 0x10000000
#define ATMEL_BASE_DDRCS 0x20000000
+#define ATMEL_BASE_CS1 0x60000000
+#define ATMEL_BASE_CS2 0x70000000
+#define ATMEL_BASE_CS3 0x80000000
#define ATMEL_BASE_QSPI0_AES_MEM 0x90000000
#define ATMEL_BASE_QSPI1_AES_MEM 0x98000000
#define ATMEL_BASE_SDMMC0 0xa0000000
*/
#define ATMEL_BASE_PMECC (ATMEL_BASE_HSMC + 0x70)
#define ATMEL_BASE_PMERRLOC (ATMEL_BASE_HSMC + 0x500)
+#define ATMEL_BASE_SMC (ATMEL_BASE_HSMC + 0x700)
#define ATMEL_BASE_PIOB (ATMEL_BASE_PIOA + 0x40)
#define ATMEL_BASE_PIOC (ATMEL_BASE_PIOB + 0x40)
/* No PMECC Galois table in ROM */
#define NO_GALOIS_TABLE_IN_ROM
+/* Boot modes stored by BootROM in r4 */
+#define ATMEL_SAMA5D2_BOOT_FROM_OFF 0
+#define ATMEL_SAMA5D2_BOOT_FROM_MASK 0xf
+#define ATMEL_SAMA5D2_BOOT_FROM_SPI (0 << 0)
+#define ATMEL_SAMA5D2_BOOT_FROM_MCI (1 << 0)
+#define ATMEL_SAMA5D2_BOOT_FROM_SMC (2 << 0)
+#define ATMEL_SAMA5D2_BOOT_FROM_TWI (3 << 0)
+#define ATMEL_SAMA5D2_BOOT_FROM_QSPI (4 << 0)
+
+#define ATMEL_SAMA5D2_BOOT_DEV_ID_OFF 4
+#define ATMEL_SAMA5D2_BOOT_DEV_ID_MASK 0xf
+
#ifndef __ASSEMBLY__
unsigned int get_chip_id(void);
unsigned int get_extension_chip_id(void);
}
#endif
+#if defined(CONFIG_SAMA5D2)
+struct {
+ u32 r4;
+} bootrom_stash __attribute__((section(".data")));
+
+u32 spl_boot_device(void)
+{
+ u32 dev = (bootrom_stash.r4 >> ATMEL_SAMA5D2_BOOT_FROM_OFF) &
+ ATMEL_SAMA5D2_BOOT_FROM_MASK;
+ u32 off = (bootrom_stash.r4 >> ATMEL_SAMA5D2_BOOT_DEV_ID_OFF) &
+ ATMEL_SAMA5D2_BOOT_DEV_ID_MASK;
+
+#if defined(CONFIG_SYS_USE_MMC)
+ if (dev == ATMEL_SAMA5D2_BOOT_FROM_MCI) {
+ if (off == 0)
+ return BOOT_DEVICE_MMC1;
+ if (off == 1)
+ return BOOT_DEVICE_MMC2;
+ printf("ERROR: MMC controller %i not present!\n", dev);
+ hang();
+ }
+#endif
+
+#if defined(CONFIG_SYS_USE_SERIALFLASH) || defined(CONFIG_SYS_USE_SPIFLASH)
+ if (dev == ATMEL_SAMA5D2_BOOT_FROM_SPI)
+ return BOOT_DEVICE_SPI;
+#endif
+
+ printf("ERROR: SMC/TWI/QSPI boot device not supported!\n"
+ " Boot device %i, controller number %i\n", dev, off);
+
+ return BOOT_DEVICE_NONE;
+}
+#else
u32 spl_boot_device(void)
{
#ifdef CONFIG_SYS_USE_MMC
#endif
return BOOT_DEVICE_NONE;
}
+#endif
u32 spl_boot_mode(void)
{
switch (spl_boot_device()) {
#ifdef CONFIG_SYS_USE_MMC
case BOOT_DEVICE_MMC1:
+ case BOOT_DEVICE_MMC2:
return MMCSD_MODE_FS;
break;
#endif
if ARCH_ZYNQ
-config ZYNQ_CUSTOM_INIT
- bool "Use custom ps7_init provided by Xilinx tool"
- help
- U-Boot includes ps7_init_gpl.[ch] for some Zynq board variants.
- If you want to override them with customized ones
- or ps7_init code for your board is missing, please say Y here
- and add ones into board/xilinx/zynq/custom_hw_platform/ directory.
-
-choice
- prompt "Xilinx Zynq board select"
- default TARGET_ZYNQ_ZC702
-
-config TARGET_ZYNQ_ZED
- bool "Zynq ZedBoard"
-
-config TARGET_ZYNQ_MICROZED
- bool "Zynq MicroZed"
-
-config TARGET_ZYNQ_PICOZED
- bool "Zynq PicoZed"
-
-config TARGET_ZYNQ_ZC702
- bool "Zynq ZC702 Board"
-
-config TARGET_ZYNQ_ZC706
- bool "Zynq ZC706 Board"
-
-config TARGET_ZYNQ_ZC770
- bool "Zynq ZC770 Board"
- select ZYNQ_CUSTOM_INIT
-
-config TARGET_ZYNQ_ZYBO
- bool "Zynq Zybo Board"
-
-endchoice
-
config SYS_BOARD
default "zynq"
default "zynq"
config SYS_CONFIG_NAME
- default "zynq_zed" if TARGET_ZYNQ_ZED
- default "zynq_microzed" if TARGET_ZYNQ_MICROZED
- default "zynq_picozed" if TARGET_ZYNQ_PICOZED
- default "zynq_zc70x" if TARGET_ZYNQ_ZC702 || TARGET_ZYNQ_ZC706
- default "zynq_zc770" if TARGET_ZYNQ_ZC770
- default "zynq_zybo" if TARGET_ZYNQ_ZYBO
+ string "Board configuration name"
+ default "zynq-common"
+ help
+ This option contains information about board configuration name.
+ Based on this option include/configs/<CONFIG_SYS_CONFIG_NAME>.h header
+ will be used for board configuration.
endif
* board/xilinx/zynq/(platform)/ps7_init_gpl.c, if it exists.
*/
}
+
+__weak int ps7_post_config(void)
+{
+ /*
+ * This function is overridden by the one in
+ * board/xilinx/zynq/(platform)/ps7_init_gpl.c, if it exists.
+ */
+ return 0;
+}
+
+void spl_board_prepare_for_boot(void)
+{
+ ps7_post_config();
+ debug("SPL bye\n");
+}
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+ /* Just empty function now - can't decide what to choose */
+ debug("%s: %s\n", __func__, name);
+
+ return 0;
+}
+#endif
move.l %d0, (%a1)
move.l %d0, (%a2)
- /* set stackpointer to end of internal ram to get some stackspace for
- the first c-code */
- move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
- clr.l %sp@-
+ /* put relocation table address to a5 */
+ move.l #__got_start, %a5
+
+ /* setup stack initially on top of internal static ram */
+ move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp
+
+ /*
+ * if configured, malloc_f arena will be reserved first,
+ * then (and always) gd struct space will be reserved
+ */
+ move.l %sp, -(%sp)
+ bsr board_init_f_alloc_reserve
+
+ /* update stack and frame-pointers */
+ move.l %d0, %sp
+ move.l %sp, %fp
- move.l #__got_start, %a5 /* put relocation table address to a5 */
+ /* initialize reserved area */
+ move.l %d0, -(%sp)
+ bsr board_init_f_init_reserve
bsr cpu_init_f /* run low-level CPU init code (from flash) */
+ clr.l %sp@-
bsr board_init_f /* run low-level board init code (from flash) */
/* board_init_f() does not return */
move.l %d0, (%a1)
move.l %d0, (%a2)
- /* set stackpointer to end of internal ram to get some stackspace for the
- first c-code */
- move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
- clr.l %sp@-
+ /* put relocation table address to a5 */
+ move.l #__got_start, %a5
- move.l #__got_start, %a5 /* put relocation table address to a5 */
+ /* setup stack initially on top of internal static ram */
+ move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp
+
+ /*
+ * if configured, malloc_f arena will be reserved first,
+ * then (and always) gd struct space will be reserved
+ */
+ move.l %sp, -(%sp)
+ move.l #board_init_f_alloc_reserve, %a1
+ jsr (%a1)
+
+ /* update stack and frame-pointers */
+ move.l %d0, %sp
+ move.l %sp, %fp
+
+ /* initialize reserved area */
+ move.l %d0, -(%sp)
+ move.l #board_init_f_init_reserve, %a1
+ jsr (%a1)
/* run low-level CPU init code (from flash) */
move.l #cpu_init_f, %a1
jsr (%a1)
/* run low-level board init code (from flash) */
+ clr.l %sp@-
move.l #board_init_f, %a1
jsr (%a1)
move.l %d0, (%a1)
move.l %d0, (%a2)
- /* set stackpointer to end of internal ram to get some stackspace for the first c-code */
- move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
- clr.l %sp@-
+ /* put relocation table address to a5 */
+ move.l #__got_start, %a5
- move.l #__got_start, %a5 /* put relocation table address to a5 */
+ /* setup stack initially on top of internal static ram */
+ move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp
+
+ /*
+ * if configured, malloc_f arena will be reserved first,
+ * then (and always) gd struct space will be reserved
+ */
+ move.l %sp, -(%sp)
+ move.l #board_init_f_alloc_reserve, %a1
+ jsr (%a1)
+
+ /* update stack and frame-pointers */
+ move.l %d0, %sp
+ move.l %sp, %fp
+
+ /* initialize reserved area */
+ move.l %d0, -(%sp)
+ move.l #board_init_f_init_reserve, %a1
+ jsr (%a1)
/* run low-level CPU init code (from flash) */
move.l #cpu_init_f, %a1
jsr (%a1)
/* run low-level board init code (from flash) */
+ clr.l %sp@-
move.l #board_init_f, %a1
jsr (%a1)
return 0;
}
-void uart_port_conf(void)
+void uart_port_conf(int port)
{
}
move.l %d0, (%a1)
move.l %d0, (%a2)
+ /* put relocation table address to a5 */
+ move.l #__got_start, %a5
+
+ /* setup stack initially on top of internal static ram */
+ move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp
+
/*
- * set stackpointer to internal sram end - 80
- * (global data struct size + some bytes)
- * get some stackspace for the first c-code,
+ * if configured, malloc_f arena will be reserved first,
+ * then (and always) gd struct space will be reserved
*/
- move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
- clr.l %sp@-
+ move.l %sp, -(%sp)
+ bsr board_init_f_alloc_reserve
- /* put relocation table address to a5 */
- move.l #__got_start, %a5
+ /* update stack and frame-pointers */
+ move.l %d0, %sp
+ move.l %sp, %fp
+
+ /* initialize reserved area */
+ move.l %d0, -(%sp)
+ bsr board_init_f_init_reserve
/* run low-level CPU init code (from flash) */
bsr cpu_init_f
/* run low-level board init code (from flash) */
+ clr.l %sp@-
bsr board_init_f
/* board_init_f() does not return */
move.l %d0, (%a1)
move.l %d0, (%a2)
- /* set stackpointer to end of internal ram to get some stackspace for the
- first c-code */
- move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
- clr.l %sp@-
+ /* put relocation table address to a5 */
+ move.l #__got_start, %a5
- move.l #__got_start, %a5 /* put relocation table address to a5 */
+ /* setup stack initially on top of internal static ram */
+ move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp
+
+ /*
+ * if configured, malloc_f arena will be reserved first,
+ * then (and always) gd struct space will be reserved
+ */
+ move.l %sp, -(%sp)
+ move.l #board_init_f_alloc_reserve, %a1
+ jsr (%a1)
+
+ /* update stack and frame-pointers */
+ move.l %d0, %sp
+ move.l %sp, %fp
+
+ /* initialize reserved area */
+ move.l %d0, -(%sp)
+ move.l #board_init_f_init_reserve, %a1
+ jsr (%a1)
/* run low-level CPU init code (from flash) */
move.l #cpu_init_f, %a1
jsr (%a1)
/* run low-level board init code (from flash) */
+ clr.l %sp@-
move.l #board_init_f, %a1
jsr (%a1)
movec %d0, %RAMBAR1
#endif
- /* set stackpointer to end of internal ram to get some stackspace for
- the first c-code */
- move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
- clr.l %sp@-
+ /* put relocation table address to a5 */
+ move.l #__got_start, %a5
+
+ /* setup stack initially on top of internal static ram */
+ move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp
- move.l #__got_start, %a5 /* put relocation table address to a5 */
+ /*
+ * if configured, malloc_f arena will be reserved first,
+ * then (and always) gd struct space will be reserved
+ */
+ move.l %sp, -(%sp)
+ move.l #board_init_f_alloc_reserve, %a1
+ jsr (%a1)
+
+ /* update stack and frame-pointers */
+ move.l %d0, %sp
+ move.l %sp, %fp
+
+ /* initialize reserved area */
+ move.l %d0, -(%sp)
+ move.l #board_init_f_init_reserve, %a1
+ jsr (%a1)
/* run low-level CPU init code (from flash) */
move.l #cpu_init_f, %a1
jsr (%a1)
/* run low-level board init code (from flash) */
+ clr.l %sp@-
move.l #board_init_f, %a1
jsr (%a1)
move.l %d0, (%a1)
move.l %d0, (%a2)
- /* set stackpointer to end of internal ram to get some stackspace for the
- first c-code */
- move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
- clr.l %sp@-
+ /* put relocation table address to a5 */
+ move.l #__got_start, %a5
- move.l #__got_start, %a5 /* put relocation table address to a5 */
+ /* setup stack initially on top of internal static ram */
+ move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp
+
+ /*
+ * if configured, malloc_f arena will be reserved first,
+ * then (and always) gd struct space will be reserved
+ */
+ move.l %sp, -(%sp)
+ bsr board_init_f_alloc_reserve
+
+ /* update stack and frame-pointers */
+ move.l %d0, %sp
+ move.l %sp, %fp
+
+ /* initialize reserved area */
+ move.l %d0, -(%sp)
+ bsr board_init_f_init_reserve
jbsr cpu_init_f /* run low-level CPU init code (from flash) */
+ clr.l %sp@-
jbsr board_init_f /* run low-level board init code (from flash) */
/* board_init_f() does not return */
#ifndef _ASM_CONFIG_H_
#define _ASM_CONFIG_H_
-#define CONFIG_SYS_GENERIC_GLOBAL_DATA
-
#define CONFIG_NEEDS_MANUAL_RELOC
#define CONFIG_LMB
#include <asm/types.h>
-typedef struct fsl_i2c {
+typedef struct fsl_i2c_base {
u8 adr; /* I2C slave address */
u8 res0[3];
default "mips"
config SYS_CPU
- default "mips32" if CPU_MIPS32_R1 || CPU_MIPS32_R2
- default "mips64" if CPU_MIPS64_R1 || CPU_MIPS64_R2
+ default "mips32" if CPU_MIPS32
+ default "mips64" if CPU_MIPS64
choice
prompt "Target select"
select SUPPORTS_LITTLE_ENDIAN
select SUPPORTS_CPU_MIPS32_R1
select SUPPORTS_CPU_MIPS32_R2
+ select SUPPORTS_CPU_MIPS32_R6
select SWAP_IO_SPACE
select MIPS_L1_CACHE_SHIFT_6
select SYS_MIPS_CACHE_INIT_RAM_LOAD
select MIPS_TUNE_4KC
+config ARCH_ATH79
+ bool "Support QCA/Atheros ath79"
+ select OF_CONTROL
+ select DM
+
config MACH_PIC32
bool "Support Microchip PIC32"
select OF_CONTROL
source "board/micronas/vct/Kconfig"
source "board/pb1x00/Kconfig"
source "board/qemu-mips/Kconfig"
+source "arch/mips/mach-ath79/Kconfig"
source "arch/mips/mach-pic32/Kconfig"
if MIPS
depends on SUPPORTS_CPU_MIPS32_R1
select 32BIT
help
- Choose this option to build an U-Boot for release 1 or later of the
+ Choose this option to build an U-Boot for release 1 through 5 of the
MIPS32 architecture.
config CPU_MIPS32_R2
depends on SUPPORTS_CPU_MIPS32_R2
select 32BIT
help
- Choose this option to build an U-Boot for release 2 or later of the
+ Choose this option to build an U-Boot for release 2 through 5 of the
+ MIPS32 architecture.
+
+config CPU_MIPS32_R6
+ bool "MIPS32 Release 6"
+ depends on SUPPORTS_CPU_MIPS32_R6
+ select 32BIT
+ help
+ Choose this option to build an U-Boot for release 6 or later of the
MIPS32 architecture.
config CPU_MIPS64_R1
depends on SUPPORTS_CPU_MIPS64_R1
select 64BIT
help
- Choose this option to build a kernel for release 1 or later of the
+ Choose this option to build a kernel for release 1 through 5 of the
MIPS64 architecture.
config CPU_MIPS64_R2
depends on SUPPORTS_CPU_MIPS64_R2
select 64BIT
help
- Choose this option to build a kernel for release 2 or later of the
+ Choose this option to build a kernel for release 2 through 5 of the
+ MIPS64 architecture.
+
+config CPU_MIPS64_R6
+ bool "MIPS64 Release 6"
+ depends on SUPPORTS_CPU_MIPS64_R6
+ select 64BIT
+ help
+ Choose this option to build a kernel for release 6 or later of the
MIPS64 architecture.
endchoice
config SUPPORTS_CPU_MIPS32_R2
bool
+config SUPPORTS_CPU_MIPS32_R6
+ bool
+
config SUPPORTS_CPU_MIPS64_R1
bool
config SUPPORTS_CPU_MIPS64_R2
bool
+config SUPPORTS_CPU_MIPS64_R6
+ bool
+
config CPU_MIPS32
bool
- default y if CPU_MIPS32_R1 || CPU_MIPS32_R2
+ default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R6
config CPU_MIPS64
bool
- default y if CPU_MIPS64_R1 || CPU_MIPS64_R2
+ default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6
config MIPS_TUNE_4KC
bool
config MIPS_TUNE_24KC
bool
+config MIPS_TUNE_74KC
+ bool
+
config 32BIT
bool
libs-y += arch/mips/lib/
machine-$(CONFIG_SOC_AU1X00) += au1x00
+machine-$(CONFIG_ARCH_ATH79) += ath79
machine-$(CONFIG_MACH_PIC32) += pic32
machdirs := $(patsubst %,arch/mips/mach-%/,$(machine-y))
# Optimize for MIPS architectures
arch-$(CONFIG_CPU_MIPS32_R1) += -march=mips32 -Wa,-mips32
arch-$(CONFIG_CPU_MIPS32_R2) += -march=mips32r2 -Wa,-mips32r2
+arch-$(CONFIG_CPU_MIPS32_R6) += -march=mips32r6 -Wa,-mips32r6
arch-$(CONFIG_CPU_MIPS64_R1) += -march=mips64 -Wa,-mips64
arch-$(CONFIG_CPU_MIPS64_R2) += -march=mips64r2 -Wa,-mips64r2
+arch-$(CONFIG_CPU_MIPS64_R6) += -march=mips64r6 -Wa,-mips64r6
# Allow extra optimization for specific CPUs/SoCs
tune-$(CONFIG_MIPS_TUNE_4KC) += -mtune=4kc
tune-$(CONFIG_MIPS_TUNE_14KC) += -mtune=14kc
tune-$(CONFIG_MIPS_TUNE_24KC) += -mtune=24kc
+tune-$(CONFIG_MIPS_TUNE_74KC) += -mtune=74kc
# Include default header files
cflags-y += -I$(srctree)/arch/mips/include/asm/mach-generic
#include <common.h>
#include <command.h>
-#include <netdev.h>
#include <linux/compiler.h>
#include <asm/mipsregs.h>
#include <asm/reboot.h>
li t0, -16
PTR_LI t1, CONFIG_SYS_INIT_SP_ADDR
and sp, t1, t0 # force 16 byte alignment
- PTR_SUB sp, sp, GD_SIZE # reserve space for gd
+ PTR_SUBU \
+ sp, sp, GD_SIZE # reserve space for gd
and sp, sp, t0 # force 16 byte alignment
move k0, sp # save gd pointer
#ifdef CONFIG_SYS_MALLOC_F_LEN
li t2, CONFIG_SYS_MALLOC_F_LEN
- PTR_SUB sp, sp, t2 # reserve space for early malloc
+ PTR_SUBU \
+ sp, sp, t2 # reserve space for early malloc
and sp, sp, t0 # force 16 byte alignment
#endif
move fp, sp
1:
PTR_S zero, 0(t0)
blt t0, t1, 1b
- PTR_ADDI t0, PTRSIZE
+ PTR_ADDIU t0, PTRSIZE
#ifdef CONFIG_SYS_MALLOC_F_LEN
PTR_S sp, GD_MALLOC_BASE(k0) # gd->malloc_base offset
move a0, s2 # a0 <-- destination address
/* Jump to where we've relocated ourselves */
- PTR_ADDI t0, s2, in_ram - _start
+ PTR_ADDIU t0, s2, in_ram - _start
jr t0
nop
PTR_L t3, -(1 * PTRSIZE)(t0) # t3 <-- num_got_entries
PTR_L t8, -(2 * PTRSIZE)(t0) # t8 <-- _GLOBAL_OFFSET_TABLE_
PTR_ADD t8, s1 # t8 now holds relocated _G_O_T_
- PTR_ADDI t8, t8, 2 * PTRSIZE # skipping first two entries
+ PTR_ADDIU t8, t8, 2 * PTRSIZE # skipping first two entries
PTR_LI t2, 2
1:
PTR_L t1, 0(t8)
PTR_ADD t1, s1
PTR_S t1, 0(t8)
2:
- PTR_ADDI t2, 1
+ PTR_ADDIU t2, 1
blt t2, t3, 1b
- PTR_ADDI t8, PTRSIZE
+ PTR_ADDIU t8, PTRSIZE
/* Update dynamic relocations */
PTR_L t1, -(4 * PTRSIZE)(t0) # t1 <-- __rel_dyn_start
PTR_L t2, -(5 * PTRSIZE)(t0) # t2 <-- __rel_dyn_end
b 2f # skip first reserved entry
- PTR_ADDI t1, 2 * PTRSIZE
+ PTR_ADDIU t1, 2 * PTRSIZE
1:
lw t8, -4(t1) # t8 <-- relocation info
2:
blt t1, t2, 1b
- PTR_ADDI t1, 2 * PTRSIZE # each rel.dyn entry is 2*PTRSIZE bytes
+ PTR_ADDIU t1, 2 * PTRSIZE # each rel.dyn entry is 2*PTRSIZE bytes
/*
* Clear BSS
1:
PTR_S zero, 0(t1)
blt t1, t2, 1b
- PTR_ADDI t1, PTRSIZE
+ PTR_ADDIU t1, PTRSIZE
move a0, s0 # a0 <-- gd
move a1, s2
# SPDX-License-Identifier: GPL-2.0+
#
+dtb-$(CONFIG_TARGET_AP121) += ap121.dtb
+dtb-$(CONFIG_TARGET_AP143) += ap143.dtb
dtb-$(CONFIG_TARGET_PIC32MZDASK) += pic32mzda_sk.dtb
+dtb-$(CONFIG_BOARD_TPLINK_WDR4300) += tplink_wdr4300.dtb
targets += $(dtb-y)
--- /dev/null
+/*
+ * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+#include "ar933x.dtsi"
+
+/ {
+ model = "AP121 Reference Board";
+ compatible = "qca,ap121", "qca,ar933x";
+
+ aliases {
+ spi0 = &spi0;
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&xtal {
+ clock-frequency = <25000000>;
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&spi0 {
+ spi-max-frequency = <25000000>;
+ status = "okay";
+ spi-flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ memory-map = <0x9f000000 0x00800000>;
+ spi-max-frequency = <25000000>;
+ reg = <0>;
+ };
+};
--- /dev/null
+/*
+ * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+#include "qca953x.dtsi"
+
+/ {
+ model = "AP143 Reference Board";
+ compatible = "qca,ap143", "qca,qca953x";
+
+ aliases {
+ spi0 = &spi0;
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&xtal {
+ clock-frequency = <25000000>;
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&spi0 {
+ spi-max-frequency = <25000000>;
+ status = "okay";
+ spi-flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ memory-map = <0x9f000000 0x00800000>;
+ spi-max-frequency = <25000000>;
+ reg = <0>;
+ };
+};
--- /dev/null
+/*
+ * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include "skeleton.dtsi"
+
+/ {
+ compatible = "qca,ar933x";
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "mips,mips24Kc";
+ reg = <0>;
+ };
+ };
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ xtal: xtal {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-output-names = "xtal";
+ };
+ };
+
+ pinctrl {
+ u-boot,dm-pre-reloc;
+ compatible = "qca,ar933x-pinctrl";
+ ranges;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x18040000 0x100>;
+ };
+
+ ahb {
+ compatible = "simple-bus";
+ ranges;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ apb {
+ compatible = "simple-bus";
+ ranges;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ ehci0: ehci@1b000100 {
+ compatible = "generic-ehci";
+ reg = <0x1b000100 0x100>;
+
+ status = "disabled";
+ };
+
+ uart0: uart@18020000 {
+ compatible = "qca,ar9330-uart";
+ reg = <0x18020000 0x20>;
+ interrupts = <128 IRQ_TYPE_LEVEL_HIGH>;
+
+ status = "disabled";
+ };
+
+ gmac0: eth@0x19000000 {
+ compatible = "qca,ag7240-mac";
+ reg = <0x19000000 0x200>;
+ phy = <&phy0>;
+ phy-mode = "rmii";
+
+ status = "disabled";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+ };
+ };
+
+ gmac1: eth@0x1a000000 {
+ compatible = "qca,ag7240-mac";
+ reg = <0x1a000000 0x200>;
+ phy = <&phy0>;
+ phy-mode = "rgmii";
+
+ status = "disabled";
+ };
+ };
+
+ spi0: spi@1f000000 {
+ compatible = "qca,ar7100-spi";
+ reg = <0x1f000000 0x10>;
+ interrupts = <129 IRQ_TYPE_LEVEL_HIGH>;
+
+ status = "disabled";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+};
--- /dev/null
+/*
+ * Copyright (C) 2016 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include "skeleton.dtsi"
+
+/ {
+ compatible = "qca,ar934x";
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "mips,mips74Kc";
+ reg = <0>;
+ };
+ };
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ xtal: xtal {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-output-names = "xtal";
+ };
+ };
+
+ ahb {
+ compatible = "simple-bus";
+ ranges;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ apb {
+ compatible = "simple-bus";
+ ranges;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ ehci0: ehci@1b000100 {
+ compatible = "generic-ehci";
+ reg = <0x1b000100 0x100>;
+
+ status = "disabled";
+ };
+
+ uart0: uart@18020000 {
+ compatible = "ns16550";
+ reg = <0x18020000 0x20>;
+ reg-shift = <2>;
+
+ status = "disabled";
+ };
+
+ gmac0: eth@0x19000000 {
+ compatible = "qca,ag934x-mac";
+ reg = <0x19000000 0x200>;
+ phy = <&phy0>;
+ phy-mode = "rgmii";
+
+ status = "disabled";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+ };
+ };
+
+ gmac1: eth@0x1a000000 {
+ compatible = "qca,ag934x-mac";
+ reg = <0x1a000000 0x200>;
+ phy = <&phy1>;
+ phy-mode = "rgmii";
+
+ status = "disabled";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ phy1: ethernet-phy@0 {
+ reg = <0>;
+ };
+ };
+ };
+ };
+
+ spi0: spi@1f000000 {
+ compatible = "qca,ar7100-spi";
+ reg = <0x1f000000 0x10>;
+
+ status = "disabled";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+};
--- /dev/null
+/*
+ * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include "skeleton.dtsi"
+
+/ {
+ compatible = "qca,qca953x";
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "mips,mips24Kc";
+ reg = <0>;
+ };
+ };
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ xtal: xtal {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-output-names = "xtal";
+ };
+ };
+
+ pinctrl {
+ u-boot,dm-pre-reloc;
+ compatible = "qca,qca953x-pinctrl";
+ ranges;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x18040000 0x100>;
+ };
+
+ ahb {
+ compatible = "simple-bus";
+ ranges;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ apb {
+ compatible = "simple-bus";
+ ranges;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ uart0: uart@18020000 {
+ compatible = "ns16550";
+ reg = <0x18020000 0x20>;
+ reg-shift = <2>;
+ clock-frequency = <25000000>;
+ interrupts = <128 IRQ_TYPE_LEVEL_HIGH>;
+
+ status = "disabled";
+ };
+ };
+
+ spi0: spi@1f000000 {
+ compatible = "qca,ar7100-spi";
+ reg = <0x1f000000 0x10>;
+ interrupts = <129 IRQ_TYPE_LEVEL_HIGH>;
+
+ status = "disabled";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+};
--- /dev/null
+/*
+ * Copyright (C) 2016 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+#include "ar934x.dtsi"
+
+/ {
+ model = "TP-Link WDR4300 Board";
+ compatible = "tplink,wdr4300", "qca,ar934x";
+
+ aliases {
+ serial0 = &uart0;
+ spi0 = &spi0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&gmac0 {
+ phy-mode = "rgmii";
+ status = "okay";
+};
+
+&spi0 {
+ spi-max-frequency = <25000000>;
+ status = "okay";
+ spi-flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ memory-map = <0x1e000000 0x00800000>;
+ spi-max-frequency = <25000000>;
+ reg = <0>;
+ };
+};
+
+&uart0 {
+ clock-frequency = <40000000>;
+ status = "okay";
+};
+
+&xtal {
+ clock-frequency = <40000000>;
+};
unsigned long tbl;
unsigned long lastinc;
#endif
+#ifdef CONFIG_ARCH_ATH79
+ unsigned long id;
+ unsigned long soc;
+ unsigned long rev;
+ unsigned long ver;
+#endif
};
#include <asm-generic/global_data.h>
/* detect associativity */
srl \sz, $1, \off + MIPS_CONF1_DA_SHF - MIPS_CONF1_DA_SHF
andi \sz, \sz, (MIPS_CONF1_DA >> MIPS_CONF1_DA_SHF)
- addi \sz, \sz, 1
+ addiu \sz, \sz, 1
/* sz *= line_sz */
mul \sz, \sz, \line_sz
--- /dev/null
+menu "QCA/Atheros 7xxx/9xxx platforms"
+ depends on ARCH_ATH79
+
+config SYS_SOC
+ default "ath79"
+
+config SOC_AR933X
+ bool
+ select SUPPORTS_BIG_ENDIAN
+ select SUPPORTS_CPU_MIPS32_R1
+ select SUPPORTS_CPU_MIPS32_R2
+ select MIPS_TUNE_24KC
+ help
+ This supports QCA/Atheros ar933x family SOCs.
+
+config SOC_AR934X
+ bool
+ select SUPPORTS_BIG_ENDIAN
+ select SUPPORTS_CPU_MIPS32_R1
+ select SUPPORTS_CPU_MIPS32_R2
+ select MIPS_TUNE_74KC
+ help
+ This supports QCA/Atheros ar934x family SOCs.
+
+config SOC_QCA953X
+ bool
+ select SUPPORTS_BIG_ENDIAN
+ select SUPPORTS_CPU_MIPS32_R1
+ select SUPPORTS_CPU_MIPS32_R2
+ select MIPS_TUNE_24KC
+ help
+ This supports QCA/Atheros qca953x family SOCs.
+
+choice
+ prompt "Board select"
+
+config TARGET_AP121
+ bool "AP121 Reference Board"
+ select SOC_AR933X
+
+config TARGET_AP143
+ bool "AP143 Reference Board"
+ select SOC_QCA953X
+
+config BOARD_TPLINK_WDR4300
+ bool "TP-Link WDR4300 Board"
+ select SOC_AR934X
+
+endchoice
+
+source "board/qca/ap121/Kconfig"
+source "board/qca/ap143/Kconfig"
+source "board/tplink/wdr4300/Kconfig"
+
+endmenu
--- /dev/null
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += reset.o
+obj-y += cpu.o
+obj-y += dram.o
+
+obj-$(CONFIG_SOC_AR933X) += ar933x/
+obj-$(CONFIG_SOC_AR934X) += ar934x/
+obj-$(CONFIG_SOC_QCA953X) += qca953x/
--- /dev/null
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += clk.o
+obj-y += ddr.o
+obj-y += lowlevel_init.o
--- /dev/null
+/*
+ * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/addrspace.h>
+#include <asm/types.h>
+#include <mach/ar71xx_regs.h>
+#include <mach/reset.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static u32 ar933x_get_xtal(void)
+{
+ u32 val;
+
+ val = get_bootstrap();
+ if (val & AR933X_BOOTSTRAP_REF_CLK_40)
+ return 40000000;
+ else
+ return 25000000;
+}
+
+int get_serial_clock(void)
+{
+ return ar933x_get_xtal();
+}
+
+int get_clocks(void)
+{
+ void __iomem *regs;
+ u32 val, xtal, pll, div;
+
+ regs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE,
+ MAP_NOCACHE);
+ xtal = ar933x_get_xtal();
+ val = readl(regs + AR933X_PLL_CPU_CONFIG_REG);
+
+ /* VCOOUT = XTAL * DIV_INT */
+ div = (val >> AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT)
+ & AR933X_PLL_CPU_CONFIG_REFDIV_MASK;
+ pll = xtal / div;
+
+ /* PLLOUT = VCOOUT * (1/2^OUTDIV) */
+ div = (val >> AR933X_PLL_CPU_CONFIG_NINT_SHIFT)
+ & AR933X_PLL_CPU_CONFIG_NINT_MASK;
+ pll *= div;
+ div = (val >> AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT)
+ & AR933X_PLL_CPU_CONFIG_OUTDIV_MASK;
+ if (!div)
+ div = 1;
+ pll >>= div;
+
+ val = readl(regs + AR933X_PLL_CLK_CTRL_REG);
+
+ /* CPU_CLK = PLLOUT / CPU_POST_DIV */
+ div = ((val >> AR933X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT)
+ & AR933X_PLL_CLK_CTRL_CPU_POST_DIV_MASK) + 1;
+ gd->cpu_clk = pll / div;
+
+ /* DDR_CLK = PLLOUT / DDR_POST_DIV */
+ div = ((val >> AR933X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT)
+ & AR933X_PLL_CLK_CTRL_DDR_POST_DIV_MASK) + 1;
+ gd->mem_clk = pll / div;
+
+ /* AHB_CLK = PLLOUT / AHB_POST_DIV */
+ div = ((val >> AR933X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT)
+ & AR933X_PLL_CLK_CTRL_AHB_POST_DIV_MASK) + 1;
+ gd->bus_clk = pll / div;
+
+ return 0;
+}
+
+ulong get_bus_freq(ulong dummy)
+{
+ if (!gd->bus_clk)
+ get_clocks();
+ return gd->bus_clk;
+}
+
+ulong get_ddr_freq(ulong dummy)
+{
+ if (!gd->mem_clk)
+ get_clocks();
+ return gd->mem_clk;
+}
--- /dev/null
+/*
+ * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
+ * Based on Atheros LSDK/QSDK
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/addrspace.h>
+#include <asm/types.h>
+#include <mach/ar71xx_regs.h>
+#include <mach/reset.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define DDR_CTRL_UPD_EMR3S BIT(5)
+#define DDR_CTRL_UPD_EMR2S BIT(4)
+#define DDR_CTRL_PRECHARGE BIT(3)
+#define DDR_CTRL_AUTO_REFRESH BIT(2)
+#define DDR_CTRL_UPD_EMRS BIT(1)
+#define DDR_CTRL_UPD_MRS BIT(0)
+
+#define DDR_REFRESH_EN BIT(14)
+#define DDR_REFRESH_M 0x3ff
+#define DDR_REFRESH(x) ((x) & 0x3ff)
+#define DDR_REFRESH_VAL_25M (DDR_REFRESH_EN | DDR_REFRESH(390))
+#define DDR_REFRESH_VAL_40M (DDR_REFRESH_EN | DDR_REFRESH(624))
+
+#define DDR_TRAS_S 0
+#define DDR_TRAS_M 0x1f
+#define DDR_TRAS(x) ((x) << DDR_TRAS_S)
+#define DDR_TRCD_M 0xf
+#define DDR_TRCD_S 5
+#define DDR_TRCD(x) ((x) << DDR_TRCD_S)
+#define DDR_TRP_M 0xf
+#define DDR_TRP_S 9
+#define DDR_TRP(x) ((x) << DDR_TRP_S)
+#define DDR_TRRD_M 0xf
+#define DDR_TRRD_S 13
+#define DDR_TRRD(x) ((x) << DDR_TRRD_S)
+#define DDR_TRFC_M 0x7f
+#define DDR_TRFC_S 17
+#define DDR_TRFC(x) ((x) << DDR_TRFC_S)
+#define DDR_TMRD_M 0xf
+#define DDR_TMRD_S 23
+#define DDR_TMRD(x) ((x) << DDR_TMRD_S)
+#define DDR_CAS_L_M 0x17
+#define DDR_CAS_L_S 27
+#define DDR_CAS_L(x) (((x) & DDR_CAS_L_M) << DDR_CAS_L_S)
+#define DDR_OPEN BIT(30)
+#define DDR_CONF_REG_VAL (DDR_TRAS(16) | DDR_TRCD(6) | \
+ DDR_TRP(6) | DDR_TRRD(4) | \
+ DDR_TRFC(30) | DDR_TMRD(15) | \
+ DDR_CAS_L(7) | DDR_OPEN)
+
+#define DDR_BURST_LEN_S 0
+#define DDR_BURST_LEN_M 0xf
+#define DDR_BURST_LEN(x) ((x) << DDR_BURST_LEN_S)
+#define DDR_BURST_TYPE BIT(4)
+#define DDR_CNTL_OE_EN BIT(5)
+#define DDR_PHASE_SEL BIT(6)
+#define DDR_CKE BIT(7)
+#define DDR_TWR_S 8
+#define DDR_TWR_M 0xf
+#define DDR_TWR(x) ((x) << DDR_TWR_S)
+#define DDR_TRTW_S 12
+#define DDR_TRTW_M 0x1f
+#define DDR_TRTW(x) ((x) << DDR_TRTW_S)
+#define DDR_TRTP_S 17
+#define DDR_TRTP_M 0xf
+#define DDR_TRTP(x) ((x) << DDR_TRTP_S)
+#define DDR_TWTR_S 21
+#define DDR_TWTR_M 0x1f
+#define DDR_TWTR(x) ((x) << DDR_TWTR_S)
+#define DDR_G_OPEN_L_S 26
+#define DDR_G_OPEN_L_M 0xf
+#define DDR_G_OPEN_L(x) ((x) << DDR_G_OPEN_L_S)
+#define DDR_HALF_WIDTH_LOW BIT(31)
+#define DDR_CONF2_REG_VAL (DDR_BURST_LEN(8) | DDR_CNTL_OE_EN | \
+ DDR_CKE | DDR_TWR(6) | DDR_TRTW(14) | \
+ DDR_TRTP(8) | DDR_TWTR(14) | \
+ DDR_G_OPEN_L(7) | DDR_HALF_WIDTH_LOW)
+
+#define DDR2_CONF_TWL_S 10
+#define DDR2_CONF_TWL_M 0xf
+#define DDR2_CONF_TWL(x) (((x) & DDR2_CONF_TWL_M) << DDR2_CONF_TWL_S)
+#define DDR2_CONF_ODT BIT(9)
+#define DDR2_CONF_TFAW_S 2
+#define DDR2_CONF_TFAW_M 0x3f
+#define DDR2_CONF_TFAW(x) (((x) & DDR2_CONF_TFAW_M) << DDR2_CONF_TFAW_S)
+#define DDR2_CONF_EN BIT(0)
+#define DDR2_CONF_VAL (DDR2_CONF_TWL(2) | DDR2_CONF_ODT | \
+ DDR2_CONF_TFAW(22) | DDR2_CONF_EN)
+
+#define DDR1_EXT_MODE_VAL 0x02
+#define DDR2_EXT_MODE_VAL 0x402
+#define DDR2_EXT_MODE_OCD_VAL 0x382
+#define DDR1_MODE_DLL_VAL 0x133
+#define DDR2_MODE_DLL_VAL 0x100
+#define DDR1_MODE_VAL 0x33
+#define DDR2_MODE_VAL 0xa33
+#define DDR_TAP_VAL0 0x08
+#define DDR_TAP_VAL1 0x09
+
+void ddr_init(void)
+{
+ void __iomem *regs;
+ u32 val;
+
+ regs = map_physmem(AR71XX_DDR_CTRL_BASE, AR71XX_DDR_CTRL_SIZE,
+ MAP_NOCACHE);
+
+ writel(DDR_CONF_REG_VAL, regs + AR71XX_DDR_REG_CONFIG);
+ writel(DDR_CONF2_REG_VAL, regs + AR71XX_DDR_REG_CONFIG2);
+
+ val = get_bootstrap();
+ if (val & AR933X_BOOTSTRAP_DDR2) {
+ /* AHB maximum timeout */
+ writel(0xfffff, regs + AR933X_DDR_REG_TIMEOUT_MAX);
+
+ /* Enable DDR2 */
+ writel(DDR2_CONF_VAL, regs + AR933X_DDR_REG_DDR2_CONFIG);
+
+ /* Precharge All */
+ writel(DDR_CTRL_PRECHARGE, regs + AR71XX_DDR_REG_CONTROL);
+
+ /* Disable High Temperature Self-Refresh, Full Array */
+ writel(0x00, regs + AR933X_DDR_REG_EMR2);
+
+ /* Extended Mode Register 2 Set (EMR2S) */
+ writel(DDR_CTRL_UPD_EMR2S, regs + AR71XX_DDR_REG_CONTROL);
+
+ writel(0x00, regs + AR933X_DDR_REG_EMR3);
+
+ /* Extended Mode Register 3 Set (EMR3S) */
+ writel(DDR_CTRL_UPD_EMR3S, regs + AR71XX_DDR_REG_CONTROL);
+
+ /* Enable DLL, Full strength, ODT Disabled */
+ writel(0x00, regs + AR71XX_DDR_REG_EMR);
+
+ /* Extended Mode Register Set (EMRS) */
+ writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL);
+
+ /* Reset DLL */
+ writel(DDR2_MODE_DLL_VAL, regs + AR71XX_DDR_REG_MODE);
+
+ /* Mode Register Set (MRS) */
+ writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL);
+
+ /* Precharge All */
+ writel(DDR_CTRL_PRECHARGE, regs + AR71XX_DDR_REG_CONTROL);
+
+ /* Auto Refresh */
+ writel(DDR_CTRL_AUTO_REFRESH, regs + AR71XX_DDR_REG_CONTROL);
+ writel(DDR_CTRL_AUTO_REFRESH, regs + AR71XX_DDR_REG_CONTROL);
+
+ /* Write recovery (WR) 6 clock, CAS Latency 3, Burst Length 8 */
+ writel(DDR2_MODE_VAL, regs + AR71XX_DDR_REG_MODE);
+ /* Mode Register Set (MRS) */
+ writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL);
+
+ /* Enable OCD defaults, Enable DLL, Reduced Drive Strength */
+ writel(DDR2_EXT_MODE_OCD_VAL, regs + AR71XX_DDR_REG_EMR);
+
+ /* Extended Mode Register Set (EMRS) */
+ writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL);
+
+ /* OCD exit, Enable DLL, Enable /DQS, Reduced Drive Strength */
+ writel(DDR2_EXT_MODE_VAL, regs + AR71XX_DDR_REG_EMR);
+ /* Extended Mode Register Set (EMRS) */
+ writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL);
+
+ /* Refresh time control */
+ if (val & AR933X_BOOTSTRAP_REF_CLK_40)
+ writel(DDR_REFRESH_VAL_40M, regs +
+ AR71XX_DDR_REG_REFRESH);
+ else
+ writel(DDR_REFRESH_VAL_25M, regs +
+ AR71XX_DDR_REG_REFRESH);
+
+ /* DQS 0 Tap Control */
+ writel(DDR_TAP_VAL0, regs + AR71XX_DDR_REG_TAP_CTRL0);
+
+ /* DQS 1 Tap Control */
+ writel(DDR_TAP_VAL1, regs + AR71XX_DDR_REG_TAP_CTRL1);
+
+ /* For 16-bit DDR */
+ writel(0xff, regs + AR71XX_DDR_REG_RD_CYCLE);
+ } else {
+ /* AHB maximum timeout */
+ writel(0xfffff, regs + AR933X_DDR_REG_TIMEOUT_MAX);
+
+ /* Precharge All */
+ writel(DDR_CTRL_PRECHARGE, regs + AR71XX_DDR_REG_CONTROL);
+
+ /* Reset DLL, Burst Length 8, CAS Latency 3 */
+ writel(DDR1_MODE_DLL_VAL, regs + AR71XX_DDR_REG_MODE);
+
+ /* Forces an MRS update cycle in DDR */
+ writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL);
+
+ /* Enable DLL, Full strength */
+ writel(DDR1_EXT_MODE_VAL, regs + AR71XX_DDR_REG_EMR);
+
+ /* Extended Mode Register Set (EMRS) */
+ writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL);
+
+ /* Precharge All */
+ writel(DDR_CTRL_PRECHARGE, regs + AR71XX_DDR_REG_CONTROL);
+
+ /* Normal DLL, Burst Length 8, CAS Latency 3 */
+ writel(DDR1_MODE_VAL, regs + AR71XX_DDR_REG_MODE);
+
+ /* Mode Register Set (MRS) */
+ writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL);
+
+ /* Refresh time control */
+ if (val & AR933X_BOOTSTRAP_REF_CLK_40)
+ writel(DDR_REFRESH_VAL_40M, regs +
+ AR71XX_DDR_REG_REFRESH);
+ else
+ writel(DDR_REFRESH_VAL_25M, regs +
+ AR71XX_DDR_REG_REFRESH);
+
+ /* DQS 0 Tap Control */
+ writel(DDR_TAP_VAL0, regs + AR71XX_DDR_REG_TAP_CTRL0);
+
+ /* DQS 1 Tap Control */
+ writel(DDR_TAP_VAL1, regs + AR71XX_DDR_REG_TAP_CTRL1);
+
+ /* For 16-bit DDR */
+ writel(0xff, regs + AR71XX_DDR_REG_RD_CYCLE);
+ }
+}
+
+void ddr_tap_tuning(void)
+{
+ void __iomem *regs;
+ u32 *addr_k0, *addr_k1, *addr;
+ u32 val, tap, upper, lower;
+ int i, j, dir, err, done;
+
+ regs = map_physmem(AR71XX_DDR_CTRL_BASE, AR71XX_DDR_CTRL_SIZE,
+ MAP_NOCACHE);
+
+ /* Init memory pattern */
+ addr = (void *)CKSEG0ADDR(0x2000);
+ for (i = 0; i < 256; i++) {
+ val = 0;
+ for (j = 0; j < 8; j++) {
+ if (i & (1 << j)) {
+ if (j % 2)
+ val |= 0xffff0000;
+ else
+ val |= 0x0000ffff;
+ }
+
+ if (j % 2) {
+ *addr++ = val;
+ val = 0;
+ }
+ }
+ }
+
+ err = 0;
+ done = 0;
+ dir = 1;
+ tap = readl(regs + AR71XX_DDR_REG_TAP_CTRL0);
+ val = tap;
+ while (!done) {
+ err = 0;
+
+ /* Update new DDR tap value */
+ writel(val, regs + AR71XX_DDR_REG_TAP_CTRL0);
+ writel(val, regs + AR71XX_DDR_REG_TAP_CTRL1);
+
+ /* Compare DDR with cache */
+ for (i = 0; i < 2; i++) {
+ addr_k1 = (void *)CKSEG1ADDR(0x2000);
+ addr_k0 = (void *)CKSEG0ADDR(0x2000);
+ addr = (void *)CKSEG0ADDR(0x3000);
+
+ while (addr_k0 < addr) {
+ if (*addr_k1++ != *addr_k0++) {
+ err = 1;
+ break;
+ }
+ }
+
+ if (err)
+ break;
+ }
+
+ if (err) {
+ /* Save upper/lower threshold if error */
+ if (dir) {
+ dir = 0;
+ val--;
+ upper = val;
+ val = tap;
+ } else {
+ val++;
+ lower = val;
+ done = 1;
+ }
+ } else {
+ /* Try the next value until limitation */
+ if (dir) {
+ if (val < 0x20) {
+ val++;
+ } else {
+ dir = 0;
+ upper = val;
+ val = tap;
+ }
+ } else {
+ if (!val) {
+ lower = val;
+ done = 1;
+ } else {
+ val--;
+ }
+ }
+ }
+ }
+
+ /* compute an intermediate value and write back */
+ val = (upper + lower) / 2;
+ writel(val, regs + AR71XX_DDR_REG_TAP_CTRL0);
+ val++;
+ writel(val, regs + AR71XX_DDR_REG_TAP_CTRL1);
+}
--- /dev/null
+/*
+ * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
+ * Based on Atheros LSDK/QSDK and u-boot_mod project
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <asm/asm.h>
+#include <asm/regdef.h>
+#include <asm/mipsregs.h>
+#include <asm/addrspace.h>
+#include <mach/ar71xx_regs.h>
+
+#define SET_BIT(val, bit) ((val) | (1 << (bit)))
+#define SET_PLL_PD(val) SET_BIT(val, 30)
+#define AHB_DIV_TO_4(val) SET_BIT(SET_BIT(val, 15), 16)
+#define PLL_BYPASS(val) SET_BIT(val, 2)
+
+#define MK_PLL_CONF(divint, refdiv, range, outdiv) \
+ (((0x3F & divint) << 10) | \
+ ((0x1F & refdiv) << 16) | \
+ ((0x1 & range) << 21) | \
+ ((0x7 & outdiv) << 23) )
+
+#define MK_CLK_CNTL(cpudiv, ddrdiv, ahbdiv) \
+ (((0x3 & (cpudiv - 1)) << 5) | \
+ ((0x3 & (ddrdiv - 1)) << 10) | \
+ ((0x3 & (ahbdiv - 1)) << 15) )
+
+/*
+ * PLL_CPU_CONFIG_VAL
+ *
+ * Bit30 is set (CPU_PLLPWD = 1 -> power down control for CPU PLL)
+ * After PLL configuration we need to clear this bit
+ *
+ * Values written into CPU PLL Configuration (CPU_PLL_CONFIG)
+ *
+ * bits 10..15 (6bit) DIV_INT (Integer part of the DIV to CPU PLL)
+ * => 32 (0x20) VCOOUT = XTAL * DIV_INT
+ * bits 16..20 (5bit) REFDIV (Reference clock divider)
+ * => 1 (0x1) [Must start at values 1]
+ * bits 21 (1bit) RANGE (VCO frequency range of the CPU PLL)
+ * => 0 (0x0) [Doesn't impact clock values]
+ * bits 23..25 (3bit) OUTDIV (Ratio between VCO and PLL output)
+ * => 1 (0x1) [0 is illegal!]
+ * PLLOUT = VCOOUT * (1/2^OUTDIV)
+ */
+/* DIV_INT=32 (25MHz*32/2=400MHz), REFDIV=1, RANGE=0, OUTDIV=1 */
+#define PLL_CPU_CONFIG_VAL_40M MK_PLL_CONF(20, 1, 0, 1)
+/* DIV_INT=20 (40MHz*20/2=400MHz), REFDIV=1, RANGE=0, OUTDIV=1 */
+#define PLL_CPU_CONFIG_VAL_25M MK_PLL_CONF(32, 1, 0, 1)
+
+/*
+ * PLL_CLK_CONTROL_VAL
+ *
+ * In PLL_CLK_CONTROL_VAL bit 2 is set (BYPASS = 1 -> bypass PLL)
+ * After PLL configuration we need to clear this bit
+ *
+ * Values written into CPU Clock Control Register CLOCK_CONTROL
+ *
+ * bits 2 (1bit) BYPASS (Bypass PLL. This defaults to 1 for test.
+ * Software must enable the CPU PLL for normal and
+ * then set this bit to 0)
+ * bits 5..6 (2bit) CPU_POST_DIV => 0 (DEFAULT, Ratio = 1)
+ * CPU_CLK = PLLOUT / CPU_POST_DIV
+ * bits 10..11 (2bit) DDR_POST_DIV => 0 (DEFAULT, Ratio = 1)
+ * DDR_CLK = PLLOUT / DDR_POST_DIV
+ * bits 15..16 (2bit) AHB_POST_DIV => 1 (DEFAULT, Ratio = 2)
+ * AHB_CLK = PLLOUT / AHB_POST_DIV
+ *
+ */
+#define PLL_CLK_CONTROL_VAL MK_CLK_CNTL(1, 1, 2)
+
+ .text
+ .set noreorder
+
+LEAF(lowlevel_init)
+ /* These three WLAN_RESET will avoid original issue */
+ li t3, 0x03
+1:
+ li t0, CKSEG1ADDR(AR71XX_RESET_BASE)
+ lw t1, AR933X_RESET_REG_RESET_MODULE(t0)
+ ori t1, t1, 0x0800
+ sw t1, AR933X_RESET_REG_RESET_MODULE(t0)
+ nop
+ lw t1, AR933X_RESET_REG_RESET_MODULE(t0)
+ li t2, 0xfffff7ff
+ and t1, t1, t2
+ sw t1, AR933X_RESET_REG_RESET_MODULE(t0)
+ nop
+ addi t3, t3, -1
+ bnez t3, 1b
+ nop
+
+ li t2, 0x20
+2:
+ beqz t2, 1b
+ nop
+ addi t2, t2, -1
+ lw t5, AR933X_RESET_REG_BOOTSTRAP(t0)
+ andi t1, t5, 0x10
+ bnez t1, 2b
+ nop
+
+ li t1, 0x02110E
+ sw t1, AR933X_RESET_REG_BOOTSTRAP(t0)
+ nop
+
+ /* RTC Force Wake */
+ li t0, CKSEG1ADDR(AR933X_RTC_BASE)
+ li t1, 0x03
+ sw t1, AR933X_RTC_REG_FORCE_WAKE(t0)
+ nop
+ nop
+
+ /* RTC Reset */
+ li t1, 0x00
+ sw t1, AR933X_RTC_REG_RESET(t0)
+ nop
+ nop
+
+ li t1, 0x01
+ sw t1, AR933X_RTC_REG_RESET(t0)
+ nop
+ nop
+
+ /* Wait for RTC in on state */
+1:
+ lw t1, AR933X_RTC_REG_STATUS(t0)
+ andi t1, t1, 0x02
+ beqz t1, 1b
+ nop
+
+ /* Program ki/kd */
+ li t0, CKSEG1ADDR(AR933X_SRIF_BASE)
+ andi t1, t5, 0x01 # t5 BOOT_STRAP
+ bnez t1, 1f
+ nop
+ li t1, 0x19e82f01
+ b 2f
+ nop
+1:
+ li t1, 0x18e82f01
+2:
+ sw t1, AR933X_SRIF_DDR_DPLL2_REG(t0)
+
+ /* Program phase shift */
+ lw t1, AR933X_SRIF_DDR_DPLL3_REG(t0)
+ li t2, 0xc07fffff
+ and t1, t1, t2
+ li t2, 0x800000
+ or t1, t1, t2
+ sw t1, AR933X_SRIF_DDR_DPLL3_REG(t0)
+ nop
+
+ /* in some cases, the SoC doesn't start with higher clock on AHB */
+ li t0, CKSEG1ADDR(AR71XX_PLL_BASE)
+ li t1, AHB_DIV_TO_4(PLL_BYPASS(PLL_CLK_CONTROL_VAL))
+ sw t1, AR933X_PLL_CLK_CTRL_REG(t0)
+ nop
+
+ /* Set SETTLE_TIME in CPU PLL */
+ andi t1, t5, 0x01 # t5 BOOT_STRAP
+ bnez t1, 1f
+ nop
+ li t1, 0x0352
+ b 2f
+ nop
+1:
+ li t1, 0x0550
+2:
+ sw t1, AR71XX_PLL_REG_SEC_CONFIG(t0)
+ nop
+
+ /* Set nint, frac, refdiv, outdiv, range according to xtal */
+0:
+ andi t1, t5, 0x01 # t5 BOOT_STRAP
+ bnez t1, 1f
+ nop
+ li t1, SET_PLL_PD(PLL_CPU_CONFIG_VAL_25M)
+ b 2f
+ nop
+1:
+ li t1, SET_PLL_PD(PLL_CPU_CONFIG_VAL_40M)
+2:
+ sw t1, AR933X_PLL_CPU_CONFIG_REG(t0)
+ nop
+1:
+ lw t1, AR933X_PLL_CPU_CONFIG_REG(t0)
+ li t2, 0x80000000
+ and t1, t1, t2
+ bnez t1, 1b
+ nop
+
+ /* Put frac bit19:10 configuration */
+ li t1, 0x1003E8
+ sw t1, AR933X_PLL_DITHER_FRAC_REG(t0)
+ nop
+
+ /* Clear PLL power down bit in CPU PLL configuration */
+ andi t1, t5, 0x01 # t5 BOOT_STRAP
+ bnez t1, 1f
+ nop
+ li t1, PLL_CPU_CONFIG_VAL_25M
+ b 2f
+ nop
+1:
+ li t1, PLL_CPU_CONFIG_VAL_40M
+2:
+ sw t1, AR933X_PLL_CPU_CONFIG_REG(t0)
+ nop
+
+ /* Wait for PLL update -> bit 31 in CPU_PLL_CONFIG should be 0 */
+1:
+ lw t1, AR933X_PLL_CPU_CONFIG_REG(t0)
+ li t2, 0x80000000
+ and t1, t1, t2
+ bnez t1, 1b
+ nop
+
+ /* Confirm DDR PLL lock */
+ li t3, 100
+ li t4, 0
+
+2:
+ addi t4, t4, 1
+ bgt t4, t3, 0b
+ nop
+
+ li t3, 5
+3:
+ /* Clear do_meas */
+ li t0, CKSEG1ADDR(AR933X_SRIF_BASE)
+ lw t1, AR933X_SRIF_DDR_DPLL3_REG(t0)
+ li t2, 0xBFFFFFFF
+ and t1, t1, t2
+ sw t1, AR933X_SRIF_DDR_DPLL3_REG(t0)
+ nop
+
+ li t2, 10
+1:
+ subu t2, t2, 1
+ bnez t2, 1b
+ nop
+
+ /* Set do_meas */
+ li t2, 0x40000000
+ or t1, t1, t2
+ sw t1, AR933X_SRIF_DDR_DPLL3_REG(t0)
+ nop
+
+ /* Check meas_done */
+1:
+ lw t1, AR933X_SRIF_DDR_DPLL4_REG(t0)
+ andi t1, t1, 0x8
+ beqz t1, 1b
+ nop
+
+ lw t1, AR933X_SRIF_DDR_DPLL3_REG(t0)
+ li t2, 0x007FFFF8
+ and t1, t1, t2
+ srl t1, t1, 3
+ li t2, 0x4000
+ bgt t1, t2, 2b
+ nop
+ addi t3, t3, -1
+ bnez t3, 3b
+ nop
+
+ /* clear PLL bypass (bit 2) in CPU CLOCK CONTROL register */
+ li t0, CKSEG1ADDR(AR71XX_PLL_BASE)
+ li t1, PLL_CLK_CONTROL_VAL
+ sw t1, AR933X_PLL_CLK_CTRL_REG(t0)
+ nop
+
+ nop
+ jr ra
+ nop
+ END(lowlevel_init)
--- /dev/null
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += cpu.o
+obj-y += clk.o
+obj-y += ddr.o
--- /dev/null
+/*
+ * Copyright (C) 2016 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/addrspace.h>
+#include <asm/types.h>
+#include <mach/ar71xx_regs.h>
+#include <mach/reset.h>
+#include <wait_bit.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * The math for calculating PLL:
+ * NFRAC * 2^8
+ * NINT + -------------
+ * XTAL [MHz] 2^(18 - 1)
+ * PLL [MHz] = ------------ * ----------------------
+ * REFDIV 2^OUTDIV
+ *
+ * Unfortunatelly, there is no way to reliably compute the variables.
+ * The vendor U-Boot port contains macros for various combinations of
+ * CPU PLL / DDR PLL / AHB bus speed and there is no obvious pattern
+ * in those numbers.
+ */
+struct ar934x_pll_config {
+ u8 range;
+ u8 refdiv;
+ u8 outdiv;
+ /* Index 0 is for XTAL=25MHz , Index 1 is for XTAL=40MHz */
+ u8 nint[2];
+};
+
+struct ar934x_clock_config {
+ u16 cpu_freq;
+ u16 ddr_freq;
+ u16 ahb_freq;
+
+ struct ar934x_pll_config cpu_pll;
+ struct ar934x_pll_config ddr_pll;
+};
+
+static const struct ar934x_clock_config ar934x_clock_config[] = {
+ { 300, 300, 150, { 1, 1, 1, { 24, 15 } }, { 1, 1, 1, { 24, 15 } } },
+ { 400, 200, 200, { 1, 1, 1, { 32, 20 } }, { 1, 1, 2, { 32, 20 } } },
+ { 400, 400, 200, { 0, 1, 1, { 32, 20 } }, { 0, 1, 1, { 32, 20 } } },
+ { 500, 400, 200, { 1, 1, 0, { 20, 12 } }, { 0, 1, 1, { 32, 20 } } },
+ { 533, 400, 200, { 1, 1, 0, { 21, 13 } }, { 0, 1, 1, { 32, 20 } } },
+ { 533, 500, 250, { 1, 1, 0, { 21, 13 } }, { 0, 1, 0, { 20, 12 } } },
+ { 560, 480, 240, { 1, 1, 0, { 22, 14 } }, { 1, 1, 0, { 19, 12 } } },
+ { 566, 400, 200, { 1, 1, 0, { 22, 14 } }, { 1, 1, 0, { 16, 10 } } },
+ { 566, 450, 225, { 1, 1, 0, { 22, 14 } }, { 0, 1, 1, { 36, 22 } } },
+ { 566, 475, 237, { 1, 1, 0, { 22, 14 } }, { 1, 1, 0, { 19, 11 } } },
+ { 566, 500, 250, { 1, 1, 0, { 22, 14 } }, { 1, 1, 0, { 20, 12 } } },
+ { 566, 525, 262, { 1, 1, 0, { 22, 14 } }, { 1, 1, 0, { 21, 13 } } },
+ { 566, 550, 275, { 1, 1, 0, { 22, 14 } }, { 1, 1, 0, { 22, 13 } } },
+ { 600, 266, 133, { 0, 1, 0, { 24, 15 } }, { 1, 1, 1, { 21, 16 } } },
+ { 600, 266, 200, { 0, 1, 0, { 24, 15 } }, { 1, 1, 1, { 21, 16 } } },
+ { 600, 300, 150, { 0, 1, 0, { 24, 15 } }, { 0, 1, 1, { 24, 15 } } },
+ { 600, 332, 166, { 0, 1, 0, { 24, 15 } }, { 1, 1, 1, { 26, 16 } } },
+ { 600, 332, 200, { 0, 1, 0, { 24, 15 } }, { 1, 1, 1, { 26, 16 } } },
+ { 600, 400, 200, { 0, 1, 0, { 24, 15 } }, { 0, 1, 1, { 32, 20 } } },
+ { 600, 450, 200, { 0, 1, 0, { 24, 15 } }, { 0, 1, 0, { 18, 20 } } },
+ { 600, 500, 250, { 0, 1, 0, { 24, 15 } }, { 1, 1, 0, { 20, 12 } } },
+ { 600, 525, 262, { 0, 1, 0, { 24, 15 } }, { 0, 1, 0, { 21, 20 } } },
+ { 600, 550, 275, { 0, 1, 0, { 24, 15 } }, { 0, 1, 0, { 22, 20 } } },
+ { 600, 575, 287, { 0, 1, 0, { 24, 15 } }, { 0, 1, 0, { 23, 14 } } },
+ { 600, 600, 300, { 0, 1, 0, { 24, 15 } }, { 0, 1, 0, { 24, 20 } } },
+ { 600, 650, 325, { 0, 1, 0, { 24, 15 } }, { 0, 1, 0, { 26, 20 } } },
+ { 650, 600, 300, { 0, 1, 0, { 26, 15 } }, { 0, 1, 0, { 24, 20 } } },
+ { 700, 400, 200, { 3, 1, 0, { 28, 17 } }, { 0, 1, 1, { 32, 20 } } },
+};
+
+static void ar934x_srif_pll_cfg(void __iomem *pll_reg_base, const u32 srif_val)
+{
+ u32 reg;
+ do {
+ writel(0x10810f00, pll_reg_base + 0x4);
+ writel(srif_val, pll_reg_base + 0x0);
+ writel(0xd0810f00, pll_reg_base + 0x4);
+ writel(0x03000000, pll_reg_base + 0x8);
+ writel(0xd0800f00, pll_reg_base + 0x4);
+
+ clrbits_be32(pll_reg_base + 0x8, BIT(30));
+ udelay(5);
+ setbits_be32(pll_reg_base + 0x8, BIT(30));
+ udelay(5);
+
+ wait_for_bit("clk", pll_reg_base + 0xc, BIT(3), 1, 10, 0);
+
+ clrbits_be32(pll_reg_base + 0x8, BIT(30));
+ udelay(5);
+
+ /* Check if CPU SRIF PLL locked. */
+ reg = readl(pll_reg_base + 0x8);
+ reg = (reg & 0x7ffff8) >> 3;
+ } while (reg >= 0x40000);
+}
+
+void ar934x_pll_init(const u16 cpu_mhz, const u16 ddr_mhz, const u16 ahb_mhz)
+{
+ void __iomem *srif_regs = map_physmem(AR934X_SRIF_BASE,
+ AR934X_SRIF_SIZE, MAP_NOCACHE);
+ void __iomem *pll_regs = map_physmem(AR71XX_PLL_BASE,
+ AR71XX_PLL_SIZE, MAP_NOCACHE);
+ const struct ar934x_pll_config *pll_cfg;
+ int i, pll_nint, pll_refdiv, xtal_40 = 0;
+ u32 reg, cpu_pll, cpu_srif, ddr_pll, ddr_srif;
+
+ /* Configure SRIF PLL with initial values. */
+ writel(0x13210f00, srif_regs + AR934X_SRIF_CPU_DPLL2_REG);
+ writel(0x03000000, srif_regs + AR934X_SRIF_CPU_DPLL3_REG);
+ writel(0x13210f00, srif_regs + AR934X_SRIF_DDR_DPLL2_REG);
+ writel(0x03000000, srif_regs + AR934X_SRIF_DDR_DPLL3_REG);
+ writel(0x03000000, srif_regs + 0x188); /* Undocumented reg :-) */
+
+ /* Test for 40MHz XTAL */
+ reg = get_bootstrap();
+ if (reg & AR934X_BOOTSTRAP_REF_CLK_40) {
+ xtal_40 = 1;
+ cpu_srif = 0x41c00000;
+ ddr_srif = 0x41680000;
+ } else {
+ xtal_40 = 0;
+ cpu_srif = 0x29c00000;
+ ddr_srif = 0x29680000;
+ }
+
+ /* Locate CPU/DDR PLL configuration */
+ for (i = 0; i < ARRAY_SIZE(ar934x_clock_config); i++) {
+ if (cpu_mhz != ar934x_clock_config[i].cpu_freq)
+ continue;
+ if (ddr_mhz != ar934x_clock_config[i].ddr_freq)
+ continue;
+ if (ahb_mhz != ar934x_clock_config[i].ahb_freq)
+ continue;
+
+ /* Entry found */
+ pll_cfg = &ar934x_clock_config[i].cpu_pll;
+ pll_nint = pll_cfg->nint[xtal_40];
+ pll_refdiv = pll_cfg->refdiv;
+ cpu_pll =
+ (pll_nint << AR934X_PLL_CPU_CONFIG_NINT_SHIFT) |
+ (pll_refdiv << AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT) |
+ (pll_cfg->range << AR934X_PLL_CPU_CONFIG_RANGE_SHIFT) |
+ (pll_cfg->outdiv << AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT);
+
+ pll_cfg = &ar934x_clock_config[i].ddr_pll;
+ pll_nint = pll_cfg->nint[xtal_40];
+ pll_refdiv = pll_cfg->refdiv;
+ ddr_pll =
+ (pll_nint << AR934X_PLL_DDR_CONFIG_NINT_SHIFT) |
+ (pll_refdiv << AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT) |
+ (pll_cfg->range << AR934X_PLL_DDR_CONFIG_RANGE_SHIFT) |
+ (pll_cfg->outdiv << AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT);
+ break;
+ }
+
+ /* PLL configuration not found, hang. */
+ if (i == ARRAY_SIZE(ar934x_clock_config))
+ hang();
+
+ /* Set PLL Bypass */
+ setbits_be32(pll_regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG,
+ AR934X_PLL_CLK_CTRL_CPU_PLL_BYPASS);
+ setbits_be32(pll_regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG,
+ AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS);
+ setbits_be32(pll_regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG,
+ AR934X_PLL_CLK_CTRL_AHB_PLL_BYPASS);
+
+ /* Configure CPU PLL */
+ writel(cpu_pll | AR934X_PLL_CPU_CONFIG_PLLPWD,
+ pll_regs + AR934X_PLL_CPU_CONFIG_REG);
+ /* Configure DDR PLL */
+ writel(ddr_pll | AR934X_PLL_DDR_CONFIG_PLLPWD,
+ pll_regs + AR934X_PLL_DDR_CONFIG_REG);
+ /* Configure PLL routing */
+ writel(AR934X_PLL_CLK_CTRL_CPU_PLL_BYPASS |
+ AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS |
+ AR934X_PLL_CLK_CTRL_AHB_PLL_BYPASS |
+ (0 << AR934X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) |
+ (0 << AR934X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) |
+ (1 << AR934X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) |
+ AR934X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL |
+ AR934X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL |
+ AR934X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL,
+ pll_regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG);
+
+ /* Configure SRIF PLLs, which is completely undocumented :-) */
+ ar934x_srif_pll_cfg(srif_regs + AR934X_SRIF_CPU_DPLL1_REG, cpu_srif);
+ ar934x_srif_pll_cfg(srif_regs + AR934X_SRIF_DDR_DPLL1_REG, ddr_srif);
+
+ /* Unset PLL Bypass */
+ clrbits_be32(pll_regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG,
+ AR934X_PLL_CLK_CTRL_CPU_PLL_BYPASS);
+ clrbits_be32(pll_regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG,
+ AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS);
+ clrbits_be32(pll_regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG,
+ AR934X_PLL_CLK_CTRL_AHB_PLL_BYPASS);
+
+ /* Enable PLL dithering */
+ writel((1 << AR934X_PLL_DDR_DIT_FRAC_STEP_SHIFT) |
+ (0xf << AR934X_PLL_DDR_DIT_UPD_CNT_SHIFT),
+ pll_regs + AR934X_PLL_DDR_DIT_FRAC_REG);
+ writel(48 << AR934X_PLL_CPU_DIT_UPD_CNT_SHIFT,
+ pll_regs + AR934X_PLL_CPU_DIT_FRAC_REG);
+}
+
+static u32 ar934x_get_xtal(void)
+{
+ u32 val;
+
+ val = get_bootstrap();
+ if (val & AR934X_BOOTSTRAP_REF_CLK_40)
+ return 40000000;
+ else
+ return 25000000;
+}
+
+int get_serial_clock(void)
+{
+ return ar934x_get_xtal();
+}
+
+static u32 ar934x_cpupll_to_hz(const u32 regval)
+{
+ const u32 outdiv = (regval >> AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
+ AR934X_PLL_CPU_CONFIG_OUTDIV_MASK;
+ const u32 refdiv = (regval >> AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
+ AR934X_PLL_CPU_CONFIG_REFDIV_MASK;
+ const u32 nint = (regval >> AR934X_PLL_CPU_CONFIG_NINT_SHIFT) &
+ AR934X_PLL_CPU_CONFIG_NINT_MASK;
+ const u32 nfrac = (regval >> AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
+ AR934X_PLL_CPU_CONFIG_NFRAC_MASK;
+ const u32 xtal = ar934x_get_xtal();
+
+ return (xtal * (nint + (nfrac >> 9))) / (refdiv * (1 << outdiv));
+}
+
+static u32 ar934x_ddrpll_to_hz(const u32 regval)
+{
+ const u32 outdiv = (regval >> AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
+ AR934X_PLL_DDR_CONFIG_OUTDIV_MASK;
+ const u32 refdiv = (regval >> AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
+ AR934X_PLL_DDR_CONFIG_REFDIV_MASK;
+ const u32 nint = (regval >> AR934X_PLL_DDR_CONFIG_NINT_SHIFT) &
+ AR934X_PLL_DDR_CONFIG_NINT_MASK;
+ const u32 nfrac = (regval >> AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
+ AR934X_PLL_DDR_CONFIG_NFRAC_MASK;
+ const u32 xtal = ar934x_get_xtal();
+
+ return (xtal * (nint + (nfrac >> 9))) / (refdiv * (1 << outdiv));
+}
+
+static void ar934x_update_clock(void)
+{
+ void __iomem *regs;
+ u32 ctrl, cpu, cpupll, ddr, ddrpll;
+ u32 cpudiv, ddrdiv, busdiv;
+ u32 cpuclk, ddrclk, busclk;
+
+ regs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE,
+ MAP_NOCACHE);
+
+ cpu = readl(regs + AR934X_PLL_CPU_CONFIG_REG);
+ ddr = readl(regs + AR934X_PLL_DDR_CONFIG_REG);
+ ctrl = readl(regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG);
+
+ cpupll = ar934x_cpupll_to_hz(cpu);
+ ddrpll = ar934x_ddrpll_to_hz(ddr);
+
+ if (ctrl & AR934X_PLL_CLK_CTRL_CPU_PLL_BYPASS)
+ cpuclk = ar934x_get_xtal();
+ else if (ctrl & AR934X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL)
+ cpuclk = cpupll;
+ else
+ cpuclk = ddrpll;
+
+ if (ctrl & AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS)
+ ddrclk = ar934x_get_xtal();
+ else if (ctrl & AR934X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL)
+ ddrclk = ddrpll;
+ else
+ ddrclk = cpupll;
+
+ if (ctrl & AR934X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
+ busclk = ar934x_get_xtal();
+ else if (ctrl & AR934X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL)
+ busclk = ddrpll;
+ else
+ busclk = cpupll;
+
+ cpudiv = (ctrl >> AR934X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
+ AR934X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
+ ddrdiv = (ctrl >> AR934X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) &
+ AR934X_PLL_CLK_CTRL_DDR_POST_DIV_MASK;
+ busdiv = (ctrl >> AR934X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) &
+ AR934X_PLL_CLK_CTRL_AHB_POST_DIV_MASK;
+
+ gd->cpu_clk = cpuclk / (cpudiv + 1);
+ gd->mem_clk = ddrclk / (ddrdiv + 1);
+ gd->bus_clk = busclk / (busdiv + 1);
+}
+
+ulong get_bus_freq(ulong dummy)
+{
+ ar934x_update_clock();
+ return gd->bus_clk;
+}
+
+ulong get_ddr_freq(ulong dummy)
+{
+ ar934x_update_clock();
+ return gd->mem_clk;
+}
+
+int do_ar934x_showclk(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ ar934x_update_clock();
+ printf("CPU: %8ld MHz\n", gd->cpu_clk / 1000000);
+ printf("Memory: %8ld MHz\n", gd->mem_clk / 1000000);
+ printf("AHB: %8ld MHz\n", gd->bus_clk / 1000000);
+ return 0;
+}
+
+U_BOOT_CMD(
+ clocks, CONFIG_SYS_MAXARGS, 1, do_ar934x_showclk,
+ "display clocks",
+ ""
+);
--- /dev/null
+/*
+ * Copyright (C) 2016 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+
+/* The lowlevel_init() is not needed on AR934x */
+void lowlevel_init(void) {}
--- /dev/null
+/*
+ * Copyright (C) 2016 Marek Vasut <marex@denx.de>
+ *
+ * Based on RAM init sequence by Piotr Dymacz <pepe2k@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/addrspace.h>
+#include <asm/types.h>
+#include <mach/ar71xx_regs.h>
+#include <mach/reset.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+enum {
+ AR934X_SDRAM = 0,
+ AR934X_DDR1,
+ AR934X_DDR2,
+};
+
+struct ar934x_mem_config {
+ u32 config1;
+ u32 config2;
+ u32 mode;
+ u32 extmode;
+ u32 tap;
+};
+
+static const struct ar934x_mem_config ar934x_mem_config[] = {
+ [AR934X_SDRAM] = { 0x7fbe8cd0, 0x959f66a8, 0x33, 0, 0x1f1f },
+ [AR934X_DDR1] = { 0x7fd48cd0, 0x99d0e6a8, 0x33, 0, 0x14 },
+ [AR934X_DDR2] = { 0xc7d48cd0, 0x9dd0e6a8, 0x33, 0, 0x10012 },
+};
+
+void ar934x_ddr_init(const u16 cpu_mhz, const u16 ddr_mhz, const u16 ahb_mhz)
+{
+ void __iomem *ddr_regs;
+ const struct ar934x_mem_config *memcfg;
+ int memtype;
+ u32 reg, cycle, ctl;
+
+ ddr_regs = map_physmem(AR71XX_DDR_CTRL_BASE, AR71XX_DDR_CTRL_SIZE,
+ MAP_NOCACHE);
+
+ reg = get_bootstrap();
+ if (reg & AR934X_BOOTSTRAP_SDRAM_DISABLED) { /* DDR */
+ if (reg & AR934X_BOOTSTRAP_DDR1) { /* DDR 1 */
+ memtype = AR934X_DDR1;
+ cycle = 0xffff;
+ } else { /* DDR 2 */
+ memtype = AR934X_DDR2;
+ if (gd->arch.rev) {
+ ctl = BIT(6); /* Undocumented bit :-( */
+ if (reg & BIT(3))
+ cycle = 0xff;
+ else
+ cycle = 0xffff;
+ } else {
+ /* Force DDR2/x16 configuratio on old chips. */
+ ctl = 0;
+ cycle = 0xffff; /* DDR2 16bit */
+ }
+
+ writel(0xe59, ddr_regs + AR934X_DDR_REG_DDR2_CONFIG);
+ udelay(100);
+
+ writel(0x10, ddr_regs + AR71XX_DDR_REG_CONTROL);
+ udelay(10);
+
+ writel(0x20, ddr_regs + AR71XX_DDR_REG_CONTROL);
+ udelay(10);
+
+ writel(ctl, ddr_regs + AR934X_DDR_REG_CTL_CONF);
+ udelay(10);
+ }
+ } else { /* SDRAM */
+ memtype = AR934X_SDRAM;
+ cycle = 0xffffffff;
+
+ writel(0x13b, ddr_regs + AR934X_DDR_REG_CTL_CONF);
+ udelay(100);
+
+ /* Undocumented register */
+ writel(0x13b, ddr_regs + 0x118);
+ udelay(100);
+ }
+
+ memcfg = &ar934x_mem_config[memtype];
+
+ writel(memcfg->config1, ddr_regs + AR71XX_DDR_REG_CONFIG);
+ udelay(100);
+
+ writel(memcfg->config2, ddr_regs + AR71XX_DDR_REG_CONFIG2);
+ udelay(100);
+
+ writel(0x8, ddr_regs + AR71XX_DDR_REG_CONTROL);
+ udelay(10);
+
+ writel(memcfg->mode | 0x100, ddr_regs + AR71XX_DDR_REG_MODE);
+ mdelay(1);
+
+ writel(0x1, ddr_regs + AR71XX_DDR_REG_CONTROL);
+ udelay(10);
+
+ if (memtype == AR934X_DDR2) {
+ writel(memcfg->mode | 0x100, ddr_regs + AR71XX_DDR_REG_EMR);
+ udelay(100);
+
+ writel(0x2, ddr_regs + AR71XX_DDR_REG_CONTROL);
+ udelay(10);
+ }
+
+ if (memtype != AR934X_SDRAM)
+ writel(0x402, ddr_regs + AR71XX_DDR_REG_EMR);
+
+ udelay(100);
+
+ writel(0x2, ddr_regs + AR71XX_DDR_REG_CONTROL);
+ udelay(10);
+
+ writel(0x8, ddr_regs + AR71XX_DDR_REG_CONTROL);
+ udelay(10);
+
+ writel(memcfg->mode, ddr_regs + AR71XX_DDR_REG_MODE);
+ udelay(100);
+
+ writel(0x1, ddr_regs + AR71XX_DDR_REG_CONTROL);
+ udelay(10);
+
+ writel(0x412c /* FIXME */, ddr_regs + AR71XX_DDR_REG_REFRESH);
+ udelay(100);
+
+ writel(memcfg->tap, ddr_regs + AR71XX_DDR_REG_TAP_CTRL0);
+ writel(memcfg->tap, ddr_regs + AR71XX_DDR_REG_TAP_CTRL1);
+
+ if (memtype != AR934X_SDRAM) {
+ if ((gd->arch.rev && (reg & BIT(3))) || !gd->arch.rev) {
+ writel(memcfg->tap,
+ ddr_regs + AR934X_DDR_REG_TAP_CTRL2);
+ writel(memcfg->tap,
+ ddr_regs + AR934X_DDR_REG_TAP_CTRL3);
+ }
+ }
+
+ writel(cycle, ddr_regs + AR71XX_DDR_REG_RD_CYCLE);
+ udelay(100);
+
+ writel(0x74444444, ddr_regs + AR934X_DDR_REG_BURST);
+ udelay(100);
+
+ writel(0x222, ddr_regs + AR934X_DDR_REG_BURST2);
+ udelay(100);
+
+ writel(0xfffff, ddr_regs + AR934X_DDR_REG_TIMEOUT_MAX);
+ udelay(100);
+}
+
+void ddr_tap_tuning(void)
+{
+}
--- /dev/null
+/*
+ * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/addrspace.h>
+#include <asm/types.h>
+#include <mach/ath79.h>
+#include <mach/ar71xx_regs.h>
+
+struct ath79_soc_desc {
+ const enum ath79_soc_type soc;
+ const char *chip;
+ const int major;
+ const int minor;
+};
+
+static const struct ath79_soc_desc desc[] = {
+ {ATH79_SOC_AR7130, "7130",
+ REV_ID_MAJOR_AR71XX, AR71XX_REV_ID_MINOR_AR7130},
+ {ATH79_SOC_AR7141, "7141",
+ REV_ID_MAJOR_AR71XX, AR71XX_REV_ID_MINOR_AR7141},
+ {ATH79_SOC_AR7161, "7161",
+ REV_ID_MAJOR_AR71XX, AR71XX_REV_ID_MINOR_AR7161},
+ {ATH79_SOC_AR7240, "7240", REV_ID_MAJOR_AR7240, 0},
+ {ATH79_SOC_AR7241, "7241", REV_ID_MAJOR_AR7241, 0},
+ {ATH79_SOC_AR7242, "7242", REV_ID_MAJOR_AR7242, 0},
+ {ATH79_SOC_AR9130, "9130",
+ REV_ID_MAJOR_AR913X, AR913X_REV_ID_MINOR_AR9130},
+ {ATH79_SOC_AR9132, "9132",
+ REV_ID_MAJOR_AR913X, AR913X_REV_ID_MINOR_AR9132},
+ {ATH79_SOC_AR9330, "9330", REV_ID_MAJOR_AR9330, 0},
+ {ATH79_SOC_AR9331, "9331", REV_ID_MAJOR_AR9331, 0},
+ {ATH79_SOC_AR9341, "9341", REV_ID_MAJOR_AR9341, 0},
+ {ATH79_SOC_AR9342, "9342", REV_ID_MAJOR_AR9342, 0},
+ {ATH79_SOC_AR9344, "9344", REV_ID_MAJOR_AR9344, 0},
+ {ATH79_SOC_QCA9533, "9533", REV_ID_MAJOR_QCA9533, 0},
+ {ATH79_SOC_QCA9533, "9533",
+ REV_ID_MAJOR_QCA9533_V2, 0},
+ {ATH79_SOC_QCA9556, "9556", REV_ID_MAJOR_QCA9556, 0},
+ {ATH79_SOC_QCA9558, "9558", REV_ID_MAJOR_QCA9558, 0},
+ {ATH79_SOC_TP9343, "9343", REV_ID_MAJOR_TP9343, 0},
+ {ATH79_SOC_QCA9561, "9561", REV_ID_MAJOR_QCA9561, 0},
+};
+
+int arch_cpu_init(void)
+{
+ void __iomem *base;
+ enum ath79_soc_type soc = ATH79_SOC_UNKNOWN;
+ u32 id, major, minor = 0;
+ u32 rev = 0, ver = 1;
+ int i;
+
+ base = map_physmem(AR71XX_RESET_BASE, AR71XX_RESET_SIZE,
+ MAP_NOCACHE);
+
+ id = readl(base + AR71XX_RESET_REG_REV_ID);
+ major = id & REV_ID_MAJOR_MASK;
+ switch (major) {
+ case REV_ID_MAJOR_AR71XX:
+ case REV_ID_MAJOR_AR913X:
+ minor = id & AR71XX_REV_ID_MINOR_MASK;
+ rev = id >> AR71XX_REV_ID_REVISION_SHIFT;
+ rev &= AR71XX_REV_ID_REVISION_MASK;
+ break;
+
+ case REV_ID_MAJOR_QCA9533_V2:
+ ver = 2;
+ /* drop through */
+
+ case REV_ID_MAJOR_AR9341:
+ case REV_ID_MAJOR_AR9342:
+ case REV_ID_MAJOR_AR9344:
+ case REV_ID_MAJOR_QCA9533:
+ case REV_ID_MAJOR_QCA9556:
+ case REV_ID_MAJOR_QCA9558:
+ case REV_ID_MAJOR_TP9343:
+ case REV_ID_MAJOR_QCA9561:
+ rev = id & AR71XX_REV_ID_REVISION2_MASK;
+ break;
+ default:
+ rev = id & AR71XX_REV_ID_REVISION_MASK;
+ break;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(desc); i++) {
+ if ((desc[i].major == major) &&
+ (desc[i].minor == minor)) {
+ soc = desc[i].soc;
+ break;
+ }
+ }
+
+ gd->arch.id = id;
+ gd->arch.soc = soc;
+ gd->arch.rev = rev;
+ gd->arch.ver = ver;
+ return 0;
+}
+
+int print_cpuinfo(void)
+{
+ enum ath79_soc_type soc = ATH79_SOC_UNKNOWN;
+ const char *chip = "????";
+ u32 id, rev, ver;
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(desc); i++) {
+ if (desc[i].soc == gd->arch.soc) {
+ chip = desc[i].chip;
+ soc = desc[i].soc;
+ break;
+ }
+ }
+
+ id = gd->arch.id;
+ rev = gd->arch.rev;
+ ver = gd->arch.ver;
+
+ switch (soc) {
+ case ATH79_SOC_QCA9533:
+ case ATH79_SOC_QCA9556:
+ case ATH79_SOC_QCA9558:
+ case ATH79_SOC_QCA9561:
+ printf("Qualcomm Atheros QCA%s ver %u rev %u\n", chip,
+ ver, rev);
+ break;
+ case ATH79_SOC_TP9343:
+ printf("Qualcomm Atheros TP%s rev %u\n", chip, rev);
+ break;
+ case ATH79_SOC_UNKNOWN:
+ printf("ATH79: unknown SoC, id:0x%08x", id);
+ break;
+ default:
+ printf("Atheros AR%s rev %u\n", chip, rev);
+ }
+
+ return 0;
+}
--- /dev/null
+/*
+ * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/sizes.h>
+#include <asm/addrspace.h>
+#include <mach/ddr.h>
+
+phys_size_t initdram(int board_type)
+{
+ ddr_tap_tuning();
+ return get_ram_size((void *)KSEG1, SZ_256M);
+}
--- /dev/null
+/*
+ * Atheros AR71XX/AR724X/AR913X SoC register definitions
+ *
+ * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
+ * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
+ * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_MACH_AR71XX_REGS_H
+#define __ASM_MACH_AR71XX_REGS_H
+
+#ifndef __ASSEMBLY__
+#include <linux/bitops.h>
+#else
+#ifndef BIT
+#define BIT(nr) (1 << (nr))
+#endif
+#endif
+
+#define AR71XX_APB_BASE 0x18000000
+#define AR71XX_GE0_BASE 0x19000000
+#define AR71XX_GE0_SIZE 0x10000
+#define AR71XX_GE1_BASE 0x1a000000
+#define AR71XX_GE1_SIZE 0x10000
+#define AR71XX_EHCI_BASE 0x1b000000
+#define AR71XX_EHCI_SIZE 0x1000
+#define AR71XX_OHCI_BASE 0x1c000000
+#define AR71XX_OHCI_SIZE 0x1000
+#define AR71XX_SPI_BASE 0x1f000000
+#define AR71XX_SPI_SIZE 0x01000000
+
+#define AR71XX_DDR_CTRL_BASE \
+ (AR71XX_APB_BASE + 0x00000000)
+#define AR71XX_DDR_CTRL_SIZE 0x100
+#define AR71XX_UART_BASE \
+ (AR71XX_APB_BASE + 0x00020000)
+#define AR71XX_UART_SIZE 0x100
+#define AR71XX_USB_CTRL_BASE \
+ (AR71XX_APB_BASE + 0x00030000)
+#define AR71XX_USB_CTRL_SIZE 0x100
+#define AR71XX_GPIO_BASE \
+ (AR71XX_APB_BASE + 0x00040000)
+#define AR71XX_GPIO_SIZE 0x100
+#define AR71XX_PLL_BASE \
+ (AR71XX_APB_BASE + 0x00050000)
+#define AR71XX_PLL_SIZE 0x100
+#define AR71XX_RESET_BASE \
+ (AR71XX_APB_BASE + 0x00060000)
+#define AR71XX_RESET_SIZE 0x100
+#define AR71XX_MII_BASE \
+ (AR71XX_APB_BASE + 0x00070000)
+#define AR71XX_MII_SIZE 0x100
+
+#define AR71XX_PCI_MEM_BASE 0x10000000
+#define AR71XX_PCI_MEM_SIZE 0x07000000
+
+#define AR71XX_PCI_WIN0_OFFS 0x10000000
+#define AR71XX_PCI_WIN1_OFFS 0x11000000
+#define AR71XX_PCI_WIN2_OFFS 0x12000000
+#define AR71XX_PCI_WIN3_OFFS 0x13000000
+#define AR71XX_PCI_WIN4_OFFS 0x14000000
+#define AR71XX_PCI_WIN5_OFFS 0x15000000
+#define AR71XX_PCI_WIN6_OFFS 0x16000000
+#define AR71XX_PCI_WIN7_OFFS 0x07000000
+
+#define AR71XX_PCI_CFG_BASE \
+ (AR71XX_PCI_MEM_BASE + AR71XX_PCI_WIN7_OFFS + 0x10000)
+#define AR71XX_PCI_CFG_SIZE 0x100
+
+#define AR7240_USB_CTRL_BASE \
+ (AR71XX_APB_BASE + 0x00030000)
+#define AR7240_USB_CTRL_SIZE 0x100
+#define AR7240_OHCI_BASE 0x1b000000
+#define AR7240_OHCI_SIZE 0x1000
+
+#define AR724X_PCI_MEM_BASE 0x10000000
+#define AR724X_PCI_MEM_SIZE 0x04000000
+
+#define AR724X_PCI_CFG_BASE 0x14000000
+#define AR724X_PCI_CFG_SIZE 0x1000
+#define AR724X_PCI_CRP_BASE \
+ (AR71XX_APB_BASE + 0x000c0000)
+#define AR724X_PCI_CRP_SIZE 0x1000
+#define AR724X_PCI_CTRL_BASE \
+ (AR71XX_APB_BASE + 0x000f0000)
+#define AR724X_PCI_CTRL_SIZE 0x100
+
+#define AR724X_EHCI_BASE 0x1b000000
+#define AR724X_EHCI_SIZE 0x1000
+
+#define AR913X_EHCI_BASE 0x1b000000
+#define AR913X_EHCI_SIZE 0x1000
+#define AR913X_WMAC_BASE \
+ (AR71XX_APB_BASE + 0x000C0000)
+#define AR913X_WMAC_SIZE 0x30000
+
+#define AR933X_UART_BASE \
+ (AR71XX_APB_BASE + 0x00020000)
+#define AR933X_UART_SIZE 0x14
+#define AR933X_GMAC_BASE \
+ (AR71XX_APB_BASE + 0x00070000)
+#define AR933X_GMAC_SIZE 0x04
+#define AR933X_WMAC_BASE \
+ (AR71XX_APB_BASE + 0x00100000)
+#define AR933X_WMAC_SIZE 0x20000
+#define AR933X_RTC_BASE \
+ (AR71XX_APB_BASE + 0x00107000)
+#define AR933X_RTC_SIZE 0x1000
+#define AR933X_EHCI_BASE 0x1b000000
+#define AR933X_EHCI_SIZE 0x1000
+#define AR933X_SRIF_BASE \
+ (AR71XX_APB_BASE + 0x00116000)
+#define AR933X_SRIF_SIZE 0x1000
+
+#define AR934X_GMAC_BASE \
+ (AR71XX_APB_BASE + 0x00070000)
+#define AR934X_GMAC_SIZE 0x14
+#define AR934X_WMAC_BASE \
+ (AR71XX_APB_BASE + 0x00100000)
+#define AR934X_WMAC_SIZE 0x20000
+#define AR934X_EHCI_BASE 0x1b000000
+#define AR934X_EHCI_SIZE 0x200
+#define AR934X_NFC_BASE 0x1b000200
+#define AR934X_NFC_SIZE 0xb8
+#define AR934X_SRIF_BASE \
+ (AR71XX_APB_BASE + 0x00116000)
+#define AR934X_SRIF_SIZE 0x1000
+
+#define QCA953X_GMAC_BASE \
+ (AR71XX_APB_BASE + 0x00070000)
+#define QCA953X_GMAC_SIZE 0x14
+#define QCA953X_WMAC_BASE \
+ (AR71XX_APB_BASE + 0x00100000)
+#define QCA953X_WMAC_SIZE 0x20000
+#define QCA953X_RTC_BASE \
+ (AR71XX_APB_BASE + 0x00107000)
+#define QCA953X_RTC_SIZE 0x1000
+#define QCA953X_EHCI_BASE 0x1b000000
+#define QCA953X_EHCI_SIZE 0x200
+#define QCA953X_SRIF_BASE \
+ (AR71XX_APB_BASE + 0x00116000)
+#define QCA953X_SRIF_SIZE 0x1000
+
+#define QCA953X_PCI_CFG_BASE0 0x14000000
+#define QCA953X_PCI_CTRL_BASE0 \
+ (AR71XX_APB_BASE + 0x000f0000)
+#define QCA953X_PCI_CRP_BASE0 \
+ (AR71XX_APB_BASE + 0x000c0000)
+#define QCA953X_PCI_MEM_BASE0 0x10000000
+#define QCA953X_PCI_MEM_SIZE 0x02000000
+
+#define QCA955X_PCI_MEM_BASE0 0x10000000
+#define QCA955X_PCI_MEM_BASE1 0x12000000
+#define QCA955X_PCI_MEM_SIZE 0x02000000
+#define QCA955X_PCI_CFG_BASE0 0x14000000
+#define QCA955X_PCI_CFG_BASE1 0x16000000
+#define QCA955X_PCI_CFG_SIZE 0x1000
+#define QCA955X_PCI_CRP_BASE0 \
+ (AR71XX_APB_BASE + 0x000c0000)
+#define QCA955X_PCI_CRP_BASE1 \
+ (AR71XX_APB_BASE + 0x00250000)
+#define QCA955X_PCI_CRP_SIZE 0x1000
+#define QCA955X_PCI_CTRL_BASE0 \
+ (AR71XX_APB_BASE + 0x000f0000)
+#define QCA955X_PCI_CTRL_BASE1 \
+ (AR71XX_APB_BASE + 0x00280000)
+#define QCA955X_PCI_CTRL_SIZE 0x100
+
+#define QCA955X_GMAC_BASE \
+ (AR71XX_APB_BASE + 0x00070000)
+#define QCA955X_GMAC_SIZE 0x40
+#define QCA955X_WMAC_BASE \
+ (AR71XX_APB_BASE + 0x00100000)
+#define QCA955X_WMAC_SIZE 0x20000
+#define QCA955X_EHCI0_BASE 0x1b000000
+#define QCA955X_EHCI1_BASE 0x1b400000
+#define QCA955X_EHCI_SIZE 0x1000
+#define QCA955X_NFC_BASE 0x1b800200
+#define QCA955X_NFC_SIZE 0xb8
+
+#define QCA956X_PCI_MEM_BASE1 0x12000000
+#define QCA956X_PCI_MEM_SIZE 0x02000000
+#define QCA956X_PCI_CFG_BASE1 0x16000000
+#define QCA956X_PCI_CFG_SIZE 0x1000
+#define QCA956X_PCI_CRP_BASE1 \
+ (AR71XX_APB_BASE + 0x00250000)
+#define QCA956X_PCI_CRP_SIZE 0x1000
+#define QCA956X_PCI_CTRL_BASE1 \
+ (AR71XX_APB_BASE + 0x00280000)
+#define QCA956X_PCI_CTRL_SIZE 0x100
+
+#define QCA956X_WMAC_BASE \
+ (AR71XX_APB_BASE + 0x00100000)
+#define QCA956X_WMAC_SIZE 0x20000
+#define QCA956X_EHCI0_BASE 0x1b000000
+#define QCA956X_EHCI1_BASE 0x1b400000
+#define QCA956X_EHCI_SIZE 0x200
+#define QCA956X_GMAC_BASE \
+ (AR71XX_APB_BASE + 0x00070000)
+#define QCA956X_GMAC_SIZE 0x64
+
+/*
+ * DDR_CTRL block
+ */
+#define AR71XX_DDR_REG_CONFIG 0x00
+#define AR71XX_DDR_REG_CONFIG2 0x04
+#define AR71XX_DDR_REG_MODE 0x08
+#define AR71XX_DDR_REG_EMR 0x0c
+#define AR71XX_DDR_REG_CONTROL 0x10
+#define AR71XX_DDR_REG_REFRESH 0x14
+#define AR71XX_DDR_REG_RD_CYCLE 0x18
+#define AR71XX_DDR_REG_TAP_CTRL0 0x1c
+#define AR71XX_DDR_REG_TAP_CTRL1 0x20
+
+#define AR71XX_DDR_REG_PCI_WIN0 0x7c
+#define AR71XX_DDR_REG_PCI_WIN1 0x80
+#define AR71XX_DDR_REG_PCI_WIN2 0x84
+#define AR71XX_DDR_REG_PCI_WIN3 0x88
+#define AR71XX_DDR_REG_PCI_WIN4 0x8c
+#define AR71XX_DDR_REG_PCI_WIN5 0x90
+#define AR71XX_DDR_REG_PCI_WIN6 0x94
+#define AR71XX_DDR_REG_PCI_WIN7 0x98
+#define AR71XX_DDR_REG_FLUSH_GE0 0x9c
+#define AR71XX_DDR_REG_FLUSH_GE1 0xa0
+#define AR71XX_DDR_REG_FLUSH_USB 0xa4
+#define AR71XX_DDR_REG_FLUSH_PCI 0xa8
+
+#define AR724X_DDR_REG_FLUSH_GE0 0x7c
+#define AR724X_DDR_REG_FLUSH_GE1 0x80
+#define AR724X_DDR_REG_FLUSH_USB 0x84
+#define AR724X_DDR_REG_FLUSH_PCIE 0x88
+
+#define AR913X_DDR_REG_FLUSH_GE0 0x7c
+#define AR913X_DDR_REG_FLUSH_GE1 0x80
+#define AR913X_DDR_REG_FLUSH_USB 0x84
+#define AR913X_DDR_REG_FLUSH_WMAC 0x88
+
+#define AR933X_DDR_REG_FLUSH_GE0 0x7c
+#define AR933X_DDR_REG_FLUSH_GE1 0x80
+#define AR933X_DDR_REG_FLUSH_USB 0x84
+#define AR933X_DDR_REG_FLUSH_WMAC 0x88
+#define AR933X_DDR_REG_DDR2_CONFIG 0x8c
+#define AR933X_DDR_REG_EMR2 0x90
+#define AR933X_DDR_REG_EMR3 0x94
+#define AR933X_DDR_REG_BURST 0x98
+#define AR933X_DDR_REG_TIMEOUT_MAX 0x9c
+#define AR933X_DDR_REG_TIMEOUT_CNT 0x9c
+#define AR933X_DDR_REG_TIMEOUT_ADDR 0x9c
+
+#define AR934X_DDR_REG_TAP_CTRL2 0x24
+#define AR934X_DDR_REG_TAP_CTRL3 0x28
+#define AR934X_DDR_REG_FLUSH_GE0 0x9c
+#define AR934X_DDR_REG_FLUSH_GE1 0xa0
+#define AR934X_DDR_REG_FLUSH_USB 0xa4
+#define AR934X_DDR_REG_FLUSH_PCIE 0xa8
+#define AR934X_DDR_REG_FLUSH_WMAC 0xac
+#define AR934X_DDR_REG_FLUSH_SRC1 0xb0
+#define AR934X_DDR_REG_FLUSH_SRC2 0xb4
+#define AR934X_DDR_REG_DDR2_CONFIG 0xb8
+#define AR934X_DDR_REG_EMR2 0xbc
+#define AR934X_DDR_REG_EMR3 0xc0
+#define AR934X_DDR_REG_BURST 0xc4
+#define AR934X_DDR_REG_BURST2 0xc8
+#define AR934X_DDR_REG_TIMEOUT_MAX 0xcc
+#define AR934X_DDR_REG_CTL_CONF 0x108
+
+#define QCA953X_DDR_REG_FLUSH_GE0 0x9c
+#define QCA953X_DDR_REG_FLUSH_GE1 0xa0
+#define QCA953X_DDR_REG_FLUSH_USB 0xa4
+#define QCA953X_DDR_REG_FLUSH_PCIE 0xa8
+#define QCA953X_DDR_REG_FLUSH_WMAC 0xac
+#define QCA953X_DDR_REG_DDR2_CONFIG 0xb8
+#define QCA953X_DDR_REG_BURST 0xc4
+#define QCA953X_DDR_REG_BURST2 0xc8
+#define QCA953X_DDR_REG_TIMEOUT_MAX 0xcc
+#define QCA953X_DDR_REG_CTL_CONF 0x108
+#define QCA953X_DDR_REG_CONFIG3 0x15c
+
+/*
+ * PLL block
+ */
+#define AR71XX_PLL_REG_CPU_CONFIG 0x00
+#define AR71XX_PLL_REG_SEC_CONFIG 0x04
+#define AR71XX_PLL_REG_ETH0_INT_CLOCK 0x10
+#define AR71XX_PLL_REG_ETH1_INT_CLOCK 0x14
+
+#define AR71XX_PLL_DIV_SHIFT 3
+#define AR71XX_PLL_DIV_MASK 0x1f
+#define AR71XX_CPU_DIV_SHIFT 16
+#define AR71XX_CPU_DIV_MASK 0x3
+#define AR71XX_DDR_DIV_SHIFT 18
+#define AR71XX_DDR_DIV_MASK 0x3
+#define AR71XX_AHB_DIV_SHIFT 20
+#define AR71XX_AHB_DIV_MASK 0x7
+
+#define AR71XX_ETH0_PLL_SHIFT 17
+#define AR71XX_ETH1_PLL_SHIFT 19
+
+#define AR724X_PLL_REG_CPU_CONFIG 0x00
+#define AR724X_PLL_REG_PCIE_CONFIG 0x18
+
+#define AR724X_PLL_DIV_SHIFT 0
+#define AR724X_PLL_DIV_MASK 0x3ff
+#define AR724X_PLL_REF_DIV_SHIFT 10
+#define AR724X_PLL_REF_DIV_MASK 0xf
+#define AR724X_AHB_DIV_SHIFT 19
+#define AR724X_AHB_DIV_MASK 0x1
+#define AR724X_DDR_DIV_SHIFT 22
+#define AR724X_DDR_DIV_MASK 0x3
+
+#define AR7242_PLL_REG_ETH0_INT_CLOCK 0x2c
+
+#define AR913X_PLL_REG_CPU_CONFIG 0x00
+#define AR913X_PLL_REG_ETH_CONFIG 0x04
+#define AR913X_PLL_REG_ETH0_INT_CLOCK 0x14
+#define AR913X_PLL_REG_ETH1_INT_CLOCK 0x18
+
+#define AR913X_PLL_DIV_SHIFT 0
+#define AR913X_PLL_DIV_MASK 0x3ff
+#define AR913X_DDR_DIV_SHIFT 22
+#define AR913X_DDR_DIV_MASK 0x3
+#define AR913X_AHB_DIV_SHIFT 19
+#define AR913X_AHB_DIV_MASK 0x1
+
+#define AR913X_ETH0_PLL_SHIFT 20
+#define AR913X_ETH1_PLL_SHIFT 22
+
+#define AR933X_PLL_CPU_CONFIG_REG 0x00
+#define AR933X_PLL_CLK_CTRL_REG 0x08
+#define AR933X_PLL_DITHER_FRAC_REG 0x10
+
+#define AR933X_PLL_CPU_CONFIG_NINT_SHIFT 10
+#define AR933X_PLL_CPU_CONFIG_NINT_MASK 0x3f
+#define AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT 16
+#define AR933X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f
+#define AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT 23
+#define AR933X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7
+
+#define AR933X_PLL_CLK_CTRL_BYPASS BIT(2)
+#define AR933X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5
+#define AR933X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x3
+#define AR933X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10
+#define AR933X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x3
+#define AR933X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15
+#define AR933X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x7
+
+#define AR934X_PLL_CPU_CONFIG_REG 0x00
+#define AR934X_PLL_DDR_CONFIG_REG 0x04
+#define AR934X_PLL_CPU_DDR_CLK_CTRL_REG 0x08
+#define AR934X_PLL_SWITCH_CLOCK_CONTROL_REG 0x24
+#define AR934X_PLL_ETH_XMII_CONTROL_REG 0x2c
+#define AR934X_PLL_DDR_DIT_FRAC_REG 0x44
+#define AR934X_PLL_CPU_DIT_FRAC_REG 0x48
+
+#define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT 0
+#define AR934X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f
+#define AR934X_PLL_CPU_CONFIG_NINT_SHIFT 6
+#define AR934X_PLL_CPU_CONFIG_NINT_MASK 0x3f
+#define AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT 12
+#define AR934X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f
+#define AR934X_PLL_CPU_CONFIG_RANGE_SHIFT 17
+#define AR934X_PLL_CPU_CONFIG_RANGE_MASK 0x3
+#define AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19
+#define AR934X_PLL_CPU_CONFIG_OUTDIV_MASK 0x3
+#define AR934X_PLL_CPU_CONFIG_PLLPWD BIT(30)
+#define AR934X_PLL_CPU_CONFIG_UPDATING BIT(31)
+
+#define AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT 0
+#define AR934X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff
+#define AR934X_PLL_DDR_CONFIG_NINT_SHIFT 10
+#define AR934X_PLL_DDR_CONFIG_NINT_MASK 0x3f
+#define AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT 16
+#define AR934X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f
+#define AR934X_PLL_DDR_CONFIG_RANGE_SHIFT 21
+#define AR934X_PLL_DDR_CONFIG_RANGE_MASK 0x3
+#define AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23
+#define AR934X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7
+#define AR934X_PLL_DDR_CONFIG_PLLPWD BIT(30)
+#define AR934X_PLL_DDR_CONFIG_UPDATING BIT(31)
+
+#define AR934X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2)
+#define AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3)
+#define AR934X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4)
+#define AR934X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5
+#define AR934X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f
+#define AR934X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10
+#define AR934X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f
+#define AR934X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15
+#define AR934X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f
+#define AR934X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20)
+#define AR934X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
+#define AR934X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
+
+#define AR934X_PLL_SWITCH_CLK_CTRL_MDIO_CLK_SEL BIT(6)
+
+#define AR934X_PLL_DDR_DIT_FRAC_MAX_SHIFT 0
+#define AR934X_PLL_DDR_DIT_FRAC_MAX_MASK 0x3ff
+#define AR934X_PLL_DDR_DIT_FRAC_MIN_SHIFT 10
+#define AR934X_PLL_DDR_DIT_FRAC_MIN_MASK 0x3ff
+#define AR934X_PLL_DDR_DIT_FRAC_STEP_SHIFT 20
+#define AR934X_PLL_DDR_DIT_FRAC_STEP_MASK 0x3f
+#define AR934X_PLL_DDR_DIT_UPD_CNT_SHIFT 27
+#define AR934X_PLL_DDR_DIT_UPD_CNT_MASK 0x3f
+#define AR934X_PLL_DDR_DIT_DITHER_EN BIT(31)
+
+#define AR934X_PLL_CPU_DIT_FRAC_MAX_SHIFT 0
+#define AR934X_PLL_CPU_DIT_FRAC_MAX_MASK 0x3f
+#define AR934X_PLL_CPU_DIT_FRAC_MIN_SHIFT 6
+#define AR934X_PLL_CPU_DIT_FRAC_MIN_MASK 0x3f
+#define AR934X_PLL_CPU_DIT_FRAC_STEP_SHIFT 12
+#define AR934X_PLL_CPU_DIT_FRAC_STEP_MASK 0x3f
+#define AR934X_PLL_CPU_DIT_UPD_CNT_SHIFT 18
+#define AR934X_PLL_CPU_DIT_UPD_CNT_MASK 0x3f
+#define AR934X_PLL_CPU_DIT_DITHER_EN BIT(31)
+
+#define QCA953X_PLL_CPU_CONFIG_REG 0x00
+#define QCA953X_PLL_DDR_CONFIG_REG 0x04
+#define QCA953X_PLL_CLK_CTRL_REG 0x08
+#define QCA953X_PLL_SWITCH_CLOCK_CONTROL_REG 0x24
+#define QCA953X_PLL_ETH_XMII_CONTROL_REG 0x2c
+#define QCA953X_PLL_DDR_DIT_FRAC_REG 0x44
+#define QCA953X_PLL_CPU_DIT_FRAC_REG 0x48
+
+#define QCA953X_PLL_CPU_CONFIG_NFRAC_SHIFT 0
+#define QCA953X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f
+#define QCA953X_PLL_CPU_CONFIG_NINT_SHIFT 6
+#define QCA953X_PLL_CPU_CONFIG_NINT_MASK 0x3f
+#define QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT 12
+#define QCA953X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f
+#define QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19
+#define QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7
+
+#define QCA953X_PLL_DDR_CONFIG_NFRAC_SHIFT 0
+#define QCA953X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff
+#define QCA953X_PLL_DDR_CONFIG_NINT_SHIFT 10
+#define QCA953X_PLL_DDR_CONFIG_NINT_MASK 0x3f
+#define QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT 16
+#define QCA953X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f
+#define QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23
+#define QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7
+
+#define QCA953X_PLL_CONFIG_PWD BIT(30)
+
+#define QCA953X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2)
+#define QCA953X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3)
+#define QCA953X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4)
+#define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5
+#define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f
+#define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10
+#define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f
+#define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15
+#define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f
+#define QCA953X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20)
+#define QCA953X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
+#define QCA953X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
+
+#define QCA953X_PLL_CPU_DIT_FRAC_MAX_SHIFT 0
+#define QCA953X_PLL_CPU_DIT_FRAC_MAX_MASK 0x3f
+#define QCA953X_PLL_CPU_DIT_FRAC_MIN_SHIFT 6
+#define QCA953X_PLL_CPU_DIT_FRAC_MIN_MASK 0x3f
+#define QCA953X_PLL_CPU_DIT_FRAC_STEP_SHIFT 12
+#define QCA953X_PLL_CPU_DIT_FRAC_STEP_MASK 0x3f
+#define QCA953X_PLL_CPU_DIT_UPD_CNT_SHIFT 18
+#define QCA953X_PLL_CPU_DIT_UPD_CNT_MASK 0x3f
+
+#define QCA953X_PLL_DDR_DIT_FRAC_MAX_SHIFT 0
+#define QCA953X_PLL_DDR_DIT_FRAC_MAX_MASK 0x3ff
+#define QCA953X_PLL_DDR_DIT_FRAC_MIN_SHIFT 9
+#define QCA953X_PLL_DDR_DIT_FRAC_MIN_MASK 0x3ff
+#define QCA953X_PLL_DDR_DIT_FRAC_STEP_SHIFT 20
+#define QCA953X_PLL_DDR_DIT_FRAC_STEP_MASK 0x3f
+#define QCA953X_PLL_DDR_DIT_UPD_CNT_SHIFT 27
+#define QCA953X_PLL_DDR_DIT_UPD_CNT_MASK 0x3f
+
+#define QCA953X_PLL_DIT_FRAC_EN BIT(31)
+
+#define QCA955X_PLL_CPU_CONFIG_REG 0x00
+#define QCA955X_PLL_DDR_CONFIG_REG 0x04
+#define QCA955X_PLL_CLK_CTRL_REG 0x08
+#define QCA955X_PLL_ETH_XMII_CONTROL_REG 0x28
+#define QCA955X_PLL_ETH_SGMII_CONTROL_REG 0x48
+
+#define QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT 0
+#define QCA955X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f
+#define QCA955X_PLL_CPU_CONFIG_NINT_SHIFT 6
+#define QCA955X_PLL_CPU_CONFIG_NINT_MASK 0x3f
+#define QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT 12
+#define QCA955X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f
+#define QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19
+#define QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK 0x3
+
+#define QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT 0
+#define QCA955X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff
+#define QCA955X_PLL_DDR_CONFIG_NINT_SHIFT 10
+#define QCA955X_PLL_DDR_CONFIG_NINT_MASK 0x3f
+#define QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT 16
+#define QCA955X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f
+#define QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23
+#define QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7
+
+#define QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2)
+#define QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3)
+#define QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4)
+#define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5
+#define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f
+#define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10
+#define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f
+#define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15
+#define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f
+#define QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20)
+#define QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
+#define QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
+
+#define QCA956X_PLL_CPU_CONFIG_REG 0x00
+#define QCA956X_PLL_CPU_CONFIG1_REG 0x04
+#define QCA956X_PLL_DDR_CONFIG_REG 0x08
+#define QCA956X_PLL_DDR_CONFIG1_REG 0x0c
+#define QCA956X_PLL_CLK_CTRL_REG 0x10
+
+#define QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT 12
+#define QCA956X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f
+#define QCA956X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19
+#define QCA956X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7
+
+#define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_SHIFT 0
+#define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_MASK 0x1f
+#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT 5
+#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK 0x3fff
+#define QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT 18
+#define QCA956X_PLL_CPU_CONFIG1_NINT_MASK 0x1ff
+
+#define QCA956X_PLL_DDR_CONFIG_REFDIV_SHIFT 16
+#define QCA956X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f
+#define QCA956X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23
+#define QCA956X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7
+
+#define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_SHIFT 0
+#define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_MASK 0x1f
+#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT 5
+#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK 0x3fff
+#define QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT 18
+#define QCA956X_PLL_DDR_CONFIG1_NINT_MASK 0x1ff
+
+#define QCA956X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2)
+#define QCA956X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3)
+#define QCA956X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4)
+#define QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5
+#define QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f
+#define QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10
+#define QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f
+#define QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15
+#define QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f
+#define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_DDRPLL BIT(20)
+#define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_CPUPLL BIT(21)
+#define QCA956X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
+
+/*
+ * USB_CONFIG block
+ */
+#define AR71XX_USB_CTRL_REG_FLADJ 0x00
+#define AR71XX_USB_CTRL_REG_CONFIG 0x04
+
+/*
+ * RESET block
+ */
+#define AR71XX_RESET_REG_TIMER 0x00
+#define AR71XX_RESET_REG_TIMER_RELOAD 0x04
+#define AR71XX_RESET_REG_WDOG_CTRL 0x08
+#define AR71XX_RESET_REG_WDOG 0x0c
+#define AR71XX_RESET_REG_MISC_INT_STATUS 0x10
+#define AR71XX_RESET_REG_MISC_INT_ENABLE 0x14
+#define AR71XX_RESET_REG_PCI_INT_STATUS 0x18
+#define AR71XX_RESET_REG_PCI_INT_ENABLE 0x1c
+#define AR71XX_RESET_REG_GLOBAL_INT_STATUS 0x20
+#define AR71XX_RESET_REG_RESET_MODULE 0x24
+#define AR71XX_RESET_REG_PERFC_CTRL 0x2c
+#define AR71XX_RESET_REG_PERFC0 0x30
+#define AR71XX_RESET_REG_PERFC1 0x34
+#define AR71XX_RESET_REG_REV_ID 0x90
+
+#define AR913X_RESET_REG_GLOBAL_INT_STATUS 0x18
+#define AR913X_RESET_REG_RESET_MODULE 0x1c
+#define AR913X_RESET_REG_PERF_CTRL 0x20
+#define AR913X_RESET_REG_PERFC0 0x24
+#define AR913X_RESET_REG_PERFC1 0x28
+
+#define AR724X_RESET_REG_RESET_MODULE 0x1c
+
+#define AR933X_RESET_REG_RESET_MODULE 0x1c
+#define AR933X_RESET_REG_BOOTSTRAP 0xac
+
+#define AR934X_RESET_REG_RESET_MODULE 0x1c
+#define AR934X_RESET_REG_BOOTSTRAP 0xb0
+#define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac
+
+#define QCA953X_RESET_REG_RESET_MODULE 0x1c
+#define QCA953X_RESET_REG_BOOTSTRAP 0xb0
+#define QCA953X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac
+
+#define QCA955X_RESET_REG_RESET_MODULE 0x1c
+#define QCA955X_RESET_REG_BOOTSTRAP 0xb0
+#define QCA955X_RESET_REG_EXT_INT_STATUS 0xac
+
+#define QCA956X_RESET_REG_RESET_MODULE 0x1c
+#define QCA956X_RESET_REG_BOOTSTRAP 0xb0
+#define QCA956X_RESET_REG_EXT_INT_STATUS 0xac
+
+#define MISC_INT_MIPS_SI_TIMERINT_MASK BIT(28)
+#define MISC_INT_ETHSW BIT(12)
+#define MISC_INT_TIMER4 BIT(10)
+#define MISC_INT_TIMER3 BIT(9)
+#define MISC_INT_TIMER2 BIT(8)
+#define MISC_INT_DMA BIT(7)
+#define MISC_INT_OHCI BIT(6)
+#define MISC_INT_PERFC BIT(5)
+#define MISC_INT_WDOG BIT(4)
+#define MISC_INT_UART BIT(3)
+#define MISC_INT_GPIO BIT(2)
+#define MISC_INT_ERROR BIT(1)
+#define MISC_INT_TIMER BIT(0)
+
+#define AR71XX_RESET_EXTERNAL BIT(28)
+#define AR71XX_RESET_FULL_CHIP BIT(24)
+#define AR71XX_RESET_CPU_NMI BIT(21)
+#define AR71XX_RESET_CPU_COLD BIT(20)
+#define AR71XX_RESET_DMA BIT(19)
+#define AR71XX_RESET_SLIC BIT(18)
+#define AR71XX_RESET_STEREO BIT(17)
+#define AR71XX_RESET_DDR BIT(16)
+#define AR71XX_RESET_GE1_MAC BIT(13)
+#define AR71XX_RESET_GE1_PHY BIT(12)
+#define AR71XX_RESET_USBSUS_OVERRIDE BIT(10)
+#define AR71XX_RESET_GE0_MAC BIT(9)
+#define AR71XX_RESET_GE0_PHY BIT(8)
+#define AR71XX_RESET_USB_OHCI_DLL BIT(6)
+#define AR71XX_RESET_USB_HOST BIT(5)
+#define AR71XX_RESET_USB_PHY BIT(4)
+#define AR71XX_RESET_PCI_BUS BIT(1)
+#define AR71XX_RESET_PCI_CORE BIT(0)
+
+#define AR7240_RESET_USB_HOST BIT(5)
+#define AR7240_RESET_OHCI_DLL BIT(3)
+
+#define AR724X_RESET_GE1_MDIO BIT(23)
+#define AR724X_RESET_GE0_MDIO BIT(22)
+#define AR724X_RESET_PCIE_PHY_SERIAL BIT(10)
+#define AR724X_RESET_PCIE_PHY BIT(7)
+#define AR724X_RESET_PCIE BIT(6)
+#define AR724X_RESET_USB_HOST BIT(5)
+#define AR724X_RESET_USB_PHY BIT(4)
+#define AR724X_RESET_USBSUS_OVERRIDE BIT(3)
+
+#define AR913X_RESET_AMBA2WMAC BIT(22)
+#define AR913X_RESET_USBSUS_OVERRIDE BIT(10)
+#define AR913X_RESET_USB_HOST BIT(5)
+#define AR913X_RESET_USB_PHY BIT(4)
+
+#define AR933X_RESET_GE1_MDIO BIT(23)
+#define AR933X_RESET_GE0_MDIO BIT(22)
+#define AR933X_RESET_GE1_MAC BIT(13)
+#define AR933X_RESET_WMAC BIT(11)
+#define AR933X_RESET_GE0_MAC BIT(9)
+#define AR933X_RESET_ETH_SWITCH BIT(8)
+#define AR933X_RESET_USB_HOST BIT(5)
+#define AR933X_RESET_USB_PHY BIT(4)
+#define AR933X_RESET_USBSUS_OVERRIDE BIT(3)
+
+#define AR934X_RESET_HOST BIT(31)
+#define AR934X_RESET_SLIC BIT(30)
+#define AR934X_RESET_HDMA BIT(29)
+#define AR934X_RESET_EXTERNAL BIT(28)
+#define AR934X_RESET_RTC BIT(27)
+#define AR934X_RESET_PCIE_EP_INT BIT(26)
+#define AR934X_RESET_CHKSUM_ACC BIT(25)
+#define AR934X_RESET_FULL_CHIP BIT(24)
+#define AR934X_RESET_GE1_MDIO BIT(23)
+#define AR934X_RESET_GE0_MDIO BIT(22)
+#define AR934X_RESET_CPU_NMI BIT(21)
+#define AR934X_RESET_CPU_COLD BIT(20)
+#define AR934X_RESET_HOST_RESET_INT BIT(19)
+#define AR934X_RESET_PCIE_EP BIT(18)
+#define AR934X_RESET_UART1 BIT(17)
+#define AR934X_RESET_DDR BIT(16)
+#define AR934X_RESET_USB_PHY_PLL_PWD_EXT BIT(15)
+#define AR934X_RESET_NANDF BIT(14)
+#define AR934X_RESET_GE1_MAC BIT(13)
+#define AR934X_RESET_ETH_SWITCH_ANALOG BIT(12)
+#define AR934X_RESET_USB_PHY_ANALOG BIT(11)
+#define AR934X_RESET_HOST_DMA_INT BIT(10)
+#define AR934X_RESET_GE0_MAC BIT(9)
+#define AR934X_RESET_ETH_SWITCH BIT(8)
+#define AR934X_RESET_PCIE_PHY BIT(7)
+#define AR934X_RESET_PCIE BIT(6)
+#define AR934X_RESET_USB_HOST BIT(5)
+#define AR934X_RESET_USB_PHY BIT(4)
+#define AR934X_RESET_USBSUS_OVERRIDE BIT(3)
+#define AR934X_RESET_LUT BIT(2)
+#define AR934X_RESET_MBOX BIT(1)
+#define AR934X_RESET_I2S BIT(0)
+
+#define QCA953X_RESET_USB_EXT_PWR BIT(29)
+#define QCA953X_RESET_EXTERNAL BIT(28)
+#define QCA953X_RESET_RTC BIT(27)
+#define QCA953X_RESET_FULL_CHIP BIT(24)
+#define QCA953X_RESET_GE1_MDIO BIT(23)
+#define QCA953X_RESET_GE0_MDIO BIT(22)
+#define QCA953X_RESET_CPU_NMI BIT(21)
+#define QCA953X_RESET_CPU_COLD BIT(20)
+#define QCA953X_RESET_DDR BIT(16)
+#define QCA953X_RESET_USB_PHY_PLL_PWD_EXT BIT(15)
+#define QCA953X_RESET_GE1_MAC BIT(13)
+#define QCA953X_RESET_ETH_SWITCH_ANALOG BIT(12)
+#define QCA953X_RESET_USB_PHY_ANALOG BIT(11)
+#define QCA953X_RESET_GE0_MAC BIT(9)
+#define QCA953X_RESET_ETH_SWITCH BIT(8)
+#define QCA953X_RESET_PCIE_PHY BIT(7)
+#define QCA953X_RESET_PCIE BIT(6)
+#define QCA953X_RESET_USB_HOST BIT(5)
+#define QCA953X_RESET_USB_PHY BIT(4)
+#define QCA953X_RESET_USBSUS_OVERRIDE BIT(3)
+
+#define QCA955X_RESET_HOST BIT(31)
+#define QCA955X_RESET_SLIC BIT(30)
+#define QCA955X_RESET_HDMA BIT(29)
+#define QCA955X_RESET_EXTERNAL BIT(28)
+#define QCA955X_RESET_RTC BIT(27)
+#define QCA955X_RESET_PCIE_EP_INT BIT(26)
+#define QCA955X_RESET_CHKSUM_ACC BIT(25)
+#define QCA955X_RESET_FULL_CHIP BIT(24)
+#define QCA955X_RESET_GE1_MDIO BIT(23)
+#define QCA955X_RESET_GE0_MDIO BIT(22)
+#define QCA955X_RESET_CPU_NMI BIT(21)
+#define QCA955X_RESET_CPU_COLD BIT(20)
+#define QCA955X_RESET_HOST_RESET_INT BIT(19)
+#define QCA955X_RESET_PCIE_EP BIT(18)
+#define QCA955X_RESET_UART1 BIT(17)
+#define QCA955X_RESET_DDR BIT(16)
+#define QCA955X_RESET_USB_PHY_PLL_PWD_EXT BIT(15)
+#define QCA955X_RESET_NANDF BIT(14)
+#define QCA955X_RESET_GE1_MAC BIT(13)
+#define QCA955X_RESET_SGMII_ANALOG BIT(12)
+#define QCA955X_RESET_USB_PHY_ANALOG BIT(11)
+#define QCA955X_RESET_HOST_DMA_INT BIT(10)
+#define QCA955X_RESET_GE0_MAC BIT(9)
+#define QCA955X_RESET_SGMII BIT(8)
+#define QCA955X_RESET_PCIE_PHY BIT(7)
+#define QCA955X_RESET_PCIE BIT(6)
+#define QCA955X_RESET_USB_HOST BIT(5)
+#define QCA955X_RESET_USB_PHY BIT(4)
+#define QCA955X_RESET_USBSUS_OVERRIDE BIT(3)
+#define QCA955X_RESET_LUT BIT(2)
+#define QCA955X_RESET_MBOX BIT(1)
+#define QCA955X_RESET_I2S BIT(0)
+
+#define AR933X_BOOTSTRAP_MDIO_GPIO_EN BIT(18)
+#define AR933X_BOOTSTRAP_DDR2 BIT(13)
+#define AR933X_BOOTSTRAP_EEPBUSY BIT(4)
+#define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0)
+
+#define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23)
+#define AR934X_BOOTSTRAP_SW_OPTION7 BIT(22)
+#define AR934X_BOOTSTRAP_SW_OPTION6 BIT(21)
+#define AR934X_BOOTSTRAP_SW_OPTION5 BIT(20)
+#define AR934X_BOOTSTRAP_SW_OPTION4 BIT(19)
+#define AR934X_BOOTSTRAP_SW_OPTION3 BIT(18)
+#define AR934X_BOOTSTRAP_SW_OPTION2 BIT(17)
+#define AR934X_BOOTSTRAP_SW_OPTION1 BIT(16)
+#define AR934X_BOOTSTRAP_USB_MODE_DEVICE BIT(7)
+#define AR934X_BOOTSTRAP_PCIE_RC BIT(6)
+#define AR934X_BOOTSTRAP_EJTAG_MODE BIT(5)
+#define AR934X_BOOTSTRAP_REF_CLK_40 BIT(4)
+#define AR934X_BOOTSTRAP_BOOT_FROM_SPI BIT(2)
+#define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1)
+#define AR934X_BOOTSTRAP_DDR1 BIT(0)
+
+#define QCA953X_BOOTSTRAP_SW_OPTION2 BIT(12)
+#define QCA953X_BOOTSTRAP_SW_OPTION1 BIT(11)
+#define QCA953X_BOOTSTRAP_EJTAG_MODE BIT(5)
+#define QCA953X_BOOTSTRAP_REF_CLK_40 BIT(4)
+#define QCA953X_BOOTSTRAP_SDRAM_DISABLED BIT(1)
+#define QCA953X_BOOTSTRAP_DDR1 BIT(0)
+
+#define QCA955X_BOOTSTRAP_REF_CLK_40 BIT(4)
+
+#define QCA956X_BOOTSTRAP_REF_CLK_40 BIT(2)
+
+#define AR934X_PCIE_WMAC_INT_WMAC_MISC BIT(0)
+#define AR934X_PCIE_WMAC_INT_WMAC_TX BIT(1)
+#define AR934X_PCIE_WMAC_INT_WMAC_RXLP BIT(2)
+#define AR934X_PCIE_WMAC_INT_WMAC_RXHP BIT(3)
+#define AR934X_PCIE_WMAC_INT_PCIE_RC BIT(4)
+#define AR934X_PCIE_WMAC_INT_PCIE_RC0 BIT(5)
+#define AR934X_PCIE_WMAC_INT_PCIE_RC1 BIT(6)
+#define AR934X_PCIE_WMAC_INT_PCIE_RC2 BIT(7)
+#define AR934X_PCIE_WMAC_INT_PCIE_RC3 BIT(8)
+#define AR934X_PCIE_WMAC_INT_WMAC_ALL \
+ (AR934X_PCIE_WMAC_INT_WMAC_MISC | AR934X_PCIE_WMAC_INT_WMAC_TX | \
+ AR934X_PCIE_WMAC_INT_WMAC_RXLP | AR934X_PCIE_WMAC_INT_WMAC_RXHP)
+
+#define AR934X_PCIE_WMAC_INT_PCIE_ALL \
+ (AR934X_PCIE_WMAC_INT_PCIE_RC | AR934X_PCIE_WMAC_INT_PCIE_RC0 | \
+ AR934X_PCIE_WMAC_INT_PCIE_RC1 | AR934X_PCIE_WMAC_INT_PCIE_RC2 | \
+ AR934X_PCIE_WMAC_INT_PCIE_RC3)
+
+#define QCA953X_PCIE_WMAC_INT_WMAC_MISC BIT(0)
+#define QCA953X_PCIE_WMAC_INT_WMAC_TX BIT(1)
+#define QCA953X_PCIE_WMAC_INT_WMAC_RXLP BIT(2)
+#define QCA953X_PCIE_WMAC_INT_WMAC_RXHP BIT(3)
+#define QCA953X_PCIE_WMAC_INT_PCIE_RC BIT(4)
+#define QCA953X_PCIE_WMAC_INT_PCIE_RC0 BIT(5)
+#define QCA953X_PCIE_WMAC_INT_PCIE_RC1 BIT(6)
+#define QCA953X_PCIE_WMAC_INT_PCIE_RC2 BIT(7)
+#define QCA953X_PCIE_WMAC_INT_PCIE_RC3 BIT(8)
+#define QCA953X_PCIE_WMAC_INT_WMAC_ALL \
+ (QCA953X_PCIE_WMAC_INT_WMAC_MISC | QCA953X_PCIE_WMAC_INT_WMAC_TX | \
+ QCA953X_PCIE_WMAC_INT_WMAC_RXLP | QCA953X_PCIE_WMAC_INT_WMAC_RXHP)
+
+#define QCA953X_PCIE_WMAC_INT_PCIE_ALL \
+ (QCA953X_PCIE_WMAC_INT_PCIE_RC | QCA953X_PCIE_WMAC_INT_PCIE_RC0 | \
+ QCA953X_PCIE_WMAC_INT_PCIE_RC1 | QCA953X_PCIE_WMAC_INT_PCIE_RC2 | \
+ QCA953X_PCIE_WMAC_INT_PCIE_RC3)
+
+#define QCA955X_EXT_INT_WMAC_MISC BIT(0)
+#define QCA955X_EXT_INT_WMAC_TX BIT(1)
+#define QCA955X_EXT_INT_WMAC_RXLP BIT(2)
+#define QCA955X_EXT_INT_WMAC_RXHP BIT(3)
+#define QCA955X_EXT_INT_PCIE_RC1 BIT(4)
+#define QCA955X_EXT_INT_PCIE_RC1_INT0 BIT(5)
+#define QCA955X_EXT_INT_PCIE_RC1_INT1 BIT(6)
+#define QCA955X_EXT_INT_PCIE_RC1_INT2 BIT(7)
+#define QCA955X_EXT_INT_PCIE_RC1_INT3 BIT(8)
+#define QCA955X_EXT_INT_PCIE_RC2 BIT(12)
+#define QCA955X_EXT_INT_PCIE_RC2_INT0 BIT(13)
+#define QCA955X_EXT_INT_PCIE_RC2_INT1 BIT(14)
+#define QCA955X_EXT_INT_PCIE_RC2_INT2 BIT(15)
+#define QCA955X_EXT_INT_PCIE_RC2_INT3 BIT(16)
+#define QCA955X_EXT_INT_USB1 BIT(24)
+#define QCA955X_EXT_INT_USB2 BIT(28)
+
+#define QCA955X_EXT_INT_WMAC_ALL \
+ (QCA955X_EXT_INT_WMAC_MISC | QCA955X_EXT_INT_WMAC_TX | \
+ QCA955X_EXT_INT_WMAC_RXLP | QCA955X_EXT_INT_WMAC_RXHP)
+
+#define QCA955X_EXT_INT_PCIE_RC1_ALL \
+ (QCA955X_EXT_INT_PCIE_RC1 | QCA955X_EXT_INT_PCIE_RC1_INT0 | \
+ QCA955X_EXT_INT_PCIE_RC1_INT1 | QCA955X_EXT_INT_PCIE_RC1_INT2 | \
+ QCA955X_EXT_INT_PCIE_RC1_INT3)
+
+#define QCA955X_EXT_INT_PCIE_RC2_ALL \
+ (QCA955X_EXT_INT_PCIE_RC2 | QCA955X_EXT_INT_PCIE_RC2_INT0 | \
+ QCA955X_EXT_INT_PCIE_RC2_INT1 | QCA955X_EXT_INT_PCIE_RC2_INT2 | \
+ QCA955X_EXT_INT_PCIE_RC2_INT3)
+
+#define QCA956X_EXT_INT_WMAC_MISC BIT(0)
+#define QCA956X_EXT_INT_WMAC_TX BIT(1)
+#define QCA956X_EXT_INT_WMAC_RXLP BIT(2)
+#define QCA956X_EXT_INT_WMAC_RXHP BIT(3)
+#define QCA956X_EXT_INT_PCIE_RC1 BIT(4)
+#define QCA956X_EXT_INT_PCIE_RC1_INT0 BIT(5)
+#define QCA956X_EXT_INT_PCIE_RC1_INT1 BIT(6)
+#define QCA956X_EXT_INT_PCIE_RC1_INT2 BIT(7)
+#define QCA956X_EXT_INT_PCIE_RC1_INT3 BIT(8)
+#define QCA956X_EXT_INT_PCIE_RC2 BIT(12)
+#define QCA956X_EXT_INT_PCIE_RC2_INT0 BIT(13)
+#define QCA956X_EXT_INT_PCIE_RC2_INT1 BIT(14)
+#define QCA956X_EXT_INT_PCIE_RC2_INT2 BIT(15)
+#define QCA956X_EXT_INT_PCIE_RC2_INT3 BIT(16)
+#define QCA956X_EXT_INT_USB1 BIT(24)
+#define QCA956X_EXT_INT_USB2 BIT(28)
+
+#define QCA956X_EXT_INT_WMAC_ALL \
+ (QCA956X_EXT_INT_WMAC_MISC | QCA956X_EXT_INT_WMAC_TX | \
+ QCA956X_EXT_INT_WMAC_RXLP | QCA956X_EXT_INT_WMAC_RXHP)
+
+#define QCA956X_EXT_INT_PCIE_RC1_ALL \
+ (QCA956X_EXT_INT_PCIE_RC1 | QCA956X_EXT_INT_PCIE_RC1_INT0 | \
+ QCA956X_EXT_INT_PCIE_RC1_INT1 | QCA956X_EXT_INT_PCIE_RC1_INT2 | \
+ QCA956X_EXT_INT_PCIE_RC1_INT3)
+
+#define QCA956X_EXT_INT_PCIE_RC2_ALL \
+ (QCA956X_EXT_INT_PCIE_RC2 | QCA956X_EXT_INT_PCIE_RC2_INT0 | \
+ QCA956X_EXT_INT_PCIE_RC2_INT1 | QCA956X_EXT_INT_PCIE_RC2_INT2 | \
+ QCA956X_EXT_INT_PCIE_RC2_INT3)
+
+#define REV_ID_MAJOR_MASK 0xfff0
+#define REV_ID_MAJOR_AR71XX 0x00a0
+#define REV_ID_MAJOR_AR913X 0x00b0
+#define REV_ID_MAJOR_AR7240 0x00c0
+#define REV_ID_MAJOR_AR7241 0x0100
+#define REV_ID_MAJOR_AR7242 0x1100
+#define REV_ID_MAJOR_AR9330 0x0110
+#define REV_ID_MAJOR_AR9331 0x1110
+#define REV_ID_MAJOR_AR9341 0x0120
+#define REV_ID_MAJOR_AR9342 0x1120
+#define REV_ID_MAJOR_AR9344 0x2120
+#define REV_ID_MAJOR_QCA9533 0x0140
+#define REV_ID_MAJOR_QCA9533_V2 0x0160
+#define REV_ID_MAJOR_QCA9556 0x0130
+#define REV_ID_MAJOR_QCA9558 0x1130
+#define REV_ID_MAJOR_TP9343 0x0150
+#define REV_ID_MAJOR_QCA9561 0x1150
+
+#define AR71XX_REV_ID_MINOR_MASK 0x3
+#define AR71XX_REV_ID_MINOR_AR7130 0x0
+#define AR71XX_REV_ID_MINOR_AR7141 0x1
+#define AR71XX_REV_ID_MINOR_AR7161 0x2
+#define AR913X_REV_ID_MINOR_AR9130 0x0
+#define AR913X_REV_ID_MINOR_AR9132 0x1
+
+#define AR71XX_REV_ID_REVISION_MASK 0x3
+#define AR71XX_REV_ID_REVISION_SHIFT 2
+#define AR71XX_REV_ID_REVISION2_MASK 0xf
+
+/*
+ * RTC block
+ */
+#define AR933X_RTC_REG_RESET 0x40
+#define AR933X_RTC_REG_STATUS 0x44
+#define AR933X_RTC_REG_DERIVED 0x48
+#define AR933X_RTC_REG_FORCE_WAKE 0x4c
+#define AR933X_RTC_REG_INT_CAUSE 0x50
+#define AR933X_RTC_REG_CAUSE_CLR 0x50
+#define AR933X_RTC_REG_INT_ENABLE 0x54
+#define AR933X_RTC_REG_INT_MASKE 0x58
+
+#define QCA953X_RTC_REG_SYNC_RESET 0x40
+#define QCA953X_RTC_REG_SYNC_STATUS 0x44
+
+/*
+ * SPI block
+ */
+#define AR71XX_SPI_REG_FS 0x00
+#define AR71XX_SPI_REG_CTRL 0x04
+#define AR71XX_SPI_REG_IOC 0x08
+#define AR71XX_SPI_REG_RDS 0x0c
+
+#define AR71XX_SPI_FS_GPIO BIT(0)
+
+#define AR71XX_SPI_CTRL_RD BIT(6)
+#define AR71XX_SPI_CTRL_DIV_MASK 0x3f
+
+#define AR71XX_SPI_IOC_DO BIT(0)
+#define AR71XX_SPI_IOC_CLK BIT(8)
+#define AR71XX_SPI_IOC_CS(n) BIT(16 + (n))
+#define AR71XX_SPI_IOC_CS0 AR71XX_SPI_IOC_CS(0)
+#define AR71XX_SPI_IOC_CS1 AR71XX_SPI_IOC_CS(1)
+#define AR71XX_SPI_IOC_CS2 AR71XX_SPI_IOC_CS(2)
+#define AR71XX_SPI_IOC_CS_ALL \
+ (AR71XX_SPI_IOC_CS0 | AR71XX_SPI_IOC_CS1 | AR71XX_SPI_IOC_CS2)
+
+/*
+ * GPIO block
+ */
+#define AR71XX_GPIO_REG_OE 0x00
+#define AR71XX_GPIO_REG_IN 0x04
+#define AR71XX_GPIO_REG_OUT 0x08
+#define AR71XX_GPIO_REG_SET 0x0c
+#define AR71XX_GPIO_REG_CLEAR 0x10
+#define AR71XX_GPIO_REG_INT_MODE 0x14
+#define AR71XX_GPIO_REG_INT_TYPE 0x18
+#define AR71XX_GPIO_REG_INT_POLARITY 0x1c
+#define AR71XX_GPIO_REG_INT_PENDING 0x20
+#define AR71XX_GPIO_REG_INT_ENABLE 0x24
+#define AR71XX_GPIO_REG_FUNC 0x28
+#define AR933X_GPIO_REG_FUNC 0x30
+
+#define AR934X_GPIO_REG_OUT_FUNC0 0x2c
+#define AR934X_GPIO_REG_OUT_FUNC1 0x30
+#define AR934X_GPIO_REG_OUT_FUNC2 0x34
+#define AR934X_GPIO_REG_OUT_FUNC3 0x38
+#define AR934X_GPIO_REG_OUT_FUNC4 0x3c
+#define AR934X_GPIO_REG_OUT_FUNC5 0x40
+#define AR934X_GPIO_REG_FUNC 0x6c
+
+#define QCA953X_GPIO_REG_OUT_FUNC0 0x2c
+#define QCA953X_GPIO_REG_OUT_FUNC1 0x30
+#define QCA953X_GPIO_REG_OUT_FUNC2 0x34
+#define QCA953X_GPIO_REG_OUT_FUNC3 0x38
+#define QCA953X_GPIO_REG_OUT_FUNC4 0x3c
+#define QCA953X_GPIO_REG_IN_ENABLE0 0x44
+#define QCA953X_GPIO_REG_FUNC 0x6c
+
+#define QCA955X_GPIO_REG_OUT_FUNC0 0x2c
+#define QCA955X_GPIO_REG_OUT_FUNC1 0x30
+#define QCA955X_GPIO_REG_OUT_FUNC2 0x34
+#define QCA955X_GPIO_REG_OUT_FUNC3 0x38
+#define QCA955X_GPIO_REG_OUT_FUNC4 0x3c
+#define QCA955X_GPIO_REG_OUT_FUNC5 0x40
+#define QCA955X_GPIO_REG_FUNC 0x6c
+
+#define QCA956X_GPIO_REG_OUT_FUNC0 0x2c
+#define QCA956X_GPIO_REG_OUT_FUNC1 0x30
+#define QCA956X_GPIO_REG_OUT_FUNC2 0x34
+#define QCA956X_GPIO_REG_OUT_FUNC3 0x38
+#define QCA956X_GPIO_REG_OUT_FUNC4 0x3c
+#define QCA956X_GPIO_REG_OUT_FUNC5 0x40
+#define QCA956X_GPIO_REG_IN_ENABLE0 0x44
+#define QCA956X_GPIO_REG_IN_ENABLE3 0x50
+#define QCA956X_GPIO_REG_FUNC 0x6c
+
+#define AR71XX_GPIO_FUNC_STEREO_EN BIT(17)
+#define AR71XX_GPIO_FUNC_SLIC_EN BIT(16)
+#define AR71XX_GPIO_FUNC_SPI_CS2_EN BIT(13)
+#define AR71XX_GPIO_FUNC_SPI_CS1_EN BIT(12)
+#define AR71XX_GPIO_FUNC_UART_EN BIT(8)
+#define AR71XX_GPIO_FUNC_USB_OC_EN BIT(4)
+#define AR71XX_GPIO_FUNC_USB_CLK_EN BIT(0)
+
+#define AR724X_GPIO_FUNC_GE0_MII_CLK_EN BIT(19)
+#define AR724X_GPIO_FUNC_SPI_EN BIT(18)
+#define AR724X_GPIO_FUNC_SPI_CS_EN2 BIT(14)
+#define AR724X_GPIO_FUNC_SPI_CS_EN1 BIT(13)
+#define AR724X_GPIO_FUNC_CLK_OBS5_EN BIT(12)
+#define AR724X_GPIO_FUNC_CLK_OBS4_EN BIT(11)
+#define AR724X_GPIO_FUNC_CLK_OBS3_EN BIT(10)
+#define AR724X_GPIO_FUNC_CLK_OBS2_EN BIT(9)
+#define AR724X_GPIO_FUNC_CLK_OBS1_EN BIT(8)
+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7)
+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6)
+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5)
+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4)
+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3)
+#define AR724X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2)
+#define AR724X_GPIO_FUNC_UART_EN BIT(1)
+#define AR724X_GPIO_FUNC_JTAG_DISABLE BIT(0)
+
+#define AR913X_GPIO_FUNC_WMAC_LED_EN BIT(22)
+#define AR913X_GPIO_FUNC_EXP_PORT_CS_EN BIT(21)
+#define AR913X_GPIO_FUNC_I2S_REFCLKEN BIT(20)
+#define AR913X_GPIO_FUNC_I2S_MCKEN BIT(19)
+#define AR913X_GPIO_FUNC_I2S1_EN BIT(18)
+#define AR913X_GPIO_FUNC_I2S0_EN BIT(17)
+#define AR913X_GPIO_FUNC_SLIC_EN BIT(16)
+#define AR913X_GPIO_FUNC_UART_RTSCTS_EN BIT(9)
+#define AR913X_GPIO_FUNC_UART_EN BIT(8)
+#define AR913X_GPIO_FUNC_USB_CLK_EN BIT(4)
+
+#define AR933X_GPIO(x) BIT(x)
+#define AR933X_GPIO_FUNC_SPDIF2TCK BIT(31)
+#define AR933X_GPIO_FUNC_SPDIF_EN BIT(30)
+#define AR933X_GPIO_FUNC_I2SO_22_18_EN BIT(29)
+#define AR933X_GPIO_FUNC_I2S_MCK_EN BIT(27)
+#define AR933X_GPIO_FUNC_I2SO_EN BIT(26)
+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_DUPL BIT(25)
+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_COLL BIT(24)
+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_ACT BIT(23)
+#define AR933X_GPIO_FUNC_SPI_EN BIT(18)
+#define AR933X_GPIO_FUNC_RES_TRUE BIT(15)
+#define AR933X_GPIO_FUNC_SPI_CS_EN2 BIT(14)
+#define AR933X_GPIO_FUNC_SPI_CS_EN1 BIT(13)
+#define AR933X_GPIO_FUNC_XLNA_EN BIT(12)
+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7)
+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6)
+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5)
+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4)
+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3)
+#define AR933X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2)
+#define AR933X_GPIO_FUNC_UART_EN BIT(1)
+#define AR933X_GPIO_FUNC_JTAG_DISABLE BIT(0)
+
+#define AR934X_GPIO_FUNC_CLK_OBS7_EN BIT(9)
+#define AR934X_GPIO_FUNC_CLK_OBS6_EN BIT(8)
+#define AR934X_GPIO_FUNC_CLK_OBS5_EN BIT(7)
+#define AR934X_GPIO_FUNC_CLK_OBS4_EN BIT(6)
+#define AR934X_GPIO_FUNC_CLK_OBS3_EN BIT(5)
+#define AR934X_GPIO_FUNC_CLK_OBS2_EN BIT(4)
+#define AR934X_GPIO_FUNC_CLK_OBS1_EN BIT(3)
+#define AR934X_GPIO_FUNC_CLK_OBS0_EN BIT(2)
+#define AR934X_GPIO_FUNC_JTAG_DISABLE BIT(1)
+
+#define AR934X_GPIO_OUT_GPIO 0
+#define AR934X_GPIO_OUT_SPI_CS1 7
+#define AR934X_GPIO_OUT_LED_LINK0 41
+#define AR934X_GPIO_OUT_LED_LINK1 42
+#define AR934X_GPIO_OUT_LED_LINK2 43
+#define AR934X_GPIO_OUT_LED_LINK3 44
+#define AR934X_GPIO_OUT_LED_LINK4 45
+#define AR934X_GPIO_OUT_EXT_LNA0 46
+#define AR934X_GPIO_OUT_EXT_LNA1 47
+
+#define QCA953X_GPIO(x) BIT(x)
+#define QCA953X_GPIO_MUX_MASK(x) (0xff << (x))
+#define QCA953X_GPIO_OUT_MUX_SPI_CS1 10
+#define QCA953X_GPIO_OUT_MUX_SPI_CS2 11
+#define QCA953X_GPIO_OUT_MUX_SPI_CS0 9
+#define QCA953X_GPIO_OUT_MUX_SPI_CLK 8
+#define QCA953X_GPIO_OUT_MUX_SPI_MOSI 12
+#define QCA953X_GPIO_OUT_MUX_UART0_SOUT 22
+#define QCA953X_GPIO_OUT_MUX_LED_LINK1 41
+#define QCA953X_GPIO_OUT_MUX_LED_LINK2 42
+#define QCA953X_GPIO_OUT_MUX_LED_LINK3 43
+#define QCA953X_GPIO_OUT_MUX_LED_LINK4 44
+#define QCA953X_GPIO_OUT_MUX_LED_LINK5 45
+
+#define QCA953X_GPIO_IN_MUX_UART0_SIN 9
+#define QCA953X_GPIO_IN_MUX_SPI_DATA_IN 8
+
+#define QCA956X_GPIO_OUT_MUX_GE0_MDO 32
+#define QCA956X_GPIO_OUT_MUX_GE0_MDC 33
+
+#define AR71XX_GPIO_COUNT 16
+#define AR7240_GPIO_COUNT 18
+#define AR7241_GPIO_COUNT 20
+#define AR913X_GPIO_COUNT 22
+#define AR933X_GPIO_COUNT 30
+#define AR934X_GPIO_COUNT 23
+#define QCA953X_GPIO_COUNT 18
+#define QCA955X_GPIO_COUNT 24
+#define QCA956X_GPIO_COUNT 23
+
+/*
+ * SRIF block
+ */
+#define AR933X_SRIF_DDR_DPLL1_REG 0x240
+#define AR933X_SRIF_DDR_DPLL2_REG 0x244
+#define AR933X_SRIF_DDR_DPLL3_REG 0x248
+#define AR933X_SRIF_DDR_DPLL4_REG 0x24c
+
+#define AR934X_SRIF_CPU_DPLL1_REG 0x1c0
+#define AR934X_SRIF_CPU_DPLL2_REG 0x1c4
+#define AR934X_SRIF_CPU_DPLL3_REG 0x1c8
+#define AR934X_SRIF_CPU_DPLL4_REG 0x1cc
+
+#define AR934X_SRIF_DDR_DPLL1_REG 0x240
+#define AR934X_SRIF_DDR_DPLL2_REG 0x244
+#define AR934X_SRIF_DDR_DPLL3_REG 0x248
+#define AR934X_SRIF_DDR_DPLL4_REG 0x24c
+
+#define AR934X_SRIF_DPLL1_REFDIV_SHIFT 27
+#define AR934X_SRIF_DPLL1_REFDIV_MASK 0x1f
+#define AR934X_SRIF_DPLL1_NINT_SHIFT 18
+#define AR934X_SRIF_DPLL1_NINT_MASK 0x1ff
+#define AR934X_SRIF_DPLL1_NFRAC_MASK 0x0003ffff
+
+#define AR934X_SRIF_DPLL2_LOCAL_PLL BIT(30)
+#define AR934X_SRIF_DPLL2_OUTDIV_SHIFT 13
+#define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7
+
+#define QCA953X_SRIF_BB_DPLL1_REG 0x180
+#define QCA953X_SRIF_BB_DPLL2_REG 0x184
+#define QCA953X_SRIF_BB_DPLL3_REG 0x188
+
+#define QCA953X_SRIF_CPU_DPLL1_REG 0x1c0
+#define QCA953X_SRIF_CPU_DPLL2_REG 0x1c4
+#define QCA953X_SRIF_CPU_DPLL3_REG 0x1c8
+
+#define QCA953X_SRIF_DDR_DPLL1_REG 0x240
+#define QCA953X_SRIF_DDR_DPLL2_REG 0x244
+#define QCA953X_SRIF_DDR_DPLL3_REG 0x248
+
+#define QCA953X_SRIF_PCIE_DPLL1_REG 0xc00
+#define QCA953X_SRIF_PCIE_DPLL2_REG 0xc04
+#define QCA953X_SRIF_PCIE_DPLL3_REG 0xc08
+
+#define QCA953X_SRIF_PMU1_REG 0xc40
+#define QCA953X_SRIF_PMU2_REG 0xc44
+
+#define QCA953X_SRIF_DPLL1_REFDIV_SHIFT 27
+#define QCA953X_SRIF_DPLL1_REFDIV_MASK 0x1f
+
+#define QCA953X_SRIF_DPLL1_NINT_SHIFT 18
+#define QCA953X_SRIF_DPLL1_NINT_MASK 0x1ff
+#define QCA953X_SRIF_DPLL1_NFRAC_MASK 0x0003ffff
+
+#define QCA953X_SRIF_DPLL2_LOCAL_PLL BIT(30)
+
+#define QCA953X_SRIF_DPLL2_KI_SHIFT 29
+#define QCA953X_SRIF_DPLL2_KI_MASK 0x3
+
+#define QCA953X_SRIF_DPLL2_KD_SHIFT 25
+#define QCA953X_SRIF_DPLL2_KD_MASK 0xf
+
+#define QCA953X_SRIF_DPLL2_PWD BIT(22)
+
+#define QCA953X_SRIF_DPLL2_OUTDIV_SHIFT 13
+#define QCA953X_SRIF_DPLL2_OUTDIV_MASK 0x7
+
+/*
+ * MII_CTRL block
+ */
+#define AR71XX_MII_REG_MII0_CTRL 0x00
+#define AR71XX_MII_REG_MII1_CTRL 0x04
+
+#define AR71XX_MII_CTRL_IF_MASK 3
+#define AR71XX_MII_CTRL_SPEED_SHIFT 4
+#define AR71XX_MII_CTRL_SPEED_MASK 3
+#define AR71XX_MII_CTRL_SPEED_10 0
+#define AR71XX_MII_CTRL_SPEED_100 1
+#define AR71XX_MII_CTRL_SPEED_1000 2
+
+#define AR71XX_MII0_CTRL_IF_GMII 0
+#define AR71XX_MII0_CTRL_IF_MII 1
+#define AR71XX_MII0_CTRL_IF_RGMII 2
+#define AR71XX_MII0_CTRL_IF_RMII 3
+
+#define AR71XX_MII1_CTRL_IF_RGMII 0
+#define AR71XX_MII1_CTRL_IF_RMII 1
+
+/*
+ * AR933X GMAC interface
+ */
+#define AR933X_GMAC_REG_ETH_CFG 0x00
+
+#define AR933X_ETH_CFG_RGMII_GE0 BIT(0)
+#define AR933X_ETH_CFG_MII_GE0 BIT(1)
+#define AR933X_ETH_CFG_GMII_GE0 BIT(2)
+#define AR933X_ETH_CFG_MII_GE0_MASTER BIT(3)
+#define AR933X_ETH_CFG_MII_GE0_SLAVE BIT(4)
+#define AR933X_ETH_CFG_MII_GE0_ERR_EN BIT(5)
+#define AR933X_ETH_CFG_SW_PHY_SWAP BIT(7)
+#define AR933X_ETH_CFG_SW_PHY_ADDR_SWAP BIT(8)
+#define AR933X_ETH_CFG_RMII_GE0 BIT(9)
+#define AR933X_ETH_CFG_RMII_GE0_SPD_10 0
+#define AR933X_ETH_CFG_RMII_GE0_SPD_100 BIT(10)
+
+/*
+ * AR934X GMAC Interface
+ */
+#define AR934X_GMAC_REG_ETH_CFG 0x00
+
+#define AR934X_ETH_CFG_RGMII_GMAC0 BIT(0)
+#define AR934X_ETH_CFG_MII_GMAC0 BIT(1)
+#define AR934X_ETH_CFG_GMII_GMAC0 BIT(2)
+#define AR934X_ETH_CFG_MII_GMAC0_MASTER BIT(3)
+#define AR934X_ETH_CFG_MII_GMAC0_SLAVE BIT(4)
+#define AR934X_ETH_CFG_MII_GMAC0_ERR_EN BIT(5)
+#define AR934X_ETH_CFG_SW_ONLY_MODE BIT(6)
+#define AR934X_ETH_CFG_SW_PHY_SWAP BIT(7)
+#define AR934X_ETH_CFG_SW_APB_ACCESS BIT(9)
+#define AR934X_ETH_CFG_RMII_GMAC0 BIT(10)
+#define AR933X_ETH_CFG_MII_CNTL_SPEED BIT(11)
+#define AR934X_ETH_CFG_RMII_GMAC0_MASTER BIT(12)
+#define AR933X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13)
+#define AR934X_ETH_CFG_RXD_DELAY BIT(14)
+#define AR934X_ETH_CFG_RXD_DELAY_MASK 0x3
+#define AR934X_ETH_CFG_RXD_DELAY_SHIFT 14
+#define AR934X_ETH_CFG_RDV_DELAY BIT(16)
+#define AR934X_ETH_CFG_RDV_DELAY_MASK 0x3
+#define AR934X_ETH_CFG_RDV_DELAY_SHIFT 16
+
+/*
+ * QCA953X GMAC Interface
+ */
+#define QCA953X_GMAC_REG_ETH_CFG 0x00
+
+#define QCA953X_ETH_CFG_SW_ONLY_MODE BIT(6)
+#define QCA953X_ETH_CFG_SW_PHY_SWAP BIT(7)
+#define QCA953X_ETH_CFG_SW_APB_ACCESS BIT(9)
+#define QCA953X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13)
+
+/*
+ * QCA955X GMAC Interface
+ */
+
+#define QCA955X_GMAC_REG_ETH_CFG 0x00
+
+#define QCA955X_ETH_CFG_RGMII_EN BIT(0)
+#define QCA955X_ETH_CFG_GE0_SGMII BIT(6)
+
+#endif /* __ASM_AR71XX_H */
--- /dev/null
+/*
+ * Atheros AR71XX/AR724X/AR913X common definitions
+ *
+ * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
+ * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_MACH_ATH79_H
+#define __ASM_MACH_ATH79_H
+
+#include <linux/types.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+enum ath79_soc_type {
+ ATH79_SOC_UNKNOWN,
+ ATH79_SOC_AR7130,
+ ATH79_SOC_AR7141,
+ ATH79_SOC_AR7161,
+ ATH79_SOC_AR7240,
+ ATH79_SOC_AR7241,
+ ATH79_SOC_AR7242,
+ ATH79_SOC_AR9130,
+ ATH79_SOC_AR9132,
+ ATH79_SOC_AR9330,
+ ATH79_SOC_AR9331,
+ ATH79_SOC_AR9341,
+ ATH79_SOC_AR9342,
+ ATH79_SOC_AR9344,
+ ATH79_SOC_QCA9533,
+ ATH79_SOC_QCA9556,
+ ATH79_SOC_QCA9558,
+ ATH79_SOC_TP9343,
+ ATH79_SOC_QCA9561,
+};
+
+static inline int soc_is_ar71xx(void)
+{
+ return gd->arch.soc == ATH79_SOC_AR7130 ||
+ gd->arch.soc == ATH79_SOC_AR7141 ||
+ gd->arch.soc == ATH79_SOC_AR7161;
+}
+
+static inline int soc_is_ar724x(void)
+{
+ return gd->arch.soc == ATH79_SOC_AR7240 ||
+ gd->arch.soc == ATH79_SOC_AR7241 ||
+ gd->arch.soc == ATH79_SOC_AR7242;
+}
+
+static inline int soc_is_ar7240(void)
+{
+ return gd->arch.soc == ATH79_SOC_AR7240;
+}
+
+static inline int soc_is_ar7241(void)
+{
+ return gd->arch.soc == ATH79_SOC_AR7241;
+}
+
+static inline int soc_is_ar7242(void)
+{
+ return gd->arch.soc == ATH79_SOC_AR7242;
+}
+
+static inline int soc_is_ar913x(void)
+{
+ return gd->arch.soc == ATH79_SOC_AR9130 ||
+ gd->arch.soc == ATH79_SOC_AR9132;
+}
+
+static inline int soc_is_ar933x(void)
+{
+ return gd->arch.soc == ATH79_SOC_AR9330 ||
+ gd->arch.soc == ATH79_SOC_AR9331;
+}
+
+static inline int soc_is_ar9341(void)
+{
+ return gd->arch.soc == ATH79_SOC_AR9341;
+}
+
+static inline int soc_is_ar9342(void)
+{
+ return gd->arch.soc == ATH79_SOC_AR9342;
+}
+
+static inline int soc_is_ar9344(void)
+{
+ return gd->arch.soc == ATH79_SOC_AR9344;
+}
+
+static inline int soc_is_ar934x(void)
+{
+ return soc_is_ar9341() ||
+ soc_is_ar9342() ||
+ soc_is_ar9344();
+}
+
+static inline int soc_is_qca9533(void)
+{
+ return gd->arch.soc == ATH79_SOC_QCA9533;
+}
+
+static inline int soc_is_qca953x(void)
+{
+ return soc_is_qca9533();
+}
+
+static inline int soc_is_qca9556(void)
+{
+ return gd->arch.soc == ATH79_SOC_QCA9556;
+}
+
+static inline int soc_is_qca9558(void)
+{
+ return gd->arch.soc == ATH79_SOC_QCA9558;
+}
+
+static inline int soc_is_qca955x(void)
+{
+ return soc_is_qca9556() || soc_is_qca9558();
+}
+
+static inline int soc_is_tp9343(void)
+{
+ return gd->arch.soc == ATH79_SOC_TP9343;
+}
+
+static inline int soc_is_qca9561(void)
+{
+ return gd->arch.soc == ATH79_SOC_QCA9561;
+}
+
+static inline int soc_is_qca956x(void)
+{
+ return soc_is_tp9343() || soc_is_qca9561();
+}
+
+int ath79_eth_reset(void);
+int ath79_usb_reset(void);
+
+void ar934x_pll_init(const u16 cpu_mhz, const u16 ddr_mhz, const u16 ahb_mhz);
+void ar934x_ddr_init(const u16 cpu_mhz, const u16 ddr_mhz, const u16 ahb_mhz);
+
+#endif /* __ASM_MACH_ATH79_H */
--- /dev/null
+/*
+ * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_MACH_DDR_H
+#define __ASM_MACH_DDR_H
+
+void ddr_init(void);
+void ddr_tap_tuning(void);
+
+#endif /* __ASM_MACH_DDR_H */
--- /dev/null
+/*
+ * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_MACH_RESET_H
+#define __ASM_MACH_RESET_H
+
+#include <linux/types.h>
+
+u32 get_bootstrap(void);
+
+#endif /* __ASM_MACH_RESET_H */
--- /dev/null
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += clk.o
+obj-y += ddr.o
+obj-y += lowlevel_init.o
--- /dev/null
+/*
+ * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/addrspace.h>
+#include <asm/types.h>
+#include <mach/ar71xx_regs.h>
+#include <mach/reset.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static u32 qca953x_get_xtal(void)
+{
+ u32 val;
+
+ val = get_bootstrap();
+ if (val & QCA953X_BOOTSTRAP_REF_CLK_40)
+ return 40000000;
+ else
+ return 25000000;
+}
+
+int get_serial_clock(void)
+{
+ return qca953x_get_xtal();
+}
+
+int get_clocks(void)
+{
+ void __iomem *regs;
+ u32 val, ctrl, xtal, pll, div;
+
+ regs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE,
+ MAP_NOCACHE);
+
+ xtal = qca953x_get_xtal();
+ ctrl = readl(regs + QCA953X_PLL_CLK_CTRL_REG);
+ val = readl(regs + QCA953X_PLL_CPU_CONFIG_REG);
+
+ /* VCOOUT = XTAL * DIV_INT */
+ div = (val >> QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT)
+ & QCA953X_PLL_CPU_CONFIG_REFDIV_MASK;
+ pll = xtal / div;
+
+ /* PLLOUT = VCOOUT * (1/2^OUTDIV) */
+ div = (val >> QCA953X_PLL_CPU_CONFIG_NINT_SHIFT)
+ & QCA953X_PLL_CPU_CONFIG_NINT_MASK;
+ pll *= div;
+ div = (val >> QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT)
+ & QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK;
+ if (!div)
+ div = 1;
+ pll >>= div;
+
+ /* CPU_CLK = PLLOUT / CPU_POST_DIV */
+ div = ((ctrl >> QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT)
+ & QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK) + 1;
+ gd->cpu_clk = pll / div;
+
+
+ val = readl(regs + QCA953X_PLL_DDR_CONFIG_REG);
+ /* VCOOUT = XTAL * DIV_INT */
+ div = (val >> QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT)
+ & QCA953X_PLL_DDR_CONFIG_REFDIV_MASK;
+ pll = xtal / div;
+
+ /* PLLOUT = VCOOUT * (1/2^OUTDIV) */
+ div = (val >> QCA953X_PLL_DDR_CONFIG_NINT_SHIFT)
+ & QCA953X_PLL_DDR_CONFIG_NINT_MASK;
+ pll *= div;
+ div = (val >> QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT)
+ & QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK;
+ if (!div)
+ div = 1;
+ pll >>= div;
+
+ /* DDR_CLK = PLLOUT / DDR_POST_DIV */
+ div = ((ctrl >> QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT)
+ & QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK) + 1;
+ gd->mem_clk = pll / div;
+
+ div = ((ctrl >> QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT)
+ & QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_MASK) + 1;
+ if (ctrl & QCA953X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL) {
+ /* AHB_CLK = DDR_CLK / AHB_POST_DIV */
+ gd->bus_clk = gd->mem_clk / (div + 1);
+ } else {
+ /* AHB_CLK = CPU_CLK / AHB_POST_DIV */
+ gd->bus_clk = gd->cpu_clk / (div + 1);
+ }
+
+ return 0;
+}
+
+ulong get_bus_freq(ulong dummy)
+{
+ if (!gd->bus_clk)
+ get_clocks();
+ return gd->bus_clk;
+}
+
+ulong get_ddr_freq(ulong dummy)
+{
+ if (!gd->mem_clk)
+ get_clocks();
+ return gd->mem_clk;
+}
--- /dev/null
+/*
+ * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
+ * Based on Atheros LSDK/QSDK
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/addrspace.h>
+#include <asm/types.h>
+#include <mach/ar71xx_regs.h>
+#include <mach/reset.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define DDR_CTRL_UPD_EMR3S BIT(5)
+#define DDR_CTRL_UPD_EMR2S BIT(4)
+#define DDR_CTRL_PRECHARGE BIT(3)
+#define DDR_CTRL_AUTO_REFRESH BIT(2)
+#define DDR_CTRL_UPD_EMRS BIT(1)
+#define DDR_CTRL_UPD_MRS BIT(0)
+
+#define DDR_REFRESH_EN BIT(14)
+#define DDR_REFRESH_M 0x3ff
+#define DDR_REFRESH(x) ((x) & DDR_REFRESH_M)
+#define DDR_REFRESH_VAL (DDR_REFRESH_EN | DDR_REFRESH(312))
+
+#define DDR_TRAS_S 0
+#define DDR_TRAS_M 0x1f
+#define DDR_TRAS(x) (((x) & DDR_TRAS_M) << DDR_TRAS_S)
+#define DDR_TRCD_M 0xf
+#define DDR_TRCD_S 5
+#define DDR_TRCD(x) (((x) & DDR_TRCD_M) << DDR_TRCD_S)
+#define DDR_TRP_M 0xf
+#define DDR_TRP_S 9
+#define DDR_TRP(x) (((x) & DDR_TRP_M) << DDR_TRP_S)
+#define DDR_TRRD_M 0xf
+#define DDR_TRRD_S 13
+#define DDR_TRRD(x) (((x) & DDR_TRRD_M) << DDR_TRRD_S)
+#define DDR_TRFC_M 0x7f
+#define DDR_TRFC_S 17
+#define DDR_TRFC(x) (((x) & DDR_TRFC_M) << DDR_TRFC_S)
+#define DDR_TMRD_M 0xf
+#define DDR_TMRD_S 23
+#define DDR_TMRD(x) (((x) & DDR_TMRD_M) << DDR_TMRD_S)
+#define DDR_CAS_L_M 0x17
+#define DDR_CAS_L_S 27
+#define DDR_CAS_L(x) (((x) & DDR_CAS_L_M) << DDR_CAS_L_S)
+#define DDR_OPEN BIT(30)
+#define DDR1_CONF_REG_VAL (DDR_TRAS(16) | DDR_TRCD(6) | \
+ DDR_TRP(6) | DDR_TRRD(4) | \
+ DDR_TRFC(7) | DDR_TMRD(5) | \
+ DDR_CAS_L(7) | DDR_OPEN)
+#define DDR2_CONF_REG_VAL (DDR_TRAS(27) | DDR_TRCD(9) | \
+ DDR_TRP(9) | DDR_TRRD(7) | \
+ DDR_TRFC(21) | DDR_TMRD(15) | \
+ DDR_CAS_L(17) | DDR_OPEN)
+
+#define DDR_BURST_LEN_S 0
+#define DDR_BURST_LEN_M 0xf
+#define DDR_BURST_LEN(x) ((x) << DDR_BURST_LEN_S)
+#define DDR_BURST_TYPE BIT(4)
+#define DDR_CNTL_OE_EN BIT(5)
+#define DDR_PHASE_SEL BIT(6)
+#define DDR_CKE BIT(7)
+#define DDR_TWR_S 8
+#define DDR_TWR_M 0xf
+#define DDR_TWR(x) (((x) & DDR_TWR_M) << DDR_TWR_S)
+#define DDR_TRTW_S 12
+#define DDR_TRTW_M 0x1f
+#define DDR_TRTW(x) (((x) & DDR_TRTW_M) << DDR_TRTW_S)
+#define DDR_TRTP_S 17
+#define DDR_TRTP_M 0xf
+#define DDR_TRTP(x) (((x) & DDR_TRTP_M) << DDR_TRTP_S)
+#define DDR_TWTR_S 21
+#define DDR_TWTR_M 0x1f
+#define DDR_TWTR(x) (((x) & DDR_TWTR_M) << DDR_TWTR_S)
+#define DDR_G_OPEN_L_S 26
+#define DDR_G_OPEN_L_M 0xf
+#define DDR_G_OPEN_L(x) ((x) << DDR_G_OPEN_L_S)
+#define DDR_HALF_WIDTH_LOW BIT(31)
+#define DDR1_CONF2_REG_VAL (DDR_BURST_LEN(8) | DDR_CNTL_OE_EN | \
+ DDR_CKE | DDR_TWR(13) | DDR_TRTW(14) | \
+ DDR_TRTP(8) | DDR_TWTR(14) | \
+ DDR_G_OPEN_L(6) | DDR_HALF_WIDTH_LOW)
+#define DDR2_CONF2_REG_VAL (DDR_BURST_LEN(8) | DDR_CNTL_OE_EN | \
+ DDR_CKE | DDR_TWR(1) | DDR_TRTW(14) | \
+ DDR_TRTP(9) | DDR_TWTR(21) | \
+ DDR_G_OPEN_L(8) | DDR_HALF_WIDTH_LOW)
+
+#define DDR_TWR_MSB BIT(3)
+#define DDR_TRAS_MSB BIT(2)
+#define DDR_TRFC_MSB_M 0x3
+#define DDR_TRFC_MSB(x) (x)
+#define DDR1_CONF3_REG_VAL 0
+#define DDR2_CONF3_REG_VAL (DDR_TWR_MSB | DDR_TRFC_MSB(2))
+
+#define DDR_CTL_SRAM_TSEL BIT(30)
+#define DDR_CTL_SRAM_GE0_SYNC BIT(20)
+#define DDR_CTL_SRAM_GE1_SYNC BIT(19)
+#define DDR_CTL_SRAM_USB_SYNC BIT(18)
+#define DDR_CTL_SRAM_PCIE_SYNC BIT(17)
+#define DDR_CTL_SRAM_WMAC_SYNC BIT(16)
+#define DDR_CTL_SRAM_MISC1_SYNC BIT(15)
+#define DDR_CTL_SRAM_MISC2_SYNC BIT(14)
+#define DDR_CTL_PAD_DDR2_SEL BIT(6)
+#define DDR_CTL_HALF_WIDTH BIT(1)
+#define DDR_CTL_CONFIG_VAL (DDR_CTL_SRAM_TSEL | \
+ DDR_CTL_SRAM_GE0_SYNC | \
+ DDR_CTL_SRAM_GE1_SYNC | \
+ DDR_CTL_SRAM_USB_SYNC | \
+ DDR_CTL_SRAM_PCIE_SYNC | \
+ DDR_CTL_SRAM_WMAC_SYNC | \
+ DDR_CTL_HALF_WIDTH)
+
+#define DDR_BURST_GE0_MAX_BL_S 0
+#define DDR_BURST_GE0_MAX_BL_M 0xf
+#define DDR_BURST_GE0_MAX_BL(x) \
+ (((x) & DDR_BURST_GE0_MAX_BL_M) << DDR_BURST_GE0_MAX_BL_S)
+#define DDR_BURST_GE1_MAX_BL_S 4
+#define DDR_BURST_GE1_MAX_BL_M 0xf
+#define DDR_BURST_GE1_MAX_BL(x) \
+ (((x) & DDR_BURST_GE1_MAX_BL_M) << DDR_BURST_GE1_MAX_BL_S)
+#define DDR_BURST_PCIE_MAX_BL_S 8
+#define DDR_BURST_PCIE_MAX_BL_M 0xf
+#define DDR_BURST_PCIE_MAX_BL(x) \
+ (((x) & DDR_BURST_PCIE_MAX_BL_M) << DDR_BURST_PCIE_MAX_BL_S)
+#define DDR_BURST_USB_MAX_BL_S 12
+#define DDR_BURST_USB_MAX_BL_M 0xf
+#define DDR_BURST_USB_MAX_BL(x) \
+ (((x) & DDR_BURST_USB_MAX_BL_M) << DDR_BURST_USB_MAX_BL_S)
+#define DDR_BURST_CPU_MAX_BL_S 16
+#define DDR_BURST_CPU_MAX_BL_M 0xf
+#define DDR_BURST_CPU_MAX_BL(x) \
+ (((x) & DDR_BURST_CPU_MAX_BL_M) << DDR_BURST_CPU_MAX_BL_S)
+#define DDR_BURST_RD_MAX_BL_S 20
+#define DDR_BURST_RD_MAX_BL_M 0xf
+#define DDR_BURST_RD_MAX_BL(x) \
+ (((x) & DDR_BURST_RD_MAX_BL_M) << DDR_BURST_RD_MAX_BL_S)
+#define DDR_BURST_WR_MAX_BL_S 24
+#define DDR_BURST_WR_MAX_BL_M 0xf
+#define DDR_BURST_WR_MAX_BL(x) \
+ (((x) & DDR_BURST_WR_MAX_BL_M) << DDR_BURST_WR_MAX_BL_S)
+#define DDR_BURST_RWP_MASK_EN_S 28
+#define DDR_BURST_RWP_MASK_EN_M 0x3
+#define DDR_BURST_RWP_MASK_EN(x) \
+ (((x) & DDR_BURST_RWP_MASK_EN_M) << DDR_BURST_RWP_MASK_EN_S)
+#define DDR_BURST_CPU_PRI_BE BIT(30)
+#define DDR_BURST_CPU_PRI BIT(31)
+#define DDR_BURST_VAL (DDR_BURST_CPU_PRI_BE | \
+ DDR_BURST_RWP_MASK_EN(3) | \
+ DDR_BURST_WR_MAX_BL(4) | \
+ DDR_BURST_RD_MAX_BL(4) | \
+ DDR_BURST_CPU_MAX_BL(4) | \
+ DDR_BURST_USB_MAX_BL(4) | \
+ DDR_BURST_PCIE_MAX_BL(4) | \
+ DDR_BURST_GE1_MAX_BL(4) | \
+ DDR_BURST_GE0_MAX_BL(4))
+
+#define DDR_BURST_WMAC_MAX_BL_S 0
+#define DDR_BURST_WMAC_MAX_BL_M 0xf
+#define DDR_BURST_WMAC_MAX_BL(x) \
+ (((x) & DDR_BURST_WMAC_MAX_BL_M) << DDR_BURST_WMAC_MAX_BL_S)
+#define DDR_BURST2_VAL DDR_BURST_WMAC_MAX_BL(4)
+
+#define DDR2_CONF_TWL_S 10
+#define DDR2_CONF_TWL_M 0xf
+#define DDR2_CONF_TWL(x) \
+ (((x) & DDR2_CONF_TWL_M) << DDR2_CONF_TWL_S)
+#define DDR2_CONF_ODT BIT(9)
+#define DDR2_CONF_TFAW_S 2
+#define DDR2_CONF_TFAW_M 0x3f
+#define DDR2_CONF_TFAW(x) \
+ (((x) & DDR2_CONF_TFAW_M) << DDR2_CONF_TFAW_S)
+#define DDR2_CONF_EN BIT(0)
+#define DDR2_CONF_VAL (DDR2_CONF_TWL(5) | \
+ DDR2_CONF_TFAW(31) | \
+ DDR2_CONF_ODT | \
+ DDR2_CONF_EN)
+
+#define DDR1_EXT_MODE_VAL 0
+#define DDR2_EXT_MODE_VAL 0x402
+#define DDR2_EXT_MODE_OCD_VAL 0x782
+#define DDR1_MODE_DLL_VAL 0x133
+#define DDR2_MODE_DLL_VAL 0x143
+#define DDR1_MODE_VAL 0x33
+#define DDR2_MODE_VAL 0x43
+#define DDR1_TAP_VAL 0x20
+#define DDR2_TAP_VAL 0x10
+
+#define DDR_REG_BIST_MASK_ADDR_0 0x2c
+#define DDR_REG_BIST_MASK_ADDR_1 0x30
+#define DDR_REG_BIST_MASK_AHB_GE0_0 0x34
+#define DDR_REG_BIST_COMP_AHB_GE0_0 0x38
+#define DDR_REG_BIST_MASK_AHB_GE1_0 0x3c
+#define DDR_REG_BIST_COMP_AHB_GE1_0 0x40
+#define DDR_REG_BIST_COMP_ADDR_0 0x64
+#define DDR_REG_BIST_COMP_ADDR_1 0x68
+#define DDR_REG_BIST_MASK_AHB_GE0_1 0x6c
+#define DDR_REG_BIST_COMP_AHB_GE0_1 0x70
+#define DDR_REG_BIST_MASK_AHB_GE1_1 0x74
+#define DDR_REG_BIST_COMP_AHB_GE1_1 0x78
+#define DDR_REG_BIST 0x11c
+#define DDR_REG_BIST_STATUS 0x120
+
+#define DDR_BIST_COMP_CNT_S 1
+#define DDR_BIST_COMP_CNT_M 0xff
+#define DDR_BIST_COMP_CNT(x) \
+ (((x) & DDR_BIST_COMP_CNT_M) << DDR_BIST_COMP_CNT_S)
+#define DDR_BIST_COMP_CNT_MASK \
+ (DDR_BIST_COMP_CNT_M << DDR_BIST_COMP_CNT_S)
+#define DDR_BIST_TEST_START BIT(0)
+#define DDR_BIST_STATUS_DONE BIT(0)
+
+/* 4 Row Address Bits, 4 Column Address Bits, 2 BA bits */
+#define DDR_BIST_MASK_ADDR_VAL 0xfa5de83f
+
+#define DDR_TAP_MAGIC_VAL 0xaa55aa55
+#define DDR_TAP_MAX_VAL 0x40
+
+void ddr_init(void)
+{
+ void __iomem *regs;
+ u32 val;
+
+ regs = map_physmem(AR71XX_DDR_CTRL_BASE, AR71XX_DDR_CTRL_SIZE,
+ MAP_NOCACHE);
+ val = get_bootstrap();
+ if (val & QCA953X_BOOTSTRAP_DDR1) {
+ writel(DDR_CTL_CONFIG_VAL, regs + QCA953X_DDR_REG_CTL_CONF);
+ udelay(10);
+
+ /* For 16-bit DDR */
+ writel(0xffff, regs + AR71XX_DDR_REG_RD_CYCLE);
+ udelay(100);
+
+ /* Burst size */
+ writel(DDR_BURST_VAL, regs + QCA953X_DDR_REG_BURST);
+ udelay(100);
+ writel(DDR_BURST2_VAL, regs + QCA953X_DDR_REG_BURST2);
+ udelay(100);
+
+ /* AHB maximum timeout */
+ writel(0xfffff, regs + QCA953X_DDR_REG_TIMEOUT_MAX);
+ udelay(100);
+
+ /* DRAM timing */
+ writel(DDR1_CONF_REG_VAL, regs + AR71XX_DDR_REG_CONFIG);
+ udelay(100);
+ writel(DDR1_CONF2_REG_VAL, regs + AR71XX_DDR_REG_CONFIG2);
+ udelay(100);
+ writel(DDR1_CONF3_REG_VAL, regs + QCA953X_DDR_REG_CONFIG3);
+ udelay(100);
+
+ /* Precharge All */
+ writel(DDR_CTRL_PRECHARGE, regs + AR71XX_DDR_REG_CONTROL);
+ udelay(100);
+
+ /* ODT disable, Full strength, Enable DLL */
+ writel(DDR1_EXT_MODE_VAL, regs + AR71XX_DDR_REG_EMR);
+ udelay(100);
+
+ /* Update Extended Mode Register Set (EMRS) */
+ writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL);
+ udelay(100);
+
+ /* Reset DLL, CAS Latency 3, Burst Length 8 */
+ writel(DDR1_MODE_DLL_VAL, regs + AR71XX_DDR_REG_MODE);
+ udelay(100);
+
+ /* Update Mode Register Set (MRS) */
+ writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL);
+ udelay(100);
+
+ /* Precharge All */
+ writel(DDR_CTRL_PRECHARGE, regs + AR71XX_DDR_REG_CONTROL);
+ udelay(100);
+
+ /* Auto Refresh */
+ writel(DDR_CTRL_AUTO_REFRESH, regs + AR71XX_DDR_REG_CONTROL);
+ udelay(100);
+ writel(DDR_CTRL_AUTO_REFRESH, regs + AR71XX_DDR_REG_CONTROL);
+ udelay(100);
+
+ /* Normal DLL, CAS Latency 3, Burst Length 8 */
+ writel(DDR1_MODE_VAL, regs + AR71XX_DDR_REG_MODE);
+ udelay(100);
+
+ /* Update Mode Register Set (MRS) */
+ writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL);
+ udelay(100);
+
+ /* Refresh time control */
+ writel(DDR_REFRESH_VAL, regs + AR71XX_DDR_REG_REFRESH);
+ udelay(100);
+
+ /* DQS 0 Tap Control */
+ writel(DDR1_TAP_VAL, regs + AR71XX_DDR_REG_TAP_CTRL0);
+
+ /* DQS 1 Tap Control */
+ writel(DDR1_TAP_VAL, regs + AR71XX_DDR_REG_TAP_CTRL1);
+ } else {
+ writel(DDR_CTRL_UPD_EMR2S, regs + AR71XX_DDR_REG_CONTROL);
+ udelay(10);
+ writel(DDR_CTRL_UPD_EMR3S, regs + AR71XX_DDR_REG_CONTROL);
+ udelay(10);
+ writel(DDR_CTL_CONFIG_VAL | DDR_CTL_PAD_DDR2_SEL,
+ regs + QCA953X_DDR_REG_CTL_CONF);
+ udelay(10);
+
+ /* For 16-bit DDR */
+ writel(0xffff, regs + AR71XX_DDR_REG_RD_CYCLE);
+ udelay(100);
+
+ /* Burst size */
+ writel(DDR_BURST_VAL, regs + QCA953X_DDR_REG_BURST);
+ udelay(100);
+ writel(DDR_BURST2_VAL, regs + QCA953X_DDR_REG_BURST2);
+ udelay(100);
+
+ /* AHB maximum timeout */
+ writel(0xfffff, regs + QCA953X_DDR_REG_TIMEOUT_MAX);
+ udelay(100);
+
+ /* DRAM timing */
+ writel(DDR2_CONF_REG_VAL, regs + AR71XX_DDR_REG_CONFIG);
+ udelay(100);
+ writel(DDR2_CONF2_REG_VAL, regs + AR71XX_DDR_REG_CONFIG2);
+ udelay(100);
+ writel(DDR2_CONF3_REG_VAL, regs + QCA953X_DDR_REG_CONFIG3);
+ udelay(100);
+
+ /* Enable DDR2 */
+ writel(DDR2_CONF_VAL, regs + QCA953X_DDR_REG_DDR2_CONFIG);
+ udelay(100);
+
+ /* Precharge All */
+ writel(DDR_CTRL_PRECHARGE, regs + AR71XX_DDR_REG_CONTROL);
+ udelay(100);
+
+ /* Update Extended Mode Register 2 Set (EMR2S) */
+ writel(DDR_CTRL_UPD_EMR2S, regs + AR71XX_DDR_REG_CONTROL);
+ udelay(100);
+
+ /* Update Extended Mode Register 3 Set (EMR3S) */
+ writel(DDR_CTRL_UPD_EMR3S, regs + AR71XX_DDR_REG_CONTROL);
+ udelay(100);
+
+ /* 150 ohm, Reduced strength, Enable DLL */
+ writel(DDR2_EXT_MODE_VAL, regs + AR71XX_DDR_REG_EMR);
+ udelay(100);
+
+ /* Update Extended Mode Register Set (EMRS) */
+ writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL);
+ udelay(100);
+
+ /* Reset DLL, CAS Latency 4, Burst Length 8 */
+ writel(DDR2_MODE_DLL_VAL, regs + AR71XX_DDR_REG_MODE);
+ udelay(100);
+
+ /* Update Mode Register Set (MRS) */
+ writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL);
+ udelay(100);
+
+ /* Precharge All */
+ writel(DDR_CTRL_PRECHARGE, regs + AR71XX_DDR_REG_CONTROL);
+ udelay(100);
+
+ /* Auto Refresh */
+ writel(DDR_CTRL_AUTO_REFRESH, regs + AR71XX_DDR_REG_CONTROL);
+ udelay(100);
+ writel(DDR_CTRL_AUTO_REFRESH, regs + AR71XX_DDR_REG_CONTROL);
+ udelay(100);
+
+ /* Normal DLL, CAS Latency 4, Burst Length 8 */
+ writel(DDR2_MODE_VAL, regs + AR71XX_DDR_REG_MODE);
+ udelay(100);
+
+ /* Mode Register Set (MRS) */
+ writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL);
+ udelay(100);
+
+ /* Enable OCD, Enable DLL, Reduced Drive Strength */
+ writel(DDR2_EXT_MODE_OCD_VAL, regs + AR71XX_DDR_REG_EMR);
+ udelay(100);
+
+ /* Update Extended Mode Register Set (EMRS) */
+ writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL);
+ udelay(100);
+
+ /* OCD diable, Enable DLL, Reduced Drive Strength */
+ writel(DDR2_EXT_MODE_VAL, regs + AR71XX_DDR_REG_EMR);
+ udelay(100);
+
+ /* Update Extended Mode Register Set (EMRS) */
+ writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL);
+ udelay(100);
+
+ /* Refresh time control */
+ writel(DDR_REFRESH_VAL, regs + AR71XX_DDR_REG_REFRESH);
+ udelay(100);
+
+ /* DQS 0 Tap Control */
+ writel(DDR2_TAP_VAL, regs + AR71XX_DDR_REG_TAP_CTRL0);
+
+ /* DQS 1 Tap Control */
+ writel(DDR2_TAP_VAL, regs + AR71XX_DDR_REG_TAP_CTRL1);
+ }
+}
+
+void ddr_tap_tuning(void)
+{
+ void __iomem *regs;
+ u32 val, pass, tap, cnt, tap_val, last, first;
+
+ regs = map_physmem(AR71XX_DDR_CTRL_BASE, AR71XX_DDR_CTRL_SIZE,
+ MAP_NOCACHE);
+
+ tap_val = readl(regs + AR71XX_DDR_REG_TAP_CTRL0);
+ first = DDR_TAP_MAGIC_VAL;
+ last = 0;
+ cnt = 0;
+ tap = 0;
+
+ do {
+ writel(tap, regs + AR71XX_DDR_REG_TAP_CTRL0);
+ writel(tap, regs + AR71XX_DDR_REG_TAP_CTRL1);
+
+ writel(DDR_BIST_COMP_CNT(8), regs + DDR_REG_BIST_COMP_ADDR_1);
+ writel(DDR_BIST_MASK_ADDR_VAL, regs + DDR_REG_BIST_MASK_ADDR_0);
+ writel(0xffff, regs + DDR_REG_BIST_COMP_AHB_GE0_1);
+ writel(0xffff, regs + DDR_REG_BIST_COMP_AHB_GE1_0);
+ writel(0xffff, regs + DDR_REG_BIST_COMP_AHB_GE1_1);
+ writel(0xffff, regs + DDR_REG_BIST_MASK_AHB_GE0_0);
+ writel(0xffff, regs + DDR_REG_BIST_MASK_AHB_GE0_1);
+ writel(0xffff, regs + DDR_REG_BIST_MASK_AHB_GE1_0);
+ writel(0xffff, regs + DDR_REG_BIST_MASK_AHB_GE1_1);
+ writel(0xffff, regs + DDR_REG_BIST_COMP_AHB_GE0_0);
+
+ /* Start BIST test */
+ writel(DDR_BIST_TEST_START, regs + DDR_REG_BIST);
+
+ do {
+ val = readl(regs + DDR_REG_BIST_STATUS);
+ } while (!(val & DDR_BIST_STATUS_DONE));
+
+ /* Stop BIST test */
+ writel(0, regs + DDR_REG_BIST);
+
+ pass = val & DDR_BIST_COMP_CNT_MASK;
+ pass ^= DDR_BIST_COMP_CNT(8);
+ if (!pass) {
+ if (first != DDR_TAP_MAGIC_VAL) {
+ last = tap;
+ } else {
+ first = tap;
+ last = tap;
+ }
+ cnt++;
+ }
+ tap++;
+ } while (tap < DDR_TAP_MAX_VAL);
+
+ if (cnt) {
+ tap_val = (first + last) / 2;
+ tap_val %= DDR_TAP_MAX_VAL;
+ }
+
+ writel(tap_val, regs + AR71XX_DDR_REG_TAP_CTRL0);
+ writel(tap_val, regs + AR71XX_DDR_REG_TAP_CTRL1);
+}
--- /dev/null
+/*
+ * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
+ * Based on Atheros LSDK/QSDK
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <asm/asm.h>
+#include <asm/regdef.h>
+#include <asm/mipsregs.h>
+#include <asm/addrspace.h>
+#include <mach/ar71xx_regs.h>
+
+#define MK_PLL_CONF(divint, refdiv, range, outdiv) \
+ (((0x3F & divint) << 10) | \
+ ((0x1F & refdiv) << 16) | \
+ ((0x1 & range) << 21) | \
+ ((0x7 & outdiv) << 23) )
+
+#define MK_CLK_CNTL(cpudiv, ddrdiv, ahbdiv) \
+ (((0x3 & (cpudiv - 1)) << 5) | \
+ ((0x3 & (ddrdiv - 1)) << 10) | \
+ ((0x3 & (ahbdiv - 1)) << 15) )
+
+#define SET_FIELD(name, v) (((v) & QCA953X_##name##_MASK) << \
+ QCA953X_##name##_SHIFT)
+
+#define DPLL2_KI(v) SET_FIELD(SRIF_DPLL2_KI, v)
+#define DPLL2_KD(v) SET_FIELD(SRIF_DPLL2_KD, v)
+#define DPLL2_PWD QCA953X_SRIF_DPLL2_PWD
+#define MK_DPLL2(ki, kd) (DPLL2_KI(ki) | DPLL2_KD(kd) | DPLL2_PWD)
+
+#define PLL_CPU_NFRAC(v) SET_FIELD(PLL_CPU_CONFIG_NFRAC, v)
+#define PLL_CPU_NINT(v) SET_FIELD(PLL_CPU_CONFIG_NINT, v)
+#define PLL_CPU_REFDIV(v) SET_FIELD(PLL_CPU_CONFIG_REFDIV, v)
+#define PLL_CPU_OUTDIV(v) SET_FIELD(PLL_CPU_CONFIG_OUTDIV, v)
+#define MK_PLL_CPU_CONF(frac, nint, ref, outdiv) \
+ (PLL_CPU_NFRAC(frac) | \
+ PLL_CPU_NINT(nint) | \
+ PLL_CPU_REFDIV(ref) | \
+ PLL_CPU_OUTDIV(outdiv))
+
+#define PLL_DDR_NFRAC(v) SET_FIELD(PLL_DDR_CONFIG_NFRAC, v)
+#define PLL_DDR_NINT(v) SET_FIELD(PLL_DDR_CONFIG_NINT, v)
+#define PLL_DDR_REFDIV(v) SET_FIELD(PLL_DDR_CONFIG_REFDIV, v)
+#define PLL_DDR_OUTDIV(v) SET_FIELD(PLL_DDR_CONFIG_OUTDIV, v)
+#define MK_PLL_DDR_CONF(frac, nint, ref, outdiv) \
+ (PLL_DDR_NFRAC(frac) | \
+ PLL_DDR_REFDIV(ref) | \
+ PLL_DDR_NINT(nint) | \
+ PLL_DDR_OUTDIV(outdiv) | \
+ QCA953X_PLL_CONFIG_PWD)
+
+#define PLL_CPU_CONF_VAL MK_PLL_CPU_CONF(0, 26, 1, 0)
+#define PLL_DDR_CONF_VAL MK_PLL_DDR_CONF(0, 15, 1, 0)
+
+#define PLL_CLK_CTRL_PLL_BYPASS (QCA953X_PLL_CLK_CTRL_CPU_PLL_BYPASS | \
+ QCA953X_PLL_CLK_CTRL_DDR_PLL_BYPASS | \
+ QCA953X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
+
+#define PLL_CLK_CTRL_CPU_DIV(v) SET_FIELD(PLL_CLK_CTRL_CPU_POST_DIV, v)
+#define PLL_CLK_CTRL_DDR_DIV(v) SET_FIELD(PLL_CLK_CTRL_DDR_POST_DIV, v)
+#define PLL_CLK_CTRL_AHB_DIV(v) SET_FIELD(PLL_CLK_CTRL_AHB_POST_DIV, v)
+#define MK_PLL_CLK_CTRL(cpu, ddr, ahb) \
+ (PLL_CLK_CTRL_CPU_DIV(cpu) | \
+ PLL_CLK_CTRL_DDR_DIV(ddr) | \
+ PLL_CLK_CTRL_AHB_DIV(ahb))
+#define PLL_CLK_CTRL_VAL (MK_PLL_CLK_CTRL(0, 0, 2) | \
+ PLL_CLK_CTRL_PLL_BYPASS | \
+ QCA953X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL | \
+ QCA953X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL)
+
+#define PLL_DDR_DIT_FRAC_MAX(v) SET_FIELD(PLL_DDR_DIT_FRAC_MAX, v)
+#define PLL_DDR_DIT_FRAC_MIN(v) SET_FIELD(PLL_DDR_DIT_FRAC_MIN, v)
+#define PLL_DDR_DIT_FRAC_STEP(v) SET_FIELD(PLL_DDR_DIT_FRAC_STEP, v)
+#define PLL_DDR_DIT_UPD_CNT(v) SET_FIELD(PLL_DDR_DIT_UPD_CNT, v)
+#define PLL_CPU_DIT_FRAC_MAX(v) SET_FIELD(PLL_CPU_DIT_FRAC_MAX, v)
+#define PLL_CPU_DIT_FRAC_MIN(v) SET_FIELD(PLL_CPU_DIT_FRAC_MIN, v)
+#define PLL_CPU_DIT_FRAC_STEP(v) SET_FIELD(PLL_CPU_DIT_FRAC_STEP, v)
+#define PLL_CPU_DIT_UPD_CNT(v) SET_FIELD(PLL_CPU_DIT_UPD_CNT, v)
+#define MK_PLL_DDR_DIT_FRAC(max, min, step, cnt) \
+ (QCA953X_PLL_DIT_FRAC_EN | \
+ PLL_DDR_DIT_FRAC_MAX(max) | \
+ PLL_DDR_DIT_FRAC_MIN(min) | \
+ PLL_DDR_DIT_FRAC_STEP(step) | \
+ PLL_DDR_DIT_UPD_CNT(cnt))
+#define MK_PLL_CPU_DIT_FRAC(max, min, step, cnt) \
+ (QCA953X_PLL_DIT_FRAC_EN | \
+ PLL_CPU_DIT_FRAC_MAX(max) | \
+ PLL_CPU_DIT_FRAC_MIN(min) | \
+ PLL_CPU_DIT_FRAC_STEP(step) | \
+ PLL_CPU_DIT_UPD_CNT(cnt))
+#define PLL_CPU_DIT_FRAC_VAL MK_PLL_CPU_DIT_FRAC(63, 0, 1, 15)
+#define PLL_DDR_DIT_FRAC_VAL MK_PLL_DDR_DIT_FRAC(763, 635, 1, 15)
+
+ .text
+ .set noreorder
+
+LEAF(lowlevel_init)
+ /* RTC Reset */
+ li t0, CKSEG1ADDR(AR71XX_RESET_BASE)
+ lw t1, QCA953X_RESET_REG_RESET_MODULE(t0)
+ li t2, 0x08000000
+ or t1, t1, t2
+ sw t1, QCA953X_RESET_REG_RESET_MODULE(t0)
+ nop
+ lw t1, QCA953X_RESET_REG_RESET_MODULE(t0)
+ li t2, 0xf7ffffff
+ and t1, t1, t2
+ sw t1, QCA953X_RESET_REG_RESET_MODULE(t0)
+ nop
+
+ /* RTC Force Wake */
+ li t0, CKSEG1ADDR(QCA953X_RTC_BASE)
+ li t1, 0x01
+ sw t1, QCA953X_RTC_REG_SYNC_RESET(t0)
+ nop
+ nop
+
+ /* Wait for RTC in on state */
+1:
+ lw t1, QCA953X_RTC_REG_SYNC_STATUS(t0)
+ andi t1, t1, 0x02
+ beqz t1, 1b
+ nop
+
+ li t0, CKSEG1ADDR(QCA953X_SRIF_BASE)
+ li t1, MK_DPLL2(2, 16)
+ sw t1, QCA953X_SRIF_BB_DPLL2_REG(t0)
+ sw t1, QCA953X_SRIF_PCIE_DPLL2_REG(t0)
+ sw t1, QCA953X_SRIF_DDR_DPLL2_REG(t0)
+ sw t1, QCA953X_SRIF_CPU_DPLL2_REG(t0)
+
+ li t0, CKSEG1ADDR(AR71XX_PLL_BASE)
+ lw t1, QCA953X_PLL_CLK_CTRL_REG(t0)
+ ori t1, PLL_CLK_CTRL_PLL_BYPASS
+ sw t1, QCA953X_PLL_CLK_CTRL_REG(t0)
+ nop
+
+ li t1, PLL_CPU_CONF_VAL
+ sw t1, QCA953X_PLL_CPU_CONFIG_REG(t0)
+ nop
+
+ li t1, PLL_DDR_CONF_VAL
+ sw t1, QCA953X_PLL_DDR_CONFIG_REG(t0)
+ nop
+
+ li t1, PLL_CLK_CTRL_VAL
+ sw t1, QCA953X_PLL_CLK_CTRL_REG(t0)
+ nop
+
+ lw t1, QCA953X_PLL_CPU_CONFIG_REG(t0)
+ li t2, ~QCA953X_PLL_CONFIG_PWD
+ and t1, t1, t2
+ sw t1, QCA953X_PLL_CPU_CONFIG_REG(t0)
+ nop
+
+ lw t1, QCA953X_PLL_DDR_CONFIG_REG(t0)
+ li t2, ~QCA953X_PLL_CONFIG_PWD
+ and t1, t1, t2
+ sw t1, QCA953X_PLL_DDR_CONFIG_REG(t0)
+ nop
+
+ lw t1, QCA953X_PLL_CLK_CTRL_REG(t0)
+ li t2, ~PLL_CLK_CTRL_PLL_BYPASS
+ and t1, t1, t2
+ sw t1, QCA953X_PLL_CLK_CTRL_REG(t0)
+ nop
+
+ li t1, PLL_DDR_DIT_FRAC_VAL
+ sw t1, QCA953X_PLL_DDR_DIT_FRAC_REG(t0)
+ nop
+
+ li t1, PLL_CPU_DIT_FRAC_VAL
+ sw t1, QCA953X_PLL_CPU_DIT_FRAC_REG(t0)
+ nop
+
+ li t0, CKSEG1ADDR(AR71XX_RESET_BASE)
+ lui t1, 0x03fc
+ sw t1, 0xb4(t0)
+
+ nop
+ jr ra
+ nop
+ END(lowlevel_init)
--- /dev/null
+/*
+ * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+#include <asm/addrspace.h>
+#include <asm/types.h>
+#include <mach/ath79.h>
+#include <mach/ar71xx_regs.h>
+
+void _machine_restart(void)
+{
+ void __iomem *base;
+ u32 reg = 0;
+
+ base = map_physmem(AR71XX_RESET_BASE, AR71XX_RESET_SIZE,
+ MAP_NOCACHE);
+ if (soc_is_ar71xx())
+ reg = AR71XX_RESET_REG_RESET_MODULE;
+ else if (soc_is_ar724x())
+ reg = AR724X_RESET_REG_RESET_MODULE;
+ else if (soc_is_ar913x())
+ reg = AR913X_RESET_REG_RESET_MODULE;
+ else if (soc_is_ar933x())
+ reg = AR933X_RESET_REG_RESET_MODULE;
+ else if (soc_is_ar934x())
+ reg = AR934X_RESET_REG_RESET_MODULE;
+ else if (soc_is_qca953x())
+ reg = QCA953X_RESET_REG_RESET_MODULE;
+ else if (soc_is_qca955x())
+ reg = QCA955X_RESET_REG_RESET_MODULE;
+ else if (soc_is_qca956x())
+ reg = QCA956X_RESET_REG_RESET_MODULE;
+ else
+ puts("Reset register not defined for this SOC\n");
+
+ if (reg)
+ setbits_be32(base + reg, AR71XX_RESET_FULL_CHIP);
+
+ while (1)
+ /* NOP */;
+}
+
+u32 get_bootstrap(void)
+{
+ void __iomem *base;
+ u32 reg = 0;
+
+ base = map_physmem(AR71XX_RESET_BASE, AR71XX_RESET_SIZE,
+ MAP_NOCACHE);
+ if (soc_is_ar933x())
+ reg = AR933X_RESET_REG_BOOTSTRAP;
+ else if (soc_is_ar934x())
+ reg = AR934X_RESET_REG_BOOTSTRAP;
+ else if (soc_is_qca953x())
+ reg = QCA953X_RESET_REG_BOOTSTRAP;
+ else if (soc_is_qca955x())
+ reg = QCA955X_RESET_REG_BOOTSTRAP;
+ else if (soc_is_qca956x())
+ reg = QCA956X_RESET_REG_BOOTSTRAP;
+ else
+ puts("Bootstrap register not defined for this SOC\n");
+
+ if (reg)
+ return readl(base + reg);
+
+ return 0;
+}
+
+static int eth_init_ar933x(void)
+{
+ void __iomem *rregs = map_physmem(AR71XX_RESET_BASE, AR71XX_RESET_SIZE,
+ MAP_NOCACHE);
+ void __iomem *pregs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE,
+ MAP_NOCACHE);
+ void __iomem *gregs = map_physmem(AR933X_GMAC_BASE, AR933X_GMAC_SIZE,
+ MAP_NOCACHE);
+ const u32 mask = AR933X_RESET_GE0_MAC | AR933X_RESET_GE0_MDIO |
+ AR933X_RESET_GE1_MAC | AR933X_RESET_GE1_MDIO |
+ AR933X_RESET_ETH_SWITCH;
+
+ /* Clear MDIO slave EN bit. */
+ clrbits_be32(rregs + AR933X_RESET_REG_BOOTSTRAP, BIT(17));
+ mdelay(10);
+
+ /* Get Atheros S26 PHY out of reset. */
+ clrsetbits_be32(pregs + AR934X_PLL_SWITCH_CLOCK_CONTROL_REG,
+ 0x1f, 0x10);
+ mdelay(10);
+
+ setbits_be32(rregs + AR933X_RESET_REG_RESET_MODULE, mask);
+ mdelay(10);
+ clrbits_be32(rregs + AR933X_RESET_REG_RESET_MODULE, mask);
+ mdelay(10);
+
+ /* Configure AR93xx GMAC register. */
+ clrsetbits_be32(gregs + AR933X_GMAC_REG_ETH_CFG,
+ AR933X_ETH_CFG_MII_GE0_MASTER |
+ AR933X_ETH_CFG_MII_GE0_SLAVE,
+ AR933X_ETH_CFG_MII_GE0_SLAVE);
+ return 0;
+}
+
+static int eth_init_ar934x(void)
+{
+ void __iomem *rregs = map_physmem(AR71XX_RESET_BASE, AR71XX_RESET_SIZE,
+ MAP_NOCACHE);
+ void __iomem *pregs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE,
+ MAP_NOCACHE);
+ void __iomem *gregs = map_physmem(AR934X_GMAC_BASE, AR934X_GMAC_SIZE,
+ MAP_NOCACHE);
+ const u32 mask = AR934X_RESET_GE0_MAC | AR934X_RESET_GE0_MDIO |
+ AR934X_RESET_GE1_MAC | AR934X_RESET_GE1_MDIO |
+ AR934X_RESET_ETH_SWITCH_ANALOG;
+ u32 reg;
+
+ reg = readl(rregs + AR934X_RESET_REG_BOOTSTRAP);
+ if (reg & AR934X_BOOTSTRAP_REF_CLK_40)
+ writel(0x570, pregs + AR934X_PLL_SWITCH_CLOCK_CONTROL_REG);
+ else
+ writel(0x271, pregs + AR934X_PLL_SWITCH_CLOCK_CONTROL_REG);
+ writel(BIT(26) | BIT(25), pregs + AR934X_PLL_ETH_XMII_CONTROL_REG);
+
+ setbits_be32(rregs + AR934X_RESET_REG_RESET_MODULE, mask);
+ mdelay(1);
+ clrbits_be32(rregs + AR934X_RESET_REG_RESET_MODULE, mask);
+ mdelay(1);
+
+ /* Configure AR934x GMAC register. */
+ writel(AR934X_ETH_CFG_RGMII_GMAC0, gregs + AR934X_GMAC_REG_ETH_CFG);
+ return 0;
+}
+
+int ath79_eth_reset(void)
+{
+ /*
+ * Un-reset ethernet. DM still doesn't have any notion of reset
+ * framework, so we do it by hand here.
+ */
+ if (soc_is_ar933x())
+ return eth_init_ar933x();
+ if (soc_is_ar934x())
+ return eth_init_ar934x();
+
+ return -EINVAL;
+}
+
+static int usb_reset_ar933x(void __iomem *reset_regs)
+{
+ /* Ungate the USB block */
+ setbits_be32(reset_regs + AR933X_RESET_REG_RESET_MODULE,
+ AR933X_RESET_USBSUS_OVERRIDE);
+ mdelay(1);
+ clrbits_be32(reset_regs + AR933X_RESET_REG_RESET_MODULE,
+ AR933X_RESET_USB_HOST);
+ mdelay(1);
+ clrbits_be32(reset_regs + AR933X_RESET_REG_RESET_MODULE,
+ AR933X_RESET_USB_PHY);
+ mdelay(1);
+
+ return 0;
+}
+
+static int usb_reset_ar934x(void __iomem *reset_regs)
+{
+ /* Ungate the USB block */
+ setbits_be32(reset_regs + AR934X_RESET_REG_RESET_MODULE,
+ AR934X_RESET_USBSUS_OVERRIDE);
+ mdelay(1);
+ clrbits_be32(reset_regs + AR934X_RESET_REG_RESET_MODULE,
+ AR934X_RESET_USB_PHY);
+ mdelay(1);
+ clrbits_be32(reset_regs + AR934X_RESET_REG_RESET_MODULE,
+ AR934X_RESET_USB_PHY_ANALOG);
+ mdelay(1);
+ clrbits_be32(reset_regs + AR934X_RESET_REG_RESET_MODULE,
+ AR934X_RESET_USB_HOST);
+ mdelay(1);
+
+ return 0;
+}
+
+int ath79_usb_reset(void)
+{
+ void __iomem *usbc_regs = map_physmem(AR71XX_USB_CTRL_BASE,
+ AR71XX_USB_CTRL_SIZE,
+ MAP_NOCACHE);
+ void __iomem *reset_regs = map_physmem(AR71XX_RESET_BASE,
+ AR71XX_RESET_SIZE,
+ MAP_NOCACHE);
+ /*
+ * Turn on the Buff and Desc swap bits.
+ * NOTE: This write into an undocumented register in mandatory to
+ * get the USB controller operational in BigEndian mode.
+ */
+ writel(0xf0000, usbc_regs + AR71XX_USB_CTRL_REG_CONFIG);
+
+ if (soc_is_ar933x())
+ return usb_reset_ar933x(reset_regs);
+ if (soc_is_ar934x())
+ return usb_reset_ar934x(reset_regs);
+
+ return -EINVAL;
+}
#ifdef CONFIG_FSL_CAAM
sec_init();
+
+#if defined(CONFIG_PPC_C29X)
+ if ((SVR_SOC_VER(svr) == SVR_C292) ||
+ (SVR_SOC_VER(svr) == SVR_C293))
+ sec_init_idx(1);
+
+ if (SVR_SOC_VER(svr) == SVR_C293)
+ sec_init_idx(2);
+#endif
#endif
#if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001)
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#define CONFIG_SYS_FSL_ERRATUM_A005125
+#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 3
+#define CONFIG_SYS_FSL_SEC_IDX_OFFSET 0x20000
#elif defined(CONFIG_QEMU_E500)
#define CONFIG_MAX_CPUS 1
#define CONFIG_SYS_FSL_DDRC_GEN3
#endif
+#if !defined(CONFIG_PPC_C29X)
+#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
+#endif
+
#endif /* _ASM_MPC85xx_CONFIG_H_ */
#include <asm/types.h>
-typedef struct fsl_i2c {
+typedef struct fsl_i2c_base {
u8 adr; /* I2C slave address */
u8 res0[3];
u8 res6[0xE8];
} fsl_i2c_t;
+#ifdef CONFIG_DM_I2C
+struct fsl_i2c_dev {
+ struct fsl_i2c_base __iomem *base; /* register base */
+ u32 i2c_clk;
+ u32 index;
+ u8 slaveadd;
+ uint speed;
+};
+#endif
+
#endif /* _ASM_I2C_H_ */
/* I2C Registers */
typedef struct ccsr_i2c {
- struct fsl_i2c i2c[1];
- u8 res[4096 - 1 * sizeof(struct fsl_i2c)];
+ struct fsl_i2c_base i2c[1];
+ u8 res[4096 - 1 * sizeof(struct fsl_i2c_base)];
} ccsr_i2c_t;
#if defined(CONFIG_MPC8540) \
/* Daul I2C Registers(0x3000-0x4000) */
typedef struct ccsr_i2c {
- struct fsl_i2c i2c[2];
- u8 res[4096 - 2 * sizeof(struct fsl_i2c)];
+ struct fsl_i2c_base i2c[2];
+ u8 res[4096 - 2 * sizeof(struct fsl_i2c_base)];
} ccsr_i2c_t;
/* DUART Registers(0x4000-0x5000) */
void outw(unsigned int value, unsigned int addr);
void outb(unsigned int value, unsigned int addr);
+static inline void _insw(volatile u16 *port, void *buf, int ns)
+{
+}
+
+static inline void _outsw(volatile u16 *port, const void *buf, int ns)
+{
+}
+
+#define insw(port, buf, ns) _insw((u16 *)port, buf, ns)
+#define outsw(port, buf, ns) _outsw((u16 *)port, buf, ns)
+
+/* For systemace.c */
+#define out16(addr, val)
+#define in16(addr) 0
+
#include <iotrace.h>
#include <asm/types.h>
# architecture-specific options below
+config AHCI
+ default y
+
config SYS_MALLOC_F_LEN
default 0x800
to be used for speeding up boot time on future reboots and/or
power cycles.
+ For platforms that use Intel FSP for the memory initialization,
+ please check FSP output HOB via U-Boot command 'fsp hob' to see
+ if there is FSP_NON_VOLATILE_STORAGE_HOB_GUID (asm/fsp/fsp_hob.h).
+ If such GUID does not exist, MRC cache is not avaiable on such
+ platform (eg: Intel Queensbay), which means selecting this option
+ here does not make any difference.
+
config HAVE_MRC
bool "Add a System Agent binary"
depends on !HAVE_FSP
config GENERATE_ACPI_TABLE
bool "Generate an ACPI (Advanced Configuration and Power Interface) table"
default n
+ select QFW if QEMU
help
The Advanced Configuration and Power Interface (ACPI) specification
provides an open standard for device configuration and management
by the operating system. It defines platform-independent interfaces
for configuration and power management monitoring.
-config QEMU_ACPI_TABLE
- bool "Load ACPI table from QEMU fw_cfg interface"
- depends on GENERATE_ACPI_TABLE && QEMU
- default y
- help
- By default, U-Boot generates its own ACPI tables. This option, if
- enabled, disables U-Boot's version and loads ACPI tables generated
- by QEMU.
-
config GENERATE_SMBIOS_TABLE
bool "Generate an SMBIOS (System Management BIOS) table"
default y
Check http://www.dmtf.org/standards/smbios for details.
+config SMBIOS_MANUFACTURER
+ string "SMBIOS Manufacturer"
+ depends on GENERATE_SMBIOS_TABLE
+ default SYS_VENDOR
+ help
+ The board manufacturer to store in SMBIOS structures.
+ Change this to override the default one (CONFIG_SYS_VENDOR).
+
+config SMBIOS_PRODUCT_NAME
+ string "SMBIOS Product Name"
+ depends on GENERATE_SMBIOS_TABLE
+ default SYS_BOARD
+ help
+ The product name to store in SMBIOS structures.
+ Change this to override the default one (CONFIG_SYS_BOARD).
+
endmenu
config MAX_PIRQ_LINKS
Check http://www.seabios.org/SeaBIOS for details.
+config HIGH_TABLE_SIZE
+ hex "Size of configuration tables which reside in high memory"
+ default 0x10000
+ depends on SEABIOS
+ help
+ SeaBIOS itself resides in E seg and F seg, where U-Boot puts all
+ configuration tables like PIRQ/MP/ACPI. To avoid conflicts, U-Boot
+ puts a copy of configuration tables in high memory region which
+ is reserved on the stack before relocation. The region size is
+ determined by this option.
+
+ Increse it if the default size does not fit the board's needs.
+ This is most likely due to a large ACPI DSDT table is used.
+
source "arch/x86/lib/efi/Kconfig"
endmenu
obj-y += early_uart.o
obj-y += fsp_configs.o
obj-y += valleyview.o
+obj-$(CONFIG_GENERATE_ACPI_TABLE) += acpi.o
--- /dev/null
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/acpi_table.h>
+#include <asm/ioapic.h>
+#include <asm/mpspec.h>
+#include <asm/tables.h>
+#include <asm/arch/iomap.h>
+
+void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs,
+ void *dsdt)
+{
+ struct acpi_table_header *header = &(fadt->header);
+ u16 pmbase = ACPI_BASE_ADDRESS;
+
+ memset((void *)fadt, 0, sizeof(struct acpi_fadt));
+
+ acpi_fill_header(header, "FACP");
+ header->length = sizeof(struct acpi_fadt);
+ header->revision = 4;
+
+ fadt->firmware_ctrl = (u32)facs;
+ fadt->dsdt = (u32)dsdt;
+ fadt->preferred_pm_profile = ACPI_PM_MOBILE;
+ fadt->sci_int = 9;
+ fadt->smi_cmd = 0;
+ fadt->acpi_enable = 0;
+ fadt->acpi_disable = 0;
+ fadt->s4bios_req = 0;
+ fadt->pstate_cnt = 0;
+ fadt->pm1a_evt_blk = pmbase;
+ fadt->pm1b_evt_blk = 0x0;
+ fadt->pm1a_cnt_blk = pmbase + 0x4;
+ fadt->pm1b_cnt_blk = 0x0;
+ fadt->pm2_cnt_blk = pmbase + 0x50;
+ fadt->pm_tmr_blk = pmbase + 0x8;
+ fadt->gpe0_blk = pmbase + 0x20;
+ fadt->gpe1_blk = 0;
+ fadt->pm1_evt_len = 4;
+ fadt->pm1_cnt_len = 2;
+ fadt->pm2_cnt_len = 1;
+ fadt->pm_tmr_len = 4;
+ fadt->gpe0_blk_len = 8;
+ fadt->gpe1_blk_len = 0;
+ fadt->gpe1_base = 0;
+ fadt->cst_cnt = 0;
+ fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED;
+ fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED;
+ fadt->flush_size = 0;
+ fadt->flush_stride = 0;
+ fadt->duty_offset = 1;
+ fadt->duty_width = 0;
+ fadt->day_alrm = 0x0d;
+ fadt->mon_alrm = 0x00;
+ fadt->century = 0x00;
+ fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042;
+ fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
+ ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON |
+ ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_RESET_REGISTER |
+ ACPI_FADT_PLATFORM_CLOCK;
+
+ fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO;
+ fadt->reset_reg.bit_width = 8;
+ fadt->reset_reg.bit_offset = 0;
+ fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
+ fadt->reset_reg.addrl = IO_PORT_RESET;
+ fadt->reset_reg.addrh = 0;
+ fadt->reset_value = SYS_RST | RST_CPU;
+
+ fadt->x_firmware_ctl_l = (u32)facs;
+ fadt->x_firmware_ctl_h = 0;
+ fadt->x_dsdt_l = (u32)dsdt;
+ fadt->x_dsdt_h = 0;
+
+ fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+ fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8;
+ fadt->x_pm1a_evt_blk.bit_offset = 0;
+ fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
+ fadt->x_pm1a_evt_blk.addrl = fadt->pm1a_evt_blk;
+ fadt->x_pm1a_evt_blk.addrh = 0x0;
+
+ fadt->x_pm1b_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+ fadt->x_pm1b_evt_blk.bit_width = 0;
+ fadt->x_pm1b_evt_blk.bit_offset = 0;
+ fadt->x_pm1b_evt_blk.access_size = 0;
+ fadt->x_pm1b_evt_blk.addrl = 0x0;
+ fadt->x_pm1b_evt_blk.addrh = 0x0;
+
+ fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+ fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8;
+ fadt->x_pm1a_cnt_blk.bit_offset = 0;
+ fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS;
+ fadt->x_pm1a_cnt_blk.addrl = fadt->pm1a_cnt_blk;
+ fadt->x_pm1a_cnt_blk.addrh = 0x0;
+
+ fadt->x_pm1b_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+ fadt->x_pm1b_cnt_blk.bit_width = 0;
+ fadt->x_pm1b_cnt_blk.bit_offset = 0;
+ fadt->x_pm1b_cnt_blk.access_size = 0;
+ fadt->x_pm1b_cnt_blk.addrl = 0x0;
+ fadt->x_pm1b_cnt_blk.addrh = 0x0;
+
+ fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+ fadt->x_pm2_cnt_blk.bit_width = fadt->pm2_cnt_len * 8;
+ fadt->x_pm2_cnt_blk.bit_offset = 0;
+ fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
+ fadt->x_pm2_cnt_blk.addrl = fadt->pm2_cnt_blk;
+ fadt->x_pm2_cnt_blk.addrh = 0x0;
+
+ fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+ fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8;
+ fadt->x_pm_tmr_blk.bit_offset = 0;
+ fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
+ fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk;
+ fadt->x_pm_tmr_blk.addrh = 0x0;
+
+ fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+ fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8;
+ fadt->x_gpe0_blk.bit_offset = 0;
+ fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
+ fadt->x_gpe0_blk.addrl = fadt->gpe0_blk;
+ fadt->x_gpe0_blk.addrh = 0x0;
+
+ fadt->x_gpe1_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+ fadt->x_gpe1_blk.bit_width = 0;
+ fadt->x_gpe1_blk.bit_offset = 0;
+ fadt->x_gpe1_blk.access_size = 0;
+ fadt->x_gpe1_blk.addrl = 0x0;
+ fadt->x_gpe1_blk.addrh = 0x0;
+
+ header->checksum = table_compute_checksum(fadt, header->length);
+}
+
+static int acpi_create_madt_irq_overrides(u32 current)
+{
+ struct acpi_madt_irqoverride *irqovr;
+ u16 sci_flags = MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH;
+ int length = 0;
+
+ irqovr = (void *)current;
+ length += acpi_create_madt_irqoverride(irqovr, 0, 0, 2, 0);
+
+ irqovr = (void *)(current + length);
+ length += acpi_create_madt_irqoverride(irqovr, 0, 9, 9, sci_flags);
+
+ return length;
+}
+
+u32 acpi_fill_madt(u32 current)
+{
+ current += acpi_create_madt_lapics(current);
+
+ current += acpi_create_madt_ioapic((struct acpi_madt_ioapic *)current,
+ 2, IO_APIC_ADDR, 0);
+
+ current += acpi_create_madt_irq_overrides(current);
+
+ return current;
+}
return 0;
}
-int reserve_arch(void)
-{
-#ifdef CONFIG_ENABLE_MRC_CACHE
- return mrccache_reserve();
-#else
- return 0;
-#endif
-}
#endif
void reset_cpu(ulong addr)
{
u32 reg32;
- io_apic_set_id(0x02);
+ /* Make sure this is a unique ID within system */
+ io_apic_set_id(0x04);
/* affirm full set of redirection table entries ("write once") */
reg32 = io_apic_read(0x01);
U_BOOT_DRIVER(ahci_broadwell_drv) = {
.name = "ahci_broadwell",
- .id = UCLASS_DISK,
+ .id = UCLASS_AHCI,
.of_match = broadwell_ahci_ids,
.ofdata_to_platdata = broadwell_sata_ofdata_to_platdata,
.probe = broadwell_sata_probe,
return 0;
}
-int reserve_arch(void)
-{
- return mrccache_reserve();
-}
-
int dram_init(void)
{
struct pei_data _pei_data __aligned(8);
return default_print_cpuinfo();
}
-int last_stage_init(void)
-{
- if (gd->flags & GD_FLG_COLD_BOOT)
- timestamp_add_to_bootstage();
-
- return 0;
-}
-
-void board_final_cleanup(void)
+static void board_final_cleanup(void)
{
/*
* Un-cache the ROM so the kernel has one
}
}
+int last_stage_init(void)
+{
+ if (gd->flags & GD_FLG_COLD_BOOT)
+ timestamp_add_to_bootstage();
+
+ board_final_cleanup();
+
+ return 0;
+}
+
int misc_init_r(void)
{
return 0;
#include <errno.h>
#include <malloc.h>
#include <asm/control_regs.h>
+#include <asm/coreboot_tables.h>
#include <asm/cpu.h>
#include <asm/lapic.h>
#include <asm/microcode.h>
#include <asm/mp.h>
+#include <asm/mrccache.h>
#include <asm/msr.h>
#include <asm/mtrr.h>
#include <asm/post.h>
}
#ifndef CONFIG_SYS_COREBOOT
+/*
+ * Implement a weak default function for boards that optionally
+ * need to clean up the system before jumping to the kernel.
+ */
+__weak void board_final_cleanup(void)
+{
+}
+
int last_stage_init(void)
{
write_tables();
+ board_final_cleanup();
+
return 0;
}
#endif
return 0;
}
+
+#ifndef CONFIG_EFI_STUB
+int reserve_arch(void)
+{
+#ifdef CONFIG_ENABLE_MRC_CACHE
+ mrccache_reserve();
+#endif
+
+#ifdef CONFIG_SEABIOS
+ high_table_reserve();
+#endif
+
+ return 0;
+}
+#endif
return -ENODEV;
/* Cause the SATA device to do its early init */
- uclass_first_device(UCLASS_DISK, &dev);
+ uclass_first_device(UCLASS_AHCI, &dev);
return 0;
}
#include <dm.h>
#include <asm/cache.h>
#include <asm/control_regs.h>
+#include <asm/i8259.h>
#include <asm/interrupt.h>
#include <asm/io.h>
-#include <asm/processor-flags.h>
-#include <linux/compiler.h>
+#include <asm/lapic.h>
#include <asm/msr.h>
+#include <asm/processor-flags.h>
#include <asm/processor.h>
#include <asm/u-boot-x86.h>
-#include <asm/i8259.h>
DECLARE_GLOBAL_DATA_PTR;
i8259_init();
#endif
+ lapic_setup();
+
/* Initialize core interrupt and exception functionality of CPU */
cpu_init_interrupts();
#include <asm/irq.h>
#include <asm/pci.h>
#include <asm/pirq_routing.h>
+#include <asm/tables.h>
DECLARE_GLOBAL_DATA_PTR;
priv->irq_mask = fdtdec_get_int(blob, node,
"intel,pirq-mask", PIRQ_BITMAP);
+ if (IS_ENABLED(CONFIG_GENERATE_ACPI_TABLE)) {
+ /* Reserve IRQ9 for SCI */
+ priv->irq_mask &= ~(1 << 9);
+ }
+
if (priv->config == PIRQ_VIA_IBASE) {
int ibase_off;
priv->ibase &= ~0xf;
}
+ priv->actl_8bit = fdtdec_get_bool(blob, node, "intel,actl-8bit");
+ priv->actl_addr = fdtdec_get_int(blob, node, "intel,actl-addr", 0);
+
cell = fdt_getprop(blob, node, "intel,pirq-routing", &len);
if (!cell || len % sizeof(struct pirq_routing))
return -EINVAL;
rt->size = irq_entries * sizeof(struct irq_info) + 32;
+ /* Fix up the table checksum */
+ rt->checksum = table_compute_checksum(rt, rt->size);
+
pirq_routing_table = rt;
return 0;
}
+static void irq_enable_sci(struct udevice *dev)
+{
+ struct irq_router *priv = dev_get_priv(dev);
+
+ if (priv->actl_8bit) {
+ /* Bit7 must be turned on to enable ACPI */
+ dm_pci_write_config8(dev->parent, priv->actl_addr, 0x80);
+ } else {
+ /* Write 0 to enable SCI on IRQ9 */
+ if (priv->config == PIRQ_VIA_PCI)
+ dm_pci_write_config32(dev->parent, priv->actl_addr, 0);
+ else
+ writel(0, priv->ibase + priv->actl_addr);
+ }
+}
+
int irq_router_common_init(struct udevice *dev)
{
int ret;
pirq_route_irqs(dev, pirq_routing_table->slots,
get_irq_slot_count(pirq_routing_table));
+ if (IS_ENABLED(CONFIG_GENERATE_ACPI_TABLE))
+ irq_enable_sci(dev);
+
return 0;
}
return 0;
/* Cause the SATA device to do its init */
- uclass_first_device(UCLASS_DISK, &dev);
+ uclass_first_device(UCLASS_AHCI, &dev);
ret = syscon_get_by_driver_data(X86_SYSCON_GMA, &gma_dev);
if (ret)
#include <fdtdec.h>
#include <rtc.h>
#include <pci.h>
-#include <asm/acpi.h>
#include <asm/intel_regs.h>
#include <asm/interrupt.h>
#include <asm/io.h>
#include <dm.h>
#include <fdtdec.h>
#include <malloc.h>
-#include <asm/acpi.h>
#include <asm/cpu.h>
#include <asm/cpu_x86.h>
-#include <asm/lapic.h>
#include <asm/msr.h>
#include <asm/msr-index.h>
#include <asm/mtrr.h>
/* Enable the local cpu apics */
enable_lapic_tpr();
- lapic_setup();
/* Enable virtualization if enabled in CMOS */
enable_vmx();
#include <common.h>
#include <dm.h>
#include <asm/msr.h>
-#include <asm/acpi.h>
#include <asm/cpu.h>
#include <asm/intel_regs.h>
#include <asm/io.h>
U_BOOT_DRIVER(ahci_ivybridge_drv) = {
.name = "ahci_ivybridge",
- .id = UCLASS_DISK,
+ .id = UCLASS_AHCI,
.of_match = bd82x6x_ahci_ids,
.probe = bd82x6x_sata_probe,
};
return false;
}
-int reserve_arch(void)
-{
- return mrccache_reserve();
-}
-
static int copy_spd(struct udevice *dev, struct pei_data *peid)
{
const void *data;
void enable_lapic(void)
{
- msr_t msr;
-
- msr = msr_read(MSR_IA32_APICBASE);
- msr.hi &= 0xffffff00;
- msr.lo |= MSR_IA32_APICBASE_ENABLE;
- msr.lo &= ~MSR_IA32_APICBASE_BASE;
- msr.lo |= LAPIC_DEFAULT_BASE;
- msr_write(MSR_IA32_APICBASE, msr);
+ if (!IS_ENABLED(CONFIG_INTEL_QUARK)) {
+ msr_t msr;
+
+ msr = msr_read(MSR_IA32_APICBASE);
+ msr.hi &= 0xffffff00;
+ msr.lo |= MSR_IA32_APICBASE_ENABLE;
+ msr.lo &= ~MSR_IA32_APICBASE_BASE;
+ msr.lo |= LAPIC_DEFAULT_BASE;
+ msr_write(MSR_IA32_APICBASE, msr);
+ }
}
void disable_lapic(void)
{
- msr_t msr;
+ if (!IS_ENABLED(CONFIG_INTEL_QUARK)) {
+ msr_t msr;
- msr = msr_read(MSR_IA32_APICBASE);
- msr.lo &= ~MSR_IA32_APICBASE_ENABLE;
- msr_write(MSR_IA32_APICBASE, msr);
+ msr = msr_read(MSR_IA32_APICBASE);
+ msr.lo &= ~MSR_IA32_APICBASE_ENABLE;
+ msr_write(MSR_IA32_APICBASE, msr);
+ }
}
unsigned long lapicid(void)
void lapic_setup(void)
{
-#ifdef CONFIG_SMP
/* Only Pentium Pro and later have those MSR stuff */
debug("Setting up local apic: ");
LAPIC_DELIVERY_MODE_NMI));
debug("apic_id: 0x%02lx, ", lapicid());
-#else /* !CONFIG_SMP */
- /* Only Pentium Pro and later have those MSR stuff */
- debug("Disabling local apic: ");
- disable_lapic();
-#endif /* CONFIG_SMP */
+
debug("done.\n");
post_code(POST_LAPIC);
}
#include <dm.h>
#include <errno.h>
#include <malloc.h>
+#include <qfw.h>
#include <asm/atomic.h>
#include <asm/cpu.h>
#include <asm/interrupt.h>
#include <asm/mtrr.h>
#include <asm/processor.h>
#include <asm/sipi.h>
-#include <asm/fw_cfg.h>
#include <dm/device-internal.h>
#include <dm/uclass-internal.h>
#include <dm/lists.h>
cpu_get_name(processor_name);
debug("CPU: %s\n", processor_name);
- lapic_setup();
-
apic_id = lapicid();
ret = find_cpu_by_apic_id(apic_id, devp);
if (ret) {
return 0;
}
-#ifdef CONFIG_QEMU
+#ifdef CONFIG_QFW
static int qemu_cpu_fixup(void)
{
int ret;
if (ret)
return ret;
-#ifdef CONFIG_QEMU
+#ifdef CONFIG_QFW
ret = qemu_cpu_fixup();
if (ret)
return ret;
ifndef CONFIG_EFI_STUB
obj-y += car.o dram.o
endif
-obj-y += cpu.o fw_cfg.o qemu.o
+obj-y += qemu.o
+obj-$(CONFIG_QFW) += cpu.o e820.o
#include <cpu.h>
#include <dm.h>
#include <errno.h>
+#include <qfw.h>
#include <asm/cpu.h>
-#include <asm/fw_cfg.h>
DECLARE_GLOBAL_DATA_PTR;
--- /dev/null
+/*
+ * (C) Copyright 2015 Miao Yan <yanmiaobest@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/e820.h>
+
+unsigned install_e820_map(unsigned max_entries, struct e820entry *entries)
+{
+ entries[0].addr = 0;
+ entries[0].size = ISA_START_ADDRESS;
+ entries[0].type = E820_RAM;
+
+ entries[1].addr = ISA_START_ADDRESS;
+ entries[1].size = ISA_END_ADDRESS - ISA_START_ADDRESS;
+ entries[1].type = E820_RESERVED;
+
+ /*
+ * since we use memalign(malloc) to allocate high memory for
+ * storing ACPI tables, we need to reserve them in e820 tables,
+ * otherwise kernel will reclaim them and data will be corrupted
+ */
+ entries[2].addr = ISA_END_ADDRESS;
+ entries[2].size = gd->relocaddr - TOTAL_MALLOC_LEN - ISA_END_ADDRESS;
+ entries[2].type = E820_RAM;
+
+ /* for simplicity, reserve entire malloc space */
+ entries[3].addr = gd->relocaddr - TOTAL_MALLOC_LEN;
+ entries[3].size = TOTAL_MALLOC_LEN;
+ entries[3].type = E820_RESERVED;
+
+ entries[4].addr = gd->relocaddr;
+ entries[4].size = gd->ram_size - gd->relocaddr;
+ entries[4].type = E820_RESERVED;
+
+ entries[5].addr = CONFIG_PCIE_ECAM_BASE;
+ entries[5].size = CONFIG_PCIE_ECAM_SIZE;
+ entries[5].type = E820_RESERVED;
+
+ return 6;
+}
+++ /dev/null
-/*
- * (C) Copyright 2015 Miao Yan <yanmiaobest@gmail.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <errno.h>
-#include <malloc.h>
-#include <asm/io.h>
-#include <asm/fw_cfg.h>
-#include <asm/tables.h>
-#include <asm/e820.h>
-#include <linux/list.h>
-#include <memalign.h>
-
-static bool fwcfg_present;
-static bool fwcfg_dma_present;
-
-static LIST_HEAD(fw_list);
-
-/* Read configuration item using fw_cfg PIO interface */
-static void qemu_fwcfg_read_entry_pio(uint16_t entry,
- uint32_t size, void *address)
-{
- uint32_t i = 0;
- uint8_t *data = address;
-
- /*
- * writting FW_CFG_INVALID will cause read operation to resume at
- * last offset, otherwise read will start at offset 0
- */
- if (entry != FW_CFG_INVALID)
- outw(entry, FW_CONTROL_PORT);
- while (size--)
- data[i++] = inb(FW_DATA_PORT);
-}
-
-/* Read configuration item using fw_cfg DMA interface */
-static void qemu_fwcfg_read_entry_dma(uint16_t entry,
- uint32_t size, void *address)
-{
- struct fw_cfg_dma_access dma;
-
- dma.length = cpu_to_be32(size);
- dma.address = cpu_to_be64((uintptr_t)address);
- dma.control = cpu_to_be32(FW_CFG_DMA_READ);
-
- /*
- * writting FW_CFG_INVALID will cause read operation to resume at
- * last offset, otherwise read will start at offset 0
- */
- if (entry != FW_CFG_INVALID)
- dma.control |= cpu_to_be32(FW_CFG_DMA_SELECT | (entry << 16));
-
- barrier();
-
- debug("qemu_fwcfg_dma_read_entry: addr %p, length %u control 0x%x\n",
- address, size, be32_to_cpu(dma.control));
-
- outl(cpu_to_be32((uint32_t)&dma), FW_DMA_PORT_HIGH);
-
- while (be32_to_cpu(dma.control) & ~FW_CFG_DMA_ERROR)
- __asm__ __volatile__ ("pause");
-}
-
-static bool qemu_fwcfg_present(void)
-{
- uint32_t qemu;
-
- qemu_fwcfg_read_entry_pio(FW_CFG_SIGNATURE, 4, &qemu);
- return be32_to_cpu(qemu) == QEMU_FW_CFG_SIGNATURE;
-}
-
-static bool qemu_fwcfg_dma_present(void)
-{
- uint8_t dma_enabled;
-
- qemu_fwcfg_read_entry_pio(FW_CFG_ID, 1, &dma_enabled);
- if (dma_enabled & FW_CFG_DMA_ENABLED)
- return true;
-
- return false;
-}
-
-static void qemu_fwcfg_read_entry(uint16_t entry,
- uint32_t length, void *address)
-{
- if (fwcfg_dma_present)
- qemu_fwcfg_read_entry_dma(entry, length, address);
- else
- qemu_fwcfg_read_entry_pio(entry, length, address);
-}
-
-int qemu_fwcfg_online_cpus(void)
-{
- uint16_t nb_cpus;
-
- if (!fwcfg_present)
- return -ENODEV;
-
- qemu_fwcfg_read_entry(FW_CFG_NB_CPUS, 2, &nb_cpus);
-
- return le16_to_cpu(nb_cpus);
-}
-
-/*
- * This function prepares kernel for zboot. It loads kernel data
- * to 'load_addr', initrd to 'initrd_addr' and kernel command
- * line using qemu fw_cfg interface.
- */
-static int qemu_fwcfg_setup_kernel(void *load_addr, void *initrd_addr)
-{
- char *data_addr;
- uint32_t setup_size, kernel_size, cmdline_size, initrd_size;
-
- qemu_fwcfg_read_entry(FW_CFG_SETUP_SIZE, 4, &setup_size);
- qemu_fwcfg_read_entry(FW_CFG_KERNEL_SIZE, 4, &kernel_size);
-
- if (setup_size == 0 || kernel_size == 0) {
- printf("warning: no kernel available\n");
- return -1;
- }
-
- data_addr = load_addr;
- qemu_fwcfg_read_entry(FW_CFG_SETUP_DATA,
- le32_to_cpu(setup_size), data_addr);
- data_addr += le32_to_cpu(setup_size);
-
- qemu_fwcfg_read_entry(FW_CFG_KERNEL_DATA,
- le32_to_cpu(kernel_size), data_addr);
- data_addr += le32_to_cpu(kernel_size);
-
- data_addr = initrd_addr;
- qemu_fwcfg_read_entry(FW_CFG_INITRD_SIZE, 4, &initrd_size);
- if (initrd_size == 0) {
- printf("warning: no initrd available\n");
- } else {
- qemu_fwcfg_read_entry(FW_CFG_INITRD_DATA,
- le32_to_cpu(initrd_size), data_addr);
- data_addr += le32_to_cpu(initrd_size);
- }
-
- qemu_fwcfg_read_entry(FW_CFG_CMDLINE_SIZE, 4, &cmdline_size);
- if (cmdline_size) {
- qemu_fwcfg_read_entry(FW_CFG_CMDLINE_DATA,
- le32_to_cpu(cmdline_size), data_addr);
- /*
- * if kernel cmdline only contains '\0', (e.g. no -append
- * when invoking qemu), do not update bootargs
- */
- if (*data_addr != '\0') {
- if (setenv("bootargs", data_addr) < 0)
- printf("warning: unable to change bootargs\n");
- }
- }
-
- printf("loading kernel to address %p size %x", load_addr,
- le32_to_cpu(kernel_size));
- if (initrd_size)
- printf(" initrd %p size %x\n",
- initrd_addr,
- le32_to_cpu(initrd_size));
- else
- printf("\n");
-
- return 0;
-}
-
-static int qemu_fwcfg_read_firmware_list(void)
-{
- int i;
- uint32_t count;
- struct fw_file *file;
- struct list_head *entry;
-
- /* don't read it twice */
- if (!list_empty(&fw_list))
- return 0;
-
- qemu_fwcfg_read_entry(FW_CFG_FILE_DIR, 4, &count);
- if (!count)
- return 0;
-
- count = be32_to_cpu(count);
- for (i = 0; i < count; i++) {
- file = malloc(sizeof(*file));
- if (!file) {
- printf("error: allocating resource\n");
- goto err;
- }
- qemu_fwcfg_read_entry(FW_CFG_INVALID,
- sizeof(struct fw_cfg_file), &file->cfg);
- file->addr = 0;
- list_add_tail(&file->list, &fw_list);
- }
-
- return 0;
-
-err:
- list_for_each(entry, &fw_list) {
- file = list_entry(entry, struct fw_file, list);
- free(file);
- }
-
- return -ENOMEM;
-}
-
-#ifdef CONFIG_QEMU_ACPI_TABLE
-static struct fw_file *qemu_fwcfg_find_file(const char *name)
-{
- struct list_head *entry;
- struct fw_file *file;
-
- list_for_each(entry, &fw_list) {
- file = list_entry(entry, struct fw_file, list);
- if (!strcmp(file->cfg.name, name))
- return file;
- }
-
- return NULL;
-}
-
-/*
- * This function allocates memory for ACPI tables
- *
- * @entry : BIOS linker command entry which tells where to allocate memory
- * (either high memory or low memory)
- * @addr : The address that should be used for low memory allcation. If the
- * memory allocation request is 'ZONE_HIGH' then this parameter will
- * be ignored.
- * @return: 0 on success, or negative value on failure
- */
-static int bios_linker_allocate(struct bios_linker_entry *entry, u32 *addr)
-{
- uint32_t size, align;
- struct fw_file *file;
- unsigned long aligned_addr;
-
- align = le32_to_cpu(entry->alloc.align);
- /* align must be power of 2 */
- if (align & (align - 1)) {
- printf("error: wrong alignment %u\n", align);
- return -EINVAL;
- }
-
- file = qemu_fwcfg_find_file(entry->alloc.file);
- if (!file) {
- printf("error: can't find file %s\n", entry->alloc.file);
- return -ENOENT;
- }
-
- size = be32_to_cpu(file->cfg.size);
-
- /*
- * ZONE_HIGH means we need to allocate from high memory, since
- * malloc space is already at the end of RAM, so we directly use it.
- * If allocation zone is ZONE_FSEG, then we use the 'addr' passed
- * in which is low memory
- */
- if (entry->alloc.zone == BIOS_LINKER_LOADER_ALLOC_ZONE_HIGH) {
- aligned_addr = (unsigned long)memalign(align, size);
- if (!aligned_addr) {
- printf("error: allocating resource\n");
- return -ENOMEM;
- }
- } else if (entry->alloc.zone == BIOS_LINKER_LOADER_ALLOC_ZONE_FSEG) {
- aligned_addr = ALIGN(*addr, align);
- } else {
- printf("error: invalid allocation zone\n");
- return -EINVAL;
- }
-
- debug("bios_linker_allocate: allocate file %s, size %u, zone %d, align %u, addr 0x%lx\n",
- file->cfg.name, size, entry->alloc.zone, align, aligned_addr);
-
- qemu_fwcfg_read_entry(be16_to_cpu(file->cfg.select),
- size, (void *)aligned_addr);
- file->addr = aligned_addr;
-
- /* adjust address for low memory allocation */
- if (entry->alloc.zone == BIOS_LINKER_LOADER_ALLOC_ZONE_FSEG)
- *addr = (aligned_addr + size);
-
- return 0;
-}
-
-/*
- * This function patches ACPI tables previously loaded
- * by bios_linker_allocate()
- *
- * @entry : BIOS linker command entry which tells how to patch
- * ACPI tables
- * @return: 0 on success, or negative value on failure
- */
-static int bios_linker_add_pointer(struct bios_linker_entry *entry)
-{
- struct fw_file *dest, *src;
- uint32_t offset = le32_to_cpu(entry->pointer.offset);
- uint64_t pointer = 0;
-
- dest = qemu_fwcfg_find_file(entry->pointer.dest_file);
- if (!dest || !dest->addr)
- return -ENOENT;
- src = qemu_fwcfg_find_file(entry->pointer.src_file);
- if (!src || !src->addr)
- return -ENOENT;
-
- debug("bios_linker_add_pointer: dest->addr 0x%lx, src->addr 0x%lx, offset 0x%x size %u, 0x%llx\n",
- dest->addr, src->addr, offset, entry->pointer.size, pointer);
-
- memcpy(&pointer, (char *)dest->addr + offset, entry->pointer.size);
- pointer = le64_to_cpu(pointer);
- pointer += (unsigned long)src->addr;
- pointer = cpu_to_le64(pointer);
- memcpy((char *)dest->addr + offset, &pointer, entry->pointer.size);
-
- return 0;
-}
-
-/*
- * This function updates checksum fields of ACPI tables previously loaded
- * by bios_linker_allocate()
- *
- * @entry : BIOS linker command entry which tells where to update ACPI table
- * checksums
- * @return: 0 on success, or negative value on failure
- */
-static int bios_linker_add_checksum(struct bios_linker_entry *entry)
-{
- struct fw_file *file;
- uint8_t *data, cksum = 0;
- uint8_t *cksum_start;
-
- file = qemu_fwcfg_find_file(entry->cksum.file);
- if (!file || !file->addr)
- return -ENOENT;
-
- data = (uint8_t *)(file->addr + le32_to_cpu(entry->cksum.offset));
- cksum_start = (uint8_t *)(file->addr + le32_to_cpu(entry->cksum.start));
- cksum = table_compute_checksum(cksum_start,
- le32_to_cpu(entry->cksum.length));
- *data = cksum;
-
- return 0;
-}
-
-unsigned install_e820_map(unsigned max_entries, struct e820entry *entries)
-{
- entries[0].addr = 0;
- entries[0].size = ISA_START_ADDRESS;
- entries[0].type = E820_RAM;
-
- entries[1].addr = ISA_START_ADDRESS;
- entries[1].size = ISA_END_ADDRESS - ISA_START_ADDRESS;
- entries[1].type = E820_RESERVED;
-
- /*
- * since we use memalign(malloc) to allocate high memory for
- * storing ACPI tables, we need to reserve them in e820 tables,
- * otherwise kernel will reclaim them and data will be corrupted
- */
- entries[2].addr = ISA_END_ADDRESS;
- entries[2].size = gd->relocaddr - TOTAL_MALLOC_LEN - ISA_END_ADDRESS;
- entries[2].type = E820_RAM;
-
- /* for simplicity, reserve entire malloc space */
- entries[3].addr = gd->relocaddr - TOTAL_MALLOC_LEN;
- entries[3].size = TOTAL_MALLOC_LEN;
- entries[3].type = E820_RESERVED;
-
- entries[4].addr = gd->relocaddr;
- entries[4].size = gd->ram_size - gd->relocaddr;
- entries[4].type = E820_RESERVED;
-
- entries[5].addr = CONFIG_PCIE_ECAM_BASE;
- entries[5].size = CONFIG_PCIE_ECAM_SIZE;
- entries[5].type = E820_RESERVED;
-
- return 6;
-}
-
-/* This function loads and patches ACPI tables provided by QEMU */
-u32 write_acpi_tables(u32 addr)
-{
- int i, ret = 0;
- struct fw_file *file;
- struct bios_linker_entry *table_loader;
- struct bios_linker_entry *entry;
- uint32_t size;
- struct list_head *list;
-
- /* make sure fw_list is loaded */
- ret = qemu_fwcfg_read_firmware_list();
- if (ret) {
- printf("error: can't read firmware file list\n");
- return addr;
- }
-
- file = qemu_fwcfg_find_file("etc/table-loader");
- if (!file) {
- printf("error: can't find etc/table-loader\n");
- return addr;
- }
-
- size = be32_to_cpu(file->cfg.size);
- if ((size % sizeof(*entry)) != 0) {
- printf("error: table-loader maybe corrupted\n");
- return addr;
- }
-
- table_loader = malloc(size);
- if (!table_loader) {
- printf("error: no memory for table-loader\n");
- return addr;
- }
-
- qemu_fwcfg_read_entry(be16_to_cpu(file->cfg.select),
- size, table_loader);
-
- for (i = 0; i < (size / sizeof(*entry)); i++) {
- entry = table_loader + i;
- switch (le32_to_cpu(entry->command)) {
- case BIOS_LINKER_LOADER_COMMAND_ALLOCATE:
- ret = bios_linker_allocate(entry, &addr);
- if (ret)
- goto out;
- break;
- case BIOS_LINKER_LOADER_COMMAND_ADD_POINTER:
- ret = bios_linker_add_pointer(entry);
- if (ret)
- goto out;
- break;
- case BIOS_LINKER_LOADER_COMMAND_ADD_CHECKSUM:
- ret = bios_linker_add_checksum(entry);
- if (ret)
- goto out;
- break;
- default:
- break;
- }
- }
-
-out:
- if (ret) {
- list_for_each(list, &fw_list) {
- file = list_entry(list, struct fw_file, list);
- if (file->addr)
- free((void *)file->addr);
- }
- }
-
- free(table_loader);
- return addr;
-}
-#endif
-
-static int qemu_fwcfg_list_firmware(void)
-{
- int ret;
- struct list_head *entry;
- struct fw_file *file;
-
- /* make sure fw_list is loaded */
- ret = qemu_fwcfg_read_firmware_list();
- if (ret)
- return ret;
-
- list_for_each(entry, &fw_list) {
- file = list_entry(entry, struct fw_file, list);
- printf("%-56s\n", file->cfg.name);
- }
-
- return 0;
-}
-
-void qemu_fwcfg_init(void)
-{
- fwcfg_present = qemu_fwcfg_present();
- if (fwcfg_present)
- fwcfg_dma_present = qemu_fwcfg_dma_present();
-}
-
-static int qemu_fwcfg_do_list(cmd_tbl_t *cmdtp, int flag,
- int argc, char * const argv[])
-{
- if (qemu_fwcfg_list_firmware() < 0)
- return CMD_RET_FAILURE;
-
- return 0;
-}
-
-static int qemu_fwcfg_do_cpus(cmd_tbl_t *cmdtp, int flag,
- int argc, char * const argv[])
-{
- int ret = qemu_fwcfg_online_cpus();
- if (ret < 0) {
- printf("QEMU fw_cfg interface not found\n");
- return CMD_RET_FAILURE;
- }
-
- printf("%d cpu(s) online\n", qemu_fwcfg_online_cpus());
-
- return 0;
-}
-
-static int qemu_fwcfg_do_load(cmd_tbl_t *cmdtp, int flag,
- int argc, char * const argv[])
-{
- char *env;
- void *load_addr;
- void *initrd_addr;
-
- env = getenv("loadaddr");
- load_addr = env ?
- (void *)simple_strtoul(env, NULL, 16) :
- (void *)CONFIG_LOADADDR;
-
- env = getenv("ramdiskaddr");
- initrd_addr = env ?
- (void *)simple_strtoul(env, NULL, 16) :
- (void *)CONFIG_RAMDISK_ADDR;
-
- if (argc == 2) {
- load_addr = (void *)simple_strtoul(argv[0], NULL, 16);
- initrd_addr = (void *)simple_strtoul(argv[1], NULL, 16);
- } else if (argc == 1) {
- load_addr = (void *)simple_strtoul(argv[0], NULL, 16);
- }
-
- return qemu_fwcfg_setup_kernel(load_addr, initrd_addr);
-}
-
-static cmd_tbl_t fwcfg_commands[] = {
- U_BOOT_CMD_MKENT(list, 0, 1, qemu_fwcfg_do_list, "", ""),
- U_BOOT_CMD_MKENT(cpus, 0, 1, qemu_fwcfg_do_cpus, "", ""),
- U_BOOT_CMD_MKENT(load, 2, 1, qemu_fwcfg_do_load, "", ""),
-};
-
-static int do_qemu_fw(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- int ret;
- cmd_tbl_t *fwcfg_cmd;
-
- if (!fwcfg_present) {
- printf("QEMU fw_cfg interface not found\n");
- return CMD_RET_USAGE;
- }
-
- fwcfg_cmd = find_cmd_tbl(argv[1], fwcfg_commands,
- ARRAY_SIZE(fwcfg_commands));
- argc -= 2;
- argv += 2;
- if (!fwcfg_cmd || argc > fwcfg_cmd->maxargs)
- return CMD_RET_USAGE;
-
- ret = fwcfg_cmd->cmd(fwcfg_cmd, flag, argc, argv);
-
- return cmd_process_error(fwcfg_cmd, ret);
-}
-
-U_BOOT_CMD(
- qfw, 4, 1, do_qemu_fw,
- "QEMU firmware interface",
- "<command>\n"
- " - list : print firmware(s) currently loaded\n"
- " - cpus : print online cpu number\n"
- " - load <kernel addr> <initrd addr> : load kernel and initrd (if any), and setup for zboot\n"
-)
#include <common.h>
#include <pci.h>
+#include <qfw.h>
#include <asm/irq.h>
#include <asm/post.h>
#include <asm/processor.h>
#include <asm/arch/device.h>
#include <asm/arch/qemu.h>
-#include <asm/fw_cfg.h>
static bool i440fx;
+#ifdef CONFIG_QFW
+
+/* on x86, the qfw registers are all IO ports */
+#define FW_CONTROL_PORT 0x510
+#define FW_DATA_PORT 0x511
+#define FW_DMA_PORT_LOW 0x514
+#define FW_DMA_PORT_HIGH 0x518
+
+static void qemu_x86_fwcfg_read_entry_pio(uint16_t entry,
+ uint32_t size, void *address)
+{
+ uint32_t i = 0;
+ uint8_t *data = address;
+
+ /*
+ * writting FW_CFG_INVALID will cause read operation to resume at
+ * last offset, otherwise read will start at offset 0
+ *
+ * Note: on platform where the control register is IO port, the
+ * endianness is little endian.
+ */
+ if (entry != FW_CFG_INVALID)
+ outw(cpu_to_le16(entry), FW_CONTROL_PORT);
+
+ /* the endianness of data register is string-preserving */
+ while (size--)
+ data[i++] = inb(FW_DATA_PORT);
+}
+
+static void qemu_x86_fwcfg_read_entry_dma(struct fw_cfg_dma_access *dma)
+{
+ /* the DMA address register is big endian */
+ outl(cpu_to_be32((uint32_t)dma), FW_DMA_PORT_HIGH);
+
+ while (be32_to_cpu(dma->control) & ~FW_CFG_DMA_ERROR)
+ __asm__ __volatile__ ("pause");
+}
+
+static struct fw_cfg_arch_ops fwcfg_x86_ops = {
+ .arch_read_pio = qemu_x86_fwcfg_read_entry_pio,
+ .arch_read_dma = qemu_x86_fwcfg_read_entry_dma
+};
+#endif
+
static void enable_pm_piix(void)
{
u8 en;
enable_pm_ich9();
}
- qemu_fwcfg_init();
+#ifdef CONFIG_QFW
+ qemu_fwcfg_init(&fwcfg_x86_ops);
+#endif
}
int arch_cpu_init(void)
#include <common.h>
#include <mmc.h>
#include <asm/io.h>
+#include <asm/ioapic.h>
#include <asm/mrccache.h>
#include <asm/mtrr.h>
#include <asm/pci.h>
mrccache_save();
#endif
+ /* Assign a unique I/O APIC ID */
+ io_apic_set_id(1);
+
return 0;
}
return;
}
-
-int reserve_arch(void)
-{
-#ifdef CONFIG_ENABLE_MRC_CACHE
- return mrccache_reserve();
-#else
- return 0;
-#endif
-}
compatible = "intel,irq-router";
intel,pirq-config = "ibase";
intel,ibase-offset = <0x50>;
+ intel,actl-addr = <0>;
intel,pirq-link = <8 8>;
intel,pirq-mask = <0xdee0>;
intel,pirq-routing = <
#include "microcode/m0230671117.dtsi"
};
update@1 {
-#include "microcode/m0130673322.dtsi"
+#include "microcode/m0130673325.dtsi"
};
update@2 {
-#include "microcode/m0130679901.dtsi"
+#include "microcode/m0130679907.dtsi"
};
};
compatible = "intel,irq-router";
intel,pirq-config = "ibase";
intel,ibase-offset = <0x50>;
+ intel,actl-addr = <0>;
intel,pirq-link = <8 8>;
intel,pirq-mask = <0xdee0>;
intel,pirq-routing = <
microcode {
update@0 {
-#include "microcode/m0130673322.dtsi"
+#include "microcode/m0130673325.dtsi"
};
update@1 {
-#include "microcode/m0130679901.dtsi"
+#include "microcode/m0130679907.dtsi"
};
};
};
irq-router {
compatible = "intel,queensbay-irq-router";
intel,pirq-config = "pci";
+ intel,actl-addr = <0x58>;
intel,pirq-link = <0x60 8>;
intel,pirq-mask = <0xcee0>;
intel,pirq-routing = <
stdout-path = &pciuart0;
};
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "cpu-x86";
+ reg = <0>;
+ intel,apic-id = <0>;
+ };
+ };
+
tsc-timer {
clock-frequency = <400000000>;
};
irq-router {
compatible = "intel,quark-irq-router";
intel,pirq-config = "pci";
+ intel,actl-addr = <0x58>;
intel,pirq-link = <0x60 8>;
intel,pirq-mask = <0xdef8>;
intel,pirq-routing = <
+++ /dev/null
-/*
- * ---
- * This is a device tree fragment. Use #include to add these properties to a
- * node.
- *
- * Date:
- */
-
-compatible = "intel,microcode";
-intel,header-version = <1>;
-intel,update-revision = <0x322>;
-intel,date-code = <0x4012014>;
-intel,processor-signature = <0x30673>;
-intel,checksum = <0x17b0d914>;
-intel,loader-revision = <1>;
-intel,processor-flags = <0x1>;
-
-/* The first 48-bytes are the public header which repeats the above data */
-data = <
- 0x01000000 0x22030000 0x14200104 0x73060300
- 0x14d9b017 0x01000000 0x01000000 0xd0cb0000
- 0x00cc0000 0x00000000 0x00000000 0x00000000
- 0x00000000 0xa1000000 0x01000200 0x22030000
- 0x00000000 0x00000000 0x31031420 0x11320000
- 0x01000000 0x73060300 0x00000000 0x00000000
- 0x00000000 0x00000000 0x00000000 0x00000000
- 0x00000000 0xf4320000 0x00000000 0x00000000
- 0x00000000 0x00000000 0x00000000 0x00000000
- 0x0ae10178 0x7c98f9d1 0x41962d85 0x19391270
- 0xcf3c0336 0xc1f13d6f 0xe46abaf6 0x3b65ca6b
- 0xdb666815 0x5a17bfc4 0x4fca009d 0x099ae8b3
- 0x198e2c7d 0x7c665bbf 0xc07a1a7a 0x7dbcee26
- 0x867296b2 0xc885b6ce 0xe602baff 0x68544b14
- 0xc928c400 0x3add156d 0x531946f9 0x92a03216
- 0xda352322 0xd967ee1f 0x3c5170a7 0xf6de834e
- 0x5a2ed8b3 0x9fb8f050 0x450de17f 0xfd5ef070
- 0x4954575f 0xa3a071ab 0xb56e2afb 0xe2b48302
- 0x6655a958 0x57c9a438 0x1b2f688a 0x09309bc4
- 0x0be95612 0x529c1633 0xc48515d9 0x29eb78df
- 0x9933409f 0xda58dea9 0x58c805fd 0xbc110f5a
- 0x40780ec0 0x6ad59bb3 0xc7387fb8 0x591c1490
- 0xf9335932 0x32130e0b 0xef4b3c96 0xacd903f2
- 0x5b362539 0xe7f85529 0xcb17c41f 0xe7e440d8
- 0xfaf7e925 0x969b76fb 0x5edab8c7 0xf00012e8
- 0x121c2971 0xe5b18959 0xadfd07c0 0x1f09c9d7
- 0x9781006a 0x39550073 0x6c438b6d 0x436f60bc
- 0x11000000 0x8514b971 0x40df7b4a 0x6a6b7285
- 0x7978ef59 0x319bddf5 0x04c68e5a 0xe1c28b10
- 0x172f63dc 0x306fb95d 0x31d881e8 0x69f8e08d
- 0x617a99e1 0x1ab6b574 0x2951fa5b 0xcc7e3e94
- 0xff379d19 0x5c035dec 0xe28ed726 0x22b8a5ac
- 0xd08b3ac5 0x45c03b9e 0xcea4083c 0xc26758aa
- 0xbe7cf81e 0x43d898f3 0x5c45a635 0xc9cac095
- 0xb89aea20 0x2c02b40e 0xe3a8b48d 0xeabfb60e
- 0x776ed2a9 0x080ae6d5 0x7f64b1df 0x00e40ee6
- 0x0f1c10f4 0x792e5423 0x787f5459 0x63a8b02c
- 0x3fd6a255 0x049cae26 0x0949f5ff 0x9aebb236
- 0xecc01775 0x91b57b84 0xe0e45ea3 0x5a8bf79e
- 0x356a843a 0x2406795f 0x8aaae5d8 0x6a8c877c
- 0xa8b2b8f4 0x04cf8f49 0x422d9e2c 0xf09f9896
- 0xe9b92215 0x9c98fb44 0x88556b7f 0x519d6f4c
- 0x9e8a016b 0xcb18d16c 0x419b4ee7 0x080b49c8
- 0xc51b875e 0x46aabc9c 0x262d27eb 0x93ea189d
- 0xdd0da69d 0x3e5b17e8 0xcc78509a 0x00b07e6e
- 0x363d5a70 0x64572070 0x8a84abc4 0x1cb03838
- 0x965fd76a 0x540aafc9 0x83a91654 0x1a722e67
- 0x4bf98ce1 0x2b3c2ff9 0x972cebd4 0xf3a68395
- 0x2613e422 0xf8d031d7 0xb1c79a0f 0xfd44f65b
- 0xa7012a9b 0xd9a15a60 0xc311fc0c 0x6f52f878
- 0x3d68381d 0xd2a035d7 0xb790c50e 0x9f1e5010
- 0x41877064 0xa9d1e4ae 0xfe9abbd5 0x60c2c748
- 0x8167e5ad 0x022dbfb3 0x75abe483 0x51c37170
- 0x09b8590d 0xc1bb323d 0x2c7336b1 0xd4d0d49b
- 0xc7f6152b 0x7919d596 0x1e1ff62e 0xc49604a0
- 0x33857369 0xeaa3f382 0x98b8cd86 0x176e1bf3
- 0x1a68867b 0x6af0a11c 0x69a82b25 0x48c72525
- 0xa00aae2d 0xb09f67f4 0x1a99f83d 0x7266cca3
- 0x8d03a7da 0x2e1d7c49 0x01ac68ae 0x93188770
- 0x0609e769 0x982ed28d 0xe40999e0 0x8932ebab
- 0x5637ad5a 0x2725e8ad 0x56d7caaf 0xc351faa2
- 0x09dbd737 0x0d2f3bf0 0x0623330d 0xdd547489
- 0xcca7e722 0xa9096d13 0x95b17818 0xc092cb81
- 0x72c6eefc 0x1811c37e 0x78161497 0x8be0c4c6
- 0xd63aeb19 0x91ab68df 0x8f2e5e4d 0xf4c74566
- 0x7677a553 0x19698ac3 0xedca0620 0x77f32470
- 0x031e011b 0x751f6696 0xb277d06e 0x3eae2742
- 0x133e621a 0x38fa3172 0x9398cc1c 0xf42a507b
- 0x4547d933 0x63a91eb0 0xf5bcf6a4 0x926ba056
- 0x0adf5bce 0x140f53e4 0x7ff6bb5c 0x87dd79ba
- 0xbba240ac 0x694f743d 0x709cdb20 0x5b4d4401
- 0xc9693610 0x55f9f268 0x1142bc3f 0xf8fe3689
- 0x04a93c4c 0x33dedc46 0xdc73c725 0x2f5ba264
- 0x5b7a6a69 0x024b64f5 0x6e8bfa12 0x62bf2aa7
- 0x520f5a07 0x3c7c4292 0xb7ad2613 0x1f78fc87
- 0xd5284e4e 0x2c730f33 0x8861e947 0x8bacef7d
- 0xbafa2608 0x14ed0b5b 0x3b9bfb02 0x24ced271
- 0x002b2941 0x22d4431c 0x855f4248 0x5ec46e29
- 0x6f1f42fb 0x5dd24fe0 0x290961f6 0xf392dbaf
- 0xa1a8d9c2 0x61e18f4e 0xfda59a70 0x5498daa5
- 0x5ae7ea6f 0xf058c635 0x6817ebee 0x8e30dc8b
- 0x7c8d79be 0x5fb15b9b 0xeed64741 0xe2642a94
- 0x680d7e6e 0x3cbad7aa 0x808c415f 0xe9323aa2
- 0xaadf5b25 0xf60abf13 0xd5c47967 0xc248d0b3
- 0x0f232cbd 0x84092449 0x5744384b 0x5e153ded
- 0x8bb19817 0x34430271 0x917d2315 0x1fc790c7
- 0xc21b5db6 0xec578b1f 0x903a286e 0xca0c59bc
- 0x03e95c7a 0x8c659e99 0x7b09da0a 0xd61e7517
- 0x90b1c519 0x8deac92c 0xf99c7bec 0xb6257d92
- 0x3d61c16e 0xebd58be0 0xb470e655 0xa44bbf4f
- 0xfebe5313 0x4662110a 0x5d42ccd9 0x140845ec
- 0xc80329a9 0x915ca966 0x71e33828 0xe46c870a
- 0x7da9a490 0x255544da 0xa20fb8df 0xf94062b3
- 0xb2df5870 0xebf31e88 0x6e723e2f 0xe6ba9cf1
- 0x7e7084c2 0x1782ac71 0x0a0b0127 0xe9234e38
- 0x881356d6 0xb27a54b6 0x5594730e 0x9a14bd8f
- 0x6dba7da9 0x1069e285 0x02a52798 0x61ea7d86
- 0x665b2572 0x29d41eb5 0x1d211169 0x1218b345
- 0xbfbd264c 0x5b8b0625 0xbbfdcf39 0x6768dfce
- 0x0b5f10cb 0xe159414c 0x74356ed6 0x70077f49
- 0x672107e8 0x11616856 0x824e6f2f 0x99614958
- 0x5857305d 0x416a193f 0x010d266c 0xe5194f03
- 0x152d6516 0xeb83872e 0x4923cc1f 0x1191d1ca
- 0x23feb738 0x6817c1d7 0xe49129ed 0x4a53132a
- 0xdb46b95b 0x3f970366 0x93f1a518 0xae8d72ae
- 0xb689d915 0x0bdfda17 0x2ac7238d 0x1c4291e7
- 0xc5b11085 0x3c51c1ba 0x9fd63edd 0xe464d740
- 0xc17f2789 0x0adef6b9 0xf9aaf83e 0xfb2a9798
- 0x7f16268b 0x4c8ca6c5 0x2b17be52 0x00c91157
- 0xb69eb5db 0xe55ed94a 0xdf13b5a5 0xbb52d1e3
- 0x651bb017 0xc7795724 0x0dfd4711 0x02d2d6e0
- 0xc835e771 0x8ab5dd50 0x7caca109 0xd5c18d6e
- 0xbef0e727 0xaff2dd07 0xf1062a32 0x26d14796
- 0x97f6e36c 0xf845278e 0x185eb5b3 0xcde4e201
- 0x13166ab7 0xcdcebcdc 0x143ef0c7 0x2349893f
- 0x9dfcb70e 0x7ef72725 0x141c5b71 0x7da0f5d3
- 0x76bebb67 0x28bc0a83 0xb67ecf0f 0xd60a1303
- 0x9391b279 0x6ad41154 0x317896b0 0x1237efa6
- 0x7b2a2e6c 0x3ad9a110 0xb44357d4 0xb32e39fe
- 0x2358d28e 0x76e847d9 0x3e85db01 0x6c74e466
- 0x9e4e6b32 0x13072a53 0x5972132e 0xd97cb04d
- 0x55ee6a0b 0xc1434b92 0x772f6a1d 0x0f81f7a6
- 0x072aa8f7 0x179da0e0 0x976bd78c 0x2e43c16b
- 0x4f4a6b51 0x92d9c61b 0xa9c15fe4 0x3f8a527a
- 0x3a232408 0x543d7957 0x21cbd682 0x896de3b0
- 0xba6b3df6 0x2ec86e51 0x2be889e3 0xae764ff0
- 0x3a2f0003 0x7a5f7949 0x577fb5ce 0xb5cbd1a6
- 0xc910ffe2 0x7fd76712 0xfc1e93ff 0xbee7b15c
- 0x5db2356d 0x9721a3fd 0x0d408aed 0x4df4c922
- 0x45d5be91 0x6c79b1fc 0xf0bf73bd 0x3f6a73b6
- 0xdcc1b51e 0x2049fe2d 0xf2b2ad4b 0xd0484d3a
- 0x1f097d3f 0xced1bf3d 0x10f4416b 0x73cb307c
- 0x4b4d94b4 0x2918ece0 0x0cfe69f3 0xb7e86cfb
- 0xa6c373b4 0x0d862b62 0x1735cd72 0xef23c127
- 0x09809c16 0x86cfb70b 0xe67c6903 0x743223a7
- 0x13c7d27f 0xb70a58cc 0x82c57566 0x2ead3c65
- 0xf9409863 0xf2b578ef 0x1622a34d 0x5ae8e861
- 0xf4384016 0x443ff5f4 0x088b8510 0xd738d1c5
- 0x577d624b 0x5adf3973 0x5f79add3 0xed7e7145
- 0x29008fc0 0xd5b278cf 0x5b4c08c2 0xb063af5c
- 0x67d41bd9 0x2d11424a 0x727924de 0x8903a86f
- 0xb122d314 0xd9675c8b 0xc2eb1382 0x4c4185da
- 0x257a0fe1 0xc3fd536b 0xadbfc223 0xc940dab4
- 0x2e83d4b0 0xf1135ad4 0xfeb1cc1a 0x9178ae04
- 0x996d72ba 0x07f6bf0f 0x6588f833 0x44f95205
- 0xee4e6897 0xa9006735 0xa5f5502c 0xeb61aca6
- 0xf2ceddb5 0x40ef9001 0xf862c3d7 0x73deaad3
- 0x7b1d8b1d 0x467bcbcf 0x7f76f969 0x6c8e7f8c
- 0xfb8e27c3 0x5075ce65 0x1c8628a8 0x7b6e3e32
- 0x4885fc9f 0xa9fa768c 0x15426120 0x1df9d006
- 0x31c52df4 0x1457f5c6 0xde5f2daa 0xfa250108
- 0xbcf7e460 0x565d4679 0x82c94142 0xae76342a
- 0x85aca7c7 0x8bc49e03 0x73f03da3 0x1e500b4c
- 0x250288a2 0x25a39951 0x66087700 0x6317754b
- 0x6ff62bdc 0xa519ad4f 0xa537b8ac 0xea6292ab
- 0xb5d66b68 0x15997d1f 0x0fdbf04a 0xaa2b1a25
- 0x74b72321 0xf8b1753a 0x33658d1e 0xb1cc5d96
- 0x5b0da6af 0x48f24997 0xb031146e 0xfe98e8d1
- 0x9bd75bf0 0x0ae088fe 0xb8fce721 0x964bc398
- 0xe82daef6 0x393884b5 0xa814f792 0xb3667bde
- 0x1d1cf32d 0xce862720 0x7b69e921 0xabd26f33
- 0x61fad35f 0xd7144eeb 0x74016bce 0x1d56277b
- 0x7f934eed 0xb1a3396a 0xd5090c7a 0x4ea94d12
- 0x1455ac10 0x7c37294c 0x06c60a9a 0xa735ab29
- 0xbffb880f 0x59e2cb48 0x54cca9d7 0xb569da05
- 0x595e72ec 0x7c82f204 0x7690420d 0xe02fbb37
- 0x4dbf4e68 0x221eda99 0x31868046 0xda435487
- 0xb4c0dcc4 0x37610096 0x35569b02 0xefcd4ecf
- 0x7b6917bf 0x45946a25 0x5d42a84a 0x8c3801b7
- 0x5ac838fa 0x7a7f252d 0xbccf3cb5 0x99a54c4c
- 0x39145831 0xfd5c1af3 0xcabb180c 0x8f0fe9dd
- 0xabd42357 0x3b6d9aa9 0x0e87ede1 0x65ea46ae
- 0xd89b618e 0x1e5cc772 0xfb43c9b4 0xdad3fdb2
- 0x96be6600 0x4887696e 0x82a4e73a 0xb2ca2cf0
- 0xc6840738 0x397d27a9 0xce971271 0x067e4de6
- 0xb593f079 0x6a77de2f 0xf9a92497 0xdc3e94aa
- 0x03239a80 0x7f38430a 0xf7f87908 0x682a8425
- 0x2d491962 0xb5737b4b 0xa26434e5 0x238ced20
- 0x1ed9fcbe 0x283a8f7b 0x18f33cf6 0x29f27cd5
- 0xd95018aa 0x883dbd25 0xfb216723 0xe939d42c
- 0xf4b1207d 0x54f5e102 0xbe2e46eb 0xb2ca8219
- 0xab181ad4 0x3a7dc3e6 0xf3713256 0x53f081ab
- 0xd630a7a3 0x07c40bc3 0x7a1fde0c 0xb368bab8
- 0xc0baaad3 0xf070baac 0xe4ab7a4f 0x82a8cf5e
- 0x9c3d7bb5 0xfe5f74a3 0x02548e86 0x2710ff5d
- 0x1b42a8c4 0x34d4f5d8 0x8dfde8f2 0xf2949298
- 0xe9d711bf 0x44d91e17 0x51ba8b32 0xbc3f60cc
- 0xa0d6c440 0xf71959b4 0x3b5f0603 0x02465794
- 0xff5d9b8a 0xd4a4abcf 0x8123626c 0x883ed4e4
- 0x9eaeaa09 0x91c38865 0xa0aaeebf 0xc48983ab
- 0x1df7a001 0x7519a65e 0x5ef3cd1d 0x8348225d
- 0x0f318b0b 0xbab1d51b 0x15ba9b84 0xef8c57bf
- 0x15d0a8c1 0x0b542fb4 0x1d51ccc8 0x6c297041
- 0xf3bee946 0x6a8c3d64 0x6e16361d 0xed50ca69
- 0x8c1f66ba 0xff7220e0 0x84a87cba 0x15d75922
- 0x77546d82 0x7bd456e3 0x10166195 0x55604f1f
- 0x894280d2 0x0ed406c4 0xc1b4058e 0x645252e5
- 0x670ea74e 0xd5b07337 0x9944e2cf 0xf2ac2579
- 0xd00c3ae8 0x2df3146d 0x4ee1c72a 0x3a3621cf
- 0x8c099145 0xf5f530e6 0x210da136 0x7908cec6
- 0xc6e47e22 0xe9bcbe4e 0x94cbcb12 0xb81f0792
- 0x1111f81e 0x4df4ac93 0x335c69be 0x9e3546b9
- 0x06c046b4 0x6f29a99c 0xbcd48ee7 0xeb011efe
- 0x41e80474 0xcee30bf4 0xad4e2ae0 0x6929a359
- 0xbdaa88e3 0x9e68a38e 0x16bbdac7 0x020d8d61
- 0x7bab6738 0x559cddbd 0xa6ae3d0c 0xe032c355
- 0xcb45a045 0x9f7680b2 0xc1cb73da 0x466052f7
- 0x488cb929 0xd93f0307 0xb2c9d81c 0xe25fdcd9
- 0xfe8b08c4 0xae6230bd 0x5238b335 0x3474b2a5
- 0x480ce0b7 0xd9a2942f 0xe830fa5b 0x3efa774f
- 0x84e53e93 0xf49e7d79 0x59897b26 0x75b1080f
- 0xc2212b0f 0xe5fe56bd 0x4556e908 0x1bd0bb17
- 0x2f159d20 0x866477e5 0x4e95a374 0xbdc9fd65
- 0x2ff87073 0x5d7dceea 0x69ada0c7 0x89f16ad0
- 0x97da55d8 0xe4457728 0x5ab7613e 0xf6bbe6ec
- 0x56b83617 0x9119b521 0x4fabf948 0x2e1ab994
- 0xd16363f0 0xaee14b3f 0x5461ea55 0x55d95d02
- 0xf72c902c 0x1ede6c56 0x697006d9 0x4d15007f
- 0x0c1cb5e5 0x55d3d5d5 0x1f18d76f 0x55c9f017
- 0x3e1d3b5b 0x8f775636 0x97e6bf8f 0x360a9fb5
- 0x1e080721 0xf9825356 0x30e900f3 0x55453bfe
- 0xbd8f1df0 0x35b43ba8 0x45db013f 0x20484d34
- 0x944ca654 0x79c2c151 0xd4e9b39b 0x1b2e79b6
- 0x554314d6 0xce4ee44d 0xd0394232 0x9da4db20
- 0xa70beed6 0x4ae4ed10 0x4c244770 0x4b91208c
- 0x39a01e0b 0x5eea0a55 0x4b36ffbe 0x6fd18df2
- 0x43fd13e3 0xa99302bc 0x63762b5d 0xd014d6b4
- 0xbf0e53d2 0x0f5b5aa5 0x3c23f5b7 0x16335036
- 0xe011bd10 0x66e596a3 0xf463e3ad 0x9670c0a3
- 0x4004e177 0xbd2b3260 0x01967017 0x1159a682
- 0x62931eb8 0xc581df9e 0x6710932f 0xfb2bb0b2
- 0xb8a0339c 0xc66f0fff 0x333f5ee3 0xc06f8586
- 0x7b9f47f1 0x9aaedaa3 0x6044562a 0x26c73565
- 0x82c6e5b2 0x39d4eed0 0x83b7432e 0x0c4f0e4a
- 0x4d9df788 0x989e7f41 0x61cacc3b 0xdc34efeb
- 0x240b22a8 0x70a508b0 0x7554f517 0x7269f02b
- 0xd27ffcf6 0x96a5879f 0x0650f7e4 0xdc1fc1ac
- 0x80781334 0x04ab3381 0x8bad17c1 0x18311833
- 0x65f06ee9 0xfaac30e1 0xe39b8b54 0x20b988ce
- 0xa6a818f3 0x75ac753b 0x66f815a4 0x224d7121
- 0x63dc6031 0xcfeed2c7 0x3ccd07d7 0x9df44157
- 0xb9dcca97 0xcf5178f1 0x10e8fb28 0xa1faa527
- 0x8851846e 0x01f56075 0x2dd4fff2 0x40786960
- 0x41aa9e6c 0xf7c85573 0x64a36432 0x4449e726
- 0x7aa7bb0d 0x08f596cc 0x248e1eb3 0x5c5567cb
- 0x62ffd012 0x2d79ce59 0xf9ed4239 0xe98e107a
- 0x4da25561 0xc6f83333 0x1ca0482d 0xcc3f3b69
- 0xa9f48711 0x99139510 0xc5777d2b 0x9c80814d
- 0xab47fbe4 0xf302d145 0x20aecccc 0x3be9e431
- 0x7dc34793 0x4d38171c 0xaa34e505 0xc32e492b
- 0x4f31bd0b 0xb7549889 0xdb3da9cf 0x084d0791
- 0xa4c63c9f 0x62e770e9 0x862fdb93 0x52c45b9e
- 0xf21019a5 0xdde6aa07 0xcb46386e 0x830693a8
- 0x651510c8 0xf3af66a4 0x78775e07 0xc9f22414
- 0x5769f089 0xac2ae873 0x044357d8 0x9fdc76f8
- 0xea16ade5 0x144e9211 0x181ade72 0xba50ce80
- 0x4573571a 0x5437c668 0x39c3b81d 0x013d766d
- 0xc1754b48 0xa611fa3b 0x725eae72 0x04b02ca9
- 0x186a2541 0xa2784e47 0x8b7601bb 0x7f9132e3
- 0x3295d5b5 0x4b470dee 0xaf5ec559 0xc4c442d6
- 0x5b07293d 0x9a68b079 0xc1408c0c 0xc2371025
- 0x4af99e8c 0x332c416a 0xec04321b 0xb8493ffb
- 0x51eab7de 0x26d7e9db 0x7880126e 0x439be5e3
- 0x7e8910f0 0xa8ba727b 0x88cb04df 0x70750495
- 0xc13413f6 0x684312db 0x0579d5b1 0x05fe44f7
- 0x627e04f3 0xe85b47da 0xbf646f0b 0x2ddf4932
- 0x1bcb6fc0 0x611de27d 0xb3ee1bed 0x247dad06
- 0xa7107d34 0xba434b88 0x6eb90466 0x45a65871
- 0xa9a67088 0x6af3b796 0xf5b73689 0xcab03ca4
- 0xca1f25e6 0xd4b7c32b 0x5908c88d 0xac6c1fa3
- 0x653184a5 0x062bc0bf 0x383de594 0x17064fc6
- 0x0650dbad 0xaec15153 0xab0572ff 0xab8c6f3c
- 0x37a93f91 0xbe51b8c5 0xabcd8573 0x05b3ad78
- 0xad6c9ecc 0xf302c7ab 0x4b3b88f7 0x805a0107
- 0xa5821ddd 0xc36f10ad 0x374b1056 0x79e69f8c
- 0x8368b6cf 0xf69458a7 0x9fad691d 0xb937724e
- 0xc542bfb1 0x37c0178d 0xc4707414 0xd6c7fa86
- 0xb3933710 0x227800f4 0x6dca3e39 0xd88bdb91
- 0x03755bda 0xa7f2d11d 0x4ab40803 0xf353e7ed
- 0xf2464ee4 0x8e58cea4 0xd05807fd 0xd8d8da5f
- 0x1a461333 0x5e84830d 0xb94ea4bc 0x5bf3506f
- 0x76461ba7 0xabe88c54 0x124c2e39 0xc3b01867
- 0xc6b0d4d1 0x9cc3c7be 0x8039ce38 0xfceb0e88
- 0xa965c5ce 0x9ff3811a 0x1af1c60e 0xae9c5f9b
- 0xee28bd50 0x202cbd2e 0x340a1312 0xa8f7115e
- 0xb000cf3a 0x21ff4052 0xa555f08f 0x1bead4d7
- 0xac14e135 0x449e208c 0x05ef8d94 0xb555a613
- 0x9d65a902 0x3ad8cc2a 0x55170533 0x75782927
- 0xefd4b5e5 0x6127ef1e 0x23fb5114 0x7ca3e1bc
- 0xc08957ba 0x44c4e2cd 0xc0b97ef9 0xea99db5a
- 0x53fdeb31 0x61721ee2 0xe41ef3c1 0x5f4788f5
- 0xa8543eca 0x3f36d642 0xda6eccef 0x0341c756
- 0xbfe7d2b9 0x66bb5cef 0xbfb43507 0xbd9c878e
- 0x94f307bc 0x7cd56198 0xf98596ba 0x21e9c50b
- 0xb9c9d725 0xf16211c2 0xe594b398 0x7e01aefc
- 0x745e5ddb 0x00bae556 0xc317ed35 0x4269b4c6
- 0x02f6b67d 0xccb4aa57 0x8a3fa0fa 0xcc660149
- 0x57cf5e87 0x4ed03819 0x77286134 0x631cc0a5
- 0x877fe8e0 0xa48856dc 0xe1c57e93 0xef04482a
- 0x40cd9ac8 0xc7f43528 0x473306c8 0x01eb339e
- 0x52612a88 0x65c3212f 0x7cc5f5e6 0xd3efbc2a
- 0xf2537dbc 0xa9428ffd 0x76ff40f9 0x0ad4a8e6
- 0x2020fbab 0xf8c5bbe4 0xb409e5a0 0x358d7b37
- 0x08220bd3 0xd3707d96 0x5e2f5edc 0x638feed5
- 0x045afa36 0x4f1604b4 0xd4dc85c7 0x37f97cef
- 0xe1c8f5a6 0xd16fdbbc 0x986137fd 0x25b3e84c
- 0x7f73be76 0xe25dbdcb 0x1f13d28a 0x7a31215b
- 0x241967d2 0x2c5b4063 0xe8339988 0x13689262
- 0x0b6d2b79 0x58773464 0xe822e560 0x77d6ba8e
- 0x6ae6c07f 0x105e1e88 0x0045bc6d 0x88ad198e
- 0xa350b9de 0xd5d0b3e6 0xc4e1cd14 0x47ca431a
- 0x2ee94476 0xa2aae1f9 0xfa2042a7 0x37b0cf82
- 0xb1aca28e 0x9a019883 0xbfb11afb 0x754ffff9
- 0xf065a9b5 0x916e14f2 0x93fba80f 0x1dd82da0
- 0xe41c950a 0x12b374bb 0x0f4d533f 0xbef539e2
- 0x1eb5c86a 0x577dd484 0x98900e2f 0xcaec8695
- 0x6a6ab336 0x135e9e68 0xc9b62a35 0xb8982b6c
- 0x5bcdb533 0x389b1517 0xbb106e40 0xd402a301
- 0x7446687b 0x35eda3ec 0xd44ceb2a 0xcfa4e441
- 0x29664690 0x598a273e 0xf2a144b1 0x68f81403
- 0xca53e666 0x064e69a4 0x87bb8ca8 0x58193c68
- 0x9b34b17a 0xde2bffc7 0xf72594dc 0x388d3f3f
- 0x638a1273 0x5ccf3567 0xcf1017a9 0xe616a6fd
- 0x64cab73c 0xd209b022 0x6f08cd26 0xc30f57b1
- 0xac2295b2 0x0c05b1c8 0xf7915ad8 0x9bcf836f
- 0x56d8b57a 0xc8b65a2c 0x11868dd3 0xea4764f8
- 0xa7bd30e8 0x8c895321 0xd276a894 0x86042daa
- 0xaf6cd261 0x18cc4ea4 0x2c2185f6 0x2bf3ae70
- 0xf3023c31 0x49f4b0e2 0x1e00afc3 0x2053b3c6
- 0xb188c9cc 0x7437a27a 0x1b29925e 0xbc488906
- 0x81cd9003 0x332fcf9b 0xeb20987a 0x831f912a
- 0x857387da 0xaf1edccb 0xfe01d809 0x05351b4a
- 0x31ec96ac 0x4f064e52 0x10ec8119 0x96c2d29f
- 0xc6e1f3fe 0x15b0d45f 0xdca23bc6 0x7b672563
- 0xa94fdc1b 0x7dd22f4f 0xd4d2260f 0xc9e055ff
- 0x89e066cc 0x98200d25 0xcba82cf7 0xffb8475b
- 0x26550a20 0xf5b4f84a 0x506cb84b 0x00d92997
- 0x7a5c5535 0xe11194eb 0x1ff21f4b 0x725d2be5
- 0xbe89242f 0x0b18afa7 0x6f5b1433 0x829bdaf9
- 0x42db07b9 0x479493cb 0xabd2ead3 0xea6afa58
- 0xf994c740 0x4cb77f7e 0xb946cbdc 0xfe558e82
- 0xa2ed5c20 0x7012b99c 0x72a41e08 0x2058815b
- 0x0528d06d 0xe6dbd7e1 0x3d1f6f9e 0xca78b63c
- 0x91fa57a2 0xb6d524a7 0x1a61863d 0x89c25c5f
- 0x16960596 0x6ebed63e 0xfcd617d1 0x0a927121
- 0x887fdc75 0xec27c8de 0x8c91a821 0xd6bb116d
- 0x51fe2c18 0x4af774d9 0x7aa13fdb 0xfc6ff59d
- 0x27dd287b 0xe7e3151c 0x835552ea 0xe628aa1c
- 0xe0edda2a 0x1957ade4 0x52336fae 0x9cecef28
- 0x2be84cbf 0xa5959450 0x65299682 0x8151d4f8
- 0x716a5209 0x0a8ca663 0x2187bc46 0x000767f5
- 0xe7295b8d 0xa8bc7a6c 0x2b4d2f10 0xf251372f
- 0x92ff27ff 0x9bfd83e8 0x8e2b593e 0x8915fd15
- 0x1e44eed0 0x4a3a4679 0xce135f45 0xf996ec1b
- 0xfd86c8ac 0x25b008fa 0x8973cf58 0x481512ae
- 0xf2bc46f1 0x8b3a92bf 0xbf2a7b24 0xb19e88be
- 0x1823f658 0xa8486c11 0x237771c0 0x6f5f0da2
- 0xb05a42e3 0xb562583c 0xa13d37f7 0xe8eede16
- 0xc5154af2 0xfdf7f9b9 0x0b907685 0x1f567e56
- 0x19987b40 0xc82974ab 0xf02ae429 0x9c356634
- 0xb85ba9e9 0xda2141b7 0xd44e331f 0x1dd722d3
- 0x68fd2f4e 0x4e7f88a2 0xab7314b3 0x3dd05c4e
- 0x1bb4093f 0xff73db9b 0xf917c6e0 0xae822501
- 0x05cab9fe 0x67c91c76 0x1ebd2575 0x1ae193fd
- 0x6f154ae6 0x13780ac7 0x6ff5bf0c 0x6b664594
- 0x494a71d1 0x9bc35a0f 0xb34f175b 0x0069468c
- 0x9b125042 0x7df22e49 0xf39cf8ed 0xbe020df1
- 0xe206848b 0x8c428e75 0xc76c05d4 0x0089e2c4
- 0x5bf9a75a 0x30677869 0x544797ed 0x68456dbd
- 0x45b8f0aa 0xac5c82d1 0x05aefb75 0x6d5c28bf
- 0x009ddb3b 0x551ff144 0xd19127ea 0xfc860071
- 0x30c93457 0xa4c4b56a 0x6928a07c 0x9f63e6a7
- 0x9fa2b174 0x7c1b2fa4 0x4a5a1f25 0x24acb022
- 0x0c3c11f4 0xc7d4cec8 0x4484a031 0x6d3cc1c7
- 0x2eb86733 0x8cd4f77d 0x7b551519 0x124b6805
- 0x57385eef 0x3efd3da9 0xea300d5d 0xe64fc82d
- 0x7d33386b 0x3933c4d3 0xe3cb61f8 0xc6fe8846
- 0xbe0df669 0x8646e4cf 0x194a444a 0x404c81af
- 0x9448791e 0x586f2132 0x3def508a 0xa3edebe5
- 0x2f3b0b5c 0xc974f91f 0x400ec25b 0xf1513ffb
- 0xc13b8859 0x32ac4d39 0xf8f334b2 0xab53ba5d
- 0x9e196996 0xf14d8046 0x22fcb441 0xf27ac4c8
- 0xbbdf5623 0x255df428 0xd95a2352 0x8d26f0dd
- 0x60a301d1 0x4a2e3e49 0x4654b081 0xf775e35f
- 0x592b5eba 0x6a3f9583 0x6ec3d395 0xc8ab02e8
- 0xf343f806 0x62745498 0xb499dbf3 0xd427334a
- 0xdf0b61e7 0xda67999e 0x14f9be12 0xf164898a
- 0xd6347aa7 0x079a537e 0x294542e1 0x687b7b6b
- 0x8478cffc 0xf335963f 0x6c1b9ac2 0x68ff2779
- 0xe3d3f8a8 0x5453c548 0xd968189b 0x13ad95b4
- 0xd71bee24 0x3939f36e 0xb19b3595 0x001961aa
- 0x5f2f001a 0x77137eea 0x477698a0 0x1c07c440
- 0x9606b6d3 0x6ce95229 0x25445629 0x5a935f13
- 0x3e2154aa 0x6876442c 0xd9175c78 0xc94d2535
- 0xf2070dd4 0xd4d1f50b 0xa04d18e5 0x3456cfa4
- 0xc7610f62 0xb705a1a8 0xb8766e3e 0x225642de
- 0x4be5b1b5 0x44d32453 0x80b8a9d4 0x7297d633
- 0x09e8aa04 0x540929ec 0xbcc58c41 0x6dcf7b61
- 0x6992928c 0xcd40ff22 0x13e4a724 0xd331d5f3
- 0xa512aeb5 0x1c1c4ae8 0x5f0fe5d2 0x3d539538
- 0x383c214c 0xd0a983e9 0x977e8682 0xf38a571d
- 0xdb92de78 0x04ba543f 0xb531e880 0xfea55473
- 0xd6d17b05 0xbdd676ed 0xfc7d4f68 0x8b5170ed
- 0xa738734f 0x8a25fff2 0xb1b0239f 0x60545acb
- 0xcfb00725 0x35f58585 0xcce4ed42 0x05da1c3f
- 0x29428b1b 0x099680c9 0xb4608916 0xa9f177b7
- 0x3b393c9d 0x92d19426 0x472dfe73 0x7b12de81
- 0x557ec0f2 0x166fa28f 0xfb6855da 0x592d3e69
- 0x373a1dba 0x9c76abae 0x13c7f717 0xbc53e796
- 0xb2d39602 0xf1efa3b2 0x00046c93 0x1faf82fa
- 0x55dec395 0x22a034c8 0x576bd5f2 0x97c36a45
- 0x08a1a923 0x9ac2f22c 0xb029e4bf 0x6c4ca958
- 0xed7276cb 0xa0924918 0x1894c9d8 0xdb993c42
- 0xc31c6e18 0xbadc738b 0x57f95d64 0x4d766a25
- 0xea41493b 0x60c19727 0xe7c63d8a 0xcbc52763
- 0x7882b244 0xe2da61e5 0xd19111df 0x526d01d2
- 0x4e7021db 0xa13fb9fb 0x23e082cd 0xb426b603
- 0x9cac0cdc 0x44a94870 0xd0adbbe2 0x9b77a80b
- 0xe1845f75 0xa1704da3 0x2d1c6207 0xba3ee883
- 0x0c3089d8 0x0cba7fdb 0xcb069fb0 0x38738df4
- 0x89971c2a 0xfbaeb7e6 0x459e1365 0x45fba877
- 0x02046ea3 0xd9d0bdb7 0x83c74383 0xc248e9d5
- 0xaae85a56 0x33092ec7 0x6bece02b 0x3b7af1d3
- 0xc92b6e83 0xba032588 0x70e61198 0xa5eb1239
- 0x4d9a6456 0x7d3fe964 0xdb3eb780 0x7e188648
- 0x511a6402 0x48c4ade9 0xba7e9153 0x09490df7
- 0x11b5ea7c 0x4e63145f 0x07ca7947 0xc337360a
- 0x2b399632 0x5d1fef78 0x9b1e439e 0x8daa70b7
- 0xf55a59bb 0xc3a8c84c 0x4d18eb22 0x74568737
- 0xf0419b6a 0xbab459a5 0x0cb07a0a 0xeeb8e086
- 0x0a9241a7 0x419c5ce5 0xec841275 0x3ec13615
- 0x49e42b6f 0x2dae6c7d 0x3fc35088 0x1b92ff9e
- 0x573b1cda 0x54381503 0x29a5b7b6 0x82994130
- 0xffb93c4c 0xc0a66aa1 0x68889181 0x0826e555
- 0xe81cdf31 0x740109a6 0xb8835558 0xaa5d9aac
- 0x0d97ea3b 0x89f744c6 0x2b702162 0x992fe0ea
- 0xab3a585a 0x3e7554db 0x9d97ebdc 0x9939bce8
- 0x486a5f50 0x804ccd06 0xff2e15cc 0x67bf77cb
- 0xf9beadd4 0x2da33477 0x18adbaf0 0xdb00dae4
- 0xe727033c 0xd10ce1ac 0x4f8c4a29 0x281bf150
- 0x764e1387 0x8c65a901 0x841521e3 0x31d9dfd7
- 0x1e7ba122 0xe8fd6d3b 0x4bfe880b 0xd2c1c20f
- 0x9a07169f 0xedbb94b8 0xe9cbcd9e 0x33cac378
- 0xa42fef1e 0xf0e5ff32 0xa86b9038 0x7dbec0cd
- 0x7ad1abe8 0x5e3e4e8f 0xc4dfe8cd 0x86630ba1
- 0x02003c6f 0xbcb50d9c 0x65d874b1 0x01a09ddd
- 0xc97d3d65 0x2d02bedf 0x6fc63309 0x214b421b
- 0x72e0a28d 0xd9c8a577 0x1c8665a1 0xd33b4583
- 0xfa004d9b 0x5c2470b7 0xc671fed3 0xe033617a
- 0x5a86c333 0x13388e4e 0x3bccdcda 0xc62fd60b
- 0xcae17379 0xf6d84d27 0xaaa52422 0x5771e380
- 0xeb1feaf3 0x3c28e7fe 0xa0fded4c 0x5f63a3c7
- 0x3b42ed09 0x1748d617 0xbc2d4fd6 0x3416fabc
- 0xc1e60e41 0x48ffe41d 0x4ea5532b 0xba7dba76
- 0x21378ac1 0x7425d0f3 0x426b3153 0xdc57d14a
- 0x54997f9a 0xeda2a56a 0xfcec5ef5 0x6fd7acb3
- 0xf2691009 0xc1a219e3 0x09a82589 0xc6e1792c
- 0xb4674578 0x0aaf55d2 0x23c7e9dc 0x7607d612
- 0x580fc695 0xd24b2629 0x0a8726a1 0x3544e0a2
- 0xc1de7011 0x30982b80 0x9cf4f328 0x02b22d26
- 0x78e33c10 0x2ce6bb5a 0x92280ed7 0x2ce5b007
- 0x64552836 0xda4a7b51 0xa6122870 0x00b28bb1
- 0xb98cda46 0x84cbe910 0xeccb62a8 0xe13c3645
- 0x2f4494e4 0xed0da7b1 0xb8aa8a1a 0x1adcbc0a
- 0xdab03e90 0x904d9041 0xaa8fe377 0x087cf59e
- 0xa123b5aa 0x633c29c0 0x36d915d6 0x8f5cacbb
- 0x8834d1b5 0xa2c12731 0xfab5176b 0xe1888d76
- 0x4875b9d7 0x5747b32c 0x73fc6d36 0x202ffb90
- 0x62900e06 0xa5f2a41f 0x497589c6 0x7ec701fd
- 0x45801f09 0x1833e8fd 0x734acfc5 0x2f65bdb8
- 0xe6add84d 0x4ad6dfaa 0xf59dd63b 0xb2150e00
- 0xed32ddd6 0x370ce8d7 0x5fec9315 0xb8e6ba73
- 0xccb15a6b 0x302a0084 0x9e49e2ce 0x7af3bc8b
- 0x488e6ee3 0xcdbf0b31 0x762ce0d4 0xc50a111c
- 0xd07d6e3e 0x18c391a2 0x1a7a559d 0x10b4b3bd
- 0xd0703a3d 0x4e431eb9 0xf78edbe3 0x896604ba
- 0xc0e8d4c9 0xd42f2292 0x5414ea6f 0x0ce7d429
- 0xbb659e0d 0x46fa830f 0xdad39c12 0x0f65fa5b
- 0xa002e598 0x5408cfcf 0xc1c3a5e0 0x28ca35fc
- 0x52b2b588 0xb76e1f54 0xb6c355c7 0x08e3ba79
- 0xfd89c1f8 0x6ebf03a9 0x51ebb756 0x729e1c5c
- 0x1ed0cce2 0x29733f1c 0x42b76fcc 0xd94022b4
- 0x3efc8ac9 0x3f23eae1 0xa0ccf230 0x9da59cf1
- 0x5f6db360 0x922686e1 0xc9138d5d 0xda43fd20
- 0xe0757988 0xa315c62f 0xe3642291 0xc45d9701
- 0x2c394ee3 0xab92e7bf 0xf6037b8e 0x1f523243
- 0xe91791d1 0x19961c4d 0x35d3b069 0x1596143c
- 0x203bca40 0xd26d72c1 0x94c059c2 0xae0df468
- 0x3b0909a4 0x34aa916f 0xe0c254e6 0xd0969c55
- 0xa9b0b923 0x80a9dd5c 0xe79b8d8a 0x3599f269
- 0x623c20dd 0x41e11b9c 0x40fcee5d 0x65dfa8f5
- 0xbffa7357 0xa5b8f59e 0x2bb8191f 0x226a1b43
- 0x910b6d4f 0x73837092 0xd666f5da 0x14fd4426
- 0xd41a8547 0x6f4e928d 0x8096c2f2 0x525ba180
- 0xc6a28d43 0x960b7cb0 0xb76dacbc 0x024de046
- 0xc8e3c937 0x0217493b 0x1516dc22 0xe19e70d0
- 0x655321c8 0xa46a9105 0x61ec2a61 0x1400405b
- 0xcd0a758d 0xdc792982 0xbd994932 0x6565c8b2
- 0x187be349 0x0afa44ad 0x714870fc 0xede1b8dc
- 0x2c4ac6b5 0x7d9793ea 0xe0bc3c0d 0xaa56f23a
- 0x7fd4e2ec 0x2131ad26 0x2cd34428 0x45e9dec0
- 0xc15b692a 0xae73e713 0x37c5c3d4 0x70ff213c
- 0x4d6322fe 0xa29a9b4a 0xca7d3c65 0x1024df74
- 0x308f4a3f 0x4f48c7d9 0x0c71a17b 0x540441ed
- 0xbc2f36a8 0x2592d7d4 0xbb643dd3 0xb8fb607b
- 0x6b2b339b 0x9a40ecc7 0x59226bdc 0x42a5c04c
- 0x6a1dc320 0x14e3c7c4 0x39cb912c 0xcf5eb477
- 0xa3a43975 0x79f92cc3 0xe9d4cdfd 0x02dc8fb3
- 0x240b6842 0xe9ff7bed 0x8f5269b3 0xc4f44baa
- 0x1f1c74b8 0xb5c39051 0x291cce82 0xfc129a8b
- 0x0fae02cf 0x31b4d4cc 0x1dfe9722 0x093cd430
- 0x96c2a838 0x19b3a068 0xa7ead8c3 0xa2b3b92c
- 0x2e1dc49f 0xe2f84217 0x670e73d3 0xd7c3710e
- 0x94e4a7c9 0x33e063ab 0x35176206 0x910504bf
- 0xb04b61d3 0xbed9c702 0x5d6c4cc3 0x63276a86
- 0x0bfe5143 0x7ed925a1 0xc455934b 0x402a8b04
- 0x01c03292 0x5de0933c 0xd932d260 0xb5b3b5ce
- 0xde53664e 0xeaec4fc0 0x506030ac 0x6fbd8304
- 0x0b0e4881 0x99c16b3a 0x6fc976ad 0xeae57df9
- 0xc53a953c 0xca681bc7 0x905e49e1 0x405d42c5
- 0xef39b878 0x57ded0df 0x56b98e32 0x392ce7d0
- 0xaa7fbfb5 0x6ff550e8 0xf346ae82 0x2b25a8dc
- 0x3ff980eb 0x302aff14 0x1a43c7ae 0x23f8ec16
- 0xf774024b 0x1c4e163d 0x6b6f9408 0x0646b4e5
- 0x2e55bfcb 0x14e3f7bf 0x86fec07a 0xda898470
- 0xd99a274a 0x8630e98f 0x8c843f0e 0xa840c028
- 0x950d7fb1 0xeca930fd 0xd281c9e3 0x29b3aed6
- 0xc419314d 0xa6147b28 0xb504311a 0x91c07531
- 0xe19ac720 0xfa8cfb5c 0xf8158bcd 0x42202a1d
- 0xfff43b87 0xdc6fa0d9 0x8a599eeb 0xac3a8df2
- 0x83ffa50f 0x346a8ff1 0x0947d1ca 0x318a8949
- 0xe409dd30 0xf73ac9cd 0x9504c972 0xa2392b4c
- 0x5594ac9f 0x7a45c3e8 0x181d42db 0x085e24a9
- 0x6cb3e60b 0x3568d771 0xfa96b628 0x945817e8
- 0xca9d28da 0xcd3a174b 0x7f84ca3d 0x90381d0e
- 0x09a6f9d7 0x11396376 0x4d158586 0xcc451745
- 0x9844225c 0xa45b8a9c 0x0c64efde 0x7429ee29
- 0x308c39b5 0xa3454fb6 0xf949f709 0x09391206
- 0x0168257e 0x94e10cb6 0x48e49996 0x92928443
- 0x4a826036 0x9a777b3f 0xf77adfdf 0xc111b354
- 0xa7ece533 0x050706ac 0x91ed3fd2 0xca15baf6
- 0xd1714105 0xb564c842 0x886800cc 0xd57309e1
- 0x38e4fa43 0xb74fe550 0x26f300bc 0x6349cbe6
- 0x4bc132ae 0x310c1d40 0x3353100c 0x0a308892
- 0xea6ab62d 0x0a438e7c 0xb000cf51 0xa21aadb3
- 0xd3628343 0xee7f1a6f 0x3ee28d91 0xa846f25a
- 0xc898e7c0 0x1198f67e 0x2401caf3 0x78d7acfc
- 0xbc592220 0x1efd847f 0x1e3e935d 0xdb9025f6
- 0x41ab6bb6 0x08a10f85 0x160dc5b4 0x4f0ed74e
- 0x8c3db59d 0x34034397 0xe26017c3 0x03fe3b41
- 0xc4480582 0x7c0c85de 0x4957c26d 0x9eb32143
- 0x28676ce2 0xe3627f34 0x71e3afb1 0x7e978fbe
- 0x3b3ee0f9 0xb5ae1bcf 0x474dc4cc 0x470e2114
- 0x2490e60c 0xbb534e7c 0x7a8ad252 0x7cc08810
- 0x9ea23718 0x04ecf4e1 0x732a9f10 0x62c69e22
- 0x5a94fb4e 0xc1da497b 0x3ab3f2b9 0x09ff7310
- 0xd7749df9 0x170471dd 0xaa551e91 0x2d605856
- 0x66a13f75 0x0be4b8a2 0xe64a0c3f 0x288e5671
- 0x5ee690c8 0x9e1c4b10 0x9f055568 0x8c6ff177
- 0xa7229231 0x19e678db 0xd90be83f 0x0cf70d67
- 0x47462463 0x327fdd91 0x51986170 0x3ad883b2
- 0xa32fa5f2 0x82167691 0x74b6c59e 0x3eae0a3a
- 0x569386dc 0x6d67fc33 0xa0943958 0x40b2939f
- 0x334acedf 0x91b6a866 0x5debd880 0xa6f3712d
- 0xbe8ca5c8 0x4b43fa68 0x72b677d7 0xa42b4d60
- 0xc719163c 0xa469fbb9 0xb484def6 0x508ddfd1
- 0x23bf14bd 0x857a13ad 0xf7a47090 0xe6816794
- 0xbf6d3db3 0xd19fe091 0xb9421e39 0x35b184c2
- 0xa5c94a6c 0x13b2b25c 0x5c7b45cf 0x648fdd47
- 0x8832d949 0x0e2380c2 0x2f8e4f88 0xc01022aa
- 0x4dec89bb 0x0a2c5bff 0xa97e58f8 0x304dddd1
- 0x468828ac 0x603da881 0x646ddc90 0x1afa151b
- 0x985bf8ad 0x6e3635d5 0x181268c6 0x420e1647
- 0x913af569 0x14075a17 0x803aba15 0x2a2562b7
- 0x2f0627db 0x52785b48 0x36ce7fc3 0x6057349e
- 0x4affb11c 0x84e82be9 0xa0f60f66 0x1d176256
- 0x9f1dba85 0x2852129f 0x4592540a 0xae083e7e
- 0x744edf82 0x75a1e1b7 0x518fbebc 0xf1828d15
- 0xfa1e31b7 0x88ebf51e 0x0a648385 0x956c002d
- 0xc8b660cd 0xa82eeb58 0x0754bcf9 0xc4873df1
- 0xf06c843b 0x7e5ac181 0x59661ea5 0xef2ae542
- 0x0fea9691 0x9493a352 0xb401f705 0x85573914
- 0x4e1eefc9 0x45e51c5f 0xd713688c 0x97efca3f
- 0x292d0e73 0x8db44fd8 0x9f4479e0 0xc049ff9a
- 0xfac5ddbb 0x4d610fdf 0xa9e01cdf 0x93b4dafd
- 0x925004b9 0xb0796ea4 0x7e166ac1 0xd030c4ea
- 0xa9f34c73 0x276cbadb 0xf3b9c282 0xa5bd6a69
- 0x53df3f11 0xded46173 0x70bff329 0x0ddd0e77
- 0x52e4a782 0xf01b024c 0xda90618a 0x34a2dd05
- 0xc144d1fe 0xbaca12a5 0xbbd28cf1 0xc54d84f5
- 0x0e7cb67b 0xe009e900 0x23657441 0x2214b4fe
- 0x37693ee7 0x62e093d0 0xf79ca670 0xf1bc6cec
- 0x1b91f787 0xc9d234c4 0x2a193a4c 0x8c2bfaf4
- 0x75f4514b 0x03501d9a 0x5554de35 0x5ff35a26
- 0x670ad976 0xbc8151eb 0x725fb971 0x5768e86f
- 0x7fdcf5ad 0xe814f3ce 0xe8b9510a 0x55bf074a
- 0x415fc288 0xa1a360c5 0xf5fef671 0x2d6253fd
- 0x7fa09b81 0x2bb2e018 0x7159e648 0x10d5d59d
- 0x462047cd 0x77583e64 0x47f1074c 0xc3c0e0d3
- 0x023a55b5 0x4ad55057 0xe6d4b9d2 0x9cdd844f
- 0x87eff8f4 0xd95c1e55 0x7499004e 0x2a43a598
- 0x0c1472b4 0x33c90a5c 0xc4703c62 0xf293e2d9
- 0xc3153c7e 0x6eeffef9 0x115e14ec 0x4ad27157
- 0x888d87c3 0x33edc70f 0x7c38ce66 0x61c10a52
- 0x5db41c48 0x8e309060 0x7b847b63 0x6b619cd1
- 0x12855e03 0x52c3281e 0x704f969e 0xf9ab7862
- 0xb143fc54 0x1ac23fd5 0x89dcd807 0x40a7ffc7
- 0xc84245b8 0x0248d94d 0x29aca158 0x92d7b241
- 0x751588ff 0xe8203587 0xc5bd7cdc 0x9de82608
- 0xb075493c 0x5d43c228 0xff6a5345 0xa64cae5c
- 0x4a1a9a26 0x08c60b16 0x9399ba46 0x3f535d1c
- 0x3b9a6ab1 0xa446115c 0xa77bd99c 0x2431dc72
- 0x729a637f 0x13f960d4 0x230d4e9f 0x0c608153
- 0x9b9670fc 0x72494838 0x14832ade 0x65aba892
- 0xd6434455 0x17697982 0x68b9bb34 0x1d700b3f
- 0x6d0dda39 0x30e0d15e 0x87de41fa 0x9fc55b16
- 0x0f5730d3 0xc3ea8127 0xeee64f5f 0xa02c5baf
- 0x64e18d74 0x31de5660 0x5cf8d724 0x6c07ceca
- 0x409e862a 0xd4ee7999 0x90c22c99 0x59cd395f
- 0x09c36563 0x1993b09f 0xb0c4e064 0x8d6870a5
- 0xe2e8e337 0xe8bef0cd 0x708d869e 0xdf808519
- 0x6fa61e32 0x27161ea8 0x063c783c 0x2aa55c1a
- 0xa6fcc8a3 0x918b284d 0xbb7870b9 0x788102c3
- 0x3e49edfa 0x6c5eae4e 0x1c9fc361 0x554ca60b
- 0xa08364d3 0xa7bd4442 0x204822a5 0x000b71a2
- 0xd4dff005 0x43265901 0xbdb99200 0xc438e254
- 0xa4982e58 0x02812101 0xfacbff1d 0xeec56aaa
- 0xa5525774 0x21ada574 0xffe2f703 0x15d30ea7
- 0x600696f9 0xc7ff3f59 0xdb57c175 0xa16f78df
- 0x54a15622 0xe3742dcf 0x06d32994 0xd48463a2
- 0x44c7c25a 0x41d6ded1 0x3b314de0 0x09992482
- 0xbeb183c5 0xa0a65c27 0x842075b7 0x9b97e3c6
- 0xd9545fc7 0x16d00629 0xd85640df 0xe79e694a
- 0xe818d277 0x1c3d4623 0x23a9a926 0x83ac1b3d
- 0x39e890c8 0xb3738b84 0x54b772ef 0x74518f0c
- 0x7190098e 0xe26aff75 0xf6237011 0xbd3400fe
- 0xda1b8fa6 0xdbf5566b 0x5155cef3 0xddbf1973
- 0x34e2cb2e 0x535fd6b8 0xbfd337aa 0x6dd1fb0e
- 0x52b04fbb 0xab5eca05 0xdb740dc1 0x104e6131
- 0xbf4dcb75 0xaeff3524 0x4257c6b9 0xbf1c8cbb
- 0x0a69ed82 0x90d991c7 0xea075cba 0x5e3c8330
- 0x823116f8 0xba8f8a2d 0xcb98a1e9 0x8b2655c6
- 0xd2f11133 0x3422f3ba 0x3e3a5742 0xdb9714fd
- 0x91701f60 0xeba19983 0x8bf9f157 0xec87cd03
- 0xb63260fa 0x207c345c 0x0c838d5a 0x736415ba
- 0x9638ab07 0xb32c72bc 0x304d191b 0x7775adc8
- 0x57ece662 0x0467bb66 0xb7cf80e8 0x4c635024
- 0x176946c3 0x29cba0ae 0xf214b3f2 0x6e727126
- 0x87b3747c 0x4c19b86b 0xfcc66fce 0x86681713
- 0x636387f1 0x589e78f3 0x2e8abf1c 0x22c828f7
- 0x99653c62 0x8e3bd31c 0x79187a73 0xc6d0e5e2
- 0x8005a045 0x78a38c60 0xe1e8ff4b 0x1102d320
- 0xaaf4ba7a 0x7223d041 0x45f73e81 0xaf7168af
- 0x218ab3ae 0x8b1956a7 0x4db00173 0x482c3bc2
- 0xd982b945 0x4bd7757d 0x0c5ef18e 0x74e66de3
- 0xcf421ae1 0xf2ddc098 0xcec27e0c 0xe79e711c
- 0x6f76e136 0xa8d72245 0x196390a6 0xbf56633d
- 0xd1156298 0x5712cd8b 0xaed801ae 0xa345fab5
- 0xfde1ba97 0x437a0b29 0xfc5628a4 0x93acf698
- 0x83ce0bff 0x212f15c3 0x723ef016 0xe793bd50
- 0x8bc51b39 0x42f17ad2 0x1df73878 0x19af3c24
- 0xf55b6f93 0x506138d0 0x164c542a 0x8d4e1a26
- 0x6c606f83 0x6fbebdf5 0x0e4ad76e 0xabd88e6b
- 0x0e0d74e6 0xd139e08d 0x8b6cf03b 0x04a527b1
- 0xe619c7a8 0xbf0d57f6 0xb38a5f5f 0x3f328013
- 0x374c0a9d 0xff36910c 0xe950a494 0xfc477720
- 0x37bd9390 0x4667497e 0x724eb66b 0x86bda8f7
- 0x52efc959 0x32d5c2bd 0xddbb49ca 0x9c1eef2c
- 0x508d8b81 0xc33d7001 0x360ae3c7 0x1197f6c2
- 0x25efc933 0x4ad234a5 0x9e9c8658 0xc16d4aff
- 0xbc428573 0x30e8b4c0 0x728c2c48 0xf34e1e70
- 0xd62187c5 0xca869f89 0x34685a33 0x85d9b877
- 0x9f77605f 0x93724d34 0x5fc8e8d1 0x70dd81a6
- 0x643e543b 0xe4ad6c73 0xd6b4e5cd 0x387519c3
- 0x719d8c6a 0xb2e0565f 0x02235c90 0x230c9b5e
- 0xe76841a3 0xc2833be0 0x4dab4a72 0x0ae6c0a9
- 0x0b5e12e2 0x4cda3610 0x954b6ff8 0x6d89a683
- 0x3583e633 0xdc540da7 0xe2955deb 0x0f290d9d
- 0xb01e57c4 0x977f4588 0x24b95f0c 0x45529128
- 0x4528b5ee 0x27511439 0xd088d9bc 0x7c471853
- 0xf03b8455 0xbda4a828 0xf49736df 0x50eb17c3
- 0x2affe0e6 0x6727858c 0x6500b8f0 0x0483aa89
- 0x0e1f6a41 0x72666733 0x85617ce8 0xa0c86838
- 0xbccd2eed 0x06e8462d 0xc947bf5c 0x4d2d0a53
- 0x02e70008 0x5039a596 0xb0118cc1 0x690ba325
- 0x057ca95e 0x032cc1ba 0x3dae2c88 0x4eaa740e
- 0xf07b09b5 0x6b2c2135 0xeca746b7 0x76019533
- 0x4cf477b7 0x31848299 0x6b5c7df9 0xc0db5ff1
- 0x7cd3e08d 0xe25fa562 0x260d66a4 0xda30cf2c
- 0x14ab6c70 0x029a8dd5 0x7cd5fe2d 0x98ea5852
- 0x555cf635 0x6c72ccbd 0x64120bef 0xd9e19613
- 0xf26ac6e8 0xafea03a4 0xc14a11d7 0xb2f8420e
- 0xe319634a 0x8a8fedd9 0x6ce0da89 0x74269f31
- 0xd7e0d776 0x86ae9513 0x48bdea80 0xb2e4c581
- 0xab25566e 0x9ccb71a5 0x7cedb09f 0xd2bdade6
- 0x39c96ad5 0xe8ebbeec 0xac8a2e2a 0x915be930
- 0x95e7c98b 0xd00e1d3b 0xdacd08ac 0xd9f515fd
- 0x45cd3946 0x828a2cc3 0xfbe1bd9a 0xc5e1ebcd
- 0xac69128c 0xcd6423ba 0xd8653b60 0x48f0614f
- 0x0c1ebbbe 0x7ab89792 0x9a4b0097 0x2bda854d
- 0xf17ab2c9 0xcde54eb9 0x4b53a030 0xe2399c4c
- 0x19454a2f 0x473fe390 0x3a42c16c 0xc4c106a9
- 0xf5d96e73 0x2ab4078c 0x5d20e7ba 0x47880aab
- 0xff5e0d78 0xa374bdc2 0xc17109ea 0x39fce648
- 0x00821cbe 0xc54a60ee 0xd753386e 0x7b28fc16
- 0xb6309bbe 0xaefd0548 0x41168500 0xee5989a3
- 0xe0177f09 0xc9fc9eb6 0x09a6e188 0x45776a0d
- 0xf19a4830 0xc6774893 0x814b2e43 0xf8be5e3c
- 0x22fa8237 0x75c98f46 0xb1c52edc 0x443d54f8
- 0x6a1a886e 0xc7f33598 0xaa794644 0x685e5ca2
- 0x97a735ba 0x3c1a391c 0x13f6f89a 0x660d7041
- 0x333c3eef 0x40541bb9 0x5c3724d5 0xc348023e
- 0x89791dd9 0xe72fba89 0x5af98b2c 0xb534fd29
- 0x64d0e6b1 0xa578e77f 0xf311215e 0x634cc8cb
- 0xbc534e51 0xdfce3ac7 0x90f88f51 0xb3f7dd48
- 0x20b3e0ae 0xf4456e85 0xacb3925b 0x2eb3ce78
- 0x37e61d82 0x724b9cbc 0x1462d9c1 0xd3f49dc4
- 0xc1ffcc00 0x7c3e3f86 0x6f283bf8 0xf43671ab
- 0x90cbfb35 0x55390829 0xc8fd0d31 0xc687c45d
- 0x724ee656 0xfc1eab3c 0x3c8c2f04 0x3caa3af4
- 0xbe220358 0x4d5b49a2 0x12cf4893 0x867173fb
- 0xccd4b513 0x7c94a1bb 0x86c42c18 0x2b2070f3
- 0xd2a70638 0x9d7c07e3 0xd02ed59e 0xd349488f
- 0x1e85754d 0x333db889 0x0d0defdf 0xef282e45
- 0xac3f6c29 0xd65a68d1 0x5d0914e4 0x395ec78a
- 0xb056aa6b 0x4d98d059 0x7ae08f88 0x25c923d2
- 0x79670f38 0xa881d62f 0x89cd5015 0xfb01da43
- 0x5861244c 0x05e201eb 0x41d71eda 0xb2babb53
- 0xc3845fb3 0x1f3b5c56 0xde6c10ac 0x73adb998
- 0x714aac3f 0x4ad9fc65 0x3acdd014 0xeb319d58
- 0x48842806 0x47ec1040 0xbfdf0052 0x3c478ec6
- 0x83b43a0f 0x9e727e69 0x9f4d5925 0x9f45c13e
- 0x30b8572b 0x26edf8cb 0x577e8b9d 0x9b98d7b3
- 0xa44a9bbb 0x903e39eb 0x51226dbc 0x933a52b7
- 0x14c6dc86 0xbc24db59 0x21054454 0x98fc5fa6
- 0x2c9d8606 0x19178173 0xeda24205 0x90dfaca4
- 0x21d562ad 0x7e3ad05e 0x2b3a40a4 0x46513f35
- 0x0d13a598 0x8bf71ca2 0x6a36c430 0xe66f5587
- 0xc9f13bd6 0xb6534a8b 0x8a3fbfd6 0x38cdfe6c
- 0x1a1c89f8 0x6d782709 0x7919c451 0x6ccc96fa
- 0x334029b2 0xa638356e 0x001e709f 0xb2132b06
- 0x483f1933 0x189ab8f9 0x4ba0ec13 0x490aee0a
- 0xda63f1fc 0x5679d38a 0xcf1e92f3 0xe7257fbe
- 0xfeb733d7 0x0704860a 0x34ce2032 0x663b948f
- 0x544cc928 0x8c23d5aa 0x67986469 0x93f9ac08
- 0x4fa9a13f 0x9eb311d4 0x41a64161 0x29d1050a
- 0xa5285c24 0xb53d03a6 0xc5de26f3 0x7876d1c5
- 0xbdcdcb4b 0x79d1196c 0xe9890732 0x3e58a8c0
- 0x874f03c7 0xfdfc9cac 0x5d57fa57 0xa3ef01df
- 0x47bcff48 0x8beb1aae 0xf4bb4f9b 0xa5c83b64
- 0xd69ab0ce 0x40f6691d 0x2eb8fb7d 0x22640f8d
- 0xac1ba157 0x3687d705 0x7fac8727 0x4ad75cd8
- 0x7016d2e9 0x25c36c08 0x7e4248ea 0x292bda19
- 0x2acf589d 0x0ef7726d 0x835f9e62 0x3f9a1973
- 0xbb6d2588 0x078ff6b4 0xaec22b5d 0xc740501e
- 0xa2ab115a 0xea993e64 0xa0cc3ed1 0x934e4e0e
- 0xd732b66d 0x5fd28c47 0xe4ccb898 0xc6a101c0
- 0x78274bae 0x625df6a1 0xaf774052 0x3b7c08d2
- 0x6180ac39 0x3e5aa769 0x6ec74578 0x6b5d27b9
- 0x98e58a17 0x119dd7d4 0x39429c5a 0xe3d5b391
- 0xbb8fddb8 0x5929801c 0x68cef71c 0xc36fa301
- 0xeace4850 0x29f4f97d 0xa58bad79 0x2823998f
- 0x0fe1352b 0x5960ded0 0x69308816 0x0d7e33c8
- 0x2fb13bfa 0xff6a326f 0x69cb631a 0x839ea2a1
- 0x528a8065 0x34cbebfa 0xd4432cc4 0xe13b550b
- 0xe046569f 0x87b41fb1 0x7751107c 0x0ef6e60b
- 0x856ffc50 0x11995683 0x77c2ebf1 0x4dec97f9
- 0x3a28ebc0 0xb7bfa04a 0x40cdceb0 0xd559dd06
- 0x61c2cd6a 0x8a906fa2 0xd55f43d6 0x7fb3ac35
- 0x8cea4e81 0x1d359c2e 0xec447c57 0x3414f7f1
- 0x18243b84 0xdf76849f 0xd753044a 0x7af2d51e
- 0xaee26ecc 0xae6946b2 0x7478c675 0x88b22f49
- 0x4de13fc9 0xd35c5956 0xeebb60b6 0xa15b1736
- 0xa6e78d78 0xfd5e30b3 0xb4fade2d 0x964eb418
- 0xe9035f51 0x22ab8242 0xfaa64053 0xdfe03834
- 0x47beb588 0xb82a0887 0x11182e85 0x2f2f9a67
- 0x4b612f11 0xae04077e 0x7f783c25 0x883a34e1
- 0x32d43beb 0x6f0536f7 0x85c1537e 0xfb26199a
- 0x45417e88 0x4af2c8cf 0x0a334486 0x2a3e6838
- 0x31b8725b 0x63d64541 0x7e516a0e 0x7e42e766
- 0x4cf30198 0x68abecff 0x7fb49c43 0x8f5b558b
- 0x32b99abe 0x67337248 0x224c3411 0x4e7c41b7
- 0xd3aee3a2 0xca19e704 0x2a430b7d 0xe9aee453
- 0xf4ce492d 0x48fab2a9 0x42ec2076 0x0182cea5
- 0x8a6373c7 0x18f41b5d 0xdd062fd5 0xb1db44a7
- 0x285ad917 0xeaaabbd1 0x359b1b23 0xcc123c8e
- 0x38b70cb9 0xb01ae722 0xa6e72010 0xb647530e
- 0xf9651d41 0x366d6d0f 0x4b656a6d 0xd36637f0
- 0x4b5ab8bf 0xc22fdb1e 0xc57c8250 0x799f4e60
- 0xb55bd50b 0xe8a3432b 0xe752e4e0 0xd0c86482
- 0x122991f1 0x5bec598e 0xbcb89abd 0x739f61d0
- 0xd230ae2a 0xd0b99c05 0x2a998a6d 0xab715831
- 0xb7dd1939 0x57db0ea7 0xed1f4952 0x49274caa
- 0x35e319b0 0xed2c9cb3 0x601caa20 0xfe782688
- 0x64b6d30b 0xcd5c325c 0x2c836157 0xa3552f79
- 0x188094db 0xa42dd7e8 0xc09c2dda 0x02d98d8d
- 0xed270d28 0xb0f38ada 0x5d7b4261 0xb41df8d8
- 0x7341b6ae 0x024ce90a 0x0727ae4c 0xa8dd3a0d
- 0x390f84d5 0x43f5bd12 0xd11fb61f 0x6fc330e1
- 0x7f2d7fa6 0xf758a4e0 0xceb1f3c3 0x2f341836
- 0x98fb470f 0x5bf68e58 0x1917a5b2 0x75f33be6
- 0x16e22316 0x8aa810a0 0x1fc6c9b2 0x22179249
- 0x3de701e9 0xec48d8b6 0xe85248c1 0x314ce9c1
- 0xddeb2f47 0x0187909e 0xaa755f62 0xb2019460
- 0xb2016a9c 0x91f789be 0xe5925997 0xe4864300
- 0x1fd13759 0x0ad97c1d 0x7cf08c01 0x7eac2dd6
- 0xcf61a7f3 0xaf9e108f 0x939a2fd9 0x0cb48e78
- 0xe6ea1a8b 0x0b968273 0xef1c9310 0xf60e82b7
- 0xe76e9bed 0xb8fa9668 0xf889765b 0x0e51eed6
- 0x6b6566ea 0xa8f7e2c5 0x9d8c283a 0x879afdcf
- 0x944873c5 0x58afcfa2 0x2e60600e 0x59666667
- 0xc812b833 0x5842d0be 0xdbdc0829 0x786bcff9
- 0x5857ba06 0x6968c729 0xf5447949 0xdb1ceeb0
- 0xaf04d1f5 0x30614f7f 0x3e80fdc9 0x8a6e1ce0
- 0xa267d7d5 0x8896143e 0x24e59072 0x68122e1d
- 0x3ce24add 0xda677bdc 0x8c3f74ef 0xfa60e825
- 0xf5c136cc 0x2cc5f249 0xa1c6b642 0x47a2305f
- 0x52cadbc8 0x4d0c32f6 0x07f4d344 0x1f496d59
- 0x5699b970 0xb8cbe564 0x707f7a2e 0x818bfd45
- 0x800a8be0 0xd3de4f1f 0x62de0a3a 0x6b342869
- 0x054daa7c 0xc72b945f 0x1612f126 0xdb4ad492
- 0xa28c467b 0x78542799 0x61607353 0x39f1c142
- 0xebf30ad6 0xabe076d0 0x5125cce4 0x5584149c
- 0x65fa33f4 0x878a918f 0x8c7e5c37 0x334c4284
- 0xbfd816e1 0x0f0f3460 0xd54519fd 0x03701ca9
- 0x64885229 0x00e841d0 0x756a9472 0x0c16c5f6
- 0x65560e81 0x129b6995 0x91c9dd1e 0xe9730dae
- 0xce47f2a2 0xead8a0ee 0xcd58078f 0x7ca2df31
- 0x0ebbf13d 0x3c74e061 0xb7f3980a 0x0d354b88
- 0xfd8db90c 0xec6726d0 0x6bfce0f5 0xea98b7a0
- 0xac5ddde2 0xb372a14c 0x47b09ed5 0x531bd5c3
- 0xcfaf5a0a 0x51d6394f 0xe9efdfa8 0x37c79445
- 0xb13ebf62 0x46715efb 0x31e6a0d7 0xfa48ab48
- 0xc6552f2c 0x3067b978 0x0afa4ab7 0xc2c17055
- 0x68dd427d 0xeac01e43 0xe90f12d8 0x6d97c3b1
- 0xe0d339b0 0x2f3c84cd 0xca3eb3b1 0xbc0d86e1
- 0x3566f657 0x083374b0 0x199c677f 0xa4a8a4d3
- 0x224dd5a8 0x8f304abf 0xe1019878 0x9b290d4c
- 0x5cef7341 0x59ff7e48 0xc91663ac 0xb0b1bede
- 0xe9d8a9a5 0x8f34cb70 0x588d00d6 0xb7fe69b6
- 0x29036caa 0xd21d7998 0x4edc3ee9 0xdbd94f37
- 0x99c63455 0xac94efda 0x545635dc 0xb787b5e1
- 0x8228666b 0xc7cd8170 0x4f1924a5 0x437884c1
- 0xfa9236fb 0x1f0f949c 0xd1dc0597 0x56082a24
- 0x04e51919 0x05dd926f 0x06d264ac 0xaa672d38
- 0x5a3e396b 0xab48a57c 0x53489bd1 0xb36b3ba2
- 0x55164db6 0x5b52c5f9 0x68aa8b7f 0x922ce829
- 0x09e6e5bd 0xbc488a86 0xc0fb6dab 0x98e7754b
- 0x4c9ad717 0xe3ae7045 0x0b498742 0x80a4384b
- 0x0dfe0b99 0x70eab3b9 0xbee30b9f 0x4237ca85
- 0xe67662b1 0xdae3dce5 0x47c84a45 0xf72febf2
- 0xa58dfdc8 0x77ae88d4 0x038c76b7 0xae699990
- 0xf5f10de7 0x65d4c59a 0x004a8b4b 0x67c788ec
- 0x71c918d7 0x0ec70171 0x7041de53 0x43591e1c
- 0x807242f8 0xa27fe146 0x0055fc7e 0x2f08467e
- 0x5e04a068 0x54dab094 0x4f6e8c7a 0x20ac2825
- 0x47949a42 0x9181486c 0x038e3132 0x7c1c51be
- 0x97544f38 0xe2d27588 0x64889c21 0xdad9a1a9
- 0xf1d328a4 0x7d47991f 0x2faa1b85 0x2430cab0
- 0x0e849f91 0x213686c1 0xa2635f37 0xee7983ae
- 0x87871273 0x6867d60f 0x04cb29ae 0x4e0ee4ee
- 0xfbd2666a 0xfd7fe017 0x870b26ee 0xc42e104b
- 0x78919117 0x19590e66 0x9e1a5039 0x9609471b
- 0x4057fde6 0xc1f27544 0x30af8a8b 0x2ea267a6
- 0xcfd886b6 0xe632b1f3 0x3f10bc50 0xf38a1bd8
- 0x7ae1e284 0xe3876d7a 0xb4ce64f8 0xf74b4100
- 0xa97686da 0x17ebacde 0x2ab068e8 0xcebd1076
- 0xee8f81d8 0x0d394301 0x6f32c277 0xa926dc1c
- 0xd5d2ea55 0xdc016b6b 0x6a96022f 0x0143e314
- 0x23836eed 0xa3e18369 0xd2a155bd 0x8022cef6
- 0x080b32a8 0x74ba38f0 0xd1ca2089 0x7c80219e
- 0xf536af16 0xd7a337e3 0xa33600a6 0x39c7754d
- 0x7d215312 0x1dd65026 0x8cb496c7 0x89dfd508
- 0x9f945a1c 0x45caec32 0x020a1edc 0x5917baa3
- 0x296b4b1a 0xcfaa2023 0x63e7a0e5 0xc48b19ae
- 0x78d98b1e 0xc5d6be01 0xfe4ef13d 0xea6c9915
- 0xb8190f09 0xf1793822 0x9acf1593 0xc7710fa0
- 0x6b9a9f3d 0x0220ee2a 0x5d63043d 0x7292a0d5
- 0xba9a1682 0x6f1e7c19 0xed7cc52e 0x6bb89645
- 0x4370269c 0x9cb2c1a1 0xa7135973 0xfd1f3bbb
- 0x50e6eb67 0xf2b9bd22 0xd891f6a7 0x4e0a7449
- 0xc3dc0005 0x878e3333 0x3b4b8686 0xb215c65c
- 0x5d8d24c0 0x8d203496 0xff20d243 0x0a6c1253
- 0x2385c79f 0x52e8d6dc 0xda4bb8b7 0xfab66d97
- 0x05a4a795 0x6876e856 0x9dabedc2 0x53550c20
- 0xb3bba16e 0x853bf1cf 0xb85b906d 0x3f374468
- 0x62e07c2c 0x6903a495 0xdb119586 0x07e91546
- 0xa8388945 0x5a4e1dda 0xf054cdad 0x4b052880
- 0xe9bbc9ec 0xe3555e11 0xd4d6479a 0xcad6a986
- 0x31d9c4ae 0x510ff951 0xcb2f3164 0xbe283401
- 0x0c390b9e 0x0c9cb487 0xe64e8ffe 0x611a63c0
- 0xa1d700a5 0x3f864335 0xd1fdf32d 0x7a3aeb09
- 0xabbc8c4d 0x4d703604 0x6532c8e7 0xccebc529
- 0xf3c0f514 0x1567f19d 0x591abf6c 0x6c7fc459
- 0x0858b061 0x092b2489 0x33c1a9cd 0xd6cc8e2e
- 0x7c1ffeb3 0x3f45cf40 0x1fbcbd39 0xc6f0e628
- 0xb88bab4d 0xc699de42 0xb62d850c 0xf71a6768
- 0x2866b891 0x13093fcc 0xc730c502 0x2deaeff4
- 0xb1bc8535 0x4303997b 0xb31ebd2f 0x82debe94
- 0x843fa02d 0xba29f80d 0x03cb58c1 0xef1d2017
- 0x0b5aadf0 0x6c5c3286 0xf084faeb 0x8b96a39b
- 0x67cb38f8 0xf686ee62 0xbfdc22a1 0xee3f779c
- 0x8ec73c8c 0xb448536d 0x67bb5d68 0x4369ea8d
- 0x4b5367cd 0x2dbbc0be 0x8f5986e7 0x798c8392
- 0xd3aac078 0x0081c0bd 0x94d9d70b 0x40bdeae8
- 0x6b528e89 0xb0713745 0x063e535f 0x7d696463
- 0x64f0666b 0x68a82e8c 0xc749dd19 0x875883cc
- 0x3d35728d 0x4c0e5d8d 0x135f11b3 0xb649b37f
- 0x8aead5cb 0xdfbd573e 0x563bf917 0xcdb75f08
- 0x024b93fb 0xc6477eea 0xd88ce51d 0x95f7d77f
- 0x0b561446 0x2fb6992c 0x4b48c8b1 0x940da60f
- 0xf1be60b9 0x66d8641b 0x17a0ce15 0x49d22f40
- 0xb8c494da 0x91930bb1 0xcd317991 0x4c5b4c23
- 0xafda60eb 0x212c9f04 0xe4732f4e 0xf731ae57
- 0x19165943 0x2d9288c3 0xc9c45dd3 0x2e05b148
- 0x225a256a 0xc0249ea2 0xe96733d1 0x56a6803f
- 0x20458549 0x28210fd6 0x13da740e 0xf0f0be41
- 0x029c1fa9 0xb1daf3f7 0x1bf0c9aa 0x6f0d5221
- 0x998b3616 0xa02212a3 0xe76b39b1 0xba0823e6
- 0x146da6a4 0x858a3e0e 0x58e75b32 0x732f75ed
- 0x8d88385e 0xe0e7ed55 0xc08ca86d 0x97e2ef67
- 0xbb048208 0xd384c40b 0x8595bc69 0x65581977
- 0x7b091c4c 0x60bfbbb5 0x23bcf38f 0x32e4621a
- 0x7f790d95 0x72c3267c 0x34dd0c12 0x27438915
- 0x5619893a 0x09d55159 0xdba7eef9 0x7413634f
- 0xf4883417 0x59a2f28e 0x491f5779 0x0c138f9c
- 0xc52a03de 0xcb1f92d0 0xb6cfcd21 0xbba95c83
- 0x5302f12d 0xfc4c030f 0x18722dde 0x131cd3b1
- 0xa19a1cdb 0x103d9216 0x403e45db 0x5cab72f3
- 0x17e18f5c 0xbad9d0d9 0xd0d2e010 0x798106fc
- 0x3abace6c 0x2c3131c6 0xf9529b61 0x27cfa158
- 0x8890951f 0x87ccf0f3 0xa112b1e8 0x3e0eb033
- 0xd7469e14 0xb6ccd2ca 0x3d238069 0xb32f057e
- 0x8d2c939b 0x18d8aa3d 0xdb3cdb2b 0x861ba258
- 0x46e7b170 0x4830d004 0xeea1b8b2 0x44e29b51
- 0x0cdd8591 0xf93ad973 0x9383c44d 0x24e323be
- 0xaaac87a1 0x84eb09d7 0x1f66b641 0x303f92b4
- 0x81a63a86 0x516321e4 0xe33dfe2e 0x371a4624
- 0x8f936425 0x596976ca 0x7b1947ef 0x83a9db29
- 0xc5f337b0 0xe4d51b73 0xb35b56ce 0xb9cac5ba
- 0x51705ecf 0x93e7d63f 0x5ee7d916 0x479f25b9
- 0xe90bb406 0xfcd6e78d 0xbd8ed9b7 0xbca7c8b7
- 0xdf95f4cb 0xc28baeba 0xb4534bbb 0x98b4f840
- 0xf2218357 0x726e4f81 0x7591ebc4 0xc0523d15
- 0x6bc82550 0xedfbcfa0 0x57280f50 0xbe7e420c
- 0xd1152012 0xbf3ee0a2 0x11825710 0x18e728d1
- 0xb8af00b5 0x2d1e940d 0x1c9ade8f 0x923ed269
- 0xfd8c2580 0xf6477ff7 0x476a486e 0xd09c18dd
- 0xaede7959 0x55fb68fc 0xe5692f7f 0x0bf4bd18
- 0xf5fede2b 0x07bb05e7 0x1bb8ec54 0xa46bba84
- 0x15051826 0x762ce6ae 0xa0246225 0x35c38cab
- 0xbbd00a24 0x8205d3f4 0x4cb33ba4 0x293013fd
- 0xd4f67965 0xe9c1951b 0xff108efa 0xb8e68197
- 0x36d51e4c 0x2959f7f9 0xf2e4206f 0xc9973e09
- 0xb61ce3fa 0x9543be90 0x63642668 0xcaaf02be
- 0x7346a8eb 0x4111f5b5 0xa453cc2b 0xdb524b49
- 0x4d528cfa 0x71e5fc4d 0x62cbbab2 0x8423f40b
- 0x1a4db908 0x560c41c2 0x03982d88 0xa49c553a
- 0x529f6acc 0x82dae294 0x6c5dbaa4 0xfb4ae1f2
- 0x36e31345 0xb5cba88e 0x3704c623 0xe35245ea
- 0xa412107c 0x35faf59c 0x08ceb649 0xbd67a6b9
- 0xe37ddfdf 0x21303abc 0xb7de5e8e 0x88d9366f
- 0x49bdd73c 0xeca0cd02 0xfe1e01eb 0x30a56c2d
- 0x0cae1f5b 0xe77521c7 0x5ca59eaf 0x1288aa13
- 0xc60bc96f 0xf7292504 0x2b037e4d 0xf34757b4
- 0xedcdc492 0x39044092 0x5d710fbb 0xb8658511
- 0xe23e4d57 0x595d4d3f 0xc0f80105 0xfe952879
- 0xe81e2cb6 0x4f5a8fed 0x3bd0d700 0x211887d3
- 0x6ea6e78a 0xe066640c 0x0d29c725 0xdabbeedd
- 0xd2aca4d4 0x65c4a06a 0x6645b62f 0xb1de0cd7
- 0x022e07ea 0xe9f9248b 0x0a2251da 0xdf34159c
- 0x7894bab3 0x72e465eb 0x37448fca 0xbfbc1911
- 0xa79e4938 0x48b83ec3 0xb9c6833f 0x19d24abb
- 0xa434e777 0x77947277 0x2309612e 0x546a6ebb
- 0x4c96447e 0xab918dce 0x5075ba1d 0x0aa55a7c
- 0xadcce25b 0x837819d4 0x90d62a9d 0xf116ede5
- 0xb056cc7f 0xb036353e 0xb7c1af8d 0x014c2cd1
- 0x356f1593 0x008c2634 0xf7cd0cb0 0x02b0576c
- 0x5364c954 0x5b40800b 0x60054bd7 0xef31bb60
- 0x1a85370a 0x458c4348 0x435b8da2 0xd8df0e06
- 0xde0cf1b8 0xd3c6171c 0x0bc14938 0xdc874128
- 0x694f96cc 0x7b6687e0 0x9ca59f25 0x617aea60
- 0x63ebcc8d 0x4bb44d00 0xce46d01c 0x4ab07a75
- 0x64757638 0xe5903811 0x3562895b 0x760627ce
- 0x8939cc7f 0x225db9b1 0x730062d9 0x7a5a7a15
- 0x49678fc3 0x8620cb95 0x9439dee1 0x501f2cae
- 0x3d08a33c 0x352de5c1 0xe7b24442 0x6ec76b79
- 0xc575a1e8 0xb7024b20 0xc9dbb9f0 0xfe2303c0
- 0xba3716ae 0x0cf37bdc 0x1c68a4a7 0x7ba0d609
- 0x43003a93 0x17dd96c3 0xb884aa37 0x15b2d65f
- 0xf6016133 0xd1fd7e04 0xc0a22822 0xf8c26247
- 0x818c35fa 0x4e2b3605 0x83923c44 0x4ddd4397
- 0x6faf6a11 0x50438703 0x67796dac 0x3443b780
- 0x484f5bb9 0x8ead98ea 0x472ae543 0x94b0b17b
- 0x1307833e 0xcb0e8286 0xb02e1ab1 0x36a89f9a
- 0x372e82f0 0x84741303 0x111ad8ae 0xb1eeacb7
- 0xd7d8ccd6 0x5f779f32 0x0d65184c 0x0a398467
- 0xc07c099f 0x0704ffdc 0xa10b2f17 0x4c926dc9
- 0xd80829ee 0x0821015a 0x512e6d0e 0x57b514dd
- 0x509cdfd6 0x7e08ef24 0xf536c381 0x65483797
- 0x439311fd 0xabed0f15 0x51a372c2 0xdd24c506
- 0x839cdd63 0x0c21c8dd 0x513d9eb4 0x43c6a95e
- 0x5d543848 0x64843a49 0x687bbf41 0x93d3bce3
- 0xcf85eea3 0x5f3a6fc4 0xe7b45979 0x4c5848ce
- 0x924188e3 0xbcbded12 0x0cc18c86 0xf3fd5723
- 0x148dddb6 0x77cb388f 0x30afd47c 0xa306c453
- 0x1da0b234 0x0f206f46 0xf25975bb 0x9c75d28f
- 0xc60ad2fe 0x0067c5b0 0x497a1617 0x81d330e6
- 0x2c5362ef 0x86a54b1e 0x80ad976e 0x0a86ed37
- 0x1183b84e 0x2e2ce6e5 0x10b02598 0xd56fb0b7
- 0xe3e0bca5 0x755d2333 0xe0be1b85 0x6c976f4a
- 0x555a1465 0x8ab38399 0x51d4a5c8 0xec3d86e1
- 0x2a85d0dd 0x0d31c16f 0x603f2d48 0x274d5d68
- 0x292e7df9 0xe444f292 0x329946f1 0x132c3230
- 0xb2c3ec05 0x88362f92 0x763dc2fa 0x7ee6f3ab
- 0x7ca649e8 0xafee8a8b 0xeef65517 0x4789c1e3
- 0x85bd4cb3 0xc87762d3 0xfa528ba7 0xa8e20dde
- 0xd369c227 0x97e7f300 0x8256f4ce 0xdd5d2901
- 0x1e37c55e 0xbb6e22fa 0xd9424392 0x8798d9a5
- 0xc118ddb2 0xc3c91c40 0xe68ead77 0x8cf3655b
- 0x4381e8fc 0xc94f312a 0x0b372483 0x70b620df
- 0x53820813 0xb50d6f0c 0x64a53e9e 0x6f7f19f3
- 0x6315f718 0x9aafff2e 0xf3b5a338 0xf1f3293c
- 0x750ac26c 0xefe3ddf9 0xdc7369eb 0x024dafe0
- 0xf56354fe 0xf0afaf86 0x7da1df00 0x7447ffa2
- 0x4afd091f 0x24f39c82 0x3b3c8aa3 0xd90fc65d
- 0x10d90b8a 0xf05d49fd 0x281320fe 0x75f62523
- 0x0537b558 0xf52ae61c 0x77961852 0xbd0db386
- 0xcb650cb6 0x7387ec69 0x320764c4 0xf5013b3f
- 0x4f4239c8 0x4983a307 0xf510f405 0x7e355790
- 0x4f8480d2 0x50dd84ca 0x66947bed 0x56efdfe0
- 0xa593407d 0xdac216de 0x642a5f74 0x92bb9c2f
- 0xf37abdd9 0xa24b1b64 0xca1f722c 0xaa5de969
- 0xb6cb128a 0x697f787b 0x5bd74fb3 0x6de74e39
- 0x2bc9a4aa 0x634455ab 0xa82aecc4 0x69647f0d
- 0x4be06592 0x0c220c92 0xb08adf1f 0xd4571d2a
- 0x0fadece6 0x297c124f 0x2830a499 0x3cc8363f
- 0x44e34d3a 0x27b4d820 0x98be7f08 0x43417964
- 0x8a3af8ac 0x89c42336 0xe55d19dd 0x00ee1f6e
- 0x47d48658 0x55986f58 0x11ccb046 0xf3b97a07
- 0x7ed364a3 0x106cfcd0 0xc1533857 0x3add2c15
- 0x143852c7 0x55b38512 0x49a85ce8 0xd61a285d
- 0x513bd0b9 0x21bde48e 0x4f231482 0x93aa6dde
- 0x88035659 0xa83e3d2b 0x542513f8 0xe6e74a1c
- 0x06092343 0xd37c8770 0x41553ead 0x09980a79
- 0xb0e45895 0x80db4662 0xa6ce0960 0x965cfa7e
- 0xfea96644 0x2a79157e 0xf020e115 0x61823e96
- 0xf14f63d7 0xd753d1bd 0xd24a060d 0xfd2691b9
- 0x18da9d0e 0x9f3c93c4 0x2730e0f2 0xb47e2afa
- 0x920fda38 0xb5d89646 0xfb4728e5 0x7e78c2cb
- 0xe46f812c 0xe51cc5c0 0x9d2957fc 0x548798a1
- 0x240c2103 0xd650ff70 0x15c49ff6 0x99587c0a
- 0x1bb4a5ca 0xd6db66e7 0xec2d3ac5 0x54164690
- 0xe61bd6f8 0xc7a45cf8 0xee25f4f4 0xd1eb3ae7
- 0x90085a1b 0x46a7a74b 0x829717f2 0x7f0769cd
- 0x3ef72792 0x0c8617a7 0xa86becad 0x9dfe5329
- 0x1a33c5a6 0x47d4c75b 0x2e10b45f 0xbd11762e
- 0x15b72a9b 0x015c7f84 0x379c6bd2 0x27525345
- 0xff3ac5a6 0xac916082 0xf5c24317 0xcc43fc64
- 0x7f092c8d 0x931d9a0c 0x5a07f13e 0x3e1aa46b
- 0x717a343f 0xd51221c4 0xc9422fcd 0x63f7af00
- 0xde81a497 0x0322d271 0x972a4065 0xd75df029
- 0x343a94a0 0x8c225f7d 0xb4abe87e 0x3cb8ba1b
- 0x0babab14 0xf29704e7 0xd7134233 0x391f1a35
- 0x33aca565 0xe6ae586b 0x0470a42c 0x570efddf
- 0xfea26a3b 0xcee8d934 0x99ece522 0xb8af1375
- 0xfe4dea4b 0xb96a32c2 0x3469ef9c 0x029fade7
- 0xc4e77d55 0xc0449b95 0x63336e95 0x8d46c2e0
- 0xd86d6e23 0xd365b781 0xe73ba0fe 0x10a354c5
- 0x2d4511a0 0x077206cf 0x1c0dbd55 0x03396771
- 0x8bce27af 0x70355b4b 0xc2275e58 0x3cfa4df5
- 0xc8b3b9b8 0xf3fd510f 0x6b055de5 0xb3fef295
- 0x42b95a20 0x5b5e75e7 0x0aaaa734 0x636d50ae
- 0x8329283e 0x446e76f3 0x6adc320d 0x69a3e9df
- 0x1da68939 0x6f071783 0x498dfee5 0xaece51ed
- 0x4f8a72a8 0x4f2f2f65 0xdac3ba47 0xcbab0287
- 0xf966cb4d 0xba27861f 0x54c79a21 0x44e2359a
- 0x6e6b0e7f 0xceae84fb 0xb1530a59 0xecb8cd96
- 0xff60633e 0xed748fe3 0xf1ab0d95 0x59997216
- 0x6894cf41 0x948fc7bc 0xfb162ae5 0xeb9951a1
- 0x99d0a7a3 0x9234587f 0xcd42615b 0x6f9ad0e8
- 0xeb936dbe 0xbe72b62c 0x44ab5e9f 0xed736b08
- 0xffaedca9 0x103b89bb 0x7896b40e 0x13a5a924
- 0x56786357 0x02ab80ec 0x72ef47fd 0x81bf0fd7
- 0x6661b300 0xaefadc79 0x9968433a 0x16f3718b
- 0xe997a663 0xbbb55a49 0xf9b9a710 0x5727271f
- 0x20e9bf55 0x358e3986 0xd1214e1f 0x4d42c46f
- 0xa6bf8194 0x0c14a853 0x7b51aeb0 0x2f3d4de4
- 0x3d6ffef6 0x4e94ba19 0x71a9c861 0xcade2398
- 0xe0b3eb18 0xc9f028b0 0x7d29d2d0 0x372ec60a
- 0x288a5bfd 0x4fc2bab3 0xc01dd045 0x8222e147
- 0xe06676de 0x750bbfea 0x586ffb3d 0x2addb655
- 0x767a6528 0x78abceec 0x1646cb38 0x21e26890
- 0xd2a7937b 0x2463457c 0x764103fb 0xd540867f
- 0x3566875f 0x007449ba 0xf9c0c523 0x2c51c86c
- 0x437e1196 0x69fc0059 0xe0103408 0x19f23997
- 0x23fdf335 0x7262eef4 0xcbe09390 0x583d0099
- 0xe862084d 0x19fffbab 0xd2958a5a 0xcb165416
- 0x32f3a97c 0xe502303a 0x16c4eda5 0xa1bcfd1d
- 0xc4f35053 0xfd037f66 0xdeac9fee 0xbfb167b1
- 0x39804db6 0x0bc2011d 0xf56bcd68 0x368cb345
- 0x52fcb352 0xc306c535 0xf6bff09c 0xa429cbf7
- 0x7e504be4 0xd2240214 0xf09ee41f 0xcbcf1fe4
- 0x70f96a85 0x8394bf28 0x3cc19a50 0x49581f96
- 0x58da5ae0 0x94708c48 0x63febeaa 0x4f656940
- 0xa7fd6879 0x65524f66 0x5f7ee0df 0x11d487f9
- 0xb494641e 0x7eb57255 0x5aa208c0 0x5666243a
- 0x7d5970b5 0x71ea69a1 0x67059c9d 0xd3bde5bc
- 0xe952b3fe 0x27bbf258 0x197504f4 0x5da6649d
- 0xecddf4de 0x2d040d3d 0xbc9d3ab6 0xd8cdfb81
- 0xb36ab627 0x7a548111 0xaaeefa4c 0x0e55b263
- 0x4f9da6e6 0x26a137dd 0xdea03395 0x23b87267
- 0x5b3cc98a 0x206de858 0x8d2e5cd2 0xb60f14e6
- 0xfc10356f 0xeecae1d5 0x39783cbe 0x1a1c9a70
- 0xb52c6f05 0x64adf10b 0xe12d9f3b 0xb3fb7cf1
- 0x9051fdea 0xc16ed3bc 0x697199b0 0x08f34342
- 0x2fb2bab6 0x729ed2b8 0x7691088b 0x82bc9cc1
- 0xafce7ac3 0xe167bbb9 0x362e5d43 0x945510ec
- 0xf32dce5e 0x4aec9a82 0xb80520d3 0xd8fcbe40
- 0xf4877350 0xcfdd487e 0x8c9ff8b5 0x84ce70df
- 0xffa6abd3 0xf9d2f273 0x342dbff8 0xa72580e3
- 0x6ffccdc3 0x0c7ccc0f 0x6b24afd4 0x82b71a25
- 0x1ba361f2 0x6ed8a67d 0x243ce000 0xd16b2e19
- 0x86d3c3e6 0xca209063 0xaff0b983 0xf411f71f
- 0x0f2ca724 0xa6fb0fb6 0xfa663640 0xe40fe20e
- 0xf8e2a5cc 0x1a0e8862 0x11de13a4 0xc811e4a7
- 0xfe6fa8e6 0xfefce644 0x8f7fcde9 0x94477c62
- 0xec9b942f 0xfda6b166 0x91330c4d 0xd059d679
- 0x96b0f7a1 0x22df13ce 0x3f36c3e9 0xc814e342
- 0x7b7dce7c 0x1000640a 0x8cbe7a56 0x622fa655
- 0x209d82d7 0x55668514 0x1534f8af 0xc2b7dc1f
- 0xd89da0dc 0x3ddfe751 0x0532dfe4 0xd39c360c
- 0x090f91d6 0x48587117 0x8ee383fe 0xf5ffdee4
- 0xd8bca448 0xd26d6d82 0xe8adcc12 0x8b14b8c1
- 0x7f872f36 0xb8cb0e16 0x76d60c06 0xf62ddbec
- 0x3ec7c151 0xe418a789 0x920a3bf8 0xc5b62e09
- 0x4974ea7e 0x0d8d7962 0x5bbb246a 0x37183d1c
- 0xf25c63dd 0xb15730a5 0x903e3400 0xdab426eb
- 0x0323289f 0x9bc16f49 0x2dfd02a1 0x3ab916a1
- 0xcb6f770a 0x342021b2 0xf9f5c9c0 0x9c8d53a5
- 0x3d53f39b 0x8e693c58 0xebecc732 0xbf30c538
- 0x96648d11 0x60f62751 0x29745559 0x8e365fb3
- 0x7d0b1179 0xea5abbb2 0xe45c4af0 0x53056b1d
- 0xac7b03dd 0x7015c355 0xf17f8dfd 0xe1ace271
- 0x9abacdc0 0x5ccedc75 0x478c717d 0xc01dfdad
- 0x26fb551f 0x73e61f00 0x8bc0b111 0xb6855743
- 0x28690dc2 0xf13b6766 0xc098861c 0x5c0ffa55
- 0x271e7d0c 0x66b47b80 0x9921a158 0xd9c560d0
- 0xb29b6ee7 0x50a9bc97 0xbec4d91e 0xdb2c1fcc
- 0xdf215786 0x1541e380 0x59cae516 0x2342b2ee
- 0x8088cd9b 0x7312579d 0xb17be14a 0xa1638c41
- 0x805c6b18 0xb8a56151 0x56f0a6da 0x96b114d2
- 0x0845ea7c 0x23e8f7eb 0x4e88e7ce 0x84640f2c
- 0xacf8eebe 0x4039725a 0x49bf9982 0xfbcfcbd9
- 0xfbbfb1c1 0x8041659b 0x5b8ee4f3 0x1b6d7a38
- 0xeb634fc4 0xbf818ab6 0x8076c921 0xc50be762
- 0x24c43f4b 0x3252acca 0xa7528630 0x9885b151
- 0x9154b37f 0xfd9d3ab1 0x4f93c117 0x578fba44
- 0xa56851fc 0x9d8083de 0x769f6fb4 0xd89fec27
- 0x747c8071 0xe6b2b747 0x8196e2a8 0x3ed6c699
- 0x8716f1df 0x65325e96 0xfbc715d5 0xb06f9171
- 0x7aa9cbdd 0x84bda56b 0xdeab06ee 0x80432d8b
- 0xd76f0a57 0xe0ed5f9a 0x70f991a2 0xf1a9e557
- 0xcbecbcdd 0xcf0d91fc 0x6751fd67 0x590f206a
- 0xa26d8130 0x1df02179 0x826303ce 0x6cd58190
- 0x1219d005 0x4bb2f3b2 0x0dbd8193 0xd8d8f582
- 0xa5867eed 0x2d6b8ec9 0x5f85ec18 0x7983775a
- 0x214ca0c1 0x9af3febb 0x213d6568 0x2f8e8c43
- 0x92add018 0x6e33e00f 0x6fa6834f 0xc3c2cbbc
- 0x1c65c8c5 0x1827f812 0x868d3a09 0xdac83ade
- 0x57623da5 0x5ff83257 0x0992e621 0x25cc9ca9
- 0x10580130 0xff2ae8fe 0x40a58253 0xffdc24d5
- 0x3e4dbe68 0x291b11f7 0xb3594b9a 0x570c7b6d
- 0x38d31bd4 0x7155ba24 0x84d56490 0xd98842d5
- 0xe037d2f6 0xdd2ba821 0xbeb861d5 0x0fda5758
- 0x5921c665 0x98c7676d 0x8eee487b 0xac0f2411
- 0xb332d321 0xa0816c65 0x76edde5c 0xab868b36
- 0x3f8da4fd 0x516af4e7 0xabf748a8 0xbe7820fc
- 0xbf763827 0xa03a3566 0x8a63e804 0xb4f8f901
- 0x5d262ee9 0xaf905cf5 0x896d0c94 0x5f992cab
- 0x81c2faf9 0xda3c686a 0xb01a06dc 0x45ef0c90
- 0xf2ca525f 0x0e74fe18 0x36ecdb11 0x494125d2
- 0x226b4aab 0x3e92ae29 0x5bb48774 0xc2c2ef90
- 0xa9e77d5a 0x409db546 0x7728f003 0x72229503
- 0x2e8febab 0x8322cfbc 0x5eaf74e9 0x621837f8
- 0xc70668d1 0xb25c1325 0xd741c010 0xf52e3166
- 0x71ef7a87 0x74cc93a4 0x7c25ecf4 0xb8b8e20f
- 0x3658c239 0xbc58fba7 0xf13ec858 0x9271b2a1
- 0x37084dd5 0x6fc92e82 0x44a6abe6 0x92b9238a
- 0x9ad3a57e 0xd75daf92 0x8ea573d6 0x69ce1fb6
- 0xe80df5f2 0xcc1c6ae7 0x6d565a77 0x6981ae63
- 0x18af1922 0x6e8a7af8 0x10716aa0 0xa7da9970
- 0x1abbc7cd 0x114f814a 0x4ebb0c07 0xc8fe6a69
- 0x93d7bc2e 0x0a16181c 0x0379c950 0x4b2e8c18
- 0x670b83f8 0x82a75eda 0x6eb772dd 0x42cfe197
- 0xd91ec29c 0x29fb4812 0xab693ead 0xb2f25a1c
- 0x0b9df6cf 0xb7a1aba2 0x1d7d90bf 0x7de14655
- 0x649965f6 0x11fbe065 0xa54ac5a3 0x418bd3df
- 0x4223c00f 0x7bfcf9ae 0xbd979739 0x6a2ee697
- 0x54e7d9c8 0x73803bdb 0x06654716 0x72225136
- 0xfaef3873 0x0b4b40dd 0xd3b98b57 0xc56cbab5
- 0x32174c47 0x4d4d8c32 0xd6f1bf93 0xeefb6950
- 0xb84ed0da 0x590723d4 0x2d006f09 0xc4bc139c
- 0x55434982 0x8734189f 0x0e314a50 0x94340d09
- 0x021c24a4 0x0b0f022d 0xa61f9025 0x71eb72b6
- 0x744ccea1 0x2030b859 0x78203d74 0x0b8a8389
- 0xd5211777 0x2609edfc 0x6134eede 0xec74584f
- 0x0bdb2d06 0xb1768f76 0x56221895 0xfc49bdae
- 0xbcc6e6ed 0xfeb19c0c 0x18652996 0xaa1a0164
- 0x3ffdcb94 0x2dc1b090 0xb68bf220 0xc33b967d
- 0xc907a1aa 0xa3968cb1 0xb3cc65e5 0x33e2b077
- 0x2bb22904 0xe0fe8fc2 0x4affcc46 0x6b0f0bbc
- 0x5d1bef41 0x2de11c7f 0xb0d864ee 0x6e96d8dd
- 0x59c1c108 0xb2544572 0xab3400af 0x604aefcd
- 0x81be22c3 0x6741e6ca 0x3a93dc1c 0x7b10e639
- 0x0add7a92 0x39fc1df3 0x884f150b 0xd666a96d
- 0x87da0c1a 0xf0f73c15 0xc0c00957 0x011ba61d
- 0xa77e9463 0x96020e4e 0x92416e99 0x881e89c4
- 0x46981327 0x3bc624f4 0x57f226f5 0xac340cd8
- 0x3ce239b2 0xec6b33bc 0xa9123e11 0x70640b6b
- 0xc30f59f0 0x411576fe 0x5ab12c3b 0x3cc20b85
- 0x924b3be2 0xd1fc7a28 0xa4b0cf7a 0x88098404
- 0xbbd331e3 0xff2b6047 0x2a1ab042 0xdf220849
- 0xaf774ae3 0x5a8da79d 0xf18450c8 0x8e6e235f
- 0x1dd3c039 0x1a867ae2 0xe4ccd1f4 0x50dd3f39
- 0x8be186ba 0xc7e30fe2 0x17552d4d 0xffac16e4
- 0x4094bbc4 0xc18a2513 0x650e707f 0x8ecdbba2
- 0xf53e8e7d 0x047dbce2 0x7fc2a89f 0x07628f94
- 0x2a8bfc67 0x0d738727 0x7b5c2fd4 0x2c89d27f
- 0x47f37a64 0xc63debc9 0x15d6c414 0x242c300a
- 0x645d95ab 0x29e1a49d 0xaf77fab1 0x643b4cd5
- 0x3e0f63db 0x4f7cc43a 0x33d6797b 0x497d4332
- 0x7160786f 0xe0c5b75d 0xfb08ecb2 0x26063065
- 0x9835bf7c 0xf5465591 0x63155d2d 0x14babba1
- 0x384a0879 0x460db3b1 0xcd37760b 0xad675a77
- 0xf1dceded 0x69df690a 0x44c6f456 0x87d6a7a4
- 0x4e0d6504 0xf967f55f 0xca9bb20d 0xd5eb41f6
- 0xa9aa9b2a 0xa907387b 0x965b6f23 0xdcd47eb5
- 0x43b5b1a0 0xec876728 0xee7339e8 0x10c5ee16
- 0x1bd8c0bb 0x7235ae07 0x063e3564 0x388d0bb5
- 0x80f9a9f6 0xaf96f714 0x6895c899 0x00ad21bd
- 0xee67961b 0x873781a9 0x22cf435a 0xee90cf3e
- 0xc9a4fadd 0x9bc1af4c 0x35c0e803 0x211ce71a
- 0xb9af86bb 0x97828ab5 0x9dbd002a 0x1cc981c7
- 0xefb36876 0xea739a75 0x5d5abcc1 0xd42260f2
- 0x95083e0a 0x31fb0b51 0xf243ab8f 0x628b1913
- 0xe74eb210 0x620b7d9f 0xc81666d2 0xc8fd1ce1
- 0xf054bd9e 0x78ba7618 0xe1df4e38 0x5e381b3a
- 0xcc68da1b 0xb3ce70ac 0x7ecda229 0xf8778140
- 0xae823fa1 0x12af1708 0xc9373879 0x1e687d29
- 0x96062069 0xf1bfde2b 0x999ff6c0 0x8cbeddf0
- 0xc825a2bb 0x78106bbb 0x87a964fc 0xb358ec2f
- 0x4d959300 0x0fe9706a 0xabb1d003 0x72b65294
- 0x43816b1f 0x6c83b958 0x5549567c 0xb474aa55
- 0x98851640 0x751a670f 0x25900026 0x2ab174e3
- 0x1952c3dd 0x38b47c29 0x32c0af52 0x460c8fad
- 0x85a1004e 0x8cbddcd7 0x66578310 0x4904dcfb
- 0x04b7a746 0x00c91fb7 0xb1ab2edb 0xd0178ae2
- 0xc4b8b57e 0x981d4753 0xfdd8939a 0xa8a05055
- 0x47c8c30e 0x0fab4f6b 0x6ea54079 0x23dc4151
- 0xc23e83aa 0x2ed2ce8a 0xff95b763 0x08df1d51
- 0xd16d104e 0x0fa3ee3b 0xdcfe8541 0xa0622490
- 0x085e5c0f 0xd9bc007b 0x24794e89 0xce341d16
- 0xf090a98c 0x317150a2 0xcc036257 0x3296722d
- 0x9c8d4f58 0x7ca5f53b 0xb0e4f9d4 0x1f178bbe
- 0xc0dcde7c 0x18551596 0x0507b8e2 0x3c40a8ca
- 0xc632f82b 0x5d1965f9 0x92a00465 0x13a8ca32
- 0xc0b6756f 0x669d706c 0x58056b22 0xaa25fd37
- 0x128b731c 0xb141ed31 0x0a8d3ddf 0x48b63bd1
- 0xd24c5c4e 0x0ccd96b8 0x4b1ff726 0x309be62b
- 0x26002e68 0x436f2bd0 0xacb62068 0xce098f50
- 0x330e6160 0x434da66d 0xce14054a 0x0a877e41
- 0x705eb2fb 0x8433fc7e 0xc1bd475b 0xb550de6d
- 0xf4faf808 0x9f9b6ebe 0x0ff98ef7 0xace2766f
- 0x01cc9606 0xd9654327 0x3544cf5b 0xbffbcd80
- 0xb4a5948f 0xcded4d04 0x69ef5a24 0xf5ae46de
- 0xe2139499 0x549f82bf 0x2cdfc6b7 0x5fdd2462
- 0x63c68a37 0x8bce0d04 0x9c66ae30 0x9fd94951
- 0x5774366d 0xd671675a 0x5582f253 0x436c5b6b
- 0xfc151e77 0x1974df45 0x5ea9eac2 0x30689b8a
- 0x9806681a 0xb74d3ec8 0x4f207181 0x668b4951
- 0xb06514b2 0xeccffed1 0x16188ff2 0x5914d385
- 0xed4b7023 0xfb0640e8 0x179adcda 0x6e806687
- 0xb4f0ac07 0x35813615 0x143e66b4 0x1b012a50
- 0x384f31c5 0x1500dbca 0x06e47afe 0xa8a17374
- 0x9d0f5c57 0x4574db82 0x91b3680e 0x794683a7
- 0x30c25d5d 0xf8748c08 0x2e601dfc 0x553152f7
- 0xec5d489a 0x4bd37616 0xdc04dc7b 0xf0a35ba2
- 0xb36975db 0xbfe6f98a 0x6d744996 0x5507380b
- 0x4191e01a 0x0092c384 0xcf3a4388 0x6b0e89c7
- 0xded7b820 0x1fbd6bba 0x3af210b1 0xfc4a608e
- 0xa920eb22 0x22db2d65 0x7d6f0447 0x090f3679
- 0xc4c759cd 0x9758aac6 0xa63251a9 0x47b7a974
- 0x65421071 0xdca8495e 0x96f879d7 0x1d22ea6f
- 0x46dd72ba 0xe0c59ccc 0x15737309 0x6d945f11
- 0xbcb15c8a 0xb11ef0b9 0xe2072633 0xccbd61dc
- 0xfcb51c44 0xd2315c65 0x3087a6f8 0x5609ee34
- 0x94c7f951 0x0a057b31 0x6e6f2733 0x179facec
- 0x36c005b9 0x60184919 0x50b3db1f 0x7a827d7f
- 0x88755ecc 0x3fb0d6c3 0x63b150d4 0xe2ec3004
- 0xe0ee30f1 0x118d7040 0x2f4689e7 0xa78be0be
- 0x3c9bb853 0x75c326cc 0x84097407 0xb0107b5e
- 0x83a56a91 0x14e60445 0x0fa72553 0x1385e6ce
- 0x9b8bbdcd 0xe6aa6a9b 0xc2072ccc 0xee916592
- 0xe44082e1 0x43dbf6d8 0x09f821fc 0xdc84b023
- 0x0e6a518b 0x945fb180 0x185d0841 0x9ece88f8
- 0x844558c2 0xed85f422 0xeceb983c 0x6db16826
- 0x7612b243 0xee3bf226 0xb8eebb7b 0x22e16615
- 0xc892bb7a 0xdc475a47 0xae390e93 0xe00baa1b
- 0x725fca23 0xbb868b3a 0x17c62a69 0xeccd3731
- 0xbe1a4223 0x05c8fd7e 0xa8354afa 0xbbb09f8c
- 0x31a77e83 0x01f17a68 0x5f37c847 0xa0fdd7db
- 0x9f8da870 0x98f02167 0x1e966884 0x00e19b81
- 0x50c91add 0x6aba2a55 0x60be9575 0x3da40b37
- 0xde13ff4d 0x5b7a79ec 0x4700ffd9 0xfee5ea61
- 0xaf4d1d1e 0xfccb6f04 0xcf5076d2 0x48c4c98a
- 0xd6a8915e 0xe4a58522 0x6bf3a6a9 0x4e7c2f15
- 0xcd7e8d2f 0x843b56b1 0xa35f1a5d 0x1ca226dc
- 0x917fb163 0x44751f0a 0xd96fa8aa 0x5028dccc
- 0x7792dd96 0x2a9d749d 0xe48385fb 0xde111e91
- 0x805e6581 0x3d9b9fad 0x5b750544 0x03785b71
- 0x9b583214 0x80022658 0xcf1f3730 0xa1be7be7
- 0x6c1e26f2 0x26de584b 0xb4fc8e35 0x072b520b
- 0x55db3ac9 0x81e9d490 0x4b5ea53e 0xd5628e00
- 0x71bfcac3 0x79956bbf 0x275fab80 0x2ad497ed
- 0x423854b2 0x686451ad 0xfd59d64e 0x9f2049d7
- 0xcb0f8f32 0x74d7545d 0x4f9c1df8 0x6fbf0afa
- 0x7ef06915 0xc5117549 0xf20088b4 0x731a5ccf
- 0xe78bbe74 0xdcb4996e 0x7062a6f1 0xa624b59a
- 0x7b2d5e41 0xc1065234 0xa7c32078 0x367e7134
- 0x86f55f58 0x3084ee83 0x0c599d1f 0x69380e2e
- 0xe59482b3 0x7096432e 0x81124388 0x5be8d01e
- 0xeb25ec24 0x8b47e9ad 0x432216fd 0xdc496dea
- 0xcb05fefe 0xe76eb9ab 0x8ed568d2 0xfa963d68
- 0x70ed6f4e 0xb2b88d58 0x15fc42bb 0xe992ec48
- 0x359856b3 0x4a0f7741 0x3f0b6eca 0x07c16950
- 0xcb9dae59 0x209570c2 0xf196555d 0xbf7c0a0f
- 0x4a814210 0xf8f206c7 0x8bbb0763 0x360fa596
- 0x13d46195 0x901170e8 0x6dc2e376 0xbfa00989
- 0xd12cab90 0xf4f4699d 0xbc88b362 0x4827dbd5
- 0x7cde5cf5 0xe45dff5e 0x2d661b05 0x8902d99e
- 0x6c9f3584 0x0db3f864 0x1132773f 0x3e944120
- 0x27058ae1 0xef978864 0xe58eff42 0x020ae503
- 0x77fe075b 0x9c577e08 0x210b42b9 0xcb8160c0
- 0x09f99f36 0x6a0b6bee 0x6f18b0ef 0x5452ee3f
- 0x6c8c4a4d 0x480cb803 0x892f3973 0x066dbb63
- 0xf7f845c8 0x7ceeee7e 0x7c26c5ce 0xec89119a
- 0xc64bdc20 0xf46e4324 0xff34c833 0x555b4b3c
- 0x23ff2701 0x52360759 0xf60acad8 0x241ccb7b
- 0x29e14901 0xcc068e2b 0xedd0ee02 0xc33a425d
- 0x7d889b28 0x88577f8d 0xaaf614b1 0x8e8c8eb5
- 0x81a363f8 0x29f5bcc6 0x08aeb8e9 0x6f9ee222
- 0x1c50045b 0x792c9434 0x62bc2601 0xc9289175
- 0x374fc38c 0xbae91a86 0x3268e89b 0x5b008f10
- 0x0ea6b759 0x9d43ce10 0x09b30dd2 0x643e2b94
- 0x5c19bafb 0x29515176 0x56a81f95 0x60a80534
- 0x22fa0a73 0x1259cf8d 0x323fa5b3 0x6322f1d0
- 0x30581c47 0x50458048 0xd711c1b6 0x4a34236e
- 0xb60a2e40 0x58df96c9 0x947b90d7 0xd327d664
- 0x5fe528db 0xf6d9c575 0xb0a251b9 0xed961301
- 0x2fee3cf9 0xb687e226 0x78fc46c2 0x29e9fef4
- 0x84bff086 0xd0482ed1 0x018996f1 0xb8b9cdf8
- 0x20885e68 0xa6f848e2 0xfddabc3e 0x5c9a7f67
- 0x7cbc3e40 0x5197ebe2 0x41a15775 0x8024fd2a
- 0x7864106f 0x7cfaf482 0x27798720 0x4956355f
- 0x30f7195e 0x6ea09dd6 0x6f2b5f3c 0xf38df38e
- 0xcae7e8cb 0xf8a80b0b 0xbeb227ba 0xbbfa2428
- 0xbbba3ab6 0xbf83edbc 0x2cdcaa9b 0x2b0841a7
- 0x79d52e5e 0x40260460 0xb27709be 0x07e3bf6a
- 0xbdccc2b9 0x369d0069 0x9d745e50 0xff251486
- 0x1e14957f 0xf7253467 0x9a31eeb9 0x4d77108a
- 0x44fefc47 0xd02d4082 0x232e3fc1 0xce39396b
- 0xd7a13714 0x2bd57e7e 0x00876803 0xee73377e
- 0x78bb6240 0x2ae63c46 0x11e009d2 0x922539cd
- 0xf3bef05a 0xf0c664c3 0x6e132a0b 0xb0c5bddd
- 0x40c66494 0xd7d0d02a 0xa73110d0 0x4b409d78
- 0x6f49bf88 0xcfc9d22e 0x4836da89 0xde5a80be
- 0xb9c8bdb3 0xe99b2e9d 0xf1b05e68 0x8ab599fc
- 0x22675035 0x3c8480c0 0xfa3cd457 0xba617098
- 0x422eca1c 0x0cdc0d01 0x4779b95e 0xccfa0bfa
- 0xd22674a4 0x76462be6 0x3015ab3b 0x7891688e
- 0x1c83bf8b 0xaa55839a 0x7a71a83f 0xad451c1b
- 0xf8b8bf06 0xc75a91be 0xcac50366 0x87e365ae
- 0x9013ac11 0xe9cec5a5 0xef4d88f5 0x15c27162
- 0x3dcaf8ae 0xe023891b 0x7b6f1706 0x2f1198e4
- 0x048e34ba 0xb647b5e8 0xa1826caa 0xed3bc134
- 0x43b14d28 0xf0c49b54 0x1a6362d4 0xc77fa378
- 0x3bb12e79 0xcba4cd2b 0x620f2476 0x7729add6
- 0x9876c439 0x5f7d8795 0x858f7ac8 0x68b94589
- 0x1321d70b 0x5353a2fc 0x912a5ea4 0x390cf0f5
- 0x37320473 0x51b3cacf 0xe45046d2 0x9188dcc5
- 0xb3713b54 0xc9b936e3 0xe9f24574 0x5977a68c
- 0xc23c56bd 0xcfc39ca9 0xc891b8d0 0x3683ef22
- 0xc1ce304a 0x3ebf1ce1 0x52cd1cc0 0x3777d973
- 0xde614072 0xf2efe226 0xbe1f9f9b 0x92a1896b
- 0x9ca62763 0xcf5703be 0xa6d9c56a 0x185260d6
- 0xd9e3b86f 0x5c47180b 0x71a7a219 0xe9974375
- 0xf22af4d3 0xfbc92962 0x968c3fe4 0xc584b60e
- 0xb9abee26 0x7e9737d8 0x5947da83 0x2f8ccad0
- 0x7b4ee942 0x51ad62dc 0xf517400c 0xe2bf9e37
- 0x63057e05 0xe1bfabf8 0xbf118805 0xc038de9c
- 0x7aa57b7b 0x05584eff 0xb15ea286 0x26c6a6c0
- 0x8e1392e8 0x7dbf22e1 0x3546f5bd 0x0f84ed9b
- 0x0b01da4d 0x6dc47417 0xadc6f687 0x4160c045
- 0xdc26765f 0x63b70c6e 0x8f177107 0x6a5f13cd
- 0xb56fce56 0x5d1f5ed1 0x62f6a18e 0xf7235691
- 0x222fa999 0xd48b1435 0xe597d406 0x8dacf828
- 0x694ecd8c 0xe5283c02 0x60bcdcd3 0xfb9eb384
- 0x9895492c 0xd38172dd 0xe7b6dff6 0x0ead5894
- 0x910e2675 0x97d9ee09 0x270b2d8a 0xd03e25e0
- 0x9e7bbb69 0x57ab1d31 0xf2e7a13d 0x9c8e5baf
- 0x65fa03f4 0xc66bcbfc 0xf2d8bfe1 0x23059412
- 0xa3ae7654 0x3a4734a3 0x32c0a8d3 0x4e007b8a
- 0x5ce30660 0xbd10c57c 0x5365f540 0xeaed3002
- 0xc377d84d 0x87097a59 0x929edec9 0x5878368b
- 0xbd450478 0xc3fab275 0x128fdced 0xb706fbb5
- 0x146f1d41 0x86782651 0xa530ca29 0xa3e1b6be
- 0x25390048 0x572b4a05 0x8c9b4c90 0xb05428cd
- 0x33fabab5 0xd16e513e 0x1d6cc812 0x4d80a6ed
- 0xd6a5a07e 0xc0ee4c19 0x544b75d1 0x3f887360
- 0xb2f46d1d 0x21609cbd 0xe340211d 0xe9202fb6
- 0x3023b005 0x3341ead9 0x76c99537 0xc9d76547
- 0xfb736c3f 0xf6385346 0x93fe2a05 0x92de6df5
- 0x7793acd1 0x68249b3e 0xc22cae3b 0x668988e0
- 0xdc1ea28c 0x7ef72b95 0x974098f9 0xb214701c
- 0xc2de7d98 0xeb1d443e 0x5975f0ec 0x21d67037
- 0x721e8e99 0x42105562 0x74b1e821 0x20193b2c
- 0x743a7bb3 0x24643c9c 0x240b331c 0xdf125e2e
- 0xcb4b0205 0x19edb174 0x505eb85c 0x1830bf22
- 0x6bf7a528 0x86a7281d 0xfee3488d 0x6c26f4ab
- 0xbff4ce7a 0xff7cfaf1 0x5df6fd66 0x523f0802
- 0xf8a87595 0x463b5c19 0x72c564fd 0x2e4797d6
- 0x1f04a1af 0x0be96baf 0x44552094 0x2a158f50
- 0x83dac587 0xad4c881d 0x3178e710 0xe938d1be
- 0xab715a65 0xc34b451e 0x1942832e 0x91557ecb
- 0xdaf0606d 0xa64623d9 0x84e11fbb 0xa9c9d11b
- 0x577a15b1 0xd49a2f23 0x6f204e0b 0x0a6e6a2f
- 0xdaf13637 0x6b4ef557 0xdcaac9a3 0xad97c404
- 0x8471691a 0x50ca3cf5 0xde57c446 0x70aa02f1
- 0x84baa6de 0x0232bc79 0xa06427af 0xd2ce56be
- 0x5da13949 0x254f5f4c 0x3fc3fd02 0x00b5f8eb
- 0x54a0d4b8 0x5e3ec3b1 0xc6718376 0x5acce6d8
- 0x614c56e0 0x89a6b00e 0x6cb4e087 0xa9822fe9
- 0xdea290c6 0xb294582f 0x36f9640e 0x30d0afc4
- 0xef7d75b9 0xfd9aae2d 0xd6729573 0xac442321
- 0x158224fc 0xfd6632df 0x10cebf98 0xc3864dd8
- 0x31577c58 0x49e71f9c 0xb96d876c 0xd867604e
- 0xba74c3f0 0xad69752f 0x716eb51a 0x469d9d03
- 0xda4b2e16 0x9e80a908 0x9bcb18e8 0x2f1c595a
- 0xe823ecfa 0xdfd5badc 0xe460e9e0 0xae418438
- 0x457811b4 0x29df713a 0xd90b0d29 0x415ba2de
- 0xa0af6489 0x4922a50e 0x2efa0b0b 0x9394e4cc
- 0x0ef8f59b 0x0f851711 0xa4670f3b 0xcc6bbfc6
- 0xae194dfe 0x78e51752 0x4c65a2d2 0x1b0741cd
- 0xc9f401c0 0x4a678062 0x290d2bc5 0x1a4279c4
- 0xb5f9160f 0x40ef7c77 0xa9bcfba9 0xaec75f21
- 0x53d6258e 0x8587eb74 0x0721d492 0x2c6a6e2d
- 0x8e6cb70e 0xa6bee309 0x6faf5706 0xf8eee239
- 0x52c85943 0x8c198893 0x3db37858 0x557fbf2e
- 0x92f1a0e5 0xbd279594 0x46d65132 0x90a2c32a
- 0xd11db660 0xc73b3922 0x9d1075ff 0xdb80a1cb
- 0x54158743 0x39694d0a 0x4a0ddc7c 0x721f9dc9
- 0x04b1b044 0x3bb40aed 0x6be7a88a 0x429a3b09
- 0xa6e9dfa8 0xba412f0c 0x354f08d2 0xa4569516
- 0x928cca34 0x398b1a99 0xb7e80291 0xe67d7b71
- 0xa6582bf0 0x556ebb23 0xdc6d9f6a 0x11b3b753
- 0xbdf31ae5 0xd3399560 0x6148cec8 0x5188689e
- 0xde18f46b 0x3da414ad 0x4c44ad29 0x68582541
- 0x75c8b1e6 0x7ba572de 0xd753ed20 0x4a9c4578
- 0xf1c9159d 0xcfd9da31 0x46799fbe 0x1aee4426
- 0xdcdf7b57 0x327db61b 0xa160ea1c 0x84a01fc2
- 0xbe0aa020 0x5963688b 0x24f32751 0x885b4177
- 0x26cde88c 0x39e6df90 0x1c7fee90 0x882a5c0c
- 0x56f1f2e0 0x10bb9f52 0x4f0502aa 0xeae6e5b9
- 0x65e7ee25 0x8ed230ac 0x38b5e02c 0x5f5311f7
- 0x929491c0 0xdd923e62 0x5bc6166e 0xa3c89f4e
- 0x5844fb12 0x0c40f02f 0xdda07582 0x8ca1b803
- 0x9398b0d0 0x4dba17f9 0xb9879c85 0x26956147
- 0x3c26a130 0x58cdc52b 0x21fa4801 0x9d965ce6
- 0xb9942dac 0xd83d1518 0x36e630dc 0x50bb2822
- 0xcd472a65 0x6feee2f4 0x4853b680 0x7f54945f
- 0xa522c561 0x28134f6a 0x89b46cb2 0x4fe0047e
- 0xad602b28 0x4942494f 0x1536ea37 0x40ea6278
- 0x5020bdb1 0xad3c9f7e 0x1356d0ce 0x411700c8
- 0x1ba61954 0x65dece8c 0xb788efb9 0x26efcd5e
- 0x9833fa21 0xea0052b8 0x119a994f 0xa71b168b
- 0x164a96e0 0x0bd1b4e9 0xaae1e562 0xb550f48c
- 0x3a3b55e1 0x4d921246 0xcb28af65 0xdd2388ff
- 0xa63988c3 0x7dfa5a8b 0xc7c44102 0xc75e9f3a
- 0x5e4305db 0xacb34d1c 0x9b50976b 0xad3f6379
- 0x6cd20ee3 0xba806f21 0xcd0fcf4a 0x18a55973
- 0xbafe5266 0x03ee9b8c 0xa35fbfde 0x7f2eb71b
- 0x23d9aa11 0x0e183c35 0xefb0ae3e 0xc6093786
- 0x5b380af5 0x64838229 0x3bd69926 0xe9758e1d
- 0xde439e4a 0x0cbc4bdd 0xda5858e8 0xbe8afc07
- 0x676379e1 0xccc4c628 0x763e3b38 0xb4823c67
- 0x9f4aa538 0xd8d33f50 0x41291e48 0xaed28ade
- 0x6c72eea8 0xa751f4e8 0x3a75dba2 0x5073e3bd
- 0xf10b4756 0xdf46ab98 0x9ad689f1 0xc2ba74a4
- 0xf2ce9419 0x4cf9732e 0x75cf58ca 0x249e3c52
- 0x95d10a93 0x51120008 0x7438d467 0x0a5e7f2d
- 0xb7a44e46 0xe31e5dee 0x26e2ed14 0x8f16a7d2
- 0xfcda431c 0xab32ada3 0x3a863c94 0x5fe91346
- 0x2a92c590 0xb8c17e6b 0xcaf753fe 0x50283647
- 0x533c8f3c 0x1233e1c1 0x7a5b2eb0 0x79b4ba22
- 0x3164670c 0x201c500d 0xafeac6bf 0x2fbb0884
- 0x915de3b0 0xbf733b7f 0xc45d1a42 0xa3b86d4a
- 0x333ef605 0x6348522a 0xd28d1d19 0xa2cad790
- 0xf8ad449c 0x05aacdcf 0x64500018 0xb1d8cb18
- 0x9e4a2ecc 0x091282c7 0xfd64bcf8 0xe1e7c24d
- 0xfcd0f386 0x0c9faa0e 0xa82f265c 0x83cafc3e
- 0xcad43563 0xc110837c 0x2a2da74f 0xbd98e00b
- 0x5c24553d 0x41c75caa 0xe75cb110 0xa004b946
- 0xd4daa77c 0x88d07273 0x0c75c7eb 0xaf05657a
- 0xbe1f8336 0x122a7acc 0xe0e5c29d 0xd5896217
- 0xfb2f909a 0xa74b6458 0xb33a1a38 0x815f7832
- 0x9584b271 0x9a3bb26e 0x39aa6d36 0x2fba41db
- 0x133797be 0x9993699e 0xdb50268d 0xccd54ff0
- 0xb7a33011 0x71db612b 0xef9a4429 0x7217f1d0
- 0x0ee420ba 0x1f7eb025 0x26572853 0x72712e17
- 0x5bd7be37 0x74b2288e 0x3ffd1f1f 0xed566562
- 0x744f4159 0xdbedb36b 0x69e25131 0x604ccb70
- 0x50d83542 0xe4704ddb 0xdc5144aa 0x33467434
- 0x1c7c4f2b 0xac774e8e 0xce9c4d1b 0xa0e3c7f7
- 0xffbecc1c 0xa1c25fb2 0x0e9f6039 0xbe9ed6d0
- 0xf958fb6a 0xaec3fba8 0x2944e767 0x77dc717e
- 0x06e9fe1d 0xaf3a4928 0x7d4f3f29 0xead3972b
- 0x65670bc4 0xd058cc70 0x9fb58c45 0xf5f08926
- 0x9aed1955 0xb1a5d161 0x14b5aa11 0x66e14cee
- 0x28d7aae3 0xae45fcec 0x92dc7dc3 0xe9eda97f
- 0xbee84f22 0xea6f71ac 0x6347c2b8 0xe919afff
- 0x2c409d7c 0xa9800c52 0xd8033a17 0xc3794565
- 0xb5311fe8 0x80d8a030 0xf9cf179a 0x508ea242
- 0x4464cd33 0x91da91a8 0x6c0806cd 0xb5473d09
- 0x0a0b99b3 0xdaf528eb 0xca1e99e7 0x064055ef
- 0xc2dce623 0x0b4c15ac 0x23c13327 0x3f9fc266
- 0x335d9c40 0xaca940c2 0xc18c0797 0xd5027a07
- 0xb0a4d322 0x2e601275 0x6cc88888 0x658eaf8d
- 0x509e2247 0xbae254d6 0xf097f138 0xa163751e
- 0x19558f7c 0xb66f0cd4 0x87b1d966 0x81dd2cad
- 0xf0c25e6d 0xb8e72dd1 0x00f15f42 0x6d2c1c68
- 0x43c7e436 0x68eedad4 0xc2686b38 0x6ff30211
- 0x197c7734 0x905b8602 0x6ab9d204 0x0d16385c
- 0xb1cb5e16 0x8249a5c4 0x29d1ce0e 0x779f7b63
- 0x63042725 0x12ce98e3 0x11282058 0xca3a9eb2
- 0xdb8294e7 0x423e41ac 0xc3ab2774 0xca658d6d
- 0x519f8896 0xaf6010f0 0xd57a94aa 0xcc17df91
- 0x7d25cf8b 0x041e6835 0xa056d9e0 0xf90f3964
- 0x7f99ae59 0xd80125d7 0x9961d6e5 0x41b3da06
- 0x65c254e4 0x787d2c61 0x16aafb02 0x157ab4a8
- 0xdee3674a 0x1ed1b601 0x2e36dae9 0xad57ad38
- 0xaaf25b15 0xd3c37a01 0x68ca9eba 0x2a1bc480
- 0xba157917 0xc00017c0 0x190bd74a 0xd6c6c1cd
- 0x4efd4f71 0x388ed702 0xc8812950 0xd0019ca4
- 0xd44cc835 0xd838fd6a 0x1432ce88 0xce98d932
- 0xaea21cf4 0x54a44cdf 0xdb4dc5ad 0x1d23a7ae
- 0x5ae126ad 0x100dcb50 0xa9727413 0xcf1c61cc
- 0x72f9d2f8 0x4d32d201 0xe27586a8 0x0a1cc932
- 0x21858469 0xf1cda3f2 0x59703f35 0xbd81f9f4
- 0xad6ac9cc 0x25665703 0x1212d5cc 0x98a243d3
- 0x8f47e113 0xd98feef4 0x3c93e832 0xfd67097a
- 0x0c73fea5 0x6132ec59 0x1dc9bdb7 0x791f79eb
- 0x84d83574 0xbd5817e6 0x7d5a0f8d 0x18482a08
- 0x53ac8e4f 0xadd3378f 0xd48540ac 0x4082f5d2
- 0x3ff5badc 0x24855b3d 0x7bb948f8 0x72637822
- 0x0687e93b 0x61290b4b 0xd9f20b3f 0xcc0e5beb
- 0x141ca01f 0xecd1337b 0x8576ec65 0xb6f825a2
- 0x8b84e8b6 0x5bac53f1 0xd4edd06a 0x76ae712b
- 0xdc00a887 0x798c2ee1 0xe74a5ab5 0x1539fa68
- 0xa30817da 0x06f7c53a 0x1930c59d 0xd4232359
- 0x0dfb1427 0x58d7180b 0x53bf57f9 0x5f001d08
- 0xd08128ed 0x3208b7be 0x5c2aba8c 0x0abbd0d0
- 0x424f2041 0x7982f731 0x010ec811 0xa3489c82
- 0x71ffdfa7 0xda0ed41f 0x8a9e806b 0xfa9bddcb
- 0x7a9e1a41 0x53c7603f 0x9e3df28d 0xd06dd100
- 0x2cc64f4a 0x0dfdccf2 0xb4eb9101 0xf56d506d
- 0xdaeed218 0x45523a16 0x4d6d68ba 0xff9a8f72
- 0x5358b2f1 0x2511a591 0x9ea2c2fb 0x08cafc7d
- 0x7ed34bb1 0x0cf2301e 0x62b6c05d 0xc05095ec
- 0x52128c55 0x030576af 0xef5f37a5 0xdf5ae47a
- 0x39e55496 0xb2c2129e 0xb2d67d77 0xc5adf049
- 0x15a1cb4f 0x981948e5 0x7d18acc0 0xec7abb43
- 0x23f7e366 0xa919a355 0x23872683 0xb7b6d84b
- 0x4767dab1 0xd133feb1 0x2e5536cd 0x587683d4
- 0xa181575c 0x4329e640 0x1244ae40 0x5be82f66
- 0x4b28dc4b 0x4106c9a9 0x517fad7e 0x9e334ca8
- 0x3c3ba741 0xe902a475 0x91d046a8 0x31361f96
- 0x911b83bc 0x6607fac7 0xdfbc6390 0x7213aab0
- 0x8ca8a47a 0x4f3d1f3a 0x3ee76c84 0x22bac3f0
- 0x475f3cab 0x05d05569 0x92b3f912 0xc632a733
- 0xd79b7448 0x595b82fa 0x6013b96e 0x6d03b5eb
- 0xe37045fb 0x6e4add26 0x11f116da 0x4ac8bd3b
- 0xacb5f8a9 0x8fb943d6 0xa9ac31c7 0xf1ba9752
- 0x43a6b29a 0xf123766f 0x536fcc32 0xcf8168ad
- 0xd8fb1e4d 0xb9562fa5 0xfe6d8dea 0xd31ab16c
- 0xf7dfc381 0xb70f11cb 0x371c6688 0xac3fccee
- 0xf130a51b 0xc5b8cad7 0x0cb13762 0x64ae00f2
- 0x45cfad12 0x753d6a4a 0xc6f69472 0x695fba60
- 0x49d1f754 0x9db947f2 0x2364ae20 0x197492e4
- 0xc5b9562e 0x34963cec 0xdc26402a 0xa1c88d01
- 0x58e27195 0x9d60f5c4 0x3e200a43 0x7e9827f2
- 0x0a4feee5 0xd401e139 0x17352152 0xd509564a
- 0x4b3142ed 0xef7567fd 0x9a619dbf 0x56ec2cb7
- 0xc64bb290 0x3d69fd89 0x897325a1 0x74e2cb7c
- 0xf270fdac 0x2beb6a4f 0x5b60de30 0x49df7517
- 0x294966cf 0x87f5f667 0x4a9e1f6a 0xabc332c3
- 0xfaf358aa 0x5baa6cfb 0x36b99bfa 0x40259687
- 0x584539e2 0x2710ce99 0xec1959aa 0x642c8413
- 0xfc005d36 0x2b2e6245 0x0012d041 0x09f6b626
- 0x70fe9e2b 0x3cf30c5c 0x69d0a3ed 0xfe621601
- 0xb6fa9267 0xe9b507dc 0x49f35866 0x4b97647a
- 0x9e721adb 0x89e6e8d6 0x407a2f49 0xd977cbaa
- 0xd9359f5d 0x7b69702d 0x22d6e818 0x57eaa5a3
- 0xdd5063b0 0x4d7d2312 0x7a865203 0xb7f0905f
- 0xdd2c2b87 0x7215803c 0x1abe5307 0x2926f38b
- 0xf6b0cacc 0x96f50647 0xb612feb7 0x6915bfcc
- 0x058b5cb0 0xc39e47d5 0x7513abdd 0x9e43972a
- 0x1e55f640 0x896db1c5 0xd9382d2c 0xa52c1f99
- 0x8afaf5cf 0x36500aa3 0x2e65fa1a 0xbb40d668
- 0x81188e3f 0x143fba69 0x3f61fc90 0x438d759c
- 0x893bb96a 0x069f349f 0xffdc43c7 0x6ebfa943
- 0x671b4751 0x629cec23 0xe717fb9c 0x53fadc0a
- 0xddc1e212 0xb99788ba 0x78378cf8 0x2ed91106
- 0xec1de376 0x98d86b3a 0x312a190f 0x0208a0da
- 0x6dcb469f 0xe6407c6b 0x1c7fea86 0x83841afa
- 0xa9caaffe 0x86e3fd0a 0x918af9b0 0x0fabdf39
- 0xdd9fc8f7 0xf9ddd98f 0x3dd0acce 0x2064360b
- 0x29006620 0x5d7733c2 0x682c4093 0xf038a8b4
- 0x3a688845 0xf9d0b9d2 0x27f51a57 0xb63b063c
- 0x533b082b 0x7f0d0dd1 0x7abdb018 0xea6f6176
- 0x13394ac6 0x825339bb 0x1835fd8d 0xaa46df84
- 0x0751fe4b 0xbc9fb7c7 0x233873ff 0xca200e1c
- 0x668fd5a5 0xda059135 0x2baf8828 0x7a2efc0e
- 0x7c63d98c 0xe71ea373 0x0f218e88 0xa031f88f
- 0xf32bccf3 0xf15eadad 0x6df44be6 0xb2536e4b
- 0x2903a9aa 0x42ef8689 0x444432f2 0xd27a6c4c
- 0x0992a32e 0xaf6e65d2 0xcbefdf23 0xe602151e
- 0x21beace6 0xd9b992b2 0xe43286cb 0xdb315c09
- 0x0de7672d 0x9d518ff0 0x75c4e9a0 0x64b2f70a
- 0x9deb697d 0x5bcf59b8 0x2e4b9a8a 0xd9294b49
- 0x3fee760e 0xfba8fec6 0x1c140305 0xe400487f
- 0xc4cd4a38 0x14e6f1c6 0xdf98e7f8 0xfa6c4992
- 0x62908c82 0x37393196 0xc02464b8 0x4b119742
- 0x83e5e79d 0x15ddd908 0xf75d1820 0x363025b9
- 0xd9e1a04b 0x9e110da7 0xd8caf954 0x30f62bc6
- 0x875fd2b7 0x8b67bc8e 0xd5c77d4c 0x1a8ce00a
- 0x7cfb14dd 0x3a39fd65 0xaecc2b5f 0xb017dbb5
- 0x6a57b4f3 0xa27b6509 0xcdb06076 0x000d6366
- 0x66e4f311 0xf22e25d7 0xf91d9bc5 0x5f9d3a05
- 0x3b37c96c 0xb0596f50 0x53c24ede 0xb620106a
- 0x5e675314 0xd98d5b02 0x75261f6e 0x5610c20f
- 0xedcbe43f 0xbe85b8c2 0x16f7ffb4 0x55eb91fc
- 0x2605ab1b 0x5ad3b426 0x3658d764 0x639c0560
- 0x987249ed 0xdc470fa2 0x0d112f6e 0xd8ab77f7
- 0xaed9455f 0xd9f6a341 0xb9b21249 0x3ff2b69f
- 0x37ad61d4 0xdd6a089f 0x609233f7 0x46a923f4
- 0xe5c23e8b 0x6aff8687 0x5e8ece1e 0xc65e1e4f
- 0xfb96cf51 0x9b697cce 0xb08e02e2 0xf874e0e9
- 0xbc983fa6 0x870375e3 0xc88bcd2b 0xc6bb19ae
- 0xaa0c99e3 0xb301ab7f 0x024ba529 0x4449828a
- 0xd226454a 0x0a610f3a 0xf302a0f4 0x021a3cc2
- 0xa9e4b6ea 0x0b690b92 0x3379c01c 0x36265ea4
- 0x29fbc8a3 0xe6279573 0x3cdb8a1e 0x005b5332
- 0xbab71a8e 0x9677db73 0xa8a6d6ea 0xf0afbd3d
- 0x576fbee6 0x49a54473 0xfa7c6e95 0xcb914daf
- 0x58266856 0xa6b53a63 0x7136515a 0x2a3da411
- 0xb1c994e0 0xbdaecd7b 0x5b436ff8 0x6334ec5f
- 0x0172b5d2 0x57acd652 0xca4efacd 0x87e7d313
- 0x78ac87c8 0xaf7602aa 0x3769ff6e 0x86d39747
- 0xd32a7aa7 0x840cb30c 0x3e7da9b1 0x3c905b44
- 0x90290dd7 0xebc85f3e 0x32693a53 0xc7140058
- 0x6ca5cf6c 0xdabfbc3b 0x3d559486 0xe5ce93b9
- 0x8d3c428a 0x9d18b8ee 0x404f58d3 0x151b4a78
- 0x2f393e9e 0x69c59344 0x7879e974 0xc32217f5
- 0xb946562f 0x1d1b8745 0x3666cd1a 0xc6a1e2ef
- 0xe22d2e5e 0x9e7ed504 0xe6c32118 0xb2919117
- 0xb2bad34c 0xe7177e87 0x47b68328 0xe579fe7b
- 0xd0d33f00 0x96923c90 0x5ff2bf45 0xff074961
- 0x4dce1092 0xe8a89464 0xc0b1ea51 0xd65f0f12
- 0x6b2389bb 0x48fa0960 0x82722b27 0x62625540
- 0xd4ff4985 0x768b7c26 0xb36a4ec6 0xf6a66375
- 0x1c89e246 0xb629fce9 0x6aa72399 0xd783733f
- 0x6478b123 0xa374412c 0x11b5cfc8 0x73cf2286
- 0x443f5601 0xd817fca7 0xb2ce2d63 0xf6c63479
- 0xd16b0550 0xf2a52ac4 0x7843803c 0x1ac3b58b
- 0x7f96b915 0x732403a1 0x64634349 0xd2ec0bf9
- 0x10410c08 0xe95d8dfa 0xaaeb33a5 0x57893eaa
- 0xb59afac2 0xe9fd6dd2 0x50d11a7f 0xde479c58
- 0x9dac27dc 0xebba7d8b 0x17fa1420 0x74a1678c
- 0x71ccdaa3 0x5e44b0bb 0x5927a75a 0x7b7580a8
- 0x33330c9a 0x40192652 0xba6308de 0xecc81fbe
- 0x41d48824 0x6ce4e0c7 0x145e9225 0xf8484bee
- 0xc8675611 0x750ec207 0xfa5f5b85 0x618b9f8a
- 0x007cdb05 0x67f98d4b 0x1035f305 0x8d700e9b
- 0x9857a0bf 0x4b774ad8 0x8960c81e 0x344a9462
- 0xee2680d0 0xebb5f6cf 0x7397c9f2 0xcafa01ec
- 0xaf69f3f4 0x0a1699cb 0x90ed82f8 0xc5c8ac04
- 0xe50bd06d 0xf75741c6 0xea52365c 0xd0c03f33
- 0xb5e4e95c 0xebf55379 0x0aae6e4a 0x29f8b91b
- 0xef8ad2b9 0x7bebf2ca 0xb194b728 0x7df7b083
- 0x0ea527c4 0x6d55939f 0xb9242c58 0xb3e1f570
- 0x4fba0507 0x82d7259b 0xb5be7b54 0x0aff6ff9
- 0x88391023 0xfe352956 0x4a6bfb30 0xa00c9644
- 0xc478d534 0x0cdb509d 0x9611713c 0xd7c442be
- 0x8d16889f 0x93abfefe 0x435fa757 0x40d95d3d
- 0x11b7bdce 0xd074874b 0xdce6add2 0x0b652a4e
- 0x595a88e6 0x307a223d 0xb624b9bd 0x855ba51f
- 0xad43c800 0x1fcf6afd 0x4bdd921a 0xd6777384
- 0x8da9f15f 0x5fb03ee2 0x5e6d04e2 0xb33751cf
- 0x55d9d38e 0x41589fad 0x6d311b4a 0x43046a7a
- 0x8d9c7304 0xe25f9788 0x8b459e1b 0xc9a3cfe2
- 0xe6ab721e 0x4de3c89c 0x5c2d2398 0x085d8d69
- 0x4e27ce73 0x1cc1f44e 0x05aeaebe 0x8cedb916
- 0x370b4d46 0x1bc29579 0x33d08b75 0x06b77cff
- 0x155693d7 0x125d3f0b 0xd8714e15 0x3b7427ba
- 0x13f6684d 0x834ee449 0xc5a45189 0xb2ad214c
- 0xa61be586 0x4e4727cd 0x563d1c31 0xd4ba1cc3
- 0xdb08cd16 0x4940a42c 0x43dfd0cc 0x9d43222c
- 0x638a0d11 0xc33d3992 0x98bf11f0 0x1aebf6b5
- 0x1e206582 0x5647f772 0x9255ad74 0x75915665
- 0x0fe7dd12 0x9def740a 0x9361bdf1 0xc1409fc0
- 0xd3bac631 0x7492ee87 0xe1e99dde 0x2fbaf552
- 0xfc24f52c 0xc080882a 0x0a2417c8 0xcea3da70
- 0x4fe34fad 0xb4e55427 0xd5d54d76 0xf36686ba
- 0xd6ab1798 0x1868e364 0xa380f948 0x0eaee02a
- 0xad5a44e8 0xb6d119f4 0x82a43444 0xafad0e68
- 0x595c3ab7 0x385746b3 0x32df6d2a 0x0b01b2de
- 0x51d3d6bc 0x107d8620 0x6d215143 0x29d0e901
- 0xbc57a3ec 0xd584ba34 0x8c244547 0x23d396fa
- 0xffb03cb4 0x8396c1a7 0x3f251905 0x8bc769b3
- 0x68f4696c 0xfc297895 0x9ec65e40 0x22deb20b
- 0x5d1def76 0xa7a095b1 0x3aa6a458 0x6ca11880
- 0xcde44ece 0x62b59f4c 0x067f272d 0x9a5aae97
- 0xc60a8d62 0xeb0f40c9 0x83ebae30 0x07dc9cb0
- 0x05dbdc76 0x0c108eb1 0x314f9247 0x7bfd6072
- 0xf648e1c0 0xae70bd5e 0x7c27b4d1 0xb0cff1c3
- 0x8c2dd93c 0x580a4b19 0xfaa1ee8b 0x4173a23f
- 0x838fa15b 0x2b0fe3c5 0x8059250d 0x659a445d
- 0x2a1c1968 0xbf13412b 0x1a9f915e 0xaf80263d
- 0x24508a66 0xe381d252 0x4e0f55a2 0x7ce1f4fb
- 0xc145da4d 0xbd4b29c3 0x27540ac2 0x23ad4b42
- 0x8e6bcda5 0x20061c20 0x1d3cb3fd 0x5c5498f3
- 0xc468681d 0x4c28ef55 0xf0165c1d 0x2dd6d032
- 0x7e347ccc 0xe04db59c 0x7caa883b 0x1f43df4f
- 0xc300031c 0x85f19e9b 0x22811fa7 0x2622940e
- 0x6299f57b 0x5c106568 0xd7da296e 0xccd36b39
- 0xe349afc0 0xd2c2463e 0xf7f55aef 0x0e0a7e3d
- 0x6b6fc6d1 0x8854098e 0xc87edace 0x8190c437
- 0x333b8ec6 0xe49b3a5b 0x4aecd4e3 0x14cc5f22
- 0xa11faf96 0x3d1cd023 0xae614c70 0x0ab662b4
- 0x908d8082 0x76316cd0 0x3068ec32 0x829b047d
- 0xf08d1b94 0x3b2b33f6 0x03df9ae8 0x40f632d0
- 0x3590085b 0xa33aad24 0x39597da2 0x99415f4e
- 0x7aed6e11 0x61a920ab 0xca851d8b 0x2606f821
- 0xeb7c0e8b 0x8bd6edb1 0x725b39f6 0x3afa6248
- 0x03540044 0xfb118ecf 0x8e18bd5a 0x2a85cc05
- 0x4ecac12f 0xf53a4d25 0x8e3fc6fe 0x32233799
- 0xc7ebb5e6 0x058fdcaa 0xe6db17ed 0x2751405c
- 0xa195a515 0x34410c51 0x4517154e 0xbbb5674f
- 0x28050e40 0x8fd71724 0xbe78711c 0xc1b18693
- 0xd202b9d2 0xdf4e0b62 0x460349da 0x71463aef
- 0xb2fb55d3 0x54a972dd 0x49379f09 0x7a7fdff3
- 0xbd82d4f8 0xd2894393 0xa82bca57 0xe61ca9b4
- 0x9e08e6a0 0x53dffe9d 0xe7ae1c5c 0x65bff365
- 0x7564aef8 0xd94abd3b 0x18d1ba52 0x64a759f0
- 0x65c5dd4f 0x6f9d433a 0x57cb5a25 0xc1862d25
- 0xcf50223f 0x90c2724d 0xf5527605 0xb085f18a
- 0x41e2b17d 0xfb1cabc4 0xd8ab04cc 0x761c2166
- 0x8365afd4 0xc3276657 0x14f64be6 0x5dd779b7
- 0x3b3f1faa 0x358d01e8 0x4c821ddd 0x7ada9f95
- 0x2970bad5 0x3b54a4bd 0x3ca7f039 0xcb67aabc
- 0x3b264655 0x96401a5e 0xa3990376 0x90834685
- 0x8ba56352 0xee98c564 0x4a0534ed 0x7d70fad6
- 0x5d73a1e7 0x23fd8de5 0x39c52296 0xefef1540
- 0x7bc934dc 0xeed157b4 0x898d8bfa 0x5761e88f
- 0x73af2674 0x2fb88d9e 0x28de1281 0x9aa76119
- 0xa3ac21ea 0x28ce635c 0x7596d79a 0xd3295e0b
- 0x7826630d 0xd815ef01 0x27cf2899 0xf3de6a01
- 0xcbb32e58 0x6c57be3c 0x292f819f 0xaa4623d6
- 0xb96ab772 0x90a6f778 0x44b9933b 0xa43e7543
- 0xb9f417b7 0x7a6537a5 0xf36a6da2 0x0a9bb3fb
- 0x177c1f28 0x0512c07f 0xdda55932 0x060dda31
- 0x14465771 0xf3f96780 0xb459e5e3 0x49aaefbd
- 0xb07db15d 0x2ac82807 0x8404060d 0x417d036b
- 0x70946fb1 0xe39e68f5 0x5f9b3035 0xf0335e7f
- 0x2ba457c6 0x2d97ba3a 0xc05156e7 0xbbc9afb2
- 0xd25981ea 0xe70d060b 0x805c231d 0xae471b34
- 0x31964d8d 0x3f34e35a 0x8355ee21 0x73822024
- 0x9ce5f2d6 0xdff19812 0xae55cbaa 0x55f5ecbd
- 0xfe558210 0x09b95751 0x41ee7cb8 0xd2b9fa15
- 0x342c07e5 0x7ee50e8e 0xb6154e01 0xdbf4df3a
- 0xd43e2c77 0xc3ff0498 0xd8106f33 0x9bdb25bd
- 0x40cb843e 0x106b08a9 0x3227ce7b 0x58bb7cb6
- 0xb84e3244 0x3f1d0e20 0x76dcbcfd 0xb750bce7
- 0xa8c11f3f 0x161a8610 0xdc1ef5bd 0x14270b6e
- 0x285e7898 0x68375db6 0x01d23b44 0x35a17fb0
- 0x7c9ad882 0x7bda2e0b 0xca67bfcf 0x6e2dd9ab
- 0x227a6aba 0x5d295397 0x5061f96e 0x47a20c68
- 0xf5427e3d 0x3a0a3165 0x2438fd9c 0x2dc91147
- 0xeabab62a 0xdc358e4d 0x7e1fcc9b 0xdc2a328e
- 0x6e6bf75c 0x68c45517 0x594fe5a7 0x2feac658
- 0x1f0a4d49 0x97575e83 0xcccbdab8 0xc13f3b64
- 0x8bfe659f 0xa4ebf545 0x2c3cf874 0x7d78ceba
- 0x46ac5d6e 0x09309533 0x78ffb6e3 0x7336541e
- 0x3d270f70 0xd71e72b4 0x9772402a 0x4ed185b7
- 0x213da698 0x78a54587 0x18054eb4 0x99179a25
- 0xf758337b 0x94629a30 0xec6bf4e0 0x255ac299
- 0xe56f52b1 0x1c2a6136 0xfb7cc1f6 0x87b53b53
- 0x079ca1f7 0x3a8c340f 0xeb70ef48 0xfd1caae4
- 0x564445e7 0xc1d5c663 0x658fb5fa 0x62d2debe
- 0xc0907042 0xb5402269 0x16965193 0xc038c21f
- 0x780f8b76 0x33ffeb3d 0x03ad9602 0x4a7b6432
- 0x93c2b2f5 0x40720fcd 0xf44c164f 0xcbd43d01
- 0xcf7098cd 0xc43242fa 0xc530a6b3 0xcc33c1f7
- 0xde3d648c 0xf1def13d 0x2a22f5d1 0x77704fc6
- 0x08ed5552 0x3e2295d0 0x00584764 0x6af8585e
- 0x43f845da 0xa92e38df 0xd98c12b4 0xb4fac901
- 0x0b05a079 0xa05f215a 0x27d635c6 0x9fc897e5
- 0x0eb91a30 0x43bdad4c 0x705df05f 0x6b7864b7
- 0x1b6380ba 0x4a64e8ec 0x517b7b68 0x67336d4b
- 0xc6d51eab 0xfac40c57 0xb977cbcd 0x0674e5dc
- 0x74ce2339 0x891cc5f5 0x3230ca78 0xa8a653a0
- 0xa8d4b370 0x496d2f7f 0x6ca677c5 0x54260ac2
- 0x630e1143 0xcbf6f819 0x546b2874 0x02267559
- 0xa2e23914 0x7c9a0393 0x1704bcb3 0x6d680415
- 0x91da300d 0xe2ce21d2 0xc38faf3e 0xcc8be7cb
- 0x14496036 0xc98e253a 0x05ca6582 0x8c566616
- 0xd26204dc 0x3335bd81 0xa94e5af0 0x76fbb455
- 0x23b27f08 0xc4db6f93 0x5cb5401c 0x7cb2ed29
- 0x7cbbad8b 0xfc1e8f5e 0x2bc79e28 0xf69228fe
- 0xbde16357 0xc9ac3b53 0xa6afbc74 0x984bb3f4
- 0x98a8b9d6 0xdd21c848 0x33e65c3a 0xc53c772c
- 0x633022f8 0xa324bd5a 0xd260a77a 0x668ca5d3
- 0x4b79a6b3 0xbfd19bbe 0xca2eb497 0x8e7eb5c9
- 0x169b2184 0x0503d4f6 0x24f35c00 0x0ac930ab
- 0xf694120f 0xcee12db4 0x9305757c 0x798a2db2
- 0xed27ebec 0x2f35829b 0x4294e805 0xa7994ad7
- 0x49fd229c 0x5d63fe52 0xb7cd7641 0x1a68af3b
- 0x6f952e97 0x1c02f4de 0xca3a1515 0xed5bf092
- 0x123c32ea 0x602030aa 0x7811cd1f 0x1b6c38dc
- 0xeb7712b4 0x4aa767e1 0x6b49d384 0x7ba4ee1a
- 0x87f02cd2 0xb8e6b0b1 0x090e9f89 0x95f8b90e
- 0x8d76892c 0x0be06870 0x9ec963c1 0x75d67c9d
- 0xdde23799 0xf9e3be20 0x549442fc 0x09cb0906
- 0x95ee6c4b 0x25a2d9b7 0x98154023 0xdda91829
- 0x0c46879b 0xfbf0e362 0xb7223786 0x7cfbc839
- 0x3b251e5c 0x8be187a6 0xa24f9da6 0xc3192693
- 0x7a8ac8b9 0xc493ca03 0xc736b974 0x369db725
- 0x85a6e92f 0x26dbef75 0xa61a71e9 0x38a08fb9
- 0x4a214ed6 0x57fc6f4b 0x9cf91617 0x322e13fe
- 0x5ac816a3 0x748a9728 0xdc777bd6 0x69fb5335
- 0x258439e8 0xf171a221 0xfa7a07af 0x26447b9f
- 0xadcf3734 0x5af34b97 0xf8b4b0dd 0x08c79517
- 0x28861618 0x64692555 0x19fe9897 0xe3bda02c
- 0x77df51ff 0x93dedf7a 0xc7cb57c4 0x02ee5928
- 0xd4aeb644 0x01d511e6 0x6512bd02 0x5d8f90f8
- 0xe77ccfe0 0xe6ee3ecd 0x5403139e 0x6f7075e5
- 0xb6484511 0x3bd42a35 0x5dcea90c 0x5bb1c6e1
- 0xb69b5847 0xfe106914 0x74442ce9 0x10997c57
- 0x1595af7f 0x9f04a8bb 0xa7d2870e 0x19e57681
- 0x54b276be 0x11c3e3f9 0xc5401783 0x9c413cda
- 0xa6aa9e8d 0x23ff8569 0xf1797ea7 0x86ce3e8e
- 0x9ef0a776 0x56a1c30d 0xf5e18916 0xb11464d1
- 0x7f313c1e 0x49c15cff 0xe2dcfb73 0x637819d8
- 0x2d6ce0e2 0x2170cd43 0xb750902d 0x5eb02cd2
- 0x6cadb7d4 0x89b96f3b 0x8d749ca2 0x8ac7abb7
- 0x31fbdb51 0x7a6df774 0xfb9139f0 0x56f3d9c3
- 0x0f104f2f 0xfaba3c49 0xe53aefff 0x932237d0
- 0x8ee10e80 0xadad6e20 0x19883a1a 0xf45a543b
- 0xd560ff0a 0x8c7b4e03 0xe35696d6 0x9e0ec159
- 0xfc2cbae5 0x6ce2cddc 0x14a72474 0x89757fe3
- 0x6b788e7b 0xc16fa200 0xad36bdf7 0x57bdc4d1
- 0x55146f2b 0xa57db4c5 0x313952e1 0x2c55d0d2
- 0x32ab0208 0x10f846bc 0xdcba1674 0x436485bb
- 0x932704de 0xcd7e2e1c 0x59f78879 0x7ca21395
- 0xbcc07be6 0x2b101e5b 0x38924c37 0xb90928f4
- 0x8f824214 0x55699b67 0x54cba493 0xe71c27a3
- 0xdde01c05 0x48d822fd 0x734ed8fe 0x29dbf298
- 0x9ef3a499 0xfb517934 0x19c8ce8b 0x38b8bf00
- 0x75da50eb 0x237f3b1d 0xa8940707 0xa98a4149
- 0x35ec2d39 0xee862d31 0x36659949 0x8f3dffc2
- 0x70afb227 0x94f443c1 0xb6f9308e 0x0e8ebd54
- 0x92b8960f 0x56d21560 0x8453d1ca 0x74c680c0
- 0x2d706dfc 0xd0b81c18 0xbac65445 0x40a34988
- 0x498145a9 0xf436ae10 0x9b72fec6 0xb4100aed
- 0xe305983c 0x349fe379 0xbf31cfa7 0xba624703
- 0x4a491754 0xf973a686 0xa2ba725c 0xd0a23615
- 0x31903086 0x4ae46e45 0x0f705e05 0x4ea6bbc8
- 0xbf299e43 0x0689709c 0x9fc93571 0x07cbc14f
- 0x542ef992 0x80ce91f1 0xf86014aa 0x17d533d1
- 0xb55e63e2 0xe02e0e4c 0x88a5ed22 0x6302126a
- 0x56b32e90 0x5fec4381 0xe2e98b3f 0x30693509
- 0x862e1d75 0x2da30e3c 0xad992d90 0xc62cae4b
- 0x379c77ba 0x467ea8f1 0x8a820048 0x74cc474e
- 0x6bca3803 0x18aaa3f3 0x1fafd26a 0x0865f360
- 0xe3479d10 0x6cefb2b9 0xf6612730 0x2e0f222a
- 0x749a89e0 0x75b1fa05 0xe2ea0874 0x5d422c20
- 0x24707d46 0x6d475835 0xed1e556e 0x6aa4543e
- 0x28b36c16 0x22d83c4a 0x8c3e6d51 0x42a94c9f
- 0x0c603d0e 0xa8c7f417 0x845997ff 0xdc79494e
- 0xa130d628 0xc2df082a 0xa3a2c27e 0x3f93b00f
- 0x1521a7e5 0xca15bae4 0x57e4e836 0xb915a471
- 0xd9147115 0xad52f80e 0x5fd2a2be 0x15972ed7
- 0xb69ec21c 0x502f2627 0xfb46a1ca 0xea685d34
- 0x9226f7f2 0x4b41927d 0x7965eaa0 0xb702e76f
- 0x79a54721 0x5b8e984a 0x37efcd59 0xfeabf30a
- 0xd4ad7db5 0xbb2282ab 0x8a5c840b 0x2ba370c5
- 0xdef5758d 0xa69a9aa1 0x46082250 0x6e8e8477
- 0xf6280c61 0xf99e4a14 0xcf3c5cbd 0xcce657f0
- 0xca635eae 0x0be182b5 0x58e8b43a 0x5c717ce5
- 0xaa7aaff7 0xc329c6b6 0xf1cc91ef 0x8d7cc520
- 0xda155783 0xd5e2e54c 0xf466f010 0xc5dfac4a
- 0x606ad5de 0xf4992f1a 0x1344c9ce 0x4aea9020
- 0xa30447c7 0x0a99ad18 0xd3caa96c 0xfe5b0b4e
- 0x7b50bbd1 0x33e50575 0xa22d1d06 0x73a1820d
- 0xce4c4c8c 0x2cde7764 0x511d1c26 0xad0cf826
- 0x086dc311 0x3060ef7d 0xe6fdc617 0x3050b179
- 0x1dbb5316 0x4145fcb7 0x2eb62505 0x2e1359e2
- 0x79cab612 0xaa9282c9 0x7eede562 0xb016f7ed
- 0x1445fefb 0x809b2e00 0xfafaa754 0x69ac113c
- 0x548a6e3a 0x6d444c14 0xb3d355d8 0xbbadcd2b
- 0x3032d634 0x7df39948 0x4c1f9098 0xa9d138ce
- 0x42823bbe 0x2ef39e3f 0xaaf9ef1d 0x63369afb
- 0x2bb76c9d 0xb7d38558 0x354160ce 0xc04c6378
- 0x6c71ab10 0x7914af1a 0x1c1a4694 0x2f9fce8a
- 0xe28f18d3 0x3acaa573 0x2503b236 0x90ca20e1
- 0xd2c77ccc 0xc3005311 0x836d9430 0xe91d8463
- 0xb53e4cb7 0x4e373c67 0xd06ef659 0x27e1a21c
- 0x285c0391 0x32046fa9 0x8b1b9c92 0x49a22f4e
- 0x81411430 0x050110e3 0x56144e6a 0x47fb824a
- 0xdb2e9a6a 0xb5fe97a9 0xabd37259 0x93da3055
- 0x19fb35e6 0x66661115 0xa27149a2 0xfb7d94b5
- 0xa315f9af 0xd7d97596 0x134d7d09 0xd5cde0e9
- 0xbc3f143a 0x1b2061ea 0xd7b15227 0xe8f506e3
- 0x0aa17e92 0xc8565276 0xc7d90586 0x22a26c8e
- 0x6d462029 0xe7b1ad73 0xd11fa609 0x67643f2c
- 0x64f1ef34 0xa0e7e0b6 0x9687611d 0x09c2d32b
- 0xb494937a 0xcc36510c 0x70555bfd 0xfa25e917
- 0x7d88b6da 0x30f3b531 0xd19b224a 0x999d0f7a
- 0x9fe0da18 0x45947b87 0x536dbf3b 0xa6f5182d
- 0xdf11f95d 0xa5abcdbf 0x7528110b 0xf54fe792
- 0x71a97619 0x680bd3ff 0x6981ea39 0x683ff854
- 0x302fbbe4 0x12129f84 0xf63cd448 0x69fe289b
- 0x568da933 0x2f1e1146 0xe7404e52 0xcd329394
- 0x02e41762 0x94456d4d 0xe9416a20 0x4e5920e7
- 0xe8db71fe 0x527a5313 0xe42c7d9e 0x58c8c1fb
- 0x28949bc1 0x312fdf97 0x3569f41f 0x3ed5f092
- 0x44baef39 0x5c11d5ad 0xb5d172cf 0xa9e4cfa3
- 0xbc5ed197 0x2f290ead 0x747f53ed 0xadf1b698
- 0x1b90440a 0x4cdfe154 0x9b24b832 0xeb97d794
- 0xc90fe91e 0x4fef1271 0x8bf96025 0xbdb49f79
- 0x63910640 0x26a05cce 0x3318e422 0xb2fc61de
- 0xf14cedd1 0x4bd7687a 0x8c4c91dc 0x48a857a2
- 0xb47aac94 0x787526e2 0x99349c7a 0x0bd6ba75
- 0xbfbc4b0b 0x040fbec9 0xd00de44b 0xc4c7f0f5
- 0x74a8653b 0xbd3cc036 0xa601a4f3 0xb82c0da0
- 0x2709b674 0x73065351 0xaf4cd23f 0x3481ea0f
- 0x6a1fa77c 0x26a9d280 0x95f4a170 0x393e7590
- 0x015b3d73 0x36d91e55 0x61a7f3f5 0xf6d39c21
- 0xd9ee4701 0xe57af451 0x5e141761 0xf6b6e472
- 0xa6efc965 0x9606aa1b 0xfb8ce005 0x831ab2d1
- 0xfe7a1af6 0x5e326881 0xa0ad32ae 0x15f86ecc
- 0xa1a634d2 0x3a40c4a9 0x88e10130 0x2e6c4556
- 0x8526aa32 0xa81b0d30 0x19c83936 0xdcaa556b
- 0x6dc8064e 0x5709ad31 0x1b6fba18 0x9ebe34b1
- 0x28abc3e6 0xd76c3908 0x4374657e 0x6f0fc085
- 0x4f19a108 0xb774421d 0x405228d5 0x123dbbab
- 0x18535471 0xfc6bde41 0xd4b2d82e 0x65b85772
- 0x64731e41 0x29e886f6 0x4c2c7eda 0x91586a5f
- 0x15b2407b 0x5fa08a72 0x56898e51 0x5424e976
- 0x19ce4a36 0x0ada4656 0xe634446a 0x478da533
- 0x36f1c763 0x01ec46c3 0x5e1d1040 0xf6da1918
- 0x831f8f94 0x43ddb630 0x80b5d4e5 0xfc403ba5
- 0x40dcdd4e 0xa19d0aa9 0x6c32fad7 0x7cdd6f3d
- 0x8e9c123a 0x42c4edd0 0xc8247030 0xf0e6cebb
- 0xf8d1425f 0xcfa8e403 0x67646391 0x9dee9f9b
- 0x5683c4f6 0xd958ae1c 0xc62eedfa 0xbd67ea10
- 0x253398d4 0x18b7f92a 0xf101a7de 0x60066732
- 0x4ca1e3dc 0x6e1eb0a0 0x115aa9e1 0x8370aae0
- 0xe46756d8 0xa02eb1aa 0x854dbb8a 0x6334873e
- 0x87613a81 0xb5bd56df 0x491371d1 0x02bbace8
- 0x2a2e45f9 0x91bdc460 0x2bcf90b6 0x81df2f07
- 0x34aa2dd5 0x5b54a117 0xb7a5bd42 0x713e2287
- 0x1ea184d6 0x176bdda0 0xa19c0d86 0x4180fd5c
- 0xd018a4cc 0x60120a37 0x8f6e094b 0xfebe1b15
- 0x42866bb7 0x4a9f772e 0x0bcf9cad 0xd936a924
- 0xec6cf0a1 0x1f9ccf16 0x81f8229f 0xdcef1733
- 0xb4a31fca 0xefbf0a0a 0x057e0b4b 0x59491c96
- 0x70ce99bb 0x908ce274 0x637ae09c 0x479fdd52
- 0x11ea6250 0x7778cdf6 0xd0ffe2ca 0x539b18dc
- 0xbcdab649 0x3066399b 0xd685edc0 0x79d8d588
- 0x32942aa1 0xd03531f7 0x5d024d56 0x4dc99729
- 0xd1efff53 0xdf3ce9a1 0x31462a0e 0xe5427113
- 0x395e2980 0xcf5c9d4e 0x91e11088 0x7e4d31e2
- 0x5ff91ae8 0x9340e815 0xfcb89789 0xcb1b2f58
- 0x655aa934 0x2eb022da 0x419104a9 0x6b648411
- 0x582048e2 0xa0db392a 0x1e1d6443 0xf3c7a401
- 0x1e737591 0x452af94c 0xfcb74331 0x2da70f75
- 0xa8b59eb9 0x736224c8 0x5ba81657 0xfb36eac0
- 0x4e0336b4 0x8925a32c 0xa4d60fde 0x8a95ff27
- 0x57a7e536 0x7e6a2f58 0xd9e9751e 0x817cc66a
- 0xca4bd134 0x627382fe 0x00e56736 0x74844fbc
- 0xab1f8265 0xa32955e3 0x41cd361a 0xb3ae6366
- 0x1f77ea37 0x2200c6ef 0x81854e76 0x49ed4e92
- 0xb57a7fbd 0x7b9de6d2 0x128feedf 0x57bb65fd
- 0x20ccd650 0xdcde5458 0xd5461b27 0x465147f4
- 0x70719068 0x2cb48f5d 0x6edc0d43 0x83dbda97
- 0xf077ea64 0xf61423e2 0x39a55177 0xb23ff07c
- 0xa02e4ca4 0x9e6250d3 0x77f1df9c 0x238c632e
- 0xce253a6a 0x096327c5 0x87f1db29 0xd75ac0de
- 0x456704b5 0x9ee7046e 0xd693dfe0 0xf995c6b9
- 0xa354d140 0xf16bf090 0xaf511cdd 0xdc56d21e
- 0xd7cc4d4c 0x5398cc1e 0xe5444b3b 0xe192f473
- 0xd09ae67d 0x8af2775e 0xc1af44a9 0x57bc4586
- 0xa6ff5419 0xdd4ba49d 0xec4864fa 0xda9d0357
- 0x84dfbe33 0xf41ba9c4 0x99e2bda8 0x9fba720b
- 0xa7dd9e92 0xa0d43386 0x3e0f9ef2 0x6e388282
- 0x8f47ea95 0xac920523 0xa98ae8a5 0xf6a6a4d4
- 0xc3fa2e55 0x74a21b36 0x9c0b14b2 0xc6b8a79a
- 0x367b7036 0x24b9f255 0x0b543b75 0xb630fa41
- 0x1b260452 0x7daf6714 0xdb8a13d9 0xede8f6bc
- 0x47a21d0c 0x01d9ca54 0x4a8e5cd4 0x257cd217
- 0x7504cecc 0x973bbf11 0x992b731e 0xaab55b65
- 0x77e2f058 0xf580b58e 0xb10419fe 0x679aa4df
- 0x296c1d64 0x751380f0 0x8f70f0de 0x3f78bdb8
- 0x1ee68ad6 0x7d5d50e4 0x823710a4 0x18b98d13
- 0x86bdf798 0x953b8131 0xb5da3d24 0x2eccd3b1
- 0x828a154c 0xed51b913 0x566e58ef 0xab8ff1b4
- 0xc744d227 0xe705bbc6 0x6032eb64 0x5495e4a5
- 0xe83add11 0x08429de8 0xa2e397dc 0x4f00c90b
- 0xcb7672e8 0xa1d55607 0x0741ca2a 0x323d64f2
- 0xa700ef1e 0x6ccb2967 0x07c29e41 0x018440a9
- 0xbb1880cc 0x35502720 0x8a13a96e 0xe2bfcd29
- 0xa76ad3aa 0xd95be915 0x6dd66033 0x41d655f3
- 0x02009028 0xb44ec634 0x82e61d87 0x216e624a
- 0x7fc79105 0xac0307cb 0xd22fa331 0x63746b2f
- 0xe51ab72d 0x9b550c82 0xb28dbc01 0xd569d017
- 0xd168d372 0x8d6bfe6b 0x5820751c 0x820a4e23
- 0x13cfd07a 0x678c8319 0xd1e65476 0x752967ee
- 0xafb28392 0x390d5488 0x53668098 0xa0c92673
- 0xaf0549c2 0x644f51c3 0xd59df083 0x7cb37a42
- 0x12261017 0x038c15b3 0xccc30b03 0x85ee24ce
- 0x1e029b23 0xb6bb2845 0xb62a305e 0x2d0cf4e9
- 0x182b887f 0xec423ce7 0x8c1c0b25 0xc83b4737
- 0x71fb9023 0x63d639f6 0x16c1ce44 0x66ac8331
- 0xd9aa0975 0xba3d445c 0x5d097729 0xb353a034
- 0x23811786 0xb81394b5 0x5323f1b3 0x7a3e1576
- 0x3f2867ad 0x0bc88c8e 0x74b60d63 0xd56335de
- 0x0d40f71c 0x55ec2524 0xea3a2c78 0x19e5e0ae
- 0x9bf3d033 0xf57bbc94 0x05b6ac55 0x4c368744
- 0xae8c68f2 0xf23aad06 0xcf94d185 0x2360ff3d
- 0x0e8a87f9 0xb97c8d33 0xa7122e6e 0x5ad4dc50
- 0x6145ff8e 0x617389df 0xe8a0e09b 0x4d40ce6f
- 0xee2b65fa 0x4104d368 0xf4bc9d85 0x0b67abbc
- 0x7bbad9ff 0x26b293a2 0x06055372 0xbbb05665
- 0x0560311d 0x421dc535 0x9c451ac7 0x38c83a74
- 0xc8921ff8 0x634d52c5 0x6e66dae7 0x1c86fae3
- 0x5a0645bd 0x6e5fddc9 0x86852d55 0x76207d9a
- 0x6a4b7990 0x661c00eb 0xb268e55b 0x17daec24
- 0xa2854da4 0x9b1f3f63 0xdd200bc5 0x0b50aecf
- 0x8242f913 0xc7ab6eea 0xaa977c22 0x748d0d1b
- 0x4490aae4 0xaa293e18 0x69aa0720 0x6115eb81
- 0xa5b187fe 0x828bfe34 0x5fb6d155 0xe764d755
- 0x08833186 0x8475cce3 0x718bfb48 0x063b287b
- 0x7ea71b59 0xbedbfd29 0x3736aa07 0xe2dfd533
- 0xf2ea49a3 0x96b0983a 0xc1f60b14 0x511bed9e
- 0xac976686 0x9c60ce3d 0xfffd0b07 0x59d7cf79
- 0x477942b4 0xff2f43cf 0xeb4b899b 0x37a47783
- 0x8e6602a7 0xb6bfc410 0x7685c6e4 0xb7ec103a
- 0xd54fdb01 0x3933d261 0x725982d1 0x86ada0a9
- 0x83788370 0xbafb1498 0x13972979 0x2157be41
- 0x5e976c80 0x05501107 0xb3b66da9 0xeebcb8fb
- 0x42ac1fee 0x1dba34a9 0x3f5a7582 0x362e7ed7
- 0xaa69be91 0x419f4d18 0xb09a9967 0x31aba127
- 0xaa247bff 0xb31f4958 0xe79562af 0xfb73878c
- 0x47dc697a 0x5d08fa9b 0x91dcd3c2 0x53e52d33
- 0xc84ddc84 0xdb5f8e17 0xe51889e2 0xb1aff523
- 0x4ffa0702 0x2c72b35a 0x9a4246fc 0x62420517
- 0xaad11acc 0x18190bf9 0x11e140de 0xacc99086
- 0x39347992 0x191a53d7 0xbe92c4ef 0x9a934b5d
- 0x64cf7353 0xe30a3e8d 0x0aa6db52 0xb0a7e26d
- 0xc8fe2f52 0x2e274a07 0x0c94b6ba 0xf80eaf3c
- 0x1ba3e94e 0x5853ffe3 0x11652833 0xce7b0839
- 0xd1893c23 0xd06d2078 0xa65f020e 0x281e6a7d
- 0xdf1da5a2 0xcdf69d20 0x74fa9b92 0xd98d6000
- 0xb732496c 0xbd12f87e 0x561dc55a 0x651d42ff
- 0x5736b74a 0x2c48a906 0xfdcbaf15 0xf76606e1
- 0x80dd0254 0x8105e60b 0x143200b2 0x0f02f524
- 0x1580d2c6 0x7281c6fc 0xc971cd31 0xd4a57180
- 0x5051e5ec 0x193c72eb 0x930332c4 0x488d7403
- 0xa93e425c 0x93e8ca97 0xa0a55070 0xafd8f8fc
- 0xc424f1bf 0x11050ed2 0x855d0923 0xa0fcef35
- 0x61f9e84a 0xc2196706 0x7221d5f7 0x96d036a5
- 0x137ca3fb 0xfd632623 0x30b10850 0xdda390eb
- 0x270fc9af 0xe6a8d748 0xf55bc288 0x8cc912d1
- 0xf2d9cd15 0x5ded2f07 0x2de9b076 0xf5088354
- 0x885becf4 0x959ef88a 0x0d9ea589 0x2ceb0a27
- 0x8925270e 0xca5ecd99 0x8ba9265c 0x209eb0b7
- 0x2e8b51d8 0xc598e096 0x23c17aa7 0xf600bcae
- 0x7b33f831 0x223e1501 0x361c9f12 0xe6aeea94
- 0xa5c6948f 0xd1daf8cc 0x0b0e0b54 0xb0cea6c7
- 0xa437fbc8 0xdb4139ab 0xcbbad47a 0x124e2117
- 0xfb80c5dd 0xef085f4a 0xd24c5fa8 0x2548a1db
- 0x5e6cdeb2 0x8e4f0290 0x78cd8245 0x1ebb5eb6
- 0xd9bf1208 0xf20eaf0a 0x544df94d 0xebc9c742
- 0xbc5b4bbe 0x33f6fcaf 0x32efb07a 0x55d91b59
- 0x2c0ed1bf 0x39985cb7 0x4cab882f 0x530cdaca
- 0xccc78cfd 0xdd834c48 0x7ce7898d 0xf7458891
- 0x933c2ae8 0xa06c5762 0x2eb03e35 0x8e938b71
- 0x3636f142 0x0026efb8 0x183d71c4 0x7e8ff92a
- 0x63265ea6 0x0f1352b8 0x73f8a8fa 0x6594e921
- 0x401f88db 0x64abd8e6 0x994140c7 0xb2258b0c
- 0x9bd6e6a1 0x92bab589 0x5919a943 0x29ab4d8e
- 0x33cbb8d4 0x57084d92 0x006c4d50 0x57c49e54
- 0xec1ecfe6 0xeaa8109a 0x269d94a5 0x4a664f84
- 0x2bda2944 0xdafb85c7 0x2a7b4b8c 0xd8f124d6
- 0xbbac0e70 0xeac5a129 0x308d7e39 0x99a023a9
- 0xf616fc22 0x76fcc40f 0x7f745409 0x83872303
- 0x0b067846 0xdf90a414 0xb6d9b6e1 0x8d0f93d8
- 0x6f76a627 0x02f89060 0x392cb9e0 0x6acf19a9
- 0x7cffe4d1 0x9928b4a0 0x87a031bf 0xecff42d5
- 0xa376e023 0x69d2e1e3 0x1fb67afd 0x5396049a
- 0x45538549 0xec0e6f60 0xf1ab27e5 0xc679e764
- 0xee430c38 0xa6b0c2dc 0x92824db1 0x65d5ffe7
- 0x448b17d7 0x9c67c8e0 0x14b36e2a 0x283de0a8
- 0xc59bb35d 0x8faf1ca7 0x4265db7f 0xb0e74749
- 0x0924d389 0xc22bf3fa 0x017c143d 0x93b4e0d4
- 0xf8aa8e07 0x07e0293d 0x5b40bba8 0x619c8946
- 0xc817ee7a 0x82fd526b 0x3e5b0f9a 0x5b352d98
- 0xc786d63a 0xcbec5c0d 0xd05e9640 0x7cab758e
- 0xaa9bd61d 0x205ff53f 0x2f093865 0x55ef390d
- 0x4b008d12 0x0344c52d 0x64820f87 0x8e9c5202
- 0xdd3f2276 0xf3b46630 0x80e85ea0 0x9aea428f
- 0xa205b11f 0xa8506b8f 0x2c89f419 0xb0b9694b
- 0x21029e6a 0x5e05869b 0x3baf3c6f 0xde680ae1
- 0xd65b5eb0 0x99a6937c 0x52a78fe0 0x6f577b06
- 0x8dea8d63 0x2417d49c 0x1a0ecb5d 0x91f22002
- 0xc540298f 0xea9f8f6d 0x01ccfdb5 0x287138c1
- 0xef206774 0x9d5deed8 0xba844833 0xf612317d
- 0xe0bd4bb4 0x595d0440 0x73643204 0x2c21370c
- 0xf9d5df6e 0x05614527 0x73c4edee 0x33f45ded
- 0xbc47170a 0x24b94b30 0xff304e54 0x4e0c3b53
- 0x658af390 0x402418bf 0x9db7318c 0x058721ed
- 0x896bdd56 0xa956c5cd 0x3f928400 0x94c93146
- 0x56600758 0xf46f4f66 0xa5bf66d5 0x0e8b5870
- 0x8ba7e755 0x4177fee6 0x32cc8824 0x90b677d8
- 0x307e9dd3 0x853a7e3b 0xa2f064a4 0xa42dbd46
- 0x243ed6a9 0x7164eb1f 0x9e97212a 0x9757d142
- 0xde296a05 0x8699a74a 0xeb02fa7d 0xf80b41fa
- 0xd9dd2198 0xd7ffbd00 0x21b15853 0x11b78093
- 0xbb329142 0x5260fb1f 0x22fb24fe 0x7a5e7e71
- 0x71434197 0xc5ddca32 0x930c8cb9 0x65192958
- 0xad1a41f1 0xc77442ca 0x72b64ff7 0xa90bcde5
- 0x184a19de 0x71df036e 0x1b69b0ed 0x023c391f
- 0xd9847da5 0xca57d383 0x0d21255d 0x2ea68d9b
- 0x0189eeb5 0x1ea62386 0x4c8d42f0 0xac20dd55
- 0xacceef1d 0x972f56e3 0x0bc40455 0x3853c5a7
- 0xcab0d1f5 0x0d2a990b 0x525be1ba 0x5cc6daf5
- 0x4d564f06 0x834d8f94 0xc0c055e1 0xef34557b
- 0x354537de 0x7207e6b8 0x659c9298 0xa88ac04e
- 0x80d8014a 0x7f4f6e7b 0x1136e621 0xb1b62f79
- 0x8d4613ec 0x673699ee 0xdd6d7741 0xdba1ffa9
- 0xe219e1b3 0x8bf64c21 0x14aadc3b 0xc4dc4e19
- 0x47ae1e52 0xc5409e4b 0xce8d29d8 0xe0b1cf25
- 0xcaf06411 0xd5450dcc 0xf14f29ee 0xf3611dd5
- 0x52bc02f3 0x886b68aa 0x3b2853ef 0x110aafb0
- 0x6b6d765a 0x87fbaa12 0xc79f134e 0x88b910fb
- 0xe04aa148 0x33feeccf 0x3be43d3b 0x067854eb
- 0xf22561e5 0x56c3abc3 0xcf0ff408 0x6291d940
- 0xe26819d9 0xcfd04da7 0x94ab2808 0x156dcd0a
- 0xb6d1c47b 0xdca4aa76 0x877f870d 0x4e06ec17
- 0xbb560b01 0xbe1b62e7 0xd98b51b2 0x7083e3d5
- 0x427ab621 0xe5fce36f 0x606dc14a 0xe4b70b49
- 0x982d2446 0xf2d2e82a 0x60836061 0x681317fe
- 0x1667e3c8 0xf6eef490 0x1ad768d2 0xbc86ae5c
- 0xfbb392de 0x868caaaf 0x8429b5ff 0x266b6d5b
- 0x372e8f2e 0x6e875cce 0x3a972f08 0xabddef20
- 0xc777c559 0xd8f924a4 0xad39137e 0x4c16a4f0
- 0x91d51877 0xae645599 0x4d09feb1 0x0cdededf
- 0x5749b5b8 0x513c9745 0xf4da62f7 0x6583b20d
- 0xb599bb89 0xaf6bea53 0x7275f6b3 0xdefc5092
- 0x01a3734f 0xd95f4c5f 0x37bce97c 0x63610b99
- 0x30555fe4 0x20af2f26 0xf84b2652 0x67ef6d87
- 0x2119805a 0xcc79747f 0xaa479405 0x63a02857
- 0x1953fc39 0x4f952879 0x886bfe97 0xf0067752
- 0xa08b5005 0xcd9a5ebb 0xb04486e6 0x560c79ae
- 0xe8faf52c 0x64a9a961 0xae9a5f1b 0x74cb5ef7
- 0xf8d0269d 0x2fb63c57 0xd78a9a90 0x99cc0a42
- 0x46bb0252 0xe56b026b 0xfb5ff703 0xdc8e0588
- 0xe5d9e280 0xa73ec2b3 0xe21bccb0 0xe22ee743
- 0xd1bb3217 0x5d4b3f92 0x0a627d8b 0xf2fd974a
- 0xad0a57c4 0x261ba12e 0x1670f842 0x996ab25d
- 0xf6f8043d 0xa6cbb362 0xcac3044e 0x6fe01268
- 0xa54ab676 0x54d7444a 0xf3be5437 0x6b2b737c
- 0xbe10300c 0xea505599 0xd60a15f6 0xd971ecc0
- 0x9c480c46 0x2233038d 0x66d38df9 0xcb566912
- 0x63cffade 0x75811ca6 0x8dbfa4cc 0xee5fc07b
- 0x23329e49 0x39ee07e5 0x5de33ff1 0x601f8348
- 0xb60a8bc3 0x832d3660 0xd1bee11b 0x1a38d12c
- 0xaf00744f 0x21c2639b 0x0fd34252 0xcd63a9f1
- 0x60f34993 0xf8728afe 0x75f8bb5c 0x74a250ca
- 0xb9f51490 0x6ac643a6 0x4011a0e5 0x77288317
- 0x57f772b9 0x92c0715c 0xd5d0e030 0xde335025
- 0x669f6b14 0x55c74853 0xf3ac7cd5 0x38284e8c
- 0xb0fda481 0xf9b7f045 0x839293cc 0xdf91a0a0
- 0x18d20454 0xf73214fc 0x09577b9d 0xb5febd00
- 0xd9b96c88 0xb454ea2c 0x6204a932 0x736edf8a
- 0x9724f56e 0x3092f58d 0xac17cced 0x5ae87e39
- 0x28dd2a0d 0x3806d96f 0x5e7c8c68 0x72df4471
- 0x0207de38 0xf026ecac 0x13258e9a 0x34a8e8ce
- 0xdd7d7286 0x8d7553af 0x11ebac36 0xfb9965ff
- 0x9beda82d 0x1cd898cf 0x1b791830 0xe96ca8f0
- 0xa0d274d6 0xdd6fea3a 0x7537177f 0xdd93627c
- 0x60b64e47 0x10f30724 0x12489cf7 0x4587e1ac
- 0xe7835522 0x61d48d9d 0x6afd081d 0xafbbcf2c
- 0xe31d79cd 0x49ae4218 0x7c2c4a33 0x4fdf949d
- 0x52ccd576 0xef2c3d62 0xfd5b75db 0xe6a5c2e9
- 0x04fc9c6e 0x47fde414 0x8a87ebfa 0x850904e4
- 0x2f49b552 0xb5f186fd 0x772a4ba3 0x48d0be3c
- 0x846c7d78 0xc1c2a1d7 0xb9375f9d 0x302ed828
- 0xf79208f1 0x8fdc4f71 0xc749ed51 0x1cd0c28c
- 0xee5a5f7e 0x7f02b7ca 0xdc3b531f 0x99c0119d
- 0x428e5474 0x10515459 0x8d804d27 0xb7c00220
- 0x264c2695 0x7aa6e5af 0xef807715 0xa444f446
- 0xe51c7755 0xcd825b6c 0x39afa440 0x88638e46
- 0x4ea4366d 0xddfc9854 0x99696f2d 0x210592ea
- 0xf4763dcf 0x7358acdb 0xedfc8523 0xe46031c8
- 0xc9762414 0xa71a348b 0x084b6c82 0x9162e0d7
- 0xda6a5b8a 0x68ca14d5 0x6385741f 0xb103d4c2
- 0x44299ef8 0x9aba89fa 0x2c87dcfd 0x476865df
- 0x1189dbb2 0xdcd9d19c 0xac2bbd51 0xa71526f5
- 0x745222d7 0x4813ca98 0xcfa5802c 0x5d2b3907
- 0x8a17d1b8 0xea56f907 0x3ea58d71 0x933fa242
- 0x021f46a7 0xab8d4e86 0xfa4eb33e 0xaecbd5c3
- 0xb3258e74 0xaac9f193 0x415a5518 0x28b13031
- 0xbae39e53 0x1072fd5a 0x4e0fbf55 0xb02c5d77
- 0x5949c780 0xbecf72df 0x15e52c72 0x3ffeb165
- 0xa8e73d50 0xa52fd918 0x2b3c4d7c 0xa1e9e021
- 0xd8e91949 0x63bf63ed 0x8f2e150a 0x9cbceca9
- 0x33b10a97 0x4d2c69f7 0xf26371bf 0x0b5214ec
- 0x10eb7fca 0x1958b429 0x25f190be 0xafcfb396
- 0x7aec0c45 0xf9a0f163 0x9c966818 0x28f83619
- 0xe35c61d4 0x1ad8a656 0x576dba63 0x7aa44804
- 0xf941b7b8 0xc5faf3cc 0xdf1fd628 0xc009417b
- 0x366ea78d 0xd3cb7030 0xf3f12e97 0x5298cc89
- 0xbb43c8ef 0xd0a8ef96 0x564bced6 0xbcbd865c
- 0x5c80b1d7 0x131ccb04 0x7502d06e 0x465f5cb0
- 0x93320c4c 0x9df42986 0xbdb1fe26 0x48ae8bdd
- 0xaf44e912 0x6aa468a5 0x67ecbb05 0x30b7c0a5
- 0x3ad75711 0xa2d5f63c 0x30150058 0x4d748121
- 0x70804875 0xf46b6ea6 0xa3fcbb7b 0x1af6b4c4
- 0x48496de1 0xdb1a2321 0x758eb79a 0xf35f697f
- 0xb4ff9dfa 0x38ab5b31 0xc918f6f1 0xb3a259fb
- 0x3610afe7 0xdfcaaa0b 0x00c747dc 0x96c40b4a
- 0x5c815168 0x29198fee 0xc94eeea9 0x70432b55
- 0x5de7bbd4 0x0995652d 0x4b3e846c 0x7e4c9ca1
- 0x7c0e91e6 0x401a820e 0x3ca3429a 0xd3812f44
- 0x9cb6a5eb 0xf03ce395 0xefca548b 0x8943bc10
- 0x472b2108 0x82d4a386 0x1d0ef931 0x94cd70ef
- 0x2d00d619 0x40d36f80 0x238ccc47 0xe0856568
- 0x9f06ad8b 0x95a4052f 0x287a57fb 0x9e9f9891
- 0x62bc3a31 0x24c3c1f8 0xbabdc3c4 0xfa40629d
- 0xd16f1f33 0xa9f7600d 0xbcbdb2d9 0x214f24be
- 0x623ea3b0 0x8d650418 0xe86635b7 0xb834745f
- 0x20771340 0x3c69a0b2 0x8b7c84cc 0x740e475c
- 0xe5a540eb 0x9e216852 0x1383201e 0xfbf1f572
- 0x9680d736 0x3d7f8d69 0x615ea313 0x87bc1297
- 0xe552725c 0x9bfee104 0xf2e87d90 0xde9188b4
- 0x028d268b 0x51c75c60 0xed93377f 0xc380d9d9
- 0xe858bf8c 0x5d0b4a40 0x05a3171f 0x76ae3ec0
- 0xf86e3fe6 0xc3d78254 0x7cd640c5 0x6835dacb
- 0x983bd9a8 0x05d1e564 0xc5d5e9b3 0xf81c6560
- 0x8ecba474 0x071daa33 0xf5010276 0x5432ba59
- 0x10f2dbc1 0xbe892680 0x7e92d3d7 0x8d2f0113
- 0x37fa8034 0xb13058f4 0x44684553 0x2bd0e36a
- 0x67ea83ef 0x815e7115 0x3cd123af 0xd9aec852
- 0x67c61c95 0x861d068a 0x60c7797e 0xd9733b31
- 0x9ed29f37 0x1ccc8e08 0x34bcfa7f 0x1c66914d
- 0xc64dc834 0xad884c08 0x2b22b8de 0x53d6fd78
- 0x0355dcc8 0xfd363485 0x62370358 0x0dcb046d
- 0x22fe7d2f 0x5fdd1117 0xccd6d8d1 0xe97925a4
- 0x309aca3d 0x56c31fb9 0xe6f81e08 0x24fc0560
- 0xa78d459b 0x4940b35b 0x9a4a2fdb 0x203eafb8
- 0x91e5fcab 0xfb9be08e 0x9cb903ac 0x31598d89
- 0x4f41986c 0x77206f4e 0x61811c9d 0xff51d95b
- 0x2d7b4c66 0x84ceb768 0xfb135597 0x58087b13
- 0xa1681cc2 0x14009e31 0x778c3fec 0xe3faf2fb
- 0x5092b2c9 0x8919c362 0x34e2b174 0x7bb04f44
- 0x63c39b5e 0x8ef696ff 0x2e4c612d 0x77d390e2
- 0x5dc958a1 0x528bb31a 0x1cb07e7a 0xe37c9c53
- 0x002856d7 0x6a10b962 0x423a7b39 0xc6da9227
- 0x207800e9 0xe200c119 0x0e5af6f3 0xfb580459
- 0x71dc40a0 0x70434cd9 0x13f7f455 0xdf3fd7ca
- 0x37cbc698 0xf5a5808d 0xa7bfdf32 0x8a0774c7
- 0x75b67d50 0x5a6908c9 0x23611a6d 0x8b50c483
- 0xfe1e2eba 0x7ee1c732 0x2191e47f 0x9e63eb3a
- 0x379cd875 0x4df7258d 0x166a8aa8 0x1c94586a
- 0x2456c4d3 0x000185fa 0x7a196b46 0x914e789c
- 0xf562c939 0xb3bad5db 0xc2c19b89 0x8a621ffd
- 0x0c807ce0 0x701a938f 0x69234cdd 0x36a00f09
- 0x964c43f7 0xcf71cd85 0x5f504e16 0x446c6388
- 0x25742397 0xf1a375c8 0x6bcf822c 0x1b175fd7
- 0x0fe78e56 0xfe7817d6 0x66da0366 0x904e8327
- 0x5a0749fa 0xef3ede57 0xd0fa2ac8 0x89791771
- 0xa5cd616f 0xe9ef2860 0x9b533bc3 0x1d746f03
- 0xf4bb82b5 0xacae0438 0x840b3e34 0x30371a0d
- 0x8590acf3 0xeb4ff7e4 0x40437052 0xba847bf6
- 0x24059538 0x44daca63 0x23b32e28 0x091386e0
- 0xc480e66a 0xe4a839f5 0x34929bcc 0xb9051207
- 0xd21252f9 0xc6524769 0x8c422851 0x36280aad
- 0xbf00b1a1 0x4e36c85d 0x7949e8ef 0xf76be57e
- 0x373a0ab9 0x1b7555a0 0x0c2caf56 0xc9241f75
- 0xbe5b0ee8 0x5a486f75 0xfb2c050d 0x6aeda464
- 0x3fa744ee 0xf6e055a1 0x0a7324ab 0xfab58776
- 0x09baaf66 0x459ce186 0xc6eb1894 0x56a4ce4a
- 0x58ce1069 0xf4debf5e 0x04a145b9 0x1a246583
- 0x9b07fe23 0xd4d37068 0x7321e0bf 0x2dfe17f3
- 0x426dd8a7 0xc561a2d5 0x7f515a47 0xe57d37fa
- 0xa85f0aa5 0xffb78cd7 0xf30c4551 0x3572c02b
- 0x6f4a4cbd 0x7322ecc7 0x170a7b9a 0xa1e80d28
- 0x5a366af2 0x4f24a3a7 0xfefd29ca 0x0d7b02dc
- 0x1adde2e1 0x5c426cc5 0xb1e53b76 0x5dba2c5c
- 0x1458b6ca 0x73cea912 0x39626c25 0x7547e76d
- 0xfcddbb97 0xf03d59ee 0x3cfdab3d 0x309db86e
- 0x3de8df47 0x4a570e6d 0x09c9579a 0x19ac033e
- 0x0a7a9a86 0x3662d261 0x048fa67f 0x4aa4009e
- 0xc7660654 0x524d81f1 0x3157ec52 0x857d1f10
- 0x3770162e 0x3d1ff919 0x732d2b13 0x84187da0
- 0x95722d45 0x362cada5 0x5d67637f 0xdaae8465
- 0x9f5c0699 0xab9aba98 0x6f97d3fa 0xf9cc4120
- 0x0ca1872c 0x1a832c9e 0x7b74d6ae 0x98dca967
- 0x03eb7699 0x5fd02b54 0x962c6224 0xde1ab807
- 0x800af435 0x2458a4ca 0x717de910 0x31648afc
- 0x871527de 0x3cb93892 0x45237e37 0x446b1315
- 0xecd807e8 0x70f38e30 0x140dc60e 0xaef7b7c1
- 0xadec312e 0x94d45820 0xb8960073 0xe8dd5bac
- 0x7616ab11 0x0c3cc190 0x516003e3 0x323cdb39
- 0xd679f9f4 0xd7c179d2 0xdfbc5e24 0xaa1226df
- 0x3cd41b0e 0x88f436f0 0xbd5b6cb1 0xb78c69aa
- 0x982e0ca0 0x91f852a3 0xb331636a 0x28df67ee
- 0x81b029a1 0x9e7375e3 0x56e874c0 0x8b93a735
- 0xa47eaa4e 0x772ad825 0xfb83ba8b 0xc08db79a
- 0xcb7a34be 0x14214d72 0x7d6fa82e 0xe75c7002
- 0xa6290902 0x716d04c1 0xc75f0a97 0xb68e0912
- 0x08b5ef1b 0x507ecac3 0x2d740b08 0x43b6c7bf
- 0x3965675a 0xf56dc4fd 0x1ba44239 0x36753f70
- 0x0b2452fc 0xe36bafe9 0xfc3134c3 0x2ac78286
- 0x69ba53b8 0x225b9bd9 0xaf426f79 0x99bd2d3e
- 0x0bcb8e18 0x28c87047 0x2045b3b9 0x730ec870
- 0xe6558839 0x9ca3de82 0x263a41e7 0x1c8ea255
- 0x334eb3ad 0xc36d6793 0x66add8ee 0x652c8548
- 0x79dca1a8 0xc2526972 0xd10f03e2 0xdbae6f42
- 0xe223bf69 0x10082495 0x74ba4cf9 0xeb71ef5f
- 0xafae5d4e 0x7b3663e9 0x9339468c 0x31edca72
- 0x65a07876 0xf336fc1a 0xaa505397 0x011d5253
- 0x99b88ade 0xa688f0fa 0xedac589d 0xab4d8f45
- 0x0ff866a1 0x61280e9b 0x65c5a63f 0x8b372073
- 0x7a4c88df 0xc74f7959 0x19597c51 0x97c8a27f
- 0x33eb652a 0xffd40c86 0x57a2ca0c 0xaabc6cc8
- 0x54fd2280 0xd5b59006 0x2e00f009 0x72bd86c4
- 0x24936e04 0x877188de 0x91b60401 0xb949b337
- 0xdab93e69 0xdffeab2e 0xb3aa7c79 0xb8612f31
- 0xf0c53b58 0x8896833f 0xda35944a 0x1867027a
- 0xef6bfce9 0x8213f320 0xac477eb2 0x92368362
- 0x606cfdc4 0x27c98907 0x50673ac5 0xec48f5f4
- 0x39e879f8 0x80d050c8 0x9febddbe 0x5d797725
- 0x06d8b755 0x0319d93d 0x7eae3ce5 0x8963ed64
- 0xc91772c9 0x4e031095 0x2fd03d3e 0xe774ea89
- 0x7dbc97ab 0xe8d8f361 0x6e167fa1 0xd1520c5a
- 0xb3278325 0x8acaf913 0x6ea81dd4 0x9e3b2a97
- 0x0a5b8a09 0x84000db1 0x59a30fa9 0xf0b6868d
- 0xfb62b0ed 0x8953057f 0xdbbca3c0 0xc103b876
- 0x47420e14 0x1eb22bed 0x58c8f65e 0x3a689da6
- 0x8ed1a99c 0x869ddc49 0x60015d09 0x2264c797
- 0xdc10c6ac 0x7275327e 0x8d47d2ab 0x87a75624
- 0x3dd8fcb6 0x40e67a31 0x98114b1f 0x7e3a5976
- 0x1d9e62a6 0x988c0398 0x0c7c0d8d 0x0aad4954
- 0x3c40a234 0x7b752b7b 0x79f94813 0xa0b86dec
- 0xe3f646ac 0xa993f76a 0x6f9d1f99 0xe883dabf
- 0xb8ab1b2d 0x6766ac8d 0x6b9a793a 0x02f55fa5
- 0x351a96ad 0xd190f768 0x35667fe0 0x6a85c938
- 0x72444e33 0x5140a848 0xd3062250 0xe4ce902a
- 0x44e7d9d3 0x7c8d48fe 0x4d26a61d 0xbd013c4b
- 0x540d32bb 0x9152cafd 0x09840a30 0xd7a8663a
- 0xd5a3ca17 0xfd5dbe65 0x655b226f 0x7cb9debc
- 0x59d300dd 0x13737132 0xdf0d004f 0xe98bbd9e
- 0x5626fb54 0xb6d66fbd 0x273087a8 0x032969ea
- 0xbd69c191 0x010cdfff 0xb2a9cea5 0xb8778e4c
- 0x8f0dd084 0xc75b4ce6 0x9c027c6f 0x36c58105
- 0xac424eb8 0xa15d2883 0x9e73b7b8 0x54e9aade
- 0xb9500a5a 0x97505e35 0x4c59b36c 0xb3ad1302
- 0x31e21ed1 0x78bcd74e 0x2d9fc122 0x49bae35e
- 0x5c8f01c0 0x8d29829c 0x0c672566 0x37938db5
- 0x4959e71f 0x0d2365bf 0xaab666b9 0x52b2cffc
- 0x200ee1f5 0x5dbb262b 0x9aae28df 0x3223780a
- 0xb65218cd 0x633b797d 0x93f42423 0x3268b3ae
- 0x141e506e 0xb1ed94b2 0x497b7973 0x9f2db9f6
- 0x5260bf9d 0xb30e4310 0x4a3539ec 0x275d2ae2
- 0xff43e500 0x645e30e5 0xf1527598 0xb76ec4cf
- 0x88fc44e9 0xde68932c 0xe61aff6b 0x19d042b6
- 0x11981ff8 0xb0d595d9 0x52764f82 0x7e0ca214
- 0x8cc51237 0x581f2a1a 0x482420b3 0xd47ff971
- 0xcff78344 0xc019eca7 0x3146ab02 0x107a3ee4
- 0x16dc120d 0x33a239ec 0x0ea84236 0xebc7a1f4
- 0xd1f2fa2a 0x9464c008 0x2b76a4fd 0x9b4acb99
- 0x00f6a92a 0xd68b8d15 0x25e1e58d 0xe1fe3cd1
- 0x6fbce2cd 0xf78be2dd 0x09b9c08d 0x6b32d210
- 0xd06e7c95 0xd62f47f4 0x92c717ca 0x44fe3d2d
- 0xaa13cc08 0x3d411f94 0xc2eba262 0x7521c9e4
- 0x77d6cdc7 0x22d76158 0xca2efacf 0x3e51004c
- 0xef9a82d6 0x1508d20c 0x923f18ff 0x3eaa88e6
- 0xf2f32bc7 0xe74b8483 0x82529884 0x58b38ad8
- 0xdd9f2a5f 0xdf54adc3 0xd4497667 0x789c000b
- 0x935d1743 0xa52d5f1a 0x4e27adf6 0x5c3334af
- 0x6cf71ba0 0x501f8353 0x031fd6cd 0x4831ec4f
- 0x08c847db 0x6a6e0657 0x0bd803d4 0xd7c48cfe
- 0x94b7e25f 0xc6516ebe 0x1001c08a 0x0e165da9
- 0x4e39605f 0xe3f3637a 0x013daae9 0x217168b0
- 0x6013ab5f 0xd5b7eb97 0x8ce6b6ef 0xc4259f29
- 0x470e90a9 0x7a254ff5 0x8dcbf841 0xa2541a7f
- 0x4880c5ea 0x28c750ea 0x043a0200 0xbeb9653c
- 0x46e354d1 0x64f7104e 0x05a64bf3 0x7db42752
- 0xbbd38c7b 0xca7da1d9 0x916c7ebf 0x1df5e3e1
- 0xef0897f5 0xd0456a5c 0x629b50a3 0x8caefdc3
- 0xddbf8b94 0xf6e6b341 0xd8ce3e02 0x27c96419
- 0xb2659ab5 0xe8d576df 0x9f136353 0x6f5230f5
- 0x68417adc 0x39b65378 0x4b742f21 0x96d071b1
- 0xeb046da9 0x245ecb46 0xc17eeec3 0xd7c56615
- 0x07df9b8c 0x647ee4f4 0xf15f7e7b 0x825b87eb
- 0xdc67dd20 0x43c38867 0x977868ca 0x3a299ef2
- 0xa75073f7 0x2dcd59e6 0xc6c78c75 0x63a00767
- 0x74dfba2d 0x7880c7da 0x83f72bc6 0xa9750166
- 0x716b3abe 0xc949a1ea 0x7e5fc036 0x574ee475
- 0x39c3cae9 0x8c1dacdb 0x640fcc41 0xc69437e8
- 0x5d33a950 0xa28e483a 0x4031cf9b 0x0007e3be
- 0x6e3f277f 0xe25d3025 0xdcbc4a0a 0x7451a537
- 0xb372169f 0x21ff0e91 0x1978aa74 0x6471624e
- 0x01a03f20 0xeb391a3c 0x70d18ad5 0x47c9ddcf
- 0xd9415b2f 0xd9ea29ce 0xffa0677e 0xeff7a04d
- 0x1d384ff4 0x66195704 0x22736810 0xad754f27
- 0x782ae9bb 0xffed05b6 0x5ae3f21d 0x5eb2c577
- 0x0101cf91 0xed0322ad 0x56ac50c8 0xc513b1c6
- 0x4f62ba8b 0xbaffd6b6 0x6649baa2 0x8702464e
- 0x78947007 0xd6e97d6e 0xde7c6abf 0x2bdee498
- 0xcee1db1a 0xb98149de 0x47f32f5c 0xc6c354fc
- 0x6e148fad 0xb343cf2f 0xeac6a9f0 0x33dd1560
- 0x923403bb 0x87d6e292 0x0b1cf653 0xe8b76402
- 0x5f21a955 0x236dec28 0x214663fd 0x1917539e
- 0x3f11ce80 0x1bb35a2c 0x38a358f1 0x15f67224
- 0xc65394f9 0x63cd4887 0xe8e73d2b 0x51b6204a
- 0x8eeae8f5 0x6e071c8f 0x55c23dca 0x4862eaee
- 0x0afa0037 0xc98446f3 0x09181a1c 0x41e46e02
- 0xcf13d6b9 0x85907776 0x30116b18 0x27b8c7b1
- 0xd153a5ce 0xc95c90b2 0x34392718 0x8103dbe4
- 0xe012a7be 0x6aeb8c6a 0x5bbaddbe 0x221eab21
- 0xaf769239 0x2621a689 0xe8c41061 0x5890f76b
- 0x2c4dadd4 0x2ad2e669 0x394209b5 0xb272b2ef
- 0x560031cb 0x4ab7be9c 0xcc5e92e4 0xc0de0667
- 0x7a39cf63 0x03482c6e 0xd653de11 0xe14466e1
- 0xf2dbaf25 0xc34d1c0c 0x03eeb3e3 0x8260874f
- 0xf6e2ef37 0x13626fba 0x15b7efe4 0x069cd153
- 0xbf631788 0x797668a9 0x724d831a 0x0ceeb589
- 0x9559cd31 0xb995d2d2 0x7564c4ef 0xfc45a3dc
- 0x1cd999e3 0xbe090229 0xab4f9383 0x879156a0
- 0x06e1d37b 0x3796487a 0xaf1e3884 0x1f9a59ef
- 0x6c2d8a7b 0x0a8a5ffc 0x4cd60f03 0xa60bfc63
- 0xf67c6872 0xf19b75cf 0x041cc864 0xc563566f
- 0x58ae88a0 0x3747b0c1 0x64cd86fa 0xed185c5a
- 0xb71533c9 0xf15672fa 0x2722d209 0xb71ec7d7
- 0x3143a8a5 0x61c18934 0x3a899ec5 0x4274f336
- 0xea7c52a9 0x9193cd11 0x44c471e7 0x57fff360
- 0x53923783 0x76d57ce6 0xbff32513 0x4dbe0d39
- 0xb9f80483 0x62ce4d25 0x5941e9fb 0x7dfedfe1
- 0xa33f9130 0x336e6539 0x1de31e79 0xb6855a41
- 0x4db2db67 0x02a9f1ed 0x019bcf20 0x53ad0ce3
- 0x4d049f95 0xa9de2c6f 0xa26f6997 0x28eafacb
- 0xa5220548 0xb4675e1b 0xe776ee88 0xc93e6c37
- 0x7868630d 0x1690625e 0x6eba0fd4 0x78f598ff
- 0x113fa1b7 0xcb025590 0x2ee34123 0x92241df5
- 0x6edbf0b2 0x3bc2e0a7 0x710ce59f 0x656f0eb7
- 0xa598424e 0xeca53268 0xb6a44542 0x5bf6674f
- 0xad483960 0x35290b93 0xfba74c81 0x78141ea2
- 0xd6baf9e7 0x8e5a08e6 0x4910c5b0 0x7b140d21
- 0x1958c79e 0x0dbed125 0xcfbe41dc 0x089fc4ab
- 0xbf014fa7 0xff961610 0x7a2ae6c3 0x560d3a9c
- 0x2cd77620 0x3a7c15cb 0x9464d8f1 0x249a93ff
- 0x96fe6c56 0x7231a31c 0x4bcdadd7 0x62edd9f4
- 0x8ad1916c 0x3a5fbc8d 0x2a2ccd7a 0x558980b1
- 0xb0137cfa 0x3cae6929 0x587c349c 0xbcfee701
- 0xbddd49df 0xa0da6dbe 0x4cb03dac 0x5f84ba2d
- 0x7fb3063c 0x66de2150 0xbf7dbcf2 0x1c0892aa
- 0x4be8b0ae 0x5d9845ab 0xa21455af 0xc42f2e68
- 0x9b6f438f 0x5eaf4941 0xabbf9079 0x94984a47
- 0x542bdea4 0x34cf3d67 0x854010a4 0xf39a9b19
- 0xd25ffb6a 0x04364e75 0x0af97ef8 0xe10e3620
- 0x2184d002 0x0c0ca683 0xc19963c6 0x4c428d15
- 0x47ae4151 0xd11ea57c 0x437a9ed6 0x50a6b8a2
- 0x141b16e9 0xeb4ae873 0xb51180fa 0xe3dc318d
- 0x7744a06f 0x64d297d2 0x845fac66 0x5854d172
- 0xc14dbe9d 0xccba053f 0x4620a715 0x405d728f
- 0x28b86cec 0xcba09cdc 0x92823f94 0xeae2664c
- 0x48eda6ae 0x4b60f5f6 0x1772f309 0x8af285bf
- 0x9c3ae474 0x13149ebf 0x2bc835c2 0xafcaa560
- 0xc11b6f91 0x94861d9a 0x089c0d82 0x1e04d66d
- 0xf0e497fb 0x6b2d8b6a 0x9d7f0cae 0x4a93ba71
- 0x1c006123 0xed4b5f75 0x76e7826d 0x4f884ba9
- 0xbba28011 0x1e275278 0xfa72461d 0x7e70e215
- 0x1427ba3c 0x467e4f3c 0x781c5f92 0x357b7951
- 0x9de2cce4 0x524a0de6 0x12e15f95 0x7b64fae0
- 0xf27e93cf 0xc6f48158 0x9b71dbd6 0x081dc1b3
- 0x47c9c2c8 0xf110add7 0x7881b556 0x0404bf1c
- 0x58e7d936 0x04442173 0xe1e7f0cc 0x128ce897
- 0x169c0a11 0xf30b5575 0xf2ac0bab 0x91515620
- 0xe8b809b0 0x2a73d5a0 0x9ed32dae 0xcf943a47
- 0xfc157bf9 0x1a53054d 0xf0657e2f 0xf39f6ea7
- 0x92a5834a 0xcdca0c13 0x40a7b40e 0xba0e0cdd
- 0x72f595c3 0x6b7eeaf3 0x4d0fd8ed 0x9a856082
- 0xd75402c8 0xe0f8d3b9 0xee57a2a5 0xe1ccf4a7
- 0xa4fc4fa6 0x9f2407c7 0x75f94c0e 0xbf2361de
- 0x2d3b4782 0x72c35e50 0xb97f7d4e 0xbc880223
- 0xb0b24073 0x08931201 0x40e0d18b 0x559db40c
- 0x6216a921 0x031a379c 0x29bff1ac 0x1c522c12
- 0x583bfe94 0x2519ba2a 0xd691d08e 0x905dc62f
- 0x43b421b0 0xd45caaa0 0x5f099da2 0x012fc4a5
- 0x509712b3 0x67e5d441 0xc843de50 0x7e1c756f
- 0x91368900 0xc6ec0dd4 0xa41e838f 0x58eabda5
- 0xd6ad78a9 0xa037b655 0x8af4e767 0xa9b95900
- 0xdcf1780e 0x64e28d82 0x215ad981 0x292dfcc3
- 0x708d8557 0x0a507562 0x486022ad 0x8165bc7e
- 0xabffce1d 0x78fbe480 0x77b916f6 0x88f8167d
- 0xae8b8edb 0x62698ab6 0xdbc6bbbd 0x001819a6
- 0x8c096fb3 0x40a121e9 0x7b96a718 0xf6d256ed
- 0xe5c0a484 0xa09bd764 0x6552b5a2 0x1847ae3f
- 0x0669a650 0xccabc209 0x85246d20 0x61158f3c
- 0x379d8086 0x02135988 0x1eccc6db 0xf8f38c67
- 0x8e1b0f3d 0x0f6e87e5 0x936bbb84 0xe04839eb
- 0xe26b3e5c 0x3f35ffda 0x4920e752 0x014c876a
- 0x25189061 0xbe2bc4ec 0xbb2ca0f2 0xe2c1c9b0
- 0x747df643 0x26da8dbd 0xdacc3c8a 0x7d93b22a
- 0x922d9a0a 0xf82d65b6 0xd56e5f35 0x7aea7534
- 0xf1808648 0xdfa7ec9a 0xff00f8c6 0x69091da7
- 0xbb478c83 0x64e24ae6 0xf2371faf 0xcff5732a
- 0x4da88e73 0x9c8494df 0x4c0da767 0x3e22bd67
- 0x059298eb 0x9d7611ce 0x74b4a198 0xbcbe440c
- 0xe2bb1a9f 0x0ba3e5f7 0x65a5cf9c 0x8b24b6f4
- 0x7784ca5c 0x24ffc234 0xece71bbd 0x36f8e876
- 0x1b55d68b 0x2b9163a5 0xaf8be424 0x958eeaef
- 0x5d711c41 0x66d11cbe 0xfce42868 0x4a3c819c
- 0xf66d295c 0x629402f7 0x64b2ee3d 0xc0b74538
- 0xe93a735d 0x3b9e807f 0xd1d0d7c8 0x69588f34
- 0xae92b6fe 0xf5508d03 0x45b6ccd6 0xf85a18c6
- 0xe1a28a53 0x438f9a35 0xf4fe84dd 0xe3f95791
- 0x16860340 0xefe72aee 0xb13575c6 0x3d730481
- 0x3cf2a43e 0xa6ed239e 0xd7529176 0x8ad63f3f
- 0x5efe8f4d 0xe9cad7df 0x44fefef4 0xc7198f50
- 0x85aabf5c 0x15c175c2 0x26f7a0cf 0xf06782f0
- 0x4dfadfa7 0xbc57a087 0x21406f0b 0x692a8f18
- 0xd17a358b 0x19d1b2a6 0x6c35022e 0x87d8c987
- 0xe7f2d06c 0x91c4daa6 0x4a132822 0x1e864671
- 0x5cbf0c4d 0x6a34f073 0x1c87a8e5 0xb38f1717
- 0x1cac430b 0xf733ee6e 0xdf73201f 0x71026328
- 0xee976531 0x661c9d28 0xdeefcd7f 0xdefb4607
- 0xfca9ef3a 0x3e1b9b38 0xd204c892 0x6b059f5f
- 0xd5b8665f 0x4eec24fd 0x09b21b40 0x364c708c
- 0xebe0d543 0xc3d64eed 0x8facb895 0x8f415f31
- 0x3dd25b0b 0x95f4072e 0x85e6f4c1 0x3345e2a5
- 0xa56e8dcf 0x3ed8df67 0xa8194a81 0xafe613c7
- 0x384b25b9 0xe7661836 0x5ad6476d 0xeb0ae982
- 0x19afdf2f 0x4efb8658 0xff07e358 0x96c469d2
- 0xf3030add 0xf5bf5b51 0xba03b24c 0xcb77143f
- 0x134fba20 0xa126558a 0x193cd220 0x48f43727
- 0x156f2b18 0x4e599917 0xc3ac4eac 0xcc460648
- 0x67974a2a 0xe2917a7a 0x02998a74 0x470c60d1
- 0xbacbc868 0xfef38d84 0x3e4597a9 0xa1723ab7
- 0x8ffed7b2 0xe489b151 0x34b982fa 0xf67bf8ce
- 0x043cbb33 0xe3927c98 0x3c8fb221 0xbff0644a
- 0x886d333c 0x1f4cd6b7 0xe9b744f0 0x443ef364
- 0x04847d65 0xf3c2ba04 0x60a8e656 0xab4dca06
- 0x620dbf22 0x5b0221e5 0x877973ab 0x128b5a6a
- 0x4696b5d7 0x8f034e85 0x18796215 0x8579ec7c
- 0xf8917eae 0xa98bffce 0xfc67e9de 0xa897445e
- 0x2f115777 0x990bfb90 0x1de53f71 0xfa2e5c1f
- 0x24a5b882 0x0f871a5b 0xe7fc33a0 0x6927a106
- 0xb210bc90 0x2ef851de 0x09629147 0x2553882d
- 0x77393353 0xeacf977e 0x470198f7 0xb7564a05
- 0x4d575fb4 0x1d980371 0x0feeebba 0x26ba3c12
- 0x17b21567 0xfb664d1d 0xcee1a603 0xa8881580
- 0x8a47e853 0x6511027f 0x734f6fd7 0x2977b345
- 0x7465e47c 0x0e3c4c8c 0x3185ac04 0x2450ea5d
- 0xa6e97dba 0xf52b2f4b 0x328ac24f 0x5a507ad2
- 0xac05d4f7 0xca332e1e 0x44b6cdd5 0xe22b049b
- 0x55b885d1 0x71144ba1 0xf57284d9 0x76cb0900
- 0x8266cfae 0x82bb0271 0xfe547080 0x53e4dac9
- 0x0546dcb9 0xa09a8de0 0xd55d15a9 0x7a3a96ad
- 0xd23c33ed 0x7a8fa769 0xa0542b10 0xdaf92f2c
- 0xd6433b0e 0xad7cf7b9 0x72c54814 0x38ff5c07
- 0xddee72d7 0x6c29582d 0xa1574da8 0x418272ea
- 0x0a9e21f3 0xa34bb5ea 0x1e78630b 0x9238d5d2
- 0x7cfa682f 0x6e8e841b 0xa4b3d17d 0x70b6d075
- 0x704db3f8 0x76aa7d19 0x1cd3e85b 0x2ae7fa63
- 0x5ff0dad0 0xdd92c129 0xce7d884a 0xa7ba03ab
- 0x3b366560 0xfeaf75c5 0xd08856c3 0x01ffbced
- 0x089aa8a3 0x2e4b36f1 0x03955648 0x882468ba
- 0x534abc87 0x28c08402 0xa7512f6a 0x1fab044e
- 0x6595e159 0x92fdef27 0xa0b6093a 0x5fdb5f3e
- 0xd0facb7d 0x512a8b83 0xd7f31adc 0x82166318
- 0xf9ad7f02 0x9120b349 0xab744947 0x2787d6bf
- 0x489e3546 0x02a7ce3b 0xd3812409 0x819a092d
- 0x94a48db8 0x49d8dff3 0xdd4e9b5f 0x330d32d0
- 0x203cad0d 0xace20075 0xfd019f42 0x1cc56871
- 0xe53e452b 0x51e7c9e6 0x1d6732c7 0x03694ca7
- 0x900ecdb4 0x3251d119 0x2c4a0669 0x3243bb5e
- 0xb434326f 0xd6eb26b8 0x8ceb7328 0xff30d7e3
- 0x861fa43d 0x15386557 0x3fa11d24 0x86590299
- 0xc3cbd319 0x8d1031a5 0x80db9f63 0x9d957321
- 0xdec927f4 0x1468a2a1 0xff1b8842 0x4c403eed
- 0x62140459 0x912ddd25 0x36252404 0x49052d26
- 0x22205558 0x53773ca0 0x3428d400 0x51002834
- 0x6b5baa18 0x838bcf14 0x30d09ce0 0xf1c456bd
- 0xb1fc90c1 0x525dbb0f 0x64a9105e 0xe0a5cc89
- 0x293f2441 0x335b1c7d 0x55842eff 0x6c7f60dc
- 0x903fd793 0x868589ef 0x50a596a6 0x337c6988
- 0xb7a670a9 0xa46b1a8d 0xdf8c013c 0x3dcdfd02
- 0x01075847 0x06c3a7e6 0xc8f22594 0xfcd94f04
- 0x8b6ddbbb 0x5a138f6a 0xf43d2cca 0xcf4df232
- 0x088cddf4 0x9adce26d 0xee803f2c 0xedf042d5
- 0x7d738c39 0x8f02cc34 0x3f964043 0xbfae17d7
- 0x5f2dd670 0x177a9f36 0xf0e1dc28 0x07082ed9
- 0x90534419 0xf03db66a 0xb8ccbbbf 0x739d2ae4
- 0x3509b32d 0xf0105125 0x2d603572 0xbd1a6b64
- 0x50959fe9 0x26100668 0x758e250c 0x9b372d1b
- 0x0f1e1bde 0xd53edd46 0x0187d6e6 0xd0158da6
- 0x05dd0922 0x3fc0a182 0xd7f70ebd 0xeeda22e1
- 0x1c7f99ad 0x9b39bee9 0xf101d67c 0x1ffea21d
- 0x5494b799 0x787a77ca 0xe8908c34 0xdd00d1db
- 0x25e21bcc 0x30bf0b70 0xd8cd0350 0x96f2d414
- 0xa9a4cb6d 0xa3f3c207 0x2db5c7bf 0x88e8837b
- 0xb157189a 0xb9fb869e 0x48c2a7b3 0xf5e0c692
- 0xf9103c12 0x6c590e9a 0x7e0aac34 0x97392b87
- 0x8e6c201b 0xc6d68ddb 0xb5fbaf0a 0x1f8e411f
- 0x6355e9d9 0x05fcca55 0x9b0250dc 0xec9c5d7d
- 0x668075bd 0xb93078f1 0xcefa1755 0x216c5e0c
- 0xa83ae6b5 0x748bff79 0xfee9e797 0xc6acb230
- 0x1243bc06 0xfee350e0 0x3ee5f8e0 0x0508fb60
- 0x87d9d24d 0x0b54ac94 0xfc37c8fc 0xe9958f2f
- 0x3a927f73 0x04933b6a 0xa195a6dd 0xda96dca3
- 0x9c1799c4 0xd055fc63 0x05deebbd 0x2b5400fb
- 0xf157f110 0x80b1e79a 0xd7f1e4b7 0x5a1fab0d
- 0xbaaa81c3 0xa42489e8 0x594a791a 0x29f18382
- 0xe86f0358 0x5aa5f4b0 0xa682993b 0xedbfc5b7
- 0xf1eac55d 0x9b1716bc 0x907d9d1e 0xb2205254
- 0x4fbba0f3 0xacea63a4 0xc518d83b 0x8449fef8
- 0x80b4f69b 0x95dc7429 0x16c22c9b 0x6e116239
- 0x4c4bfd11 0x56f159fa 0x60cbb0a5 0xa2f4721f
- 0xa829cf9b 0x5ddbb3af 0x2db824cf 0xe82f3fd1
- 0xe5dcb2db 0x185fe7af 0x0775003d 0x38669aba
- 0x7b540eea 0x94ce3d10 0xba77f357 0x63507853
- 0xb50ebb0c 0xb614739b 0xea3a3c47 0xf2b6176a
- 0xf805b28d 0xdd0819b7 0x9f4b2799 0x18bdadb8
- 0x7d58d588 0xc4f0994a 0xef834870 0xef2d6ce4
- 0x97a36a52 0xb6e581e6 0xddd9aa9b 0x6437d4e8
- 0x43f74dc5 0x8cbbd744 0xf394a2a0 0x4a1e7f75
- 0x395bd36f 0x27a8f9e9 0xed62f4a5 0x7c2f0484
- 0xf394f837 0x5f69d50e 0x86ef57af 0x7af052f0
- 0x85dee180 0x125f56fa 0x87291494 0x141931ac
- 0xabca9ae0 0xbc1e4e4d 0x541e2edf 0xa3551bb4
- 0xed2766fd 0xf6e778c2 0x3a82644f 0x67c47659
- 0xb81b826c 0xb11603ee 0xba6cc507 0x691fdb74
- 0x06507f6e 0x64ef2a0f 0xebd9b51d 0xee620487
- 0x82991d7c 0x1493fed5 0x08af819e 0x7066de45
- 0xdeee1600 0xde12b903 0xe572ced5 0x81b897be
- 0x458d0db8 0xc9970232 0x7402dd05 0x44e1c70c
- 0x1619441f 0x9ea0c392 0x1d13c3dc 0x34737cbb
- 0xe1d726e1 0xbe7d749d 0x304892a5 0x71c7bb33
- 0x608bb696 0xd334cfd7 0x862e360e 0x868757ad
- 0xb7d8aa70 0x81031f5e 0xdb64b80c 0x954ff4c1
- 0x5c66d432 0x08c77a67 0xd5e298af 0xb6074be1
- 0xd687a163 0xac2fd525 0x14e6ab5a 0x6ca4232d
- 0x8a921092 0x0a19e936 0xd4464ee4 0x0da28777
- 0x6b6d4131 0x975111bc 0x3f26afae 0x5a6faf38
- 0x867d7956 0x554aa8be 0xf9898211 0x3afcde65
- 0x493dac6c 0x61d901b2 0xbaf3e9fe 0x2a3758fa
- 0xc2ad3ee4 0x97d13dad 0xe84b02f9 0xaaf5ca63
- 0x41a94864 0x6d7b71be 0xd843e866 0x83c3193b
- 0x972d4bbf 0x55c3a234 0x0d03b540 0x53396a64
- 0x98b5c0f3 0x36708484 0x38363c7a 0x0076dbf8
- 0x5edbd01a 0xf6e835d6 0xccb95e4f 0x2bd2907e
- 0x210f9312 0xf4ec9221 0x343697d6 0x3913cd41
- 0xb02ced20 0xba991ee5 0x09c7893c 0x749da3c0
- 0x46e5ad3b 0x871b685d 0x02358659 0xca76706d
- 0xe61524a2 0xf46ac4a9 0x4f6c9e19 0x68a86d0c
- 0x9d16bc4f 0xa9157a1f 0x830993b8 0x3738896c
- 0x7c821db5 0x02de8542 0xb17e3767 0x455a0b40
- 0x19b707eb 0xed81e63d 0x568e1e36 0xbf5cee00
- 0xaa12957f 0x67f65ecd 0xb940789c 0x0ab3bab8
- 0xd7e3a789 0x777b64ba 0x4e00d3be 0x46887a34
- 0x08f0127f 0xf5027e8f 0x9cdb4671 0xb7a7eac4
- 0x9be5cfb5 0xb1f57dbd 0xbce97b11 0x41525f56
- 0x5e847d16 0xf71585b3 0x1ce5047b 0x1bc2fa00
- 0x860aa4ca 0xf97ee77d 0xe7843ee6 0xf07bd865
- 0xfa059452 0x58a59ce9 0x24f03b1b 0xd18a52c2
- 0x180426ab 0x2ced0003 0x399234cd 0xe43f91e9
- 0xa0516a92 0x8088d598 0xc3a41365 0xd1f044ef
- 0xfb3808f9 0x1770e594 0xf96c4185 0xc6b67b9f
- 0x5c01c703 0x65c6ef8d 0xd49310f3 0x0f962bd1
- 0xfb3c96f1 0x4d501516 0xa09beeb5 0xce9df639
- 0xf792c71f 0x392b420d 0xc03c9099 0xcab5dc42
- 0xbdfea308 0x84c80c32 0xcd66ec3f 0x68932191
- 0x62b69b08 0xcacb4a8b 0x0415feff 0x84673edf
- 0xe61b5ff3 0x6107a18e 0x6a7a206b 0xed64aa34
- 0x1bbaef36 0x22a3f0fa 0xb0945c72 0xd1a7f7f8
- 0x65fd1b29 0xa34d99a9 0xb6f2ea53 0x055ab055
- 0x433c3eb2 0xe591d68b 0xcabb8a71 0xfb055c2e
- 0x37e1efec 0x558fd45e 0xa5358766 0xe0c450f3
- 0x78ed3061 0x8713e084 0x4b0d2ec4 0x24feb10e
- 0x6689fc4e 0x0c83f1c9 0x7490df57 0x00d618bc
- 0x2c510caa 0xc5e2838a 0xcfae6669 0xdc2fa4b0
- 0xa4569e3e 0xcee095c4 0xcb5f42ee 0xdc11393f
- 0x69f1c5aa 0xa495fae6 0x64c53ea4 0x4477aeb8
- 0x2ff43cef 0x660aa186 0x5dec9e67 0xa59f6aab
- 0x51504061 0x28279b5a 0x4e245278 0xdbf53c73
- 0x01a77ff9 0x7d771730 0xa8d19fc6 0xce3697dd
- 0xecc405d8 0x22f1872a 0x683afa3f 0x725f7e03
- 0x14c7acb2 0x845efb20 0xf3e03095 0x8c9a7d04
- 0xa9f115d3 0xb93fa8ef 0xd2e78a32 0x91e3cc61
- 0x805d48de 0xc9fcc672 0x225d36f0 0xb32e7627
- 0x11b7a585 0xa7321798 0x9b40640f 0x0c3a6b7f
- 0x3337c762 0xbbe54bb3 0xc8316a84 0x0d487a67
- 0xa6d6b86b 0xd1fb2b92 0x15805dfe 0x5cd49b21
- 0x9855f2c2 0x74e2a195 0xbdc0729f 0x29f680a9
- 0x092f47ad 0x0e7091d1 0x6e7d2020 0x0a7b5d47
- 0xc9c4065b 0xc4cacd97 0xcd7b4071 0x7986cc7a
- 0xb1c29ef5 0x47ced57d 0xc08a8b40 0x12102685
- 0x685caae1 0x1ebf3635 0xdfe6af15 0x8a0496f4
- 0xb9c07f19 0x1f62a68f 0x0133de0a 0x993017d9
- 0xd0553b5c 0x0c8f1311 0x7d979028 0x6001db26
- 0x1caf7ffd 0x76ced0cf 0xc33d3f23 0x9fc27423
- 0x235fc137 0xf85a079b 0x78174474 0x1d15b725
- 0x20162abf 0x62e0712d 0xa03f9cf0 0x0f4ff140
- 0xaa389d0d 0xd58e1171 0x8f5d21f4 0x3ad5b3c4
- 0x03003b51 0x49b29d4f 0xa3d82796 0x9c7f3391
- 0xe34de3a8 0xab75e6f4 0x3f06b52d 0xb8092f83
- 0x01f14341 0x929a3b8a 0xa630aa03 0x4b7e055e
- 0x90b06e58 0xeaf2ad79 0xe8c5b756 0xf46f44e3
- 0x6693ff09 0x499d2790 0xd0d81c69 0x72d7a2bd
- 0x794d242b 0x9be19084 0xddd51a72 0xf4f60698
- 0xd1747d6a 0x24dc87dd 0x78ba7af6 0x548b43d0
- 0xa2b03ee8 0x100ef53b 0xe836488a 0xf4b9a443
- 0x41d61bdc 0xee4bedb1 0x8f0ec0b0 0xc0125983
- 0xaa919a7f 0x6677db37 0x78e7d366 0xc7bef834
- 0x967a54e7 0x5f78951a 0xc0fddf1f 0xbd5cf29a
- 0x3fa13be8 0xca67a695 0xc13e8c23 0xaff54342
- 0x94f4bc22 0x85512c06 0x1439cd71 0x7d13b7b5
- 0x76f8bd59 0xffe02871 0xbd88ccb1 0x2597d721
- 0x80a52e2e 0x1f696120 0x689e73aa 0x7d085fa0
- 0x0e183650 0xe041d3fb 0x5a340dd0 0x26a6c10c
- 0xe6fef6d0 0xdb18b3b8 0x2fc6df63 0xfa695c57
- 0xfb3e6a3a 0x64fb412f 0xc1cf1e32 0x6edd945f
- 0xcee44d66 0xdfb2ec8c 0x5eb84515 0x177f031b
- 0x56a9db8a 0x0e247577 0x99004862 0xa5805854
- 0x04b1afc9 0x9c649998 0x908a1424 0xb595099b
- 0xb91fb0ce 0x8c4bdd8a 0x78de806e 0x65ff3cba
- 0xb66aeda0 0xe22d3592 0x7c0cdebf 0xc15c0853
- 0x80f31d27 0x84dfc7ed 0xc96a5992 0x939b3d6c
- 0xf0ffac53 0xe4be269e 0x4d56d528 0xb0477318
- 0x40a4b528 0xd938f1bb 0x2b25a6c2 0xc93b3c9f
- 0x179c9571 0x999c2e91 0xe7280616 0xee6e0481
- 0xc30eae2a 0x7d6f0458 0x0b7a52ff 0xd44e0a23
- 0x81d661ee 0x9d0f857b 0xe7fa9d18 0xd499cb85
- 0x4e27e30a 0xd51d1f9a 0x14195d32 0xccca7d6e
- 0xc1703a6e 0x15664170 0x7f51c821 0xf1363619
- 0x37dc27f5 0x6aea6223 0xd574e44c 0x4b683223
- 0x4135ad1a 0x7694390a 0x0bf4bddf 0x9522f11b
- 0xc20797be 0x45fb151e 0x96f2a952 0xedfd5f2c
- 0xdfbcac7f 0x58f5dba6 0x68204d0d 0x52eeb34a
- 0x8313fd8b 0xda2f1243 0x195a1479 0x19bb2970
- 0x1c2131e5 0x6841c28c 0x1ec33cfd 0xd3e489de
- 0xd9b70b18 0x81503d32 0x9642a53e 0x02470015
- 0xb8d1087f 0x4b629e77 0xd7ec9ee0 0x795ffd91
- 0xcfa71aeb 0x4bae649a 0x7f768123 0x69f501d5
- 0x56c19a0c 0x4bfaac57 0x90ea664a 0x4d428e1a
- 0xaee71c90 0x198fc316 0x549f5572 0x07a22e58
- 0xe8f444e3 0xedc7fc23 0xe96c1595 0xc4bdad06
- 0x751a3df5 0x3bc4fba4 0x58cd19b3 0x3665000a
- 0xe4371d96 0x6c50d4e6 0x5d1d6a57 0xf130eabf
- 0x48fd82ad 0x42a8bee8 0x71f89c32 0x95fba6dc
- 0x9150b601 0x72c361b0 0x71a3c317 0x149614f9
- 0x224e67fa 0xf6a3fea9 0x5461cefa 0x367bc566
- 0x2226ee83 0xaa13e83f 0x8d7dc705 0x417c7afd
- 0x8a0f2e17 0xbb4003df 0xd1c27124 0xaaaede8d
- 0xd4ed5bcd 0xd0102aa8 0x3b519bfa 0xb82d6932
- 0x50b8f966 0xec685a1d 0xffb18b64 0x538955b2
- 0xac4b6cf1 0x0a86d32f 0x34e4cc05 0x02adcf17
- 0x7c80379f 0xcfb5bcb5 0x842190e7 0x8348cd1f
- 0xabf77742 0x3332866f 0xa56fb2e6 0x6c1fec47
- 0xf2fbb22c 0x7230d805 0xed17d8f5 0x3426e157
- 0x1d045cb2 0x6c1e349f 0x3a6116ca 0x4baf0bdb
- 0xab68daad 0xc4867466 0x7bb15fd9 0x707a6a1a
- 0x83157678 0x277cffd1 0x8d48e5d2 0xf829bd6d
- 0x1fd2750e 0xb6bb8854 0x66d0a20a 0x38f47b92
- 0xa3568b90 0x0d091e16 0x65a8245b 0x238e4299
- 0xd0bc6bbe 0x8ef67730 0xf976b632 0x326d9d24
- 0x96833335 0x1d475e95 0x1f8f41b6 0x65c9dabe
- 0x2133b931 0x43be592d 0xb887160c 0xf21fbfce
- 0xd83ca306 0xa0fb3fe7 0x7da09bf9 0x3f464aa6
- 0x37a7e40a 0xbb0c85bc 0xb172ff01 0xee62de6f
- 0x59d2d646 0x4262e938 0xcd96f5e3 0x0c1862cc
- 0x438388c7 0x9f45d4b2 0xc65ab0b0 0xd24a381c
- 0x1d6c6767 0xedaa1ae2 0xa93eaec0 0x662d776b
- 0x192a88c9 0x6c9d860d 0x61106181 0x30027db0
- 0xa5ae7b76 0x73fc43da 0xd77472b0 0xf4ceba3d
- 0x7cd642c6 0x903dd266 0xe33f58e9 0xbd088621
- 0x8e4c2c12 0xd8c4288e 0x24fdbb22 0xf72ee1f9
- 0xf291bd7e 0x94e68382 0xbbdd9240 0xb59602de
- 0x1b59afd0 0xe5417cf5 0x20bbb538 0xe28fdee3
- 0x0bb16920 0x77d6712a 0x1a0ae5f6 0x0156c43e
- 0x976b53c4 0xef856d7b 0x5a974cfe 0xec53404b
- 0xc627c557 0x3318542a 0x8fd883e6 0x508562b3
- 0xe0ab7501 0x9ae57262 0x95611b5e 0x50c699fd
- 0x984bb8ab 0x5983ed68 0x9947a7c5 0xc0d2374a
- 0xe0845ab6 0x9ffec0fe 0x41873bf5 0xc85c1a4c
- 0x7ef2b12d 0x9e1a3857 0x444da53d 0xb8947919
- 0x84c8588c 0x268f34e3 0x1974cf3d 0xfa67e03f
- 0xc4478570 0xc1896f5c 0xf86de14a 0x9d27ddb7
- 0x5da1c695 0x73c74ab7 0x9123a47b 0x1c9d9563
- 0x7b96bb9f 0x98d20464 0x1f46fd8d 0x4bc35857
- 0xc221a75f 0x04b24c86 0xbe1c7271 0x21a7b19a
- 0x9e050b54 0x8d93d0fb 0x98d7b55b 0xe5fe9502
- 0x9471bff8 0xb3825934 0x5f22d5b2 0x47f4ae9c
- 0x62d7623f 0xfdeef9b6 0x38c64ff3 0x9268fd7b
- 0xa7cfd22e 0x80eeed4c 0xf80a4a3e 0xc9a7e4f4
- 0x6f334b52 0x48e932a5 0xef8720eb 0xb9e86512
- 0xc4183682 0x08142405 0x0a32902d 0x34503fb5
- 0x4c7f132b 0x8db9be38 0x82c20236 0x80a79fa5
- 0x9a31e682 0xca61dd2c 0x2e354b63 0x8d5a4750
- 0x7a838960 0x24dffeb5 0xc7d19837 0xebfbc508
- 0x82e8dbdb 0xe732eaf4 0x109470c1 0xb012af6e
- 0xe2ce17be 0x79db33be 0x281184f3 0xc813df9d
- 0x9e6a771f 0x4a81882c 0xda5baf2c 0xfecbbb6b
- 0x4621a151 0xf4cece92 0xfc230416 0x8d4e758e
- 0xf69c296c 0x9fa2490a 0xeaa56785 0x3075ed95
- 0x4c2ffe06 0x817caf32 0x5a72f33a 0xc6d99da3
- 0x2bbc3dde 0xade463f7 0xb74af1a3 0x738d809d
- 0xd244aeaa 0x7302a2db 0xcb6e9b1d 0xe297c027
- 0x15dbaff6 0xce99c273 0x2810eb0e 0xafbe1f09
- 0xd316d8ba 0x27b8af19 0xb66bdf45 0x3e3b5fbe
- 0x318a4f05 0x2ea7807b 0xed6d40a0 0x58ba8267
- 0x1d1c9d15 0x29af51cd 0x04a46683 0x4b759694
- 0x20ce21e6 0x19ef8036 0x141a8064 0xca36f583
- 0x6d47da5f 0x3a8f6b9a 0x70a99a79 0x03677150
- 0x0feb8c70 0xf3509842 0xf33b5dde 0xbef320a3
- 0x932f9512 0x87497bf0 0xf521a0c8 0xa813483b
- 0xcd6fae43 0xbb7e4dce 0xc7d039b3 0x2d1e6f8b
- 0x1b19cb9e 0x8341c193 0xeffde49d 0x4c40621b
- 0x19d60210 0x8846c540 0xea735ec0 0x0c995dbd
- 0x9aefe2f3 0xbd46f954 0x9b315f98 0x2819307e
- 0xebe2c1f5 0x05919533 0xa52921ee 0xa0bd6746
- 0xd754f5d1 0x39eb2ce6 0x8442d51e 0xb1f75159
- 0x1b617cd1 0x046fc90a 0x6452daca 0xe8d3e3e1
- 0x77406387 0xe3ffbfca 0x89387e91 0x7e348a53
- 0xa5bd3b60 0xc113e95f 0x2ad5a7c4 0x45c1f445
- 0x2a683930 0x3428246c 0x4b89cf6b 0x05e66b1a
- 0x571737eb 0x6e55a8e1 0xbc96ce28 0x24d501f3
- 0x242c8191 0xde8c9472 0xbff946e4 0x551b5759
- 0x411e3420 0x0f0b9299 0x44aaaf70 0xacf2f3df
- 0xe9c44a27 0x781ffdce 0xa39651a5 0xdb7b44a5
- 0xed0ec4d9 0xec17fca2 0xd3ccb15f 0x2b9bd010
- 0x0446a9ef 0x18df586c 0xe227ae08 0xbbaff527
- 0x7958fb15 0x03bfc823 0xc09b7b6b 0xce07b0b3
- 0x0161a359 0x8e21f733 0x8f8168bf 0xc1e2207e
- 0xf9f65e93 0x831b4ba8 0x4b3677f9 0xf8342d03
- 0x03c10268 0xd07233c1 0x0df67d97 0x72434732
- 0x059c7679 0x96526a88 0xb54f9440 0x19e7327f
- 0x6f7f52c1 0xb4b8d069 0xcc4681eb 0x26ea581b
- 0xc26fe16e 0x4073cc56 0x6d252a42 0x689fd0fd
- 0x5d93f1b3 0x070ad283 0xa07cb95b 0x6effe0d1
- 0xe303ed01 0xb8e9b3f4 0x0721647a 0x31f877c6
- 0x134518e5 0x08694d5a 0xb0e6ef3b 0xc7fdc67e
- 0x6111276e 0x45185e0a 0xe13cb5c7 0x7c6ec9e9
- 0xfdee9721 0xc1fb8bcc 0xe25a2bc1 0x075f717e
- 0xd37b7698 0xa9cbfeae 0x6b7d0a28 0x1f1c8bdf
- 0x35d0e6b2 0x8b988b79 0x54f02ea3 0x3426ae01
- 0x5e402b08 0x840d3b8e 0x221527ff 0x906a86f8
- 0x411ce6dc 0xe4b3056e 0x26c9ed04 0xf3d8bc97
- 0x3b02cf67 0x11309c45 0x06ea08bd 0x1c698922
- 0x04e1e492 0x06e0c39d 0xed2937ab 0x83f1911b
- 0x25a94599 0x75d365f0 0x98f191e9 0x845f5e0f
- 0x49547aa4 0x42a0ae2e 0xb7e77fb7 0xe132bfb9
- 0x1cc087a2 0xb0435a85 0x4818ee36 0x4cd90b16
- 0xf56d5e22 0xdc49137b 0xb5f16e70 0x8f8ac784
- 0x84b020c7 0x83c26ace 0x090b3489 0xde14f529
- 0x6ee716ba 0x9deabba1 0x2c230ded 0xd6a68037
- 0xe626043f 0x33431885 0xd26423e7 0xcf259f47
- 0x335dfa6d 0xf052f836 0xcadf2fa5 0x6f2125d9
- 0xafbb23bf 0x19ec69ba 0x84d10bad 0x8cd3ebd5
- 0x36f0fbb1 0xbc1cbfbe 0x96c56812 0x0b05c939
- 0xbd79989d 0xffe74b98 0x6f99405a 0x9f10b14c
- 0x9d8efef4 0x299d21b5 0x9dd2df5a 0xc7ea511b
- 0xbdde106f 0xe5dc7d17 0xee136bc7 0xc4521b6b
- 0x823d31d0 0xcc3c32eb 0xb35ffb33 0x84dd8acd
- 0xe8ddf3d6 0x4611888c 0xfe469f52 0xf8e18215
- 0x768747f0 0x86379e46 0xd3cf9eb7 0x86f1e47d
- 0x30e68652 0x740203fe 0x1031b14e 0x96ce6827
- 0x45f57455 0xe41b7656 0xaa8496d3 0xb99701d0
- 0x485f88ed 0x1d064ef7 0xc7e3348e 0x110d938f
- 0x0c3c9604 0x786b0b35 0x2b2aa6ad 0xdcc45e0b
- 0xe9b29146 0xdbb00ed2 0x0527d574 0xc8029ff1
- 0x5699dfd0 0xd627ff70 0x285fb3d8 0xcf2e6b75
- 0xefad87da 0x4fa21893 0xa391388c 0x5760b28e
- 0x41a95b55 0x82001638 0x6f0e2d45 0xd30f70aa
- 0x5eca612f 0x946317f4 0x24c44ef7 0x470d26f2
- 0xf7e65ef4 0x3a831857 0x53c5699e 0x1af6ff3f
- 0x675b46c3 0x1bd5cfbb 0x03ab61be 0xa67a2b7b
- 0xbae16286 0xe1522d53 0x076d8ec2 0x3a603daa
- 0x0dbacfd9 0xd32acae8 0xe8a23399 0xdf3330bf
- 0xe990c05d 0xfe56bcc3 0x165f868a 0xdf42a220
- 0x6587e194 0x0a31eb94 0xa72a98fb 0x5512801d
- 0xc5fd9c69 0xf7210367 0xcc80f30c 0xc08755bc
- 0x3afe8202 0xc47d603e 0xd17d2990 0xa4addd73
- 0xce89fcc5 0x55726cbd 0xeeb77a64 0x628b3d1c
- 0x2297e332 0x6ecab8e4 0x9739c0d1 0xd53d619c
- 0xbf1a3371 0xe29ea297 0x140436d5 0xfa4802f8
- 0x1b277664 0x4f101407 0xde441685 0x1d36bbf4
- 0x057d9f25 0x7949dbc2 0x57686ffc 0x12984cb7
- 0x0721d76b 0x81ac7aac 0xeb40577c 0x43aaa8d4
- 0xb4e06e63 0x7054a526 0x18bced57 0xa37d26a0
- 0xac039a34 0x156e6d9f 0x07ae4487 0x0e59f4db
- 0x28aeb416 0xc1c4dafd 0xe0357fef 0x683adca7
- 0x93f2d62b 0x8f1f6ec6 0xd42fcbd8 0xfc4e3fad
- 0x082e4bbe 0x578bdbee 0x42dcda04 0x7684e947
- 0x20853da1 0x207dd044 0x56e372bb 0x5ef4c033
- 0x83353865 0xb3b42465 0xb80c9c79 0xffedbed0
- 0x09e45d5b 0x794fe5c7 0x498d4fbd 0xb1cd7a48
- 0xfc89b057 0xc1d19df8 0x9654d056 0xc94cd085
- 0xd7cb03b5 0x13a52c5b 0x52471fd3 0x990aaebe
- 0xe8bed6a7 0xa6960d01 0x68011da1 0x021bf151
- 0xaaa196f2 0x9e3b6188 0xbb28f2c5 0x559d3dd2
- 0xc38861b2 0xfd7242b1 0x716c29e2 0x270236a9
- 0xaaf33479 0x610a7d76 0xc0d564fc 0xf0bb1bd8
- 0x31fb232b 0xf19ebb3f 0xd62acd99 0x5e45578e
- 0x467c587f 0x0ac00140 0x9c7c1705 0x61a8a1ea
- 0x4c5e4e5d 0x0e0d846c 0xd199939c 0xb4c615ae
- 0x4cfe60cd 0x6b4e5cf4 0xe97ad9ec 0xf325a456
- 0x6ca45a64 0xb88b4506 0x9f751f49 0x1d66e330
- 0x59b40444 0x00f530b0 0x9242124d 0xac6de2f9
- 0x7b7e7a67 0x64962ed3 0xfd0825bc 0xbdbcc113
- 0x38d8d589 0x3cedb53e 0x17d95495 0x020b8ac2
- 0xe9aa9bdf 0x0a5a2820 0x64670635 0x91a2a89e
- 0x91bec6be 0xe9b4f902 0x1ef88ee7 0xec6e1208
- 0x149e39ca 0xb140ce3b 0x3210a2a7 0x8e489c45
- 0x59d3ebad 0x30275658 0xc20708d2 0xffdc3e00
- 0x96c700b8 0x3d03aea6 0xf0ce7ad3 0x232a5585
- 0xb0dc6620 0x1c1357b3 0xfb4c6d29 0xe5c5b7b7
- 0xc4bfe2aa 0x37f7ce13 0x433eb884 0x3dde220f
- 0xc1c34602 0xea700f6f 0x37b79490 0xad5761a3
- 0xfc5917b1 0x22f7e1be 0xa90566d8 0x89e9db15
- 0xf91bfa1f 0xdad2260c 0x93eba86f 0x2d94c130
- 0x777290f1 0x2e656559 0x9be4a490 0x377a6ea0
- 0x1b4523e4 0xdca0c8a5 0xb00eed31 0x6baeb803
- 0x9601ee69 0x13d53e86 0xba8d6d8f 0xed6203ce
- 0xc844f9c7 0x91e8a556 0x39974676 0x3b81329b
- 0xdd7f10e1 0xbccb6558 0xb20de25c 0x448c44ee
- 0x8932398a 0x76717b57 0xb20a667a 0x14e2df4a
- 0xa57107f6 0x701b6c36 0x4b83a1ac 0xb39a1c9e
- 0x2cc7e9fe 0xf5ae4a62 0x620687b6 0x2d6aef9d
- 0x6672612c 0x168cdc7e 0x8b09abea 0x522692da
- 0x6461676d 0x34ab3a9c 0x0d61a2ba 0x0590fef1
- 0xe9b4b475 0x2dfb6081 0xbcdafb25 0xdae642aa
- 0x9a9230fd 0xfd67f346 0xdb9d66e1 0x5b307b61
- 0x9d4f1869 0x21133d6f 0x5157502f 0xcc8ccbc5
- 0xb6631100 0xa33f48db 0xc0172774 0x5cb276ac
- 0xe6e5c560 0x07e126dd 0x42bcf23a 0x8064fd70
- 0x567ece78 0xbbc2fe32 0x9d5ee1bb 0x175b24be
- 0xf0feac7a 0x57322618 0xfe9e893f 0xa9b2d67b
- 0x36d03f5a 0xdf178831 0x4da346c5 0x843b1b10
- 0x0d688dca 0x41a475c6 0x4b7adf33 0x145a00dc
- 0xcd226a4d 0x4c40cf2c 0xd4972929 0xbad5ea65
- 0xa96987fa 0xbe247d1c 0x49f2ce89 0xe09bbe72
- 0xee48486e 0x34b41435 0xb41dbb86 0xe58866c9
- 0xe848e228 0x18880947 0xd03cd275 0xca285915
- 0x53dd0097 0xff9069f9 0xaff6a8cd 0xbfe16ac5
- 0x5e88e076 0xac629a26 0x5a99bee9 0xea892a43
- 0x8d1d5ce8 0x806a38e3 0xc4d99fcd 0x331a4a01
- 0x0e586310 0xdd2dfabb 0xe7e6ad37 0x31d67fb1
- 0xbb985560 0xc969ce24 0x3a424634 0x20a2080e
- 0xeb1b587c 0x5cf7da4b 0xdaec0133 0xc99abb17
- 0x63ab9c8f 0xef7e4042 0xca513c8a 0x4e15f5d9
- 0x7cf8fc96 0x464cea5a 0x2363577d 0xd21bb7db
- 0x1d977a0f 0xb02f4878 0x4fd1a03b 0x435b9149
- 0xdfba062e 0xa2f7fc23 0x5ebde93c 0x28e9ed7a
- 0x4023b147 0x9cac0cf9 0x7c5d5ca1 0xb7453148
- 0xa52197d9 0xb85dd94b 0x72ee7e51 0xb81f4f5c
- 0x97a4b485 0x13d8858a 0xa0aabd28 0x9d381125
- 0x4960d2a7 0xa62787b2 0x865231c2 0xd637cc90
- 0x6d58f3b7 0xe2759f6e 0xa28af8da 0x5a005f20
- 0xc11c495b 0x85ecc413 0x657e7b91 0x10b39f7e
- 0x3fcc394a 0x94b3fc3a 0xb359d60e 0x2e6c1555
- 0x67d6d21d 0xb0457bc4 0x004f329a 0x2e131d8b
- 0xfbfbff2a 0x2c1bcbef 0x181f26b6 0x32ebda60
- 0xa0839e5a 0x241097df 0xb3f070a7 0xefbbd9f0
- 0x7c3669c7 0x265f2dbc 0x0bd00e42 0x80d6c4c2
- 0x44874336 0x0b6e7e0a 0xec590889 0xef865c09
- 0x1a02ac8a 0xfbf78784 0xaaf89d75 0xa86c9caa
- 0xc626528d 0xfbcec50f 0x2955f18e 0xb5e9a833
- 0xae60f6bb 0xb3f4c51e 0x21bd6a6e 0x092a6861
- 0x162d73dd 0xacfa4f0e 0x4efed2bd 0x88980089
- 0xa2cee6d9 0xdf0953b8 0x6bf5208d 0x4364ed53
- 0x1a5f19ad 0x2ec7711e 0x7d18832b 0x0f1b28a6
- 0x0e127845 0x278a6a61 0x9e236436 0xf4646e82
- 0x07fff0f3 0x34ae92f9 0xec3e71af 0xf7ec7c67
- 0xdb9ddd62 0xe664e712 0xbb48a158 0x30a14ae6
- 0x0d93b021 0x83082cc8 0x68952311 0x001b0003
- 0xf0688e25 0x6c3b5161 0xfff18a53 0xbd1fb0c9
- 0xe3cc9013 0x1d1e553e 0xa85cdfb0 0x358afc14
- 0x61749007 0x6fad59bd 0xe85f4500 0x26a5ffa1
- 0xedd69e21 0x4c1db8ce 0xaf3be18f 0xcd75c259
- 0xd05f62ee 0x2f0ff1b7 0x717d9bd3 0x62e13392
- 0x159ce5ce 0xcd9e9bff 0x8964600e 0x57d85abb
- 0x3f5ead09 0x2d5d4a55 0x87da8369 0xc7944933
- 0xcde9a717 0x55fa318d 0x112e1607 0x2ca832cb
- 0xb1181bd5 0x7541a7d4 0xac1a1e20 0x6ad024c8
- 0x119378ec 0x60b6cbfb 0x068e2f24 0x83acecb1
- 0x87fd0df3 0x94c9552f 0x08c3d8dc 0x56f1b514
- 0x717d50e9 0x9680fc39 0xa1bdb28a 0x3dfa1c7c
- 0x8fc84774 0xb72e06d7 0x42b7ad1e 0x93646393
- 0xd3632e4a 0x368d78f2 0x36a5ac5b 0x6576a4d8
- 0x8bc6856c 0xd447936a 0xbec6fb22 0xab285e59
- 0x3db2c781 0x72eda32a 0x9d654f18 0xdbd78e99
- 0xbba310ad 0x938ecfc6 0x72d5079a 0x49e2fad4
- 0x4b44dc75 0x81e82165 0xbe269c9c 0x2558ae80
- 0xa3bb693e 0x107d10fd 0x8e4fd977 0x22926b4f
- 0x68c9a7f8 0x6b7439e0 0x5c71c127 0xff5d88b3
- 0x9d8cce8e 0x02982a71 0xf8fe1ceb 0x3ed3996b
- 0x1e4f9957 0x63aca642 0xcc9db51b 0xbcb5af80
- 0x7b2bf393 0x2915079f 0x87f531c5 0xfb06b13a
- 0x550b261c 0xf01fa342 0xcdf4dd86 0x76718f50
- 0x717c6bde 0xf460ef23 0x7f912022 0x54fe5b9b
- 0xc7a5261b 0x073ea6e7 0x71504d55 0x91dd9b8e
- 0x6d259452 0x2dc96e43 0x289959ca 0x128176a5
- 0x8d004371 0x835c494e 0x0efa1879 0xddc02e95
- 0xf0f4618e 0xc67656e2 0xd2bde6b1 0xccaa5e84
- 0xc6592f19 0x91d01db8 0x2b697d22 0x8adfa55f
- 0x5a49e4e7 0x897d5c43 0xd326d94f 0xf5ff0c5b
- 0x57976ca6 0xeff0db4e 0x6d49d466 0x7c054970
- 0xd3eb0f9f 0x0cbdce79 0x1beaf714 0xfe2df967
- 0x6a50895e 0x013167bf 0x6139e59c 0x0662ecee
- 0x9a8d6b53 0xfffb8649 0xce0e685f 0xea5b2a7a
- 0x8819a629 0x5f96afb4 0x8891acfe 0x545f1097
- 0x9f314e1b 0x248a5272 0xa40b8424 0xe42af07a
- 0xa180f331 0x904f3c05 0x98455bc5 0x46198ed7
- 0x03e208e5 0xcf670099 0x7a85b08c 0xba921ae2
- 0x1e6947d0 0xddffa6ec 0xea6330d3 0xcda6957e
- 0x19525cd3 0x311fb407 0x796c1ff4 0x3a2760fb
- 0xde4bdd71 0xdb289b69 0x9811773c 0xa72cd839
- 0x03da90de 0xd42912e8 0x8da1fb0a 0x985d4132
- 0x5890ae40 0x1f7724d0 0xa336824f 0xca19df32
- 0xf8ac73d1 0x61c370a9 0xe152b073 0xdafc6461
- 0x23672042 0x9e6982b6 0x1256c6b4 0xe6bf2c9c
- 0x9dae123e 0x30896b8f 0x99acf3a3 0xaa05d384
- 0xea3b7bb7 0xe711d473 0xa9053351 0x71a85cb4
- 0x3a0f5d25 0x2db3cb48 0x86314a6e 0xf7a2265b
- 0xf7dc1cc3 0x548f56cf 0x4028a1ee 0x7d2e25d5
- 0x68c87e37 0xbced6b8c 0x536cc252 0x68bab5ca
- 0x1158c6c5 0xae0e9509 0x66fa6885 0x22bf2b9a
- 0xa7a60a97 0x18f4f609 0x348623eb 0x773e705f
- 0xb3d6622f 0x8f348186 0x81cb9856 0x64bf21ba
- 0x47e1f96d 0xc95a5843 0xeff6cfce 0x08cb092c
- 0xf214e48d 0xce272fec 0x57bf90df 0x3c425ea8
- 0x856e1f5e 0x5c21d1b6 0x105488a3 0x553971eb
- 0xde614ee5 0xdfa3ac81 0xc5eca5b1 0x69d02d23
- 0x2a0fefb7 0xf9a01854 0xdd99f277 0x75014d7d
- 0x3830e3dd 0x7dd8f1e7 0xdac5ac92 0xbf57c03a
- 0xa5e6a6c7 0xb7c1b7a9 0xc8c8405e 0xfd1977da
- 0x1e6a7ca4 0x299e1025 0x651a0e55 0x53d624a7
- 0xccc9e861 0x901bce45 0x1de5a1ab 0x6140dcef
- 0x3e09eafb 0x20c63cd0 0xff642faa 0xbc91a0a7
- 0xe373e111 0x857236e7 0xe3e61037 0x0b6cc497
- 0xca1da7e6 0x60e53803 0xb68663db 0x42e9956a
- 0xbf4a1650 0xb43f25ec 0xc1232a3a 0x283c2ff3
- 0xcd233183 0x17ccdfc0 0x03ac3e6d 0xa68ced48
- 0xe38217d5 0x03c6472d 0x6a623afc 0xfce0d117
- 0x448ee829 0x0909efd4 0x843a3b4a 0x9ad07683
- 0x2250af2a 0x01ecc053 0x29684919 0x4ee0c62e
- 0xa326a904 0x3ec83943 0xc42b0663 0x966379b2
- 0xc672ece4 0x39391ad3 0x689a10f9 0xd3e9cbd6
- 0x4bfa8446 0xd1ef6375 0xfe01b6a9 0xbda7d01a
- 0x1e6879bf 0x05bdf46e 0x14ccab04 0xb02ae668
- 0x58b51752 0x5eb8e83c 0x753d99de 0x87e4235b
- 0x80b2afe7 0x127439fe 0x127a98a4 0xe5934c92
- 0x86044bc0 0xa9664abb 0x91365b53 0x35b14bda
- 0x67755842 0x7239651a 0x49e0b2e6 0xbb1d25fe
- 0x51ca7213 0xaff2fd82 0xc1223aba 0x02941bcf
- 0xb6ec2cfe 0xaa817dc0 0xe0475250 0x78098112
- 0x750ae102 0x0b3135fa 0x23b648d4 0xbc9d78bd
- 0xc5d7e046 0xe90ef47c 0x7f21eb75 0xdb304b0b
- 0xa2c12ee2 0xb45e62ed 0x9f50feb6 0xe036ff55
- 0x422f410b 0x2385de45 0xb37df6a5 0x4c2abf10
- 0x6a2c7370 0xf35197ac 0x381face9 0x694761c6
- 0xb2275097 0x208824c7 0x945300a0 0x4ad3f83d
- 0x38a7aa12 0x00daaf41 0xcd4b2c19 0x25b2e8f7
- 0x60d3e39b 0xb3dd8220 0x152f86ab 0xd1ec4233
- 0x1c3df78a 0x5aeac74e 0xdeea2fe3 0xcfcf9b2e
- 0x6efc8b2a 0x12a8c5c3 0xb56384e4 0x1b1fe549
- 0xc55acb4d 0x78e7306a 0x733b0f70 0xf4afe6be
- 0x6d904b03 0x7ddd7862 0x4da02602 0xfce1e904
- 0x78773a4b 0x9083e908 0xda8a7593 0xafd8776e
- 0x9e5ae37a 0xd6e7c557 0xad27adaa 0xd0f1a995
- 0x1c84e046 0x3319b21a 0xd24c0d03 0x1789df77
- 0x0f02b9ff 0xdb911f76 0xb2df7654 0x2e75a7bd
- 0x8acc6fd3 0x3c16ec0b 0xe0d7ac22 0x3ddd1ce1
- 0xfa9ec67a 0x48f2c409 0xf8099606 0xd73a459d
- 0x9b2b3fa5 0x8e3c3e9c 0x8b99286a 0x006c0e07
- 0xc299ded3 0x8a2bd400 0x74508dd4 0x609b4afc
- 0x1a532838 0xb352a629 0xd390d8af 0x440a5798
- 0xd31f6ad5 0x161aa48e 0x24a4359f 0xf39f49f7
- 0xff160d2a 0x27a24637 0x84c46d40 0x988d026a
- 0x5697a68f 0xeae970a0 0x42689e3d 0xc84ee62f
- 0x764aabd5 0xb6d74ba5 0x8efc05a6 0xf2d0eccb
- 0x2b4fa41c 0xad24799f 0xf73b8353 0x76bcd448
- 0x08172d5e 0x5c6be301 0x926ffdd6 0xfa31009f
- 0x8339c5f9 0x9dde2840 0x00c2d730 0x6402335f
- 0xf6f84eda 0x5b0e628a 0x140dbafb 0x0533ee67
- 0xa7523e60 0x20ca14b3 0x1145d280 0xb0c0ba41
- 0x81f174d1 0xb80fc64e 0xe8321cfe 0x5762e501
- 0x9e266b75 0x2695a738 0xe3104779 0x1d1ea19e
- 0x15fd1d53 0xf0fbd4ee 0xc82f4552 0x4ea98e23
- 0xec892d69 0x66ccadeb 0x2fdf99b4 0xafffec15
- 0x2de5ee13 0x5e6ead7f 0x20b111cd 0x752254d1
- 0xc0126f43 0xe2695fd8 0x38651d40 0x15b708ce
- 0xf2c2ffdc 0xec24c68c 0x04351ddc 0xceac029b
- 0x0525fc89 0x90e28526 0x0a23a4c2 0xbb33a5c4
- 0x13f1fc38 0x66d79cd9 0x0acabe80 0x8d4ef5d8
- 0x4091808e 0x02f7150b 0xf550597e 0x52703c3f
- 0xfc954b68 0xe9ebaccb 0xd4f35b2a 0x93793446
- 0xc40799e6 0xa963fc0c 0x92c8d8f1 0xbc8218dc
- 0x9ec5c30a 0x8a6a2217 0x63d13dfe 0xea664e1e
- 0x487192a7 0x1c8f8610 0x88e20f93 0xc54a6de3
- 0x0111ae79 0x1335f02e 0xa2e2d37d 0xc2563697
- 0x5fffcdec 0x233919ab 0x3bab1329 0x61943e99
- 0xea7940f7 0x3cc62cf4 0xaedc5bc4 0x41b63f2c
- 0x6dbf285f 0xb4793534 0x0e1013f2 0xc54d8c2d
- 0x23c587f7 0x75df0092 0xc055254a 0x55db2c71
- 0x518eaa5b 0x55c810d6 0x9c44ca37 0x034287ea
- 0xe06a0567 0x221a0d8c 0x037a9164 0x36693ef9
- 0xb7d270a6 0xa8d84a63 0xe8862970 0x484077b7
- 0xab426cb7 0x37db7c9e 0xb34e1752 0x35444958
- 0x00d48e90 0x8142602d 0x8ca28e2c 0x714598c9
- 0xb1cce1be 0xbb98db74 0x400e1029 0x330cb2b6
- 0x1fd3f8ce 0x2abf7516 0xc2d07e5c 0x2b1d2b80
- 0xf06bd895 0x2fa7bc09 0xbdbdf893 0xd8466f85
- 0x61e551b0 0x5b99bfb8 0x86ea5ee7 0xfd82ff9a
- 0xd7c6344a 0x1fa144d8 0x650f0f02 0x71bd73cf
- 0x2825177d 0x56c76399 0x2e0b873e 0xc3bf939d
- 0xf8bc3c1b 0x468482e7 0x33cb98a7 0xa679eaf4
- 0x32ba9b49 0xde86d50c 0x9eeeeee5 0x94a306e5
- 0x432e1c9c 0x37997d0c 0xa84d981f 0xbe07b56d
- 0x4ab6d465 0xa3cd92c4 0x5dea82ab 0xf771249d
- 0x78f87ba5 0x8105df1c 0x3d74e1c1 0xf48cd4c1
- 0x8ad010e1 0x9e9a2758 0x509c8953 0xeaaed79a
- 0x97a4ecb7 0x23ffceb0 0xb3e42e61 0x5f41b4eb
- 0x14d2804c 0x2d635ad3 0xe1314781 0x3921ec18
- 0x3dbebec3 0x94e0df22 0xb0b4724e 0x0e7f986b
- 0x83dd7694 0x7041a22e 0x3c942757 0xd6ff5cbb
- 0x048b0426 0xa5d6c4cb 0x1f4e3bbd 0x78d5924e
- 0x6a857d77 0x1d115ecc 0x73c6a888 0xefb934ee
- 0xa7d1702b 0x6794a668 0x03715b90 0xfbab19f9
- 0xd5a433df 0x12f4d421 0x40519650 0x636a093e
- 0x1601be15 0xe0fbef6f 0x79d775bc 0x789c3a30
- 0x4d9fa618 0xedf8fa70 0xb0fa402d 0x692ee91b
- 0x5a593e5c 0x0fa3667f 0x3f51a636 0x935e28c7
- 0x230b725a 0x4929bc83 0x76de40ad 0x2d9a5f7f
- 0x8799e033 0xbf2700b0 0x5220159d 0x1ed71ca5
- 0xcc66f114 0x15fd868d 0x4236645a 0xded2558e
- 0xa561cc0d 0x02822e5b 0xd0177f80 0xf09badd9
- 0xd5380ae3 0xcfc11a46 0x36713416 0x7f3d60cc
- 0x4018797e 0xc6b23941 0xcb5a4861 0x614ce6df
- 0xabfc0629 0xa519bcfc 0x911f04f0 0xe509b546
- 0xbb411eb9 0x9e6b921c 0xbf0b1c70 0x80c2901c
- 0x85786713 0xad2aafec 0x62711ba7 0x6edb4971
- 0x214eb137 0x45b1b313 0x6742d5e9 0x7daf37a6
- 0x21d6a27a 0x059424f7 0x2c8c3dfb 0xe7a06c77
- 0x10815625 0xb4dc69e8 0x52767f66 0x44d48738
- 0x84d26c93 0x09008893 0xfc21394a 0x82155a72
- 0xc4fd7512 0x6d43cd2f 0xcae99e08 0x453175ae
- 0xc6ee93a3 0x2fed0eac 0xe48fb73d 0x0afe2d2a
- 0x5966735e 0xdc7e5fb6 0xed1ef13d 0x7e08a106
- 0xd3ca0e6b 0x4ce5ca02 0xa0beebed 0xe982c609
- 0x1ee9e5a2 0x24ae26cb 0xfd4c08d4 0x5e85e850
- 0x11b54b3b 0x87209692 0x4a5b0c35 0xcd25dd6f
- 0xd9570253 0xaad0b9fe 0xaf984fee 0x6cf7ae2d
- 0x45d9926c 0x07a66ac6 0x8e7aacdc 0xaf587d66
- 0x53972a4e 0x8da4a6c9 0x2bc311e5 0x36938ae8
- 0x179b965d 0x515743f7 0xb5bbbdcd 0xd8602715
- 0x9e43049f 0x4e78a080 0xba3f1750 0x68635cf0
- 0x85823047 0xbb03b5fd 0xb0d747c8 0x58d214af
- 0x94b1ba85 0x6d2cf8ac 0x2bc1faeb 0x6bd7c1e3
- 0x127658e9 0x8b499020 0xab8f0f62 0xee665a6a
- 0x89240e4d 0x8a95342b 0x00b38ccc 0xe6b14d9d
- 0x32a2af71 0x4c9ecb69 0xc8de2685 0xd7385184
- 0x8e943872 0x809b2c79 0x108511da 0x08b4f54d
- 0x95f52442 0x26fe296f 0xf7e037c0 0xa1aecdd3
- 0x89774a91 0xde67c55f 0x1f9816dc 0x1469a4c2
- 0x28240be2 0x5fd0ad14 0x0949db3a 0x451b94d3
- 0x637e6d49 0x8a4771c8 0xf65104b7 0xc3058c40
- 0x592fe4d0 0xe26129f0 0xe66e6ce9 0x26ab39b8
- 0x308da532 0x205afe77 0x6dc78664 0x84d4890f
- 0x9d49fcb0 0xcac8f2ed 0xe713d798 0xfed7c75b
- 0xe441a0d4 0xdf60df37 0xc2eed2f5 0x2d68b20e
- 0x7827c89a 0x9d4cb9f2 0xb8912cce 0x07516335
- 0x976ffbb6 0x5cd0de48 0xed716f54 0x6f3c9f7f
- 0x34cf42d1 0xc1027cbb 0xde67c065 0xe0a229af
- 0xfc8bd2e8 0xd62ca176 0x8bfb76b2 0x54a1388f
- 0xe0650bb6 0x6d60682b 0xe16cf130 0xbd7c3ca2
- 0xea642814 0xa25f4d44 0x27013786 0x7316aa38
- 0x571511c8 0xf1b6b789 0xb7bfe72b 0x8fd2652c
- 0xbfc7771a 0x51a2e551 0x3bd738c2 0x2698b495
- 0xec69a196 0xd5ecb5c4 0x9bd3224c 0x6d9ab4cf
- 0x326c9942 0x4d711191 0xde9be50a 0xa980ca0b
- 0xe8e59dd0 0x4439e4ae 0x35de914d 0xee499a84
- 0xd1ca0c9d 0xfe6ee96d 0x5b1f4fd0 0xabf0621a
- 0x0c8220c7 0xcb6dbb1e 0xa5116036 0xe858d3c3
- 0x728e3a56 0x3b33e818 0xbe2643c1 0x497bbcc7
- 0xeb369828 0x9a4a01be 0x8c7e72a6 0xaf052f25
- 0x8d3ca85b 0x4703e55e 0x45647d4c 0x86d1e3e8
- 0x40ab59f9 0x3259b195 0xf979a147 0xb8961870
- 0x88b024f9 0x366e26bc 0xd6811525 0x252910c2
- 0x4223a20e 0x7fc971a3 0x4a639bf3 0xb6550c3b
- 0xfe05e552 0xbdc98897 0x509923ff 0xf51a5abc
- 0xc6cc0891 0x61cdac05 0x03a68664 0x1b80cc76
- 0xe18d8ee1 0x798bb4d2 0xd7769bf9 0x9ab4c02d
- 0x7484774b 0xa9ee2c8b 0x87d34c85 0x15697682
- 0x9f6a4a55 0x9d7a731c 0x10014d6a 0xb9798070
- 0xd42f79cb 0x89db59b3 0xd5b0a0b6 0xf60864a5
- 0x2d6fb084 0x1cb607b2 0x48232701 0x9310cbc6
- 0x5bc81c98 0x6b25016c 0x2014b99d 0x0836e60b
- 0x0addbc4c 0x3b8bac7c 0x8d95ac77 0x1d56c3c7
- 0x58333104 0x3d6eb719 0x676eb951 0xd5c2d1a3
- 0x239dae86 0x92181ab8 0xbdde9741 0x7995d452
- 0xe0020661 0x2f80c8b7 0xeedcd4fc 0xe4bde175
- 0xb98fdf78 0x84b9228f 0x78ecb4f3 0xe99e5d46
- 0xa33b9b96 0xe2cbc71c 0xc19e2146 0xdc0ee758
- 0x2d8f8767 0x2036685b 0x149df155 0x2e7ab376
- 0xb13b4266 0xf5c8a3b0 0x02ca1e19 0x1badd81b
- 0xb9c1832a 0x73b31f75 0x69979b55 0x567070a2
- 0x2edeb3dc 0x26b55921 0x461df49f 0xc1aba883
- 0x25d6faec 0x5260e9bf 0xa8ccdd4c 0x04291961
- 0xfaf7a1b8 0xbc2d36e3 0xd6c86385 0x2757fbb9
- 0x62c7107c 0x87dac461 0x0c006454 0x0e971e49
- 0x4749afca 0x7f1fb389 0xdc0b69d3 0xc69fab09
- 0x12c372c9 0x78480a51 0x8ab03a94 0xb37022ca
- 0x1d00e893 0x0989de45 0x8c819503 0x8e0e1c06
- 0x11cfef86 0x3c2386a6 0x66c0e6c8 0x1befa478
- 0xd2e7a4a7 0x9a8b5917 0x2cfa1816 0xaf7e6c7a
- 0xd6c9f0ff 0x1aada3e0 0xbe36a471 0x5a91f3c7
- 0x6c61ea95 0x5246ef7c 0x20bc86c4 0xcfd87abd
- 0xdc61f595 0x8310a684 0x0477e35c 0xe59e776f
- 0xfa403863 0xdaf7bcb1 0xd6084825 0xb90bb047
- 0xeb9ff684 0x7223fbca 0x6b4af987 0x6b2553f8
- 0xdaabc6d2 0x82e2ebc3 0xa7c1c054 0x667eb0a7
- 0x53a0c7d4 0x3fcba743 0x38170187 0x2a2e5830
- 0xee134608 0xcd6e0112 0xac0831f9 0x9537d532
- 0x1e176b9c 0xe3fcb69f 0x17a2eee9 0xa9e6467f
- 0xbf6b0246 0x6a08c0fb 0x7fb943b6 0xb8f67c0e
- 0x2b3b4ffc 0xb155d20c 0x4eb5de53 0xf078715b
- >;
--- /dev/null
+/*
+ * ---
+ * This is a device tree fragment. Use #include to add these properties to a
+ * node.
+ *
+ * Date:
+ */
+
+compatible = "intel,microcode";
+intel,header-version = <1>;
+intel,update-revision = <0x325>;
+intel,date-code = <0x11192014>;
+intel,processor-signature = <0x30673>;
+intel,checksum = <0x5edcd570>;
+intel,loader-revision = <1>;
+intel,processor-flags = <0x1>;
+
+/* The first 48-bytes are the public header which repeats the above data */
+data = <
+ 0x01000000 0x25030000 0x14201911 0x73060300
+ 0x70d5dc5e 0x01000000 0x01000000 0xd0cb0000
+ 0x00cc0000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0xa1000000 0x01000200 0x25030000
+ 0x00000000 0x00000000 0x19111420 0x11320000
+ 0x01000000 0x73060300 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0xf4320000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0xfff634fa 0x937ca2ab 0xb28d19b6 0xdefc54a7
+ 0xd8df0b32 0x13e9a2a8 0x7b7cb24d 0xd588d3a7
+ 0xdb666815 0x5a17bfc4 0x4fca009d 0x099ae8b3
+ 0x198e2c7d 0x7c665bbf 0xc07a1a7a 0x7dbcee26
+ 0x867296b2 0xc885b6ce 0xe602baff 0x68544b14
+ 0xc928c400 0x3add156d 0x531946f9 0x92a03216
+ 0xda352322 0xd967ee1f 0x3c5170a7 0xf6de834e
+ 0x5a2ed8b3 0x9fb8f050 0x450de17f 0xfd5ef070
+ 0x4954575f 0xa3a071ab 0xb56e2afb 0xe2b48302
+ 0x6655a958 0x57c9a438 0x1b2f688a 0x09309bc4
+ 0x0be95612 0x529c1633 0xc48515d9 0x29eb78df
+ 0x9933409f 0xda58dea9 0x58c805fd 0xbc110f5a
+ 0x40780ec0 0x6ad59bb3 0xc7387fb8 0x591c1490
+ 0xf9335932 0x32130e0b 0xef4b3c96 0xacd903f2
+ 0x5b362539 0xe7f85529 0xcb17c41f 0xe7e440d8
+ 0xfaf7e925 0x969b76fb 0x5edab8c7 0xf00012e8
+ 0x121c2971 0xe5b18959 0xadfd07c0 0x1f09c9d7
+ 0x9781006a 0x39550073 0x6c438b6d 0x436f60bc
+ 0x11000000 0x1f504653 0xe21b5652 0xe97686b4
+ 0x5f67c59f 0xa9b26fd4 0x9dc84f1a 0x0f02451e
+ 0x0a821675 0x12547714 0xefe1084e 0x91260f23
+ 0x17e46cf5 0x3dad6dd8 0x4e16210b 0x0472bd56
+ 0xd3fca8a6 0xfa3f5184 0x87d91976 0xa7b008eb
+ 0x17bad553 0x89835b41 0x32e7d87c 0xdfcf298a
+ 0x6a740196 0x0405a296 0x4f830df5 0xfcf047f1
+ 0xca0e7a10 0x8d0afa7b 0x08facdae 0xcf7bbe22
+ 0x8e08e283 0x6b51333b 0x452cf734 0x03da5390
+ 0x7075365b 0x402e71ba 0x4a8d4547 0x0da62d39
+ 0x3fcae342 0xe8cb1437 0x6ddc21bd 0xe22b5edb
+ 0x319decc1 0x6c558ad3 0x3b44648a 0x8cdf8642
+ 0x5a3a8cdf 0x6aae06b2 0x7360d1a5 0x774351c9
+ 0x88681d42 0x466d3573 0x6d8538cb 0xa3350f1e
+ 0x7b431d3c 0x21074f32 0x6955a68f 0xa3988611
+ 0xad1c79d3 0xe00884c6 0x12e5baa8 0x7dad4109
+ 0x61d16a48 0xd2074a23 0x58611da6 0xad7b774e
+ 0x90a80987 0x05aca95d 0x482b51ca 0xbb8fe27d
+ 0x2abe5e48 0x590c8b98 0xef745dbf 0xce17a591
+ 0x6607216b 0xbefec476 0x7a8b08a9 0xb281bfc4
+ 0x76f7dc81 0xaacd78a8 0x38cd6888 0x9636aa2e
+ 0x7035053d 0x069305f5 0x0da92823 0x46d344df
+ 0xce46f308 0x1fcca5d0 0xf4b0daa0 0xed8ecd8e
+ 0xdae9e33d 0x69be5bef 0xc545c95b 0xadeaeeb8
+ 0xdd903783 0x5a2f3287 0x73865fd0 0x865d709d
+ 0x1ed58537 0xe44c821a 0xc9ad0d97 0xe81b9851
+ 0x552cf1e7 0x03a3b2dc 0x219194a0 0xd8875c82
+ 0xe39b25b7 0x61149b84 0x79a99812 0x287eada3
+ 0x057cc940 0x0ed85405 0xf4cbb20d 0x8d87a099
+ 0x2018b6ae 0xd14f3646 0x35bf5bd8 0x82931be1
+ 0x52234bd1 0x9143a967 0xd9d1a3d4 0x869c266c
+ 0xcaff55f0 0x64ad39c2 0x02435da4 0x32e2907c
+ 0xbc2682a9 0x60863cea 0x163028c0 0x007fc9fd
+ 0x6553eb56 0xab00c11c 0x3aa77e22 0x87f722d4
+ 0x004850a6 0x5460e040 0x9e91042c 0x46dd43c7
+ 0x3b05c92f 0x060ce074 0x62730a12 0xc6d47872
+ 0x03d26f06 0xf7b3d04f 0x92adc672 0xc31d8130
+ 0xd40eab22 0x616b7f8f 0x56b2c742 0xde6015c3
+ 0xc10c0d02 0x3ab28f97 0xa091494f 0x1fa0c28b
+ 0xc76c5661 0x27effd8f 0x3de80c1e 0x5713a42c
+ 0xd9114db2 0x17ab3314 0x0e3aea42 0x60712f1f
+ 0x4a7d4389 0x9db1857c 0x1103baa8 0x579462a6
+ 0x82ac5a7e 0xda8d9f67 0x835bed5a 0x08705479
+ 0xbf4bd494 0x082d8b22 0x408878b0 0xa698e9d8
+ 0x27fba6da 0x2308fb71 0xcc1b9c9c 0x5200bd18
+ 0xf1baf601 0xe67b1d1b 0xf3c95153 0xf8fb4f22
+ 0x2859e330 0x3e7bc864 0x02c88201 0xf835c5f7
+ 0xcefd31e1 0x4c430b43 0xce13d99c 0xf9aa01ab
+ 0x9f5c0d3a 0xbf06696f 0xc834c22c 0x145cf026
+ 0xb45e1f1b 0x97302dd5 0x5b5d108a 0xffde5401
+ 0xffbd2caf 0x8eb5c823 0x3f113711 0x144ec354
+ 0xab3864a7 0xeee70354 0x208ea79c 0x1b2c7364
+ 0xc3cb82d0 0x21d9b3bc 0x27846121 0x50bd8910
+ 0x43a2616a 0xface9686 0xe12195b9 0xde4639d9
+ 0x0b88b493 0x32b1685e 0xbd782bea 0xc674188e
+ 0x23425d26 0x9d2d3c81 0x33b3a260 0x4ebebf2f
+ 0x6a634d1f 0xb977b1c1 0x476223c5 0x654c5461
+ 0xbeaa9c98 0x75242b30 0x26061148 0x69889154
+ 0x910a2132 0x07df3136 0x372a7cf0 0x58541d8f
+ 0x65ce78aa 0x0c6e4ff7 0xab8c31b6 0xbe39960d
+ 0x63bc072d 0x53872b7c 0x959f3049 0xc13ba7a0
+ 0xd7111cd7 0x5e68763f 0x923dc674 0xdb2e8a4d
+ 0x5c2cd5e0 0xd93be0e2 0x1bccff32 0xbbdffc8a
+ 0x1641ff1b 0xeab24fc7 0x70aff37e 0xc87fe4f8
+ 0x32afd630 0x060dbdf9 0x6e119a8c 0x987e51c5
+ 0x57abb8f6 0x15b3755b 0x938f709a 0x7c4b5522
+ 0xfd376691 0xd909457d 0x58656778 0x3bdee518
+ 0xaf65afd2 0xe1cd74ec 0xd2bc8a3a 0x9aa30f8b
+ 0x6e1f183f 0xc2fa7bf8 0xa60385fd 0xe0320d46
+ 0x2e5bc0df 0xf95b8c37 0xfa760bc7 0xc8960509
+ 0xdebed2f2 0x560ac9de 0xb3ac0e62 0xefe328dc
+ 0x358d5330 0x72c31526 0x5932780a 0xb3b824b4
+ 0xda37daae 0x69dd74c1 0x41c91b5c 0x8180b956
+ 0xc69574b5 0x1830993b 0x0d5ef14b 0xa8dec45f
+ 0x5c4019ed 0x559e7b51 0xd07a3c14 0x49208a2b
+ 0x5265dad8 0x1b9826c0 0xb8cc3edf 0x63ccaf33
+ 0xdfdfb78b 0x3292f976 0x9f1ddbc1 0x2e3bfa8f
+ 0xc4b5a941 0xd8b1fcea 0x68764a2c 0xbec828e1
+ 0x07db4118 0x2022cfd1 0x6be82389 0x7ecb046a
+ 0xd31a639f 0xa0f50a18 0xbb4dc035 0x765a6e5f
+ 0x59fe51c8 0xd2138643 0xccfeebae 0x234c0440
+ 0x49bcdabd 0x88e86cb6 0x48760e88 0xcc34f20c
+ 0x0977dead 0xf3f0d324 0x736f4df6 0x0a94f658
+ 0x0bbb01cb 0xe962549c 0x6a1c39c6 0xbec25a26
+ 0x4cb71dd7 0xf1043105 0xba0f3726 0xc97645e3
+ 0x23d4b508 0x7c0827ae 0x097f96f0 0x0a054e0a
+ 0x79e7a543 0xbedbd7d1 0x52d2b51f 0xebabfee4
+ 0x1f0e76e2 0xa07922a8 0x3a630243 0x41b8b460
+ 0x11f8e1be 0x97ab45cf 0xd952588f 0x70461a90
+ 0xdf62afd8 0x169cd499 0xc9a38028 0xe2d36ebf
+ 0xa86477c5 0x1890d4fb 0xb78c189e 0x6002b07d
+ 0x346599a1 0x998b8687 0xa073f3ff 0x561c2a62
+ 0xc4904bcd 0x59a5194c 0x6b2d285d 0x3c7208dd
+ 0x1a2e9b5e 0x7a7732a8 0x2c803c45 0xb307e8fe
+ 0x9a402093 0x521740de 0xb25a372e 0x1abeec65
+ 0xd9f84a17 0xed465fd4 0xfcc2e034 0xdc9bc727
+ 0x9607ab7b 0xe0bd62d8 0x8630873a 0x361b3b75
+ 0x603255fa 0xd815876b 0x32d0e705 0x5f99a520
+ 0xf15a63b3 0x83f3009f 0x7ad4b916 0x1ba9093c
+ 0x824dc86d 0xcd792af9 0x8d1e623d 0xad4877c1
+ 0x2c09f508 0xab062540 0x242c5f5e 0xb46796bd
+ 0x0bbc1a5d 0x02be8545 0x4ad68f23 0x370b4b1b
+ 0xc16c7ebf 0x8b65ef74 0x11b64ded 0xc00f5586
+ 0x41d6033a 0x0f79c8e9 0x356094c0 0xff3ec289
+ 0x11a0d26f 0x347ebbef 0x23f2b11a 0xb6b15aca
+ 0xe6856320 0xacecde47 0x513fbdea 0x7d7ac026
+ 0xb72b0011 0x7d8cac25 0x222704f3 0xabc6b166
+ 0x60995d26 0x95ccf438 0xce21d44f 0x27e15e98
+ 0x9e229da5 0x929009b0 0xe79afdb0 0xf91bcab4
+ 0xe5894312 0xe98d7607 0xb2bd2408 0x5abc5003
+ 0x532b2c0a 0xb41dbdf7 0x248d6b00 0x7b811187
+ 0xff7afcb3 0x818c2c38 0xacc7a704 0xaa14713a
+ 0xeed076d3 0xcca8d4aa 0xd90177c0 0x9fcc01ae
+ 0x8edd4189 0x1c896cfe 0xc4856a25 0xbeeb2217
+ 0x52249b24 0xad45ff42 0xb43ae3a7 0x4bf0df57
+ 0x91e369cf 0xcfafc488 0x6c218f44 0x0aab7b09
+ 0x5f9c2410 0x87cdac03 0x986e83cd 0x56a7bba7
+ 0xc7d2270b 0x467b995a 0x4b398fc4 0x64f04f87
+ 0x30334708 0x8d0c7e49 0x69c792c2 0x725eba77
+ 0x6870df0c 0x84d8a30c 0x0c5c6ac2 0xd9bc43cb
+ 0xc52ab350 0x64878641 0xef306551 0xcfe54739
+ 0x1aa176e8 0x6f1a7e1a 0x965be809 0x21e345f9
+ 0x9ad41590 0x5e5de630 0x82cc1207 0x6120734f
+ 0x846449fb 0x9d822218 0x2c8e025f 0x747f180c
+ 0x90a64365 0xec79c646 0xaf2a29b0 0xb5a4cfa3
+ 0x4f5b82de 0x0b7ad494 0x3b02b3e0 0xe5d96463
+ 0x241aa4f3 0xefeeed3d 0x6e6d49ff 0x2d45821c
+ 0x4598f881 0x7de00efb 0x25509321 0xc64ceb14
+ 0x218dde9d 0x59c3cf6b 0xf8f702e6 0x3e0cf0c0
+ 0x178f8a4a 0xc8aa3338 0xdcb7989d 0x297f30a0
+ 0x270b7ea6 0xceff00a3 0x22ec287d 0x50673360
+ 0x1fccbc8f 0x66c3805a 0x8a327234 0x52e1978f
+ 0x538b121c 0x1f2fa957 0xeada2b4e 0x29423125
+ 0x81d3a179 0x968b4097 0x3522324d 0x5cccf20c
+ 0xa6adfc16 0x3d1cb3b9 0xbaefea60 0x57978720
+ 0xf5eb4b9c 0x5a8b3acf 0x4f3ac467 0x94a7e4ca
+ 0xb4100044 0x54fc2e4c 0x16ec9a22 0x3aecc34a
+ 0x6df7f52a 0xe1279f5c 0xaa25ad1a 0x907baa13
+ 0x51c19956 0x35987a2e 0x1adbb651 0xaf0a5285
+ 0x83ce12f0 0xcbabf9e6 0xfaa1cbff 0x73139922
+ 0xc6f5b18a 0x9f91c4fd 0x6583a1bf 0xa144eed0
+ 0xc9f2b43b 0x249407d3 0xe3520b2c 0x60dc9aba
+ 0x53ff14c4 0x24133ac0 0x4b6a4452 0xe0aea55c
+ 0x884302dc 0x24d8ced4 0x3db6976b 0x48aad95a
+ 0x7e4defba 0x80215bbf 0x62241272 0x0747edc0
+ 0x32206c16 0xffebdcc1 0xdd1662c9 0x1bd3eb01
+ 0x785d4a0f 0x4b37087b 0xce5142e8 0x1262ef36
+ 0xb04665e5 0x84491927 0x9df53726 0x8d175409
+ 0x79fcc87b 0x647f1da3 0x68c89316 0x14926e0b
+ 0xf7ca65bb 0x20634f45 0xbd13da4c 0x683991d5
+ 0x81cab56c 0xeb840c6a 0x8954031e 0x06deeb42
+ 0x92f26c77 0x6b2de0c6 0x80a23d71 0xd11b9d58
+ 0x703498a0 0xacade451 0x797bf69b 0x0f6b0db2
+ 0x92430faa 0x1756940d 0x99aa9ef0 0xcee8c383
+ 0x8bc70735 0x19b263e3 0x36a5345d 0x271c893d
+ 0xa32a1999 0x0345759b 0x3f89c616 0x52132086
+ 0x10d16c86 0xd7425739 0x961a376a 0x3c4f62a9
+ 0x64c0bbe2 0xbf9fcf69 0x3b9055a6 0x88ce084f
+ 0x12d088cc 0x2ca9dba5 0x01e2d480 0x7510c47a
+ 0x48439c10 0xb82ea353 0xc749c7e4 0x9a768665
+ 0xb4233311 0xd62cc354 0x978f7fb4 0x24598a22
+ 0x559f80e1 0x18038c96 0xf4a8607a 0x9b45454a
+ 0x966c8058 0xbad65e97 0x3247c4c1 0xf402cdb6
+ 0x9210a715 0xa4f007f1 0x99154ab2 0x65fbcbfe
+ 0x9f80323c 0x34699431 0x01676213 0x30a1e6fa
+ 0xd25522c1 0x379c77d4 0x1871da5e 0xce5e5496
+ 0x3d6b8be4 0x1dca1d1a 0xa00a2d5c 0x87e10ca3
+ 0xe693d866 0x460474d3 0x3f63c391 0xe7ea29d1
+ 0x2cec6e1e 0x14d4984b 0xc5d6b60b 0x6d6e0837
+ 0x3d4c924c 0x90489257 0xfc8d6a83 0x925c8cb2
+ 0xbfe92b1c 0x49242696 0x2e61cd01 0x2257e796
+ 0x05a1a9bf 0x3cf1f59c 0x8dbca249 0x224abfe4
+ 0xd03b80f2 0x69958e27 0x2ab3a3cd 0x12c385a2
+ 0x009f8225 0xfdd732be 0x008ab069 0xf3c83e93
+ 0xaeb24747 0xc589db37 0xcde6618d 0x20bd0207
+ 0x385e9501 0x0fd9495c 0x5b2e2ed8 0x1078f265
+ 0xc90dbe7a 0x1a41d9c9 0x8f9874d3 0xafddd25a
+ 0x6c06f499 0x30fbfec6 0xd7c880a7 0x88707b30
+ 0xa6dbcb05 0x952fbc2c 0x634e6259 0xe6b40847
+ 0x6461bd47 0xae4d5763 0x2b2bba28 0xb80d9555
+ 0x2ec5ca1e 0x29d9df5f 0x41cc03d9 0x2235582b
+ 0x23835179 0x21d0ccf1 0x804ba9b0 0x57b9b8d7
+ 0x1497654c 0xf1e54c96 0x9049e9bf 0xec7a7398
+ 0xcfe60cef 0xd8a41f9e 0x924e41e8 0xd4310360
+ 0x0bc22c8e 0x8e9949f5 0x1de2e407 0x83cb7e67
+ 0x43eadc46 0x428a67b1 0xc3be2567 0x2e64f02d
+ 0x416bb222 0xbc70ec3a 0x582bb3ed 0xcda0b133
+ 0xb906e982 0xcaa44950 0xf9c503a3 0xe83283a1
+ 0x5126b967 0x525d3279 0x0ac69ff9 0xcd705322
+ 0x2d8429a9 0x6e76fe2e 0x81794602 0x666ab1bc
+ 0x3f31b894 0xcffd21c4 0xf5cd3705 0x114db9a9
+ 0x4ab6f993 0xc413712b 0x4d3e7649 0xd167da79
+ 0x33c9f1ce 0x1d7c81f4 0x06f9b423 0x747aff7d
+ 0x0d52f157 0x839b8075 0x0a853d42 0x6203b11e
+ 0x4677d3af 0x38abf342 0x3623c79f 0xbca55b66
+ 0x8bc84201 0x4bc018ea 0x03233c7c 0x615f7eb2
+ 0x0c60cef9 0xe0308dbf 0x12031915 0xb29fbfb7
+ 0x78434066 0x4ee2c89a 0x184f0327 0x47f9d7be
+ 0xcce175a6 0x6b3e0b3c 0xdc5b8812 0xc4a0678b
+ 0x4023109a 0x152b2c76 0x363fc158 0x8c3e2f21
+ 0xa064aed6 0xeb042d45 0x23c24cc2 0x1a8af60b
+ 0x07b9b84b 0x29d990b4 0x2609d654 0xddb12106
+ 0x23cb29bb 0xfd7be4d6 0x458e378f 0x3435ef60
+ 0xf4c5a257 0xfe2b302b 0xa44c6fca 0x9594eb9c
+ 0x42562735 0xdcd2ae0f 0x6b121b2b 0x955db8b2
+ 0x99324409 0xf9040b5a 0xd4ee06a6 0xe02dde19
+ 0x1d689a66 0x01c5034b 0xe16762ff 0x404c08a4
+ 0xb797f9f9 0x409e15c8 0x7f8a86d5 0x8c097dc3
+ 0x88853010 0x7870d226 0xd9684129 0x5b1f1ff5
+ 0xcf0f9327 0x5631fdd0 0x85ad0d39 0x9a7a3da0
+ 0x2f196f96 0x98f80f57 0xc2f5bc2b 0xf3c89a99
+ 0x5167b4e8 0x38a5b8da 0x31274e92 0x316736b3
+ 0x0ba380a6 0x4cdab635 0x55c10afd 0x0aa42f67
+ 0x5cb9233d 0xefbea208 0x614caf1e 0xa7b51e52
+ 0xbca0669b 0x3e82e113 0x8437d9ea 0xed52af57
+ 0x90c58450 0xd58d0939 0x6065bacb 0xa0f03557
+ 0x28dacf55 0x95616db9 0xe22c6304 0xf95f1451
+ 0x68a017d1 0x744940a8 0x29656d46 0xb462a093
+ 0xda67e118 0x9beae14d 0x41295fc2 0xf4832210
+ 0xd546e11c 0x9a6fbd36 0x1fa63a12 0x080dd512
+ 0x142445a8 0xd7924445 0x7e81a85d 0x0fe2facb
+ 0xaea25515 0xdadd52ac 0xd4d4c9d1 0xe53a1391
+ 0xf23efc0e 0xae8d8a11 0xe4a18294 0x7897206d
+ 0x882f7598 0xcfba1c50 0xd2ab7795 0xabce7dd4
+ 0xf953ec47 0xe61d6306 0xd16895b7 0x8754c3fe
+ 0x71b45033 0xa13c4375 0x12eeaccb 0x982003cc
+ 0x207896e1 0x49d067a4 0x5f302283 0xe4df36fd
+ 0xb00cfa4d 0x9ae60753 0xd7bac02a 0x994f4996
+ 0xfe146dae 0x97626cf2 0x9e42c940 0x6e337e36
+ 0xb6afed1a 0xeb2fd381 0x934baf9a 0xf832addc
+ 0x6f979a6f 0x99487a6c 0x57544e74 0x0c66d838
+ 0xa061f71b 0x0ddcd233 0x1848e2c7 0xd4c88955
+ 0x6c64fe17 0x9bd44131 0xe582e3d4 0xa005bd26
+ 0x703b0eea 0x21bd18c1 0x664a9e98 0xe0590718
+ 0xd3e4736d 0x0ff91923 0x5dc8871d 0x31699e80
+ 0x61a37893 0x1ae82483 0xe45118a2 0xfecea103
+ 0xf41828d5 0x4ed049d7 0xdfbade95 0xd238ccf9
+ 0x992a8e55 0xa09b38ba 0xcfbd44d9 0x91504f56
+ 0xdaa43955 0x1b33f9f3 0xa78246cd 0xa8fd012c
+ 0x45af83b9 0xaac19610 0xd89f53b1 0xffd31eeb
+ 0x6197b65d 0x7f47d34b 0x6e93fdfb 0x595a289f
+ 0x385174bf 0x6f3496b9 0xe49b3f1a 0xfe745cd6
+ 0xfdb24e8e 0x6269a7ac 0xa8deb024 0x959a4ca3
+ 0xfb164ad5 0x0a74d852 0xc022a450 0x7c46bbb4
+ 0xb2cb2e2d 0x1fc8d084 0xd1cd2aa7 0xf301e029
+ 0xd0d8bb65 0x89968da9 0x05409da8 0x24134907
+ 0x48c6a151 0x390da0bc 0x32816da9 0x6fdda0f8
+ 0x7a5e60ca 0xc500eb10 0xdbd2126f 0x22dc1c8c
+ 0x165efc8e 0xc52f4553 0xe4488f60 0xbbbd961c
+ 0xa965f0db 0x256cafb8 0x35b82b80 0x1b9bbf5d
+ 0x69aa3130 0x2f5402f1 0xb7db92c6 0xcdda626d
+ 0x9d50e8f8 0xd75b2b43 0x23869cbb 0x18f1fc43
+ 0xc4500abc 0x7b22b871 0x93d281b7 0xe72b7f91
+ 0xb8a3d2f7 0x40de9703 0xfde8a07c 0xff614acf
+ 0x14ba7173 0x4c9d758d 0x67ba546f 0x6edc57de
+ 0xe3397593 0x6076ad6f 0x54bbf0fb 0xc7aa004a
+ 0x9099bac2 0x43001c2e 0xef39dc79 0xfbf16c39
+ 0x43d3b4d9 0x4e1ccb60 0x0a5770ee 0xfeb0bb21
+ 0x8f5ef605 0xd69a2259 0x5ae00282 0x81422a35
+ 0x537fcf9a 0x740907f9 0x1e980cf1 0xfaf41103
+ 0x8554081f 0x9044d4fa 0x9349fecb 0x2e12081a
+ 0x9c63d3ad 0xb02fc0e9 0xb9f71ff1 0x7ffc123b
+ 0x221be745 0x6b1378b4 0x283d86e2 0x24fbdd88
+ 0xecaa1214 0x0e2a05b0 0x49256317 0xe1efbdd1
+ 0x2b40232e 0x8a44c71e 0xe5ab10ac 0x55baf697
+ 0x57c9cb8c 0xef2cdf39 0x9e28e29c 0x82fa8623
+ 0x85090ab9 0x4bf3c17f 0xeb34b5e7 0xbbffc965
+ 0x9be897b7 0x7a54a66a 0x0182c5b7 0xfbe04efa
+ 0x79a3aedf 0xb04bdde6 0x12396b09 0x7f2eea54
+ 0x139fced2 0x2ed4e710 0x8e587a3e 0xc1150171
+ 0x3d4475eb 0x3bd4dcbc 0xd15a4ee5 0xf6a03e6d
+ 0xd6946d8b 0xc7f12861 0xb46f2665 0x4778aaaa
+ 0x90fd4944 0x91b58ad9 0xce88f970 0x6b002000
+ 0x3942bf93 0x58560cb2 0x555f27b8 0x51e7e2cb
+ 0xe8d32c0a 0x76979f1c 0x0fbbef02 0x784ee6f6
+ 0x72e1f85a 0xd2006d22 0xe142e64c 0x0e821726
+ 0x0204234c 0x76aff6dd 0x72c02389 0x79674b40
+ 0x48c827a4 0xd60a816e 0x4361e2a7 0x20575b11
+ 0xc0a15faa 0x1bd24f4f 0xde97121a 0x886610d9
+ 0x3c1488dd 0x74331a2c 0xb80b075b 0x1cbaab02
+ 0x310e08f5 0xe7e63832 0xf5559bc2 0x5939166c
+ 0xfb966138 0x2c192ef1 0x3022c840 0x4760139f
+ 0xfc9e25c7 0xa40b3af5 0xf960ef95 0x4bd0fe44
+ 0xf951e214 0x320d1105 0x3886b597 0x90be3da2
+ 0x16b5e7ee 0x81b43af0 0x4a83b571 0xea294a6f
+ 0xe879058d 0xb80d4a36 0x4f3807d6 0xee2a3d4f
+ 0x90fd7abf 0x76a13008 0x3a31e37a 0x60cbe826
+ 0xfddf43df 0xeb00f98e 0xb22c6cf8 0xc17d7ca7
+ 0x82c1b9d2 0xd8408d4c 0x349a8c22 0x55273d19
+ 0xc841f4f1 0x6d54d550 0xcc41b69b 0xc7365812
+ 0x85f41eea 0x432850c3 0xc27c009d 0xe397479c
+ 0x86fe387b 0x578837d7 0xbe61890c 0xdbb0ccd7
+ 0x7be07b26 0xeb6f962d 0x02e3e226 0x490c78fa
+ 0xba8357ca 0xe0e28646 0x098fdd96 0xaf92d911
+ 0xb94371e8 0x2f172a39 0x548d45d0 0x30fad17f
+ 0xfb74d606 0x2f5cbfa2 0x25f720a7 0x9bb55ff9
+ 0x95af7efd 0xbd078a82 0x67acecf6 0x5890b891
+ 0xadb4266b 0x4de99f69 0xa6f5513d 0xc639cde0
+ 0xadf8f9db 0xe49c0753 0xf7abf355 0xccbc3ef2
+ 0x4da3b1b0 0x6b4930ae 0x0e4dcc32 0x44d27988
+ 0xd8a0742a 0x85f9141e 0x4af69334 0x3b02912d
+ 0x8d90147b 0xecdeb8e5 0x8c5c76c7 0xf64f4537
+ 0x4c2e07c6 0x6caa89b2 0x22fbb640 0x75540372
+ 0x07c538a5 0xe3dd71f7 0xd54e1233 0x2bff75b2
+ 0x1b65ed38 0x5d5ee6d6 0xf3d99db4 0xe535f17d
+ 0xe9b355d0 0xfb27c862 0x2418a7e9 0x83020f9b
+ 0x17c850b5 0xc7a49afd 0xfa7cc598 0x4caa65b0
+ 0xe35d78ab 0x5fbe5a68 0xb8b23c84 0xdd30c3c7
+ 0x166d9c71 0xce9512ca 0x8ff12b46 0xc4f5a4e1
+ 0x772f87cb 0x9910eba8 0xd8f966e7 0x1e7a1029
+ 0xbdb95937 0xe8745fd3 0x97bd0c23 0xf08d29cb
+ 0x3e144fc2 0x4ea5c2d2 0x4dbb3579 0xb2d6d1fb
+ 0x59a9499a 0x07de7cf3 0xe5093e74 0x9620e2ba
+ 0x98db53bf 0x0088a257 0x81575927 0x1572a999
+ 0x85014396 0xf252e4c7 0x935494a7 0xba6777de
+ 0xf0cbee95 0x89224156 0x726f5f9c 0xc6a97741
+ 0x438936dd 0x02982457 0x69e0b7aa 0x6b2cfa7a
+ 0xd920fc79 0x088f473f 0xbdc049ad 0x26fe03eb
+ 0x51ce0c14 0xd4ee50da 0xefba7a8d 0x41d48c15
+ 0x2fc64c16 0xb910ee77 0x8fd3c6cc 0xf2ea6eae
+ 0x799585ed 0x78bb8529 0xf5e8dafe 0xc4d2e7ec
+ 0xacb82780 0xc366cc65 0x786dfbe0 0xf6858178
+ 0xc0737f16 0xcd7ac719 0xfc1d25f9 0x9bac062a
+ 0xf861f2c3 0x534306a2 0xc885076c 0x228b59be
+ 0xb5a03917 0xa49ee2e1 0xd7e3f947 0x2993430b
+ 0x936b3a69 0xfddd2df8 0x409bcbfc 0x9a49ea67
+ 0xda19b129 0x52d00d43 0x594b5373 0xb3ec4e85
+ 0x99ba948e 0xd5a139e7 0x0e309bcb 0x824bdac4
+ 0xe846138e 0x8e867ec9 0x3b3b3de0 0xb193c1c3
+ 0x1d972fb9 0x37e7c572 0x2312fe3f 0x233675c4
+ 0xccbe653e 0x7f33fdcf 0x6dbb5b33 0xa1482994
+ 0xb053851f 0xa136a22b 0xab83000c 0x8baa7f8c
+ 0xf63ce4d1 0x0add4950 0x1e2118a1 0x778b55d9
+ 0x11283afb 0xa0ece7a4 0xd5cf4afb 0xaa425954
+ 0x735e7cdf 0x915f28bb 0x9f257f4c 0x35f60425
+ 0x428317aa 0xde7e7394 0x903cd466 0xd3b76f46
+ 0x440cb5c7 0x926ead8a 0x4ad0bc01 0x589d2503
+ 0x36c6dbe2 0xae3cb112 0x8af34336 0x98086144
+ 0x998764a3 0xf18c15fa 0x4c6b1e80 0xdbea3a77
+ 0xdbca504d 0x48e922eb 0xe7d2efd1 0xb2a55650
+ 0xd40359eb 0xd669304f 0x3e0d1323 0x8fdbf002
+ 0xb8cd2146 0x4f70e597 0xadb80b28 0x6968f1aa
+ 0x5785cb7b 0x09d452e1 0x2a24c269 0xeda3c6e0
+ 0x3d3c6920 0xb635c806 0xcc205fd1 0xcc273f90
+ 0x92f36850 0xc094ef55 0x99e33eee 0x775ea554
+ 0xea124752 0x8b006562 0x38bbcb67 0xd2008955
+ 0x14ee116b 0x964f634c 0x5bcf34e0 0x58c28331
+ 0x01cbb9c6 0x56df247b 0x8fe03e91 0x9646fe0f
+ 0x650d96fa 0xe8c99df2 0x7458f4fa 0x76491d87
+ 0xaa84a44a 0x48b0ad6a 0xc0d8c6d1 0xd8ad81e9
+ 0x65b48f71 0xd254bde2 0x2f34f225 0x4eccf8b9
+ 0x25fa9135 0x3662dd06 0x17c9a780 0x1996ed2e
+ 0xadfd4c99 0x613f14c0 0xd80c9926 0x2ef5e5f5
+ 0xb06ec784 0xf7e430e8 0x19e9ef08 0xe3ac3c51
+ 0x78cb1177 0xaf255850 0xcaa6fb41 0x735550b7
+ 0x67eb076e 0xf17b3cb4 0xaa8edd18 0x4aa229c7
+ 0x74492140 0x11d71f59 0x8c275a99 0xcb217ed7
+ 0xa4273190 0x7d9dab3c 0x934381c2 0xdd6176e6
+ 0xdece7df1 0x7ab6bea8 0x303bd86b 0xa9170bfd
+ 0xc8412491 0x84da3ea1 0xd57e97f7 0xbe0bb91f
+ 0x9efc9c8a 0x1c09a4a5 0x83cf52a3 0xd342460d
+ 0xd302163d 0xd05c637b 0x1ebb7326 0x79ba20d9
+ 0xc944f204 0x18a78657 0x89542294 0xf7bd975d
+ 0x5fd7140b 0xbfc96910 0xdc339353 0x952f97d7
+ 0x253d4006 0x99fdff85 0x8116afcc 0x328ac2a3
+ 0x4410871b 0x2dfe8e51 0xf45c01a6 0x40217a8a
+ 0x0c0d19c1 0xd96351fb 0x3bb0b96e 0x287d0ad7
+ 0x5a63c6ea 0x037477b9 0x33ead7f1 0x0183222e
+ 0xbd1242cf 0xbce09c86 0xa9efc50a 0xe388da86
+ 0xabffd93a 0xcadb61fb 0x94320786 0x36731cf5
+ 0x4169fb6c 0x60a3e64d 0x22881d97 0x7eed6b34
+ 0xe3e6b7cf 0x011047ef 0x514a380d 0x1063defb
+ 0xb5c55e9b 0xf548dcfc 0xaa1d300e 0x5aba83f5
+ 0xc02e41b6 0x44925671 0xd7d2129f 0x917539db
+ 0x9f5d234c 0x6122338f 0x3f8a847c 0x9e65ba6b
+ 0xd28e9f70 0x04e78d83 0xad696012 0x471c8f88
+ 0xf42ce5db 0x9f0b9849 0x5db38a8a 0x7fd7d4ca
+ 0x244ea3e2 0xf352a9d7 0xa670c8c9 0xab7fca55
+ 0xec9c1042 0x625ed8e7 0x31f4ff8b 0xa3a8a576
+ 0xec645cff 0x3c971f8c 0x527fdc5d 0x77e4d1cd
+ 0xa8746a1d 0xc4b9af0c 0x41d2e8fc 0x62456003
+ 0x792138ed 0xe672d51b 0x119befb9 0xfd2b4348
+ 0x3b14d25d 0xd36edca6 0xd2f74bdb 0x9ec52dfe
+ 0x97b55659 0xee80103c 0x12555012 0x6d4a8def
+ 0xf1454d26 0xf5c41569 0x4b6e604f 0x92c0851d
+ 0x9f4618c7 0x4e5ad7c9 0x41c7cd36 0xe50a1a4c
+ 0x74c5b18a 0x721bddb3 0x8d67f6fe 0x7afdca7e
+ 0x0a545134 0x137f4344 0x9e5f2d92 0xafc74bda
+ 0x0a18eb99 0xb2718bd1 0x1d9b8d07 0x80232c83
+ 0xe962d93a 0xabc0f007 0x204f0def 0xb292a3d5
+ 0xdfca18f9 0x34fe2939 0xccb61664 0x419dee6d
+ 0x4070f1b7 0x334975c6 0x283a9bd6 0x3dc4a721
+ 0xea8bd79c 0xa4401e2e 0xa378d378 0xf03ebd34
+ 0x5cd39e42 0x0a4ba860 0x34b26a87 0x9979e96f
+ 0x8e872a1d 0xaae3cfc2 0x25876b90 0x8bf1b190
+ 0x6864856d 0x4965cab9 0x9c49f4a8 0x7d9efd8d
+ 0x313413d0 0x52905c5b 0xd43b4f40 0xb3a1cfe8
+ 0xb09d2a80 0x6655a633 0xaee4a3b0 0xdbad5f59
+ 0xffa56b65 0xa0bec51f 0x10e511f1 0x3091be0e
+ 0xb4899296 0xb6640c3e 0x4b0bfd96 0xbb4c2d9f
+ 0x7d6ba4ca 0xe0de7fa7 0x3a7c39c2 0x03d52694
+ 0x9af37318 0x0f1f28e1 0x629c5821 0xfb78261e
+ 0x34c74091 0xab92d7a7 0x226a753c 0xbdb6aafb
+ 0x76c9434c 0xfa167b4d 0x640e7dc7 0x1070355b
+ 0x2264b655 0x03ded64e 0x100ff664 0x38d25b67
+ 0x6715611f 0xef479b2f 0x8f52b055 0x0789f609
+ 0xc84baeec 0x16021597 0xc6d924ee 0x32913130
+ 0x8e86b7c9 0x8532fc4b 0x27c9b92c 0xfd9c38f2
+ 0x63e8c76b 0x9ba845fa 0xad507144 0x7c1eca93
+ 0xaec2e059 0xadf30a5b 0xe9133d92 0x7ef687e7
+ 0x5c89bfc9 0x58d8f8a1 0xcd70ad24 0x316ea0a7
+ 0x5d0957ef 0x8b630a27 0x2c43bd03 0x7925f21e
+ 0x42bb7aa2 0x08bc5d8f 0xcdcb9090 0x417ea6c0
+ 0xce5c5f86 0x10112aa8 0x19674618 0x3e3809da
+ 0x40c7caf6 0xa0753b11 0x7e718c19 0x50bccb67
+ 0xd08e448f 0x5f7cf11a 0xc4fa6c6d 0x9aabb2f8
+ 0xdda811c3 0x37b24fd5 0x31fbd13b 0x954355ff
+ 0x0a3f8036 0x3cc96699 0xc1d0f52d 0x4e976ed4
+ 0xe24ee785 0x3ea3647b 0xc2486a7f 0xe24b8488
+ 0xa23f433a 0xd0ec2901 0x079da6cc 0x617282e7
+ 0xa65c81dd 0x0651acd5 0x14adbf87 0xb62a352b
+ 0x33c9a353 0xbb74a62d 0x97fe7ac7 0x2709dd2f
+ 0x1bd03373 0x5fdb088a 0x94b8675a 0xdb3edd44
+ 0x378021b1 0xafa448c9 0xedad3e93 0x68bc71c1
+ 0xe32f7e72 0x28ad6d83 0x97670184 0x2dfbc275
+ 0xc238281f 0xd07c0e6a 0xc3b12738 0xd0af1b0d
+ 0xfa161509 0x6af28479 0x6350ddcf 0x5de28d1d
+ 0xa2504310 0x1fa39c51 0x41c24f45 0x588cc066
+ 0xcc1f3a6d 0x6231cbac 0x2b60a3b7 0xfe35561e
+ 0xcf92322f 0x412dce5f 0xf7d5628a 0x4eb7aa88
+ 0xd832c865 0x6a97e393 0x1ca8f5aa 0x0fb9d833
+ 0x52a134d6 0x11ede00d 0x091040d6 0xbcee0e8e
+ 0x3065f06e 0xfed5b966 0x5a304bfa 0xecaba5a4
+ 0x71142b74 0x44a849d0 0x7334c493 0xdb5ee797
+ 0xe537a453 0x849f4cf0 0x435923ac 0xad3a754d
+ 0xa78c3e5b 0xdb062ce7 0x874d85ad 0xc80e3955
+ 0x3db9ad97 0xbe5ee26c 0x4627c40b 0x095ffa45
+ 0xc2affd98 0x5f4d1325 0x7e4e1cd0 0xf87f1a1d
+ 0x5ee40ff9 0x87b4a4db 0x32d4d331 0xc75f8a6b
+ 0x79cdb281 0xf7b41e82 0x6e38397a 0x9af320c4
+ 0x57da9320 0x154f9f49 0x3451d8b8 0xe3520cd1
+ 0xd8df7d66 0x15d80b8a 0xfedf9cd0 0xa86675fc
+ 0x7fc8e941 0xf7f21238 0x8966e9a8 0x416da7bd
+ 0xc44d7d8f 0xecf21ce0 0x801b2813 0x16545fa6
+ 0x3c438b30 0x37200a5f 0xeb8ebb3b 0x6d90077b
+ 0x123c3d29 0xef11bccb 0x7b107fd9 0xa4fb179d
+ 0x7abc5dfb 0xe4817640 0xd3788477 0xd954d092
+ 0xa8b16c03 0x694941a7 0xf499fc7d 0x8d65681c
+ 0x8c6016b5 0xce3a995f 0x15ce39df 0x9bd26a97
+ 0xfa6c7a38 0xa66670e3 0x0932cac5 0x9a4ebbd3
+ 0x4c06bc72 0xb0dcb9c0 0x3598f7cd 0x7557e021
+ 0xba16f52e 0x32cd1c62 0x12cfc28d 0x544b3d77
+ 0xd780755e 0x340fea59 0xefb9b1ae 0xeada06ae
+ 0xaafbc431 0x275071ef 0xe8d19426 0x714a2ba3
+ 0x81a7c4a5 0xb5599e4c 0x9637445c 0x4af7df96
+ 0x5ffb2f87 0xc0aefa6a 0x30a00ede 0xf8ec4413
+ 0x2fb53e35 0x1084dd22 0xc04e8437 0x25197744
+ 0xb68a5330 0x1fd2f46b 0xda66de26 0xd0db8e5f
+ 0xb782db5a 0x34f4a30a 0x9b249d48 0xb0d081fb
+ 0xcc18d9bc 0xe7f0f327 0xd651dee6 0xfa7603b6
+ 0x3df72308 0xb6e0bbe3 0x0cea0072 0x2895be61
+ 0x30e976de 0x3201e40a 0x9e7421c4 0x7df47822
+ 0x82a04ba5 0xf9a16c26 0xd76b42ae 0x5b7f7455
+ 0xeda1add5 0x60189560 0x875db6fa 0x1315b3cc
+ 0x40c629c9 0xf5033d8b 0x10338d35 0x00f5e8c9
+ 0xc15acd41 0xe952cb8e 0xfbf03648 0xfab3a0c6
+ 0x3c23ac72 0x8206fe5e 0x831da221 0x67d3676e
+ 0x4a64ac61 0x98dc0ccd 0x68ffdd6a 0xa2a0edfe
+ 0x534d47a3 0xf79b6154 0x3d2bc073 0x50c2b839
+ 0x03932319 0x64342c82 0x92d92fd6 0x9a9ba8db
+ 0xefb42d33 0x28d07ff0 0x5db4fdfd 0x39225ab4
+ 0x37f24ea5 0xa82e9e1a 0x26c4bd1c 0xcb365ab6
+ 0x60553456 0x03efa3b9 0xd7b8d40b 0x4858269c
+ 0x0eef7011 0x19d7f85b 0x938e59bd 0x24f33de1
+ 0x2d466d05 0x3ac7c2b4 0xbb7af230 0x3ec5069c
+ 0x2abe2941 0xf5db8b3f 0x902f1251 0x9a6e0bb7
+ 0x1d2cc0cf 0xf65d6e88 0x03365f91 0x3a2ecb53
+ 0x4a59e1e9 0x0b252007 0xddd6c5b8 0x1c4d54a2
+ 0xc1edf67c 0xb066e206 0x6c8c9894 0xe8426c70
+ 0xc9f6ec2b 0x425c161a 0xc585a39a 0x064e4452
+ 0x5294148a 0x36c0a919 0xc84d33e9 0x1a5fbdb9
+ 0xfaec593d 0xd8d248f3 0x2fb18459 0xcbe7a0ce
+ 0xd70e9e1c 0x1afed776 0xecd2959a 0x7d8a5f35
+ 0xf1c70be6 0x2650b3c7 0xf0c46fa6 0xbf6bb842
+ 0xbf279282 0x4120728c 0x7f6b506a 0x87064748
+ 0x0bcbd2a6 0x2757fe8a 0x1db17cec 0x7517ef49
+ 0xbec921f1 0x804cb1d9 0xb9217e2e 0xb9ec624c
+ 0xcdc5e715 0x30bc1f23 0xaca1b3c0 0xf88bf420
+ 0xb5a8ac78 0xe93a9e75 0x0d15ac6c 0x12547703
+ 0x57a4e428 0xd1404e52 0x03f6e562 0x168cf122
+ 0x08da568d 0xdb96b84f 0x533c183c 0xa9dad7f0
+ 0xe2cd7e2b 0xc4162c32 0xbff6345e 0x69307759
+ 0x98b07a47 0x08f8219d 0x0d604427 0xc4305cac
+ 0x294162b6 0xa15a6c1c 0x04f692ad 0xb8da5cb7
+ 0x4839cc8a 0x91488ef3 0x08061887 0xebb839ba
+ 0x322ad7d6 0x490ac9ad 0x90ce1d35 0x83bf44d1
+ 0x1f988e2b 0x7acf6511 0xfc46e340 0xdb66656f
+ 0x9fc8938a 0xbe5afc17 0x7349bf91 0x1c36730c
+ 0x3b7f643f 0x06a42553 0x6142e212 0x8fb07289
+ 0xc9b53580 0xe927620d 0x0e966437 0x60a4867c
+ 0xc93e5e14 0xb5d54cac 0xd1c63103 0x30bbcbec
+ 0xbd22bce2 0xf48e5a20 0xab393f90 0x0a265db2
+ 0xe4805f5a 0x2d0941ba 0x8a877e27 0x141d94bd
+ 0x30ef8a0c 0xfd82b15a 0x36c3c125 0x402c1a1a
+ 0x0fa86d0e 0xa195b994 0x4c309653 0xbea4fdd4
+ 0xfad010e5 0xb7e3cb7e 0xd5bce9ec 0x0e366de0
+ 0xc6515a96 0x68ca6f82 0x73720af2 0x5d9a3be5
+ 0x16ea24de 0xeac200df 0x7ebb1e44 0x486bba64
+ 0xa8c68872 0x53008115 0x968633d8 0x7b9b000c
+ 0x0c1aff43 0xd83875a2 0xcc3e1339 0xf1cf9b3f
+ 0x5da5f6d7 0xfd5570be 0x649ee5c3 0x0ad7de54
+ 0xe4d4c568 0x04d8521d 0x322df607 0x5d0f20df
+ 0xf4a8d682 0xed3275eb 0xf8159013 0x3a7ee2d7
+ 0x706bb51e 0xac4fa1d1 0xf7245344 0xb5a352f5
+ 0xaf84a731 0x073beb18 0x05679002 0x414a0323
+ 0x9eb69396 0x9e57bbb4 0xf5765947 0xcf85bf53
+ 0x90cb7bff 0x9aca4c64 0xd87c65dd 0x717cb65a
+ 0x6598389e 0x75938c29 0x3a73f234 0x265cb77a
+ 0x9fdf49f2 0xf6c60084 0x175963d1 0x27f213af
+ 0x0d5a9f2d 0x22593c74 0xce596562 0xb41196c7
+ 0x707d6606 0x8d953238 0x61481d28 0x2fe1e9c1
+ 0x5dd2d437 0x65f8fa05 0x56732403 0xb989d4f7
+ 0x917ea769 0xd4bebdbc 0x13d39d92 0xfecf7388
+ 0x6f3597d2 0x76147a5d 0x01c51f65 0x0ad769e0
+ 0xd96c281d 0x9983cce8 0x4d2bde45 0x151ea741
+ 0x99d61b62 0x0d603ea8 0xfc85937d 0x427d7b10
+ 0xe8d15c97 0x13ef1e0b 0xf4f79fef 0x62b76eb7
+ 0x21d65b86 0x6a72263c 0x166b02b1 0x36b13710
+ 0x2ff6fbac 0x1b853cad 0xbdc93294 0x6f5f6b9d
+ 0x06ce7ded 0x49120f04 0xc9e09c7b 0x3d049a07
+ 0xb606d45b 0x12dcecb4 0xb50b3b8a 0x7c198d4d
+ 0xfa0f1618 0xac7968b2 0x33eb7dcb 0x07dee874
+ 0xcb4d9d96 0x66eeb30b 0xef1ebf3a 0x06c281b9
+ 0x44bfdd0b 0xbe4936c8 0xff238c39 0xc87beaf2
+ 0x7b3b032b 0x87e37014 0x09a4a1c5 0x2a60e1c8
+ 0x1bd67945 0xbec8a12e 0xf1837ea6 0x7a9a4aff
+ 0x7b0a9211 0x00e8551a 0x1f2b699d 0x9b38fdea
+ 0x43c58686 0x1d98737d 0x0f772a4d 0x7660c66c
+ 0x3bbda6b4 0x42df1fb1 0xc1c5aeec 0xe5f13157
+ 0x2926d26c 0x57ab1234 0x47626eb8 0x8b55b251
+ 0xf0a4dccd 0x6dc4e449 0x1573d97f 0x26f463c7
+ 0x9a87f877 0x19b07943 0xeafc72a2 0x9723ada4
+ 0xab30aacc 0x1d6df35c 0xd1c891ba 0xe93769c8
+ 0xa58ba86a 0x5d13eca7 0x29d0280e 0x1fb8c99e
+ 0x5caaff2c 0x7cbcbdc9 0x64d2cfe7 0x7586ca1b
+ 0xdb371ead 0xc5c037b8 0x80bf52bf 0x3d3c3ad2
+ 0x6b7e425c 0x113409d4 0xa5e1aa77 0x521317f1
+ 0xcc3b148e 0x7b99be8e 0x8362b991 0xc7bf1ee7
+ 0xdfbb5ddd 0x94edb425 0xf0ae4ea6 0x846a026b
+ 0xeb8befdc 0x54090284 0xdbb22f07 0x8aa40ce0
+ 0x23fe1e1c 0x47f383c6 0x3e7e8fce 0x0e533a25
+ 0x8a31b356 0x6dfc7274 0x2de64ecf 0x941161f9
+ 0x85e6296d 0x25d0f616 0x0a818f46 0x8ba2e331
+ 0x3193d742 0x4aad0883 0xa97e4d89 0x6c380aa3
+ 0x7cf9f824 0xf4b0880d 0x2105a500 0x4b21aa24
+ 0x85a37c7a 0x8b6e6ee0 0xc6907e75 0xd289dd04
+ 0x97859658 0x056e5df8 0xbc67be96 0xaf5b7d8d
+ 0x70426841 0xe8910781 0x3a2a84cc 0x029a8b16
+ 0x4a01f9fc 0x56fc8172 0xa406a272 0x86c6995e
+ 0x902a269c 0x3e2f46c8 0xdf628cad 0xe9c917ca
+ 0xb2fc0fcb 0x1433c09f 0x720db1ee 0x66372abc
+ 0x29e7b946 0xa8f8ae57 0x94a75fb4 0xc5b89188
+ 0x46aff2c6 0xcaef0590 0x5c3c8f11 0x1f89b174
+ 0x1536e302 0x456b8947 0xc7449e60 0xabbf6bbd
+ 0xd7dfa543 0x243a10c0 0x58f4ec8b 0x0bd3f346
+ 0x6a7f8d3d 0x9615e391 0x63810f52 0x4679abe7
+ 0x35060bdb 0x90518f32 0xef673aec 0x3b119149
+ 0xe61749bf 0x105aae24 0x134e5f31 0x7773bf1e
+ 0xa317a8d3 0x136a9ed5 0x18d9b8c5 0x2d9ef922
+ 0xc09d3a82 0x2fd65aec 0x3c9c867c 0xe13d79f4
+ 0xe8f10d6d 0x367416b9 0x08cad24c 0x634ded9c
+ 0xff5e5041 0xb95a0220 0x90941112 0xad6a6fae
+ 0xabbd6a68 0xda8df1bf 0x64ecab3e 0xad163a7a
+ 0x4bbf0be2 0x92dd3c4d 0x14e405c7 0x7259c058
+ 0xa925a2f9 0xbe6343c3 0xde477a54 0xbe622353
+ 0x68e87028 0xa0e7bef2 0x907c2d70 0x0717cb56
+ 0x60162a22 0x9279454f 0xb4bc4db0 0x1444a062
+ 0x46ff359c 0x7ef881b2 0x882bc1b5 0x5a5547f9
+ 0x9d288801 0xe5e9be86 0x8c22d3fe 0x2c9cfd0a
+ 0x1fad5fda 0x23ba1388 0xd0af08a0 0x4f218b5d
+ 0x372a023f 0x498a3301 0x37d89270 0xc7f3f2d0
+ 0x5bcd1b11 0x3cae2643 0xdb8a3acf 0x760b973d
+ 0xea3476ac 0x09795d63 0x3a926c84 0xf668f08f
+ 0x962aa19b 0x4a9d8ba5 0x852ec947 0xe742453a
+ 0x86436cda 0x12632bd6 0xffd300d7 0xce3e66c0
+ 0x1d8fbfa7 0x74dabeee 0x629376c8 0x8dde3458
+ 0xbe7f9e18 0x1eef9cec 0x7f026424 0x919e5361
+ 0x009daea3 0x66d9ac59 0xbfa09c85 0x86f78426
+ 0xd82a9ca9 0x94cec335 0xdbef6b65 0x0507c651
+ 0xbb34d330 0x17bc84e0 0xaee42b53 0xcb41b21a
+ 0x25b45399 0xea54d11c 0x57e7b13a 0xaec71577
+ 0x18fa957c 0xda47937a 0x7d0c72a6 0x2ce6856f
+ 0x5d513cd1 0x48560d4b 0xd0505c7e 0x75060791
+ 0x8ad85f16 0x8ee29517 0x029144f3 0xe811ce82
+ 0x49790987 0x890a38a8 0x4959350d 0x85120232
+ 0xc40d93f6 0x8419b3f7 0x3d1938d1 0xa0fb7571
+ 0xf2a22104 0xa8eb4259 0xe6b69491 0x6367059c
+ 0xc5f4d067 0xfbb99b36 0xe22a7fac 0x1aa67168
+ 0x4e352bcd 0xc02b9339 0x4dcbef0e 0xe72cb674
+ 0xe91e6e6a 0x6ded5223 0xe8520b54 0x842d4e80
+ 0x4caf72dd 0x40eeb737 0x7c213234 0xa169be4b
+ 0x6a88b02a 0xce540994 0x280cb749 0xa5c13190
+ 0x0067bae1 0x26254839 0xcab1fc69 0x630b961c
+ 0x8275487d 0xbb8b20f3 0x757de8f1 0xb652de6e
+ 0xfa845694 0x4aeb9f77 0xf477f13b 0x18f42a8c
+ 0xfd6a12f9 0xa97f9a78 0x8b56105c 0x765f4381
+ 0x1ac648d9 0xea0b5b90 0x526bf787 0xe975c883
+ 0x8cf8c115 0xa9d20628 0x3f663ddc 0x6e1bb3f6
+ 0xf3852873 0xb8296270 0x7e3c9e91 0x45e48c69
+ 0xb1a875b1 0xe4a210ed 0xe2552d56 0xa78fad94
+ 0x970ff726 0x95a4beea 0xf9d5505d 0xfc87ac3c
+ 0x179da815 0xee295504 0xecccdf4e 0xfe9786a2
+ 0x9536ae1a 0xc130fc4e 0x10e2738e 0x27aa298e
+ 0x96613a99 0xcd92fe53 0x8e7b1cb7 0xd708df30
+ 0xd45c95eb 0x34d09a74 0xa746f62d 0xbfcbceb3
+ 0x925da8da 0x0da0aa75 0xe44f0e36 0x06982962
+ 0xe5471959 0x56a37f36 0x7a5c58f5 0x82386903
+ 0xa7e18350 0x3c00ad76 0x33affdea 0xa179837a
+ 0xfcafe757 0xd0b14701 0x7f9ec58a 0x878407f0
+ 0x229afe49 0x2d6345bf 0xe3399a6f 0xf01376fe
+ 0x689f49eb 0x816b6543 0x4c6735cc 0xe596f327
+ 0xca2604df 0xf089bd37 0x2b554507 0xb830a463
+ 0x2fef8d6c 0x9b70f1dd 0xae54c418 0x899e40a5
+ 0x85ecfe99 0x8016eb0a 0xefd1150b 0x2e3b2e2b
+ 0x8d9a2ce2 0x94af20ef 0x96d16f0e 0xa1644c8f
+ 0x7181fca0 0x79eab0b8 0x10c0e6ff 0xfef780c8
+ 0x54202790 0x470e8daa 0x2e63a9b4 0xd3e91716
+ 0xd435d270 0xe63f7af3 0x2eb78830 0xf4c6f669
+ 0x27240ae4 0xe6206d76 0xae9639c5 0x9299d54b
+ 0xb8bcbf88 0xa2b90455 0xc94aeb91 0x5b23387a
+ 0x18434a0d 0xcd8562b4 0x787d88c1 0xa00161e5
+ 0xc5a526e2 0xa4ac9832 0x377cdd34 0x7bd3e6b5
+ 0x9b19c204 0x208d76d4 0xc22dba4d 0x7c72c839
+ 0x4aa16eba 0x1dfbcdfd 0x824f3395 0x560b6ffb
+ 0x9cdce848 0x925b6be9 0x37649256 0xe1e06b14
+ 0x34ba53b1 0xa81b7478 0x9ae2578a 0xab07c5ef
+ 0x496f97f1 0x40ba5c08 0xd34fb442 0xdbccf108
+ 0x24211f41 0x9a3c6829 0x1ea2c1c3 0xb3545a48
+ 0x967a5e54 0xaf506484 0x6cec3593 0xc1bc8d22
+ 0x35142a18 0x8352db87 0x18a9c31d 0x900c54e3
+ 0x0e07f4e7 0x8fa7248f 0x80c2af22 0x115c188d
+ 0x14d68800 0xcfac8e36 0x777cb6a5 0xc1f2879d
+ 0x23fc81b6 0x2c864c6c 0x0e8dfe68 0x451fd26a
+ 0x4b65b016 0xe3a5141f 0x8323b451 0x62e5cdba
+ 0xec14db6f 0xc8de546a 0xe29e8674 0x187681a4
+ 0x31d91dd6 0xbf21549f 0xb670f1f9 0x2accef94
+ 0xd9255c53 0x1ff2b607 0x69dcef61 0x5806864f
+ 0x736d774f 0x44701bb2 0x6007ce5f 0xcbcc4c13
+ 0xfb7ef6bb 0x6f2ea43d 0x791bad8d 0x6c0e4c02
+ 0x600853e7 0x95258757 0x4aaf3143 0x4ffbee3a
+ 0x166847a5 0x1b5b21e8 0x3d56cf37 0xc11e2fa8
+ 0x7df56f7d 0x4f193858 0x36da7870 0xe29ae1ab
+ 0x2571f278 0x7d81f452 0x37ed737d 0xe4d109d5
+ 0x8b0d7bf5 0xdd8fae7c 0x1691cb26 0x94bf321f
+ 0x8aad839c 0xafe85792 0x694eb2c8 0x8a256274
+ 0x48dd295a 0xd07e2d18 0x031b5e4c 0xe9059897
+ 0xf98cfd9a 0xe46dd735 0x1185fea1 0xa4123e79
+ 0x5f123825 0x54b6b92c 0x32cf6a3e 0x3ab5bb75
+ 0x18cb657c 0x0971a1bd 0x70aefd2b 0xfa48beae
+ 0xd6a57c5b 0x289ffd4f 0x9feb0a93 0x3e19add2
+ 0xe99862e3 0xf0db195a 0xa28af96f 0x9a22b6d1
+ 0x077800de 0x74687d2f 0x77bf648b 0xb0e6b32b
+ 0xfc91951c 0x0b30916f 0x6bb88661 0x7e99e24e
+ 0xb35ab07f 0xdcb43d79 0x578ff682 0x5d8e242b
+ 0xe5643628 0x3b84abc9 0xeac7cd6d 0xe811eb8b
+ 0xae728ed5 0x0235b55f 0xa0b6d2e5 0xca735341
+ 0x4bb6eed1 0x3a0336f5 0xdc365965 0xe159015d
+ 0x89e52c09 0xc3d9429e 0x4638e951 0xdfad21b8
+ 0x0650f1cb 0x61b2df08 0x0bca3a7b 0x58def8bf
+ 0xf9be3645 0x475c2308 0x4f3808f9 0x472a95d5
+ 0x9f557c1e 0xb6427b22 0xa5edbb0a 0x8a0787b1
+ 0xda40c48d 0x445e50ac 0x8c01527b 0x21dc6254
+ 0x14bfaee0 0xeca3a219 0x0e2dbdf6 0x6ab66c33
+ 0xbd20d715 0xb65e8e67 0xec888c3e 0x5023fbeb
+ 0xad4c82c4 0x5f793ba6 0x28d79a02 0x23948e5b
+ 0x6f1503e1 0x37604f55 0xa6bcdbd2 0x998bc834
+ 0x8f372c52 0xdfe4110f 0xad098b4d 0x3d49720e
+ 0xa229229e 0xc2c0cf38 0xbe32eafe 0xe992cae8
+ 0xe19c55ff 0xfb38fc31 0xcaf2c5be 0x3a61f1aa
+ 0xea316472 0x3973d416 0xd047814d 0x5f86de99
+ 0x09f5d09c 0x220c0773 0x93c04b91 0x99f3099f
+ 0x5fd0948c 0x8abc9565 0x70818172 0x7dab758a
+ 0x50415032 0x77bb8a97 0x527c0cfe 0xb9c3b837
+ 0x105822e9 0xe286154b 0x1c00f912 0xfe7825c8
+ 0x9b76bd3c 0x0af6a65b 0x23215707 0x8836d3c4
+ 0xf44ce91d 0x417b6212 0x8f28ec23 0x3f0f597f
+ 0x2caaa865 0xd7ff95c7 0x4d4d4458 0x732a75b7
+ 0x1d3031c4 0xf8ad5064 0xda73dc99 0x431864af
+ 0x38d7bbd5 0x332a2d0c 0x347e68ea 0xbfe2ecf2
+ 0x74f6ee17 0x7cdf983a 0xef7dd066 0x1262bdc0
+ 0xa7efbccd 0xf3ba76b8 0x3815f62f 0xa1fe8170
+ 0x52897deb 0x20f8dc2e 0x5a8953f4 0x8fcc182b
+ 0xf6d4dad0 0xfe7fa13a 0x1778ee2f 0x2f289b50
+ 0xd9f69db2 0x32d125b0 0xa3ca42a3 0x3075c1d2
+ 0x59e7b61c 0xa734845b 0xf183a080 0x9530fa32
+ 0x6c59a39e 0x420410e1 0x9f76df13 0xdda0a047
+ 0x0073a389 0xe55e57bf 0x926c3ba1 0xa9a94122
+ 0xa1283d02 0x74f1e874 0x332b8e81 0x812f3e9e
+ 0x81577778 0x30d86799 0xec4960ff 0xd446557a
+ 0x49f05905 0xb9fef70a 0x30d403dc 0x6a4498d4
+ 0xdc1a7e15 0x445bb9a5 0x1455ba4c 0x9d4a37a4
+ 0xeec57bb1 0x34ac00e0 0x7127c2f7 0x44b5a260
+ 0x9c71f1f8 0xada2be3d 0xe1cec205 0xc163f099
+ 0xe0dca849 0x86ab7f72 0x5c6f4c92 0x93b0eb07
+ 0x7ec203f2 0xcc399989 0x75bb2533 0x89ec7a1c
+ 0x118371b3 0x7497d553 0x03f2d03b 0x7e7b4d81
+ 0x478b1cb4 0xe4801e36 0x808d7527 0xbc1d3ea0
+ 0xb297b06f 0xa579d810 0xf07aea4f 0x9e6dd0ef
+ 0xad0240bb 0xfd5b94d1 0x0f8037fa 0x944d3fff
+ 0xc6fc7d3b 0x4c9761f3 0x68440387 0xc0496074
+ 0x32cd1609 0xd67b2de6 0x700adfc9 0x2d284f80
+ 0xcc5393b6 0x32d83e64 0x2ac02cc4 0xb759a6bd
+ 0x9d8a2f64 0x2ef1b8d8 0x0f574410 0x4cb81db6
+ 0x922af2e1 0x56231889 0xf4353d11 0x6d6e9050
+ 0x4523c317 0x229d9291 0xbc16016d 0xf1381dff
+ 0x84f6e1b7 0xc7378275 0x7045561c 0xd4736ef9
+ 0xb863b8bf 0x902bfe68 0xb0811fda 0x9df8d9b8
+ 0x6ad9c691 0x4cdf381d 0x68be4e7d 0xd03f2cec
+ 0x8166ecf6 0xdcf45f29 0xfbbc6dd0 0x791cf886
+ 0x3639c902 0x1f1dab00 0x1abb48ce 0x9f2f4d79
+ 0x992b2df2 0x44e8ae22 0x7fa777d4 0x62f1a754
+ 0x57448154 0x662948e3 0xe50c5f0f 0x83adfbc2
+ 0x669f3fd4 0xf4bf4a87 0x0a1b01ce 0xef6471b2
+ 0x49778a6e 0xe470e785 0x5fb3cb5a 0x9767dad7
+ 0x04c4f262 0x9cc1944a 0x8bf5062a 0xd316b454
+ 0xbed231df 0x9f9e1984 0x915c06ce 0xbfee9689
+ 0x6d1b7d27 0xeadc62e0 0x85fe6b06 0x97a92ce4
+ 0x879344a7 0x8ce19261 0x48508a42 0x7f63ec53
+ 0x05de4fea 0xef725c06 0x23c17065 0xa8c4ab97
+ 0x8e304029 0xf25c4857 0x3ddbaa04 0xfd325479
+ 0xd6eb3fd0 0x25f8ed38 0x67e70d61 0xe894d72a
+ 0x5fc7779a 0xa862b7e4 0x27a93aee 0xa3c8807f
+ 0x1dcd0622 0xb90b336c 0x7b89617c 0x300bea80
+ 0xbbfb1898 0xd61dee74 0x80ce1142 0x4829c4e9
+ 0xbe50282b 0x41a5ed8e 0x27150e7e 0x86f18198
+ 0xa9bf6e31 0xe4f36079 0xa5c241ab 0x61ab2326
+ 0xbf7be24b 0x4c87e8a8 0x170a4d05 0x05941c41
+ 0xd0ea7712 0x505b8ad5 0x33ab4e89 0x334ea7de
+ 0x32119057 0xfbaeb5e7 0xd00a75b6 0x8e467276
+ 0x8260a778 0xbf2d6a39 0x139ef440 0xa7b44a0b
+ 0xca0a2442 0xbfd7790e 0x353f6026 0xa418156a
+ 0xabc15fad 0x365ca72a 0xb9c5f379 0xeeb91216
+ 0xae8a7e67 0xff621bc6 0x5f6767b4 0x703e08f5
+ 0xa91b4d87 0xcbbeed4d 0x0f7aeb4f 0x7d7b88a8
+ 0x3144ff32 0xbbde4be4 0x1a9af3b1 0x218b80f4
+ 0x000342ef 0x0752f7e6 0x98ccb7bc 0x58fb806f
+ 0x32b3a302 0x67435abd 0x7462e773 0x3cbbb910
+ 0x391c6346 0x939e79b3 0x28cde352 0xbfa8866b
+ 0x8a4dba83 0x14dcb04c 0xf2f9f462 0x5fdf6d07
+ 0xf0a8de85 0x63046ef4 0xbc007be0 0xa5014d97
+ 0xb966e6e8 0x31308a90 0xd5fc5756 0xdd21483d
+ 0x4ab980b8 0x48b8708b 0xdcdb9363 0x9188fcc3
+ 0x790c58d6 0x2c1e2cc3 0xcc621f2a 0x4c36fbc2
+ 0x739f934e 0xf666cf77 0x5082421a 0xbe98a7d6
+ 0x722fb2d0 0xb8bd4af7 0x371c6eb4 0x13141930
+ 0x73320cd1 0x2085f28f 0x49dafcb8 0xe5627dce
+ 0xcf40e9f5 0x279fb8b1 0x61775564 0xf9751e18
+ 0xc9a50230 0x54aead9c 0xf295e9c1 0x5edfcc4a
+ 0x965eee7d 0xd4a0fb0f 0xbc1c32bc 0xd63bb4aa
+ 0x9f5e3cfd 0xf0f1f047 0x1a1bb313 0x762a6e08
+ 0xd1e112fc 0xd07737cc 0xeb85de60 0xa81adb27
+ 0xf56a8804 0x927e4a07 0xa03f4c55 0xa75c038c
+ 0x4aa72639 0x856b7a63 0x8e0b5b09 0x0b650c8e
+ 0xdce67a0a 0xb093aaa4 0xee9c495a 0x397c9b72
+ 0x00201e9a 0x0f3654d1 0x44303f3e 0xdc708b39
+ 0xab8bd5d9 0x1ed28dbb 0x1e91ab78 0x9357e946
+ 0x0591f394 0x3f174806 0x7e5363e2 0x10d73f05
+ 0xb18094b7 0x5c0cd26b 0xffa4c529 0x914ded6b
+ 0x247a68f8 0xec8a2133 0xe368fe87 0xf18c26fb
+ 0x8e442fff 0x39ea6ecc 0x9743be65 0xcac5d694
+ 0x24c4bcbe 0x2edee596 0xbd052bd1 0x70adaca0
+ 0x30c241a2 0x62b3f644 0x061f6b48 0x2fb91a6f
+ 0xc92df68d 0x73d41f19 0x3c18cae5 0xa04fbf36
+ 0x0ee5c645 0xee7973d9 0x7eee5dec 0xf11a3fc3
+ 0x06acd8c5 0x8ea5b050 0x652b3270 0x0f1e47fd
+ 0x82ba02c9 0xba7622be 0x9031734e 0x29e08f94
+ 0xe204f41c 0x95d57dde 0xc178791d 0xb4af2e68
+ 0xaf7e788a 0x17925d4b 0xdf417ecf 0x9193b6b0
+ 0x1ca32a5a 0x767d122a 0x0718eea6 0x1da6aaa8
+ 0x30497c08 0x32a6b264 0x7e0d781c 0x040010c3
+ 0xda2d6754 0xa3f9bb71 0x40ca8c26 0xea70e76a
+ 0xc90365e0 0xe6102f4b 0x728b93fa 0x8c9b288e
+ 0x9acf17a7 0xe1164350 0xf0103d84 0x3201abfd
+ 0x28e96191 0xa85a975f 0xfd89e4c5 0x33b397e3
+ 0x688bf58e 0x69d4bfc9 0x38d9d38d 0x395c61c4
+ 0x46b33a28 0x59d8b30d 0x5fcd406a 0x36dcf494
+ 0x3e6e1d45 0xdad47f30 0xe23d6c85 0x05c0f5da
+ 0xb2eb2523 0x617f5209 0xc4bd50ef 0x9a40d446
+ 0xf6706e43 0x8a41211b 0x141e5cdd 0xe5f4763d
+ 0xaadf5d59 0x34ecff99 0x4ebc45d5 0xdb4b1578
+ 0x33ec85da 0x67ee6b0f 0xc5789628 0xf67e6663
+ 0x1b19bab3 0x58620745 0x3e1929b3 0xa3ef35c1
+ 0x6233b038 0x928c9bde 0xfc1a74d9 0xe290e8e8
+ 0x2dc2b3ce 0x13533357 0x865397bf 0x551b56cb
+ 0xce7a7ef5 0xa3788428 0x7eeb6f73 0x7537f3ea
+ 0xfdd77af1 0x35343358 0xca248bee 0xf3726d8b
+ 0xbd027aff 0x43cbbd5d 0x4627b904 0xdcaed70a
+ 0x3f17a9df 0xbf2158fa 0x6953f389 0xb2bb4bcc
+ 0xfd56ff25 0x482cb729 0xa7c7d9cf 0x029c2e69
+ 0x4f3605c6 0x4f148ef9 0x29b6c0a4 0x2f556532
+ 0x6a298f9e 0x25945e4b 0x0a464d76 0x1fabd60a
+ 0x7f4c7d56 0x3b138677 0xa4d89ab4 0x5ccd85fb
+ 0x8c39f4e2 0xe77261b0 0xc3f3e6e5 0xdbf298ac
+ 0xe18fa767 0x89b19fed 0x65f32b00 0x042d50cf
+ 0x769900d8 0xf2c8dcdc 0xcddd6fa8 0x125af4db
+ 0xff808661 0xfd607112 0xcd9b7d51 0x65189811
+ 0x125c6011 0xec46f0b4 0xabbaa61a 0x35e5ab40
+ 0x0b66213e 0x8f0b1471 0x54a54816 0xfd70f393
+ 0x8efe0bcd 0x9727c46b 0x3f91f2b7 0x60d13926
+ 0xbf074154 0x5ff54e1b 0x9b7aace3 0x5507beb8
+ 0xb54dd8b3 0x4bd21318 0xc16e8f89 0x75aef7e7
+ 0x42520647 0x71cc3319 0xe9bcb41a 0xd0b016fd
+ 0x98fbdf6d 0xb124aff6 0x81b21f00 0xf5025987
+ 0x629e381b 0x3d971a74 0x2d20c3e7 0x1f990330
+ 0x9798ef1a 0xab4c06cd 0x9bcdbde3 0xf58187f1
+ 0x5349ee2d 0x9befe269 0x92512cb4 0x7a90a7fa
+ 0xc8bcb803 0x7213b43d 0xc54b82ec 0x57395c83
+ 0x80483b13 0x9d9e3384 0xfe9e19f5 0xbd75b346
+ 0x445ecce5 0xf549df86 0x43abdfdb 0x579c16ea
+ 0x2d838513 0xd8c030a2 0x0f26f21f 0x86dd65c7
+ 0xa56f5587 0xaae5e6eb 0xff6cae9a 0x2b6a5082
+ 0xe8cfea92 0x426e5b12 0xeb6b5e11 0xef748b88
+ 0xa7c52873 0x884b93ae 0xeec07e07 0x7f822b08
+ 0xc88c1c51 0x2fdfbfcb 0xde46bd4f 0xc0f72284
+ 0xe5afdd1e 0xc831d473 0xf3b02b32 0x610530cb
+ 0xdc57ebbe 0x0789b8b2 0xb1e004fb 0x98954e9f
+ 0x56e27413 0x840b2e16 0x53af5141 0x05cc609c
+ 0xa5652e91 0x982ae5ed 0x757c75a6 0xd31d253f
+ 0xbff9ff00 0xf7dedf5d 0xb7a15617 0x514aff52
+ 0x4c04184b 0x9e7a31e9 0x31485a41 0xead3407e
+ 0x50e1cecf 0x601f296f 0x85d903dd 0x54308603
+ 0x877a8cb0 0xa0f0949a 0x3cd9dc5e 0xa62b3ca1
+ 0x79db50f1 0xa49b5ffc 0x7afa975c 0x1007d484
+ 0x7700bc31 0x2b8431ed 0x8f1c2ccb 0xd26b396d
+ 0xe6a2abb7 0x64f78fa3 0xace8788a 0x8ba6f357
+ 0x01cb3b57 0x60ea304f 0x44bc28f1 0x2e16fa08
+ 0x4e9a2b65 0x89c2a14c 0xc521051c 0x2bee04b1
+ 0x10c0bb27 0x1ab75887 0xd819df0d 0x0b21368b
+ 0xe924da32 0x628af541 0x6d6eb08c 0x0a418b53
+ 0xac19e5cc 0xb2704fba 0x759df88a 0x76df6bdd
+ 0xb2ed3a34 0xf52af31a 0x44f6fb45 0x8885764b
+ 0x6397d609 0xa5803b66 0xbd3c3ee9 0xfd91fc62
+ 0xa92ad0e7 0x4075feea 0x1b73b846 0x1840a431
+ 0xc23ea4d5 0xf4be4c2e 0xe45fb99d 0xbc96c887
+ 0xa707bacf 0x40adabb9 0x2b1a8d08 0x05d5f8e2
+ 0x94578102 0xd032c431 0xe633de5d 0x9fa46925
+ 0xe4f78f93 0x09b5a508 0x68797087 0x75a4cf41
+ 0x68f34d2c 0xbc9d676a 0x939c00ec 0xdba51b90
+ 0x9bdab841 0x96c079a3 0x4c926224 0x046417a3
+ 0xa3090fe1 0xe2395840 0xff85d732 0x16eb0672
+ 0x1f2b4c36 0x10432695 0xea175319 0xac6b4fec
+ 0x22abeca3 0xaf42dfef 0xed67fef5 0x556b9185
+ 0x79318868 0x013082bf 0x882b4c74 0x17232518
+ 0x5ab0b8a9 0x565064e0 0x61bde558 0xc2f9f27d
+ 0x08d57cec 0xe02dd914 0x7e9a5972 0x856d0859
+ 0xe5488341 0xa0dd98de 0xa3c88a46 0x22c7bbce
+ 0x5924efc2 0xd15e2a36 0xfbabdd34 0x19e4838e
+ 0x1510c1f3 0x70f94986 0xde0505a6 0xe34df2cd
+ 0x39bc87ba 0xb0b6a36a 0x35bfd415 0x8b71c8e8
+ 0x074bf788 0xc7322d81 0xdfe4c9d3 0x14e4a913
+ 0x1d559696 0xc539cac3 0x91b6dd2b 0xc198e564
+ 0xc762ea2b 0x8b7f7f5e 0x3928468f 0xbf5e5a5a
+ 0xe5151ed4 0xf7abecf6 0x379c3bde 0x81ca5b6f
+ 0x6da09c5a 0x361d2f8e 0x7b38f326 0x0906a7ab
+ 0x1afafd4d 0x24fbcb5f 0xf02ed4a9 0xad2f8a2c
+ 0xccac956a 0x9a906a0d 0x55742842 0x08a7d782
+ 0x250e3581 0xd2328a15 0xcf943410 0x0c90aabb
+ 0x158fb11b 0xfb4c7ec3 0x51784a26 0x00b63b38
+ 0xfa9d20fe 0x6c3f5841 0x91204efe 0x70471fcb
+ 0xd7158a2c 0x09dc4685 0xefa8ef7e 0xd9e5c6b1
+ 0xfcc7c7f8 0x8f6fc8c1 0x4217f7a4 0x41e6d387
+ 0x26b12c91 0xe547e92f 0xe0a03d8d 0xe37b6003
+ 0xccd60f64 0x43a58a44 0x83ab597a 0x084b5c9a
+ 0x73f053c8 0x7590140d 0xad7d7fb7 0x9f1c8d60
+ 0x2f96ec1e 0xd73ceb36 0x18c9db5a 0xb144c70f
+ 0x745ca3d3 0x4b6a2615 0x09b7a09e 0x5c9e6f60
+ 0x60431f35 0x13fb02c4 0x6a6a2aee 0x0052d8e0
+ 0x3f120080 0xef5b3906 0xaf071511 0x981b4584
+ 0x7e21a2a6 0xe6fd2e96 0x67f460e0 0xc2f8f323
+ 0x22538f24 0x042f44e3 0xf271ed0e 0xa6fd7882
+ 0x0a469528 0xd1997489 0xa005e740 0x1b37ed35
+ 0xc546aa6b 0x5defa5e7 0x0df0e3b1 0x20de0573
+ 0xafdaf222 0x4efa11c4 0x129e4d10 0xa5b36477
+ 0x3cfd82fa 0x143f99ce 0x6277d132 0x41bc6588
+ 0xa96832b8 0x8e448a33 0x64d475b3 0x0d03dde7
+ 0xb9b7274a 0x7c43c3bd 0xcd7dea08 0x64f213a9
+ 0x4e5e3b17 0x59f0ccf5 0x149d6092 0xb3da7ff0
+ 0xe4bc1141 0xd6e3ad13 0x309b6d3f 0xa8bc2b2f
+ 0xfe8c49c8 0xfcb93795 0xa21e6218 0xfa789db6
+ 0xeda40d1b 0x8a571368 0xb20288ba 0x8f590d4b
+ 0xe2d350ee 0x55de37b7 0xa6b1545e 0xd34397bf
+ 0x2ca3cb72 0xc858a6e2 0xf18eb4f0 0x13162f7c
+ 0x3c73d583 0xf42f4f2d 0x2190c996 0x5842aeb4
+ 0x0fb8fac9 0x91835b21 0x768e94b3 0x0ee40fa7
+ 0x0bb4abf4 0x5d634b0a 0xf05614d1 0x8421bf96
+ 0xadc9bc41 0xc3c25730 0xead6783d 0x6b26a26e
+ 0xa5654315 0xddfdbd76 0x0e9efb4b 0x2523aeec
+ 0x0ded6345 0x9e745201 0xd74941e6 0xde1a8779
+ 0x8369587e 0xfe9e7ff8 0x7361da63 0x3b392b9d
+ 0x294fda91 0xd2bb0865 0x2584a967 0x2eaa63af
+ 0xf24d9e7e 0x02f0b739 0xe78adfad 0x803d1b65
+ 0x4fe08993 0xbbb8b6fd 0xee720db4 0xb9bc4da7
+ 0x05d068c8 0x3e76a5a6 0x7ff1a6ca 0x2370982e
+ 0xeea006ab 0x39482f79 0x9887af2c 0xdba4de83
+ 0x9ecd4cfc 0x6978eaaf 0x1c910836 0x90abaf2f
+ 0x66fbbb3b 0xdba1eb1b 0x7c5d8640 0x10e2b54a
+ 0xbc9bae3b 0x4ab513c1 0xc3916328 0x923f610d
+ 0x8a55ff24 0x3efba683 0x25f2c4be 0x58e5374c
+ 0xd307e907 0x48ea462a 0x2dd7509e 0x870a5dcf
+ 0x08012046 0x3cd12b1d 0x6a47b79b 0x4113492b
+ 0x652e973c 0x9249d11d 0xcd2703e1 0x2fbe5959
+ 0xbe07c47e 0x441a0496 0xe7a6c7e5 0xf7cbd2ac
+ 0x44fca640 0xb264be8a 0x87b3042a 0xd347d1fd
+ 0x8dbb5347 0x60a9b650 0xa5fa99b3 0x6745855a
+ 0xea6324e2 0x380882cc 0x7d220119 0x344e1982
+ 0x906ade50 0x24e90f8c 0x490d112f 0xf111aa2e
+ 0xb08f13b7 0x8e1d7590 0xe9370ed1 0x62eb39e0
+ 0x35927fb1 0x829a40cb 0x0806336a 0xbaa04062
+ 0x9939850a 0x0869ac12 0x54b03562 0xa4f5c614
+ 0x392c62cd 0x7c23d63c 0x85fd1195 0xb7ed5546
+ 0x686e1f4f 0x55edcc7f 0x3094818f 0x2537a964
+ 0x664d5c0a 0xe80e1cbf 0x7948cae1 0x23c64375
+ 0xd418e137 0x78c3642e 0xecc9da92 0x79aa46e8
+ 0x59be9660 0x88058e58 0xc3c31420 0x378a39d2
+ 0xad44e929 0xb3131130 0x11a55e4e 0xf34bec26
+ 0xdb1bdb5b 0x0e9c986c 0x21472aad 0xd10cb0ad
+ 0xcfa7f425 0x8cc73d4c 0x935ad802 0x8a8252a8
+ 0x4ef3c4af 0xa9ea8d4d 0x8b8d2327 0x49221fa4
+ 0xb7a9a150 0xe635f856 0x37df5260 0x8d47a600
+ 0x736ff5bc 0xfe702551 0x622bb56c 0xafdf67b9
+ 0x394d0c63 0x1895e424 0x788eedd0 0xb8e7f6f6
+ 0x57a690b6 0x7f37de59 0x5f4cf3e0 0x1211b1b4
+ 0x9fd82e02 0x5c21f2af 0xdc016937 0x5c3a60f6
+ 0xf7729837 0x77758003 0xc470bc58 0xed2622e4
+ 0x88ba5184 0x18418beb 0x75659944 0x790ee40c
+ 0xd7db7e2e 0xb263b2ed 0xae90b658 0xe31faa45
+ 0x084b7b2b 0xe2817433 0x5fb477b6 0x05b99337
+ 0x20897d5a 0xdd5349f3 0xb6de2ced 0x0ad02021
+ 0x667a11e2 0x45fa8d58 0x7d9f7b52 0x982be1bd
+ 0x80d9b10f 0x1311fdbe 0xfd0c3612 0x77d03036
+ 0x9fc16296 0x60e450a5 0x329af69a 0x2fcd48be
+ 0x9c61579a 0x398ee2e5 0x18d52ae0 0x2e6d52bb
+ 0x0b1d391e 0x17d677a3 0xa56308dd 0xca961ae8
+ 0xaa08b85d 0x230a894e 0xfd1bb53c 0x40f070c6
+ 0xe536f86d 0xace6b686 0xb2ee8045 0x3ca0ca1c
+ 0xdc14297a 0x016e04bd 0xd298babf 0x1775685c
+ 0x25eeee81 0xeabf3996 0xdbac64c0 0xb644a8b1
+ 0x1d034410 0xee2f26f5 0x646f8804 0x0a219178
+ 0x88b774f5 0xb7757133 0x3ed44b66 0xbafb3535
+ 0x7f28dad2 0xd9be6e16 0xc1ee44aa 0x6473e8c3
+ 0xce6a8d51 0x58996952 0x74d779f5 0x7a332ec1
+ 0x93b1ae48 0x072f4696 0x91a59962 0xd1b4650d
+ 0xdf7bc203 0x5a1e01e1 0x0cc1c256 0x5f038178
+ 0x316dfbd6 0x6b6066c8 0x88d3c99d 0xf4593234
+ 0x7744e3e1 0xb986b226 0x122c5c78 0x98c304b6
+ 0x8d8e5248 0x258ad65d 0x887d2b33 0xddbcf246
+ 0x1079b709 0x69e5336c 0xaebbc436 0x021f40cd
+ 0x1c5c888f 0xadf4031e 0x773c6a1f 0xca6a4b54
+ 0x678a48b0 0xa83766e2 0xb51fc797 0x9378d2ff
+ 0x24617e89 0x63b6f24b 0xdff10c7e 0xd7899313
+ 0xa117de13 0x9ce9fe62 0x93568bd0 0x79525643
+ 0xe73d74ca 0x6fa05775 0x16532ef4 0xf158297c
+ 0x43d5b180 0xb3713768 0x42f5c74c 0x360674db
+ 0xd503b365 0x85f2e190 0xe02701bd 0xc4f72047
+ 0x9f0e8c3b 0xcb74c0d9 0x26a763f3 0xf052587f
+ 0x1e6382a6 0x98957c55 0xf84848a6 0xc899e8a1
+ 0x8baf0ead 0x04efc2de 0xfe51e034 0x31838b1b
+ 0xfc488265 0x54c21df4 0x3a1a09df 0xc3197a60
+ 0xf82505eb 0x01b09802 0xde6c5986 0xfa64e8e7
+ 0xd46b602b 0xd4b8abae 0xfd712f8c 0x374a2d31
+ 0x10bdfd5d 0x8b2c581c 0x11b999ce 0x93cb6b25
+ 0x03f83c15 0x5e2ca149 0x3cf835ac 0x8952786d
+ 0xde9aa5f2 0xc64c816f 0xcd56d134 0x6341ba5d
+ 0x48f8b46d 0xa6465fc8 0xf17c3199 0xf8945500
+ 0x52591640 0x126a5e9b 0xe4ef95ce 0x092ce906
+ 0x60feea4d 0x3ed8d81b 0xe13b4585 0x3699ea3f
+ 0x3c99d800 0xfb45a4c6 0x80b9af7b 0xdc1a8f13
+ 0x42793d11 0xf5b680b5 0x17443c44 0x339178cf
+ 0xe9122d87 0x60c79f06 0x2516b5c1 0x5225d594
+ 0xeb2dcf80 0xcfe02eda 0x7719eab8 0xf4beaf16
+ 0xce7d36ad 0x49a95435 0xacee9deb 0xc79cd246
+ 0x8ed659c5 0x66894b11 0xaedd26b6 0x9ce7d941
+ 0x294b5830 0x105962ad 0xeb5b34e6 0x31917645
+ 0x122c34fa 0xc7c82bd1 0x6ee4ea9a 0xe2fe7f27
+ 0xb1fd4c3d 0x702e9bff 0x7788ddba 0xbd3d942a
+ 0x75159d12 0x6aaec1ca 0xc3b4abcd 0x37a69572
+ 0x1fce87c2 0x01fbc543 0xacdd6775 0x2c7890d1
+ 0xbc1563c1 0x413dd754 0x5b7970d0 0xfef5b1ca
+ 0x8079af11 0xd551824a 0x5409896f 0x54e0be68
+ 0x8bcd30ff 0xc8375f42 0x30c06a2f 0x779c737d
+ 0x32d3e66b 0x7bd05d0f 0xb9c67b23 0xf273695e
+ 0x13528262 0xe4a790e9 0x0805aaea 0x3907f7c9
+ 0xd7abc54a 0xa4cc51a4 0xf49493f0 0x472aa285
+ 0x4dbed2c4 0x4864edaf 0xa46700a8 0xd7542f0c
+ 0x7c0ae286 0x951dd824 0x3c73e333 0x52eb49b3
+ 0x70516de8 0x7efae010 0xfe0bb650 0x786eb317
+ 0x43fb3ab7 0x4c86f7b0 0xab0c578a 0x59787f35
+ 0x719e2575 0xe5c919b4 0x26076c48 0xf4c5cee0
+ 0xa832e1c0 0xe0e719e9 0xeb978049 0xfde5093b
+ 0xe1c5a86f 0xc0ca654b 0x07140b4e 0xcee94a0c
+ 0x684f8c9c 0x0dc722ef 0x3f81b654 0x24f6b59e
+ 0xc9366802 0x07317ae5 0xb07bc322 0xa68d61a8
+ 0xfba88f10 0xdb077c88 0x2e2d4cae 0xf950f615
+ 0x0eb4b1d4 0xcc43df94 0x7f76068d 0x9998b11a
+ 0xd8c4c734 0x2444116b 0x6f387abf 0x402ba3a7
+ 0xb343b091 0xbf1ed457 0x0325a66e 0xac685f81
+ 0x3b13da49 0x71bfeadc 0xb706c3cf 0xc18367a7
+ 0x74e05a7b 0xf15ce88f 0xb7effab8 0x8e79599b
+ 0x758e0fd3 0xec60aff7 0xa36b3584 0x978555f1
+ 0xf03e26ce 0x05b7f39f 0x0f44d1e7 0xdb301d27
+ 0x2734c001 0x1ba4bb02 0xbed0c57b 0xbbb082d7
+ 0xa0f5c163 0x7b081aff 0x8f6020f0 0xb2363b33
+ 0x50fba5d4 0x8f862718 0xcfd4080e 0x31881dec
+ 0xcea35f4d 0x0ce550bc 0x968bcd16 0x701e96b4
+ 0x70104a77 0xd1381316 0xfa0b6bf6 0xd0800a1f
+ 0x30dd27e3 0x53396989 0x58066430 0x6fe20758
+ 0xe4776597 0x85bc8231 0x6f013aa1 0x8b0f1a6c
+ 0x1d41e906 0xd476acb1 0x1f50f428 0x61ebc0b6
+ 0x78c6389b 0xc70b922e 0x4d4c6fc5 0x97931134
+ 0x9d157c3c 0x053d63fa 0x4ee4dbe3 0x351ccb06
+ 0xdabfd086 0x6759fab0 0x277549b8 0x7a265b93
+ 0x35d1a141 0x972395a4 0xffd773c2 0x9ba52eb4
+ 0x41574c66 0xd4195554 0x49ccaa22 0xfe228bd6
+ 0x6977e1af 0x100a9948 0xb6c9667a 0x276c9a27
+ 0x169ba199 0x395986bc 0xa7079788 0x40b6deb8
+ 0xe74c106a 0x620f202d 0x32b4ee73 0xe7916e7a
+ 0xc949eba9 0xbf56f13f 0xa76139d6 0xfdca38ac
+ 0x7a295c2f 0xebdb2f5f 0x452694f2 0x6183f044
+ 0x0f29f26c 0x41760fa1 0xbf1fd689 0xd3055c3b
+ 0x1edb2239 0x5e9aa007 0x193c6ca9 0xa5f75684
+ 0x281732f2 0x99308898 0x78c4f631 0x6673d2bf
+ 0x62b8251d 0x4a466036 0x9641449d 0x138ce807
+ 0x3d637a7f 0x7d09bdf2 0x433bad7c 0x71bad217
+ 0xfb587029 0xa9a436f5 0x0e24623e 0x0aa852a8
+ 0xe86564a8 0xcdb686e4 0x65c48b10 0x2973caa6
+ 0x62d4e121 0x4b0835ae 0xa17bd769 0xac4a2db1
+ 0xf185166c 0x50f2fdfc 0xc39f14a0 0x5ef9dace
+ 0x0e70ecb6 0xfa577352 0xf944271a 0x4219017f
+ 0x4023cd16 0xcb999031 0x3435d9a3 0x376a38d8
+ 0xf9c5020b 0xf607d1b3 0x20899f9c 0xd4a0c8ba
+ 0xbb8afd18 0x4171935c 0xd949dd4c 0x2e33f6fb
+ 0x02af555a 0x0c2cbed6 0xba680cc6 0x07f0e58a
+ 0x88750bfa 0xdad6ce37 0x90e0e1be 0xfde50439
+ 0x714c6da7 0x52d79397 0x73f2dd50 0x0ec2df57
+ 0x38f609ac 0x6978ea5f 0x2b4f2a8e 0x977c5d83
+ 0x40f4581e 0x9c862f00 0x0ec9124f 0xcec0f275
+ 0x0830a2bc 0x1e620c5e 0x1c99889d 0x88fa02b2
+ 0x12cdc5c6 0xd1308d75 0x68c1c312 0x4dfee754
+ 0x8c7637a4 0xacd042fd 0xf9fa1e7c 0xa3fe1a74
+ 0xbabca0bd 0xf2c4f9cf 0xedb898d7 0xbf68ed2a
+ 0x88f88f66 0xba7eb154 0x8b657afb 0x8cdefdac
+ 0xa2becf86 0xcdcbe0d7 0x9481c98b 0xb194eca7
+ 0x2a0a02d4 0xfb00d895 0xcfae192c 0x304180f0
+ 0xa82bcede 0x3f9407eb 0x6f616505 0xf2679357
+ 0xc74ff05e 0xa42d33b6 0x6d131a74 0x46837c8f
+ 0x618d8b8e 0xae3fdf80 0x5ac56792 0xe8204095
+ 0x7fe678de 0x0aabe905 0xe23966fb 0xdfc3ae2f
+ 0xbfba369d 0xd362d0ad 0xe4d00bd1 0x36468346
+ 0x142ed1df 0xc97cad2c 0xe5c1035d 0xf6c78877
+ 0xe00295da 0x3be8b0dc 0xb59cef1a 0xe8ed05c6
+ 0x514ea1ef 0xf7633df2 0xb7e10bca 0x44cc343e
+ 0xdb5ebaed 0xe10b3589 0x60fd04b2 0xfacbfe1e
+ 0x93a1e9b8 0xee694238 0xd693b0b3 0x2812a260
+ 0x08db3159 0x59ca9d4b 0x4153cc57 0xf0ecf932
+ 0x438d4d1a 0x52c232d7 0xdf6d7a95 0x5b6f5092
+ 0x81e98659 0x8f9a196b 0x99acb238 0x19f97546
+ 0xba51ca3c 0x6c65e249 0xf45c7ad8 0x05bb02f7
+ 0x3ef3a052 0x61ea6df3 0x3d28d168 0x085c370f
+ 0xc2da1e98 0x7808a8c7 0x25be8a1b 0x89aaaf9c
+ 0xb66b1fa7 0x3f734eef 0xa845dc71 0xf66dc75e
+ 0x8a3fd539 0x7b0edfcb 0x93a439f3 0x835fd4cd
+ 0xef222958 0x476a8df5 0x41622b4d 0x8bf6f823
+ 0xd2c72644 0xb28c401a 0x2e56d5ef 0xb7762140
+ 0x6640e607 0x825f8ab6 0xeb42e497 0x8c92adee
+ 0xf680d2a1 0xc2f96614 0x014f5191 0x47becd6b
+ 0xe2d06126 0xd5e04451 0xa03771d6 0x459e86bf
+ 0x72d63346 0x908e8298 0xebc918c1 0x6deecf70
+ 0x8bc4f332 0x79a31a01 0x2114b2df 0x0180e3e3
+ 0xe2c91e71 0x0811ee5f 0x2c016723 0x069618e4
+ 0xb3b08ed9 0x1d9fa7bc 0x657733f2 0x86e610f3
+ 0x2621f0b7 0xd9f6651b 0xbefc2f7d 0x76a0b063
+ 0x604856fd 0x94a4ec8f 0xd7472d38 0x64b07478
+ 0xa4b4d499 0x43235f22 0x5319c88f 0x911e6372
+ 0x89ff9bf8 0x54455299 0x7b3e4e02 0x2335f31d
+ 0xf10efd89 0x652e4e5e 0x8a9325c3 0x4064cb40
+ 0x59ea7010 0x97fbfdcc 0x7836d7cc 0x88d05455
+ 0xf6a719e0 0xe6841411 0xd54f36de 0x2cb4c908
+ 0xbf87b0f0 0x6b1bfb7f 0x4dd2f56d 0x699aa41f
+ 0xb330eb1a 0xe1f021f6 0x65be482a 0xd48dc3cf
+ 0xedc98989 0xc38a4452 0xc4d0144a 0x812fab34
+ 0xbf112bd0 0xc9d10e16 0x6600a506 0x87955675
+ 0xbf65cf7e 0xd0d0e097 0x789c3540 0x1b6c3b27
+ 0xa17f9e2a 0x0d47f6c5 0x08ba8430 0x0ea5ab50
+ 0xe6875bff 0x745f6e88 0xe91a037b 0x9da767c1
+ 0x4673b150 0xbe14d919 0x3164e3d0 0xab5d0c2c
+ 0x33a0c5c8 0x67436862 0x0f043a50 0xb48a4fdf
+ 0xf2bebb0f 0xfc4df25a 0xd31c6354 0x21b41071
+ 0x2f29814c 0x2eb38275 0x7d7b4493 0x3235611e
+ 0x65e3106e 0x4fbcf4c7 0xe131e9d3 0x44b7028c
+ 0xf424c38a 0x709a1171 0x0bf1900f 0x5228b316
+ 0xda000118 0x61d8b278 0x0f4df4b4 0xdf948e72
+ 0x289dbff5 0xef421693 0x0e9b89cf 0x809db1a4
+ 0xde5468fd 0x937b068d 0xfd94e40f 0x397379be
+ 0x9d41a041 0xc01b0889 0xd4fcd1e8 0x0456e57f
+ 0xe91261fe 0x32ba801b 0x7edc2183 0xde70ea6b
+ 0x3a81dd35 0x4641b2c0 0x016e7025 0x1c164cab
+ 0x8430aace 0xa14e3de9 0xbeedfaf4 0xd5416157
+ 0x89212bc3 0x8f517277 0x64dc0c28 0x051c353c
+ 0x052f38fd 0xb4b9c162 0x087db1bf 0x384e2051
+ 0x8012f360 0x31a94aeb 0xfdc99124 0x3cd37d7c
+ 0x34067dc0 0xd4a35bfc 0x1fe16dde 0xd1f99248
+ 0x5a9cec00 0x25a73f12 0x861daf34 0x956456b0
+ 0xf042d8df 0x0b23f39c 0xf3dcf643 0x9ba5ce10
+ 0xbac25abc 0xb8c56204 0x10db5a6e 0x8de89772
+ 0x1e968309 0x4a478676 0x119afb50 0x988930b9
+ 0x6119d759 0x51788bfc 0x1d61e721 0x3d480f67
+ 0x66075802 0x45eb1829 0x118b4be5 0x7efeea7c
+ 0xba49b891 0x4dd11852 0xf71b4788 0x99c2f05e
+ 0xbd28303e 0x5ee62804 0x1b072acc 0x2d017ce9
+ 0xc33294a8 0x57312d2c 0xfd67b2b0 0xbb18b0bf
+ 0x2ec80198 0x26175f00 0x35255b65 0x516f5a38
+ 0x0890895a 0xd965ce68 0xbd651309 0xf4eb8906
+ 0x7e07e61d 0x7e9ef0f9 0x42865474 0xfeb2a58a
+ 0xd7c2f2c5 0x1641fd75 0xa24be73d 0xca6e52f5
+ 0x40cac5d6 0x24fee627 0xe56c185d 0x29cfe810
+ 0x871b030f 0x3b139120 0x19f07175 0x230b1346
+ 0x46d300da 0x04d6348a 0x9edc107e 0xeefed616
+ 0x673a9e51 0x2daa84b6 0xa19fcd37 0xdecc2c69
+ 0x3a683f29 0x17770c30 0xb5395aca 0xf8a977ee
+ 0xfa920726 0x7ccd7850 0xc259807c 0x46f03a5e
+ 0xb5049f0a 0x09a23cad 0x96208471 0xac73f67c
+ 0x91555dac 0x2eda61f6 0x11997b88 0xf82227f5
+ 0x333f3844 0xbbe6b077 0x9fa39297 0xa9731383
+ 0x3a6e781f 0xc0d3f568 0xf97d2c47 0x84831be6
+ 0xc4b64556 0xf9a8de4f 0x19eb50d8 0x72e5a15e
+ 0x054a8fd2 0xc1c6345e 0xc0f7b580 0x9704a4a4
+ 0xc4226ac9 0xc4ea548e 0xd513e3f5 0xd6af08f6
+ 0x831ed495 0x01e6c528 0x1a54b048 0x96dd6e66
+ 0x47988fff 0x188566a1 0x8e1313e1 0x5a7f71da
+ 0xd3967f1d 0x7690d3b6 0x2f8f2fb0 0x6f6251d2
+ 0x4c8aad64 0x02e2fa38 0x85287186 0x14a660ac
+ 0x76d76c09 0x1cdd99e0 0x9469a4c1 0x2e627afd
+ 0xb3c2e2ee 0x96ccf8e9 0x71d2baca 0xbc6e3480
+ 0xf2aac857 0x937f744b 0x0aef9370 0x29ab7ff8
+ 0x2d7df775 0x89a4880e 0x40b33115 0x1681969b
+ 0x38f87c90 0x58d99e75 0xe0bdcf8d 0x0748a43b
+ 0x815cc6fd 0xab02e1fb 0xa556d9c4 0x28045ce9
+ 0x92cfd9e4 0x53c48e36 0x10e2102b 0x14bdbdad
+ 0x072e7bfa 0x05f11cb6 0x647faaed 0x817802b7
+ 0x37514080 0x34e1952c 0x2f97aa78 0x67e5480d
+ 0x41c23454 0xb674bf64 0xf1059ebd 0x05bf0d65
+ 0x8cea89fe 0xe4c80026 0x19c6c2ce 0xc7ba0a80
+ 0x72361b09 0x40442dc7 0x0ea61783 0x0ae238b2
+ 0xfd189442 0xc777a400 0x407c0ba0 0x0068c8f4
+ 0xbdc3758c 0xccd5a384 0x78c17a8a 0xd9cace15
+ 0x0b0cc384 0x4def636a 0xc9ac6e70 0x0b47f099
+ 0xec8e3fd6 0x56de8792 0x613589e8 0x3625caae
+ 0x54c9ba96 0x61af1ee3 0x22c13793 0x2bb28eb7
+ 0xda0bf41c 0x37818fdf 0x66d06085 0x6ed9a2ea
+ 0xbd2f6197 0xe019fef9 0x58b35249 0xf7c471d2
+ 0xe08ee8c3 0xc0e4f4f8 0x2222e0bf 0x939049a3
+ 0x0f81527c 0x6e9d9062 0xb98e6ab9 0xe131178f
+ 0x9df0684a 0xfe4b3755 0xe29cc274 0xebbb906d
+ 0x5c1ff361 0xf6f785ac 0x925c1ffe 0xbe66b7e7
+ 0x341ce7cf 0x86b9e13b 0x3cde9717 0x528413e9
+ 0x47017637 0x8fbdb425 0x75bade38 0xaaca2a42
+ 0xc2cc87fd 0x341d3b6f 0x810374f7 0x539d08ca
+ 0x370a9899 0x13c63028 0xf6121e3a 0x1b6b6379
+ 0xe54543e7 0xd6c28f9c 0x92cad6e7 0x0c7805df
+ 0xa74ec04c 0x0220c53e 0x02bf9983 0x67b30801
+ 0xcfac9bdb 0x30ad34b1 0x623e6398 0xf72dff83
+ 0x6d6fed19 0xf62750ba 0x3238cd67 0x520b85f3
+ 0x814273a7 0x62249749 0x805a6f0f 0xe38b536d
+ 0x41e5a937 0xa93cf20e 0xa751645b 0x8b3e9866
+ 0x30967b99 0x3601f932 0xe3ff9f11 0xc4f80f52
+ 0x79431f0a 0x6231aac1 0xc62affa6 0x460653a1
+ 0x76e31119 0x06034ef6 0x1c69c3ee 0x93d7c70b
+ 0x72090aa9 0xc6e716b4 0x694be9b7 0xe2824b39
+ 0x669ac02d 0x443fbcab 0x1401440c 0x9e39be06
+ 0xf0e38a3a 0x01e81eb2 0x2f04f9fc 0xf8b9e3cb
+ 0x997f336e 0x276f6a76 0x4ad5de0b 0x4f1d43c9
+ 0xa0de062b 0xbedbcc1e 0x490e9ef0 0x3b9c1a9b
+ 0x1df97641 0x90a7dece 0x54b793c3 0x0ace3e2c
+ 0x06858b88 0x9474b6ef 0xbbc9955d 0xd882fc18
+ 0xb2c19d95 0xa2979c3b 0x2b87a2a0 0x25ab6e6b
+ 0x9744f6df 0x8a58cd8c 0x299a4009 0xaf51abcd
+ 0xf568b3ae 0x5ef83c60 0x491ed983 0xd3b384bf
+ 0xfc42e31f 0x908aaedd 0xaaea2da9 0x62f5607a
+ 0x3925938c 0x69432bc0 0xb94c3fd1 0xfa6e119c
+ 0xf004de98 0xf26dc0f6 0x58ffc4ca 0x1e215ba3
+ 0x77f52343 0xd9930eb4 0x84ff5f85 0xe357c135
+ 0x7ca48937 0x45acab8b 0xeb8cb3a7 0x79697bd9
+ 0x7aa4e063 0xc275dd65 0x9fce5cb8 0xfdea246f
+ 0x8bf8ca24 0x8b61b9c4 0x6a000d59 0x383d33f7
+ 0x89727da8 0xb6359382 0xf22d9f92 0xba35a48d
+ 0xe8b29b52 0xee2ceb3e 0xb2fc82e2 0x8f343501
+ 0x86312bd0 0xad483690 0x751629f5 0xb67a2e3c
+ 0xd076ad22 0xc01b43d7 0x2f4f9e6a 0x08b72eb6
+ 0x8db81d53 0x4e14b531 0x058c3ab5 0x81b3fbbd
+ 0x334ebfc6 0xd0c30788 0x9efef6c7 0x9d468836
+ 0xcf54f32f 0x18100d0f 0x75d013a9 0x872ca0a6
+ 0x48b656df 0x856d0f88 0x726d5762 0xb1b2dc0d
+ 0x49c7039f 0x2b9a468c 0x37f2cda8 0x62d964f0
+ 0xc50299b2 0xbe5f6cac 0x67899dfc 0x96ee110f
+ 0x7a00c5b8 0x9e9cdfcd 0x0b713ae1 0x06835e3c
+ 0xd243476d 0x5b140c30 0x65d5bdaa 0xd6bb4f4a
+ 0x1fde9ee1 0x12fd8800 0xd7a7c764 0x0fcca914
+ 0x8bd85200 0x40957099 0xe27b21a7 0x46a7fd6b
+ 0x0c16e600 0x4385aeee 0x157ada11 0xa750f2ae
+ 0xcb37c17a 0x1246d3d1 0x0b8cf308 0xa4a006c6
+ 0xa8649968 0x1e07eaad 0xe257f62b 0x966e3ab6
+ 0x424bd346 0x9a3b57b6 0xc5a443e4 0xb839b41f
+ 0x5ff5721d 0x78844fe7 0x210ef7ef 0x408c4278
+ 0x1892d6a9 0x9c3f0954 0x8d607ffc 0xc4cf44d7
+ 0xe1b650c5 0x4d417fb0 0x90d99753 0xf2fa12c1
+ 0x40a80089 0xd8afda76 0x90885dd2 0x1ad599e6
+ 0x828bf177 0x9969fafe 0x34232f6d 0x815828c9
+ 0xe851cd4f 0x22d909c5 0xd8b4ed0f 0x388ce97d
+ 0x651d147b 0x53d51595 0x09dce7cf 0x04a62df5
+ 0x10eb3d91 0x634ab2f7 0x707583c8 0x0f1ce97c
+ 0x61135a7f 0x14255857 0x17bcef54 0x24591002
+ 0x26b42928 0x5bdfcd75 0x04fafa75 0x0b77e81f
+ 0x3d149568 0x40074834 0xc9ed3122 0xa00483d1
+ 0xd1094f89 0xfc7e9697 0xbdc02fd6 0x5c0dd406
+ 0x55b3af34 0x147221f4 0x6a4e4493 0x70b27ba9
+ 0xa839c20a 0xb4ca83c6 0x6976e395 0x53823387
+ 0x7e7fa8dd 0x62f3eecb 0xe87a5081 0x2d2e5da9
+ 0x2dc917a1 0xa840aa15 0x3ae4b7de 0x818020d9
+ 0xe27c54d1 0x863b4ea7 0x3d770e0c 0xc913d78b
+ 0x22b6ce26 0xa38d471d 0xd86dfbb0 0x43c94bd8
+ 0xbb4e34a4 0x737265fb 0x68698195 0x89ec336f
+ 0x61e94b6f 0x01661a18 0x3378d7af 0x2abdd82b
+ 0xbc68f021 0x010136bc 0x54be683d 0x9600e0f0
+ 0x2710a3e4 0x1fc8650a 0xffc41bfc 0x764776e4
+ 0xdef736af 0x80a5b3e0 0x6ba97e54 0xdb90b4cf
+ 0x33ca5c3a 0x7dffb784 0x82c7bff6 0xb5c67d89
+ 0x8b39d097 0x87b0760a 0xe75b7bc8 0x67a40fdc
+ 0x2e77c957 0x8e9e397e 0x8c7b8e80 0x8bd64f05
+ 0xfc65f423 0x1ee3b99a 0x13d3c9bf 0xb37869d0
+ 0x385dda4e 0x03eb3c6a 0xdf1d4a3b 0x0944847f
+ 0xdb5d82be 0x6d8954c7 0x8fc3be6e 0x733e2ddf
+ 0x561f1d46 0xebf0b439 0x9d1583dc 0x65406edc
+ 0xa981414b 0xc57e522e 0xc960f260 0x6b23dc83
+ 0x710d10b2 0xab5f0fb0 0x2d724302 0x03acc581
+ 0xb7a06490 0xf3e2489e 0xef949571 0xcd054246
+ 0x094e6a1f 0x6ed5f8c1 0x7db5c90e 0x2d52f22b
+ 0xa0843e2d 0x4c0645df 0xe30eb8b6 0x10701a24
+ 0x8adb03e2 0x98d68158 0xc838134b 0x631f2ac7
+ 0x6e181502 0x0ebe0e06 0x39baa3e7 0x20d71f40
+ 0x212b2283 0x7387444f 0xb6f617a5 0x17b0015e
+ 0x390110fc 0x76f888ae 0x94399a20 0x14a05962
+ 0x59a68ad8 0x4dec4aa2 0xfed32466 0xac0f4040
+ 0xaa67f018 0xabb1afc0 0x96017ce4 0x55c61e4e
+ 0xf549b0d4 0x050889f5 0x4d7d29c6 0xa65e7c08
+ 0x87cda967 0x8fc571c4 0xac89bcb7 0x84e41f05
+ 0x2316e3e4 0xd11c78e0 0xd7519fc5 0x311ae321
+ 0x9443b018 0xd2d850b5 0x9df96b70 0x48b39b10
+ 0x17afbb5a 0x81a8970e 0xaca67baa 0x76a0b500
+ 0x0b9886f2 0x14e5edba 0x5193071e 0x266148b2
+ 0x4a91857b 0x97d18119 0xe095541a 0x40f027a4
+ 0x42a63a25 0xd47b0a19 0x537ebca4 0x953aac61
+ 0xb601a00b 0x93f621bf 0x71ec4f8a 0x9f2a46e5
+ 0x11ad282d 0xc2824e65 0x69bd7aab 0xc75c3965
+ 0x2d760621 0x66d29d8c 0x669536b3 0x95524faa
+ 0x7bbfc249 0xc459d1b6 0xb818eb26 0x14350530
+ 0x2c023f4a 0xce54b444 0xc8373dbe 0x187fd195
+ 0xb3b898d6 0x4af556e9 0x6b6c5ee5 0xcdd35ec5
+ 0x44e2ae62 0x6d57b2b3 0xca4753ec 0x7cbfd888
+ 0x9e4dc38e 0xcde55903 0x293d2710 0xd236f84b
+ 0x016997aa 0xe415f003 0xf3c9043a 0x3c17d8cf
+ 0xab946c5b 0x1492fa88 0xe800dc8c 0x694bf983
+ 0x6330ade6 0x73cc7c36 0xb190371a 0x340a333e
+ 0xcadb7168 0x46544957 0x161ce821 0xaf5aba0b
+ 0x2a483074 0xdc414466 0xff89c2c3 0x6be345e5
+ 0xcc6d38ab 0xb7184bee 0x2d3d3014 0xfab468b1
+ 0x58769273 0x4cd9b32d 0x9904046a 0x93127753
+ 0x6f750d9b 0x1b01b4b7 0xf5a8f0a7 0x06daf1ea
+ 0x06688114 0x205f441c 0x807747f3 0xdf29ce48
+ 0x9693acd2 0x648c00bd 0xdaf0730e 0xb5705538
+ 0x1aef0ba0 0x5a41b185 0xe5ad0226 0x50714598
+ 0xa6aaa344 0x849c7e6e 0x3c71f72b 0x4078f3fb
+ 0xde8f37c0 0xccfa72b1 0x49606c96 0x49585dea
+ 0xad971ab4 0x50208dfe 0xff446e7f 0xfac4de46
+ 0x81cd1577 0x3bbf8978 0x5e11789b 0x3e7ce21d
+ 0x53f9ecf1 0x22eb632a 0x26b3d386 0x35676803
+ 0xa426e362 0x924fabde 0x858f8242 0xa626e03f
+ 0x6b265948 0x2f7b1f45 0x1a3757ca 0xd7dfc2f1
+ 0xa9324b7b 0x13ffad69 0xeea8f8b4 0xc9acc8b2
+ 0xc3913f85 0x74df9857 0xa7743982 0x257c9f59
+ 0x87e6f0a6 0x0ad53759 0xdeee3892 0xfc83ab6d
+ 0x7f394faa 0xe7000ce0 0x7fdf6667 0xcaea0850
+ 0xb51da301 0x2b534d21 0xade4d5d5 0xef584f5d
+ 0xe22f4151 0xcc181641 0x7cb60248 0x43c7f754
+ 0x0be0cbb0 0x0e1c1ae4 0x9846f0d6 0x5c26632e
+ 0xee7f2381 0x37eb79a1 0xf27b2c89 0x45d49782
+ 0x7df3e51c 0x838220f1 0x41173453 0x704695e2
+ 0x8e697330 0x37860def 0xf5ebc630 0x468095b5
+ 0x5222f701 0xebfa262b 0xb8482a3b 0xace9be0c
+ 0xb7161f6d 0xc7ad9a9b 0x6e73d814 0x0980ff34
+ 0x8efc3ee5 0x470779fa 0xbdd71e46 0x230371cf
+ 0x0baad09c 0xcc68ac6e 0x6d2e0c74 0x328c9f08
+ 0x6752d432 0xd42288b3 0x1739034f 0x8b80c37e
+ 0x6338280a 0xd55a35bd 0x30799d71 0x7af5110b
+ 0x17773f78 0x362581f6 0xdfee41dd 0xbfb03d86
+ 0xd091d481 0xb6b0af6f 0x2c81daf0 0x049e0706
+ 0x317622a7 0xb2b1df89 0xe1cb1376 0x6c9e5e92
+ 0x809baf89 0xa6c275be 0xb942a1dd 0x9fe1efce
+ 0x5fcf873a 0xfab5e544 0x471617fe 0x00be2ce9
+ 0x65f76905 0xd96185d6 0xe7bfed6c 0xb9a24e09
+ 0x776d6d5d 0x64ae6e94 0x90da99e5 0x4e12adc7
+ 0x2362ce5d 0xa65c09e1 0x7f27fea7 0x8ea78f0d
+ 0x7d33fcdd 0x7ece6d71 0xd873c817 0x63df756b
+ 0x4215a6f2 0x657d792e 0x9f514868 0x6d19aa19
+ 0xf6276b52 0x7a5046d9 0x0e642e24 0xb19ffed9
+ 0xefa48aeb 0xd496077a 0x14f6f686 0xb013697f
+ 0xbb28a39f 0x0b49c8e9 0x9fa12b7d 0x45ed23c1
+ 0x7d5f545b 0x4c5eebc2 0x87457417 0x9912cd28
+ 0x16456561 0xdc8bf90a 0x1eb50230 0xc5ca2117
+ 0xc76a221e 0x32c46625 0xd718e8cd 0x4f391d4d
+ 0x408d6ae1 0x59a1e68d 0xdc2164d0 0x1a27eb34
+ 0x1226ab65 0x79b411ad 0x1e288871 0x9f1149b2
+ 0x0c291b3b 0x65564605 0xa5577204 0x5d6418a4
+ 0x74074f29 0xd475ca11 0xa47167dc 0x1e2a636e
+ 0xc667c8ac 0x74ae41dc 0x80b486f9 0xf3e571c9
+ 0xf5b58f5f 0x972066f2 0x9ab34e6b 0x36959a1b
+ 0xc35b30cb 0x16535e2c 0xf4f343f4 0x3c4ce4c0
+ 0x0d23dffb 0x7f5c7ac6 0x4b240af9 0x719656ce
+ 0xd13cfc1b 0x5d391014 0x1df24571 0xe60eae06
+ 0xe9b8348b 0x84318f32 0xe59b73b9 0xff61511a
+ 0xad38aa99 0x9704f905 0xfbc7422f 0x99581ae2
+ 0x59d4f702 0x29920e96 0xfd4605e0 0x45d6dd5d
+ 0x6a8ae3a3 0x18a754a1 0x162a9f48 0x3d3cadcb
+ 0x930114f9 0xc3157003 0x0e69fb18 0x3bef1ddc
+ 0x5c75246c 0x7e45b98a 0x4c5d3d8a 0x5c7ba0d2
+ 0x576de26f 0xc1717477 0x5289e141 0xed1703cf
+ 0x5c541296 0xb4fd3ec2 0x8299b3ff 0x833d1918
+ 0xb9c9d6df 0xfb864144 0xc68b2140 0xeef94cb1
+ 0x3081ac6d 0x11e679fb 0x28a8d6ee 0x1450fa01
+ 0xf2eb7690 0x069f4e2c 0xd82d9e66 0x90d0a134
+ 0x94506a6b 0xb156f8e7 0x15d4988e 0x61e838b1
+ 0x4050c1c8 0xf5480167 0x6c6b5387 0x882040e1
+ 0x1c576822 0x721faf51 0xc62e23f4 0x0a5ce137
+ 0x92e71c95 0x03704ca2 0xd4f4ffa7 0x62ce6831
+ 0xf75937db 0x6ec41127 0x5a0f6b9d 0x740db083
+ 0x17c844ef 0x2ff5f033 0xaa6c4c4b 0x1ba43741
+ 0x82d539f3 0x89f8c559 0xe5d7d8b0 0x6cde9f35
+ 0xe09dd140 0x752a39c6 0x357ab644 0x6d725123
+ 0xd3156805 0x2a667adc 0x8fba9fc0 0x2b95f6a6
+ 0x5b445475 0x1b6939dd 0x6d355453 0xd597908e
+ 0x1eae67e2 0xbde7e7e4 0xc8b0f418 0xc30b9fd5
+ 0x8429be75 0x39fc4443 0x5574e8b3 0x2737caa2
+ 0x63f52048 0xd8eba3b2 0xb5d6817d 0x440701e8
+ 0x8fa3c203 0x0b14345c 0x0f3de5f2 0x883b0407
+ 0xf9a050ac 0x7708b92b 0x3a4e2047 0x6514b530
+ 0x316caadf 0xba8f264d 0x2bb4e870 0x5c290444
+ 0xb92c8256 0x69e74855 0x3bef0744 0x85074b9b
+ 0xcd1cd441 0x65d7aa91 0xa6e6b18e 0x00950ef4
+ 0x4b7e155b 0x0f20d1cb 0x66967570 0x4329041c
+ 0x2822ef7c 0x5d23d9cd 0x8d9a08eb 0x22ece0fc
+ 0xfd70002e 0x6dafb2cc 0x4d6245c5 0x4f922e5e
+ 0xae71bfa6 0xd77143b4 0xec36850a 0x1141be49
+ 0xeb354327 0xbd2e81c1 0xf1e02b23 0x36e6c56a
+ 0x5b00e6ea 0x01523f35 0xdd467c4e 0xe0b68aaf
+ 0x5add5b4f 0x8af89711 0xb3a6df1d 0x10d73bbf
+ 0x7da50182 0xf7eef4bf 0xac8ab46b 0x9192187f
+ 0x9a77b25d 0xa6fb4e3a 0xd974f36b 0x2d5d4287
+ 0xfb8c99d5 0x8e09f429 0x87406c64 0x5b568921
+ 0xb1f0c18e 0x07127af1 0x2a7e0373 0xfabaaf7f
+ 0x0641e396 0x2c13d47b 0x7fc2c3cb 0x9923354b
+ 0x0781b144 0x14565ec6 0xeecdcb1c 0x198deed8
+ 0x756e2db1 0x9d63f9fa 0x8adad5a9 0xfed7f9a0
+ 0x4e7e42a4 0xde606824 0xdd7a7b46 0x5bfdedd5
+ 0x9de3bc4f 0x33632d20 0xa46f862a 0x44e7ee86
+ 0x7f1dab81 0x04bc42d1 0xcab0836d 0x27a79498
+ 0xf0908ee1 0x77bbe9d9 0xd5545f4c 0x96bdf186
+ 0x43562be9 0x1aca7e5e 0x10a6afaf 0xe77f4331
+ 0xd7a714f9 0x7d69bb8f 0xa6f7c2c6 0x5b47765d
+ 0x85cf795d 0xec3bf9f8 0x6120a5a1 0x1221b3dc
+ 0xa40eebd7 0x4b1a850f 0xc54b5f45 0x70696a91
+ 0x95e4f994 0x68a4e7d7 0xf73610ab 0xbf9a918e
+ 0xc296c1b2 0x22c94b51 0x7251446b 0xfa106d69
+ 0x3a483b82 0xffbe90a5 0xb5193f29 0x4eab332a
+ 0xcb256d5a 0x80a1d4f2 0xd0c82576 0xf206a4b2
+ 0xa87c5194 0xeb9794c5 0x1f2de60a 0x03d24a40
+ 0x7513f5b8 0x7c9eb6f1 0x310b3fb8 0x44db613b
+ 0xe6a87138 0x01c2affb 0x86f7502e 0x4646c069
+ 0x760cf456 0xaf1729d5 0x0cda28b0 0x05d25b38
+ 0x75775802 0x0aec6066 0x398e862d 0x5cb646f2
+ 0x27498e91 0x0d21c41a 0xc28f7d53 0x26b34c20
+ 0x0def57d0 0xfbe8f668 0x54aacccf 0x31f671d5
+ 0xfeb727ff 0xd1134b18 0x984befab 0xe8018e3f
+ 0x5664fca1 0x9b4f89e4 0xa5f9e765 0x1c81abdc
+ 0x07c807da 0x3eb61d45 0xd01e03dc 0x81685d21
+ 0xa0e0fbce 0x054b75b6 0x7c0d5f19 0xdf75841f
+ 0xd30386f4 0x7fbf1c38 0xd335b8ae 0x861b77af
+ 0x01c0945b 0x159d55f5 0x658164a7 0x82460382
+ 0x3889b1a2 0x69d1df23 0x9db51495 0xab5a40ba
+ 0xe8ffb5cc 0x7f97ce27 0x72297780 0x08564c09
+ 0x25245263 0xc77ac799 0xf020b6ee 0xa1a43e26
+ 0x30a5e09f 0x01f6f829 0x97961644 0x398fb5c0
+ 0xff8efc8d 0xaf5973be 0x39d03242 0x1102ccbb
+ 0xf41e180f 0xf8b9b39f 0x58827e26 0xc3e85cca
+ 0xf117b142 0xb1b72156 0x00fa68d1 0x6bd0cd65
+ 0xd7baac93 0x71b6b09a 0xb051efc5 0x1abaca81
+ 0xf1ec4198 0xc18d57c2 0xe3f81760 0x446267ea
+ 0xd165cd13 0x623770fa 0x46f98309 0x84119b56
+ 0x56687c4d 0x9276c444 0x3e1111cf 0x60cc43eb
+ 0xca66d039 0x8a721094 0xb78bf506 0x45eadd1f
+ 0x6dd24d41 0x4bf63cd0 0x4274755c 0xcb3c9104
+ 0x65dd66e6 0xa017ea2b 0x18bcf547 0x54815e68
+ 0x5d65b5ab 0xb14f312d 0xf2f888f6 0x367f0867
+ 0x7d06617f 0x4cf5660d 0x90331978 0x2358e1b5
+ 0xaf55418c 0x9700cb8f 0x04f04ddb 0xad2d66fa
+ 0x14ff5f50 0x9ecec2bd 0x9d8e9213 0x3c02ad40
+ 0xafad80ba 0x33997a50 0x8c314e5d 0x18485a60
+ 0x147cd77d 0xb2e6d561 0xe1d7f391 0x4a774594
+ 0xa2b31804 0x1c9573c7 0xade0a878 0x9d325428
+ 0xe59a890a 0x4e14d3db 0x98828e72 0x62f061b2
+ 0xa34102e0 0xe405b8b7 0xe70eb2b1 0x8305fffa
+ 0x15fd4b1b 0x3647130a 0x0fa693fa 0x213bccff
+ 0x8be2f93c 0x5fccc005 0x409b798b 0xae31fe47
+ 0x7e5a0b87 0xbfaf1412 0xfcba0901 0x2c50e788
+ 0xb03c6658 0x5bdc9914 0x461ca4ee 0x7a67fa0d
+ 0xe452cdbf 0x3bdaa6f4 0xf05e956b 0xe5af1519
+ 0x608afb31 0x04d305f6 0xa7942ddb 0xb42b9fca
+ 0xf5377403 0x1a41b1fb 0x729c80aa 0x23b9f813
+ 0x5259f61e 0x1dfbc47c 0x49cc1ba4 0x83f36f0a
+ 0xa659d988 0x3411d8ba 0x9d283718 0x377cdf0a
+ 0x0971775c 0x3301339d 0x15c9e915 0x57961066
+ 0xd7a71fc0 0x0e61722d 0x18dde63e 0x88ac866e
+ 0xe33c7e5a 0x1e10ee2f 0x1b4ed88f 0x24dab92c
+ 0xba3ebd7d 0x045cd9c7 0x38349770 0x19c58bed
+ 0xa84e8401 0x005f57e2 0x6c351717 0xdb0bd6f9
+ 0xe02a7d13 0xa1c30bfd 0xe820c746 0xbb1b3319
+ 0x6ff3592a 0x8d8805f0 0xf7f07017 0x4c445824
+ 0x3ab65173 0x31e34226 0x0a64e317 0xea7adb49
+ 0xd01b5114 0xe042a694 0xd4659e02 0x5a8a4094
+ 0x68c06794 0x7ac9c7f1 0xbb195a3e 0x8c25b1b6
+ 0xe61f7da6 0xa7377050 0x800d5805 0x728a3816
+ 0x3556e2b1 0x7edad3ad 0x880ccd19 0xf704f716
+ 0xa704fdbd 0x6c506715 0xb01c7949 0xe2c853b8
+ 0x22d69d3b 0xd979fbce 0x61dbec7d 0x2e24a0f5
+ 0xc44c42a1 0xa4371aa7 0x1c921c85 0xe163563f
+ 0xdeb9aef6 0xb07a6815 0xc6113b37 0x0977db61
+ 0x956a4697 0xd47e14ba 0x3ed9d661 0x2b6b483d
+ 0x9ee66746 0xd77dcc87 0xd7b27bed 0xd6fd72c7
+ 0x06fdef68 0xb9d02089 0x364995ec 0x201bf111
+ 0x8ea2580e 0x831b0b8f 0x879de175 0x6cbff50b
+ 0x4905be36 0xe2223f45 0x10c33c9d 0x4819cf52
+ 0xfb24288e 0x71bce828 0xdc31a0bc 0x7a1f9638
+ 0xe061635f 0x81a3bb35 0x0e7a5f23 0x30ebdea8
+ 0xcdb09f35 0xf3a78100 0x014b1c6e 0xe40d0e4f
+ 0xb4fd80a3 0xf625ee7d 0x83932d77 0x802a8bf6
+ 0xacd62133 0xefa074df 0xfbbc8752 0xd03130c7
+ 0x825f6a0d 0x13bc90d0 0x15461b35 0xf65bbcef
+ 0x834d860b 0x10b85d8b 0xb0e6a6ba 0x073a2724
+ 0x7b36fe04 0x3c5f6c40 0xb7267f96 0x8d41b32c
+ 0xd14fa5e5 0xd0f1cefd 0xf16b4378 0x1b30158d
+ 0xb8bc4c8a 0xcdd5bcb7 0xf599d6a7 0xae6c497f
+ 0xa3295605 0xed018953 0x279e0aca 0xe4130d76
+ 0x1346ca12 0x7c99293a 0x6a88d6a7 0x96a8e21b
+ 0x4b2dec5d 0xe3a0d997 0x18884dc5 0x16b0c992
+ 0xb305cf1c 0x059536a7 0xf9e8dd61 0x35f36076
+ 0x411da268 0x0fbd04b7 0xbfc0286b 0x3f43d4a5
+ 0x6ff425a7 0x191b9399 0x16955429 0xe7291c9a
+ 0x94266d2f 0x0020ea77 0xe97a491b 0x05f3d64b
+ 0xe904e7cd 0x1fc996ee 0xb5267321 0x0b045416
+ 0xa05b8e9a 0x7e87b890 0x0418e547 0xc7d8381a
+ 0xbfe27290 0xf1bf710d 0xf541392c 0x9d731a97
+ 0x10d83fd4 0x1142fdd3 0xd45205a3 0x778ff68d
+ 0xffe89291 0xef551eee 0x1cd65c9f 0xc0570b59
+ 0x9cab6077 0xe382c833 0x2de6e07c 0x4503d1e3
+ 0x611d3337 0x0db6912b 0x63e87ba7 0xec4cefef
+ 0xc9f68c05 0x5d9f296b 0x668eb313 0x72606184
+ 0x5c40431b 0x03883e0f 0x0c5ee3e7 0x9446406b
+ 0x74ff15a7 0x2b7b26f3 0xe793f913 0xdbf796eb
+ 0x33fb9128 0x5fa6a230 0x57b72dae 0x19a1645f
+ 0x758e2f95 0x64bc0874 0xfaad2208 0xb272f8a9
+ 0x8a3c1ba2 0x173aa881 0x2eda89f8 0x10be1bbe
+ 0x7e6290a6 0xaa5a1c2f 0x2bd0e8c7 0xfd2ab92f
+ 0xeb213701 0x643842e7 0x30896c22 0x1d5930c6
+ 0x2a63e6ab 0x681be1eb 0x96e99eca 0x16086415
+ 0x7adb7562 0xb8162576 0xfaf355f3 0xd62e8194
+ 0x7d89824c 0x0d90dc84 0xec6045ed 0x0ec71061
+ 0x36bac535 0xe97a4722 0x026e2cc3 0xc2a52ad2
+ 0xf0fbdfe0 0x86d47f96 0x38783397 0x13e179ad
+ 0x3939cfc6 0xc7a90e66 0xad11c691 0xd310ea0c
+ 0x74c6848b 0xedff38b0 0x709e0c0b 0xb7fd3c3e
+ 0xa7e61dd6 0x0cf5e31c 0x6c7da0c0 0xbfef7b85
+ 0x212613d6 0x619e6170 0x6d664486 0x0aa491f2
+ 0xffa6d7d3 0x5c1f2498 0x2909bf7f 0x7dc0d0bf
+ 0xae5f6cb7 0x918acaae 0x2da16456 0xc237f9b2
+ 0xb550afce 0xc9d12467 0x0e1fb820 0xe9089a77
+ 0x7395b303 0xa226ef7a 0xa9763cca 0x16fa1f04
+ 0x6ed0a254 0xe79a3e2d 0xbbabcd55 0x40b9f8a9
+ 0x4381487f 0x04f4544b 0x492385cc 0x9b30b9f2
+ 0xab640975 0xa2dc4c51 0xe11ce677 0x1679489e
+ 0xe5d3a517 0x0fed6647 0x2392fae4 0xe658e71b
+ 0x273c5243 0x0685982c 0x27c1cf33 0x6275ecd4
+ 0xc6ff317e 0x7c4a29a1 0x0b426fcf 0x0991acf1
+ 0x9feaa45b 0x1d1ffa07 0xf54687d3 0xb18f5d7e
+ 0xdbc422d2 0xf70244c8 0xe5548cea 0x3a0c907f
+ 0xdbf45c62 0x59b57e9f 0xa48f5e63 0x5c72e8a6
+ 0xb5b47cca 0x8168e20a 0x34b27256 0x9038f6fa
+ 0xe0ddd466 0xc2a48c7c 0x960db9c6 0x0f2732cf
+ 0x3dcc51d4 0x9391c39e 0x357979a0 0x80e62d2e
+ 0xdf3263d6 0x00524093 0xd370fc30 0xce834f90
+ 0x7b9186ad 0x0a52f586 0x91f6a338 0xb1c0683d
+ 0x19c473a0 0x58175c01 0xe2ddd12b 0x2eff8804
+ 0x5edf1891 0x42b13b8a 0xe29cf9cf 0x1a9a57e0
+ 0x551ae904 0x611c65d1 0xdfae00a2 0x5709d8a6
+ 0xe8e96058 0xaccb2248 0x1329913a 0x3c94a76d
+ 0x732eba5b 0xda39f17b 0x3c88c5d5 0x6d07ab0b
+ 0xb74969d1 0x75af86cf 0xc8f4e048 0xdaa00f5e
+ 0x8702a790 0x674d81bc 0xb4e1ab44 0xc2ea8673
+ 0xfbd8ce22 0x14f850e2 0xb580842b 0x7246150c
+ 0x3a6dee51 0x0766713a 0x8eed598f 0xa80b43d1
+ 0xc2c7917c 0xe2ef5cbd 0x83251950 0xf4079d78
+ 0x71f63dc0 0x6da3360f 0x001f8d0a 0x2f135670
+ 0xc85d6376 0x6754e59d 0xf53b5205 0xea0b3d07
+ 0xad19e39c 0x82408613 0x00c282cf 0x6bdfad45
+ 0x62f0ab66 0x770cd75d 0x2ba77a49 0x7233cc6e
+ 0xf9c76754 0x36880b84 0xc834c8fc 0xdec5ef03
+ 0x968aeb22 0xcffe64df 0x5851070b 0x17f63d5e
+ 0x48e7f121 0xc482ec1b 0xabd98aa7 0x5be312a7
+ 0x156e01a4 0xd526a4d1 0x8b75c41c 0x441f8ad4
+ 0x6ec314c1 0xef1cd01b 0xda6d9713 0x26cac0e4
+ 0x836bfd8d 0x433df830 0xe5a42260 0x31422f67
+ 0x81a83d78 0x0e3018de 0xad1c722f 0x110471d1
+ 0xff047a60 0xf4c77372 0x2e7d944d 0x04ee0afc
+ 0x627575af 0x1a3abe82 0x3beff798 0x8f492986
+ 0xd20456ca 0x3502f3df 0x3b02e7c3 0x03365dc8
+ 0x7705ea0c 0x3633c422 0x65b0b3ec 0x3e9ed973
+ 0x750cd309 0xda693bad 0xa890b0fa 0xb40c4dca
+ 0xd16afcca 0x49b9b449 0xae166692 0xc79d1384
+ 0x9cb9e327 0xa56a7d17 0x3e10ae3a 0x8ec84814
+ 0x1f82254a 0x07b889b8 0x7da971f2 0x540ac0cd
+ 0xea60e782 0x3bea0849 0xb17dae28 0x50dba88b
+ 0xd4df4a4e 0xda155e3f 0x672c95ba 0x1e91da48
+ 0xaa6cce17 0x002dbf3c 0x886b0944 0xee556fef
+ 0x4937b75f 0x3b5a6976 0xab70332b 0xc6335496
+ 0x641b7e15 0x7db46337 0xe7271920 0xc22323c6
+ 0x65ad4099 0x7cd99598 0x3ddd7e16 0x6835f314
+ 0x145cec8f 0xb2e7a3c3 0x09170052 0x2c34fc34
+ 0xabe9c170 0x765f3077 0xdcf265a0 0x95d95aec
+ 0xa1485bcc 0xbfb16108 0x01694ecb 0x6bab8f30
+ 0xaa4fdcde 0x2844bf83 0x677c7891 0x2b5304e9
+ 0x3a2deee5 0x6b8ce685 0xc4adc75d 0xa9698b2b
+ 0x7b83712a 0x178eac03 0xa51f95b7 0x1057a7c0
+ 0x28fdc9a8 0xbbf9a172 0x6da21335 0x2c0ed8ae
+ 0xbb41c417 0x8f2f2f7a 0x2d47a852 0xc5fef121
+ 0x07b2f438 0x53ddb4e4 0x297629cc 0x060f4905
+ 0x3b4b4b4f 0xcfa9601f 0x29ac502b 0x2ed377f7
+ 0xfe6fd814 0x46674670 0x40b07340 0x1594a18d
+ 0x3133a783 0x166dcbe4 0x6fdac44a 0x7966e454
+ 0xbb31b980 0x64ebaa4b 0x66b8036c 0x6d1a6bc2
+ 0xc9943328 0xce5c0b4f 0xc92855e1 0xc988f7b6
+ 0x965f1b48 0x88139c7f 0xd7f572a6 0xd8b4ef45
+ 0xfc3fb2bd 0x6e7e9728 0x98770466 0xe1ab3558
+ 0x9bd99c5a 0xf4a7b8af 0x26961742 0x130a1467
+ 0xf67c1237 0xf75ed2fe 0xc8edbf81 0x5d375cc7
+ 0x1ca686c5 0x6428a8e6 0xb6a89c96 0x838620b8
+ 0xa29ef90e 0xce6cc74d 0xc9a7ba3c 0xb8aaae94
+ 0x7e2e7496 0xfe89d0e6 0x886b55d8 0x053559f6
+ 0x13788e3f 0x1fe94926 0xe6be2cb0 0xb69bd93d
+ 0xe080a734 0xef31884e 0x1b7ee144 0xd3c0e444
+ 0x0dbd197c 0xa97c4e40 0x742fb324 0x60777e37
+ 0x65a0e07a 0x60e4a524 0xdea92cde 0x9d53a354
+ 0x054925d8 0xbed53c15 0x19a56f63 0x8e1d7d0a
+ 0x385c0655 0x6127884c 0xd90669c3 0xfd01eb5d
+ 0xba5230e8 0x8be4e0af 0x641ac70c 0x9da4bec4
+ 0x491b3fdc 0x72088377 0x6fadbb6b 0x1eb3f194
+ 0x138f76e6 0x06e5cfa1 0x50e6c02d 0xced3bc9b
+ 0x4f3cb822 0xe7c05bef 0xb8939b8c 0x228423bd
+ 0x2826da45 0x7c7a4327 0x69ee1772 0x6ce06d42
+ 0xdde9f377 0xfd8296f0 0xcacf450b 0xac8a79cc
+ 0x2515f4f1 0xb8877606 0xe3c75f15 0x87eefd57
+ 0xd5f83e31 0x8ad83ed0 0x645c8379 0xfb2c09b1
+ 0x29fa9f1c 0x523070c4 0xbdb3b12c 0x56b5dcde
+ 0xf8426a93 0xe4b2c23d 0x3d5b9e33 0x82b25356
+ 0xd92445db 0x33022612 0xb8ccdb74 0xa20ca557
+ 0x55345b9d 0x8e9c951d 0x97a6866d 0x494c6e01
+ 0x70210570 0x5a43c02e 0x6fe89bef 0x2cb5ad9c
+ 0xe0ab87e5 0x75adcb6e 0x45405e26 0xa692bf48
+ 0x5b609761 0x030a9467 0x40a759b5 0x106bb462
+ 0x620a7d75 0xe929da61 0x071bd58e 0xee378d68
+ 0x6b08d4d3 0xb8a36917 0x45efd5a4 0x62fa1ee8
+ 0x267621c8 0x01fcc95a 0xb313963f 0x881e32d5
+ 0xac58d47a 0xe8e98407 0x940144d3 0x9f4fe111
+ 0x99c16f87 0xa6f50b4f 0xa9407cbe 0xe1ed1a1f
+ 0xf7af2972 0xe3236e66 0x1514a6ef 0xa4838377
+ 0xb6b7bb2d 0xe9c12d6f 0xffbc47d4 0x0009e283
+ 0xe066bfd9 0x9453acd9 0x3a53516f 0x1565d9e4
+ 0x05623966 0x1b1dbdff 0xd1d630e9 0xd0144dfd
+ 0xc97ff66f 0x269311de 0x1f9661d8 0xc35a0169
+ 0x8b206d41 0xc078f81a 0xe0d268b1 0x612f66ae
+ 0xcef1e654 0x9ae0237c 0xa9a6db51 0x2ec4dc13
+ 0x31225c9d 0x201ddb16 0xcb8c3092 0x92b5bce7
+ 0xa554dd54 0x715c2779 0xaf77d5db 0x0e66d154
+ 0x4346695e 0x096b18b3 0x4bfffc37 0xc12f275b
+ 0x75be5fa0 0xe0844620 0x8ce45a27 0xbeb23c8a
+ 0x038acf17 0xbe750146 0xcb50aa60 0x28b17d7a
+ 0xf2c24fae 0xe80da3e4 0x53bda2ba 0x0db14ce5
+ 0xd4562d22 0x906e6c6d 0x2228060e 0x7b758425
+ 0x5120152e 0x79fab288 0xaa30431e 0xe02aff0d
+ 0x11cf0942 0xd6dec434 0xa37c5532 0xdc75fcaa
+ 0x6e709ccd 0x0fd6d302 0x9c0cff7b 0xa9ec920c
+ 0x4930add6 0x9dc7080b 0xf7e84e66 0xedafc508
+ 0xded94db8 0x32848bc3 0xb46e6e41 0xe9aec094
+ 0x2c6ed428 0x81998fb9 0xba44962a 0xbd47d39f
+ 0x69c5f06a 0x527f64a0 0x3863510e 0xabedb09e
+ 0x66ba1af5 0x2f4701a2 0x89619e66 0x2a8213b6
+ 0x96b35155 0xe36f9bf1 0x4e4c9831 0x41e29f39
+ 0x8a38c10e 0xc6b0b3bc 0xb9a8bbf7 0x1b3feff6
+ 0x116cee15 0x7a26aee6 0x8aa5e277 0xe033f839
+ 0x03ae9486 0x87feab5c 0x2a76ec0a 0x2c9f5bb7
+ 0x979e8365 0xb735d5fd 0xc5b2684c 0x65bec358
+ 0x20ed649c 0x6044f3e2 0xe964aaca 0x083c0fc7
+ 0x64c6f5ec 0x58c2f1a0 0x7248e733 0xf86633d0
+ 0x155e08f1 0xb5105931 0xc3a675f3 0x58beb5c4
+ 0xce27bb83 0xc317c8e5 0x08c20bd5 0xb52687ee
+ 0xef5115d3 0x4c01fe14 0x031db379 0xcb219aa3
+ 0x42ba3a94 0xe51c3809 0xae496040 0xf8a9cd70
+ 0xcc5753ae 0x0540afc7 0x2f967c3b 0x7ef7aeac
+ 0x4a41f6eb 0x705f7bed 0x556adf2e 0x68b38e05
+ 0x86bc6414 0x0dd9c2a7 0x31d0f0bc 0x148062f4
+ 0x2ee98f94 0xd62fe807 0x11d37fe3 0x052ecb38
+ 0xca75133c 0x2ed8c2c6 0x8e604160 0x392e1fa0
+ 0x8544d810 0xbf670aac 0xea63e11f 0x69f8e72e
+ 0xe5ea3048 0xf33a1162 0x51def599 0x5aa97dd8
+ 0xa7af7df6 0xcf7ac38b 0xfac81bb1 0x5c13e786
+ 0xafb6c23b 0xf51f6a22 0xb07484dc 0x476b48a5
+ 0x88a4b41a 0xac65199e 0x30206ad2 0xda03b33a
+ 0x5c1f02c6 0xc47f63eb 0xf32643e7 0x963d6f51
+ 0xa7154c6a 0x927627aa 0xf46ce42a 0x363f40e5
+ 0xb4bf67e3 0xe47052d5 0x9e0b47e1 0x6b0fe58b
+ 0xa03a9c49 0x5e945cb0 0x6ad3cee7 0x6e5bd7d6
+ 0x11acd8c7 0x79545822 0x255b7b5a 0x5f909b17
+ 0xafb63f90 0x5a407558 0x47b10cb2 0x510251c2
+ 0x7534555e 0x374d4ac8 0xae77ac8d 0x42134d42
+ 0x2eadea43 0x3abcc1c0 0xa3281b92 0x7883d25d
+ 0x41825437 0x9a5e2c5e 0x805c11b3 0xf2fd6d24
+ 0x9e5c2348 0x61cd2c3b 0x4290dcd5 0x906ac92c
+ 0x75a98667 0x29a0953f 0xea6f3127 0xcf96cccd
+ 0x255aa79f 0x566e1f66 0x6368bf00 0xd54ac5e9
+ 0x364a210d 0x68739b18 0xa482d61d 0xbf54b83a
+ 0xa572f37a 0xf3cb277b 0xecd0a7b0 0x4dadcf68
+ 0xe611e146 0x9cf2a4d4 0x89b685e8 0x72b99e7e
+ 0xe2571569 0xc136a3bb 0x7876c300 0xaa37ffbb
+ 0x4733aa9a 0x9f5af114 0x288961fe 0xe4435cf7
+ 0x7e72625e 0xa2c435bb 0xce8fa422 0xa457a9e8
+ 0xfb68cabf 0x74968fa8 0xc3070a6d 0x785da5d2
+ 0xf3405cae 0x0fe4988d 0xa0dfc0bd 0xf9e6e423
+ 0xf6146969 0xb7aa7f77 0x5a57e757 0x6db990ee
+ 0xc49f092e 0xb1dcf93b 0x3b5499ee 0x45551aea
+ 0xfda57777 0x114422ef 0x2469c86b 0x50990211
+ 0xd8de398b 0x0f1a46f9 0x82aaba33 0x41f2f3e8
+ 0x64ad897f 0x6e00f781 0x6cf84715 0x46b63df4
+ 0x1ba8220d 0x93f57e2e 0xd884801a 0x2be20427
+ 0x98284ea3 0x69a7ab50 0xf92720f6 0x2669b337
+ 0x72c26a6a 0xec7f7086 0x1241983e 0xb46cf0e4
+ 0x05c303aa 0xf319d17c 0x1675bf24 0xbf3fcb76
+ 0xfd40cd25 0x8f4b1a94 0x4c16fada 0x2a315da8
+ 0xdf3ea7a2 0x98c05b13 0xd8a0daf7 0xbc0dcc30
+ 0x1468a240 0xb52d9ee6 0xcd66c460 0x2a1a4d2c
+ 0xf745b0e0 0xb5bc837c 0xeb6b1f38 0x9123504d
+ 0xeba7ef5b 0x2b10b0d4 0x5e22dfcd 0x4738c874
+ 0xb0f1d3d8 0x7bdd395c 0xd4f6a2b6 0x27fd3105
+ 0x18fa05b0 0x19ff0580 0x990ccdb4 0xb81e67e0
+ 0xb5bc6686 0x669059f3 0x6977de9d 0x876053bb
+ 0x5b50f1b5 0x71c07729 0x7e1305e5 0xc248bd65
+ 0x5f3c8c80 0x5b4c883d 0xeaf29302 0x764b7c09
+ 0x95f53d63 0xa99544ec 0x04c35881 0x34e0c07c
+ 0x2038454f 0xe5b98ad8 0xe076ee6a 0xe708b760
+ 0x9420d20c 0x4bfea03a 0xf1588ed4 0x13d9a7de
+ 0xe3a56c16 0x5216ae46 0x0bb1d9db 0xe78f9080
+ 0x14f9bdb0 0x54382a55 0xfc2bcee9 0xcf678d72
+ 0xafe6f3c2 0xe6266a66 0x81d8e14a 0x9df511f5
+ 0xb76bbf2b 0xcd27eed7 0xca08842b 0xf982f551
+ 0x358d4c7a 0x341eb98e 0x78b3248b 0x2c3ddf2b
+ 0xbaa24b24 0xdd1b8ffa 0xbbbba633 0xdb05116b
+ 0x124a84ce 0xeb724c87 0x46247d39 0x7373c479
+ 0xf9153a17 0x670c54ed 0xa0f9332d 0x251d955b
+ 0xf341ea7b 0xf3c7ed67 0xe54f4b60 0x2fb2a89c
+ 0x1db5be18 0x6d87706f 0xb35bad8c 0x94f00821
+ 0x7f1d5e2e 0xb94d96ab 0xb1bcfb5f 0x77f3e9c1
+ 0x22a74758 0x12507b73 0x07454515 0x539ef418
+ 0x991f26d3 0xb8a7e4fe 0x88f43bef 0xe5106dec
+ 0xf08d35bd 0x37b78b97 0xdef6d486 0x36e9afec
+ 0x44256976 0x8fa27327 0x5e4510e1 0x62b1d6ab
+ 0x739f6a3a 0xe53b2560 0x0eee61ab 0xce5c2195
+ 0x2a11d29a 0xfcc773c2 0x998f0377 0xfd0cfbab
+ 0x60531b2d 0x0f163a3e 0x056e4ea3 0xcbf8f075
+ 0x8eecb224 0xdb6f6564 0x9994cf11 0xf2da6068
+ 0x7edf2d60 0x3484e010 0x3986d352 0x3215d09b
+ 0x8acec634 0x88beb778 0x384583be 0xcfa9469d
+ 0x3eaa128f 0xd2584846 0x526e16c5 0xe62c56b0
+ 0x28878619 0x451a3cc6 0x9d6b3b22 0xbb4595e7
+ 0xc41c5702 0x8eaf59af 0x3ec60116 0xcd3fdf25
+ 0xf4baa3ee 0x995acf3d 0xfe048b4f 0x34bf9b46
+ 0xef80dd5d 0x715270f8 0x7a0c0212 0xdf084b0b
+ 0x6823f5b0 0xd63885c6 0x68fa0d06 0x4d4cdbb1
+ 0xe3b28319 0x15e287fb 0x7c8a7c24 0xb260381c
+ 0x956d8721 0x02e9a6a2 0xc43316e0 0xf8e8f45b
+ 0x3b98c8f6 0x5ac45695 0xec28fec3 0xc122e2a9
+ 0xd54498ee 0x075854eb 0x24a9c53a 0x88f82fcc
+ 0x6a300c63 0xefd1ae69 0x547a9ec3 0xa137e93c
+ 0xaaa2242f 0xd84cccfd 0x4b317c9a 0xa73c890f
+ 0x53563e89 0x496e871f 0xacb487cd 0xac528731
+ 0x979bd60c 0x1644d04b 0xfb25ec8f 0xa13f6ce3
+ 0xfc0c1a00 0x13545d49 0x4b7f9ec9 0x4bd41253
+ 0xe2b467a7 0xd677887b 0x3e52951d 0x1b16be80
+ 0xb335a750 0x0cbe6466 0xd7b20d9a 0x2fc717da
+ 0x7b421a32 0x361f1f9b 0x7a690107 0x07418186
+ 0xbe912ff0 0x19ab248f 0x45f15951 0x928dc0bd
+ 0x34b6d079 0x0e232ff2 0x905d8b2d 0xdfbe8b6e
+ 0x9329a93d 0x730f6446 0xfd66b27a 0xfc2ee1e1
+ 0xc7843f87 0xfb41abd9 0xe195709a 0xa55268ad
+ 0x7fafd370 0x5b3d3940 0xd0499932 0x68b122f4
+ 0xb68060a9 0xd8bc5e9c 0x3e97aa65 0x81d088e4
+ 0x1f1d516b 0x91025dbd 0xa2bd0027 0xae82f668
+ 0xd7b9a631 0x0a498109 0x4ffa40bd 0x82778f22
+ 0xe57c458a 0xdfb5fc7b 0xe87374e1 0x8886dcc2
+ 0x2cbc6bcc 0xcd024d5b 0x21987f5b 0x5bee50d5
+ 0xcfc95d59 0xbfeaecce 0x35e308b2 0x1c431c62
+ 0x63834bd5 0x9a93892a 0xdf509f2e 0x7a5ad3da
+ 0xe11a9e99 0xc7363cd2 0x84e195f2 0xf18d74ad
+ 0x5cd07824 0x5e632fb1 0xabf51bdd 0xbdcdb3b9
+ 0xe7f2b97f 0xe0319ac1 0x92515886 0xdc4a11de
+ 0xd2a8b48b 0xc713272b 0x1e1250d0 0x59d87385
+ 0x7f962a6a 0x07c50bb2 0x935a13aa 0xbbdf216d
+ 0x22bfe2cc 0x9c587c77 0x4e3d6997 0xb5b9030a
+ 0xfe9131af 0xfafc7485 0x35a53be7 0xdd7a91ef
+ 0xb790c7a5 0x5077a502 0x7670eb90 0xa032fe17
+ 0x79f1a53c 0x426d12f7 0xda45810e 0x1892e046
+ 0x1f11dace 0x1b80983c 0xed8401f4 0xd5813b24
+ 0xe1d5665e 0x5d5086bf 0xbd7605cd 0x1ef38e49
+ 0x79848055 0x0c537b4a 0x85198fdf 0xc13d9914
+ 0x61c2d22c 0xc3a71565 0x80aa108a 0xbc6cee1d
+ 0xa01d35d4 0xe1bd82df 0x11867dad 0xd04b476d
+ 0x23f6bf14 0x1b326624 0x908504ab 0xbe631bc9
+ 0x7bd48d7b 0x715d075e 0xdb00938f 0x295c2109
+ 0x555dc4ef 0xfc476f0c 0x704f2970 0x1528a393
+ 0xf5a5a3e5 0xb98429e2 0xf00ddc40 0x23df90f6
+ 0x31d70e78 0x7ed4eb17 0x078264e7 0x0604a330
+ 0x7f1a2a62 0x339ebf28 0xb6a7f8c7 0x459323a4
+ 0x5e0da59c 0xe0f45bfe 0xc718dc9a 0x4b1b6237
+ 0xe06bbf0e 0x195f6811 0x474d7c3d 0xcca640ae
+ 0x77a48b6d 0x96eb434e 0x8a118ca1 0x55a513d8
+ 0x2b4c0414 0x2bed5335 0x8feeeaf0 0x1e3ed22c
+ 0x887a2db3 0x3e9cd3fa 0xe836764b 0x9833144f
+ 0x9be55821 0xc45ca6ed 0x65419d88 0x4f4e8dd6
+ 0xe159296d 0x1fe302bb 0xcdfa2bfc 0xf6cd6f1a
+ 0x8acdeed0 0x8bcdb4c9 0x36c82e69 0x4ec65b26
+ 0x10498082 0x6e267465 0x3b0831ed 0xafae25ca
+ 0xf02be37e 0x930c689d 0x44d149c6 0xfcc96fed
+ 0x39ea636e 0x02009f40 0x4e1de152 0x8c138829
+ 0xa16e6860 0x33a5f206 0x9c97bd93 0x58af75fe
+ 0x984e0f23 0x4abfa9f6 0x99693bab 0xa787d2e5
+ 0xaff87efe 0xd5078255 0x21d6f10d 0xff7db25e
+ 0xc3431f52 0x20918eb7 0x1b8605d0 0x23b92d4d
+ 0x4a72f632 0x80c1fd17 0x0c02d9d5 0x1ae9c1c1
+ 0x076b6166 0xa7182495 0xbbd4d5b7 0x81aa4b26
+ 0x00ef55f9 0x3ee3d821 0x0b84ad77 0x2bcd72cc
+ 0xf1787994 0x13422b02 0x9137efd5 0x4da3a99f
+ 0x7ffc5321 0x4b2bc219 0xe96631b6 0xaeb03a4c
+ 0x0296e305 0xf923b421 0x519becdc 0xf918f411
+ 0xaf036986 0x85e8ccb5 0xfa7da8fe 0x50f4919d
+ 0x1fb7158c 0x1cc71295 0x87b14315 0x68bf833c
+ 0xe0e2f829 0x0899a1bb 0x7d0d6259 0xb3e0d938
+ 0x87247548 0xc4b8b45a 0xa1a198bc 0x86553eb2
+ 0x07903528 0x3468e45b 0x3f619b4b 0xd76e9f2f
+ 0x1fe52ccd 0x1fa7489e 0x1a0944a9 0xa3001f22
+ 0x52e29e4a 0xd8583e6e 0xa2f8bf9a 0xbb596023
+ 0x78d13b38 0x37722a86 0xad2630f9 0xbe615c28
+ 0x8d660703 0xd2c60522 0x93600693 0xb8026ec2
+ 0x04d71941 0x0188c650 0x8fde0e25 0x00bb1949
+ 0x18cbf921 0x9efafd39 0x61e2c5f8 0xd7e129d6
+ 0x1da1c371 0xeebb9552 0x3d89d2fd 0x507ddb33
+ 0x59aefa5c 0xa96050c9 0xa89753f6 0x8a6a3724
+ 0x249e55af 0xf5d712aa 0x165332e5 0xeb8b8fe6
+ 0xdd58d97b 0x696b8de9 0x1aaddbfd 0x5b70ab39
+ 0xd3cfae84 0x43d4ed0a 0xc3e62170 0xff5a2f1d
+ 0x4dcac28f 0x483e6b75 0x6f499dc7 0xe322ea5d
+ 0x435cab14 0x9c83b6e3 0x03b8cd4b 0x4a773061
+ 0x8dd12c6a 0xe16e0b85 0x71754c74 0x61da9e61
+ 0x6b0a5780 0xec507e7c 0x67d251f3 0xd158d66e
+ 0x5d554986 0xf1b869f5 0x3846a89a 0x93203735
+ 0x1fee1e40 0xfedb9d4a 0x833f3275 0x4efbb610
+ 0x84e139dc 0x391caafe 0x72ded682 0xc4578cc9
+ 0x2a97e6a6 0x31ae0a21 0x61b759e8 0x7dba8f29
+ 0x9f44920d 0x2a682773 0xe0973858 0x4fe8d93f
+ 0x4461e195 0xb4e9d538 0x35244354 0x71e1e076
+ 0xe7c9a805 0x9281e7bc 0x9c5866ff 0x8d3fcc6b
+ 0x96bf9d94 0x081b5f1f 0x59f1c86f 0xc7624b4a
+ 0x642828b5 0x2d1adf14 0xa23027b0 0x203baa5e
+ 0x383020e7 0x9270e519 0x5c9db413 0x65de52bb
+ 0x427d85ca 0x9be72540 0xcc42320a 0x2a540c30
+ 0xb5f05697 0x94deb4f7 0x85931ed3 0xf6985f6d
+ 0xcdbefa9b 0x4c3b4518 0x23900cdd 0xb61242cd
+ 0x551f4fcd 0xe32114c9 0x1463bf4f 0xb1ab0b15
+ 0x9d3bd7d5 0x482ba600 0x2a1905df 0xeca00b13
+ 0x4231c992 0xbee51476 0xd53b8a3c 0x84e444b3
+ 0xf580de73 0xb77ae962 0xd317f0f7 0x0696e18c
+ 0x548cc93a 0xe84e9eaf 0xd3a112ba 0x09203e1e
+ 0xe5fcf34f 0x8cbbcad0 0xbd39deba 0x3f3c444c
+ 0x9b42960d 0xa7cfd77c 0x6fe061f4 0xa47cde9e
+ 0xc6e0d1c0 0x73c66abf 0x5d1e8fbd 0x3623c582
+ 0x661501cd 0xf82c02b3 0x1fdddc43 0x41326004
+ 0x7e66833c 0x9b87f09e 0x460e9f29 0xaa42d4c7
+ 0x9de056bf 0x7a04e294 0x4f45a29e 0x4dc53b68
+ 0x35f66dc3 0xe5d61f33 0xdf1c3b74 0x7a800188
+ 0xd2d69278 0x51d10dec 0x36ba5a27 0x84710d0f
+ 0xdb9d4265 0x0cdb2557 0x2294b43b 0x21fd5276
+ 0x8e242a48 0x534b736e 0x517c06fe 0xddae34d2
+ 0xc9963646 0x316a2866 0xf78e670a 0x4354b9ad
+ 0x6478b461 0x41bc356b 0xadc9d69f 0x86310701
+ 0x698b5dd4 0xac1a065b 0x325b19b6 0xdd8c1424
+ 0x9782ac36 0xd07f2b25 0x3142d1ef 0x1b65cce6
+ 0x45dc809d 0x26b47e8a 0x47ffd190 0xddd23daf
+ 0x852c505c 0xc68d8c2b 0x76f71872 0xd62371f2
+ 0xa85876ff 0xd67bee5f 0x9c7f08df 0x7cffada6
+ 0x1f87b705 0xb7395ce6 0x5f20c731 0x83b83c9f
+ 0x39b72eb9 0x33402454 0xfaa4a4f4 0xce09b8a9
+ 0x8fc8ec39 0x8282f919 0x18a12d7a 0x669b255e
+ 0xe63cf97b 0xe06c98ad 0x9e9c48c4 0x9e1eca60
+ 0xade5b5a5 0xe871bbcc 0xf5c4459a 0xd239cca5
+ 0xbc690a32 0x8e6a5a36 0xf656c3cd 0x2aea3748
+ 0xcd89e82a 0xd727974c 0xc89c15d3 0x2cb3d656
+ 0x5ea5697f 0x95351d3f 0x3c51294d 0x19dad085
+ 0x9875ff98 0xcbe290c9 0xec1db1d1 0x06dad038
+ 0x59676ed1 0xd4ffaa52 0x67b53321 0x406d0405
+ 0xb63b27b5 0x02a7acfe 0x0218e862 0x0600e77e
+ 0xc5ab4fd1 0x59614324 0x0711ff6b 0x66aadc1f
+ 0x03d4783b 0x260efa73 0x595b8ff7 0xcc38a258
+ 0xf581cde6 0x54ad0529 0xe7fd85e0 0x865cdb10
+ 0xb36829e6 0x292a183f 0x0365b477 0x699539bc
+ 0x1bab4354 0xef8fbc6e 0xcd13d0d0 0xae88592d
+ 0x1fd2b9ab 0xc73c4087 0xd443f88b 0xd954a62e
+ 0x98f330f4 0xec153762 0x79ab5dde 0x576b971d
+ 0x32bfeb19 0x8cb0fc53 0x0adf7206 0x1fd5c3dc
+ 0xbf2937d0 0xe3a27af7 0x7a5985c4 0xf385bd6a
+ 0x4749ff2a 0x2c9dbb25 0xfb5ec7e6 0xd35e3858
+ 0x6b02a00f 0x39648c79 0xea16560c 0x7426126c
+ 0x2e48ff85 0x7db3751d 0x5caa6cae 0x9d7bf7fb
+ 0x7dc3045f 0x11a58714 0xb1c7ec05 0xd861d92e
+ 0x3b9335a5 0x369f36de 0x86537f91 0x6df69efe
+ 0x097f9eeb 0x21a1c221 0xe705e58c 0x814c6d6c
+ 0x3b15231e 0x27348dc5 0x31904ae2 0xe795e0bd
+ 0xd66763ea 0xe8d72c3e 0xa98152da 0xe13f01ee
+ 0x3f309623 0x4af332ab 0xfa907056 0x55f64e59
+ 0xec5b728e 0xffb73bfa 0x01e03bd0 0x78b40ce6
+ 0x494800ba 0x391c7b3c 0xb1a5f6bd 0xc08f1e24
+ 0x3e463ced 0x365110ba 0x637cb6b0 0x75753237
+ 0x8a7eb826 0x10017424 0xece96fac 0x7e1ee939
+ 0xa11e1553 0xfca3f88c 0x20937141 0xa10f07ed
+ 0x2be3baa4 0x0b1abf6a 0x446bb4ac 0x431fcc86
+ 0x4d13befb 0xa1dde1c8 0x956aa819 0xa6a6bb8b
+ 0xca2e0a62 0x7ebd0a45 0x1ffbd5b8 0x95c8518a
+ 0xa69b829e 0xba2506fa 0x8969eb89 0xb8989e02
+ 0x2cc46256 0x52f394ba 0xef94217d 0xc397b570
+ 0x029acc3f 0xe4ed9f6e 0x15d2b07b 0xe0e0e7b5
+ 0xf0a90eda 0xd2b9c951 0xe7fd0d22 0xa11b524e
+ 0x297192fe 0x09494708 0xc3231693 0x23057014
+ 0x2347f4f8 0xecb07723 0x78d5387e 0xd950aa5a
+ 0xb8b89982 0x3d4eb0fe 0x9a5eac36 0x3c314180
+ 0x037ef95a 0xe5a07f1d 0x963d7545 0xda533ac8
+ 0x652420c3 0xecba1589 0x69956916 0x7118042a
+ 0x010cc872 0xca74ec31 0xb65b0a15 0x24d7076c
+ 0x7835e3c4 0xae04ce57 0xb9106c38 0x450147a7
+ 0xfcd308a6 0x3780795d 0xf127d659 0xabd3762a
+ 0xc33508cf 0xd43c2743 0x13f9c4b7 0xb811ccee
+ 0x60ea88e9 0xfeaf11ed 0xa2e4e08a 0x679a8a16
+ 0xfe2f179d 0xf9d71588 0x46a5b44d 0xa3739f11
+ 0x026aece1 0x27227337 0xa67499e7 0x150941d7
+ 0x3acb3852 0x36e4a886 0xb3cdac7e 0xa6cc4731
+ 0x3da129f9 0x8945d1d3 0x0ca8e53a 0xefc7a5a8
+ 0xde9550b5 0xa2838b96 0x85855f0e 0x5f527d35
+ 0x6f7cc825 0x3376c65d 0xe11c296e 0x31b6c238
+ 0xaa78ce8f 0xed627ba3 0x8b341b27 0xe5ae270a
+ 0xe4def7ab 0x4956ab96 0x8fe3e3e6 0xc38a8264
+ 0x4a580ee0 0xa367eff8 0x30cd46a1 0x63bfb7de
+ 0x0f077d1a 0x071655c1 0x9cd20ef5 0xbd910426
+ 0x5ff8d076 0x780541e2 0xb1b78ae6 0x8d4f3e25
+ 0x0d607fbe 0x6553eaa5 0x295663d7 0xad96bd90
+ 0x3fb8d299 0xa876e194 0xeff9ad1b 0x8eca7226
+ 0xae0822a1 0x2f2665b7 0x8c380d8c 0xdc3dced0
+ 0xc5902d53 0x9487cbc7 0xaee8d33b 0x9918bc49
+ 0x172b80a4 0x54da0366 0xb0480c4d 0x8505c00c
+ 0x95f9d4e8 0x04f6c56c 0x4f1992d7 0xd5be2a99
+ 0x9cfd5518 0xae36133b 0x68cfab7a 0x93c5b3c9
+ 0x5c3e00de 0xfdba8d1a 0x1950a499 0xf585b68f
+ 0xd7877843 0x31f26d1c 0xf6aaff0a 0x8422439b
+ 0x34932e6a 0x9fdef126 0x004902f2 0xcfeb933f
+ 0x461cde2e 0xbf0c2348 0x6f378884 0xc6f28584
+ 0x0e8e1484 0x487df649 0xaa6d7abe 0xabe47e51
+ 0x9c037ac3 0xa7d9a917 0x017ce418 0xd3fcfe05
+ 0x45d44ef0 0xe2122eda 0x3dd12c7b 0x2b943ac1
+ 0xe944001a 0x9ea8c0f5 0x13887de2 0xcdeac67e
+ 0x661926c8 0x464d7d92 0x2153bc27 0x28f366b0
+ 0x95aaccf9 0xf58e42a6 0xe2b74b95 0xc4e76731
+ 0x8bbe0115 0xc13d03b0 0xdfd3c57d 0xa6a6a376
+ 0x33054af1 0xf2164000 0xf12d1b3e 0x10aaba39
+ 0x8c48e878 0xf62e4034 0x9989fe81 0x3cce7788
+ 0x33dedaab 0xecce3579 0x52a1a0f9 0x25f7e0b1
+ 0x00024fcc 0x9d315f1a 0xf9243a7f 0x51b5bfcb
+ 0x4cf926ca 0x19a4e8f4 0x729db9a8 0xc3f0cda4
+ 0x2cd53230 0x1d86dc30 0x7b20b7cb 0x1bdbf1f8
+ 0x208a3bed 0x175ce105 0xfd45df17 0xdd3f5fc1
+ 0x689efdd6 0x0ab4123b 0x7329b958 0xac90a04e
+ 0x32caa96a 0xf7609907 0x862ee458 0xaa328d13
+ 0xa839f1ba 0xe7da448a 0xb5f361c0 0x5d5f16c2
+ 0xcb3faf23 0x9d6fca62 0x80ed4411 0xfb134416
+ 0x39ab14a9 0x305ab74b 0x76312b28 0xea38b1bf
+ 0x45dee43e 0x4890904e 0x548bdf7d 0x20ef92c4
+ 0x86704c38 0x8366dde4 0xafc9d551 0x01486482
+ 0x2a66f042 0x819315ea 0x59aef12f 0x5c4d2f1f
+ 0xd1d0fb21 0xa286aa99 0x59fe8c60 0x0fb2275d
+ 0x455d95c1 0x665c9783 0x4c6a7fda 0xd78f1536
+ 0x2cca3af5 0xe7fc1c83 0x12836c68 0xe40afac4
+ 0x04971027 0x15033991 0x1599b526 0x28f271d6
+ 0x249e2db4 0x8c87a3cb 0xd8949626 0x467b165a
+ 0x9834d5dc 0xaca55a99 0xae403e0e 0x5e44dfe6
+ 0xb5cb972f 0x4affd423 0xdfe3a0ba 0xba66ddd3
+ 0x8fb8afbf 0xf7d2127d 0xc56b4e4e 0x801ee995
+ 0x3af70660 0xe4271646 0xfc9b3f0b 0x0d1b714c
+ 0x2899451e 0xc0d2ac1d 0x5376412e 0xf8830b3b
+ 0x00730f02 0x2070e1c3 0xaa3ecdf4 0x61c2b089
+ 0x43160e14 0x1c909bca 0xb12b3e7d 0x563aa455
+ 0xa6c82117 0x2fd25eb2 0xcbf7402d 0x5fd16485
+ 0x2a903214 0x10b1e25f 0x20ec92fa 0x03e38321
+ 0xe264cf01 0xd0b18d0a 0x529610d3 0x6a862094
+ 0x0021652b 0x3e41ec43 0x68753afa 0x578208f8
+ 0x63fc6585 0x3c065808 0x15072917 0xe530dbca
+ 0x4fd31ab6 0x90ec9f1d 0xd21347c2 0x1aa8057c
+ 0x707ac53d 0x3a6f6cff 0xef4f5bfb 0x91f9df78
+ 0xd4d8e7b3 0x85b23779 0xd70dfb50 0xfc3eb090
+ 0x2afb8f1e 0xd17d1671 0x887adc0d 0xbd01123f
+ 0x39584f27 0xe5bdc9fb 0x8c1f74ea 0x4771c3ed
+ 0x994f3f8f 0x71f73dfe 0x6d8f1065 0xe639d542
+ 0x1a0c1e63 0x87d4f6cc 0x6b7d3f3d 0xf04e1fa7
+ 0x83d6c73d 0xd674b74e 0x3c68a8c6 0x018b543f
+ 0x3c1e295d 0xece6274d 0x1119b65a 0x74a6967a
+ 0x69e31d43 0xed442719 0xb6d4d76c 0x0c634c05
+ 0x94ee29e8 0xd780bfe7 0x2bfa6dd0 0xa84c1e0e
+ 0xc5a76023 0x8513aaab 0x67104dd1 0x6758d5ef
+ 0xb804c65a 0x4b5eae39 0xcdf42fc7 0x0a409263
+ 0xd5172df1 0xe06de198 0x221b3d16 0xd389dea9
+ 0xdc7ec34a 0x0cdb0c31 0x74aa5423 0x1a3a12f0
+ 0x84af11b6 0xed5484a9 0x48a42703 0xf88a5554
+ 0x1fb1c3e8 0x14f0139f 0x5bb798d4 0xa44d0a7a
+ 0xffe63aaa 0x2623dfb2 0x3dfdf073 0x7c5f64c5
+ 0x7fb8e776 0xd6ec4cda 0xbbbcc9c5 0x543d4e67
+ 0xe6261cdd 0x5fa93a6b 0xb2f22232 0x46b3bf1d
+ 0xc85c492f 0x3e9b59c8 0xc57467e9 0x3ef1cca2
+ 0x885c11b4 0x430b945b 0x7e866a53 0x35640ef2
+ 0x2bc250d2 0x143e8bcd 0x526e160a 0xaf195f5c
+ 0x6b7af12d 0xae86e442 0xa8a7e79b 0x348e2f45
+ 0x83464bf9 0x7e9217f2 0x633167d5 0x7f48a7d9
+ 0xc0e68db1 0xe20a73d3 0x08631c1e 0x6d1c947c
+ 0x09f758fb 0x4e7a91f8 0x6310962f 0x4cb9d435
+ 0xc4e0d790 0x516ff75d 0x7d94e8f9 0x5e096081
+ 0x54c45793 0x5c4006ad 0x96597e18 0x8288ae51
+ 0x80b02790 0x07a93092 0xc3c4f812 0x5370f66d
+ 0xb0dbdcf4 0x7b3989b6 0x401ba87c 0xb6583c3d
+ 0x172f026b 0x14f6a157 0xf38c63d1 0xdd649ff5
+ 0xf3f4e004 0xf35ada45 0xb4ef6088 0xf4dd2f84
+ 0x45cfd771 0x87f4aea6 0x258285ab 0xd6cd6526
+ 0x6ef11ebc 0xc9fe8974 0x19fa04ad 0x42f2cb41
+ 0x1f79e225 0x4a377d25 0x21bfba29 0x344a68e1
+ 0xf5ecce49 0xfbb59c84 0xd79e3b7a 0x66abbfbf
+ 0xf472eadc 0x96e131d4 0x582cc500 0xd6e66fbc
+ 0x89514daf 0xfc33243d 0x03f2ef3c 0xc89b7e63
+ 0x81690099 0x3d7b84fa 0x760c3e67 0xd17dc669
+ 0x5d224d4c 0xf4ff8750 0x0156afad 0x65d31848
+ 0xb90d0084 0x5f8bca59 0x30fe3607 0xf42d02d2
+ 0x1a1433d9 0x83e8ac6f 0x580fbfdd 0x621b4f0c
+ 0x8a0384c3 0x8f2bb99e 0xcde8d946 0x656c0982
+ 0x4e6ba947 0x6111abba 0xd2a533df 0x9d173834
+ 0x12ae87b7 0x9c96dcc9 0xcb38017f 0xcfdb1a79
+ 0xa812fa65 0x7e94957d 0x448b6e54 0x951db061
+ 0x95413429 0xa9b8f2a2 0xed53849d 0x0df306e6
+ 0x47ad8eee 0xc89bbc9b 0x2c812451 0x8a8cd47d
+ 0x7f6fd5e3 0xac4f541e 0xd0141031 0x1bc101b8
+ 0x445eabc8 0x8812e01f 0x1972aad1 0x490e0983
+ 0xde196258 0x8a1f4280 0x7d4bbc9f 0xd8828045
+ 0x6d0b5f9c 0x99300545 0x2245bb3d 0xa6212403
+ 0xa16fedfe 0xd14bf451 0x26146824 0x56fb7edb
+ 0xc569ab9c 0x3ee4ca51 0x4769b0c7 0x9702340a
+ 0x81477a5c 0x5e5e2b00 0xecdf796e 0x1b71f918
+ 0xeb7b0bef 0x4943478f 0x996aa457 0x563df3ea
+ 0xc13e9084 0x84a710c6 0x51aae833 0x1286b9b6
+ 0x646e93d2 0x27cdb6ae 0x2c5131d4 0x80331468
+ 0xa2de5ec3 0xcc2f6702 0x3e395dc6 0x06faa48d
+ 0x395bf0b8 0x2ab561f5 0xbf8d67e3 0x8faf4cea
+ 0x51e93442 0xcf47cea8 0xbf63b9ee 0xe927b21c
+ 0x1a03197c 0xec291d24 0xfb8519d7 0x4d955d6c
+ 0x2df0903d 0x5a706cd0 0x61ef0856 0x494d1444
+ 0x86699045 0x067b12c0 0xbe0a1b48 0x234b346c
+ 0x34cd7efa 0x6a4ae615 0xcd91c638 0x954b84f4
+ 0x1a128af5 0xd969cc17 0xf4dc37e1 0xaa5e52d8
+ 0xde59f894 0x0f5a917c 0xb4fb57e7 0x0cab7d81
+ 0x9aac2151 0x4cdbb7c2 0xacd786a1 0x3a7b62d3
+ 0xf240daa6 0xff356dad 0x758d1e15 0x193a13f2
+ 0xee61d3e3 0x981a74fa 0x227adbf5 0xce83506e
+ 0xa1e3af28 0x5d4885c1 0x6c1f694a 0x96986af4
+ 0xe458cbbe 0x91951817 0x854ec652 0x71e35285
+ 0x89afd078 0x26170aa3 0xe65e2d7d 0x457ed03f
+ 0xc2fc1735 0x026e2185 0x7084e0e7 0x118e91fb
+ 0xba85dfc6 0xe658f66a 0x0c19dbe3 0x17dc8f29
+ 0xa75cbee5 0x1ad8e022 0xf5458efe 0xbc5c0628
+ 0x8bd901d6 0x8a986723 0x492e7376 0x7c35b261
+ 0x39d55be9 0x3768fe66 0x7467ae3e 0x2388e33e
+ 0x5b91e770 0x55d12deb 0x2c12b96d 0x82664969
+ 0x6fddc486 0x790b4248 0x0a1a279d 0xd9b92a2e
+ 0xe316f88e 0xf21cc3df 0x51038908 0xb3aecc0b
+ 0x9b4048a0 0x21748d61 0xd65d0a32 0x0ba4dd14
+ 0x51606dfc 0x23715771 0xce5bd0ca 0x26b7d411
+ 0x87029a42 0x3a02968a 0x0b81412a 0x7fbf7638
+ 0x6935a48d 0xd29ddd49 0x5e60b89a 0x498efa41
+ 0x37756ec5 0x7a07ae76 0x60b6cad3 0x521dbbf6
+ 0xa1d46ac0 0x61279e7e 0x28bdb70c 0xdae29099
+ 0xb075ba91 0x6096a79d 0x2bee42c2 0xe2632f66
+ 0x6f63ee5e 0x3c1635a8 0x9cc893f5 0x74fd1f0c
+ 0x0e979de0 0x3cdf28f0 0x5a0f41c5 0xdad09973
+ 0xc57f47f6 0xdde7dd76 0xd05965a8 0xdeadd87d
+ 0x1d87a754 0x5513a4c6 0xbd5fef6b 0x0d649214
+ 0x5b36915c 0x568038c0 0xc775afc7 0x7d32462b
+ 0x78ae7ed5 0x132a1ae2 0x248359de 0x2550a259
+ 0x7ff08337 0x2dd48301 0x7d11da38 0x4076b6a1
+ 0x8d6ac3b8 0x2858fcf5 0x102ba807 0x6508bb1c
+ 0xa5aa0335 0x25d56586 0x53b990b0 0x7e4e4c49
+ 0x67b37e21 0xd4646417 0xcbf0e82a 0xa2eb08a7
+ 0x53761d3b 0x3bc87b03 0x0e8da6ae 0xa867b1b6
+ 0x03704bed 0x5460a156 0xdbc7b432 0x861e76c6
+ 0xd9a25796 0x746ff2ff 0xea2ded19 0xc0c12f66
+ 0xbed173c7 0xcba2a17f 0x073ade3d 0xcd20aa31
+ 0xef12f091 0x306a0d01 0x683ffda0 0x6a4d3ced
+ 0x2f19e821 0x2f220131 0x59c46a40 0x7370fda6
+ 0x6c8268c2 0x82e5ef45 0xd79dee43 0xe7779aec
+ 0x94ed3852 0xed0e12c7 0x6ab12986 0x32d1f391
+ 0x10d545fa 0x5771a8a2 0x0cc7aac1 0x90352208
+ 0xb8f980be 0x39d2c41d 0x60474238 0x54f2ab34
+ 0x29cf4e10 0xf29aeabc 0xf1ab8e24 0x167c2b39
+ 0x83e05ce0 0x12e6ce1e 0x35afe73e 0xd9095f05
+ 0xfb41fec5 0x564488c8 0x94a858b5 0x8e940dea
+ 0xf624ae34 0x85efbb1b 0xcbcfb146 0xb9455026
+ 0xb4e40bba 0xc3195d35 0x1cfa4bf8 0x2d49eec2
+ 0xf6695b41 0xd220af6f 0xfad02fa4 0x8af9362b
+ 0x7d1dedcd 0xc5667cff 0x897bc389 0x831fb846
+ 0x2442033e 0x41ebff58 0x05502fd4 0x43574914
+ 0x58530064 0x11c1e752 0xbbe62845 0xa7618ec6
+ 0xf1627ff5 0xafb00250 0xc3824684 0xee3eec52
+ 0x337942b2 0x7a3a291e 0x857f05f3 0x15719b81
+ 0x66fe3f57 0x88280481 0x5c866ada 0x2c1f07c6
+ 0xcef7155b 0xd3a236b7 0x90c96bdb 0xedebecad
+ 0xc478b1d3 0x75dc8363 0x340738ac 0x4d15034c
+ 0x1cb8e2e7 0x41ab7b1d 0xe798cf70 0x3a33131e
+ 0x6a43e6a3 0x386192c6 0x59693949 0xd6b28e16
+ 0x22468abb 0x6f23eff8 0x22aaa858 0xcfc1443e
+ 0x092215c9 0x894b362a 0x17819cca 0x75eacf86
+ 0x9e8edcd7 0x578501fa 0x888b8186 0x7849f9ea
+ 0x18a5f279 0x1a0608e0 0x3f79a285 0x5a9cccb7
+ 0xc8288846 0x8153e63b 0x06745426 0xfeb7dd82
+ 0x37967ee7 0x6501bdc8 0x2b1303ff 0xf105ea53
+ 0x1afd9ea4 0xd7f0c26e 0xfc9d98e0 0x3adcfa5b
+ 0xb95372a6 0xcf0737ae 0xd6f56c9b 0x3d047e23
+ 0x1742e108 0x730cea46 0xd61b5674 0x1d4a0bf5
+ 0x9f9a0d2d 0x15751fa5 0xd1f78c6e 0xbcbf0f49
+ 0xf02861da 0x75c73284 0x565ac314 0x74f424cd
+ 0x2de2c5d0 0x8b81d64d 0x7da7ed9d 0x0dec53d5
+ 0x119bcb0c 0xe3280bc2 0xb8876379 0x61d9315e
+ 0x76e711d2 0x5f7d25f6 0xe536781e 0x48bb7127
+ 0x0241bdb6 0xa3f5c283 0xa4e289e7 0xb0c00a9b
+ 0x31437997 0x8360ae3f 0xa89404b6 0xb5049139
+ 0xecbe777a 0xd5aae954 0xa7e3497d 0x766e436a
+ 0x00311364 0x09c314f6 0x03f4992b 0x57cf2522
+ 0x717d0b4b 0x3f0c50a4 0x6f2faa6b 0xfdd19e4d
+ 0x136b4811 0x2ec4df6d 0x540e503a 0x4ef99a84
+ 0xe190e376 0x4c6a2b6d 0x898e2adf 0x30816632
+ 0xb595e258 0xe1b16383 0x9a0dff8f 0xed42f0a8
+ 0x12314f07 0x2d51c21c 0xf31c3c3f 0xc112dd94
+ 0x052fcfe0 0xa567c821 0x6892dec8 0x07c26300
+ 0x1799a9ef 0xf2ef0828 0x30cefea6 0x3f6919cf
+ 0x5d3d2396 0xcb2f347e 0xf626b1ef 0x449fbf5b
+ 0xffe2da0a 0x33d5d2bd 0x44d7d222 0xb24a94a0
+ 0x04503d1b 0xde3efdb1 0xb6a30029 0xac134d4f
+ 0xabb57951 0x4f3e6cb8 0xdd738dc0 0x598dd5ef
+ 0x80fdf47f 0x756d4968 0x95449696 0x44dd4689
+ 0x3781c7ee 0x8b3c7403 0x51b86cce 0x90d40f13
+ 0x50296220 0x85637fab 0x11430ba6 0x37b6fe45
+ 0x06923d07 0x75119847 0x2b16990a 0x558a824c
+ 0x4f7ed662 0x6ff01850 0x73301b84 0xa9f8cacb
+ 0xd47591c9 0x239f5de5 0x978dcd1c 0x50c99641
+ 0xc4331a17 0x9c42adda 0x33adb88d 0xf278e923
+ 0xe4f30829 0xe505a03c 0xd83ee3b1 0x46bf73fa
+ 0xcfd0610b 0xe5904ea6 0xf1aef3d8 0x4f38284b
+ 0xdc0ae0bb 0xb63412e0 0xd871cbc5 0x95e54457
+ 0x4e6b6ee0 0x796e632d 0xb02c54d5 0xff6e3a26
+ 0xcf25f241 0xa264f1e9 0x9c4c5a83 0xe8c67201
+ 0x8a54d34c 0xefeef65e 0x224eda49 0xb66a6c4a
+ 0xb7947d42 0x1b9cc0c4 0x18f24b32 0x265ba45d
+ 0xfe433ce5 0xc878de4a 0x66239035 0x3e55f422
+ 0xabc11200 0x5b3ceeb2 0x79972610 0x13b5b5ba
+ 0xe0ec8eca 0xf5f2a0ee 0x98bf92e3 0x5bd78dbb
+ 0xfe01740f 0xc089bd76 0x033dc19b 0x43d76143
+ 0x34ce988f 0x57c18ffb 0x73d1ddb2 0x051a4e3d
+ 0xc635e701 0x4a0ddefd 0xb10b6cda 0xabcccffd
+ 0xbe1055e2 0x5ecae7cf 0x880329ec 0x7590ea81
+ 0x967cc129 0x78faa2e6 0x7e0f8e38 0x222bd775
+ 0x31943949 0x8c5e77ef 0x9fa68d99 0x5d90ff61
+ 0x62b9de80 0x8f42ed5c 0x907a18fc 0x851b4e2b
+ 0x46992571 0x0a2b6586 0x938b91c8 0x4475b4f1
+ 0xefdd87e5 0x28c7339f 0xadc025bd 0xfe9a46ef
+ 0x96b62846 0x9600fd60 0x8d30853c 0x5321f086
+ 0x51504b37 0x70f70c0e 0xd3c63718 0x4ee48d14
+ 0x0f42ece6 0x4c7788db 0x8d0838d7 0x487d073f
+ 0x3c0c9a41 0xb02bd044 0x8509af73 0x6dd6f7a3
+ 0xb0fb556f 0x92c15d39 0x35c3dad0 0xcea85451
+ 0xc7d26893 0xd59a4be3 0x24c3b5e8 0x20ae4992
+ 0x46fdf7ed 0x237c7116 0x6cf591ab 0x069f6538
+ 0x0c1b1441 0x3b5be741 0xb410ff01 0x20d511b0
+ 0xf2c96bda 0xeed21dc8 0x2a3602ee 0x08f774b9
+ 0xf77317f1 0x788a9067 0x70907446 0x16affdee
+ 0x999869fa 0x4d164296 0xab34d654 0xf7992cf2
+ 0x676ec9ef 0x8e9b8b12 0x33ae21bc 0x1971e43c
+ 0x28880c9f 0x1a62e925 0x76dc574f 0x15765e0d
+ 0xe41a9f10 0xa7bfa8bc 0xa6a68542 0x5368b186
+ 0xe235e3d0 0xc89c2aaf 0x2644f5e8 0x577a3fc5
+ 0x0529603c 0x77c89615 0xb89aec94 0x9c8406a1
+ 0xa340c976 0x343625f9 0x2e6031ea 0x2202e06e
+ 0x97d888d1 0x1902d335 0x86c3b9e9 0xebefbeab
+ 0xd0732d32 0x8be1ac34 0x4289df13 0x4f44a9fc
+ 0x0871780d 0x413a895d 0x893db7cd 0xb58cabf0
+ 0x8a20ff00 0x6529c6d3 0xd6d22f25 0x4cf7c2f8
+ 0x427e50d9 0xaec1c707 0x91695339 0x711708d4
+ 0xdfdd7fe1 0x5e9df851 0x65722a04 0x05d8da5f
+ 0x27c91699 0x1efd60c9 0x940a132b 0x7ea2851a
+ 0xd9fd9dff 0x0a541bbe 0xc0d63c35 0xc12929b2
+ 0x33610416 0x502b2626 0x5228b15b 0xd94d4b35
+ 0x14c0b45f 0x64ed4b0b 0x78af7626 0xc2e9046f
+ 0x7a12f190 0x42beb256 0xaea48841 0xf0e790d7
+ 0x72973deb 0x11cfeefb 0xba5cd0e5 0x1a1f41a7
+ 0x65c06ace 0xac49a1f8 0xbbd82cf8 0x415035e0
+ 0x33ebda26 0xc908a605 0x8dcf8b85 0xd4569ab9
+ 0x2e5f7de4 0x2d0a3ced 0xe7c29493 0x6fb32111
+ 0x71f9535b 0x63cef544 0xc2215455 0xb1574011
+ 0x17b0b0af 0x4c9436d5 0xb16fdefb 0xe33c66aa
+ 0xcc2e67f6 0x10f09eda 0xd46e0144 0x99dc690a
+ 0xdecf7f81 0xc421b916 0x703e1199 0x6e074b90
+ 0x259fcebd 0xb4e7dbcb 0x4045f119 0x4034d34f
+ 0x0a52aeeb 0x0f8e2b36 0x3ddaede3 0xbd012dd3
+ 0x7fdef8b3 0xe0071859 0xfb279d23 0xa8eff030
+ 0x30e2b0a6 0x7c50a0c6 0x97dd696c 0xee072f57
+ 0xe45d0547 0x3a4a96a7 0xc59bfeb4 0x37e4449b
+ 0xb165ce74 0x2939ff17 0x2c16376b 0xacde50da
+ 0x3e57b316 0x589a14a2 0x8ed5557e 0xfd6bdf76
+ 0x57348636 0x77df0b9d 0x49e6e4ac 0xe9a3ce3f
+ 0xc1b06ddd 0xaa5111eb 0x748a53ae 0xbde72bb6
+ 0x7b2d7f63 0x7ed5bf06 0x98389845 0x17c8d9a3
+ 0x4cace2c0 0x441e3441 0x67eb5256 0x59e7cd3d
+ 0x46ffac59 0x8bd74b6b 0x09abf015 0xdedf14a6
+ 0x92ed879b 0x116b4a44 0x471ce853 0x9c649ad6
+ 0x9f1838c5 0xc4beea8e 0x747900dd 0x48ca9e9e
+ 0xaeaf94fa 0x1c03c132 0x44662d4f 0xa537d972
+ 0x589a90fa 0x57332041 0x2f8349cf 0x64364c6d
+ 0xff5f1aeb 0x681dba1d 0x4eeebbef 0xedade9ef
+ 0xcb938dfd 0x0164c6d7 0x13b9bc03 0x18b407e9
+ 0xb298e043 0x9b224562 0xb645ffd8 0x5815aa44
+ 0x4793d73d 0xb56f0e9f 0x8c9044d7 0xe41109b1
+ 0x2710c352 0x4b7dcbac 0x38f754b7 0x3c6cf465
+ 0xb54ee7b2 0x856a179e 0xe86338dc 0x1e7e2b53
+ 0xe89b7e12 0x15c42976 0xad7a65ae 0x0d8a7cc3
+ 0x4bc02b15 0x517a40d9 0x11c81722 0xb2bff7aa
+ 0x0ba28f37 0x6c9e84b4 0xa1de9a97 0xdafdc842
+ 0x418082c7 0xac99eb05 0x440d81bc 0x0f8281e7
+ 0x62386c2a 0xe9772f62 0xdc79a423 0x09b53e98
+ 0x84c3c90f 0xca17ba91 0x1c6389ac 0x873c14d9
+ 0x2c259be5 0x1cc07fd2 0xfec486d5 0xc24694f4
+ 0xdf474401 0x7be2a72b 0xadb66511 0x81209edc
+ 0x62da35e7 0xcb368410 0xe80b6818 0x26cf9c82
+ 0x321e312f 0x9cc8a82b 0xbf9ebd18 0xc598d6fb
+ 0xc21858cb 0x6dc72a46 0xe44aa56a 0x82fbdec9
+ 0xbd732010 0x6975adca 0xe5ddf36c 0x72bedc92
+ 0xde4c0ccb 0x9e6e20b4 0x6bf5ce44 0x0a6eb5d8
+ 0xa439cda7 0x055f776e 0xedf823ad 0x298c0f7d
+ 0xdd6c8d9c 0x066e9378 0x86847ddd 0x151bda4c
+ 0x61ec7724 0xbf3de534 0x64d80341 0x9c608f22
+ 0xde5d94a9 0x7423895b 0xadfe2881 0xc7acfc0c
+ 0x7ff035db 0x42c2ae6a 0x0cd9e52e 0x425bf47a
+ 0x41cb2f2f 0xb0d034ae 0x1cbc0c50 0x9ae9ee61
+ 0x40fd456e 0xcc5ddf76 0x3e5c52d7 0x4f7e55df
+ 0xe88c725f 0xa38d12db 0xa63d5340 0x7a65f347
+ 0x5d8e6ed0 0xb6140480 0x1d038fd8 0x32041136
+ 0x1c45b5ee 0x5100ab0e 0x98473545 0xa92e7dab
+ 0xbddefe68 0x6eee94c9 0xcd046fd5 0x9269ca4c
+ 0x9244ed01 0x68b9272c 0xa2abf1f9 0x0c5eb602
+ 0x3cee855a 0x8d449506 0x968687a8 0x69fc4521
+ 0x89fb7d41 0x82d335c1 0xcc7e2c7f 0xdbdc20c1
+ 0x5adb4bc7 0x429ea826 0x99c6d2b9 0x8f684704
+ 0x53361f81 0xb8c4a550 0xd079cafa 0xe28fb54a
+ 0x170c157f 0xe5faa727 0x9d37b6f8 0x7a0f88b6
+ 0xdad0aa7d 0xe6eb4a39 0xa8391bbf 0x912bd27d
+ 0x7676a2c9 0x67ebb91d 0x4f090fec 0x4148f1c1
+ 0xb8456040 0x56befd92 0x9089e3a8 0xc2568a9d
+ 0xeb649427 0xd904af9e 0xf99984b8 0x4467144f
+ 0x79efc76d 0x75589aec 0x9f168b29 0x4c048855
+ 0xc0fd5d25 0x4a58fa2c 0x31b194c1 0x8a801969
+ 0xd5e0000f 0xa2f9f4e8 0x8591ac20 0xc0fe5118
+ 0x5b7f969f 0x21a9dff2 0xbef3c51d 0x51873dda
+ 0x207120cc 0x690d99c9 0xd532b33d 0xab0d4ccc
+ 0x7452bd5a 0xa17f7858 0x5289f83c 0x7d0e053a
+ 0xd906a982 0x6778d47f 0x005db3a7 0xe88104e2
+ 0xc52df471 0x44db6099 0x995d4c1f 0xeca903fb
+ 0x3eb38a46 0x3a656171 0x24945ee1 0x35439de7
+ 0xbf95525d 0x9b4030a0 0xb518b00a 0x137ebe42
+ 0x0997e7a3 0x1f344a83 0x00241146 0x40e74f33
+ 0xb1cd34d2 0xfda51a35 0x7cc94789 0x2cc46a7b
+ 0xb966a92b 0xdc8f9838 0x2a2fc869 0x846778b0
+ 0xc2ded51a 0x88000d7a 0xc6d1a90d 0x2e4c17a2
+ 0x112e4409 0x489edcfe 0x5be08376 0xf004d962
+ 0xe26e28db 0x4ddb374f 0x6801cce8 0x35826ef1
+ 0xeb3b8c3a 0xf209ce2b 0x728ad017 0xac4e76c3
+ 0x721ad4c1 0x67da600f 0xeb8fe821 0xdecace00
+ 0x0c355770 0x3d28fc3c 0x2eebca24 0x4753b9cd
+ 0x0b945832 0xf4120f6d 0x588409fb 0x15a94438
+ 0xa727a943 0xa95217fd 0x0ded75a8 0x1a556482
+ 0x767d35c3 0x9d96d689 0xe8c6df73 0xbf229244
+ 0x12bf8389 0xd5dc4782 0x2b2bba74 0x53a49a14
+ 0xffa085b8 0x314087f6 0x3e036542 0xa9517e8c
+ 0x6b6da9d0 0x15dd4ae0 0xe7ce03db 0x7abff8e0
+ 0x89fdc6ab 0x28ed5196 0x8c79b0d9 0xa80f7919
+ 0xf121a584 0x9809d3e9 0x83cc73dc 0xa4e51962
+ 0x370d9307 0xda518436 0x5ed4c7e0 0xe024a1ea
+ 0x0c524b24 0x3bb0bbc8 0xb4cee95e 0xb2622308
+ 0x1fc85d64 0x1e836175 0xd43fdb9a 0x39d05c71
+ 0xf8bcc9fc 0xd33a53d7 0x9c4d3858 0x2fa63ff2
+ 0x351e8720 0x32419c0c 0x8fe0b68d 0x326a8a91
+ 0x44625b27 0x52b2716c 0x22eb5861 0xe1a87187
+ 0xf5ff95b5 0x0e9a42c0 0x3700221f 0xda6c81dc
+ 0x6ec82ed7 0xebbc013b 0x907b528e 0x71222e15
+ 0x17bf4813 0x9d8577e3 0x325ad1bf 0x2f98087e
+ 0x6656baa6 0xf5bd91a2 0xe5bf2aba 0xc2e16644
+ 0x8fb13479 0x0a19eb78 0x80cab720 0x02889d26
+ 0x81d32f06 0x666bed5c 0x58aba47e 0x9f36ec4e
+ 0xa6f8a312 0xd50dfc50 0xda6ee1c8 0xbf2dbd1e
+ 0x6dbe34cb 0x2ee1459f 0xaf3ba125 0x69453966
+ 0x0cf984ef 0xbee72495 0x9e1befb9 0x9785668d
+ 0x7861dc74 0x16dd92c3 0x9c39366d 0x376b20bb
+ 0xb08d0942 0xd2415614 0xb5eeddaa 0x92f148b3
+ 0xc1fdb0ab 0xa64e8a08 0x11e6d898 0x7e345541
+ 0xd7d875a5 0xd396f516 0x8cdf8a23 0xb324f279
+ 0x07382961 0x35e5b607 0xff378354 0xa61e6e1d
+ 0xe7b6830a 0xe4022021 0x7230e616 0xe113b776
+ 0x595fc933 0x7052027b 0x02525cc7 0x23637336
+ 0xae0dabfb 0x46492daa 0xb57f5cc3 0x7f8ff15a
+ 0x70126d10 0x6a6b896e 0x330654c5 0x3680f93b
+ 0x04e705e7 0xf89c1eca 0xab401dab 0x7fad939b
+ 0xc9d8900b 0x29ca3871 0x2931e4be 0x26d73a89
+ 0x74c2602f 0x61920680 0xbf532c23 0xfbe87348
+ 0x5ee7efcd 0x8228b6e9 0x404e6492 0xbd577535
+ 0x1ae12b2c 0xff26b6cc 0xeac396f4 0x04102950
+ 0x28a698a1 0x26ab1d9a 0x06f0e8d1 0x82eba335
+ 0xbace28f5 0x7f7efab6 0xc9ef2555 0xc5b33992
+ 0x74f481eb 0xcfc2a96b 0xbcabf5cb 0x118a80c5
+ 0xf815ac13 0x06da52e5 0xd70f8c6f 0x54af4177
+ 0x7890b2ad 0x20c1a59b 0x5d1e3c26 0xb0fdd3aa
+ 0x53b8120f 0xfff85542 0xfa402307 0xbc0736ae
+ 0x3b05c066 0x9e8794ca 0x075af678 0xc540a9db
+ 0x40d0dcf9 0xa9bba474 0xebb1b883 0xff1f4933
+ 0x97a47b97 0x321b2d6b 0xf01a64f1 0x7d571e58
+ 0x8889079e 0x86077eb3 0xe9f91569 0xdf70fe84
+ 0xc6bb5b9a 0xf648ed36 0xb75c1714 0x0438e727
+ 0xb30d2344 0x6e972d08 0x45164e18 0x3b325aa6
+ 0x5fb60f83 0x8e836a45 0x55a693bf 0x704da46a
+ 0x0924a501 0xff86991e 0x55bef546 0x9f8b4aa0
+ 0x91574c19 0xa3e712de 0x4f9c39a5 0x227962ec
+ 0xaece98a3 0x717c7193 0x8bebd8ee 0x8a63eed6
+ 0x8907428b 0xd6293e59 0xc4b12c7e 0xc8deb375
+ 0x686f9d67 0x141838c7 0x45e4c565 0x814d20e2
+ 0x140103b1 0xf88b55c4 0x8b128c94 0x449cd74c
+ 0xe4ea1fff 0x9432845f 0x8e700f5b 0x148a70d1
+ 0xd0d20a83 0x5422d311 0x4b2562fc 0x0002e6f0
+ 0x624bce41 0xfb72d76e 0xaec8229b 0x8511a0e1
+ 0xaf3358be 0x23161922 0x7e4a88d4 0x0792e30e
+ 0xc29c52b8 0x0ee24229 0x9ec21326 0xa53a3904
+ 0x0a3c0eb2 0x973b1d25 0x02884f03 0xcdac8153
+ 0xa8f17003 0x2ab6a386 0x59057b41 0x2bc5d886
+ 0x86e91ce5 0x7211383c 0x06e20628 0x09361cd9
+ 0x8128d9d9 0xc21195c0 0x43f63562 0x46d05de0
+ 0x7ed2ef09 0x65ab5805 0xb6963bee 0xa1873132
+ 0xf9998e7e 0x84ff6a0c 0x00fa22b5 0xc84432c6
+ 0xae963ba5 0x80660ec9 0x2c25ca27 0x17b0b858
+ 0x935459ff 0x6dddbdfb 0x418d3c0f 0xd3c6b5af
+ 0x1e19e0a1 0x720d5e50 0x0ec48992 0x577c29ff
+ 0x5837580d 0x0a7bd481 0x3f13a685 0x96b9ef69
+ 0x977ead5e 0xa3e4ae2b 0x96f97a6f 0xd93d0904
+ 0xdd5128c5 0xd2a00577 0xc1e6b315 0x175f49e8
+ 0x79a4afad 0xa6d864a3 0x98d68c49 0xc54d1d7f
+ 0xa0031e9f 0x82580ab0 0xe8567a5f 0xd853d485
+ 0x0704e3ca 0xd8afbd7c 0xfe0ab692 0xa8dcd22e
+ 0xeb7f1064 0xe565a37b 0x0f429464 0x94df9a46
+ 0xb4a43a3a 0x85e7520a 0x828f17d3 0xe404df1c
+ 0x02a24101 0x107347d3 0x64eb1552 0x127f2f6c
+ 0x8722ba2d 0xb0e56339 0xf9ea6f68 0x80a535ee
+ 0xbbc273e7 0xaf777c05 0x8638b501 0xb855c346
+ 0x3c0a200f 0x280d2842 0xf727be3e 0x9d322582
+ 0x71cf64f5 0x8ac26843 0xd4e8cba9 0x41b357d3
+ 0xbdcbde9e 0x606b63d5 0xc793a0f4 0x729b875a
+ 0x6a8f1a7a 0x5e0c326c 0x40780713 0x0ae7bb36
+ 0x84184229 0x583b1e87 0x2c931de0 0x34d75344
+ 0xd38c92ef 0x6a90cd78 0x4442aa32 0x48ce80eb
+ 0x7419f27d 0x1f6971c5 0x94f2a389 0x38c4009b
+ 0x3b663629 0x19adf150 0x8874214f 0x08a52607
+ 0x946fcf9b 0x27c2cbaf 0x2969f147 0xf8fa352c
+ 0x5422ac80 0x732d4b75 0x9c44517c 0xdd5e855e
+ 0x24325f35 0xb56ff386 0xf2eac65c 0x09382b69
+ 0xd6d63436 0x00b3471d 0x9cc6bb3e 0xd64770bd
+ 0x4fee58cd 0x400cecfa 0xc9bbf876 0xaa4becb4
+ 0x65d693d3 0x4ebd85fd 0x5274bf54 0xc28419ef
+ 0x019bd1ce 0x8828234f 0x2361215c 0x9c996c26
+ 0xde0560da 0x3be8a4c3 0x63f1a25b 0x1f3db503
+ 0x433fcba7 0x27bdf9db 0x9e75e926 0xfa9a0c86
+ 0x93144220 0x7b5c5dfb 0x831b0bba 0xac237612
+ 0x9125e97d 0x18bc3d44 0x187e65d6 0xa7f1e29f
+ 0x4949a362 0x49490a5b 0x9fd7f5c9 0xd4aa1ed0
+ 0xae02d433 0x3c8a1c45 0x74aece0a 0x9281873b
+ 0x74d67c84 0x7c3ce8bf 0x42d390b2 0xe1b67960
+ 0x924c912b 0x39db2dd8 0x0fc0daae 0xefeb1793
+ 0x86933e2a 0x79dc30d5 0xd6093f15 0x69c3e88d
+ 0x4b4f4281 0x5aa01736 0xc6d4be3b 0x9e961328
+ 0xe7c9d7f3 0x4cf1cfe3 0x2b7d0cb1 0x018e150d
+ 0x15780565 0xf076db48 0x63c70787 0xcaa9d201
+ 0xfb417ce2 0xba23b25c 0xc54e1651 0x9bf2a3c8
+ 0x8bed1da7 0x842a94a0 0xd5a7eb11 0x06913cbd
+ 0x4620eb05 0x76076fe6 0xfe87a105 0xcac81f51
+ 0x9ddeec05 0x83ae9c88 0x682fb66e 0x71f2eabc
+ 0xbab703ff 0xab9d687e 0xcbe35917 0x5976ce5e
+ 0x0ef568be 0xdd8a23ab 0xd1b94ce9 0x14d47a65
+ 0x0a21b6d5 0xb2cabc60 0xab6fbe1d 0x55ffee0f
+ 0x59509606 0xf353d47c 0x83ae774a 0x3666736a
+ 0xf5fb86ee 0xa1aeb0da 0x1d826dfd 0x873340a2
+ 0xc1ea76d1 0xe05c76af 0x2ee20af9 0x27a1d100
+ 0x9c4a42cd 0x0c44fe38 0xeff8de27 0x05ca0de9
+ 0xe95f6fa1 0xb7bcff23 0x5c523206 0x4f31cdc5
+ 0xbfe4910d 0xb1b1c09b 0x7f947c52 0x5cf70669
+ 0x5be2fccc 0xf0f52eba 0xf8891b30 0xdbcd2578
+ 0xed18f963 0x6953d3f0 0xdbc69319 0x4ac03f2e
+ 0xbb073adf 0xbac8210e 0x3f7454da 0xe250ff05
+ 0x53fe6a2c 0x9b096e66 0x0c2b33be 0xc9a66cc8
+ 0x25fdfa7a 0x211597d8 0xdac355c6 0x3b0b8086
+ 0xe1cb957b 0x34ead4b4 0xaaaace1d 0x45470209
+ 0x4afe8bab 0x1f383d95 0xc4eb5e38 0x3a4adec6
+ 0x9b68485d 0x0028ac74 0xc892a7ae 0x112963c8
+ 0xedfbfd1b 0x9bc2a1e7 0x77e86452 0xf7285e2d
+ 0x5165641f 0x0be144bb 0x26f32616 0xa889df07
+ 0x8de11d0c 0x1ae8026b 0xa40c0afc 0xf66e6b1b
+ 0x2f3a3959 0x0f96159e 0xd383fa2c 0x6d8ac6f1
+ 0x77e3e042 0xe9d05a47 0x3483a623 0x0e13671a
+ 0x8afb2f74 0xad1ee74c 0x2008e340 0xf5b7fe4d
+ 0xbd46ec33 0x4cadba9a 0xc86ee5e5 0x12a441bf
+ 0x8700bd26 0x1677d9a5 0xbb5299a4 0xc03f06ff
+ 0xc015876d 0xdf3ae9d3 0xebafa8c3 0x7407fc93
+ 0xc13c4432 0x5263ee0c 0x85b4cb87 0xe95c88fa
+ 0x812ba6fd 0xf117a989 0x82a07176 0x1051b99f
+ 0x3998d57d 0xa182e824 0x26d164ad 0x47244eca
+ 0x436b2d02 0x5690b951 0xc4a2b7e5 0x9c3f4d63
+ 0x9d5771ca 0x74bff8cb 0x3063c36d 0xc6624e63
+ 0x93cfbdff 0xa392d1a7 0x8917d687 0x542dca54
+ 0xf930db3c 0x530a62e0 0x6c3139ca 0xc733bbf5
+ 0xfa22ff43 0xf91198d2 0x27ebc843 0x6fc4a872
+ 0xeeba081f 0x71d8a984 0x2cbb615e 0x08f28f4d
+ 0x2c242252 0xde7bd041 0x5e337eb6 0xdd6a8653
+ 0xbe10c145 0xfb5c313f 0x9c8be692 0x3e9c4715
+ 0xd3a028c0 0xd87cf41b 0x2d7ce48a 0x3527909f
+ 0x2fe5a866 0xb8d7d44a 0xdeea8a8f 0x7e39ca58
+ 0xaac93e0a 0xec7dcb33 0x0ddf07db 0x024c82f9
+ 0x4c06c528 0xb1c9bbfd 0xdea798d2 0xc0518d93
+ 0xf9309f76 0xe3a80954 0x5f5fc8e7 0xe42ce642
+ 0xc13a067b 0xeae08cce 0xbf7a70a0 0xc23e36fc
+ 0x57b7e071 0x74b9fd8b 0x49cc2ee7 0x566ae6f2
+ 0x1a566458 0x0fba6473 0x207838e2 0xf830c013
+ 0x2ad8f7e7 0x4a962bab 0x5656179b 0x50edfc20
+ 0xd7eceadd 0x19833983 0x0ac98913 0xc78e1e72
+ 0x22626a8f 0x07abac2f 0xbf64e3b9 0xd6e2be8f
+ 0xf3bd33f4 0xc1d727dd 0xe6ab80c7 0xe01d5026
+ 0x0b9f81b1 0x167d09db 0x168f9fd8 0x270f1384
+ 0xeeaf0e65 0x33f0c489 0xd3871743 0xd885ee70
+ 0x49157f15 0x4677fd7c 0x06211cc1 0x4dd6cda4
+ 0x92f0e059 0x8bd2481d 0xf580ab05 0x74cea2fe
+ 0x0972a039 0xe362b4a9 0x18a688a6 0x32eea77a
+ 0xb4b28ba8 0x366b59f2 0xfd04f522 0x97cee744
+ 0x455e8819 0x2db1da4b 0xb2ac81ad 0x85868d24
+ 0x91a9b381 0x2ce1ae15 0xc8261a26 0x3c314755
+ 0xf57d98fc 0xcbc1eeaf 0x26a2423d 0x3e4b57c1
+ 0xd411d2c7 0xfd70ba8f 0x42940578 0x1fffe7a8
+ 0xa34c60b5 0x8fe0d771 0xeae9f523 0x928d2b17
+ 0x6174105b 0x42e3ab20 0xfc8477d0 0x0ff054a1
+ 0x2896b26c 0x33fc61cf 0x5b8097d5 0xafd8a429
+ 0xf18e6b50 0xcdc292e9 0xa2846d37 0x82656479
+ 0x05e34533 0x3cc6434f 0x5a132ede 0xb2b47148
+ 0x2380b9fc 0x6413dca9 0x3609f82a 0xbcfd5ce8
+ 0xa234f6a1 0x70c158c2 0x8d516132 0xf8ffa8b9
+ 0x39629663 0x361d3077 0x54d3a1d5 0x5c78770b
+ 0x0d12c667 0x200ee0a0 0xb4c5494c 0x417161ad
+ 0xd641d326 0x7e6c924e 0xdcb14454 0x52ec57a9
+ 0xbdb8a491 0x214411c6 0x0f7aa41a 0x219a4610
+ 0x77aa93a6 0x9f260e58 0xab671d2d 0xa738db71
+ 0x3b794aba 0xd4d96e58 0xf4234dd4 0x119417e2
+ 0xcc18e115 0x28abe734 0x2e3364f8 0x0eafdb5b
+ 0x9a917e82 0x6c49a8c8 0x41cd3d33 0xd4d4c8dc
+ 0xf2fdd3b7 0x9f033d83 0xc6383f73 0x615ab71f
+ 0xd59d74b9 0xfdb24bd3 0x1a2b929e 0x9850abc1
+ 0x06ebadb9 0x452d5748 0xd4dbd979 0x319b06e5
+ 0x8cda871e 0x4c4d8acf 0xa65d3c10 0xceb80135
+ 0x6362f88c 0x588c3cbb 0xc92e07a6 0xdf156666
+ 0x5776a8dc 0x24615805 0x78a31c47 0x0a8e2897
+ 0x924e21ea 0x3c9e4844 0x8beb8379 0x1a97c923
+ 0xa66ce316 0x19b2520f 0x613db392 0xde86323b
+ 0x6d986a88 0xcaa79411 0xe5236511 0xdcb10401
+ 0x180e3dd3 0xccd3566c 0x34fe6a8c 0xdca4d272
+ 0x7dc2d6b7 0x3445be9a 0x60ab92ae 0x973b90de
+ 0xa0819660 0x3f3da862 0x7f948121 0xe35d655f
+ 0x1f974969 0xd77e51db 0xbcac7e3f 0xc2e5ca0d
+ 0x4a0fa8bd 0x3089fa79 0x5038a272 0x1309f923
+ 0x2e2615f2 0xb1b51edd 0x6c74acb2 0xdc1348ca
+ 0xf72c0596 0x7fc0ff17 0x23d5de89 0xe57f53b2
+ 0xc2c3bd15 0xeb38d68a 0x0f5fc1aa 0x048aceb3
+ 0xaf834119 0xb87a70cd 0x6f55c303 0xe805dc32
+ 0x428f2215 0x8c1fe4a2 0x60f3f83c 0x958b6397
+ 0xe1636adb 0x2d664743 0x407145a1 0xb99881f5
+ 0xe69cdc72 0xf9ea8ca8 0x10990d7e 0xdce842e9
+ 0xf516bbbb 0xa135ecd6 0xadbf1a3e 0x894687d9
+ 0xa7f833a2 0x7c28a41f 0xb2bae9e9 0xb601eb62
+ 0xd15f1fb0 0x812f61cf 0xe3833aa1 0x9dbeef8f
+ 0x44020023 0x8dc8bed3 0x89319828 0xfd2eb018
+ 0x00fedd3e 0x484dfa16 0xf7509751 0x5efe134d
+ 0x30e92cba 0xd3d915cb 0xe2a6ea2e 0x6980c6f7
+ 0xbaa228cf 0x439a0d8c 0xfb7dbfcc 0x482b24f1
+ 0xe7de15dd 0x2fbfba0b 0x32ff4379 0x6d3235f5
+ 0x643c45ec 0x271b652a 0x89e7ff62 0x0ab8b2be
+ 0x09378021 0xce24e1e2 0x6565cf41 0x6f72e9d1
+ 0x8767b9b2 0xa07dee1d 0xfecced65 0xf99321f0
+ 0x8005ef02 0x842d1c6e 0xcd2c837f 0xe3614a4c
+ 0xec977891 0xe632b995 0xbea82e41 0xd31418d5
+ 0x96608016 0xa7ceb9fb 0xb02cb3ea 0xb0343ccd
+ 0xacc278bd 0x142e4f1b 0x3d233a7f 0x4af4c3db
+ 0x85279e02 0xe7b8cf1c 0xfa9bcc8a 0x72b8902f
+ 0x7f45fe1d 0xb2726325 0x9c1d71f7 0x83935b50
+ 0xa136f758 0x396424e4 0x674c2a3b 0xb8077412
+ 0x547677bd 0xc47f916e 0xb4c3357f 0xd1147d60
+ 0x228303a1 0x97d7b3e1 0x355d23a5 0x778f2f18
+ 0xa20d6acb 0x7062246d 0x04aad4d3 0x4696f496
+ 0x1000ac5b 0x5005eea8 0x51a26d3c 0xd782018b
+ 0x65eeee7f 0x4a37d244 0x8d5c78f5 0x4276c06f
+ 0x7b051c97 0x340f3f54 0xc818f340 0xd5436752
+ 0x311d7cee 0x87f1ae54 0x77c99d33 0xcf913f56
+ 0x97a1faaa 0xfe3a1719 0xba390f82 0xb715b00b
+ 0xddfa1183 0xf3af7c0f 0x8601aa46 0xd18e0cbb
+ 0xff036109 0x4985dbbc 0x4ed2596b 0xaa4dc69c
+ 0x707e2300 0x51d4ed57 0xceef773d 0x7b70150e
+ 0xfe007480 0x000041fb 0xc0fb79a8 0x437f1ab9
+ 0x7fb711e5 0x833c06f9 0x064f9291 0xa9c5a76d
+ 0x402383f9 0x9a5b6de3 0x5fdd7c09 0x69c57f17
+ 0x243a4d39 0x4b91a17a 0xadb16f23 0xa95843ba
+ 0x52dc3827 0x5c15f379 0x76f0179a 0x65792a3e
+ 0x5becc4c3 0x879159af 0xdc96e7b4 0x81c96a72
+ 0x9cc3ef98 0xc9a03721 0xb5e0e950 0xba46151d
+ 0x73522da1 0x8e5f8e26 0x0ab8c9a1 0xb9e86fd6
+ 0xb133c5fb 0x0605aa96 0xadd00ab0 0x759b6321
+ 0x7f9d9ef8 0xdb242bb2 0xa4b339ad 0xe332a5e7
+ 0x66d52605 0x3a03f318 0xff0d15ae 0x1db610dd
+ 0xf65b1039 0x97be3c69 0x22a104ab 0x4a6c1b6e
+ 0xc1bc3435 0xd57c4c33 0xec1a3ca2 0x5161f419
+ 0xb2cd0cee 0x71a394dc 0x94c23225 0x42b398ad
+ 0x29164e15 0xfaad2b2e 0xca59ad9c 0x360a976a
+ 0x0c8d7304 0x8fd6ac30 0x684c3d63 0x564defb6
+ 0x265b343e 0x22158f4b 0x354cc488 0xb5059d68
+ 0x014520a1 0x6c493ce9 0x221166bd 0xdea1f9e3
+ 0x2f69ca64 0x9c3ce396 0x7d1a5f8f 0xfd6a57c4
+ 0x8764c0ec 0x41e15814 0x35c1bad6 0x2c539519
+ 0x65087c3b 0xf5b3830c 0xc2bc2993 0xa1b3cf19
+ 0x576391f6 0x5ce0cc84 0xab879f90 0xced4619d
+ 0x19b6bd51 0x355d2c3c 0xa4133356 0x8a0e318d
+ 0x535b8cc9 0x35660d4d 0xbca8d6ee 0x32215f13
+ 0xde46d9f9 0x982ad7db 0x9f7eec2d 0x5282abc7
+ 0xddf348d7 0x43cd6a3d 0xd63c9cca 0x7ca44fa2
+ 0x0bc2f640 0x97498df6 0x30501800 0xd61520cf
+ 0xbe3f76b1 0xa25a0c07 0xaa57867b 0xc0315c66
+ 0xf4310292 0x21811c11 0xebc3482a 0x3a7b6e50
+ 0x9cf2d841 0x92f00e94 0xefba5af9 0x25d2d9cd
+ 0x737be378 0xdce27210 0xdf16478e 0xd9e45484
+ 0xe402d70b 0xd797db64 0x03fe0e77 0xa89c88d9
+ 0x09f22ee4 0x729caf19 0x23290678 0xa4bb622a
+ 0x8730fe6d 0xb71f3eb2 0xb48452d2 0xe6dee29e
+ 0xb91933b9 0x2a4ef477 0x7d5c4791 0x8b35cf57
+ 0x3f1a49a4 0x3f585ea9 0x4d3d06a2 0x3531f766
+ 0x4e9314ab 0x82e165b1 0x9b0493c3 0x898c6db7
+ 0xdb53b9a8 0x266dd07c 0xb2be18e2 0x1ba50fca
+ 0x7cf32c0e 0x227afc92 0x52c76fc4 0xe7f17624
+ 0x0cf1789e 0xb1adfa4d 0x67773b86 0xcd46a6a1
+ 0x3c9ea75d 0x73d3fbe7 0x7b0d0b80 0xe88f3ddf
+ 0x20bd2842 0xb67a3c9b 0x0b3db9b2 0x62fbbdfd
+ 0x76df2365 0x4b2bff0c 0x9c26c9f8 0x26079266
+ 0xfc18b24e 0xc38a4fd6 0xd45ce2e8 0xb30cbcae
+ 0x0f80fdcf 0xf2e8adfb 0x11f4bc7c 0x98102829
+ 0xe40358f3 0x50d35ad4 0x117432cc 0x4e6fce32
+ 0x695d7b3e 0x98d28a2e 0xe570db97 0xc015fd81
+ 0x137f73dd 0xab23d5f1 0x7e8c0e6e 0x72a1a57e
+ 0xe58cfb67 0x604f84cd 0x43ffacb6 0xae73cc50
+ 0xab34f299 0x0b3035d0 0xfe214b74 0xed2a8168
+ 0x3da3450f 0x8e51b78e 0x253e72b7 0x8b620f54
+ 0x8b63af50 0xce340e10 0xbb419809 0x5ba00635
+ 0x42493b0b 0x8ee85bd3 0x49b6a7df 0x808fea2b
+ 0x091c809d 0x0cc496db 0xea6642fc 0x601d5000
+ 0x3589e04b 0x714096d2 0x4e55569b 0x1c45121a
+ 0x04a6050d 0xfd47c074 0x57269ffc 0x3e06836b
+ 0xdf8f7d43 0xab671a69 0x0d0df4dd 0x54a67c89
+ 0x92d408a0 0xf378abb8 0x214d6425 0xd91d7194
+ 0x6dcc9cdd 0x02d27ea9 0xd4d4a4e2 0x7bdf848f
+ 0xaa4149c3 0x9df0d2d7 0x8800c904 0x192fd5f5
+ 0x10dbb590 0x5b8b1e2c 0xd5b5dad6 0x30ddbf84
+ 0x405edb23 0xcb906b8b 0xd9a124c7 0xe7ac7fb1
+ 0x2a7a4ba5 0x90fe1e2b 0xbf9323e3 0x50469643
+ 0x16c8926c 0x6dff898a 0xd56a03ee 0x29ee3e30
+ 0xb1893885 0xdc1e2e0b 0x87cedfd0 0xe458d4b5
+ 0xdb878d28 0xd151d52e 0x6e5aad6f 0x0ccc8b2a
+ 0x5a1fe08d 0xed61dc74 0xa4649fb0 0x670c43b9
+ 0xd7b22c7a 0x4fbfeee6 0x77341a4a 0x28b2f3b8
+ 0xd81079dc 0x9a81c4ad 0x1dcebd98 0xcbee2e9c
+ 0x746399bf 0xf3383a23 0x5c5468e6 0xefadf365
+ 0xc2a7a3db 0x08c1c628 0xf14191fb 0xbbde23aa
+ 0x47f7c782 0x357b117a 0x2c2a92a1 0x87ed1511
+ 0xa8d709e8 0x7de8749b 0x92199870 0xb8017e07
+ 0x481b9913 0xf1a31212 0x5fb4f7df 0x07e246e2
+ 0x274c1754 0x14fc9659 0x2513158f 0x4f8639b4
+ 0xa602189b 0xbc1e3f31 0x311ff0b7 0x5ca7c9e1
+ 0x49747707 0x350cc8ac 0xf6bf896f 0xdc0bc1ac
+ 0x1f0d3ddf 0x21a21a62 0x80711ab4 0x60f70fe0
+ 0xaa5ade5f 0x914eba42 0x0fed2bc8 0xaf4d97d1
+ 0xf294b5ed 0x24ec5df9 0x66db067f 0xfb2b6ce1
+ 0xce42c8b3 0xfb027c19 0x79447655 0xf0673adb
+ 0x72befbe6 0xb25247a3 0x0813dc37 0xe640e10a
+ 0xf45759f6 0x328aee51 0x95d537c2 0xd2de2137
+ 0x30327a18 0x9e934258 0x5f0dfd3c 0x34b88261
+ 0x5ca0fc63 0xd4ff6e27 0x2f287435 0x38be55d3
+ 0x3590bf93 0x6497ddca 0xb48bf82d 0x3aa7c943
+ 0xf705e627 0x2ecefc01 0xe85a739b 0xd91d2b1a
+ 0x178dcb38 0xded1e432 0xe119864d 0xec965444
+ 0xb6866cc7 0x84160d5f 0xa72c6b30 0x78223f8e
+ 0x303132db 0x00f10c7a 0x6238a0de 0x9217bb53
+ 0xe0313377 0x318ebadc 0xf9854726 0x632b2df3
+ 0x16ac7842 0x2c0958df 0x49a879ac 0xc49f1fe9
+ 0xa3e7c05a 0x811e01d4 0x9b11ccf2 0xc32eb57f
+ 0xefdfc729 0x38fb8cc3 0x6781c78b 0xfab82792
+ 0x08da3c82 0xaf0346f6 0x6588d336 0x06ae489a
+ 0xb58419ba 0x771f3fd4 0x53f42a79 0x0653504f
+ 0x93330a58 0xcddab350 0x2d44eda6 0x7860152c
+ 0x63b3e12e 0xaf7dc6f6 0x5cc5ad4f 0x95b9d06e
+ 0xddcfc613 0x84f74de5 0x51694312 0x1950051d
+ 0x62cc7724 0x06742036 0x92e8805f 0x679a3c64
+ 0x87b8f43e 0xce386713 0x5b476587 0x300ca68b
+ 0x7d2fa903 0x552489d8 0x25ead402 0x8d0cc96c
+ 0xb5c5ee96 0xf0b74e97 0x999b0e56 0x217d326d
+ 0x45edc298 0x5d269e37 0xc88487f1 0x27ef568e
+ 0x833ff6a2 0xf832552b 0x5a56b672 0x21379d3c
+ 0x5de123ed 0x1617159c 0x666699f2 0x165b3fc5
+ 0x04a8177e 0x9412ca1e 0x196a603a 0x752d8a13
+ 0x46bd8094 0x200d93cd 0xe6f9002a 0xd2444774
+ 0x29aee76a 0x13d6cb75 0xc947e68d 0xbfea3352
+ 0x2fbbf62d 0x89dad4df 0x0f771fcd 0x2b5c3135
+ 0x658aac69 0xe980266e 0xaa657242 0x8440f399
+ 0x19ac2617 0xe74b3e55 0x9639c72c 0x25bc2843
+ 0xe5428269 0xb06b7e52 0x47e3f96f 0xc3ff329c
+ 0x7e428457 0x3b877e30 0x824d6981 0x8d66bccd
+ 0x3ef8b239 0xb90ceaa8 0x5323ddd1 0xfd9f9711
+ 0x747920e0 0xe64253b6 0x7bd26403 0x1cc2ad5e
+ 0x51612252 0x39d671d7 0x5043d9db 0x4c1d9cd3
+ 0xf1e48340 0xb68e5148 0x77d7ee51 0xb345cb5a
+ 0x639e92e6 0x458cb2b0 0x2cb49fe4 0x01683f64
+ 0xbeae5114 0x20d167c3 0x8439bb31 0xaa11d7f3
+ 0xdb14315f 0xc474fe90 0x2992dc24 0x8ed70fb4
+ 0x73228ecf 0x016c6e08 0x9bf91825 0xa13662f4
+ 0x86a759da 0x0cb6d6b7 0x43d67df0 0x2badff1c
+ 0xd1769bfa 0x0f5aefd4 0xbe2e49b0 0xa6e91ea4
+ 0x046c73fd 0x38b33892 0x37a3ab24 0x30225f43
+ 0xb4e9d784 0x0b8d3c79 0x83411221 0x0080586f
+ 0x0383f4d7 0xb4733a71 0x4609dc6f 0x149e2be3
+ 0x16be8f2a 0x6155a89e 0xdb42ebbc 0x4790004d
+ 0x0b84706e 0x24d8e7a7 0x7434cf91 0x4aa01729
+ 0xb285bf41 0x894256a9 0xc346c2ca 0xcf83c38d
+ 0xd7a9df68 0x61e95cf5 0x05458abb 0x2468d516
+ 0x6cfc6f97 0x06792edb 0x0faec9e3 0xcece2cd5
+ 0xfcc300d4 0x93b52c8b 0xf9f81fa4 0x8a9d62d0
+ 0x94715de5 0xcc4f5ae0 0x724c65ed 0xbc9d2513
+ 0x3ff58f0e 0x2571d254 0x1b2f8fb2 0x593ff054
+ 0x1542e7fa 0x5e2b8733 0x135f62d2 0xe5b8f1de
+ 0xee3852fb 0x9e1bb2ff 0xcfe6ef95 0x85e3d35e
+ 0x5fc2f0e4 0x1e391bc0 0x0c282cc5 0xc14e84a3
+ 0x4a566eaf 0xac04ab06 0x15e9bb8c 0x74a82932
+ 0x615af08f 0x92ca2937 0xa04182e1 0x8964f936
+ 0x9c00cfec 0xf8ee661e 0x60c0bfe4 0x9d1c2a39
+ 0x164f0f50 0xc1cde961 0x1ec2dbab 0x441312dc
+ 0xff8f746b 0x4fd8e2f4 0x7d41bec2 0x610c39b8
+ 0xe54eb811 0xed6eb997 0x6aef9b63 0x2ca1fa79
+ 0x6a0741bd 0x9b323ed4 0xa9e51346 0x4c7c19dd
+ 0x980117a9 0xba0a00c4 0x501e433f 0x3010f10c
+ 0xd7cf710d 0xf03ab992 0xa9df2b11 0x2939a708
+ 0x90182f87 0x2f5c228a 0x7982d287 0x4cc9aa36
+ 0x4db0ac5f 0x2d5eb58f 0x78029b74 0x9e592313
+ 0xac57236e 0xf5d3ba18 0x1310184a 0x0291a22f
+ 0xa2bcae47 0xd4aafc4d 0x50f97087 0x9f428c85
+ 0xe8b1d16b 0xbcf3cc24 0x2febcdef 0x8baaf25d
+ 0x4839894d 0x713618c7 0xc6b4119c 0xa72804f7
+ 0xf9ed3930 0x947ab473 0x52ba8d8b 0x9d3ef240
+ 0x928262f3 0xde8a2e3e 0x0dd1a3bb 0x124cb146
+ 0xbff6b771 0x8768185f 0x9dcfc72f 0xec46ce1f
+ 0x55eb08e9 0xee110630 0x4f1abbdf 0x790d96fc
+ 0x0edeee84 0xf4effcfe 0xf171d08d 0xf0ea076d
+ 0xcfc6bcbc 0x2df2d7a3 0xba1a967b 0x1cea509a
+ 0x1594c0cc 0x08339c8f 0x8633f7ad 0xcffdc9c1
+ 0xb620cf8d 0x3807a89f 0x6b992761 0x222d9a95
+ 0x900f8f87 0x0f085c6c 0x5ce2975f 0xfc2d28e0
+ 0x1f1e2d6b 0xd2af1514 0xa3cc5dfd 0x301cca91
+ 0xb02b1b87 0x070126f0 0xa18820db 0xaeec06dc
+ 0x7f12ad58 0x79c8c8ba 0x173b231a 0xd52de2f0
+ 0xdb67eb9e 0xd50fd00c 0x1767d59c 0xe83c1fb0
+ 0x3d079a0a 0x34aad1b7 0x8e410684 0xd17f51a4
+ 0xadadb74a 0xcc20b073 0xce1fc8e2 0xf9faa5e7
+ 0xf7b96bfe 0xf1dc7007 0xf2a5df74 0x3036f630
+ 0x0fddcd9b 0xd3292ad3 0x2e565365 0xa0bdfdc8
+ 0xcea1dfaa 0xb161265e 0x28e1b5e4 0x6b718da8
+ 0xab2fd7cd 0x06cf49cc 0x00db7d65 0x6bb855c2
+ 0x6c58fb02 0xc34b1948 0xbbb039a9 0x7df185a1
+ 0x323d797f 0x1f21b9d4 0xf63332de 0x03d84887
+ 0x8dacb69f 0xb33e6158 0xf378a088 0xcdf7408d
+ 0x9d54f759 0xc94c5d13 0xdf657953 0x77f8dc3f
+ 0x432fb39d 0xedef8db3 0xd8443326 0xa06eab9b
+ 0x77029612 0xcd729e14 0x3d1b4677 0x07c424af
+ 0xf599ada6 0xb0eb8eee 0xd775afea 0x3013ddbf
+ 0xe9d06eef 0x09600082 0xe8cd4c2a 0xd3ff4417
+ 0xfe29cad1 0x2173b541 0x33585437 0x769344c8
+ 0x02de5ca2 0xf5206b44 0xf3e34d41 0x6deba140
+ 0xa79632c6 0xc9ba3a50 0xb3515fa1 0x9eee380c
+ 0x4ad5290c 0xcb4739c3 0x71da64eb 0xfb559aef
+ 0xa3091f65 0xfdef610a 0xce5412ec 0xcf498deb
+ 0x26e1c1b3 0x2a8fb23c 0x0695459d 0x5a4c277a
+ 0xdd483fbb 0x1a78ddd3 0x24c0c414 0xaa24b351
+ 0x20c848cf 0x94dd1387 0x0fb0016d 0x9e1b83a4
+ 0xafe2c58d 0x596d1cc6 0x42376363 0xa6b0a5ac
+ 0xa6c30abd 0x067d634f 0xf921e454 0x1e86e083
+ 0xb5986bd4 0x3e4e7b76 0xe02427d9 0xf39df942
+ 0x77f82cee 0xd7cad721 0xf884ea2f 0x0247e300
+ 0x4dcfd3ec 0xcd3595ab 0xca789c58 0xfd6f4b59
+ 0xf39a1fb9 0x60d80d9c 0x67dc447d 0xd061e922
+ 0x5c4ddc32 0xd87a0e11 0xec53091b 0x88f73838
+ 0x4a30fbf4 0x77ddf719 0xec903563 0x1103cc06
+ 0x38d36baa 0x6e7822ae 0x7e238d27 0x9f10f184
+ 0xdc571ae9 0xbfe5a7be 0x60796471 0xe7193642
+ 0x8f4932fb 0x3288ea54 0x880b61bc 0x6f5adeba
+ 0x88078ffc 0xf53a7321 0xda5f397b 0x797d53cb
+ 0x170023b2 0x2ae674b8 0x41ed6927 0xfc416bac
+ 0x9517d112 0x8131bc8b 0x9207340f 0x0860f495
+ 0x5ee42625 0x21abd2f4 0x730cc2bf 0xb705d5a7
+ 0xb0ceef46 0xa9e1580f 0x04379973 0xbc2de3f3
+ 0xbbf47518 0x8135e690 0x7dcaa849 0x2d284fcc
+ 0xdb956dc3 0xa01dcee4 0x204879a0 0x25d4ec0a
+ 0xab883c9b 0xf4c98ae4 0xd6ff96c8 0x1c44bb4e
+ 0xefc0ce75 0xa018f744 0xf3b708b1 0x5219e162
+ 0x03c478dc 0x56de45d4 0xd16b9680 0xf3809c02
+ 0x3078072b 0xd1b792b0 0x1dc53f6c 0xf39f77ee
+ 0x74db19ab 0x2d9772bf 0x1d117036 0x8439e76e
+ 0x15550137 0x9378cce1 0xa3007b8d 0x44246b55
+ 0xe27a583c 0x93fbb9d2 0x14b875ab 0x58ba4172
+ 0xf70336a2 0x1a193fa6 0x6edd7c7a 0xf9d7abad
+ 0xce49c41f 0xd59e4f0a 0x87c209a9 0x6c531d65
+ 0x5e8b2912 0x4985e164 0xaa30d916 0x04c7a98a
+ 0x92ec0a16 0xc81e0c8c 0xaa7fbc60 0x73c9997e
+ 0x1080f5ff 0x05824cca 0xa465ca7a 0x4e7aec8e
+ 0x5e230d7f 0xbd80153f 0x2f9fc7a6 0xfdc2e4c6
+ 0x8447f46f 0x2b98b918 0x934e2131 0x89e96a33
+ 0xaafe33c9 0xe821a560 0x3a7c81b7 0x3905eae1
+ 0xec902015 0x8b70db58 0xc6e5cfd2 0xfffeeb18
+ 0x4b79d360 0xb7d2a21d 0xa6742dd5 0xc38a9ac5
+ 0xe4f33f88 0xf7864b38 0xb937ed2b 0x286ea756
+ 0xc7b977e8 0x117abf40 0xc52e4e8b 0xd8423c60
+ 0x4edaf3de 0xca387d75 0xb9fbe5f7 0xda6f9543
+ 0x29684231 0xfdde17b2 0x55d9da3c 0x047472cd
+ 0x48aa5670 0xd0fc555c 0xb694d68a 0x225d0c82
+ 0x65da3f2a 0xa8da5a72 0xba791eb0 0xf6dda6d0
+ 0x6f408fba 0x0f3e53c4 0x42dfdd18 0x83afd9ec
+ 0xc0c28641 0xe9aceda4 0x9a57bb91 0x509ae5bc
+ 0xfab6364d 0xa965bb80 0xed52b4ce 0xa9637114
+ 0x1ba06d2d 0xe2a071a7 0x4f8005f7 0xc01078e5
+ 0x6c8c1b40 0x0d785131 0xf89f318a 0x7a859d66
+ 0xa54c61ba 0xa1ac3829 0x5846abc4 0xa4bbee21
+ 0xc150c513 0xc43e56b0 0x2b9b6c2e 0xbd23ac4b
+ 0xd5bb877a 0x26aab6e9 0x3175a360 0xa417779e
+ 0xceda5542 0xd6ac1111 0x3631f049 0x822d6fd7
+ 0x456b5441 0x14815178 0xf26c6347 0xcb2f0ac9
+ 0x2876a89e 0x5d77052c 0x1dd9903e 0x1a243b17
+ 0xd32ff417 0xf2ee16cd 0x29c1e28a 0xab23c5a1
+ 0x7bf92552 0xb3ff18d6 0x7218138a 0xfc4c7fb0
+ 0x8b431515 0xf42dc92e 0x39c27b33 0x5439b8c4
+ 0xa044cf7a 0x1904dafc 0x8334b7b5 0x5285f6b1
+ 0x64cec961 0x90bca178 0xe3108fb7 0xa0f64d12
+ 0xf1bb4b0e 0xff22ca3d 0x455af526 0x45398675
+ 0xac6db8a4 0xdd6b3cdd 0xd93e0ade 0x6407f4cb
+ 0xe1434f7a 0x5048390b 0x9ecb584c 0xbaabceb3
+ 0x592859c7 0x0b6dbd23 0xf5579ec8 0xfd372708
+ 0x8d306020 0xafda0c88 0xe93bbcf9 0xeb0f3a50
+ 0x8a0e1c30 0xfb926ba9 0xf628b5f4 0xbbef7f64
+ 0x59bee520 0x8c95cf83 0xa9ff6a92 0xe8d43591
+ 0xca0252b7 0x44311a65 0xa90c0287 0xd6769de5
+ 0x647a9d7d 0xb3430eee 0xfc295b9d 0xfaa99965
+ 0xfbc57eaf 0xcd1e38dd 0x4173522c 0x815845c3
+ 0x2146414c 0x5d5c5b01 0x8a309fe7 0x6aa610e5
+ 0xd102780f 0x89e6e565 0xbdac3838 0x32626179
+ 0xa2a55556 0xca7a20a0 0x9e746a00 0x02726584
+ 0x804f9c1c 0xa1edaa0a 0xe2a2ee7c 0xd1c5657b
+ 0xea483c23 0xc6642eae 0x0a85bd37 0xf1f3be44
+ 0xf82905bc 0xe412fc3f 0xf6bf0714 0xf91a7e1f
+ 0x661f92e0 0x7283395f 0xf014d2a6 0x499044df
+ 0xefdc70b2 0xb0f4e6af 0x75ef5398 0x08ecefe1
+ 0x8be7f455 0x29b91faa 0xcd1622ee 0x3b4c3bf9
+ 0xba7b11c5 0x0e4e91ad 0x29af310a 0x774115fc
+ 0x7e6f4914 0x4ba6c995 0x211268e1 0x03b24064
+ 0x558cc226 0x40d503c0 0x2af0591e 0x99792856
+ 0xc5b667cf 0xd1e2cf31 0xdce9955a 0x061782c1
+ 0x82b31a76 0x67bb7082 0xecab8414 0x0b20cf81
+ 0xb8a21305 0x2bc2c62e 0xfb6a7ebb 0x598d2036
+ 0x9f7f9f79 0xad9d6b51 0xa30bfc49 0xfec190dd
+ 0x17fe7e3e 0xd020fbae 0x52ec37c5 0x6d9dfd4f
+ 0xb4d1cf48 0x4d91b929 0x1b3e4116 0x81e109c2
+ 0xe13316aa 0x8b49b605 0xd5c036d5 0x4feae27e
+ 0x452760a0 0x308d5266 0x5af8ac2e 0x519bdab9
+ 0xe2c88a12 0xbfe6a961 0x6e54bc3f 0x8143030f
+ 0x5d47796a 0xe91fa496 0xd80e7e62 0xc5274d87
+ 0xf0f7414f 0xd8a592cc 0x41fbae5c 0xdf848359
+ 0x545f2e32 0x8650dbfd 0x116de333 0x5a013231
+ 0xa9c16828 0xc103b508 0xc2230535 0x7167b332
+ 0x7c0c8804 0x0a4f7a6f 0x3ef1104a 0xfa3401d3
+ 0x042ba25c 0x05716cbb 0x88954de8 0x769902f8
+ 0x93f8369f 0xdce3dc03 0x0f5bd13b 0x3417fbb1
+ 0xe311cf44 0x8b6d116e 0x8a940805 0x53023454
+ 0x2b608182 0x67424c31 0x9528932e 0xb4b69459
+ 0x75308580 0x0d3097fa 0x4381d82b 0x75d297bf
+ 0xda6c7f10 0x6adca79a 0xdd174f45 0x6e237e9a
+ 0x5f17578d 0xea2869b6 0xd4ef7d60 0xdcf1e34f
+ 0x39c0984e 0xca3cbf68 0x2b846994 0xf3c04152
+ 0x58ad6900 0xa27a0473 0xa86814e1 0xb504c81d
+ 0x0a263d9c 0xa21f5bfc 0x3634f89c 0xf2698fcf
+ 0x0f10789f 0x580923ee 0xdd27aafd 0x49334c8f
+ 0x6fc30ea1 0x535b6eec 0x103d548e 0x57681176
+ 0x17152c46 0xf67cce7b 0xc6f1f215 0x763ec7d2
+ 0x66f46032 0x9c7749b9 0x6ba3832a 0x24d788bc
+ 0xcbe6ac21 0x1cc634fa 0x06b8d601 0x68b1c34d
+ 0xef7a7f38 0x92c02580 0xfd5be079 0x67ec014a
+ 0xda6a5b4c 0x9c884cf2 0x2e0cd606 0x1cb05866
+ 0xf333f9be 0xd5585da9 0xedcecefa 0xb0224027
+ 0xb2511fcf 0xab2440e6 0x77414c23 0xdc9263a6
+ 0x25926b77 0x6083751b 0x825d995a 0x10ce9058
+ 0xd91e2b6d 0x76126062 0x5f28b9fe 0x8df86405
+ 0xb6e5bb6f 0x8eceac86 0xd08d074e 0xff4ed3d4
+ 0x5fa5cf88 0x53c405b4 0xc60e7599 0xc07ef3e0
+ 0x4435a7a4 0x28c490fa 0x9140004b 0xdb19895c
+ 0x25d05b82 0x53d58535 0x8a2d6446 0x3e87d549
+ 0xd961b6fd 0x76f8b718 0x6f0fd68e 0x86a7da31
+ 0x4fcac697 0xcb4385aa 0xceca1471 0xc9ea76e9
+ 0x18a36661 0x8da1db39 0x02bdd85a 0x56b5f9a5
+ 0x39bdf861 0x206004b2 0x7a780b2e 0x9512fc70
+ 0x8e128f45 0x964b5d31 0xc60ad183 0x763695fb
+ 0x7addd1a6 0x8efae2e7 0x57b23dfd 0x91cdfc82
+ 0x203aae3c 0xca53b1ca 0x05388d1c 0x3d5715bc
+ 0xba33759d 0x2d3470b5 0x3b36c53c 0xe38fb71f
+ 0x4c37e926 0xcba524c6 0x00d65da4 0x9d0dcb37
+ 0x3a291c08 0x81ee1ef2 0xce1ecb25 0x6e34393f
+ 0x4c7f9478 0x7bfa3437 0x3cf9d845 0x900979e0
+ 0x1ae6a7c3 0xd5b64d84 0x467a16e6 0x489a3fee
+ 0x73f7a7b3 0x29d2d941 0xbbb6cf3c 0x7478de98
+ 0xa4618be0 0xecd3bf7b 0x9ec7a549 0xd762012a
+ 0xbfc200db 0x172876e7 0xe3686578 0x74a03861
+ 0x499dd970 0xb3600340 0x17a21676 0xe4f76eca
+ 0x413c2938 0xa21b445b 0x30e36091 0x095c523a
+ 0xf30af4b4 0x236740c6 0xb6a50c97 0xc285f888
+ 0x5c45b9f2 0x6d2e28a5 0x561afb4e 0x112576fb
+ 0x7740b38e 0xfe3789e5 0x5099bd10 0x8e565b15
+ 0x463baaaa 0x8b712085 0x99fbb7fd 0x8b415a46
+ 0x517c8de4 0xfcc385fc 0xac9fd9b4 0xdb29a377
+ 0x3494419f 0x825386fc 0x6eeaa91d 0x2f48dbba
+ 0x4615049f 0x90530f6b 0xfd2ddf08 0x97ee1b44
+ 0xeea55310 0x6802e808 0x116d9cd5 0x874699d5
+ 0xb9ec222c 0xbbc6e9f1 0x339cda6c 0x32d2c15f
+ 0x10f073fe 0x2c544e3c 0x518503a8 0x24b730a0
+ 0xf252cc99 0x6518b218 0x771d5ff3 0x841cc2cb
+ 0xd3870e5d 0x6b166d5b 0xef10e55a 0xc873d615
+ 0x5531c97b 0x6a10a199 0x63158156 0x40740e69
+ 0xed060c8d 0x37625a2e 0x939ccd42 0xd225f0c8
+ 0x060be21a 0xab542cb2 0x564ebdad 0x6d0e949c
+ 0xc162caa1 0x22560483 0x26ed1b27 0xc8fedf98
+ 0xd7358719 0x7b219308 0x327139b1 0xfb660fd8
+ 0xe2d4e408 0xf9019405 0x38e6c024 0xe6ca02af
+ 0xdaedb8e2 0xa81c4fec 0xa163e63a 0x9469e3e3
+ 0x8bd652d8 0xd9692460 0x61671766 0x566dd7d7
+ 0xd4ea8885 0x9f7c006f 0x963a23f9 0xc2a2abc8
+ 0xe3f08b74 0x3411628d 0x0d5d26ea 0x368aebf4
+ 0xeb8dcadb 0x3573f8aa 0xd23cd73b 0xa9b3c7d5
+ 0x3119a47e 0xa5354659 0x7e375817 0xc7b36bf5
+ 0x70c7ba81 0xda84798c 0xecf9aae1 0x52423bc0
+ 0xb848058f 0x5dfbc1fe 0x4bd58fc6 0x38dffde2
+ 0x8f41473b 0x8f2e8d22 0x5ba888ce 0xe7496da4
+ 0x46ec5aa5 0xbb8cf063 0x9effa0b6 0xa487f166
+ 0x1ceb3e26 0x468aac4b 0xe006c9c2 0x97b79086
+ 0x1e53d58e 0x4ef59d4b 0x4ecfbb2c 0xb6ecbec0
+ 0xc82338ae 0x7db1ab21 0x24d1e3e5 0x04c19de5
+ 0x376f474b 0x6369bdaa 0xd3220ffd 0xc05ee6a8
+ 0x24c3a90b 0x34a6c61a 0x811ce30e 0x4dfe9d6e
+ 0x12a85352 0x38014645 0x1c07851e 0xe9beb298
+ 0x0ed63abf 0xd5b40ba9 0x7f83d8e7 0x7a53ae4a
+ 0x7360dd8f 0x1be62e35 0x5511f901 0xfbb6afc2
+ 0xf788d81b 0xecfb7225 0xacb286fc 0x148e9a49
+ 0xac3ff738 0xa3f93f2e 0x47f89037 0xc3226d1c
+ 0x9d349976 0xcd757aa8 0x2eec4d43 0xdd7e7c19
+ 0xbe13b149 0x60b4013d 0x988966e5 0xa41bd486
+ 0x2a364043 0xb7a77403 0x60188f16 0xd5a13b2d
+ 0xebf92c64 0x8e82daa8 0xa302aa28 0x33bac63b
+ 0xbeb1e4bd 0x27bd0430 0xbd8d35ce 0xd14a8967
+ 0xa7016b70 0x8a6722c3 0x6ff26f0e 0xfa50fc75
+ 0x59e52041 0x339151c0 0x9c4a41ab 0x9edb4197
+ 0x08eb539c 0xc13c7254 0x7fcd3f75 0xb3ac16f7
+ 0x1b15d8cd 0x0505c2f1 0x076a2636 0x1d3bdeeb
+ 0x798f8347 0x70e1fe1f 0xfa8c3373 0x1d26dda4
+ 0x8911d6eb 0xc7278a2b 0x7208b02b 0x028e3adc
+ 0x18f8ab78 0x68377e63 0xd61901af 0x2c2e46b8
+ 0x32b7e434 0x63cdafd4 0x78e918d1 0x0b674143
+ 0x8293d0c5 0x0ea5da68 0x4984eefe 0x9b67e25c
+ 0xf4aa5f43 0x877688e8 0x2d1c032a 0x55548305
+ 0x64ef45d5 0xf73d1301 0x2418537b 0x60c08c65
+ 0x24329668 0xc4ef5f1d 0xdfa2aafa 0x8958d85c
+ 0x9d5924c6 0xfc1c041c 0xf507ea2c 0xf922715d
+ 0x3e895a74 0x1689f90d 0x59da19ec 0xff295078
+ 0x423557cd 0x5902762b 0x7e11ad6e 0x52b10c3b
+ 0xb5d68631 0xe0278437 0xf9b57e12 0xaf124829
+ 0x7e9a1960 0x5f3585f9 0x54dc91e9 0x6d421667
+ 0xbecf1cd8 0x00077b85 0x56c0b10f 0xefe280bc
+ 0xaf20574c 0xfdee86e1 0xf6404d91 0x90bf47af
+ 0xd916e601 0xfb81954f 0xc095cb29 0xf5bec4a5
+ 0xfcef97bf 0xb07e37ee 0x82b6b56d 0x04ea42db
+ 0x60abe29d 0x8222eab3 0xfbbb230b 0x73d93c02
+ 0x40da8a92 0x524ff943 0x78bf83d4 0xe1c37afd
+ 0xa35155c2 0x48329b3e 0xc762a668 0x68b6aa7d
+ 0x41b5876c 0xbf8a8e45 0x3e1a53b1 0x76e546ab
+ 0x79abb608 0x4c0501a0 0x18206179 0x61ef55f3
+ 0x8fa514c8 0xbee9cc2c 0xde6def99 0xdd666c88
+ 0x0b0a5c54 0x2857ceb5 0xceed57a8 0x62d86d3a
+ 0x1bea74c3 0xf35942a6 0x684295f2 0x561a041e
+ 0xf305e199 0xcf0c0f81 0xf9ea7e7a 0x3484577b
+ 0xb3ee4a37 0x02b7863d 0x9cea59bb 0x847f5fcb
+ 0x3903c152 0x05482a5b 0x9ad5099f 0x28dea11b
+ 0x47e3968a 0xf6080cea 0x1a63a706 0x8100411c
+ 0x0227c6f2 0x52e5a652 0x91e7ac8b 0x989b3811
+ 0xe10a5c8c 0x65eac802 0xbebb07db 0x823f8119
+ 0x1f25f0ef 0x47e69451 0x9a6794f5 0x9b9fab61
+ 0x4244a127 0x556c18e5 0xa94651d0 0xbe8a0554
+ 0xedbc5f9c 0x6e8fa53d 0xebe3d4d2 0x91d3194a
+ 0x1ab227de 0xcce6da7c 0x300e6080 0x9c8fee09
+ 0x21baa932 0x2c807700 0x422d0f10 0x2b318ab9
+ 0x45f759c5 0x5f7a961b 0x7e3e7554 0x52651209
+ 0x1e3e9181 0x7c583d7b 0x74bc7215 0x397bbca3
+ 0xc969c761 0x89692bbb 0xffe3e02c 0xb3cbaf98
+ 0xeb9f4218 0x97269337 0x201b4633 0x47bbf0ab
+ 0x954f00f0 0xe50597d8 0xfa30bd0e 0x34f97b08
+ 0xe70230b8 0x5175d237 0xf6f05156 0xc6ef5b9a
+ 0x5d34628f 0x96ae0d57 0xc4a1c34e 0x2883f6b3
+ 0x813ae49e 0xb7afbea1 0xb369902c 0x236fcaab
+ 0x9bd3e129 0x1167510b 0x935bde08 0x74782cce
+ 0x76c4d54c 0x67324fe8 0x20fdf163 0x30edb4ec
+ 0x3baf38e0 0x3338e653 0x632f3e83 0x53754073
+ 0x87587c1e 0x505229c8 0xd84db10d 0xa011f5de
+ 0x89a24ace 0x0ede0052 0x24cb60ce 0xed01cd5f
+ 0x1a5dc2a4 0x40a1c78f 0x08c394c9 0x94e53eb7
+ 0xc36d5906 0x9c0411c6 0xa47e0212 0xb8a09053
+ 0x789bbd30 0x185e99df 0x4e7f5e66 0xea395698
+ 0x5b9185a3 0xb12ef72a 0x3bf786da 0xfcfc87e1
+ 0x706f7e71 0x1defdb8f 0x6209ff4f 0x0fcf979c
+ 0x368d78c3 0x7325607c 0x09cd4106 0xb2b5eacd
+ 0xd91e2de6 0x3b208bcd 0x763aaea6 0xd2e67e50
+ 0xb42c3b86 0x68442e72 0x607c9e3d 0xe50c8c69
+ 0x9b04293b 0xd06db29e 0xd709d11e 0x4d87a088
+ 0xf9d5a59c 0x90e387b6 0x1d6d00af 0x959e019a
+ 0x3fbab7c2 0xbc2d59a3 0x22b7b925 0x5cc6bf71
+ 0x7f4e1225 0x65f80dc5 0x92d6299c 0x464ece21
+ 0xf107bdf3 0x93e265bd 0x596b14bb 0xc3ceeef7
+ 0x4a821410 0x712ab8b3 0x976e8cd6 0x4ea91f29
+ 0x72ce3351 0x4d18420c 0x186fe8f8 0xe1729dd8
+ 0xe5ba8e5c 0x565b6c62 0x38727f8a 0x5eb3ca68
+ 0x82238397 0x6addab1f 0x10ab1bd9 0x55847072
+ 0x2fdf1819 0x48452cc0 0xf52b3405 0x430d0d3c
+ 0xde25205c 0xc928a846 0x8a49a600 0x2e0f347d
+ 0x68dd5eeb 0xb668738c 0x921c4293 0x28d3220c
+ 0xea3a76e8 0x8e56a305 0x6232fe74 0x4002c4b4
+ 0x9452e5a7 0x4a7d0781 0x6208ec18 0x1f223625
+ 0xe16ed578 0x14d4fdf8 0x04d47966 0xe96a08fd
+ 0xd95cb585 0x576321a1 0x00a8c07a 0xf0626b43
+ 0x68e468db 0xe7e333b7 0x5145a525 0xb4a393ac
+ 0xa7d58ab1 0x57d8ab46 0xd3803314 0xd8fa8397
+ 0x73f0b404 0x07af9046 0xd7adc0bd 0x3fa6678c
+ 0xebb05a2b 0x577b2e2c 0x52792d07 0x24abf050
+ 0xe1046a1a 0xda2cadbd 0x9493d8c2 0x4fb41ba7
+ 0x26f3f8b3 0xbfd58a43 0x15f53d77 0x3957de3a
+ 0xf055d7dd 0x1056a0c1 0xcac3f7a0 0xd2433645
+ 0x518c6d33 0x49b3af19 0x5ec8f961 0xfcca0f3b
+ 0x91f9ab7a 0xac41e597 0x8eb537e0 0xc8642907
+ 0xe293232d 0x8853aa59 0x8ac14c3a 0xfd6d1609
+ 0x7989ba9f 0xecec948a 0x89b9adfa 0x2c1a155f
+ 0x717d44ca 0x3b0b4808 0x679e6079 0x7f509dff
+ 0xf46b7089 0xb9b93a45 0x973cda23 0xcb5aeecc
+ 0x8bfcfcce 0xb3a0326f 0xd72feb16 0x1aa69d84
+ 0xd63a720c 0x17917f37 0x6ce5305e 0x1d4be016
+ 0xcd461cb6 0xdeb337c2 0x93f3aad9 0xb4392d5f
+ 0x3794070d 0xf66b315f 0x773ebbe7 0xb49bca0e
+ 0x6399ff52 0x666923d2 0x7da14294 0x62735522
+ 0x607a3e72 0x74cfdf97 0x5120de20 0x87efd2a5
+ 0x42ace644 0xe6bbe848 0x3c913024 0xcbe9c195
+ 0x4cbfab2f 0x283d55c9 0x4124679e 0x9104dd52
+ 0x402353b2 0x1d2934c2 0xd078f360 0x1e612c3d
+ 0x55d7560b 0xc6fa6c69 0x8f3d701a 0xfe8d0621
+ 0xf728b0ad 0x621bc481 0x767c00b2 0x20bd9a33
+ 0x43153fb8 0x1dbaf9e9 0x9aacfe31 0x0c13b370
+ 0x5207070f 0xcbe94b63 0x16107ec2 0x5948fc06
+ 0xac484ba9 0x005295c4 0xdbc6c45d 0x0d0b938d
+ 0x2ca516ed 0x0b0affd1 0x100d782d 0x6b13fe4b
+ 0xdcf4adf6 0xed2d24f7 0x2528f40a 0xae52c51e
+ 0xb4548c92 0x048c762f 0xf4be834d 0x36453c04
+ 0x9d2ea546 0x13b9ee9c 0x018a9896 0x0fa6031e
+ 0xbef7a3b3 0x4abc8aa5 0x78244a79 0xf77d7b9d
+ 0x5ab92df7 0x653ab84b 0xd40e8ad7 0xbfe0f037
+ 0xb08c3f61 0x3511b9df 0x71f4ac45 0x18f8feba
+ 0x14b6bcb6 0x9f7f0ff2 0x0fbd67d4 0x08662b13
+ 0x663606a5 0xcc43f0bc 0x119aba1a 0x6f078180
+ 0x2ee00979 0xf9dc663d 0xcfb6e229 0x59e6535a
+ 0xb9041219 0x5096ef84 0x5a7058c1 0x80841a9d
+ 0x923c2063 0xdce14c17 0x540f2785 0x5789b67b
+ 0x370c8d98 0xd1e83ce8 0x936e3988 0xbce0476b
+ 0x80d96d9c 0xb40fb347 0x7276d0ef 0x34e41df1
+ 0x4dbefc05 0xc0a109ad 0xa8a76647 0x0b324453
+ 0x82a88349 0xaa8619a0 0xc90adf91 0x6db31b49
+ 0x20b8ea53 0x6971e930 0x5ab45e41 0xac318e8f
+ 0xf8440d27 0x6e7b4f5f 0xd641f8cb 0xee4b486f
+ 0x376e4d85 0x40f86be5 0xbcf3fd65 0x711296a5
+ 0x171dc6de 0xd76bb94b 0x486488ee 0x29869fb1
+ 0x0eedf832 0x088222c7 0x79db06c6 0x08093c31
+ 0x78e6af7c 0x7e92a84c 0x5b7af1e8 0x9ed1082a
+ 0xb2cf6495 0xfe566712 0x810f6623 0x06f5b7f0
+ 0x57ef86a2 0xd3d0543e 0x7b272150 0xd4eb6f7f
+ 0x802d6331 0x8566d10e 0x07e3e6fe 0x1447cf0e
+ 0x60b3e885 0xf89a005b 0x37110b56 0x68ae7dbf
+ 0x72f27442 0x3df57b64 0x2fbf6e25 0x7ee42060
+ 0x1415c9a2 0xbdcc37ac 0xf31ae0c0 0x172e8e14
+ 0x8b5d2cef 0x27fe63eb 0xa9219d96 0x429a6e0a
+ 0xdc3f1f05 0xe19d1296 0x36da614d 0x0e9ec19d
+ 0xc66d4ce1 0x291d49ca 0x83a3d92f 0x1d9b06bf
+ 0x733aaab2 0xacf961e8 0x63e9a69f 0xa7a075e1
+ 0x4e23b6f0 0x81cc07f0 0xde10c07e 0xd331c8b5
+ 0xfbf18a1a 0xfc755121 0x886c628b 0x79fea666
+ 0x7ce1bc5f 0xec5b3ce7 0xebd177cd 0x66400f87
+ 0x764b1291 0x5ea94164 0xfc0a0fb7 0x0fa43dd2
+ 0x49235d17 0x37926a51 0x8526a177 0x773fc730
+ 0xa0f54815 0xed6f01a4 0x5bb24014 0x8539b71c
+ 0x132fd915 0x5f000b68 0xc06aff07 0xc8277dc5
+ 0x2ddbbbca 0x3ba503ac 0x63b3052e 0x30b5342a
+ 0x2af7a786 0x09da5bd6 0xe4bec048 0x133d461a
+ 0x795f4916 0x419808e7 0x26261e73 0x56e041cf
+ 0x4dabd60e 0x1831430b 0x2e98bb48 0xfd18b5b1
+ 0x29b89cdd 0x5970a40d 0x6345a28c 0x12843c53
+ 0x2313d471 0xbf22181a 0xeed3b409 0x2b998b70
+ 0x6734d4e9 0x4a99f823 0xd29ee17c 0x2bd55ce0
+ 0x815732a1 0xdebf0e7d 0xee592700 0x2b0e5cdd
+ 0x6d1165f2 0xdd1cb298 0x21d59792 0x29ed1d86
+ 0x838769d2 0x9e571c56 0x488df973 0xcdda2fd9
+ 0xc2aa23fe 0xec54f33d 0x4071d93d 0xd436a884
+ 0xfbacc598 0xec188594 0x2d58f807 0xd77c2f9f
+ 0x4cc2ecdc 0x38b99efb 0x9ad5c2cd 0xcf93ac82
+ 0x19fd53b4 0xc61c4afd 0x9019c128 0xe642476d
+ 0x12975e1b 0x70406aed 0x0bba3c07 0x94944b64
+ 0xf26214c7 0xa8504bd9 0x0e5dd9d7 0x0f0e705c
+ 0xe1d40427 0xcf6ca05b 0xfad2e372 0xb635f645
+ 0xf048ea3b 0x1a39e8cf 0x386a19d2 0x4b495c31
+ 0x10ac1cc0 0xc3b65767 0xf36cf20e 0x5ad6c70f
+ 0x83512822 0xfc78a6d6 0x63f73285 0xbbc3ebdb
+ 0x9fe2c227 0x7b1bae2f 0xae794110 0xe438ab6a
+ 0x368b06a3 0x5d98b357 0xaea10310 0x51de113e
+ 0xa19bf885 0xa46d4603 0x16a6cd3a 0x87d0cb12
+ 0x0b319013 0xed4495c9 0x8710f555 0xe051c6d1
+ 0x6c0d2f47 0x1a09af9b 0xbc5da303 0xb3c33c15
+ 0xb5ab2df0 0x7b1a02ef 0x0b7558f8 0x99faea0b
+ 0x2694715b 0x1e418212 0x28163f30 0x9f842906
+ 0x9ee82eb6 0xdf04c95a 0xf7f3e610 0x873f8210
+ 0xe514e5b1 0x65426e17 0x1bb7426e 0xfbab6b85
+ 0xa08ae8b3 0x854ca95a 0xd0d2d6ff 0x63225f99
+ 0xb961fad2 0x2b4cfa45 0x51dda947 0x67405e3e
+ 0x9617808f 0x4b49c09b 0x5ead3eb3 0x465177b4
+ 0xabea9a4e 0x1e4272b6 0x8e0e4d16 0xfe2174d9
+ 0xa604e462 0x02bae16c 0x214aaa79 0x55588fd7
+ 0xa06c6534 0x52174dd8 0x1ffde727 0xb5cb4ff3
+ 0x58e8e401 0x874ba1fc 0x09f52e68 0xe2ab8893
+ 0x49943632 0xbe02e3ed 0xdade2e8b 0xa5da9671
+ 0x31f393d2 0xfb4f4e01 0x10c03e2e 0x94fac702
+ 0xccdd9c33 0xd51373c5 0x32f67c97 0xf75f6dc5
+ 0xf7c56120 0x429a4417 0xee3533ff 0x6395711b
+ 0x84c30f8a 0x87e400c9 0xdb34cbb8 0x554373dd
+ 0x89c3032d 0xb54a2095 0xbf8ca76f 0x32b9528f
+ 0x45a716a0 0xdabd57bc 0x0b5a9419 0x0607f8e7
+ 0x97bd8515 0x34fcfa92 0x89914683 0x596ce15d
+ 0xa0d16b41 0x0475dcba 0x530d9b55 0xb2f6980d
+ 0xeeb49560 0x9ff9f979 0xffb3b3f2 0xf8dc90c2
+ 0x7df7ec78 0x663f667a 0xda25d7f1 0x4e5e1a1f
+ 0xb8017f9e 0xaaab7404 0x0fbc96a3 0x2e6883da
+ 0x70b4ef71 0xe68fd886 0xbf9813e5 0xfbea41ec
+ 0x0e9c7205 0x4f4324b3 0xe9f241c0 0x59848c26
+ 0xa6c883b0 0x6fed019d 0x3bea1228 0xd636e300
+ 0x6950359e 0xcf52052c 0x1b528057 0x06fe6742
+ 0x04965c8d 0x9a7b26c5 0xc99230d8 0xb579c7aa
+ 0xe24a7255 0xe814e07a 0x76f58992 0xbad495de
+ 0x55700746 0xfaf4da35 0xb5536992 0x1008288a
+ 0xd867fd0b 0xb1c9720c 0x047d6414 0x561bdcc4
+ 0x74e334f1 0xb66a42e7 0xc08e03a2 0x859a375c
+ 0x2d6c3b8b 0x0aa6b45f 0xc97b7c6b 0x5765735c
+ 0x5367cf95 0xd957151b 0xb6354238 0x7c9dbd21
+ 0x97fbcb95 0x110361bb 0x2394edad 0xbf8e18b3
+ 0x2d4d9bd2 0x24b42b08 0xace76b11 0x2b8fb939
+ 0x04105821 0x79af703d 0x434c240e 0x2a019bf0
+ 0x02a38fc2 0x9c640e05 0xdde8995a 0x3b8c0b1d
+ 0xb44190f0 0x3c84367d 0xdbb9bb01 0x27c42ea7
+ 0x87f24ef1 0xc9abb097 0xe4df5c7b 0x45e04755
+ 0xe29ab2aa 0x29be8522 0x4efa4f5f 0x2b4522d2
+ 0x67f465fd 0x4171364a 0xd2bed8f0 0x477e8b5c
+ 0x982c0339 0x48fcc0aa 0x06206cf1 0x4c132f24
+ 0xc2a78b32 0x18a3806e 0x84551ba3 0xbc8dab25
+ 0x3cea4ede 0xbe3cb62f 0x7be253ed 0x828e2dca
+ 0xae76b847 0xc018fe6f 0x09e3d2ab 0xfd775e4c
+ 0x80f2595b 0x1a1d440b 0xc48f9889 0x52d1cadb
+ 0x99fd2c1a 0x3d700d86 0x079d1761 0x6811c4eb
+ 0xcc2f677b 0xe5422423 0x11a606e9 0x3fd6ea3d
+ 0xf9ae700e 0x09aca633 0xa7097790 0x5db8d41b
+ 0x34941e1b 0x3fc50d4c 0x2fd2cf3d 0xa60aa40a
+ 0xed6381c1 0xb192e754 0x3248af41 0xe0cc843e
+ 0xef3c9504 0x3712da7c 0x9fffb613 0xdef40782
+ 0x86f9bd62 0xbd8a3260 0xf6dcbb87 0xf9a264e7
+ 0x3bb46aee 0x6f92d88e 0x6b0861e4 0x5ab7d4cb
+ 0x2f1cf740 0x8213ac78 0xa34f0812 0x4d7db7bb
+ 0x20d1abcc 0x9c519247 0xbc708c1a 0x66871981
+ 0xc436271e 0x88247723 0x2996c404 0xca9c48f6
+ 0xdcea7c3d 0xf6cdd451 0xbab6a23f 0xf064060b
+ 0x3c0d3775 0x3a7ccc2d 0x5d056c98 0xa6521199
+ 0x7f3b8753 0x3ca8407a 0x3097264f 0x60c75837
+ 0x96e43535 0x5d17c5bd 0x89bb2825 0xd35fac11
+ 0x1c323feb 0xe8fd05e7 0xcad8184e 0x23456746
+ 0x6e4f1d7d 0xfbfada38 0x20faac8d 0xdcedab37
+ 0xf094bd0c 0x7d4e750c 0xbd7ef698 0x0125c05a
+ 0x17d840cc 0xf44bd1bc 0x236e7f10 0xdd53c6ac
+ 0xb0bc6a1e 0x019b1a51 0xfd99d0b1 0xb723b517
+ 0x728e0e9f 0x4280e2d0 0x8da35086 0x2e3cb572
+ 0x2a53e018 0x6f7a3e41 0x7afe2ee6 0xe4efc53a
+ 0xe2ed04c6 0x67112c67 0xe7e43b4a 0x03f680d7
+ 0xe3434120 0xe2c12215 0x63ff546e 0x4d87e2b7
+ 0x6f95093f 0x7c7a5e18 0xef98c38b 0x8ccf2684
+ 0xf4619327 0x148676c5 0x4be2254a 0xcda85631
+ 0x00ae4a2c 0x2df961dc 0x85b6fd89 0x1512b1fb
+ 0xc17a7547 0xbd062ec9 0x91229a47 0xf6d4b08c
+ 0xf7d3c4f1 0x4d951e94 0x62c8a9e9 0xd7df6f2a
+ 0xce34f11d 0xc04b655f 0xfcf369b9 0x40eb0ec3
+ 0xf7b55c23 0x8edce54f 0xba8ce0db 0x2a5e5a92
+ 0x3b243dcc 0xbcc8c5d0 0x906db8bd 0x6a0aee9f
+ 0x9e6c3df4 0x16f2252d 0xd389126d 0x5118a5bc
+ 0xa75cc327 0x559dde05 0x5bb43b00 0x7fbe942e
+ 0xa24e752a 0xabbfe05c 0x916daec7 0x8817b357
+ 0x5be9fbfb 0x6e8bc90d 0xcdf7cb49 0x0b28069a
+ 0x1922e927 0x24713a66 0xb9c800e5 0x63968dee
+ 0x34464be9 0x712fa6d8 0x9f9c814f 0xf6121f78
+ 0x12863a08 0x349158d3 0x66556d8b 0x4938c818
+ 0x69374151 0x55046a98 0x94c8e4f4 0x48430cff
+ 0xb885cdc4 0x762fb5b6 0xee98caee 0x8e582d5c
+ 0x808ba575 0x7878cbac 0x1d257ec1 0x85bb9f16
+ 0x50adfb99 0x98e3f712 0x532b6bb5 0xd3aa0b14
+ 0x07369ec9 0xc6f71890 0x1bb76ff9 0x0e91023e
+ 0x7d6e119a 0xe8c5f447 0x49edf0c4 0x8d380eed
+ 0x99984929 0xd37dd90b 0xfffb0a41 0x69eb9ab1
+ 0x67b2585d 0xe3a5a664 0x7f9d9156 0x0454b9c2
+ 0x4b5d28f2 0xfa6d0a33 0x3c9206a7 0x5aa2fb75
+ 0x767201c8 0x7db04d90 0xc27e89a0 0x4df1cfb8
+ 0x81efb5ad 0x2eeee02b 0x42d5ef5c 0x394fdbd2
+ 0x0bcc3166 0x2f43982b 0x832520df 0xdb6fb558
+ 0x63fccc0d 0xc42816d3 0x5cf66464 0x2b4b89e7
+ 0x2d62dcb5 0x6c4f52fb 0x6c3ac264 0xc92c6977
+ 0x1f6cc458 0xd639250c 0x4044e6b0 0xc39df4c4
+ 0x65595b2b 0x1c9be044 0x5242d7f4 0xec710e0e
+ 0xa991869f 0xacb3cd55 0x4e82d850 0xa7ddd47c
+ 0x12c0cc9d 0x8ff166b2 0x89d6bb4a 0x136ef38b
+ 0x3875e7df 0x8d59d30b 0x3d22b091 0xc64b065e
+ 0x73077e1e 0xcdbbe7db 0x000e842c 0xd5147941
+ 0x8fbcd501 0x6d731511 0x1a45fa09 0x1579e7bb
+ 0x4dfa5ed6 0x192d360a 0xc36e445d 0x6df0bb79
+ 0x9c60d757 0x99067a40 0x286e1450 0x21d95d9d
+ 0xbffde5f4 0x5b6e43a1 0x61b62406 0x87e27b1d
+ 0x12fbc7cb 0x52332046 0xe2ac85fa 0xe6dc1b49
+ 0xb04e0d61 0xf9cd9aa9 0xe56424ff 0xc5b0b353
+ 0x7b99dc04 0xf8bf97d2 0x3fc86848 0x396441ff
+ 0x92c981c7 0x97a58a03 0x18862056 0xc9849658
+ 0x683cec3b 0x3298b913 0x1d381d39 0xbe687457
+ 0x1598e8c8 0xb4944287 0x59e42ebd 0xaf631121
+ 0x81c6ed2b 0x811cd718 0x9d9ece91 0x6d26ed1c
+ 0xca577a45 0xe87b71a4 0xf9d884ed 0x8c88c874
+ 0x452020b4 0x9e6ac4b8 0xa99fb35c 0x3d0acc96
+ 0x6d0220f5 0xcd4a9041 0x0f7b3489 0x4de2fca5
+ 0xd91865bf 0x7ae85bea 0xd0ac675f 0x3643cfd2
+ 0x9c9e938a 0xcc24771c 0x04a8d771 0x69ea870c
+ 0x536c78b1 0x9c986d53 0x188133ed 0xc2449d1a
+ 0x949dcfee 0x657b7cbb 0xbac748a6 0x5469c94f
+ 0x58b00d1b 0x4a95f324 0x9e3d996a 0x7d61363b
+ 0x95c3b5e5 0xe0c628e5 0x89ba2777 0x92530a59
+ 0xa52ed8d8 0x96f64b04 0xd7a09900 0x2b7bdcec
+ 0x31ddf392 0x796d19fd 0xdbaac550 0xc1b483dc
+ 0x7003a526 0x260f55db 0x2065f6ad 0x97c38ccc
+ 0x2a6b7ce5 0xec4e0018 0x990007bd 0x93e4d47f
+ 0x04d2536e 0x4bfd17fd 0x173af016 0x26515f4e
+ 0x9051893d 0x63333e26 0xe47971be 0xd909f5f9
+ 0x2f5be247 0xfade7a04 0x121542b3 0xcd5f8f3b
+ 0x416d8352 0xa66d58b6 0x5656d408 0x10ee1bf2
+ 0x3c65b26a 0x31dbef80 0xb3badd4d 0x388342da
+ 0xc430266f 0x53fa9fe3 0xfecd7bd3 0xac043f73
+ 0xc94b4ee6 0x1dd26332 0x993b8b27 0x1d78261e
+ 0xbd4a0564 0x170a57fb 0xaaa7be6c 0x9bbde43e
+ 0x70d16f35 0x11525ae1 0x00b8c636 0x7088bf37
+ 0xed6ea850 0xaa37bc1f 0xe08e79ea 0x7d4ed426
+ 0x95f8916a 0xc2fdd49f 0x1fa1bc9a 0xb759624c
+ 0xd7159d5d 0x65762aba 0x50c99a62 0x8879a995
+ 0x496ad905 0xcf5447b3 0x230a9e21 0xb6d586ac
+ 0xccfd911b 0xa4a58d33 0xbef8ff75 0x6381b0c3
+ 0x62d0e4ad 0x2f0992a0 0x27d2e923 0xc9d67860
+ 0x46f394b2 0x877ea324 0x6ed5c693 0x386dbfd3
+ 0x5f5c1f7b 0x1a339481 0x1cd12853 0x4da6425d
+ 0xe50aa540 0x2dd400e8 0xd7b37c5f 0x52046ed3
+ 0xdb24073b 0xb28cbf56 0x67e62bdb 0x32f6e9bc
+ 0x8f2f443b 0xacedd944 0xfa99423f 0x3ae8d636
+ 0x613a42fb 0x1a410513 0x4469e127 0x2fdb4b5e
+ 0xf86ed877 0x07637d77 0xbb197929 0xa8fa021b
+ 0x9a9f4341 0x35e36444 0xc6728094 0x54c438fb
+ 0x17b46ef7 0x152d988b 0x42c512fd 0xcc4f36dc
+ 0x1ab4ed10 0xd367833b 0x1c08b3d9 0xb5d182e1
+ 0x198f9d7a 0xd68ac623 0x964db9a6 0xd6c121f9
+ 0xdb56e5d9 0x69e61f26 0x6b9fe5f6 0xc414f7ed
+ 0x812a505a 0x7b73b945 0x08000c8a 0x8ed6ff2e
+ 0x19b9394d 0xcce2bc3a 0x46d66935 0xf3e5468b
+ 0xf345f275 0x5f9bf5c1 0x46ceb342 0x45149107
+ 0xc02af675 0xbf3ca371 0x55237036 0x8ae2d3bd
+ 0x19b01471 0xa77a83f0 0x6b003b46 0x29a22e11
+ 0x89a94839 0xd0c249a3 0xdb36a03a 0xe38f4040
+ 0x88f9c8b9 0xef50fad5 0xd69b106c 0x5f314dd3
+ 0xde5e9f87 0x91c24944 0x49eee859 0x2aaeaa65
+ 0xab45e53c 0xf3a0e4c0 0x200a36e5 0x77e484f5
+ 0xcbf8952d 0x64d6ebfc 0x1f832895 0xd835590f
+ 0x13f5a770 0x190849af 0x3068c161 0x61a78e84
+ 0xd7567c5c 0x4a1ab2db 0x524ae318 0xd488b5be
+ 0x1703785a 0x0a1889eb 0xd39c572a 0x4f99ba34
+ 0x3015e101 0x99e6ff5d 0x13cee969 0x0d66997b
+ 0x8e3dafe4 0x9c0507b7 0x28cebbab 0x2e6cf3d1
+ 0xb24b11bc 0xe411de4c 0x64d5f845 0xb0b20f46
+ 0xa49b7b52 0x9b65793d 0x8756f69d 0x0e0bfcd9
+ 0x6631f0ee 0xfea0c152 0xc54d903a 0xe05159f1
+ 0xb2cd54ac 0x039a6d29 0x81cd7e6b 0x58cd335c
+ 0xf6e95cc4 0xa6a02bf1 0x62e10eb8 0x0b11d249
+ 0x5b52a70a 0xff2eb36e 0x9ce7f597 0xfc4421c4
+ 0xba74bbfa 0x4ba989b4 0xce7c369a 0x8c149a5f
+ 0x063745c9 0x4a1dc1ba 0x3c798afe 0xa47ef113
+ 0x54c6c987 0xa6623430 0xed26b37f 0x0ebac834
+ 0x54cb0233 0x92995cf3 0x5412dbfb 0xaf94b295
+ 0x80ea9fea 0x6c776fea 0xc638768e 0x3e2cd596
+ 0x8c6f6218 0xe5b70298 0xad6cb433 0x0271dd2a
+ 0x25c9a276 0x24ee6a85 0xe72e9d3f 0x3bdf3f97
+ 0xabf11c1e 0x99937754 0x2bb62c14 0xf3da4c81
+ 0xc962c562 0x727c4e26 0x97b1c000 0x0de49161
+ 0xdb8d6318 0xc9b83dd7 0x40901e67 0x68ac3dd3
+ 0x217fecae 0xfa36644a 0xb9399c9f 0x620ccdbf
+ 0x81fa634f 0xdb38edb1 0xf7e11418 0x1f580868
+ 0x48b35cae 0x7230c6e3 0xf7cc6a25 0x440c45d7
+ 0xb390e675 0x9b78318a 0x0d359239 0x97e078cc
+ 0x80e65a34 0xd71dbf0b 0xd112cd54 0x53a3f81e
+ 0x098f7be4 0xa11d522e 0xebbb20dd 0x2c4a78c0
+ 0xd4e79e2e 0x01c919dd 0x2fa34e3f 0x6a16a7df
+ 0xb81c9cf9 0x472fd48e 0xd197dae0 0x94cc62c4
+ 0xe052d018 0x1ca9bf15 0xb44ddb70 0x814d856c
+ 0x68927beb 0x5622d712 0xfb289586 0xd40ab10c
+ 0x4c7f3469 0x357a822a 0x717a3720 0x3f3a99ed
+ 0xf13943e4 0x043dbfae 0x6fb72671 0x06bcaf58
+ 0x790c1e70 0x3e8e537f 0x5a4fb50e 0xa2fe476d
+ 0x9db652cf 0xace6b43f 0xd1273d75 0x88727f3f
+ 0xe66f9c36 0x24339816 0x28f8dd6c 0x5a4f8879
+ 0x51ebf963 0xd64769b3 0xd9006ec3 0x20bd215b
+ 0xce24e7cc 0x61c00c46 0xf9b16868 0x429a54f8
+ 0x328834df 0xfcdbb181 0xd782c3e9 0x6b71dbe0
+ 0x70dcfe9d 0x95c1a80b 0x5ae919c7 0x7e71afab
+ 0x4103d80a 0x955c62d8 0xca197e33 0x4b579a1e
+ 0x94521734 0xa9bd1f4d 0x112ef524 0xbfafeec9
+ 0x6358d4de 0xe68efe2d 0x93c564db 0xa3e4ac68
+ 0xc61833f9 0xef2e5dbb 0x4d3a5a3d 0x30e7a355
+ 0x6b1ed181 0x1e6cbb81 0xb6fa389c 0x0c7e7ee9
+ 0xc20c8770 0xcb04a3ac 0xa4ba69e0 0x7e87b290
+ 0x8c67e8db 0x2c3a40f7 0x366bc618 0xdeaab8e0
+ 0x95d11262 0x665c9d87 0x68435cf0 0x924c1e1b
+ 0xc8f8c882 0xdff0c036 0xfe411797 0x2bd049c1
+ 0xf4def28d 0xd8d01637 0xc7ef2c00 0x6367f83f
+ 0xd34fdf44 0xd392e10a 0x6d522ea0 0x16f8e3c6
+ 0x4d9b0149 0x6ce5ac26 0x57431d08 0x77f105e2
+ 0xe9f6f804 0x92dae4d9 0x63baf9f0 0x17056564
+ 0x010e1d9f 0x50231c43 0x5ba79db6 0x8517839f
+ 0x18afe138 0x88d3a85e 0x786ed442 0x9cf4a72b
+ 0x629ebf65 0x613d8e8e 0x712a0fd8 0xbc88b08b
+ 0x81ea88b3 0x3ac5f023 0xb93c236e 0x93a3468c
+ 0xd86745c6 0x6df47eb2 0x10e2e256 0x2da86820
+ 0x1513101f 0x38128155 0x7fbc9673 0x5e8aca10
+ 0xc79677d1 0x8006a420 0x56909452 0xde047cd6
+ 0x33256da8 0x63637d54 0xdbb682c2 0x9b00c56d
+ 0x9f62d072 0xb7be713a 0xb0e603d8 0x047e37e3
+ 0xd51ffb7a 0xeec69890 0x1e72d673 0x6d7f5c0d
+ 0xa80c0473 0x12b89507 0xd605abac 0xd4c6899d
+ 0x9bb98856 0xa6269a33 0xe08135cc 0x8a69b777
+ 0x077837e8 0xd13014ea 0x9ca638ad 0x908e6612
+ 0x5bf969fd 0xfd9da209 0x3e72a1a3 0xc7cbec2b
+ 0x66cf84a1 0xd67e67eb 0x1684ed54 0x22feca3c
+ 0x9c0d00c2 0x6337c641 0x89f65117 0x7fa4c657
+ 0xebbd3208 0x89322dfb 0x925f82c7 0xebeef669
+ 0x8cf74ade 0x55847368 0x28fd1623 0x5c2e0709
+ 0xceb12802 0xbc4de4d3 0xec44bd13 0x33574d46
+ 0xe89ce0f8 0xc09d2036 0xf83ce68e 0x0da18b34
+ 0x30bd2849 0x252235cd 0xae7b84e6 0xb894640f
+ 0x5b84fc6c 0x23f8cca0 0xd5a506ad 0x5605e837
+ >;
+++ /dev/null
-/*
- * ---
- * This is a device tree fragment. Use #include to add these properties to a
- * node.
- *
- * Date:
- */
-
-compatible = "intel,microcode";
-intel,header-version = <1>;
-intel,update-revision = <0x901>;
-intel,date-code = <0x4212014>;
-intel,processor-signature = <0x30679>;
-intel,checksum = <0x69c4e6f1>;
-intel,loader-revision = <1>;
-intel,processor-flags = <0x1>;
-
-/* The first 48-bytes are the public header which repeats the above data */
-data = <
- 0x01000000 0x01090000 0x14202104 0x79060300
- 0xf1e6c469 0x01000000 0x01000000 0xd0cb0000
- 0x00cc0000 0x00000000 0x00000000 0x00000000
- 0x00000000 0xa1000000 0x01000200 0x01090000
- 0x00000000 0x00000000 0x18041420 0x01320000
- 0x01000000 0x79060300 0x00000000 0x00000000
- 0x00000000 0x00000000 0x00000000 0x00000000
- 0x00000000 0xf4320000 0x00000000 0x00000000
- 0x00000000 0x00000000 0x00000000 0x00000000
- 0x3b6ec6fe 0xc0fda75e 0xb4ea6a9f 0x8fd6ed15
- 0xd537f374 0x669bf3bb 0xebedec72 0xb4cbc889
- 0xdb666815 0x5a17bfc4 0x4fca009d 0x099ae8b3
- 0x198e2c7d 0x7c665bbf 0xc07a1a7a 0x7dbcee26
- 0x867296b2 0xc885b6ce 0xe602baff 0x68544b14
- 0xc928c400 0x3add156d 0x531946f9 0x92a03216
- 0xda352322 0xd967ee1f 0x3c5170a7 0xf6de834e
- 0x5a2ed8b3 0x9fb8f050 0x450de17f 0xfd5ef070
- 0x4954575f 0xa3a071ab 0xb56e2afb 0xe2b48302
- 0x6655a958 0x57c9a438 0x1b2f688a 0x09309bc4
- 0x0be95612 0x529c1633 0xc48515d9 0x29eb78df
- 0x9933409f 0xda58dea9 0x58c805fd 0xbc110f5a
- 0x40780ec0 0x6ad59bb3 0xc7387fb8 0x591c1490
- 0xf9335932 0x32130e0b 0xef4b3c96 0xacd903f2
- 0x5b362539 0xe7f85529 0xcb17c41f 0xe7e440d8
- 0xfaf7e925 0x969b76fb 0x5edab8c7 0xf00012e8
- 0x121c2971 0xe5b18959 0xadfd07c0 0x1f09c9d7
- 0x9781006a 0x39550073 0x6c438b6d 0x436f60bc
- 0x11000000 0xf03f27bc 0x3ed2262b 0xe1f8f63d
- 0xc164c68f 0x92e5df39 0x46108645 0x99a9968f
- 0x1dfa58a4 0xd1ebfd99 0xca4dae70 0xe466a06a
- 0x49575333 0xe30f49f0 0x814e5961 0xfa4bb7bd
- 0x2e212282 0x31912456 0x7d722c47 0x9cda0657
- 0x111985e9 0xd28d3b0b 0xec52f0c2 0x956b5b95
- 0x0806f491 0xa8096786 0x1e4c1248 0x42ea1ecf
- 0xea09d662 0xa821f68e 0x4b84d60a 0xa6f61348
- 0xfc95c139 0xebcebc32 0xd68ffe3e 0xa9aefabe
- 0xf653aafc 0x2a9f10e4 0xdaf3d51d 0x5f25aaa5
- 0xdedacabe 0xf2e08b12 0x6fb9f444 0x31b13d4e
- 0x13074cd3 0x68905491 0x08ce3a00 0xb3e5a3dc
- 0x9554ca97 0x5955c3a4 0x2e9951fd 0x5d708c9f
- 0xf3abe824 0xcb9105a1 0x3f51122e 0xd2152f23
- 0x2873cd28 0x463c0ff3 0x7bb81500 0xaa360665
- 0xbe69bdf9 0xa32415d6 0x111af68c 0xd129eaf6
- 0xdd102779 0x098a2b08 0x90363b85 0xdb5d3420
- 0xd1d116e3 0x9e5dd54e 0xb4a93d32 0xb5ee99fe
- 0x409f0bca 0x40302319 0xe175ddaa 0xfd7c8d00
- 0x2c28edb9 0x698d27f4 0x2e7945f1 0xc0150485
- 0xf9c599fc 0x139824cb 0x1571f70e 0x222565e8
- 0x3377eb7a 0x70fdee6f 0xd409f0a6 0xc875d05f
- 0x70d6a86b 0x66201d61 0xf8fcb733 0x14279707
- 0xc204e0e4 0x124c89be 0x8b298d1d 0x79bfe168
- 0xdbf7fe94 0x0358af09 0x8291ef8a 0x3e74a2ea
- 0xb7780782 0x0194d445 0x0bab231d 0xd76f85b2
- 0xc7510861 0x4b9a5c80 0x6c9c8583 0x4e18d7db
- 0x7dfeaea8 0x59be4d17 0x8e96f5b7 0x51bcb2da
- 0x5f3afeed 0xd3f46ecd 0x10da04eb 0x29dd87db
- 0xb7df24c5 0xd58dc2dc 0xede0603f 0xadf00cf7
- 0x50090b9f 0xc9130c82 0x854fc603 0x13b8b4be
- 0x10e2e41f 0x5c1d2246 0x0ee11843 0x6d38356d
- 0xd3bd47ae 0xb419f115 0xb118cac7 0x9c61aa7d
- 0xca22cf8a 0xd41af2f1 0x0b5ebfab 0xc0889746
- 0x078c705f 0x9e5b2b7a 0xb886ff49 0x1ab413e4
- 0x085cebc5 0xe3a44ab5 0x8844df92 0x075a79cf
- 0xb8fdc33b 0x1766265c 0x9340a734 0x4af860c9
- 0xa933586e 0x3e8a9a5c 0xf6419a1b 0xa70a1556
- 0xf930240e 0xe294fb1f 0x9bba35c5 0x4051819b
- 0x6799015f 0x7eb725ad 0x3953fe03 0xb8760679
- 0x54c7978c 0x3dfd36c2 0x631212bb 0xdeaca312
- 0x56d994dc 0x3a1696d1 0x214451fd 0x6dc505f7
- 0x7bbf210f 0xa266b569 0x8fb5eb6f 0xa6b76bf8
- 0xc9e782a1 0x8456765d 0x0a9eb223 0xa67e533f
- 0x211016f4 0xd8783c3e 0xc35574b8 0xd97e9b52
- 0x28ad2911 0xbffc5dad 0xd807d783 0x3050f3d1
- 0xcc33efa8 0xb9cf97c2 0xee5dfc8c 0x2adad5bb
- 0x4011c50b 0xa16f5d93 0x5e2ac188 0x521c977f
- 0x6af1b858 0xcd7e4b4c 0xfc988f66 0xc0e4cee9
- 0x82ac99ea 0x54353832 0x2308e02f 0xd084d198
- 0x03574ad5 0xbe4b698f 0xe1d7d294 0xd772d08d
- 0xb7a4fb2a 0xf7c93bb8 0x42fb2f4b 0x98cb1a11
- 0xf564f28e 0xd6ace35f 0xc43f6639 0x85be741d
- 0x079b8c1f 0xb5b45522 0xfedab918 0xf7fa7494
- 0x32204c16 0x1c8d5434 0xc39e58e4 0x99c7a2c4
- 0x3ccfbc3a 0x3f5ba9ef 0xf919921b 0xcffbeb79
- 0xd2927d86 0x5a50486d 0x62bdb218 0x22731dcd
- 0xbad1db2c 0x2f4af4a5 0x8f7eded6 0xeca3dcca
- 0x0bb5ecf7 0x05e6f3c6 0xa38cddff 0xc7cae177
- 0x1d115485 0x711ea542 0x33729cf9 0x59000680
- 0xcaf26070 0xd2647235 0x4ce354fc 0x76d9bdbe
- 0x53e39ec2 0x2d8acfb3 0x193c03b9 0xb3cef3ba
- 0x1da26bd5 0x8dfeeaa5 0xc199d90d 0xcfc8ee2d
- 0x4cb1bd52 0x521d197c 0x008bf34b 0xb6ff25ca
- 0xf4922b7c 0xa91893a8 0xbd3d7874 0x32865e72
- 0xca72c49d 0x02733201 0x6156051d 0x47464b81
- 0x353a3c14 0xa87475c8 0x9681a015 0x4b58832d
- 0xea65c6a2 0xfefef1fb 0xd5fa7dbf 0x13aeee80
- 0x2915b47b 0xe4a54fca 0x31615326 0xbad80f83
- 0x21eedfcc 0x2a2787da 0x6eaa2c9c 0x9de76356
- 0x8a34d823 0x2e7641b8 0xef16714d 0x8267bad4
- 0xacdfff45 0x09a93862 0xf63863de 0x7eec7d8b
- 0x70b4cf72 0xc7a8118c 0x4ed89774 0xc12a5e0d
- 0xe77cc023 0xcdee8fd8 0x20ffe6d9 0x88bcfaa0
- 0xd945e4fb 0xf496fccc 0xe7587e99 0x42252ec4
- 0xcc47d738 0xcc549ca3 0xd5059657 0xfbf502a5
- 0x2788945d 0x4f8ca4d6 0x41b7c069 0x618ebdf6
- 0x0354452c 0xf7249d75 0xe048dd38 0x4ca484b3
- 0x0347342c 0x23608b20 0x8a76cb28 0xd445886d
- 0xfe0e1e6a 0x46678478 0x230c0ef0 0x3add3053
- 0xa6a158c1 0x22c589d3 0x3b728538 0x5f78bfe8
- 0xab0bb3ab 0xb39e20b7 0xbb913a69 0xdf8bb73c
- 0xc2d5bb32 0xbd3e928c 0x30374965 0x9accaf18
- 0x60bb410e 0xa7786a6d 0xd368444d 0xc5eda57d
- 0x7a835abd 0x9f5f74e9 0x33b14a30 0xc0129833
- 0xc5d2e117 0x5f884f0f 0xae6fd2f7 0x3ef71ba2
- 0x0f0b944c 0x1a8dd932 0x2448f0ed 0xfb8ca949
- 0x9d08756f 0x7914384d 0xdd70f795 0x8cf8daff
- 0x6755785b 0xf4e6a191 0x8c5a9a2e 0xfdc19939
- 0x66f39dc0 0x3da9fcc2 0x2c22797b 0x63f892d3
- 0xdcb75a66 0xa043c021 0xcb0f9292 0x887eb1a2
- 0x9d588452 0x9fdc185f 0xf481d465 0xbfef53b9
- 0x38da9baa 0x9d35c4f4 0xa652c843 0xf80f0007
- 0xb482a32c 0x7ae4df5b 0x74ad41c2 0x15d849b3
- 0xc4235054 0x36d44d98 0xc06ad604 0xdc83d81f
- 0xd4b87511 0xab79b430 0x832a7ce1 0xafe26f16
- 0x9f7d26db 0xd00816cd 0xec6e7b8b 0x0392bd20
- 0xfe4b6e2f 0x87795026 0xf9e4eef8 0x06cd2ec8
- 0x91670e6a 0x17aad6af 0x399050d1 0x043d05f8
- 0x5dd8e105 0xa2938113 0x2c47ea5e 0x64a062f8
- 0x14dd01cf 0x6773f479 0xf2b4a773 0xeefe3b89
- 0x8cf35404 0x0f02b236 0x430023ff 0x04ecae31
- 0x6949cdfb 0x65b63ba6 0x86c5a7c6 0xd53cc1b5
- 0xdc1ee770 0x30ebc654 0x67a95215 0x2e4508a9
- 0x9df37690 0x33baf9e5 0x9a58d5c0 0xe99baa0c
- 0x4b7446eb 0xfc7c8340 0xfa5ee60a 0xd1d873b4
- 0x302f882f 0xcff8ac83 0x56d809d2 0xcab281e6
- 0xadca5551 0x50691975 0x7766b753 0xdb7adecd
- 0x131c83af 0x1b09ee46 0x87fdd3ef 0xfe3037c2
- 0xcd2b5362 0x5f21384b 0xacd78f4e 0x145a4793
- 0x131a6a20 0x0fc1adf5 0x3707f20b 0x5d37ba20
- 0x6c8448e6 0x76f721a4 0x348b0456 0x608453ed
- 0xb1185c8a 0x18bbdaa1 0x7c1c6e05 0x46fa7cdf
- 0x390cf9b7 0xe9c825bf 0xf77554c5 0x7dd5a47c
- 0x49cfca16 0x5fd7e6dd 0xf707ac36 0xdb6f0142
- 0xaabda9b0 0xe7ac02e7 0x0a1eb844 0x225686b2
- 0x7852c1cf 0x3912115d 0x89d65081 0xc3f4faee
- 0xfedeba97 0x073395d9 0x33d20ce3 0x56c6c126
- 0x378f822e 0xf575b487 0x043da151 0x1ccae8c2
- 0x5fa2279b 0x0608f618 0x4c90662b 0x30591d0c
- 0xcf217166 0xacdbf6fe 0x1a653b17 0x6fa76090
- 0xc804480e 0x44c5b06b 0x1ebb8a6d 0x2f6f6f08
- 0x6bbeb75c 0x21c5c48d 0xd4c4cc2d 0xfdeab68f
- 0x25cd39e3 0x62970aa2 0x48aa915f 0xca38c833
- 0x9cfd1d10 0x81dbc61d 0x51702e45 0x8f80e492
- 0x07e89651 0x920e9f7d 0xdfa9f973 0x8cbfa187
- 0xbd3e7a14 0xee191486 0xb0077d2e 0x7345adcf
- 0xce36b2ea 0xc73aec7d 0x9278ac37 0xe07c6d96
- 0xf90f78a5 0x38f5584c 0x4941da80 0x67ff3048
- 0x3c263914 0x49656179 0x22f066a5 0x1f5a5e3e
- 0xce9ce83f 0x8e7446a2 0x85473d62 0xd7622673
- 0x3941bc22 0xf879d494 0x0936a517 0x2bba925e
- 0x516761b3 0xe238a8e3 0x11a0c8bf 0xd53cb861
- 0x60c0f0d5 0x63f7f157 0xb23dd4f9 0x5a4fd86c
- 0x3851d435 0x483b98c7 0x71c55b1d 0x1931d219
- 0x7bd54621 0x108bb4af 0xa72c8b97 0x51d985e2
- 0x598a521e 0x7efcf984 0x69b02671 0x5746157d
- 0x60cfc339 0x629567fe 0x2236a93a 0x520d0094
- 0x61811f40 0x856aeba6 0x4fc0a2b3 0xedcc9fb2
- 0x8fce6123 0x2ba53b1b 0x6fc610d4 0xabb564f4
- 0x957158aa 0x1d2b7989 0xaca5dedc 0x684a7086
- 0x1610e1ef 0x2abdf9b0 0xd9e9d205 0x0119ab86
- 0x6da64982 0x71f274b0 0xf425e61b 0x029dc92f
- 0xb13ff88f 0x064ecf92 0x4070c36d 0x58bd6ebd
- 0x629bcf8a 0x9091566a 0xc947a42e 0xd0475c87
- 0xe7773220 0x7b61f2fc 0xae0c08e3 0x44582521
- 0x557dfbaa 0x92fba0ef 0x529900aa 0x90fef908
- 0x570b0495 0x704125df 0xd8f9448e 0x9a7cf1f3
- 0xd83a747b 0xe27e3d56 0x4da6aaa3 0x55439398
- 0xce0d1c02 0xdebd6473 0x580f141b 0xcd5a5e57
- 0x1c64cc23 0x53f8f9c7 0xcfb5b464 0xa4939b05
- 0xc0bb3066 0x37923d76 0xe5e9b428 0x6f4f2894
- 0xe5144757 0xa9cfdc46 0xe3448b78 0x7e0bac3a
- 0x38066245 0x0d7c86fa 0xb7fd09a6 0x075426bf
- 0x3de7c82a 0x1f8d1b36 0x34144ca2 0x6c03ad9d
- 0x34305ef0 0x0a5269ce 0x82a9eeed 0x3be63f82
- 0x2001cea7 0xbba641a8 0xa4dad9e4 0x92e0fb69
- 0xa166dfad 0xd1ae10ab 0x0372e102 0x88469aeb
- 0xaa11bae9 0xf1006dc9 0xa8648217 0xe171b6e8
- 0x590ba849 0xa593cf1f 0x4cf079d4 0xe451e193
- 0x4355a93f 0x54dfcade 0x1a918a74 0x88eff191
- 0xd5a2bf54 0xb9962550 0x58d478ab 0xc78828a9
- 0xe2cff385 0x9ff810e7 0x9643953f 0x84764dee
- 0xe4950d03 0xdf17e0e5 0x4da892d6 0x48145872
- 0xb7453254 0x41240a2a 0x7ddf94bc 0x898771f1
- 0x61a423be 0xcfb46db4 0x7db27a89 0x2feeaa82
- 0x24d86326 0x043f5b1c 0x8cc6bd73 0x934b7b3e
- 0xac4a1262 0xebc494bd 0x53921696 0x115c4d9a
- 0x1d73de18 0x6417f141 0x9fdce4cd 0x8f72ccdd
- 0x3bb26030 0xdaf43da3 0x1e26758b 0xad1234be
- 0xe5bdf477 0xd2dd9e46 0x1270838f 0x557f3bd2
- 0xaa5a28c1 0x61e0d535 0xdc5aa028 0x9af22a6d
- 0x9b669fbb 0x979b5586 0xabf8264f 0xbcf91b17
- 0xda92e3cf 0xaaa87ae0 0x52336f6d 0x5beef95f
- 0x7c310125 0x8858f708 0x3c6e6d73 0x6720d3c6
- 0xed51b365 0xa9e50de2 0x865a7fc1 0x756b5758
- 0xbe13f4ca 0xf2eb039e 0x187d1641 0xc6e37977
- 0xbc3a2d64 0x6523583c 0x70db0cf9 0xebdba06e
- 0x632e8e5a 0x7b44144b 0x338bf7e2 0xf43dd8e4
- 0x2d91d815 0x9aff02dc 0x700ebe20 0xe9b6ea5f
- 0x776cdc38 0x43324788 0x53458290 0x2e22910d
- 0xed0fdf3b 0x279fc3ca 0x5a01f65c 0xc4ad1598
- 0x7a1fa09f 0xd12f97bf 0x34d99bad 0xfcecf69c
- 0x2b5567af 0x57a93cb3 0xfcf93005 0x3a403789
- 0xecaad383 0xc63fe190 0x5b8de563 0xbd9b876d
- 0xa20b875b 0x79db86f9 0x1917cad6 0xe925d5e9
- 0x8a233ed2 0xda8e6369 0x43028013 0x91b72d39
- 0x6b75eb99 0xc7bb03bb 0xab135e5f 0xb73cbade
- 0xfb7b0cfa 0x62ef94cc 0xdfdaa5ee 0x75c0f3ef
- 0xf020108a 0x6c54535f 0xc9583167 0x68fdd582
- 0xc6c95829 0x7fa6f2b4 0x9c7f494c 0xde5daac7
- 0x10088178 0xc27f2052 0x84714bf4 0xd2eb0ba2
- 0x23fd2e08 0x7c2fceb7 0x119bfd3a 0x029faaba
- 0x41c8cd67 0x2461da7f 0x25acc8ef 0xece252ec
- 0x997d4b00 0x3f19f111 0x68237934 0x518f427d
- 0x6c2a04d9 0x27f61e6d 0x68ebf9c6 0xf3ca994f
- 0x43e5c576 0xc4e1fd3b 0xe2393151 0xbf97bbec
- 0xefd161e9 0x5e3a816b 0x1d8b9bd3 0xecbc57f5
- 0x042c1237 0xcb1c852c 0x546f4d72 0x01b37ce2
- 0x20e30817 0x3fbd20d1 0x2ca11cc3 0x63cf6770
- 0xa65064ac 0x32d2cbab 0x9c1fb334 0x37c097ea
- 0x63ea10fd 0x7db8fc2f 0x8a4425dc 0x752ca318
- 0x9a570211 0x50f90038 0x90abfad1 0xe81169f7
- 0xd804a9b7 0x18b7efa2 0x6daabb80 0xf098566e
- 0xb5df2af6 0x8f23ef8d 0xed7dac93 0x4fbed0de
- 0x929b870e 0x60b5c69b 0x5589cc4d 0x588914af
- 0xfd78c6f8 0xd4018180 0x43d22344 0x873ee413
- 0x0ad0f12a 0x15200a82 0x749bff31 0x6fd4ca58
- 0xeea48890 0xc1507520 0x7a750a56 0x87c85e9b
- 0x2bc19182 0x9e7084d6 0xee8595b0 0x3c35ef78
- 0xaa19db33 0xbc4d7c20 0xa7b2c1ef 0x51ccd346
- 0x72b24c95 0xedf9e250 0x88a582df 0x42a27480
- 0x8fe7bfa3 0xb5f08d25 0x2cfb9e8c 0xcc118d13
- 0x50d9c479 0xf4abe2bd 0x1b22edbf 0x8f525f45
- 0xac39c5d6 0xb35d5c21 0x0e588e14 0x4715d55a
- 0x1b0ecbad 0x16e9e58d 0xcefb1002 0x8a37403e
- 0x70e90356 0x9b7a48f6 0x43bcf700 0x70470d6e
- 0x8e0dd0ea 0x7620f026 0xb4809687 0x8a3d8bef
- 0xdc0261a9 0x3e8d2dbc 0x6d48a5b3 0x4107a6d9
- 0x2dc369b0 0x671d66a3 0x559e6e50 0x4b8098ba
- 0x28209e38 0xf2bd6114 0x0a6f4f54 0x77a82065
- 0x406470a2 0x93cae58d 0xcf774ed5 0x7f4cdd72
- 0xfb869931 0x4ab42cd8 0x8251ded1 0x2c85fccd
- 0x14a8ae06 0x92333b50 0x53f605f9 0x3347f24f
- 0xf190509f 0xf72b525e 0x13a0f3ae 0xc04c7e10
- 0xa735fbf2 0x94df568b 0x71f6306e 0xcad6592e
- 0x1690c07f 0x64dda7ef 0xb03c8822 0x41f58140
- 0xc1953b66 0x2b4bae6a 0x278c23d4 0x0a02a425
- 0x10942d48 0x70557bb5 0x94981643 0x63214c9e
- 0xaa7ea265 0x505bf23b 0xa66c7082 0xf428671e
- 0xd1fdc33d 0x5817c28b 0x2ad4649a 0xb22b1eb1
- 0x17f29535 0x0423d04e 0x8b4d30cb 0xc36089f1
- 0x492dcfa4 0xe7842e60 0x7d4805de 0x02d4f43f
- 0xd3b6933d 0xa763e450 0x4301f667 0x58318b37
- 0x78d9dd14 0x84343bf2 0xf62e93a3 0x76d9d617
- 0x82c37d71 0xc3fa7cda 0x3dffa327 0xa171b148
- 0x4654011a 0x7cbd5689 0xaabe734f 0xb8226cd0
- 0x9d846c68 0xb9233e88 0xfc0b0bcc 0x2138ccfe
- 0xaff53d8f 0x9b0b8b80 0xb2be2912 0xcc871084
- 0x47a380a1 0x593c82ed 0x3cc8424f 0x5e77c12d
- 0x813626a2 0x8021e31e 0xeede3c2c 0xb8fea5ea
- 0x236a7fc6 0x783bdc5b 0x0d67a0ab 0x8987c13f
- 0xb6381e65 0x3b313687 0x52ad7a81 0x759ae49d
- 0x468ab620 0x8b735c2e 0x60937053 0xb3cf5867
- 0xb48525fe 0xd8bc07fa 0xf092e18b 0x6d8ce7a3
- 0xfeec327d 0x752e3f43 0xf106ac62 0xfe3489b7
- 0xa699af8d 0x1c5dcb5a 0x3a931d51 0xc1409944
- 0x843c3667 0xb923eb17 0x67c3d38f 0xd1edd5bb
- 0x4bffe68e 0x8b7acab6 0xe0058382 0x79de2e31
- 0x1e48cc0f 0xc4b8ad1e 0x5a00cf89 0xa4f6b8e4
- 0x29d42e0a 0x3d483f3e 0x746de9bf 0x0ce78994
- 0xcb6df646 0xe287b7f6 0x85907659 0x333127fb
- 0x6aac4a54 0x5ff7c669 0xd42ea2ac 0x92ae55b9
- 0x952f68e5 0x3273a013 0xec6cedbe 0x9ede1ad3
- 0x76d7c595 0x167c73fe 0x7c2572f4 0x8f653319
- 0xa1c726a4 0xf7ba8a71 0x5bc9b17c 0xc0d89104
- 0xc0ba5907 0x0e8c9c27 0xc8205b68 0x74f8aebf
- 0x02acd438 0x28783ffd 0x143ea70d 0x9c82abd6
- 0x9eb156e1 0x5951d075 0x5afb06d9 0xd14bac91
- 0x6ae19745 0x728cd46e 0x775cf71d 0x1126cf7e
- 0x058d4dcb 0x7f5f648d 0x5f37a908 0xd2fd843e
- 0x8dd64fb8 0xcdaa761a 0x105c38c1 0x9b5f440f
- 0x2dad00c4 0xd3c25b11 0xcc07bfb0 0xbc432852
- 0xc2d34e0c 0x0b1978f9 0x95a119ee 0xfc4dbdfd
- 0xae6d3b7a 0xff06ff00 0x30976600 0x9e47e68f
- 0x3308cf27 0x0a2d1580 0xe91ea75e 0xcbf12170
- 0xc7da3143 0xbe0a6ded 0x74d03d5a 0xb0869deb
- 0xbb94dec7 0xec2a053f 0xcb4fd13f 0x04912071
- 0xb1af28a2 0xee094f0f 0xa78a4965 0xcdded4aa
- 0x6d4959cb 0x93ee7709 0x2901d3af 0x6ad494ad
- 0xb95203f0 0x1fa160d4 0x7a06d88f 0x35f89a76
- 0x5e151830 0x27feb3eb 0xa9a9805f 0xc43b9387
- 0x5b6bf76e 0x3372d23a 0xbe2d27f1 0xad9b7282
- 0x5d67323b 0x2e96328d 0x3d90fe8a 0x9e4d4522
- 0xa2eba985 0xe1ed3264 0x28eab708 0x2551ba26
- 0xc143badb 0x3bebdacd 0x4da62bf1 0x875ffcaa
- 0xcc643e34 0x1b75c14d 0x13b84e83 0x8abb6f10
- 0xb82dd0fb 0xf31e4572 0xca8a5f58 0xb98da99f
- 0xec33fc4c 0x952384ca 0xd673c525 0x45f36727
- 0x269b8efb 0xfe5bc4a4 0x90325548 0xb8aefb93
- 0x6a2381c6 0xdc4ecc1e 0x7fc546b2 0x5348ca20
- 0x8eca0f26 0x5a49fa01 0x4b0822fd 0x862e680f
- 0x5abdf88e 0xeb23e8fb 0x2c023eb8 0x092cdb59
- 0xa15e0fbf 0x03f1e5e9 0x2c343bfd 0x8876aa74
- 0x5b80428d 0x4a4fba83 0xeea3da82 0x414a610d
- 0xecb123db 0x0f81b8b2 0xfdd1c970 0x8de71d6f
- 0x0ca553b1 0x57fc98ad 0x47d44eb3 0x17827c70
- 0x2d91f5b1 0xecf63cb7 0xb4fdb928 0xc49c42ed
- 0xeea589bd 0x62cf916b 0x02a553a6 0x50cb4523
- 0x959d3831 0xebfa026e 0xd2483d91 0x140364c2
- 0xa8ddcdd6 0xca343670 0x589a154f 0x6bf369ed
- 0x40eff32d 0xd7b49920 0xf4bff896 0x5a62c192
- 0x0a4cb0bc 0x449533d6 0xace20ca3 0xfae7465b
- 0xb6e0edda 0xda214fa1 0xcc08b6be 0x54c342cb
- 0xc09f8db1 0xead565c0 0xe38b2187 0xd0d0be68
- 0x16748998 0xced5a632 0xa0636b45 0xc71ab63f
- 0xfe161e04 0xe8b66fdb 0x878e2039 0x17af26c2
- 0x6851cb01 0x9484d4a5 0x697e6981 0x9946e0fc
- 0x970cbede 0x87d887f2 0xd987bd44 0x10dcae60
- 0x20239b60 0xe9ef795c 0x536f0f3b 0x2d4de85d
- 0xd50035c9 0x335410a8 0xee350c4f 0xcf94d278
- 0x688c98c6 0x3c0402d5 0xa8b8a81c 0x952c67e6
- 0xdf432d95 0xb74dd56d 0x77316d7c 0x56df9401
- 0xb8aad070 0xf5d1cbb6 0x206f18bd 0x59fdf55d
- 0x5de26069 0x31ab08b6 0x719a4d81 0x8f1c8212
- 0xc792bd91 0xd6f262c9 0xab4bd545 0x36f3c600
- 0x917c135e 0x1aa0455b 0xc1de8100 0x855db3e9
- 0x42d41a24 0x40955a66 0x8475c651 0xc7f44c6a
- 0x4e1f0df2 0x7cc5cd54 0x35a47bec 0xe6ac8550
- 0x8b43af30 0x6fcd1cb0 0xf37de1ef 0x00c70de7
- 0x63913125 0xb33688d5 0x8c296f13 0x93570308
- 0x6d8aafbf 0x67a574e9 0xf297b1a6 0x53600c84
- 0xfdea2e69 0xe75cf59a 0x1b0e3dd0 0x7f7fa8c2
- 0x7e463346 0x97c7069a 0x671ce307 0x2441f370
- 0xbbeb3a08 0xc2e4448b 0x2157fe23 0x70954499
- 0x3038e792 0x4a8a2fb0 0xa1f4541d 0x7c88605a
- 0x6a4edc03 0x689fe83b 0x93835e79 0x19c99c39
- 0x9ea7dfa9 0x36bd28c2 0x64ac057b 0xa2987c35
- 0x9c3f17ad 0x0be5e9f8 0xef63c94d 0xee32f2b1
- 0x3781a3ae 0x9ebe229f 0x77467a2a 0x1dfd79fe
- 0x24ed349a 0x3008c1c8 0xb77520f3 0xbf831d15
- 0x11dc4dee 0x7b5e47fc 0xfefa0f69 0x2a820af8
- 0x8e133d47 0xa021cf99 0x7886d896 0x8edadf3d
- 0x89a10318 0xb048ce73 0xd9843457 0xe000594b
- 0xff3c1ea8 0xd93a7c02 0x8471da9b 0xf24ccfcc
- 0x6f0576b7 0xeb024ef8 0xaf75787b 0x508fca52
- 0x18315250 0x74482410 0x169985c9 0x911c14ef
- 0x96575aa6 0xd4791358 0x1bcd07b0 0xf91ff654
- 0xc3b9c8d0 0x101e8aaa 0x84b8352b 0x16f57154
- 0x843a47f1 0x88269e3d 0xa625bd0d 0x99c91f9c
- 0xfe79c26c 0xd1844839 0xaa59ec6d 0x1e1b9ca5
- 0xb99e4bf7 0xc8c06104 0x29985a13 0x2aa0dea8
- 0xa92de35e 0x8242311d 0x61e0a059 0x09232eac
- 0xc7e8f2b4 0x05fbcfa5 0x41d2cac9 0x5d2026f9
- 0x69b970c0 0x0274700a 0x1f5f23d6 0xb98aea3b
- 0xd879d256 0x69230276 0xbec32596 0x6d4dcd0c
- 0x04efed6b 0xcf5ca09b 0xddd17a77 0x821a0172
- 0xe656d7e6 0x70dd6839 0x75710294 0x59765f6f
- 0xa3174d9b 0x4227c2a1 0x23ddd6c4 0x1d7d8c79
- 0xb2e50bb1 0x98744c39 0x853152f9 0x4d439b89
- 0xf852ac32 0x89ad2fd8 0x613c8c1d 0x47ab4071
- 0xdd62c705 0xe623a5ec 0x93f4bf07 0x5053a3fe
- 0x2545e42c 0x03e4ca84 0xa5dcf9cf 0xc279dd6e
- 0x6e3e2248 0x51c6338b 0x1b79f55d 0x871d7595
- 0x1991ba98 0x697bf68a 0x634bef62 0x415df824
- 0x007523ec 0x595fe4f3 0xd2018516 0xcfa8f6b3
- 0x1e3d33da 0x141858c4 0xa553fa95 0x0ba00794
- 0x923edb17 0x86a18480 0x4aa94d38 0x429814d8
- 0xdd0d853b 0x375808f6 0xcf857aba 0x6f6d5dc9
- 0xdc27fee9 0x7c49718b 0xb3eb09ee 0xf48ba9f7
- 0xa7f8deaa 0xa0afa80f 0x84a0ea27 0x63858132
- 0xa552f06d 0xcce0bc50 0x70a6b770 0xe21c7251
- 0x1fb70601 0x2e93b5f3 0x1f257ad1 0xab09dde3
- 0x176c80a3 0xa1845a72 0xcf68a2e2 0xe3bdd613
- 0xa41d6e7e 0xde870606 0xc292df07 0x7093562d
- 0x692e5e51 0x179dd237 0x01dc96ea 0x3a2efdfc
- 0x6088f181 0x7c3d290f 0xbd38e29c 0x340cead8
- 0xdca8ea9a 0xa43a7899 0xf6541b9c 0xafabfe18
- 0xb5557f4b 0x995bcd2a 0x5355ea0e 0xf3dcdf66
- 0x02216d50 0xaa3a8f23 0x1c63637e 0xb8950554
- 0x7199e726 0x20fed1f2 0x027d67e3 0x7d5a236d
- 0xd1e01da6 0x2db0e750 0xfba1d718 0xa58b42ea
- 0x839b80e9 0xcc55d1aa 0xb1da75e5 0x50789516
- 0x818913cc 0x03facba2 0x6e2bda29 0x1e3c1120
- 0x8fe64712 0x12317a15 0x6e6bb39f 0x7edd5bbb
- 0x900bf72d 0xc6a822c8 0x3353d602 0xd9965f2a
- 0xfc290ed8 0x9c8210e3 0xaa84d5ae 0xdf9f1507
- 0xbd10f9ff 0x50a4d9f4 0x22111607 0xd4043bad
- 0xfb7b42e2 0xe0285329 0x4e76e1a7 0x4188ed50
- 0x88cd2a99 0x4727768e 0xba625d6a 0xf8ad5d67
- 0xcc1595cd 0x36984dda 0x7c9f8fcb 0x4e9ec35e
- 0x37f95b62 0x8e70690a 0x8e43aeec 0xf3434e0c
- 0xa4b3ccee 0x99c0d714 0xee0082c0 0x9d9f002d
- 0x3eab3543 0x829e9098 0xafe4e802 0x5337a928
- 0x9bfd2d3c 0x43b69305 0x2c10167b 0x8b06b92e
- 0x949049c3 0xc98231a3 0xf77c9543 0x9961f18a
- 0x36a63fa0 0x039932f1 0x1179d978 0xb43063e0
- 0x89bc1a9a 0x2a61348d 0x34113ada 0x1866335c
- 0x8b0249ef 0x94c2a8a9 0xd002ae9c 0x029e1f71
- 0x989a3204 0x57b1aaea 0xf2d06793 0x62f17706
- 0x656e06b8 0x022897b3 0x09c381bf 0xafd90766
- 0x8c79df8e 0x665a6727 0x33c2cd0c 0x2e61c4aa
- 0x9dd83f35 0x01b2b241 0x70f5d0e4 0x0e98f63f
- 0x800dc70c 0x8eb5c772 0x7defbb2f 0x763810f0
- 0x7ff959ab 0x07640942 0x7ca07fa5 0xa7bace66
- 0x208a078f 0x2975dd73 0xa4866e67 0x271f5bac
- 0xdca36998 0xe5e1d1fd 0x511f9ffc 0xafac1c08
- 0x827968f9 0x8823df83 0xba2c243c 0x3e2a0d33
- 0x77e0cd0a 0x623d50a3 0x278f115b 0xb79a27e0
- 0x51ab943e 0xdda62a6a 0xb42ea0e4 0x2ae47d5f
- 0x5ceb281f 0x022dfce9 0xe1f879f7 0x6fe70f50
- 0x1d98abe7 0x0828e611 0x8ad0ba15 0x61bbd7be
- 0x5cde8df9 0xd78b7375 0xe1cf9350 0x9faae80b
- 0x5564c0dd 0x3d735e25 0x64985c05 0x20ac585d
- 0x57e9da3d 0x495cf386 0x1889c50e 0xc313efb3
- 0xb3f5e423 0xbb87a9b0 0x3cd06b09 0xdf51b230
- 0xeb2801dd 0x6d5d43cf 0x1fba7400 0x08791e6f
- 0xf90e0873 0xa65df0b8 0x64369b67 0xc22c9200
- 0xd840f9f0 0xcc49d4de 0x9987db7f 0x8fec9974
- 0xc826c852 0x657bd87c 0xcaddde2c 0xeb0dc447
- 0x4a45ffa9 0x035d22b0 0x236eceff 0xa3ba5f8c
- 0xccee0a9a 0xbad5d1dd 0x1cc8b587 0x5f11d469
- 0x99f8c63e 0x64311906 0x43c19b36 0xef9d5e86
- 0x00705473 0x78100dd0 0xedab57b3 0xf3b00610
- 0xfc6e3467 0x6c4bff2f 0x97227c44 0x38ca257b
- 0x4e79fd63 0x0c8b3466 0xa2ae7e62 0xb01fba5c
- 0xdeee261d 0x2a4c6387 0xb9dce78a 0x2f0905c3
- 0xa76a7929 0x5f3fa1f0 0xca4e5260 0xccba772d
- 0x862fec80 0xb8257aa1 0x7c79cfac 0xc75d7230
- 0x387e536a 0xaff486e5 0x3c549063 0xeea5fc5c
- 0xc433a55c 0xbfb619b4 0xf36fb0c5 0x4faab4e4
- 0xbcd75d84 0x6eb5ee8c 0xaa4e29a9 0x551db0d6
- 0x1ccbc659 0x9b5e8c52 0x1e33bab4 0xcfd30d60
- 0x6366c21d 0x3f0d7056 0x7f2247da 0xaba4f322
- 0x7b0ec4fe 0xdd64dd73 0xcd538711 0x67dfcd4b
- 0x02d1b6f0 0xef0b6e60 0x1058738d 0x0c056ad5
- 0xb40abdbc 0xfc2549e2 0x6fb269b6 0x08f7ec08
- 0xea0a76de 0x7e97ee14 0x4eed0856 0x75ba49db
- 0x8145dd79 0x43101098 0xac911399 0xf8aab5ed
- 0x1e9d391b 0xb2a3fbe1 0xa394939f 0x12b8300e
- 0xa5f5200f 0xc350dcc7 0x1b2380d2 0xa599b322
- 0xe219e0d0 0xe4912308 0x0ad305cb 0x2e22d468
- 0x599eacdc 0xcf3b7eba 0x65fe5903 0x44f6cb16
- 0x0ab29b19 0xa74185e6 0x41736bf9 0xeaf231f9
- 0x762d0e7f 0x8b445ce4 0x173d3775 0x138da565
- 0xe4f7f652 0xe62e4ae8 0x91ce0ed8 0x1fc94878
- 0xe44acd84 0xe4402b5c 0x6437aaff 0xe7b0d8d8
- 0x514fbcf5 0x4b3bf5bf 0x0696b5d0 0x89a562ee
- 0x02408e77 0x94cc3287 0x47860ed4 0x42aedc7e
- 0xe9f0f3a2 0x4cf19812 0x3181341b 0xd72803a2
- 0x42f5c8b3 0x5735456a 0xef70c247 0x5943b8e4
- 0x7c62b0e9 0xc507e2e6 0x85a2c82f 0x95c6d92d
- 0xfeefff6e 0x5740c004 0x1958f117 0x44ebaa15
- 0x9f061786 0x732a8720 0x9483f974 0x839d5b20
- 0xeefb728b 0xae2d4b7c 0x49bcb243 0xd86db07b
- 0x73b0542f 0xc5a34fd7 0x5b9401fd 0x7f75e686
- 0xb239ec36 0x41e7943d 0x2bc517f7 0x27057733
- 0xf6c9cbd1 0x2965ef66 0x969b44e6 0x77b66e0f
- 0x68b93916 0x31d581c2 0x8520df18 0x16ce6af1
- 0x70bbf865 0x6d1ea78e 0x989ed713 0xf97c0d1d
- 0x538aef6b 0xf1ac3c76 0xf65f8bf6 0x4f4d3a8d
- 0x639d90ee 0x43079e8c 0xc9d50f0a 0x9b12ec49
- 0xaebe3d8a 0xd1bc3cc6 0x8b92e348 0xd056119c
- 0x7aec25f3 0xb3d2cf65 0x32c03540 0x53287cff
- 0x0bfa781b 0xf8610282 0x18a2d96a 0x541a6f1a
- 0x6052aac0 0x4f79e46a 0x7c868b93 0x6547a94d
- 0x58326c30 0x98e46f02 0x77cdd3c2 0x204ce551
- 0xa5e32028 0x679e3153 0xc7880c16 0xf32743f0
- 0x63c8892b 0x51d8a6ea 0x42bc6417 0xdb8ae71d
- 0x04c71f86 0x1a5bd80b 0x810f3b56 0x049580a6
- 0xd384d2b4 0x92cd10c8 0xaf4e6ce2 0xac955cc4
- 0xf57b42b7 0x1017f2b4 0x3031fafb 0x3d1a8024
- 0x3aca42cb 0x75514d81 0x454b1806 0x5505c3e5
- 0x26d2c642 0x57454f1b 0x5e2d3c9b 0x6535eaf5
- 0x370de383 0x6adfbbe2 0x513a5d0f 0xfc48c333
- 0xa0a70bcd 0x35777e16 0x5ecec516 0xb7879d7b
- 0x08928fd4 0x88c8048f 0x4a0d2896 0x5bdae2f1
- 0x8761b488 0xfae8bb60 0x3c8e8abc 0x13939d3c
- 0xc29493ca 0x585a71c8 0x43205f16 0x06a3be38
- 0x4be88f47 0xd2be8c8e 0x3d721e2a 0x43051f74
- 0x922a9a30 0x6391fc85 0xc4965afc 0x61f082e9
- 0xc2686e37 0x4f77b6a1 0xac47fa16 0x1eb05157
- 0xe6f767a0 0x24177985 0xdf80b368 0xb54d959c
- 0xa5719425 0x656c70de 0xf35dfd40 0x702d5063
- 0x4e7ac001 0xc4bb4fb2 0x4af7b9e5 0xe0eb5c48
- 0xf08b19c0 0x468b1471 0x74af9030 0x51d171e9
- 0x81a59926 0x55b893e4 0x17adeb1e 0x72084962
- 0x7f358bec 0xbd4363b9 0x75a56726 0x3a033a75
- 0xd0fbf874 0xa6bf634f 0xa5e4be7f 0x4cd8338c
- 0xef6838b8 0x1d458215 0xff7698ba 0x4ba19dec
- 0x87f58c07 0x2c7933a6 0x1cd4f99a 0x158bba9f
- 0xffcedb5d 0x256eb5d7 0xcb6dadde 0x980349bc
- 0x6169dcf3 0x94267861 0x168ba5e4 0xd2063474
- 0x156c9738 0xc4bd2c2d 0x31ad709c 0x58cd43e6
- 0x76ba9c33 0x070f490b 0x357c3929 0x103bef50
- 0x82ebacfe 0x5affdca2 0x96d0965d 0x60911a5f
- 0x65d4f52a 0x795b3094 0xf56291dc 0x6e614bb5
- 0xf701246d 0x4953b1b4 0x15e4e5fa 0xb6954973
- 0x43ada767 0x4c0a9f27 0xa47f78da 0x52375c95
- 0x79770885 0x479c5aed 0xca2ac2b8 0xee74cc5d
- 0x752f00d4 0x2b5532d6 0xd3641edd 0x05eb0e05
- 0x5118c9a9 0x47a0e0b5 0x5f12d793 0x92019247
- 0x27d77d98 0x0e413c92 0x76e4aea0 0x9fa8e3f1
- 0x3c57e54d 0xf4a60ba2 0x5bb37f64 0x8b214f1d
- 0x320f3bec 0x1cfd1f0f 0xb0cf5b70 0xf26a138e
- 0x37bb143f 0x993d3fa6 0xde4138c2 0x9fa287ba
- 0x137617ff 0x591624c0 0x1d10f02a 0xf7e350a2
- 0x76bc2933 0x12af6e72 0x1777e320 0x3e161b20
- 0x6c9fd66a 0x0b30f462 0x9cb717cc 0xee2902ba
- 0x466d7b9e 0xe97c26a4 0x7406b88a 0xf15a7209
- 0x3d2815c1 0x3eb961e1 0xe5321371 0x05f60ece
- 0x39168ef2 0x201a9dfc 0x90fdb132 0xe4531401
- 0xbef01e52 0xade4b385 0x6ca0c911 0x7586ff60
- 0xe457457c 0xfbfa3688 0xc826a1e9 0x10360416
- 0x192b51d4 0x18471973 0x3f0dd5ae 0xea2bbfc1
- 0xbe099b58 0x8bd8efda 0xdfc56e40 0x9e50f4e9
- 0xceeaab0a 0xd1eeb5d2 0x840a3cd2 0x6b739449
- 0x4a94e95f 0xe53720e7 0x68c70986 0x1cec3aeb
- 0x2423ad9a 0xe83b9246 0x7ac4b815 0x3796ec1c
- 0x65ec7484 0x79e5b0cb 0xd25f4790 0x55573d75
- 0x0f24c1ae 0x6d5d9b62 0xf3b2788c 0x2c695087
- 0x0980abb0 0x5086c2b1 0x26a247e9 0x72071084
- 0xe76c66a2 0xcc9c0bba 0xc67723b5 0x19a809d9
- 0xddc03879 0x7161b52d 0x24ee285c 0x5a345427
- 0x0626ef30 0xb734a77e 0x8ff087f3 0x80222e05
- 0x91b6c40a 0x4fe76862 0xef66e1df 0xeedb9f06
- 0xb785ea7e 0x0e84aab2 0xd0a669d6 0x7ccc77d0
- 0x264df92e 0xe9d1b14a 0x4b517134 0x05444463
- 0x408e7bb2 0xe7ad2bc4 0x5d8cb4c5 0x61e508ab
- 0x9798953a 0xa6848924 0xf26be53c 0x8940d4f6
- 0x56f11005 0x6d8d60ef 0x03c374a9 0xce0dbc18
- 0x341e634f 0x64e7d2f8 0xeb201eb7 0x2dee184b
- 0x57ecd83f 0xd8f644a9 0xca4493e8 0x66347804
- 0x542e06e8 0x55f607ea 0x7f425fa6 0x362807b4
- 0x731c87c3 0x4b5d6e1f 0x03e70201 0xbc5f4080
- 0x899cfd7b 0xa651d567 0x9c333e24 0x8b0eedc1
- 0x53ff0c74 0x7db69633 0x6637bbda 0x5ce53c7c
- 0xe93bd003 0x91234974 0xe8a626f2 0xc6550418
- 0x1b4157aa 0xc42ff7e4 0x1b9213ae 0x70d84165
- 0xc7cb09cc 0x38bf0221 0x238ff6b7 0x3688fd5b
- 0x5694728f 0x4a8e4cfb 0x3cd7e1d2 0x72a41c1a
- 0x2d098e4c 0x5a0ab21d 0xc8a40160 0xf252b062
- 0xc172763a 0xaedea2e4 0xeedcbcf9 0x4c0d2216
- 0x02b5eba5 0x410139da 0xde4ff14c 0xa53ca456
- 0x8c30792f 0x6af27a7b 0x734b1dab 0xf4f60014
- 0x79fc3cc7 0xfc578e4f 0x20948f41 0xb4fbe4c4
- 0xdbb21292 0xac1aa341 0x7ffb8913 0xa498296d
- 0xae1e8f6a 0x167d82cb 0x094513fd 0x8f0810c7
- 0xd01d348f 0x700d0063 0xeaacbad2 0x23d45e0a
- 0xe3b3a244 0xf2f7100b 0xf680fb9b 0x529efdd1
- 0x01dc5480 0x263328c6 0x686fbe31 0xbf3a1057
- 0x34c763da 0xae45207e 0xcb5abb2b 0x011c0faf
- 0xde2b6f4e 0x3d95034b 0xacec6e7a 0xc792595e
- 0xeb3cd922 0x7894f0d5 0xd9a7e62a 0x1a3c2ea9
- 0xa8f22d99 0x1ffaa636 0x47c6f1ff 0x69feca71
- 0xcf8d73d6 0x1c85d0fd 0xcce984c1 0x993f7a9f
- 0xc095c139 0x1c013486 0x675a753e 0x01030902
- 0xccab4cd7 0x0c14c605 0x5ebc19b1 0x60ad33a1
- 0xe80e1200 0xdf49db31 0x855aee7a 0xbfa37ef2
- 0x135d844f 0xdde541e3 0x0522f180 0xa27312bc
- 0x57046808 0xb96fe1b6 0x77c2806e 0xb90ac06f
- 0xa425864e 0x857ff22f 0x16eca5a6 0xbaa58ca6
- 0xab30772e 0xb20507fc 0xa593f6cb 0x9e7e8409
- 0xac4ecd8d 0xa9c0561b 0x0c462492 0xb3ee5aa1
- 0x83d3d56c 0x5bc20412 0x03365294 0x09758ede
- 0xe9e6968a 0x80ffc576 0xe62ddfd6 0xd5934635
- 0xe07f36e1 0x99c0db4e 0x2dcdb7ed 0x68749a34
- 0x4f718748 0x630b1315 0xe632adbb 0x4c111085
- 0x13bbfaf1 0xb70bd522 0xf22068d1 0x4ed37edb
- 0x7c50ff42 0xa6b61456 0x828deb4d 0xf19dc8ae
- 0x7ed7560e 0xb47a1aed 0xb79beb35 0x720d104f
- 0xff5ecb74 0x1e7d9f8c 0xa69f72fc 0x743e81bc
- 0xa11aacfc 0xab8fdc17 0x263ea36e 0x840bc0ec
- 0xb994aefc 0xcc5922c4 0x08411c01 0x0073895d
- 0x7b661458 0x8bf91a68 0x93112089 0x541e53ed
- 0x37706daf 0xc8733951 0xe74fa74e 0x638cfb72
- 0xe696bdc6 0x87f4b7c7 0x413acce6 0x16642eec
- 0x83b0ecf9 0xcf770d15 0xa4aad143 0x2ecd9f9a
- 0x5bd7a2c0 0x07dca9c3 0xf6ab7c5d 0xaa4a55c2
- 0xd410d6a8 0xdb84dc85 0x6b8e3aa6 0x8f268bb5
- 0x1e9604cd 0xb5fabbcd 0xc8a519d7 0x07fdab7f
- 0xceee08f1 0x08b9566e 0xaa646716 0x4ba7ca9f
- 0xe0166e0d 0xb31e9561 0xbb9315cd 0x42201352
- 0x5eae88f3 0x8b8e8eee 0xd63d0610 0xe64a45bd
- 0xc2e8a084 0x2e421cb3 0xda754ee9 0xcdfe2c8b
- 0x52b5544c 0xe5c0616e 0x387916c6 0x204c7ca3
- 0xdc507264 0xca026018 0xb4dc7a91 0xa9f27453
- 0xfb6995c8 0x349b640d 0xe59e1670 0x53d18974
- 0xa61ee5e8 0xdc8b88d7 0x78d2f8f8 0x72ddf8c1
- 0x7345705a 0x1e6ecb19 0xff0f4f31 0x197ae361
- 0xc2e43f5f 0x80a2bf1e 0x274d46c4 0xbb3ae1ff
- 0xd59798f3 0x5bf16015 0x871d2acc 0x4044c5b1
- 0x9ea15fc0 0x9a735765 0x1683fd6f 0xfeb503d9
- 0xc3de1998 0x14405d5b 0x86b76966 0xb3893dbd
- 0xdb365404 0x6636d465 0x63558798 0x758d5f12
- 0x6e225d18 0xad787cc5 0x775a5c1b 0x68112320
- 0x23e1ea3d 0x8cf63961 0x0596cb9d 0xe9ca89e5
- 0x96cb88a3 0xb7cac802 0x3b38edc2 0xb455d1ae
- 0xfb215ed9 0x9cfe7580 0x0410155a 0xc6b75ca3
- 0x359ef846 0xf96db47a 0x9800cc06 0x9ab0eeac
- 0x1c86094d 0x19537992 0x3cc54b13 0xe877a758
- 0x35c01849 0x396470de 0x8c229cb6 0x2b01a145
- 0x54ae9638 0x33b0bb07 0x5d38fbfa 0x3a08d46b
- 0xab433b4a 0x6be993fa 0xe85fe0e6 0xd4d2b82c
- 0xc35398ca 0x66200602 0x51df5ed3 0xddb67c76
- 0x6a4c2d36 0x9a02eb04 0x8ce871ce 0x66753dbc
- 0x5441d00a 0x3d331728 0x80c55fcc 0xac286e97
- 0x71fad042 0xe99c0cdb 0x3120ef01 0xfabe32e3
- 0x265699eb 0xa73e31be 0xdd44e3fa 0x668531dc
- 0xd4ba1078 0x0f13c8fb 0xa136ed20 0x010f3c83
- 0xb3f8eaa6 0xc6d95837 0x0e09bd46 0xf0ecb760
- 0x8dd905c0 0x02cbe8fd 0xfa898489 0x14ab16b4
- 0x6ae99a74 0x516a171a 0xaa60c4c8 0xc075f0cb
- 0xef530ecc 0xf6fffd33 0xe1d2af99 0x6913b9ec
- 0xc96666c1 0x20743c9d 0xf65cd424 0xa671b903
- 0xcbff34ba 0x60df0c1c 0x0d610133 0x4281a959
- 0x656230ac 0x1693d52a 0xf4d37186 0x203caa5c
- 0xa54cad8d 0xea1c8816 0x5bd54f8c 0x2a3c33c3
- 0x151f72b6 0x63061580 0x0bc7f244 0x882f7656
- 0x243d76fe 0x9b3bf7c6 0x3337a21b 0x8b9e3e63
- 0x106289a1 0x74ae0571 0x8a43a5a9 0x7ad8c804
- 0xb6867d45 0x45732f84 0x0d1773f6 0x9fc01aa7
- 0x7b192c33 0xeeab4a4c 0xc96ae493 0xb5aad8be
- 0x8b32c8cf 0x8ebf63c8 0x5f2a5e17 0x43a2899c
- 0x35ec1fc2 0x7c675072 0x6673d01f 0xc1d85b58
- 0xf73dec41 0xc1c89c18 0xff8fac98 0x434c3c5d
- 0x184ee2bc 0x3469f366 0x2558fbf7 0xa0e5622a
- 0xebb39f69 0xe9020554 0x3cd80512 0x767bcd48
- 0x2e388fca 0x32eaa226 0xeaf4f6a4 0xbf7fb5ce
- 0xdde75b24 0x30365d1b 0x48fd5203 0xca805f98
- 0x82526a04 0x51a8dd82 0x61fdd2d0 0x3ef56891
- 0x6d5d53d0 0xd83646eb 0x1d7a7086 0x7ac52300
- 0x69e4359c 0x7c8058f5 0xf47d703a 0x21b863a1
- 0x608b8362 0xb9a78389 0xa9d2280e 0x16672055
- 0x05501917 0xf2e01be2 0x261a10f7 0xfe455dd0
- 0x902a0cf3 0xbed63a74 0xeb4bfe27 0xab8b091c
- 0x4cd8f22e 0x48dbda13 0xb3d29b0b 0x65bf3d3f
- 0xe9be4080 0xfdbf0a24 0x9181ebdc 0x5faf48d6
- 0xaaf1acb3 0xe2a2aaff 0xe1ae56f7 0xbd475702
- 0xbfbe292a 0xa6133579 0xadfd6723 0x289485b4
- 0x92667c06 0xee16866a 0xfbc71087 0x0cd78050
- 0xfd40dfba 0xc9834441 0x5cfac60c 0x844b44ba
- 0xe1e4d8ac 0xd6775e4f 0xd4f01979 0xab5faf6a
- 0x63e03982 0x7789e272 0xb75dd171 0x39d0666e
- 0xbd90a902 0xa4eebba3 0x2640274b 0xbcedd52b
- 0x87033b15 0x2048812d 0xc13c2230 0xa7d345d9
- 0x84b4fb4d 0xbc0960cc 0x4c7422ec 0x4bff7ea9
- 0x16315057 0x1a9c50ee 0x5441830e 0x61cc7b9d
- 0x2f7cd3eb 0x6ae05c81 0xc264d759 0x4c6dd592
- 0x3d47dbbe 0xf8797367 0x4ae67c6a 0xdb42d373
- 0x0f6a6e9f 0x3d6c6b82 0x16906b77 0x80f7dbbc
- 0x6ee0683a 0x1afb8d53 0x4df1322e 0xc7d489a0
- 0x9d06aab8 0x08c5ebc4 0xd8cf4766 0x0be222da
- 0xd45596ee 0xa8113953 0x1a42b7c0 0xf4de2c73
- 0xe5741505 0xeb9032d7 0x480ab9f4 0x595e824f
- 0xc87c4e6a 0xe636b3c0 0xddb3438a 0x03f6ba20
- 0xd43d9bf5 0x3bbe086f 0x6385fdd6 0x0b9d62ae
- 0x1b9fc458 0xf6d1cffa 0x168ec5f7 0x93c98771
- 0x018c51fc 0x3a6c5880 0xbc4d25c9 0xb90c47db
- 0xccee6371 0x289878aa 0xb63ebf23 0x9fdff591
- 0x863d71c7 0x1301cab8 0xead66f03 0xf8a74303
- 0x91439b31 0xcbfc5008 0xc78a05c7 0x172ddb38
- 0x16254ebb 0xf490cd3e 0x9724bdba 0x915c5eaa
- 0x2d971801 0x672389af 0x25023172 0x69fb7e23
- 0xc5d66742 0xdb578a72 0xbb6fe6ef 0x9ff3920f
- 0x9e04e6bb 0x9bd9079c 0xe70a3479 0x1f423c00
- 0xd3a901dd 0x7fceda2a 0xf1999db6 0xeb73cb34
- 0x891cf0c9 0x55313b9a 0xe74ad3b2 0x98fc0593
- 0x9ec6c756 0x7b84cb06 0xb06c9cf4 0x604b8b04
- 0x112e4063 0xeec6c6a8 0xab9b6bb0 0x33e24999
- 0x14c1cb98 0xac0fdd7f 0x2b9a1d04 0x7fb3667d
- 0xd4375e71 0xe0b840e4 0x1c0789d3 0xe67c6b6e
- 0x00b8439f 0xc0be1ba8 0xfd6bac10 0x3a7e3be0
- 0x3c6a0d2a 0x38eb71ab 0x43711d1e 0xdbce233d
- 0xce91e57b 0x2f386b58 0x88ca7857 0xbe5bf50e
- 0x487a5b5d 0xb6470361 0x91e09471 0x18ee543d
- 0xe1857917 0x60d489ae 0x5d44c618 0xc6f46454
- 0x3cc37b33 0x9f8cf96f 0xd365b8f1 0x721f6448
- 0xdbe1a2e8 0x81651a33 0xcf105b61 0xf4ef4f94
- 0xc4693805 0x801e2a58 0xc932d045 0x6352f5b8
- 0x731cb8aa 0x3b2a6546 0xad87d205 0xa6b41613
- 0x8cc971a6 0x5cb47978 0x86b89ba4 0xb482b4a0
- 0xe326080c 0x821b137c 0x2a154131 0x094b02a8
- 0x56a1868b 0xa8a38181 0x8815878e 0x749bb12a
- 0x8bab2a16 0xfbe0bfd1 0xabef2266 0xd59d9169
- 0x975b6018 0xdb45a39d 0x6e31771d 0xa373d6a0
- 0x214d69c0 0xa4cfc886 0x30a8b314 0x558b670c
- 0x7cb96533 0x9c6c1dbd 0x3bae20a8 0x6a792685
- 0x1a5d6816 0xd085f694 0xcf367101 0x908cc2d7
- 0x9a7eed70 0x1e19978c 0xbf77c25e 0x5098a627
- 0x2129095d 0xcb5c81c7 0xa2888a61 0xc9df4b0f
- 0x0f20511c 0x6a16bb53 0xda26eb80 0x9a0190c2
- 0x372ff753 0xe1ae8ecb 0xe54e1e31 0x967b935a
- 0xd58c26d6 0x7d4a5515 0xa8f41efd 0x737a8b53
- 0xb2a33b65 0x7d04ef67 0xfd491b9c 0xffe6c29c
- 0x54424355 0x50c502e3 0xd8400ac4 0x6f17dffe
- 0x8be39f17 0x6b3055b6 0x20c445f3 0x6cef7ee4
- 0x821cfb2b 0xab19d476 0x540476d6 0xa6d1099c
- 0x223acfda 0xbda49356 0x403d63a5 0x2b83600e
- 0x45e5e0db 0x10323cf9 0x80675f78 0x6acc9d72
- 0xf0d7b6bc 0x122fbbaf 0xafef53d0 0xa606b680
- 0x13e91e0b 0x95a464dd 0x54ae9057 0xf12e1c07
- 0xde806b00 0xce8904ca 0x44ef27a3 0x14f85e0a
- 0xbc1bd0a7 0xa19863a4 0x7bb14eab 0xc3fe7ff3
- 0x1c915fe0 0xfa45a07f 0xab471bb8 0x335918ae
- 0xbc91e280 0xd27ab8c6 0xf79a0fec 0x0d54b501
- 0xf870aaee 0x44c1b504 0x60d2338c 0xe2f01abb
- 0xad4ca3b9 0xe8f97018 0xb3810e3b 0x3f885db3
- 0x6890f6a4 0x8568faf9 0x503d9690 0x709dc422
- 0x11f02c4f 0x57305bce 0xc1e07251 0x3b8b0c3d
- 0x3da8d742 0xe5956aa6 0xf394f116 0x07daa257
- 0xfd5b1b25 0x354b3d77 0xc2587f36 0x6fa8083c
- 0x6b8b8a0a 0x71cebc82 0x799e5566 0xd66e6525
- 0x3d80e29e 0x0a1dd883 0x7886487e 0x5d80604e
- 0xf7533c54 0x53c428c2 0xdb5c0cb9 0x211fbb3a
- 0xc7fd4590 0x409ec2d9 0xce50ff5b 0x142bcc4b
- 0x475f8d75 0xdc4b4f3a 0x1f230600 0x863d868a
- 0x5a8cfd49 0xc761fa43 0xa2ee8f88 0x5e8dbe56
- 0x9a140e41 0xf5c00dcb 0x04786e5f 0x6c2baa7f
- 0x9e4cb1d6 0x4074ee5d 0xbb4f106e 0x9afa4259
- 0xefa345c2 0x806cd3a0 0xf51afbd2 0x653502a7
- 0xcdf6fac2 0xdf756b85 0xb89ef192 0xba0b2652
- 0xea1b3853 0x4edf3f15 0xccaf559c 0x11721dba
- 0x36ab3f38 0x198d218d 0x5bdd7b39 0x3be8d3cf
- 0xea3e6882 0x6ed8fc9d 0xbffeed09 0xe513b75e
- 0xdbb9f2c9 0xf693d870 0x7bed8b14 0xe98cae50
- 0x591d36d1 0xba55333c 0x20048cad 0x7104e6ea
- 0x08a1335a 0x6dc416cf 0x431d8dfb 0x3f4db80e
- 0x3ae3f65d 0xdec93bf5 0xe1773712 0x8b9d6e9e
- 0x7a3599f4 0xa6292450 0xb7b68277 0xe57c20ce
- 0x3cf4eb70 0xf00d3dd3 0x9da300bd 0xa4b25418
- 0x6273314b 0xc5be2c6d 0xf297eb77 0x851334b9
- 0x9eba7308 0x7a015151 0xa3416ae4 0x7c54c0b7
- 0x352083c7 0x5c56ffda 0x1cf4d4e3 0x6ffef4b0
- 0xa8c972d1 0x6db1761c 0x4b2f3400 0xfab16aaa
- 0x437f0125 0x0c3ba2ac 0x89680f6f 0x7e48432a
- 0x0e465f0a 0x943cc778 0x075156f7 0x46249153
- 0xcbc017fb 0x0de6f92e 0xf380bcf4 0x9732a788
- 0x6e01dc94 0x5329275a 0xec971ab8 0xea971178
- 0xc1e3cbee 0xe598c0af 0xc5ca63a9 0x06018d8c
- 0xc55446d0 0x18e04c29 0xd19da94b 0x74536dd4
- 0x9837bbec 0x64bba10b 0xa63810e6 0x2189497c
- 0xfab9e5a0 0xde0267ed 0xbfb94a58 0x377e52fb
- 0xc8f5016f 0xd34b0180 0x2a5e942c 0x2ca6fe08
- 0xfd52fd5e 0xcc2f838b 0x7aeb73c7 0x43832892
- 0x2a44684b 0x0d8a7b22 0x9b84347a 0xacfedd86
- 0x966aed18 0x66eb4a8e 0x890108b1 0xda13caac
- 0x36c0f2c2 0xe2d85d85 0xc51f9f4e 0x9594e1b0
- 0x0707929f 0x63fa9d30 0x2b461080 0x18566f8d
- 0x40e12ea7 0x83e37963 0xa8d0eab6 0xb242700d
- 0xd928ecb1 0x6f5d6d73 0x603f5d48 0x4902cf34
- 0x9a477f4f 0x1b282220 0x3645ae11 0x09acad23
- 0xf772e479 0xd3c5b6b6 0x09abad03 0xdcbffe41
- 0xc971e22a 0x360a0c86 0x102ee956 0x9162221c
- 0x6a59f30b 0x9685277a 0x6dc283ba 0xcffd7ce3
- 0x0e487e66 0xd4dd807b 0x686bd0f2 0xc44a3392
- 0x6422fa86 0x6716d62b 0x2ac73404 0xc88fe77f
- 0xc49b6e01 0x8f011f47 0x5bb1ac5d 0x1d0ba4e8
- 0x7eb0d0c7 0x9db01b4e 0x6cbdaccb 0xd46f1c0d
- 0x96cc24e9 0xdbbaf254 0x9c5c45d6 0x325aadfd
- 0xca9638fb 0x1aeb36f3 0x8be8295b 0x705d0bab
- 0x9ceab5e3 0x5eb5288e 0xd7ec61fc 0x69bb3afa
- 0xad60164b 0xc435c21c 0xeb79ab88 0x145a58f4
- 0xae1e30ea 0x29987183 0x0a2a0432 0x160daa37
- 0x14e295e9 0x978315c9 0xf323f88f 0xe24d5136
- 0xae6ed24d 0x4a812cf8 0xd1e45d3a 0x64894447
- 0xf47d0453 0xb6fb5f02 0x34685ba2 0x8c700222
- 0x4dec7d3b 0xf035a0dc 0x9a802102 0xc3e27d5f
- 0x1928580f 0xeaa68f5c 0x46aad88c 0xfa913719
- 0x4fb0b232 0x3a638afb 0x4cd2068a 0xf26e4c98
- 0xe9da3c5e 0xc7ad41bd 0x3f1cc280 0x1fca9886
- 0xa777ff80 0x1ca76273 0x6a63123f 0x46d87fb4
- 0xd9282597 0xab9e06bf 0x3e244814 0xd9653380
- 0x48ab7d76 0x65d98e81 0x06047ee3 0x29b7ce31
- 0xae94d96c 0x856f9e8f 0x158f1b6b 0x9de1570b
- 0xca4ce67d 0x6f09907f 0xc891e152 0x6867c97c
- 0x02a5b2d4 0xf2e7c715 0x84f6da46 0xd603e51d
- 0xd837b33c 0x70de8d6a 0x598dd9df 0xed29a7a6
- 0x42da0f62 0x893fc276 0x56b43a06 0x949d4f05
- 0x7dde2d34 0x8b3f4c32 0xccc9c0af 0x01fdbdd1
- 0x2a3a3cdf 0xb6763454 0x7377862d 0xb99dd58f
- 0x9ad6cf20 0x2f80a8b8 0xc11b356d 0x4adae4cb
- 0xe808d693 0x3e8605d2 0x005cbfb2 0xfe966e1d
- 0x713b365a 0x4d12fc2f 0x1664286b 0xb5d41f0a
- 0x4420d15f 0x63e106bc 0xc2fe4169 0xe5f440c4
- 0x7fc0ae73 0x35ba3ba1 0x7a228157 0xfc50c107
- 0x2bd1f472 0xa9d03dd6 0x62d1a612 0xf93c55e6
- 0x6677a632 0xcd874d7b 0xa76ba1f1 0x2d82a8a8
- 0xa65e30ef 0xe48eaccf 0x4d7a4adf 0x8c276f69
- 0x0e229210 0x0096b100 0xa039ae73 0xea245d6b
- 0x0ea50d26 0x99b480cf 0x159ea81e 0xfa45f5a4
- 0xafd411d8 0xe1190cd5 0xc9e85cff 0x1e037ea1
- 0xf4be41e6 0x48fd1c6d 0x24d52f02 0x3780b91f
- 0x8e31dd07 0x1d392b15 0xb07e9d5d 0xf05b19bc
- 0x4f52d03d 0x846cf6a0 0x4d51d2e6 0xe4144ab9
- 0xa8f9558a 0xdbea007c 0x770f27bd 0xef95e02f
- 0xc01ba9db 0x8ad80d07 0x039bfc69 0x8f5d2e43
- 0x8640ff02 0x31872f4d 0xb959380e 0x027a8268
- 0xf39dd7d6 0x7c84199f 0x8f977814 0x6830b481
- 0x46495e33 0xd5c68952 0x6f2c3636 0x8de0e29d
- 0xc03f0b39 0xbc54910d 0xfa46af50 0xe81542c8
- 0x462d1ff8 0xb229a9cc 0x6a234b00 0xc96f857d
- 0x0a932f55 0xbd7fcba7 0xf937d965 0xc90cfd53
- 0x2ff150f6 0x0f5a40a8 0x805bfff9 0x92056edd
- 0xf6326626 0xe18371b2 0x9b9ce558 0x252d7e17
- 0xfbb7fdfa 0x3cf275e9 0x8ddc0be6 0x7e83319f
- 0xc61ee1ef 0xee1751d6 0xe267323c 0xd7229015
- 0x4a9cda9c 0x841730a9 0xd924dc44 0x619f2cee
- 0xb5172002 0x210144df 0xf6fda998 0x64f75cb0
- 0x3cd50175 0xdc7d3564 0xad0e94bd 0x18c876d5
- 0x7532124e 0x3b99841f 0x1a2c6219 0xe7d5ffe8
- 0x9f76b0ed 0x63437918 0x2b14f1ce 0x898a1cc3
- 0xfad43f4c 0xde5adcb2 0x8b9d0166 0xb4f2370c
- 0x1d212e4b 0x1f55058f 0x26bc79ad 0x681d1014
- 0xe0ddd0bd 0x4c256b7d 0x7268e89e 0xa422562d
- 0xd7a55326 0x6955e943 0x86ccb09f 0x03133a0e
- 0x2fe2399d 0xd9601d6d 0xdd128b8b 0x182251f6
- 0xa041ce84 0x5b5bc49f 0xbad64d6f 0xa7594fcf
- 0xb6dce9ff 0x69c7e4bc 0x83d16d70 0x41c2593e
- 0x282d55c7 0xcdcdddf9 0xd9855130 0x83fca027
- 0x32379a19 0xf8fa8dfe 0x0720d059 0xcba2a7b7
- 0xeab4e686 0x228601ac 0x660b45f0 0xecde3baa
- 0x4047d983 0x4ced2e8f 0x77aa1d0c 0x7e6cd6a5
- 0x80e06058 0x95d27baf 0x071433d6 0xc7d3d431
- 0x7856634a 0xa1b894d8 0x2faedc1d 0x1e05a846
- 0xa9bc7fa7 0x0ca15e02 0xbcc96351 0xb483c979
- 0x239681be 0x24354ba0 0x5c743a31 0x7ed77958
- 0x20a4d718 0x7b37986f 0x43a9e233 0x02091eb0
- 0xebdbf21c 0xffd2069b 0x6f191684 0x111e2666
- 0x8adb42dd 0xf26db866 0xff83d42a 0xc7d28a0e
- 0xec1bf909 0x10434bd9 0x6404e8c0 0xae30d43f
- 0xf415a59e 0x3daeca66 0xe1be615b 0x04db2d3f
- 0xa53b33b3 0x5fd6479c 0xab5ffe67 0x2cdaaaef
- 0x61087f2e 0xd805a00c 0x11d85656 0xc1ae3754
- 0x1fe38c7d 0x108e2ccd 0x3c6e1773 0x512eb70d
- 0x86142b5f 0x826ec294 0x956a3025 0x8b04e083
- 0xd69cd3bf 0x04f39016 0xf362b172 0x960466d0
- 0x230a3139 0x19378fba 0x335f3518 0x206a29a3
- 0x82465579 0xc1e4684b 0x9ac06746 0x1f0138e1
- 0x875a9aae 0x35ed8dfa 0x030c59c3 0xb3ed8018
- 0x2e91fa18 0x93739c48 0x172ed0d3 0x13722907
- 0x8e4e0426 0x47f72379 0x8bc54eb7 0x8657e9b7
- 0x0472cf9c 0x1424f3da 0xdf83007f 0x87aa810c
- 0x0e14e6e1 0x9d0dcfdf 0x9e7696b0 0xe019c6aa
- 0xa866fc9d 0xc19a1ff2 0xb187dffa 0x220adae1
- 0x16deb6d0 0x57bb035e 0x8084703f 0xabca8b49
- 0x577af6a8 0x520ff09f 0x3d87711f 0x1d2254a2
- 0xe161d5be 0x23287038 0x11722e48 0xdc7c6153
- 0x7e953ad9 0x1797ca90 0xd56bdecd 0xf7973432
- 0x5804968f 0xb688ad25 0xfda5e113 0x584d2c84
- 0xc5c02d74 0x7b6235b9 0x6c1712cf 0xb8ef7795
- 0x26d414d0 0x4b705388 0xa5725233 0x4e29eb6a
- 0x4e2f32b6 0x4996ed96 0x45b98f88 0x67ed828c
- 0x34e7af7b 0x5640103f 0x6aacf602 0x354d85f7
- 0xf6e8983e 0x1468e2dd 0xacae2dcb 0xd3bcf29a
- 0xa176799f 0x57a1bd66 0x7971495d 0x44dfac4c
- 0x32c643f6 0x57cc7b19 0xfee17e6e 0x1505f974
- 0xbaef1420 0x3b930cd2 0x65fd2cad 0x92ce1aa5
- 0x734f0807 0x65a5a815 0xa7124d4c 0x1ad9684b
- 0x32eb33c0 0x761f49ca 0x10b49a88 0xf0af198e
- 0xd7173b32 0x640b00ce 0xd3ffd60b 0x3a92cb20
- 0x71eccf6b 0x7c1c49e4 0xc7401cfc 0xf3f52441
- 0x736776c9 0xe8609667 0x8cbb06c9 0xc821f68e
- 0x827c67ac 0x0a98a704 0xd71e62bc 0x349fe1e0
- 0xac56ba89 0xd36baf48 0x54af6806 0xaeb2f143
- 0x0247d79b 0xfd27b357 0xec131b3d 0xd9fecc41
- 0xfdcb3993 0xec61c159 0x911a6bb6 0x849e85d1
- 0x5e4794d1 0x3c771cb5 0xdbc45603 0x76ef6090
- 0x4bfa505e 0x592b3fd9 0x05509bbf 0x2766b252
- 0xd9b66afd 0xe80fb26a 0x1ea90db3 0x61b1e2e9
- 0x5899953a 0x08c3bdea 0xe6393951 0xd2db7170
- 0xaa7031f2 0x5afce44e 0xed13e406 0x2af7388f
- 0xc6254e8c 0x3a846e5a 0x49de8429 0x56792361
- 0xa9fa85eb 0x4d97a05d 0xbd804c72 0x9e3f10be
- 0x94c6cb39 0x38a2729c 0xf71833f6 0xb9b36d59
- 0x8d7a74cc 0x4d9d5b59 0xaa9a735a 0x4ebac1ef
- 0xf073c9ee 0x38d2ea0f 0x87247f61 0x2e110dfd
- 0xca47846c 0xbcfd03d4 0xea058e96 0x40cb9628
- 0xaea31bc5 0xf39d05d9 0x246bec2d 0xb514efa1
- 0x5861299d 0x148ef9d0 0x1f5e33bc 0x444e79ef
- 0x52d62130 0xf391282b 0x93fcd860 0x6c3065e6
- 0x8a739db1 0x51f6cd7f 0x2da05ac4 0xe8f8b6e0
- 0x48adb62a 0x8c0c687a 0x2dc37ce7 0x993b198b
- 0x31008c46 0x3e509467 0x514a6614 0xca7c1511
- 0x5d3bca38 0x3a8188ee 0xedc7da67 0x3d243fe7
- 0x209f9238 0x03b4bc67 0xbefb5ed1 0x644e60ef
- 0x708021de 0xe7a8f948 0x8ec69a79 0xdde65d7f
- 0x2304f3f8 0x616643fb 0x7343b800 0x102f165a
- 0x848f5616 0xa85d42ef 0xc725fcf8 0x63207a50
- 0xa10f827c 0xd23d11c4 0x9832e62f 0xe7e99da8
- 0x492e1355 0x63882a0d 0xbeb2e2e6 0x02fdc22d
- 0x1a696e02 0x9821f6db 0xadf34cb4 0x2b274251
- 0xc40e4a88 0x7b22d05a 0x42574be2 0x004de66d
- 0xccd4a41c 0xd19863df 0x2f1965ae 0x868d7221
- 0x07cf8546 0x3fba2d34 0xb39e65cd 0x425bf20e
- 0xa61be150 0x191d3530 0x4f975298 0x37e1f881
- 0xd45df57f 0xbaba406d 0x06385459 0x4b105297
- 0x1669f5df 0x0ff8db41 0x258d3667 0x8592fb19
- 0x20f3da88 0x8bc12e8c 0x4247ed36 0x9d6ad7ec
- 0x26128a8b 0xbfd08579 0x084e2fcb 0x9279b5dc
- 0x3a33654d 0x1e40c91c 0x8f0a953d 0xdfd96c06
- 0x8703d737 0xca1f3200 0x60ec2e4a 0xa8814a20
- 0x6d9950a8 0x4b2438ea 0xc6ca6580 0x99f2f4ad
- 0x42dc5043 0x1bec10b7 0xce44a349 0xa6b35911
- 0x3583a4ec 0x65bcf9c1 0xd25c3af5 0xcb72222f
- 0x97cb8371 0x85f75c9b 0x03b1d637 0x6f80294c
- 0x3bdb3942 0x91126cd9 0xd3fbb35c 0x752a7251
- 0x5ed886d2 0x19c91d06 0x7a883d41 0x550a9331
- 0x371f617e 0x61543776 0xaf4b02a2 0xa390ca74
- 0x99d106c5 0x3f8c2d8d 0x01ca467e 0x20e50f07
- 0xa40edcb3 0xdd2b0317 0xf96342e4 0x94a6e3ae
- 0x17431448 0x789ea7b0 0x7bb4fbf6 0x03839d5f
- 0x13f86c23 0xc6efbe86 0x9f891cd2 0x3e3af545
- 0x0b1d0457 0x481e80cf 0x406bd13a 0xb277b63b
- 0xfb5d99bd 0x6fea0963 0x5b48c16e 0x0ac10b3d
- 0xcfd388d4 0xe07a502b 0x4466cac6 0xaa21c31d
- 0x806ba060 0xf175bac7 0xfee9f170 0x38d1af9e
- 0xae1f0f7a 0x6252edb4 0xb23c56c1 0xede12e73
- 0x5747e22d 0xc3b58928 0xaf586774 0x9b6e8b87
- 0xeaf2016e 0xd1fa9a90 0x986a5882 0xdfe68064
- 0x5657ea69 0x237bbb3e 0x01e22722 0xb7bd28e1
- 0xb75d98c8 0x31ecee6a 0x861d60e1 0xebe8bebb
- 0xdc35606a 0x447f0a45 0x9f50d631 0xcaab3492
- 0x76035cd3 0x9d84a371 0x51b55a55 0x263fabd4
- 0x62ff9ab5 0x8b1ee33a 0xdc85e9eb 0x0471df10
- 0x29cabc6f 0x47467a07 0x6ee73133 0x536f5c8f
- 0x15f2a4bd 0x2ad7e8af 0x631a9bb4 0x9ce75522
- 0x228d008e 0x86fc05c2 0x5526b054 0x8db9d95c
- 0xdea2c7d4 0x1336add2 0x901543ce 0x2a855d2a
- 0x4c7e054d 0x967eab4f 0xca5c932d 0xec109941
- 0xf1752baa 0xd4b3a39d 0xd999886a 0x1a6cd856
- 0xb11f6348 0x60a21b64 0xea4467ca 0x51db6925
- 0xf8ee33a9 0xc674ce6c 0x5fa834a4 0x17f2b8ad
- 0x2eab9ce0 0x0ad42708 0xd8a6740d 0x164c4fe6
- 0x1f9d12c5 0x3efb12ee 0xedf0e724 0x7e8880ba
- 0xe9c55084 0xd9d6e9f0 0x8f4ec3ae 0x2d6aaa11
- 0x480e0081 0x28b6c152 0xee01619c 0x79ddd62c
- 0x4b17ea62 0xeda6fb70 0xd3673924 0x02e84486
- 0x4c0d66ec 0x9ab8cd5c 0x340fa6eb 0xf8db9df6
- 0xc72b2937 0xc09cdf2c 0x7ba60229 0x5318612b
- 0x08a07717 0x81cfe5ca 0x32a3b0e9 0x03cc518e
- 0x1085bd98 0x16069e72 0x6aa01ff2 0x0b512345
- 0x5ce6b51a 0xb58b347d 0x0dad3da5 0x7bc5aae3
- 0x81a88658 0xd9857a74 0x4fb95187 0xe03045db
- 0xbe4ddc3a 0x68be74f7 0x9663e4ac 0x4d31a7d2
- 0x7a2a70fd 0x03dde6ec 0x827e2f9a 0x17cf679d
- 0xb34aefe8 0x085aaebe 0xcff354e3 0x18754a97
- 0x10c4a4f6 0xb21d4e04 0x8e93af63 0x226ea564
- 0x6c3608a8 0x9fa96865 0x24f420b6 0x7d4a31e3
- 0xb7852762 0xd1c752f5 0xbcfe1a9f 0xe3cd44ba
- 0x800d6669 0x08455dfc 0x2bbdab4b 0xcc8cb0a5
- 0x268cd5d3 0x2b0cbe1b 0x40cd57e0 0x939c0f22
- 0xb85a1372 0x6c06319b 0x2be94501 0x9e13089d
- 0x2df0027a 0x47bb8a84 0x660234b0 0x6a05c46c
- 0xde9eb668 0x2fbef0ec 0x8e7391db 0x875bd721
- 0xa1e55bf5 0x31dc45aa 0xeb0fa893 0x36f0fbf8
- 0x8edacf6d 0x61c11564 0x9fe655fc 0x34378418
- 0xe032bb0a 0x5e996c49 0xaa576bb3 0x88f1f99d
- 0x08562a6b 0xa4d7900e 0x3d124350 0xf10984ba
- 0x65af441f 0x8329eb45 0xfa1c3069 0xd9c18941
- 0x6bf28004 0x32d89f25 0x107ae0eb 0xf23bea70
- 0x709b7c6f 0x7f6bc1b7 0x6829a1cb 0x770fec21
- 0x6dc4d64e 0xa37d7219 0xe5551a04 0xcd470067
- 0x81d6207e 0x81bc2a06 0x5330dc76 0xbe8b6aa2
- 0x5080f90e 0x7f393edf 0x37194036 0x1b19bf9e
- 0x4ff560fc 0xeb207634 0x2fa526e9 0x9c48acd4
- 0x9b9be6b0 0xfa749280 0x715fb587 0x50287f59
- 0x04bd42c6 0xf8674fd2 0x614fde7e 0xf0482894
- 0xa402a285 0x54813092 0xf50e474a 0xfa420315
- 0xfe7f82a9 0x835dbfdd 0x08540acd 0xabba517d
- 0x197c438e 0x3f69c2c6 0xdf1b60b0 0xbcc4b1c5
- 0xbb967e53 0x8a2e2be3 0xb78406f4 0x6cca685b
- 0x2877516c 0x3159fdb2 0x3f48f0a2 0x88c2ed5a
- 0xe8731530 0x227413ef 0x50b5610e 0xd0e7d76d
- 0x68b8a8e9 0x2f251606 0x0ba3ca68 0x3f470646
- 0xa473b7e8 0xa36ec586 0x0f41792e 0x4ef380fe
- 0x938d7626 0xbdf5914a 0xde6b5c26 0x26306e15
- 0xfbb123bc 0x9cd3a83f 0x5d621b36 0x9c391ee7
- 0x0921d18e 0x261a36c2 0x28cf5843 0x1b65db1b
- 0x28cf152a 0xd1308452 0x6aa9803c 0x8f11c7bf
- 0x42797ebc 0xd02410f3 0x56b4c779 0x22e788d9
- 0xc3fee627 0xa1673ded 0xa389d31d 0x47563835
- 0x4e963ba3 0x2acbc139 0x70da7525 0x39b3ada3
- 0xdf20f92b 0x1ff80e87 0xf847db4c 0xefae0a2b
- 0x42139d4f 0xd311a9d8 0xc54ccfcb 0x3b7c939c
- 0xb2eefc73 0x4908680b 0x30f160ab 0xa15abe60
- 0x31cdcc4b 0x2b5d457e 0xa264ccd5 0x73dfc993
- 0xa75c34aa 0x1b302cce 0xd5c93553 0x6982ca4f
- 0xf83cfac6 0xb1235d67 0x25780fb9 0x78af4f8c
- 0x76b1412e 0x139afea7 0x291cebe3 0xbd275519
- 0x18c300d8 0x33502f82 0x86f1d060 0xc83323f7
- 0xc8d57b77 0x928a2c82 0x9ba9d389 0x4942f49c
- 0x04c5abcd 0xc5fa8ab3 0x3e4936d5 0x6c5a6c16
- 0x69f97f82 0x277e2c29 0x4f5a84b1 0xcc546d60
- 0x887d8de1 0xbe980c48 0x6fb583bb 0x8f0dda22
- 0x64ed4be5 0xd3be3a6d 0x615532b2 0x260b87f7
- 0xb54915d9 0x9222464c 0xd447b5fb 0x08ef3c9d
- 0x1e68ebaa 0x16d60b49 0x67b5c5af 0xef5d90fa
- 0xf2fd3185 0xdb03838d 0x17ffffae 0x43304284
- 0xabdcf858 0xfa019d66 0x80a891f8 0x4b2898ac
- 0x676c113d 0x711d2b3c 0x59323717 0x912dbb50
- 0x55afd393 0xde134c0e 0xaaf1d1b7 0x97975a07
- 0xb66e6cab 0xfb0f54c1 0x6dae6384 0x04405a5b
- 0x95df053f 0x125f371c 0x6656c332 0x5801265f
- 0xcf365f00 0x31c300a5 0x2a7617ca 0x65ce79bb
- 0x4cc96bed 0x1af82f49 0xfefea103 0x49054f1e
- 0xb9341875 0xb37952dc 0x1db40d2e 0xe23154e5
- 0x5a4e8bcd 0xed67b774 0x6639eb56 0xa4b3a6f9
- 0xc0918496 0x295261ff 0x08b0f294 0x54573333
- 0xff925b65 0x7872e916 0xbd5552d8 0x5d72050d
- 0x1cf126d7 0x9dfc6d65 0x3b107698 0x0b9f2951
- 0xeba14913 0x5c065af1 0xb5dd50ea 0xbe47408c
- 0x3c9da76d 0xbafbaad6 0xef2b0118 0xa97bf92a
- 0xf2d0b2d6 0x39c8bf7d 0x3017810f 0x35583abd
- 0x2f430d70 0x7d08a9a6 0x4304c566 0x295fbed9
- 0x07412bc8 0x833dd8bc 0xf086a3c8 0xf0836418
- 0x85985a3a 0xd620dec9 0x3c81fc7a 0x08fbadb5
- 0x55d56912 0x6e63f48a 0x3e178cb9 0xaf43c5d2
- 0xce83c97e 0x0b59010c 0x7806f1e8 0x5ceda01b
- 0x0cbfd565 0x1234bea9 0xadf6ad5b 0x68c5c83f
- 0x7b5ceb7d 0x55bcd3f5 0x1e1fe06e 0xe6c9bce5
- 0x95b5563d 0x0318973d 0xc2c4b750 0x8297ff40
- 0x1223837b 0x8264fea3 0x1e9a70df 0x69ed57ff
- 0x9598bb0d 0x1647c7a6 0xc2f1e9ea 0xc47f77d7
- 0x5e088380 0x31b7cf46 0x7aca1985 0xea1bcad7
- 0x058afbcb 0x05929ff9 0x2d5c85fa 0x19b2eded
- 0xfb6bd501 0xa0ea0987 0x4b8dae5a 0xc9bc0d84
- 0x2d1841ff 0x58b4bbb3 0x5f3494c1 0xce489fcf
- 0xf048eee3 0x8a146cfb 0xcb5d2fce 0xf24dc8ab
- 0xac9a22f4 0x1c0e8be0 0x8f1982e2 0x979abeb6
- 0x2e61de90 0x7096ecd1 0xe6326066 0xf6b2c331
- 0xc8035863 0x23ac48f7 0xcc6a8a96 0x6d2a847c
- 0xe3cd2dfc 0xcb224f09 0x5274254d 0x1052513b
- 0xdd244a04 0x2b583887 0x24b623f9 0x1cde29e4
- 0xf86fdcab 0xf3fbee4a 0x34804cb5 0xe4d2d1be
- 0xe3ee0459 0xba8e1428 0xd0d61467 0x493d74a8
- 0xda33b30c 0xef080476 0x6c4f86a2 0x3917c5f6
- 0x14052bd1 0xc5d10f70 0x3eb72eb5 0x2939b07d
- 0xcf722a48 0x330615a8 0x797bfb7e 0x9c604abd
- 0x612ca005 0x716bdbee 0x8098f5f9 0x4a591363
- 0xbd89a21f 0x5e3787ea 0x2acbffa1 0xff907f14
- 0x42ca9221 0x4d15a235 0x76d4e9bc 0x2080e33b
- 0x6437bd3d 0x3d5b4267 0x9ac9655b 0x857b5a56
- 0x8db93b3d 0xe1c45c90 0x0872b3e1 0x4935532b
- 0x314c8628 0xa43c7d03 0xba6468b3 0x93056b1d
- 0x60e61ab4 0xb6995957 0xcd37b047 0xc50cd92b
- 0x259a8690 0xc78684a3 0x96384186 0xd9bcb24d
- 0x31b39f0a 0x0fbbae5f 0x869a70da 0x80f0714f
- 0x50070cea 0x2643b25c 0x164c01e3 0xc77d8624
- 0x48f047b4 0x0cbd2c71 0x4c0b13b2 0x667fc4a4
- 0x848c28cf 0x05443953 0xfdbd5329 0x3aeae7b7
- 0xeaa0de2d 0x498be6e8 0x9663391f 0x8d55c785
- 0x20c68ab6 0xfc7591cc 0x5f757324 0xa30d684f
- 0x6ccb9c33 0xe90c74ae 0x488bc0dd 0x08231a14
- 0xe253a7fd 0x9196b1cc 0x25a54296 0x0f70ba47
- 0x9ee0a233 0x43c2e7bf 0x2d927857 0x1fde792e
- 0xc0598134 0x7aac6123 0x39da69f7 0x99233284
- 0x5894e482 0x396fb16c 0xcc554518 0x61784cde
- 0xf12b0d7d 0xf1e7ee64 0x53a93eaf 0x142d292c
- 0x52c36ba0 0xd9037d20 0x9eba60f0 0x4a041620
- 0x5462a0d2 0x9ae6663b 0x0a5dfe17 0x9307f8f7
- 0xc3532fd2 0xd20b3393 0x82d40f2d 0x3b139fca
- 0x6ec0948f 0x1434629e 0xa529a79f 0x3a607eee
- 0x07ee780e 0xa407a5ac 0xbad8d686 0x888401a7
- 0xf221e944 0xe8ba61c6 0xc3caabc4 0xd610be89
- 0x0e5432fe 0xb38b44a2 0x65a48b8d 0xcc044491
- 0x253a116a 0x96c20a3a 0x13bf416e 0xbd80a231
- 0xc94420a6 0x8ffee6ea 0x35bd2c90 0x39bbc314
- 0x762981a5 0x7217db3b 0x8ace0761 0x31e2506a
- 0xf1d679eb 0xab0b8a9b 0xaaff2f04 0xf40502fd
- 0xe56aa165 0x418522a3 0x2fb1212e 0xc25102c4
- 0xae39da06 0xe708d400 0xfedfc55d 0xcf13fc39
- 0x77cc3ff3 0xb70b7ee5 0x57e2732e 0x54eafd32
- 0xee513833 0x2f2f685e 0x17c8b664 0x4b22ab02
- 0x684951ca 0x67844071 0x27c3c09e 0x36f129d3
- 0xf5d71bbc 0x251d6129 0x6cd71b6a 0x975e1d42
- 0x89142f16 0x6c250a42 0x9058209b 0x7f713bc6
- 0x7bfa7c2c 0xe6a5a5cc 0x90a74d5f 0x79902546
- 0xd43e0042 0xc3b12519 0x2afa12af 0xf11aadc6
- 0x5ee59722 0x802b403c 0xa282210c 0x7658c843
- 0x88a81f68 0x25b8fcd9 0x967d3058 0x1ecbeac8
- 0x9b1f0dc3 0x16dd19ac 0x3c279aa7 0xed5c8077
- 0x2c03b915 0x3b0cd605 0x3677eef0 0xddddb73e
- 0x407a5512 0xb8cbb129 0x7d6f0f97 0x96e41ef0
- 0x7d1bbca8 0x7fa26a3b 0x025ed42a 0xceea965b
- 0x4a10020b 0xc3c47832 0x171644f2 0x75baa013
- 0x436abd20 0xc7000fa8 0x03123e13 0x3b80f711
- 0xee4401b5 0x34bb57b4 0xb7fd072c 0xfb5cb343
- 0xf6ed3bc1 0xd83b2953 0x9285bbb6 0xb9e9afb3
- 0x23ef8322 0x46111ee3 0x1b5ee880 0x994b4698
- 0x11348ba1 0x358ca0d0 0xf9e1e517 0x58150115
- 0x31b69c9c 0xb59d1a14 0x736d1af4 0xa2b6fb4f
- 0x6df398ad 0x5f5ee1c6 0x499e00ab 0x65024633
- 0x32af0af6 0x61aecdc3 0x19dc2376 0x061c1132
- 0x09eb3e31 0x53edd271 0x280ad517 0x167d6297
- 0x11da637a 0xfee5d512 0x86ba451b 0x9ac4dd03
- 0xae09fe4a 0x011fb154 0x5dde9f8d 0x66b77ebc
- 0x348f5dc4 0x89d838c5 0xd1076c44 0xb7207c6b
- 0x288ef144 0x4ddbbc30 0x8ab3181a 0xb3a9cd9c
- 0xe8da4c2f 0x5f51ea25 0x25698b3c 0xe5d8be42
- 0x9033461a 0x08ab6b56 0xd3ef4e5e 0x22fef14c
- 0x40e6cbd2 0x8023d0d9 0xd3624fa1 0x05058ed6
- 0x7f9e29d4 0x2d679020 0xbd8a9438 0xfc2c7ae1
- 0x43ff62ce 0xa5c960de 0xca118741 0x1d3ff652
- 0x7aad82fa 0x7e05c2b1 0xaa60d6b5 0x1b44c011
- 0x3d8ed489 0x33e5569f 0x954c9df9 0x6a3f3eec
- 0x185e0868 0x0b261932 0x4abcec9d 0xe91a01b5
- 0x2dcb391b 0x2623c791 0x4054eeb7 0x39f859cf
- 0x838a2034 0x89b408d4 0x58976dd9 0x130dc93c
- 0xd7c36f4c 0x65a57934 0x87364549 0x5e9e1b78
- 0x598c3e00 0x1267d53c 0x12655bdc 0x757ba8ec
- 0x20897226 0x121f8469 0x4db11ce8 0x6c4457ce
- 0x408c5799 0x0dafde84 0x34e803f9 0xe6c40be2
- 0x76601d29 0x6f382889 0x60a7602d 0x0e9f8f86
- 0xd02bde01 0x6bbe40f2 0xcfc7e18d 0x18bb288d
- 0x7693588d 0x93b5bf2c 0x257a886d 0xa444942b
- 0xddc30b6d 0x0c733fc6 0x59c7fb0c 0x1e7428e1
- 0x00e95317 0x8bb2b789 0xd1e8d918 0xe79d96be
- 0xcdaecf72 0x1f10292f 0x8550150c 0x3ac030fb
- 0xa740ed6f 0x86ca944b 0x1cb36602 0xb7a210bd
- 0xe3943a61 0x3a6eee17 0x26e3c293 0x48587d54
- 0x2e3c250a 0x9f5139ca 0x4ba8e861 0x310f187d
- 0xf30ef633 0x96708592 0x2c8219ed 0xba807709
- 0xb84d2c21 0x683d5e31 0x7c73d54f 0x20a9f6bb
- 0x8c571bfc 0x18f513b3 0x983064fd 0xfbc61cd8
- 0x34d473d7 0xe0c16341 0x3a51b21a 0x3f7ffd24
- 0x33d20d89 0x92ed2b84 0x711d3f75 0x4437d1d2
- 0x19ffb997 0x03fc59d2 0xd73c4ce0 0x1c048be1
- 0x3e1c70e6 0x2132c8dd 0x96883172 0x9e7ceb89
- 0x03c9bd60 0x6a288f88 0x9b69b2e3 0x21de2320
- 0x7ec42f80 0xfa9c1431 0x421447e9 0x82b422b8
- 0x691d53b6 0xe5adfacd 0x58d1fd02 0x5e66ac2d
- 0x1020615a 0xf1a5aa71 0x9ae9f314 0x61a8780f
- 0xfd35d0c2 0x6d0acb7f 0x8665a3cc 0x638dfdae
- 0xf77cd507 0x9e896caa 0xf023fe26 0x138ad408
- 0xd4a3d2a9 0x20392108 0x4e259b7a 0x294084a2
- 0x353ddca7 0x6b4e0d0b 0x2ecb3b7f 0x2e72b5f6
- 0xbd09b0dd 0x4de2ddab 0x27bbaf57 0x93c0044b
- 0x0c9ff149 0x5e06496d 0xae665015 0x422e1608
- 0xfb06c77c 0x7f49815c 0x74b36569 0x97c6b34d
- 0xb2171d9d 0xd85c83a7 0xd95e5cd4 0x474b6faf
- 0x4276a8cc 0x3eebf9da 0x373c9404 0x0fe5b125
- 0x2140e5d1 0x99fd5df9 0x1b624b9a 0xd277f04d
- 0x57d365a0 0x49fef587 0x1e8c3af0 0x4d827485
- 0x075a70d4 0x75569578 0x9d03ee73 0x2956bfcf
- 0xc45c3dff 0xe15ef324 0x4389e20b 0xb2b6a465
- 0x863fbaf3 0x7503fb46 0x41d8f4c8 0x871f04e5
- 0xb677456b 0xc806932d 0x99d586ce 0x94ad33e6
- 0x996a43b8 0x4c7ff253 0x441e68ea 0x3f2454f6
- 0x7b33925a 0xed5a56d7 0xfa40f2f5 0x3e7a60f0
- 0x45bae53b 0xc3237b7d 0x3d6fe60a 0x7ef17115
- 0x6df8dbb2 0x26d1240a 0x7372d23d 0x5767532e
- 0xa72e2c58 0x2a0d2f14 0x74d029c2 0x1bcf8b01
- 0x513dd7e4 0x800a6440 0xe0f3a8be 0xf951cd2a
- 0x5795eb8e 0x3384450b 0x46e7970e 0xb4434ac3
- 0x468194b1 0xc562555b 0x76d9cb19 0xdf109cad
- 0x57f1ac2f 0x1207af15 0x19d7cfda 0xfb4c069b
- 0x306802c4 0xe8aedc76 0x0170ab97 0xd19b99d6
- 0x7fe69394 0x60b6dd20 0x184caddf 0xd4c81b0d
- 0x008ebffd 0xfd615c94 0x813a5a30 0xb3386934
- 0x5c54130d 0xbe0a6b6f 0x91b127cb 0x7207bbff
- 0x176cac26 0x450be167 0x53563516 0xd6f5ed1b
- 0x90ce178b 0x80e28eba 0x4ddf538c 0xb8037a72
- 0xceaaa6ff 0x3e0eabdc 0x2af375b6 0xfafdf3bf
- 0x24bb3630 0xbcd6da54 0xc59375ce 0x4e9d08c9
- 0x7953057e 0x81ef3d8b 0xcb641721 0x8fb73300
- 0x07f1dd2f 0xda12a374 0xae008fff 0xd106aaac
- 0x5a4f59a3 0xe01bd4ef 0xe1ff2c4e 0xd58c4500
- 0x283e8041 0xb2c7ec64 0x81077f24 0x304fd646
- 0xb5554330 0x098fe673 0x9e5976ba 0x2e24c1c4
- 0x3dfad07f 0x3d64fa0b 0x78a9c65f 0x282c343f
- 0x755810ff 0x363e7150 0x692be96c 0x62cc0559
- 0xb7b9e8c1 0xe35abebf 0xf28d706e 0xea9b31da
- 0xd4762701 0xce0654fd 0xc10a087e 0x0ee813cc
- 0xc66364cf 0x56a8143a 0xb8eafc6c 0x085125a4
- 0x758752b3 0xfd8df76e 0x483c550a 0xc155fb38
- 0x20188374 0x118c9519 0x2e1dad79 0x45b648e2
- 0x32eea6a4 0x73373bbd 0xce78e1b1 0x49b6150b
- 0x826f31d7 0xf5b27772 0x76467cdb 0xab248975
- 0xc98c52c2 0x331e7992 0xb7ca3cb9 0x65fba8de
- 0x8d9df126 0xafb34641 0x83627ecf 0x4f6f5711
- 0x0a18b1bd 0xbf9f7e56 0x5b532a14 0x2c1c7f27
- 0xaaba76a3 0x0019b4c1 0xad0dec08 0x0a090710
- 0x9d092403 0x4b7f63f4 0xdda21492 0x5ac79d8a
- 0x53636303 0x8baacf07 0xd0e54e2a 0x06af65bc
- 0x1776250d 0xe3b7a745 0x3ed99c2e 0xcdfa72f1
- 0x28e2c19c 0x972ed696 0xc40238be 0x2eae4108
- 0x16dbeec2 0xe5aab504 0xb752b0ec 0x908c027a
- 0x5d6706f5 0x5dc64b1f 0xda6012bb 0xd823ba00
- 0x21227a10 0x99c8a5f7 0xe13e863c 0x7271ad65
- 0x37341fc0 0xed4f202f 0xe9394896 0x8c51a222
- 0xc730618d 0x61f38ac7 0x077bbea0 0xf7068ed0
- 0x9fe0eff4 0x09f20a63 0x692cb600 0x965b334c
- 0xe4d16d0a 0xabfd76d4 0xcebb865d 0x52ae79e3
- 0x54be2cc4 0xcada0fcf 0xdc531eda 0x0f6f5a07
- 0x45c26e9b 0x1b65c5da 0x747e35ce 0x28e8f353
- 0x8b14a4dc 0x70fec472 0x386766f5 0x452ec69d
- 0xea3d1060 0x4ad0a84b 0x74947e04 0x241d736e
- 0x67087154 0xa8429f6c 0x93f6fa81 0xc8ae48e8
- 0x8bc37b91 0x3c412b3c 0x5a9b6ea0 0x77b1267c
- 0x4e654c9e 0x3af8be15 0x0c1fcc1a 0xdd53e911
- 0x4133f74d 0x19b478ea 0x935059e6 0x602d1c43
- 0xef2f0dc5 0x606c328e 0x3bcb34f9 0xd3e43917
- 0xa4b13432 0xe32ca0b7 0xe72cf4f7 0x89e64046
- 0xf7665787 0x0e2ceb68 0xad0326bf 0x0df255df
- 0xfbe35bd7 0x452ad738 0x151ded08 0x4977f8b4
- 0xfb0d8ce6 0x55ba4d5e 0xacc482b6 0x685f74cc
- 0x483dcc86 0x09346c6c 0x1bfb0413 0xc8454c50
- 0xed0ab7fb 0xbd60dc85 0x2d4ce7f7 0x7e374d17
- 0x97c4de4b 0x8e241f8e 0x0c63ba83 0xfe2b6605
- 0x0d16e6b6 0xd2b65dc7 0x574904d1 0x57013653
- 0x02bbbb72 0xa1a951e7 0x2e06e4c8 0xaf8a0ce2
- 0xe45132d5 0xc335004b 0x7a80a191 0x70abfb32
- 0x0e6dae78 0x47ae882d 0x2ffb0f2c 0xfbfb1549
- 0x3f5d2a7b 0x9df9be34 0xb69b7919 0x051a54d4
- 0x3e7822d9 0x83f3988b 0xf4f6a380 0x382ec90d
- 0x19ec37e6 0x41da0b90 0x63edbfe6 0xb53fca2b
- 0x4117bab8 0xe711495d 0x93b066cf 0xfa436ab7
- 0xafeb2443 0x842a6a7e 0x92dbfd01 0x5536c8ab
- 0x87706182 0x95b19ae4 0x20a5243b 0xd17d6e3a
- 0xacc705bc 0x02124f77 0xcdd25a60 0x27f2cfd0
- 0xab63270b 0x5d0d50c7 0x626b463b 0x8d1c6c67
- 0xcd8faed9 0xdec15e02 0xeead3ca7 0x35e6b1b6
- 0xa3404975 0xa40c4d99 0xba2aafa7 0x9fd543c8
- 0x737fca65 0xf825b862 0xed028145 0xa19ab5c0
- 0x7a5cf4c9 0x29275a49 0x4e70bfae 0xa68d7af7
- 0x4027d4ad 0xc0f1f772 0xb1857bf2 0xeff36b41
- 0x1cefd1be 0x609569f1 0x5e4a45ba 0x3982f52e
- 0x2662da23 0x9995e160 0xa5236c1a 0xfc3dbe22
- 0xe2cf629e 0x1927e9bb 0x890c2c5d 0x9b1a74a5
- 0xd98da36d 0xd6394f24 0xea08f3ef 0xd7543732
- 0x2c08cff2 0xb338420e 0x954ebee4 0x8f62faf8
- 0x30001084 0x6209f495 0x4bf3151d 0x549fe524
- 0xf0a233cc 0x3d9520f6 0xc3bb7564 0x724bf6b8
- 0xf0364758 0x8c780cc2 0x85041d68 0x004c18d6
- 0x7e1b0aed 0xe515764b 0x3f646ea8 0xfa14a4d7
- 0x1d197044 0xf3eddc81 0x8aa91a1e 0x16256c4f
- 0x8199c0df 0xbf9a50ac 0x568a0f09 0x2cb00264
- 0xd72fd139 0x2705356f 0xcbca00f3 0xd1d48350
- 0xd9ea820e 0x8cef5c8f 0x208f4413 0xa8cc4af4
- 0xd3925d45 0xcacb25be 0xf5c478f0 0x2d98856a
- 0x9b2ca15c 0xa866f9c0 0xd11e9a8c 0xecf63535
- 0x26afb8e5 0x07582187 0x68e92d2c 0x701732d1
- 0xcfa17e9d 0xcb923dcc 0xc6fd0935 0x2949f3f7
- 0x2f819c1e 0xea483296 0xb234a335 0xe3e174f1
- 0x2e79e24c 0xcebb3426 0xc7b11c2e 0x09c50c12
- 0x1a776bec 0x9eb75be2 0x906fc75b 0xa951a0bc
- 0x067984cb 0xeef41487 0x592d71bb 0x6d830d75
- 0x9315da53 0xfc4a745d 0xf55687dc 0x41d554e7
- 0xd9f4873c 0x51680147 0x70a32832 0x514a6b9b
- 0xdb221d0c 0x5d8a04f2 0x56d0d2e7 0xea241411
- 0x2fddf98e 0x4f114da4 0x5b08dece 0x4a1deb72
- 0x8a05c6d7 0x5412556f 0xb34099d8 0x769a94dd
- 0xa5e5f79d 0x2aeed8ec 0xb2c36124 0x4049a237
- 0x14984601 0x1a595742 0x64490292 0x630c8cd2
- 0x55e6bb46 0x6a0d06ab 0x2b0b11b4 0x7c616e40
- 0x88ad3ace 0xd51e4e32 0x09b91afd 0xe7e15aeb
- 0x0050ef89 0x4330509d 0x12cb2d58 0x8aa65df5
- 0x6a3a7bfe 0x13110a63 0x6e0321e3 0xe00dafca
- 0x71e02a28 0xbb179946 0xa46ec287 0xec8a407f
- 0x71e4ecb1 0x9aa3eaf1 0xccc68628 0xc593d002
- 0xadc7003a 0x4266b50b 0x3c1883ee 0x6dccb885
- 0x417c946d 0xbed06b8c 0x333c5aae 0xb05e54ee
- 0x16d7a8d5 0x2c4711e4 0x77f99748 0xea4f1ce3
- 0x99077ba5 0x3efe0258 0xd6df1959 0xa68402c4
- 0x17fb46f9 0x84dd7f43 0x2743ad55 0x4c3618ab
- 0x066e70fb 0xa7ae2740 0xabfa9383 0x3550f323
- 0x12df0416 0xf1453568 0xa72e19a3 0x858f6f03
- 0xf17cc616 0x4ae587bd 0x18a72aff 0x3a7e96e0
- 0x742fcbfa 0xf2978c0c 0x1c9b4647 0xead5df7c
- 0xa4006862 0x4ff1f7ad 0xad9ef88a 0xf2e10660
- 0x408e1435 0x54fce4ac 0x3b362a56 0x31215f74
- 0xaa3c9bda 0x9e20dbdf 0x0d5fce6a 0x282c976f
- 0x0edc8226 0x373f111f 0x3e98c061 0xf268555d
- 0x2bc94957 0xaea989d8 0x509c71ba 0x12314a4c
- 0xf763fd18 0x756c083a 0x210052bf 0xc8a587ec
- 0xad316f0b 0x8bdc25ef 0x97d826c2 0x2b2274e0
- 0xb2d83dc0 0x758a648c 0x98f048ed 0xc049ee18
- 0x86a7ae90 0xb2cd2e74 0xbf05a5fa 0x99569e00
- 0x91ef2ef3 0x0fa73191 0x8fbe0377 0xd833195b
- 0xa8f92c91 0xd5180d87 0x78e66404 0xa6932c29
- 0x63767065 0x212597be 0x71443fa5 0xc7f0f7e7
- 0xee005d0f 0x3f554ee1 0x0ce921c3 0x11f7aa65
- 0xab833603 0x226583ac 0xdc02270f 0x582acced
- 0xe4873a4e 0x4789f1b5 0xe4556ae0 0x2db116e3
- 0x4dcf008e 0x94848eef 0x33dd4850 0x763ee311
- 0x8d129dec 0x37584ab5 0x2a72a7f1 0xc3812cba
- 0x8b28d2f2 0x0adb3ef1 0x77c139ed 0xa024d006
- 0x77b56ff4 0x237a0ef1 0x70c06866 0x3f678b49
- 0x758b3ce4 0xac6fba3c 0x425f5226 0x736cb61c
- 0x6d33908e 0x2db271b8 0x57a0b9e2 0xafa0c8eb
- 0xe16670ac 0x01358d54 0x291458e7 0x20dbb518
- 0x750ebeed 0x3b7ce363 0xab142fda 0x2f827c5c
- 0xe4b63c2f 0x25b21550 0xd9a7d8a4 0x9a0d0235
- 0x6ccbe996 0xbd16a832 0x408c6b6e 0x264e7057
- 0xf76251cc 0x10b292aa 0x44e35c08 0xe10072a1
- 0x8496f9f9 0xf3f14db0 0x903e0d04 0x437cbdab
- 0x94bba5f6 0xd93cb547 0x6c8c5b9c 0xdaef1d7c
- 0xc9245303 0xb8327055 0x17b4f91f 0x9609ed57
- 0x276a2fef 0xd6547d96 0xd845e2a3 0xdb17e11c
- 0xe06b1865 0x91ac2801 0x7499b2bf 0xfcc13e08
- 0x4d2c3ad7 0x33f551e1 0x7d9409c7 0xafc9eb56
- 0xd1b99328 0xfb86b03f 0x386621b1 0xc937917d
- 0xd049796a 0xb61b9848 0x6e6c850d 0x9acceebb
- 0x2335fff6 0xba4cc878 0x71410231 0xe2f8c5ab
- 0x9af0d19d 0x28ec5cf5 0x756ac8b7 0xbef10a49
- 0x0845244c 0x1d73e741 0x9062b8e2 0xda4ff7ed
- 0x02b84967 0x1dfa2bce 0xa39fde98 0xb9754114
- 0xf1d1128c 0xfe4a89f5 0x7f752ab4 0xc079051f
- 0x9d280392 0x8e4405b6 0x9a78116b 0x93ccc928
- 0x9423c484 0xd9d02b55 0x8b293206 0x4e1ba855
- 0x8b163dac 0x86097281 0x5fed4e15 0xa3a9986f
- 0x6aceb1fd 0x9840a4a6 0xb9159ba5 0x43a6a036
- 0x48c6b148 0x741b03e3 0x2034fa35 0xa2238e26
- 0xcbd2d186 0x543a2254 0x52bee0c4 0x3d86f09b
- 0x91b2c0f1 0xbcc3b745 0x2f74849a 0x0330c741
- 0xbe83b31b 0x2be0b1e3 0xb5289590 0xd70e1559
- 0x575ed5ef 0x26095dad 0x243db065 0x7deef6bb
- 0x65d12981 0xed493443 0x8bbb1d52 0xad9cceeb
- 0x9d2347e0 0x6cca137f 0x17470bbb 0x7e3c2e70
- 0xf8f031e4 0x089ffd36 0x54188a4b 0x0da3ca59
- 0x89502f42 0x118865a6 0x188d2f03 0xbab32122
- 0x8b7dce7e 0xd560dcf2 0x3b664c1f 0xc75878ec
- 0x24483e82 0x5f98c3ad 0x30f8edb6 0x750517a4
- 0x26b74663 0x4a92cf2c 0x34142eea 0x74434b26
- 0xef952153 0x499bb195 0x0eef898b 0xc87096df
- 0xebb06a79 0x6f85e09d 0x61582c0d 0xf067fa23
- 0xe800ddac 0x5d94560b 0x7b3c3438 0xf8656d92
- 0xbb2e740f 0x3919d1e9 0x4ae59719 0x9884c38e
- 0xab33c8f3 0x2b6fe11e 0xbb918fe1 0x78b89ddf
- 0x28ff265a 0x8d1be42f 0xc7ae521f 0x59021a63
- 0xc8feb2b0 0xf4adb84d 0x1627d0ad 0xdf2f54b9
- 0x6c34378c 0x19905a68 0x751ab74a 0x4ac834b3
- 0x0482a8a0 0x3fa5727e 0xc67e56e6 0xe9a7fa62
- 0x138c624b 0x8cfa9421 0x777be58a 0xa77e4a9c
- 0x317880c6 0x784adbec 0xf24af624 0xca7b14cf
- 0x0733ca3a 0x4df8fa2b 0xe737de97 0x8221ad28
- 0x12318567 0x1143d1b5 0x6d785e96 0x96b4706f
- 0x62b54a94 0x2cc3c8f4 0xf4509cba 0x013b1838
- 0xeb30c28f 0xafdce478 0xb079b9e2 0xf7fde255
- 0x369de668 0x51eaacb3 0x1a4857b1 0xdc155799
- 0x14312bb5 0x88e95615 0x3baea03c 0xda51f1b7
- 0x2ba9c897 0x02acb260 0x45d16629 0x69f4125c
- 0xb814d67f 0xd9371fdb 0x2abe9516 0xcb4347a5
- 0x8499fa6d 0x548d5caf 0xeaaea9a8 0xd2050d3e
- 0xe7ffd097 0x1343ddc5 0x2c063604 0xd4860459
- 0xe97d7e58 0x2b039549 0x7f9abb32 0xce9ae49e
- 0x6a9f2bc8 0xf42c6e74 0xa2cc44a3 0xa586ee59
- 0x9468aff1 0x9baa9f44 0xc672fa47 0x81af898d
- 0xbe2e0747 0x2568ec6c 0x5a297908 0xa3a45a84
- 0x86e7b0c8 0x25d653d0 0x2e1dd924 0xb8b8401d
- 0xb6132a11 0x63380a89 0x70457a9c 0x5599343c
- 0xdfe56efc 0x7347c609 0xd2a0254b 0xddb9eff8
- 0x2ff89812 0xc3fb0b4c 0xaabcb56d 0x8ea167d7
- 0x3058af81 0x90c13947 0xd2d066bc 0x9187a7c2
- 0xea3f4bc7 0xde558f0c 0x553387c2 0xfe52ae90
- 0x55e9dfc9 0x280c76a9 0x22029fbb 0x695decb6
- 0x37e156cb 0x636cd8d0 0x314735a1 0x6b97c31e
- 0x5990da35 0xa36210e3 0x731aa846 0x3e9f4591
- 0x1c311983 0x1b05ca14 0xd26366ce 0x35108fc6
- 0x6ec7c06a 0xe5479ece 0xabda431a 0xe876a3b9
- 0x7306ec54 0x8ac2dbd7 0xb6025692 0x60e08291
- 0xbd2d5771 0xae63c08b 0xb57f59d0 0xa0b7a4d2
- 0xa1975545 0xd4246fff 0xb541c3e7 0x80579f75
- 0x350f9ba5 0xc167fd9c 0xa4753b37 0x614432a2
- 0x8c2a5225 0xcacb408d 0xc692b149 0x44eb19e3
- 0x9e36674a 0x4221e3a5 0xc8847980 0x22188be7
- 0x9f3b54db 0xca30b3a9 0x4f23026c 0x1ac563dd
- 0x0cef9dbe 0xde1759e4 0x88a1ac44 0xdb249ed0
- 0xcccf2728 0xc54995cd 0x1410f555 0xe68a533c
- 0xbf63c4b7 0x53890c13 0x501696a3 0x09695674
- 0x49675e62 0xd5859fac 0x62dfaa74 0xc2837e8f
- 0x5693d6bd 0x6c4b7df7 0x19673414 0x436523f6
- 0xd7476fa4 0x1c123daa 0xf160418d 0xb022c7e0
- 0xa0798def 0x908aaeed 0xab420cd0 0xb42b83a2
- 0x779b9257 0x8bd0dafd 0x17088cc8 0xe5707f57
- 0x7e95cb37 0x2f0975fe 0xf6c69671 0x9adb2ac8
- 0x9744adf6 0x534f59b4 0x70126a4c 0x094dc52f
- 0xeb1bca01 0x8439872b 0xa9eb2393 0x93466ee6
- 0xfaefa751 0x407578bc 0xf96695f3 0xece8916c
- 0x90555ebe 0xd4bbb5e8 0x521e0328 0x733e7a44
- 0x6b38d125 0xaf78c4f6 0x02a68e77 0xf0b3de08
- 0x6b7055a7 0xe173c89d 0xf8d502e8 0x0af8722a
- 0x0cb5d7c7 0x67fd3443 0xc3ece1f6 0xd1e3476a
- 0x6c51b69e 0x1e4d6701 0xd30b9ed8 0xcae0b2cf
- 0x107a07cf 0x9e995fe8 0x96be9a9e 0x9679a48c
- 0x56e943fd 0x5840eba2 0x903172e8 0x030e7848
- 0x01aa0b3c 0x3430ee93 0xd9074e67 0xba76da7c
- 0xac651f8a 0x4776630f 0x335cc3e6 0xf196a501
- 0x3946d5ab 0x9521219b 0xd5c1b923 0xea8a860d
- 0xb68cd8e3 0x422fe195 0xee228116 0x7935c07c
- 0xf9a777a8 0x5ebb5f11 0xca9af85c 0x2ced106a
- 0x839746e2 0xb278a109 0xd80ac684 0xad50dc92
- 0xcb1306fc 0x03b5953b 0xa1739037 0xb3d2eca5
- 0xa2177c85 0x331d941e 0x07d760f1 0xaf91e655
- 0x37859c68 0xa93f3fe7 0xfd8c0c27 0xfbaa7226
- 0xf9ebb691 0x378f97ba 0xbff7118a 0xe2dcdddd
- 0xbbcb31c6 0x690c39d0 0xa87db784 0x71e8f7e3
- 0x6030ca21 0x4a0e52fd 0xfbfb507d 0x162bf88c
- 0xaa2641c4 0x8df9c9b8 0x23266298 0xc3c49ddd
- 0xd285aff8 0x3b867dd6 0x0be83ba1 0x0f4a797c
- 0x1c934d37 0x0e0fcb24 0xa0a4d4bb 0xa4c9e180
- 0x1f151322 0x44b9bce0 0x047feb93 0x3e05cf8a
- 0xa9b3e489 0x43f0da55 0x6fcddbe2 0xa402623a
- 0x5c8ad2f4 0xf7ea52fb 0x3da14b50 0xbf8849bd
- 0xb45ca440 0x2893d691 0xf6d8ee21 0x9dc0cf25
- 0xfa6be75a 0xeb27219e 0x9b160b84 0x1867d384
- 0x5b536f15 0xdac9e97e 0x1d290193 0x683d4a93
- 0x4c449e2d 0x493edc1b 0x8ae3a3aa 0x3a49ca51
- 0xd6751c65 0x174ef916 0x94118e1d 0x0bc6adeb
- 0x49c4b0cd 0x04668564 0xc9e39f39 0x19907555
- 0x0320cb0e 0x32a643db 0x4ba9edc5 0xce11afee
- 0xce71c45c 0xebe0c707 0x48d1d23f 0xb2704cfb
- 0x94b97cba 0xaa934cb4 0x7e375bf3 0x7c9f87b7
- 0xb34ebd26 0xb1ed5855 0xdd458d3f 0xcf071bd0
- 0x3204188c 0x744959b0 0x20eb0748 0x1b863237
- 0xc36fad4a 0xde026857 0x74c278b2 0x7be0749e
- 0xd61895dc 0x509355a2 0xab890c09 0x210ef412
- 0xae4678f3 0x3605af3b 0xc111b378 0x81f0173e
- 0x4ac61ae9 0x2efebbd3 0xec8a55b0 0x5c60addb
- 0x19ab7fa7 0xbf5bb0ab 0x7b55db2b 0xa246b5b0
- 0x70739cad 0x20bcca0c 0x152a98a3 0xb1ada872
- 0xf3a401eb 0xb169b481 0x1024e632 0xb285ec8a
- 0x42f7bc38 0xe6ce9265 0x05ce19a1 0xf89e52ec
- 0x2dd6f337 0x81b30e86 0x459ac80d 0xfa83fd49
- 0xc0ba36eb 0xaeaf8c90 0xab621eec 0xe94ee998
- 0x0f693a97 0x5d9a589e 0x439e79a6 0x565ea22d
- 0x60d8e090 0xa021284f 0x4dd58eab 0x35cbe80c
- 0x386c67b8 0xb260ff41 0x9b2685c2 0x37c33d86
- 0x2b922b27 0x1aeb19d2 0x9d503c43 0x0fff6ce2
- 0xf400393b 0x70be801b 0x8cfb132e 0xbb1781c6
- 0xbeaf80e2 0x2a5a64c7 0xc02c7ebb 0x8f870c7b
- 0x6bfecce5 0x8d885183 0x4f2c1b6a 0x0a3e6c0a
- 0xb7d17ad8 0x7d593bb0 0xb1e00ea2 0x8d553de0
- 0x07ecf8c5 0xde0c3afd 0x40f193a0 0x77030199
- 0x458046a0 0x21b67cd9 0x836ef83b 0x53563580
- 0x4edacbc3 0x1263d410 0x2b217042 0x4e3ad860
- 0xd51576cc 0x714ba8f7 0xe02e102c 0xb38770fc
- 0x34270f26 0xe7aa59c0 0x17a3461c 0xe6667980
- 0x9d5ed074 0x4168f2da 0xdefefcf8 0xc6b3031c
- 0x27c4d4f0 0x5e51e5be 0xf90cb81c 0x26ff3f7c
- 0xabc25d19 0xd65e5687 0xa5ee2995 0xc4e545b1
- 0x0184fab9 0xa44f4395 0x2aaef6da 0x33a682a0
- 0x5f878a4d 0x0b808a4e 0xb95490e1 0x4e4b3902
- 0xa1815407 0x3769d4f8 0x81943938 0x0d8b44d2
- 0x89c90314 0xb779e2b3 0x1acfa29a 0x3ee54de2
- 0x203c8450 0xfdbf24da 0x8b9bc91b 0x41a25706
- 0xab9b74a3 0x6feaa6a3 0xed50c416 0x5dca2489
- 0xf9d58d01 0x57682903 0xd951335c 0x55a323f2
- 0xe6c10c4b 0x0983a265 0x50df7efa 0xc550b079
- 0x1e670ce5 0xca74138e 0xa7e01118 0x4d1cd2e3
- 0xcd3b73d7 0xc5c0d501 0xdd56b269 0xbc6bf217
- 0xa3094ee9 0x794e6e21 0xc097fddf 0x191a1b70
- 0xe6a45c45 0x47a1899e 0x29fe5a55 0xaf88ab14
- 0x0a05bec0 0x05c97061 0x0b7654a3 0xfcb357b7
- 0x31657eec 0xb5aeed41 0xc70ea45e 0x096075af
- 0xf5236b88 0x6329310c 0xe1bdaf51 0x569053d0
- 0x7679fcd0 0x04c70d46 0xcce2d566 0x0316e8c7
- 0x391cdf9c 0x47045b03 0xac63bff0 0x1a7bdde9
- 0xa5a725bf 0x6dc151e9 0xf02a3df4 0xfb01c649
- 0xa6690e2f 0xd561a5df 0xbe0efc39 0xd35f7dd6
- 0xddbe2e12 0x8f403837 0x1c92e116 0x1b47ecde
- 0xabd75d5d 0x3b39c5a3 0xbc8a81e2 0x5beaaeef
- 0x1206f28d 0x7aa1852e 0x96eb9ef2 0x30911a7b
- 0xc1ed82f9 0x0940dcef 0x07c62124 0x1ec437a5
- 0x688e0a9e 0xc26852a2 0x01bb985a 0x55429a26
- 0xc90b329d 0xf618584f 0x1ed4fb9d 0xfe605231
- 0xc20810d3 0x7cf66bbc 0xadf11084 0x80697ce9
- 0x473457b6 0xd162e619 0x4e452b78 0xd39ddbdd
- 0x8591db3a 0xb225b8e7 0x208855e9 0xefa860f0
- 0xdd96e987 0x074a8ff1 0x1cf505b1 0x78d7b7d5
- 0x8cd1cc29 0xae25f5c3 0x4fdb0160 0xc4cef03e
- 0x9a9c5704 0x47032d85 0x3486b65f 0xd3ecb515
- 0x58bd87e4 0xa408f421 0xca577e46 0xa5e921df
- 0x5a295aa1 0xe53f571f 0xc03f9dd4 0xf1d6a0c4
- 0x711016e1 0x300d5999 0xc321eef2 0x96669e94
- 0x2925f8c6 0xf7096453 0x65d21402 0x6f7462ab
- 0x826ee986 0xfd04606c 0x5554d246 0xb3d98bcf
- 0x237e9d62 0x82224172 0x35ea607d 0x8142bbeb
- 0xcb0edddd 0xc0a9233b 0x64be095a 0xf8b39e85
- 0xde2d0b29 0x69e2d7a1 0x6737f156 0xf85e0d4f
- 0xc194effb 0xed018c03 0x873a1908 0xa4fa5da8
- 0xf6eb812f 0x04e4819c 0xd189a19b 0x94694499
- 0xd0545215 0x371f62e8 0x2208dede 0xcb49f3ad
- 0x192654ac 0xf36c1f49 0xeb3af0c4 0x54bfd20a
- 0xb86f85aa 0x3d94435d 0x31a9a1ed 0xd02b0620
- 0x0b44bc44 0xb4861a1f 0xb4605284 0x1c83e472
- 0x055d7e70 0x717bb954 0x44d8e8bd 0xbd9af75d
- 0x068d8de3 0xe25b73ad 0x8df23c60 0x4050ca9b
- 0x86c000d7 0x67a9e98d 0x437bb833 0xe26ca015
- 0xcc53371b 0xa0ce2a4c 0x83bfc220 0xc392520e
- 0x38d7f316 0x4801955c 0xcebd086e 0x6a3b8eeb
- 0x83d63b2a 0xcf516140 0x3f0d648a 0x58b62c57
- 0x7ef3bffa 0xa6976628 0x8f3a5c55 0x42a3baa3
- 0xedeb9c23 0xb477c88c 0x63d7c7bc 0x2bdd0e26
- 0xfe7b9821 0x31fe5981 0xdb5425a8 0xc716b3c4
- 0x0a6f1597 0x34a8a007 0x36b0614f 0x8362c856
- 0x5e0f52b9 0x9398b4d7 0xc5c5590f 0x4af55ddb
- 0x1ec59258 0xaf0222f6 0xcc2c7b6c 0xf0413081
- 0x1ac15bcd 0xf0bf09a8 0xbdd23bc0 0xd75ed77f
- 0x551c6a1e 0x5380ca48 0xf5f30a44 0x88ecff13
- 0xa5f8130c 0x7cb60dc0 0x9eb26ba1 0x3f883068
- 0xd954b9a3 0x95c87a30 0xefcc0c68 0xf7337080
- 0x1eb12337 0x125c5a7f 0x25a0fee6 0x439a4a47
- 0x02ac17fa 0x5d581e53 0xafb9d7be 0x914f9ebe
- 0x82f5c4e8 0x7d29838a 0xe8d6c3ac 0x1192f816
- 0xdbfa1251 0x239defaf 0x8d4a48d0 0xa48bf5a7
- 0xae7149d2 0x9c349068 0xe7e1f6c3 0x8c28773a
- 0xd441626e 0x81fbd796 0x3597d8c0 0xb8f39eef
- 0xbafa40c7 0xe4e53aa9 0xb678c826 0x1ac82ff4
- 0x9e7fa0bb 0xe8bb2559 0x064e4e96 0xb0e6f10f
- 0x9ae0ee3d 0x7d9b0b42 0xadd1c5df 0xf095f8a0
- 0x30f172ae 0x61caddf6 0x4ce89732 0x06099b54
- 0x011266e7 0xbec76cea 0xf7f8d2f2 0xdfbb7f1b
- 0xbb003bf7 0x425d3677 0xfdef38c8 0xadbe4b40
- 0x634753c2 0xe53ae88c 0x1714dc8c 0xb788dd35
- 0xcbaffa0e 0xffbda6ca 0xe1f91cc6 0xf92d121a
- 0x9a260275 0x45b2c1ca 0x707a08b6 0x2a8db106
- 0xa7df6894 0xe7189751 0x206259b0 0xde37dfea
- 0xe468cebe 0x2476d774 0x1687f09f 0x2c06af20
- 0x60fa742d 0x81aca355 0xef888aa1 0xc1847c88
- 0x32036160 0x29a779b5 0x47d9e830 0xb9f83d5f
- 0x3fa4e61b 0x038f4901 0xda804b60 0x231c9fff
- 0x8070517b 0x2a4e6c70 0x9485f89a 0x7b57f832
- 0x0d92d4cd 0x04aa0eba 0xdcf5c49a 0x3b3a772e
- 0xe9df2e03 0xde378b39 0x3bdfbf09 0xa60790df
- 0xdd8826c0 0x3de3b41d 0x68c3f5bc 0xd6f093d4
- 0x41bd42c0 0xc68291ba 0x12f94625 0xae5ca753
- 0x0abd919d 0xf48b4d3c 0x57c0c82a 0x5ba454cb
- 0xce5a94ff 0xae3cab47 0x4aa33823 0x1afaffe8
- 0x7d4136c6 0x2be28394 0xfb7602ee 0x39eb1300
- 0xd12bae68 0xe4b7a0c0 0x94f94c06 0x048abf82
- 0x4eb3e435 0x6fd07abf 0xd471636c 0x5c6c299f
- 0x702a9e43 0xf239358f 0x82dc3598 0xc76a572b
- 0x48b47811 0x1de592d8 0x258a64a6 0x9b61d81c
- 0xf44f9c0f 0x737b3537 0xc6e0eef8 0x169efe91
- 0x834cc9a3 0x67d42617 0xa3df949c 0x2e4601f3
- 0x21630729 0x7bb68a4c 0x7e489647 0xfa9179b3
- 0xf2588707 0x4fddeedb 0x7a1f612d 0xb55787d0
- 0xafee1501 0xb3e7b9c6 0xba804c9e 0xd4ae95e0
- 0xac524f6d 0x58cf914f 0xe057bd9d 0xf3ac907f
- 0xb03a6d32 0x2260788c 0x4caaa555 0x984ca3f0
- 0x2129f747 0xc8d68e34 0xa87c8179 0xa480412b
- 0x63e15d82 0x41cbe3df 0xdf1a76d2 0xc60c1cde
- 0x7648f22c 0xacd4fc11 0x06b9d04f 0x991c16ed
- 0xcb417c7f 0x479c604b 0x5582e2c5 0x40f9c0e7
- 0xc2d613be 0x136c76be 0x91e780bb 0x2063d01b
- 0xc4e5d68c 0x6862f436 0xa56544a2 0x5d022a83
- 0xf72335d0 0x85e89050 0x89306316 0x1f0514bb
- 0xa5080fbb 0x2a7369e4 0xeac3af3d 0xca7607a5
- 0x5c743d9a 0x7ffe728c 0x9e8fb02f 0xa0c5eab4
- 0x0fab7728 0x4cb95891 0x2e79d596 0x018ccc65
- 0x0b58f60f 0x2ca2b629 0x046ea589 0x3b30acb7
- 0x8ba03fbc 0xf22519b6 0x8cb72f21 0x202dee89
- 0xf9d00d21 0x2ec96d07 0x4b83c51b 0xa9fe32cc
- 0x1d8f9267 0x1a432a84 0x6d823868 0xc7911f1d
- 0xcb21bb51 0x3c2456f1 0x1a03390d 0x25052957
- 0x20616d36 0x4fb85138 0xcdd69e20 0x42b7854b
- 0x158e4668 0x6303770e 0x96e26c4d 0x71b527a5
- 0x11319d1d 0x6d75f287 0x1dba9eaf 0xccd4fce8
- 0xf5d9cfa1 0xe9fd8f1d 0xb6f43134 0x2d4cbbab
- 0x1304d4a3 0x7a05977a 0xe773bf6f 0x30baa540
- 0x61f204da 0xc5a5aaba 0xb9957e48 0x3262daf3
- 0x78511464 0x2ab04e32 0xc89d96b6 0x14246913
- 0x4b836fc9 0xf50f4f05 0xff2d221c 0xc14a1bbf
- 0xe05e4591 0xf4c57aa1 0x935d6b79 0x0878ec6d
- 0xdf4537d9 0x8a82fb47 0x6510da09 0x37a2a471
- 0x216f3f32 0x40bac353 0xbd273df0 0x92a53e79
- 0x54e1c315 0x494f9ef0 0xf206a246 0xb536ed59
- 0xbd90d8ac 0xe7cd65db 0x1528ae70 0xa999b3ea
- 0xfc3616b9 0xf26b0fb8 0x0d26f2e9 0xbf44ebf3
- 0x690d86fd 0xbfa22568 0x760c8270 0xb51e0a14
- 0x3f9d311e 0xac848312 0xfc101499 0x553fe2a4
- 0x6a6b0f3e 0x6f970879 0x2be81e35 0x6144ac40
- 0x501451ea 0x268aa441 0xc6cf124f 0x6bf90440
- 0x08fa587c 0xc04bf04e 0x25bfb03a 0x3741f6db
- 0x26242832 0x5bf071f0 0x8d6463b9 0x500e503c
- 0x1a9468ce 0x5d23d18f 0xf2f8163c 0x0d7e519f
- 0x98f0edd1 0xdd12a97d 0xba39e22d 0xc91cace2
- 0xb2204698 0x87eaa42d 0x7968cfdc 0xe32a8876
- 0x6799323a 0x5df22ef3 0xa674dfd7 0xb46117cb
- 0x8294a996 0xac7d3b17 0x30c06dd6 0x3b827594
- 0x1cd8770a 0x026d3220 0xb9efe807 0xb3d73bad
- 0x68c78f8f 0x8f8a13ea 0x1ffb9590 0xe99cef6f
- 0x03cd123d 0xfb1bb840 0xaff37d51 0x199b5161
- 0x842c3d56 0xf31e3aa0 0x218ed36e 0x16bbd3f8
- 0x733a6088 0xed5c4240 0x29ac4df9 0x65765620
- 0x1645afd8 0xb9af1aa2 0xdad3a6b0 0xa1007b56
- 0xe709a529 0x51a7d880 0xe58a2cd7 0x79c1915a
- 0xf63df885 0x83e87bf9 0x33e3818e 0x3e3c0136
- 0x59b684da 0xc03628d4 0xfc3e229f 0x67fdb30e
- 0xe965e7c5 0xcd262320 0x171c70a9 0x85d68571
- 0x1da4d76a 0x59e854d3 0x138428bd 0x0804e776
- 0x948e121e 0x410cd3d9 0xdc4834a3 0xecaa7f10
- 0x6d2993a3 0xfe17843d 0x518ec623 0x70c3f7f1
- 0x418d09b8 0x04272bf6 0xbb6f5ac6 0x86993bb5
- 0xae28afb6 0x1afa1ba2 0xf1231937 0x599c8856
- 0x47eb85af 0x6cdf0c60 0xc08098ee 0xa26eaa47
- 0xabcead3c 0x72e567a9 0x54196049 0x502ed324
- 0x2c8773c1 0xb109a085 0xe8a25547 0xe13f68a0
- 0x08ceb631 0x024c1b3f 0xb1701b83 0xe3602a0a
- 0x2d9d092b 0x55f9960b 0x1eaeb777 0xcb422b9d
- 0x15484e5b 0x3b040ae5 0x6851c37d 0xbe99e012
- 0xdf731c32 0xf2a4ddc2 0x4f18a7b1 0xf244d571
- 0x20a13803 0xcff77b0e 0x6a32c0ba 0x6db996c1
- 0x83b3dba1 0x0287b69e 0xc8132123 0x1cf51166
- 0xeae54e68 0x64c974a8 0x4d6add7b 0x58a87bc3
- 0xa70799a9 0xd6575ef6 0x9c67be5f 0xe565e7f2
- 0x6c602d11 0x47a2332b 0x58e3a7c0 0x4bb04592
- 0xb899331e 0x28691b63 0x35a5b304 0x590e8684
- 0x398bce23 0xa6e5d1a7 0xbe941045 0x8248a1c7
- 0xe2f0f0b3 0x8fedacf9 0xe9412fa0 0xfcdd0389
- 0x0aadca9a 0x592efaa5 0x5b32f7ca 0x59331bb2
- 0x8c3edeb1 0x327d14ad 0xaf6ee0de 0xba015362
- 0x331e2a77 0xd0759b70 0xd80e1d52 0x8f24b791
- 0xa77b5abf 0x0dc0bb13 0x22d28613 0xf579ac0e
- 0xfb8f0252 0x7073e4df 0x28a4aa05 0x7e665e37
- 0x8459682e 0x17ce0744 0x55c15497 0xf0d506ed
- 0xe4402e0f 0xeb964b36 0xadf8cdfa 0x51e408b2
- 0xac8f1f75 0x21da7eab 0xd8be84a6 0xb889de7f
- 0xa3b7ccba 0x2e92096f 0x51dea741 0x4bc8b6b7
- 0x509d1e16 0xa51680d2 0x94570667 0xac5f5203
- 0x916845a5 0x1e2b4162 0x39f55bf1 0x903c4c15
- 0x0953148e 0xe0ebd00e 0xcb659fdf 0xd3574623
- 0x4d97e3cf 0x49f4b61e 0x44007063 0x20a32437
- 0x7c5dde33 0x8c7145df 0x9db86b04 0x19b6dc0c
- 0x18ae6d06 0xa7e11c47 0xbf60d44b 0xf8670b5b
- 0xe9e8e361 0x6bea92d7 0xddb5fbf3 0xfe493a6a
- 0xe0010eca 0x472558e9 0xd3438288 0x67dff800
- 0xdcf99ebc 0x8550e460 0xd4f74bf2 0x9cd801bf
- 0x69a5fcc4 0x70ca0a39 0x8ca2156b 0x7c3d451f
- 0x688ccdc8 0xcf6fe525 0xc39776e6 0x2d71269f
- 0x9bac002d 0xdb4bd577 0xaaff71ad 0x99a880ee
- 0xc4e77913 0x4f58dea4 0xb0d35b3c 0xb7dd5cd6
- 0x368f88e0 0x1a153497 0xa61a686a 0xb4b29fc0
- 0xa2605188 0xf1bc0648 0xb2ad7cbd 0xac582f14
- 0xdfb3bac0 0x079fd5f3 0xfb336ee5 0xdbd17aac
- 0x5c5da53d 0x89d5d69e 0x07451fc0 0x53f3ee4c
- 0xfd1e08cc 0xcf46a702 0xe9b4e436 0x25e13d98
- 0x809a73ab 0x07b25e94 0xd5845739 0x7eb131f1
- 0xd3e5d83c 0x5fa46a68 0x178d2b05 0x94ee2f16
- 0x75c6be0b 0x01716271 0x359790a8 0x754a16c4
- 0xa26be7f5 0xd998b02e 0x25497107 0xb842f73a
- 0x34f680a0 0xae8c305d 0x5b9b239c 0x0f2b009d
- 0xfe440280 0x145d1126 0x6d102c8b 0x402b89b6
- 0x9a580c40 0x91aa00a9 0xa03d8974 0x4d2a26a1
- 0xb75b8202 0x16600764 0x211ebb2e 0x28bd93d9
- 0x6518d2cf 0x6d5bd308 0x382c5ed7 0xa29e0aa3
- 0xf89cf93a 0x74a0b016 0x3ca612f5 0x24064cf1
- 0x47747a5d 0xd22975dc 0x3c696e1b 0x0e4d0a5a
- 0x3718d1a4 0x1fcc5ea4 0xab35093b 0xb50603ea
- 0x3650c65f 0x32858ec5 0xa87dd504 0x687c5833
- 0x2a36de42 0x9cb6868a 0xe78d1072 0x675eb362
- 0x64e67cfc 0xcdab05b7 0x72e23276 0xc7dd5753
- 0x409f3b09 0xfa93587d 0x99eb8cff 0xb6c5fc09
- 0xca99a2a2 0x7f5583e9 0x2fd55cd2 0x38a65dd0
- 0xa16d92a2 0x286f021f 0xd71619c3 0x7d1c61f3
- 0xf7507ce9 0x6c2a3eee 0x1053a2ae 0xb63e258e
- 0x86f335a4 0xb5b07b32 0x0d156a38 0x53755412
- 0x76a542d2 0x26f25a85 0xfc038aab 0xa9d96a0c
- 0x8575d08a 0x24805c0c 0x39ea0650 0xb2edc539
- 0x1df34734 0xf7728395 0xe17c0196 0x54079a46
- 0x5c52fc37 0x09d2d435 0x19f28d5d 0x92dc3611
- 0x4f7fa756 0x19a128f0 0x3e273d1d 0xff6309c9
- 0x2c34216c 0xba4cc184 0x8873b38c 0xcd84fcdb
- 0x3ede1e50 0x286cfb74 0xef17d548 0x01e12784
- 0x5365dfce 0xe808116d 0x619f6117 0xaaa322f5
- 0xc81e268a 0x8303df05 0xe251ffa3 0x86b43181
- 0x1f6ab10b 0x60c48f73 0xf0a299df 0x311f1a35
- 0xcf1b31d1 0x67bbee54 0x4be22f23 0xe1cbb341
- 0xce778173 0x495c5dd4 0x2597b567 0xda1bda27
- 0x45409289 0x5f8290bf 0x9b3d5714 0x5a732f3e
- 0x9ec75a75 0xa062a5ae 0x1d9b6d09 0xa983c663
- 0x0fc1863b 0xef46c113 0xaf6517a2 0x3a90caa4
- 0xc1c36909 0x16a68595 0xd83751da 0xf965e105
- 0xf0a2c08f 0xaf5a83cb 0xb1ef85a2 0xb994a331
- 0xd0dc78d2 0xeb278a2a 0xe22a165d 0x3f1f999c
- 0x5b7c2d89 0xa0a9afbd 0xc42db24e 0x061c9ef4
- 0xbf09c71b 0x2e14198c 0x8765e181 0x6eb6884d
- 0xa91be755 0x8d203fe3 0x80e25674 0x0b39ba38
- 0x12cb68bc 0xf0dbdc5d 0xb95f1bab 0x7ce7663c
- 0x227dc658 0xcd46afb7 0xaf9127c3 0x0ba73835
- 0x613b23f0 0x599e6f37 0xb5e6463b 0x49557c88
- 0xb104b402 0xd5276a66 0xa68ce0da 0x5d229e9f
- 0x59292206 0xe71d18a5 0x3627be43 0xa1931f4d
- 0x9b282f64 0xa429e37d 0x2954801c 0x78f8ff7d
- 0x72d0997e 0xb6333f10 0x9db0ae49 0x849d6972
- 0xf3105f52 0x42413f96 0xddb2c652 0x99802d95
- 0xeeedf598 0xfd785866 0xd13a7b1a 0x225a59fd
- 0x19722276 0x9a016c80 0xf4d22f4e 0x5a739fb9
- 0xbaa3488e 0xcf913c7a 0x7ff05f65 0x0b5ecfe3
- 0x86a7dbde 0x2de1255b 0xbadc1a92 0xe8be38c4
- 0xf13fa2fb 0xd46894cd 0xc48b9503 0x8e715854
- 0x3a03fe9a 0x013e5b08 0x4f46f488 0x7e27181d
- 0xec159b58 0xc4977b80 0xcd454784 0xbbaa3742
- 0x124eaaa3 0x66414ef9 0x1e514b4e 0xe978d0e6
- 0x46d8c643 0xd316c855 0xb84dd9b7 0x5122465d
- 0x34c59dac 0xa6f10643 0xd80b3949 0x07536f2d
- 0x4fbcc30a 0x8aa8a4b6 0xdc2be5ef 0xbc3e1c78
- 0xc25d1ebd 0x96919bed 0xdb37931b 0x6e077871
- 0xfb2bf61b 0x9a659648 0xeccda7dc 0x79e86b23
- 0xf1c18329 0x59830510 0xf1dcfedb 0xdc7d2b84
- 0x41e7afd1 0xeca8021d 0x7312d4fb 0x7a45eeb5
- 0xbffc8a1e 0x494d7c24 0xc2a84a95 0x460a0ddd
- 0x7e44dbd5 0x2109fdbf 0x556374c2 0x616bf76c
- 0x8b3ae7b6 0x0e2cfcd1 0x65370b6c 0xf1fbb913
- 0x81c57609 0x4c2cadad 0xfc74a3cc 0xc9556305
- 0x16464838 0x5ef7fb12 0xc90eb9f4 0x72353a20
- 0x46bc1ec8 0xd3b12916 0x51c45e0e 0x061b53b2
- 0x1a203faa 0x4e5e3054 0xbaff1858 0xb65398a0
- 0xd5b4eca8 0x5649844c 0x2e1c6f6c 0xf828c53c
- 0x689565ba 0x76f11b18 0x5dfd40ae 0x1d98abf6
- 0xc9322c46 0xa22604ad 0x2740ba5b 0x99eb85be
- 0xb52a3340 0x3fde5fb7 0x5e0e3a01 0x60f69345
- 0x37f6fd3d 0xd084006d 0x26c3a62b 0x161b206a
- 0x2a224c7e 0x93a45c60 0xfacdce07 0x2e7b4058
- 0x3c79d10a 0xd7939bc8 0xbca2e30f 0xf22b6c21
- 0xbb03c5e1 0xf30b3651 0x2fbb40f4 0x8050c8d8
- 0x8683e045 0xe6024d08 0x81dc0b0c 0x8cd923e3
- 0xdf8df717 0xb1f8d6f6 0xb0469246 0x79ea7958
- 0xe3743d7d 0x83e1cad3 0xeaa7fd02 0x4d3aebc0
- 0xba63ef51 0xd5cde1ca 0x1bdf1383 0xbb462d70
- 0xb777376c 0x5a382db2 0xaed44fff 0x130fdd93
- 0x1ed8bc23 0x1f3c7297 0xf3e79215 0xaabc0139
- 0x50005a1e 0x55ca82c7 0x58778cb8 0x2e58a478
- 0x4c4cff0b 0x3c44a21f 0x8f108d67 0x58211b23
- 0xd233181a 0x9e46b169 0x37533a95 0x33bddfef
- 0x777df938 0xda8a8239 0x45af2beb 0x3613b03e
- 0xe6ae05f4 0xe33730a2 0x1e65dff3 0x7a64a0d2
- 0x79273ca5 0x580a16b5 0xc51b39b5 0xccea7be3
- 0x29d9caff 0xf7377acf 0x0bc27444 0xb68b6ba4
- 0xa75ccbbb 0xdbf69f05 0xe8be0152 0x569bdc28
- 0xb8ebe746 0x43398e79 0xa7def566 0xc99e1f1c
- 0x3be29c87 0x6e4c4b68 0xb8a37b2e 0x84970f9c
- 0x178d4e72 0xac72ec6f 0x0862e04d 0x85cdb66d
- 0xd6f2feb9 0x10d299c2 0xd91a74a1 0x831697bc
- 0xd0038240 0xbe9aed06 0xe808bb08 0x49462fac
- 0x7efb2fbe 0x1e276eb9 0xf83b97b5 0x3754f4bb
- 0x4449cb0c 0xcf2a2866 0x04840e6d 0x9d9b6551
- 0x3b50f722 0xd8f7f14c 0x9ba685f6 0xcf6bed00
- 0x41012924 0x82b27e98 0x7541d6e5 0xfa5b81cc
- 0x91d44937 0x46d27cdd 0x91570abf 0x959e1e97
- 0x7ee9da66 0xf82883a5 0x87afb380 0x761c818a
- 0x180811ad 0x095d4970 0x751dee19 0x9f438246
- 0x32a3c642 0xb3b34b98 0xab450f56 0x539a6ffd
- 0xb339563e 0xe8808c93 0xc7ad9eef 0x0dc36b70
- 0x1278e749 0xe83d046b 0x987de721 0x2115e00d
- 0x7a09efd3 0x8e56c4f1 0xd5de351b 0x98eb73c2
- 0x9becebb9 0xb18998d9 0x3ee01945 0x20eea116
- 0x846bb55c 0xb7f624c5 0x6f7b7463 0xcbb986ad
- 0x545c3c41 0xd754bfbd 0xfc4148ec 0x312f89dc
- 0xe2894337 0x7867e25b 0xeb11c6df 0x9fb721ac
- 0xa843962b 0xef242fd4 0x6fcf4b6c 0xea208951
- 0xd521c86f 0x08f67a28 0x07209b9c 0x6ee42989
- 0x9fdc0e42 0x3794b7db 0x038a398a 0xb339b4b8
- 0x6d621319 0x6b9d713f 0x3537ff34 0x3fff0baf
- 0xa5c0e302 0x8fdfa8da 0x50dede4b 0x448ed0b2
- 0x2178bf5d 0xf7dc834b 0x9762f1aa 0x087a9b65
- 0x7f3cc965 0xcd1c011a 0x4c630727 0x755908c4
- 0xe33580fd 0xca010764 0x677b59b5 0xb3d182d3
- 0x55c2d739 0x8c6f67df 0x10f6b558 0xf034ee76
- 0x540009e2 0xe6343edf 0x95f2508e 0x2a9c22c9
- 0x5d42e77e 0x82216d23 0x10ad67da 0x8ec77e6e
- 0xa88a3bb0 0x4e10dc6d 0xf3fa2dcf 0x59be53e7
- 0x25f758c1 0x2c42fef5 0xba575ddc 0x0435bf50
- 0xd390d087 0x6e230259 0xf7e3c764 0x52c16ff4
- 0xf2a6105a 0x31f0188f 0x83f2582c 0x2b73521d
- 0x6b320332 0xcb7f3899 0x17f23cd3 0xab7d47d2
- 0x535f1340 0x700ea217 0xbcf4f83b 0x16ea4470
- 0x76a618f7 0x30216e93 0x6e80cfd7 0xcf706ae5
- 0xd766457d 0x0ebc1377 0xdcb10949 0x2f679120
- 0x5cc6abdf 0x65754d61 0x1a3dab69 0x8f349b8e
- 0x95bb833b 0x5588b280 0x0f0fa923 0x21250ef5
- 0x73bc2547 0xcd7dabe5 0x4795737a 0x82b92e90
- 0x896f9de5 0xa18ae6d7 0xfeeffde3 0x346b0557
- 0xdc7c068a 0x4e6eed51 0x4ff07c63 0xdd15b445
- 0x97808676 0x304a0912 0x7fe07453 0xb9e64599
- 0xd7a57b8d 0x7f4fd506 0x226719e4 0xe6c251e1
- 0x7ea1ee5d 0x6051b787 0xb00b6e40 0x6babdb06
- 0x725fc094 0xf35fc6d2 0x4e7d6c3e 0xa5a718f4
- 0x17f63fb4 0xc39bf11c 0x808332f9 0xd2c07986
- 0x57bf130e 0xe1f5656d 0xb52a43b6 0x9a105745
- 0xafc22c4c 0xeb5b8a45 0x39153d0c 0x55f1b477
- 0x4a947d5d 0x83dee3b3 0xc3d1e1c1 0xc6dc4d47
- 0xfb93a531 0xea002909 0x95e58a9e 0xf14453ee
- 0xe7fe7f8a 0x6eb7bf4e 0xfd74da03 0xe2a994cf
- 0x4ec6321a 0x27c4a2d8 0xfaecde76 0xd4ba53bc
- 0x22b291c3 0x32dad786 0xedc8172b 0x98f6cbe5
- 0x0407f9c5 0x0e3e7894 0x68c4562a 0x2264dbe4
- 0x938a45c1 0xb02c5428 0x31df8b31 0xefb49223
- 0xad0abeb3 0x9ce02ca2 0x7906e6d5 0x2fbe9f55
- 0x3dfed450 0x9a9f5854 0xa99171aa 0xdedd910f
- 0x3e7727bd 0xbf49e35f 0xfb435c59 0x872ca461
- 0x9693c2e5 0x4d9f7917 0xbf9b494b 0x4cb695ce
- 0xc21c2629 0xaceab2b2 0x30a8686c 0xc09e85e3
- 0xe3cf9904 0x39d0db4d 0x73e0c451 0x64b5d63f
- 0xc27777a3 0x91272d8e 0x511db1dc 0x9d1a6175
- 0x9c7e83c0 0x60037169 0xe9d248c6 0x54d04f10
- 0x99787291 0xc3ee42f5 0xbbd26f8d 0x7fa0ab4c
- 0x1e1e7f10 0x170b04bd 0xdf46d792 0xb17864a5
- 0x832c1074 0x17783980 0x174f75ea 0x92980341
- 0x7aca43ef 0x851a6e2d 0xa25dfbd7 0xf84cff03
- 0x8a3d6563 0x8fff04c8 0x9ac359da 0x58a7b145
- 0x57c1e741 0xbc735a98 0x171bc199 0x9f704237
- 0x1efbde72 0x79b48991 0xa7d67d95 0xe9869769
- 0xf6324dbe 0x17360a53 0x2131f704 0x5cf7b840
- 0x53101e35 0xe71c8bb6 0x1c10fa64 0x28aa5883
- 0xc41d3377 0xe6c3556a 0xa5140cf0 0x1e0224b6
- 0xaabe86f5 0x00b520f4 0x346aa560 0x7de8aef9
- 0x2a19e4a0 0xbe2a2772 0x93653c17 0x2ec53d8c
- 0xd0a5ea33 0x985e6fd7 0xd300651c 0x72ce1567
- 0x16559001 0x6e459145 0x2dafc413 0x28f514cc
- 0x2d1b9e94 0x798b5770 0x3bd27af8 0xd5437be9
- 0x0bc1de32 0x83f58c43 0x4a968323 0x873cf533
- 0x44b8f501 0x8caa31dc 0x90961244 0x257e5811
- 0xfb1c4c4d 0x7203f540 0x9d2294eb 0x533e9896
- 0x670bf234 0xefde4d0a 0xace846e0 0x16a1421f
- 0xe6a40e79 0x8b0f861c 0x63b8416a 0x80bc7963
- 0x035bcc06 0x2f3a8636 0x4adeb4a8 0x527a1f98
- 0x6d0ae365 0xd430ee93 0xa54d6e88 0x9e492859
- 0x6d435e2a 0xf3f336df 0x8789fe48 0x04683847
- 0xeb35012c 0x793f787f 0x1649fc98 0x4daae27a
- 0xa899ef37 0x0aa874e3 0xe877985f 0x3877168e
- 0xbcd9af49 0x925bd4a0 0xd7653ea4 0x1a7356c1
- 0x53cf5cbb 0x5b3e660a 0xce923831 0x42ea11b2
- 0xcb85c607 0xcb4fef4b 0x33ac8e92 0xc68e0ee8
- 0xda28f304 0x34466a58 0x4e3ed659 0x433c37d5
- 0x6e5d8f11 0x2306c1d7 0xb8562926 0x857280be
- 0x7f6978c9 0xb6127ef8 0x848ff180 0x3f175d08
- 0xc9ea3682 0xa7f8401b 0x073a04ee 0x75d43c6e
- 0x193e70e8 0x9e6ee78f 0x5eda1df9 0x53e54ed1
- 0x94a57a5c 0xd66dc923 0x121c0f87 0x637f93d0
- 0x52b5658f 0x34ca3432 0xed262d4d 0xe7c3c8bf
- 0x05519bb1 0xa27335b6 0x8aeba357 0xa9edeef9
- 0x06dad515 0xcc0258ca 0x0db85a3d 0x4edbeee7
- 0x8efdc1fa 0x53f1f91c 0x367b73bd 0xc9785288
- 0x8046ec91 0x1270cb82 0x6a5cc22b 0x7c56f6c4
- 0x09140a7f 0xa362df46 0x794ba791 0xc280f317
- 0x0a8c218e 0x8fd18bc7 0x9d112770 0x4a94c675
- 0xd08f6e86 0x200978a2 0x08bb8824 0xeda38a74
- 0x396364ed 0x4cf3fae5 0xd1bbcc8a 0x38e68b54
- 0x49fe9e89 0x0f372a6f 0xcb8206ec 0x686c51df
- 0x3d21fba2 0xeed5addc 0x8cb09804 0x7b144b6c
- 0xc31b72c5 0xb2e1fc8a 0x699440df 0xa1484706
- 0xbfd64898 0x87c7d89f 0xdd1f06e2 0x9048531b
- 0x3fb97a6f 0xec79fb12 0x1a81577f 0xf6fe7c86
- 0xfa572435 0x0ed1607e 0x85823de4 0x2688f491
- 0xcd6f5341 0x55c944e2 0xd94a5421 0x43b0eb08
- 0xabc52c65 0x3f624e64 0xaaec22a7 0x0b6fc108
- 0x0b5e8a54 0xb9f36d25 0xf531e230 0x18405343
- 0xadf99cb1 0x779851bb 0x93aec541 0x8364b884
- 0x9e14f66a 0x389f6625 0x94d43b9a 0xd9f3b002
- 0x34b23621 0x80599e02 0x7ab4a0f0 0xb0428b5c
- 0x8510def7 0x2871743f 0x350d0bc3 0xdbe61d9a
- 0x787b3c6c 0x80272431 0x2ed6efd3 0xcf77c8b4
- 0xa21f406c 0xcb82aafc 0x451b3a49 0x4bfd9ae6
- 0x4bb86748 0x03fbd542 0x329ad4fd 0x0761e756
- 0x07f31e88 0xe6aa2f44 0xc209345b 0x250eab3a
- 0x2710b3b1 0x710bb403 0x921c083c 0x94e25ccb
- 0x6b344255 0xda1501d3 0x3e0dc98c 0x2c09adda
- 0xefbf0286 0xdec41f1c 0x3865e02d 0x211215e6
- 0xbd3e4351 0xa3b9abc0 0x9ab908b2 0x5c345108
- 0x0175a871 0x3611d15b 0x54733b2a 0xe57bfda6
- 0x3b507ed3 0xcdcd1007 0x5314fc0d 0x3ef57680
- 0x181ffd9e 0x27a7e64f 0x7a780684 0xc8fadf11
- 0x13415b31 0xce53dcd9 0x55488687 0x858b70cc
- 0x14067837 0x0f3f012f 0x41f0636b 0x1c8d2f52
- 0x9dacc300 0x63b27876 0xe1c23617 0x02c57956
- 0x85a91d2c 0x0740e7a4 0x619eab0c 0x10f254ca
- 0x9ec8ca01 0xdfd090f4 0xbac084ac 0xa1f8168e
- 0x7fa0e114 0x282b1cac 0x8e1283be 0x9e108b3b
- 0xc6eb7a09 0xf8d643a3 0x3b4afa67 0x3e7f307c
- 0xa5fb1937 0x0b00178b 0x017369f8 0xafe1fcff
- 0x29987f54 0x965cfcd5 0x0e362047 0xd03dfc30
- 0x9540bd32 0x2c688ee6 0x6c32d9c1 0x5935278a
- 0x11b6c4c9 0x69202bd5 0xce48e114 0x9c5bc22e
- 0x3e92fc71 0xb77657e2 0x9232fd3f 0x76dbd637
- 0x1d672fbf 0x4dcb0727 0xe719838c 0x3db49bc3
- 0x77d94683 0x6d82214f 0xdd3d51cb 0x3c23f486
- 0x46253c8d 0x347089d1 0x7fef2912 0xee1d3cb4
- 0x10da8cbd 0x7172b3ac 0x95c24117 0x60d1bd52
- 0x1b2b9552 0x20ac6729 0x3614535b 0x830844db
- 0xd9310617 0x3480f0ae 0x8e2e14df 0x4a02c210
- 0xf5944144 0x680b5216 0x5b5ff941 0x921f8c17
- 0x798012fa 0x43dd9855 0x725e40e7 0xb3bbac37
- 0x44ef21ec 0x7fcbcfe0 0x0630ce23 0x3f39b5dd
- 0xf0b3f7dc 0x51bdefd5 0xf5e0b7ec 0x3a2c2398
- 0x00e4ad5c 0x4017fa32 0x205c567e 0x70c646e9
- 0x81c0291b 0x33c5050c 0xeda458a6 0xa6c868fd
- 0x1b70f270 0xb661cd4e 0x322b97a9 0x1572f522
- 0x004792fd 0x01d23270 0x667b335f 0x5da3142d
- 0xb7de831d 0x9736e866 0x0a70d898 0x16d1b373
- 0x70bd1a6b 0x75170aff 0xe98d71af 0xb9829684
- 0xedaa0924 0xbc67c151 0x155b4797 0x63c8d08c
- 0x7811c5b5 0x84a348e8 0x6d841a8a 0xdc0e3707
- 0x3defd447 0xac78f3ba 0x44ac7616 0x68147936
- 0xc3f6fe4f 0xe3550b13 0x1dbb593e 0xeede24e0
- 0x3935ec43 0xe0a30569 0x66a0223f 0x32b741c6
- 0xd9e35135 0x77793169 0x8479a087 0xcf7433a2
- 0x91d6967a 0x34aee2fd 0xfd68c051 0x6375cafa
- 0xe5d7a0bf 0x1a3cdf26 0x4f0765b6 0x89dd8de2
- 0x0ebfa813 0x8a5b91c0 0xd698549a 0x4ee2cfb4
- 0xc2dbd4a5 0xd0e2ab9b 0x9765a4e8 0x880f32ac
- 0xf0f30fcd 0x74021c54 0xa1d6944f 0x25270ba8
- 0x75dd0748 0x770e7b69 0xd6dafdd2 0x0254ea84
- 0x427eb60e 0xf5a422b1 0x53fbc0e3 0xb470027c
- 0x3ff09ede 0xbecc9100 0xba2d3ea8 0x86295a6c
- 0xf3a8690e 0x503f198e 0x7498daba 0x4c04fd03
- 0xcebcfdcb 0xec671b62 0xeb98f36e 0xcf3d095d
- 0xfc627be1 0x7a6aa482 0x4961f814 0x82a9df39
- 0xeab68128 0xe618105e 0x603e4e80 0xd42305a1
- 0x2ab596b0 0x66ef4bf8 0xbe2d8a31 0x7571fd10
- 0x6ad34e73 0x77c92e69 0xf70829d0 0x243bca33
- 0xa41899b2 0xad3847d1 0x326085c9 0x1e32f76a
- 0xe5939032 0x2ef87117 0xedd0598b 0x0f5b0ab6
- 0x843d972e 0xbdedfd02 0xf6f281d2 0x806f8619
- 0xc0d4e6f7 0xc7c752e2 0x4cb18e8c 0xa3109bc7
- 0xb3c9d39f 0x5fed1b89 0xf56bf4a6 0x1ef9ad37
- 0xb6d27d00 0xd62e0e2f 0x427c1f76 0x64b708e3
- 0xe61b8094 0x58c140cf 0xc9ed8bfd 0x549d8321
- 0x887f495a 0x9b92965e 0x19dd4f23 0x48faa916
- 0x536988d2 0x5c41f555 0x78dd7a98 0x52c98af1
- 0xaf1aa0a7 0x472d9c18 0x5072ec30 0xcb8d8c2a
- 0x20ca2831 0x54741df0 0xde485e64 0xde719ed4
- 0xd0e4fa14 0xdbe68e08 0xc4b52f6b 0x7c478181
- 0x5ce15685 0x20bf9757 0x01ccdc90 0x3f59a540
- 0x09dfd538 0x96d5313a 0x11b8a5b5 0xb185b4a6
- 0x80b8ebac 0xdcbf7885 0x1f78d8ed 0x3f845528
- 0x8f10047b 0x31048ec4 0x08b16c82 0xef8212ce
- 0xba7e12b6 0xbb27b4dd 0x880c366b 0xbb9013e9
- 0x680e9afc 0x639c8dd4 0x67a899a9 0x95d99658
- 0xcdcd0ef6 0xd35bf9ae 0x73dc39ff 0x1159cdd6
- 0x820e821a 0x233b30ac 0xa5355178 0x508a060b
- 0x70f8eb69 0x7dd6cd6a 0xc9babdac 0x952886c9
- 0x20a4d780 0xcafe7a7d 0x4a564d22 0x23c88386
- 0x95dcd3ba 0x57e703c6 0xbafaa61d 0xd515f701
- 0x1634dc08 0xaf721b5c 0xdb4b52e4 0xcb54c7f2
- 0x1bdf64d1 0x7e798a76 0x20066741 0x1ecacec1
- 0x2d5be224 0x8eec039c 0xa2adcff2 0x6abe342a
- 0x15929ccb 0xde4a5a29 0xb0ef2733 0x51e6e38e
- 0x88f7ded5 0x9a7c3d12 0x0102cd55 0x1e5fa60d
- 0x43e10b70 0x17c67005 0x6d60158b 0x03ebc351
- 0xc1877454 0x99486475 0x68e31d63 0x4ef41164
- 0x1250792d 0xe2dbb2b7 0x3f041adf 0xc00f1ca1
- 0x0bf6b065 0x581d1496 0x6babf291 0x0cab401a
- 0x37305a02 0xd8b025f0 0xd9aad863 0x33378c27
- 0xfce64bab 0xb944fc9a 0x421cb71a 0xeaaf1a0e
- 0x08c62ae4 0x4be73168 0x95907070 0x7b40f3dd
- 0xa0273b1e 0xe4995d27 0xb6aa456f 0xbbefad85
- 0xdf650ed9 0xcdfde8ec 0x8f3ba9b3 0x6c8aaa45
- 0xbb938c57 0x2d26fcf3 0x1fc85e00 0x30338e08
- 0xe3502aad 0xfe0528ba 0x25c888e4 0x136224fd
- 0xe3fb8d06 0x8b521420 0x8d4849b0 0x128a5579
- 0x485bd52d 0x46ced7d5 0xe922bb2d 0x76d52253
- 0x976436c0 0xc3fa64e6 0xf900fa97 0x1ef8db2d
- 0x79a8b6e9 0x1ff2b058 0x61dd59cb 0x76eaffd9
- 0xdaad829b 0xaf929bc6 0x7f1461f0 0x28541e57
- 0xdb2223ca 0xb5a41af3 0x963dfe3c 0xf332afee
- 0xf01270c1 0x37fff0d5 0xa8db736d 0xbf6b8ace
- 0x060b9827 0xe04fa359 0x8483405b 0x526756af
- 0xf93bd116 0xaaf82ddc 0x3d800e46 0xa462a35c
- 0xb62236e3 0xab42ba34 0xb662603a 0xe8a24ea0
- 0x4b13879b 0x0271f215 0xb7227ebc 0x1c85b75a
- 0x06a7f989 0x5a58a071 0xf027ba62 0x3940d149
- 0x174c162e 0x1710f899 0xe50684e0 0xe58982ee
- 0xcb3b9fa5 0x545dd73d 0x42a33d21 0x14ce3ed8
- 0x151fc3e7 0x6fa96a65 0x60131642 0x20115648
- 0xe2fe3663 0x618bb9ab 0x9b2fe08c 0xce906711
- 0xb9fbe11b 0xce79c0a2 0x76320db5 0xd2b8956d
- 0x3c8fba1b 0xda7d5cfd 0x79930fde 0x7b1eaab3
- 0xe4190098 0xe46cc648 0x796557fa 0xe61f5c5d
- 0x85341adf 0xa01cc486 0x1460f8f8 0x0de8488c
- 0xc3575498 0xdaba60b1 0x6e00e9de 0x8de1e277
- 0xd7ef67e0 0x6f209a77 0x582ec810 0x4636f6cc
- 0x6bd9e60d 0x64ea05fc 0x580f9f7a 0x0f18218c
- 0x240f624a 0x0afc252f 0xb025c839 0xe6a5afc3
- 0xd5e32234 0xf30ced0c 0x90f032cf 0xb6fd59b8
- 0x2ef1aeb8 0xdd5d3fe6 0xa18a909d 0x65c3e9e1
- 0xe821d2f9 0x957146ce 0x86ea8c2e 0xea79a59c
- 0x91bbff8c 0x50efab7f 0x4a8c0919 0x11faafd8
- 0x3f3463b9 0x80e0e50a 0xdbcc8485 0x3f7c058b
- 0x4cfa4e1f 0xff8867ed 0x6bf2f6e9 0xa61daaaf
- 0xb718eeec 0xefe4f834 0xd0c4727d 0xec787df0
- 0x85bfe1f5 0x7329affc 0xf4c0ed95 0xa6a8b495
- 0xb3bd1c06 0xd38e0a09 0x26e3f747 0x6bd5ceb3
- 0x5eef12c8 0xd1011d66 0xb1dd692a 0xba1294c7
- 0xf7ddcb0f 0x4dbd2861 0xb29db408 0x051fb421
- 0xa4fd5f8c 0x1ad5a3d0 0xd95aee42 0xd52203b8
- 0xc4e76978 0x5780ee25 0xc38f6280 0x0e4bdb05
- 0xdeaf0dc3 0xcada9dc0 0xf7dd201b 0xffe07b67
- 0xe486f4d5 0x72a0b32a 0x518c1122 0xc240db35
- 0x1d7b5a09 0xa26636f5 0xe1b716fb 0x9158d0d9
- 0xfbe3b60e 0xd37c00dc 0x551615da 0xc7fde3ed
- 0xac94b6ae 0xcc87d6a7 0x0d010d6c 0xe1bc4072
- 0x8d8a4caf 0xf4381342 0xe3efc8dd 0x64be88ba
- 0x0eac9658 0xd10e87c6 0x8dc223f5 0xbbadd543
- 0x3ad28376 0xba68d553 0xbce5620d 0x1adc3d5e
- 0xa64d27fe 0x65086819 0x80b82c62 0xff91b5cd
- 0x97cadf1a 0x2cb0d45c 0xa73587ca 0xdaffecee
- 0x299e3888 0xb4c116f2 0xd7aee299 0x9c33d177
- 0x8af686c9 0xba6b45b6 0x47fe7688 0x1e49d908
- 0x721370a8 0x1220ffc9 0xeb62dcbd 0x4255a463
- 0x13ef302e 0x619bc137 0xce369fdf 0x3a1ded2d
- 0x88dc709e 0x4b10b186 0x582eba1a 0xb508101b
- 0x6e827983 0xb25e5755 0x9f29bac5 0xdd946461
- 0xa6b87255 0x92471f76 0xac61af93 0x670e9ae7
- 0xb3cc278f 0xb674f114 0x5616b751 0x527869b2
- 0xb6847ec3 0x7c94f508 0xdedd2e51 0xe322e023
- 0x3ef45d78 0xc95848ce 0xd53c243c 0x645d8456
- 0x1c510cde 0x243ad2e5 0xfafac2e4 0xc23ad8fc
- 0x481fe577 0x1f73fdc8 0x4cf5388c 0x8afb0c47
- 0xe39a7e0e 0x439e32a0 0x1a3af126 0xdd0ddbcf
- 0x56efe7bb 0xa4526c50 0x1f1e8d7c 0x6fff2758
- 0xa9cfc7c8 0x9aed3088 0x1419791f 0xc41006c6
- 0xe665ffb4 0xe0cfc001 0x5ac279f7 0x8dda44e8
- 0x6ba63b5d 0x11cd5e85 0x87b35603 0xfcb57486
- 0x64df1bbe 0x1df9ceb9 0xc2565187 0xbb6b4730
- 0xa60ba743 0xb50ca534 0x224eecf0 0x8acbd1e3
- 0xff2a22f6 0x00b94b20 0xb2bb1824 0xe3af6f67
- 0x78db1d5c 0xa3dfaa5e 0xb23a1a59 0x234628d1
- 0x46a0b6b1 0x6d7b354d 0xd7f14b18 0x492cdb7a
- 0x4b0e5fb1 0x3b210deb 0x82ba85b1 0xe5af7727
- 0xde5e2892 0xf4ba96b6 0x1011fde0 0xb96e65b0
- 0xb3f72d55 0x4388cb56 0x09f8801d 0x534eecde
- 0xa30f33cf 0x2454f5c5 0x5f32f1a1 0xd1d008eb
- 0xadb25f06 0xea32375f 0x71734ccd 0xc989e49c
- 0xb45f560d 0x49ed0d08 0x5ccf1394 0x5115dd15
- 0x46876215 0x20e6e84f 0xd5deaeea 0xe559d4f2
- 0x1e1c44d0 0x9f582603 0xad90b17d 0xf16c26c9
- 0x7f0708f0 0xfeb0b9e1 0xb853f20e 0x16f3ff5c
- 0x1789f6ba 0x236bb3aa 0x906f2ccb 0x255c8814
- 0x9d762cb2 0x2846e2b6 0xa34f8522 0x2502c2fe
- 0x698ad3e5 0x09c88175 0xdbee86b6 0x264167d1
- 0xcce5d399 0x78a3f959 0xa0a515c8 0x36c2db5c
- 0x5dec037f 0x56a558ad 0xa17a21b5 0xca0296a3
- 0x963a70b4 0x2733e44e 0x4f979549 0xf3738ba0
- 0x60aff2d1 0xf66ed176 0x8f658d9b 0x1e83fc2b
- 0x28a3d57c 0x1d50c6d7 0x434f286e 0xbbd6f950
- 0x5bfebf75 0xe366392a 0xbd328d7b 0xf10a2ad9
- 0x59504439 0xac3f2cb8 0x28cd3fd9 0x3776a6d9
- 0x5ac2b26e 0x25171f43 0xfb20e0e7 0xda4565f0
- 0xcf0cd438 0xf54f1ff9 0x33322457 0xaa368462
- 0x540acfd9 0x331fff32 0x8b66b3b4 0x19a74ca7
- 0xe3037b68 0xa4ddcf1a 0x48dfd4e6 0xe0302745
- 0x21522f0a 0x3b9f1cf8 0x2f7da1d2 0xd1e02b1a
- 0x89d834ef 0xc03b327c 0xa32b106f 0x2bfb3409
- 0x7f001db1 0x9ad9a334 0x0f2e5ed3 0x1063a583
- 0x6cb009d2 0xe9670521 0xdfcab184 0xd02add2b
- 0xfa7721f2 0x6e772878 0x11c5f0cd 0x1d228ded
- 0x54d84a8b 0xffbb136f 0x489a4619 0xf51cd9d7
- 0x6618cdff 0x76685892 0xfebcf111 0x02ee0a86
- 0x77ffdd9e 0xd36303bf 0xed4a8619 0x0160eb27
- 0x0b7ae017 0x7e3919a8 0x1b0c65ca 0xc8c7ef9a
- 0xdd593e48 0x48091b98 0x5ad15379 0xf9f54186
- 0x8c064d3f 0x09f23b45 0xb1bf1f50 0xdefe3c11
- 0x3d9c3506 0x328acb8a 0xc0efd1cc 0x7f3e472c
- 0xbd0855c8 0xc32d33ea 0xb2aedfad 0x5f9c5e3f
- 0x39fab7b6 0x3d58511c 0x74dce606 0xca5975f2
- 0x7adc328c 0xa7f2cf36 0x9084c11d 0xa25fccfd
- 0x0f5591e9 0x7c912a6d 0x6bcd5638 0x74174d51
- 0xe4f38864 0x545a4f72 0xad79bce7 0x68f23ea3
- 0x2c29455e 0xb2dce3e7 0xf75922bd 0x62d9d813
- 0x2ea9daf9 0x9544ba17 0x1036f50d 0x003d0734
- 0x6de2f91d 0x12de6d4e 0xbe6f77c9 0xcdc6f7e0
- 0xb7bc6908 0x8102989a 0x81b1ecc4 0xbec4c06b
- 0x57ae207e 0x0d9bf8ed 0xf82fd233 0x626e99b4
- 0x775ba43d 0xfdbe57b3 0x9e13e0ae 0x8f9e71cb
- 0x22e5b181 0x879a9646 0xa59f02b6 0x315bea64
- 0xfc2d998e 0xf3ee358a 0x465f0469 0xae5e30d1
- 0x8667c5ea 0x4d3797f1 0xdd9119c1 0x8a5c7526
- 0xefdbe49b 0xcba8bf75 0x31c56598 0xb089371a
- 0x50b88730 0x8b04e9ea 0xbe766234 0xb589b311
- 0xac86a2dd 0xf3cab9d4 0x8392e86e 0x459f4c2d
- 0xdc6e9e42 0x38fc7db6 0xbe1c3f55 0x87827bb1
- 0xd3fb2dae 0x29f65cb9 0x288ee868 0x44ef835c
- 0x5412f96d 0x8db90a63 0x619eb896 0x819145d0
- 0x4c334fcc 0xb28d29d1 0x71198c8e 0xcb7a1ec7
- 0x67d911c8 0x83e5b451 0x18dc1483 0x74d2d7fc
- 0xfebe405b 0x1b1865d7 0x552adee0 0x62e24345
- 0x4c772a36 0x047bfaa5 0x848961c3 0x86f2f24c
- 0x3f5db1e9 0x48c4d9c7 0xd7902c02 0xa0dfb8c6
- 0xb16ca129 0x7df0a350 0x58e2570b 0x6c0aefa5
- 0x2c8a35be 0xd155ab73 0x0801d1ad 0x913ac469
- 0xc6398211 0xa44aabec 0x74f991fd 0x122423d0
- 0xd1d7f77d 0xeccf8eff 0x59ecfdbb 0xb85cd73f
- 0xbd10ba8d 0x0c9880b2 0xcabcba47 0xc11e71ef
- 0xcb57870b 0x3a29030f 0x0bff4c01 0xf2629315
- 0x6686b1e9 0xd2b50835 0xec24eb6c 0xb23c7e88
- 0x045a35c1 0x5fb62127 0x2dcc31f7 0x5c47cd7b
- 0x1059b75c 0xe2d6d12d 0x6bc8f0da 0x30ade89c
- 0x35b06222 0xd13a1347 0xacbb2f8a 0xb7fc8acb
- 0x2edd849b 0x8d74157a 0x562d8d4d 0xa393948b
- 0xb89b904c 0x418eee39 0xd42898ae 0x630e1cda
- 0x96c56104 0xdd16c830 0x89ae9ec2 0x1e1cadb2
- 0xb8ea73b8 0xabaa7ad5 0x654ab956 0x17b2bb13
- 0xb064652a 0xbf9897cf 0xaabb9b9e 0x38a0654f
- 0x8bc378bf 0x11559864 0xd193ee51 0x3883fef8
- 0x461d458b 0xc35b1b22 0x570015df 0x2b18a043
- 0xab4aee83 0x4e0bff9e 0x323dafd6 0x8bec69ed
- 0x1846d886 0x0ed944bd 0x9a2b4a60 0x132616d5
- 0x86f3c871 0x76ee6765 0xe971f2cc 0xabaac761
- 0x59bf478b 0x0d83ee79 0x0883a1e1 0xbb4660cd
- 0x24c77bd5 0xed55f531 0xfaea8dbc 0xdfecc13d
- 0x285e5bef 0x7b14cc12 0x68cb6d5c 0x07b7a0a8
- 0xaf3d6e45 0xbceb6223 0x1eeaa87b 0xbf0f9998
- 0xf7582f97 0xce1d2f25 0xd8509595 0x1f6729ba
- 0xe3fccc36 0x7ca2d51b 0xa92c327c 0xe1b49064
- 0xe3cc87e9 0x82c05001 0x9d855812 0x0a7cda02
- 0x65017632 0x1b226e96 0xd4ffaa0a 0xc5a5e42e
- 0x04ba35e1 0x39f6606d 0x23668a62 0x9f670515
- 0x4fa60d9a 0xc8bd3911 0xd95d20c8 0xfe483aa8
- 0xbad0ea2f 0x3a443ce8 0x3857d9f0 0x4516097c
- 0x98d96ee3 0x11529725 0x85c93890 0x47461181
- 0xf6fbe21d 0xda939a92 0x1bf3d3d2 0xf5385362
- 0x31937784 0xa7b86d9e 0x42bbf80b 0xaa3c390a
- 0xf4b7d5bf 0xb1c43ae7 0x59efcce8 0xb69885db
- 0x2a6ff378 0x20f6ecb3 0x5cd55e2b 0xcb345f54
- 0x6ff1d8c8 0xa6766f2a 0x80b3f21e 0xb69aa081
- 0x7b685d4b 0x2b84356d 0xc8f7c968 0xdd9582cb
- 0x2ae3329d 0x2884e0a1 0xcfba6d58 0xe80ffa06
- 0x1d9e8104 0xb1cb5fdd 0xdff34ce8 0xa3d46b2d
- 0x229a693e 0x02c1ffad 0xb52810d7 0x94a5f91f
- 0xb2410f87 0xb827abdf 0xd608ca6f 0xb1091e4d
- 0x75b7eb78 0xc40d51ea 0xe8c64259 0xa2b38060
- 0xd3284d20 0xc7bcf1f7 0x380b300b 0x469fd0aa
- 0x39f0e4a8 0x58b56c61 0xe42a3c3e 0x95afbad6
- 0xd989f15c 0x12f9d899 0xaa41188b 0x5ef0a7dd
- 0xe50d22a6 0xceda0b9e 0x53e0fd62 0x4f974e41
- 0x78684102 0x743bc6aa 0x973a47ff 0x48a09dfd
- 0x815546e1 0x346ef0a9 0xd8b9f0d9 0x1f990a29
- 0x1cb7cda3 0x93b243b5 0x081298b4 0x8b1c0520
- 0x6740563f 0xad1275bb 0x82aeb54c 0xcedb023e
- 0xfa9275e3 0xac1918df 0x395ffc44 0xe52017e0
- 0x9b88236b 0x47229fe7 0xafe00678 0x1b506855
- 0x6cd90e68 0xee6332a0 0x806910a8 0xf42b4856
- 0x99ba5340 0x8a0f68d6 0x7a7442e0 0x01f543b9
- 0xd3ae2a29 0x82006e7f 0x84f3c581 0x945c25c6
- 0x08ebe7a0 0xa544b292 0xa828419b 0x17363dec
- 0xf772131d 0x59edff26 0xd05d94c9 0x86f00bb9
- 0x45ce081c 0x25916c63 0xbc881029 0xa52c11da
- 0x846b2a91 0x5802a2cf 0x4a8de481 0x2b418464
- 0xfc6c04ee 0xf23c0f6c 0xc470aa16 0x5f168faa
- 0x544e44ed 0x66e02d1d 0xe4316d32 0x5faa049a
- 0xa3b599c1 0x1712d5c0 0x22c049f6 0x0dcf6498
- 0x59d976ff 0x5729d27b 0x20667d36 0x5e94eb1b
- 0xfe9f912a 0x5b31c8d7 0x96754466 0xb5b7387f
- 0xe6557f48 0xc095086b 0x1876dd38 0xbe3bd213
- 0x2a956ef8 0x59cde6dc 0x79ef6f14 0xd479ac9c
- 0x4fb12aa6 0x1773ac27 0xc99a79b7 0x88319c2e
- 0x017171b0 0xe9322144 0x89ad5ffa 0x66bce095
- 0xe7feea4a 0x67457e06 0x4c85a956 0x91eeaf30
- 0x8e9a3fb3 0x04029d73 0x831daebb 0x15105d48
- 0x855d539b 0xe041b09a 0x64d2d1bb 0x3c3249f1
- 0x9e601a46 0xf6c06195 0x9304a550 0x07ba1e54
- 0xe0e41cbc 0x686ba561 0x92a1174e 0x8dae719e
- 0x7363732a 0xe31c5716 0x75ea27ac 0x20dce24b
- 0xcdd0cb3a 0x7510e7dc 0x6b438775 0x7dc88707
- 0x097883a8 0x9a0653ba 0xa5b58b39 0xb4dffe70
- 0x3dbf5354 0x1296bec8 0x6afea6f7 0x5a396962
- 0x44c59723 0x00197649 0x88476700 0xcebb0206
- 0xc6cb5364 0x01ab08a9 0xefc19a10 0x98b3dbb7
- 0x79290d1f 0xeeb1cee1 0x155d3eb0 0x0d1ad333
- 0xbecbaf44 0xcb494c9e 0xfaba7d92 0x8f0a38d2
- 0xd71aadd7 0x96898e98 0xfae22e00 0x5cdf8ce9
- 0xec12989e 0xc0e235d6 0x35ffad3b 0x0607e758
- 0x146c87c7 0xd441c093 0x94ba23ed 0xf9029146
- 0xb2a55678 0xd9575a72 0xc8d977ea 0x3e4ee1e9
- 0x929514f0 0x947b0b81 0x7659a020 0x1e889477
- 0x47fc8fc3 0xba26006b 0x11ba9b5a 0x296ee7c0
- 0xb9625907 0xce20ae26 0xab5c4ffd 0xc8fb7bdb
- 0x09b94a92 0x96955d13 0xcc165a1c 0x59774853
- 0xd033d21c 0xfcb748fe 0xcca14a49 0xf7c3bddb
- 0x1699d641 0x5a7df26f 0x800db96f 0x3f06e996
- 0x32cb5eec 0xcfed09a3 0x590f6e50 0xe0de426a
- 0x8818035d 0x3e864da1 0x9915f5a5 0x0c9f0e01
- 0xc039e81e 0xbd41702e 0xedeb91f3 0x58bb813e
- 0x58d88d4f 0xcc9aebb9 0x1f16b1f6 0x20289a23
- 0xfc74f52d 0xf76141fe 0xefeea38e 0xb264ab37
- 0x5761d199 0xa615c301 0x854a2586 0xece5890d
- 0x25687347 0xdd5b00cf 0xdc380b09 0x3679f957
- 0x8d28f162 0x8d192079 0xc5018575 0x84e7dc2b
- 0x6801ba12 0x0ff46ee9 0x05977f7a 0x2804d141
- 0x2d66aef1 0x12b96d1e 0xbd0fee36 0xeb61eb3e
- 0x3bfadea6 0xecc451ad 0x6a7c496d 0xa9df4093
- 0xba53eb3b 0x6fc140f0 0xa10e0b45 0x7177ac62
- 0xcf5fb075 0xf15384d3 0xe76956d2 0x6bfe3cd0
- 0xd4c176b1 0x7b83caa4 0x6fcb1c28 0x7013d243
- 0x8303b45f 0x77217eec 0x5f04b4cf 0xed77af47
- 0x4ee8c05b 0x84d50949 0x4af30115 0x6536adfa
- 0xe3460043 0x42d089f5 0x6e7b3b0a 0xa33f554f
- 0xb2f9a7f4 0x8b1ee0d4 0x75b77494 0x5084f874
- 0xd12a5561 0xe22cc792 0xc5b37ca4 0xd3325f7f
- 0x941da42e 0x5f3faf13 0x4d328409 0x2efe01d3
- 0x54742b4e 0xd07c956a 0x57f65956 0x6c1af66e
- 0xe0a2f710 0xe90fc5fb 0xaabb9038 0xb1b78f53
- 0x2235d7ef 0x5421ca3d 0xc2d423e7 0x0d44fe4f
- 0xcb104bc7 0xc68e796d 0xc9f45636 0xd019c30a
- 0x14bdaf28 0x8c1a1651 0x90ab3551 0x9f19da7d
- 0x9b987a22 0x8d49388b 0x89c83ae3 0xafa42208
- 0xf29b54a3 0x83bc5cbe 0xe250c960 0x2c902a21
- 0x057042d0 0x6cfce181 0xca9a5abc 0x43739c7b
- 0xdcaa30b7 0x658f0a5f 0xfc3a3524 0xf1d40104
- 0x611b0e9b 0xf50e2887 0x0fd173f1 0xa0e9597e
- 0xd70ca0e4 0x66657238 0x4c6b155d 0x46021c60
- 0xf6abb98a 0x8b8eca83 0x63a6b1c6 0x000761db
- 0xb9280399 0x68593f55 0x7515caff 0x2c50e58e
- 0x512cab6d 0xebe2dd7d 0xe627fe0f 0x1c85dc4b
- 0x867a14e9 0x5052f8d0 0x8c4bfb3b 0x77047e84
- 0x650c4f5a 0x8f28e68f 0xe50223bb 0xd38f07d5
- 0x1924055d 0x0a89a801 0x9ebb9896 0xd4c7c7e0
- 0x6edea478 0x74ec0a2a 0x4d70ace1 0x1f57c098
- 0x9acae446 0x2d695902 0x0b7b67bb 0xf2c1cd8d
- 0x9d999240 0x02916fc1 0x9eb6f334 0xe7b45cc4
- 0x1155b93b 0x8a101032 0x71a1014b 0xf01bb4e8
- 0x04a38871 0x57d7d947 0xa7b9d28b 0x3f7969d0
- 0x3aca24a4 0xf9d4c499 0x2220fe8b 0x94b1f831
- 0x42f919fa 0x68bed324 0x15a50bdc 0xe29db9d4
- 0x7fb44468 0x3d82d179 0x4736a849 0xc04dbc09
- 0x797c4eba 0x7a6e09e6 0x3704f556 0xe0200cd1
- 0xc52dd55a 0xc80971f0 0xe6c01cfb 0x8057e7bb
- 0xd36b505e 0x85d81001 0x569f284b 0xf44d32cd
- 0x8b6860e5 0xa65bcde5 0xe55c743a 0x9a8a1caa
- 0xd3f91d2b 0xb27506e9 0x82316358 0xbe864575
- 0x809bb916 0xc978bc53 0x4725378d 0x30e50762
- 0x67586f24 0x01a9fcb6 0xe9f6c5b9 0x19719844
- 0x9fb9fad4 0x08c4b450 0x4a45b9ac 0x3048f27b
- 0x077c4a30 0x4aea9304 0x3b2a2216 0x3cf58019
- 0x84f1cf20 0xca0eb68e 0x50775bc5 0xd1f7aea7
- 0x8ae46127 0x54edb313 0xf845afb0 0x61f398d3
- 0xf536b987 0x0b9e6912 0xdb2f264e 0x78e46fdb
- 0x41fbda89 0xf03fe81f 0x187c1ef1 0x17bc721b
- 0x41cf8c8b 0x9b011fb1 0x1aeb5155 0xd0a0fefa
- 0x6751ef85 0xd5d88dc7 0x10825111 0xfc087529
- 0xe33dffad 0x6e82678f 0x50cb45b1 0xd5cc582b
- 0x5df4b1f5 0x6f4f0276 0xcd6aecb6 0x80c6602b
- 0xaf862a20 0x882518ae 0x69fbcf16 0xf3e38188
- 0xa7b35576 0xe40eb7b7 0x879a2088 0x55944f95
- 0xcf7672f2 0xc4541a5c 0x6e09ad3a 0x38075dfd
- 0x2ed6c693 0xc4fa0139 0x671c3821 0x038d5dc5
- 0x09793c52 0xb6a931be 0x453d79e9 0xecd6cd11
- 0x960f0fae 0x7649359f 0x19766e8f 0x4a7fb57d
- 0xb18746cb 0x8c3f492e 0xb91a220a 0xaa889e36
- 0x246cb452 0xa7f61e5f 0xf9fb9e07 0xef7c0d56
- 0x4f8d0024 0x082dd2a2 0xa8c091f1 0xd7466121
- 0x10c79d8a 0x3300740b 0x6d1f3780 0xf60f731c
- 0xf2d58803 0x6a80b882 0xd5d9c4fa 0x3dfc9be7
- 0x9dfe48fb 0xed7e7e88 0xcdd5dbdc 0x485b67d4
- 0xd19f715f 0xce7d6a99 0xed483597 0x2f0eb52b
- 0x7546c358 0x54f1cbcc 0x5df93879 0x79693708
- 0x8eba40f1 0x8f705e5c 0xd1154fc1 0x9f99ac65
- 0xb92d1d22 0x07c98e9a 0x21a14255 0x78c68738
- 0x7cd994da 0xbad78e73 0x463d5997 0x83a71109
- 0x53bb8986 0x15bd8dc5 0x7e1f1998 0xa8c5391b
- 0xc5abc962 0xd9a0bd54 0x48f64292 0x77410557
- 0x09db7193 0xf835577c 0xfd0f32fd 0x578d5fe4
- 0x198232a3 0x5e332aa4 0xce6b2647 0xeabc740e
- 0xf8e545ba 0xcd7d6c42 0x2776f043 0x3f0486c9
- 0xeea7d9b9 0x6773671d 0x08043447 0x290896a7
- 0xe5d05e2d 0x1701dd00 0xe2ac31a2 0xc7a96166
- 0xaff6d0c2 0xfd73837f 0x0bd95906 0xdbbbd03e
- 0x93406214 0x8e4827ef 0x67c7af4b 0x2e83eefb
- 0xac7857ea 0x6a3705ba 0x0e6694ad 0x5b7cf57b
- 0x12b302ab 0xe302c65a 0xb86a70e4 0x558c3c3b
- 0x516b9e0e 0x14a404ac 0xc2125bf6 0x7b004a59
- 0x65781699 0xb455f1c2 0x1f1f7b0c 0x800225a8
- 0x382ec77a 0x31f3d8ee 0xeedbcabd 0x6b95ea73
- 0x7a3a3f50 0x49b810d1 0xb682073c 0x36971f10
- 0x10eec5e1 0x9b9354cf 0x220dc62a 0x0f901007
- 0x204baa07 0x8b028c1e 0x7e4fff42 0x19123ff4
- 0x0219d4f0 0xfd355ae0 0x82e8c025 0x04daa19d
- 0x1d65eb84 0x282aa6ae 0x40dbee56 0x906b6b46
- 0xe1112280 0x031a9dcb 0x61dd8e8c 0x42504f64
- 0x1cb256d9 0x569448f3 0x9ed09cc2 0x52cffe5d
- 0xa0d21264 0xad756a66 0x42743067 0xbc6a7470
- 0x3950b8e6 0x62a4ec00 0x1743a299 0x659adbca
- 0x7206b852 0x156b6cf0 0xa54cca90 0xd4f789b8
- 0x177e7e86 0x6b19f13e 0xd7fadfd1 0x68ef1abc
- 0xbad802eb 0x3802a623 0x43b08974 0x23bc8939
- 0x8ee2bb67 0xbdc11c8e 0x2efbf4e3 0xc550bd4f
- 0xfb7e6923 0x9fd78d20 0x0238fc36 0xa733dd00
- 0x1ae532d2 0x83f4e497 0xca0f4cdd 0x3b204df2
- 0x0d5084f2 0x15da2f6a 0x904b1dc3 0x7418ce5e
- 0x28258fee 0xbc0292b7 0xf2002944 0x73720375
- 0x2486734c 0x1883172b 0xe1dda0b6 0x8e1ead82
- 0x18e47d65 0x9b8178a1 0x0251a0af 0x5a8577c3
- 0x1c5ce32f 0x0220633e 0xc90c9de8 0xe63cc5b7
- 0x7f334c91 0xfe0e70da 0x0af05ce6 0x8506f70d
- 0x52ee885c 0x1c723bd5 0xc547fa0b 0xeaf183de
- 0x5bf6e086 0x436d2b8e 0x3d7ad97e 0x9b766a06
- 0x021e0e79 0xdd17bae6 0x04607ea8 0xb8d174a6
- 0xc3b99816 0x9f2bf1fd 0x6521b1c9 0xc6373e8f
- 0x9c472d66 0xa71f624a 0x14af923d 0x52266735
- 0xa0a0bb3e 0xba8d52d2 0x54c78a14 0x4dd0708f
- 0x190c6c33 0xbfcc1963 0x3ed502c8 0x0766a192
- 0xe1724557 0x32271339 0x6078e163 0x8de0c570
- 0xd8e8dd17 0xce6b4b31 0xb341a175 0x8b8da109
- 0x557dbde6 0x4863ddc1 0xd345fd2d 0xbe39b49f
- 0x0b46caa9 0x572a2334 0x67d7e89e 0x658e947b
- 0x6afe994a 0x17bd769e 0x054b5949 0x850db30c
- 0x20ac6bb6 0x50480eb7 0xe06ebba0 0xacb7497f
- 0x1dadb5c5 0x4d33366e 0x8559d54a 0x7cce6ef5
- 0xfffed33f 0x7695b9c7 0xbec2d062 0x92a1c084
- 0xe0220148 0xfef08bee 0xc3ee1787 0xbe7151b6
- 0x86c8e888 0x4cae3d51 0xbeb8686a 0xa4b252b9
- 0x54d8cfd3 0x8d38b0a7 0x2f8051f8 0xeb3e0808
- 0x7bd6ef4a 0x6d3850d0 0x718b796e 0x20aa1cda
- 0x0a2ae34a 0x1f786b4d 0x1ef65ce3 0x5a710df0
- 0x618056a7 0x1863794c 0xb98ee235 0x9627fafe
- 0x48c9dc0d 0x33a09717 0xc985c1e1 0x0dcd0297
- 0xd8559f14 0x0925fff7 0x1ec6e43b 0xeabd0343
- 0xdf224c30 0x1560e2d0 0x11072a5e 0x5439abec
- 0x68539ad2 0x7e220044 0x8a1285a6 0x1728d4a5
- 0xf9d7cce1 0x6797757d 0x65c9101e 0x6e40134a
- 0x2a3bf252 0x5859d1c3 0xd42d7037 0xe519f182
- 0xa52ca09f 0xa4b8a207 0x3e2c5afa 0xa2dd1581
- 0xfc43c1a6 0xc10737bf 0xc3196027 0xdbae602c
- 0xa8b8bb9d 0xd092e4ae 0xd08b558f 0x41b0c1e1
- 0x6523934c 0x2c339d81 0x903f234e 0xb24cdff6
- 0x98e056ff 0x7f3d915a 0x87d1fa96 0xfbf87d09
- 0x9543241e 0x5d7df767 0x81082a30 0x206e5ca0
- 0x3c78dd55 0x3c4ef16f 0x0cdcda86 0x41b65308
- 0x04001fd9 0x51647a1b 0xd0eba6a6 0xea5b6d04
- 0xe6040387 0x0d8bb27e 0x68cf3432 0xd05a4c2d
- 0x23c1f2b6 0x17241b34 0xebb1ca9a 0xf37a448d
- 0xece67298 0x0487a8e5 0xfcb0bcef 0x31be2771
- 0x82bce53c 0x85b84892 0xdabc1c6e 0xfa2abcdd
- 0xd1df67c0 0x16f1ede8 0xff1a16b7 0x0d8c5570
- 0x51fbe82b 0x8bbb72cc 0x2329bada 0x3085b33c
- 0xb57804b1 0xb0e794b0 0x15c12782 0x607ef889
- 0x0f812dee 0xf4cd98ef 0xb952b6f0 0x5a58331d
- 0x5ec46323 0x125057ea 0x622c0ff6 0x883106d2
- 0xfb3dffea 0xdc3e0223 0xa97ab5da 0x654600ad
- 0x933167a6 0x374ed2a9 0x937eb718 0xd9501125
- 0x1ab096d8 0x7c9e0cbc 0xe4977ce0 0xc5f10f9d
- 0x34d150bb 0x964e8a96 0x45ca9ad2 0x4682d4cc
- 0x1a547f3f 0x48fca7f6 0xd7bcc4a6 0xd97d99ae
- 0xd8f0abc1 0x66cc1dc0 0x97db316e 0x8a382cab
- 0xbfbd6c74 0xa48d1b1c 0x2699542e 0xfd497691
- 0xface9d1f 0xb9efda89 0x4bbd1fc2 0x92f8afc1
- 0x43b37edd 0x6dde4632 0x3919ef3b 0x895378e1
- 0x87bef27b 0xf411bf33 0x656ba5fe 0x8b265339
- 0x50901749 0x3bde1f64 0xd6ca273f 0x896cbaf0
- 0x94122826 0x34ea9bf5 0x15d3043b 0xf332ff70
- 0x2b95d76e 0x57a79ba3 0x71c1f063 0xe71fc35b
- 0x8f07ee43 0x048ac612 0x65aac513 0x68ea6eb7
- 0xf730ded5 0x4402fb34 0x70ac795c 0x69800516
- 0xb1b869f3 0x6f4bbd00 0xe7447778 0xa36497f4
- 0x1c59ed09 0xb2992d4a 0x93c6a1d3 0x11d3ce10
- 0xdef0a673 0xe86e3d99 0xf1468e25 0xb272fd13
- 0xd407426f 0x95497062 0xcad1dae1 0x5a483a78
- 0x0bdb41a5 0x2899f32b 0xbb8bac96 0x5003c23b
- 0xf88ffbad 0xf4155bd2 0x4dea88df 0x5507bfac
- 0x86bd066f 0x7c993d88 0x89ad6efa 0x2dc99462
- 0x8d634a1d 0xebd312d7 0xfc8a8549 0x26f6cc24
- 0xdfc6c501 0x9615c1c4 0xa48293ef 0x52aa4e4d
- 0x7c1126b1 0xed10ce8f 0x39d15759 0xf6dd7f71
- 0x2f4d86f5 0x151da4d4 0xd9175dd4 0xb2d20142
- 0x20fe7518 0xf35752a8 0x37ae7efc 0xc210d83a
- 0x5d9ff559 0x33e91d21 0xd1c7714d 0xa98c7599
- 0x8ee50ccd 0xc747a3b1 0x9dbc5317 0xc25ae129
- 0x51b3647e 0x25aa4406 0x6e123b35 0xcc8fe12f
- 0xdf9c6d92 0xff1e6b44 0xc294d3cf 0x458dbe77
- 0x8176b64a 0x4daa895b 0x5ecc9d75 0x1b570965
- 0xd563bbb7 0x297b9784 0x4129fd5b 0x77beeb2d
- 0x82bab257 0xca55d798 0x4d413dfa 0x27214528
- 0x918d94a4 0xe9dc1881 0x17a00e62 0xff38fe70
- 0xf0578886 0x99fc567e 0x89728e9e 0x267a192e
- 0x5e16982a 0x5da1f959 0x3c407435 0x9c5cfe85
- 0xa7626913 0xb1145c57 0x174daaa8 0x0487ef1a
- 0x11d7b896 0xcd48cce8 0x464ceff1 0xbdc0f36b
- 0xffdc957b 0xb94233f9 0x61dd9f4b 0xfbc1fe7c
- 0x45f0195e 0xd7c92251 0x6c4ba5b1 0xc780a5a0
- 0xe8fc9220 0xa7ca21ed 0xa82eab05 0xd6050a60
- 0x68bf3f0e 0x50214ae8 0xb83e6b76 0xa435330c
- 0xefe62d27 0xd3b40484 0xe96a563c 0xc93296b2
- 0xd1531895 0x5db76e04 0x491b827a 0xf160fcf4
- 0x4b82737c 0x3c72de73 0x1996e649 0xd2d79c59
- 0xb1263519 0xb8660e24 0x4b07996d 0x71df252d
- 0x58f95a70 0x8618a823 0x94239726 0xd6d92a80
- 0xd8142a6b 0xc98c3175 0xfaa52b59 0xe91fdee1
- 0xd9a1fbff 0x8d63a59a 0xe0bd9077 0xbb1cddda
- 0xad57fea1 0x32af0614 0xea652e8d 0xa02ef7b3
- 0x07440720 0xbac50654 0x5e32309d 0x444a9d5b
- 0x9c5d9ff4 0x6b0ef745 0x248f1f75 0x7d87e2e8
- 0x27490681 0xfc2a7b49 0xd81d2e73 0x76b09294
- 0x4512b27e 0xcd72c2f1 0x41d3ba4f 0xc752688d
- 0xc22a2077 0x45a01ca2 0x82b5ba56 0x9f12c039
- 0x44cc1b0f 0xe8b8353d 0x0c26d80b 0xe54b917e
- 0x62df727e 0xfce091be 0x79ca5f3c 0xec222126
- 0x4df04d01 0xcd7566d0 0x839eb434 0x9b6d3415
- 0x61fda637 0x3549727b 0x44117109 0x9d1c3ed2
- 0x2c3cfce8 0x2e2acd9d 0x4ba9129d 0xbe14efef
- 0x5d07e000 0x2081f339 0x1daf0bc2 0x74d098c3
- 0x301e59a7 0xfd696b42 0xfc4d3387 0xa5c09d3c
- 0xf8b0e4d8 0xadd63e51 0x5815b319 0xec7e8516
- 0xc8d93178 0xdf1b9e1d 0x22107d46 0xa3a99acb
- 0xfffc3859 0xd00561d4 0xb383323f 0xf6b7033a
- 0x90f781a0 0xf5f2ce72 0x6eb3fdf3 0x8cc20a5b
- 0xc97c9c66 0x95135ade 0x24880471 0x9bb65b03
- 0x81b19c7f 0x700d0f5d 0xd13737b5 0x6607133b
- 0xfbe4e7d6 0x3c4f45fe 0xfd6782c1 0x93aa0e29
- 0x5e80ece2 0x16609c87 0x238ba834 0x1ddda4b4
- 0x6d07bef6 0x23422da6 0x034a0e64 0x9fbd2d4d
- 0x29f9bf71 0x009ca5a7 0xf483d433 0xcc5b600b
- 0x6bc292eb 0xbbec5d01 0x3e45ed47 0x1f19013c
- 0x9beb22ac 0xab5e821e 0xa1430d82 0xd88d6684
- 0xf8e70a20 0x4e267714 0x32740299 0xc87b9d0d
- 0x61e7c75a 0x967f007c 0xe1f93f4c 0x11a1c3a5
- 0xbbee7b5f 0xd1ef645f 0x141aba51 0x70694200
- 0x71945636 0xc9dde72f 0xc5955db8 0xdbef5230
- 0xbd17479b 0x53159bd5 0x0878bdc2 0x9fdd9d07
- 0xaf67a519 0xadca8377 0x13841851 0x97f464f6
- 0xea749381 0x47018b36 0x42cfffdb 0x2366f112
- 0xe280757d 0x7426dc87 0xcd5252bc 0xe5bdda7d
- 0xc9728a8e 0x8e08cd82 0x66797c08 0xe1600e06
- 0x149121b9 0xf9ea0e1b 0xc3da0d90 0xde18b684
- 0x0c568801 0x58e83138 0xfe3fe553 0xc52b4e60
- 0xb6afb01c 0x9154fba6 0xddabb2f2 0x018eaeac
- 0x7c9640d4 0x9c7c86dc 0x41b8d514 0x8bd27333
- 0xf07f842e 0xb75e7858 0x990187d3 0x316ef3a6
- 0xfaf22ada 0x95356100 0xd0ed3ad6 0x3d9951bd
- 0xd4aa1b22 0xf3a6ad11 0x797f6e48 0xb2428538
- 0x91466c20 0xf17569d0 0x62d5d1b3 0x5a3d69e4
- 0x6d869d97 0x82a84e5d 0xf6a45cdd 0x8781c19a
- 0x0dac70b8 0xe79a4712 0x4617b8c0 0x3167f846
- 0x9c6e7b77 0xc60b0e08 0xd85879c1 0x2be3a597
- 0x06a6daf1 0x80915697 0xa3452bde 0x9cfd11d6
- 0x69be41f8 0xebcadb24 0x315dcb53 0xc35f3e59
- 0xd5b2edf3 0x443859d5 0x7d54f6a5 0xdcdac118
- 0xe767ecbd 0xd017fb76 0xd0e7b4eb 0x8d9bb8f4
- 0xce7b7d9a 0x92c0b4a2 0xcd5d8e1b 0x6f83d592
- 0xc17f2b68 0x2cdab9c7 0xb6e70484 0xe5fe74c6
- 0xe87747d2 0x228d5a4e 0x9dde03e2 0x9a14ba34
- 0x471229ca 0x69be2353 0x74450c0a 0xd1eb650d
- 0x78501400 0x1c4f2372 0x1fa1b6fb 0xaae57238
- 0xd724663b 0x05f5c43f 0x402bc254 0x68877f3a
- 0x57e6c691 0x0a51ef53 0xb65a2733 0x57431f71
- 0xceb73088 0x03c761af 0xb4542581 0x23933fee
- 0x4d726fc8 0xe6474d89 0x4816a760 0x97f68d6e
- 0xb892a46f 0x1fffcbc0 0x63f9c6a2 0x19ec45f7
- 0xad0f5d1a 0xe1436104 0x02db0bbf 0xa88a4df2
- 0xca060341 0x7bef4581 0xbbfae170 0xedf98d3a
- 0xc3972d10 0xce08a7a5 0xf2554832 0xb22c4280
- 0xf51295a7 0xaafe76f2 0x0503afd6 0xadc0191f
- 0xf788a6a8 0x32dde44d 0x2e148322 0xe4f4dd86
- 0xa8012f5f 0x68950d8e 0x40ba9fb7 0xeff278cb
- 0xf1f29ebb 0x5f273270 0x54db6ab6 0x032c76d6
- 0x28b7a8ba 0xe06ee4ec 0x95b4c36f 0xf895a4bd
- 0x6e886a7b 0x29ca6362 0x5ab44a12 0x122b4b0b
- 0x77542b75 0x4254355b 0x8ba85616 0x78f02722
- 0xad2c32f4 0x7a8b56be 0xda66fe2b 0x1018c515
- 0x8e963b24 0x492cd4fa 0x8e8daa8b 0xbbf9a920
- 0x5e1c170b 0x5b55acbc 0x96a08ca9 0x87628e01
- 0x7daf9cde 0x402b7363 0x704db5b5 0x4ed3e581
- 0x0b76bc99 0xee629701 0x976cfef1 0x222eb820
- 0x1eae4155 0xce2c39a0 0xfc80e3ff 0x46604921
- 0xa6411e39 0xc64f34d4 0xc2506d0d 0x9175c98e
- 0x2b41e939 0x9f612788 0xe84717b2 0xdd5f3d18
- 0x011ccf8c 0xd47c6dbc 0xc42724e4 0x4ecdb867
- 0x88c2fc65 0x7146f321 0x426ce2d0 0x21874594
- 0x94752082 0xac96eef9 0xbfaa8f43 0x4b599929
- 0xc40c67df 0xc2f88319 0x6c13b780 0x0331ddf3
- 0x03141f93 0xc8792b1d 0xa5cbe506 0x68424a36
- 0x35fe7a9b 0xc42db001 0xa2c5e600 0x2e9f8f21
- 0x7733f912 0x24b163b0 0x71003270 0xe5a5c52a
- 0xf08c8455 0x9f6b0203 0xfa048b10 0xfb2ef899
- 0xe9b81eef 0xc5d91db3 0x604bdb10 0x30a2bab3
- 0xbf75341a 0x1609bb55 0xfe4d07ec 0x0ffabee5
- 0xbfb339e1 0xb3f43c0e 0x66cd4d8e 0x752b5a86
- 0x9908cfea 0x237d4b88 0x1e4c78d1 0x41914cb7
- 0xe2d72121 0x815cc67e 0xfbf32db4 0xd4ab50c3
- 0x5b8f8ca4 0xd7f0225d 0x75662558 0xe1586c50
- 0xb9add021 0x1475644f 0x7d4d1e0f 0xb078549d
- 0x64edd4ae 0xe9aa17b1 0xe03324aa 0xad30bdda
- 0x2f27b674 0xf65879fa 0x5b5d7360 0x75905386
- 0xc2ecd3f8 0x373566df 0xb7de23e1 0x91805774
- 0x86162380 0x449b798d 0xaaaa35b5 0x0c72c757
- 0xda4f445f 0xa83096b7 0x86002daf 0x7749832b
- 0xf3a61bab 0x5feb28a1 0x26ee7610 0x5a5c40b6
- 0x42c9ee14 0xc4dbb8b6 0x1f67936a 0xe1b56bbe
- 0xe027f6b9 0xe63fb059 0xc88bc732 0x3111de49
- 0x35c2305a 0xcbf91704 0xbd792b65 0x36de53d2
- 0xe2de429e 0xb90aad73 0xa9f473a4 0xca054a43
- 0xa984faa3 0xe8ddfb62 0xc36104c8 0x95e7e647
- 0x17437e84 0xa20c074f 0xb5609b79 0x468c3b7b
- 0xc0bc3e20 0x368c94fa 0x04ff3519 0x60b01b2e
- 0x4a3ad0b2 0x4d8b4633 0xb1dc5e67 0x7e14c0be
- 0x58a6cde6 0xc88980d9 0xb4ca1c86 0xe17c13bc
- 0x3efb7728 0xadecba18 0x369ab25f 0xcda74fec
- 0xe9c4c6aa 0x55590211 0xbe191ec5 0xed8ffbcd
- 0xea3bd84f 0xe1fde7c5 0x5c788a9f 0x31a7b858
- 0xd65315a8 0x62be6ed6 0x04b8be91 0x73548a2f
- 0x93f9cbe6 0xcae8695c 0xea678c66 0x618251bf
- 0xbe8920fc 0xf4f76833 0x15ad8be7 0x5ccf9cb0
- 0x8d6a4fb9 0xe1a946c0 0x00fe7631 0x6abf0c2a
- 0x72fbb39d 0x72bd5bac 0x7d679c95 0xaa5ccef7
- 0x6df60938 0x9f08de64 0xb13afd73 0x61e2cc19
- 0x31485e10 0x2e125f53 0x74021ab6 0x43fd53f4
- 0xe506757a 0x454bd201 0x84947916 0xc89e453b
- 0xa92324cd 0x3667608a 0x28e2645f 0x17e1f1ad
- 0xa300d261 0xc9662fd3 0x987795f5 0xad6c0302
- 0x55d47cc3 0xe96259cd 0x0d67ce7d 0x07bccb37
- 0xf43d61a5 0xbd7131a5 0x686bdc7f 0xd570d5e4
- 0x9ff9331a 0xac9d1d6e 0xa1702a68 0x4a5775b9
- 0xa5624641 0xf65bd241 0x2ac16f90 0xe3413b5a
- 0x17ffa019 0x9d46dc7a 0x2a3081b6 0x857ce29e
- 0xe6640ac4 0x6445b538 0xad3d7e1c 0x9b79c366
- 0xf462361f 0xd1097ef6 0xca1c68f6 0xb5f30167
- 0xc14a23d8 0xc10dcd22 0x2a2fc332 0xfb253533
- 0x65fdf0b5 0x404b7ad8 0xa9ba6f4d 0xaba569c0
- 0xbaa52473 0x0e4627a8 0xc5f59463 0x362e6c4e
- 0x4b2a486d 0x0259c34b 0x28c473f1 0x503bb776
- 0xc5c0c537 0xa8b225c1 0xeea3c262 0x576dd495
- 0x571ada41 0x9f7cd0c7 0xd7496acd 0x05feea00
- 0x41201b9e 0xc77a94fc 0xe9bbcdcb 0x57b23f11
- 0x0804834e 0xd03b6bc7 0x01010b7e 0x1398ab11
- 0x16c14655 0x3c6e5e32 0x420bcbd9 0x8047a032
- 0xf70c4e5e 0x2a3e76ac 0xedd3223c 0xbbba8d71
- 0xba2a9916 0x1b83f930 0x4c93f25b 0x79731cc9
- 0x77925eaa 0xb2fee6dd 0x01f12a1b 0xd797d09f
- 0x1d63619b 0x2b04daaf 0xcaa55fcd 0xc4628c52
- 0x930f5701 0x0293b2d8 0x00e82920 0x3c4f3f60
- 0x6c0990ea 0xec07864f 0xfd650432 0x5bdb68df
- 0x9d138863 0x2a06928c 0xe0f69d3e 0x5310dae5
- 0x5bd2c0a7 0x775d764f 0xd8aadd14 0x20ba7850
- 0x358aabd2 0x192ce2f0 0xfe029fcb 0x9a787089
- 0x032bd81a 0x2033745b 0x11b36de7 0x38e63443
- 0x26a6a138 0xfe1b4cf0 0x8e8c2e54 0xd8d68982
- 0x1f8bfd73 0x11132e4d 0x217497b3 0xa882ae2a
- 0x895350e6 0x58042447 0x027e3513 0x9b23ecfd
- 0x0368bfc8 0x1f2bb5be 0xe81d1738 0x69176a5d
- 0xb4e0531d 0xc899b145 0x9fd09aef 0xabf6b854
- 0x2f1856dc 0x4186e028 0x02aab53b 0x0231c01f
- 0x543d0d94 0xbc207922 0xef61da69 0xe1056724
- 0x67fd8072 0xc98426e2 0xc7635142 0xff184885
- 0x653f91f3 0x1ab5cd1d 0x133df7d9 0x67b35000
- 0xb5880c56 0x21e4c4b3 0x6773270c 0x1c30a75d
- 0x360b8cbd 0x0efa143e 0x025c298e 0x8bea4b71
- 0x903465e9 0x99521cf4 0x2e1857e7 0x13266774
- 0x72f6d2f6 0x36a1a4fc 0xf0e38e70 0xc9d613d7
- 0x765b045c 0x28ea90e7 0x99766fb3 0xcdb93ca8
- 0x4ef82ae9 0xfa083dbb 0x280d6bc6 0x5fa6f9f4
- 0x8232c95e 0xe899ae64 0x9757bcb7 0x7b9a3fbf
- 0x7ee59763 0x707c1e8f 0xb09b26cf 0x39b130f4
- 0x57b13cca 0x9431c3bc 0x03074f78 0x77108240
- 0x2243cf2e 0x79f1c09b 0x2d7051d7 0x1e896e0e
- 0xfca3c98a 0x033f9d17 0x8a84fa5f 0x54ef6d59
- 0xea4f038d 0x37de0f3a 0x290fdf6d 0x87a99d3f
- 0x03539027 0x423a6a72 0x1751d4ef 0x3307e618
- 0xff81f836 0xeff8f63b 0x5fd7f014 0x5d2a7e84
- 0x9bb1c22a 0xd90f6902 0x53594d40 0x2a06777c
- 0xbfb045d9 0x3a994642 0x5d3bb1c9 0x92ebe0c2
- 0x1351d163 0x1d164e51 0x646facf6 0x5a09577c
- 0x1d67f8e2 0x5857aedf 0x4325f877 0x40b104d9
- 0x417b2244 0x944a7154 0x46887db2 0x8e5c72f6
- 0xb1e4105d 0xe23955a6 0x32c458f7 0xc5b0adfc
- 0x45b48308 0xccde9154 0xa84cfc72 0xc4f67710
- 0x19a5d6c9 0x18feea83 0xf731b3f5 0xd26e63c9
- 0x3869ef48 0x70b962d6 0x5f2b4ba3 0x5dd5a9c3
- 0x1efc97a6 0x09be830d 0x791d72d3 0x53f2948a
- 0xf5bdc706 0xa5b6aeb0 0x6c35db0e 0xc312c33b
- 0x6dca7a95 0x9f890aae 0x75308dfd 0x7de2239b
- 0xf530420c 0xe085f9b7 0x2d48c359 0xa8d1fcef
- 0xcb3f9669 0xdf491f38 0xc59ffdd0 0x995cda92
- 0xdef37f3b 0xe056b574 0x676eafd4 0xd4bd9336
- 0xda3ada02 0x290cf756 0x991efdaf 0x2f70baa2
- 0x515ced1a 0xaa0fa199 0x77f09ee0 0xafc3d840
- 0x79e5ada0 0x7900a254 0x4ca65cb7 0xb3eaba8f
- 0x98cd17e0 0xe179d477 0xe80d2f39 0xd89f3b4c
- 0x8d3ca0dd 0xd1d87ab1 0xf9368d54 0xe885ded8
- 0xd500c7f7 0x04910374 0x7c6467be 0x5ad058ce
- 0x5f8885b8 0x08a4a3c9 0x90583a94 0x369f4c36
- 0xafbd90a9 0x6eec8300 0x1fd17777 0xaa8ba562
- 0x24531969 0x64eae352 0x6f7e72c5 0xca5e2247
- 0xee11333d 0x4e96b233 0xcc9c45db 0x377d9b3b
- 0xac17897f 0x8d4f2cf7 0x03786608 0x2ed70cb9
- 0xabb521fc 0x27ae8324 0x99fedf05 0xfa60f2f4
- 0x60fe2470 0xd9994193 0xce4a1f0c 0xdf803250
- 0x7773e538 0xe3461726 0x8f1fb31a 0xe20b4ba0
- 0x247a6bd0 0x33f33c29 0x0534675d 0x9df47ebd
- 0xcb86d416 0xfca6bde0 0xc2113e28 0xac64d376
- 0xd34923e0 0x128f937c 0xc74b76b6 0xb653872c
- 0x05c78e23 0x482ece1a 0x17cd4da8 0x460f5a20
- 0xa9a3676e 0x0776830a 0x9c5764a5 0x7c0bf0f2
- 0xe193d4be 0x31b71120 0x4beed8fe 0x8426bc77
- 0x9f665f9d 0x4e2b00be 0x2dd365af 0x015f5889
- 0x92bd288b 0x4bda3b7a 0xeb2b0605 0xaadc6a84
- 0xf715172f 0x1b0fdedf 0x17ccd242 0xd511eab2
- 0x75829b1c 0x0f5861b7 0x229338cb 0xcad5ac0d
- 0x95ed8bb9 0xe719c62b 0x2e50c781 0x40492cc9
- 0x7ac3e8c2 0x4881bef1 0x8359b0a8 0xd0a8713e
- 0x3808db04 0x847e12f9 0xd28ee5b2 0xc77f7a81
- 0x2e89e5ae 0x95296641 0x55f44a6a 0x22c16d11
- 0x1fa9d5ec 0x3b131a56 0x6b113976 0x057616a9
- 0xf4813132 0x003fbe23 0x082a9ff4 0xd0db4d18
- 0x84be1702 0xc9c51278 0x9f5bc62e 0x5691be5d
- 0xc12f7c79 0xa84f8dc9 0xa9b2b8db 0x0ab996e3
- 0xd25a2195 0x91584ae2 0x11e0a407 0x9faf14ef
- 0x7ecf8b2d 0x64d1b392 0x8292b54e 0xaec7c7d8
- 0xedf1eec6 0x9164a0a8 0x16132244 0x07077758
- 0x32f53095 0x8036d28b 0x5534fa23 0x66869c3f
- 0x3a503595 0x87706388 0x315540f8 0x5348f0c9
- 0xfbe7451a 0x491d7c96 0xa70ad473 0x5d7975c1
- 0xa51c99b0 0xdc0320d8 0x259a0935 0xf15dee76
- 0xb080d4bc 0x1d8611f7 0x64b6c12d 0x115bb158
- 0x1ae6f885 0x9b7bddbb 0x74107ba0 0x5ec2433f
- 0xc05198b8 0x4e3921cc 0xf866e4ee 0xdf4e5b52
- 0x93dc0bfc 0x9f5957eb 0xffebb962 0xb2845803
- 0xf16acbdf 0xda0923e7 0x2b7d8663 0xeef7ea5e
- 0x5c468035 0x1bf5eeb4 0xcf04aad0 0xa898340b
- 0x58f32310 0x6502901b 0x151e45a6 0x4e0a8176
- 0x312d5e40 0xb0a82dd9 0x7461f194 0x5d955cc7
- 0xbc26c368 0x26cc45a5 0xfff346fb 0xcdbdad82
- 0x1f0da6e7 0x6800be4d 0x931a3413 0xd471a14a
- 0x773ade46 0x525f8a29 0x416f7b22 0x75c2b0cd
- 0x5abe1934 0xbb87502d 0xb1568281 0x95c1abf6
- 0x491971cc 0xbac11423 0x0daf5cfb 0xb5e37509
- 0x2eb36341 0x1784cff3 0xdcebc5df 0xdb10122f
- 0xbbed7029 0xb7b66506 0x2b732807 0xb5524662
- 0x37c211d4 0x0730df05 0xe09e9822 0xd6910951
- 0xc6ed46f2 0xfc7d7cd6 0x8d6af74d 0x4697b13d
- 0x7959b678 0x9c67c19e 0x96686e89 0x7f973e98
- 0xe5759786 0x42ba4801 0x05416f70 0x87a85c5e
- 0x8f21af39 0xc64ce827 0xf658f857 0x3b75a282
- 0xf6813344 0x0e9adb2c 0x46ca59b3 0x2f2c4fd5
- 0x1a7ee3ef 0x1e3202ce 0xc4135b57 0x22792d11
- 0xe399a044 0x9453c580 0x639da579 0x80239655
- 0xb1b68953 0xbd677cce 0x9163a0fd 0x766c5b7e
- 0x46ed281d 0x99ec91f2 0x7db3499c 0xbf2b9793
- 0xb111887d 0x3906e075 0x9e211f1c 0x16f15768
- 0xd27474c3 0x8813b27a 0x3393ce5a 0xe73aeee6
- 0xfe056806 0xfe4bf0fa 0xe106529b 0x317d9099
- 0xd2ad43c4 0xbd618f1f 0x77d8e13f 0xd4c10bc0
- 0x30a335fe 0xd7a4b251 0x84c67582 0x1bc0723e
- 0x7a1cded2 0xf6664fce 0x2bd8c844 0x967cc741
- 0x8cb6bf8e 0xb8c49dd9 0xc167221d 0x5c65b9b7
- 0x1f32b243 0x5729b02f 0x76f22a55 0x22ef22f7
- 0xabcde168 0x273b0513 0xb8cc1b47 0xf0e378e7
- 0xc3e189b3 0x344090c4 0x3cac2fc3 0x2a06749a
- 0xb026617d 0x26bbe774 0xb15d08d3 0x6b29e7ed
- 0x34b5145f 0x740f6f69 0x7edb95a3 0xf55df95f
- 0x25061c1e 0x45192d2e 0xdef6bb9a 0x5538188a
- 0x2f7ff744 0x6592e57e 0xdfc302eb 0x8564f70a
- 0x81f22fc6 0x1ed3f7b7 0x3eb74e98 0x84ff649b
- 0x40535223 0xa81996a5 0xb30b0b97 0x9ca701de
- 0x45bd91f2 0x07e94e32 0xb2f60f7f 0xc3d68aec
- 0x2296450f 0x31567179 0x5fa15060 0x6ade7193
- 0x7ca6e320 0xb231f34c 0x1e392751 0x3fb50014
- 0xff632467 0xff33f75b 0x65f2dcdf 0xfa464ff7
- 0x1ffd17ab 0x34c38154 0x72906efc 0x2f649bd5
- 0x5349c835 0x6c83e7da 0x9e0ff921 0xf2ad6dd4
- 0x5afa8581 0x2d6deedc 0xf582ce84 0xda7ddfa8
- 0x6485db26 0x874585e9 0x13bbb0a1 0x4283bb8d
- 0x1648cc58 0x69fae5da 0xa5d7bc2c 0xd7fce256
- 0xc2e25ab7 0x7ec604af 0x1efde306 0x36422ec5
- 0x78e9bd5d 0xbfa63459 0x052efdbd 0xfbc9d2eb
- 0xd8b729ee 0x888dfd1b 0xb64a687f 0x9ebd05b2
- 0x622c28ed 0x3801fff8 0x476285e1 0x262e5f3d
- 0xd6ba77c4 0x8d5663fe 0x4b9bb3c5 0x1909dfb2
- 0x40db7079 0x2799a10d 0x1e2e55a7 0xe597551f
- 0x4d38f913 0x972b1b35 0x92f77eb6 0xb2dcdb5e
- 0xe275428e 0x0f136b53 0x321b55ba 0x70f7edf1
- 0xc41fe047 0x332e9ff5 0x3c372115 0x2ea1c88d
- 0x3ea09444 0xe93066a0 0x666670f5 0xee9553d0
- 0xa817ee82 0xde3fd981 0xf6c5b2b7 0xe88e3857
- 0xec60b610 0x4b0e1af7 0xceaa144f 0x0a8f8703
- 0xd7969cd7 0x0a946a3a 0xc6f77ae4 0x3805f71d
- 0xd5d56360 0xbee37cf5 0xfa524a3b 0x68ba0662
- 0xdf153cee 0x5954f21a 0x05aedb31 0x340e4963
- 0x129115db 0x271db9a2 0x70984fa6 0x7daf0407
- 0x5fcd11d1 0x750f56c1 0xf1a93401 0x3a3aca1a
- 0x8a6d152e 0x9c65e58d 0xf0afd845 0x3abef6ea
- 0xe6e1ff7e 0xf8407d49 0x45dea271 0x545631ca
- 0x73fad7df 0x21e60e47 0x3bd83fd5 0x12b4394e
- 0xba4731b1 0x786279a0 0x97c6d6ab 0x2591deb2
- 0x4b33bf75 0x772fb5bf 0xe9060fd5 0x6a752986
- 0xdf3090d4 0x9de70555 0x471c2e4d 0x5305f077
- 0xf2bdabad 0x2a4ed093 0x36e029a8 0x17b7a5b1
- 0xce75a688 0x8377b839 0x731fa872 0x63f45ed1
- 0x010bdd8c 0x4366cba1 0xd899b1b2 0x839a8a34
- 0x4914176e 0x58fec42f 0xb3ecd171 0xa88b5247
- 0xbfecbafb 0x65962301 0x7b5a7822 0x08b1056f
- 0x6f0cf6b5 0x5dbe0084 0x3280b172 0xc77913e4
- 0xa298f67e 0x2131f5c2 0xb9b9b501 0x7f30b7ef
- 0x55d8cdb6 0x3b0c0dde 0xbf9a5cb6 0x50ba39ab
- 0x0741872a 0x69217ea4 0xad4b12ca 0x14dd5da0
- 0x5d220b6b 0x9d0356b5 0x9608d36a 0xdef765ca
- 0x7d55819c 0xb57ca102 0x9f2a2c76 0x5efc9c7d
- 0x42952b33 0xc8e2749b 0x2eff7d6b 0x211caa64
- 0xec846e0c 0xf3119325 0x31bf7f1d 0x984fadb5
- 0x36670140 0x6419ae9a 0x1c206656 0x86cb7d35
- 0xbd323508 0x5f970165 0x21777792 0xc8808541
- 0xecba85e0 0x0b4b3240 0xa70d8609 0xc68913f2
- 0x67415bba 0x26af0069 0x81974b27 0x92066952
- 0x5f6aa2e7 0x0dfa50b9 0xc1e65cad 0xb93b9d66
- 0xad6c8ff8 0x8e885310 0x5f77e1eb 0x2dccb750
- 0x8f18f33a 0x6ad45207 0x921285f5 0xf3d2d3ab
- 0x1be2996f 0x9bc30897 0xc7c85614 0xce88b0ca
- 0x55a5fec7 0x0570e871 0x50cd5f3b 0xb723a9a4
- 0x8c2f6fd8 0x3a0bfcc5 0x0b75181c 0xe595e483
- 0x063a7f01 0x16984414 0x9c74253c 0xd9627dee
- 0x0b8aa93f 0xef9f3c7e 0x186719dd 0xb0311955
- 0x4ffcf417 0x519b631c 0x295cb456 0x58494234
- 0x81ebafc8 0x02002fdc 0xb28044e7 0x2682e878
- 0xb86f281b 0x108f9c77 0x99368ca5 0x24887533
- 0x37676f0e 0x71230faf 0x8e689144 0x81bbe972
- 0xc8dbab68 0xca5a3ed9 0x878d622c 0x05217a5b
- 0x7ce7e849 0x0416578f 0xc43b026a 0x86abc8bd
- 0xf0fdc5dd 0x1684665c 0xf167d783 0x00d58f21
- 0xb4929559 0x70572ce4 0xbfe6985c 0x051bdcce
- 0xa9307ffe 0x2fa9902c 0xd8f76dbc 0x6dcd4744
- 0xecb46877 0x18ac0a40 0x6f8a8064 0x66dff5e2
- 0xa55d991a 0xfcd7e70b 0xad9c7fd7 0xb77415a6
- 0x761134a9 0xa76e4079 0xe9ca8a5f 0xdb627ec1
- 0x328cd5a8 0xc3f378c6 0x7f5ae9a2 0x5a144e26
- 0xc4b778f8 0x1910215f 0x1d29a078 0x728c7575
- 0xc2017bc9 0x201a0601 0xea1e939b 0x7ed85f43
- 0x92893ace 0xb97613d5 0xa3e47eb1 0xaea2a6b7
- 0x45b4de8e 0x864e3d12 0x300eb84b 0x57246fa1
- 0xf9e50600 0xc5fb68af 0xff700271 0x4ecfe6df
- 0x195f3f4e 0x9bdcfa8b 0x1bcca506 0x0ee96e1e
- 0x4d722003 0xe6ffe15a 0xc3a392d5 0xedc4ea2f
- 0x1cc2bc4e 0xf133ded3 0x584bcee5 0x63e54048
- 0x34f57fa2 0xe606b846 0x82dece0c 0x7bc24217
- 0xf45b9ac3 0xd9949991 0xbc262aef 0x7949bbec
- 0xf37e0563 0x716bdca0 0xef533f5b 0xfa53b4e0
- 0x97365a61 0xbf4cd291 0xc69c9c3f 0xb5ddd420
- 0x92a65067 0x4a63f3ce 0xf53104a3 0x0053fca8
- 0xb8f972b1 0x7eb74704 0x2bc2ef35 0x491b520f
- 0x80f67bbe 0xd36fc91a 0x8babbc98 0xdd3aa4a7
- 0x1005ace4 0xafe0a165 0x921ee005 0x9d05e888
- 0x4e7913ee 0x43690cb8 0x634c75a1 0xf2ca1d08
- 0x6f453485 0x1a62b5f4 0x692608a8 0x76837c9a
- 0x222f6cb2 0xbc883372 0xc785ebf7 0x21b16a27
- 0x5ad7860b 0xd5fec2ec 0xa573aead 0x9c0bd90b
- 0xec3b5d8d 0x393a1263 0xd0cddd05 0x08477829
- 0xd4bb3080 0xd1580e80 0x614e8dae 0x7e789a32
- 0x273b2589 0xe5368d97 0x8db1b602 0xbd06492d
- 0x6760aca0 0xee176a78 0xce44021c 0x4d35c720
- 0xcc3d8185 0x752005a2 0xffdb4703 0xf01771b1
- 0xfccc8abf 0xadca3bbc 0x2c2a4739 0x970d0fb8
- 0xa829ca54 0xc4301da7 0xa56d3181 0x24a95701
- 0xb760d1ee 0xea87f071 0xfabc32df 0x465f142e
- 0xe0998f0c 0x6923edf6 0x3a1debda 0x3e88908d
- 0x7069f55a 0x0cd61367 0x1218e044 0x99713258
- 0xbb60c477 0xe3997857 0xc4e9ca48 0x4be6b283
- 0x1bde70e0 0xb0f3e15d 0x40cfb11c 0xbb9e0879
- 0xc4c732e7 0x2aa169d3 0xa2bff233 0xaa50e35c
- 0x2d0989e3 0x6f39a59d 0x7a7b69c5 0xe66152bb
- 0x69c74ec0 0x46ea7bc3 0x59c93af6 0x0a036f99
- 0x95698244 0xe0ca1af8 0x3565483c 0x8abcce28
- 0x6b322770 0x188e97b6 0x77874604 0x93298d36
- 0xbc4a0f5e 0xbf367940 0xf69906ef 0xf2b5975b
- 0x5968ec40 0xd0e75276 0xdf02b089 0x60b72248
- 0x32de1e9a 0xe52bb0f9 0xf4b33702 0x87b4cd47
- 0x31c86ac5 0x77106507 0x20ec46fd 0x5086dc0a
- 0xadce33fc 0x898ee47a 0x3c6f8af9 0xb4a26000
- 0x8f11d65b 0xf83d2284 0xe512bf22 0x24a7d8af
- 0x12b194cd 0xa530f50a 0x1f64f621 0x6160f047
- 0x8f223c99 0xc7e0809f 0x99312a95 0x5c729b2b
- 0x4af6e5b7 0x8c6e5da4 0x93a07403 0x89fb2a5d
- 0xeb347cfb 0x0d127850 0xc3278db5 0x456e3472
- 0x731c2b96 0x841ed8d1 0x5ed8671a 0x16814226
- 0x4cc3932a 0x556b1403 0xc8547260 0x52340a36
- 0x78b8243c 0x9ce3ac1e 0x997c64d4 0x25812f0d
- 0x5cd3b82f 0xaefcd02b 0xda85628a 0x3b9e3e2d
- 0x4780e91b 0xbb265ae9 0x4667a62e 0x7fde4743
- 0xae2d2c8a 0xbdf272d6 0x490e5bf1 0x8f764531
- 0x59a8ca61 0xc39751a0 0x9777eddb 0xc89da92e
- 0xfd46b968 0xd5383421 0x916ced6c 0x9fc14c5e
- 0x91ff992e 0xd59cd577 0xf5cdda19 0x99ed4f29
- 0xea30d84d 0x868bb72d 0xcd3e19d8 0xefba277e
- 0x9b895f2b 0xb67570ae 0x7b963bfb 0xb7f59d33
- 0xc82c0da2 0x713c0ebc 0xd2e19b6d 0xfdd7cb4f
- 0x0442a88d 0x58e2e7e8 0x7b179f2b 0x12013442
- 0xbbd1c2d1 0xc4e7d279 0xddb4cd95 0x18a254ad
- 0xb2876346 0x4bdca7ab 0x94dc9778 0xb648e703
- 0xeed00eb6 0xab02dd6b 0x3e25115d 0x45cedb33
- 0x906c2403 0x457849ca 0xfea6f2d9 0x252fb56e
- 0x2bbe39b4 0xa35c94e8 0x04952551 0xad733a12
- 0x40bf3982 0x30cb3742 0xd6c149da 0xb6d29f20
- 0x9df8b8eb 0x706065f5 0xfa915b7f 0xd2bdc0ca
- 0x0a4c462a 0x288ef8ee 0x2fa27cdb 0xea11b73f
- 0x5e909f42 0x06d764f5 0x1e2deaaa 0xfae5dbe8
- 0x0ec720a8 0x8fd675b6 0x58ee95de 0x19fd1ca4
- 0x4308d173 0x1884c251 0x56ffe45e 0x961c6bdc
- 0x44582512 0xb76a958a 0x12cdc33f 0xdee5c784
- 0x8dbbe9fb 0xe327f532 0xefb271ca 0xedecdca5
- 0x798e60f3 0xcf2d194a 0xee275fd0 0xd8fe6f12
- 0x30ce7bd8 0x3e17e29e 0x351ec4bf 0xe23692ac
- 0x0bb60ab1 0x60818dc2 0xdfaea801 0x1afe161f
- 0x72fbcb53 0x9382e661 0x56054fdf 0xe6261b4b
- 0x97e746c7 0x6257411b 0xf0bbac9d 0x8fd6478e
- 0x203e690f 0x9758da43 0xef6ede77 0xe85fc9e5
- 0x8e5315ed 0x479c6f9a 0xeceaa8b8 0x4f626f85
- 0xe79c2ead 0x14e97f8c 0x2bb51ff0 0x6b733645
- 0x9e578a09 0xcf424ddc 0xb315bb19 0xc4833717
- 0x3890ca82 0xf00aa52d 0x9e652f98 0x87ea3177
- 0x7acc6baa 0x531c5eb4 0x6a85b1f5 0x7b1c0192
- 0x0b32c8d7 0x735c5791 0x86c1ebc4 0xa4361511
- 0x0c7bce26 0x1357809c 0xa382b877 0xa4f9a0ed
- 0xca30e907 0x277d3c65 0xec0bba64 0xf5169aa9
- 0xb8a1305b 0xbb4059a3 0xa44d32ca 0x76b0141b
- 0x7bacc1c2 0x51273c1c 0xf8f4d7af 0x0278678d
- 0x04d36367 0x38ed7b1e 0x8a45327a 0xdd19324f
- 0x36a5952f 0x97661f43 0xe2671856 0x1eb34493
- 0x8708de21 0x080f9e7d 0x070d13a0 0x2c54a64f
- 0x86ef2751 0xf83a87e8 0xf61841fa 0x0ade1426
- 0xe1cca086 0x96a9a439 0x648f53e0 0x378a6cf4
- 0x894a3c7d 0x9bf1031a 0x2f0affd0 0x4688048d
- 0xec159b64 0x28b103ac 0x462767a5 0x278ac30f
- 0x3e5bf100 0xdd860ac2 0x384e9dea 0x55abe65b
- 0xbc95d098 0x905277bd 0x8b47e264 0xf4cc82c5
- 0x8f06e7ef 0xf2fb2364 0x13f70c45 0xc5eb083c
- 0x6c4ee92e 0xb2f7719c 0x19883212 0x611f22c8
- 0x8c742ec0 0x1550089f 0xc6c5933d 0x1a6aab8a
- 0x27ac73c0 0x4b8be65d 0x25c17a0f 0xd1ee7238
- 0x54a47bdf 0x9bf2d8e7 0x223873f1 0xb0825f98
- 0x6263a6a5 0x6e732bde 0xcb2460bc 0x195b6758
- 0x74eab2c0 0x10509c33 0xad5153c2 0xa9c77d09
- 0x5581bc9e 0xe85a2906 0x19ecd606 0x22d04481
- 0x2acc285c 0x4b01bec7 0x7946efc4 0x3fcc4f9b
- 0x7711e2ba 0x769501b9 0x565ed3a5 0xa6a2e0c2
- 0x2fc9f212 0x1da1dc7f 0x1e354a51 0x42f070bf
- 0x96f603fe 0xa11ea899 0xefa65c44 0x309f3b3d
- 0xa4e7de23 0x0fc0ecf0 0xed135d01 0x11526284
- 0xe1535798 0x46236948 0xbbf375f3 0x33d03953
- 0x057340ac 0x1f8d08bd 0xd3e19b4a 0xd1a074e8
- 0xe8f7b3c1 0x81f4e7cc 0x7efb3ce4 0x2d7b8dfe
- 0xc35c1b7d 0xa981b243 0x56dc3df2 0x7b0cdd73
- 0xba20923b 0xe4469620 0x9999a05a 0xd558e6c9
- 0x1b2a6e34 0x1a03ad40 0xead427a9 0xdfbdf1ea
- 0xe9b9c758 0xe1ce3e74 0x2ee3013c 0x37fde647
- 0x7528f451 0xdb169663 0xc1595963 0x487703e0
- 0x649824fc 0xf4e557c4 0x26ff0cfb 0xa6c61495
- 0xbf6ff8a8 0x1e936c2f 0x28170318 0x16623623
- 0x7cf43aa9 0xcf44b9bd 0xee05bbe9 0xbc364396
- 0xfac9c35a 0x70664227 0x4200bc74 0xc847c1f3
- 0x393b52cf 0x67df2a37 0x24828663 0x85c64437
- 0x0ca91fc4 0xbbab8588 0x170d40ec 0x6a5270d7
- 0xd873cb99 0xc461e41e 0x68fb5dcb 0x175808d3
- 0xb3c75d6c 0x5f8659a3 0x164af2cd 0x491ed225
- 0x21b774d4 0xfc5f44e0 0x5a761165 0x8394b784
- 0xa3625993 0x23db8229 0x18adfc19 0x7a86dcaa
- 0x3759a419 0x8236b6a0 0x866eb76b 0x40e3936d
- 0xa327f573 0x0793a949 0x5511fbac 0x7aa8017a
- 0x869d2433 0x9fb80368 0xd9b8d14a 0x725f0a17
- 0x50ec0c4d 0xeb8bd3bb 0x6785d7c0 0x9882836f
- 0x0c164e65 0xa7ff708a 0x3f4b7ded 0x160237e4
- 0xfa551105 0x7dfeb41d 0xf60157d5 0xf863bb00
- 0x23d96b49 0xc8b80eea 0xd395a7bb 0xa6cb0b99
- 0xdae2d53e 0x374d5699 0xede8a731 0x64e2eb82
- 0x3aaffc9a 0x03da3d18 0x775890e8 0x3842a94c
- 0x863c3914 0x4cf8cc03 0xc40d3d2c 0xb5514333
- 0x1254c457 0xae791759 0x7eebf7c4 0xcaac9331
- 0xb3f9a144 0xf9430aa4 0xc241038c 0x7b481099
- 0x6ffaf560 0x504946d2 0x5ad1fb41 0x4c4ed169
- 0x1331c934 0xfc02efaa 0x519b65e5 0xa2eb152b
- 0xe3b78626 0xf6cc1ce2 0xaba6d9c6 0x6c117767
- 0x3ba1a970 0xab320fb2 0xa17ae6c9 0x07f8b830
- 0x1752f87c 0xcadd1616 0x81229b18 0xb8f1c91b
- 0xf62e10f9 0x40fb1a82 0x6feed0ca 0x375b3f31
- 0xcc951ee2 0xdbbc0a84 0xc3caf9d9 0x51e4f7e2
- 0x6c2cc2da 0x86994a97 0x58516036 0xa680e1ff
- 0x83255438 0xe304daf0 0xabf95c4b 0xeeecb868
- 0xf258ca56 0xc63b1f45 0xe4637c07 0x4bd8052a
- 0x01515dbd 0xa3d3dca6 0x79565fed 0x0427abda
- 0xeb640f00 0x4f34d441 0x135af3a0 0xad86ce4d
- 0x83daca30 0xd9ae59ab 0xad9edd9a 0xbb18a84d
- 0x9163b7ae 0x68c45613 0x4eeb7297 0x12c0aa50
- 0x0003968c 0xb872a623 0xa39b33c0 0x4c934155
- 0x658bcce4 0xfa7c8c07 0x062681c6 0xd091dce3
- 0x6b421cf0 0x726aae92 0x623e4f88 0xd74b50b4
- 0x0a6410e7 0xe6158980 0x2956f74c 0x5e18c87c
- 0x6fd6e24d 0x8afdf654 0x928a859a 0x55edce30
- 0x63a859ef 0x4b82ee8c 0x6eda25a4 0xf8b32d44
- 0xdc47b7f0 0x5ff1c6d3 0x8ec85752 0xfbcddc99
- 0x86b90e33 0xe9fe679e 0xf6933cee 0x7054cf99
- 0x7fca8ff3 0x06bbad7c 0x1a5a6f2f 0x1effefd9
- 0x1aae25a8 0xc594864f 0x8df29cf4 0x373b22ee
- 0xfd7cc798 0x2d3018a5 0x31806f07 0xaeadce1e
- 0x9eb56db2 0x997e6a02 0x3f6ad090 0x8d13dedf
- 0x6fb3b150 0xbd15fe3c 0x35b6e654 0xfd9cda44
- 0x77864119 0x7ab48f53 0xf0cf2f91 0x16c955fe
- 0x06ae6500 0x11969961 0xcf4c27cc 0xe0500cae
- 0x361b4f0a 0x95eafe71 0x9ec8e2a0 0xafd6afe8
- 0x424b6b80 0x4b2e1810 0x3b474219 0x142aea44
- 0xf3654186 0x3ba86c0b 0x833f65c2 0x6d47eb79
- 0x62dd2140 0xd94a70fb 0x8ca1614f 0xaf4b2f5a
- 0x49a94d86 0xd1bcf8ff 0x75758118 0x4d249643
- 0x1998d0e3 0x9138a5d2 0x25c3285d 0x94aff0c3
- 0xa3b5228a 0xd19437b7 0xef21e585 0x1b7e4f3c
- 0xd641981d 0xb402e718 0x864429c0 0xdea501be
- 0x106824bd 0xfa029c7e 0x24d7c5b1 0x392faf14
- 0xc6d34b80 0xcdae7248 0x8fcda2d8 0x4ea47d55
- 0x6159a07e 0x7321230e 0x898acb28 0x1ee768ef
- 0x18d5b5ce 0xad651352 0xcdb1b265 0x51344650
- 0xac50b615 0xe63a8384 0x80662716 0x82a18a79
- 0xa5a7efaa 0x7a145b9c 0x849e7f01 0x6798d58b
- 0x040590b7 0xc5ea38e3 0xc801c79c 0xbb195537
- 0x928bbb0c 0x38dbcc6c 0x78392d00 0x7a1ab99a
- 0x7ab11689 0x5da16626 0x01fc4fc1 0x73aaf369
- 0x4ae39f8f 0x5615a7a3 0x973313fa 0xc7ad9ba8
- 0xd58a9805 0xf600d196 0x2acf7e8a 0xa9781219
- 0x2f60bfd1 0x73dd49ed 0x08e92462 0x7c088af6
- 0xc0ec767b 0x813d1a47 0xc854915f 0x38c19883
- 0x3d68948b 0x37013904 0x7d673d86 0x9a347e46
- 0x89b64816 0xe2eea157 0x9c9e7b43 0x88894832
- 0x4e420ce2 0xff8ca9a2 0xc152fd87 0xfb407682
- 0xe2808404 0x4c386f6e 0x053cd949 0x08f55f48
- 0xf89b7624 0x37e43a08 0xf9bc62ae 0xa6d76f51
- 0x4e400425 0xda181f10 0xad190c86 0x6952cd23
- 0x1c1fc245 0x44d3449b 0x2383b865 0xfe9bb854
- 0x745990c5 0x34be0541 0x3ec0104d 0xda80eb99
- 0xf0b3f266 0x29caf9a7 0xf4ff713b 0xebd3c95c
- 0x1b2223d9 0x14809a4b 0xde8ecf29 0x2140f249
- 0x9da938f4 0x5376618d 0x45e1c6b9 0xcde4cb9b
- 0x1dad65a2 0x47567cc3 0x285f8145 0x080df22d
- 0x61f570bd 0x54c91058 0x597a3472 0x4e2199a7
- 0x54bc0b43 0xbbe1df4b 0xdf0843a0 0x007ffa70
- 0x44a969ce 0x2b10aaad 0x337ffb08 0xd176496c
- 0xe89a0d63 0x953fb0c5 0xc3cfcb1c 0x92a96ea5
- 0xbde759f4 0x497e8adf 0xad8b516c 0xfb6967f2
- 0xdc9031a4 0x6a200ab4 0xd93f8951 0x28e22ade
- 0xf54c1c4d 0x8b6325f0 0xa7946fbb 0x76ed4a4d
- 0x6b808dd2 0x86634406 0xa5044ca5 0xe0d0591a
- 0xd817455d 0xc00d1daa 0xc7c40850 0xe2e025fd
- 0x74ba9bad 0x550c236d 0x29b44966 0xdcbd8276
- 0xc4b6586d 0xb1702e0f 0xaebf15a6 0x7d2f1cd7
- 0x9ccc8b24 0xd2fe8842 0x1fe70488 0xffe89b22
- 0x7600ef41 0x75569ee5 0x89f065c0 0xda8d0c8b
- 0x27296329 0x99241565 0x611cc8c9 0xc67415f1
- 0xf0cf41fb 0x38f066ea 0xc13dff67 0xbc04723e
- 0x8f6f8db7 0x94821abe 0x45a5c57a 0x0c3c2474
- 0xd80aa358 0xf95e1874 0xaf4258aa 0x325f2c1d
- 0xcb15342c 0x40d77acf 0xefad72fd 0xb154345e
- 0x9584df00 0xd0712387 0x6d7d329b 0x8c8ff2eb
- 0xebd94378 0x8b0bae9d 0xeecd6bc3 0x529a6a69
- 0x797edc8f 0x4845ef9f 0xa0d083f8 0x14cd8c0b
- 0x775ef704 0x1f83b4f0 0x0047afdf 0xebf6dd6f
- 0xad0a5557 0x9a9beed1 0x9784c839 0xc5fb7640
- 0xe0b3993c 0xaaf9fee0 0x59976746 0x79e0674a
- 0x82b5ffca 0x608e4a56 0xdb81df21 0x3a558382
- 0x17a7c643 0xd9112bd2 0x2e2a3121 0x852a0836
- 0x5625abd8 0x57f8621c 0x7d64dd40 0x2a8d920f
- 0x5fe3e399 0x4486edd8 0xd36655a2 0x23851557
- 0xa096b610 0x06d36c37 0x05d1fb87 0x953aea36
- 0x168daec1 0xbb219585 0x5f17aa7c 0x35d378ae
- 0x76e183ff 0xd6ec5f10 0x4bda67c1 0x96859188
- 0xb328559f 0x834f3e93 0xab87eb5b 0xa8bdb45c
- 0x6e81579f 0x07fee7e4 0x426aa06f 0x7380dc40
- 0x27cb618e 0x05d41994 0x98876595 0x4e6ecda7
- 0xd0549783 0x21b62d1c 0x85058d66 0xbeb36620
- 0x3457564f 0xc29012ee 0x40f30d02 0xa19964e0
- 0xe6f4e733 0x629df93f 0x958abe90 0xab4c3d2a
- 0x55c626d3 0x63cd0ce5 0x832f8ae1 0x8dc5bc20
- 0xcd0b0550 0xfeee65eb 0x0b8309a7 0xdaa9623c
- 0xb5e51b5a 0xf00c9323 0x6b897c27 0x0bd12d37
- 0xf42f8ae6 0x48b81705 0x155e9392 0xb40ca230
- 0x798cd836 0x58e7eb07 0xca2eb2d6 0x238429bc
- 0xdb60b26c 0xca555fd8 0xac907a1c 0x2307f54a
- 0x74b44142 0x44d620aa 0xabf0208d 0x8904f028
- 0x264f31eb 0x5096576e 0x470ccc88 0xed1d68c2
- 0x03ddf124 0x507bec18 0x262b5988 0xb9b530e2
- 0xd1ac6728 0x3a407a87 0x92308c30 0x7394af8f
- 0x4273dd50 0x1abd7a7d 0x28374e74 0x87404b18
- 0xcf9b2454 0x2da15860 0xfb151dad 0xd7c5e552
- 0x58a49994 0x7daa7fb6 0xf5c7032d 0x199c156c
- 0xe42c6748 0x7ab9b557 0x547802b8 0xc606a059
- 0x3d89ff21 0x4fcdec22 0xb1087ad2 0x5521be5a
- 0x5bd9618f 0x93aabce7 0x28be0c32 0xcae8c149
- 0xe98236c3 0xe4be458c 0x805a0a38 0xb300ceb7
- 0x1dcb3642 0x33d87e03 0x81c17b3a 0xf8b59cd4
- 0x9ed300eb 0x5e99acb6 0xab24565e 0xa7e9d72a
- 0x92f97cf2 0xb61fa917 0xbc4167ea 0x5c37d1f6
- 0xcd5200f3 0xc48dcdf1 0x3ba93fe4 0xf5045cec
- 0xc09adede 0xdeef5953 0x1d7c6b08 0x77f2cd7c
- 0x025d30ab 0x206b53a8 0x8140335f 0xed1751b1
- 0x9fc265b6 0xdc56b2ba 0x6f60ddda 0xf92d7837
- 0x3560dc91 0xed0140fd 0x12071a5e 0x397e7dba
- 0x8d9c89b8 0x5f79e3f3 0x41add538 0xafce559e
- 0x8956bcaa 0x76854169 0xac9d211d 0x1d9d2f47
- 0xa4c8cf2f 0x0bdfa060 0x35ca5f3b 0x1ec524c5
- 0x859b6ead 0xb3bd5250 0x1616fbf5 0xd18e5d38
- 0x8b1b06a7 0x9b6e1a2b 0x128e9c72 0xbb672bb7
- 0xd50b0234 0xfe1f75c3 0x40062da3 0x7b875ae3
- 0xca401a1c 0x1668185e 0x25002654 0x314eb038
- 0xd03a8be3 0x86717b8c 0x1bd58524 0xe17ba392
- 0xaf90d12d 0x7b3afe6e 0xcad2b963 0xb91245fe
- 0xe0c7c9f6 0xf98b3bd5 0x305bd207 0x713515d1
- 0x4677d009 0x20e34228 0x6128d849 0x5fb620df
- 0xe3274241 0xd3814ecd 0x223303a7 0xcba4f054
- 0x73a34ab0 0x874fb4ce 0x390efd43 0x490a7a12
- 0xa45a9d66 0xde80cd80 0x9a36beaa 0x2cfca0fc
- 0x231f4d1d 0x04c1fad2 0x5ad83a8d 0xc2931f83
- 0x97f63f61 0x38a6029c 0xe34de276 0x699fa28b
- 0x458d2e15 0x67b57701 0x49385ab4 0x09417b0c
- 0x18897b93 0x516f5749 0x4578a8ff 0x52fbda3e
- 0x2da1dd8a 0xf22e616a 0x7806ab6e 0x92886668
- 0xaf7e056f 0xd9a35959 0xf6ae0b16 0xa42d213d
- 0x928ba1be 0xb61f8e2a 0x6635e3c8 0xbaf76f05
- 0x693d4eb0 0x69546031 0x00427e2b 0x97e563bd
- 0x2857d47f 0x28aaa688 0xf91ec5a8 0xd119289f
- 0x721dc1df 0xdc40c94e 0x67e3d987 0xd2141380
- 0x1bdb7023 0xa84158f3 0x5637a2a8 0x34f80708
- 0x7d452316 0x7cdd1f84 0xe1d1633a 0x82d9f886
- 0xad779cc7 0xd2ae85f9 0x0c467ac9 0x27c1d5f5
- 0x1b28be66 0x34d759d5 0xbcb56ec9 0x171c3020
- 0xac4319ce 0x68c1e8c2 0x3cb463cd 0x78a065bb
- 0x5188b314 0xc8566dfa 0xc93094fc 0x28a21400
- 0x9151a62d 0x678940c6 0x5023ed27 0x089290aa
- 0x327f3b1d 0x7e3d9bc8 0x2c664ff5 0x32e58da7
- 0xe998fd47 0x480411d0 0x9297db4c 0x182058ef
- 0xe21c0a93 0xa32d2771 0x91199466 0xdb8694df
- 0x6261f08c 0x3aff7da0 0x1e24865e 0xde2f7ebf
- 0x1f570473 0x3ec320a3 0x3a8461b6 0x3e1c1e73
- 0x862aa78e 0x74c9a73f 0x090973ab 0x248fb1fd
- 0xebb1b73c 0xab8cc3d0 0xa80d3a86 0xb81c4992
- 0x9f14bb10 0xef283b13 0x060ac416 0x03768c78
- 0xab1a3b35 0xa8f7cf27 0x947beee4 0xdb6d4731
- 0xbc6cebd4 0x39e3cd02 0x9ced359a 0x3358a905
- 0xa4f31baf 0x56bb572c 0x0a8ccbde 0xe701126f
- 0xad241a42 0xd66bafdf 0x5be07a77 0x4fa8a2ee
- 0xff2a829e 0xbe7aa422 0x8ba9b94c 0x20fce978
- 0x8086487b 0x66bf1d28 0x0e9a4b37 0xdf5836b6
- 0xa6eb018c 0xf6a5ef16 0xcfb3b85f 0xa8bc1ecc
- 0x3c5925ab 0x1c926d4a 0x60e2747c 0x629eb075
- 0xbdcfea23 0x10443caa 0x5d005a9a 0x4a6235b1
- 0x56b70ab3 0xff8cb97f 0x42828a8b 0x33692058
- 0x4ce783ad 0x08d1c099 0xb14379df 0xd65d24dd
- 0x14450585 0xbb0450d7 0xc8776287 0xea2eb9b6
- 0xc44d73e2 0xcb386daf 0x9d3686a1 0xb58c318b
- 0x287fbe53 0xe8d84535 0xbf17ef8f 0x98332fff
- 0x5e098cbb 0x9ecc14a7 0x08366dbc 0x55028860
- 0xc09e869f 0xa29a43e7 0x9be9daac 0xa1750a10
- 0xb2fd8da5 0xf380c1cf 0x6087ff3c 0xd69bd21c
- 0x7e14ede5 0xc0ed409f 0x12f25810 0x3f44d63e
- 0x9e7b0cab 0xcb9cc71b 0x18b66ea5 0x80843c35
- 0xf140a7ed 0x89fb323d 0x0a326c40 0xe3f9af29
- 0xf6c59365 0xad3a2017 0x906d1ce2 0xd3360e1f
- 0x046307dd 0x290ff1e8 0x910a9632 0x5cf471a7
- 0x54321c10 0x12924fa3 0xff3d87e6 0xb1687618
- 0xa2a68555 0x1a21d3bd 0x1095d6f9 0x349b25d0
- 0x8166c94a 0x006c839e 0x0094b4e4 0xdd11f901
- 0x1c40e7f0 0x50946c87 0x52bcea55 0x20b86a9c
- 0x7b386df2 0xddd48f3d 0x421d417a 0x7052e089
- 0x8ec43a4e 0x6174ca83 0x6b712d8e 0x566ae151
- 0xc38d68a1 0xf7d64e87 0x9f53d487 0x5e985461
- 0x21d27e2b 0xdbb9bf40 0x2826a5cc 0x6ca4d786
- 0x381508b8 0xd8ffd839 0xa85f5b86 0xb37fa53d
- 0xe4906f8f 0xc7329e0a 0xe56272aa 0xe7b97be8
- 0xbd6a48dc 0x935e9f91 0x02313e13 0x026b8e36
- 0x939a5293 0xe125a1a5 0x6b27d136 0x3d520ae7
- 0x7abc1309 0x183f50f6 0x08575ed5 0x1d2c4c72
- 0x0e682129 0x655ceb36 0x1a508349 0x3be034d9
- 0x4bf83c5f 0x592520d0 0x5f65a0c2 0xcad74a35
- 0x5c4e605a 0x973b60a3 0x309fc15b 0x3ea3781f
- 0xb56c3172 0x269f8d75 0xebfa9293 0x9ff8bf36
- 0x27bc0472 0x4a1888d1 0x598b47c1 0xba2d3073
- 0xf71b310a 0xb9db5309 0x065ffaf8 0xeb21604b
- 0x60875644 0x6f76cd48 0x47746357 0xbf2e90b5
- 0x7d40e67d 0xe87f11ec 0xc5409f18 0x9904fefe
- 0x9745644f 0xe1089f12 0xdc49f755 0xf0cd3596
- 0xe9e69302 0x419b9a3b 0x3f0a6315 0x8b715e28
- 0x363ede54 0xcd41a72f 0x0bafa9fe 0xd00225c7
- 0x6e8d0407 0xd1f100b9 0x0cd02e9c 0x760a2ffd
- 0x6ac6f01e 0xd2226e57 0xe7a7bd75 0x0bec05af
- 0x72b4d6c9 0x54df0f5b 0xbcb2bb34 0x20364bf2
- 0x9fc24cdf 0x83452f28 0x734248b7 0xc698bf34
- 0xee328cdc 0x8e4bff33 0xa1addacd 0x07af68c8
- 0xc34b5d25 0x8e611a0d 0xcbb8ff85 0x077c6d43
- 0x95feb2a3 0xb435fffc 0xef5eca7a 0x0ff6045a
- 0x449647ba 0x75795c99 0x9c514436 0xabbe74d9
- 0xd180f18d 0xdcdeee76 0xa9550f7b 0xb4c8e109
- 0x80b21662 0x8a407a0c 0xa6245b13 0xa16f44ac
- 0xb3db67d3 0x0b335cfe 0xd878e875 0x81d6df28
- 0x44871141 0x6a6dada5 0x7f97fcd0 0x7ee87f79
- 0xddc5bcfa 0xfc2763db 0xb11a9212 0x94ba7acc
- 0x49428749 0xd219071f 0xd91bc4c2 0x4ad5c326
- 0x54ea2297 0xdb16bca5 0x33327f3f 0xc487b8c7
- 0x54ca8d94 0x4c6f5655 0xf51c3911 0x37931433
- 0xf6506856 0x6b5a93f8 0x388950b9 0xdf5263b5
- 0xd4cf56ea 0x8da347e2 0xf20a9a39 0x1a6b8e4c
- 0x2ce3df55 0x38269e78 0xdc7a9762 0x9e73a3dc
- 0x57de6fa7 0x9c2573f5 0x3491629e 0x009452fe
- 0x8a34ddd1 0x701df9ab 0x4035380c 0x6f25e16d
- 0x0ca914de 0xf9277a06 0xca1f1fe3 0x95aec5b6
- 0x7a613e97 0x52e77607 0xd7229ff0 0x5f301016
- 0xd4e142c1 0x29a939cb 0xe96dd1ca 0xc953aec0
- 0xbf02c31e 0x02135076 0x4f931dcb 0x4b280cd3
- 0xe0cda493 0x70831c04 0x8192143c 0xc9f94a3b
- 0x13eda1d1 0xc62c39ad 0x754a5411 0xe43ce416
- 0x95ac1b10 0x871261dd 0x79f33a8a 0x77383224
- 0x98b2480f 0x2df139d4 0xd753e53b 0xbad87b53
- 0x977cc17f 0xacc4bb71 0xbde6b5f2 0x206562ae
- 0xe0319086 0xcf903501 0x56ed1506 0x64f4556c
- 0xb90bbe0f 0x2def02e5 0x9b625a9b 0x96086cce
- 0x39d1d0ab 0x8c85c5d6 0xa8199040 0x23c770e2
- 0xf5303bd0 0x51a83607 0x5afa1989 0x8a81b4ff
- 0x1b24e6a4 0x4cb58014 0xbbee7d31 0x758271fd
- 0x259bc3f5 0xb3f9c6eb 0xbd8c4f86 0x66c27a35
- 0xa41c2904 0xc9848ce3 0x9ba21676 0x18f65508
- 0xe5637556 0x031e21c0 0xc09e3c77 0x5f10856f
- 0x9b3ea697 0xd8afe20b 0x447f5be1 0x5c4b1668
- 0x71f44cc1 0x8637d0c6 0xbd182081 0x1e4221b4
- 0xd312a403 0xf49d2c96 0x686ff9e1 0xa3f9b746
- 0x3caeae90 0xf2bfb131 0x5823eb37 0xcd4edc6d
- 0x3a7f65d8 0xbb4be9d3 0xd7939b2e 0x71d03a37
- 0xa30ff63a 0xde7ccb57 0x8ea031ba 0xbcb3994d
- 0x8018d6fb 0x1c7a3610 0xac900573 0x9ad05089
- 0xe2d17d5e 0x7816b9a7 0xffcca5c1 0x9faa9a0c
- 0xadbe99e6 0x06de7ee1 0xe4ac8981 0x29ef423c
- 0x32219ad2 0x806642b8 0x412ab076 0xfe4c5196
- 0x82c2507c 0xd58c7b7c 0xfe9edc9a 0x89e4c6e9
- 0x4f122269 0xf0aeb2f1 0x77f4fbc0 0xe6692464
- 0x6e64c198 0xaf79a455 0x01e2ed98 0x897ec1b0
- 0xf7a0dd35 0x92baec5e 0x93f17b7e 0xfbf82b90
- 0x168d32c5 0x741b61c0 0xb0f5b9b5 0x0557fb71
- 0xca937e89 0xad652a2b 0x9a2121c8 0x34d189ca
- 0x037dd1a3 0x3e650192 0x4defbaa7 0x06763750
- 0x48d4d1b4 0xda2af400 0x7df71d63 0x3e0b4c46
- 0x28c645bc 0x29b15428 0x34e10558 0x1166cdd6
- 0xc259a364 0xdc7e0f21 0xb02cee35 0x3055f39b
- 0xb77a50d2 0x2c143c84 0x7903e30c 0x018e20a8
- 0xf95b4a26 0x38c84311 0x1f0c3098 0x535a95e7
- 0x730214dd 0xb0f90f53 0x625fc5d1 0x2c1f2d76
- 0x7c9b5351 0x5cc285f4 0x0f63b5f4 0x90d59d57
- 0x140213fc 0xd21a74b7 0xf85fd83b 0xd9f21e94
- 0xbbefcd30 0x5091f90f 0x8d5c47fc 0x9455364a
- 0xef89f274 0x901af041 0x782cd03a 0x086f1f81
- 0xe09eb4db 0xf7a8146c 0x41898271 0xe8be480c
- 0xdfbac329 0x5fb899cd 0xfdca25e8 0xe994b3d8
- 0x2299ede3 0xc0341512 0x0128eb87 0xd5cff619
- 0x779bba38 0x1e986657 0xc22ac15c 0x919af309
- 0xd3cd1df4 0xb4b22d9a 0x210c0617 0x5723f9e0
- 0xb7b79328 0x613e738d 0x39057942 0x48d48958
- 0xf9d80cc0 0x16f69a5c 0x6d517734 0x012f07fa
- 0x7a8329e1 0x586b22c3 0xdd0d96b9 0x0c56d5f9
- 0x60410aa3 0xd1975446 0xd2c142fa 0xb13ba75b
- 0x0b046c21 0x03afb4e0 0x346f5dce 0xd108fa96
- 0xd1ca963c 0x73f5838a 0x4b4f734f 0xa1d430a7
- 0xd0cda381 0x64fecfee 0xc5048480 0xd3bfb251
- 0x088982f9 0x2383aaee 0x9b9c8f48 0x623f2132
- 0x0f5ae663 0x3c32959a 0xa1fd9ecc 0xf62d0e4c
- 0xe690d930 0x6be7a286 0x825d0066 0xe51094ca
- 0xc99affb8 0x832222ea 0xe7296513 0x2c040c86
- 0x35f62e4f 0x6f46ba84 0x25cdb0a3 0xe8b6ec22
- 0x5b6cf8d0 0xcfd85f8a 0xf0181633 0x5362c0b7
- 0x58955c60 0xc5a36973 0x874d04eb 0xa42a42df
- 0x4bd5d994 0xee6114f3 0x671ccecb 0xf0ae2422
- 0x70c98042 0xf9ed2a1a 0x6b60f0c9 0x04b13374
- 0x96fba002 0x8b481645 0x315198a2 0x65c80b9a
- 0x31475dd9 0xe95c5c3a 0xe3c22d43 0x12659565
- 0xabec6f96 0x9446e315 0xa6552f83 0x295e2596
- 0x8b6a2d9f 0x71efb10e 0x2d309912 0xe3dd2879
- 0xabd39f50 0xcfa94a90 0x61d282b7 0x062b246f
- 0x617b7162 0x3628fffd 0x93c8c8a5 0xaa44c72a
- 0x11b78bff 0x8259874a 0x186bbcfd 0x37bf7395
- 0x6f8582a7 0x65fdd21b 0x53106cb5 0xbfbe1e4a
- 0x1ed99eac 0x670b3763 0x245db7b2 0x7584d9be
- 0xc3472009 0x572bddab 0x17e7406c 0x79e0ea4e
- 0x74779fd3 0x92d0c51a 0x1808d006 0x46c1e76b
- 0x40e48bf4 0x61e17325 0x1d437ab2 0xacf51c38
- 0xc19eab2c 0x02957308 0x0bcc40bb 0xf603815f
- 0x9c666571 0x6a7d539f 0x57f3941b 0x7af81d5c
- 0xad1427b0 0xc188d623 0xac010003 0x1ff4cdf6
- 0xfa504446 0x6425ba6c 0x27ff69fa 0x26da5613
- 0xb6fc0a69 0x1155853e 0xbab81c6e 0x3dc17909
- 0x07b209d9 0x8b269554 0x73fc8781 0xfc1c2c82
- 0x572df087 0xb71bb5e5 0x55f9d202 0x6f525daf
- 0x117755f9 0x52cce1bb 0xa789ed0e 0x1313ca47
- 0xe8bdd878 0xc37e8dcb 0x53b971fc 0x43540a80
- 0x3d2384a7 0x25ac992d 0x7aef31c8 0xb1294afd
- 0xb0a34878 0x96e9ca1d 0x82a19bcd 0x08cd2bdf
- 0xd2681e35 0x2d32fa5f 0xc7c0c8b2 0xeecd089d
- 0x97404355 0x0b34539d 0x37ce4df3 0x599352dc
- 0x06734f29 0xf47ab5d8 0xb15ea9a4 0xfd92ed2f
- 0x9510bdbd 0xb740d34b 0xbac3e94a 0x52efbc03
- 0x40bd7acb 0x1bf83a4f 0x3d76c698 0x7e691383
- 0xec85e4ae 0x55e9a446 0x1fc3ab3b 0x6aea12fe
- 0x8fab4a84 0x69cd7328 0x935a7236 0xc3f59437
- 0xb73a7d8b 0xba0f54e0 0xe8e7aafc 0x6f82ade6
- 0xed6ccaf0 0xdfddc46c 0x0763fc3e 0x778e488f
- 0x0bcc4dce 0x8f919858 0xa7bc7d1a 0xd4954eea
- 0x517b5458 0x6c3f5835 0xd960f76d 0xf5be65a7
- 0x133666d9 0x4431f94f 0xccedf47d 0x6eb21ff8
- 0xb858dfef 0x15beefef 0x9a1b6b6a 0x64890eda
- 0x2a381329 0x660302bb 0xc65c001c 0x049a4be4
- 0xfca1b112 0xb081a099 0x3a2217f8 0xeea9a2ef
- 0x7719129c 0x7c915047 0xb3fe3e16 0xf1c31548
- 0xfa84a76b 0xd7af5b51 0x0de24c14 0x89a7263d
- 0x5a9dbffe 0x7ea90ae3 0xc21a2a1d 0x65ef3a3e
- 0x90fd1fa0 0x69aa0d9b 0xb44a5778 0x5ded34b3
- 0xa0d78617 0x91817661 0xf9541869 0xa0960273
- 0x024d891a 0xbc9f6d7a 0x630bac04 0xd186ffe5
- 0x0d60d640 0xc05e4701 0xba72d775 0xacec7c0c
- 0x1680e76d 0x6b153d69 0xbcbd60c1 0x3e1ed6c6
- 0x9705975b 0xaa3cc082 0xbdd723d0 0x7c0bbdd9
- 0x2bcf8414 0x787b2dea 0xaf923561 0xe4ad94a2
- 0xa85f83a1 0x1de0ddcf 0xd96f918b 0x617b1461
- 0xb1d3e386 0xe8d80b5d 0x40dad53e 0xcd8fb285
- 0x46fb4bae 0x2845c456 0x8b261251 0xf4923055
- 0x99d0db1e 0x0d7cc781 0x9bb20af6 0x7116d81c
- 0xd7f54821 0xba4eb2d0 0xaef6b275 0x3ca796cf
- 0x8807360c 0xd887484b 0x7066ec38 0xf7262152
- 0x5ede9cc5 0x6b8eb00c 0x5564b7af 0x4726dfd1
- 0x9421fe95 0xcc0ff9e5 0x10ca7e89 0xb76760e6
- 0x3da3a50a 0xf9cd3f82 0x1eb01d3c 0x13ae6371
- 0x129747e6 0xab223504 0x9978c7e9 0x1f7ce259
- 0xb17fb162 0xd1ac0e80 0xe04bfd17 0x197d9eac
- 0x59586a32 0x7436e8ef 0xc28b1ec5 0x83af0dc7
- 0x8382692e 0x17f04148 0x31ee5ad3 0xfe89b973
- 0x0148467a 0x1a6a16ef 0xb6400bcd 0x53ae7036
- 0x6b258693 0xb6edbeca 0x2ff0b686 0xe6f0c346
- 0x0e0ff99c 0x8d369a6e 0x7d10411d 0x2ebccabc
- 0xa67435d3 0xf9901563 0x363f164f 0xf01a1b15
- 0x93b6a10f 0x81f0c068 0x89b8423d 0x60eb711a
- 0x4e45bf98 0x24845e1e 0xda91d7f7 0x561e7ab1
- 0x51a183de 0x73bf29a6 0xcdb20f84 0x46d5ab3d
- 0xce01efbc 0x8d09be04 0xbf4aee2e 0xadf03a7b
- 0xbc454c61 0x83647148 0xec9e834a 0x11527826
- 0x2c7eb009 0xc6d7e3f4 0xbe8befd2 0xd3cc42a8
- 0x0442b41e 0x89643506 0xfd1dc572 0x74b340bc
- 0x686f6f6c 0x48b92189 0xe8f88be6 0xfc591dbf
- 0x8b453678 0xea1fd8cc 0x659d57d9 0xb501f90c
- 0xa6d6b031 0x182d8378 0xd6a8d690 0x6419c2b6
- 0x523d3089 0xc23c971c 0x43994015 0xa4b23066
- 0x831e6ca5 0x03c18610 0xd6d1f4b5 0x28978a3d
- 0xdc620eba 0xc1f86faa 0xf6c4d906 0xf06f85f3
- 0x232fa1bf 0xcf80cc2a 0x6599a5b2 0xc2d4cdad
- 0x0287eb92 0x5cdc4dd6 0x34a9b6d4 0x6d4b1324
- 0x6d21a837 0x00026037 0x80a225a8 0xad75b226
- 0x414a3741 0xb74d0962 0x363b24b5 0xb5044295
- 0x0a01c1a1 0x90a110c8 0x53bdeee5 0xad31aa53
- 0xfb85cc5f 0xdf80b0f3 0x7ad3cb0f 0xb5c68bd6
- 0x89185ff8 0x41544629 0xad5adfe7 0x39061752
- 0x2e9c106c 0xbf52a0df 0x9d2cef79 0x99eba49d
- 0x4459b32c 0xdc98fd7b 0xd81f2f74 0x8aa59f53
- 0x1817857f 0x5f79e3bf 0xc4b7c810 0x9e3a9ddc
- 0x724af115 0x121239e3 0x3c33c849 0xd8abb44d
- 0x600d67b7 0xeaa06b4c 0x20fe7ba6 0x502c684b
- 0xf212d37d 0x413d883a 0x5abc83ec 0x3112bb6e
- 0x27e1b3e0 0xf6dc8508 0xfe602c4f 0xa5b34bce
- 0x4d03d689 0xdacb23c2 0xa00fb513 0x78606ea8
- 0x8fd43ecf 0x90072d2a 0xfcc7b1b9 0x7ffec951
- 0x684bbc25 0xc21a0374 0x8f06a016 0x0e28dfea
- 0x40da3a00 0x8c73a059 0xc0d565ef 0x13bb6c81
- 0x6e27c2ec 0x2f4c9a43 0xae1b4513 0x9738b38a
- 0x5557c3e1 0xa292c6ab 0xd0f78cea 0xb96402f7
- 0x6c281a04 0x948787f9 0xe59f0714 0x6f130446
- 0x4b12e263 0xcae5e073 0x00f0e279 0x9b03c647
- 0x2a141b72 0x19d1e112 0x97b3b6df 0x3c2b6c82
- 0x5b119136 0x57e2084c 0xe954bc0d 0xcdfbfa78
- 0xadc6b571 0x010b9122 0x236676d6 0x2458c822
- 0xcbb8384a 0x662cfd01 0x096c50d2 0x4959676b
- 0xf8b59f31 0xad912a4d 0x2e87fa6e 0x30182092
- 0xc0bf2c01 0x02b4bfa7 0xdd208dac 0x4c174da2
- >;
--- /dev/null
+/*
+ * ---
+ * This is a device tree fragment. Use #include to add these properties to a
+ * node.
+ *
+ * Date:
+ */
+
+compatible = "intel,microcode";
+intel,header-version = <1>;
+intel,update-revision = <0x907>;
+intel,date-code = <0x11142015>;
+intel,processor-signature = <0x30679>;
+intel,checksum = <0x1bb67b21>;
+intel,loader-revision = <1>;
+intel,processor-flags = <0x1>;
+
+/* The first 48-bytes are the public header which repeats the above data */
+data = <
+ 0x01000000 0x07090000 0x15201411 0x79060300
+ 0x217bb61b 0x01000000 0x01000000 0xd0cb0000
+ 0x00cc0000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0xa1000000 0x01000200 0x07090000
+ 0x00000000 0x00000000 0x13111520 0x01320000
+ 0x01000000 0x79060300 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0xf4320000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x9703f29f 0x1c68d65c 0x1f15f858 0x114237f4
+ 0xfef8d172 0x363b5a9d 0x4c3d9e71 0x13ff68a0
+ 0xdb666815 0x5a17bfc4 0x4fca009d 0x099ae8b3
+ 0x198e2c7d 0x7c665bbf 0xc07a1a7a 0x7dbcee26
+ 0x867296b2 0xc885b6ce 0xe602baff 0x68544b14
+ 0xc928c400 0x3add156d 0x531946f9 0x92a03216
+ 0xda352322 0xd967ee1f 0x3c5170a7 0xf6de834e
+ 0x5a2ed8b3 0x9fb8f050 0x450de17f 0xfd5ef070
+ 0x4954575f 0xa3a071ab 0xb56e2afb 0xe2b48302
+ 0x6655a958 0x57c9a438 0x1b2f688a 0x09309bc4
+ 0x0be95612 0x529c1633 0xc48515d9 0x29eb78df
+ 0x9933409f 0xda58dea9 0x58c805fd 0xbc110f5a
+ 0x40780ec0 0x6ad59bb3 0xc7387fb8 0x591c1490
+ 0xf9335932 0x32130e0b 0xef4b3c96 0xacd903f2
+ 0x5b362539 0xe7f85529 0xcb17c41f 0xe7e440d8
+ 0xfaf7e925 0x969b76fb 0x5edab8c7 0xf00012e8
+ 0x121c2971 0xe5b18959 0xadfd07c0 0x1f09c9d7
+ 0x9781006a 0x39550073 0x6c438b6d 0x436f60bc
+ 0x11000000 0x46e87267 0x7c9db265 0x4ac824e5
+ 0x94ed53c5 0x4b1bbf81 0x241a4da8 0xc3c5d866
+ 0x186d6eed 0xba1e5092 0x3d19677c 0x82b56f7d
+ 0x95d4d506 0xdccbbfb2 0xdc6be978 0x416dbe64
+ 0xe591ce22 0x02987636 0x44858276 0xfbe3729a
+ 0xee42767f 0xb415639f 0xbc959b72 0xa6919bec
+ 0xb9e2d0c5 0x2fb1e39c 0x1ebae20a 0x9a3ce21a
+ 0xebf72206 0x4020d73c 0x92674cff 0xbc607b8d
+ 0x488d8dc0 0xd1d6f435 0x39e3ee1c 0x1ed65078
+ 0x967d7a88 0xaa1b9f3b 0x38248bfe 0xb8a0aeb2
+ 0x3b8e34fb 0x86dd48e5 0x887d7432 0x3a3a3faf
+ 0xec556202 0x50ebe457 0x7676b9bf 0xe84604b0
+ 0xcb26a17e 0x52c94055 0x6b39d618 0xa82d63dc
+ 0xf583cafd 0x32107d4e 0x71d5aee8 0xad5956f2
+ 0xad58e817 0xb6da62b3 0x66d63e32 0x00a13bc7
+ 0x71233e63 0x326ef79d 0x2e3cf966 0x92b08830
+ 0x42be3b3e 0xd49905d5 0x638b6a72 0xbeaa8cbf
+ 0x5f28a0f8 0xff10578d 0x59a2d213 0x2919bc00
+ 0x61398c7c 0x2a0865e3 0xf1a42982 0xa1e24984
+ 0x2234d6c6 0xd6a9a013 0x79740c47 0x56cd5120
+ 0xc4bb279e 0x707d1519 0x33b0445d 0xae3be614
+ 0x3c3d5c9c 0x6eb115a9 0x4a2d5cbd 0x58718272
+ 0xea01ac92 0x8a6e8d3e 0xadc4315a 0xc6ba0145
+ 0x52363aac 0x4960bc5e 0x56a66f82 0xdb06eae9
+ 0xbcf5c135 0xd59539a8 0x7b68c56f 0xe298be9c
+ 0x8ac3c19a 0x3928fbea 0x4a72f2ab 0xbe32ec72
+ 0x5928b934 0x6b56ff28 0xc8f2c78e 0x97d168ee
+ 0x43381910 0xa592424e 0xb14ae0a8 0x46f724a8
+ 0xded8973b 0x9f9100a2 0xd7cbb2b6 0x2db57173
+ 0x217fd7ff 0xa85f3087 0x9e23192e 0xff8a0f31
+ 0x86f1ddbf 0xcae0ea2d 0xcd0591a1 0x10733827
+ 0x1758f010 0x38bfb48d 0xc0ec80d4 0x3a497694
+ 0xe82c7b4a 0xf21a8a2a 0xc4ba866f 0xc88fbed8
+ 0xe0e9a0f8 0x60ba6708 0x73fe95cf 0x46fab51f
+ 0xab34c80f 0xcd06bd33 0xdee23ab5 0xbb405653
+ 0x7948d7e8 0x88713e19 0xf3507645 0xc6cf938e
+ 0xa690f2ed 0xa1603eaf 0x71688d1a 0x2fc9a057
+ 0x3488d635 0x5f8eaa82 0x5c3ac4be 0xe15a8f69
+ 0x0421729e 0xfe7dbfb0 0x5fb6c672 0x99c59c6d
+ 0x2feb9ab8 0x0e831a04 0x1c8a41eb 0xe3bda963
+ 0xcac53147 0xe6a154bb 0x1dd48215 0xe0fed62e
+ 0xd0bc2263 0x820d5f12 0xc3df9df4 0x5c978a68
+ 0xd4a6d275 0xaa7525d6 0x9e7c91a5 0xad05611f
+ 0x8fa896ec 0x9d002d2c 0x06f50042 0xb05c73cc
+ 0x2362a6f3 0xb1db87ad 0x2e08390c 0xb827d183
+ 0xba59fc97 0x9c7f5996 0x5a6645b9 0x7ff51fb2
+ 0x5f8b2b55 0xbdd03e7d 0x0d7ed8c6 0x0468dd35
+ 0x4a32332c 0xfc2af9d6 0x33a14776 0x5a0b8da7
+ 0xd278a1c3 0xd3f4df32 0xf06ece96 0x08bf7444
+ 0xeb1076fc 0x7ac6604c 0x8810a1a9 0x64920094
+ 0x0e68356b 0xef753730 0x9e5a90c3 0xd050c0cf
+ 0x80c11368 0x37334deb 0x9a758bcb 0x6a50677f
+ 0xe091cba5 0x5e574d20 0xce0786da 0xe8ac8ca7
+ 0xb08cc364 0x599dec0d 0x755090c1 0xdeb882a1
+ 0xdb41e3b9 0x5bea550a 0x588fcfe6 0x2f47fda6
+ 0x3c535740 0xb01ef7a1 0x41318391 0x9573deaa
+ 0x3b049cbe 0xba4a8bca 0xc70f0a90 0xe353d011
+ 0x79493cae 0xb41bd61d 0xbb73d556 0x08fe7bac
+ 0xd8214968 0xa6fd5c58 0xb90f3e26 0x7374f308
+ 0xd9d66fb7 0x23db8822 0x1b1f7701 0xbb557c36
+ 0xd8573d73 0xaccfafa7 0x245cdb75 0xd633e6a4
+ 0x623cce13 0xff1b1379 0x068eb371 0x634b1fda
+ 0x88d187f5 0xc7524ccd 0x4f907ff9 0x65ed9ec6
+ 0x90f9f995 0xffe5e671 0xee78e6ff 0x48aa5768
+ 0x1d5401d4 0x76125937 0xda829f6b 0x7066f6ab
+ 0x35659966 0x59bf2950 0xfe3194c3 0x93e928ec
+ 0x94ea826a 0x252f240e 0xf8293138 0xbd9c56a1
+ 0x6d976d69 0x00c2bb0b 0xefe2fa50 0x718391d2
+ 0xc2856548 0xba3785dc 0x594f8bb7 0x32a3e0a0
+ 0xd4ac9cdf 0xbdee3ec4 0x0c1ed6c5 0x5cd2b1dd
+ 0x9bd8afe8 0x5598b8fa 0x8899700f 0xe5b11279
+ 0x6bc1eff5 0x81488bcd 0x0066bd0f 0x81a041c2
+ 0xb8e1db32 0xd6f00d10 0x53c9f929 0xbf537406
+ 0xe90e75b9 0x2846542a 0xf8111284 0x6f448d25
+ 0xb9303c44 0x73ce77be 0x319187f6 0x2fa38401
+ 0x6ce1515c 0x880a819b 0xf18f7bd9 0x4975e304
+ 0x7f530a68 0xa15309fe 0x5d2ccf5f 0xfa1388b2
+ 0x5abc2e7c 0xd7508296 0x90ab027f 0x1ed00025
+ 0x67ad3919 0x040191cb 0x6f2750ca 0x371e23da
+ 0x219ce1f2 0x2a94685f 0xf431a11a 0x8f3a916c
+ 0x83add01d 0x15b7c162 0xc5fba638 0xc9231626
+ 0xc44141eb 0xeb761838 0xf56010d3 0xed370b64
+ 0x3d5c291f 0x369d136d 0x64eb568f 0xf0c2fb04
+ 0x1ac908fc 0x5267daec 0x72b77c0b 0x9bd72098
+ 0x90505914 0x0ab130e0 0xe9d4cc65 0x3841a119
+ 0x49107805 0x104d8a9b 0x948432b4 0xa4d9acb4
+ 0x01708bdb 0x33867b75 0x77ed63f4 0x6c59d6df
+ 0x6ff89016 0xe140d51f 0xfd55b64d 0x2f260ed2
+ 0xf5b97bd0 0x4a278b70 0xfebc3552 0x402ab7c7
+ 0x1c563e33 0xde063184 0x32e862b1 0x56fd9e7d
+ 0x8cc320a3 0x381ad628 0x736053ae 0x8a4d3500
+ 0x9af58234 0x9a4f381c 0x2449cda8 0x8bdc08ab
+ 0xe02865f1 0xe5384199 0xbc8d798d 0x6e7539be
+ 0xbc3d0476 0x7e0d35ee 0x8bf8be24 0xfea1f124
+ 0xc93600bf 0x055e1524 0x4d2e695c 0x8ca4be1d
+ 0xf56549d1 0xb610a66e 0xf9644f1d 0x72c21fc7
+ 0x325c68f4 0x7e46995d 0x98e494b4 0xb80f3796
+ 0x63a58bb0 0xc0918dcc 0x90e1ec3d 0x02da69bc
+ 0x48d03c2c 0x50f010d7 0x4e33c8ef 0x3868bafc
+ 0xa1bbb203 0x6998fad0 0x69c1e854 0xdd61c5a8
+ 0x1eae5c43 0x325a24f6 0xcccd1c27 0x286c1720
+ 0xe4b90b87 0xae9d5754 0x35d85c1b 0x6dea7c71
+ 0x528f612d 0x7bc8e019 0x4554a520 0x06f224b1
+ 0x8f956a0e 0x3446bddb 0x05e3665b 0xf78be26d
+ 0xfc87322b 0xed1809f8 0xb00b4c9e 0xad731b02
+ 0x36cc1bb0 0x3e56e274 0xe1ef883a 0x07c6c2cf
+ 0x86055da9 0xb43d2b6d 0x5e4030d1 0xb4a60919
+ 0xbc12554c 0x0c1f4dd2 0x1cfeeebe 0x1c21eb21
+ 0x32712e65 0x4791d232 0xe35d3bcb 0xe09629b5
+ 0x34a07f0c 0x4220cfc1 0xf6b5e353 0x1ddba77b
+ 0x1f9ceb98 0x78f1db33 0x9644dcd5 0xaf097bb9
+ 0x066a83bd 0xdebaec77 0xf2c82254 0x29dc7087
+ 0xbe788ad0 0x6379772c 0x10f39ff0 0x223458b5
+ 0x28d5301a 0xd74cce3f 0xdd5a6fe3 0x8407e1fc
+ 0x3a7d4db8 0x02e0f87d 0xc3c1330b 0x2c4990f2
+ 0x50735cca 0xb9e45d2f 0x63c8c276 0xfe0b5168
+ 0x7c54350d 0x0cb05c93 0xee247fb1 0x40a2c610
+ 0x22a00f5a 0xdb4d1da6 0x2086a88f 0xd9fa3196
+ 0x9d4cb1c7 0x59d40f0a 0xf52294be 0xbc8d5d0f
+ 0xead98b7e 0xd31ff3dc 0x4e32632c 0xb9836653
+ 0xeae227e3 0x1e334cf7 0xe5ee9187 0x479d5dd8
+ 0xadf733a8 0x12c0a7ef 0xe8307249 0x8d72f210
+ 0x3336e271 0xbcc12da0 0xb8d52e29 0xe94a46ae
+ 0x5926aab4 0x7a929d80 0x60acdcd9 0x9031695e
+ 0x76244706 0x48c3995b 0x17f9966c 0x3c1a30f0
+ 0x50c0a42d 0x4ae56578 0x1a81d4ab 0x1395c82e
+ 0xdf92c366 0x90a188ac 0xe2f83649 0x5696676d
+ 0x7a507ba9 0x45f0e0ab 0x2d68a9bb 0x65d50b4e
+ 0xa684fa7c 0x63a04a35 0x0f73e4ed 0x1859da4c
+ 0x242dfeaa 0xffa2815f 0x04e5ffa2 0x30d55d0c
+ 0x559bbc55 0xe68b716a 0x7dcb07a5 0xb1d3c43e
+ 0x5b1bc142 0x77656508 0x5f03d2a7 0x13c21c86
+ 0x008bf74a 0xe2f5bbf1 0xaee8a9be 0x9bd33d42
+ 0x435aa8bd 0x9e8f958d 0x4a7a566d 0x5b2356b4
+ 0x4be34fc7 0xac3f87f7 0x7520fbfe 0x351f4afe
+ 0x67476a0d 0x64d18e88 0x71bd9d70 0x9da2e4b6
+ 0xe7c611c0 0xf009f13c 0x8eb98619 0x74c22cbf
+ 0xfe9f40ce 0x23864c9c 0xa0d7777b 0xff87bcf8
+ 0xe42e3b0b 0x9c7fe855 0xfb365cf3 0x0ae87000
+ 0x39558461 0x5a7fe922 0x52fb616c 0x1dee6ae8
+ 0x430c550c 0x0a30532a 0x87403149 0xb708a4c5
+ 0xcc1ff466 0xcfca59a9 0xd743b0bd 0xa7e0f484
+ 0x6e7ee3dd 0xd5f919e4 0x9015fc59 0x39b566fd
+ 0xdd3f25ca 0x8dfc6741 0x9179d918 0xcf08d388
+ 0xe523b058 0x0c4407e9 0x25ae6238 0xafe9cf0b
+ 0x9fc29e7a 0x236c823d 0x607add38 0x8833fd32
+ 0x21c60d26 0x362de265 0xb6bfa503 0xbd27e44e
+ 0x5b6bf836 0xe0d35274 0xebe7908f 0x7e076c9c
+ 0xa34aeb4e 0x642898f0 0xc87e1a07 0x9bda87b1
+ 0x3721f746 0x65c1ec7f 0x3d0ae8a8 0x3115b008
+ 0xcb1a56a6 0xd1a76d04 0xfacd1b7f 0xe553744a
+ 0x057f2c33 0x13caeeff 0x209c5884 0xc3211b8d
+ 0x5a8c81d2 0x1e59cc0c 0xe7b42f60 0x510fc068
+ 0xd200fa5d 0x23193201 0x1e534fe0 0xcf2037b8
+ 0x6b6bd4fc 0x3e8e94c3 0xdbe1d38a 0x597d5871
+ 0xec0129e1 0xb3be9453 0xa400f9f2 0x6ce19ff9
+ 0x259187f9 0x24ec708b 0x5fc5f413 0x847c8969
+ 0x9fcf3fec 0x0cff18ab 0x4cefa78d 0x35266a04
+ 0xbee81833 0x32634f58 0xc9a7c8dc 0x614f28e7
+ 0x4dd5ace1 0x15fc0226 0x3f8b4aa5 0x05606056
+ 0xbdb5a3f1 0x851e10b9 0x2a6053e5 0x6df96185
+ 0x2cd9cf8c 0xe28d1444 0x08d79dea 0x18da1e61
+ 0xb59950fc 0xbbc8c699 0xae43972e 0x920023dd
+ 0x13008ca7 0x54b36917 0xa35abb2c 0xd4984b2b
+ 0x606083d6 0x4e49dabb 0x372ba59d 0x380f7bb4
+ 0xeb861260 0x7f0538b5 0xef69498e 0x83bac8b8
+ 0x2344d697 0x4f789a8b 0x2d98b057 0x4e94ee3c
+ 0x983d7fee 0xaee49b46 0x00de7dcc 0x94c52878
+ 0x6f9e3754 0xaef4b9b9 0x6b46ee19 0xddb10fe4
+ 0x0dd24290 0x08f708af 0x3fb2e39b 0x3dace909
+ 0x84838754 0x94149bb0 0x2359b874 0x4e09221f
+ 0xa56ef81d 0x086f9c79 0x0d338c01 0xb2a91bf7
+ 0xaa4d6c89 0xf49969e7 0x6a509eb8 0x809ec124
+ 0x71563d2a 0x2b7dffbc 0x5bb334bf 0x18ebce8d
+ 0x3e434c67 0x4904d4c8 0xd233d209 0xca3cd2ba
+ 0x7c618885 0xf68cce7b 0x35adbff5 0xf61e3d48
+ 0x4cb3ae04 0xaa20201a 0x6f491596 0x0b934538
+ 0x16a605f1 0x57dfc39c 0x7aceebdf 0xb6082f67
+ 0xc36b7e2b 0x592f3f53 0xee3cf851 0x76ec175f
+ 0xabc73b4d 0x8d6dd974 0xca41dde5 0x74ab505e
+ 0x8c15f4c1 0x9d41aa44 0xcc8fa5d2 0xa570465e
+ 0xbbb630c6 0xfc977e06 0xa8b1775e 0x1f4dc519
+ 0xbabada41 0x91b2fad7 0x1135566b 0x567652f9
+ 0x1d0f955e 0x57c4c2dc 0x660bd5a4 0x59c92987
+ 0x9d695aff 0x88aac7a2 0x20308598 0x8e12997e
+ 0x29c5181b 0x53ae2439 0x7862d015 0x1626cc32
+ 0x10f95eb0 0xbb25f25e 0x03b241ba 0x9bdc7bd5
+ 0xf6106050 0xf5154783 0xe080521f 0x061e86cc
+ 0xb2ca16e9 0x915f0a4b 0x8f4325c9 0x1a5f2ac5
+ 0xc976520b 0xe0717cca 0x5ac6e76b 0x1f62f48d
+ 0xf31e76e4 0x8c3a146b 0xc87d8c2d 0x8ddee751
+ 0x8bf4db09 0xd2a686d8 0xf216b59c 0x911ecfcb
+ 0x65842c11 0x630e6a6b 0x48985e2e 0x9e94bce5
+ 0x5cb2afaf 0xe31d5ef6 0x7806074c 0x7744bf55
+ 0x1355a6bf 0x388865be 0xb9d900b3 0xea2bce11
+ 0xd0228c4d 0x816dd5f1 0xb3654090 0x6c296240
+ 0x5956a149 0x402672c4 0x42830ea7 0x8099a3ef
+ 0x1b0d2d24 0xc4180b6b 0x2228bf23 0x6ad12711
+ 0xb41611de 0x34c8b9e6 0xe301bdbb 0x495e50df
+ 0x809d2864 0xb3424c33 0x7399f498 0xc91b39d2
+ 0xfec47b00 0x2a2230d3 0x61341d6c 0xe7a75efb
+ 0x8aede4d7 0xb20cf7f4 0xfbef0902 0x4459ef58
+ 0x197445ab 0xa03e71a0 0x25f67b4e 0xddfcd1c9
+ 0x52f4388a 0x5af77420 0x8ffe5b18 0xa29fce69
+ 0xbb0a60e6 0x373b3ad9 0xa00e19a6 0x2db7e515
+ 0x1a77ced9 0xbd039c17 0x374d5460 0x9ec3a1e5
+ 0x77434c84 0x0c22e7d9 0x5fb76173 0x8646c434
+ 0xda49e7b0 0x03f47da2 0xc4e5ab4b 0xd3555a92
+ 0x9765dab9 0x4848b517 0x05c2b154 0x6e2b996c
+ 0x44964009 0x76fe7858 0xe9e8467e 0x1de54367
+ 0xd124abd0 0x41ae9672 0x521ae70a 0x5f7430a3
+ 0x44695344 0x576beff4 0x50ae299d 0x616c731f
+ 0x6144c083 0xf032bf4d 0x3e3cb949 0x7ead292f
+ 0x2151c92b 0xce4708c6 0x93bb3ef6 0x5795f4ff
+ 0xbc3ad2e9 0x5a65010d 0x0b96c64f 0xcc0cea06
+ 0x50e8a9ac 0x502fdfb9 0x03de0aa8 0x696fc1bc
+ 0xd8c23367 0xe966ac13 0xcdac2cea 0xb1103122
+ 0x902a809d 0xd876e570 0x197ca73c 0x6be80342
+ 0xe20bc0af 0x13558f40 0xff1b5f43 0x6c4968f9
+ 0xf707bb0b 0x2bda4cfc 0x51de4ccf 0xd9361c61
+ 0x2bfc555f 0xdbbd4b0a 0x4b9d588f 0x9a744c02
+ 0xd909ddcd 0x91a05ffa 0x2d8d4949 0x35aa9505
+ 0x9c6364fa 0x95515e59 0xace63492 0x9e33a345
+ 0x724cc057 0xb9d449f5 0xa20f8526 0xe2ed31b8
+ 0xa0e9d2e8 0xcaf765ee 0x247314b6 0xd91fad82
+ 0xab9236cf 0xea5ee132 0x10c8ed58 0x71faf9e0
+ 0x7dee7eaa 0x2470519b 0xd4c9d2e3 0xc56cc95c
+ 0xbf1a9b60 0xc170f2e7 0xa8505838 0x863fcb43
+ 0x1208ca84 0x07781d9e 0xbd944838 0x460a62d5
+ 0x0fef3252 0xca1964ce 0xfaecaa6e 0x5312a7c3
+ 0x7ec09ecd 0x0e4a64c1 0x0e4379be 0x6b1c1bc0
+ 0x47170f9e 0x12615e56 0x97d30146 0x6cdd0cd5
+ 0xb012c33e 0xd1d11658 0x11609a29 0x064562b4
+ 0x869c8b99 0xf4e59989 0x84fdc9ba 0xddd6bcf6
+ 0x5496a219 0xdb079dd5 0x244e6776 0xb0d8afe5
+ 0xf14dba52 0xceec92d9 0x73d66ca5 0x55a79142
+ 0x844cd92d 0xf79ced97 0x1857b9dc 0x9addd16b
+ 0xcb87c2d4 0xcc47c5c8 0xf6216778 0x047364f6
+ 0xa3f057e5 0xc47f4b92 0x49b65696 0xc8476f0b
+ 0x6150cae4 0x83e956ee 0x84952a17 0x32c001f4
+ 0x12e6c124 0x8733ed63 0xa96622de 0x2b97d312
+ 0x3c93d154 0x4a43719f 0x5c94d4a8 0x89138d7d
+ 0x59287d4d 0xb6be0aa5 0xe38463da 0x0ad5cb61
+ 0x10c3dcc2 0xa649403f 0x763dad43 0x15e8796e
+ 0x23fed728 0xc65881e2 0xcae78b38 0xecbfa6a4
+ 0xe9f4d662 0xb49b7fae 0xbfe36a20 0x9e1034dc
+ 0x816472f9 0xb3cf5e3c 0xfd9ceb35 0x64985d38
+ 0x28e5462d 0xe617f874 0x9d1cc79a 0x14987e3d
+ 0x48847394 0xe396e54d 0x2a9d37e2 0x90d2c038
+ 0x4680ae11 0x8ab15c2d 0x12e5372e 0x18b67728
+ 0xffd655a8 0x8c0aeba6 0x42c3e703 0x996c63e2
+ 0x0a5ff71a 0x242c4779 0x33068ece 0x59abc18b
+ 0xea60c431 0x5992a226 0x5041dccf 0xfec6e22c
+ 0x11146c09 0x77be906c 0x82879c44 0x51129cc2
+ 0x77a9a0dd 0x3c68d1ca 0x02049622 0x10cb7324
+ 0x9309b245 0x42bfb895 0xe011f9c4 0x0a907dc1
+ 0xc3351de0 0x2385f003 0xf2d22a22 0xaa760f2d
+ 0x38d628bd 0x71ef5bd7 0x37127450 0x446928a8
+ 0xbb88d4d1 0xf46e188e 0x224cd2a4 0x4f56954b
+ 0x70674ab6 0x9be90549 0xafd18245 0x4689e00c
+ 0x07d8e74b 0xfe6a2759 0xa6847004 0x7025494a
+ 0x2ef97b21 0x8aabbf03 0x46cdad16 0x2b300203
+ 0xa22dcb97 0x2c643664 0xb721cff5 0xbfaa532b
+ 0x9173a582 0x0a7c7658 0xbcaa4bd2 0x3c4c82ea
+ 0xc1b1ebe2 0x1000d5db 0x178850da 0x2276213d
+ 0x1cde5666 0xecdb0d8e 0xfef90d48 0xecd4d1f1
+ 0xa96103b3 0x935c5a02 0x8e6fe155 0xd047165d
+ 0x3002cf6e 0x9ae52c60 0x62cc7175 0xcafeeb88
+ 0x826c0adf 0x4ea5baa1 0x085a2723 0xaaf5f994
+ 0xbd599d45 0x8c7084ab 0xff2acaf1 0x96fe0230
+ 0x4a22f285 0x710eb741 0x3f941922 0x0b2ca014
+ 0x6b6619ec 0x1ac478f2 0x7d74461f 0x89668c79
+ 0x3b9edd59 0xf51c425e 0xff6e246c 0x915b68ee
+ 0xa1142d51 0x62409991 0x543f5f49 0x8579d5f8
+ 0xf97989e0 0x98d23c87 0x393a9364 0xe56329cb
+ 0xf62cd0a4 0xaa01e22a 0x5bc6c70e 0x1db499e2
+ 0x2e35dc25 0x88d5fda4 0xb9204812 0xe282e4e8
+ 0xee44d3f9 0x7c2374ca 0x9558fbe2 0x0df70c02
+ 0xe78efdfb 0x4caf264e 0x757e955c 0xa06a145d
+ 0xcdb5abc6 0x10633804 0x381ef262 0xee9d22fd
+ 0x1922ed89 0x17c41f08 0x78db4265 0x47353c26
+ 0xd741f54b 0x98f1e3c0 0x2843a6e1 0xb9fc4eff
+ 0x30ba0638 0xf1e2fb9d 0x8c8f03c3 0xe300fa41
+ 0x2a0b4a8f 0xaa66ca88 0x0372d9c2 0xbf1b3283
+ 0x6d7bb883 0x073b7f90 0x90ea76ab 0x7adf3d37
+ 0x94b412d4 0x2b788f5e 0xb76fa8cf 0x2ee0492d
+ 0x2d30b5cc 0x097cb48c 0x26147e08 0xea57884c
+ 0xe1bb97d9 0xd671b4d6 0xb9f45ee6 0x709ed07b
+ 0x89e791f7 0x50a0abab 0x59bba13b 0x4c95ba8d
+ 0xf06faf1a 0x9eba91ea 0x203a0896 0xe9180d97
+ 0x2c747ad1 0x2bd9fdc3 0x9b66ccaa 0x511e730c
+ 0x4d4afe59 0x261d4191 0x431f33e2 0xa537e847
+ 0x07f3db81 0x0c553226 0x8fb5e7f5 0xdf27bec5
+ 0xa91bf277 0xafb9ea61 0xc0c18350 0x96ecd71e
+ 0x65713a84 0x913d77e0 0x740d13b7 0xb7524399
+ 0x96d50b1f 0x3c33cc3b 0x1ffd3ccc 0x220fe9cd
+ 0x13ff2a0a 0x7737d122 0x282709bd 0x66aae30b
+ 0x2578d841 0x73c6ae19 0x77d5a00e 0x54705866
+ 0x702c38d0 0x642437ab 0x97888628 0xc92ef39e
+ 0x05ff9fc3 0xeee7a2e0 0x08c849c4 0x842988c7
+ 0xff8e3d16 0xfa73e115 0x7a152edf 0xb4191cac
+ 0x0c9eea26 0x5dbb6b97 0x922fc1e2 0x3c727b29
+ 0xe447a6d9 0xe6428089 0xa1c2a174 0xa4b85d60
+ 0x5f08cbdf 0x2015182f 0x754c5beb 0xa06453e0
+ 0x20493816 0xdf17b930 0xf55bbe8d 0xdc28116b
+ 0x7c8b4c37 0x87ea1da1 0x8268b17e 0xd4c4fe34
+ 0xe2df10c2 0x240aa809 0xb0916d20 0xe96f934c
+ 0x8cc175b4 0x478cf279 0xae91f6ac 0xe09c1b44
+ 0xdab45144 0x6fd51ca0 0xda83d37f 0x37bf81df
+ 0x52fe608c 0xb3f37371 0x156d69d5 0x12b9c82b
+ 0xe7bb0089 0x01ae780d 0xe3f7be6c 0x32989ddb
+ 0x971fc124 0xd9048910 0x7166fe08 0xd2724c31
+ 0xbd2596e0 0xf7b5d8f9 0xcbb76a30 0xdbbbe890
+ 0xe506ffa8 0x5932d8c4 0xea064da2 0x881c72ee
+ 0xae1ea9f6 0x50a5c29d 0x5388f42f 0x213b990b
+ 0xeb38f978 0xfb81832a 0x702338ae 0x9264d6c0
+ 0x9640aeea 0x4f01ee0f 0xd99fe781 0xd9e8b556
+ 0x35653091 0x0e2287a2 0x90b7f886 0xd4bcded0
+ 0x4b964aeb 0x95271c62 0x12c8860d 0x196c92ca
+ 0x8e4edf59 0x4907f388 0x9d275902 0xb9009a4a
+ 0x30ecdf04 0xfbf86b10 0x94b946bc 0x5757c752
+ 0x916f5c3d 0xd4a080ea 0x7dceecff 0x42dccf57
+ 0x97ae2be6 0x4052d8f2 0xfb5cff0e 0xacb3972f
+ 0x2fdbea67 0x44fd0087 0x2c8dd356 0x702872f7
+ 0x5bdf98ba 0xcd436c1d 0x4cf42708 0xbb9b848c
+ 0xafc7e684 0xe0ae15e5 0xbe77beb7 0x5465f78d
+ 0xa1a5c3de 0xd7d1bf37 0x293dabee 0xd83985ff
+ 0xb966b1e3 0x77908298 0xc814783b 0xf43be773
+ 0xc7704e0c 0x7f6d46b0 0x1e9eae7b 0x2e110f7b
+ 0x2c3e8cd4 0x198263e4 0xf49bbfe0 0x1ddf332b
+ 0x2619d305 0x1c4f083e 0x218695b2 0xf6e9eb91
+ 0x2bd46f27 0x8c903e19 0x77c69dc8 0x49ad5596
+ 0x9b1e4064 0x33af259e 0xae57d885 0x0f89d69a
+ 0x1a3c21c4 0xfa8d3523 0x33e1e79c 0x466a8b05
+ 0x5318e75a 0xa64c31a2 0x9e8b489c 0xfa3dd512
+ 0x19b504fe 0x087795ee 0x1a1119d7 0x92fd5dc4
+ 0x161db69e 0x9b8246ca 0xa4f164c7 0xfa1310b4
+ 0x7c761994 0x07a9bfd9 0xd76cda4e 0xd220fd89
+ 0xfac3a0ab 0xa35fd4bb 0x103319e7 0x113cecac
+ 0x8a0b2dcd 0x39001a5b 0x803e3006 0xbe2e8a0c
+ 0x256961a0 0x40cf27e4 0x4229799d 0x14a30f23
+ 0x23d80ad7 0xbb1082b6 0x1325fdc2 0x41082eb9
+ 0x2c531bcb 0xd1c2c909 0x6b68d5ad 0xc7cec053
+ 0x95119d6d 0x8cc85ae1 0xfd204466 0x0dd7b4e7
+ 0x930de6b2 0xf0386cb7 0x09867321 0xea6aed3e
+ 0x0bc79d5a 0xb2d88c9e 0x387fc5be 0x264b3e24
+ 0xa962b5d4 0x6f6fc6d9 0xa1b8a9d4 0x65b61263
+ 0x91383a61 0x6b1e8571 0xbc902055 0xbc53cf50
+ 0x4fe8e29a 0x048ff6ea 0x9a7d949c 0xa83ceee6
+ 0x25b5c85a 0xa10a7511 0xf606a949 0x57b41656
+ 0x230afe7f 0x73d65619 0x9819c9cb 0xea609f2c
+ 0x4bf6fe21 0x4de72091 0xc439faca 0x58ac932d
+ 0x36944d39 0xd046acde 0x8495bc22 0xdb20e8e7
+ 0x537d1619 0x8c96eb24 0x8f0dbb8c 0x2461b9b8
+ 0x1f9e9c0e 0x0e58f1cd 0x196ecb76 0x7ce9198c
+ 0xfbea063b 0x06d810ac 0xa5acf2e2 0x2742822f
+ 0x17aa581c 0xb214addc 0x6b8da387 0x3a66dd9b
+ 0xa28ae955 0x347f5607 0x755e2679 0xd76cc2e3
+ 0x80a38077 0x2a85effc 0xc42f63c5 0xba4f0c04
+ 0x2df3075f 0xe119e31b 0x74c09c92 0x8f0de61e
+ 0xfd1c0d09 0x0e03f74b 0x3730c527 0x8913961a
+ 0xda9a8573 0x0d060655 0x41e91539 0x2f145441
+ 0xac24e688 0x71df76c3 0xdd88e778 0xd082154d
+ 0xcc87a1cc 0xca1d5469 0x55a9d11e 0xa1496402
+ 0x5328879d 0x01130306 0x0fb6e89c 0x6a88d6f5
+ 0x2c35d644 0x64787df8 0x0cda642c 0x050d559f
+ 0x34d986cc 0x4d46a0c6 0x16958610 0xb095b7f0
+ 0x42344d4a 0xaebcc04d 0x38cd1303 0xf55ef5fd
+ 0xa2229e10 0x1c84dd21 0xc751cdca 0xe70e4d92
+ 0x7cfbc446 0xc346c504 0xd1d0c3d0 0x1a11f80f
+ 0x4c3d3092 0x860608e8 0xc629974d 0x36b7ba9b
+ 0xa6954e66 0xcddd2377 0x2484d0e3 0x16364b7d
+ 0x9f5cff4f 0x510b68a4 0x3f66ffc0 0x3fd56799
+ 0xe0e9ee0d 0x2733808f 0x91e062f9 0x0194bacd
+ 0x7d0758d6 0xe5c3b76e 0x877cca91 0xb1c6caa6
+ 0x6d8390c1 0xdbef1e02 0x4900b2c5 0xb9d48fd0
+ 0xb86444ca 0x4b32cf44 0x9d52f809 0x5e465a79
+ 0xa654d13f 0x5005bc4a 0x2ff38509 0x90a06923
+ 0x567912ad 0xca101885 0x9d2362e7 0xf5dcd206
+ 0xd8b2de97 0xc9cfbff2 0x850b73b9 0xa9cce812
+ 0x1c89f5c1 0x0e93ca25 0x26977294 0x00651015
+ 0x3b6ac439 0x2454a988 0xff2cdd4e 0x0d90452a
+ 0xbc9f8a09 0x93f1c4dd 0x650c020a 0xfb9b37df
+ 0x2f7211bd 0x9cfce13d 0xb02cb359 0xe149b294
+ 0xe6c478d6 0x0ba8d9e3 0x3e8d6b1c 0x28549a36
+ 0x5b389e02 0x92d73111 0x33053a24 0xfb4295e8
+ 0xc31f642c 0xcce6d7b1 0x19256f9b 0x05af3c0d
+ 0x46c876d7 0xf3cb570a 0x5b3419c1 0xeeaf101a
+ 0x2415133a 0xa5e5d7ff 0xdfbfa790 0x5fb1acc9
+ 0x4b411267 0xfb5f01ae 0x44c85d60 0xf574f2be
+ 0xed6951a3 0xc72b9616 0x7a400d1f 0xafb1f5fd
+ 0x036d3f4d 0x00426a64 0x10152052 0x16fbc209
+ 0x5eb41a25 0xbdd91d58 0x23a593da 0xe99994ed
+ 0xe1dfc74c 0x2ace293f 0xcffca29e 0x3f9eb981
+ 0x46b74da1 0xa08addc5 0x2e4db3cb 0xbb35bd91
+ 0xcf047df0 0x9f000bc2 0x095cd891 0x0e8b0afd
+ 0xdc862db2 0x381de055 0xfe5b209e 0x98a6ce93
+ 0xe07ec88a 0xed2dace1 0xb5f6ed90 0xa59a3995
+ 0x3987443d 0x56650b10 0x0a8c01f1 0x28599c21
+ 0x51817fe4 0x88ac9845 0x8a5d7b55 0x89a15b17
+ 0x0457e30a 0x9ecfdfff 0x03c7290e 0xf14c569e
+ 0x88963e60 0x7bc5e18d 0x595ac0c1 0x29f34d31
+ 0xd0870bde 0x58fb1622 0x2736799a 0x20c6ab00
+ 0xfd606ac9 0x5931c90f 0xe93eb3aa 0x78f4fdb1
+ 0xe3c0b354 0xb02dcb2e 0x028635b1 0x6084413c
+ 0xbd262370 0xdd84b981 0x50f4cc00 0xc2a13e6a
+ 0xf195d7d0 0xa568ace4 0x3506ccda 0x1a7b1e49
+ 0x6b623dd4 0xd5b43db2 0xbd2db225 0x5fc0873c
+ 0x07b0e0e0 0x8a7c7240 0x51d21461 0xe39acfe0
+ 0xe8b1d0dc 0x319cc88c 0xdbb0501c 0x2d530ef9
+ 0x6796f013 0x8d7c42e6 0x64840fc6 0x95f18131
+ 0x14128fee 0x06ed7694 0x053701e1 0xa113706b
+ 0x7efa1437 0xd988408b 0x15a55f2f 0xdf2da6de
+ 0xe1637888 0xa6eb0132 0xe5a49f75 0x13421229
+ 0x76b358d6 0xfd430ce4 0xe4b54719 0x4d373720
+ 0x2363e083 0xc7c3365e 0xd2c691a7 0x337ba782
+ 0x85f0e27b 0x6f270f7b 0xda2e7bd6 0x86aa4e8c
+ 0xfccea641 0x4ccffdd1 0xfba17e58 0x48f98550
+ 0x7fa85f31 0xabf971fc 0xd24dd6a5 0x2a360f9b
+ 0x955234ec 0xe75f238d 0x76ce3dd7 0x9dcf7973
+ 0xd90c8737 0x23aa80b6 0x9e4f45a2 0xc8e22d59
+ 0x9e74d525 0x2cdeb43e 0xeddedd26 0x14b8ca5f
+ 0xd42f6bee 0x4ea5803f 0x772d0ebb 0xe7990ff2
+ 0x02e47c5b 0x1c88d149 0xef43755f 0x6482ddcc
+ 0x1aa8c862 0x169fd30b 0xfe19600c 0x79253784
+ 0x61d94629 0x078a3859 0xfed2680b 0x8bb14474
+ 0x9fe0981b 0x0e4cb157 0xbaaedde2 0xff3711ec
+ 0x1c03dfb4 0xdb4f9346 0x67faa4c0 0xa9fda842
+ 0xd1a08a3b 0xb675f6e9 0x2eed32af 0x54169c1d
+ 0x2ab8047e 0x0fa33847 0x69c4eda5 0x4f47713c
+ 0x8186f17c 0xc68e0d8e 0x1e512fa9 0xb200eabd
+ 0xefe05879 0xec521f72 0xc3b7670f 0x06d96a0e
+ 0x830dd6f9 0x293926e7 0x49355c40 0x4bfa924b
+ 0xb19404fb 0x4cfcf114 0x39f09bee 0xc5959edf
+ 0x17e43b2f 0x36b8cb37 0x48d36720 0x87142d1d
+ 0x4dcac00b 0x346a77e0 0x833ec251 0x180a0eb8
+ 0xec827f6f 0xd389e5b4 0x193666a3 0x40deb1ef
+ 0xeb287db0 0x59d72fdd 0x16c01b8a 0xb2f21a23
+ 0x78fae723 0x96704b79 0x1cfa8eb2 0x3174d946
+ 0xeceb41a1 0x8af02dd6 0x19b3cc91 0xfb452b01
+ 0x185564bf 0xadca8abe 0x5dc86f8d 0x6f8752d0
+ 0xef5c4281 0x57053d43 0x84ea5d02 0xb4d2053f
+ 0xd5f4c35b 0x907f2a8a 0x782ec949 0x773fd7bf
+ 0xb71de809 0x6ad67473 0xfc0f2916 0x7e011263
+ 0x8388249f 0xc222cf7d 0x1b8123e0 0x2315de70
+ 0xd8cdcf39 0x0181feda 0x6e39af97 0x0b77654e
+ 0xaa0c9e17 0x863fc367 0x0615d44c 0xe29b86e6
+ 0xa1948dff 0x6d4e1893 0x40db2923 0x4d9b1c95
+ 0x4803e7f5 0xfaff923f 0xc1031c3b 0x8ee8b451
+ 0x31288c50 0xab825d13 0x1c1473b6 0x08b41dee
+ 0xb714574e 0x574040da 0x583db761 0xd3d2139a
+ 0x9fb3f39f 0xa0cf0027 0x315521b8 0x4c1f5cc9
+ 0xdd80b461 0xf1460806 0x0f0ae57b 0x2b8258c6
+ 0x4578a951 0xc16a1b9e 0x147faa8e 0xc96ec7a2
+ 0xd03de9cb 0x8df8317e 0x0a619904 0xa65850b3
+ 0xff6b05f3 0x5f645c92 0xce69f994 0xa1846ae9
+ 0xaf8789ca 0x08dba3da 0x08dda80c 0xe8e396d0
+ 0xd9478844 0xc47706bc 0x2f56c392 0x0032ce69
+ 0x1e25b40c 0x07d67e34 0x2148bd55 0x9b196864
+ 0x7955790a 0xeed52b37 0x6e7bb914 0x3ffe3c36
+ 0xe65f8946 0xac51ada6 0xae9b3001 0x5bfd4896
+ 0x5d04baaa 0x744c6bd8 0xd8d6c510 0x25d25740
+ 0x1f97ac5b 0xc37f23a2 0x17fa1b4d 0xed300b12
+ 0xea71b408 0xceeed65e 0x96db804d 0x709d79ae
+ 0x20546660 0xbab82134 0x51d74293 0xc02a65c9
+ 0x0b1ec776 0xf2b31fc7 0xcba74077 0x4f0c1ae0
+ 0xc07f66ea 0x170f1224 0x4acb1ec3 0xfc7b9cde
+ 0x07e006ab 0x9da5ed04 0x8370e78b 0xc39691c9
+ 0xed854623 0xcfca7c05 0x3d2e700b 0xfc52eccb
+ 0xf5c71a7e 0xe4cc4143 0x9164e2b9 0xfa7fabd6
+ 0x505ff063 0x2859ed81 0x776b50ed 0x3b15d21a
+ 0xd2f03b4e 0x8315f3af 0x5269b9d8 0x31bd7c3f
+ 0xf99d8e31 0x7df70284 0x568956ef 0xbe3d74b8
+ 0x8fbed915 0xc4e227a4 0x689efb23 0x3d323ff1
+ 0xe225e3a6 0xe1fc3a94 0xf988514d 0x161b6ebd
+ 0x712dc25e 0x21aa2ce2 0x6c630ed8 0x789c1bbf
+ 0x7eddd464 0x2a79f889 0xc7c0f496 0xda39e80c
+ 0x6fc17a39 0xed41038e 0x42491e77 0x0097fdfc
+ 0x25083426 0x0ed5da03 0xa867753b 0xf2629247
+ 0x6bf18213 0xd33549e6 0xd127896c 0xbd2440ba
+ 0xba184a7d 0x5f534e5c 0x12fe02ae 0xe5234798
+ 0xb3e47348 0xad96a97a 0x177e5fe4 0x62a0ebc4
+ 0xf74d4d2e 0x2667eb23 0xca156680 0xc2d6ef24
+ 0x8b03cd6c 0x65cdd0a7 0x02a17a02 0x1e5d73df
+ 0x8d3d1985 0x634424bc 0x6e332211 0x8f619bb5
+ 0x2e57902f 0xfc18e1ea 0x5327dfc5 0x249904e0
+ 0x6c7e15d6 0x4c93e017 0x72b72678 0x47e3a4c5
+ 0xf925b0ab 0x861b9efe 0x2110a250 0x02d111cc
+ 0x01db264b 0xc78ffd32 0xd35b62ef 0xc5e26509
+ 0xaddc32b8 0x7384adb3 0x14dd80ed 0x6ea3c9a4
+ 0x8846201e 0x43f496e8 0x18dbde7a 0x9382de97
+ 0x2571ea26 0x73e1c559 0xbf0328fb 0xf54e01b2
+ 0x787b9baa 0xcda5ae3d 0xa7f7c5dc 0x794063e0
+ 0x6050f2e3 0x3d067abc 0xcd348208 0xcb7c206a
+ 0xdb0f590b 0x0556823d 0x9daafb23 0x68de4801
+ 0xdd3d5c14 0x153ae055 0x379ae503 0x05a4d468
+ 0x35a3809d 0xb41a49b6 0xbabb51f2 0xa9ade96b
+ 0x2eed4a4e 0x682e04cf 0x3fb8a3b0 0x71a6e838
+ 0x6b1924f9 0x2325ba72 0x4bc9513c 0xb95807c3
+ 0xc7e5c617 0xe0eb5303 0x22e25ed0 0xd86c0256
+ 0xbc03456a 0x985b81ce 0x9c2ecf75 0xcbe1292d
+ 0x12aee1a9 0x6f83c685 0x20e348a3 0x9576eb55
+ 0xad06f6fa 0x36293aea 0xf587b498 0x73e5eb09
+ 0xd47e5cfa 0x9379d70b 0xb87fa431 0xa4791f08
+ 0x003dd242 0xe64437bc 0xae50505a 0xc5a337ad
+ 0x9a63bf9c 0x9fb46dd8 0x06d6d6b6 0x1d557c65
+ 0xe19a751f 0x8851e1ef 0x88474420 0xbda6a5ca
+ 0xe5c570d1 0xbd520d15 0x9c991349 0x774847fb
+ 0x09062314 0x74ffcd56 0xf244496a 0xbc822fe7
+ 0x6619f249 0x19ecf3d9 0x0356ec07 0xc754b087
+ 0x0c2cc5b2 0x0a928559 0xa63defac 0x2a1016a5
+ 0x59f9579a 0xa32ac751 0x880156e7 0xfa98f785
+ 0x561f9243 0xf8ad3b44 0x88d09686 0xb7656804
+ 0x1d733be5 0xf835036c 0xd9854eb6 0xe3d3e252
+ 0xa335451d 0x6cef2f72 0xed2d8bad 0x40ccdac7
+ 0x026ccf2b 0xd8907e8e 0x6b9dcb88 0x6db1b016
+ 0x88b67853 0xf169c4f5 0x71d030fd 0xe3d0e64d
+ 0x331b875e 0x14156d9b 0x8e34aaf6 0x735eb827
+ 0x7d96125e 0x757b15ad 0xa501ab24 0xc155f8b0
+ 0x9c49cd8e 0x5a8e7118 0x74af8bb1 0x9e8de93b
+ 0x07687721 0x5ac42b56 0x3042d915 0xe30e20e2
+ 0x94a1e376 0x73d34595 0xce30d8f5 0xefafdcd4
+ 0x67a242b1 0x27dc9594 0xf8fae52f 0xc4f6ceff
+ 0xd0ffedf7 0x493359e6 0x1deda1da 0xb944d24d
+ 0xf483b532 0x40396343 0x312c13a9 0xfa616fdc
+ 0x5e318d6b 0x57bb126a 0x79433a17 0xfdae5d08
+ 0x24350f44 0x42b9819c 0x8c3e4914 0xb8fd955f
+ 0xb66519f3 0x03376aa7 0xc7b35448 0xec75d467
+ 0xf861dde6 0x75d9ebec 0xcbc3e8ca 0x5e6d47e1
+ 0xe7e499fc 0x6123c26e 0x19fe2cc3 0xde86af73
+ 0xf0de8655 0x230a6313 0xe484cae8 0xf160e445
+ 0x7c3ad8e2 0x29a2347d 0xcab560e0 0x737c2d14
+ 0xb60d784e 0xe34dc241 0x39124427 0x632bb7af
+ 0x150080d6 0x2988d6b3 0x435e4222 0xbc26852f
+ 0x2cd7e704 0x0e2a05b2 0x1c41169f 0x07c41b03
+ 0x0346f767 0xe96b6733 0x54dec6b6 0x8f2d3c90
+ 0x1fe618fa 0x75dddb13 0xc9ba2a28 0xe9cc9369
+ 0x2c8e53d7 0x3f781a20 0x5791014c 0xadebd041
+ 0x855aee45 0x996d5acf 0x9f7219fe 0x94a426a2
+ 0x779c04fe 0xd8a5f141 0x9ae3cc2e 0xce57a8ee
+ 0x4865de61 0xe14d8d5c 0x98389084 0x81bdf77f
+ 0x72aaab47 0xb11b1e31 0xb23c943d 0x65b0e428
+ 0x9d2fde62 0xd64cfc1a 0x9ded7094 0x1446e84f
+ 0x7b660a21 0xc26c252f 0x5ea92407 0xcc2dd193
+ 0xb18d6c04 0xe08faa12 0x84366ee1 0x53dd342b
+ 0x88f99d7a 0x97754233 0x54777ee2 0x72103530
+ 0xffb77bdd 0x67c3f3f9 0xd1e9396f 0xf7e91a5f
+ 0x1ca09c1d 0x148dcedd 0x4812f994 0x734bb2a8
+ 0x4c616674 0x79e0669c 0xcc3695a0 0x965c6b99
+ 0x54b4bfe6 0x24ff8fe7 0xf227fa4d 0xaeee1502
+ 0x2207334b 0x444d4768 0xd1c3e5ac 0xc635e962
+ 0xa5fdc383 0xd642360c 0x0bb1d6bf 0x40eb05b2
+ 0x563d58c3 0x37ef1c49 0xdbdef02a 0x5c954622
+ 0x249cd7d2 0xbc00f7b7 0xb9d311b0 0x84ebdfc0
+ 0xb777296b 0x8f922505 0xe3007f02 0x45369d3d
+ 0x1b1ef9ca 0x9434faf1 0x955491fd 0x918dae49
+ 0x2c55e53d 0x2bb5e664 0xe306a3da 0xe9a4b542
+ 0x74fecfe8 0x315d2566 0x42ce0ebd 0xfc8b2c09
+ 0x4503579c 0x0194db62 0xaae82e99 0x638cc58a
+ 0x6253580a 0xa9e134a9 0x7cf09364 0x2a0f2762
+ 0x555e0f4b 0xcaf84599 0x88ff57dc 0x760f71b6
+ 0x5f3b52b0 0xf8762c98 0x37d45f0d 0xcefbb54f
+ 0xc99699c0 0x54638fd8 0x5d116ae9 0x0b125847
+ 0x88aa62a0 0x8ac7b007 0xa97c115d 0x128e72e1
+ 0x035d5aa7 0x5d16a915 0x9f1ef842 0x8e23b89c
+ 0xb52d59c8 0xc048bbf4 0xca42c82d 0xdc85185d
+ 0x0011465f 0xbb025e83 0x9ea0ffe0 0xda4c0e4f
+ 0x89401781 0x7a3074d7 0x878b8546 0x9370c686
+ 0x5ca6f5ec 0x96808035 0xddb4682f 0x5a616b12
+ 0x57618954 0x0e3f255f 0xd3072641 0x8eed8068
+ 0xb8fdf1c9 0xb417e2ba 0x9c613492 0x75c3a921
+ 0x2e7e0223 0xa9a68825 0xef180ab9 0xe2550aff
+ 0xf743b61a 0x92b02868 0x2e4d4a92 0x094055f0
+ 0x5b901d5c 0x6512ecc1 0x1d6d35f0 0x114f6a1d
+ 0x40bf1f43 0x8e7ba25d 0x8cee3d80 0x5df565ca
+ 0x29403904 0x27cd7367 0xad48535d 0xa6e54d45
+ 0x24b9e3aa 0xe301871c 0x53e21f70 0x514fb2e2
+ 0x937c0248 0x82624d35 0xbbf2a9f7 0xd7b6e482
+ 0x21c76f4d 0x430c1bea 0x445ba31b 0x7732e9d2
+ 0x19175315 0x712cce54 0x56d653ba 0xe55361a9
+ 0x7543f198 0xa8f9e517 0xe8ec0529 0x4681a1aa
+ 0x3edd8dbb 0x8cec11b7 0x6b6f0bc1 0x8b9256a7
+ 0xb5e86885 0x1a2d632d 0x59dd488e 0x4d529b15
+ 0x87d3b0dd 0x3e334eb0 0x8ecc38cc 0xbcd42c7d
+ 0xee7b85ad 0xf8db1ebc 0xf7242be1 0x936c4ad5
+ 0xf0d3e133 0x15b21e10 0xe13ccd7a 0xafd28ab2
+ 0x86f873d4 0xe75498df 0x1cdcacc7 0xa0952f4d
+ 0x9c1aef8d 0x4c45d667 0x1ce18e2b 0x95e753ae
+ 0xd3cc14c1 0xbc9d6c08 0xb9bb31cd 0xc38cfc3d
+ 0xa0f90015 0xe71ec516 0x89996ee4 0x3ca7b1bb
+ 0x5cb81d2f 0xf83eba1a 0xd4c7f0ba 0x0fa3724f
+ 0xf70fc314 0x6bddc2b5 0x6b5b73ca 0x7fbeb86c
+ 0xdc04567c 0xbdee5488 0xa5e84cf9 0x2d923cd3
+ 0x10affb44 0x7072a096 0x569c6186 0x73b955ee
+ 0x5f51325b 0xdbe6d601 0x80a09027 0xdce073bd
+ 0xc4a57e68 0x8e36feb7 0xe95f03c6 0x24536972
+ 0x7e9d0914 0xae891f9f 0x71b00cfd 0x4ad1d3cf
+ 0xb0c12a1c 0xe6ae12ac 0xe55fae1d 0x41fa24e1
+ 0x26ac1069 0x07f63225 0xdc6af020 0x736be557
+ 0xbd81cca4 0x0d970e26 0x00aeee65 0x5a95aa6d
+ 0xe11d862b 0x73445f3e 0x9debc7c6 0xb9fb9316
+ 0x70c80f6b 0xdc3b462e 0x98e55897 0xe3c038bc
+ 0x1e6be1e2 0x6b73a471 0x6b08dee9 0xc11316c9
+ 0xa03ccd1f 0x9850a735 0xf6f69d7f 0x5f84661a
+ 0x35124e9c 0x580021ad 0x83f5cc8f 0xbf6299b3
+ 0x87a9300f 0xbfdeac53 0x3e71aa0f 0xef0f924e
+ 0xa05ccefc 0xdde79132 0xd37fab59 0xf09bd0f0
+ 0xe3d45f0b 0xd800d032 0x23b74559 0xccbaf882
+ 0xd7482f3e 0x19b61427 0x8812072d 0xc7b547d5
+ 0x3d77bbad 0x16a7a565 0x613512b0 0x1f5941d8
+ 0x15c469c5 0x6b594868 0xea78dc23 0xb7edca03
+ 0xec75b400 0x85960837 0xe295e802 0x442d5aa7
+ 0x1a505b0a 0xb7100575 0x126ab9c6 0x30fc8981
+ 0x33d1c5e6 0xe7b36f3e 0x2529f025 0xf7de09a4
+ 0x9a237b73 0x4199b6e5 0xcd0ca5cc 0x483c7496
+ 0x18a082e1 0x49d36b6a 0x29194f20 0x256236fc
+ 0x7ea67a7c 0xf9902240 0x29abc52c 0x58178309
+ 0x8d87c634 0xaddfa3ac 0x26a7582e 0x22a46c59
+ 0x30275956 0x823d736c 0xc3fd5992 0x49151051
+ 0x6f7e26a6 0x69f61e26 0x151611e6 0x0c0603d3
+ 0xd472a6d9 0x3b41cc64 0xb2cc8f30 0x361a119b
+ 0x2a6325f8 0x6068c424 0x770c3284 0x72ec88bc
+ 0x833bbba5 0xa70802ca 0x32a5545e 0x5c22e9d0
+ 0x5ab3d9f5 0x9007e5b7 0x24e39b69 0xd33bd9cf
+ 0xdc9d6e9c 0x2b7836d5 0x757c6cc8 0xcae907cf
+ 0x9e46c6d8 0x3bccb4b9 0xc66ab681 0xab9b12de
+ 0x366df0b5 0x7f785550 0x258959f3 0x3a72720d
+ 0xb4044294 0x11e76388 0x78006943 0x94321f26
+ 0x09e5d3f9 0x2f82cd05 0xdee1653d 0x39b9ec91
+ 0xc9012ee1 0xf885bae5 0x79493693 0x2b13808a
+ 0x5376c547 0xc997b444 0xc581c3d3 0xbad42d8a
+ 0x4901b3b5 0x968eee21 0x77455af2 0x10b0fa5b
+ 0x20d71f73 0x575412ef 0xf205f541 0xc551b8f8
+ 0x12773d9e 0x7561b494 0x8e5a2137 0xfa842331
+ 0xf4a22b14 0xfceb868d 0xc3f356af 0x99c600de
+ 0x9803462e 0x35bed02a 0x45f52576 0x3b87c4fe
+ 0x92846fbc 0xfe85457b 0x5c17ab10 0x06ce7af4
+ 0xced24e04 0xc0e6ae3b 0xb125d859 0x92364ba9
+ 0x3a0042a4 0x910bbb65 0xf23b6521 0x5c0fab3d
+ 0x3a3d8051 0xd213a5e6 0x16553ef2 0x3413123f
+ 0xf7bb2e3c 0x174d8805 0xcc640b23 0xc4713fdc
+ 0x9636237c 0xd71729a3 0xc301f9f2 0x63189fdf
+ 0x88e96526 0x71b83d67 0x5e819dee 0x03b95fd1
+ 0x50d95d14 0x6a3f8a67 0x23c337ae 0xe1863d6f
+ 0x6c4b54ee 0x2d361ae5 0x7fe534f4 0x95c737b8
+ 0xc9e50fe0 0x97c348cc 0xf007d43b 0xc6f9f79f
+ 0x23d80edb 0x921ba7d4 0xae2ae8e1 0x67a7d17e
+ 0x6773c41a 0x538aeedf 0xaae06e55 0x21150c78
+ 0x2e80e133 0x99361ca3 0x717ea509 0x039822dc
+ 0x18792613 0x55ddf173 0xc9c048be 0xd5e49d71
+ 0x8adbc8a8 0x81200c61 0x6ae354ed 0x1a708d48
+ 0xb349a77d 0x074143d8 0x2d0eac87 0xedacdf08
+ 0xa964c6e8 0x3848583d 0x7916be91 0x7be53a63
+ 0xe924661f 0x4fd00b9b 0xbfd03db2 0xb65d4052
+ 0xd33500dc 0x73a5a54f 0x93c2a984 0xe114df2a
+ 0x170408d5 0xecd50a31 0x9f20a1b1 0x34267201
+ 0xbdfce32a 0xd8006ace 0x9732c7a5 0x3334c162
+ 0x6ef73bfc 0xbfb4ae2f 0x68eddc82 0x2421d413
+ 0xa75f7db0 0xb68d99ae 0x3b77b2c4 0x2e5f5aa2
+ 0x18a02c7d 0xaecfaf69 0xa798a7a1 0x1710b58d
+ 0xdda63c42 0xc0b9f0c1 0x6e98ac03 0x0a6ec04c
+ 0x65b6d31f 0xbb420c7b 0x2d0ae4cd 0x073969fa
+ 0x075ab187 0x37ebf9a4 0x75b32e70 0xf4e3b50f
+ 0x072c13c7 0x629d6d10 0x692a9f39 0x9d424951
+ 0x7ccc6e4e 0x0df85aa1 0xaae96b53 0xf0fbe227
+ 0x79f4cba3 0x3a4cfe17 0x31005c06 0x2ee79ed9
+ 0x175662a2 0xea67d5f8 0x6a585206 0x74ff608d
+ 0x8d0e43da 0x46e465a6 0x8b3a1789 0xf58de200
+ 0x7470ee83 0xf4b3081f 0xcab7b26c 0x679c03c9
+ 0xb2f3e0b7 0x7b0ce5f0 0x54458cc9 0x10adf9d1
+ 0xc6418621 0xda7db924 0x42c87af6 0xca18ee03
+ 0xbbe316ad 0xffad751d 0xa90e2f31 0xa4f1b741
+ 0x79b692b2 0x51c015f8 0x1ec279e5 0x0b66f53a
+ 0xd873b167 0x86bb7c09 0x6250d31d 0xfc276aaf
+ 0x1b912c09 0x033c336b 0x5e23abfd 0x4f5c8997
+ 0xc674dd92 0xfa1817df 0xa56ca16e 0xec6b2cfd
+ 0x2feac778 0xc468211e 0x8b60ac67 0x712cc8fa
+ 0x4380f941 0xccc528dc 0xc71b2dfd 0xfb08d4c6
+ 0xd493c636 0xa7783d6c 0xc7df0669 0x716e9db7
+ 0xaf231a4e 0xda22d68f 0xe33184b5 0x3c207ff9
+ 0x0318cb6a 0x42e7c8d7 0x4397e1fd 0x6b178ba7
+ 0xf979d8e9 0xa968800b 0x3ef4c2f7 0x35386ad6
+ 0x1c02b942 0x7a320432 0x2b210df5 0xd2dcfeb3
+ 0x8151e49e 0x3fa01660 0x20b2c744 0x56869e1c
+ 0x536b6037 0xac6a3c1c 0x7da9b889 0x510a284d
+ 0x25e3a895 0x0dae3e72 0x54680194 0x5c8bac35
+ 0x95037fd5 0x0dc924a1 0x06eb65b6 0x7e094b2b
+ 0x34283775 0x5dd176d9 0xe30c266f 0x70249a10
+ 0x2652882d 0x07b82677 0x6f200cbd 0x7cfbde35
+ 0x7fb2004e 0x2c01c9cf 0x559cc8e0 0x61a1a572
+ 0xfe7ae6a6 0x3658fd46 0x1f72b09c 0x716562d3
+ 0xc3fd2552 0x4a7faf26 0xd1b88210 0xfcc8a888
+ 0x9352ada2 0xc9649b3b 0x864ef2f8 0x40c3cc52
+ 0x38c11046 0xf4b7b9e5 0xd3507c37 0xe0341177
+ 0x8b02f6de 0x61e57507 0x7dec5942 0x20e67c7a
+ 0x49c8d38a 0x6374e513 0xc4859401 0x3d83138f
+ 0x90721624 0xcc979f52 0x43770516 0x4ce44048
+ 0xfdcbbbba 0x195318d0 0xd4d67bbd 0xc3e3ca42
+ 0xa9a993ef 0x04cf3ccf 0xdd53b6fa 0x670788bc
+ 0x928dc8e3 0x459976f6 0x30afc373 0xaaa0421c
+ 0x25014ae7 0xf15ea02c 0xa745d8e6 0xf1e8fc13
+ 0x6e5d5330 0x2c6d628a 0x7a70b26c 0xe431d5c8
+ 0x688f05f9 0x13af38cd 0xcead3e97 0x739092de
+ 0xf947216b 0x9a7babcb 0x0ffb6763 0xa5aa9ae8
+ 0xf555aec2 0x9524406e 0xe3c1aa92 0xddaeab00
+ 0x9a8ed819 0x723cf554 0x510b9a8b 0xb0230e50
+ 0x84e77af3 0x5ad3fbe9 0xda99502a 0xd87fad7c
+ 0x90d91966 0x47afd789 0xc714548e 0x1bd44ae8
+ 0xb6bbffb1 0xe212610f 0xa7be9aa5 0x2d7a51a7
+ 0x58ad5cff 0xa69a29f2 0x56650abe 0x60ef1148
+ 0x41c878ad 0x99e7cdd0 0xf942c629 0xda11df04
+ 0x68a8d833 0x837dc701 0x21c1c80f 0xac3611c4
+ 0x9fffc67a 0x46b75e05 0xa297896f 0x5b461329
+ 0x72c55e08 0x9069d0f7 0x12e2bc4d 0x0087d348
+ 0xcbf33420 0xb4daf92d 0x852a7cd8 0x640647eb
+ 0xb08e6b2c 0x7f3b928d 0x4c01bc4d 0xfca759ea
+ 0x7106955c 0xcf4a3778 0x6f55efab 0x07447abf
+ 0x0cff9f74 0xd42ff16a 0xa03f4bbe 0x7dc27f82
+ 0x752e070f 0x573515a9 0xe666b080 0x993fc9b3
+ 0x0538fda9 0x5e4a60be 0x5cd19062 0x54dd5d8a
+ 0x534e1037 0x75fb6cdd 0xa1e2e1cb 0xa5697b97
+ 0x71e3eaac 0x78ebda0a 0x9909eff0 0xc8c9917c
+ 0xe52fdd67 0x99f087cd 0x25fc8e89 0x901c2ec5
+ 0xd35c94dd 0x2df236f6 0x1373f129 0xfa2de0f5
+ 0x9243449b 0x665b513c 0xace1a572 0x9058a604
+ 0xab37ecf8 0x22e84435 0x76a79cbe 0xd95909d8
+ 0x1b517a23 0x3105603d 0xf6a11df5 0x137c2f63
+ 0x444603cb 0x1d763abf 0xb71c6817 0x46b6a93d
+ 0x46a43774 0x96db6af2 0xa14bac62 0x695d653e
+ 0x99897538 0x6a5780ff 0x58415eb4 0xb907ecf9
+ 0x3cb7d6ae 0x4541d829 0x482562ac 0xc4de34a8
+ 0xbc2114e7 0xf54eacfb 0xc5b65bf6 0x7c7b3db6
+ 0x6c885294 0x5193ac1a 0x7e80e8a8 0x255e7372
+ 0x71935b44 0x70599b03 0x7240a62d 0xcc8ab48c
+ 0x4eda8111 0x554286db 0x54166dc5 0x7c8029d1
+ 0xf79fc09e 0x418c4256 0x045c82b8 0x2de3c54e
+ 0x32dac6ec 0x2a5ddc75 0x69be6373 0x22bf468e
+ 0xda52d5d1 0xb123f760 0x3c4d7690 0x5e00046a
+ 0xd3102e82 0x15e20bce 0x3425b5ec 0x4b28fe48
+ 0x6a942095 0x79199aec 0x566369e7 0x27821292
+ 0x3dba6081 0xf72378e2 0x8e06822c 0x59669bcb
+ 0xbc891709 0xc6af2d1b 0x909e57de 0x7ed2b997
+ 0xa06ce64a 0x0b09c561 0x00a1a65f 0xa11faa7a
+ 0xe7d1e118 0xfaeeb687 0xd05b4158 0x3b4c1135
+ 0x18c1016f 0x556841af 0x09d960f5 0x88a98a6a
+ 0x841d61e1 0x54c4a616 0x2ef515db 0xaa6f8670
+ 0xa1f4b97d 0x54bd1997 0x95ded232 0x82257303
+ 0x3f1565cc 0x65d285a2 0x2828f910 0x7a2290dd
+ 0x7f0a8e0f 0x96470c2d 0x8efdb971 0x790fa536
+ 0x90b9d2f4 0x615c9b2a 0x5ec4f5ce 0xc7489b5c
+ 0x2ab45d94 0xf7bb05cb 0xec8e149f 0x94bb8b1c
+ 0x1a6fb3ba 0x77d22379 0x82a8e9d2 0xce732d90
+ 0x7108cffd 0x03ded7da 0x06e86199 0x8e2c02b0
+ 0xcb2c0281 0x4c49ee4f 0x4b00e705 0xf828ee69
+ 0xaab31af5 0x275ee2c0 0xec247123 0xfded371e
+ 0x440d3f1d 0x201bd35b 0x76e6b8c1 0x7cccc245
+ 0xdc0403c8 0x2c539a1b 0x80db718d 0xb738778f
+ 0x489698c2 0x78928e8d 0x7f241403 0x83b5aa04
+ 0x99d19efe 0xc52c6981 0xee504664 0xab09e1a3
+ 0xf1d99af9 0x3987f801 0x6f666ccd 0x41ebab71
+ 0x954645a2 0x7d037670 0x2dae35fa 0x82b60622
+ 0x761d5e16 0x0a2aad58 0x9706d97b 0x1347e659
+ 0x274d4c0a 0x74e8f15b 0x63129b5b 0x901ad757
+ 0x8777b117 0x44e63d79 0x8bd3b480 0x07108a1d
+ 0x02e03a7c 0x923e9811 0xaab4b369 0x51fe2c08
+ 0xdc8456e3 0xfe49f3c4 0x2954e5eb 0xc54dee8d
+ 0x0f80df98 0x63aaba57 0xe45d04bd 0xb15d4d92
+ 0x2c8d9557 0xa04d0109 0x309ea608 0xcb0738c6
+ 0xe9dacd06 0xee68f11d 0x693a4dbc 0xb11287d6
+ 0x1a2e0e76 0x10fdf2aa 0x9c7ea896 0xfd6d6a64
+ 0xb45df9bf 0xb55eb016 0xec82d40b 0x8d1ed23b
+ 0xff38e0b7 0x9e330c13 0x7d537ac1 0x12cf35ac
+ 0x6e6c90ee 0x2941504e 0x783385a9 0xb311af56
+ 0xc08a6072 0xcd4f0ef2 0x3e076723 0xff3d56f9
+ 0x161acea2 0x2eff759f 0xa506452c 0xa5a71901
+ 0x658eaa33 0x6ff385d3 0x57b6eb6b 0x6d66aeff
+ 0xacf53aed 0x74eb0676 0xb47ca784 0xfde6497a
+ 0xaba4fe9b 0x29f52e2f 0xe785df06 0x1a21f65d
+ 0xe339fc97 0xbff4f394 0x635c50a9 0xe7993eac
+ 0x169f7568 0x9afbd085 0x3790fd86 0x89708c40
+ 0xaf08378f 0x8cddfe3f 0x512e5e7b 0x2ccac57e
+ 0x432d49a7 0x922fe1ac 0xd0f7416c 0x2cf9ea13
+ 0x0fbad9e2 0xb9282867 0x1bcdd5f8 0xd50eb8c4
+ 0x6ee9c0af 0x1a109a02 0xa233e0c1 0x77cd4e43
+ 0xfd9876e7 0x81c98fd0 0x226a35bb 0xfb975e44
+ 0xc5e290a9 0xd2f46341 0xcfb8d819 0x66a7274a
+ 0x94e02e2b 0xdf3ca2bc 0x2f1dd3af 0x78462257
+ 0x490f62c1 0x5ea11bd1 0x23d01a6c 0xffb348fa
+ 0xda323bb3 0x17fce38d 0x8924bbc8 0x37c696ae
+ 0xc35e964b 0x696ecb76 0x63e8f910 0xe1ba966a
+ 0xb3b00602 0xf47e8114 0x2615a30b 0xbfaeabe2
+ 0xf8d5020f 0x12781ee1 0xc0ab16d5 0x90020b18
+ 0x66845dd4 0x6e66a277 0x8572a535 0xf7797d8c
+ 0x348de75e 0x86f89a83 0x64848b5b 0xd7dca20e
+ 0x57d60248 0xd8e4fe98 0x3a17c717 0x176435b5
+ 0x52ab4735 0x6f9f35f5 0x615f63aa 0x48cc2329
+ 0x5aa3897d 0xee9999bb 0x92a2bb36 0x8d40208f
+ 0xc76f48e7 0xe648c445 0x782c5ae6 0xf83280d7
+ 0x47f0d558 0x8deffa11 0x6524c319 0x9f60b5f2
+ 0x9a6b7d9d 0x200e1d14 0x88d0c8a2 0x38506369
+ 0xfd64aa87 0xecf06513 0x8a26932b 0x8b27c57f
+ 0xcfbff561 0x4ee1d390 0xcb61a62a 0x490d373f
+ 0xdc60f0ee 0x457fa88e 0x804c0d6c 0x71b52b54
+ 0x9174b1a3 0xd63cc831 0xb65bbb2a 0xe47078b0
+ 0xf526f67a 0xa722a8d7 0xb3f347ac 0x443ad7af
+ 0xedb9147a 0x4393902a 0xbab30f17 0x2ac69afe
+ 0x41fa55ff 0x88d1b1aa 0xa3dc36e3 0x9cbb4707
+ 0xedff1826 0xfa80b980 0xd15aa9ba 0xcc5565df
+ 0x71d1097a 0x1ded7d44 0x515af4f4 0x91f132a2
+ 0x3833086b 0x0778bb7d 0xb50b443b 0xc42bbf30
+ 0x0de19bda 0x7a2278d9 0x98452188 0x7f5e566c
+ 0x428c699a 0xdd3082e5 0x57ffe68f 0x51faa68f
+ 0x6e57e480 0x709147bc 0xdc526111 0x1d01f1fb
+ 0x199410a3 0x75a82d1e 0x35e77131 0xbfb66d4d
+ 0xd20cf839 0x17a00050 0x13020cd7 0x07738d81
+ 0xc03ce801 0xa4336caf 0xc86ffe7a 0x5bcbc12e
+ 0x9b7efdf4 0xa7b61193 0xe029ff62 0x29a61ff1
+ 0x80b9e172 0xaa3e57bf 0xad1d11d2 0xce16c606
+ 0xa92322da 0x16b79015 0xc4c6e8c0 0x27ece292
+ 0x830bbab2 0x941a8f76 0x9d765045 0x9cd9aad9
+ 0x5bdf199a 0x388659b8 0xc21a9647 0x3ca3e970
+ 0xea948455 0x7e962f48 0x05aea56f 0x50933a6e
+ 0x32f844ea 0x00925b86 0xe1e520b0 0xddff7542
+ 0x9670ee54 0xe9ccf36d 0xfdcc295f 0xe328ac55
+ 0x5b9a5638 0xf2caf15a 0x4f369aac 0x15d9eb8e
+ 0xb57ba439 0x141f2467 0x02691964 0x4a27215e
+ 0x049827da 0x1c06854e 0x9a1a7f56 0x227d90ad
+ 0x585d7d0f 0x02120773 0xb76a4d3f 0xee4fd64f
+ 0x7f94945a 0x0ec9beb0 0xfec85f9a 0x01d52eea
+ 0x11269008 0x417decde 0xb66ff3c2 0x6ec6d1de
+ 0x180cd9da 0x733ecaa1 0x9cd6385d 0xd9caa54c
+ 0x4d8d26ff 0x85f4fdf7 0x48196b4f 0xcd1ceda8
+ 0xb6c7c863 0x5c3671f0 0x10784425 0x0311bcb0
+ 0x5e3f100d 0xd88aaa51 0x12e0eb23 0xc29a35ca
+ 0xa1790cbf 0x3d9e3ca6 0x8b773d4a 0x0c8b4f02
+ 0x79a0dd34 0xc8780264 0xadf4a473 0x9eb41db7
+ 0x89f3aa34 0x10c7c008 0x08279d39 0xccbbffe6
+ 0x306be328 0x52d44c5c 0x73cfae89 0xb5c82711
+ 0x5d15bed7 0x3a4e311e 0xd9d7046c 0x9254b741
+ 0x42018289 0x5fa67a0d 0x85b9a2ea 0x419b7b3c
+ 0xe8821339 0x36f5a2e8 0xb447d566 0x553340e3
+ 0x3132df32 0x48d0deab 0x0bb49158 0x75355135
+ 0x3aa4c569 0x3cb9ac54 0xa73a9867 0x5e4899e4
+ 0x2615816b 0x0604b573 0x9c070767 0xd26356e8
+ 0x53933261 0xa6175afb 0x1632f9c3 0x2bcab1e7
+ 0x37c57c51 0xe97811e3 0xb719360b 0x51ab2348
+ 0x39aca372 0x5f0451f8 0x1068d924 0xf622d0d8
+ 0x723b6015 0xd08141b6 0xc12c5c86 0x5d9c54c9
+ 0xdc5f75de 0xbf48170a 0x5bf2c552 0x67c44ec1
+ 0xe3cbe281 0xac7d823c 0xa0d9ed54 0x8d5e7191
+ 0x119b69d1 0x81bc5077 0x70ab7567 0xe64e4de6
+ 0xe8dad08f 0xb0885ce4 0x5d4df047 0x6a505a49
+ 0xc90979d5 0xba8bcbb6 0x86357aaf 0xa35de476
+ 0xcc238d23 0xee718054 0x95422094 0x92f40612
+ 0xbce5dfc3 0xbfda5955 0xc1110667 0x33832607
+ 0x923d8479 0x0819e80f 0x6ecb452c 0xaa408266
+ 0x859e7e19 0xbf885a99 0x8ed80943 0x5717a581
+ 0xc3f68967 0x72443b1b 0x4116229a 0xaa61a840
+ 0x18f78912 0x032c14e5 0x5f3b85eb 0x28662050
+ 0x0b10d6c9 0x3435eba6 0xc620a491 0x40ace7d3
+ 0xa960f987 0xf17de397 0xcc385654 0x1c5ab258
+ 0xd855b9a4 0x1a431ddb 0x39842fa4 0xfc639afe
+ 0xf3ff2d7c 0x0bfd7666 0xdb189c2c 0x8c529267
+ 0x8a4e8b6d 0x28b9c6e9 0xbe497951 0xcec75e71
+ 0x96f3c1c2 0x72f16e15 0x946a9fed 0x12b84763
+ 0xdf5a28c5 0xb5964d08 0x6135ecda 0xbe070220
+ 0x3fcb729c 0xd29323d4 0x7759247b 0x5e5492a5
+ 0xeac7b650 0x4c34a70c 0x5a97eedd 0x26bb2fed
+ 0x7cc4b125 0xb89cd8da 0x6cf8e4b2 0xafefad13
+ 0xc39a73d7 0xca78640c 0xe866bc2e 0x06e9ffe8
+ 0xbeae327e 0x48be3d47 0x9b795815 0xb8f41c1c
+ 0x26562469 0x26840fb6 0xe1b315b0 0x72c869b3
+ 0x199c61cf 0xdb0be36f 0xe748b500 0x1580d2b9
+ 0x6dfd3b43 0x5c02e6a7 0xf9720399 0x2c686d4f
+ 0xabda5878 0x1652d37c 0x202fc972 0xae9dd35e
+ 0xe805bc3f 0x24352d9e 0x1dfea6de 0xf7d81750
+ 0x48b2ed34 0x8ac388e6 0x5283720d 0x09b4fb5a
+ 0x1b94cb22 0x3bf2261c 0xa829a09f 0xa95e2122
+ 0x16361e5a 0xd7554d4b 0xfc0d42ac 0x2e24554d
+ 0xff51fb78 0x26ebfea0 0x58395138 0x143c8a55
+ 0xc2293b7f 0xe9aa4b72 0xd1424a85 0xff9b8181
+ 0xbb3eebaf 0x266de1fd 0x90db257e 0x7d35beb4
+ 0xeaffac02 0xf79c88ff 0x3e14f387 0x0bc083b5
+ 0xcbd395ab 0x1041b3b3 0x08ea7750 0x8728fc11
+ 0xf61bd8b3 0x1f88ef7b 0x78b7e9b4 0x17b5c1f5
+ 0x025e6c82 0x57f8d81e 0xde5866a8 0x7b7cba80
+ 0x28221a45 0x96f83ebd 0x77c715ed 0xd3a4e160
+ 0xd4be9d72 0xed659f39 0x7af0b3f6 0xb1d83c34
+ 0x2876540e 0x0aa244e8 0x6af45032 0x52cc08ef
+ 0x69b51eef 0x94367800 0x80adf5d4 0xcdf9cfc5
+ 0x367d995e 0xa22aefd9 0x2faa28ea 0xf15648a2
+ 0x8e397577 0x5e449c5a 0xb046cedb 0x17072ee4
+ 0x9499b958 0xb230dbc1 0xffbdbc91 0xd8d60c85
+ 0x0a139cb8 0x36e99cdf 0x4bdc3842 0x320fa3e6
+ 0x075cfaa3 0x43240bd7 0xc8c6a0e3 0x43a14f16
+ 0xd7d5d7fe 0xba846e6a 0x0579ab86 0xbf084d77
+ 0xe8c4765d 0x8bd7ee60 0x8c4e7a16 0x2cad2f9c
+ 0xd5bd8a08 0x63eefdd7 0x7528a1ef 0xb7512102
+ 0xda25ea2c 0x4654e6ab 0x4cfc6989 0x84539f52
+ 0x00f79862 0x65074163 0x45e2c2ee 0x28731aa6
+ 0x7e9f6395 0xf8555873 0xd33bc4a7 0x8ecdbea6
+ 0x49f0e7e1 0xa26ef54d 0xfb3e6779 0x35292faa
+ 0x4ba9d214 0xead84a75 0x02cfdafa 0xbd1b47e7
+ 0x36e2b9a0 0x98779f87 0xfc4ec502 0x71854294
+ 0x5826c064 0xbfbbfaaf 0xa00db5c6 0xdea7f68e
+ 0xa2d32e0f 0x46954ffd 0xeb66d2f9 0x35fb88c7
+ 0xa2465311 0xf989f526 0xbdfa214d 0x95f0afd5
+ 0x43a1041e 0x7740e027 0x9bb117fb 0xa63c0645
+ 0x9db93447 0x5f250441 0x6537eac1 0x29f787fb
+ 0x60f5a17c 0xec8f80e3 0x83c9165e 0x1d9ff136
+ 0x8f43938d 0xf040a1d8 0x9e938a3a 0x48606674
+ 0x932d15d5 0x383fcd65 0x4d7db303 0x5f633834
+ 0x8a17761e 0x19528112 0x371b0358 0x1e34cfba
+ 0x7046c689 0x438c7afa 0xad1bc6b0 0x9bb9e775
+ 0x4d703091 0x04d9fc0d 0x494ebf77 0x610c1855
+ 0x4b88816e 0x6c591a81 0x15597954 0x0fe13112
+ 0xa949a9e5 0x4022dfd1 0x8eaf10e2 0xc436ad18
+ 0x337254bf 0x0c44812d 0xc759ce3d 0x1da78e29
+ 0xdba82250 0xe355c8df 0x6e614615 0x791713b6
+ 0x247baf0c 0x9636e6b3 0x092382bc 0x196a100b
+ 0xa0478de9 0xfd4f26b0 0xa5a1c49b 0x70d1ca23
+ 0x6c54086c 0x47286307 0xa185c373 0xaec65e82
+ 0x6ce77213 0x463b07d7 0x5420939d 0x3ee4fc03
+ 0xc4cd11de 0x65d521b8 0x5304e894 0x8c707b4a
+ 0x455ec718 0x10d082cf 0x20535bc1 0x0c3b1016
+ 0x90cf26d0 0x25919378 0x671c24f7 0xeaa83d6c
+ 0x9cbb1c64 0x42f1bbfd 0x43b5fba4 0xf4f6ef30
+ 0xd2034c56 0x6f7d60a1 0xeeadc1f3 0x319af4d6
+ 0x0c7e9098 0x0655d994 0x340a3544 0xb37d57bb
+ 0x78d086b8 0x350297da 0xc8540081 0x7918666e
+ 0x422de0b9 0xbed54d9b 0x03e32a80 0xf0d0c693
+ 0x2fe80f16 0x5941f0db 0xa824c1e8 0xe46e7a57
+ 0xfcfa4b53 0xb7d8ff24 0x3ab82e1e 0x0332c4fd
+ 0x669fd568 0x64adabf1 0xd9c372b3 0x5ce6c28f
+ 0xaa8a0e64 0xd4ced1ba 0xfa74c3f8 0x8a59e9fe
+ 0x009f47ea 0xe7c2505e 0xad0470b9 0x92abdb75
+ 0x9215812b 0x1fb86f54 0x57268f45 0xe91fc794
+ 0x9bb1be94 0xc40daab9 0xb75cecd5 0x293c40c8
+ 0xe507f284 0xb79f199a 0xa6a0cbdb 0x505cd140
+ 0x04a6d213 0x84812279 0x09e5720e 0xf42e2fde
+ 0x112178ca 0x1bfcbf80 0xf42738a3 0xd4e205fe
+ 0x204c92ad 0xb916f4c3 0x0d7ce99a 0x90eef87f
+ 0x924a4183 0x48d1978d 0xe6e16abd 0x5d9eb6aa
+ 0xa7a0ee24 0x5aa5ab50 0x563ba4b3 0x7f2b08ce
+ 0x641ec0be 0x955af0f3 0x4689d1ab 0x8625ae9a
+ 0x11eda5e0 0xe5cbdb1e 0x010591c2 0x632b37eb
+ 0xbc20a998 0x33b69747 0x414334ae 0x92b82687
+ 0xdba623c3 0xb0d2d852 0xddf1511f 0xeca97e4f
+ 0x8ebf5668 0xee509e06 0x8a9ceca2 0x7391233e
+ 0x19e71554 0x02315bfd 0xa3fe5260 0x6e6b8370
+ 0x1cfab468 0xf3cec4bc 0x11a6a066 0x129d2ead
+ 0x79d0f2c1 0x6aab68d0 0xa243135c 0x5be05f22
+ 0xba353845 0x7b96f7d8 0x2ba7c6c8 0x67b38557
+ 0xedf2c1a9 0x9bc7531e 0xf72fbdda 0xcef2d3a8
+ 0xa471a9d9 0x33a35e80 0xffe32136 0x974bf4e7
+ 0x70c2d3be 0x95ab3510 0xd878a265 0x16548746
+ 0xca45cfd5 0x2b22b0ae 0xf4f855b7 0x3f44b872
+ 0xb66db844 0x680417dd 0x72188a88 0x27f830d0
+ 0x09d64419 0x35989f77 0x33b7c1c1 0xf6e14634
+ 0x3a0d712e 0x42b02a73 0x37592d52 0x34a2bf38
+ 0x4434fa60 0xf1fa3c09 0x91ab7747 0x429124cf
+ 0xa6b8eebf 0x5d2bbd8e 0x3dfd42c4 0xcd9ada39
+ 0xbc3ecf68 0xf5b00eac 0x6e81fc62 0xf58437d7
+ 0x09b3139f 0x27fc4f88 0x2d76418a 0xba8deabc
+ 0x79557497 0xd322c58e 0x6669c5c0 0x97939ba1
+ 0xe96972fa 0xe69d1ec9 0x816a4730 0x693cf703
+ 0x1c350d84 0x328e1953 0xd29e402e 0xd4b68664
+ 0x3070a143 0xf332f24a 0xf8f3519d 0x4829f694
+ 0x15c92ec2 0x4c09709e 0xacad6a79 0x706821ed
+ 0xffb8343f 0xa51a014b 0xec3bae13 0x2691fa26
+ 0x50af71aa 0x9ccbbecb 0x25cacfab 0x4ff30e8b
+ 0x827c619f 0x912c486a 0x8bddf9cb 0x1ca329c6
+ 0x3c2494d4 0x4e3c0761 0x231246b5 0x1bd705f9
+ 0x9b15013d 0x78fcda4d 0x42e62ef5 0xb7dcdac0
+ 0xb27efdb9 0x09dfc5c3 0x5e6286f2 0xaeea106a
+ 0x7869f2cd 0xe41b3015 0x8046e217 0xd2145f6a
+ 0x45c88a59 0x892b2ea4 0xc8525432 0x1036d246
+ 0x8e6045a6 0xf4f56dd2 0xb7bf140a 0x28cf6014
+ 0x142b6c0d 0x27e31fe7 0x52ced865 0x4fdafb4a
+ 0x68177bcf 0x2bdd5bdb 0x2b0fa0a6 0x0fcafe58
+ 0xddbf88c7 0xde93d5b3 0x49e297a9 0x771049ab
+ 0x3c2c3287 0x09134d1b 0x3764389a 0x3781cba4
+ 0xed665fe8 0x9b055946 0xdc3ded39 0x6576e100
+ 0x6826150c 0x68151773 0x9d1bee18 0x777ea1b7
+ 0x4b09a72b 0x973120f9 0x92cc1baa 0xe610b576
+ 0x7f08cb8b 0x12f9788f 0xa8387cab 0x38bfd391
+ 0x6cb0b1b0 0x0b76d93d 0x73ebec97 0xf152a945
+ 0xbd3d40c5 0x54362aa7 0x90e626af 0xa92dca8c
+ 0x7865aa83 0x7defce09 0x2a173231 0xf1f322a3
+ 0x6dcbe003 0xa82ec53f 0x609d2fba 0x7ed0daf8
+ 0x21d72068 0xe50202d5 0x99324a58 0x5cd587b1
+ 0x22de1ca5 0x8bbfc6f3 0xb4ef3242 0xb73aea5b
+ 0x200b456c 0xa14a0da9 0x7ca58ac5 0x1a187705
+ 0xd58896e9 0xa5bc10cd 0x3470d7ad 0x1247dc26
+ 0x877172d9 0x3b1dc34b 0xb88494e1 0x39db9c8a
+ 0xb802b911 0x20701030 0xea20b1c6 0xd28d8a3e
+ 0xbd9d9f75 0xe371ca39 0xfe361a6f 0xedd62fb0
+ 0xe76daec9 0xd600efb1 0x5f90ed95 0x5d6fb5bd
+ 0xdb0ac4f4 0x8008a84e 0x845d50aa 0xe19c4754
+ 0xe68847eb 0x8e5b5c61 0x994239fe 0x9834f61d
+ 0x024a2077 0xc3fc21ab 0x6a45af08 0x35258359
+ 0xf16b1eba 0xb3bc5423 0xc92d6b29 0x54e02b89
+ 0xe6aa9df1 0x8a38aec0 0x031a68f9 0x1107d939
+ 0xd7e0a74f 0x976c7d59 0x3fc7896b 0xa247b93c
+ 0x58d2e8c5 0x6168e2ca 0x65ce7a4d 0x07eecbe9
+ 0x064c67b2 0x06f57d98 0x2fb63ba1 0x7632e204
+ 0xa6c9de98 0x8c382895 0xe74fc689 0x2a1def5e
+ 0x31002493 0xc185e709 0xd18edc2d 0x7137deb8
+ 0xabe21a4b 0xd17d019f 0x95274457 0x737b6860
+ 0x9e0f6c6c 0x3fb11486 0xdf8897f2 0xf0d628ab
+ 0xb290a618 0x3aab7d23 0x05677cf1 0x5056127c
+ 0x14cfd11e 0xeb24053f 0x9654344e 0x6b1d8c8c
+ 0x68cc5f04 0xbf17e79c 0x54cfe8d8 0x107f0a52
+ 0x9bca389f 0x24252885 0xd758eef5 0xd898d717
+ 0xeadf045e 0x165e25d7 0xa685595d 0xf637d696
+ 0xebca236c 0x368079c3 0xfdafe821 0x89715066
+ 0x6cd7aa80 0x31775690 0x0de0b4d8 0xae9fde9b
+ 0xb425dead 0x41471330 0xcd4e58bd 0xf484f0b9
+ 0xcbfbf813 0x1a25e5ee 0xe6456cea 0xc956ef7f
+ 0x8ac948a2 0x775b1bfc 0x9739ab03 0x4f0b6411
+ 0xb6b76e6b 0x9ec9343e 0x4f84c648 0xe1e66557
+ 0x94f9fdec 0x386e4616 0x05c69bdb 0x93b0d440
+ 0x9e5a3f61 0x635a80dd 0xdb6c23ba 0xc8d5f680
+ 0x53767271 0xc0df8ca0 0x117efc6f 0x78758796
+ 0xb3c77572 0x40e23c4e 0x82d7a503 0xaec195a8
+ 0x53c1fe03 0xa131e6c9 0x2abdf9e1 0xa586fef5
+ 0xb6d68103 0x34de4b9b 0xd4c02e0b 0xe5cda9cc
+ 0x1a7e7917 0xb9b2f0f0 0xcabd1b03 0x18c17e71
+ 0x07a37b1e 0xa83d6960 0x4dd66c28 0x32cc6b02
+ 0x6eaca18d 0x7b166b05 0x095d85fb 0x938ec035
+ 0x1a7e82ff 0x54bfb69e 0x6fbb6339 0xbeeaf829
+ 0x8802a09c 0x604bdd0a 0x8191f84d 0x7da1e89c
+ 0x64b9b0a5 0x6a5b6428 0x93eea3b9 0x21c433e8
+ 0x8043427f 0x605e743a 0x9c81808f 0x7c976479
+ 0xd7ef98c6 0x8b39cbee 0x89be6e39 0xd01dc72f
+ 0xe6c09227 0xc8ecb3f2 0x399d3a41 0x4a91d1a8
+ 0xf83eeda9 0xe1d4fe01 0x518ca766 0x0c3b1ce3
+ 0x828f30cd 0xd3edf647 0xac126894 0xdd3f996c
+ 0x601e5d4d 0xdd7856cd 0xce16a70a 0x99212df2
+ 0x5e2b3d89 0xdb8d2ef6 0x70b79dd9 0x361a3a38
+ 0xf6ec33e6 0x4ec9a451 0x1a280939 0x2d9d6d7f
+ 0xfd4e1f43 0xfd5ffd39 0x83921d68 0x37db0d24
+ 0x77c94204 0xf11165db 0x5cc1103a 0xab1d0669
+ 0xd12ee8b4 0xa9ff0fdb 0xa494ff37 0x694f46c7
+ 0xf64b5f33 0x520f1325 0x141eb18b 0xd29adbb7
+ 0xa68fe24f 0x3d430328 0xedd40f99 0xdb5725f5
+ 0xd3b0249b 0xf430037e 0xd105a0b1 0x95fe82ab
+ 0x72dc63c8 0x8c1b45fc 0x96355d54 0x76e40b98
+ 0x5f7baeed 0xba9b2590 0xbd64bbb4 0xf1541f6c
+ 0x7ca49b5a 0x111f2640 0x4b86cb63 0xfe71a409
+ 0x3ec03f6b 0xae4aa450 0x525163aa 0x1123ab5f
+ 0xb385fc44 0x6901f207 0x2ff5773c 0xd55b0a75
+ 0x6732e0e1 0x773f7dee 0xfe70aee9 0xd856780d
+ 0xdee051e7 0xd950ffd9 0x4da637f7 0x13b4c650
+ 0x2eff422d 0x0871c35c 0xb3e61664 0x1fb1abad
+ 0x78e2ad46 0x44f63fe4 0x1e9e1d36 0xacf791a1
+ 0x4fb51853 0xd0d5b2c3 0xf9728625 0x7160dab7
+ 0xafe5d4b3 0x8bf7b7f0 0xd49a6ea5 0xab1694a1
+ 0x1bc22cb3 0x3fcf2c26 0xf3237c26 0x442367ba
+ 0x5dda5917 0x20031a86 0x1f1b8a1a 0x1477325a
+ 0x546ee877 0xd347d71d 0xba45204b 0x750c5e9a
+ 0xde39e049 0x4a544c72 0x627d76c3 0x13b7f044
+ 0xe173e94a 0x64337a88 0x8e0548bd 0xfd0f0271
+ 0x45721e1e 0xaecb5a8e 0xfb1f7bec 0x42449a14
+ 0x620a6043 0x6310cdf1 0xb49eaae5 0x2bbf380c
+ 0x26b7090b 0x4dc2da7e 0x3218693c 0xa6866d0f
+ 0xcc998a27 0x57fa9a65 0x38a55c26 0x2d110f40
+ 0x75fd7072 0xe147d675 0xb40adfba 0x3ea3896d
+ 0xf289c62b 0xfad4fc7d 0xe5e10d26 0x1bd5f851
+ 0x96f5e841 0x36a4e81e 0x670ba3f9 0x67aa030e
+ 0x5577f4be 0x953b0bf3 0x307d00c6 0xbb9eabe1
+ 0x871966cf 0xeb40c08d 0x74fd7e0c 0x49d4864e
+ 0xf908f80f 0x1ea32c4a 0xd69e9ad0 0xaad2ad31
+ 0xccf27a60 0x41ee5ebd 0xfe1dafcc 0x71cef55c
+ 0x784168de 0xc4a0c447 0x315d99b3 0x0c2470f3
+ 0x9002b535 0x29b95878 0x7a8a2ce4 0xb49967d5
+ 0x37814d76 0x333b15fe 0x8a964085 0x3cd76bbb
+ 0xfd1d1834 0xba0c3dfc 0x61d29379 0x8764238f
+ 0x5aaf4d00 0x24c3bf1c 0x9c3c7488 0x94dd60f6
+ 0xc844a0a1 0xef8b2bfc 0x0e8d1c17 0xd6d4d2d4
+ 0xeb15153b 0x4f1233f6 0x8ed307ac 0x749fa7f8
+ 0x387d4e80 0x80904eb7 0x53385377 0xf77ca9fc
+ 0xbb037920 0x3cd8ef96 0x05ea8e91 0xdd0e0501
+ 0x29779eac 0x55de6e6f 0x89874da9 0x56ad3af4
+ 0xd8228766 0x9887bc22 0x213a0648 0x4db466af
+ 0x550f82e4 0x964ab9e9 0x0cbcb32f 0xad872a85
+ 0x97ef2fdd 0x8e78bb79 0x95be67ea 0x44c2d180
+ 0x236b246a 0x3b253079 0x15c0dd93 0xef4b0368
+ 0x30f36d65 0x506737dd 0xcc93b5e0 0xaf00bfff
+ 0x1a79a0e6 0x4dad4900 0xe59a76c8 0xe1533fb5
+ 0x75a4d69d 0x80744617 0xdc92e0f6 0x18e53a7d
+ 0x9c1190f4 0x6411a55a 0x24137a70 0x3fad9fde
+ 0xdfb6e346 0x7221d85c 0x6f6e2aa4 0x3ade33c8
+ 0x9410407a 0x953aab54 0x8dde9999 0x7afd3ca3
+ 0x1a92d29b 0xa78e9ace 0x95d15c64 0x95e9314a
+ 0x0cf548cf 0x31bf5f8c 0x5cbae6b2 0x883b14a2
+ 0xe21a9715 0xba500b0f 0x34ec849c 0x2ee98b5a
+ 0xa3bdccfb 0x1022fa85 0xbf97abdc 0xf5bd1fe1
+ 0x542d7143 0x896ed934 0xd3c42da1 0x13d90044
+ 0x0573619d 0x305067bf 0x6f02b13f 0x0c516dc8
+ 0x378699d9 0x838166f7 0x380ddd16 0x4c0e8bdb
+ 0x61ba5a38 0xd5cf4a2b 0x0733d359 0x39468b9d
+ 0x0d9e90c5 0xe8717681 0xe2d0a06a 0x8a436126
+ 0xa5a31cea 0x03e217c7 0xe00398c3 0x1e36ee68
+ 0x6bec78cb 0xd2de6eab 0x7d252266 0xbb4e8fb2
+ 0x96c7fa6b 0x5758c3a7 0xe81f9a51 0x0337916f
+ 0x4f31084b 0xa0dd1f6d 0x7da31b5d 0xbfbd5092
+ 0x7d9f1e22 0xced1d5d3 0x8c397f51 0x68488587
+ 0x2c89b78b 0x5c95b114 0x03a124b7 0xa9c22961
+ 0xd05b4125 0x7987a218 0x9b33b81a 0x8dbece84
+ 0xcd44692f 0xc2f7e2bc 0xee62478b 0x19a72768
+ 0xf89a81c2 0xde94f042 0xe786cc87 0x1cf6dfe8
+ 0x97357227 0x5d0b8ccd 0x210ded20 0xa3415b63
+ 0x5a44c511 0xe00d553f 0x9106e41b 0xbb90e29c
+ 0x4278fb00 0x13c4d245 0x0da5d28a 0x33bcd03f
+ 0x622f99a2 0x5403b878 0xb755e5bf 0x93260477
+ 0x57163c58 0xd5ad8ede 0x38597763 0x843ee2e7
+ 0xf6bbfd8c 0xa80486d1 0x0aa9d04a 0xc3a21001
+ 0x0988ea5f 0xa599060f 0x35ed1e4c 0x6861fb9d
+ 0xdb49e460 0xeea1563c 0x630322fa 0x1db98607
+ 0x061ce758 0x0ac92a43 0xb86273fa 0xc74cff34
+ 0xf754e2f4 0x1d2a92f5 0x7345cab9 0x684f75ff
+ 0xd68ac78d 0x7ac26120 0x2849d90a 0x9b9e68f1
+ 0x61f0cf5c 0xa8ca277c 0x59b364c2 0x0c697e32
+ 0x299f1644 0x390cc831 0x52f8fcc7 0x324a355a
+ 0x245255d6 0x66571e06 0xff7cfc9f 0x9a1d968a
+ 0x77d5b3bd 0x02118c12 0x886cb817 0x86863d76
+ 0x6e9e8f89 0x16b32373 0x548c53ea 0x366dd932
+ 0xc8bc0ed7 0xc55d2cb3 0x382a1401 0x0c343f0a
+ 0xbb7022cd 0x775c425a 0xc942868c 0x491c03f1
+ 0xe4e8bc37 0x57eb119b 0x161f1c40 0x78813d90
+ 0x64ba5ad4 0x8c1a3687 0x6cc54f9c 0xe838a982
+ 0xcb582447 0x946585f3 0x513fb0ca 0x1207f8f3
+ 0x2c317225 0xd3144a73 0x937db9b9 0x1512f0fa
+ 0x0144c46f 0x617ee635 0x6abb13d1 0xa5735cbf
+ 0x28c41d41 0x4bf3cc5b 0xef15db89 0x93fd1b38
+ 0x9429d27d 0xbe2c2385 0x8ad8bf36 0x47b18f4b
+ 0x439baf8b 0x9f7b5c0c 0x403263e8 0x85a4a0ed
+ 0x2ab72c87 0xe5962ae7 0xb2eb376e 0x023c83ea
+ 0xe14729a5 0xef1f1f07 0xe8ad7262 0x4577adfe
+ 0xb27407ff 0x299d5afd 0x2def24cf 0xb0fb321a
+ 0x91a3ca39 0x549ffb9b 0x00c11c2f 0xd52620d2
+ 0x483c3576 0x21b03393 0x6c19a634 0x60949c8e
+ 0x2eb2bcb0 0x77b950fb 0xe5762d8e 0x491bfad9
+ 0x6ecbc8ca 0x8f6665f1 0x1d76f0fa 0xe07c8ed7
+ 0x93c70313 0xe3846992 0x84364566 0x642caf16
+ 0x5ac66840 0xa8e4829c 0x1503a3f0 0xf0b7d2eb
+ 0xac163682 0x4da9a902 0xcb03ab68 0x95395ba3
+ 0x9c33a7cb 0xdeed8413 0x9d6b8d5c 0xb802340b
+ 0x1ea7fd81 0x99313f3b 0x6b85ad1b 0xeb6ebef3
+ 0x6e59a06b 0xfdc0fd57 0x0062b9e8 0xbf16842a
+ 0x6cbd26a9 0x83444a69 0xa6f6c1f1 0x2cf5a079
+ 0x1c3f8b9b 0x5c95aa6e 0xcdae53bd 0xdfce79db
+ 0x3908fced 0x5e5d8e6d 0xbb15c722 0x1aaf5bd0
+ 0xd978d536 0x91f112d0 0x3dde83fc 0x1abfd9dc
+ 0xc42b4d93 0xb91530fd 0xe782c8b7 0xa78637ae
+ 0x87827a53 0x332a694d 0x2fe77c47 0x4310fb1e
+ 0xd9ce00ed 0x41458131 0x2db53f24 0x58e70ac0
+ 0x48ae6ac7 0xf99f1548 0xb4547cf4 0x5d87e704
+ 0x5f6481e6 0x4cc4b6d8 0x38e87cd7 0x9dc7790c
+ 0x1a2458d3 0x1cb3d6dd 0x6b42515c 0xe4ad86f6
+ 0x3854471f 0xe599520f 0x0499246e 0x9d76565c
+ 0x75019717 0x5607a929 0xfcbae54a 0xc98593da
+ 0x5d9c3101 0x80dd77cf 0xe8c8d2b7 0x40ce61b9
+ 0x2090ba2c 0x487bd52e 0x2e4ed94c 0x3f2f0d11
+ 0x7b66d583 0xd91b93db 0x7bb06fc3 0x80c38aa9
+ 0xff6d96de 0x47806328 0x255fef60 0xefa54a24
+ 0x74dc5c69 0x4b4db032 0xe15621c1 0x11c6b1c5
+ 0x30e4067a 0x07d4b9a6 0xc466c81a 0x3d1baac3
+ 0x9ccfb9d7 0x13d170e2 0x43ce03b0 0x6a010f61
+ 0x53fca3f5 0x2c25ab82 0x09f729fc 0x9f706241
+ 0x6a53b88a 0xec3b1246 0x6977fa94 0x02cfcfd4
+ 0xe4a7c27d 0xe8e8ea3d 0xe845b11c 0x19862507
+ 0x8acf6cd7 0x978be162 0xf01ded4d 0x7ff7e81e
+ 0xe6f36ca6 0x22a0a9f6 0xcb178f7f 0xe2e15339
+ 0x2f71a56f 0x75fd3f09 0x03c93002 0x26784382
+ 0xf21aff81 0xe23413b4 0xdd1330df 0x2ecd91d4
+ 0x7fd8d558 0x76878bfe 0x8b1dbba7 0x4383885d
+ 0x003baaf5 0x299b274a 0x69e5c88b 0x55b2b499
+ 0x522f83f3 0xa46c9774 0xb0212460 0x3085a0b4
+ 0xdb229bc9 0x963f7774 0x47267dcb 0x1fa9ce5f
+ 0x9433ccb5 0x2848a201 0x93019d81 0x421e703e
+ 0xb121c267 0xcc2ad207 0x7f17e83a 0x596a8994
+ 0x96f27104 0x89b2eae1 0xa544803e 0x5cb08340
+ 0x2f720974 0x1350dcba 0x78ce7ae4 0x7d320399
+ 0x3735c25a 0x0545b42e 0x3e4c7d54 0x6ed68501
+ 0xc9b2f3f8 0x4e949c93 0x389f0e89 0x43ee36f3
+ 0xb3c459f1 0x17513779 0x8229f712 0x215bde53
+ 0x4b4b07a0 0x90ad9983 0xaeb3494f 0xf6f727ca
+ 0xc28fabb6 0xddabcdab 0x01febf71 0xb244b8c2
+ 0x0a455225 0x2901729a 0x0a7b35ca 0xf1b23e0c
+ 0xa5f7c517 0x92f8e547 0x233ec55b 0x2bb537f0
+ 0xeaf1b875 0x289e0104 0xda51c3d3 0xdfabadde
+ 0x06a41866 0x4bf82f47 0x12060655 0x153525e2
+ 0xb8cfef42 0xc307b295 0x778b6b82 0x036e40c8
+ 0x6a4cdec0 0x750e09f6 0x0806ab28 0xf8dee912
+ 0x45b906e8 0x08fb675d 0xae22c34a 0x2f54dc88
+ 0xe98c7993 0xb76b6518 0xc70d5d8f 0x5987130a
+ 0xd89d1cec 0x1744e957 0x22db0f57 0xc7501e9b
+ 0xe9c9dc0b 0x1a8553a7 0xc15a4e4c 0x9e1840d5
+ 0xeac1888a 0xba4c0a4b 0xdad84202 0x2d1b2d75
+ 0xef06c127 0xd319a36c 0xd60b9d92 0xded20da2
+ 0x00d23bdf 0x96b431fe 0x636914b8 0x494e02a4
+ 0xc8c4ad31 0xe56bf0b2 0x28f07451 0xd86917f1
+ 0xf7299383 0x977635a5 0x9026dc33 0x3e3b3b57
+ 0x767118a5 0x04182a61 0xab5ee0ea 0x34f4cc0c
+ 0xce072097 0x78d15c95 0x6735d38b 0xc23bab3a
+ 0x7633847c 0xdd6d33fe 0xa1df1bc2 0x864ebeed
+ 0xda785538 0xe87d3586 0x1b22b9ff 0x13160899
+ 0x63bf5870 0x3e2955dd 0xf0ef68c7 0x51265578
+ 0x63b70533 0xcfd7b598 0xeef8ed8d 0x760fa884
+ 0x6375b455 0xa9c173e5 0xbee01756 0x6dd2f4a6
+ 0x47ed59f1 0x7720dc3e 0x629c2a41 0x782040c2
+ 0x7b86f562 0x7d5ff40b 0x17fb5fb0 0x26c157bf
+ 0xbf0060e2 0xd9688952 0x98374c22 0x59ea8e69
+ 0x252e4b81 0x123bf2e0 0x3d56230a 0x5188164e
+ 0x93261c35 0xa564aa88 0x121bd9cd 0x5c16aec8
+ 0x2fa246a9 0x15789e4d 0xa4bb3b72 0x5bafbec9
+ 0xcd1b93fd 0xe2d0427b 0x56f5694e 0xf48953b2
+ 0xc50fc819 0xe0af3ffa 0xc3e48bda 0xb80b874a
+ 0xf9258e7f 0xad9f4362 0xfca90c4b 0x4884b4bf
+ 0x4dee8a41 0x5c4d0196 0xc249d85c 0xbb5b9632
+ 0x8b5635c4 0x2b637b4f 0xb840896a 0x4ca8646d
+ 0x4696be9c 0x6630a968 0x5c5b4533 0x29eb7b7c
+ 0x55f67376 0xa8dc36cd 0xb4f4474d 0xef64a1fb
+ 0x1418534d 0xa76530c5 0xdcb4641b 0x8dfc7ae5
+ 0x9afc17a6 0x44dab843 0x80f1f874 0x23b8762f
+ 0x6cb7650f 0xf30d05cc 0x1f1fe1c0 0xba28476d
+ 0x066fbc0d 0x97d7e010 0xb2d29434 0x4a42af7e
+ 0xe0292aa5 0xfb450fe3 0x670c292c 0xdb35b707
+ 0x8a981c83 0x30e2c3ac 0xe0e9c1b1 0xa8331796
+ 0xcf5af247 0xc01b2f47 0xd25679ff 0xd5388c03
+ 0x94227b44 0x95b55fa5 0x72fae874 0x4c760f50
+ 0x3279c236 0x4b0e3026 0xf0ef3721 0x30ed3945
+ 0x99f7e6e1 0xb985557e 0x6f5599cb 0x5c4d76d8
+ 0x559f7096 0x183f53c7 0x7ddaabff 0x92ec2b04
+ 0x5935371b 0xd968d5aa 0x4818a8f0 0x76d10b5b
+ 0xcc0eddb8 0x86a730b6 0xaa95c741 0xdd404554
+ 0xcc529f43 0x28567f77 0xe9dcde95 0xcfbfbf96
+ 0x1f1253fe 0x60822fd3 0x2b0ed852 0x80e06c9b
+ 0x5e8d23cf 0x577c0905 0x96069c6d 0x99c241c8
+ 0xe5ae5dda 0x99539ee1 0x56abf146 0x917dfb3c
+ 0xe84801fa 0x3d9b7e26 0x404c8082 0x3d704cfe
+ 0xb6f7453d 0x1f509b7b 0x846b280d 0x8d20fa61
+ 0x1990f9da 0x6dd00698 0xd0b108e0 0xfd767fe1
+ 0xa6270bb9 0x1aeff8d4 0x7621ae8f 0x37f5f2a4
+ 0x95bc6d03 0xf98e99fe 0x2b03c0d9 0x928b4e3b
+ 0x3493fbbf 0xe5833647 0x42a92ec1 0x3ae9f16d
+ 0x39089d52 0x8ebfa3e7 0xc05c7627 0x0b42a1ad
+ 0x2773bd44 0x10f95843 0x53994b3b 0x0d3f8f05
+ 0x4745c534 0x073c3264 0xe7d88425 0x12ce91fc
+ 0xc45eed99 0xacda7b87 0x34819b15 0x44cbba73
+ 0xd939e0cc 0xd02b4d35 0x2c2174ae 0xd8d25155
+ 0x8af4ec1d 0xcbf70b9b 0x647e75a3 0xb5db7051
+ 0x978b8f7a 0xb74404d2 0x1635f61b 0x8c1db8cc
+ 0xd1414536 0x4caa27ad 0x58aec877 0x625683ae
+ 0x076d11fd 0xe2bbbc48 0x75c3d352 0x25dc3bf9
+ 0xbc0097b4 0xd8fa1b96 0xc9f01dbe 0x449393d2
+ 0xda1893be 0x741f6c84 0x71538d10 0x38d42ac3
+ 0x20f9e95f 0x3b6d6511 0x3547488d 0x9ec4e3a0
+ 0xaa096298 0x7738626a 0x56a4a9c0 0x79a865c1
+ 0x8a590afa 0x8d60b288 0xdb1e68ac 0xd4d1b724
+ 0xdc734e47 0x167bbde8 0x43e2fdf9 0x847cd1c0
+ 0x49034f8c 0xe9aff87e 0x8b743e83 0xb811b6cd
+ 0x3546ec3e 0x856eb97c 0x41d4c579 0xad60d402
+ 0x4f0ff4d6 0x9afbee57 0xe678e2e1 0x53a1d97d
+ 0x22f885dc 0x642856fd 0x4a81b1a9 0x265dd2ba
+ 0xef16b9ec 0x8eb61d21 0x4f484265 0xa668418b
+ 0x5c28fe6a 0x895c076f 0x22294668 0xae1d0869
+ 0x103b8f52 0x348edc9d 0x8094074f 0x00635bed
+ 0x0e48d8b3 0x85a44cf4 0xc06e8cd2 0x96b3bb35
+ 0xf80f6829 0x72070e75 0x45f139d0 0xae3c90ba
+ 0x72eab68d 0x6dbaf724 0x7b1bb04d 0xeccdd042
+ 0x6c55b042 0x5c2d3da9 0xe6883282 0x43085add
+ 0xfed4e6d4 0xf6a4e8fa 0xd2609bb6 0xda70dfba
+ 0x9e9d1d8d 0x4c4928c8 0x74ef7983 0x76c471e6
+ 0x0a84f86b 0xc90a6f35 0xa6a3d84a 0x534312a3
+ 0x021377f9 0x3e38177b 0xb7411fdf 0x47d09e78
+ 0xbeedc504 0xc69f3e45 0xb9ad6ddf 0x67305b87
+ 0x0eee93ad 0xeb42ec4a 0x2d792e40 0x36b38150
+ 0x70553e78 0xc9faca6b 0x109523e8 0x92907948
+ 0xb1bcea74 0xe949a024 0xa8416c81 0x535456c0
+ 0x338ce49f 0x0fe855b3 0xcfe9d839 0x4a71671b
+ 0x3b39dca4 0xe7f2f3b0 0x9670c765 0xd0b5582e
+ 0x8af482af 0x4de8e13d 0xfc229249 0xa44568d7
+ 0x9af47a09 0x56d992f5 0x6359b7aa 0x26179b95
+ 0x681fcbc8 0xfa67fff3 0x253b2406 0x900be39e
+ 0x1b918c3c 0x184cd65b 0x86dbb9a1 0x406555c0
+ 0x9e71c8ce 0x08aafc7e 0xcf7bcca8 0xdbfee8b9
+ 0xf6690e2f 0x67dc077c 0x971b0e18 0x93eabd5c
+ 0x995e6579 0xe02aef8a 0x1dd8edf8 0x21e5a297
+ 0xd8fbd7d1 0x6b778ea7 0x73818f7e 0xec9c60c5
+ 0xbda7ec46 0x290f2b1b 0x9b9c1ff5 0xdbc720e0
+ 0x4057d01c 0x583aaca8 0x42157273 0xd04cc9e7
+ 0x17f006dc 0x7a0061c7 0x5092ebc6 0xaf39abc4
+ 0xc83234b4 0x95766854 0x26beaf6b 0x7707852f
+ 0x26b81ab3 0xf32e8f16 0x0fb218d3 0x92128d4e
+ 0xa1c881e4 0xd99b97b9 0x32ddfdc4 0x788499e7
+ 0xbd4da7e6 0x2134a49b 0x768f16f1 0x651e8ca4
+ 0xde95ac3b 0xd63d22ce 0x2f7d34de 0x1f44aec0
+ 0x22cf59ef 0xe845473d 0x249699b8 0xee698261
+ 0xafdf6327 0x4b6c1eed 0xd55259f0 0xac3c90d3
+ 0x4a5691b9 0xc2056b30 0x46726519 0x99097fe0
+ 0x36204d12 0xae5f9c05 0x6146df29 0x2e3777e1
+ 0xd96ff159 0xd6a25f3c 0xc39cf188 0xce8035c3
+ 0x18915c69 0x6336aed8 0xba4ee698 0x14160c9c
+ 0x5b3f9df0 0x76bae97e 0x42e4feaa 0x3977a8d0
+ 0x37dc468f 0x04b24cc9 0x0bba0dcf 0xbfa6e345
+ 0x44bdd1e8 0xc92547c6 0x6788da17 0x59e796b1
+ 0xe2770fb4 0xd92b9ad4 0xd03d1b8b 0xd07b8c2e
+ 0x8a543f84 0x05b0d456 0xfaed7eed 0x52d3fd0f
+ 0xf9591f25 0xa00b2f73 0xf0107935 0x91e5b227
+ 0x18850204 0x8dcfc51b 0xb6db0c07 0xf7116316
+ 0x6a5dbd17 0x0d76e281 0x6005fac7 0x16d79045
+ 0x31895a18 0x399371cf 0x536e420c 0xc49323af
+ 0xd2b27dc7 0xe9a2c450 0xd1aacbd0 0x8e899397
+ 0x67aa7c54 0x235619ff 0xec87a0b5 0x71be4483
+ 0x06657d96 0x884020df 0xb8f2a975 0x12e2440e
+ 0xd1966cb0 0xa7bfde0f 0xbb51bf79 0x8604d7ad
+ 0x4f09e7a3 0x32e6bdf9 0xc964da28 0xa751b31a
+ 0xdb35eee7 0x8c27e01a 0x26b538d4 0x0dd36be9
+ 0x706170af 0x3b18f53b 0x9c7992d9 0x5ed9eaa4
+ 0x47347d24 0x1ba8eb3a 0xa510b5b2 0x033d7153
+ 0x7e91532d 0x4a81361c 0x288d3cdb 0x563dd47c
+ 0xe7cd0eb7 0xfed9fb6c 0x4d4967a8 0x78f79653
+ 0xf1325f1d 0xc165b27e 0x3b92daf4 0x3796065a
+ 0x86eda8ed 0x8ac83880 0x4292f50f 0xd9afc9c1
+ 0x9fb0b6c8 0x14eb0c0c 0x26cf5e56 0xcd98b055
+ 0x1e40d460 0x872376a9 0xb5f0201e 0x90eb25f8
+ 0xb4239ea3 0x146369b3 0x778889ae 0xc64a629e
+ 0xd687e1e0 0x02663180 0xd37cfdf4 0xc3a99b90
+ 0x936df670 0x343064b5 0x65faa530 0xfd161930
+ 0x5d89793a 0x7cda7663 0x2a0078c3 0x9caff427
+ 0x7c7eb5bf 0xa738ac55 0xa3ec5238 0x50d6b47e
+ 0x6006e6be 0x9ce735cc 0x6f0b9435 0xefcd8529
+ 0x5e49fa2d 0x3c56e74a 0xe5953695 0xe9435485
+ 0x03350f9b 0x94fc5471 0xf8034f8e 0x1bfaf4cb
+ 0xd99c75e1 0x8509d572 0x1d7e45a9 0x932770e9
+ 0x5c830a84 0xdfb3fe3d 0x7e9d70e1 0x2780e800
+ 0xe8408a90 0x704f3051 0x0f0756a5 0x10c5504f
+ 0xa6c1ef11 0xeaddf020 0x7978f3a7 0xf6d772e1
+ 0x0282f5fb 0x3da228bf 0x93f3edd3 0x1a3c0f7d
+ 0x51845545 0xbae91b97 0xbae42cdd 0x497addad
+ 0x7e7d072c 0xff1bcd9a 0x3329bf18 0x215c3451
+ 0x5a1be9c0 0xc3db81f9 0x0583c1a0 0x134e3d8f
+ 0x979b3eea 0x90f6eee1 0x84ce4681 0x573c40ea
+ 0x5b93038d 0xa6a8548d 0xc6fa2186 0x5445b29d
+ 0xecb121a0 0x0d1526da 0x43c6a7a2 0x5263513f
+ 0x5d8cc589 0xef87c7a9 0x352c9ce3 0x7ee7e3dc
+ 0x29d35302 0xebcc2816 0xa73da8db 0x8d6ad8b5
+ 0xae2dd2ee 0xe3b008c9 0x560f1552 0xa049ef2e
+ 0x86bd5c68 0xd28c5e3e 0x8589bc6c 0x19d2bbe1
+ 0x94e340eb 0x8b1eebe3 0x4b57554d 0x0781be17
+ 0x916fa9f5 0x603c886a 0x3762bb9d 0x6a88e776
+ 0x070b02b2 0x02b511dc 0xcb0e2fd0 0x9f610d94
+ 0x205c39b4 0x030e84bc 0x105d5847 0xd59ee0c2
+ 0x4c000cdc 0x0414fef9 0xe7e5dba0 0x311b623a
+ 0x9f8c96c8 0x61af8dcd 0x8d669491 0xb00d611a
+ 0xd7fa1cc0 0x0c14260a 0x21e3145b 0x2575cab7
+ 0x4c21c29c 0x5d35eaf4 0x888c262d 0xa370d1a2
+ 0x81cc8ab6 0x09448c73 0xbcf40a87 0x76283841
+ 0x9a2fac29 0x0b4c4aff 0x109cff31 0x289fee1f
+ 0x942dfa79 0x221584e5 0x8918480a 0x3a3cf8c8
+ 0x8870c5bf 0x79d8e3cc 0x7a5127c5 0xf50ef1ff
+ 0xce14b7a4 0x815fdff0 0x984e925d 0x4e079d76
+ 0xc48dc46f 0xffc63e16 0x3b72b70a 0x3d65ac7d
+ 0x2d09b538 0xcdd74489 0x957827d7 0xbd28802a
+ 0x7bd3a4c8 0x0323f7a4 0xd2e0fded 0x1180fffd
+ 0x943e9101 0x39771bbd 0x3c9f2cfa 0xd43fc1be
+ 0x159378e7 0x23dfd475 0x7366b82f 0xf70424ca
+ 0x39252769 0x92e4e18d 0xbf985620 0xf0304d71
+ 0x840aee3a 0x26396736 0xfa14e721 0x8496038f
+ 0x3f75d64d 0x1a555d68 0x23fe7107 0xf91d6676
+ 0x3e26d6d3 0x000d3b87 0x175a5caf 0x234c6cd2
+ 0x1bc3abb1 0xeab04320 0x8654115d 0x7d3cd3b3
+ 0x5156a35e 0x98e39a23 0x1c35f79c 0x516f34ae
+ 0x455293e2 0xf44f7c95 0x61e01820 0x7d3edd82
+ 0x9213352f 0x08966bce 0x473cbff7 0x9d139979
+ 0x50b7f69f 0xf4264832 0x6e7fcd24 0x26756e8f
+ 0xe62b221b 0xa2609ebe 0x9e88ba86 0x5505ae8b
+ 0x7a096006 0x8a4811f3 0x103db4fe 0x40a48e38
+ 0x8635607c 0xd2f38d22 0x297e3b49 0x6c90a21f
+ 0x517de294 0x5295cd01 0x5077705e 0x8a21897b
+ 0xa0ac1da0 0x221cddbc 0xa1e9653d 0x8caa99cc
+ 0x1c8246ba 0xa50aeffc 0x3d5c71be 0xe2278aae
+ 0xefca9113 0x214ecfb2 0x3e46acd0 0xcd029c62
+ 0xccc5f799 0x13ba4d53 0x01a857b6 0xce918062
+ 0xcc023172 0x70d9c96f 0xceac54cf 0xe39ea79e
+ 0x411d6d63 0x0bd9756a 0x1ca60d69 0x1d09c516
+ 0xddd3d36b 0x7fdd11a8 0x62a744ed 0x1c47b291
+ 0xe1306284 0x3dffbdd0 0xf3243232 0xf1088297
+ 0xa6f0d267 0xc1508ef1 0x1df5a29b 0xddc37fd2
+ 0x1cf8ccfc 0xcffcaeea 0xc81be18f 0x2ccad7be
+ 0xe95737e2 0xc67b0667 0x7382caa8 0x4a4a58cd
+ 0x4247ddee 0xfaba56d3 0xde82cf7a 0x5301df88
+ 0x6c57cdea 0xadd20675 0x23c86330 0x1e16d63c
+ 0x02431073 0x23630e7e 0xb0e0e940 0x099ec0d1
+ 0x6e7e854d 0x5e0bae04 0x7c650f85 0x190c0f6e
+ 0x6d55b46c 0x97c0e70b 0xbab62ddf 0x8c52867c
+ 0x5063c950 0xa38ff7af 0xbff35da2 0x4ed590fe
+ 0x42b180db 0xe31c3a64 0xee1d74dd 0xff383c52
+ 0xd3e7252e 0xcc1d120f 0x02a7cbae 0xcfefc2bd
+ 0xa1abd1f8 0xbe007fd6 0xb1c208c7 0xae640518
+ 0xc903dbc3 0xfe049c73 0x9c10ab77 0x00fb4dbf
+ 0xba1fab03 0x94472765 0xfa6b1de0 0x45c382ba
+ 0xf9e82dd1 0x6c97ffc1 0x05558b82 0xe3c461e5
+ 0xfd0f4056 0x58b131b4 0xe0a1c278 0xe7b06c07
+ 0x4aeebbdf 0xd304f26a 0x841897e3 0xab607818
+ 0xf33dafb1 0xdcc5025b 0xaef62c8d 0x7c190674
+ 0x5ccf46b9 0xac4d8f10 0x55aa5bfb 0xc4808316
+ 0xf7bc5b55 0xe67fc285 0x91d33eee 0xe5e3b446
+ 0xcf268c0c 0x00715de3 0x562415b9 0x75e45b2c
+ 0x78cec40a 0xb6b452d8 0xe7d6c7e8 0x4d957481
+ 0xd2d3ee79 0x3e31ba54 0x6045c572 0xb77d5c0c
+ 0x92bdcfd2 0x0002d033 0xb866a4c5 0x95ee6deb
+ 0x9934a3df 0xdc53496f 0x5bcff76b 0xa17ae9ef
+ 0xa420b1ea 0x7cbef81c 0xca7cc86d 0xfad89413
+ 0xf2e1fc25 0xccd1d762 0x43a52cc3 0xb8f96294
+ 0xd05db9c9 0x760aed71 0x8b0d07c6 0x12e32551
+ 0x04a17e2c 0x5559875d 0x145a9f9f 0xe8dd21cf
+ 0xc81b8d9b 0x885bb782 0x93df24ed 0xdedbd4d5
+ 0x8385507e 0x0e2e03a4 0x8b61a48f 0x452ca6c4
+ 0x800c4bc5 0x3634577a 0x8a88f244 0x7c6952e6
+ 0xba284820 0x55849ccf 0xfc706545 0x59aaf00c
+ 0xe3554b17 0x4d56a632 0xb7d06485 0x8bdd62f5
+ 0xe5f4ef61 0x16d2e19c 0xf851bea2 0x32322892
+ 0xffb592b3 0xed4e8eaf 0x92974b49 0xb24d4db8
+ 0x615c7f1a 0xfdc82a12 0x42364455 0xfc550c10
+ 0xc8af5c1a 0x1ebede22 0x3a7c3fbc 0x5e573dc7
+ 0x0382b39f 0x1f05874f 0xc03e404f 0x31fd13fb
+ 0x2b11c5a3 0x162b8ae0 0xa6861122 0xe1b824d3
+ 0x8bcfddbb 0x4dbecd7f 0xfdc25b5a 0xd16e15b1
+ 0x55b5112f 0xf11217c2 0xd8139a4a 0x79d20da5
+ 0x2c34b064 0x7cfe7771 0xd311f0aa 0x8dddcf75
+ 0x3f493817 0x9b9b193e 0x2d5dfe6f 0x10f6042c
+ 0xe7b2f72d 0xece22f9d 0xdf4fa708 0x533574f8
+ 0x3341a9d4 0xd009d35f 0xc92922c1 0xeb24b1b1
+ 0x26a9e0ab 0x288da2ec 0xc2ca2a7a 0xdad44c15
+ 0x678390bb 0x306f8dcc 0xf3cc8f58 0x1f897400
+ 0x0b08ebb6 0xc6999962 0x2d25cdb9 0xdb05ed8e
+ 0x85e94793 0xde6cd4c1 0x70c01373 0x7e329df7
+ 0x65a75cd9 0x700b19e1 0xf481c94d 0xa3946dda
+ 0x32200c19 0x92baa53b 0x4fa53b3f 0xe71b63b7
+ 0x8a74a1b0 0x490e4942 0xd256b661 0x7ceca619
+ 0x181eee74 0x151effb6 0xaaa8753f 0xe9807163
+ 0xd3ffdd84 0x9957bf49 0xe664e8a2 0xc25011a3
+ 0x2d659ad7 0xf4b1414a 0xc4cca358 0x4d91d8b9
+ 0x7530beda 0xb52bd177 0xaf8e90d2 0xd4ecbabb
+ 0xfc9fef6a 0x1344e0bb 0x39bbb6c1 0x9f4c25b2
+ 0x27c6efdb 0xb9b35e6f 0xae97797a 0xdd85fe41
+ 0xa32fb35e 0x063e2404 0xdea1a837 0xafde0fab
+ 0x55882c4e 0x38b4e391 0x437e49aa 0x2d46d297
+ 0xb2bd8e6e 0xae36a3e6 0x1977f2da 0x46ba42ee
+ 0x3f048c68 0x5f96ef92 0xea6eddd0 0x38539fde
+ 0x3cad4c53 0xda123f1b 0x7c08143f 0x995b4425
+ 0x91e7f202 0x13b3ffa2 0x6122c76d 0x27338748
+ 0xbbf19aa8 0xab13342b 0x1df4d24d 0x95d8e41f
+ 0xa85f001b 0x8b6617c5 0x8387c326 0xc63a9172
+ 0x13d34c19 0x17d87d92 0xa9865c60 0xbae3f512
+ 0x601f9f72 0x6dba49ef 0x4d62cd06 0x2cf42dc2
+ 0x5ae11fd1 0x50a35fd7 0xd7795dc7 0x40310897
+ 0x1a4bb21f 0x8c8113f5 0x55bcde16 0x2fa12370
+ 0x5c6a1c19 0xc13b2571 0xd54d67c3 0x5d9674d2
+ 0x5b28b05e 0x5dde9781 0x06a4e4fc 0x30b40878
+ 0x171a86c8 0x641386e5 0x8e04cd61 0x632b95ba
+ 0x9e802e0f 0x2b7a5305 0xeec8ea33 0xdde05bdc
+ 0x454500a5 0xc279403d 0x1bfafe51 0x8032d0ea
+ 0xa398b329 0xd6db01f5 0x1e4d454f 0x2f8c8fea
+ 0x1bf7f3d9 0xead8f047 0x8b192c4c 0xc6939f19
+ 0xe16366e7 0x107216b1 0xabd7780e 0xa24beece
+ 0x4a04cfd4 0xe633886b 0x6acf4b15 0x85d74b92
+ 0xde3358fe 0x765dfd80 0x3a14896d 0x9cc0fe2d
+ 0x7550516a 0x05f7ae59 0xfe0b042b 0xe1d7c935
+ 0x7a2e68b6 0x27d84d32 0x86f9f688 0xfc79d99c
+ 0x9f18fa11 0x0eba09e1 0x5446dac1 0xc19da943
+ 0xfd7aed7d 0xaca9b65d 0xc93f6976 0xbfeec780
+ 0xb76d13b4 0xf872fd7c 0x31a67785 0x8f1869d1
+ 0x5d95d16f 0x0eb43e3d 0x5ecccdba 0x39852805
+ 0x92c43fbd 0x1c36738d 0xa08b382a 0x5da59286
+ 0x059315ee 0xf3186365 0x5515e98a 0x23ef39aa
+ 0x1dbd4089 0xbd7f88bc 0x1123394c 0x967440ae
+ 0x97bec31e 0x4d7ad282 0xd6d8c9b1 0xa06c9673
+ 0x96c73bf8 0xd58c200a 0xbabba6b4 0x1bef7dc8
+ 0xba26cf24 0x92cb0af1 0x592f13fa 0xef4cdc58
+ 0xd65e4cb7 0x48c4106d 0x1bdb7acb 0x65a4887b
+ 0x1eb6f79b 0x7af8d180 0xfdc90059 0xefec18be
+ 0x4203d88c 0xbf756ca8 0x6b11faaf 0x507607ff
+ 0xb2af9e23 0xc74f2d6f 0x568e33ec 0x33bdb129
+ 0x63748473 0x0a1bafe2 0xdd82c263 0x93e2fcba
+ 0xe196494e 0x52005967 0x2be26f02 0x591332d0
+ 0xc8ac5d46 0x17088f44 0xeca12983 0x3799c4fd
+ 0x47f62095 0xeda06c65 0xf2cb3455 0x117e0c68
+ 0x74fec213 0xc8a652ff 0x338e4840 0xf590dddc
+ 0x0a3ee9fd 0x60e23d83 0xb44d23a6 0xe1920037
+ 0xdce96701 0xfa34277b 0x9f9ab88b 0x8cfb722c
+ 0x66431f59 0x4c37f1a4 0xfbfab598 0x95ee3437
+ 0xd338f436 0x4cd9d0be 0xffad23d9 0xa3dd4d6f
+ 0xfd4b53dd 0xdb5bc57a 0xddf2baa0 0xfdceccb1
+ 0x12025458 0x2f29cfeb 0xebfc2d0a 0xb8d6509a
+ 0xe7ce0731 0x0d8c538e 0x6454c057 0x8911157a
+ 0xe99ae359 0xb7c960c9 0x1eab1fd6 0xda058037
+ 0xa08e7b63 0x45870d45 0x0fb167a3 0xad25fed6
+ 0x0844c4d8 0xfee41e4c 0xdd53b488 0x096c6c8f
+ 0x5e6a34b7 0x5c24aafa 0x39df9116 0x101795ae
+ 0x020add80 0xd644cd6d 0xfd1d7c12 0xc59116ed
+ 0xe0b15366 0x90f56459 0xe035796f 0x698a88ed
+ 0x78700bca 0x0d9fa980 0x6368b93f 0x61feac15
+ 0xfd82b21f 0x8c694a54 0xc317fcf5 0xc2a18c95
+ 0x2a3013ad 0xf83fef17 0x44467b9c 0x4047b2c4
+ 0xdd920d54 0xd487e3f8 0xf0f92f79 0x13e48f43
+ 0x9705bf94 0xfcbc9e3b 0x6d12d9b2 0x985ee1b9
+ 0x2e24fa3c 0x46dd8662 0x1cc299dc 0xd21b40b2
+ 0xeaeda8dd 0xbfbd1a40 0x8e1a0a8c 0x56a40b91
+ 0xf95cece6 0x3a287e01 0x9e0907b9 0x3309b654
+ 0x9a5079bb 0x36dbb78b 0xf87c0669 0x775ae8f6
+ 0xd4332970 0x2a2a5975 0x28b0767a 0xc110195c
+ 0xbf8f47a5 0xb7b9ec93 0x209d3c7d 0x553d8613
+ 0x63559ade 0xf692bf89 0x4da236db 0x8d5d69c6
+ 0x0991cefa 0x8461b5a7 0xf1d154b4 0xfdaab3bb
+ 0x2959c2fd 0x1d5f7b82 0xe730df15 0x11011c88
+ 0x016c4062 0xf8d7b303 0xa8ec06f1 0xdc49a98a
+ 0xab73e277 0x6566e521 0x566feb86 0x29bb70ed
+ 0xa163cef9 0x5e927c40 0x5acffef7 0xefec277d
+ 0x07d1c031 0x63efda30 0x52aa8e08 0x3826c55f
+ 0xf09909aa 0xdabc930a 0x8266463e 0x3b83fcf8
+ 0xcc37dfb9 0x21d64edb 0x9c3b4dfa 0x39fce836
+ 0xbf169f0a 0x034979bd 0xcfb36d81 0x381c7551
+ 0x28e54be1 0xa8101c44 0x0179404e 0x0ea377f3
+ 0x33b8f2e9 0xb7169617 0x9cd2eb38 0x767db03d
+ 0xaf40bf7e 0x0ea102a9 0x7a5efc59 0xf2c4b32c
+ 0x1547d8bf 0x996d0646 0x77aa0e71 0x3955d7bb
+ 0xdd2b7fa2 0x08d5f569 0xda2425f2 0xd87cb778
+ 0xa846b6ce 0x047c29d1 0x038a55a5 0x3dfac25b
+ 0x3edb60ee 0xbbecb7d1 0x45095acd 0x3f135521
+ 0x2f01df8d 0xc1e41e56 0x454d7265 0x85a2d14d
+ 0xa233c32d 0x18413260 0xda873753 0x3084d995
+ 0x3bde0b3a 0x96523ec2 0xdf924ff3 0xb00ec764
+ 0xda13676d 0x58bc42bf 0x2829a06f 0x2efba826
+ 0x00ffe1ad 0xd6b5cc2a 0xf53ff94d 0xcd685cb6
+ 0xf9bed7db 0x0b4ddd1a 0xe8a448de 0xc495727c
+ 0x68cf6052 0x11cf0218 0xb63d6908 0x24c1b0e2
+ 0x75eaf5c5 0x7114c81d 0xd596913c 0xf8310f81
+ 0xa1dac3da 0x50c235a5 0xd535df89 0x835ccdf1
+ 0x2f0a0505 0xd6d76b3b 0x3a203ed4 0xded4a58f
+ 0x7b7dadea 0x9103eae9 0x4ee7f33b 0xe785e1ce
+ 0x5e0633f6 0x70beb9c8 0x145d7ea5 0x9e7891a8
+ 0x2845916e 0x1a61b6fc 0xd90c9265 0xf915e61d
+ 0xfcd5c8ce 0xa0f12501 0x6e2dccb1 0x388ecc82
+ 0x9519ce00 0xbdefe148 0x1392dec2 0x58e97609
+ 0x5bae1b18 0x69929d43 0xc2346b30 0xfa4a2e99
+ 0x9ab7eb3e 0x3eb11055 0xd16d2ddf 0x7b70f2c5
+ 0x55187d91 0x7d2c7520 0x0e69f3ab 0x5e2509c5
+ 0x728e44a2 0xd7a612be 0xbabc885b 0x93016436
+ 0x60258064 0x4bc489ff 0xff9de32a 0x98dbc15e
+ 0x48eac41f 0xf753d2c6 0x3661eeb3 0xdaab4d1c
+ 0x5d81d91a 0x8662b646 0x5952bdc3 0xe38c69e0
+ 0xc8537ec1 0x6a9492b9 0x02452afe 0x8f06dd3c
+ 0x565a0d06 0x67da4191 0xdc48099e 0xb777bb54
+ 0x5d857773 0xfd4ad163 0xd49a6672 0xb2ef80f1
+ 0xc6a96c41 0xa6e8db1c 0x6700f1a3 0x683d6730
+ 0xa4580400 0x5feb5d8c 0x72dc9b68 0xf40dfab9
+ 0x750400de 0x7cc468b3 0xa3e36eb6 0x5e029d98
+ 0xd4632a18 0x527a7d4c 0x62bf1ab9 0x7c3a71b1
+ 0xefe9c651 0x5e812162 0xaf0bf476 0xb11b216e
+ 0xcac9f3db 0x9f068787 0xa4230a9b 0xc4ee7735
+ 0x091099b9 0xe0c89a2e 0x844b5e78 0x9a208c07
+ 0x86f48fe6 0x1f2b8bac 0xc8873d41 0x7380cce6
+ 0x1f80f956 0xe9ca8d9e 0x4baddaf9 0x2687537f
+ 0x9d4e2f19 0x8a634fdc 0xa5c1c324 0x258f1e18
+ 0x4399e859 0xe43a7e7c 0xd572faca 0x914bcf39
+ 0xf2dd53f1 0xde126168 0xa4940acb 0xc8edb772
+ 0x4a089deb 0xe9308ae3 0xad97a55f 0x8853ae8c
+ 0x976d4337 0x919b885a 0x155ac377 0x5ffcdb2c
+ 0xec335ab0 0x4118c00d 0x10f6d291 0x89adb1bb
+ 0xf514c024 0x2d6513dc 0x8b8743e2 0xff2fa127
+ 0xf4be8a38 0xb54de614 0xaf2688c9 0xd50dc4ac
+ 0xdf71a920 0x7556deb6 0x2b0a08f4 0xeb47487d
+ 0xae9244df 0xf81216e3 0x42699e0b 0x953ce6a5
+ 0xa3fcb558 0x76547905 0x95086ca7 0xf29f303e
+ 0x027975ae 0x313b5bbd 0xa8f8d662 0xf32c6538
+ 0xa4c44558 0xe626d8aa 0xe7b73b5e 0x21957cb2
+ 0x4f830a34 0x713f6e71 0x52241020 0x4f152bfa
+ 0x1efe2a53 0xf45c268c 0x569e09f3 0x4878ef31
+ 0x77198eae 0x0057bfe0 0x71541c01 0x1eff510d
+ 0x34d84a6d 0x43787da0 0xdc4bbc4c 0x9c5656a5
+ 0x067a0908 0x806d8a21 0xff3cf1eb 0xbeb9435d
+ 0x5dd154a3 0xd4cf6735 0x376e86cb 0x114cbc28
+ 0x4e26f648 0x9e15b6a0 0x57e5ce4c 0xb9a084f1
+ 0xd9a0385e 0x4cd29cd6 0x80287ea5 0x12609d95
+ 0xc705541c 0x0b9cd2a2 0x98af1097 0x0e0ccec3
+ 0xdbfb6216 0x370549c6 0xe36cd94b 0x7a71d4b0
+ 0x09e51ffc 0xd83c2c6d 0x32e63037 0x87b7c18c
+ 0xfa74b115 0x3045a93c 0x146ecc07 0x329bf17f
+ 0xcc50fa94 0x6ae5027a 0x9ec70396 0x9b8f3ecc
+ 0x565335b9 0xce0a5dfa 0x2b41d3cc 0x6f20e5d8
+ 0xd1ab9ee0 0xd5f04207 0x4296927a 0xe5c629e0
+ 0xf7b776cd 0xdec98eae 0xff1fe0ff 0x2fe2e3f0
+ 0x9ffe3481 0x3f649922 0xfd960e99 0x88ffd8e4
+ 0x417db733 0xb233f1e7 0x9dbb56ae 0x271646bd
+ 0x8f6a6a2d 0xdf70cbff 0x64ec8381 0xfe97aca2
+ 0x48a8099f 0xbe96d90e 0xd32416b6 0x0136efca
+ 0x71676cca 0x9d6ba000 0x5c040306 0x0ea08882
+ 0xd41a8ef9 0x30dbe3f9 0x73e822db 0xd791f185
+ 0xacbe39d6 0x4ea7b8b2 0xde3092f1 0xa1b98671
+ 0x83507aeb 0x3be451ba 0x57c7c672 0x773399f7
+ 0x9cef2b76 0xaba00924 0x4a333a0d 0x59bef9b7
+ 0x77b7ae3f 0x7cbc022b 0x99825bdc 0x6b434156
+ 0xbe86d9d7 0xdfd89b81 0x615301f0 0x645c2004
+ 0x81a0d706 0xfa5fc5b3 0x3ddea2ac 0xf8b77c77
+ 0xdbb9afbf 0xb2966f32 0xa9ef0668 0xf80a9fd0
+ 0x46b678fc 0xa5e4783a 0x585cd0cf 0x8dd017a3
+ 0x5df45495 0x0f96a151 0xfbcc6c28 0xbbb01982
+ 0xc60b9014 0x0da33bd7 0x3f8c9e48 0x4bcad7ee
+ 0x8f29bea0 0x434bd06d 0x2d40ee8b 0xf674fefb
+ 0x7d13c2dc 0x8b102d90 0x25ee47b1 0xee42f973
+ 0x6abff5c0 0x90337ecd 0x650b75fe 0x57592038
+ 0x9b8172de 0xa818a53a 0xc9ba76c0 0x84f6302c
+ 0xbc2dacbc 0xa33c4350 0x05ffcbf9 0x46178e9a
+ 0xb8802aa7 0xb77cca54 0xc4acf832 0x6329da72
+ 0x9e0bc1d4 0x4dbad7cc 0xcc1435a6 0xf62df35d
+ 0x23bf4f9d 0x5655c820 0x8f362a62 0xbe3c7c4a
+ 0x7db11ca2 0x3a5c8fd5 0x04b9598a 0x67a21cf5
+ 0xfddeb57a 0xcba92e27 0x85dd2a2e 0x410c03f2
+ 0x37d01792 0x52fea426 0x6bfdf31e 0x63cb798c
+ 0x6fd48d31 0xac08449f 0x76fd6be5 0x59b6f6fa
+ 0x7d7bb61c 0x8a921346 0x5fa14930 0xd00ef222
+ 0xbb5d6d04 0x7e4542be 0x56532853 0x6074a287
+ 0x21f8b4fe 0xb91b2398 0x72287a1a 0x4edce9fb
+ 0x5418c044 0x3b90ef86 0x38620751 0x9fed1072
+ 0xc8d64b1d 0x397a4379 0xc0534beb 0x806c80e5
+ 0x309b7d0b 0x0ffe292c 0xefb53f50 0x3cd38191
+ 0xcc5a6cd9 0x1dca92dd 0x3f7af05f 0x796e20ab
+ 0x1715da6e 0x5bb48b9d 0x8a06a2fe 0xe06fd98b
+ 0xd7a429ed 0xea2c8ec4 0xb365f13f 0xa803131c
+ 0x1ebc16db 0x1e85595e 0xa370b578 0xd3036dba
+ 0x0d97668f 0x6ebf2e28 0xde53e48c 0xef8d9c9c
+ 0x1697a020 0x65362f2f 0xab0b2447 0xf06ac16b
+ 0x68cd2cc6 0x8dee764e 0x41c7f21b 0x89a7d310
+ 0x171bfbeb 0x93233fc8 0x4b72e18b 0xef38bda3
+ 0xe5a9b23b 0x1f4f7ea1 0xeed90665 0x2f8899ad
+ 0xcf933790 0x878ec306 0x59c63347 0x73da1ec8
+ 0xcd703bfb 0xdba0f460 0x412023f7 0xf5ac4823
+ 0xfd3d5203 0x34b71f30 0x280e7077 0xfab4283f
+ 0xb666f47f 0xd5410131 0x79f36bff 0xa94a4d26
+ 0x100c5a04 0x4f588fd2 0x6630ad71 0x26a5946e
+ 0x7f690901 0x82d8e4e4 0x99bfeafd 0x687f3ab0
+ 0x6c99abba 0x988bc7a7 0x23c19c3a 0xae9a5d40
+ 0xd0545a03 0x4b9eda6b 0xfc01747e 0x6c02950c
+ 0x099d4e73 0x32bc7385 0x299c25a6 0xe8a3095c
+ 0x3acaea23 0x893b3b01 0x7ce8a326 0xa4ebeb1a
+ 0x64509259 0xd9eebbb8 0xa88fd8b4 0x7b92ed79
+ 0xb41eb189 0x50bebf8c 0x9763eca9 0x861359cf
+ 0xeb0716f4 0x34d23cee 0xdb7a4372 0x193cb7cc
+ 0x7ea76d3e 0xd26c0d17 0x080753fe 0xdacb9dde
+ 0xbcda60b5 0x64f756ae 0xf19ded12 0x69775827
+ 0x9d581039 0x444e92ea 0xaf3fe40f 0x49c17460
+ 0x62b3f21e 0x2e20a0dc 0x9d1e7d46 0x66a6a703
+ 0x45c8ada5 0x6ad9e74e 0xa0ab96c8 0xa0c1ddfb
+ 0x9ed0fd66 0x659c874a 0xf3ece1d8 0x1b0302d5
+ 0xa4ab0a5b 0x78e4ad92 0xef11406b 0x3a02e6ec
+ 0xf733a593 0xea7a3997 0x0f4930b3 0x18ca72cd
+ 0x8e312e70 0x345fc898 0xb38aedd0 0xbc7adf8e
+ 0x580b9f57 0x7dd53eb6 0x1f0e7300 0x5524f2fb
+ 0x25280378 0x45dddae7 0x2f1b38fd 0xd9c448f0
+ 0x4c561bcc 0x72d2320e 0x23de442b 0x7f5b9046
+ 0xfdd80059 0xe9ca2598 0x5527ef4e 0xc834b9bd
+ 0x1dbc357d 0x2656f81d 0xa9549423 0x338e5639
+ 0xc19706ac 0x0ca6028d 0x86ef336d 0x6c822807
+ 0xe40fb194 0x4de2320b 0xb9eef8be 0x33655612
+ 0xa2cd1803 0x480ce7cd 0x51c19215 0x68f2c282
+ 0xdb097679 0x0f694612 0x03d9bf77 0x3f1e04d9
+ 0x3e613825 0xe5833060 0x729a811a 0x2a4ae763
+ 0x05cd1497 0x8fbe47ba 0x04e83aa2 0x505717f0
+ 0xbf0b978e 0xd378cc7b 0xeee38551 0x5092a751
+ 0x52dd9f6e 0xd59ee759 0x4528f839 0x2003c88b
+ 0x10b9afa8 0x0bb880c6 0x5bbdc70d 0xe9b5e179
+ 0x0941507e 0xee252bf9 0xea772da9 0xf099310f
+ 0xf6fabcb0 0xf038e392 0xac061a3f 0xd51656f1
+ 0x514935bc 0x3fd22f7d 0x254b06a8 0xff2877f5
+ 0xd848996d 0xef66e1a9 0xf79ed46c 0x2196e979
+ 0x522b472d 0xcfedf066 0x9a768bda 0xd48632f4
+ 0x4773ccbf 0xec4435f4 0x46f7be05 0x2bc5d794
+ 0x03f31d81 0xfb7103cf 0x3dedb78b 0x9fc36042
+ 0x2280e88e 0x4d250150 0x8fa7e54d 0x5cdaa33f
+ 0x4b52bf85 0xb32a714f 0xce7a9013 0xed0fcb60
+ 0x8718e79b 0x74e26a9e 0x1fb725a0 0x6e8a63af
+ 0x332eb12a 0x36c32a05 0xcc456676 0x95dc04d1
+ 0x77f85170 0x304a6906 0x8612e7d3 0xde994cd9
+ 0x0b285e4a 0xe60b523c 0xabbfd040 0x374c76b0
+ 0x5e40f411 0xe93f8f9d 0xd55059cd 0x2c40bb2c
+ 0x1d0bc87b 0xf258dca2 0xb66c26da 0xead5a854
+ 0xedf1ab2c 0x2392bf2f 0x3480ebc9 0xf5f1dfab
+ 0x4336fc17 0x89bc6f5e 0xf794b812 0x12300220
+ 0x8cf10ef0 0x55d78885 0x5c0cbf25 0x1915799b
+ 0x52b6d7e1 0x310bdab5 0x07edfb80 0x243abead
+ 0xdcf99a9b 0xa9c5148a 0x12d2c0c2 0xc1478005
+ 0xd27224d0 0x3bceb6d7 0x9e033549 0xe132349b
+ 0xdf5a4ccf 0x3e777127 0x8a2233fa 0x3758bb10
+ 0x85ccb13e 0x7b8155b7 0x85bf5cb4 0x26a7a7b0
+ 0xcc84ba7a 0xcc0285d7 0xf416da1f 0xffac6701
+ 0x95ac6f58 0x3cb13304 0x407406d7 0x14d99a71
+ 0x1cc0fdba 0x298468d1 0xbea241a6 0x126fdf79
+ 0x8875ee25 0x9f6226ba 0x64678e21 0x2509f53c
+ 0xffaf9851 0xe812f808 0x8ba956e0 0xf457db00
+ 0x518fe465 0xf160a88c 0xe448bdce 0x930c070c
+ 0x3c5c081e 0xca3ae614 0xa831d664 0xf7c4368c
+ 0x08fe2afe 0x1adf7b81 0x17f6d3f3 0xb2fee3ec
+ 0x9c28bbc0 0x79542475 0x286ef63f 0x4359beff
+ 0x7e883a76 0x197d355f 0x63b49b54 0x863a746a
+ 0xbb27e270 0xd341236d 0x12f44393 0xb466e0a4
+ 0x1d76fb92 0xfa41d1b2 0x1d8c4a73 0xb2d9dd7d
+ 0x86b63425 0x425d7223 0x15de6bf6 0x925a9489
+ 0x2bb11f48 0xf6dbba84 0xb7a7d5ef 0x20962b37
+ 0x02d0d4ef 0x8cdb97c2 0xdca7fee5 0x149444e0
+ 0xec103a29 0x7f51f8bd 0x4d5c6758 0x9eb4446d
+ 0x6ebaf66c 0x02325a25 0x8bdb761a 0x650dd77a
+ 0x1c8e75bd 0x0837afc5 0x6472dfe2 0x3830220c
+ 0xf317f6a3 0x8554a846 0x342a150c 0xe4ace9d1
+ 0x4ff2e1b2 0xa4d50080 0x95d1c85b 0xc5dfc5a6
+ 0x0766a97a 0x71b2cec1 0x8043996e 0x620fb5ac
+ 0x35cc0e1e 0x9e0be88b 0x1bd723fb 0xdbe05966
+ 0x8d7928b2 0x97561525 0x857d12a9 0xa84475bd
+ 0x94a6acd0 0xda298885 0x9a039423 0xae6cac16
+ 0x7a76851f 0x70277277 0x50a53b6e 0xa9100daa
+ 0x4090b164 0xc5dd2129 0x02475e30 0x1cc65bae
+ 0x85790253 0x5eea73b3 0x1b4343a3 0x13ece90f
+ 0x470ac2b9 0xf61841e3 0xef6655d7 0x1992dfdc
+ 0x5f5112ab 0xb4dd51a3 0xc5e87b31 0xb65f3d2d
+ 0x070e9bbf 0x05ffd055 0xf609c346 0x65fbba75
+ 0xc9108013 0x7bfaa5db 0x49dd3066 0xcd8c524a
+ 0x99d8fcbe 0xfecb842e 0x739feb70 0x79c75772
+ 0xe4cd3f68 0x1b062319 0xd3360038 0x7658335a
+ 0xabee5b58 0x466809ce 0xde21f2cc 0xa197a1f5
+ 0x92287d5a 0x21a75ff8 0x095e0058 0xa38bf1a9
+ 0x57ba37ab 0x4747ff64 0x4a12b779 0xc12ddd5f
+ 0xe7a19a45 0x1b927ca7 0x88144955 0xd35ef843
+ 0xd068337d 0x5632330b 0x65a34c89 0x775e9caf
+ 0x78c20a0f 0xff1c2f5c 0xdbdd9887 0x7f48e40d
+ 0x54ee1f8b 0x65d42710 0x5fc0d0e7 0x15fce5dc
+ 0x318b5abe 0x7860c719 0x6f63f527 0x95bc6f90
+ 0x58c37cc6 0x4334f068 0x3f51dc09 0x851a2b85
+ 0xe82b9da0 0x7d265c4c 0xfd8ebab1 0x83d54210
+ 0x3f74b74a 0x7ee0c3ca 0x61a3a8db 0xb0b704ef
+ 0x477cd2cd 0x2a796236 0xfc383efa 0xa6ed3b51
+ 0x24791edf 0x80562e6f 0x1273a1f5 0xc74e5921
+ 0x3779b3e6 0x7a3f32f0 0x49e60afd 0xa5d0fe64
+ 0x8ef054f6 0xef5be639 0xf692e588 0x54044e06
+ 0x3f27c315 0x55bb8f4a 0x96554540 0x550e1a56
+ 0xace36033 0xff19182f 0x86a5bd4c 0x85da4168
+ 0x986a002c 0xd7857384 0x76af389e 0x68ad939e
+ 0x2b70c6f2 0x449ee188 0x92c907ea 0xbf2764e4
+ 0x3bb587fe 0x783d282c 0x45534e20 0x10658cc2
+ 0x4de7c28b 0x0a1c55a5 0x2bacd66b 0xf0a46ce6
+ 0xb7ec3bbd 0x1f5e80a8 0xdd058c42 0x7332d51d
+ 0x3cef2355 0xa3b65cb8 0x1ee63aca 0x9f957ac5
+ 0x0281c9dd 0xd26aeb78 0x58cbb21d 0xac33a189
+ 0x7ee718e5 0xee82aae0 0x02a7047d 0x97ab6b72
+ 0x525cedb4 0xe2349594 0xd5ae4bf8 0xa339d3c8
+ 0x067f1b36 0xf64bdbf3 0xe9a3ddc6 0xa4c5c24c
+ 0x6e353ab5 0x0738144f 0x47a2447f 0x9e68b3ce
+ 0x78e80afa 0xf940582b 0xb89ec8c9 0x2c6d309d
+ 0xd61b1cfe 0x9636289a 0x6117fba6 0xc79f8986
+ 0xaf1541bb 0x9c0ac0e6 0x8387473d 0xb9fafa5f
+ 0x6a579a20 0xd3f7bde5 0x5cafa55c 0xc4b019eb
+ 0xd5898c2e 0x773a5c0c 0xb0094e24 0x8911c4e3
+ 0x5c1617aa 0xea4d1e5a 0x4ca917bb 0x616d3d63
+ 0xe78a22a2 0xdf438e2f 0x2a95a02f 0x7bab22b1
+ 0x7e10fe4b 0x419950b2 0x416176a3 0x87eb366c
+ 0xdab47c2c 0xf1ca38ed 0xf3e0a547 0x7a17a658
+ 0x302b56f9 0x49c64bd4 0x73411255 0xeced949e
+ 0x7b34d21a 0xfb29e71d 0x73833d01 0x03394245
+ 0x29976efb 0x43283d82 0xe99524fe 0x86cd9b90
+ 0x53908651 0x4bc2181d 0x9e5edd8b 0xa422354c
+ 0xc027e7e2 0x8ce2db84 0xc58d19ce 0x355c8b91
+ 0x25018861 0x1c72bb1f 0x751abe69 0x203350d5
+ 0x7a483fa4 0xb2c3f20e 0x1f0a5ba0 0x01b7e2eb
+ 0x1a043812 0x7103279b 0x96216501 0xce39d080
+ 0x637f4509 0x2dc69eea 0xa4efc113 0xa5d30a2b
+ 0x58340b23 0x028a5b36 0x55f38544 0x6a1446f7
+ 0xd1414b79 0x2911a443 0x0db0caff 0x5da8e7ae
+ 0xba030f57 0xe3aae6c2 0x0b058245 0x87da158f
+ 0x37e8eead 0x321192c6 0xa450f2b1 0xf1a7353c
+ 0x2a704f83 0xce0feef0 0x7d817a79 0x26831535
+ 0x365a1cd9 0xe9e2d8ee 0xe8d0f555 0xb4293ebe
+ 0x2795664b 0xecf43916 0x1a2489e4 0xfb7a2f91
+ 0x524f46eb 0xc580b7d4 0xfb48ec9f 0xe9edac5d
+ 0x687e2734 0xd4d78bfb 0x1c6693a8 0x9204e278
+ 0x2b030f0a 0x1c1e5dde 0x1233cafa 0xb28f23fd
+ 0x3e9ec6d9 0x340daf97 0xeca43ed2 0x7580c01b
+ 0x98bc3331 0x81df920f 0x66fa4723 0xb5576074
+ 0x560b0b7b 0x2b330f51 0x11d4383e 0x2403d863
+ 0x2ea9ef88 0x0a4f364c 0xff826ec8 0x1a2b598d
+ 0x27336491 0x3ed50c05 0x7fa670e9 0x117c4928
+ 0x4f7cb2e1 0x0246bfb8 0x0299dfb8 0x25da1033
+ 0xc943c492 0x0c928512 0x88231d4b 0xfa8cd638
+ 0x648b0dd2 0x8dad6a9e 0xa6fee246 0x48c260f4
+ 0x89f51cd7 0x45d87837 0x7dbc8e53 0x43ae16d4
+ 0xb6537ed6 0x5623ab3f 0xa9067ff4 0xe7357501
+ 0xb74554de 0x8db2a8ee 0xb1e92a76 0x6e8970ad
+ 0x5266a3f0 0x90df4e6e 0x8d646d19 0x4cedc27e
+ 0x2bf8d9b2 0xf525778d 0xbdd502ab 0x51bab600
+ 0x4eb5b0fd 0x7fe503f6 0xb93e599e 0x2e7d6071
+ 0xdde8884b 0xc91c3510 0xa8e14896 0x1880e079
+ 0xa4c89f7d 0xadf62f1b 0x6ff233d7 0x3be5bfb6
+ 0x6d105d93 0x120397d9 0xfed419c5 0x205a6631
+ 0x4d0ccb3d 0xae0e1f09 0x86b9112e 0xcdf2228c
+ 0xa0e388cf 0x7456f52f 0xed2d99fe 0x6914f63b
+ 0x00feaad2 0x8733d05f 0x2c466ea4 0x7fcff031
+ 0xa529f5f0 0x729f8fa1 0x7df47b76 0x1f711f4a
+ 0x81e6e406 0x5eb25e9f 0xf762231c 0x26420e88
+ 0xae513342 0x6b1ad7f3 0xa5a6a7c8 0xa1ddb22c
+ 0xb838a4c3 0xb227f5ff 0x6b86a07c 0x99414531
+ 0xde3a3511 0xc284c098 0x3946172d 0x8797e956
+ 0x5287bf4d 0xdc668157 0x514f837a 0x0898e1b2
+ 0x923d59d4 0x9bd5b501 0x24ab0c95 0xd9a6b20a
+ 0x938f61e6 0x14ff757f 0x285003aa 0xdaa7c43c
+ 0xd1831a8c 0xe3ee3682 0xf1840914 0x3925fe7d
+ 0xf0837c25 0x10228862 0x17fa9af4 0xe7dcc72a
+ 0x1849b0f5 0x51320d1f 0x0333beea 0xc35685e7
+ 0x0160dbe9 0xca507680 0xd6f2f43b 0x4c9a31d0
+ 0xdf6460dd 0xaec8cba3 0x52c8bdaa 0x2664c6ee
+ 0x4b3288c4 0x53cea59b 0xfb6ace34 0x41dc20e1
+ 0x6a5f4706 0xbbedb5f3 0x9f37322e 0x44a09752
+ 0x2ab91444 0x57b4ada9 0x6afe576e 0xaeb73b50
+ 0x97d3de4b 0xfec4d616 0x29896080 0x43fe8c34
+ 0x83842eec 0xb08f170d 0x03c432a7 0xfefc7b82
+ 0x51f66600 0xed503541 0x03b6608d 0x8e3ad843
+ 0x4bf99ad2 0x614c069f 0xce7641b6 0xd27a6f9a
+ 0xd40eaa7d 0x110c143e 0x352d0651 0x4473dffc
+ 0x5d40252f 0xa25db878 0x7df32c3d 0xf4ef6edf
+ 0xeaf881a4 0xe88b9a18 0x7df554b9 0x1891b621
+ 0x55af4ac3 0x8c39df79 0xc4c205db 0x4b34c0c1
+ 0x8c0ff68f 0x72bc50d3 0x5f99c8b5 0x7ba6188e
+ 0x798c3d10 0x26870c75 0x90a64bc3 0x6979b922
+ 0xbd185fdc 0x6b661e71 0x0beab544 0xbe84004a
+ 0x3aa803bb 0xb1e808f0 0xaf7e7b83 0xb12a39d7
+ 0x616490f4 0x920b37c9 0x857eea29 0x6d6ca978
+ 0xa8388103 0xf4218257 0xfc9a0717 0x4c739240
+ 0x3e79ce00 0x3dfd18eb 0x37138fa4 0x9894c467
+ 0x507d7d56 0x26c1bc89 0xe787e45c 0xdf554cc5
+ 0xd2279a50 0x5b172582 0xcc5d24a4 0x7dafb34c
+ 0xd4b16c6a 0x21b79147 0x89e1024e 0x04094b5e
+ 0x850c0a4b 0x0c7cf33c 0xe4da26f7 0xa1a62536
+ 0x920afaa2 0xba63c038 0x16591450 0xcb6c34ae
+ 0x29464a83 0x1cc673d5 0xa530ea51 0x265ec529
+ 0xe30bb676 0xbf18606c 0x3f12df0f 0x1ab669d7
+ 0xeee0c289 0x33106be3 0x00e39909 0x5a312123
+ 0xcbda8bb2 0x0d3ec086 0xdd7c0f83 0xb7ecd1e6
+ 0x1b3002ad 0x737b819b 0xa5dd3b45 0x632f9c32
+ 0x0ab37cb8 0xad7eb92e 0x6e2d114c 0x586e0994
+ 0x2af40df2 0x5501217c 0x0ab62f0c 0x3b7100b8
+ 0x0dc35d9d 0x3937491e 0x04f37faa 0x6933c2af
+ 0xf1e2c593 0x8c66b14e 0x7d542e43 0x970d2632
+ 0xd49e3d2f 0xaf9d7d2a 0x327e5488 0x871a50fd
+ 0x3f1158fa 0x2f3838ec 0x9617a31c 0x16e2c967
+ 0x09710826 0x077a1657 0x95a1abe9 0xea49bab3
+ 0x32ee12a9 0x2d49626e 0x9b95c7dd 0x4846b0a7
+ 0x9cfae6bf 0xa9f862b6 0x3e3d167d 0xa544a3e3
+ 0x94cccf7c 0x8b97f7c6 0x022b9624 0x5b60bf75
+ 0xbd533ed1 0x133cc7d5 0x3853ff82 0xca2bd76b
+ 0xed552e3d 0xf133d2d5 0x652c0f02 0xdec8249c
+ 0xf61921ad 0x09a9e3a3 0x2229e133 0x01afa009
+ 0xc843783f 0xba96a153 0x3d80b2bb 0xbf5398c3
+ 0xb66ed306 0xd48fdf1d 0x39040227 0x1f1980fb
+ 0x51e740a3 0x6603060c 0x9ce34405 0x9abc2a4b
+ 0x7ece5908 0x457998a7 0x45443d10 0x20f2a0d1
+ 0x9cac676e 0xb8e66c6f 0x4cbaa744 0xecdc6c5f
+ 0x5be9ad3e 0x1a7af08b 0x94375052 0x9547a526
+ 0x3f3d7a29 0xfa571d4f 0x00324a11 0x003ed568
+ 0x92224138 0x0bc6fa9c 0xd4dcb738 0x81932d66
+ 0x27525a40 0xee39a4b5 0x4ad66faa 0x59c5ca88
+ 0x578921a5 0xb493d0f3 0x005d131f 0x49bf227b
+ 0xa8ea547d 0x2e5c9a48 0x16afbca7 0x34e8a7d1
+ 0x5aea0b5b 0x82c3e281 0xc537c374 0xefe8922e
+ 0x4ed6aa04 0xc957d8d8 0x54887681 0x61da5bff
+ 0x7d116291 0xf2046fc6 0xb71da398 0xf9ddcc7f
+ 0x7a884d46 0xf0bdbbe2 0x5fd74815 0xf86cf766
+ 0xf588e4ba 0x88d910f0 0xa246d4b2 0x5b2e87cf
+ 0xef07a06c 0xefbb295a 0x6be0b60b 0xa0684b8d
+ 0x2e4ba4a7 0x32aea4e6 0xde8df602 0x9754eee3
+ 0xb79c1df3 0x92819bcf 0x6e2212c1 0xff2ec504
+ 0x970e83e3 0xe44c1588 0x25ef7a1d 0x78439e8a
+ 0x49befb02 0x30dcc732 0x2abf9573 0x8fb2d451
+ 0xb708f582 0xba802a07 0x5a4b4d7c 0xac3d8fc6
+ 0xda0c8cdd 0x616ed6ef 0x371d43ac 0xd7e81188
+ 0x197b6cce 0x598b7855 0x81091bc4 0x73115e41
+ 0xaff509b5 0x62ec8b9c 0x070f53f9 0x65e9acfa
+ 0x46b936b1 0x5a97edab 0xbd9093c3 0x7e56e0be
+ 0xceb08216 0x523f649c 0x73565919 0xd5a478da
+ 0x5e49884e 0xeed780b7 0x670f342d 0xcbec0af2
+ 0x60193aa2 0xb9b836f5 0x88142d75 0xb6ef20ec
+ 0x45ecc95a 0x86fa7d20 0xbed3332b 0xd72235ef
+ 0xf3dc1ee6 0xdee60153 0x17c288ee 0x1598ee3a
+ 0xad8be82b 0xbed18162 0xe741e3ff 0x7b2ceebf
+ 0x0c023ffd 0x228d9357 0x2519b917 0xb21337c5
+ 0xf7ef1ec9 0x1e38a02c 0x2aaca8aa 0x91ad2397
+ 0x39b94e45 0x9c16a80a 0xab4f0207 0x9fdd96e8
+ 0x4c7e82b0 0xe58e52dd 0xb35c5152 0xf72c7988
+ 0xe15b2b53 0x37b3ca5a 0x382cf820 0xe9a5b10d
+ 0xfdac3128 0xd613d631 0x0bfa05b4 0x8ed858c9
+ 0x48fa9bf3 0x6b0a24b3 0xaea3ded7 0xfe944124
+ 0xbfa01ac8 0x90c4b032 0xd506ef49 0xf3c2a52f
+ 0x1e717e29 0x9d032123 0x4eff6847 0x87fe7932
+ 0xf91e0251 0x7291c0e9 0x04c8865e 0xe26812d8
+ 0xd7af6deb 0xab8b239f 0x0d357507 0xc3f23049
+ 0x0fcefb47 0x7c1ebbbc 0xda0ff8d8 0xa2e91757
+ 0x2cdd7611 0x51b85a13 0x1a658155 0x97ba5866
+ 0x7b02d127 0x9a65f8dd 0xcea44087 0x3c44fedf
+ 0x6cba4b83 0xb30c9c48 0x5f33e368 0x46309d1b
+ 0x5e97e1a1 0xd4dfca3c 0x03762329 0xf499e182
+ 0xa8b3de50 0xd6a940c5 0x420b4200 0xebfae5a8
+ 0xfff42408 0xd034dab6 0x0fbfc9f8 0x618c48aa
+ 0x3258a668 0x040eb946 0xa3e0adf7 0xc5374611
+ 0x640a6581 0x57444570 0x4249f689 0x44f6314b
+ 0x7461455b 0x13066c2d 0x0d3d29c8 0x58e15f8a
+ 0x454ef231 0x9185d050 0xe99a20a0 0x7a06d75e
+ 0xd7449ae9 0x93e6bbd3 0x872176d4 0x333d8cd5
+ 0xcb511dda 0x3c1ccbee 0xe36c2ec0 0xe9344c87
+ 0xf54d7abf 0x531dfea3 0x7272fa0c 0x4c3dc858
+ 0x3d13b763 0xb2996ab8 0xa0a21103 0x95e9b6c8
+ 0x240dd708 0x92e0ca36 0x3945b765 0x436cc495
+ 0x333ef58c 0x463a6f85 0x793e9df9 0x9fe86bdb
+ 0xfbf0cbd5 0xdac52990 0x4c3afe5b 0x267ad809
+ 0x662c4ebd 0x6b4ac1be 0x89e7bcc0 0xfe4a7721
+ 0x48b4de81 0x4c81164c 0x1131ab47 0xc661f7e9
+ 0xe1d1bb65 0x7b57048d 0xdc99c55e 0x215a3641
+ 0xafd86760 0x1b2d56d1 0xe76d8f74 0x559c649f
+ 0x97219fc9 0xd5333043 0xf846c8fa 0x8cb63ba0
+ 0x1b320870 0x884e95cc 0x1655b161 0x4ee1ffd1
+ 0x376ce49d 0x028cc7f3 0xcc13e8db 0x9712f287
+ 0x753196b9 0x4227cf42 0xa5c3c359 0x37b5733f
+ 0x8e2920b7 0xe0e6198e 0xc9cc7de5 0x8b8d8fb0
+ 0x93807f0e 0xc476c872 0xda4d5c5a 0x4ead8398
+ 0xe5da2718 0x253611b6 0x54273437 0x435528ed
+ 0x37fe8557 0x3f31ac9c 0x4ce87c33 0x83f19d78
+ 0x5b7974d6 0xe62a980d 0x0d35445f 0x6823eeff
+ 0xfb23d49c 0xac42eaef 0x7cf3f7db 0x4703e364
+ 0x2fbad2c7 0x6ad6c9ca 0xdeac6634 0x9aa4e069
+ 0x16375fed 0x5a37affa 0x3ab2c7f4 0x576377ba
+ 0x9ca8949d 0x9eab830a 0x2eac9f46 0x20140d74
+ 0x49e169a4 0x29c8228b 0xb10c113b 0x97486ddf
+ 0xb268ccbd 0xee145285 0xf6db444e 0x2971a507
+ 0xe20506c1 0xaed3b844 0xa7d3a71f 0x0ec8a80f
+ 0x3964b61e 0x664c06c3 0x8aa6f07d 0x190bd9a4
+ 0xa713711e 0xc149601a 0x0e33b930 0x92d924b0
+ 0x3a3e6055 0x891417db 0x9da57235 0x7a5c95cd
+ 0xb220a13a 0x61486a53 0x84e823ae 0x3a525213
+ 0x8f83fed2 0x97a20f72 0x01d40e7a 0x51a8696f
+ 0xf78ee740 0xcbe3f17d 0xa03fec72 0xa3c10477
+ 0xeee0cc71 0xa4275070 0x71a4858a 0x3e6c10c5
+ 0x157f1c48 0xe761a235 0x7ebd0044 0x0587573a
+ 0x504bace1 0x18b0e30c 0x87da65c8 0xb09e218f
+ 0x394ddcbc 0x30850b35 0x870144df 0x308786b3
+ 0x3b5e72c7 0xae824b41 0x08dcbadd 0x4205606c
+ 0x0dba1b98 0xea8b026a 0x0ff80267 0x4d345dde
+ 0x3e9fe94b 0x2e5150ee 0xe690ebe4 0x7e15f05b
+ 0x6fd516be 0x113d1f78 0x8e460364 0x0a18c989
+ 0xc858ba5e 0x65229038 0x7103dd07 0x9cd5dfd4
+ 0x1d90fe4b 0xe020ff30 0xcd525bd1 0x9b44f15e
+ 0x535137e9 0x06e76f27 0x7fef31ba 0xaf21d659
+ 0x9f96533b 0xee3b980f 0xf88f1efa 0x47e69092
+ 0x7384ba38 0x76c06863 0xcdea308a 0xf05dfad0
+ 0x954345cd 0xa0c58d59 0x82cdc2ff 0x5501bae6
+ 0x1ca051d2 0xb992dc65 0x98d2f849 0x759e5af7
+ 0x3f6ba599 0xbd2b801a 0xf24cf7e1 0x523f4bc9
+ 0x280bbd9f 0xaa28b183 0x8b41afce 0xa4ffac7c
+ 0xd7555ff9 0x15e6d70a 0xf7d9ecf0 0xf647181e
+ 0xcae10548 0x7bf3059a 0x5f53e585 0xf168d5de
+ 0x78041850 0x3f3c1c0f 0xbb820ed8 0xe84de7fd
+ 0xe0f8e79c 0x06b59d3c 0x42cde450 0x40068ecd
+ 0x239241fd 0xef3e69fc 0xe54ca169 0x026d86ef
+ 0x790f5960 0xeaac92da 0xdb1ea331 0x34b1795c
+ 0x975382e6 0x383576d4 0x9846ba3e 0x7d666cfa
+ 0x63c9f2c0 0xcb0b0e51 0x15de13af 0x5b50543d
+ 0xf3088ada 0xb0a0eea1 0xa16789ae 0x023687e5
+ 0x3fe5a0a8 0x2d087c46 0x1a9f7dfa 0xc111594f
+ 0x22f0c9e5 0x23519d74 0x063af453 0x3dded0c4
+ 0x2fbec97e 0x94c3a2ed 0x712515d9 0x4e23c2bf
+ 0x47ffab6d 0xcc975cde 0xb2cba5ae 0x4f64f77d
+ 0x1170d2e3 0xc8ec9fcf 0x548eb6b2 0x28c636df
+ 0x7b85e66f 0xc3ae89e0 0xa769b4eb 0x3f7b60d3
+ 0x99ae9021 0x32951125 0x38d1f0f7 0x635b3981
+ 0x784cab8e 0xb9ac2ae0 0xd9c8e406 0x849e2f3e
+ 0xbd46e71f 0x31cc9145 0xcd817b28 0x5d234af9
+ 0x5682e8f0 0x6963b396 0xbf42c2b3 0xa6b17649
+ 0xb083630e 0xe2bbb3f9 0xe2812105 0x524c7c1a
+ 0x3587ab3a 0xe5a43843 0x9013db3e 0x1c7202b0
+ 0x059b7c45 0xa79ad1f8 0x578dcda8 0x286f7a7d
+ 0x29b82899 0x17e9a470 0x292e9656 0x4ffecb5d
+ 0xdf7d989c 0x33d2f0f6 0x1ad9a38f 0x7192ebcb
+ 0x63c0924c 0x87adf98d 0x003433bf 0x1f9dbd42
+ 0x38811388 0x032c6dbd 0x7216bfaa 0xb8405caa
+ 0x358ef886 0x0d8de625 0xda26a3cd 0x02e02bed
+ 0xbfee97ad 0x9bd94b51 0xa3e0d47d 0x07afc5ce
+ 0xf1846ab8 0x9c56da77 0xdaf48909 0x980d0cf4
+ 0x201ff73a 0xecd7d225 0x2f8b88f5 0x6afda416
+ 0x1c230e24 0x6e71c111 0xd056e64e 0x8b02a960
+ 0x7b3e5cee 0x9369c16f 0x8cc648d2 0x5b1044a3
+ 0xec7ad383 0xafdc087e 0xb7331119 0xe2b73df2
+ 0xe5aa2679 0xb68a0024 0xbf417687 0x39f8f49c
+ 0x4dc6f396 0x394c364b 0x84b262e6 0xfd08738b
+ 0xef799352 0x99f6ce19 0xf0deea77 0xff7b2b32
+ 0x9f0047ec 0x93328447 0xa68daaeb 0xa15c49d9
+ 0x9c2ee179 0xd880098c 0x591333e1 0xf95bbf1a
+ 0x99b94163 0x6775a129 0x58312bae 0xb05a0204
+ 0xb369ee9d 0xe33139c8 0x228ddb00 0xa90eb06e
+ 0x9d740ac2 0x7fe877d0 0x49e80e67 0xae0a1b4c
+ 0xe0762721 0xa8aa010c 0xe1b1c70e 0xc4cb1331
+ 0x98e2a2b1 0x95eb5adb 0x27ce7e8d 0x0c4c9fb0
+ 0xa5600d3e 0x0b1b01f7 0xf5d073ff 0x618c31f9
+ 0x09ca0170 0x6f40bf4a 0x778c6e4c 0x82a5d345
+ 0x89739b55 0x9a8055b3 0x882713f8 0x6127132b
+ 0x7dcd4b1d 0x693bcd45 0xd37be4c7 0x5cfcc650
+ 0x108ba25c 0xe514be8d 0x0e6acbe4 0x53164bbe
+ 0x04f80fc7 0x3d62e170 0xdc0977c1 0xe4e696a2
+ 0x2951e0ab 0xe7df7bb8 0xed0452f0 0xa052451e
+ 0xef71dffa 0xe7e1a83b 0xf44f3edb 0xdc8909d6
+ 0xd106ca58 0x65a50c30 0x629bbd64 0x8aa53b1c
+ 0x281d476d 0x9d8ebab9 0x7618cdd0 0x8726df1d
+ 0x873d200d 0x3f0dfd8a 0xac699c41 0x6c5fd299
+ 0x1a4ec8da 0x02849d77 0xfb9a17b8 0x97353330
+ 0xf58f4ca3 0x8cfd3379 0x560c085f 0x0b0f4412
+ 0x93abd1f6 0xa4610fe6 0xb2093ea3 0x2132e754
+ 0xa27f6dab 0x1dfdea78 0xa453f3fe 0x84952158
+ 0x40cc656e 0x6bc83102 0xbc64b5d9 0xebd58830
+ 0xae5d5041 0xcb2518e4 0xfbecfd7d 0xd35df3d3
+ 0xb1f3c02f 0x672b45c8 0xf1ec9063 0x7e1af731
+ 0x9591a4e5 0x8f6cba68 0x47961590 0x46ab9cdc
+ 0xafcc329f 0x89527de5 0x848b9e15 0x12a76f30
+ 0x8dd22cb2 0x111febb4 0x9f2b87bc 0x4d1124d0
+ 0x82885b16 0x9800ccac 0x8ab228d2 0x4edb46a8
+ 0xe3a7867d 0x6a0f0f31 0x0ba359e5 0x238c560d
+ 0x6f2e9960 0x714940fe 0x2c8b115c 0xb367636a
+ 0x5ef73955 0x1fbd0ed4 0xea769618 0x22879b8e
+ 0x19c54520 0x1d60b769 0x8f9c9206 0xe12e6178
+ 0x6f7d4e60 0x87a42234 0xbf426187 0x136d1b3b
+ 0x096388ec 0x12cf7c8d 0x4f9dc462 0xc4132bc1
+ 0xbb83ec7e 0x8a26142e 0xb2b10d85 0x0a22ac57
+ 0x587d0f8c 0xfc6566a1 0xf9a313a3 0xdf5b8e38
+ 0x3ba410d0 0xcaedcf98 0x623da0d4 0x48a77151
+ 0x9fbc8986 0x75d69451 0xdd8db5ca 0x3d143e41
+ 0x23c6ef92 0xd4e8c17f 0x50fcf1cd 0x65202d54
+ 0x7f465e5a 0xfc9487e9 0x21302b5e 0x22cf616c
+ 0x09b9278a 0x24807c5a 0x5347363a 0xa0d43079
+ 0x243222c2 0xf31afc3c 0x299615c7 0xbc9862a7
+ 0xd9fa9ffc 0xe0da4c33 0x4086d085 0xcd9fef47
+ 0xaca1ebf8 0xe9054295 0x0202a632 0x2a566a47
+ 0xde6072e0 0x12ab6f47 0x1e961f96 0x79b78cea
+ 0x178d0054 0x3a6db40d 0x1c1fa4a7 0x04aeca16
+ 0xacfc3b3d 0xa95d26ef 0x7fc56d9b 0x8cd04862
+ 0xf05ca31a 0x2f1a8451 0x1fa55f63 0x038c689c
+ 0xd275082d 0x6ce3bbb4 0xa5787d5c 0x284ad4fd
+ 0xdb456159 0x72fc2b88 0x4e8846f8 0x3652ccd5
+ 0xdb67b32f 0xea7afaf8 0x31981989 0x7479b85d
+ 0x8cd4965a 0xab410e17 0x3b6000fe 0xefe70084
+ 0x4d903c3f 0xad10aa48 0xdf7d8f3f 0x06eb3088
+ 0xf80c6c8c 0x1f45157e 0xc81017fd 0xfa4b5d19
+ 0x183d9f3d 0xa6552ca8 0x940914f7 0x0dece704
+ 0x5183a544 0x2ca83fd1 0x0d39644e 0x689020e9
+ 0x8fc6451b 0x6fd1271b 0xaa27e129 0x7c96848b
+ 0x51efc70f 0x8fc41606 0xf5d42b17 0x80694280
+ 0x1f774b0c 0xaad194cd 0xcdcb3bbd 0xa30226c9
+ 0xe94699f7 0xe7e0ad1f 0x4e0e7887 0x4a8eef8a
+ 0xd7b8d9b5 0xad81550e 0xd8a47d80 0x3b31cc2a
+ 0x283b170a 0x954184bb 0xcb4d6ef4 0xc53a8ef4
+ 0x1b9eba45 0x0df70c46 0x9ca62404 0x1960596c
+ 0xe447c659 0xbbdf89a3 0x11d5399c 0xf70d6c7e
+ 0x2f5f411b 0x55d83f23 0x49d3a5ee 0xa30d42ce
+ 0x9d7b5dab 0x798ac7a0 0x54427d51 0xb93539d9
+ 0xeab10ab0 0x9baeca42 0x5db291e4 0x6a572088
+ 0x1996c3b5 0xc49e4528 0xe5d91c6d 0xace9b18a
+ 0xdc00ef96 0xabb2be9e 0x9c8c3dce 0x5575fef9
+ 0x55ee1588 0x54fd1f04 0xb51f8054 0xa79f2970
+ 0x2b944de3 0x258bb2a9 0x6d795400 0xd8e37086
+ 0xe28e13f8 0xac866668 0xee61e623 0x74822294
+ 0xb8e40564 0xed674c7a 0x41649345 0x18f67675
+ 0xccf6dae5 0x2f771905 0x41617a0d 0x89892452
+ 0xebe9c54e 0x15c0047a 0x1360fe11 0x97e9968e
+ 0x969ba1ec 0xa8d87a94 0x89c42871 0xa3b7600b
+ 0x1eb2da3a 0x51ad206b 0x0ffa1e92 0x6b54cc4b
+ 0x551038b9 0x56d3134a 0xc604c359 0x921df194
+ 0xdd0e8901 0x0aa069b2 0x63cdd252 0x7f0eb051
+ 0x6eb669a5 0x9e4744aa 0xbbdb786a 0xade2eff8
+ 0x01735f2f 0x59b21311 0x2a9b3c19 0xfef63adc
+ 0x7f935ed5 0x4107ae2c 0x7e87a339 0x169cff65
+ 0x9c405742 0x714007c1 0xb7c3a785 0xc4c48389
+ 0x31f92159 0x0dc32968 0x52ffa3ea 0x97148ffe
+ 0x24e05234 0xaa26f639 0xfcc1d939 0x88657f96
+ 0x8f50c4f9 0xf1889d95 0x0ced35a1 0x436cecef
+ 0xeca9a15f 0xf48e7adf 0x457a7fcc 0x7a6c1239
+ 0x5034af95 0xa718db0d 0x148c7f75 0xe71321af
+ 0x6ca91aec 0xd8e3f28e 0xf1792028 0x6cd6de0b
+ 0x08a5b4f8 0x6c423f4a 0xabc9fd13 0xd9b32cb5
+ 0xa11cf2e9 0x1cf2a8d1 0x5399808b 0x41c4342f
+ 0xfc8cc322 0x886c8a1f 0xda930d22 0xcb065a7d
+ 0xac2af243 0xde40d5c4 0xbfc31749 0x1648efb2
+ 0xd7a7c284 0x66354919 0x0ae2ebfc 0xe9467716
+ 0x31bc8fa5 0xee8b06a8 0xd225ddf4 0x1abb30a5
+ 0xbab806d6 0x4089c5c5 0xda27fce1 0x049b6de3
+ 0xc750ba15 0x8a46ce66 0x036144aa 0xfe034871
+ 0x1abebc7b 0x493f7de8 0xb2159be7 0x6fa331cb
+ 0xb96cabc6 0x38c0604e 0xfc029108 0x5e60b9d0
+ 0x4659e613 0x03acd4cc 0x199fdfec 0x378d55eb
+ 0x769412a0 0x15e6347b 0x92c90797 0xc9074949
+ 0xf8122bd8 0xf412bc92 0xb78b97da 0x0b57c329
+ 0xe53305ea 0x8df0ab76 0x8306e3dd 0xd0d7318f
+ 0x36adcee8 0x874d40a3 0x01013be2 0x22ea83d6
+ 0x103a41eb 0xb0597649 0x3da90abb 0xe329568a
+ 0x197f2854 0x0bcf6548 0x9a8cadf8 0xdbcad384
+ 0xdbd146a4 0x47614216 0x20ae929d 0x700c45dc
+ 0x2957fadb 0x2ccecc42 0x59dade3a 0xbd4ba21d
+ 0xa54cbdfe 0x2168aeac 0xf3fc977e 0xb8a43acb
+ 0xb673e386 0x8374b99e 0x1c9b8514 0xb27755b5
+ 0x76a14bad 0x7f9e80f7 0x7827aad7 0xa38aace7
+ 0x09bfb029 0xd8744c16 0x60e27d36 0xf0bb9c68
+ 0x6c6ea1ba 0x1920dde0 0xfd949296 0xbdd246ba
+ 0x71b9255b 0x443eb00a 0x484b5641 0x6cf54003
+ 0x719a7b75 0x5fd6ceee 0x94379976 0x610d0ec5
+ 0x2e601eb8 0xd5b31116 0x351833bd 0x71e20a77
+ 0x1bdf31dd 0xf2b71f50 0x643e7b0f 0x14966e60
+ 0x2ea94458 0x18fd7a19 0xc2042ba8 0xa6b2a8a7
+ 0x5591ab4d 0xd62a7fb3 0x478b9fc9 0xfb0faa9c
+ 0x840848c4 0x51d8e887 0x0982b486 0xf5a7a82d
+ 0x651cd99f 0xc429c680 0xfae0f0a4 0x341f4588
+ 0x358b09c5 0xeab81b53 0x4107619a 0xfd8686a0
+ 0x23438c74 0x03e44685 0x7acd2f1e 0x0324c896
+ 0x0c4fb764 0xa859e8ce 0xc041d07b 0x1ddea0d0
+ 0x0c7d3a05 0x1a9552b9 0x791ac20b 0x135c3573
+ 0x3315a1b0 0x20f6b0ba 0x9301b576 0x5f9396fc
+ 0xd2b55a44 0x1ccf9ebd 0x8cf0350d 0xa58f9151
+ 0x251be7f3 0xce2201a3 0xdf354713 0xe1c1bb1b
+ 0x6821a792 0x8b1a47e4 0x681b765a 0x6b857d78
+ 0x4b453e66 0xecbeea8f 0x7d4aa02f 0x138ad3ce
+ 0xa2e27fdb 0x9f47ceb9 0xdb849664 0xd89748fd
+ 0x3245bf9d 0x16bdbedc 0x386f037d 0x9cc949f5
+ 0xbeda4924 0x357c0a52 0x9f6e807c 0x547bd479
+ 0x51495240 0xd1883e61 0x04869ce6 0x47f09ac8
+ 0x2e5cf223 0xc34ef901 0x15b69b18 0x052b45c3
+ 0xa045628f 0x7fdf706f 0xaa943b26 0x52a91e2a
+ 0xed73757f 0x6ddb9171 0xae2e6289 0xed44ad05
+ 0xd9ba87ac 0x5225b7f3 0xd227abe1 0xf95c862c
+ 0xf22fb4e4 0x34376d96 0x121f979b 0xb65b7535
+ 0x3bca35ab 0x579ef994 0x72659829 0xc0094673
+ 0xdea78eef 0x51248fb0 0x4a883536 0x9c69810c
+ 0x6f9e2a2d 0x33a54fa3 0xbf04ea97 0x081092e0
+ 0xe783b995 0x47f781c4 0xfe77defd 0xd0b42d36
+ 0xbe387b86 0xe3072ad9 0xa3b6908f 0xe2141964
+ 0x77d70045 0xa86ad40a 0xc3c457c5 0x3e7b7126
+ 0xbef763ea 0x0d6fc62d 0x5915bf32 0x2aff83b7
+ 0x21cb6fed 0x52903bf0 0xe020e340 0x0b3f355c
+ 0xee7c6bc1 0x060fb2a8 0xc0323dfd 0xe1dcfb29
+ 0x668647ce 0x3e46e584 0xae4baffa 0x6a77a8f6
+ 0x20d34fcb 0xd9ec900e 0x778a2afc 0x1a59fb8f
+ 0x43e94780 0xd4e333ad 0x97f82259 0x141571cd
+ 0x73aa7c5c 0x18fcf18a 0xd48a4fb8 0xc109eac0
+ 0xe8de4f47 0xfd509a7b 0x90707861 0xfb8c77cd
+ 0x3b7122fc 0x4ca78b8c 0xa35f59d0 0x45ae991c
+ 0x8e70498c 0xb9202519 0x65c96b4b 0x78a4fc95
+ 0xdcf1b9a5 0x1031417a 0x9ff8793e 0xa2030f94
+ 0x8c733cfc 0x1c91d955 0xf6a68ffb 0xedd6944b
+ 0x2aa354d3 0x6ac7af45 0xf1f3cd2a 0x4c62c093
+ 0x03480c9b 0x0f246eb1 0x2a4b1c9f 0x839b624c
+ 0x29a74da9 0x34ae761d 0xaffd7053 0x136c170c
+ 0x62d45905 0x6707d6b3 0x7c828933 0xc8df0f9a
+ 0x16917824 0xa446ec27 0xc0ebdeb3 0x78183042
+ 0xf55d10b0 0x7ac4cae7 0x1e03a86d 0x5b0469f6
+ 0xaaa1c0d0 0xe1ec5485 0xbd92cc52 0xe57b7def
+ 0x371cdae6 0x5a344a02 0x4fe6202d 0x550f73f7
+ 0x0379ceb7 0xd8136303 0xdc4359cb 0xe38ee67a
+ 0x2aa895da 0xe6cd6cdc 0xa50300f1 0xdaecc9bf
+ 0xde559d55 0xec988d8d 0x2daf3e0b 0xcae251fb
+ 0xd26d26e9 0x130ce5fe 0x86d2361c 0x3108822b
+ 0x842528a2 0x23b91b1b 0x48fb92e7 0x013305da
+ 0xb9382453 0x8e338247 0x1cee69df 0x28dda889
+ 0x3098b87d 0x2fb8a4f2 0x12cbca62 0x0050c443
+ 0xa9640f44 0x56926695 0x84f1af0f 0xe7612db4
+ 0x7ca148a4 0xde5a4740 0x04fc09c8 0x1168eacd
+ 0x3afcb851 0x481d093a 0xdab01eb3 0xad7d6f56
+ 0x0311d8e9 0x4094dbf9 0x264b6da5 0x3a5fdc11
+ 0xcd2ee17f 0x50cfbfc2 0xfdc9419f 0xa61d64be
+ 0xd9786507 0x4202f8e9 0x13f58fd8 0xae675835
+ 0xaf0c72ea 0xadd2275e 0xa0afc1b2 0xaef42673
+ 0x059895be 0x4504a91c 0x0d1abd4c 0x7986dcc6
+ 0xc13fe6f8 0x4780bfd7 0x44ae446b 0xb70c300a
+ 0xba32a5dc 0x807aa794 0x45e8373b 0x955cb2f6
+ 0x4ff6ce64 0xa75d9feb 0xf99b0f94 0x1f6f42cf
+ 0x7f3e7082 0xf05cfbc2 0x2981d66a 0x0031868d
+ 0x93ad9527 0x20e0a72c 0x7af059e2 0xb4db736f
+ 0xc1ee8a47 0xee31b1f2 0x075c758b 0xb796cef8
+ 0xe758683a 0xa417d0b8 0xec701109 0xd5db6f14
+ 0xee6759ba 0x965fd314 0xa991abc2 0xe431e1a0
+ 0x8c49bd5d 0x393827a6 0xa432862f 0xc41e1a96
+ 0xbe0bc3b9 0x3d8cf302 0x42bc70da 0x8748df76
+ 0x110951c0 0xb1685274 0x06f426f6 0x65ec87c5
+ 0xaf689ca5 0x602d9679 0x19363407 0xb0fd04c7
+ 0xa38ad24a 0xfad9b36b 0xa13c711c 0x4e386365
+ 0xa4f8a466 0x55276e7b 0x7e8f736d 0x6fb49d16
+ 0x319c5c11 0xaf40ba4c 0xe7f84dd4 0xef4dd864
+ 0x5ae207ae 0x09a3ef70 0x23a90e6b 0x9c9697f8
+ 0x7155d79b 0x131fc9fb 0xb46cb500 0xeae3eb61
+ 0x51e29783 0x3922bd46 0xdb8afa10 0x33b0ebfc
+ 0x3e43da19 0x2fc38e51 0x97f3bf1c 0x8c3ce68b
+ 0x7c0550be 0x6a53e9f6 0xbf6cf7c6 0xf338ad58
+ 0xce0f1a73 0x4d372ec0 0x29281dbd 0xf6b0bd7c
+ 0x85b26827 0xa454dfb2 0x52b28dab 0xdf3af48a
+ 0x5f533d2f 0x2a609d20 0xeaf73bed 0x5e350bb2
+ 0x95d2bd12 0x908c3f5d 0x71511f88 0xd2060f72
+ 0xa818d161 0x84f5ebee 0x59ed524e 0x4e45cb9d
+ 0x6ce00f42 0x33e0c310 0x75e34119 0x140e3cc3
+ 0xacbeda6e 0x4c450e0c 0x9ae2ef44 0x7c98afc7
+ 0xa2093bf5 0xeab6cf15 0xcba6057e 0xf04c3ce8
+ 0xcb5cf30e 0x044ff594 0xc2cdb5f4 0xc8c60b17
+ 0x701c8bbd 0xbf893762 0x2ac72a28 0xe777c968
+ 0xcd25da52 0x747eeb7b 0x76ee7f3f 0xffa7dcdb
+ 0x69e68c12 0xeec17e1d 0x93710ea9 0x5370892c
+ 0x24463499 0xfa5ec00b 0x3b1f55cb 0xa6fec9d7
+ 0x4fa50806 0x7f8066fb 0xf914e3dc 0x1f814780
+ 0xedbff426 0xfec2a635 0x5355f69a 0xf4f47000
+ 0x0be99ed6 0x6ca79305 0xb5744697 0xf50a8edf
+ 0x91fc0932 0xb3ff4411 0x4d72ecd7 0x335f8ba6
+ 0x1b393143 0xf0cdce19 0x95543420 0x88d44565
+ 0xf47e1e74 0xd7ceb70c 0x95508187 0xfc65e9f3
+ 0x92cdfb27 0xa12af6a8 0xb8754dba 0x436f5819
+ 0x0e3a952e 0x91178a2c 0xa25c2395 0x15379544
+ 0xaeffd675 0xb74779b5 0xd9229b70 0x7c72bd05
+ 0x0349e5c9 0x3f2dd364 0x96e25f24 0x5c0fca2c
+ 0xe56f81ea 0xee339b9b 0xb6f9888c 0x54ea5d03
+ 0xfd136dc5 0x78ebd8a6 0x7d65dc8f 0x1f79781a
+ 0x7f058e70 0x68caae5b 0x9e17a15c 0x0b0d7b34
+ 0xec758cfd 0x2d2d39ee 0x72b46a64 0x98569c65
+ 0xcff678a2 0x1e5eae00 0x197cff21 0xa17e1c00
+ 0xf0da9430 0xa007a848 0x0be7cd80 0xc55a8077
+ 0xbe7ed983 0x5c6626cb 0x103c6639 0xc0348431
+ 0x48a06b34 0xd8c43a93 0x94f5dc15 0xd8282ff4
+ 0x798fecbb 0x969eb56f 0x97b834f3 0x9361d4b4
+ 0x451962dc 0x9411aa6e 0xa9eb502b 0x2fa0696a
+ 0xcfce109a 0xbdbb187f 0x0cef3b86 0x7d420c93
+ 0x6a38b476 0xdc49d8b8 0x34652cef 0x1d38f2c7
+ 0x9042655d 0xfa414d42 0x79553a30 0xa1197a11
+ 0x47f0892a 0x7c7cc3cd 0x0d16e724 0x205ee0e0
+ 0xe8d2af7a 0x1b84e9e5 0x762b8343 0xe6f0d4f1
+ 0x13c47e29 0xd625bdc8 0x16136974 0x7f4e63ad
+ 0x5fb6589b 0x53699412 0x136774ad 0x4469f334
+ 0xe0e90aac 0x88a24073 0x940ce7e0 0xcef6082a
+ 0xaf7251bf 0x569dfc49 0x23058c3f 0xa2c897ce
+ 0x6a31faae 0x352ad804 0x88cc7d68 0x68570267
+ 0x07314cae 0x8cc2a6bc 0x3dabbd9f 0xdee27981
+ 0x32c1ffa8 0x826ab175 0x769de94a 0x3b11317f
+ 0x362a6306 0x2422aca0 0xfc53764d 0x2ca4c418
+ 0x5fc2d68a 0xa74a5fc5 0x949b041a 0x0f0f69d6
+ 0xd075fac4 0x965a3001 0xb6dd4eb5 0x9b5c6979
+ 0xfd84a8bf 0x4ca80a7d 0x42fb907f 0x5770680c
+ 0x3684714f 0xba50c3b2 0x0fed8f5b 0x42f42f2d
+ 0x7e98ba74 0xcf4ad155 0x33972750 0xabbbbbe0
+ 0xcab7ba1e 0xc3e54c90 0x2cf8e77c 0x7eb3c185
+ 0xafbe0fc0 0x6ff94321 0x9699d3a8 0xa8f51d2e
+ 0xaeba0be5 0xc519f879 0x73b89b8d 0x2c98994c
+ 0x5c6688ed 0x0c4edf1e 0xd27a0c40 0xe58b6112
+ 0x8b01ccb4 0x7da8a608 0x03b02b0a 0xc35c0051
+ 0x33f60875 0xa215809b 0x34e2e84e 0xb1249172
+ 0x9c9068f0 0xa4067a92 0xd6260de5 0x2e30b0b8
+ 0x895a3ef4 0x1d0df2a1 0xf5fc1a24 0x51fea72e
+ 0xa6b203f2 0x13b8ccbe 0xc411482e 0x40529a43
+ 0x8ec685c6 0x31334940 0x3758077e 0xc551b5d5
+ 0xeed75a95 0x1bbcd839 0x64b09366 0x426afc28
+ 0x70826210 0x2cfdb0b7 0x2e1d1442 0x39db3d97
+ 0x3826c5a0 0x500157d0 0xd6dacf6f 0x9b9dbe3e
+ 0xab4c2657 0x98c19ffa 0xd12dcb10 0x73d3b9ba
+ 0x0c15214c 0x737e36b0 0xb903b782 0xb7ac4e8c
+ 0x0d0a3b55 0xcf534bc7 0x3268a6aa 0xdaf914d3
+ 0x33f832b1 0x280109cf 0x270be538 0xe6bbe826
+ 0x11c372ce 0x74a668fe 0x0065b4c9 0xffc007a3
+ 0xbcea5c8c 0xf95f792a 0x88b93d2a 0xa76a2eaf
+ 0xb6dbc1be 0x8aea9c60 0xaa7f4bcb 0xb48d40c9
+ 0x5aeba8d5 0x45797ea3 0x736e4060 0x40dc0826
+ 0xd497fb52 0xcdfb751e 0xebd6fdf6 0x3471bbd0
+ 0x6d5bb733 0x02b6cbb1 0xd086c9c4 0x0485863e
+ 0x878391a4 0x57e62c09 0x37385c15 0x96e76ac8
+ 0x093dbd37 0x1ffe70f9 0xe256fc68 0x3a509a68
+ 0x019d3e81 0x038168f1 0xe0b2b6b0 0xe6eee6e5
+ 0x2080b0d1 0xe25aaf0c 0xada6ac13 0xa3755f0e
+ 0x99f9efd7 0xb0cbe867 0x1dd5fe38 0x1bb8bd56
+ 0xb54dd0ee 0x344d878d 0xf937042f 0x9ac5c721
+ 0x1a60dc54 0x643b9a83 0xe66ce361 0x0d10d718
+ 0x31aa90fd 0xf71e52c2 0xdf7eda2e 0xdc068ad5
+ 0x095f114b 0xdb1a9b68 0x64ecb9d6 0x6f13609a
+ 0x9242152a 0x1a7059cd 0xaa4c92d3 0xbf9a70e0
+ 0x93936ec0 0xc8456867 0x05118674 0x0d6289af
+ 0xacc6aedb 0x3cd3aea0 0xb11acc65 0x93121235
+ 0xd080cb09 0x1a3e9be4 0x3772ad61 0x1277ce89
+ 0x503309b8 0x7cc1ada2 0x87e93e41 0x565bfd16
+ 0x8d64db91 0x8776da19 0x8068ea78 0x8c4ed3dc
+ 0xb9904266 0xafc63a7b 0x120c746b 0xaa5503ae
+ 0xf6c8c09a 0x7390cac4 0x736c1bdd 0x03ed0655
+ 0xa692aa13 0xa95b2587 0xeeb8140f 0x97c907b5
+ 0x6665d1e1 0x335794bc 0xc59a6232 0x0a6a7bfd
+ 0x0820e282 0xde4982d4 0x43ce576f 0xca9f43cd
+ 0x439467d8 0x513c59aa 0x40a47741 0x6c92f234
+ 0x712a918f 0x5222ad75 0x90097829 0xf82f3dc7
+ 0x5c95108a 0x9432a016 0x1c13d7fb 0x6a64358e
+ 0x88c43a59 0x726c4bab 0xbba1d26d 0x3a6fbec6
+ 0x603c6edb 0x5002f608 0x65b6e6f4 0x9911d725
+ 0x1e9d73f1 0xad3facb6 0x3074a331 0xff08050d
+ 0x84efd825 0x0ba49a61 0xef94c605 0x95e6fa34
+ 0x42102abe 0xbb7a7327 0x53fb9fe5 0xbf3e7e13
+ 0x35ed38b9 0x2af0b51b 0x59d53a64 0x77963248
+ 0xe3788d31 0xe193f2b3 0xeee24485 0x8688c4ee
+ 0x9c61fe6c 0x5745fc77 0x8fb588c0 0x9b8b73a9
+ 0xddf4a85c 0x37f97b96 0x37ef756d 0x75b88955
+ 0x4ddcf2ee 0x0ddbaaa6 0x53188169 0x9c17c6e1
+ 0x6d6f6640 0x97c72398 0xf2a555d2 0xbeba7505
+ 0x8a330e05 0xfd73bf33 0xa84d8356 0x928cd08f
+ 0x302f868b 0x4dc8aaa4 0x0eae2165 0x0151f140
+ 0x1b337b5b 0x168f2728 0x377c45df 0xd5a333cd
+ 0xf9cd451c 0x386cd928 0x5e45d283 0x7e224f31
+ 0xaebe5122 0x75c7e49b 0xe3949ce8 0x397bcadf
+ 0x4c0e0f77 0xba92d6b0 0x9288f86a 0xe9a47d7b
+ 0x344fc436 0x00a9a682 0xd15e8917 0x7dcae697
+ 0xa2955662 0x9465b695 0xec9f769a 0x740159d4
+ 0x738b71ab 0xfb57cfe9 0xfa582c08 0x7d5521d3
+ 0xe2644c13 0x4311f413 0x3c2751d0 0xc9faa58f
+ 0x36b94cf3 0xcf8cff31 0x5dbf8927 0x82f8c846
+ 0x8bd2ceb8 0x2a7368e9 0x9eff066f 0xd93f3e0c
+ 0x2358ff4c 0xa41ce1e6 0x41ea009a 0x04c7a7cb
+ 0xa2897e54 0xdb46c580 0xeca4c4df 0x0920694c
+ 0xde5d8ad0 0x23968b10 0xfda8d5ff 0x6bfaebb0
+ 0x596eb388 0x797dd1b5 0x18a1e5f7 0x8b58637d
+ 0xd618cddc 0xbfe51118 0x46ba28b1 0x94854536
+ 0x0fa51257 0x381f2d54 0x20d68fc0 0x540b8ea8
+ 0x5e81f3f8 0x55409d4c 0x03768f09 0xdf9ccc98
+ 0x012b6611 0x9a8ad678 0x340313b0 0x08fb187e
+ 0x3c208640 0xca62a71e 0x75e62236 0x303002e0
+ 0x71d8ce8a 0x15cd2434 0x519570a8 0x2ad715ff
+ 0x61f33c8b 0xdd1ec924 0xb1a4c788 0xf2c36eb4
+ 0x5aa4b007 0x75e7c1e5 0x29bc37f9 0xbc7bf320
+ 0xfce34584 0xbebf90d4 0x8a8be8a2 0x3ac72a9c
+ 0x0de840bd 0xda21156f 0x06a72c18 0x0c31c6a8
+ 0x8dbfb88b 0x2c030320 0x7b91cf76 0x4b698166
+ 0x11465c72 0x2dc1af9c 0xec43656d 0x07313b0f
+ 0x2347b8c1 0x3a66229e 0x3e19108b 0xe734c641
+ 0xc8ab5c8a 0x295e857e 0x80ccac9c 0x52fc246d
+ 0xe0d5729d 0xe788795d 0x862db49b 0x81de8327
+ 0x57a24391 0x46873200 0x1d6d9e62 0xb61cbde2
+ 0x40c67928 0x5983967b 0x249cf427 0xd944ba02
+ 0xf915cb96 0x7f07bdf5 0x01d35dc8 0xaed094e3
+ 0xfb177ba3 0x81f39bdc 0xab553569 0x09e791f2
+ 0x866c4561 0xe41ed6f8 0x880ded55 0x9a6f5b07
+ 0x5457168b 0x13b672a3 0xabba6ff2 0xbb92c573
+ 0xf46b5af4 0xb8690988 0x8b767492 0x53e2f7c0
+ 0xa6b8cd45 0xccc0f21b 0x2205c607 0x97f74f86
+ 0x4a671fe4 0x2078716f 0x2530825b 0x3b0db3a3
+ 0x3c86b75d 0x780e6f20 0xdf8af7d6 0x547710e3
+ 0x397470a9 0xb3f04101 0x206511ae 0x30ccf385
+ 0x1792e9bf 0x80ad156b 0x7325e8c7 0x88ba99a8
+ 0x6d0992ce 0x07e834c7 0x334e415f 0x2c246850
+ 0x8502dfaf 0xb1ef5b19 0x75ef61a9 0x98e3b45b
+ 0xcb9f0a6f 0x8c5f2ae0 0x16e43384 0x7ed0eec1
+ 0x940e8b42 0x03fcde5b 0xcadb2d4f 0x0a3d8362
+ 0x93038e69 0xef8c8384 0x065fcb40 0xdd57dc0e
+ 0xf0362942 0xb39c96ab 0x979ec3f8 0x0efb2396
+ 0x67a7c975 0xf8f272c9 0x52461862 0xea391db2
+ 0x11f15fb5 0x2435ce54 0x9c51b8f5 0x8c7b9119
+ 0x4b48b4fd 0x9864e85d 0x9840cd3d 0xa98f4da4
+ 0x9a7f03c5 0x89e50015 0x6c6d54b2 0x9e647aa2
+ 0xb3835823 0xea9bafb0 0xa6839d36 0xecf71292
+ 0x170f2b96 0x44b0ac85 0xaf475a0e 0xa892f2df
+ 0x7e92ff6e 0x7a55a76c 0x97a6edf8 0x1a8b561a
+ 0xba061934 0x2d4ba604 0x85ece0fe 0x0ab3a735
+ 0x26935212 0xe74ea97a 0x33ed586f 0xca8989f3
+ 0x4802c043 0xef153bc8 0x32c511aa 0x994c3044
+ 0xf3608e41 0x8b2ba3c1 0x27c40d2d 0x56ae54af
+ 0xb5df3e4f 0x7cf1679d 0xf76a120d 0x28af2bf0
+ 0xf87650fb 0x4ef69312 0x2a28acb1 0xe78d71d5
+ 0x8cb89388 0x7f25bce8 0x420545da 0xe654dc1f
+ 0xe6fd962f 0xf4f06310 0x9b5ccd44 0x60e3624f
+ 0x9f38c5d8 0xe5fcf792 0x839bee9c 0xb405347a
+ 0xc8cc045e 0x61506b9a 0x3a3682e4 0x22ca3ee4
+ 0x5aff86c7 0xb9091ac9 0x2f8c8afb 0xafb29af9
+ 0x1d4a3f19 0x9de74245 0x1a0ea238 0xc8bdc6cd
+ 0xf1107b01 0x1dc7552a 0xb46a8c4f 0xe716b42b
+ 0xfc060840 0x15fbc29d 0xc532c4e6 0xe96c8306
+ 0x9e69da96 0x7f68fcc7 0x67d18b52 0x77a87432
+ 0x280a6ee1 0x9a617bd9 0xd8d601b9 0xadc7f7f1
+ 0xe3349a28 0x8efa2d8a 0x37ca44b0 0x6499f67f
+ 0x5fc7b339 0x690852bd 0x27bd71fd 0x07159d82
+ 0x9c841ba9 0x40741162 0xd7df8ef1 0x3edecc5e
+ 0x12086a65 0xe8e6ee6a 0x1c177c39 0x1bee453c
+ 0x5cc0b73b 0xec84a212 0x174a641b 0x7fa732e8
+ 0xdafe94cf 0xa8eb95d6 0xb658346d 0xceee084f
+ 0x3ed35394 0xb339f90c 0xb9bc44b3 0x1dd76c34
+ 0xf9a54771 0x1482cbec 0x3816720a 0x3a1ebcc2
+ 0x15cd4a11 0x94bc6c92 0xcb4cbf26 0xa141f0a9
+ 0x11d8331a 0x82a73ed8 0x129d4088 0x3718c117
+ 0x9fb3a041 0x51686b91 0x6f735d1b 0xd9eaabc9
+ 0x623e6caa 0xbba10978 0x4811fea9 0x9e8a6779
+ 0x007ea597 0x02a71344 0x0bc9b390 0x7bca4fb3
+ 0xecc97d95 0x1c82c55a 0x746391ab 0xb0fab9a5
+ 0x54f66c88 0x21797043 0xcca5c581 0x4fdccf5a
+ 0xaabaefdf 0xd606be82 0xcc2b2d33 0x7fd7cb14
+ 0x1e3629ea 0xd8e76e94 0xa895dfbe 0x0c06919a
+ 0x4ea7aa08 0x3a178b90 0x4a56dfa3 0xb98a1f87
+ 0xaf5a9fdc 0x7591a3c7 0xd5b58c30 0xd4028625
+ 0x55d42179 0xccf397f9 0x824b38df 0x97292483
+ 0x09119e73 0x945cc1fe 0xf4b77171 0x753154e8
+ 0xcf0740db 0x3282b3a7 0xcc266194 0x7cdf91b3
+ 0xd123931c 0xcfbb7728 0xfe410560 0xc4cce81d
+ 0x3b843933 0x75734bca 0x3ea34af3 0xb9515793
+ 0xeb66b451 0x3a6a1135 0x633d086a 0x31e627e8
+ 0x3d12a160 0x9909d28f 0x6b98e9fa 0xf5e81dba
+ 0x8d233c7c 0xbfde17d4 0x5a442267 0x228a56d4
+ 0xfcf27d3a 0x3bef2fdd 0xd0c9c057 0x84c2dd26
+ 0xcb54e412 0x01f6d774 0x78d352bb 0x3403cb49
+ 0xe16e92b7 0x25fdeaa6 0xa90610a3 0xcb43c17e
+ 0x880f57cb 0x50908846 0x8255be3d 0xc01dbf9a
+ 0x4bb1a52c 0xafc5a8c0 0xa543d14c 0xd18efbe7
+ 0x5b18ff14 0x910913a7 0xb78f2a4f 0x2e9aff82
+ 0xf3604dc3 0x77b5dc87 0xcbd16de3 0x9e9aa767
+ 0x50c14c8d 0xa53a91f6 0xf5369c5f 0x693421e9
+ 0xe7d41706 0xde2ae3c0 0x3383fe8a 0xfff54f57
+ 0xb22e6bbf 0x330cc71d 0x0566d22d 0x63726b5b
+ 0x4af41cf9 0x1da8b9c3 0xd8c5fb71 0xcb4860f9
+ 0xbd301732 0xd0300319 0x51458c3d 0x2915617f
+ 0xa76713c0 0xaab3eb2a 0x35cdab1c 0xd1958253
+ 0xc42c14ed 0x9794c64c 0x3f4860d3 0x5be281bb
+ 0x7153eb66 0x0fbe8b50 0x3296f7f6 0x14ca3bc9
+ 0x5d3e1995 0x3f54a9a0 0x3a350e66 0xe0eaec63
+ 0xf6b40eda 0xb432a3e9 0x8eaf6fd3 0xa5e02a4a
+ 0x82181320 0x7b18018c 0xeba1bb24 0x192f05f9
+ 0x95aa2c21 0x2635f2f9 0x13a81ac3 0x57feb353
+ 0xfffbdfff 0x20c3f27c 0xfe1ccfb8 0x75e9bb2d
+ 0x2470564b 0x59e7905c 0x5ad8e400 0xf575caf4
+ 0x3c99a548 0x93ff04a9 0x494be39a 0x966d5c2c
+ 0xa0439df2 0xb42ecb84 0x5ca0e55a 0x72bb3b6d
+ 0x903f12cd 0x55b67ebf 0xaf4188f0 0xdb3828de
+ 0x0e8603f1 0x35a3b856 0x63402b22 0x21ab7779
+ 0x4efeaba2 0x919829f2 0x4190e5ed 0xbd99779b
+ 0xbc96cd73 0x6d5eda45 0x872b6659 0x7c30cb30
+ 0x1ad0c877 0xa88ef386 0x03bf7f3e 0xa6c18655
+ 0xe39e2764 0xa40da119 0x01f5eb9f 0x4b6790fd
+ 0xa50414de 0x4d7d8fcf 0x28e6bdfb 0x345dae6a
+ 0xe706b08e 0x7958d05d 0xf6ea912a 0xeebf2736
+ 0xc5ddbbc1 0xdf079dad 0x09ea5e1f 0xddea3b87
+ 0x367782fd 0x7e657215 0xbce3c13a 0xd998f10e
+ 0x22a6ed1b 0xbd57ee41 0x8bd6a4ff 0xbe81acf7
+ 0x186aa189 0xe986fbb4 0xb4b798e0 0xa313653b
+ 0xec674a01 0x656d8992 0x92104018 0x01eba2fd
+ 0x99314063 0x0bc67b96 0x98891022 0x32a936e5
+ 0xee8331f5 0xff55bf99 0x2e305833 0x6fea2320
+ 0x261d4ad4 0xb357a04e 0x6086539b 0x12b59123
+ 0x170e9c0b 0x2c509ff5 0x4684fa75 0x55535535
+ 0xc47f3dd0 0xf74a35a7 0x468e5623 0xdee52521
+ 0x55f86d53 0xc6c66d4a 0x0f127241 0xa89d946c
+ 0x2054df6a 0x7555153a 0x91cf4407 0x71d0e3de
+ 0x6dc16613 0x32a44245 0x8607574d 0x6eb010de
+ 0x02cb87ad 0x16ca5da4 0x79026a0b 0xb3c22ea4
+ 0x2aad720f 0xc59c6272 0x8b0ffcbc 0x90138b11
+ 0x94960289 0x018dc9f4 0x28795fe7 0xa9d97031
+ 0xdbabb687 0xa26c631a 0x22b60590 0x816e4981
+ 0xe881272b 0xc2d2a9f3 0x251dfcc7 0xef7d7cd4
+ 0xe92e8a70 0x5a41e9db 0xe4c0d1c5 0x559d1455
+ 0xe661afb6 0x87819510 0x880a078d 0xc82fdc06
+ 0xe27e27f1 0x9912132e 0xbee4b9de 0x04477b74
+ 0xb25684d8 0xeec01992 0xd3e81251 0xfa528234
+ 0x435b2dd7 0xe45673cb 0x9b4c9767 0xde5de093
+ 0xa2e591dd 0xe4e27f7a 0xe94c0e70 0x5c392194
+ 0xff2d4212 0x810af41d 0xf8d322c9 0x14f17d5a
+ 0xac7aed44 0xb5fcd81d 0x65eb270f 0x207876ca
+ 0x8a89846e 0xe6418235 0xb5a935c4 0xf188f339
+ 0x9acf3f50 0x5083deba 0xea6c6c76 0xce7e9d9e
+ 0x22461871 0x87f0108f 0x12a97a3b 0x7c8fdec8
+ 0x8f326b24 0x617cb20e 0x21a34a79 0xce7c70ca
+ 0x1b33c68d 0x92f06767 0xc51c5649 0xf5ae12cb
+ 0x75c2ff79 0xe485811f 0x191c9dba 0xc87e8cbf
+ 0xafd4b4d2 0x6fc0af0c 0xbb76c0ba 0x6fb0336e
+ 0x46f59bb9 0x401ded33 0x88a92571 0x328d44c2
+ 0xb494f4dd 0xf5a68521 0xffbacaa9 0x30ff5d32
+ 0xa3dcc986 0xc10670cc 0x4d9d69d4 0x365865d7
+ 0x9ae0ef1f 0x97e8a835 0x83acb6d4 0xeb6fe7b0
+ 0x7337d45a 0x384731ec 0x6a12e5f5 0x5f5f0f92
+ 0xb0ab43f3 0x1ecff295 0xc2c72221 0x02d90770
+ 0x59869deb 0xe01eb4ed 0x38691b29 0x39b21ecf
+ 0x812a2a39 0x1d211c6f 0x027ebf3f 0x9b94bc94
+ 0x0be5efbb 0xd4c43105 0x0a3845c4 0xa5662a41
+ 0x5110cbef 0x127d92bc 0x99924648 0x222c4bdc
+ 0x4db3da4f 0x57c771fa 0x3820187a 0x0fb448c9
+ 0x3c17cb96 0x76d5c447 0xdd6cf323 0x180615dc
+ 0x6d133cf6 0xbed0d7f3 0xb542fdb6 0x837ff1c6
+ 0x5686629f 0x1412eea2 0x45b93f3f 0xd6c324a4
+ 0x9b3021fb 0xf0976d4c 0xfc02bea8 0xeab7f534
+ 0x0a5f2aff 0xeabbd304 0xfc2b6ef2 0x8e1444fd
+ 0x6a683e99 0xef114948 0x9c61f02f 0x702da123
+ 0xa10a252a 0xb435a995 0xc828d43b 0xeb2e16a1
+ 0xed91a2f1 0xb1783a96 0xae6eb190 0xf5b3ece5
+ 0x15caec18 0x41d2124b 0xfe97094d 0xb63028bc
+ 0x3849f412 0x60c25505 0xbee19f15 0xad10e883
+ 0xcb4529e8 0x5ff6312f 0xc081c3a8 0x51d7c2b7
+ 0xdf4b795d 0xe14ace52 0x639c5108 0xce31269d
+ 0xed005d20 0x0f251ce6 0x105051ff 0x7ace3072
+ 0x2e490489 0xd0677ac2 0x06c42d29 0x09c7eab7
+ 0x03a75852 0xda74f991 0xe8bbd5d8 0x49a04f14
+ 0xc034774c 0xcefa0c35 0xada23997 0x247c022a
+ 0xb87a5cfd 0xd47e56ca 0xc6a48f18 0x745f325b
+ 0x97fd37de 0x16ee3f7a 0x94d119a0 0xc943976d
+ 0x3969772b 0x3b4eef57 0x13b0c418 0x9a03fed8
+ 0x2311572b 0xaade9680 0xce4cd64c 0x63180789
+ 0x00abbb28 0xd10c8e72 0x55967c83 0x6eb8b4a4
+ 0x8e178a4c 0x245db146 0x37ddc447 0x265c0aad
+ 0xfd20a1c7 0x3c6972a1 0xe8f63469 0x4269bc90
+ 0xe5c9ede7 0x7b8f7b4f 0xe777406f 0x17e2a6cc
+ 0x5ffa1f4d 0xeded9e39 0xb83702c7 0x8ac429ee
+ 0x926d8060 0x91ec6bce 0x89a6f240 0xbeb1b113
+ 0xd0d62f8c 0x6282f306 0x805e8d16 0xc4ce2681
+ 0xf1a51ca3 0xd3f69f39 0x50ee27c5 0xdcdb84d7
+ 0x7744f4c9 0xe750aebf 0xae52b932 0x7833c17e
+ 0xb6adf91b 0x86c7a692 0xfb8b3854 0xee875284
+ 0xc66a6e8a 0x950e6596 0x5a21665f 0xb99421aa
+ 0xb2bddb7b 0xf0307281 0x22e79399 0xb541e0e9
+ 0x6a45bc69 0xb6ebdd7c 0xd851e16b 0x9783cf97
+ 0xafdfc7a7 0x4f011d28 0xc570cd93 0x752db80a
+ 0xcf3de399 0x907d3ad2 0x91faadac 0x8c9c578a
+ 0x61cfc727 0x8b20e89f 0x4d5a6666 0x8c28e00f
+ 0x1a1675d8 0x7c793aa3 0xa2210e0f 0xaa5a9509
+ 0xa3942ddc 0x5f8b76ec 0x00aa7a2e 0xea375121
+ 0x521b786e 0x4b27e1f4 0x262332ca 0x2a739651
+ 0xf442ed82 0x74f40d7d 0x0f374d95 0xd6121c68
+ 0xdc6aa0e4 0x0fefe09a 0xb06ef32f 0x45951415
+ 0xc25d5b51 0xa139a8f3 0x87363003 0xe59a0f0a
+ 0xbfc54dc9 0x69f84ef1 0x3804453f 0x976850ab
+ 0x65bfbe93 0xa0b4c673 0x5fd531fd 0x1b90f96d
+ 0x93c92211 0x26236f14 0x6d67aa9e 0x1fc006aa
+ 0x1e41a145 0xc952b72c 0x3e274f98 0x6cba1001
+ 0x8a3007b1 0x12318114 0x82ea0917 0x4a783735
+ 0x967e9463 0x957c4366 0x039c4f2a 0x732e105a
+ 0xbe8f62ce 0x7acf5484 0xc1dbcbf6 0x6d663150
+ 0xafcc53d0 0x9e54e869 0xaccd2f5a 0x0596bac7
+ 0x6102d4bb 0x145b2201 0x85772d86 0x157fd7a4
+ 0x27b4bceb 0xbc8634e8 0xd713f53b 0xb9a22cb9
+ 0xbb6e509a 0xec84eb87 0x58a99ff7 0x6e026c56
+ 0x262cf17a 0x96aa6b86 0xa432b5a7 0x4261f767
+ 0xdeb7cfcb 0xe52bd101 0xedce6213 0x6bd1704e
+ 0xd446c3ac 0x3396a979 0xe46c23ca 0x1be0b8bc
+ 0x04b81418 0xb74da201 0x1ba7e42d 0x96db8852
+ 0x01477c80 0x4f84f7ed 0x556e3d40 0x2c5ecaa6
+ 0x784f461f 0xe6a79f5f 0x223f6345 0x7dc789f9
+ 0x803cebab 0xc9fc7fab 0x144312b0 0xfb68670c
+ 0x8d3bd502 0xb73a19c0 0x50b4dd3b 0x4434bc5c
+ 0x3c96afa1 0x4caeef15 0x4b73b56b 0x6c2dc827
+ 0x09d29490 0xda88aafa 0x58e7d66f 0x02d85153
+ 0xe028d696 0x397376f4 0xa0b385d4 0xfc52d8ef
+ 0x9ff7f61d 0x53d9e137 0xd7eade45 0xf61a3be9
+ 0x732b9585 0x172e0d6a 0x6b439ec3 0xf7e69034
+ 0x11cf3bfa 0x72db7836 0x28a71411 0xa7e541b1
+ 0xa11a869b 0x40cc133a 0x99568ddf 0xf88f5407
+ 0x3b9566c6 0x14ee8af3 0x0a553446 0xde19963a
+ 0xb30a65df 0x620f06a9 0x23a13e20 0x677abaf9
+ 0x85348c3b 0x227e886e 0x621ada06 0x29410dd6
+ 0x1d3279c2 0xcb2e1db5 0x8f9e4dec 0x39c7ef14
+ 0x1deb388e 0x487865ab 0x2063f724 0x13309f26
+ 0xcb9c175e 0x5db6e659 0x2d4afe5e 0xf93105b7
+ 0x9c88614b 0xe4c2d81f 0xee47bc34 0x05a42aa8
+ 0xc7a366c1 0x717696ba 0xecfe37be 0x8ef87213
+ 0x7953b258 0x6b4cc006 0x9687ef62 0x7796cc13
+ 0xaeb3b791 0xd8c6d496 0x6801b485 0x75d7bc78
+ 0x6b6eeb6e 0xf38743d8 0x6eb75dcd 0x384cb686
+ 0x54bb91c8 0xa4c32f35 0x54bb1256 0xae792803
+ 0x7764e3f6 0x24ab5fa1 0x3e629e01 0xdeef8f34
+ 0xea0bd2ff 0x665e7068 0x18bdd480 0x225c0af7
+ 0x96d97929 0xee100c2c 0xeff847a5 0x714dd01c
+ 0x4e18e204 0xe804801f 0x9ee779dd 0x8b116fea
+ 0xe46e94fe 0x3a7c2031 0x059d9ae9 0x35704f42
+ 0x88d7b497 0x90c487e7 0xe82c3c79 0x4ea43be4
+ 0xa898a30c 0x68d8ad90 0x675dd885 0xcd3102d8
+ 0x527ae14f 0x6cecf590 0x85157cf1 0x713fa88c
+ 0x1a3871ae 0xa6a7901c 0x69ed7c83 0xd65a3328
+ 0xb9b99e6d 0xa8abd0a1 0x22878c58 0xfc1b1ee5
+ 0x86c19e75 0xe370301b 0x312058dd 0xf886eab6
+ 0x6887322c 0x5bb6097c 0x45710db2 0x0a0f0b3c
+ 0x77367703 0xdd22a598 0xaca61cb7 0x41a8d898
+ 0x1cfd1b9c 0x1b5efdee 0xb89bc576 0x9b7bf384
+ 0xa51b486f 0x43bd652c 0xdc2a42c7 0xf1d964e4
+ 0x60162276 0xecb776da 0x8debf109 0xffe59535
+ 0x81a2b6a2 0x3db50d88 0x2b7446a0 0x8e3db5f5
+ 0xf0e60f94 0x29c4ec91 0x7d028705 0xc9822a5b
+ 0x448ce3b1 0xbb764fd8 0xc1cc6a57 0x2209a704
+ 0x79e09f45 0x55bbb983 0xd49826d9 0xc4a8fde9
+ 0x0d21fe4a 0xba53caf3 0x7fb4bd8a 0x726917ac
+ 0x987c1240 0x06d3bec4 0x20e63056 0xb935a165
+ 0xda3ea0b9 0x17c5542f 0x608e6dac 0x0d0ae11a
+ 0xbfa956e7 0xec1c2a59 0x8f876337 0x08cc0abf
+ 0x01893ffd 0x52ad2c87 0x20b44ffb 0x9629089d
+ 0xe38c7dff 0xd170448b 0x58ec3730 0x058f49fe
+ 0xf71605f4 0xae95f30e 0x392fb97b 0x1d253d57
+ 0xaf27d084 0xf40ee99e 0xc7e6bb9b 0x2385218f
+ 0xc33d94cb 0xb3409f26 0x84aada63 0xc519ac78
+ 0xb95ababd 0x70e0d193 0x85456e9a 0x619065ab
+ 0xca86977a 0x39f8b061 0x283f9b30 0x501e24b5
+ 0xb7c6d6e4 0x4ae8a58f 0x2d1002b3 0x59987e28
+ 0x0468ccf4 0xa2f04277 0xb0ac7e87 0xb5810d46
+ 0x0bad366e 0x483e37c3 0x787222ee 0xe33251ca
+ 0x632f6dc1 0xb5cd27af 0x37152a50 0x03204246
+ 0x734a5b2a 0x884f4d38 0xe690b2ed 0x0cf8e2f1
+ 0x5e6ea1fb 0xdde6e3f0 0x2c64badd 0xb3e27661
+ 0x958d5792 0xabeb5422 0x7bd72c81 0x423ddb78
+ 0x5da377f2 0x63c26b0d 0xa5bc8b76 0x407d5d9a
+ 0x95d388aa 0x3bd4e246 0x9e0fdf3b 0x95a68a1d
+ 0xda40dc30 0x04fb17b5 0xbcac4960 0xb21548e4
+ 0xb13fb831 0x897b8443 0xba928329 0x02c9ef1e
+ 0x955b70fe 0x66decee0 0x0028f1ba 0xd6abca27
+ 0x07c3e749 0x81daf249 0xfcc77b67 0xd92cb560
+ 0x4d99bc0a 0xfd4f2868 0x835ca0e6 0xf7cbdfce
+ 0x2ef23e50 0xb73dee70 0x52c31bd3 0x0216f011
+ 0x8f843803 0xbb328ce8 0xbafe6cfa 0xdc11931a
+ 0xca78f5af 0x701901bf 0x0cb2f369 0xcf81f5ac
+ 0x130df41c 0x4ebf5b97 0xc20e71dc 0x77c7db59
+ 0x7514598e 0x076b8d81 0xb4455b6a 0xd39a43a9
+ 0x1454ec13 0x16bf144f 0x873b8300 0x8cf24e90
+ 0x06df232f 0x5d72ee57 0xe77b4ca0 0xfe7a93ba
+ 0x71a6fe0c 0xcefb044e 0xfa41f121 0x0c736797
+ 0x69d26292 0xa4571b00 0xb6cd7ba2 0xd088966e
+ 0x13ba8390 0xabd689f4 0xa7348565 0xe153af32
+ 0xd3af3755 0x3a291ac4 0xd0fed6e9 0xe76d077a
+ 0x3fa5afb7 0xea870423 0x9bc02dda 0x0696570e
+ 0xc528294c 0x8035bcb1 0x3fedf497 0x4e85da97
+ 0x87834ad7 0x4cbc4464 0x7fc32e15 0x9f248783
+ 0x74cc30fb 0xc004e66a 0x65b3e508 0x9dc7bf07
+ 0xe70e9553 0x762c4e53 0x06377c76 0x415d95dd
+ 0x4c74daf2 0x5492b248 0x2ac359c7 0xafd715ab
+ 0xeea3bba9 0xdc21177d 0xb89b4364 0xdd3fbe05
+ 0x5e2dc68f 0xc445c91f 0xe2a7305b 0x3b434867
+ 0xd55f2fea 0x028f3861 0x8c5656d4 0xe2c04c10
+ 0xaea45e47 0xe65651a0 0x6f67d97b 0x759d1fc9
+ 0xa0bea30c 0xe62c32d9 0xbb57faaf 0x40207bd6
+ 0x780de534 0x0fe4b81c 0x0735bbc5 0x25dc0c03
+ 0x3909ff0b 0x1808cac4 0x520b8337 0xb9729f84
+ 0x24fb3c1d 0xd82e0a5b 0x79f99b13 0xe9612c13
+ 0xaee4bce1 0xb6c0f691 0x32d2c31c 0x9e6f92f7
+ 0x86e98158 0x33643ab5 0x7617e010 0xb95bac7e
+ 0x0e56bb41 0x74dfabea 0x3cf7749d 0x119b9839
+ 0x875cadea 0x9327f3d2 0x1b5a9b8a 0xfcdcdd2c
+ 0xbb7300f6 0x7b532fdb 0x0bce3f2a 0x93a79dac
+ 0xb88f3690 0x342e1bed 0xefad0cd6 0xc31975b2
+ 0x575a8a01 0xa524c868 0xcde65ef0 0x97a9c33f
+ 0x735784e4 0x40498a19 0x45c63c8d 0x679a2416
+ 0x046c9898 0x8e66cc4c 0xff503359 0x95dfbe22
+ 0x2424bd50 0x2b882310 0xe4d6931e 0x55e4e1a6
+ 0x2dbfebc6 0xe2b10c94 0x2ba0b6e4 0xbda3f610
+ 0x78ccb9ed 0x15eca5aa 0xf3ef1825 0x7fff8209
+ 0xb9ae92e9 0x4344502a 0xbe549a7a 0x459997b8
+ 0x4c88c72e 0xcb6109f3 0x57879c01 0xc1e7d40f
+ 0x79cbee03 0x52a5dfc7 0xb0a3e20c 0x11cc0682
+ 0x634345d4 0xb1097bcb 0x4170bc95 0xa38e7f08
+ 0xf89ecaba 0x37f4f748 0x50fd02b8 0x6b026dd7
+ 0x8e9270f9 0x3c6bd04b 0xcbb680d1 0xe10f1161
+ 0xfa3011fc 0x273f1915 0x66bea263 0x22ba4a11
+ 0x73d679ca 0x9f88a3c7 0x40eed71e 0x974b512e
+ 0xc1fe137b 0xf0054108 0x223fb47f 0x0fd0ae5d
+ 0xd2352fbf 0xebc2229a 0xac38d629 0x25ec7169
+ 0x1939d86a 0xc879b796 0xc7f8dce1 0x92b9dc60
+ 0x3e5291de 0x936a2f7e 0x9b2d869e 0x24d0f8cd
+ 0x1ba680c9 0x0c839619 0x0d69bbdb 0x26a3644d
+ 0xb102adfb 0xec059a27 0xe2477ab9 0xc2e9f654
+ 0xe5f257ed 0xa9cd346c 0xc0f22053 0xb9dfc03e
+ 0x3f737368 0x791e3a80 0x5d6280ff 0xda55df26
+ 0x8d5740e3 0x2a6d7113 0x83a70056 0xbb31a7f5
+ 0x413f4612 0x5302ddfd 0x44f41d43 0x675b7e05
+ 0x723af78a 0x2d833251 0xaf8419b3 0x3bc05d32
+ 0xa9251294 0x92fdec09 0xa1346541 0xec186dd5
+ 0x252d4e94 0x55a207dc 0x09e57c82 0x05a8198d
+ 0xb970c263 0xa772c113 0xe625a4a9 0x780f80ed
+ 0x5391fdc9 0x40f8e6ee 0xd37cf89b 0x35e1a4b4
+ 0x8e2e14d8 0xf595c9f5 0xe457cb19 0x7da1c578
+ 0xbaee8480 0x6626129b 0xb0e949b3 0xdfa72b6b
+ 0x2df13902 0x041f7101 0xd7ad6d85 0x84a12d44
+ 0x3c48863b 0xd77a0d78 0xc4716f33 0x5f6c80b7
+ 0x8dbc331e 0xb81e99b9 0xc030f343 0x1395fa80
+ 0xbbc472a9 0xaadbddf3 0x331f1162 0x62aa6ae3
+ 0x329ef3ce 0x3c63ddf9 0xf74613a1 0xe6845844
+ 0x2bf454d9 0x9349f051 0xe47c2353 0xedd3ad76
+ 0x6e148e5a 0xefc1a92b 0x2c94fc97 0xc96ac0dc
+ 0xa1b239d3 0x56fa2e07 0x5dce9da5 0xd99fc97a
+ 0x151f4557 0x92d3b296 0x51c5adb2 0x472e3502
+ 0xa2a9ca6d 0xdf1537fb 0x7497ee54 0x652788fb
+ 0x3480f678 0x6226432d 0xd3196022 0x60af6d8e
+ 0x7b9ba419 0xd510fd1e 0x48d5309e 0x5fc1c0d2
+ 0x108a41de 0x0e9f8028 0x549710b4 0xc48d9ab3
+ 0x36fc7bff 0x7e257815 0xd51cc507 0xd321681b
+ 0xe12d9f15 0xfe39bede 0xdcc3ee34 0xeb20cba9
+ 0xcd77b4a7 0x894b9283 0x2b5c1cef 0x5200e41c
+ 0xf67270bb 0x5d104c61 0xeb64074f 0x22f5bbc2
+ 0x37d8b7cb 0x88122de3 0x009cffd2 0xe772f72b
+ 0x9c63f41a 0xc424e4ae 0x1464b37a 0xa6dda79e
+ 0xcf89c39a 0xf23eba0a 0xf3f3a685 0x50120883
+ 0xace33f54 0x53346d1f 0x3ce75d82 0x555040f6
+ 0x4b458356 0x1d617f5b 0xbd6d29d5 0x6789cae9
+ 0x3d787e1c 0xaf7dac99 0x69ae0efe 0xd5b62c89
+ 0xc1b371a8 0x466c8316 0x4a1a399c 0x02d36ce4
+ 0xcbdc024a 0xc69d6d8d 0x88926761 0x12a5d8b4
+ 0xe01c2b8b 0x1e1991cd 0xe9aca0a8 0x49410f8b
+ 0x426226d9 0x4b9d3543 0x6072827e 0x6037c39d
+ 0x40e457d1 0x3361d4fc 0x7de4c8a0 0x68800165
+ 0xc1e069b0 0x71bf38ab 0x4ab64b8c 0xc0acd6f4
+ 0xe742be7c 0x46e21cee 0xed07ffba 0x148c7fe3
+ 0x48c6a945 0x8a561bc6 0x3838c25f 0xcfed3d21
+ 0x87451835 0x3a75912d 0x2ca7241b 0x5b252f6e
+ 0xffc394b4 0xf4f62530 0xb933058d 0xe62195a5
+ 0x09542e3d 0xdc5bbbab 0xf87bfd18 0x4a0915bd
+ 0xdaee30b0 0x1c45049b 0x53057aef 0x8559c1b8
+ 0xf4bd34ef 0xa70cc429 0x37ecbe19 0x5d2c0088
+ 0x30c6e209 0x14d3f5ae 0xac2fce42 0x47b96c6e
+ 0xe0b33111 0xefc61925 0x24554cae 0x401cca83
+ 0x248148df 0x4d36387b 0x01987a6b 0x8f9ac8f9
+ 0xf93718c3 0xf4c0605c 0x35600f33 0xbb57951f
+ 0x01bd3ae3 0xd6b00ead 0x5c900933 0xbeafdfac
+ 0xb3496a47 0x0e6d06ed 0xa69a4710 0x4aeee99c
+ 0xdc59363b 0x710300bd 0x51643fc0 0xb2fa91eb
+ 0x379f7f65 0x39c6e97c 0x098d6935 0x2a9d3085
+ 0xd4df1162 0x5a2cf41b 0xe8671010 0xcc7d115f
+ 0x328d3892 0xeea7d61f 0x573ec7e9 0x741a117d
+ 0xee2ea628 0x3d1b983c 0x7f92a4bc 0x62025cbd
+ 0x7ed34073 0xddb5d088 0x10139b27 0xcc217f9c
+ 0x809352f2 0x6d1a1668 0x4ee31e30 0xd21e1f5f
+ 0x6d37301c 0x176d8faf 0xa7768fde 0xcad1bb7d
+ 0x24deebef 0x134a7f2e 0xcde8fd3d 0x409fff56
+ 0x81b89c4d 0xdadf2ef1 0xe970a40f 0x4dca9906
+ 0x948b6082 0x886f9c40 0x402ab8b5 0x3f3a363d
+ 0x31c5f241 0x6b829609 0xf8923e52 0x2c6f3dc2
+ 0x8b831a4c 0x0f847c9e 0x5dec8240 0xdd999571
+ 0xe0e0bd87 0xcdabc523 0x347a64ed 0x622a5655
+ 0x63a26351 0x29ff7cd6 0x5dd5dfa1 0x79996f26
+ 0xde481466 0x10d4782c 0xb6e77d9c 0x0dc2853e
+ 0xd0c81fd0 0x5f0bb987 0x27f4ef8d 0x9c23b96e
+ 0x98fb2a24 0xa0e15d67 0x93fe17cd 0xe628130f
+ 0xf2843acc 0x93bb57c9 0x4273a3fa 0x265976f3
+ 0xbbee8aa4 0x52d8ef84 0xb3997bba 0x369525b6
+ 0xeb7c39af 0x872c5324 0xc400f956 0x1cb37354
+ 0xf4948758 0xe3096651 0x5a0ba8fc 0xfb69c499
+ 0x312d8763 0xf3343ecd 0xe6fd3135 0xb3498520
+ 0x5c854917 0x328b3eaa 0x1c840929 0x1c36fe47
+ 0xfe0c3e42 0x56a8862d 0x3569f945 0xc22dda25
+ 0xf84b1f5b 0x004dc57c 0x8a00a3e2 0xac699574
+ 0x51039189 0x765e8036 0xc7afcc49 0x04842695
+ 0x7b84b057 0x9c97f05c 0xcc79bb47 0x17dfb4b6
+ 0x2fe652d0 0xe1498d3d 0x2ca8b3f8 0xb53ee5e3
+ 0x1050d2b3 0xa2572be1 0xfcd3c334 0x70a15f82
+ 0x1728b0db 0x6209c5fc 0xb44e5603 0x863332f1
+ 0x96838397 0x36955feb 0x0d2da0a8 0x125e7d60
+ 0xde2a310a 0xa351a181 0x6b228298 0x8a4d1cee
+ 0x5e6b14b6 0x2f3a9457 0x3e9dc04c 0x74479b2e
+ 0xd3d05a04 0x68d212fa 0x117406a4 0x4748ed39
+ 0x41d5cd60 0x8dc01410 0x3ae6572e 0x70285c5b
+ 0x83134014 0x1ef0ae5e 0x003e6be1 0x0b3ae0b5
+ 0x39185245 0x5855200a 0xa12dd85f 0x35d08c8e
+ 0xb8b9b054 0xe631c2b9 0x2008ecfe 0x8f3eb245
+ 0x79b3a1b5 0xec1b3903 0xda6d57b0 0xcdee5055
+ 0x25af467e 0x26d5f7ae 0xd97ec276 0xeea91eab
+ 0xf261e901 0x3c981d7f 0xcd9dccbb 0x32136d85
+ 0x9cfdb038 0x7fee83d3 0xf6e6d1f2 0x177663fc
+ 0x0b6ed3a5 0x72670825 0x2cbb9cef 0xe4436641
+ 0xc61f9d9f 0xb5c763d4 0x213a06bf 0xbbce6dc1
+ 0xaf464963 0x343697e4 0xa2b3af13 0xf7fdd78f
+ 0x6a460f6c 0x1b62c963 0x352ba307 0x91c830d3
+ 0x66116773 0x280dfc31 0x302844db 0xdb47b3bb
+ 0xc0ad1851 0x9979ba50 0x0083ba23 0x25c70fae
+ 0x7c06b66c 0x65d20a4e 0x9848a1a2 0x295bacc7
+ 0xe44c5837 0xfecf2330 0xe3ed6510 0xb1a48827
+ 0xe694e108 0xa8a41bf0 0x17c797d3 0xfdae9b67
+ 0x6f8ce672 0xc8d89a80 0x8f71f171 0xe95b2a4d
+ 0x99f9e617 0xa6af87d5 0xa9160687 0x9d0393de
+ 0x89bd4e6e 0x6528c903 0xa3ca2db1 0x6f77a5d8
+ 0x9c377bb6 0xb888ea4f 0x06b81f7f 0x3c5c8de5
+ 0x3bbcc468 0xcfaae47a 0x502a3f60 0x158c94c2
+ 0x225ab827 0xaa630a68 0x77afe20d 0x19fde08b
+ 0x171a5af6 0x81d81f8c 0xfde9be4f 0x69cd49b0
+ 0xd83ff3c8 0xec30b85e 0x58621479 0xda1f95a5
+ 0x0b1d8f12 0xcda765c2 0xb509d70b 0x76d158e3
+ 0x7c9d02b2 0xebfd61e3 0x6e4d8ec8 0x8b779fdb
+ 0x38d745b1 0x287a434b 0xf20a73ad 0x897e635c
+ 0xdb9c36f1 0x12d23511 0x92f661bc 0x1e46d8a8
+ 0x58d1f9e2 0x1f984e89 0x3b7d87ae 0xed74a89f
+ 0x1c5614e3 0x1498a110 0x042704c3 0x287ba930
+ 0x2f2a5122 0x5838d48a 0x85b720f4 0x2c99ed7c
+ 0x893ab885 0xe1d9b760 0x0d097bfc 0xc0b1835a
+ 0x2565db51 0x8b2c75c0 0x34b273ab 0x4e77c96b
+ 0x95d64cf4 0x466a739d 0x32f2f18e 0xb993681b
+ 0x2259c2e3 0xcd3c5fad 0x93b7a44b 0x56db345b
+ 0xcc391356 0xa56659ce 0x9ab298d3 0xf756c870
+ 0x9e8aa6b1 0x27f7ecfe 0xb02ecf08 0x3db06cfa
+ 0x62225f46 0x0cbdc0f4 0x3660bc97 0xb600d787
+ 0x47448beb 0xf2ec76e3 0x2f35cc41 0xaa07ac70
+ 0xc8d7cfb6 0x3191df12 0xa35ed6be 0x5f6350a0
+ 0xc92a1b36 0xe51e83cd 0xe67f70fe 0x2c30dc44
+ 0x2720ea68 0x8989e2e3 0x1ee7a61d 0x25e49174
+ 0x60370be6 0x4ad9f751 0x98269b55 0xe38875f5
+ 0xa7dcebe5 0x8eaf1efb 0xaca785c1 0x75ef8dad
+ 0x9c4a4e81 0x05b14e6b 0x94973929 0x8b0e51b5
+ 0xad7d26fc 0x6028aca3 0x76abe148 0x2cf38c8e
+ 0xf16de59b 0xe0e9ef73 0x14a157df 0xa487f134
+ 0x90808475 0xc7c8fdde 0x507b2fa8 0x715be38f
+ 0xe984cdcd 0xb86a2fd7 0x62996d71 0x41ae9aae
+ 0xaf328519 0x6e26bd43 0xa9259149 0x43011256
+ 0x8db13e02 0x666fcc5b 0x75850832 0x7a8967c3
+ 0x533724bc 0x57d692dc 0x4b2bfa27 0xa94f1345
+ 0xabc7f978 0x112a0629 0xdca1371b 0x99b30d9f
+ 0x171c1e7d 0xba9c4528 0x715eb21f 0x824dad28
+ 0x77b0faec 0xa8dba035 0x3026db98 0x5480ebd8
+ 0xf6dcf737 0x9f01c720 0x505379b4 0xcfb68c56
+ 0x8010d1ec 0xc0a022b6 0x0494af87 0x34a5e3bd
+ 0x5f97db91 0x91c4f8ee 0x22c177a5 0xb3b3b38c
+ 0x3b96b026 0x75e82ee9 0x6c25591e 0x79cb8247
+ 0xb81a26a3 0xe9242a92 0x8427b5f9 0x0893338f
+ 0x0d6869c3 0xec22cd57 0x5d7d4621 0x95cdac7b
+ 0x8408d975 0x11d40c4e 0xf38fe7a1 0x088dbf91
+ 0xa603a268 0xd9098a09 0xf8687105 0xba9e11eb
+ 0x197b4e7e 0x4308d671 0x50b99383 0xc29a07bf
+ 0xe1076808 0x22d410a6 0xcfdf5b6c 0x798c63b2
+ 0xf8928203 0x59341208 0x9da6636c 0x7ea8b574
+ 0x9c56d366 0x9ee85f63 0x27901787 0xf7fa83b6
+ 0x11ec3148 0xc5866a56 0x1ac9faf8 0xc8600dcb
+ 0xb4cbf815 0x6553c20e 0x408db234 0x30452ecd
+ 0xa50638c3 0xac82df8c 0xc12e0fe6 0x281e6189
+ 0x7f4d9cc0 0x5c12a79e 0x8da23fb4 0x8e495e59
+ 0xbe52507d 0xc75d5612 0x7ca07018 0xffe33c48
+ 0xe8a9c75a 0x30a3d329 0x8fda15ba 0xd7c53ea3
+ 0xdd07d298 0x968dd723 0x594af13d 0x05593aa4
+ 0x2fab8d67 0x3ea4294e 0x60c3d12c 0x1b2a165b
+ 0xe3b5d840 0xe8f078ad 0x0bcf0df1 0x56a08b20
+ 0xb99e6aa0 0xf119a946 0x1b3b1613 0x0691eae0
+ 0x20a8c753 0xb864bd3c 0xeec8d111 0xfc809ccb
+ 0x5230e148 0x968a3f36 0xbedb39ee 0x96ef8cec
+ 0xd137d35b 0x4b336a7c 0x8fcf008a 0x65a4a722
+ 0x7688912a 0x95b30531 0x8bd2df5f 0xa21f1deb
+ 0x7c8288c3 0x11cb48ba 0x3604f444 0x56af95f2
+ 0xe16135cf 0xa7b34be6 0x104db16e 0xcb94acf9
+ 0x5e9be620 0xfbdf8d99 0x61a16de2 0xf1739a2b
+ 0x177e6ccd 0x2d473093 0xf8b85187 0x10c7bdad
+ 0xcd44645f 0x6a7a371d 0xe860523c 0xf631119d
+ 0xaaa070d6 0x79668637 0xe9117794 0x42c496d0
+ 0x9d294481 0xa640ccba 0xc1201582 0x5d86a701
+ 0x1c935a06 0x10719c63 0x53889b4f 0xf0e56447
+ 0xc54e8d83 0x95968c38 0xade37a4c 0x2fd5461f
+ 0xb2e4cc0d 0x316c6c57 0x379cd5da 0xdb4510f0
+ 0x5d71f2b6 0x10786416 0x6fcad2da 0x65f1908c
+ 0x64aad9b9 0x08cc03c6 0x57ffa0f9 0xb12d0384
+ 0xe12be67a 0x3dc91a85 0xd88ca183 0xb3b3512c
+ 0x5b0d71c3 0x1389ed0f 0x99b6823c 0xc263b6d8
+ 0x7e6a18ed 0xc74c9223 0x03e92612 0xc3b16895
+ 0xebda3f4b 0x76d79b51 0x6b41a791 0xe838eb87
+ 0xf80aa3dd 0x49dc8f9c 0xad7dc06f 0x0c0e6e03
+ 0x9a533db8 0x51d66b1e 0x5415c797 0x9645217f
+ 0x34b8dd97 0xc100b64a 0x6d2de029 0x4f7e89fe
+ 0x8292bd52 0xa4309ad5 0x4a6651a4 0x4e67eaa8
+ 0x97e27f87 0xd24fdbbe 0x367ec769 0x5704cfcf
+ 0xc48e8c08 0x56fe9fe2 0xfb85f4ed 0xb0c68432
+ 0x226d73e7 0xa1ce4c14 0xa50f188a 0x33f003bf
+ 0x273e59ea 0xee1a3901 0xcf20c176 0xef66122e
+ 0x197b9e36 0x4d866dc5 0x9cf4b530 0xd56ac309
+ 0xf91f0f44 0x3143dae4 0x61ba2ac6 0xab3e3241
+ 0xb070fe2d 0x8c7ed48d 0x9cdd506b 0xd052fe76
+ 0x171287b1 0xed3fbd70 0x98f23794 0xe881dc63
+ 0x916d5bcc 0x5a5d405a 0xf450ef75 0xc99b0ee3
+ 0xfc1f0b8a 0xe05e94d6 0x1f0da54a 0xafc412bc
+ 0x838546f2 0x7913cd41 0x029b6992 0x00bc4c0f
+ 0x872c237f 0xda6114b3 0xc18ab867 0x437cfde0
+ 0x33aba1cc 0xf87d202f 0x571b233c 0xd2ebc904
+ 0x5efca706 0xa7d9aaa6 0xdc03ca11 0x1b5a00af
+ 0xf85427bd 0x5329e108 0xae95f78d 0xf38e0d3c
+ 0x8f976d3e 0x36474f32 0x8b96a672 0x2f5fb1bc
+ 0x2c12ee75 0x348265d9 0x69ccbab1 0x852631d1
+ 0x71a08001 0xc6e3ed3f 0xfa9a584f 0xa3e98596
+ 0xd6730da6 0x41300caf 0x7b5fd490 0xc9158337
+ 0xe02ed753 0x605b5f9a 0x684b6cfa 0xd8186840
+ 0x1026e9c3 0xd8550587 0x37d7fcda 0x140021ca
+ 0x13effe78 0x6f3184ca 0xa8f8ba37 0xf56a5c29
+ 0x502f4ba0 0x36901ba0 0xdf60a738 0x6afeccf9
+ 0x206e4e7d 0xe763e575 0x9e3dd2e8 0x574c3bd9
+ 0x2b9050d5 0x36b1833e 0x018a432a 0xa544ffcd
+ 0x94d11277 0x350c57f4 0xbde9ee5f 0xf2c634ee
+ 0x826933e0 0xd807dd5a 0xe9ce6b4e 0x380419d4
+ 0xc48514fa 0x9fec960b 0x612b53bd 0x3bd0f68f
+ 0xa8b9573f 0xee1af1a4 0x5ba43078 0xdc4433e6
+ 0x09980221 0x84e2b562 0xd0685c82 0xc821e22a
+ 0x2f591314 0x36cd6cf8 0x95a584ee 0x85ac1c0b
+ 0x8e1c4d17 0xfdcd3aff 0xf59140ff 0x990cecb2
+ 0x5a86b9c4 0x0be7961b 0xd10cf022 0xda4e0039
+ 0x0d42ac7d 0x6b6068ed 0x595b338f 0x8e66fbd1
+ 0x5d76290e 0x1eb1d30d 0x02681d5e 0x675f48a9
+ 0x3620fec9 0xcbeb129d 0x9d0d7d90 0x286b7f46
+ 0xc96084b6 0x001d009e 0x5e0d3f04 0xfdc775cb
+ 0xfdc6f6aa 0x4f29084d 0xf8fbd3a7 0xf859eb71
+ 0xa7e37df0 0x9efe5fef 0x2f611654 0x7061f5ce
+ 0x50f95714 0xcca9c4b2 0x72262846 0x376c21bc
+ 0x4edad528 0x5d241145 0xf2dc8615 0x9ac9da86
+ 0xbc5e3211 0xc6df5283 0x8f1346c8 0x52479029
+ 0xa38fd13b 0x7b81167b 0xf7f2eb16 0x09e4675a
+ 0xa4cbab39 0x4aaf12e8 0x0d156c19 0xf2ee198f
+ 0x857661d4 0xa39f33fb 0x6f500373 0xdcd3aab6
+ 0x5e4d97fd 0x8184eb1b 0x1e00850e 0x56037e60
+ 0x1f5c2839 0x5fdd3d3f 0xf5462ad5 0x9e96d752
+ 0xe1499fe4 0x30571868 0x895af53d 0xd37d411d
+ 0x4a1a3461 0x95c4f0b0 0x5ead887c 0xf53803ac
+ 0xf3cae670 0x09f151ea 0x102cfa3e 0x5784433d
+ 0xcf581826 0x476cfbb9 0xd1489eb6 0x68f4727a
+ 0xc4dc85a4 0x9094832a 0x0ff6725f 0x7f1f40a0
+ 0xf771d9d9 0x13c2b620 0x75448c8e 0xfec2bfc1
+ 0xd707e400 0xabd5b0ff 0x71753ced 0xd4e9fcf6
+ 0x2a4ddfd6 0x2719afe8 0xea8dc6a6 0xf75ea39c
+ 0x619a0725 0xab1110a0 0xbd63041e 0xd839bb8b
+ 0x693bfce2 0x989031f9 0xf621e105 0xedcbd708
+ 0x0cb4aa8d 0xf1ccef16 0x06894709 0x0aff3a4f
+ 0xdefe2281 0x2ad64edb 0x349b9733 0xe062b7f4
+ 0xc8aa62be 0x36a184f1 0xcb918d5b 0x844ea7ef
+ 0x78585466 0x80139ac2 0xe45b2b11 0x973f0a62
+ 0x5dea255e 0x916925c0 0xc9578efa 0x3ca7eb07
+ 0x36c02e4b 0x89cfcaa3 0x641b07ad 0xf9e7197d
+ 0xdbda750c 0x447f1191 0x690f7c39 0xd7e9a602
+ 0x6edd8896 0x2b03daad 0xbd288f1e 0x7f70057e
+ 0xc8567673 0xaf74fac0 0x37e31aea 0xd992d754
+ 0xe8211c22 0x3eaed525 0x88fc8ef2 0x2f41b02a
+ 0xf3c07f7a 0x3777c91d 0x8c3ed230 0x82c64da4
+ 0xdeff0362 0x2768503b 0xcdbaf18e 0x9a45ccca
+ 0xe92fd6ad 0x72a71f75 0xc5bd6f66 0xbeb4d59a
+ 0xe99415ab 0xf7dd10c5 0x0db15260 0xbbac9f71
+ 0xa3e434ba 0x40fdea27 0x50eb8c40 0xba26f675
+ 0x2ce865b0 0x748ec966 0x6490f9fe 0x01dbda28
+ 0xd4dfed39 0x645fb3b4 0xcdcb9de0 0xccd7fcb1
+ 0xd0dabcac 0x60fd0fbd 0x168d9289 0x270ecd39
+ 0xe1ca48ec 0xd242edb6 0x95ba25a0 0x34ef7dc9
+ 0x39b20624 0x4aab3814 0xf6fffa0c 0xe6f18c9b
+ 0xc579ea88 0x3c29d3cc 0x15358dc8 0xe2ca0595
+ 0x067a5f59 0x98ac44bc 0xf92ecfdf 0x2a8f2847
+ 0xc7098327 0xf770c58d 0x65247164 0x2356f75b
+ 0xe38ee36c 0x19bc57bd 0xd1432cf8 0x4c343d9a
+ 0x800294b0 0x41906df6 0x211fb5c3 0x13d372ca
+ 0x8649cb8c 0x54a6908c 0x12b21839 0x188da49d
+ 0xf026020b 0x9dca39f3 0x1b85ad7f 0xe16f849f
+ 0xc74d6d14 0x1542b72e 0xe2e21a4f 0x13c01264
+ 0x1af57985 0x15d69f66 0xf0475b50 0x791db250
+ 0x16c4cd65 0x6aa3172e 0x50627731 0xc050f139
+ 0x8690135f 0x6b2d53f5 0xbea8c582 0x770e5dc3
+ 0xc6f1e36f 0x532b5b3d 0x5f513746 0x16a84ad7
+ 0x1d429215 0x84b0905f 0x98a47e1b 0xc8b47605
+ 0xf67fc56b 0x862e5696 0xeaebb6c7 0x2cd4dd80
+ 0x7a2345d0 0x89f02a31 0x757d6bfa 0xe1532bd7
+ 0x0eaea9e2 0x4a00dea0 0x54414e43 0xf1b723b7
+ 0x84b589bb 0x17b823cf 0x885e8430 0xc658beb3
+ 0x7251da37 0x9c6c0c94 0xd6237fde 0x7526c254
+ 0x7abe9c40 0xc815aa39 0x5c2359f8 0xd2ccb88a
+ 0xd72c3593 0xb5bac7f5 0x500d5980 0x63d1e5d6
+ 0x43f2fd4b 0xd4e7a58b 0x682c83c0 0x372647da
+ 0x897844b5 0xc8f43767 0x52c95bd9 0xb134d1e1
+ 0xf4dcf340 0x0418a91f 0xd5f53498 0x8960aa3b
+ 0x559e959d 0xc9465034 0x92f87c38 0x030bad59
+ 0x535a65f3 0x2a77f8e5 0xdfa3bb3e 0x1cfb0e7b
+ 0x745c3e85 0x4adb107f 0xe0ad43e6 0x2d2d7110
+ 0x1d2f4281 0x2eba0483 0xf1741ce3 0x872c33d7
+ 0xf43039d9 0xfe974a77 0x5bdb65de 0xa9ae81cf
+ 0xd950f31d 0x4f9dba1d 0x86c23a69 0x091cf111
+ 0xe658a751 0x84a91276 0xcd95d552 0x28e6ca41
+ 0x49f25055 0x63d4b350 0x5bcd4eb4 0xca30011f
+ 0x80c53e84 0x09bd4736 0xbaab15c7 0x240a5c91
+ 0xc78d09a4 0xe65699e7 0xa53f862a 0x4dab9d76
+ 0xfa9a9fc3 0x59603e35 0x2ac717ca 0x46b604d5
+ 0x6c3f7387 0x8b036d97 0xf2e656e8 0x3134f9fa
+ 0x07e4c866 0x5ffe4c6b 0x0b66f7d4 0xf70ec6ae
+ 0x70a34f65 0x5b899964 0xfa6d75c8 0x1201342b
+ 0x6a97079e 0x265e17b2 0x68c65a50 0xff89ec35
+ 0x1dd400fe 0x442463d3 0x28255bc7 0x0b59c045
+ 0x3184409c 0x22149a93 0x46c4e731 0x79f055dd
+ 0x37f63a7e 0x7e756b2f 0x215965e0 0x50d6830e
+ 0xecd76722 0x7ccf6440 0x7f35066a 0x6ae5b23d
+ 0xf1b3d97b 0xc10fb8f4 0x1dc8a180 0x560fde50
+ 0xc309b2d5 0x67f045a3 0x1c9b5b82 0x5a58d04e
+ 0x1605cbe6 0xb39d46e7 0xfc73771c 0xb27cad4e
+ 0xb11e103c 0xfcf832c7 0xa445f737 0x63704126
+ 0x542bdf70 0x4a134996 0xdfbbb48a 0xd46b0c8a
+ 0x658504f0 0xff3a73cf 0xd6a37646 0xc76bd82d
+ 0x7f590e8b 0x45168edc 0xbc980f1e 0xb74cbd25
+ 0x8ed51cfd 0x42e86550 0x098d3dca 0xa1c667fc
+ 0x4a1cf2fe 0x6dac04c6 0x0c06311a 0x56c5ee6b
+ 0xae2fef37 0x3077ed34 0xed2b3c58 0x704796bd
+ 0x8d4b9dd7 0x58e93741 0x3d954ff6 0xdd2514b7
+ 0x4bd6d974 0xd6e0f1c5 0xcd38a25f 0xa5315745
+ 0x982505f2 0x16c78771 0xf03bf442 0x8433c49e
+ 0x822b13a7 0x5e52a287 0x3e837cc4 0xf5246300
+ 0x62235c2a 0x4286917f 0x92694b91 0xc149428b
+ 0xcee47250 0x1073ca49 0xadfe26e0 0x39b7b1bf
+ 0x0980b264 0x460e0f79 0xb747c221 0xd2280e13
+ 0x6ebaae7f 0xbf5e4fe1 0xd83a06ae 0x15607146
+ 0x9f80aee5 0x9d3d1ea1 0x3ac75973 0xbce15424
+ 0xd3afad28 0x60b00359 0x15b1f6a2 0x860dfc81
+ 0x3a3aced8 0x17e60cf4 0x628de10b 0x6226cf18
+ 0x94aac94b 0x04e89e23 0xd647af9e 0x34fac1a0
+ 0x82107a58 0x5ff06089 0xed899a38 0xa95fc727
+ 0xfed5f0e1 0xfe6db6fb 0x495cc0da 0xa36d9c65
+ 0x9ae386d3 0x091791a6 0xca9619dd 0xd1b1681b
+ 0x283ede9d 0x54684259 0xdc0ab403 0xabf2d823
+ 0xf2705407 0x48857264 0x5a49666d 0x8d73c4cc
+ 0xc6d6c23b 0x924b2fc1 0xbde8db0e 0x6be302a5
+ 0x13d38cee 0xab9c5a5b 0x6e3f151d 0xc68ebac7
+ 0xcab34c09 0xdd0b5340 0xd7599b20 0x5c05e5fd
+ 0x58975ebd 0x253b9809 0x90044065 0xa34a0b9a
+ 0x7b98fa31 0xba00d0ca 0xbda6fa17 0x97937eb1
+ 0x43ab04a0 0xa85e1fa3 0xe732c720 0x43113659
+ 0x80e21c8c 0xc1593d8c 0x5304dbb0 0xcdb37507
+ 0x99895f48 0xc1018047 0xeaab54ed 0xd5326d76
+ 0xc1371a9c 0xcfd263bb 0xf9ecddc0 0x2381b427
+ 0xac78b897 0x46bd1bc4 0x0b7f5dfa 0xe55ac354
+ 0xd98b29e1 0x7fb53225 0xadf7fd1d 0xe7f42f6c
+ 0xe42b58fa 0x31ba8f85 0xea3d049e 0xacfac52b
+ 0xa50181c1 0xae6a0de6 0x16cf1122 0xa5aff99f
+ 0x9d1102c1 0x10f11ca3 0xabfb8005 0x9911353f
+ 0xbb430261 0x81c1400d 0xe01c0343 0x038b2e46
+ 0x3f919f9d 0xc0e1c884 0xde6272fa 0xc25d6ea2
+ 0x72e18fb7 0x88b8b150 0x8e85cd62 0xf0e1d37a
+ 0x96ef1ce2 0xe32c8193 0x1001ff2d 0x9964ec56
+ 0xbe8aaf70 0x1a416fea 0x1eb92b2a 0xa3578712
+ 0x9504cab3 0x77e975ba 0xc491748c 0x3080c466
+ 0xc8418a02 0xf44d7998 0x77051bcc 0xff646682
+ 0x6082eb7f 0x2886a8f3 0x88315209 0xa7b9fab0
+ 0x6f6c2b63 0x2aeb4634 0x809011a2 0x2df48429
+ 0xcb39f8a6 0x6b879cb1 0xa7b47618 0x09b8666d
+ 0x706ab210 0x0864689c 0xd1ca3fd0 0x69c1e584
+ 0x5212526e 0xe1a9c5ef 0x5685d88b 0x5382bdbc
+ 0xf8d5bc5b 0x8e8ded9d 0xc8cc93c5 0xe1e226f0
+ 0xd2c17da9 0x23cd104c 0x4362ff2e 0x88a7a9c5
+ 0x8a2e8873 0xd0581d74 0xfa1d8084 0xa9829395
+ 0x31a382e8 0xf423acba 0xbd436f3e 0x00ed9514
+ 0x964d6ea8 0x45e530cd 0x7b067f2d 0xe758fa63
+ 0x82767a73 0xa5e5d959 0x83adda38 0xca815b70
+ 0xca2eb490 0x879da759 0x3af36316 0x1c398e43
+ 0xb7033303 0xde77c60d 0xa0e83068 0xa072c077
+ 0xd038adcc 0x979aa6f3 0x4ff53908 0x1fcdb043
+ 0x83ccc713 0x38bb8a83 0x185cb8be 0x32594da1
+ 0xb5771673 0x9b371c9b 0x71554d0c 0x353452e0
+ 0xeb17922f 0x86f610e5 0x219706c5 0xc2516c79
+ 0xd9f1e5a5 0x4e71dd96 0x19acd081 0xcc9e8fb7
+ 0x3cdca52d 0xa8eaf0b7 0x677a8883 0x29afcfeb
+ 0xbe65bf18 0x578d900e 0xce1f20b0 0xc0464b95
+ 0xd8a7b365 0x153ca5f8 0x338f4440 0x725fb123
+ 0x0266fe31 0x20afb681 0x6ad3e79a 0x4b0fde5a
+ 0xd482ceef 0xfbebb20d 0x9ba0e25f 0xad5e0225
+ 0xb8a55ac3 0xa1823693 0x1ec05e62 0x5f0bc17f
+ 0xd45315c1 0x581d4f7c 0x71d0fc2e 0x7ab28236
+ 0x2058473c 0x59778cad 0xa31250c4 0xf5ee4b70
+ 0x0182f25e 0x093d224c 0xc0e2a624 0xdef1a681
+ 0xc3ac2477 0x684485dc 0x248b6733 0x2154c4d0
+ 0x48125445 0xdfcc6d53 0x98648e66 0xad47ff70
+ 0x98de0ea0 0x705b6663 0x585c82f5 0x41fc7750
+ 0x0f9302ac 0xd84db157 0x5473b3af 0x47fc75e1
+ 0xfd70ad9f 0xf8ac1ad3 0x2d44d472 0xd2efebac
+ 0xc012bb8c 0xaca62095 0xb2909db6 0x71f0cd19
+ 0x10f22608 0x7d2bc553 0x6a422ca4 0x5d8ca05e
+ 0xbe2c2447 0xc6c7e0bf 0xa497d984 0xc647d81a
+ 0xcbedee3d 0xf32ffe2c 0x6162e640 0x41f69600
+ 0x91244338 0x95609997 0x8d238396 0x66e7a884
+ 0xb12cdbc7 0x47161675 0x51ecf757 0x3c82038d
+ 0x031421db 0xe2ef93ea 0xa68873df 0x039e0c25
+ 0x5572321c 0x9df1728d 0xe6ed57c0 0x57a039f2
+ 0xe31b3be2 0x55715ed2 0x59d600a5 0x3ba7f734
+ 0xa429f7da 0xff7ddad3 0x1ce287d9 0xbd308541
+ 0xa6b20324 0x1fd4c741 0x9244413b 0xd914325e
+ 0x486a10c3 0xaba191f0 0x09cd2579 0x6fbd86d3
+ 0xf9eaabea 0xcbc6a11f 0xc97eff2e 0x604949d5
+ 0x73208a00 0xc5640d64 0x75fd1830 0xea2841b2
+ 0x3efcac7d 0x3f2be687 0x9737b5a5 0x7846b723
+ 0xfeb5d90f 0xbf9b347e 0x94629b88 0x0e0bd993
+ 0xeaa3a0e6 0x92758d2f 0x06b4a92c 0xee31d291
+ 0xcf91699e 0x39b5a732 0xb63b660a 0xc5ffeaa1
+ 0x90833668 0xd1995d7a 0x84030c26 0x62b1ca49
+ 0x7efa5144 0xe7288b77 0x6230a776 0x1be6a7db
+ 0xd2a0bc0e 0xfb36d845 0x261fb4eb 0x8f8fc434
+ 0xfb833fb4 0xc7474543 0xda6c6a88 0x1659bb4c
+ 0x9194a11d 0x071154f5 0x82d51f58 0x63a2f751
+ 0x46f7a823 0x04974444 0x360cdcdc 0x7452e132
+ 0xc9a98443 0xd03ad3ab 0x30dc5c84 0xd3928173
+ 0x38b6e6e1 0x0cda2c1e 0x4cd9d2bd 0x59cfadb4
+ 0xbf73f35e 0xfed1a2e3 0x7c7f7fbd 0x9b5129a3
+ 0x780f877b 0x2104f056 0x90bdc3a4 0x9ee71bf4
+ 0xd28d3305 0xad550ee2 0x3c8f4067 0xfa0dd7e5
+ 0xd625f145 0x3b5cd69e 0x645db568 0x5e56c683
+ 0xfb1f1f24 0x2bfe72c3 0x0cdb2809 0x9404915b
+ 0x120d6624 0xcfe55309 0x0b978365 0xb4a25446
+ 0xb26e8767 0x83c6e6a8 0xaebacb46 0xd79ed05f
+ 0xd4d07268 0x1bb3faf1 0xde8dbf0f 0x2e7ba152
+ 0xabc0ff05 0x6ca54fc8 0x51acd5dc 0x65a18671
+ 0xa619f93a 0xa84535c1 0xa0ede59b 0x6bd55a4e
+ 0x5aba8fb8 0x01cc90e7 0xc3eea3cd 0x0f503e9b
+ 0xad697d5d 0x6021cacf 0x70dd0dec 0x11d7617f
+ 0x19e6864a 0x6b252ab4 0x6820dba3 0x9db53d55
+ 0x1108f4b2 0x71aeae7e 0xdff9a4fa 0xa724e0b9
+ 0xefe50832 0x91ea4d28 0x4f02d339 0x15e0212b
+ 0x2c725507 0x3de817ac 0x4fcbd836 0xf9484b90
+ 0xeb9ebf31 0xcfd90e4d 0xd3d6a071 0x3dff27c3
+ 0xb891858e 0x99daaeeb 0x3dc5528e 0xb2fea196
+ 0x2724ae08 0x6c5845a7 0x184faafc 0x44446f10
+ 0xe9d1537d 0xb0933101 0x9229e352 0x4f426c82
+ 0x98147850 0xca22c0fb 0x4d414090 0x981ac8f9
+ 0xb8d034af 0x6b8aa278 0x6508c7b7 0x6293fe73
+ 0x66f15617 0x0679cf83 0x6a58257d 0x4deae251
+ 0x6e19dc6e 0x899db947 0xcb261cce 0x9c8d3929
+ 0x64a097e4 0x38acf6ab 0x07beeeb0 0x9ba17f04
+ 0x6897fa21 0x1445cb4d 0x6d79f51a 0x83661214
+ 0x812f8cb4 0x73a15a75 0x5d9edf24 0x490b66b2
+ 0xf503c382 0x9a7b92bc 0x8367b4d9 0x8df42ea5
+ 0x790dc812 0xe8a51197 0x1f9ec3e8 0x0fe9d551
+ 0x29facbeb 0xaaa131a7 0xc0ce9784 0x3f0b2412
+ 0x63d56d18 0xe2ca7aef 0x35f66550 0xe49095c1
+ 0x8d8531f1 0x815ca696 0x18f31b28 0x39a102bf
+ 0x96bd3241 0x1b79f65f 0xb5750fc0 0x7e41b1aa
+ 0xe7c7e0f6 0x294a848b 0x0d90877b 0x87c42915
+ 0xd5839e6e 0x00635ed9 0xc51b8d91 0x34e60826
+ 0x08082536 0x3550eed6 0xc78b127e 0x2f428ec3
+ 0xaf95830e 0xb0c8fb6c 0xc0b5e989 0xb45d0020
+ 0xce6466e0 0x8e244ba2 0x17ef4563 0x2c74b037
+ 0x8d15449e 0xa96ad89d 0x0672ebbc 0xf5a037f4
+ 0x633b2cd2 0x82d1cb6a 0xeae7ab21 0xfe156394
+ 0xb223326d 0x6bf37192 0x349934ac 0x747e4995
+ 0xfff3f992 0xe916d599 0x95917b72 0xd3e810ad
+ 0x704231a5 0x041ed2f0 0x32cca85f 0x2ceb1663
+ 0x80d3e7c7 0x901d33a6 0x18a99b15 0x21b50c44
+ 0x295e5a16 0xceab5147 0x503b6e34 0x732a4fdf
+ 0xb6b38684 0xa1317fff 0xb76492ef 0x88e7eda4
+ 0x5ccde55d 0x7448f240 0x12d3436b 0x6a152377
+ 0xff0b0448 0x8b124b95 0x55321a93 0xed4229ef
+ 0x7ea05a46 0x992eb553 0x5f2d7278 0x90dd258f
+ 0x6ecd1946 0xab971c70 0x3d341faf 0x49855465
+ 0x1973c8cf 0xb5976088 0x6640e00e 0x155dd9f3
+ 0x674285a8 0x720515e1 0x5fdffc94 0x0d3a3347
+ 0x1dbfe5ff 0x7079f37e 0x8c470652 0x46d6c1e3
+ 0x1402e1b4 0x05217695 0x67e45039 0x683ba960
+ 0x97cadd4e 0x59664501 0x4726c2a6 0x7601358b
+ 0xec77b4b9 0x66a912a0 0x8f157d86 0xa0e221ba
+ 0x3aa4bd23 0x547e9323 0xaa94772a 0x1ba6ac0c
+ 0xbed2aa6f 0x8a945e94 0xeea5c775 0xf2c66a89
+ 0x89ebde2f 0xd7b4e71c 0x6a1c8bb3 0xb9392201
+ 0xc7a2191f 0xf180c19a 0xc3446d78 0x7f5f61c8
+ 0xc6a251da 0xa27c507f 0x329133a1 0x0c951593
+ 0x344ca56a 0x329dea98 0x73112997 0x32bc47a4
+ 0xbeb18227 0xd3347aaf 0x1c481ab4 0x62606e69
+ 0xe18da26b 0x8243c025 0xfe05b066 0xc1b0c590
+ 0xd8c107ba 0x235b8c6a 0xac4fe894 0xa012810b
+ 0x5470e6de 0x6f1217ae 0xcb099ad1 0x2b03655e
+ 0x91f0b417 0xc21a1af4 0xb4a8c50e 0xa5988ed2
+ 0x7f03fa1e 0xa0658a65 0x5532c4b3 0x1fdcfcec
+ 0x17f41c26 0xd6b29efb 0x3411f331 0x1b774029
+ 0x2ee2d094 0x9f5edaab 0xc644a9f3 0xdc4cf7b1
+ 0xb6304748 0xb064cfca 0x89e4dbee 0xb1563a5e
+ 0xd370bca8 0xe6cb17d8 0xbfcacc87 0x76940250
+ 0xf2456a18 0x3c1873e4 0x0a3d7d0e 0xeb145eb9
+ 0xe88a48fb 0x9413f290 0x626e4e00 0xb234a13b
+ 0xcbf49379 0xcf600cee 0xc78891b8 0x799f8e80
+ 0xdbf4e604 0x89860862 0x04fb77db 0x0fb1bf13
+ 0x3b1aa906 0xadaf9a45 0x48526bf7 0x09d8ffb3
+ 0xce751581 0x00e35b8d 0x0549e629 0x6d3cc316
+ 0x3d8f300a 0xdcd790b5 0xde1ca316 0x737d5f31
+ 0x171b2646 0x4798a85d 0xea36f650 0xcf889098
+ 0xe4ec65b8 0x944637d3 0x019c8103 0x5fbdc21c
+ 0xa61ebe77 0x74ea95a5 0x258eb8d1 0xf8c8c4d6
+ 0x9a1edc66 0x9118b309 0x639ae9b5 0xd0c40735
+ 0xc6ddec32 0x36d26a75 0x86018c99 0xe8bf66df
+ 0xf345dba0 0x780670a3 0xe34e60fd 0x733ad4ba
+ 0x2ef04d54 0xb1b9c41f 0x84cca1c2 0xaa09279b
+ 0x34797d41 0xb93d4c70 0x919ce970 0xd0d6ec5e
+ 0xdc70cc95 0xd89f4680 0x458cfd33 0xc257784b
+ 0x29ec9364 0x8e717417 0x6d9732df 0xa3658440
+ 0x8574b5c6 0xa58ebb8c 0x81bc4dea 0x1f396663
+ 0x361dfd98 0x20b35a46 0x886a7e4c 0x69f0a1c5
+ 0xd0b7de5f 0xbbc08761 0xa1cef991 0x084a8ea2
+ 0x4df68c5b 0xb84b4b2e 0xd4bf1770 0x94b4f7c7
+ 0x9906a752 0x878c7f1f 0x385b5a5e 0x99147c87
+ 0x97c54a35 0xbacb57d4 0xf85f9733 0xb5d2c83f
+ 0x4405f9f5 0x020260b5 0x5c0a8556 0xb623ad79
+ 0x8d42a6a3 0x35ae5806 0x2c28a60d 0xa0200ee8
+ 0xed9e0ece 0xb7e0442a 0x1ddf0e2b 0x26ceec5d
+ 0xda397b2c 0xb073d9a2 0x9d856bbd 0x06e35ca8
+ 0x6296193e 0x292dee18 0xf5a9bd7a 0xb62fe73f
+ 0x95a8775f 0x1efc0fd0 0xf3338af4 0x06ccbe78
+ 0xafb3f669 0xd9f7fe16 0x09beed63 0xa2f0bb3e
+ 0x02f5c52f 0x24aee650 0xf715039b 0x3f566d89
+ 0xd575429b 0x9d40207d 0xa89c7de9 0xde5157f0
+ 0xd79025ae 0x4259c4b6 0x61e86217 0x6d2e3273
+ 0x57b5c99d 0xa18edb02 0xf5f314be 0xfa58bf5f
+ 0x581e95bb 0x04967c03 0x9187d903 0xdaf34bc3
+ 0xa18e49f0 0xb7973963 0x2984967f 0x7332f94f
+ 0x57e5a8b5 0xe6e0a6f8 0xbc08c39f 0xc9e73ad8
+ 0x0ea113d8 0xa9cfdb06 0xfda1ebbb 0x1a30e9f9
+ 0x69a9029a 0x44b43320 0x04182d93 0x00220972
+ 0xa7f984c5 0xb4eeae8a 0x11718517 0x06e70840
+ 0xb3091fe5 0x099ccb1a 0xac3df88c 0xa8bd0ca3
+ 0xa202bbc0 0x19979cf1 0x8656c385 0x139abf7b
+ 0xae298ea4 0xab9481ae 0xe08e2c38 0x27967dab
+ 0x1108054c 0x1ba0d3c5 0x8a0fb923 0x9c54f682
+ 0x5f363a46 0xec564b34 0x8d53c918 0x47f39642
+ 0x3fd68743 0x197f16cc 0x2b03d11c 0xcc574d53
+ 0x8b2d1aa3 0xd403c5b0 0xce21d3a6 0x57c88abe
+ 0x56d6b12b 0x204f9ac8 0xfd44c338 0x18417de6
+ 0x5582f0bf 0x7ea9d04f 0x7bdee65d 0x9fe3f5b5
+ 0xa14edd82 0x8301f6ba 0x24bc737a 0x5c6e71a8
+ 0xdb0d7fc2 0x243b6e99 0x3941f113 0xcaaa3674
+ 0x1b25b686 0xfb219a33 0x1b122757 0x27298223
+ 0x44cbb8ad 0xed4e6ef9 0xae338c2d 0xa8d231ee
+ 0x9bc2d8f3 0xcecd4d27 0xe8ba9908 0x9a106344
+ 0xbdf27147 0x0c547009 0x46b16833 0xd89b0690
+ 0x4b742f40 0x733d4cd5 0x1abb6f77 0x803f40df
+ 0xf8d909bb 0x8fa6a921 0x08966531 0xdf093174
+ 0xc7ee92c8 0x4272612d 0x149f8242 0xf8c07ec3
+ 0x99259781 0x8bf3f9c0 0x09d6b679 0x19a1968f
+ 0x735b197e 0xa98c913f 0x3e208a56 0x59b2b40b
+ 0x0ed212ed 0xfc92d02a 0xe9b1b441 0x1429fc3c
+ 0x8a6fb38c 0x6235d73e 0x82f5aca8 0x9ebb490a
+ 0x718fed05 0xee355cdc 0xf34bbc8e 0xcfde74ac
+ 0x5c267a70 0x30b66c7f 0x9a655781 0x1d354268
+ 0xd0debf01 0x71798948 0x4542b707 0x66c02ecf
+ 0x49763e11 0xa02f170b 0xbcf30ee9 0xba9bbfec
+ 0x6d915d18 0xcadd484f 0x8eadbd10 0x91463818
+ 0xe8add34f 0x55620c30 0x14d47fa5 0x63c2a25f
+ 0x7213f2f4 0x6d96a516 0xf10f4ed1 0x9825aeac
+ 0xe9ca9b8a 0x4bb0e2aa 0x957f8851 0x1a41de29
+ 0xa0039e6c 0x3ec63393 0x66b6ac8a 0x2992d983
+ 0x2d73caa4 0xb0ae06c2 0xa4008915 0x2ba7050d
+ 0x6d9e01e6 0x908f316f 0x3f17dabb 0x8c86b0e3
+ 0x89fcebf8 0xbada4307 0x0f6e9f6f 0x07f36992
+ 0x1a82520e 0x728f11a9 0x418aa9b7 0xc57f51d7
+ 0xcffa1cd0 0xf9f6d902 0xdf22329a 0x4ac48293
+ 0x37326e23 0xbb39c187 0xc9086dfe 0x1347e4f8
+ 0x7ae88ecb 0xc280a07f 0x7f0a6b0a 0x57cff37d
+ 0x2dfd629d 0x5a8a444d 0x934bcafb 0x593b6a3a
+ 0x9c62c1ca 0x0ecdb2dc 0xb4c2fd82 0x2c19c0ab
+ 0x26acf079 0x71aa1041 0x8aeb2595 0xed90f704
+ 0x7d68f5c5 0x624429d5 0xefd0d147 0xc8682f79
+ 0xfe7e9cc0 0xaee6c970 0x33e9231e 0x4720df4d
+ 0x6a3f6428 0x463b676f 0x71960ee6 0xc684d974
+ 0x9f01a6d2 0x728cbec7 0x2e20d715 0x172a4a11
+ 0x4153ad1e 0xb1f36e53 0xc277f818 0x94ac6d39
+ 0x502f91d8 0x3028b1ee 0x48390347 0x45a8b5af
+ 0x2cb8095f 0x063cbe4a 0x07a53b3b 0xcfd08c80
+ 0x81679803 0x9fa4726a 0xa682f4c8 0x4d90e8bf
+ >;
compatible = "intel,irq-router";
intel,pirq-config = "ibase";
intel,ibase-offset = <0x50>;
+ intel,actl-addr = <0>;
intel,pirq-link = <8 8>;
intel,pirq-mask = <0xdee0>;
intel,pirq-routing = <
microcode {
update@0 {
-#include "microcode/m0130673322.dtsi"
+#include "microcode/m0130673325.dtsi"
};
update@1 {
-#include "microcode/m0130679901.dtsi"
+#include "microcode/m0130679907.dtsi"
};
};
irq-router {
compatible = "intel,irq-router";
intel,pirq-config = "pci";
+ intel,actl-8bit;
+ intel,actl-addr = <0x44>;
intel,pirq-link = <0x60 8>;
intel,pirq-mask = <0x0e40>;
intel,pirq-routing = <
+++ /dev/null
-/*
- * From coreboot
- *
- * Copyright (C) 2004 SUSE LINUX AG
- * Copyright (C) 2004 Nick Barker
- * Copyright (C) 2008-2009 coresystems GmbH
- * (Written by Stefan Reinauer <stepan@coresystems.de>)
- *
- * SPDX-License-Identifier: GPL-2.0
- */
-
-#ifndef __ASM_ACPI_H
-#define __ASM_ACPI_H
-
-#define RSDP_SIG "RSD PTR " /* RSDT pointer signature */
-#define ACPI_TABLE_CREATOR "U-BootAC" /* Must be exactly 8 bytes long! */
-#define OEM_ID "U-Boot" /* Must be exactly 6 bytes long! */
-#define ASLC "U-Bo" /* Must be exactly 4 bytes long! */
-
-/* 0 = S0, 1 = S1 ...*/
-int acpi_get_slp_type(void);
-void apci_set_slp_type(int type);
-
-#endif
--- /dev/null
+/*
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/arch/x86/acpi/debug.asl
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/* POST register region */
+OperationRegion(X80, SystemIO, 0x80, 1)
+Field(X80, ByteAcc, NoLock, Preserve)
+{
+ P80, 8
+}
+
+/* Legacy serial port register region */
+OperationRegion(CREG, SystemIO, 0x3F8, 8)
+Field(CREG, ByteAcc, NoLock, Preserve)
+{
+ CDAT, 8,
+ CDLM, 8,
+ , 8,
+ CLCR, 8,
+ CMCR, 8,
+ CLSR, 8
+}
+
+/* DINI - Initialize the serial port to 115200 8-N-1 */
+Method(DINI)
+{
+ Store(0x83, CLCR)
+ Store(0x01, CDAT) /* 115200 baud (low) */
+ Store(0x00, CDLM) /* 115200 baud (high) */
+ Store(0x03, CLCR) /* word=8 stop=1 parity=none */
+ Store(0x03, CMCR) /* DTR=1 RTS=1 out1/2=Off loop=Off */
+ Store(0x00, CDLM) /* turn off interrupts */
+}
+
+/* THRE - Wait for serial port transmitter holding register to go empty */
+Method(THRE)
+{
+ And(CLSR, 0x20, Local0)
+ While (LEqual(Local0, Zero)) {
+ And(CLSR, 0x20, Local0)
+ }
+}
+
+/* OUTX - Send a single raw character */
+Method(OUTX, 1)
+{
+ THRE()
+ Store(Arg0, CDAT)
+}
+
+/* OUTC - Send a single character, expanding LF into CR/LF */
+Method(OUTC, 1)
+{
+ If (LEqual(Arg0, 0x0a)) {
+ OUTX(0x0d)
+ }
+ OUTX(Arg0)
+}
+
+/* DBGN - Send a single hex nibble */
+Method(DBGN, 1)
+{
+ And(Arg0, 0x0f, Local0)
+ If (LLess(Local0, 10)) {
+ Add(Local0, 0x30, Local0)
+ } Else {
+ Add(Local0, 0x37, Local0)
+ }
+ OUTC(Local0)
+}
+
+/* DBGB - Send a hex byte */
+Method(DBGB, 1)
+{
+ ShiftRight(Arg0, 4, Local0)
+ DBGN(Local0)
+ DBGN(Arg0)
+}
+
+/* DBGW - Send a hex word */
+Method(DBGW, 1)
+{
+ ShiftRight(Arg0, 8, Local0)
+ DBGB(Local0)
+ DBGB(Arg0)
+}
+
+/* DBGD - Send a hex dword */
+Method(DBGD, 1)
+{
+ ShiftRight(Arg0, 16, Local0)
+ DBGW(Local0)
+ DBGW(Arg0)
+}
+
+/* Get a char from a string */
+Method(GETC, 2)
+{
+ CreateByteField(Arg0, Arg1, DBGC)
+ Return (DBGC)
+}
+
+/* DBGO - Send either a string or an integer */
+Method(DBGO, 1, Serialized)
+{
+ If (LEqual(ObjectType(Arg0), 1)) {
+ If (LGreater(Arg0, 0xffff)) {
+ DBGD(Arg0)
+ } Else {
+ If (LGreater(Arg0, 0xff)) {
+ DBGW(Arg0)
+ } Else {
+ DBGB(Arg0)
+ }
+ }
+ } Else {
+ Name(BDBG, Buffer(80) {})
+ Store(Arg0, BDBG)
+ Store(0, Local1)
+ While (One) {
+ Store(GETC(BDBG, Local1), Local0)
+ If (LEqual(Local0, 0)) {
+ Return (Zero)
+ }
+ OUTC(Local0)
+ Increment(Local1)
+ }
+ }
+
+ Return (Zero)
+}
--- /dev/null
+/*
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/arch/x86/acpi/globutil.asl
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+Method(MIN, 2)
+{
+ If (LLess(Arg0, Arg1)) {
+ Return (Arg0)
+ } Else {
+ Return (Arg1)
+ }
+}
+
+Method(SLEN, 1)
+{
+ Store(Arg0, Local0)
+ Return (Sizeof(Local0))
+}
+
+Method(S2BF, 1, Serialized)
+{
+ Add(SLEN(Arg0), One, Local0)
+ Name(BUFF, Buffer(Local0) {})
+ Store(Arg0, BUFF)
+ Return (BUFF)
+}
+
+/*
+ * SCMP - Strong string compare
+ *
+ * Checks both length and content
+ */
+Method(SCMP, 2)
+{
+ Store(S2BF(Arg0), Local0)
+ Store(S2BF(Arg1), Local1)
+ Store(Zero, Local4)
+ Store(SLEN(Arg0), Local5)
+ Store(SLEN(Arg1), Local6)
+ Store(MIN(Local5, Local6), Local7)
+
+ While (LLess(Local4, Local7)) {
+ Store(Derefof(Index(Local0, Local4)), Local2)
+ Store(Derefof(Index(Local1, Local4)), Local3)
+ If (LGreater(Local2, Local3)) {
+ Return (One)
+ } Else {
+ If (LLess(Local2, Local3)) {
+ Return (Ones)
+ }
+ }
+ Increment(Local4)
+ }
+
+ If (LLess(Local4, Local5)) {
+ Return (One)
+ } Else {
+ If (LLess(Local4, Local6)) {
+ Return (Ones)
+ } Else {
+ Return (Zero)
+ }
+ }
+}
+
+/*
+ * WCMP - Weak string compare
+ *
+ * Checks to find Arg1 at beginning of Arg0.
+ * Fails if length(Arg0) < length(Arg1).
+ * Returns 0 on fail, 1 on pass.
+ */
+Method(WCMP, 2)
+{
+ Store(S2BF(Arg0), Local0)
+ Store(S2BF(Arg1), Local1)
+ If (LLess(SLEN(Arg0), SLEN(Arg1))) {
+ Return (Zero)
+ }
+ Store(Zero, Local2)
+ Store(SLEN(Arg1), Local3)
+
+ While (LLess(Local2, Local3)) {
+ If (LNotEqual(Derefof(Index(Local0, Local2)),
+ Derefof(Index(Local1, Local2)))) {
+ Return (Zero)
+ }
+ Increment(Local2)
+ }
+
+ Return (One)
+}
+
+/*
+ * I2BM - Returns Bit Map
+ *
+ * Arg0 = IRQ Number (0-15)
+ */
+Method(I2BM, 1)
+{
+ Store(0, Local0)
+ If (LNotEqual(Arg0, 0)) {
+ Store(1, Local1)
+ ShiftLeft(Local1, Arg0, Local0)
+ }
+
+ Return (Local0)
+}
--- /dev/null
+/*
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/arch/x86/acpi/statdef.asl
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/* Status and notification definitions */
+
+#define STA_MISSING 0x00
+#define STA_PRESENT 0x01
+#define STA_ENABLED 0x03
+#define STA_DISABLED 0x09
+#define STA_INVISIBLE 0x0b
+#define STA_UNAVAILABLE 0x0d
+#define STA_VISIBLE 0x0f
+
+/* SMBus status codes */
+#define SMB_OK 0x00
+#define SMB_UNKNOWN_FAIL 0x07
+#define SMB_DEV_ADDR_NAK 0x10
+#define SMB_DEVICE_ERROR 0x11
+#define SMB_DEV_CMD_DENIED 0x12
+#define SMB_UNKNOWN_ERR 0x13
+#define SMB_DEV_ACC_DENIED 0x17
+#define SMB_TIMEOUT 0x18
+#define SMB_HST_UNSUPP_PROTOCOL 0x19
+#define SMB_BUSY 0x1a
+#define SMB_PKT_CHK_ERROR 0x1f
+
+/* Device Object Notification Values */
+#define NOTIFY_BUS_CHECK 0x00
+#define NOTIFY_DEVICE_CHECK 0x01
+#define NOTIFY_DEVICE_WAKE 0x02
+#define NOTIFY_EJECT_REQUEST 0x03
+#define NOTIFY_DEVICE_CHECK_JR 0x04
+#define NOTIFY_FREQUENCY_ERROR 0x05
+#define NOTIFY_BUS_MODE 0x06
+#define NOTIFY_POWER_FAULT 0x07
+#define NOTIFY_CAPABILITIES 0x08
+#define NOTIFY_PLD_CHECK 0x09
+#define NOTIFY_SLIT_UPDATE 0x0b
+#define NOTIFY_SRA_UPDATE 0x0d
+
+/* Battery Device Notification Values */
+#define NOTIFY_BAT_STATUSCHG 0x80
+#define NOTIFY_BAT_INFOCHG 0x81
+#define NOTIFY_BAT_MAINTDATA 0x82
+
+/* Power Source Object Notification Values */
+#define NOTIFY_PWR_STATUSCHG 0x80
+#define NOTIFY_PWR_INFOCHG 0x81
+
+/* Thermal Zone Object Notification Values */
+#define NOTIFY_TZ_STATUSCHG 0x80
+#define NOTIFY_TZ_TRIPPTCHG 0x81
+#define NOTIFY_TZ_DEVLISTCHG 0x82
+#define NOTIFY_TZ_RELTBLCHG 0x83
+
+/* Power Button Notification Values */
+#define NOTIFY_POWER_BUTTON 0x80
+
+/* Sleep Button Notification Values */
+#define NOTIFY_SLEEP_BUTTON 0x80
+
+/* Lid Notification Values */
+#define NOTIFY_LID_STATUSCHG 0x80
+
+/* Processor Device Notification Values */
+#define NOTIFY_CPU_PPCCHG 0x80
+#define NOTIFY_CPU_CSTATECHG 0x81
+#define NOTIFY_CPU_THROTLCHG 0x82
+
+/* User Presence Device Notification Values */
+#define NOTIFY_USR_PRESNCECHG 0x80
+
+/* Ambient Light Sensor Notification Values */
+#define NOTIFY_ALS_ILLUMCHG 0x80
+#define NOTIFY_ALS_COLORTMPCHG 0x81
+#define NOTIFY_ALS_RESPCHG 0x82
* Based on acpi.c from coreboot
*
* Copyright (C) 2015, Saket Sinha <saket.sinha89@gmail.com>
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
-#include <common.h>
-#include <malloc.h>
-#include <asm/post.h>
-#include <linux/string.h>
-
-#define RSDP_SIG "RSD PTR " /* RSDT pointer signature */
-#define ACPI_TABLE_CREATOR "UBOOT " /* Must be 8 bytes long! */
-#define OEM_ID "UBOOT " /* Must be 6 bytes long! */
-#define ASLC "INTL" /* Must be 4 bytes long! */
-
-#define OEM_REVISION 42
-#define ASL_COMPILER_REVISION 42
-
-/* IO ports to generate SMIs */
-#define APM_CNT 0xb2
-#define APM_CNT_CST_CONTROL 0x85
-#define APM_CNT_PST_CONTROL 0x80
-#define APM_CNT_ACPI_DISABLE 0x1e
-#define APM_CNT_ACPI_ENABLE 0xe1
-#define APM_CNT_MBI_UPDATE 0xeb
-#define APM_CNT_GNVS_UPDATE 0xea
-#define APM_CNT_FINALIZE 0xcb
-#define APM_CNT_LEGACY 0xcc
-#define APM_ST 0xb3
-
-/* Multiple Processor Interrupts */
-#define MP_IRQ_POLARITY_DEFAULT 0x0
-#define MP_IRQ_POLARITY_HIGH 0x1
-#define MP_IRQ_POLARITY_LOW 0x3
-#define MP_IRQ_POLARITY_MASK 0x3
-#define MP_IRQ_TRIGGER_DEFAULT 0x0
-#define MP_IRQ_TRIGGER_EDGE 0x4
-#define MP_IRQ_TRIGGER_LEVEL 0xc
-#define MP_IRQ_TRIGGER_MASK 0xc
-
-/*
- * Interrupt assigned for SCI in order to
- * create the ACPI MADT IRQ override entry
- */
-#define ACTL 0x00
-#define SCIS_MASK 0x07
-#define SCIS_IRQ9 0x00
-#define SCIS_IRQ10 0x01
-#define SCIS_IRQ11 0x02
-#define SCIS_IRQ20 0x04
-#define SCIS_IRQ21 0x05
-#define SCIS_IRQ22 0x06
-#define SCIS_IRQ23 0x07
-
-#define ACPI_REV_ACPI_1_0 1
-#define ACPI_REV_ACPI_2_0 1
-#define ACPI_REV_ACPI_3_0 2
-#define ACPI_REV_ACPI_4_0 3
-#define ACPI_REV_ACPI_5_0 5
+#define RSDP_SIG "RSD PTR " /* RSDP pointer signature */
+#define OEM_ID "U-BOOT" /* U-Boot */
+#define OEM_TABLE_ID "U-BOOTBL" /* U-Boot Table */
+#define ASLC_ID "INTL" /* Intel ASL Compiler */
#define ACPI_RSDP_REV_ACPI_1_0 0
#define ACPI_RSDP_REV_ACPI_2_0 2
-typedef struct acpi_gen_regaddr {
- u8 space_id; /* Address space ID */
- u8 bit_width; /* Register size in bits */
- u8 bit_offset; /* Register bit offset */
- union {
- /* Reserved in ACPI 2.0 - 2.0b */
- u8 resv;
- /* Access size in ACPI 2.0c/3.0/4.0/5.0 */
- u8 access_size;
- };
- u32 addrl; /* Register address, low 32 bits */
- u32 addrh; /* Register address, high 32 bits */
-} acpi_addr_t;
-
-
/*
* RSDP (Root System Description Pointer)
* Note: ACPI 1.0 didn't have length, xsdt_address, and ext_checksum
char signature[8]; /* RSDP signature */
u8 checksum; /* Checksum of the first 20 bytes */
char oem_id[6]; /* OEM ID */
- u8 revision; /* 0 for ACPI 1.0, 2 for ACPI 2.0/3.0/4.0 */
+ u8 revision; /* 0 for ACPI 1.0, others 2 */
u32 rsdt_address; /* Physical address of RSDT (32 bits) */
u32 length; /* Total RSDP length (incl. extended part) */
u64 xsdt_address; /* Physical address of XSDT (64 bits) */
u8 reserved[3];
};
-enum acpi_address_space_type {
- ACPI_ADDRESS_SPACE_MEMORY = 0, /* System memory */
- ACPI_ADDRESS_SPACE_IO, /* System I/O */
- ACPI_ADDRESS_SPACE_PCI, /* PCI config space */
- ACPI_ADDRESS_SPACE_EC, /* Embedded controller */
- ACPI_ADDRESS_SPACE_SMBUS, /* SMBus */
- ACPI_ADDRESS_SPACE_PCC = 0x0a, /* Platform Comm. Channel */
- ACPI_ADDRESS_SPACE_FIXED = 0x7f /* Functional fixed hardware */
-};
-
-/* functional fixed hardware */
-#define ACPI_FFIXEDHW_VENDOR_INTEL 1 /* Intel */
-#define ACPI_FFIXEDHW_CLASS_HLT 0 /* C1 Halt */
-#define ACPI_FFIXEDHW_CLASS_IO_HLT 1 /* C1 I/O then Halt */
-#define ACPI_FFIXEDHW_CLASS_MWAIT 2 /* MWAIT Native C-state */
-#define ACPI_FFIXEDHW_FLAG_HW_COORD 1 /* Hardware Coordination bit */
-#define ACPI_FFIXEDHW_FLAG_BM_STS 2 /* BM_STS avoidance bit */
-
-/* Access size definitions for Generic address structure */
-enum acpi_address_space_size {
- ACPI_ACCESS_SIZE_UNDEFINED = 0, /* Undefined (legacy reasons) */
- ACPI_ACCESS_SIZE_BYTE_ACCESS = 1,
- ACPI_ACCESS_SIZE_WORD_ACCESS = 2,
- ACPI_ACCESS_SIZE_DWORD_ACCESS = 3,
- ACPI_ACCESS_SIZE_QWORD_ACCESS = 4
-};
-
/* Generic ACPI header, provided by (almost) all tables */
-typedef struct acpi_table_header {
+struct acpi_table_header {
char signature[4]; /* ACPI signature (4 ASCII characters) */
u32 length; /* Table length in bytes (incl. header) */
u8 revision; /* Table version (not ACPI version!) */
char oem_id[6]; /* OEM identification */
char oem_table_id[8]; /* OEM table identification */
u32 oem_revision; /* OEM revision number */
- char asl_compiler_id[4]; /* ASL compiler vendor ID */
- u32 asl_compiler_revision; /* ASL compiler revision number */
-} acpi_header_t;
+ char aslc_id[4]; /* ASL compiler vendor ID */
+ u32 aslc_revision; /* ASL compiler revision number */
+};
/* A maximum number of 32 ACPI tables ought to be enough for now */
-#define MAX_ACPI_TABLES 32
+#define MAX_ACPI_TABLES 32
/* RSDT (Root System Description Table) */
struct acpi_rsdt {
u64 entry[MAX_ACPI_TABLES];
};
-/* MCFG (PCI Express MMIO config space BAR description table) */
-struct acpi_mcfg {
- struct acpi_table_header header;
- u8 reserved[8];
-};
-
-struct acpi_mcfg_mmconfig {
- u32 base_address;
- u32 base_reserved;
- u16 pci_segment_group_number;
- u8 start_bus_number;
- u8 end_bus_number;
- u8 reserved[4];
-};
-
-/* MADT (Multiple APIC Description Table) */
-struct acpi_madt {
- struct acpi_table_header header;
- u32 lapic_addr; /* Local APIC address */
- u32 flags; /* Multiple APIC flags */
-} acpi_madt_t;
-
-enum dev_scope_type {
- SCOPE_PCI_ENDPOINT = 1,
- SCOPE_PCI_SUB = 2,
- SCOPE_IOAPIC = 3,
- SCOPE_MSI_HPET = 4
+/* FADT Preferred Power Management Profile */
+enum acpi_pm_profile {
+ ACPI_PM_UNSPECIFIED = 0,
+ ACPI_PM_DESKTOP,
+ ACPI_PM_MOBILE,
+ ACPI_PM_WORKSTATION,
+ ACPI_PM_ENTERPRISE_SERVER,
+ ACPI_PM_SOHO_SERVER,
+ ACPI_PM_APPLIANCE_PC,
+ ACPI_PM_PERFORMANCE_SERVER,
+ ACPI_PM_TABLET
};
-typedef struct dev_scope {
- u8 type;
- u8 length;
- u8 reserved[2];
- u8 enumeration;
- u8 start_bus;
- struct {
- u8 dev;
- u8 fn;
- } path[0];
-} __packed dev_scope_t;
-
-/* MADT: APIC Structure Type*/
-enum acpi_apic_types {
- LOCALAPIC = 0, /* Processor local APIC */
- IOAPIC, /* I/O APIC */
- IRQSOURCEOVERRIDE, /* Interrupt source override */
- NMITYPE, /* NMI source */
- LOCALNMITYPE, /* Local APIC NMI */
- LAPICADDRESSOVERRIDE, /* Local APIC address override */
- IOSAPIC, /* I/O SAPIC */
- LOCALSAPIC, /* Local SAPIC */
- PLATFORMIRQSOURCES, /* Platform interrupt sources */
- LOCALX2SAPIC, /* Processor local x2APIC */
- LOCALX2APICNMI, /* Local x2APIC NMI */
-};
+/* FADT flags for p_lvl2_lat and p_lvl3_lat */
+#define ACPI_FADT_C2_NOT_SUPPORTED 101
+#define ACPI_FADT_C3_NOT_SUPPORTED 1001
-/* MADT: Processor Local APIC Structure */
-struct acpi_madt_lapic {
- u8 type; /* Type (0) */
- u8 length; /* Length in bytes (8) */
- u8 processor_id; /* ACPI processor ID */
- u8 apic_id; /* Local APIC ID */
- u32 flags; /* Local APIC flags */
-};
+/* FADT Boot Architecture Flags */
+#define ACPI_FADT_LEGACY_FREE 0x00
+#define ACPI_FADT_LEGACY_DEVICES (1 << 0)
+#define ACPI_FADT_8042 (1 << 1)
+#define ACPI_FADT_VGA_NOT_PRESENT (1 << 2)
+#define ACPI_FADT_MSI_NOT_SUPPORTED (1 << 3)
+#define ACPI_FADT_NO_PCIE_ASPM_CONTROL (1 << 4)
-#define LOCAL_APIC_FLAG_ENABLED (1 << 0)
-/* bits 1-31: reserved */
-#define PCAT_COMPAT (1 << 0)
-/* bits 1-31: reserved */
+/* FADT Feature Flags */
+#define ACPI_FADT_WBINVD (1 << 0)
+#define ACPI_FADT_WBINVD_FLUSH (1 << 1)
+#define ACPI_FADT_C1_SUPPORTED (1 << 2)
+#define ACPI_FADT_C2_MP_SUPPORTED (1 << 3)
+#define ACPI_FADT_POWER_BUTTON (1 << 4)
+#define ACPI_FADT_SLEEP_BUTTON (1 << 5)
+#define ACPI_FADT_FIXED_RTC (1 << 6)
+#define ACPI_FADT_S4_RTC_WAKE (1 << 7)
+#define ACPI_FADT_32BIT_TIMER (1 << 8)
+#define ACPI_FADT_DOCKING_SUPPORTED (1 << 9)
+#define ACPI_FADT_RESET_REGISTER (1 << 10)
+#define ACPI_FADT_SEALED_CASE (1 << 11)
+#define ACPI_FADT_HEADLESS (1 << 12)
+#define ACPI_FADT_SLEEP_TYPE (1 << 13)
+#define ACPI_FADT_PCI_EXPRESS_WAKE (1 << 14)
+#define ACPI_FADT_PLATFORM_CLOCK (1 << 15)
+#define ACPI_FADT_S4_RTC_VALID (1 << 16)
+#define ACPI_FADT_REMOTE_POWER_ON (1 << 17)
+#define ACPI_FADT_APIC_CLUSTER (1 << 18)
+#define ACPI_FADT_APIC_PHYSICAL (1 << 19)
+#define ACPI_FADT_HW_REDUCED_ACPI (1 << 20)
+#define ACPI_FADT_LOW_PWR_IDLE_S0 (1 << 21)
-/* MADT: Local APIC NMI Structure */
-struct acpi_madt_lapic_nmi {
- u8 type; /* Type (4) */
- u8 length; /* Length in bytes (6) */
- u8 processor_id; /* ACPI processor ID */
- u16 flags; /* MPS INTI flags */
- u8 lint; /* Local APIC LINT# */
+enum acpi_address_space_type {
+ ACPI_ADDRESS_SPACE_MEMORY = 0, /* System memory */
+ ACPI_ADDRESS_SPACE_IO, /* System I/O */
+ ACPI_ADDRESS_SPACE_PCI, /* PCI config space */
+ ACPI_ADDRESS_SPACE_EC, /* Embedded controller */
+ ACPI_ADDRESS_SPACE_SMBUS, /* SMBus */
+ ACPI_ADDRESS_SPACE_PCC = 0x0a, /* Platform Comm. Channel */
+ ACPI_ADDRESS_SPACE_FIXED = 0x7f /* Functional fixed hardware */
};
-/* MADT: I/O APIC Structure */
-struct acpi_madt_ioapic {
- u8 type; /* Type (1) */
- u8 length; /* Length in bytes (12) */
- u8 ioapic_id; /* I/O APIC ID */
- u8 reserved;
- u32 ioapic_addr; /* I/O APIC address */
- u32 gsi_base; /* Global system interrupt base */
+enum acpi_address_space_size {
+ ACPI_ACCESS_SIZE_UNDEFINED = 0,
+ ACPI_ACCESS_SIZE_BYTE_ACCESS,
+ ACPI_ACCESS_SIZE_WORD_ACCESS,
+ ACPI_ACCESS_SIZE_DWORD_ACCESS,
+ ACPI_ACCESS_SIZE_QWORD_ACCESS
};
-/* MADT: Interrupt Source Override Structure */
-struct acpi_madt_irqoverride {
- u8 type; /* Type (2) */
- u8 length; /* Length in bytes (10) */
- u8 bus; /* ISA (0) */
- u8 source; /* Bus-relative int. source (IRQ) */
- u32 gsirq; /* Global system interrupt */
- u16 flags; /* MPS INTI flags */
+struct acpi_gen_regaddr {
+ u8 space_id; /* Address space ID */
+ u8 bit_width; /* Register size in bits */
+ u8 bit_offset; /* Register bit offset */
+ u8 access_size; /* Access size */
+ u32 addrl; /* Register address, low 32 bits */
+ u32 addrh; /* Register address, high 32 bits */
};
/* FADT (Fixed ACPI Description Table) */
struct acpi_table_header header;
u32 firmware_ctrl;
u32 dsdt;
- u8 model;
+ u8 res1;
u8 preferred_pm_profile;
u16 sci_int;
u32 smi_cmd;
struct acpi_gen_regaddr x_gpe1_blk;
};
-/* Flags for p_lvl2_lat and p_lvl3_lat */
-#define ACPI_FADT_C2_NOT_SUPPORTED 101
-#define ACPI_FADT_C3_NOT_SUPPORTED 1001
+/* FACS flags */
+#define ACPI_FACS_S4BIOS_F (1 << 0)
+#define ACPI_FACS_64BIT_WAKE_F (1 << 1)
-/* FADT Feature Flags */
-#define ACPI_FADT_WBINVD (1 << 0)
-#define ACPI_FADT_WBINVD_FLUSH (1 << 1)
-#define ACPI_FADT_C1_SUPPORTED (1 << 2)
-#define ACPI_FADT_C2_MP_SUPPORTED (1 << 3)
-#define ACPI_FADT_POWER_BUTTON (1 << 4)
-#define ACPI_FADT_SLEEP_BUTTON (1 << 5)
-#define ACPI_FADT_FIXED_RTC (1 << 6)
-#define ACPI_FADT_S4_RTC_WAKE (1 << 7)
-#define ACPI_FADT_32BIT_TIMER (1 << 8)
-#define ACPI_FADT_DOCKING_SUPPORTED (1 << 9)
-#define ACPI_FADT_RESET_REGISTER (1 << 10)
-#define ACPI_FADT_SEALED_CASE (1 << 11)
-#define ACPI_FADT_HEADLESS (1 << 12)
-#define ACPI_FADT_SLEEP_TYPE (1 << 13)
-#define ACPI_FADT_PCI_EXPRESS_WAKE (1 << 14)
-#define ACPI_FADT_PLATFORM_CLOCK (1 << 15)
-#define ACPI_FADT_S4_RTC_VALID (1 << 16)
-#define ACPI_FADT_REMOTE_POWER_ON (1 << 17)
-#define ACPI_FADT_APIC_CLUSTER (1 << 18)
-#define ACPI_FADT_APIC_PHYSICAL (1 << 19)
-/* Bits 20-31: reserved ACPI 3.0 & 4.0 */
-#define ACPI_FADT_HW_REDUCED_ACPI (1 << 20)
-#define ACPI_FADT_LOW_PWR_IDLE_S0 (1 << 21)
-/* bits 22-31: reserved ACPI 5.0 */
+/* FACS (Firmware ACPI Control Structure) */
+struct acpi_facs {
+ char signature[4]; /* "FACS" */
+ u32 length; /* Length in bytes (>= 64) */
+ u32 hardware_signature; /* Hardware signature */
+ u32 firmware_waking_vector; /* Firmware waking vector */
+ u32 global_lock; /* Global lock */
+ u32 flags; /* FACS flags */
+ u32 x_firmware_waking_vector_l; /* X FW waking vector, low */
+ u32 x_firmware_waking_vector_h; /* X FW waking vector, high */
+ u8 version; /* Version 2 */
+ u8 res1[3];
+ u32 ospm_flags; /* OSPM enabled flags */
+ u8 res2[24];
+};
-/* FADT Boot Architecture Flags */
-#define ACPI_FADT_LEGACY_DEVICES (1 << 0)
-#define ACPI_FADT_8042 (1 << 1)
-#define ACPI_FADT_VGA_NOT_PRESENT (1 << 2)
-#define ACPI_FADT_MSI_NOT_SUPPORTED (1 << 3)
-#define ACPI_FADT_NO_PCIE_ASPM_CONTROL (1 << 4)
-/* No legacy devices (including 8042) */
-#define ACPI_FADT_LEGACY_FREE 0x00
+/* MADT flags */
+#define ACPI_MADT_PCAT_COMPAT (1 << 0)
-/* FADT Preferred Power Management Profile */
-#define PM_UNSPECIFIED 0
-#define PM_DESKTOP 1
-#define PM_MOBILE 2
-#define PM_WORKSTATION 3
-#define PM_ENTERPRISE_SERVER 4
-#define PM_SOHO_SERVER 5
-#define PM_APPLIANCE_PC 6
-#define PM_PERFORMANCE_SERVER 7
-#define PM_TABLET 8 /* ACPI 5.0 */
+/* MADT (Multiple APIC Description Table) */
+struct acpi_madt {
+ struct acpi_table_header header;
+ u32 lapic_addr; /* Local APIC address */
+ u32 flags; /* Multiple APIC flags */
+};
-/* FACS (Firmware ACPI Control Structure) */
-struct acpi_facs {
- char signature[4]; /* "FACS" */
- u32 length; /* Length in bytes (>= 64) */
- u32 hardware_signature; /* Hardware signature */
- u32 firmware_waking_vector; /* Firmware waking vector */
- u32 global_lock; /* Global lock */
- u32 flags; /* FACS flags */
- u32 x_firmware_waking_vector_l; /* X FW waking vector, low */
- u32 x_firmware_waking_vector_h; /* X FW waking vector, high */
- u8 version; /* ACPI 4.0: 2 */
- u8 resv[31]; /* FIXME: 4.0: ospm_flags */
+/* MADT: APIC Structure Type*/
+enum acpi_apic_types {
+ ACPI_APIC_LAPIC = 0, /* Processor local APIC */
+ ACPI_APIC_IOAPIC, /* I/O APIC */
+ ACPI_APIC_IRQ_SRC_OVERRIDE, /* Interrupt source override */
+ ACPI_APIC_NMI_SRC, /* NMI source */
+ ACPI_APIC_LAPIC_NMI, /* Local APIC NMI */
+ ACPI_APIC_LAPIC_ADDR_OVERRIDE, /* Local APIC address override */
+ ACPI_APIC_IOSAPIC, /* I/O SAPIC */
+ ACPI_APIC_LSAPIC, /* Local SAPIC */
+ ACPI_APIC_PLATFORM_IRQ_SRC, /* Platform interrupt sources */
+ ACPI_APIC_LX2APIC, /* Processor local x2APIC */
+ ACPI_APIC_LX2APIC_NMI, /* Local x2APIC NMI */
};
-/* FACS flags */
-#define ACPI_FACS_S4BIOS_F (1 << 0)
-#define ACPI_FACS_64BIT_WAKE_F (1 << 1)
-/* Bits 31..2: reserved */
+/* MADT: Processor Local APIC Structure */
+
+#define LOCAL_APIC_FLAG_ENABLED (1 << 0)
+
+struct acpi_madt_lapic {
+ u8 type; /* Type (0) */
+ u8 length; /* Length in bytes (8) */
+ u8 processor_id; /* ACPI processor ID */
+ u8 apic_id; /* Local APIC ID */
+ u32 flags; /* Local APIC flags */
+};
+
+/* MADT: I/O APIC Structure */
+struct acpi_madt_ioapic {
+ u8 type; /* Type (1) */
+ u8 length; /* Length in bytes (12) */
+ u8 ioapic_id; /* I/O APIC ID */
+ u8 reserved;
+ u32 ioapic_addr; /* I/O APIC address */
+ u32 gsi_base; /* Global system interrupt base */
+};
+
+/* MADT: Interrupt Source Override Structure */
+struct __packed acpi_madt_irqoverride {
+ u8 type; /* Type (2) */
+ u8 length; /* Length in bytes (10) */
+ u8 bus; /* ISA (0) */
+ u8 source; /* Bus-relative int. source (IRQ) */
+ u32 gsirq; /* Global system interrupt */
+ u16 flags; /* MPS INTI flags */
+};
+
+/* MADT: Local APIC NMI Structure */
+struct __packed acpi_madt_lapic_nmi {
+ u8 type; /* Type (4) */
+ u8 length; /* Length in bytes (6) */
+ u8 processor_id; /* ACPI processor ID */
+ u16 flags; /* MPS INTI flags */
+ u8 lint; /* Local APIC LINT# */
+};
+
+/* MCFG (PCI Express MMIO config space BAR description table) */
+struct acpi_mcfg {
+ struct acpi_table_header header;
+ u8 reserved[8];
+};
+
+struct acpi_mcfg_mmconfig {
+ u32 base_address_l;
+ u32 base_address_h;
+ u16 pci_segment_group_number;
+ u8 start_bus_number;
+ u8 end_bus_number;
+ u8 reserved[4];
+};
+
+/* PM1_CNT bit defines */
+#define PM1_CNT_SCI_EN (1 << 0)
/* These can be used by the target port */
-unsigned long acpi_create_madt_lapics(unsigned long current);
-int acpi_create_madt_ioapic(struct acpi_madt_ioapic *ioapic, u8 id, u32 addr,
- u32 gsi_base);
-int acpi_create_madt_irqoverride(struct acpi_madt_irqoverride *irqoverride,
- u8 bus, u8 source, u32 gsirq, u16 flags);
-unsigned long acpi_fill_madt(unsigned long current);
+void acpi_fill_header(struct acpi_table_header *header, char *signature);
void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs,
- void *dsdt);
-int acpi_create_madt_lapic_nmi(struct acpi_madt_lapic_nmi *lapic_nmi, u8 cpu,
- u16 flags, u8 lint);
+ void *dsdt);
+int acpi_create_madt_lapics(u32 current);
+int acpi_create_madt_ioapic(struct acpi_madt_ioapic *ioapic, u8 id,
+ u32 addr, u32 gsi_base);
+int acpi_create_madt_irqoverride(struct acpi_madt_irqoverride *irqoverride,
+ u8 bus, u8 source, u32 gsirq, u16 flags);
+int acpi_create_madt_lapic_nmi(struct acpi_madt_lapic_nmi *lapic_nmi,
+ u8 cpu, u16 flags, u8 lint);
+u32 acpi_fill_madt(u32 current);
u32 write_acpi_tables(u32 start);
--- /dev/null
+/*
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/soc/intel/baytrail/acpi/gpio.asl
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/* SouthCluster GPIO */
+Device (GPSC)
+{
+ Name(_HID, "INT33FC")
+ Name(_CID, "INT33FC")
+ Name(_UID, 1)
+
+ Name(RBUF, ResourceTemplate()
+ {
+ Memory32Fixed(ReadWrite, 0, 0x1000, RMEM)
+ Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , ,)
+ {
+ GPIO_SC_IRQ
+ }
+ })
+
+ Method(_CRS)
+ {
+ CreateDwordField(^RBUF, ^RMEM._BAS, RBAS)
+ Add(IO_BASE_ADDRESS, IO_BASE_OFFSET_GPSCORE, RBAS)
+ Return (^RBUF)
+ }
+
+ Method(_STA)
+ {
+ Return (STA_VISIBLE)
+ }
+}
+
+/* NorthCluster GPIO */
+Device (GPNC)
+{
+ Name(_HID, "INT33FC")
+ Name(_CID, "INT33FC")
+ Name(_UID, 2)
+
+ Name(RBUF, ResourceTemplate()
+ {
+ Memory32Fixed(ReadWrite, 0, 0x1000, RMEM)
+ Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , ,)
+ {
+ GPIO_NC_IRQ
+ }
+ })
+
+ Method(_CRS)
+ {
+ CreateDwordField(^RBUF, ^RMEM._BAS, RBAS)
+ Add(IO_BASE_ADDRESS, IO_BASE_OFFSET_GPNCORE, RBAS)
+ Return (^RBUF)
+ }
+
+ Method(_STA)
+ {
+ Return (STA_VISIBLE)
+ }
+}
+
+/* SUS GPIO */
+Device (GPSS)
+{
+ Name(_HID, "INT33FC")
+ Name(_CID, "INT33FC")
+ Name(_UID, 3)
+
+ Name(RBUF, ResourceTemplate()
+ {
+ Memory32Fixed(ReadWrite, 0, 0x1000, RMEM)
+ Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , ,)
+ {
+ GPIO_SUS_IRQ
+ }
+ })
+
+ Method(_CRS)
+ {
+ CreateDwordField(^RBUF, ^RMEM._BAS, RBAS)
+ Add(IO_BASE_ADDRESS, IO_BASE_OFFSET_GPSSUS, RBAS)
+ Return (^RBUF)
+ }
+
+ Method(_STA)
+ {
+ Return (STA_VISIBLE)
+ }
+}
--- /dev/null
+/*
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2014 Sage Electronics Engineering, LLC.
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/soc/intel/baytrail/include/soc/irq_helper.h
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * This file intentionally gets included multiple times, to set pic and apic
+ * modes, so should not have guard statements added.
+ */
+
+/*
+ * This file will use irqroute.asl and irqroute.h to generate the ACPI IRQ
+ * routing for the platform being compiled.
+ *
+ * This method uses #defines in irqroute.h along with the macros contained
+ * in this file to generate an IRQ routing for each PCI device in the system.
+ */
+
+#undef PCI_DEV_PIRQ_ROUTES
+#undef PCI_DEV_PIRQ_ROUTE
+#undef ACPI_DEV_IRQ
+#undef PCIE_BRIDGE_DEV
+#undef RP_IRQ_ROUTES
+#undef ROOTPORT_METHODS
+#undef ROOTPORT_IRQ_ROUTES
+#undef RP_METHOD
+
+#if defined(PIC_MODE)
+
+#define ACPI_DEV_IRQ(dev_, pin_, pin_name_) \
+ Package() { ## dev_ ## ffff, pin_, \_SB.PCI0.LPCB.LNK ## pin_name_, 0 }
+
+#define RP_IRQ_ROUTES(prefix_, func_, a_, b_, c_, d_) \
+Name(prefix_ ## func_ ## P, Package() \
+{ \
+ ACPI_DEV_IRQ(0x0000, 0, a_), \
+ ACPI_DEV_IRQ(0x0000, 1, b_), \
+ ACPI_DEV_IRQ(0x0000, 2, c_), \
+ ACPI_DEV_IRQ(0x0000, 3, d_), \
+})
+
+/* define as blank so ROOTPORT_METHODS only gets inserted once */
+#define ROOTPORT_METHODS(prefix_, dev_)
+
+#else /* defined(PIC_MODE) */
+
+#define ACPI_DEV_IRQ(dev_, pin_, pin_name_) \
+ Package() { ## dev_ ## ffff, pin_, 0, PIRQ ## pin_name_ ## _APIC_IRQ }
+
+#define RP_IRQ_ROUTES(prefix_, func_, a_, b_, c_, d_) \
+Name(prefix_ ## func_ ## A, Package() \
+{ \
+ ACPI_DEV_IRQ(0x0000, 0, a_), \
+ ACPI_DEV_IRQ(0x0000, 1, b_), \
+ ACPI_DEV_IRQ(0x0000, 2, c_), \
+ ACPI_DEV_IRQ(0x0000, 3, d_), \
+})
+
+#define ROOTPORT_METHODS(prefix_, dev_) \
+ RP_METHOD(prefix_, dev_, 0) \
+ RP_METHOD(prefix_, dev_, 1) \
+ RP_METHOD(prefix_, dev_, 2) \
+ RP_METHOD(prefix_, dev_, 3) \
+ RP_METHOD(prefix_, dev_, 4) \
+ RP_METHOD(prefix_, dev_, 5) \
+ RP_METHOD(prefix_, dev_, 6) \
+ RP_METHOD(prefix_, dev_, 7)
+
+#endif /* defined(PIC_MODE) */
+
+#define PCI_DEV_PIRQ_ROUTE(dev_, a_, b_, c_, d_) \
+ ACPI_DEV_IRQ(dev_, 0, a_), \
+ ACPI_DEV_IRQ(dev_, 1, b_), \
+ ACPI_DEV_IRQ(dev_, 2, c_), \
+ ACPI_DEV_IRQ(dev_, 3, d_)
+
+#define PCIE_BRIDGE_DEV(prefix_, dev_, a_, b_, c_, d_) \
+ ROOTPORT_IRQ_ROUTES(prefix_, a_, b_, c_, d_) \
+ ROOTPORT_METHODS(prefix_, dev_)
+
+#define ROOTPORT_IRQ_ROUTES(prefix_, a_, b_, c_, d_) \
+ RP_IRQ_ROUTES(prefix_, 0, a_, b_, c_, d_) \
+ RP_IRQ_ROUTES(prefix_, 1, b_, c_, d_, a_) \
+ RP_IRQ_ROUTES(prefix_, 2, c_, d_, a_, b_) \
+ RP_IRQ_ROUTES(prefix_, 3, d_, a_, b_, c_) \
+ RP_IRQ_ROUTES(prefix_, 4, a_, b_, c_, d_) \
+ RP_IRQ_ROUTES(prefix_, 5, b_, c_, d_, a_) \
+ RP_IRQ_ROUTES(prefix_, 6, c_, d_, a_, b_) \
+ RP_IRQ_ROUTES(prefix_, 7, d_, a_, b_, c_)
+
+#define RP_METHOD(prefix_, dev_, func_)\
+Device (prefix_ ## 0 ## func_) \
+{ \
+ Name(_ADR, dev_ ## 000 ## func_) \
+ Name(_PRW, Package() { 0, 0 }) \
+ Method(_PRT) { \
+ If (PICM) { \
+ Return (prefix_ ## func_ ## A) \
+ } Else { \
+ Return (prefix_ ## func_ ## P) \
+ } \
+ } \
+}
+
+/* SoC specific PIRQ route configuration */
+#include "irqroute.h"
--- /dev/null
+/*
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/soc/intel/baytrail/acpi/irqlinks.asl
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+Scope (\)
+{
+ /* Intel Legacy Block */
+ OperationRegion(ILBS, SystemMemory, ILB_BASE_ADDRESS, ILB_BASE_SIZE)
+ Field(ILBS, AnyAcc, NoLock, Preserve) {
+ Offset (0x8),
+ PRTA, 8,
+ PRTB, 8,
+ PRTC, 8,
+ PRTD, 8,
+ PRTE, 8,
+ PRTF, 8,
+ PRTG, 8,
+ PRTH, 8,
+ Offset (0x88),
+ , 3,
+ UI3E, 1,
+ UI4E, 1
+ }
+}
+
+Device (LNKA)
+{
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 1)
+
+ /* Disable method */
+ Method(_DIS, 0, Serialized)
+ {
+ Store(0x80, PRTA)
+ }
+
+ /* Possible Resource Settings for this Link */
+ Name(_PRS, ResourceTemplate()
+ {
+ IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 }
+ })
+
+ /* Current Resource Settings for this link */
+ Method(_CRS, 0, Serialized)
+ {
+ Name(RTLA, ResourceTemplate()
+ {
+ IRQ(Level, ActiveLow, Shared) {}
+ })
+ CreateWordField(RTLA, 1, IRQ0)
+
+ /* Clear the WordField */
+ Store(Zero, IRQ0)
+
+ /* Set the bit from PRTA */
+ ShiftLeft(1, And(PRTA, 0x0f), IRQ0)
+
+ Return (RTLA)
+ }
+
+ /* Set Resource Setting for this IRQ link */
+ Method(_SRS, 1, Serialized)
+ {
+ CreateWordField(Arg0, 1, IRQ0)
+
+ /* Which bit is set? */
+ FindSetRightBit(IRQ0, Local0)
+
+ Decrement(Local0)
+ Store(Local0, PRTA)
+ }
+
+ /* Status */
+ Method(_STA, 0, Serialized)
+ {
+ If (And(PRTA, 0x80)) {
+ Return (STA_DISABLED)
+ } Else {
+ Return (STA_INVISIBLE)
+ }
+ }
+}
+
+Device (LNKB)
+{
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 2)
+
+ /* Disable method */
+ Method(_DIS, 0, Serialized)
+ {
+ Store(0x80, PRTB)
+ }
+
+ /* Possible Resource Settings for this Link */
+ Name(_PRS, ResourceTemplate()
+ {
+ IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 }
+ })
+
+ /* Current Resource Settings for this link */
+ Method(_CRS, 0, Serialized)
+ {
+ Name(RTLB, ResourceTemplate()
+ {
+ IRQ(Level, ActiveLow, Shared) {}
+ })
+ CreateWordField(RTLB, 1, IRQ0)
+
+ /* Clear the WordField */
+ Store(Zero, IRQ0)
+
+ /* Set the bit from PRTB */
+ ShiftLeft(1, And(PRTB, 0x0f), IRQ0)
+
+ Return (RTLB)
+ }
+
+ /* Set Resource Setting for this IRQ link */
+ Method(_SRS, 1, Serialized)
+ {
+ CreateWordField(Arg0, 1, IRQ0)
+
+ /* Which bit is set? */
+ FindSetRightBit(IRQ0, Local0)
+
+ Decrement(Local0)
+ Store(Local0, PRTB)
+ }
+
+ /* Status */
+ Method(_STA, 0, Serialized)
+ {
+ If (And(PRTB, 0x80)) {
+ Return (STA_DISABLED)
+ } Else {
+ Return (STA_INVISIBLE)
+ }
+ }
+}
+
+Device (LNKC)
+{
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 3)
+
+ /* Disable method */
+ Method(_DIS, 0, Serialized)
+ {
+ Store(0x80, PRTC)
+ }
+
+ /* Possible Resource Settings for this Link */
+ Name(_PRS, ResourceTemplate()
+ {
+ IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 }
+ })
+
+ /* Current Resource Settings for this link */
+ Method(_CRS, 0, Serialized)
+ {
+ Name(RTLC, ResourceTemplate()
+ {
+ IRQ(Level, ActiveLow, Shared) {}
+ })
+ CreateWordField(RTLC, 1, IRQ0)
+
+ /* Clear the WordField */
+ Store(Zero, IRQ0)
+
+ /* Set the bit from PRTC */
+ ShiftLeft(1, And(PRTC, 0x0f), IRQ0)
+
+ Return (RTLC)
+ }
+
+ /* Set Resource Setting for this IRQ link */
+ Method(_SRS, 1, Serialized)
+ {
+ CreateWordField(Arg0, 1, IRQ0)
+
+ /* Which bit is set? */
+ FindSetRightBit(IRQ0, Local0)
+
+ Decrement(Local0)
+ Store(Local0, PRTC)
+ }
+
+ /* Status */
+ Method(_STA, 0, Serialized)
+ {
+ If (And(PRTC, 0x80)) {
+ Return (STA_DISABLED)
+ } Else {
+ Return (STA_INVISIBLE)
+ }
+ }
+}
+
+Device (LNKD)
+{
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 4)
+
+ /* Disable method */
+ Method(_DIS, 0, Serialized)
+ {
+ Store(0x80, PRTD)
+ }
+
+ /* Possible Resource Settings for this Link */
+ Name(_PRS, ResourceTemplate()
+ {
+ IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 }
+ })
+
+ /* Current Resource Settings for this link */
+ Method(_CRS, 0, Serialized)
+ {
+ Name(RTLD, ResourceTemplate()
+ {
+ IRQ(Level, ActiveLow, Shared) {}
+ })
+ CreateWordField(RTLD, 1, IRQ0)
+
+ /* Clear the WordField */
+ Store(Zero, IRQ0)
+
+ /* Set the bit from PRTD */
+ ShiftLeft(1, And(PRTD, 0x0f), IRQ0)
+
+ Return (RTLD)
+ }
+
+ /* Set Resource Setting for this IRQ link */
+ Method(_SRS, 1, Serialized)
+ {
+ CreateWordField(Arg0, 1, IRQ0)
+
+ /* Which bit is set? */
+ FindSetRightBit(IRQ0, Local0)
+
+ Decrement(Local0)
+ Store(Local0, PRTD)
+ }
+
+ /* Status */
+ Method(_STA, 0, Serialized)
+ {
+ If (And(PRTD, 0x80)) {
+ Return (STA_DISABLED)
+ } Else {
+ Return (STA_INVISIBLE)
+ }
+ }
+}
+
+Device (LNKE)
+{
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 5)
+
+ /* Disable method */
+ Method(_DIS, 0, Serialized)
+ {
+ Store(0x80, PRTE)
+ }
+
+ /* Possible Resource Settings for this Link */
+ Name(_PRS, ResourceTemplate()
+ {
+ IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 }
+ })
+
+ /* Current Resource Settings for this link */
+ Method(_CRS, 0, Serialized)
+ {
+ Name(RTLE, ResourceTemplate()
+ {
+ IRQ(Level, ActiveLow, Shared) {}
+ })
+ CreateWordField(RTLE, 1, IRQ0)
+
+ /* Clear the WordField */
+ Store(Zero, IRQ0)
+
+ /* Set the bit from PRTE */
+ ShiftLeft(1, And(PRTE, 0x0f), IRQ0)
+
+ Return (RTLE)
+ }
+
+ /* Set Resource Setting for this IRQ link */
+ Method(_SRS, 1, Serialized)
+ {
+ CreateWordField(Arg0, 1, IRQ0)
+
+ /* Which bit is set? */
+ FindSetRightBit(IRQ0, Local0)
+
+ Decrement(Local0)
+ Store(Local0, PRTE)
+ }
+
+ /* Status */
+ Method(_STA, 0, Serialized)
+ {
+ If (And(PRTE, 0x80)) {
+ Return (STA_DISABLED)
+ } Else {
+ Return (STA_INVISIBLE)
+ }
+ }
+}
+
+Device (LNKF)
+{
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 6)
+
+ /* Disable method */
+ Method(_DIS, 0, Serialized)
+ {
+ Store(0x80, PRTF)
+ }
+
+ /* Possible Resource Settings for this Link */
+ Name(_PRS, ResourceTemplate()
+ {
+ IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 }
+ })
+
+ /* Current Resource Settings for this link */
+ Method(_CRS, 0, Serialized)
+ {
+ Name(RTLF, ResourceTemplate()
+ {
+ IRQ(Level, ActiveLow, Shared) {}
+ })
+ CreateWordField(RTLF, 1, IRQ0)
+
+ /* Clear the WordField */
+ Store(Zero, IRQ0)
+
+ /* Set the bit from PRTF */
+ ShiftLeft(1, And(PRTF, 0x0f), IRQ0)
+
+ Return (RTLF)
+ }
+
+ /* Set Resource Setting for this IRQ link */
+ Method(_SRS, 1, Serialized)
+ {
+ CreateWordField(Arg0, 1, IRQ0)
+
+ /* Which bit is set? */
+ FindSetRightBit(IRQ0, Local0)
+
+ Decrement(Local0)
+ Store(Local0, PRTF)
+ }
+
+ /* Status */
+ Method(_STA, 0, Serialized)
+ {
+ If (And(PRTF, 0x80)) {
+ Return (STA_DISABLED)
+ } Else {
+ Return (STA_INVISIBLE)
+ }
+ }
+}
+
+Device (LNKG)
+{
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 7)
+
+ /* Disable method */
+ Method(_DIS, 0, Serialized)
+ {
+ Store(0x80, PRTG)
+ }
+
+ /* Possible Resource Settings for this Link */
+ Name(_PRS, ResourceTemplate()
+ {
+ IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 }
+ })
+
+ /* Current Resource Settings for this link */
+ Method(_CRS, 0, Serialized)
+ {
+ Name(RTLG, ResourceTemplate()
+ {
+ IRQ(Level, ActiveLow, Shared) {}
+ })
+ CreateWordField(RTLG, 1, IRQ0)
+
+ /* Clear the WordField */
+ Store(Zero, IRQ0)
+
+ /* Set the bit from PRTG */
+ ShiftLeft(1, And(PRTG, 0x0f), IRQ0)
+
+ Return (RTLG)
+ }
+
+ /* Set Resource Setting for this IRQ link */
+ Method(_SRS, 1, Serialized)
+ {
+ CreateWordField(Arg0, 1, IRQ0)
+
+ /* Which bit is set? */
+ FindSetRightBit(IRQ0, Local0)
+
+ Decrement(Local0)
+ Store(Local0, PRTG)
+ }
+
+ /* Status */
+ Method(_STA, 0, Serialized)
+ {
+ If (And(PRTG, 0x80)) {
+ Return (STA_DISABLED)
+ } Else {
+ Return (STA_INVISIBLE)
+ }
+ }
+}
+
+Device (LNKH)
+{
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 8)
+
+ /* Disable method */
+ Method(_DIS, 0, Serialized)
+ {
+ Store(0x80, PRTH)
+ }
+
+ /* Possible Resource Settings for this Link */
+ Name(_PRS, ResourceTemplate()
+ {
+ IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 }
+ })
+
+ /* Current Resource Settings for this link */
+ Method(_CRS, 0, Serialized)
+ {
+ Name(RTLH, ResourceTemplate()
+ {
+ IRQ(Level, ActiveLow, Shared) {}
+ })
+ CreateWordField(RTLH, 1, IRQ0)
+
+ /* Clear the WordField */
+ Store(Zero, IRQ0)
+
+ /* Set the bit from PRTH */
+ ShiftLeft(1, And(PRTH, 0x0f), IRQ0)
+
+ Return (RTLH)
+ }
+
+ /* Set Resource Setting for this IRQ link */
+ Method(_SRS, 1, Serialized)
+ {
+ CreateWordField(Arg0, 1, IRQ0)
+
+ /* Which bit is set? */
+ FindSetRightBit(IRQ0, Local0)
+
+ Decrement(Local0)
+ Store(Local0, PRTH)
+ }
+
+ /* Status */
+ Method(_STA, 0, Serialized)
+ {
+ If (And(PRTH, 0x80)) {
+ Return (STA_DISABLED)
+ } Else {
+ Return (STA_INVISIBLE)
+ }
+ }
+}
--- /dev/null
+/*
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/soc/intel/baytrail/acpi/irqroute.asl
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+Name(\PICM, 0)
+
+/*
+ * The _PIC method is called by the OS to choose between interrupt
+ * routing via the i8259 interrupt controller or the APIC.
+ *
+ * _PIC is called with a parameter of 0 for i8259 configuration and
+ * with a parameter of 1 for Local APIC/IOAPIC configuration.
+ */
+Method(\_PIC, 1)
+{
+ /* Remember the OS' IRQ routing choice */
+ Store(Arg0, PICM)
+}
+
+/* PCI interrupt routing */
+Method(_PRT) {
+ If (PICM) {
+ Return (Package() {
+ #undef PIC_MODE
+ #include "irq_helper.h"
+ PCI_DEV_PIRQ_ROUTES
+ })
+ } Else {
+ Return (Package() {
+ #define PIC_MODE
+ #include "irq_helper.h"
+ PCI_DEV_PIRQ_ROUTES
+ })
+ }
+
+}
+
+/* PCIe downstream ports interrupt routing */
+PCIE_BRIDGE_IRQ_ROUTES
+#undef PIC_MODE
+#include "irq_helper.h"
+PCIE_BRIDGE_IRQ_ROUTES
--- /dev/null
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/device.h>
+
+#define PCI_DEV_PIRQ_ROUTES \
+ PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, A, A, A), \
+ PCI_DEV_PIRQ_ROUTE(EMMC_DEV, A, A, A, A), \
+ PCI_DEV_PIRQ_ROUTE(SDIO_DEV, A, A, A, A), \
+ PCI_DEV_PIRQ_ROUTE(SD_DEV, A, A, A, A), \
+ PCI_DEV_PIRQ_ROUTE(SATA_DEV, A, A, A, A), \
+ PCI_DEV_PIRQ_ROUTE(XHCI_DEV, A, A, A, A), \
+ PCI_DEV_PIRQ_ROUTE(LPE_DEV, A, A, A, A), \
+ PCI_DEV_PIRQ_ROUTE(MMC45_DEV, A, A, A, A), \
+ PCI_DEV_PIRQ_ROUTE(SIO1_DEV, A, B, C, D), \
+ PCI_DEV_PIRQ_ROUTE(TXE_DEV, A, A, A, A), \
+ PCI_DEV_PIRQ_ROUTE(HDA_DEV, A, A, A, A), \
+ PCI_DEV_PIRQ_ROUTE(PCIE_DEV, A, B, C, D), \
+ PCI_DEV_PIRQ_ROUTE(EHCI_DEV, A, A, A, A), \
+ PCI_DEV_PIRQ_ROUTE(SIO2_DEV, A, B, C, D), \
+ PCI_DEV_PIRQ_ROUTE(PCU_DEV, A, B, C, D)
+
+#define PCIE_BRIDGE_IRQ_ROUTES \
+ PCIE_BRIDGE_DEV(RP, PCIE_DEV, A, B, C, D)
--- /dev/null
+/*
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/soc/intel/baytrail/acpi/lpc.asl
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/* Intel LPC Bus Device - 0:1f.0 */
+
+Device (LPCB)
+{
+ Name(_ADR, 0x001f0000)
+
+ OperationRegion(LPC0, PCI_Config, 0x00, 0x100)
+ Field(LPC0, AnyAcc, NoLock, Preserve) {
+ Offset(0x08),
+ SRID, 8,
+ Offset(0x80),
+ C1EN, 1,
+ Offset(0x84)
+ }
+
+ #include "irqlinks.asl"
+
+ /* Firmware Hub */
+ Device (FWH)
+ {
+ Name(_HID, EISAID("INT0800"))
+ Name(_CRS, ResourceTemplate()
+ {
+ Memory32Fixed(ReadOnly, 0xff000000, 0x01000000)
+ })
+ }
+
+ /* 8259 Interrupt Controller */
+ Device (PIC)
+ {
+ Name(_HID, EISAID("PNP0000"))
+ Name(_CRS, ResourceTemplate()
+ {
+ IO(Decode16, 0x20, 0x20, 0x01, 0x02)
+ IO(Decode16, 0x24, 0x24, 0x01, 0x02)
+ IO(Decode16, 0x28, 0x28, 0x01, 0x02)
+ IO(Decode16, 0x2c, 0x2c, 0x01, 0x02)
+ IO(Decode16, 0x30, 0x30, 0x01, 0x02)
+ IO(Decode16, 0x34, 0x34, 0x01, 0x02)
+ IO(Decode16, 0x38, 0x38, 0x01, 0x02)
+ IO(Decode16, 0x3c, 0x3c, 0x01, 0x02)
+ IO(Decode16, 0xa0, 0xa0, 0x01, 0x02)
+ IO(Decode16, 0xa4, 0xa4, 0x01, 0x02)
+ IO(Decode16, 0xa8, 0xa8, 0x01, 0x02)
+ IO(Decode16, 0xac, 0xac, 0x01, 0x02)
+ IO(Decode16, 0xb0, 0xb0, 0x01, 0x02)
+ IO(Decode16, 0xb4, 0xb4, 0x01, 0x02)
+ IO(Decode16, 0xb8, 0xb8, 0x01, 0x02)
+ IO(Decode16, 0xbc, 0xbc, 0x01, 0x02)
+ IO(Decode16, 0x4d0, 0x4d0, 0x01, 0x02)
+ IRQNoFlags () { 2 }
+ })
+ }
+
+ /* 8254 timer */
+ Device (TIMR)
+ {
+ Name(_HID, EISAID("PNP0100"))
+ Name(_CRS, ResourceTemplate()
+ {
+ IO(Decode16, 0x40, 0x40, 0x01, 0x04)
+ IO(Decode16, 0x50, 0x50, 0x10, 0x04)
+ IRQNoFlags() { 0 }
+ })
+ }
+
+ /* HPET */
+ Device (HPET)
+ {
+ Name(_HID, EISAID("PNP0103"))
+ Name(_CID, 0x010CD041)
+ Name(_CRS, ResourceTemplate()
+ {
+ Memory32Fixed(ReadOnly, HPET_BASE_ADDRESS, HPET_BASE_SIZE)
+ })
+
+ Method(_STA)
+ {
+ Return (STA_VISIBLE)
+ }
+ }
+
+ /* Internal UART */
+ Device (IURT)
+ {
+ Name(_HID, EISAID("PNP0501"))
+ Name(_UID, 1)
+
+ Method(_STA, 0, Serialized)
+ {
+ /*
+ * TODO:
+ *
+ * Need to hide the internal UART depending on whether
+ * internal UART is enabled or not so that external
+ * SuperIO UART can be exposed to system.
+ */
+ Store(1, UI3E)
+ Store(1, UI4E)
+ Store(1, C1EN)
+ Return (STA_VISIBLE)
+
+ }
+
+ Method(_DIS, 0, Serialized)
+ {
+ Store(0, UI3E)
+ Store(0, UI4E)
+ Store(0, C1EN)
+ }
+
+ Method(_CRS, 0, Serialized)
+ {
+ Name(BUF0, ResourceTemplate()
+ {
+ IO(Decode16, 0x03f8, 0x03f8, 0x01, 0x08)
+ IRQNoFlags() { 3 }
+ })
+
+ Name(BUF1, ResourceTemplate()
+ {
+ IO(Decode16, 0x03f8, 0x03f8, 0x01, 0x08)
+ IRQNoFlags() { 4 }
+ })
+
+ If (LLessEqual(SRID, 0x04)) {
+ Return (BUF0)
+ } Else {
+ Return (BUF1)
+ }
+ }
+ }
+
+ /* Real Time Clock */
+ Device (RTC)
+ {
+ Name(_HID, EISAID("PNP0B00"))
+ Name(_CRS, ResourceTemplate()
+ {
+ IO(Decode16, 0x70, 0x70, 1, 8)
+ /*
+ * Disable as Windows doesn't like it, and systems
+ * don't seem to use it
+ */
+ /* IRQNoFlags() { 8 } */
+ })
+ }
+
+ /* LPC device: Resource consumption */
+ Device (LDRC)
+ {
+ Name(_HID, EISAID("PNP0C02"))
+ Name(_UID, 2)
+
+ Name(RBUF, ResourceTemplate()
+ {
+ IO(Decode16, 0x61, 0x61, 0x1, 0x01) /* NMI Status */
+ IO(Decode16, 0x63, 0x63, 0x1, 0x01) /* CPU Reserved */
+ IO(Decode16, 0x65, 0x65, 0x1, 0x01) /* CPU Reserved */
+ IO(Decode16, 0x67, 0x67, 0x1, 0x01) /* CPU Reserved */
+ IO(Decode16, 0x80, 0x80, 0x1, 0x01) /* Port 80 Post */
+ IO(Decode16, 0x92, 0x92, 0x1, 0x01) /* CPU Reserved */
+ IO(Decode16, 0xb2, 0xb2, 0x1, 0x02) /* SWSMI */
+ })
+
+ Method(_CRS, 0, NotSerialized)
+ {
+ Return (RBUF)
+ }
+ }
+}
--- /dev/null
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/acpi/statdef.asl>
+#include <asm/arch/iomap.h>
+#include <asm/arch/irq.h>
+
+/*
+ * The _PTS method (Prepare To Sleep) is called before the OS is
+ * entering a sleep state. The sleep state number is passed in Arg0.
+ */
+Method(_PTS, 1)
+{
+}
+
+/* The _WAK method is called on system wakeup */
+Method(_WAK, 1)
+{
+ Return (Package() {0, 0})
+}
+
+/* TODO: add CPU ASL support */
+
+Scope (\_SB)
+{
+ #include "southcluster.asl"
+
+ /* ACPI devices */
+ #include "gpio.asl"
+}
+
+/* Chipset specific sleep states */
+#include "sleepstates.asl"
--- /dev/null
+/*
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/soc/intel/baytrail/acpi/sleepstates.asl
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+Name(\_S0, Package() {0x0, 0x0, 0x0, 0x0})
+Name(\_S3, Package() {0x5, 0x0, 0x0, 0x0})
+Name(\_S4, Package() {0x6, 0x0, 0x0, 0x0})
+Name(\_S5, Package() {0x7, 0x0, 0x0, 0x0})
--- /dev/null
+/*
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/soc/intel/baytrail/acpi/southcluster.asl
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+Device (PCI0)
+{
+ Name(_HID, EISAID("PNP0A08")) /* PCIe */
+ Name(_CID, EISAID("PNP0A03")) /* PCI */
+
+ Name(_ADR, 0)
+ Name(_BBN, 0)
+
+ Name(MCRS, ResourceTemplate()
+ {
+ /* Bus Numbers */
+ WordBusNumber(ResourceProducer, MinFixed, MaxFixed, PosDecode,
+ 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100, , , PB00)
+
+ /* IO Region 0 */
+ WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8, , , PI00)
+
+ /* PCI Config Space */
+ IO(Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008)
+
+ /* IO Region 1 */
+ WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300, , , PI01)
+
+ /* VGA memory (0xa0000-0xbffff) */
+ DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000a0000, 0x000bffff, 0x00000000,
+ 0x00020000, , , ASEG)
+
+ /* OPROM reserved (0xc0000-0xc3fff) */
+ DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000c0000, 0x000c3fff, 0x00000000,
+ 0x00004000, , , OPR0)
+
+ /* OPROM reserved (0xc4000-0xc7fff) */
+ DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000c4000, 0x000c7fff, 0x00000000,
+ 0x00004000, , , OPR1)
+
+ /* OPROM reserved (0xc8000-0xcbfff) */
+ DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000c8000, 0x000cbfff, 0x00000000,
+ 0x00004000, , , OPR2)
+
+ /* OPROM reserved (0xcc000-0xcffff) */
+ DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000cc000, 0x000cffff, 0x00000000,
+ 0x00004000, , , OPR3)
+
+ /* OPROM reserved (0xd0000-0xd3fff) */
+ DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000,
+ 0x00004000, , , OPR4)
+
+ /* OPROM reserved (0xd4000-0xd7fff) */
+ DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000,
+ 0x00004000, , , OPR5)
+
+ /* OPROM reserved (0xd8000-0xdbfff) */
+ DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000,
+ 0x00004000, , , OPR6)
+
+ /* OPROM reserved (0xdc000-0xdffff) */
+ DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000dc000, 0x000dffff, 0x00000000,
+ 0x00004000, , , OPR7)
+
+ /* BIOS Extension (0xe0000-0xe3fff) */
+ DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000,
+ 0x00004000, , , ESG0)
+
+ /* BIOS Extension (0xe4000-0xe7fff) */
+ DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000,
+ 0x00004000, , , ESG1)
+
+ /* BIOS Extension (0xe8000-0xebfff) */
+ DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000,
+ 0x00004000, , , ESG2)
+
+ /* BIOS Extension (0xec000-0xeffff) */
+ DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000ec000, 0x000effff, 0x00000000,
+ 0x00004000, , , ESG3)
+
+ /* System BIOS (0xf0000-0xfffff) */
+ DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000f0000, 0x000fffff, 0x00000000,
+ 0x00010000, , , FSEG)
+
+ /* PCI Memory Region (TOLM-CONFIG_MMCONF_BASE_ADDRESS) */
+ DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, , , PMEM)
+
+ /* High PCI Memory Region */
+ QwordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, , , UMEM)
+ })
+
+ Method(_CRS, 0, Serialized)
+ {
+ /* Update PCI resource area */
+ CreateDwordField(MCRS, ^PMEM._MIN, PMIN)
+ CreateDwordField(MCRS, ^PMEM._MAX, PMAX)
+ CreateDwordField(MCRS, ^PMEM._LEN, PLEN)
+
+ /*
+ * Hardcode TOLM to 2GB for now as BayTrail FSP uses this value.
+ *
+ * TODO: for generic usage, read TOLM value from register, or
+ * from global NVS (not implemented by U-Boot yet).
+ */
+ Store(0x80000000, PMIN)
+ Store(Subtract(MCFG_BASE_ADDRESS, 1), PMAX)
+ Add(Subtract(PMAX, PMIN), 1, PLEN)
+
+ /* Update High PCI resource area */
+ CreateQwordField(MCRS, ^UMEM._MIN, UMIN)
+ CreateQwordField(MCRS, ^UMEM._MAX, UMAX)
+ CreateQwordField(MCRS, ^UMEM._LEN, ULEN)
+
+ /* Set base address to 48GB and allocate 16GB for PCI space */
+ Store(0xc00000000, UMIN)
+ Store(0x400000000, ULEN)
+ Add(UMIN, Subtract(ULEN, 1), UMAX)
+
+ Return (MCRS)
+ }
+
+ /* Device Resource Consumption */
+ Device (PDRC)
+ {
+ Name(_HID, EISAID("PNP0C02"))
+ Name(_UID, 1)
+
+ Name(PDRS, ResourceTemplate() {
+ Memory32Fixed(ReadWrite, MCFG_BASE_ADDRESS, MCFG_BASE_SIZE)
+ Memory32Fixed(ReadWrite, ABORT_BASE_ADDRESS, ABORT_BASE_SIZE)
+ Memory32Fixed(ReadWrite, SPI_BASE_ADDRESS, SPI_BASE_SIZE)
+ Memory32Fixed(ReadWrite, PMC_BASE_ADDRESS, PMC_BASE_SIZE)
+ Memory32Fixed(ReadWrite, PUNIT_BASE_ADDRESS, PUNIT_BASE_SIZE)
+ Memory32Fixed(ReadWrite, ILB_BASE_ADDRESS, ILB_BASE_SIZE)
+ Memory32Fixed(ReadWrite, RCBA_BASE_ADDRESS, RCBA_BASE_SIZE)
+ Memory32Fixed(ReadWrite, MPHY_BASE_ADDRESS, MPHY_BASE_SIZE)
+ })
+
+ /* Current Resource Settings */
+ Method(_CRS, 0, Serialized)
+ {
+ Return (PDRS)
+ }
+ }
+
+ Method(_OSC, 4)
+ {
+ /* Check for proper GUID */
+ If (LEqual(Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
+ /* Let OS control everything */
+ Return (Arg3)
+ } Else {
+ /* Unrecognized UUID */
+ CreateDWordField(Arg3, 0, CDW1)
+ Or(CDW1, 4, CDW1)
+ Return (Arg3)
+ }
+ }
+
+ /* LPC Bridge 0:1f.0 */
+ #include "lpc.asl"
+
+ /* USB EHCI 0:1d.0 */
+ #include "usb.asl"
+
+ /* USB XHCI 0:14.0 */
+ #include "xhci.asl"
+
+ /* IRQ routing for each PCI device */
+ #include "irqroute.asl"
+}
--- /dev/null
+/*
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/soc/intel/baytrail/acpi/usb.asl
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/* EHCI Controller 0:1d.0 */
+
+Device (EHC1)
+{
+ Name(_ADR, 0x001d0000)
+
+ /* Power Resources for Wake */
+ Name(_PRW, Package() { 13, 4 })
+
+ /* Highest D state in S3 state */
+ Name(_S3D, 2)
+
+ /* Highest D state in S4 state */
+ Name(_S4D, 2)
+
+ Device (HUB7)
+ {
+ Name(_ADR, 0x00000000)
+
+ Device(PRT1) { Name(_ADR, 1) } /* USB Port 0 */
+ Device(PRT2) { Name(_ADR, 2) } /* USB Port 1 */
+ Device(PRT3) { Name(_ADR, 3) } /* USB Port 2 */
+ Device(PRT4) { Name(_ADR, 4) } /* USB Port 3 */
+ }
+}
--- /dev/null
+/*
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/soc/intel/baytrail/acpi/xhci.asl
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/* XHCI Controller 0:14.0 */
+
+Device (XHCI)
+{
+ Name(_ADR, 0x00140000)
+
+ /* Power Resources for Wake */
+ Name(_PRW, Package() { 13, 3 })
+
+ /* Highest D state in S3 state */
+ Name(_S3D, 3)
+
+ Device (RHUB)
+ {
+ Name(_ADR, 0x00000000)
+
+ Device (PRT1) { Name(_ADR, 1) } /* USB Port 0 */
+ Device (PRT2) { Name(_ADR, 2) } /* USB Port 1 */
+ Device (PRT3) { Name(_ADR, 3) } /* USB Port 2 */
+ Device (PRT4) { Name(_ADR, 4) } /* USB Port 3 */
+ }
+}
--- /dev/null
+/*
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/soc/intel/baytrail/include/soc/pci_devs.h
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _DEVICE_H_
+#define _DEVICE_H_
+
+/*
+ * Internal PCI device numbers within the SoC.
+ *
+ * Note it must start with 0x_ prefix, as the device number macro will be
+ * included in the ACPI ASL files (see irq_helper.h and irq_route.h).
+ */
+
+/* SoC transaction router */
+#define SOC_DEV 0x00
+
+/* Graphics and Display */
+#define GFX_DEV 0x02
+
+/* MIPI */
+#define MIPI_DEV 0x03
+
+/* EMMC Port */
+#define EMMC_DEV 0x10
+
+/* SDIO Port */
+#define SDIO_DEV 0x11
+
+/* SD Port */
+#define SD_DEV 0x12
+
+/* SATA */
+#define SATA_DEV 0x13
+
+/* xHCI */
+#define XHCI_DEV 0x14
+
+/* LPE Audio */
+#define LPE_DEV 0x15
+
+/* OTG */
+#define OTG_DEV 0x16
+
+/* MMC45 Port */
+#define MMC45_DEV 0x17
+
+/* Serial IO 1 */
+#define SIO1_DEV 0x18
+
+/* Trusted Execution Engine */
+#define TXE_DEV 0x1a
+
+/* HD Audio */
+#define HDA_DEV 0x1b
+
+/* PCIe Ports */
+#define PCIE_DEV 0x1c
+
+/* EHCI */
+#define EHCI_DEV 0x1d
+
+/* Serial IO 2 */
+#define SIO2_DEV 0x1e
+
+/* Platform Controller Unit */
+#define PCU_DEV 0x1f
+
+#endif /* _DEVICE_H_ */
--- /dev/null
+/*
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/soc/intel/baytrail/include/soc/iomap.h
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _BAYTRAIL_IOMAP_H_
+#define _BAYTRAIL_IOMAP_H_
+
+/* Memory Mapped IO bases */
+
+/* PCI Configuration Space */
+#define MCFG_BASE_ADDRESS CONFIG_PCIE_ECAM_BASE
+#define MCFG_BASE_SIZE 0x10000000
+
+/* Temporary Base Address */
+#define TEMP_BASE_ADDRESS 0xfd000000
+
+/* Transactions in this range will abort */
+#define ABORT_BASE_ADDRESS 0xfeb00000
+#define ABORT_BASE_SIZE 0x00100000
+
+/* High Performance Event Timer */
+#define HPET_BASE_ADDRESS 0xfed00000
+#define HPET_BASE_SIZE 0x400
+
+/* SPI Bus */
+#define SPI_BASE_ADDRESS 0xfed01000
+#define SPI_BASE_SIZE 0x400
+
+/* Power Management Controller */
+#define PMC_BASE_ADDRESS 0xfed03000
+#define PMC_BASE_SIZE 0x400
+
+/* Power Management Unit */
+#define PUNIT_BASE_ADDRESS 0xfed05000
+#define PUNIT_BASE_SIZE 0x800
+
+/* Intel Legacy Block */
+#define ILB_BASE_ADDRESS 0xfed08000
+#define ILB_BASE_SIZE 0x400
+
+/* IO Memory */
+#define IO_BASE_ADDRESS 0xfed0c000
+#define IO_BASE_OFFSET_GPSCORE 0x0000
+#define IO_BASE_OFFSET_GPNCORE 0x1000
+#define IO_BASE_OFFSET_GPSSUS 0x2000
+#define IO_BASE_SIZE 0x4000
+
+/* Root Complex Base Address */
+#define RCBA_BASE_ADDRESS 0xfed1c000
+#define RCBA_BASE_SIZE 0x400
+
+/* MODPHY */
+#define MPHY_BASE_ADDRESS 0xfef00000
+#define MPHY_BASE_SIZE 0x100000
+
+/* IO Port bases */
+#define ACPI_BASE_ADDRESS 0x0400
+#define ACPI_BASE_SIZE 0x80
+
+#define GPIO_BASE_ADDRESS 0x0500
+#define GPIO_BASE_SIZE 0x100
+
+#define SMBUS_BASE_ADDRESS 0xefa0
+
+#endif /* _BAYTRAIL_IOMAP_H_ */
--- /dev/null
+/*
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/soc/intel/baytrail/include/soc/irq.h
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _BAYTRAIL_IRQ_H_
+#define _BAYTRAIL_IRQ_H_
+
+#define PIRQA_APIC_IRQ 16
+#define PIRQB_APIC_IRQ 17
+#define PIRQC_APIC_IRQ 18
+#define PIRQD_APIC_IRQ 19
+#define PIRQE_APIC_IRQ 20
+#define PIRQF_APIC_IRQ 21
+#define PIRQG_APIC_IRQ 22
+#define PIRQH_APIC_IRQ 23
+
+/* The below IRQs are for when devices are in ACPI mode */
+#define LPE_DMA0_IRQ 24
+#define LPE_DMA1_IRQ 25
+#define LPE_SSP0_IRQ 26
+#define LPE_SSP1_IRQ 27
+#define LPE_SSP2_IRQ 28
+#define LPE_IPC2HOST_IRQ 29
+#define LPSS_I2C1_IRQ 32
+#define LPSS_I2C2_IRQ 33
+#define LPSS_I2C3_IRQ 34
+#define LPSS_I2C4_IRQ 35
+#define LPSS_I2C5_IRQ 36
+#define LPSS_I2C6_IRQ 37
+#define LPSS_I2C7_IRQ 38
+#define LPSS_HSUART1_IRQ 39
+#define LPSS_HSUART2_IRQ 40
+#define LPSS_SPI_IRQ 41
+#define LPSS_DMA1_IRQ 42
+#define LPSS_DMA2_IRQ 43
+#define SCC_EMMC_IRQ 44
+#define SCC_SDIO_IRQ 46
+#define SCC_SD_IRQ 47
+#define GPIO_NC_IRQ 48
+#define GPIO_SC_IRQ 49
+#define GPIO_SUS_IRQ 50
+/* GPIO direct / dedicated IRQs */
+#define GPIO_S0_DED_IRQ_0 51
+#define GPIO_S0_DED_IRQ_1 52
+#define GPIO_S0_DED_IRQ_2 53
+#define GPIO_S0_DED_IRQ_3 54
+#define GPIO_S0_DED_IRQ_4 55
+#define GPIO_S0_DED_IRQ_5 56
+#define GPIO_S0_DED_IRQ_6 57
+#define GPIO_S0_DED_IRQ_7 58
+#define GPIO_S0_DED_IRQ_8 59
+#define GPIO_S0_DED_IRQ_9 60
+#define GPIO_S0_DED_IRQ_10 61
+#define GPIO_S0_DED_IRQ_11 62
+#define GPIO_S0_DED_IRQ_12 63
+#define GPIO_S0_DED_IRQ_13 64
+#define GPIO_S0_DED_IRQ_14 65
+#define GPIO_S0_DED_IRQ_15 66
+#define GPIO_S5_DED_IRQ_0 67
+#define GPIO_S5_DED_IRQ_1 68
+#define GPIO_S5_DED_IRQ_2 69
+#define GPIO_S5_DED_IRQ_3 70
+#define GPIO_S5_DED_IRQ_4 71
+#define GPIO_S5_DED_IRQ_5 72
+#define GPIO_S5_DED_IRQ_6 73
+#define GPIO_S5_DED_IRQ_7 74
+#define GPIO_S5_DED_IRQ_8 75
+#define GPIO_S5_DED_IRQ_9 76
+#define GPIO_S5_DED_IRQ_10 77
+#define GPIO_S5_DED_IRQ_11 78
+#define GPIO_S5_DED_IRQ_12 79
+#define GPIO_S5_DED_IRQ_13 80
+#define GPIO_S5_DED_IRQ_14 81
+#define GPIO_S5_DED_IRQ_15 82
+/* DIRQs - Two levels of expansion to evaluate to numeric constants for ASL */
+#define _GPIO_S0_DED_IRQ(slot) GPIO_S0_DED_IRQ_##slot
+#define _GPIO_S5_DED_IRQ(slot) GPIO_S5_DED_IRQ_##slot
+#define GPIO_S0_DED_IRQ(slot) _GPIO_S0_DED_IRQ(slot)
+#define GPIO_S5_DED_IRQ(slot) _GPIO_S5_DED_IRQ(slot)
+
+#endif /* _BAYTRAIL_IRQ_H_ */
#define CBMEM_ID_CONSOLE 0x434f4e53
#define CBMEM_ID_NONE 0x00000000
+/**
+ * high_table_reserve() - reserve configuration table in high memory
+ *
+ * This reserves configuration table in high memory.
+ *
+ * @return: always 0
+ */
+int high_table_reserve(void);
+
+/**
+ * high_table_malloc() - allocate configuration table in high memory
+ *
+ * This allocates configuration table in high memory.
+ *
+ * @bytes: size of configuration table to be allocated
+ * @return: pointer to configuration table in high memory
+ */
+void *high_table_malloc(size_t bytes);
+
/**
* write_coreboot_table() - write coreboot table
*
+++ /dev/null
-/*
- * (C) Copyright 2015 Miao Yan <yanmiaobest@gmail.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __FW_CFG__
-#define __FW_CFG__
-
-#define FW_CONTROL_PORT 0x510
-#define FW_DATA_PORT 0x511
-#define FW_DMA_PORT_LOW 0x514
-#define FW_DMA_PORT_HIGH 0x518
-
-#include <linux/list.h>
-
-enum qemu_fwcfg_items {
- FW_CFG_SIGNATURE = 0x00,
- FW_CFG_ID = 0x01,
- FW_CFG_UUID = 0x02,
- FW_CFG_RAM_SIZE = 0x03,
- FW_CFG_NOGRAPHIC = 0x04,
- FW_CFG_NB_CPUS = 0x05,
- FW_CFG_MACHINE_ID = 0x06,
- FW_CFG_KERNEL_ADDR = 0x07,
- FW_CFG_KERNEL_SIZE = 0x08,
- FW_CFG_KERNEL_CMDLINE = 0x09,
- FW_CFG_INITRD_ADDR = 0x0a,
- FW_CFG_INITRD_SIZE = 0x0b,
- FW_CFG_BOOT_DEVICE = 0x0c,
- FW_CFG_NUMA = 0x0d,
- FW_CFG_BOOT_MENU = 0x0e,
- FW_CFG_MAX_CPUS = 0x0f,
- FW_CFG_KERNEL_ENTRY = 0x10,
- FW_CFG_KERNEL_DATA = 0x11,
- FW_CFG_INITRD_DATA = 0x12,
- FW_CFG_CMDLINE_ADDR = 0x13,
- FW_CFG_CMDLINE_SIZE = 0x14,
- FW_CFG_CMDLINE_DATA = 0x15,
- FW_CFG_SETUP_ADDR = 0x16,
- FW_CFG_SETUP_SIZE = 0x17,
- FW_CFG_SETUP_DATA = 0x18,
- FW_CFG_FILE_DIR = 0x19,
- FW_CFG_FILE_FIRST = 0x20,
- FW_CFG_WRITE_CHANNEL = 0x4000,
- FW_CFG_ARCH_LOCAL = 0x8000,
- FW_CFG_INVALID = 0xffff,
-};
-
-enum {
- BIOS_LINKER_LOADER_COMMAND_ALLOCATE = 0x1,
- BIOS_LINKER_LOADER_COMMAND_ADD_POINTER = 0x2,
- BIOS_LINKER_LOADER_COMMAND_ADD_CHECKSUM = 0x3,
-};
-
-enum {
- BIOS_LINKER_LOADER_ALLOC_ZONE_HIGH = 0x1,
- BIOS_LINKER_LOADER_ALLOC_ZONE_FSEG = 0x2,
-};
-
-#define FW_CFG_FILE_SLOTS 0x10
-#define FW_CFG_MAX_ENTRY (FW_CFG_FILE_FIRST + FW_CFG_FILE_SLOTS)
-#define FW_CFG_ENTRY_MASK ~(FW_CFG_WRITE_CHANNEL | FW_CFG_ARCH_LOCAL)
-
-#define FW_CFG_MAX_FILE_PATH 56
-#define BIOS_LINKER_LOADER_FILESZ FW_CFG_MAX_FILE_PATH
-
-#define QEMU_FW_CFG_SIGNATURE (('Q' << 24) | ('E' << 16) | ('M' << 8) | 'U')
-
-#define FW_CFG_DMA_ERROR (1 << 0)
-#define FW_CFG_DMA_READ (1 << 1)
-#define FW_CFG_DMA_SKIP (1 << 2)
-#define FW_CFG_DMA_SELECT (1 << 3)
-
-#define FW_CFG_DMA_ENABLED (1 << 1)
-
-struct fw_cfg_file {
- __be32 size;
- __be16 select;
- __be16 reserved;
- char name[FW_CFG_MAX_FILE_PATH];
-};
-
-struct fw_file {
- struct fw_cfg_file cfg; /* firmware file information */
- unsigned long addr; /* firmware file in-memory address */
- struct list_head list; /* list node to link to fw_list */
-};
-
-struct fw_cfg_dma_access {
- __be32 control;
- __be32 length;
- __be64 address;
-};
-
-struct bios_linker_entry {
- __le32 command;
- union {
- /*
- * COMMAND_ALLOCATE - allocate a table from @alloc.file
- * subject to @alloc.align alignment (must be power of 2)
- * and @alloc.zone (can be HIGH or FSEG) requirements.
- *
- * Must appear exactly once for each file, and before
- * this file is referenced by any other command.
- */
- struct {
- char file[BIOS_LINKER_LOADER_FILESZ];
- __le32 align;
- uint8_t zone;
- } alloc;
-
- /*
- * COMMAND_ADD_POINTER - patch the table (originating from
- * @dest_file) at @pointer.offset, by adding a pointer to the
- * table originating from @src_file. 1,2,4 or 8 byte unsigned
- * addition is used depending on @pointer.size.
- */
- struct {
- char dest_file[BIOS_LINKER_LOADER_FILESZ];
- char src_file[BIOS_LINKER_LOADER_FILESZ];
- __le32 offset;
- uint8_t size;
- } pointer;
-
- /*
- * COMMAND_ADD_CHECKSUM - calculate checksum of the range
- * specified by @cksum_start and @cksum_length fields,
- * and then add the value at @cksum.offset.
- * Checksum simply sums -X for each byte X in the range
- * using 8-bit math.
- */
- struct {
- char file[BIOS_LINKER_LOADER_FILESZ];
- __le32 offset;
- __le32 start;
- __le32 length;
- } cksum;
-
- /* padding */
- char pad[124];
- };
-} __packed;
-
-/**
- * Initialize QEMU fw_cfg interface
- */
-void qemu_fwcfg_init(void);
-
-/**
- * Get system cpu number
- *
- * @return: cpu number in system
- */
-int qemu_fwcfg_online_cpus(void);
-
-#endif
char *mrc_output;
unsigned int mrc_output_len;
ulong table; /* Table pointer from previous loader */
+#ifdef CONFIG_SEABIOS
+ u32 high_table_ptr;
+ u32 high_table_limit;
+#endif
};
#endif
* IRQ N is available to be routed
* @lb_bdf: irq router's PCI bus/device/function number encoding
* @ibase: IBASE register block base address
+ * @actl_8bit: ACTL register width is 8-bit (for ICH series chipset)
+ * @actl_addr: ACTL register offset
*/
struct irq_router {
int config;
u16 irq_mask;
u32 bdf;
u32 ibase;
+ bool actl_8bit;
+ int actl_addr;
};
struct pirq_routing {
obj-y += bios_interrupts.o
obj-$(CONFIG_CMD_BOOTM) += bootm.o
obj-y += cmd_boot.o
-obj-y += coreboot_table.o
+obj-$(CONFIG_SEABIOS) += coreboot_table.o
obj-$(CONFIG_EFI) += efi/
obj-y += e820.o
obj-y += gcc.o
obj-y += sfi.o
obj-$(CONFIG_GENERATE_SMBIOS_TABLE) += smbios.o
obj-y += string.o
-ifndef CONFIG_QEMU_ACPI_TABLE
+ifndef CONFIG_QEMU
obj-$(CONFIG_GENERATE_ACPI_TABLE) += acpi_table.o
endif
obj-y += tables.o
* Based on acpi.c from coreboot
*
* Copyright (C) 2015, Saket Sinha <saket.sinha89@gmail.com>
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <cpu.h>
#include <dm.h>
#include <dm/uclass-internal.h>
-#include <dm/lists.h>
#include <asm/acpi_table.h>
-#include <asm/cpu.h>
-#include <asm/ioapic.h>
+#include <asm/io.h>
#include <asm/lapic.h>
#include <asm/tables.h>
-#include <asm/pci.h>
/*
- * IASL compiles the dsdt entries and
- * writes the hex values to AmlCode array.
- * CamelCase cannot be handled here.
+ * IASL compiles the dsdt entries and writes the hex values
+ * to a C array AmlCode[] (see dsdt.c).
*/
extern const unsigned char AmlCode[];
+static void acpi_write_rsdp(struct acpi_rsdp *rsdp, struct acpi_rsdt *rsdt,
+ struct acpi_xsdt *xsdt)
+{
+ memset(rsdp, 0, sizeof(struct acpi_rsdp));
+
+ memcpy(rsdp->signature, RSDP_SIG, 8);
+ memcpy(rsdp->oem_id, OEM_ID, 6);
+
+ rsdp->length = sizeof(struct acpi_rsdp);
+ rsdp->rsdt_address = (u32)rsdt;
+
+ /*
+ * Revision: ACPI 1.0: 0, ACPI 2.0/3.0/4.0: 2
+ *
+ * Some OSes expect an XSDT to be present for RSD PTR revisions >= 2.
+ * If we don't have an ACPI XSDT, force ACPI 1.0 (and thus RSD PTR
+ * revision 0)
+ */
+ if (xsdt == NULL) {
+ rsdp->revision = ACPI_RSDP_REV_ACPI_1_0;
+ } else {
+ rsdp->xsdt_address = (u64)(u32)xsdt;
+ rsdp->revision = ACPI_RSDP_REV_ACPI_2_0;
+ }
+
+ /* Calculate checksums */
+ rsdp->checksum = table_compute_checksum((void *)rsdp, 20);
+ rsdp->ext_checksum = table_compute_checksum((void *)rsdp,
+ sizeof(struct acpi_rsdp));
+}
+
+void acpi_fill_header(struct acpi_table_header *header, char *signature)
+{
+ memcpy(header->signature, signature, 4);
+ memcpy(header->oem_id, OEM_ID, 6);
+ memcpy(header->oem_table_id, OEM_TABLE_ID, 8);
+ memcpy(header->aslc_id, ASLC_ID, 4);
+}
+
+static void acpi_write_rsdt(struct acpi_rsdt *rsdt)
+{
+ struct acpi_table_header *header = &(rsdt->header);
+
+ /* Fill out header fields */
+ acpi_fill_header(header, "RSDT");
+ header->length = sizeof(struct acpi_rsdt);
+ header->revision = 1;
+
+ /* Entries are filled in later, we come with an empty set */
+
+ /* Fix checksum */
+ header->checksum = table_compute_checksum((void *)rsdt,
+ sizeof(struct acpi_rsdt));
+}
+
+static void acpi_write_xsdt(struct acpi_xsdt *xsdt)
+{
+ struct acpi_table_header *header = &(xsdt->header);
+
+ /* Fill out header fields */
+ acpi_fill_header(header, "XSDT");
+ header->length = sizeof(struct acpi_xsdt);
+ header->revision = 1;
+
+ /* Entries are filled in later, we come with an empty set */
+
+ /* Fix checksum */
+ header->checksum = table_compute_checksum((void *)xsdt,
+ sizeof(struct acpi_xsdt));
+}
+
/**
-* Add an ACPI table to the RSDT (and XSDT) structure, recalculate length
-* and checksum.
-*/
+ * Add an ACPI table to the RSDT (and XSDT) structure, recalculate length
+ * and checksum.
+ */
static void acpi_add_table(struct acpi_rsdp *rsdp, void *table)
{
int i, entries_num;
}
if (i >= entries_num) {
- debug("ACPI: Error: too many tables.\n");
+ debug("ACPI: Error: too many tables\n");
return;
}
rsdt->entry[i] = (u32)table;
/* Fix RSDT length or the kernel will assume invalid entries */
- rsdt->header.length = sizeof(acpi_header_t) + (sizeof(u32) * (i + 1));
+ rsdt->header.length = sizeof(struct acpi_table_header) +
+ (sizeof(u32) * (i + 1));
/* Re-calculate checksum */
rsdt->header.checksum = 0;
rsdt->header.checksum = table_compute_checksum((u8 *)rsdt,
- rsdt->header.length);
+ rsdt->header.length);
/*
* And now the same thing for the XSDT. We use the same index as for
xsdt->entry[i] = (u64)(u32)table;
/* Fix XSDT length */
- xsdt->header.length = sizeof(acpi_header_t) +
- (sizeof(u64) * (i + 1));
+ xsdt->header.length = sizeof(struct acpi_table_header) +
+ (sizeof(u64) * (i + 1));
/* Re-calculate checksum */
xsdt->header.checksum = 0;
}
}
+static void acpi_create_facs(struct acpi_facs *facs)
+{
+ memset((void *)facs, 0, sizeof(struct acpi_facs));
+
+ memcpy(facs->signature, "FACS", 4);
+ facs->length = sizeof(struct acpi_facs);
+ facs->hardware_signature = 0;
+ facs->firmware_waking_vector = 0;
+ facs->global_lock = 0;
+ facs->flags = 0;
+ facs->x_firmware_waking_vector_l = 0;
+ facs->x_firmware_waking_vector_h = 0;
+ facs->version = 1;
+}
+
static int acpi_create_madt_lapic(struct acpi_madt_lapic *lapic,
- u8 cpu, u8 apic)
+ u8 cpu, u8 apic)
{
- lapic->type = LOCALAPIC; /* Local APIC structure */
+ lapic->type = ACPI_APIC_LAPIC;
lapic->length = sizeof(struct acpi_madt_lapic);
- lapic->flags = LOCAL_APIC_FLAG_ENABLED; /* Processor/LAPIC enabled */
+ lapic->flags = LOCAL_APIC_FLAG_ENABLED;
lapic->processor_id = cpu;
lapic->apic_id = apic;
return lapic->length;
}
-unsigned long acpi_create_madt_lapics(unsigned long current)
+int acpi_create_madt_lapics(u32 current)
{
struct udevice *dev;
+ int length = 0;
for (uclass_find_first_device(UCLASS_CPU, &dev);
dev;
uclass_find_next_device(&dev)) {
struct cpu_platdata *plat = dev_get_parent_platdata(dev);
- current += acpi_create_madt_lapic(
+ length += acpi_create_madt_lapic(
(struct acpi_madt_lapic *)current,
plat->cpu_id, plat->cpu_id);
- }
- return current;
+ current += length;
+ }
+
+ return length;
}
-int acpi_create_madt_ioapic(struct acpi_madt_ioapic *ioapic, u8 id, u32 addr,
- u32 gsi_base)
+int acpi_create_madt_ioapic(struct acpi_madt_ioapic *ioapic, u8 id,
+ u32 addr, u32 gsi_base)
{
- ioapic->type = IOAPIC;
+ ioapic->type = ACPI_APIC_IOAPIC;
ioapic->length = sizeof(struct acpi_madt_ioapic);
ioapic->reserved = 0x00;
ioapic->gsi_base = gsi_base;
}
int acpi_create_madt_irqoverride(struct acpi_madt_irqoverride *irqoverride,
- u8 bus, u8 source, u32 gsirq, u16 flags)
+ u8 bus, u8 source, u32 gsirq, u16 flags)
{
- irqoverride->type = IRQSOURCEOVERRIDE;
+ irqoverride->type = ACPI_APIC_IRQ_SRC_OVERRIDE;
irqoverride->length = sizeof(struct acpi_madt_irqoverride);
irqoverride->bus = bus;
irqoverride->source = source;
}
int acpi_create_madt_lapic_nmi(struct acpi_madt_lapic_nmi *lapic_nmi,
- u8 cpu, u16 flags, u8 lint)
+ u8 cpu, u16 flags, u8 lint)
{
- lapic_nmi->type = LOCALNMITYPE;
+ lapic_nmi->type = ACPI_APIC_LAPIC_NMI;
lapic_nmi->length = sizeof(struct acpi_madt_lapic_nmi);
lapic_nmi->flags = flags;
lapic_nmi->processor_id = cpu;
return lapic_nmi->length;
}
-static void fill_header(acpi_header_t *header, char *signature, int length)
-{
- memcpy(header->signature, signature, length);
- memcpy(header->oem_id, OEM_ID, 6);
- memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
- memcpy(header->asl_compiler_id, ASLC, 4);
-}
-
static void acpi_create_madt(struct acpi_madt *madt)
{
- acpi_header_t *header = &(madt->header);
- unsigned long current = (unsigned long)madt + sizeof(struct acpi_madt);
+ struct acpi_table_header *header = &(madt->header);
+ u32 current = (u32)madt + sizeof(struct acpi_madt);
memset((void *)madt, 0, sizeof(struct acpi_madt));
/* Fill out header fields */
- fill_header(header, "APIC", 4);
+ acpi_fill_header(header, "APIC");
header->length = sizeof(struct acpi_madt);
-
- /* ACPI 1.0/2.0: 1, ACPI 3.0: 2, ACPI 4.0: 3 */
- header->revision = ACPI_REV_ACPI_2_0;
+ header->revision = 4;
madt->lapic_addr = LAPIC_DEFAULT_BASE;
- madt->flags = PCAT_COMPAT;
+ madt->flags = ACPI_MADT_PCAT_COMPAT;
current = acpi_fill_madt(current);
/* (Re)calculate length and checksum */
- header->length = current - (unsigned long)madt;
+ header->length = current - (u32)madt;
header->checksum = table_compute_checksum((void *)madt, header->length);
}
static int acpi_create_mcfg_mmconfig(struct acpi_mcfg_mmconfig *mmconfig,
- u32 base, u16 seg_nr, u8 start, u8 end)
+ u32 base, u16 seg_nr, u8 start, u8 end)
{
memset(mmconfig, 0, sizeof(*mmconfig));
- mmconfig->base_address = base;
- mmconfig->base_reserved = 0;
+ mmconfig->base_address_l = base;
+ mmconfig->base_address_h = 0;
mmconfig->pci_segment_group_number = seg_nr;
mmconfig->start_bus_number = start;
mmconfig->end_bus_number = end;
return sizeof(struct acpi_mcfg_mmconfig);
}
-static unsigned long acpi_fill_mcfg(unsigned long current)
+static u32 acpi_fill_mcfg(u32 current)
{
current += acpi_create_mcfg_mmconfig
((struct acpi_mcfg_mmconfig *)current,
- CONFIG_PCIE_ECAM_BASE, 0x0, 0x0, 255);
+ CONFIG_PCIE_ECAM_BASE, 0x0, 0x0, 255);
return current;
}
/* MCFG is defined in the PCI Firmware Specification 3.0 */
static void acpi_create_mcfg(struct acpi_mcfg *mcfg)
{
- acpi_header_t *header = &(mcfg->header);
- unsigned long current = (unsigned long)mcfg + sizeof(struct acpi_mcfg);
+ struct acpi_table_header *header = &(mcfg->header);
+ u32 current = (u32)mcfg + sizeof(struct acpi_mcfg);
memset((void *)mcfg, 0, sizeof(struct acpi_mcfg));
/* Fill out header fields */
- fill_header(header, "MCFG", 4);
+ acpi_fill_header(header, "MCFG");
header->length = sizeof(struct acpi_mcfg);
-
- /* ACPI 1.0/2.0: 1, ACPI 3.0: 2, ACPI 4.0: 3 */
- header->revision = ACPI_REV_ACPI_2_0;
+ header->revision = 1;
current = acpi_fill_mcfg(current);
/* (Re)calculate length and checksum */
- header->length = current - (unsigned long)mcfg;
+ header->length = current - (u32)mcfg;
header->checksum = table_compute_checksum((void *)mcfg, header->length);
}
-static void acpi_create_facs(struct acpi_facs *facs)
-{
- memset((void *)facs, 0, sizeof(struct acpi_facs));
-
- memcpy(facs->signature, "FACS", 4);
- facs->length = sizeof(struct acpi_facs);
- facs->hardware_signature = 0;
- facs->firmware_waking_vector = 0;
- facs->global_lock = 0;
- facs->flags = 0;
- facs->x_firmware_waking_vector_l = 0;
- facs->x_firmware_waking_vector_h = 0;
- facs->version = 1; /* ACPI 1.0: 0, ACPI 2.0/3.0: 1, ACPI 4.0: 2 */
-}
-
-static void acpi_write_rsdt(struct acpi_rsdt *rsdt)
-{
- acpi_header_t *header = &(rsdt->header);
-
- /* Fill out header fields */
- fill_header(header, "RSDT", 4);
- header->length = sizeof(struct acpi_rsdt);
-
- /* ACPI 1.0/2.0: 1, ACPI 3.0: 2, ACPI 4.0: 3 */
- header->revision = ACPI_REV_ACPI_2_0;
-
- /* Entries are filled in later, we come with an empty set */
-
- /* Fix checksum */
- header->checksum = table_compute_checksum((void *)rsdt,
- sizeof(struct acpi_rsdt));
-}
-
-static void acpi_write_xsdt(struct acpi_xsdt *xsdt)
+static void enter_acpi_mode(int pm1_cnt)
{
- acpi_header_t *header = &(xsdt->header);
-
- /* Fill out header fields */
- fill_header(header, "XSDT", 4);
- header->length = sizeof(struct acpi_xsdt);
-
- /* ACPI 1.0/2.0: 1, ACPI 3.0: 2, ACPI 4.0: 3 */
- header->revision = ACPI_REV_ACPI_2_0;
-
- /* Entries are filled in later, we come with an empty set */
-
- /* Fix checksum */
- header->checksum = table_compute_checksum((void *)xsdt,
- sizeof(struct acpi_xsdt));
-}
-
-static void acpi_write_rsdp(struct acpi_rsdp *rsdp, struct acpi_rsdt *rsdt,
- struct acpi_xsdt *xsdt)
-{
- memset(rsdp, 0, sizeof(struct acpi_rsdp));
-
- memcpy(rsdp->signature, RSDP_SIG, 8);
- memcpy(rsdp->oem_id, OEM_ID, 6);
-
- rsdp->length = sizeof(struct acpi_rsdp);
- rsdp->rsdt_address = (u32)rsdt;
-
/*
- * Revision: ACPI 1.0: 0, ACPI 2.0/3.0/4.0: 2
- *
- * Some OSes expect an XSDT to be present for RSD PTR revisions >= 2.
- * If we don't have an ACPI XSDT, force ACPI 1.0 (and thus RSD PTR
- * revision 0)
- */
- if (xsdt == NULL) {
- rsdp->revision = ACPI_RSDP_REV_ACPI_1_0;
- } else {
- rsdp->xsdt_address = (u64)(u32)xsdt;
- rsdp->revision = ACPI_RSDP_REV_ACPI_2_0;
- }
-
- /* Calculate checksums */
- rsdp->checksum = table_compute_checksum((void *)rsdp, 20);
- rsdp->ext_checksum = table_compute_checksum((void *)rsdp,
- sizeof(struct acpi_rsdp));
-}
-
-static void acpi_create_ssdt_generator(acpi_header_t *ssdt,
- const char *oem_table_id)
-{
- unsigned long current = (unsigned long)ssdt + sizeof(acpi_header_t);
-
- memset((void *)ssdt, 0, sizeof(acpi_header_t));
-
- memcpy(&ssdt->signature, "SSDT", 4);
- /* Access size in ACPI 2.0c/3.0/4.0/5.0 */
- ssdt->revision = ACPI_REV_ACPI_3_0;
- memcpy(&ssdt->oem_id, OEM_ID, 6);
- memcpy(&ssdt->oem_table_id, oem_table_id, 8);
- ssdt->oem_revision = OEM_REVISION;
- memcpy(&ssdt->asl_compiler_id, ASLC, 4);
- ssdt->asl_compiler_revision = ASL_COMPILER_REVISION;
- ssdt->length = sizeof(acpi_header_t);
-
- /* (Re)calculate length and checksum */
- ssdt->length = current - (unsigned long)ssdt;
- ssdt->checksum = table_compute_checksum((void *)ssdt, ssdt->length);
+ * PM1_CNT register bit0 selects the power management event to be
+ * either an SCI or SMI interrupt. When this bit is set, then power
+ * management events will generate an SCI interrupt. When this bit
+ * is reset power management events will generate an SMI interrupt.
+ *
+ * Per ACPI spec, it is the responsibility of the hardware to set
+ * or reset this bit. OSPM always preserves this bit position.
+ *
+ * U-Boot does not support SMI. And we don't have plan to support
+ * anything running in SMM within U-Boot. To create a legacy-free
+ * system, and expose ourselves to OSPM as working under ACPI mode
+ * already, turn this bit on.
+ */
+ outw(PM1_CNT_SCI_EN, pm1_cnt);
}
/*
* QEMU's version of write_acpi_tables is defined in
- * arch/x86/cpu/qemu/fw_cfg.c
+ * arch/x86/cpu/qemu/acpi_table.c
*/
u32 write_acpi_tables(u32 start)
{
struct acpi_rsdt *rsdt;
struct acpi_xsdt *xsdt;
struct acpi_facs *facs;
- acpi_header_t *dsdt;
+ struct acpi_table_header *dsdt;
struct acpi_fadt *fadt;
struct acpi_mcfg *mcfg;
struct acpi_madt *madt;
- acpi_header_t *ssdt;
current = start;
- /* Align ACPI tables to 16byte */
+ /* Align ACPI tables to 16 byte */
current = ALIGN(current, 16);
- debug("ACPI: Writing ACPI tables at %lx.\n", start);
+ debug("ACPI: Writing ACPI tables at %x\n", start);
/* We need at least an RSDP and an RSDT Table */
rsdp = (struct acpi_rsdp *)current;
current = ALIGN(current, 16);
xsdt = (struct acpi_xsdt *)current;
current += sizeof(struct acpi_xsdt);
- current = ALIGN(current, 16);
+ /*
+ * Per ACPI spec, the FACS table address must be aligned to a 64 byte
+ * boundary (Windows checks this, but Linux does not).
+ */
+ current = ALIGN(current, 64);
/* clear all table memory */
memset((void *)start, 0, current - start);
acpi_create_facs(facs);
debug("ACPI: * DSDT\n");
- dsdt = (acpi_header_t *)current;
- memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
- if (dsdt->length >= sizeof(acpi_header_t)) {
- current += sizeof(acpi_header_t);
- memcpy((char *)current,
- (char *)&AmlCode + sizeof(acpi_header_t),
- dsdt->length - sizeof(acpi_header_t));
- current += dsdt->length - sizeof(acpi_header_t);
-
- /* (Re)calculate length and checksum */
- dsdt->length = current - (unsigned long)dsdt;
- dsdt->checksum = 0;
- dsdt->checksum = table_compute_checksum((void *)dsdt,
- dsdt->length);
- }
+ dsdt = (struct acpi_table_header *)current;
+ memcpy(dsdt, &AmlCode, sizeof(struct acpi_table_header));
+ current += sizeof(struct acpi_table_header);
+ memcpy((char *)current,
+ (char *)&AmlCode + sizeof(struct acpi_table_header),
+ dsdt->length - sizeof(struct acpi_table_header));
+ current += dsdt->length - sizeof(struct acpi_table_header);
current = ALIGN(current, 16);
debug("ACPI: * FADT\n");
acpi_create_fadt(fadt, facs, dsdt);
acpi_add_table(rsdp, fadt);
- debug("ACPI: * MCFG\n");
- mcfg = (struct acpi_mcfg *)current;
- acpi_create_mcfg(mcfg);
- if (mcfg->header.length > sizeof(struct acpi_mcfg)) {
- current += mcfg->header.length;
- current = ALIGN(current, 16);
- acpi_add_table(rsdp, mcfg);
- }
-
debug("ACPI: * MADT\n");
madt = (struct acpi_madt *)current;
acpi_create_madt(madt);
- if (madt->header.length > sizeof(struct acpi_madt)) {
- current += madt->header.length;
- acpi_add_table(rsdp, madt);
- }
+ current += madt->header.length;
+ acpi_add_table(rsdp, madt);
current = ALIGN(current, 16);
- debug("ACPI: * SSDT\n");
- ssdt = (acpi_header_t *)current;
- acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR);
- if (ssdt->length > sizeof(acpi_header_t)) {
- current += ssdt->length;
- acpi_add_table(rsdp, ssdt);
- current = ALIGN(current, 16);
- }
+ debug("ACPI: * MCFG\n");
+ mcfg = (struct acpi_mcfg *)current;
+ acpi_create_mcfg(mcfg);
+ current += mcfg->header.length;
+ acpi_add_table(rsdp, mcfg);
+ current = ALIGN(current, 16);
+
+ debug("current = %x\n", current);
- debug("current = %lx\n", current);
+ debug("ACPI: done\n");
- debug("ACPI: done.\n");
+ /*
+ * Other than waiting for OSPM to request us to switch to ACPI mode,
+ * do it by ourselves, since SMI will not be triggered.
+ */
+ enter_acpi_mode(fadt->pm1a_cnt_blk);
return current;
}
#define COMMAND_LINE_OFFSET 0x9000
-/*
- * Implement a weak default function for boards that optionally
- * need to clean up the system before jumping to the kernel.
- */
-__weak void board_final_cleanup(void)
-{
-}
-
void bootm_announce_and_cleanup(void)
{
printf("\nStarting kernel ...\n\n");
#ifdef CONFIG_BOOTSTAGE_REPORT
bootstage_report();
#endif
- board_final_cleanup();
}
#if defined(CONFIG_OF_LIBFDT) && !defined(CONFIG_OF_NO_KERNEL)
#include <asm/coreboot_tables.h>
#include <asm/e820.h>
+DECLARE_GLOBAL_DATA_PTR;
+
+int high_table_reserve(void)
+{
+ /* adjust stack pointer to reserve space for configuration tables */
+ gd->arch.high_table_limit = gd->start_addr_sp;
+ gd->start_addr_sp -= CONFIG_HIGH_TABLE_SIZE;
+ gd->arch.high_table_ptr = gd->start_addr_sp;
+
+ /* clear the memory */
+ memset((void *)gd->arch.high_table_ptr, 0, CONFIG_HIGH_TABLE_SIZE);
+
+ gd->start_addr_sp &= ~0xf;
+
+ return 0;
+}
+
+void *high_table_malloc(size_t bytes)
+{
+ u32 new_ptr;
+ void *ptr;
+
+ new_ptr = gd->arch.high_table_ptr + bytes;
+ if (new_ptr >= gd->arch.high_table_limit)
+ return NULL;
+ ptr = (void *)gd->arch.high_table_ptr;
+ gd->arch.high_table_ptr = new_ptr;
+
+ return ptr;
+}
+
/**
* cb_table_init() - initialize a coreboot table header
*
#include <pci.h>
#include <asm/pci.h>
#include <asm/pirq_routing.h>
-#include <asm/tables.h>
static bool irq_already_routed[16];
{
struct irq_routing_table *rom_rt;
- /* Fix up the table checksum */
- rt->checksum = table_compute_checksum(rt, rt->size);
-
/* Align the table to be 16 byte aligned */
addr = ALIGN(addr, 16);
memset(t, 0, sizeof(struct smbios_type1));
fill_smbios_header(t, SMBIOS_SYSTEM_INFORMATION, len, handle);
- t->manufacturer = smbios_add_string(t->eos, CONFIG_SYS_VENDOR);
- t->product_name = smbios_add_string(t->eos, CONFIG_SYS_BOARD);
+ t->manufacturer = smbios_add_string(t->eos, CONFIG_SMBIOS_MANUFACTURER);
+ t->product_name = smbios_add_string(t->eos, CONFIG_SMBIOS_PRODUCT_NAME);
len = t->length + smbios_string_table_len(t->eos);
*current += len;
memset(t, 0, sizeof(struct smbios_type2));
fill_smbios_header(t, SMBIOS_BOARD_INFORMATION, len, handle);
- t->manufacturer = smbios_add_string(t->eos, CONFIG_SYS_VENDOR);
- t->product_name = smbios_add_string(t->eos, CONFIG_SYS_BOARD);
+ t->manufacturer = smbios_add_string(t->eos, CONFIG_SMBIOS_MANUFACTURER);
+ t->product_name = smbios_add_string(t->eos, CONFIG_SMBIOS_PRODUCT_NAME);
t->feature_flags = SMBIOS_BOARD_FEATURE_HOSTING;
t->board_type = SMBIOS_BOARD_MOTHERBOARD;
memset(t, 0, sizeof(struct smbios_type3));
fill_smbios_header(t, SMBIOS_SYSTEM_ENCLOSURE, len, handle);
- t->manufacturer = smbios_add_string(t->eos, CONFIG_SYS_VENDOR);
+ t->manufacturer = smbios_add_string(t->eos, CONFIG_SMBIOS_MANUFACTURER);
t->chassis_type = SMBIOS_ENCLOSURE_DESKTOP;
t->bootup_state = SMBIOS_STATE_SAFE;
t->power_supply_state = SMBIOS_STATE_SAFE;
#ifdef CONFIG_SEABIOS
table_size = rom_table_end - rom_table_start;
- high_table = (u32)memalign(ROM_TABLE_ALIGN, table_size);
+ high_table = (u32)high_table_malloc(table_size);
if (high_table) {
- memset((void *)high_table, 0, table_size);
table_write_funcs[i](high_table);
cfg_tables[i].start = high_table;
--- /dev/null
+if TARGET_SAMA5D2_PTC
+
+config SYS_BOARD
+ default "sama5d2_ptc"
+
+config SYS_VENDOR
+ default "atmel"
+
+config SYS_SOC
+ default "at91"
+
+config SYS_CONFIG_NAME
+ default "sama5d2_ptc"
+
+endif
--- /dev/null
+SAMA5D2 PTC Engineering BOARD
+M: Wenyou Yang <wenyou.yang@atmel.com>
+S: Maintained
+F: board/atmel/sama5d2_ptc/
+F: include/configs/sama5d2_ptc.h
+F: configs/sama5d2_ptc_spiflash_defconfig
+F: configs/sama5d2_ptc_nandflash_defconfig
--- /dev/null
+#
+# Copyright (C) 2016 Atmel
+# Wenyou Yang <wenyou.yang@atmel.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += sama5d2_ptc.o
--- /dev/null
+/*
+ * Copyright (C) 2016 Atmel
+ * Wenyou.Yang <wenyou.yang@atmel.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <atmel_hlcdc.h>
+#include <lcd.h>
+#include <mmc.h>
+#include <net.h>
+#include <netdev.h>
+#include <spi.h>
+#include <version.h>
+#include <asm/io.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/atmel_pio4.h>
+#include <asm/arch/atmel_mpddrc.h>
+#include <asm/arch/atmel_usba_udc.h>
+#include <asm/arch/atmel_sdhci.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/sama5_sfr.h>
+#include <asm/arch/sama5d2.h>
+#include <asm/arch/sama5d3_smc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ return bus == 0 && cs == 0;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+ atmel_pio4_set_pio_output(AT91_PIO_PORTA, 17, 0);
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+ atmel_pio4_set_pio_output(AT91_PIO_PORTA, 17, 1);
+}
+
+static void board_spi0_hw_init(void)
+{
+ atmel_pio4_set_a_periph(AT91_PIO_PORTA, 14, 0);
+ atmel_pio4_set_a_periph(AT91_PIO_PORTA, 15, 0);
+ atmel_pio4_set_a_periph(AT91_PIO_PORTA, 16, 0);
+
+ atmel_pio4_set_pio_output(AT91_PIO_PORTA, 17, 1);
+
+ at91_periph_clk_enable(ATMEL_ID_SPI0);
+}
+
+static void board_nand_hw_init(void)
+{
+ struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+ struct atmel_sfr *sfr = (struct atmel_sfr *)ATMEL_BASE_SFR;
+
+ at91_periph_clk_enable(ATMEL_ID_HSMC);
+
+ writel(AT91_SFR_EBICFG_DRIVE0_HIGH |
+ AT91_SFR_EBICFG_PULL0_NONE |
+ AT91_SFR_EBICFG_DRIVE1_HIGH |
+ AT91_SFR_EBICFG_PULL1_NONE, &sfr->ebicfg);
+
+ /* Configure SMC CS3 for NAND */
+ writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) |
+ AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(1),
+ &smc->cs[3].setup);
+ writel(AT91_SMC_PULSE_NWE(2) | AT91_SMC_PULSE_NCS_WR(3) |
+ AT91_SMC_PULSE_NRD(2) | AT91_SMC_PULSE_NCS_RD(3),
+ &smc->cs[3].pulse);
+ writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
+ &smc->cs[3].cycle);
+ writel(AT91_SMC_TIMINGS_TCLR(2) | AT91_SMC_TIMINGS_TADL(7) |
+ AT91_SMC_TIMINGS_TAR(2) | AT91_SMC_TIMINGS_TRR(3) |
+ AT91_SMC_TIMINGS_TWB(7) | AT91_SMC_TIMINGS_RBNSEL(3) |
+ AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings);
+ writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+ AT91_SMC_MODE_EXNW_DISABLE |
+ AT91_SMC_MODE_DBW_8 |
+ AT91_SMC_MODE_TDF_CYCLE(3),
+ &smc->cs[3].mode);
+
+ atmel_pio4_set_f_periph(AT91_PIO_PORTA, 0, 0); /* D0 */
+ atmel_pio4_set_f_periph(AT91_PIO_PORTA, 1, 0); /* D1 */
+ atmel_pio4_set_f_periph(AT91_PIO_PORTA, 2, 0); /* D2 */
+ atmel_pio4_set_f_periph(AT91_PIO_PORTA, 3, 0); /* D3 */
+ atmel_pio4_set_f_periph(AT91_PIO_PORTA, 4, 0); /* D4 */
+ atmel_pio4_set_f_periph(AT91_PIO_PORTA, 5, 0); /* D5 */
+ atmel_pio4_set_f_periph(AT91_PIO_PORTA, 6, 0); /* D6 */
+ atmel_pio4_set_f_periph(AT91_PIO_PORTA, 7, 0); /* D7 */
+ atmel_pio4_set_f_periph(AT91_PIO_PORTA, 12, 0); /* RE */
+ atmel_pio4_set_f_periph(AT91_PIO_PORTA, 8, 0); /* WE */
+ atmel_pio4_set_f_periph(AT91_PIO_PORTA, 9, 1); /* NCS */
+ atmel_pio4_set_f_periph(AT91_PIO_PORTA, 21, 1); /* RDY */
+ atmel_pio4_set_f_periph(AT91_PIO_PORTA, 10, 1); /* ALE */
+ atmel_pio4_set_f_periph(AT91_PIO_PORTA, 11, 1); /* CLE */
+}
+
+static void board_usb_hw_init(void)
+{
+ atmel_pio4_set_pio_output(AT91_PIO_PORTA, 28, 1);
+}
+
+static void board_gmac_hw_init(void)
+{
+ atmel_pio4_set_f_periph(AT91_PIO_PORTB, 14, 0); /* GTXCK */
+ atmel_pio4_set_f_periph(AT91_PIO_PORTB, 15, 0); /* GTXEN */
+ atmel_pio4_set_f_periph(AT91_PIO_PORTB, 16, 0); /* GRXDV */
+ atmel_pio4_set_f_periph(AT91_PIO_PORTB, 17, 0); /* GRXER */
+ atmel_pio4_set_f_periph(AT91_PIO_PORTB, 18, 0); /* GRX0 */
+ atmel_pio4_set_f_periph(AT91_PIO_PORTB, 19, 0); /* GRX1 */
+ atmel_pio4_set_f_periph(AT91_PIO_PORTB, 20, 0); /* GTX0 */
+ atmel_pio4_set_f_periph(AT91_PIO_PORTB, 21, 0); /* GTX1 */
+ atmel_pio4_set_f_periph(AT91_PIO_PORTB, 22, 0); /* GMDC */
+ atmel_pio4_set_f_periph(AT91_PIO_PORTB, 23, 0); /* GMDIO */
+
+ at91_periph_clk_enable(ATMEL_ID_GMAC);
+}
+
+static void board_uart0_hw_init(void)
+{
+ atmel_pio4_set_c_periph(AT91_PIO_PORTB, 26, 1); /* URXD0 */
+ atmel_pio4_set_c_periph(AT91_PIO_PORTB, 27, 0); /* UTXD0 */
+
+ at91_periph_clk_enable(CONFIG_USART_ID);
+}
+
+int board_early_init_f(void)
+{
+ at91_periph_clk_enable(ATMEL_ID_PIOA);
+ at91_periph_clk_enable(ATMEL_ID_PIOB);
+ at91_periph_clk_enable(ATMEL_ID_PIOC);
+ at91_periph_clk_enable(ATMEL_ID_PIOD);
+
+ board_uart0_hw_init();
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+#ifdef CONFIG_ATMEL_SPI
+ board_spi0_hw_init();
+#endif
+#ifdef CONFIG_NAND_ATMEL
+ board_nand_hw_init();
+#endif
+#ifdef CONFIG_MACB
+ board_gmac_hw_init();
+#endif
+#ifdef CONFIG_CMD_USB
+ board_usb_hw_init();
+#endif
+#ifdef CONFIG_USB_GADGET_ATMEL_USBA
+ at91_udp_hw_init();
+#endif
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+ CONFIG_SYS_SDRAM_SIZE);
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+
+#ifdef CONFIG_MACB
+ rc = macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC, 0x00);
+ if (rc)
+ printf("GMAC register failed\n");
+#endif
+
+#ifdef CONFIG_USB_GADGET_ATMEL_USBA
+ usba_udc_probe(&pdata);
+#ifdef CONFIG_USB_ETH_RNDIS
+ usb_eth_initialize(bis);
+#endif
+#endif
+
+ return rc;
+}
+
+/* SPL */
+#ifdef CONFIG_SPL_BUILD
+void spl_board_init(void)
+{
+#ifdef CONFIG_SYS_USE_SERIALFLASH
+ board_spi0_hw_init();
+#endif
+
+#ifdef CONFIG_SYS_USE_NANDFLASH
+ board_nand_hw_init();
+#endif
+}
+
+static void ddrc_conf(struct atmel_mpddrc_config *ddrc)
+{
+ ddrc->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR3_SDRAM);
+
+ ddrc->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
+ ATMEL_MPDDRC_CR_NR_ROW_14 |
+ ATMEL_MPDDRC_CR_CAS_DDR_CAS5 |
+ ATMEL_MPDDRC_CR_DIC_DS |
+ ATMEL_MPDDRC_CR_DIS_DLL |
+ ATMEL_MPDDRC_CR_NB_8BANKS |
+ ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
+ ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
+
+ ddrc->rtr = 0x511;
+
+ ddrc->tpr0 = ((6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET) |
+ (3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET) |
+ (4 << ATMEL_MPDDRC_TPR0_TWR_OFFSET) |
+ (9 << ATMEL_MPDDRC_TPR0_TRC_OFFSET) |
+ (3 << ATMEL_MPDDRC_TPR0_TRP_OFFSET) |
+ (4 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET) |
+ (4 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET) |
+ (4 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET));
+
+ ddrc->tpr1 = ((27 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET) |
+ (29 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET) |
+ (0 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET) |
+ (3 << ATMEL_MPDDRC_TPR1_TXP_OFFSET));
+
+ ddrc->tpr2 = ((0 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET) |
+ (0 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET) |
+ (0 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET) |
+ (4 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET) |
+ (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET));
+}
+
+void mem_init(void)
+{
+ struct atmel_mpddr *mpddrc = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC;
+ struct atmel_mpddrc_config ddrc_config;
+ u32 reg;
+
+ ddrc_conf(&ddrc_config);
+
+ at91_periph_clk_enable(ATMEL_ID_MPDDRC);
+ at91_system_clk_enable(AT91_PMC_DDR);
+
+ reg = readl(&mpddrc->io_calibr);
+ reg &= ~ATMEL_MPDDRC_IO_CALIBR_RDIV;
+ reg |= ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_55;
+ reg &= ~ATMEL_MPDDRC_IO_CALIBR_TZQIO;
+ reg |= ATMEL_MPDDRC_IO_CALIBR_TZQIO_(100);
+ writel(reg, &mpddrc->io_calibr);
+
+ writel(ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_TWO_CYCLE,
+ &mpddrc->rd_data_path);
+
+ ddr3_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddrc_config);
+
+ writel(0x3, &mpddrc->cal_mr4);
+ writel(64, &mpddrc->tim_cal);
+}
+
+void at91_pmc_init(void)
+{
+ at91_plla_init(AT91_PMC_PLLAR_29 |
+ AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
+ AT91_PMC_PLLXR_MUL(82) |
+ AT91_PMC_PLLXR_DIV(1));
+
+ at91_pllicpr_init(0);
+
+ at91_mck_init(AT91_PMC_MCKR_H32MXDIV |
+ AT91_PMC_MCKR_PLLADIV_2 |
+ AT91_PMC_MCKR_MDIV_3 |
+ AT91_PMC_MCKR_CSS_PLLA);
+}
+#endif
atmel_pio4_set_a_periph(AT91_PIO_PORTA, 9, 0); /* SDMMC0_DAT7 */
atmel_pio4_set_a_periph(AT91_PIO_PORTA, 10, 0); /* SDMMC0_RSTN */
atmel_pio4_set_a_periph(AT91_PIO_PORTA, 11, 0); /* SDMMC0_VDDSEL */
+ atmel_pio4_set_a_periph(AT91_PIO_PORTA, 13, 0); /* SDMMC0_CD */
at91_periph_clk_enable(ATMEL_ID_SDMMC0);
at91_enable_periph_generated_clk(ATMEL_ID_SDMMC0,
- GCK_CSS_PLLA_CLK, 1);
+ GCK_CSS_UPLL_CLK, 1);
}
static void board_sdhci1_hw_init(void)
at91_periph_clk_enable(ATMEL_ID_SDMMC1);
at91_enable_periph_generated_clk(ATMEL_ID_SDMMC1,
- GCK_CSS_PLLA_CLK, 1);
+ GCK_CSS_UPLL_CLK, 1);
}
int board_mmc_init(bd_t *bis)
/* Detect storage device */
for (devno = 0; devno < USB_MAX_STOR_DEV; devno++) {
- stor_dev = usb_stor_get_dev(devno);
+ stor_dev = blk_get_devnum_by_type(IF_TYPE_USB, devno);
if (stor_dev->type != DEV_TYPE_UNKNOWN)
break;
}
#include <common.h>
#include <i2c.h>
+#include <eeprom_layout.h>
+#include <eeprom_field.h>
+#include <linux/kernel.h>
#include "eeprom.h"
#ifndef CONFIG_SYS_I2C_EEPROM_ADDR
return err;
}
+
+#ifdef CONFIG_CMD_EEPROM_LAYOUT
+/**
+ * eeprom_field_print_bin_ver() - print a "version field" which contains binary
+ * data
+ *
+ * Treat the field data as simple binary data, and print it formatted as a
+ * version number (2 digits after decimal point).
+ * The field size must be exactly 2 bytes.
+ *
+ * Sample output:
+ * Field Name 123.45
+ *
+ * @field: an initialized field to print
+ */
+void eeprom_field_print_bin_ver(const struct eeprom_field *field)
+{
+ if ((field->buf[0] == 0xff) && (field->buf[1] == 0xff)) {
+ field->buf[0] = 0;
+ field->buf[1] = 0;
+ }
+
+ printf(PRINT_FIELD_SEGMENT, field->name);
+ int major = (field->buf[1] << 8 | field->buf[0]) / 100;
+ int minor = (field->buf[1] << 8 | field->buf[0]) - major * 100;
+ printf("%d.%02d\n", major, minor);
+}
+
+/**
+ * eeprom_field_update_bin_ver() - update a "version field" which contains
+ * binary data
+ *
+ * This function takes a version string in the form of x.y (x and y are both
+ * decimal values, y is limited to two digits), translates it to the binary
+ * form, then writes it to the field. The field size must be exactly 2 bytes.
+ *
+ * This function strictly enforces the data syntax, and will not update the
+ * field if there's any deviation from it. It also protects from overflow.
+ *
+ * @field: an initialized field
+ * @value: a version string
+ *
+ * Returns 0 on success, -1 on failure.
+ */
+int eeprom_field_update_bin_ver(struct eeprom_field *field, char *value)
+{
+ char *endptr;
+ char *tok = strtok(value, ".");
+ if (tok == NULL)
+ return -1;
+
+ int num = simple_strtol(tok, &endptr, 0);
+ if (*endptr != '\0')
+ return -1;
+
+ tok = strtok(NULL, "");
+ if (tok == NULL)
+ return -1;
+
+ int remainder = simple_strtol(tok, &endptr, 0);
+ if (*endptr != '\0')
+ return -1;
+
+ num = num * 100 + remainder;
+ if (num >> 16)
+ return -1;
+
+ field->buf[0] = (unsigned char)num;
+ field->buf[1] = num >> 8;
+
+ return 0;
+}
+
+char *months[12] = {"Jan", "Feb", "Mar", "Apr", "May", "Jun",
+ "Jul", "Aug", "Sep", "Oct", "Nov", "Dec"};
+
+/**
+ * eeprom_field_print_date() - print a field which contains date data
+ *
+ * Treat the field data as simple binary data, and print it formatted as a date.
+ * Sample output:
+ * Field Name 07/Feb/2014
+ * Field Name 56/BAD/9999
+ *
+ * @field: an initialized field to print
+ */
+void eeprom_field_print_date(const struct eeprom_field *field)
+{
+ printf(PRINT_FIELD_SEGMENT, field->name);
+ printf("%02d/", field->buf[0]);
+ if (field->buf[1] >= 1 && field->buf[1] <= 12)
+ printf("%s", months[field->buf[1] - 1]);
+ else
+ printf("BAD");
+
+ printf("/%d\n", field->buf[3] << 8 | field->buf[2]);
+}
+
+static int validate_date(unsigned char day, unsigned char month,
+ unsigned int year)
+{
+ int days_in_february;
+
+ switch (month) {
+ case 0:
+ case 2:
+ case 4:
+ case 6:
+ case 7:
+ case 9:
+ case 11:
+ if (day > 31)
+ return -1;
+ break;
+ case 3:
+ case 5:
+ case 8:
+ case 10:
+ if (day > 30)
+ return -1;
+ break;
+ case 1:
+ days_in_february = 28;
+ if (year % 4 == 0) {
+ if (year % 100 != 0)
+ days_in_february = 29;
+ else if (year % 400 == 0)
+ days_in_february = 29;
+ }
+
+ if (day > days_in_february)
+ return -1;
+
+ break;
+ default:
+ return -1;
+ }
+
+ return 0;
+}
+
+/**
+ * eeprom_field_update_date() - update a date field which contains binary data
+ *
+ * This function takes a date string in the form of x/Mon/y (x and y are both
+ * decimal values), translates it to the binary representation, then writes it
+ * to the field.
+ *
+ * This function strictly enforces the data syntax, and will not update the
+ * field if there's any deviation from it. It also protects from overflow in the
+ * year value, and checks the validity of the date.
+ *
+ * @field: an initialized field
+ * @value: a date string
+ *
+ * Returns 0 on success, -1 on failure.
+ */
+int eeprom_field_update_date(struct eeprom_field *field, char *value)
+{
+ char *endptr;
+ char *tok1 = strtok(value, "/");
+ char *tok2 = strtok(NULL, "/");
+ char *tok3 = strtok(NULL, "/");
+
+ if (tok1 == NULL || tok2 == NULL || tok3 == NULL) {
+ printf("%s: syntax error\n", field->name);
+ return -1;
+ }
+
+ unsigned char day = (unsigned char)simple_strtol(tok1, &endptr, 0);
+ if (*endptr != '\0' || day == 0) {
+ printf("%s: invalid day\n", field->name);
+ return -1;
+ }
+
+ unsigned char month;
+ for (month = 1; month <= 12; month++)
+ if (!strcmp(tok2, months[month - 1]))
+ break;
+
+ unsigned int year = simple_strtol(tok3, &endptr, 0);
+ if (*endptr != '\0') {
+ printf("%s: invalid year\n", field->name);
+ return -1;
+ }
+
+ if (validate_date(day, month - 1, year)) {
+ printf("%s: invalid date\n", field->name);
+ return -1;
+ }
+
+ if (year >> 16) {
+ printf("%s: year overflow\n", field->name);
+ return -1;
+ }
+
+ field->buf[0] = day;
+ field->buf[1] = month;
+ field->buf[2] = (unsigned char)year;
+ field->buf[3] = (unsigned char)(year >> 8);
+
+ return 0;
+}
+
+#define LAYOUT_VERSION_LEGACY 1
+#define LAYOUT_VERSION_VER1 2
+#define LAYOUT_VERSION_VER2 3
+#define LAYOUT_VERSION_VER3 4
+
+extern struct eeprom_field layout_unknown[1];
+
+#define DEFINE_PRINT_UPDATE(x) eeprom_field_print_##x, eeprom_field_update_##x
+
+#ifdef CONFIG_CM_T3X
+struct eeprom_field layout_legacy[5] = {
+ { "MAC address", 6, NULL, DEFINE_PRINT_UPDATE(mac) },
+ { "Board Revision", 2, NULL, DEFINE_PRINT_UPDATE(bin) },
+ { "Serial Number", 8, NULL, DEFINE_PRINT_UPDATE(bin) },
+ { "Board Configuration", 64, NULL, DEFINE_PRINT_UPDATE(ascii) },
+ { RESERVED_FIELDS, 176, NULL, eeprom_field_print_reserved,
+ eeprom_field_update_ascii },
+};
+#else
+#define layout_legacy layout_unknown
+#endif
+
+#if defined(CONFIG_CM_T3X) || defined(CONFIG_CM_T3517)
+struct eeprom_field layout_v1[12] = {
+ { "Major Revision", 2, NULL, DEFINE_PRINT_UPDATE(bin_ver) },
+ { "Minor Revision", 2, NULL, DEFINE_PRINT_UPDATE(bin_ver) },
+ { "1st MAC Address", 6, NULL, DEFINE_PRINT_UPDATE(mac) },
+ { "2nd MAC Address", 6, NULL, DEFINE_PRINT_UPDATE(mac) },
+ { "Production Date", 4, NULL, DEFINE_PRINT_UPDATE(date) },
+ { "Serial Number", 12, NULL, DEFINE_PRINT_UPDATE(bin_rev) },
+ { RESERVED_FIELDS, 96, NULL, DEFINE_PRINT_UPDATE(reserved) },
+ { "Product Name", 16, NULL, DEFINE_PRINT_UPDATE(ascii) },
+ { "Product Options #1", 16, NULL, DEFINE_PRINT_UPDATE(ascii) },
+ { "Product Options #2", 16, NULL, DEFINE_PRINT_UPDATE(ascii) },
+ { "Product Options #3", 16, NULL, DEFINE_PRINT_UPDATE(ascii) },
+ { RESERVED_FIELDS, 64, NULL, eeprom_field_print_reserved,
+ eeprom_field_update_ascii },
+};
+#else
+#define layout_v1 layout_unknown
+#endif
+
+struct eeprom_field layout_v2[15] = {
+ { "Major Revision", 2, NULL, DEFINE_PRINT_UPDATE(bin_ver) },
+ { "Minor Revision", 2, NULL, DEFINE_PRINT_UPDATE(bin_ver) },
+ { "1st MAC Address", 6, NULL, DEFINE_PRINT_UPDATE(mac) },
+ { "2nd MAC Address", 6, NULL, DEFINE_PRINT_UPDATE(mac) },
+ { "Production Date", 4, NULL, DEFINE_PRINT_UPDATE(date) },
+ { "Serial Number", 12, NULL, DEFINE_PRINT_UPDATE(bin_rev) },
+ { "3rd MAC Address (WIFI)", 6, NULL, DEFINE_PRINT_UPDATE(mac) },
+ { "4th MAC Address (Bluetooth)", 6, NULL, DEFINE_PRINT_UPDATE(mac) },
+ { "Layout Version", 1, NULL, DEFINE_PRINT_UPDATE(bin) },
+ { RESERVED_FIELDS, 83, NULL, DEFINE_PRINT_UPDATE(reserved) },
+ { "Product Name", 16, NULL, DEFINE_PRINT_UPDATE(ascii) },
+ { "Product Options #1", 16, NULL, DEFINE_PRINT_UPDATE(ascii) },
+ { "Product Options #2", 16, NULL, DEFINE_PRINT_UPDATE(ascii) },
+ { "Product Options #3", 16, NULL, DEFINE_PRINT_UPDATE(ascii) },
+ { RESERVED_FIELDS, 64, NULL, eeprom_field_print_reserved,
+ eeprom_field_update_ascii },
+};
+
+struct eeprom_field layout_v3[16] = {
+ { "Major Revision", 2, NULL, DEFINE_PRINT_UPDATE(bin_ver) },
+ { "Minor Revision", 2, NULL, DEFINE_PRINT_UPDATE(bin_ver) },
+ { "1st MAC Address", 6, NULL, DEFINE_PRINT_UPDATE(mac) },
+ { "2nd MAC Address", 6, NULL, DEFINE_PRINT_UPDATE(mac) },
+ { "Production Date", 4, NULL, DEFINE_PRINT_UPDATE(date) },
+ { "Serial Number", 12, NULL, DEFINE_PRINT_UPDATE(bin_rev) },
+ { "3rd MAC Address (WIFI)", 6, NULL, DEFINE_PRINT_UPDATE(mac) },
+ { "4th MAC Address (Bluetooth)", 6, NULL, DEFINE_PRINT_UPDATE(mac) },
+ { "Layout Version", 1, NULL, DEFINE_PRINT_UPDATE(bin) },
+ { "CompuLab EEPROM ID", 3, NULL, DEFINE_PRINT_UPDATE(bin) },
+ { RESERVED_FIELDS, 80, NULL, DEFINE_PRINT_UPDATE(reserved) },
+ { "Product Name", 16, NULL, DEFINE_PRINT_UPDATE(ascii) },
+ { "Product Options #1", 16, NULL, DEFINE_PRINT_UPDATE(ascii) },
+ { "Product Options #2", 16, NULL, DEFINE_PRINT_UPDATE(ascii) },
+ { "Product Options #3", 16, NULL, DEFINE_PRINT_UPDATE(ascii) },
+ { RESERVED_FIELDS, 64, NULL, eeprom_field_print_reserved,
+ eeprom_field_update_ascii },
+};
+
+void eeprom_layout_assign(struct eeprom_layout *layout, int layout_version)
+{
+ switch (layout->layout_version) {
+ case LAYOUT_VERSION_LEGACY:
+ layout->fields = layout_legacy;
+ layout->num_of_fields = ARRAY_SIZE(layout_legacy);
+ break;
+ case LAYOUT_VERSION_VER1:
+ layout->fields = layout_v1;
+ layout->num_of_fields = ARRAY_SIZE(layout_v1);
+ break;
+ case LAYOUT_VERSION_VER2:
+ layout->fields = layout_v2;
+ layout->num_of_fields = ARRAY_SIZE(layout_v2);
+ break;
+ case LAYOUT_VERSION_VER3:
+ layout->fields = layout_v3;
+ layout->num_of_fields = ARRAY_SIZE(layout_v3);
+ break;
+ default:
+ __eeprom_layout_assign(layout, layout_version);
+ }
+}
+
+int eeprom_parse_layout_version(char *str)
+{
+ if (!strcmp(str, "legacy"))
+ return LAYOUT_VERSION_LEGACY;
+ else if (!strcmp(str, "v1"))
+ return LAYOUT_VERSION_VER1;
+ else if (!strcmp(str, "v2"))
+ return LAYOUT_VERSION_VER2;
+ else if (!strcmp(str, "v3"))
+ return LAYOUT_VERSION_VER3;
+ else
+ return LAYOUT_VERSION_UNRECOGNIZED;
+}
+
+int eeprom_layout_detect(unsigned char *data)
+{
+ switch (data[EEPROM_LAYOUT_VER_OFFSET]) {
+ case 0xff:
+ case 0:
+ return LAYOUT_VERSION_VER1;
+ case 2:
+ return LAYOUT_VERSION_VER2;
+ case 3:
+ return LAYOUT_VERSION_VER3;
+ }
+
+ if (data[EEPROM_LAYOUT_VER_OFFSET] >= 0x20)
+ return LAYOUT_VERSION_LEGACY;
+
+ return LAYOUT_VERSION_UNRECOGNIZED;
+}
+#endif
--- /dev/null
+dsdt.aml
+dsdt.asl.tmp
+dsdt.c
#
obj-y += conga-qeval20-qa3.o start.o
+obj-$(CONFIG_GENERATE_ACPI_TABLE) += dsdt.o
--- /dev/null
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/* Power Button */
+Device (PWRB)
+{
+ Name(_HID, EISAID("PNP0C0C"))
+}
+
+/* TODO: Need add Winbond SuperIO chipset W83627 ASL codes */
--- /dev/null
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+DefinitionBlock("dsdt.aml", "DSDT", 2, "U-BOOT", "U-BOOTBL", 0x00010000)
+{
+ /* platform specific */
+ #include <asm/arch/acpi/platform.asl>
+
+ /* board specific */
+ #include "acpi/mainboard.asl"
+}
while ((nodeoff = fdt_node_offset_by_compat_reg(blob, "fsl,sec-v6.0",
CONFIG_SYS_CCSRBAR_PHYS + CONFIG_SYS_FSL_SEC_OFFSET
- + offset * 0x20000)) >= 0) {
+ + offset * CONFIG_SYS_FSL_SEC_IDX_OFFSET)) >= 0) {
fdt_del_node(blob, nodeoff);
offset++;
}
void ls102xa_config_smmu_stream_id(struct smmu_stream_id *id, uint32_t num)
{
- uint32_t *scfg = (uint32_t *)CONFIG_SYS_FSL_SCFG_ADDR;
+ void *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
int i;
for (i = 0; i < num; i++)
- out_be32(scfg + id[i].offset, id[i].stream_id);
+ out_be32((u32 *)(scfg + id[i].offset), id[i].stream_id);
}
void ls1021x_config_caam_stream_id(struct liodn_id_table *tbl, int size)
else
liodn = tbl[i].id[0];
- out_le32((uint32_t *)(tbl[i].reg_offset), liodn);
+ out_le32((u32 *)(tbl[i].reg_offset), liodn);
}
}
dram_size = fsl_ddr_sdram();
#endif
+ erratum_a008850_post();
#ifdef CONFIG_FSL_DEEP_SLEEP
fsl_dp_ddr_restore();
#ifndef __DDR_H__
#define __DDR_H__
+extern void erratum_a008850_post(void);
+
struct board_specific_parameters {
u32 n_ranks;
u32 datarate_mhz_high;
int board_init(void)
{
- struct ccsr_cci400 *cci = (struct ccsr_cci400 *)
- CONFIG_SYS_CCI400_ADDR;
-
- /* Set CCI-400 control override register to enable barrier
- * transaction */
- out_le32(&cci->ctrl_ord,
- CCI400_CTRLORD_EN_BARRIER);
-
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
board_retimer_init();
#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
enable_layerscape_ns_access();
#endif
-
-#ifdef CONFIG_ENV_IS_NOWHERE
- gd->env_addr = (ulong)&default_environment[0];
-#endif
return 0;
}
/* Set the boot bank to the alternate bank */
void cpld_set_altbank(void)
{
+ u16 reg = CPLD_CFG_RCW_SRC_NOR;
u8 reg4 = CPLD_READ(soft_mux_on);
+ u8 reg5 = (u8)(reg >> 1);
+ u8 reg6 = (u8)(reg & 1);
u8 reg7 = CPLD_READ(vbank);
- CPLD_WRITE(soft_mux_on, reg4 | CPLD_SW_MUX_BANK_SEL);
+ cpld_rev_bit(®5);
+
+ CPLD_WRITE(soft_mux_on, reg4 | CPLD_SW_MUX_BANK_SEL | 1);
+
+ CPLD_WRITE(cfg_rcw_src1, reg5);
+ CPLD_WRITE(cfg_rcw_src2, reg6);
reg7 = (reg7 & ~CPLD_BANK_SEL_MASK) | CPLD_BANK_SEL_ALTBANK;
CPLD_WRITE(vbank, reg7);
/* Set the boot bank to the default bank */
void cpld_set_defbank(void)
{
- CPLD_WRITE(global_rst, 1);
+ u16 reg = CPLD_CFG_RCW_SRC_NOR;
+ u8 reg4 = CPLD_READ(soft_mux_on);
+ u8 reg5 = (u8)(reg >> 1);
+ u8 reg6 = (u8)(reg & 1);
+
+ cpld_rev_bit(®5);
+
+ CPLD_WRITE(soft_mux_on, reg4 | CPLD_SW_MUX_BANK_SEL | 1);
+
+ CPLD_WRITE(cfg_rcw_src1, reg5);
+ CPLD_WRITE(cfg_rcw_src2, reg6);
+
+ CPLD_WRITE(vbank, 0);
+
+ CPLD_WRITE(system_rst, 1);
}
void cpld_set_nand(void)
#define CPLD_SW_MUX_BANK_SEL 0x40
#define CPLD_BANK_SEL_MASK 0x07
#define CPLD_BANK_SEL_ALTBANK 0x04
+#define CPLD_CFG_RCW_SRC_NOR 0x025
#define CPLD_CFG_RCW_SRC_NAND 0x106
#define CPLD_CFG_RCW_SRC_SD 0x040
#endif
#else
dram_size = fsl_ddr_sdram_size();
#endif
+ erratum_a008850_post();
+
#ifdef CONFIG_FSL_DEEP_SLEEP
fsl_dp_ddr_restore();
#endif
#ifndef __DDR_H__
#define __DDR_H__
+
+extern void erratum_a008850_post(void);
+
struct board_specific_parameters {
u32 n_ranks;
u32 datarate_mhz_high;
#include <fsl_csu.h>
#include <fsl_esdhc.h>
#include <fsl_ifc.h>
-#include <environment.h>
#include <fsl_sec.h>
#include "cpld.h"
#ifdef CONFIG_U_QE
int checkboard(void)
{
- static const char *freq[3] = {"100.00MHZ", "156.25MHZ"};
+ static const char *freq[2] = {"100.00MHZ", "156.25MHZ"};
#ifndef CONFIG_SD_BOOT
u8 cfg_rcw_src1, cfg_rcw_src2;
- u32 cfg_rcw_src;
+ u16 cfg_rcw_src;
#endif
- u32 sd1refclk_sel;
+ u8 sd1refclk_sel;
printf("Board: LS1043ARDB, boot from ");
int board_init(void)
{
- struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
-
- /*
- * Set CCI-400 control override register to enable barrier
- * transaction
- */
- out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
+ struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
#ifdef CONFIG_FSL_IFC
init_final_memctl_regs();
#endif
-#ifdef CONFIG_ENV_IS_NOWHERE
- gd->env_addr = (ulong)&default_environment[0];
-#endif
-
#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
enable_layerscape_ns_access();
#endif
#ifdef CONFIG_U_QE
u_qe_init();
#endif
+ /* invert AQR105 IRQ pins polarity */
+ out_be32(&scfg->intpcr, AQR105_IRQ_MASK);
return 0;
}
LS2080A BOARD
-M: Prabhakar Kushwaha <prabhakar@freescale.com>
+M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
S: Maintained
F: board/freescale/ls2080aqds/
F: board/freescale/ls2080a/ls2080aqds.c
LS2080A BOARD
-M: Prabhakar Kushwaha <prabhakar@freescale.com>
+M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
S: Maintained
F: board/freescale/ls2080ardb/
F: board/freescale/ls2080a/ls2080ardb.c
* ranks| mhz| GB |adjst| start | ctl2 | ctl3
*/
{2, 1350, 0, 4, 6, 0x0708090B, 0x0C0D0E09,},
- {2, 1666, 0, 4, 8, 0x08090B0D, 0x0E10100C,},
- {2, 1900, 0, 4, 8, 0x090A0C0E, 0x1012120D,},
- {2, 2300, 0, 4, 9, 0x0A0B0C10, 0x1114140E,},
+ {2, 1666, 0, 5, 9, 0x090A0B0E, 0x0F11110C,},
+ {2, 1900, 0, 6, 0xA, 0x0B0C0E11, 0x1214140F,},
+ {2, 2300, 0, 6, 0xB, 0x0C0D0F12, 0x14161610,},
{}
};
.text
.set noreorder
- .set mips32
.globl lowlevel_init
lowlevel_init:
--- /dev/null
+dsdt.aml
+dsdt.asl.tmp
+dsdt.c
#
obj-y += bayleybay.o start.o
+obj-$(CONFIG_GENERATE_ACPI_TABLE) += dsdt.o
--- /dev/null
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/* Power Button */
+Device (PWRB)
+{
+ Name(_HID, EISAID("PNP0C0C"))
+}
--- /dev/null
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+DefinitionBlock("dsdt.aml", "DSDT", 2, "U-BOOT", "U-BOOTBL", 0x00010000)
+{
+ /* platform specific */
+ #include <asm/arch/acpi/platform.asl>
+
+ /* board specific */
+ #include "acpi/mainboard.asl"
+}
select INTEL_QUARK
select BOARD_ROMSIZE_KB_1024
+config SMBIOS_PRODUCT_NAME
+ default "GalileoGen2"
+ help
+ Override the default product name U-Boot reports in the SMBIOS
+ table, to be compatible with the Intel provided UEFI BIOS, as
+ Linux kernel drivers (drivers/mfd/intel_quark_i2c_gpio.c and
+ drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c) make use of
+ it to do different board level configuration.
+
+ This can be "Galileo" for GEN1 Galileo board.
+
endif
--- /dev/null
+dsdt.aml
+dsdt.asl.tmp
+dsdt.c
#
obj-y += minnowmax.o start.o
+obj-$(CONFIG_GENERATE_ACPI_TABLE) += dsdt.o
--- /dev/null
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/* Power Button */
+Device (PWRB)
+{
+ Name(_HID, EISAID("PNP0C0C"))
+}
--- /dev/null
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+DefinitionBlock("dsdt.aml", "DSDT", 2, "U-BOOT", "U-BOOTBL", 0x00010000)
+{
+ /* platform specific */
+ #include <asm/arch/acpi/platform.asl>
+
+ /* board specific */
+ #include "acpi/mainboard.asl"
+}
static void i2c_write_start_seq(void)
{
- struct fsl_i2c *dev;
- dev = (struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C_OFFSET);
+ struct fsl_i2c_base *base;
+ base = (struct fsl_i2c_base *)(CONFIG_SYS_IMMR +
+ CONFIG_SYS_I2C_OFFSET);
udelay(DELAY_ABORT_SEQ);
- out_8(&dev->cr, (I2C_CR_MEN | I2C_CR_MSTA));
+ out_8(&base->cr, (I2C_CR_MEN | I2C_CR_MSTA));
udelay(DELAY_ABORT_SEQ);
- out_8(&dev->cr, (I2C_CR_MEN));
+ out_8(&base->cr, (I2C_CR_MEN));
}
int i2c_make_abort(void)
{
- struct fsl_i2c *dev;
- dev = (struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C_OFFSET);
+ struct fsl_i2c_base *base;
+ base = (struct fsl_i2c_base *)(CONFIG_SYS_IMMR +
+ CONFIG_SYS_I2C_OFFSET);
uchar last;
int nbr_read = 0;
int i = 0;
int ret = 0;
/* wait after each operation to finsh with a delay */
- out_8(&dev->cr, (I2C_CR_MSTA));
+ out_8(&base->cr, (I2C_CR_MSTA));
udelay(DELAY_ABORT_SEQ);
- out_8(&dev->cr, (I2C_CR_MEN | I2C_CR_MSTA));
+ out_8(&base->cr, (I2C_CR_MEN | I2C_CR_MSTA));
udelay(DELAY_ABORT_SEQ);
- in_8(&dev->dr);
+ in_8(&base->dr);
udelay(DELAY_ABORT_SEQ);
- last = in_8(&dev->dr);
+ last = in_8(&base->dr);
nbr_read++;
/*
while (((last & 0x01) != 0x01) &&
(nbr_read < CONFIG_SYS_IVM_EEPROM_MAX_LEN)) {
udelay(DELAY_ABORT_SEQ);
- last = in_8(&dev->dr);
+ last = in_8(&base->dr);
nbr_read++;
}
if ((last & 0x01) != 0x01)
printf("[INFO] i2c abort after %d bytes (0x%02x)\n",
nbr_read, last);
udelay(DELAY_ABORT_SEQ);
- out_8(&dev->cr, (I2C_CR_MEN));
+ out_8(&base->cr, (I2C_CR_MEN));
udelay(DELAY_ABORT_SEQ);
/* clear status reg */
- out_8(&dev->sr, 0);
+ out_8(&base->sr, 0);
for (i = 0; i < 5; i++)
i2c_write_start_seq();
- include/cmd_bsp.h added PIP405 commands definitions
- include/cmd_condefs.h added Floppy and SCSI support
- include/cmd_disk.h changed to work with block device description
-- include/config_LANTEC.h excluded CONFIG_CMD_FDC and CONFIG_CMD_SCSI
-- include/config_hymod.h excluded CONFIG_CMD_FDC and CONFIG_CMD_SCSI
+- include/config_LANTEC.h excluded CONFIG_CMD_FDC and CONFIG_SCSI
+- include/config_hymod.h excluded CONFIG_CMD_FDC and CONFIG_SCSI
- include/flash.h added INTEL_ID_28F320C3T 0x88C488C4
- include/i2c.h added "defined(CONFIG_PIP405)"
- include/image.h added IH_OS_U_BOOT, IH_TYPE_FIRMWARE
New Commands:
-------------
-CONFIG_CMD_SCSI SCSI Support
+CONFIG_SCSI SCSI Support
CONFIG_CMF_FDC Floppy disk support
IDE additions:
--- /dev/null
+if TARGET_AP121
+
+config SYS_VENDOR
+ default "qca"
+
+config SYS_BOARD
+ default "ap121"
+
+config SYS_CONFIG_NAME
+ default "ap121"
+
+endif
--- /dev/null
+AP121 BOARD
+M: Wills Wang <wills.wang@live.com>
+S: Maintained
+F: board/qca/ap121/
+F: include/configs/ap121.h
+F: configs/ap121_defconfig
--- /dev/null
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y = ap121.o
--- /dev/null
+/*
+ * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/addrspace.h>
+#include <asm/types.h>
+#include <mach/ar71xx_regs.h>
+#include <mach/ddr.h>
+#include <debug_uart.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_DEBUG_UART_BOARD_INIT
+void board_debug_uart_init(void)
+{
+ void __iomem *regs;
+ u32 val;
+
+ regs = map_physmem(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE,
+ MAP_NOCACHE);
+
+ /*
+ * GPIO9 as input, GPIO10 as output
+ */
+ val = readl(regs + AR71XX_GPIO_REG_OE);
+ val &= ~AR933X_GPIO(9);
+ val |= AR933X_GPIO(10);
+ writel(val, regs + AR71XX_GPIO_REG_OE);
+
+ /*
+ * Enable UART, GPIO9 as UART_SI, GPIO10 as UART_SO
+ */
+ val = readl(regs + AR71XX_GPIO_REG_FUNC);
+ val |= AR933X_GPIO_FUNC_UART_EN | AR933X_GPIO_FUNC_RES_TRUE;
+ writel(val, regs + AR71XX_GPIO_REG_FUNC);
+}
+#endif
+
+int board_early_init_f(void)
+{
+#ifdef CONFIG_DEBUG_UART
+ debug_uart_init();
+#endif
+ ddr_init();
+ return 0;
+}
--- /dev/null
+if TARGET_AP143
+
+config SYS_VENDOR
+ default "qca"
+
+config SYS_BOARD
+ default "ap143"
+
+config SYS_CONFIG_NAME
+ default "ap143"
+
+endif
--- /dev/null
+AP143 BOARD
+M: Wills Wang <wills.wang@live.com>
+S: Maintained
+F: board/qca/ap143/
+F: include/configs/ap143.h
+F: configs/ap143_defconfig
--- /dev/null
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y = ap143.o
--- /dev/null
+/*
+ * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/addrspace.h>
+#include <asm/types.h>
+#include <mach/ar71xx_regs.h>
+#include <mach/ddr.h>
+#include <debug_uart.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_DEBUG_UART_BOARD_INIT
+void board_debug_uart_init(void)
+{
+ void __iomem *regs;
+ u32 val;
+
+ regs = map_physmem(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE,
+ MAP_NOCACHE);
+
+ /*
+ * GPIO9 as input, GPIO10 as output
+ */
+ val = readl(regs + AR71XX_GPIO_REG_OE);
+ val |= QCA953X_GPIO(9);
+ val &= ~QCA953X_GPIO(10);
+ writel(val, regs + AR71XX_GPIO_REG_OE);
+
+ /*
+ * Enable GPIO10 as UART0_SOUT
+ */
+ val = readl(regs + QCA953X_GPIO_REG_OUT_FUNC2);
+ val &= ~QCA953X_GPIO_MUX_MASK(16);
+ val |= QCA953X_GPIO_OUT_MUX_UART0_SOUT << 16;
+ writel(val, regs + QCA953X_GPIO_REG_OUT_FUNC2);
+
+ /*
+ * Enable GPIO9 as UART0_SIN
+ */
+ val = readl(regs + QCA953X_GPIO_REG_IN_ENABLE0);
+ val &= ~QCA953X_GPIO_MUX_MASK(8);
+ val |= QCA953X_GPIO_IN_MUX_UART0_SIN << 8;
+ writel(val, regs + QCA953X_GPIO_REG_IN_ENABLE0);
+
+ /*
+ * Enable GPIO10 output
+ */
+ val = readl(regs + AR71XX_GPIO_REG_OUT);
+ val |= QCA953X_GPIO(10);
+ writel(val, regs + AR71XX_GPIO_REG_OUT);
+}
+#endif
+
+int board_early_init_f(void)
+{
+#ifdef CONFIG_DEBUG_UART
+ debug_uart_init();
+#endif
+ ddr_init();
+ return 0;
+}
F: board/sandbox/
F: include/configs/sandbox.h
F: configs/sandbox_defconfig
+
+SANDBOX_NOBLK BOARD
+M: Simon Glass <sjg@chromium.org>
+S: Maintained
+F: board/sandbox/
+F: include/configs/sandbox.h
+F: configs/sandbox_noblk_defconfig
--- /dev/null
+if BOARD_TPLINK_WDR4300
+
+config SYS_VENDOR
+ default "tplink"
+
+config SYS_SOC
+ default "ath79"
+
+config SYS_BOARD
+ default "wdr4300"
+
+config SYS_CONFIG_NAME
+ default "tplink_wdr4300"
+
+endif
--- /dev/null
+TPLINK_WDR4300 BOARD
+M: Marek Vasut <marex@denx.de>
+S: Maintained
+F: board/tplink/wdr4300/
+F: include/configs/tplink_wdr4300.h
+F: configs/tplink_wdr4300_defconfig
--- /dev/null
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y = wdr4300.o
--- /dev/null
+/*
+ * Copyright (C) 2016 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/addrspace.h>
+#include <asm/types.h>
+#include <mach/ath79.h>
+#include <mach/ar71xx_regs.h>
+#include <mach/ddr.h>
+#include <debug_uart.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_USB
+static void wdr4300_usb_start(void)
+{
+ void __iomem *gpio_regs = map_physmem(AR71XX_GPIO_BASE,
+ AR71XX_GPIO_SIZE, MAP_NOCACHE);
+ if (!gpio_regs)
+ return;
+
+ /* Power up the USB HUB. */
+ clrbits_be32(gpio_regs + AR71XX_GPIO_REG_OE, BIT(21) | BIT(22));
+ writel(BIT(21) | BIT(22), gpio_regs + AR71XX_GPIO_REG_SET);
+ mdelay(1);
+
+ ath79_usb_reset();
+}
+#else
+static inline void wdr4300_usb_start(void) {}
+#endif
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f(void)
+{
+ void __iomem *regs;
+
+ regs = map_physmem(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE,
+ MAP_NOCACHE);
+
+ /* Assure JTAG is not disconnected. */
+ writel(0x40, regs + AR934X_GPIO_REG_FUNC);
+
+ /* Configure default GPIO input/output regs. */
+ writel(0x3031b, regs + AR71XX_GPIO_REG_OE);
+ writel(0x0f804, regs + AR71XX_GPIO_REG_OUT);
+
+ /* Configure pin multiplexing. */
+ writel(0x00000000, regs + AR934X_GPIO_REG_OUT_FUNC0);
+ writel(0x0b0a0980, regs + AR934X_GPIO_REG_OUT_FUNC1);
+ writel(0x00180000, regs + AR934X_GPIO_REG_OUT_FUNC2);
+ writel(0x00000000, regs + AR934X_GPIO_REG_OUT_FUNC3);
+ writel(0x0000004d, regs + AR934X_GPIO_REG_OUT_FUNC4);
+ writel(0x00000000, regs + AR934X_GPIO_REG_OUT_FUNC5);
+
+#ifdef CONFIG_DEBUG_UART
+ debug_uart_init();
+#endif
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+ ar934x_pll_init(560, 480, 240);
+ ar934x_ddr_init(560, 480, 240);
+#endif
+
+ wdr4300_usb_start();
+ ath79_eth_reset();
+
+ return 0;
+}
+#endif
obj-y := board.o
-# Copied from Xilinx SDK 2014.4
-hw-platform-$(CONFIG_TARGET_ZYNQ_ZED) := zed_hw_platform
-hw-platform-$(CONFIG_TARGET_ZYNQ_MICROZED) := MicroZed_hw_platform
-hw-platform-$(CONFIG_TARGET_ZYNQ_ZC702) := ZC702_hw_platform
-hw-platform-$(CONFIG_TARGET_ZYNQ_ZC706) := ZC706_hw_platform
-hw-platform-$(CONFIG_TARGET_ZYNQ_ZYBO) := zybo_hw_platform
-# If you want to use customized ps7_init_gpl.c/h,
-# enable CONFIG_ZYNQ_CUSTOM_INIT and put them into custom_hw_platform/.
-# This line must be placed at the bottom of the list because
-# it takes precedence over the default ones.
-hw-platform-$(CONFIG_ZYNQ_CUSTOM_INIT) := custom_hw_platform
+hw-platform-y :=$(shell echo $(CONFIG_DEFAULT_DEVICE_TREE))
init-objs := $(if $(wildcard $(srctree)/$(src)/$(hw-platform-y)/ps7_init_gpl.c),\
$(hw-platform-y)/ps7_init_gpl.o)
+++ /dev/null
-/******************************************************************************
-* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
-*
-* SPDX-License-Identifier: GPL-2.0+
-*
-*
-******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file ps7_init_gpl.c
-*
-* This file is automatically generated
-*
-*****************************************************************************/
-
-#include "ps7_init_gpl.h"
-
-unsigned long ps7_pll_init_data_3_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: PLL SLCR REGISTERS
- // .. .. START: ARM PLL INIT
- // .. .. PLL_RES = 0x2
- // .. .. ==> 0XF8000110[7:4] = 0x00000002U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
- // .. .. PLL_CP = 0x2
- // .. .. ==> 0XF8000110[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. LOCK_CNT = 0xfa
- // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
- // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U
- // .. ..
- EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
- // .. .. .. START: UPDATE FB_DIV
- // .. .. .. PLL_FDIV = 0x28
- // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
- // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
- // .. .. .. FINISH: UPDATE FB_DIV
- // .. .. .. START: BY PASS PLL
- // .. .. .. PLL_BYPASS_FORCE = 1
- // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
- // .. .. .. FINISH: BY PASS PLL
- // .. .. .. START: ASSERT RESET
- // .. .. .. PLL_RESET = 1
- // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
- // .. .. .. FINISH: ASSERT RESET
- // .. .. .. START: DEASSERT RESET
- // .. .. .. PLL_RESET = 0
- // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
- // .. .. .. FINISH: DEASSERT RESET
- // .. .. .. START: CHECK PLL STATUS
- // .. .. .. ARM_PLL_LOCK = 1
- // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ..
- EMIT_MASKPOLL(0XF800010C, 0x00000001U),
- // .. .. .. FINISH: CHECK PLL STATUS
- // .. .. .. START: REMOVE PLL BY PASS
- // .. .. .. PLL_BYPASS_FORCE = 0
- // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
- // .. .. .. FINISH: REMOVE PLL BY PASS
- // .. .. .. SRCSEL = 0x0
- // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. .. .. DIVISOR = 0x2
- // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
- // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U
- // .. .. .. CPU_6OR4XCLKACT = 0x1
- // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
- // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U
- // .. .. .. CPU_3OR2XCLKACT = 0x1
- // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
- // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U
- // .. .. .. CPU_2XCLKACT = 0x1
- // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
- // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U
- // .. .. .. CPU_1XCLKACT = 0x1
- // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
- // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U
- // .. .. .. CPU_PERI_CLKACT = 0x1
- // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
- // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
- // .. .. FINISH: ARM PLL INIT
- // .. .. START: DDR PLL INIT
- // .. .. PLL_RES = 0x2
- // .. .. ==> 0XF8000114[7:4] = 0x00000002U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
- // .. .. PLL_CP = 0x2
- // .. .. ==> 0XF8000114[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. LOCK_CNT = 0x12c
- // .. .. ==> 0XF8000114[21:12] = 0x0000012CU
- // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U
- // .. ..
- EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
- // .. .. .. START: UPDATE FB_DIV
- // .. .. .. PLL_FDIV = 0x20
- // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
- // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
- // .. .. .. FINISH: UPDATE FB_DIV
- // .. .. .. START: BY PASS PLL
- // .. .. .. PLL_BYPASS_FORCE = 1
- // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
- // .. .. .. FINISH: BY PASS PLL
- // .. .. .. START: ASSERT RESET
- // .. .. .. PLL_RESET = 1
- // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
- // .. .. .. FINISH: ASSERT RESET
- // .. .. .. START: DEASSERT RESET
- // .. .. .. PLL_RESET = 0
- // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
- // .. .. .. FINISH: DEASSERT RESET
- // .. .. .. START: CHECK PLL STATUS
- // .. .. .. DDR_PLL_LOCK = 1
- // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. .. ..
- EMIT_MASKPOLL(0XF800010C, 0x00000002U),
- // .. .. .. FINISH: CHECK PLL STATUS
- // .. .. .. START: REMOVE PLL BY PASS
- // .. .. .. PLL_BYPASS_FORCE = 0
- // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
- // .. .. .. FINISH: REMOVE PLL BY PASS
- // .. .. .. DDR_3XCLKACT = 0x1
- // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. .. DDR_2XCLKACT = 0x1
- // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. .. .. DDR_3XCLK_DIVISOR = 0x2
- // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
- // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U
- // .. .. .. DDR_2XCLK_DIVISOR = 0x3
- // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
- // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
- // .. .. FINISH: DDR PLL INIT
- // .. .. START: IO PLL INIT
- // .. .. PLL_RES = 0xc
- // .. .. ==> 0XF8000118[7:4] = 0x0000000CU
- // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U
- // .. .. PLL_CP = 0x2
- // .. .. ==> 0XF8000118[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. LOCK_CNT = 0x145
- // .. .. ==> 0XF8000118[21:12] = 0x00000145U
- // .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U
- // .. ..
- EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U),
- // .. .. .. START: UPDATE FB_DIV
- // .. .. .. PLL_FDIV = 0x1e
- // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU
- // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U),
- // .. .. .. FINISH: UPDATE FB_DIV
- // .. .. .. START: BY PASS PLL
- // .. .. .. PLL_BYPASS_FORCE = 1
- // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
- // .. .. .. FINISH: BY PASS PLL
- // .. .. .. START: ASSERT RESET
- // .. .. .. PLL_RESET = 1
- // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
- // .. .. .. FINISH: ASSERT RESET
- // .. .. .. START: DEASSERT RESET
- // .. .. .. PLL_RESET = 0
- // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
- // .. .. .. FINISH: DEASSERT RESET
- // .. .. .. START: CHECK PLL STATUS
- // .. .. .. IO_PLL_LOCK = 1
- // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. .. ..
- EMIT_MASKPOLL(0XF800010C, 0x00000004U),
- // .. .. .. FINISH: CHECK PLL STATUS
- // .. .. .. START: REMOVE PLL BY PASS
- // .. .. .. PLL_BYPASS_FORCE = 0
- // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
- // .. .. .. FINISH: REMOVE PLL BY PASS
- // .. .. FINISH: IO PLL INIT
- // .. FINISH: PLL SLCR REGISTERS
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_clock_init_data_3_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: CLOCK CONTROL SLCR REGISTERS
- // .. CLKACT = 0x1
- // .. ==> 0XF8000128[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. DIVISOR0 = 0x23
- // .. ==> 0XF8000128[13:8] = 0x00000023U
- // .. ==> MASK : 0x00003F00U VAL : 0x00002300U
- // .. DIVISOR1 = 0x3
- // .. ==> 0XF8000128[25:20] = 0x00000003U
- // .. ==> MASK : 0x03F00000U VAL : 0x00300000U
- // ..
- EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U),
- // .. CLKACT = 0x1
- // .. ==> 0XF8000138[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000138[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
- // .. CLKACT = 0x1
- // .. ==> 0XF8000140[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000140[6:4] = 0x00000000U
- // .. ==> MASK : 0x00000070U VAL : 0x00000000U
- // .. DIVISOR = 0x8
- // .. ==> 0XF8000140[13:8] = 0x00000008U
- // .. ==> MASK : 0x00003F00U VAL : 0x00000800U
- // .. DIVISOR1 = 0x1
- // .. ==> 0XF8000140[25:20] = 0x00000001U
- // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
- // ..
- EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U),
- // .. CLKACT = 0x1
- // .. ==> 0XF800014C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. SRCSEL = 0x0
- // .. ==> 0XF800014C[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR = 0x5
- // .. ==> 0XF800014C[13:8] = 0x00000005U
- // .. ==> MASK : 0x00003F00U VAL : 0x00000500U
- // ..
- EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
- // .. CLKACT0 = 0x1
- // .. ==> 0XF8000150[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. CLKACT1 = 0x0
- // .. ==> 0XF8000150[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000150[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR = 0x14
- // .. ==> 0XF8000150[13:8] = 0x00000014U
- // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
- // ..
- EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U),
- // .. CLKACT0 = 0x0
- // .. ==> 0XF8000154[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. CLKACT1 = 0x1
- // .. ==> 0XF8000154[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000154[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR = 0x14
- // .. ==> 0XF8000154[13:8] = 0x00000014U
- // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
- // ..
- EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U),
- // .. CLKACT = 0x1
- // .. ==> 0XF8000168[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000168[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR = 0x5
- // .. ==> 0XF8000168[13:8] = 0x00000005U
- // .. ==> MASK : 0x00003F00U VAL : 0x00000500U
- // ..
- EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000170[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR0 = 0xa
- // .. ==> 0XF8000170[13:8] = 0x0000000AU
- // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U
- // .. DIVISOR1 = 0x1
- // .. ==> 0XF8000170[25:20] = 0x00000001U
- // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
- // ..
- EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00100A00U),
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000180[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR0 = 0xa
- // .. ==> 0XF8000180[13:8] = 0x0000000AU
- // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U
- // .. DIVISOR1 = 0x1
- // .. ==> 0XF8000180[25:20] = 0x00000001U
- // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
- // ..
- EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00100A00U),
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000190[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR0 = 0x1e
- // .. ==> 0XF8000190[13:8] = 0x0000001EU
- // .. ==> MASK : 0x00003F00U VAL : 0x00001E00U
- // .. DIVISOR1 = 0x1
- // .. ==> 0XF8000190[25:20] = 0x00000001U
- // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
- // ..
- EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101E00U),
- // .. SRCSEL = 0x0
- // .. ==> 0XF80001A0[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR0 = 0x14
- // .. ==> 0XF80001A0[13:8] = 0x00000014U
- // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
- // .. DIVISOR1 = 0x1
- // .. ==> 0XF80001A0[25:20] = 0x00000001U
- // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
- // ..
- EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U),
- // .. CLK_621_TRUE = 0x1
- // .. ==> 0XF80001C4[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // ..
- EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
- // .. DMA_CPU_2XCLKACT = 0x1
- // .. ==> 0XF800012C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. USB0_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. USB1_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[3:3] = 0x00000001U
- // .. ==> MASK : 0x00000008U VAL : 0x00000008U
- // .. GEM0_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[6:6] = 0x00000001U
- // .. ==> MASK : 0x00000040U VAL : 0x00000040U
- // .. GEM1_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. SDI0_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[10:10] = 0x00000001U
- // .. ==> MASK : 0x00000400U VAL : 0x00000400U
- // .. SDI1_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. SPI0_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[14:14] = 0x00000000U
- // .. ==> MASK : 0x00004000U VAL : 0x00000000U
- // .. SPI1_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[15:15] = 0x00000000U
- // .. ==> MASK : 0x00008000U VAL : 0x00000000U
- // .. CAN0_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[16:16] = 0x00000000U
- // .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. CAN1_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[17:17] = 0x00000000U
- // .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. I2C0_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[18:18] = 0x00000001U
- // .. ==> MASK : 0x00040000U VAL : 0x00040000U
- // .. I2C1_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[19:19] = 0x00000001U
- // .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // .. UART0_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[20:20] = 0x00000000U
- // .. ==> MASK : 0x00100000U VAL : 0x00000000U
- // .. UART1_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[21:21] = 0x00000001U
- // .. ==> MASK : 0x00200000U VAL : 0x00200000U
- // .. GPIO_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[22:22] = 0x00000001U
- // .. ==> MASK : 0x00400000U VAL : 0x00400000U
- // .. LQSPI_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[23:23] = 0x00000001U
- // .. ==> MASK : 0x00800000U VAL : 0x00800000U
- // .. SMC_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[24:24] = 0x00000001U
- // .. ==> MASK : 0x01000000U VAL : 0x01000000U
- // ..
- EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC044DU),
- // .. FINISH: CLOCK CONTROL SLCR REGISTERS
- // .. START: THIS SHOULD BE BLANK
- // .. FINISH: THIS SHOULD BE BLANK
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_ddr_init_data_3_0[] = {
- // START: top
- // .. START: DDR INITIALIZATION
- // .. .. START: LOCK DDR
- // .. .. reg_ddrc_soft_rstb = 0
- // .. .. ==> 0XF8006000[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_powerdown_en = 0x0
- // .. .. ==> 0XF8006000[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_ddrc_data_bus_width = 0x0
- // .. .. ==> 0XF8006000[3:2] = 0x00000000U
- // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U
- // .. .. reg_ddrc_burst8_refresh = 0x0
- // .. .. ==> 0XF8006000[6:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U
- // .. .. reg_ddrc_rdwr_idle_gap = 0x1
- // .. .. ==> 0XF8006000[13:7] = 0x00000001U
- // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U
- // .. .. reg_ddrc_dis_rd_bypass = 0x0
- // .. .. ==> 0XF8006000[14:14] = 0x00000000U
- // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_act_bypass = 0x0
- // .. .. ==> 0XF8006000[15:15] = 0x00000000U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_auto_refresh = 0x0
- // .. .. ==> 0XF8006000[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
- // .. .. FINISH: LOCK DDR
- // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81
- // .. .. ==> 0XF8006004[11:0] = 0x00000081U
- // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U
- // .. .. reserved_reg_ddrc_active_ranks = 0x1
- // .. .. ==> 0XF8006004[13:12] = 0x00000001U
- // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U
- // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
- // .. .. ==> 0XF8006004[18:14] = 0x00000000U
- // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU ,0x00001081U),
- // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
- // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
- // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU
- // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
- // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
- // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U
- // .. .. reg_ddrc_hpr_xact_run_length = 0xf
- // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
- // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U
- // .. ..
- EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
- // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
- // .. .. ==> 0XF800600C[10:0] = 0x00000001U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U
- // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
- // .. .. ==> 0XF800600C[21:11] = 0x00000002U
- // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U
- // .. .. reg_ddrc_lpr_xact_run_length = 0x8
- // .. .. ==> 0XF800600C[25:22] = 0x00000008U
- // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U
- // .. ..
- EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
- // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
- // .. .. ==> 0XF8006010[10:0] = 0x00000001U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U
- // .. .. reg_ddrc_w_xact_run_length = 0x8
- // .. .. ==> 0XF8006010[14:11] = 0x00000008U
- // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U
- // .. .. reg_ddrc_w_max_starve_x32 = 0x2
- // .. .. ==> 0XF8006010[25:15] = 0x00000002U
- // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U
- // .. ..
- EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
- // .. .. reg_ddrc_t_rc = 0x1a
- // .. .. ==> 0XF8006014[5:0] = 0x0000001AU
- // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001AU
- // .. .. reg_ddrc_t_rfc_min = 0xa0
- // .. .. ==> 0XF8006014[13:6] = 0x000000A0U
- // .. .. ==> MASK : 0x00003FC0U VAL : 0x00002800U
- // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
- // .. .. ==> 0XF8006014[20:14] = 0x00000010U
- // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U
- // .. ..
- EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281AU),
- // .. .. reg_ddrc_wr2pre = 0x12
- // .. .. ==> 0XF8006018[4:0] = 0x00000012U
- // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U
- // .. .. reg_ddrc_powerdown_to_x32 = 0x6
- // .. .. ==> 0XF8006018[9:5] = 0x00000006U
- // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U
- // .. .. reg_ddrc_t_faw = 0x16
- // .. .. ==> 0XF8006018[15:10] = 0x00000016U
- // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005800U
- // .. .. reg_ddrc_t_ras_max = 0x24
- // .. .. ==> 0XF8006018[21:16] = 0x00000024U
- // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U
- // .. .. reg_ddrc_t_ras_min = 0x13
- // .. .. ==> 0XF8006018[26:22] = 0x00000013U
- // .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U
- // .. .. reg_ddrc_t_cke = 0x4
- // .. .. ==> 0XF8006018[31:28] = 0x00000004U
- // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D2U),
- // .. .. reg_ddrc_write_latency = 0x5
- // .. .. ==> 0XF800601C[4:0] = 0x00000005U
- // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U
- // .. .. reg_ddrc_rd2wr = 0x7
- // .. .. ==> 0XF800601C[9:5] = 0x00000007U
- // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U
- // .. .. reg_ddrc_wr2rd = 0xe
- // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
- // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U
- // .. .. reg_ddrc_t_xp = 0x4
- // .. .. ==> 0XF800601C[19:15] = 0x00000004U
- // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U
- // .. .. reg_ddrc_pad_pd = 0x0
- // .. .. ==> 0XF800601C[22:20] = 0x00000000U
- // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U
- // .. .. reg_ddrc_rd2pre = 0x4
- // .. .. ==> 0XF800601C[27:23] = 0x00000004U
- // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U
- // .. .. reg_ddrc_t_rcd = 0x7
- // .. .. ==> 0XF800601C[31:28] = 0x00000007U
- // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U
- // .. ..
- EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
- // .. .. reg_ddrc_t_ccd = 0x4
- // .. .. ==> 0XF8006020[4:2] = 0x00000004U
- // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U
- // .. .. reg_ddrc_t_rrd = 0x6
- // .. .. ==> 0XF8006020[7:5] = 0x00000006U
- // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U
- // .. .. reg_ddrc_refresh_margin = 0x2
- // .. .. ==> 0XF8006020[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. reg_ddrc_t_rp = 0x7
- // .. .. ==> 0XF8006020[15:12] = 0x00000007U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U
- // .. .. reg_ddrc_refresh_to_x32 = 0x8
- // .. .. ==> 0XF8006020[20:16] = 0x00000008U
- // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U
- // .. .. reg_ddrc_mobile = 0x0
- // .. .. ==> 0XF8006020[22:22] = 0x00000000U
- // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U
- // .. .. reg_ddrc_en_dfi_dram_clk_disable = 0x0
- // .. .. ==> 0XF8006020[23:23] = 0x00000000U
- // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U
- // .. .. reg_ddrc_read_latency = 0x7
- // .. .. ==> 0XF8006020[28:24] = 0x00000007U
- // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U
- // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
- // .. .. ==> 0XF8006020[29:29] = 0x00000001U
- // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U
- // .. .. reg_ddrc_dis_pad_pd = 0x0
- // .. .. ==> 0XF8006020[30:30] = 0x00000000U
- // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU ,0x270872D0U),
- // .. .. reg_ddrc_en_2t_timing_mode = 0x0
- // .. .. ==> 0XF8006024[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_prefer_write = 0x0
- // .. .. ==> 0XF8006024[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_wr = 0x0
- // .. .. ==> 0XF8006024[6:6] = 0x00000000U
- // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_addr = 0x0
- // .. .. ==> 0XF8006024[8:7] = 0x00000000U
- // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_data = 0x0
- // .. .. ==> 0XF8006024[24:9] = 0x00000000U
- // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U
- // .. .. ddrc_reg_mr_wr_busy = 0x0
- // .. .. ==> 0XF8006024[25:25] = 0x00000000U
- // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_type = 0x0
- // .. .. ==> 0XF8006024[26:26] = 0x00000000U
- // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_rdata_valid = 0x0
- // .. .. ==> 0XF8006024[27:27] = 0x00000000U
- // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U ,0x00000000U),
- // .. .. reg_ddrc_final_wait_x32 = 0x7
- // .. .. ==> 0XF8006028[6:0] = 0x00000007U
- // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U
- // .. .. reg_ddrc_pre_ocd_x32 = 0x0
- // .. .. ==> 0XF8006028[10:7] = 0x00000000U
- // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U
- // .. .. reg_ddrc_t_mrd = 0x4
- // .. .. ==> 0XF8006028[13:11] = 0x00000004U
- // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U
- // .. ..
- EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
- // .. .. reg_ddrc_emr2 = 0x8
- // .. .. ==> 0XF800602C[15:0] = 0x00000008U
- // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U
- // .. .. reg_ddrc_emr3 = 0x0
- // .. .. ==> 0XF800602C[31:16] = 0x00000000U
- // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
- // .. .. reg_ddrc_mr = 0x930
- // .. .. ==> 0XF8006030[15:0] = 0x00000930U
- // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U
- // .. .. reg_ddrc_emr = 0x4
- // .. .. ==> 0XF8006030[31:16] = 0x00000004U
- // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U
- // .. ..
- EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
- // .. .. reg_ddrc_burst_rdwr = 0x4
- // .. .. ==> 0XF8006034[3:0] = 0x00000004U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U
- // .. .. reg_ddrc_pre_cke_x1024 = 0x105
- // .. .. ==> 0XF8006034[13:4] = 0x00000105U
- // .. .. ==> MASK : 0x00003FF0U VAL : 0x00001050U
- // .. .. reg_ddrc_post_cke_x1024 = 0x1
- // .. .. ==> 0XF8006034[25:16] = 0x00000001U
- // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U
- // .. .. reg_ddrc_burstchop = 0x0
- // .. .. ==> 0XF8006034[28:28] = 0x00000000U
- // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U),
- // .. .. reg_ddrc_force_low_pri_n = 0x0
- // .. .. ==> 0XF8006038[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_dq = 0x0
- // .. .. ==> 0XF8006038[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006038, 0x00000003U ,0x00000000U),
- // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
- // .. .. ==> 0XF800603C[3:0] = 0x00000007U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U
- // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
- // .. .. ==> 0XF800603C[7:4] = 0x00000007U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U
- // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
- // .. .. ==> 0XF800603C[11:8] = 0x00000007U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U
- // .. .. reg_ddrc_addrmap_col_b5 = 0x0
- // .. .. ==> 0XF800603C[15:12] = 0x00000000U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b6 = 0x0
- // .. .. ==> 0XF800603C[19:16] = 0x00000000U
- // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
- // .. .. reg_ddrc_addrmap_col_b2 = 0x0
- // .. .. ==> 0XF8006040[3:0] = 0x00000000U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b3 = 0x0
- // .. .. ==> 0XF8006040[7:4] = 0x00000000U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b4 = 0x0
- // .. .. ==> 0XF8006040[11:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b7 = 0x0
- // .. .. ==> 0XF8006040[15:12] = 0x00000000U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b8 = 0x0
- // .. .. ==> 0XF8006040[19:16] = 0x00000000U
- // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b9 = 0xf
- // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
- // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U
- // .. .. reg_ddrc_addrmap_col_b10 = 0xf
- // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
- // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U
- // .. .. reg_ddrc_addrmap_col_b11 = 0xf
- // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
- // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
- // .. .. reg_ddrc_addrmap_row_b0 = 0x6
- // .. .. ==> 0XF8006044[3:0] = 0x00000006U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U
- // .. .. reg_ddrc_addrmap_row_b1 = 0x6
- // .. .. ==> 0XF8006044[7:4] = 0x00000006U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U
- // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
- // .. .. ==> 0XF8006044[11:8] = 0x00000006U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U
- // .. .. reg_ddrc_addrmap_row_b12 = 0x6
- // .. .. ==> 0XF8006044[15:12] = 0x00000006U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U
- // .. .. reg_ddrc_addrmap_row_b13 = 0x6
- // .. .. ==> 0XF8006044[19:16] = 0x00000006U
- // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U
- // .. .. reg_ddrc_addrmap_row_b14 = 0x6
- // .. .. ==> 0XF8006044[23:20] = 0x00000006U
- // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U
- // .. .. reg_ddrc_addrmap_row_b15 = 0xf
- // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
- // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U),
- // .. .. reg_phy_rd_local_odt = 0x0
- // .. .. ==> 0XF8006048[13:12] = 0x00000000U
- // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U
- // .. .. reg_phy_wr_local_odt = 0x3
- // .. .. ==> 0XF8006048[15:14] = 0x00000003U
- // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U
- // .. .. reg_phy_idle_local_odt = 0x3
- // .. .. ==> 0XF8006048[17:16] = 0x00000003U
- // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U
- // .. ..
- EMIT_MASKWRITE(0XF8006048, 0x0003F000U ,0x0003C000U),
- // .. .. reg_phy_rd_cmd_to_data = 0x0
- // .. .. ==> 0XF8006050[3:0] = 0x00000000U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
- // .. .. reg_phy_wr_cmd_to_data = 0x0
- // .. .. ==> 0XF8006050[7:4] = 0x00000000U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. .. reg_phy_rdc_we_to_re_delay = 0x8
- // .. .. ==> 0XF8006050[11:8] = 0x00000008U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U
- // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
- // .. .. ==> 0XF8006050[15:15] = 0x00000000U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
- // .. .. reg_phy_use_fixed_re = 0x1
- // .. .. ==> 0XF8006050[16:16] = 0x00000001U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U
- // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
- // .. .. ==> 0XF8006050[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
- // .. .. ==> 0XF8006050[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_phy_clk_stall_level = 0x0
- // .. .. ==> 0XF8006050[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
- // .. .. ==> 0XF8006050[27:24] = 0x00000007U
- // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U
- // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
- // .. .. ==> 0XF8006050[31:28] = 0x00000007U
- // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
- // .. .. reg_ddrc_dis_dll_calib = 0x0
- // .. .. ==> 0XF8006058[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006058, 0x00010000U ,0x00000000U),
- // .. .. reg_ddrc_rd_odt_delay = 0x3
- // .. .. ==> 0XF800605C[3:0] = 0x00000003U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U
- // .. .. reg_ddrc_wr_odt_delay = 0x0
- // .. .. ==> 0XF800605C[7:4] = 0x00000000U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. .. reg_ddrc_rd_odt_hold = 0x0
- // .. .. ==> 0XF800605C[11:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U
- // .. .. reg_ddrc_wr_odt_hold = 0x5
- // .. .. ==> 0XF800605C[15:12] = 0x00000005U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U
- // .. ..
- EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
- // .. .. reg_ddrc_pageclose = 0x0
- // .. .. ==> 0XF8006060[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_lpr_num_entries = 0x1f
- // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
- // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU
- // .. .. reg_ddrc_auto_pre_en = 0x0
- // .. .. ==> 0XF8006060[7:7] = 0x00000000U
- // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. .. reg_ddrc_refresh_update_level = 0x0
- // .. .. ==> 0XF8006060[8:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_wc = 0x0
- // .. .. ==> 0XF8006060[9:9] = 0x00000000U
- // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_collision_page_opt = 0x0
- // .. .. ==> 0XF8006060[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_ddrc_selfref_en = 0x0
- // .. .. ==> 0XF8006060[12:12] = 0x00000000U
- // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
- // .. .. reg_ddrc_go2critical_hysteresis = 0x0
- // .. .. ==> 0XF8006064[12:5] = 0x00000000U
- // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U
- // .. .. reg_arb_go2critical_en = 0x1
- // .. .. ==> 0XF8006064[17:17] = 0x00000001U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U
- // .. ..
- EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
- // .. .. reg_ddrc_wrlvl_ww = 0x41
- // .. .. ==> 0XF8006068[7:0] = 0x00000041U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U
- // .. .. reg_ddrc_rdlvl_rr = 0x41
- // .. .. ==> 0XF8006068[15:8] = 0x00000041U
- // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U
- // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
- // .. .. ==> 0XF8006068[25:16] = 0x00000028U
- // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U
- // .. ..
- EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
- // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
- // .. .. ==> 0XF800606C[7:0] = 0x00000010U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U
- // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
- // .. .. ==> 0XF800606C[15:8] = 0x00000016U
- // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U
- // .. ..
- EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
- // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1
- // .. .. ==> 0XF8006078[3:0] = 0x00000001U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U
- // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1
- // .. .. ==> 0XF8006078[7:4] = 0x00000001U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U
- // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1
- // .. .. ==> 0XF8006078[11:8] = 0x00000001U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U
- // .. .. reg_ddrc_t_cksre = 0x6
- // .. .. ==> 0XF8006078[15:12] = 0x00000006U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U
- // .. .. reg_ddrc_t_cksrx = 0x6
- // .. .. ==> 0XF8006078[19:16] = 0x00000006U
- // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U
- // .. .. reg_ddrc_t_ckesr = 0x4
- // .. .. ==> 0XF8006078[25:20] = 0x00000004U
- // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U
- // .. ..
- EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U),
- // .. .. reg_ddrc_t_ckpde = 0x2
- // .. .. ==> 0XF800607C[3:0] = 0x00000002U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U
- // .. .. reg_ddrc_t_ckpdx = 0x2
- // .. .. ==> 0XF800607C[7:4] = 0x00000002U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
- // .. .. reg_ddrc_t_ckdpde = 0x2
- // .. .. ==> 0XF800607C[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. reg_ddrc_t_ckdpdx = 0x2
- // .. .. ==> 0XF800607C[15:12] = 0x00000002U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U
- // .. .. reg_ddrc_t_ckcsx = 0x3
- // .. .. ==> 0XF800607C[19:16] = 0x00000003U
- // .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U
- // .. ..
- EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U),
- // .. .. reg_ddrc_dis_auto_zq = 0x0
- // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_ddr3 = 0x1
- // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. .. reg_ddrc_t_mod = 0x200
- // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
- // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U
- // .. .. reg_ddrc_t_zq_long_nop = 0x200
- // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
- // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U
- // .. .. reg_ddrc_t_zq_short_nop = 0x40
- // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
- // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
- // .. .. t_zq_short_interval_x1024 = 0xcb73
- // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U
- // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U
- // .. .. dram_rstn_x1024 = 0x69
- // .. .. ==> 0XF80060A8[27:20] = 0x00000069U
- // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U
- // .. ..
- EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
- // .. .. deeppowerdown_en = 0x0
- // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. deeppowerdown_to_x1024 = 0xff
- // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
- // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU
- // .. ..
- EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
- // .. .. dfi_wrlvl_max_x1024 = 0xfff
- // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
- // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU
- // .. .. dfi_rdlvl_max_x1024 = 0xfff
- // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
- // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U
- // .. .. ddrc_reg_twrlvl_max_error = 0x0
- // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
- // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U
- // .. .. ddrc_reg_trdlvl_max_error = 0x0
- // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
- // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
- // .. .. reg_ddrc_dfi_wr_level_en = 0x1
- // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
- // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U
- // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
- // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
- // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U
- // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
- // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
- // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
- // .. .. reg_ddrc_skip_ocd = 0x1
- // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
- // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U
- // .. ..
- EMIT_MASKWRITE(0XF80060B4, 0x00000200U ,0x00000200U),
- // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
- // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
- // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U
- // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
- // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
- // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U
- // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
- // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
- // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U
- // .. ..
- EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
- // .. .. START: RESET ECC ERROR
- // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1
- // .. .. ==> 0XF80060C4[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. Clear_Correctable_DRAM_ECC_error = 1
- // .. .. ==> 0XF80060C4[1:1] = 0x00000001U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. ..
- EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U),
- // .. .. FINISH: RESET ECC ERROR
- // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
- // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
- // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
- // .. .. CORR_ECC_LOG_VALID = 0x0
- // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. ECC_CORRECTED_BIT_NUM = 0x0
- // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
- // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
- // .. .. UNCORR_ECC_LOG_VALID = 0x0
- // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
- // .. .. STAT_NUM_CORR_ERR = 0x0
- // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
- // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U
- // .. .. STAT_NUM_UNCORR_ERR = 0x0
- // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
- // .. .. reg_ddrc_ecc_mode = 0x0
- // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_scrub = 0x1
- // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U
- // .. ..
- EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
- // .. .. reg_phy_dif_on = 0x0
- // .. .. ==> 0XF8006114[3:0] = 0x00000000U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
- // .. .. reg_phy_dif_off = 0x0
- // .. .. ==> 0XF8006114[7:4] = 0x00000000U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
- // .. .. reg_phy_data_slice_in_use = 0x1
- // .. .. ==> 0XF8006118[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_phy_rdlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006118[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_inc_mode = 0x0
- // .. .. ==> 0XF8006118[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_wrlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006118[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_bist_shift_dq = 0x0
- // .. .. ==> 0XF8006118[14:6] = 0x00000000U
- // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. .. reg_phy_bist_err_clr = 0x0
- // .. .. ==> 0XF8006118[23:15] = 0x00000000U
- // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. .. reg_phy_dq_offset = 0x40
- // .. .. ==> 0XF8006118[30:24] = 0x00000040U
- // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU ,0x40000001U),
- // .. .. reg_phy_data_slice_in_use = 0x1
- // .. .. ==> 0XF800611C[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_phy_rdlvl_inc_mode = 0x0
- // .. .. ==> 0XF800611C[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_inc_mode = 0x0
- // .. .. ==> 0XF800611C[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_wrlvl_inc_mode = 0x0
- // .. .. ==> 0XF800611C[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_bist_shift_dq = 0x0
- // .. .. ==> 0XF800611C[14:6] = 0x00000000U
- // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. .. reg_phy_bist_err_clr = 0x0
- // .. .. ==> 0XF800611C[23:15] = 0x00000000U
- // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. .. reg_phy_dq_offset = 0x40
- // .. .. ==> 0XF800611C[30:24] = 0x00000040U
- // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU ,0x40000001U),
- // .. .. reg_phy_data_slice_in_use = 0x1
- // .. .. ==> 0XF8006120[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_phy_rdlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006120[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_inc_mode = 0x0
- // .. .. ==> 0XF8006120[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_wrlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006120[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_bist_shift_dq = 0x0
- // .. .. ==> 0XF8006120[14:6] = 0x00000000U
- // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. .. reg_phy_bist_err_clr = 0x0
- // .. .. ==> 0XF8006120[23:15] = 0x00000000U
- // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. .. reg_phy_dq_offset = 0x40
- // .. .. ==> 0XF8006120[30:24] = 0x00000040U
- // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU ,0x40000001U),
- // .. .. reg_phy_data_slice_in_use = 0x1
- // .. .. ==> 0XF8006124[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_phy_rdlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006124[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_inc_mode = 0x0
- // .. .. ==> 0XF8006124[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_wrlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006124[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_bist_shift_dq = 0x0
- // .. .. ==> 0XF8006124[14:6] = 0x00000000U
- // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. .. reg_phy_bist_err_clr = 0x0
- // .. .. ==> 0XF8006124[23:15] = 0x00000000U
- // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. .. reg_phy_dq_offset = 0x40
- // .. .. ==> 0XF8006124[30:24] = 0x00000040U
- // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU ,0x40000001U),
- // .. .. reg_phy_wrlvl_init_ratio = 0x0
- // .. .. ==> 0XF800612C[9:0] = 0x00000000U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_init_ratio = 0xb0
- // .. .. ==> 0XF800612C[19:10] = 0x000000B0U
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002C000U
- // .. ..
- EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0002C000U),
- // .. .. reg_phy_wrlvl_init_ratio = 0x0
- // .. .. ==> 0XF8006130[9:0] = 0x00000000U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_init_ratio = 0xb1
- // .. .. ==> 0XF8006130[19:10] = 0x000000B1U
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002C400U
- // .. ..
- EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x0002C400U),
- // .. .. reg_phy_wrlvl_init_ratio = 0x3
- // .. .. ==> 0XF8006134[9:0] = 0x00000003U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000003U
- // .. .. reg_phy_gatelvl_init_ratio = 0xbc
- // .. .. ==> 0XF8006134[19:10] = 0x000000BCU
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002F000U
- // .. ..
- EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0002F003U),
- // .. .. reg_phy_wrlvl_init_ratio = 0x3
- // .. .. ==> 0XF8006138[9:0] = 0x00000003U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000003U
- // .. .. reg_phy_gatelvl_init_ratio = 0xbb
- // .. .. ==> 0XF8006138[19:10] = 0x000000BBU
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002EC00U
- // .. ..
- EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0002EC03U),
- // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. .. ==> 0XF8006140[9:0] = 0x00000035U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. .. reg_phy_rd_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006140[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006140[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
- // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. .. ==> 0XF8006144[9:0] = 0x00000035U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. .. reg_phy_rd_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006144[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006144[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
- // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. .. ==> 0XF8006148[9:0] = 0x00000035U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. .. reg_phy_rd_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006148[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006148[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
- // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. .. ==> 0XF800614C[9:0] = 0x00000035U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. .. reg_phy_rd_dqs_slave_force = 0x0
- // .. .. ==> 0XF800614C[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. .. ==> 0XF800614C[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
- // .. .. reg_phy_wr_dqs_slave_ratio = 0x77
- // .. .. ==> 0XF8006154[9:0] = 0x00000077U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000077U
- // .. .. reg_phy_wr_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006154[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006154[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000077U),
- // .. .. reg_phy_wr_dqs_slave_ratio = 0x77
- // .. .. ==> 0XF8006158[9:0] = 0x00000077U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000077U
- // .. .. reg_phy_wr_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006158[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006158[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000077U),
- // .. .. reg_phy_wr_dqs_slave_ratio = 0x83
- // .. .. ==> 0XF800615C[9:0] = 0x00000083U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000083U
- // .. .. reg_phy_wr_dqs_slave_force = 0x0
- // .. .. ==> 0XF800615C[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. .. ==> 0XF800615C[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000083U),
- // .. .. reg_phy_wr_dqs_slave_ratio = 0x83
- // .. .. ==> 0XF8006160[9:0] = 0x00000083U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000083U
- // .. .. reg_phy_wr_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006160[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006160[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000083U),
- // .. .. reg_phy_fifo_we_slave_ratio = 0x105
- // .. .. ==> 0XF8006168[10:0] = 0x00000105U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x00000105U
- // .. .. reg_phy_fifo_we_in_force = 0x0
- // .. .. ==> 0XF8006168[11:11] = 0x00000000U
- // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. .. reg_phy_fifo_we_in_delay = 0x0
- // .. .. ==> 0XF8006168[20:12] = 0x00000000U
- // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000105U),
- // .. .. reg_phy_fifo_we_slave_ratio = 0x106
- // .. .. ==> 0XF800616C[10:0] = 0x00000106U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x00000106U
- // .. .. reg_phy_fifo_we_in_force = 0x0
- // .. .. ==> 0XF800616C[11:11] = 0x00000000U
- // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. .. reg_phy_fifo_we_in_delay = 0x0
- // .. .. ==> 0XF800616C[20:12] = 0x00000000U
- // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x00000106U),
- // .. .. reg_phy_fifo_we_slave_ratio = 0x111
- // .. .. ==> 0XF8006170[10:0] = 0x00000111U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x00000111U
- // .. .. reg_phy_fifo_we_in_force = 0x0
- // .. .. ==> 0XF8006170[11:11] = 0x00000000U
- // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. .. reg_phy_fifo_we_in_delay = 0x0
- // .. .. ==> 0XF8006170[20:12] = 0x00000000U
- // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000111U),
- // .. .. reg_phy_fifo_we_slave_ratio = 0x110
- // .. .. ==> 0XF8006174[10:0] = 0x00000110U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x00000110U
- // .. .. reg_phy_fifo_we_in_force = 0x0
- // .. .. ==> 0XF8006174[11:11] = 0x00000000U
- // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. .. reg_phy_fifo_we_in_delay = 0x0
- // .. .. ==> 0XF8006174[20:12] = 0x00000000U
- // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000110U),
- // .. .. reg_phy_wr_data_slave_ratio = 0xb7
- // .. .. ==> 0XF800617C[9:0] = 0x000000B7U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000000B7U
- // .. .. reg_phy_wr_data_slave_force = 0x0
- // .. .. ==> 0XF800617C[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_data_slave_delay = 0x0
- // .. .. ==> 0XF800617C[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000B7U),
- // .. .. reg_phy_wr_data_slave_ratio = 0xb7
- // .. .. ==> 0XF8006180[9:0] = 0x000000B7U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000000B7U
- // .. .. reg_phy_wr_data_slave_force = 0x0
- // .. .. ==> 0XF8006180[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_data_slave_delay = 0x0
- // .. .. ==> 0XF8006180[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000B7U),
- // .. .. reg_phy_wr_data_slave_ratio = 0xc3
- // .. .. ==> 0XF8006184[9:0] = 0x000000C3U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C3U
- // .. .. reg_phy_wr_data_slave_force = 0x0
- // .. .. ==> 0XF8006184[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_data_slave_delay = 0x0
- // .. .. ==> 0XF8006184[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C3U),
- // .. .. reg_phy_wr_data_slave_ratio = 0xc3
- // .. .. ==> 0XF8006188[9:0] = 0x000000C3U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C3U
- // .. .. reg_phy_wr_data_slave_force = 0x0
- // .. .. ==> 0XF8006188[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_data_slave_delay = 0x0
- // .. .. ==> 0XF8006188[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C3U),
- // .. .. reg_phy_bl2 = 0x0
- // .. .. ==> 0XF8006190[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_at_spd_atpg = 0x0
- // .. .. ==> 0XF8006190[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_bist_enable = 0x0
- // .. .. ==> 0XF8006190[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_bist_force_err = 0x0
- // .. .. ==> 0XF8006190[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. reg_phy_bist_mode = 0x0
- // .. .. ==> 0XF8006190[6:5] = 0x00000000U
- // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. .. reg_phy_invert_clkout = 0x1
- // .. .. ==> 0XF8006190[7:7] = 0x00000001U
- // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. .. reg_phy_sel_logic = 0x0
- // .. .. ==> 0XF8006190[9:9] = 0x00000000U
- // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U
- // .. .. reg_phy_ctrl_slave_ratio = 0x100
- // .. .. ==> 0XF8006190[19:10] = 0x00000100U
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U
- // .. .. reg_phy_ctrl_slave_force = 0x0
- // .. .. ==> 0XF8006190[20:20] = 0x00000000U
- // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U
- // .. .. reg_phy_ctrl_slave_delay = 0x0
- // .. .. ==> 0XF8006190[27:21] = 0x00000000U
- // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U
- // .. .. reg_phy_lpddr = 0x0
- // .. .. ==> 0XF8006190[29:29] = 0x00000000U
- // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U
- // .. .. reg_phy_cmd_latency = 0x0
- // .. .. ==> 0XF8006190[30:30] = 0x00000000U
- // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU ,0x00040080U),
- // .. .. reg_phy_wr_rl_delay = 0x2
- // .. .. ==> 0XF8006194[4:0] = 0x00000002U
- // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U
- // .. .. reg_phy_rd_rl_delay = 0x4
- // .. .. ==> 0XF8006194[9:5] = 0x00000004U
- // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U
- // .. .. reg_phy_dll_lock_diff = 0xf
- // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
- // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U
- // .. .. reg_phy_use_wr_level = 0x1
- // .. .. ==> 0XF8006194[14:14] = 0x00000001U
- // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U
- // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
- // .. .. ==> 0XF8006194[15:15] = 0x00000001U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U
- // .. .. reg_phy_use_rd_data_eye_level = 0x1
- // .. .. ==> 0XF8006194[16:16] = 0x00000001U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U
- // .. .. reg_phy_dis_calib_rst = 0x0
- // .. .. ==> 0XF8006194[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_phy_ctrl_slave_delay = 0x0
- // .. .. ==> 0XF8006194[19:18] = 0x00000000U
- // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
- // .. .. reg_arb_page_addr_mask = 0x0
- // .. .. ==> 0XF8006204[31:0] = 0x00000000U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
- // .. .. reg_arb_pri_wr_portn = 0x3ff
- // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_wr_portn = 0x0
- // .. .. ==> 0XF8006208[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. .. ==> 0XF8006208[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. .. ==> 0XF8006208[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006208, 0x000703FFU ,0x000003FFU),
- // .. .. reg_arb_pri_wr_portn = 0x3ff
- // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_wr_portn = 0x0
- // .. .. ==> 0XF800620C[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. .. ==> 0XF800620C[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. .. ==> 0XF800620C[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800620C, 0x000703FFU ,0x000003FFU),
- // .. .. reg_arb_pri_wr_portn = 0x3ff
- // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_wr_portn = 0x0
- // .. .. ==> 0XF8006210[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. .. ==> 0XF8006210[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. .. ==> 0XF8006210[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006210, 0x000703FFU ,0x000003FFU),
- // .. .. reg_arb_pri_wr_portn = 0x3ff
- // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_wr_portn = 0x0
- // .. .. ==> 0XF8006214[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. .. ==> 0XF8006214[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. .. ==> 0XF8006214[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006214, 0x000703FFU ,0x000003FFU),
- // .. .. reg_arb_pri_rd_portn = 0x3ff
- // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_rd_portn = 0x0
- // .. .. ==> 0XF8006218[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. .. ==> 0XF8006218[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. .. ==> 0XF8006218[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_set_hpr_rd_portn = 0x0
- // .. .. ==> 0XF8006218[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
- // .. .. reg_arb_pri_rd_portn = 0x3ff
- // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_rd_portn = 0x0
- // .. .. ==> 0XF800621C[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. .. ==> 0XF800621C[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. .. ==> 0XF800621C[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_set_hpr_rd_portn = 0x0
- // .. .. ==> 0XF800621C[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
- // .. .. reg_arb_pri_rd_portn = 0x3ff
- // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_rd_portn = 0x0
- // .. .. ==> 0XF8006220[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. .. ==> 0XF8006220[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. .. ==> 0XF8006220[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_set_hpr_rd_portn = 0x0
- // .. .. ==> 0XF8006220[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
- // .. .. reg_arb_pri_rd_portn = 0x3ff
- // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_rd_portn = 0x0
- // .. .. ==> 0XF8006224[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. .. ==> 0XF8006224[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. .. ==> 0XF8006224[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_set_hpr_rd_portn = 0x0
- // .. .. ==> 0XF8006224[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
- // .. .. reg_ddrc_lpddr2 = 0x0
- // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_derate_enable = 0x0
- // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_ddrc_mr4_margin = 0x0
- // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U ,0x00000000U),
- // .. .. reg_ddrc_mr4_read_interval = 0x0
- // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
- // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
- // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U
- // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
- // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
- // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U
- // .. .. reg_ddrc_t_mrw = 0x5
- // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
- // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U
- // .. ..
- EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
- // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8
- // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U
- // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
- // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
- // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U
- // .. ..
- EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
- // .. .. START: POLL ON DCI STATUS
- // .. .. DONE = 1
- // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
- // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // .. ..
- EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
- // .. .. FINISH: POLL ON DCI STATUS
- // .. .. START: UNLOCK DDR
- // .. .. reg_ddrc_soft_rstb = 0x1
- // .. .. ==> 0XF8006000[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_ddrc_powerdown_en = 0x0
- // .. .. ==> 0XF8006000[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_ddrc_data_bus_width = 0x0
- // .. .. ==> 0XF8006000[3:2] = 0x00000000U
- // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U
- // .. .. reg_ddrc_burst8_refresh = 0x0
- // .. .. ==> 0XF8006000[6:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U
- // .. .. reg_ddrc_rdwr_idle_gap = 1
- // .. .. ==> 0XF8006000[13:7] = 0x00000001U
- // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U
- // .. .. reg_ddrc_dis_rd_bypass = 0x0
- // .. .. ==> 0XF8006000[14:14] = 0x00000000U
- // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_act_bypass = 0x0
- // .. .. ==> 0XF8006000[15:15] = 0x00000000U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_auto_refresh = 0x0
- // .. .. ==> 0XF8006000[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
- // .. .. FINISH: UNLOCK DDR
- // .. .. START: CHECK DDR STATUS
- // .. .. ddrc_reg_operating_mode = 1
- // .. .. ==> 0XF8006054[2:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U
- // .. ..
- EMIT_MASKPOLL(0XF8006054, 0x00000007U),
- // .. .. FINISH: CHECK DDR STATUS
- // .. FINISH: DDR INITIALIZATION
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_mio_init_data_3_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: OCM REMAPPING
- // .. FINISH: OCM REMAPPING
- // .. START: DDRIOB SETTINGS
- // .. reserved_INP_POWER = 0x0
- // .. ==> 0XF8000B40[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x0
- // .. ==> 0XF8000B40[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. DCI_UPDATE_B = 0x0
- // .. ==> 0XF8000B40[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x0
- // .. ==> 0XF8000B40[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. DCI_TYPE = 0x0
- // .. ==> 0XF8000B40[6:5] = 0x00000000U
- // .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. IBUF_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B40[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B40[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B40[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B40[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
- // .. reserved_INP_POWER = 0x0
- // .. ==> 0XF8000B44[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x0
- // .. ==> 0XF8000B44[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. DCI_UPDATE_B = 0x0
- // .. ==> 0XF8000B44[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x0
- // .. ==> 0XF8000B44[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. DCI_TYPE = 0x0
- // .. ==> 0XF8000B44[6:5] = 0x00000000U
- // .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. IBUF_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B44[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B44[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B44[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B44[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
- // .. reserved_INP_POWER = 0x0
- // .. ==> 0XF8000B48[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x1
- // .. ==> 0XF8000B48[2:1] = 0x00000001U
- // .. ==> MASK : 0x00000006U VAL : 0x00000002U
- // .. DCI_UPDATE_B = 0x0
- // .. ==> 0XF8000B48[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x1
- // .. ==> 0XF8000B48[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. DCI_TYPE = 0x3
- // .. ==> 0XF8000B48[6:5] = 0x00000003U
- // .. ==> MASK : 0x00000060U VAL : 0x00000060U
- // .. IBUF_DISABLE_MODE = 0
- // .. ==> 0XF8000B48[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0
- // .. ==> 0XF8000B48[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B48[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B48[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
- // .. reserved_INP_POWER = 0x0
- // .. ==> 0XF8000B4C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x1
- // .. ==> 0XF8000B4C[2:1] = 0x00000001U
- // .. ==> MASK : 0x00000006U VAL : 0x00000002U
- // .. DCI_UPDATE_B = 0x0
- // .. ==> 0XF8000B4C[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x1
- // .. ==> 0XF8000B4C[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. DCI_TYPE = 0x3
- // .. ==> 0XF8000B4C[6:5] = 0x00000003U
- // .. ==> MASK : 0x00000060U VAL : 0x00000060U
- // .. IBUF_DISABLE_MODE = 0
- // .. ==> 0XF8000B4C[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0
- // .. ==> 0XF8000B4C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B4C[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B4C[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
- // .. reserved_INP_POWER = 0x0
- // .. ==> 0XF8000B50[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x2
- // .. ==> 0XF8000B50[2:1] = 0x00000002U
- // .. ==> MASK : 0x00000006U VAL : 0x00000004U
- // .. DCI_UPDATE_B = 0x0
- // .. ==> 0XF8000B50[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x1
- // .. ==> 0XF8000B50[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. DCI_TYPE = 0x3
- // .. ==> 0XF8000B50[6:5] = 0x00000003U
- // .. ==> MASK : 0x00000060U VAL : 0x00000060U
- // .. IBUF_DISABLE_MODE = 0
- // .. ==> 0XF8000B50[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0
- // .. ==> 0XF8000B50[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B50[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B50[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
- // .. reserved_INP_POWER = 0x0
- // .. ==> 0XF8000B54[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x2
- // .. ==> 0XF8000B54[2:1] = 0x00000002U
- // .. ==> MASK : 0x00000006U VAL : 0x00000004U
- // .. DCI_UPDATE_B = 0x0
- // .. ==> 0XF8000B54[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x1
- // .. ==> 0XF8000B54[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. DCI_TYPE = 0x3
- // .. ==> 0XF8000B54[6:5] = 0x00000003U
- // .. ==> MASK : 0x00000060U VAL : 0x00000060U
- // .. IBUF_DISABLE_MODE = 0
- // .. ==> 0XF8000B54[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0
- // .. ==> 0XF8000B54[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B54[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B54[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
- // .. reserved_INP_POWER = 0x0
- // .. ==> 0XF8000B58[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x0
- // .. ==> 0XF8000B58[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. DCI_UPDATE_B = 0x0
- // .. ==> 0XF8000B58[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x0
- // .. ==> 0XF8000B58[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. DCI_TYPE = 0x0
- // .. ==> 0XF8000B58[6:5] = 0x00000000U
- // .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. IBUF_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B58[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B58[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B58[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B58[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
- // .. reserved_DRIVE_P = 0x1c
- // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
- // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
- // .. reserved_DRIVE_N = 0xc
- // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
- // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
- // .. reserved_SLEW_P = 0x3
- // .. ==> 0XF8000B5C[18:14] = 0x00000003U
- // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U
- // .. reserved_SLEW_N = 0x3
- // .. ==> 0XF8000B5C[23:19] = 0x00000003U
- // .. ==> MASK : 0x00F80000U VAL : 0x00180000U
- // .. reserved_GTL = 0x0
- // .. ==> 0XF8000B5C[26:24] = 0x00000000U
- // .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. reserved_RTERM = 0x0
- // .. ==> 0XF8000B5C[31:27] = 0x00000000U
- // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
- // .. reserved_DRIVE_P = 0x1c
- // .. ==> 0XF8000B60[6:0] = 0x0000001CU
- // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
- // .. reserved_DRIVE_N = 0xc
- // .. ==> 0XF8000B60[13:7] = 0x0000000CU
- // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
- // .. reserved_SLEW_P = 0x6
- // .. ==> 0XF8000B60[18:14] = 0x00000006U
- // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
- // .. reserved_SLEW_N = 0x1f
- // .. ==> 0XF8000B60[23:19] = 0x0000001FU
- // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
- // .. reserved_GTL = 0x0
- // .. ==> 0XF8000B60[26:24] = 0x00000000U
- // .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. reserved_RTERM = 0x0
- // .. ==> 0XF8000B60[31:27] = 0x00000000U
- // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
- // .. reserved_DRIVE_P = 0x1c
- // .. ==> 0XF8000B64[6:0] = 0x0000001CU
- // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
- // .. reserved_DRIVE_N = 0xc
- // .. ==> 0XF8000B64[13:7] = 0x0000000CU
- // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
- // .. reserved_SLEW_P = 0x6
- // .. ==> 0XF8000B64[18:14] = 0x00000006U
- // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
- // .. reserved_SLEW_N = 0x1f
- // .. ==> 0XF8000B64[23:19] = 0x0000001FU
- // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
- // .. reserved_GTL = 0x0
- // .. ==> 0XF8000B64[26:24] = 0x00000000U
- // .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. reserved_RTERM = 0x0
- // .. ==> 0XF8000B64[31:27] = 0x00000000U
- // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
- // .. reserved_DRIVE_P = 0x1c
- // .. ==> 0XF8000B68[6:0] = 0x0000001CU
- // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
- // .. reserved_DRIVE_N = 0xc
- // .. ==> 0XF8000B68[13:7] = 0x0000000CU
- // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
- // .. reserved_SLEW_P = 0x6
- // .. ==> 0XF8000B68[18:14] = 0x00000006U
- // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
- // .. reserved_SLEW_N = 0x1f
- // .. ==> 0XF8000B68[23:19] = 0x0000001FU
- // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
- // .. reserved_GTL = 0x0
- // .. ==> 0XF8000B68[26:24] = 0x00000000U
- // .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. reserved_RTERM = 0x0
- // .. ==> 0XF8000B68[31:27] = 0x00000000U
- // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
- // .. VREF_INT_EN = 0x1
- // .. ==> 0XF8000B6C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. VREF_SEL = 0x4
- // .. ==> 0XF8000B6C[4:1] = 0x00000004U
- // .. ==> MASK : 0x0000001EU VAL : 0x00000008U
- // .. VREF_EXT_EN = 0x0
- // .. ==> 0XF8000B6C[6:5] = 0x00000000U
- // .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. reserved_VREF_PULLUP_EN = 0x0
- // .. ==> 0XF8000B6C[8:7] = 0x00000000U
- // .. ==> MASK : 0x00000180U VAL : 0x00000000U
- // .. REFIO_EN = 0x1
- // .. ==> 0XF8000B6C[9:9] = 0x00000001U
- // .. ==> MASK : 0x00000200U VAL : 0x00000200U
- // .. reserved_REFIO_TEST = 0x3
- // .. ==> 0XF8000B6C[11:10] = 0x00000003U
- // .. ==> MASK : 0x00000C00U VAL : 0x00000C00U
- // .. reserved_REFIO_PULLUP_EN = 0x0
- // .. ==> 0XF8000B6C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. reserved_DRST_B_PULLUP_EN = 0x0
- // .. ==> 0XF8000B6C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // .. reserved_CKE_PULLUP_EN = 0x0
- // .. ==> 0XF8000B6C[14:14] = 0x00000000U
- // .. ==> MASK : 0x00004000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000E09U),
- // .. .. START: ASSERT RESET
- // .. .. RESET = 1
- // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. ..
- EMIT_MASKWRITE(0XF8000B70, 0x00000001U ,0x00000001U),
- // .. .. FINISH: ASSERT RESET
- // .. .. START: DEASSERT RESET
- // .. .. RESET = 0
- // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reserved_VRN_OUT = 0x1
- // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
- // .. ..
- EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
- // .. .. FINISH: DEASSERT RESET
- // .. .. RESET = 0x1
- // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ENABLE = 0x1
- // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. .. reserved_VRP_TRI = 0x0
- // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reserved_VRN_TRI = 0x0
- // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reserved_VRP_OUT = 0x0
- // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. reserved_VRN_OUT = 0x1
- // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
- // .. .. NREF_OPT1 = 0x0
- // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
- // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U
- // .. .. NREF_OPT2 = 0x0
- // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U
- // .. .. NREF_OPT4 = 0x1
- // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
- // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U
- // .. .. PREF_OPT1 = 0x0
- // .. .. ==> 0XF8000B70[15:14] = 0x00000000U
- // .. .. ==> MASK : 0x0000C000U VAL : 0x00000000U
- // .. .. PREF_OPT2 = 0x0
- // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
- // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U
- // .. .. UPDATE_CONTROL = 0x0
- // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
- // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U
- // .. .. reserved_INIT_COMPLETE = 0x0
- // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
- // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U
- // .. .. reserved_TST_CLK = 0x0
- // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
- // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U
- // .. .. reserved_TST_HLN = 0x0
- // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
- // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U
- // .. .. reserved_TST_HLP = 0x0
- // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
- // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U
- // .. .. reserved_TST_RST = 0x0
- // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
- // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
- // .. .. reserved_INT_DCI_EN = 0x0
- // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
- // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU ,0x00000823U),
- // .. FINISH: DDRIOB SETTINGS
- // .. START: MIO PROGRAMMING
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000700[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000700[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000700[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000700[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000700[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000700[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000700[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000700[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000700[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00000600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000704[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000704[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000704[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000704[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000704[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000704[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000704[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000704[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000704[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00000602U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000708[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000708[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000708[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000708[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000708[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000708[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000708[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000708[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000708[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000602U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800070C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF800070C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF800070C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800070C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800070C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800070C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF800070C[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF800070C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800070C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000602U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000710[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000710[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000710[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000710[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000710[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000710[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000710[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000710[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000710[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000602U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000714[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000714[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000714[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000714[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000714[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000714[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000714[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000714[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000714[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000602U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000718[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000718[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000718[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000718[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000718[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000718[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000718[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000718[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000718[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000602U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800071C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800071C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF800071C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800071C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800071C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800071C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF800071C[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF800071C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800071C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000720[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000720[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000720[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000720[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000720[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000720[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000720[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000720[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000720[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000602U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000724[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000724[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000724[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000724[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000724[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000724[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000724[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000724[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000724[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00000600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000728[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000728[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000728[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000728[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000728[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000728[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000728[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000728[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000728[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00000600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800072C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800072C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF800072C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800072C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800072C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800072C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF800072C[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF800072C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800072C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00000600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000730[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000730[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000730[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000730[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000730[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000730[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000730[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000730[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000730[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00000600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000734[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000734[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000734[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000734[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000734[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000734[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000734[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000734[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000734[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00000600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000738[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000738[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000738[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000738[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000738[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000738[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000738[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000738[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000738[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00000600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800073C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800073C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF800073C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800073C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800073C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800073C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF800073C[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF800073C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800073C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00000600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000740[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000740[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000740[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000740[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000740[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000740[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000740[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000740[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000740[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000202U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000744[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000744[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000744[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000744[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000744[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000744[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000744[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000744[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000744[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000202U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000748[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000748[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000748[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000748[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000748[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000748[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000748[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000748[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000748[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000202U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800074C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF800074C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF800074C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800074C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800074C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800074C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF800074C[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF800074C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800074C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000202U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000750[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000750[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000750[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000750[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000750[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000750[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000750[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000750[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000750[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000202U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000754[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000754[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000754[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000754[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000754[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000754[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000754[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000754[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000754[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000202U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000758[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF8000758[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000758[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000758[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000758[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000758[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000758[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000758[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000758[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000203U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF800075C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF800075C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF800075C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800075C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800075C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800075C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF800075C[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF800075C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800075C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000203U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000760[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF8000760[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000760[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000760[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000760[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000760[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000760[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000760[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000760[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000203U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000764[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF8000764[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000764[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000764[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000764[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000764[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000764[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000764[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000764[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000203U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000768[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF8000768[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000768[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000768[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000768[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000768[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000768[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000768[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000768[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000203U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF800076C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF800076C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF800076C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800076C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800076C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800076C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF800076C[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF800076C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800076C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000203U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000770[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000770[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000770[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000770[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000770[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000770[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000770[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000770[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000770[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000774[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF8000774[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000774[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000774[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000774[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000774[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000774[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000774[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000774[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000778[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000778[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000778[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000778[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000778[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000778[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000778[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000778[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000778[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF800077C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF800077C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF800077C[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF800077C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800077C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800077C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF800077C[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF800077C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800077C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000780[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000780[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000780[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000780[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000780[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000780[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000780[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000780[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000780[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000784[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000784[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000784[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000784[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000784[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000784[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000784[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000784[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000784[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000788[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000788[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000788[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000788[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000788[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000788[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000788[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000788[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000788[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800078C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800078C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF800078C[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF800078C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800078C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800078C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF800078C[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF800078C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800078C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000790[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF8000790[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000790[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000790[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000790[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000790[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000790[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000790[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000790[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000794[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000794[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000794[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000794[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000794[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000794[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000794[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000794[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000794[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000798[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000798[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000798[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000798[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000798[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000798[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000798[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000798[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000798[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800079C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800079C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF800079C[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF800079C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800079C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800079C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF800079C[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF800079C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800079C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007A0[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007A0[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007A0[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007A0[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007A0[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF80007A0[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007A0[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007A0[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007A0[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000280U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007A4[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007A4[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007A4[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007A4[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007A4[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF80007A4[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007A4[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007A4[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007A4[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000280U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007A8[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007A8[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007A8[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007A8[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007A8[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF80007A8[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007A8[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007A8[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007A8[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000280U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007AC[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007AC[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007AC[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007AC[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007AC[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF80007AC[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007AC[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007AC[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007AC[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000280U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007B0[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007B0[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007B0[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007B0[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007B0[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF80007B0[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007B0[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007B0[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007B0[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000280U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007B4[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007B4[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007B4[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007B4[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007B4[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF80007B4[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007B4[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007B4[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007B4[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000280U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF80007B8[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. Speed = 0
- // .. ==> 0XF80007B8[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007B8[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007B8[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007B8[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007B8, 0x00003F01U ,0x00000201U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007BC[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007BC[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007BC[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007BC[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF80007BC[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF80007BC[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007BC[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007BC[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007BC[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00000200U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007C0[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007C0[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007C0[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007C0[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 7
- // .. ==> 0XF80007C0[7:5] = 0x00000007U
- // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U
- // .. Speed = 0
- // .. ==> 0XF80007C0[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007C0[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007C0[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007C0[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF80007C4[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF80007C4[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007C4[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007C4[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 7
- // .. ==> 0XF80007C4[7:5] = 0x00000007U
- // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U
- // .. Speed = 0
- // .. ==> 0XF80007C4[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007C4[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007C4[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007C4[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF80007C8[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. Speed = 0
- // .. ==> 0XF80007C8[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007C8[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007C8[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007C8[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007C8, 0x00003F01U ,0x00000201U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007CC[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007CC[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007CC[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007CC[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF80007CC[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF80007CC[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007CC[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007CC[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007CC[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00000200U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007D0[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007D0[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007D0[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007D0[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007D0[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF80007D0[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007D0[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007D0[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007D0[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007D4[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007D4[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007D4[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007D4[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007D4[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF80007D4[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007D4[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007D4[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007D4[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U),
- // .. SDIO0_WP_SEL = 50
- // .. ==> 0XF8000830[5:0] = 0x00000032U
- // .. ==> MASK : 0x0000003FU VAL : 0x00000032U
- // .. SDIO0_CD_SEL = 46
- // .. ==> 0XF8000830[21:16] = 0x0000002EU
- // .. ==> MASK : 0x003F0000U VAL : 0x002E0000U
- // ..
- EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x002E0032U),
- // .. FINISH: MIO PROGRAMMING
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_peripherals_init_data_3_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
- // .. IBUF_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B48[7:7] = 0x00000001U
- // .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. TERM_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B48[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // ..
- EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
- // .. IBUF_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B4C[7:7] = 0x00000001U
- // .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. TERM_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B4C[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // ..
- EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
- // .. IBUF_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B50[7:7] = 0x00000001U
- // .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. TERM_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B50[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // ..
- EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
- // .. IBUF_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B54[7:7] = 0x00000001U
- // .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. TERM_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B54[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // ..
- EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
- // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // .. START: SRAM/NOR SET OPMODE
- // .. FINISH: SRAM/NOR SET OPMODE
- // .. START: UART REGISTERS
- // .. BDIV = 0x6
- // .. ==> 0XE0001034[7:0] = 0x00000006U
- // .. ==> MASK : 0x000000FFU VAL : 0x00000006U
- // ..
- EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
- // .. CD = 0x3e
- // .. ==> 0XE0001018[15:0] = 0x0000003EU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU
- // ..
- EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
- // .. STPBRK = 0x0
- // .. ==> 0XE0001000[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. STTBRK = 0x0
- // .. ==> 0XE0001000[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. RSTTO = 0x0
- // .. ==> 0XE0001000[6:6] = 0x00000000U
- // .. ==> MASK : 0x00000040U VAL : 0x00000000U
- // .. TXDIS = 0x0
- // .. ==> 0XE0001000[5:5] = 0x00000000U
- // .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. TXEN = 0x1
- // .. ==> 0XE0001000[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. RXDIS = 0x0
- // .. ==> 0XE0001000[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. RXEN = 0x1
- // .. ==> 0XE0001000[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. TXRES = 0x1
- // .. ==> 0XE0001000[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. RXRES = 0x1
- // .. ==> 0XE0001000[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // ..
- EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
- // .. CHMODE = 0x0
- // .. ==> 0XE0001004[9:8] = 0x00000000U
- // .. ==> MASK : 0x00000300U VAL : 0x00000000U
- // .. NBSTOP = 0x0
- // .. ==> 0XE0001004[7:6] = 0x00000000U
- // .. ==> MASK : 0x000000C0U VAL : 0x00000000U
- // .. PAR = 0x4
- // .. ==> 0XE0001004[5:3] = 0x00000004U
- // .. ==> MASK : 0x00000038U VAL : 0x00000020U
- // .. CHRL = 0x0
- // .. ==> 0XE0001004[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. CLKS = 0x0
- // .. ==> 0XE0001004[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XE0001004, 0x000003FFU ,0x00000020U),
- // .. FINISH: UART REGISTERS
- // .. START: QSPI REGISTERS
- // .. Holdb_dr = 1
- // .. ==> 0XE000D000[19:19] = 0x00000001U
- // .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // ..
- EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
- // .. FINISH: QSPI REGISTERS
- // .. START: PL POWER ON RESET REGISTERS
- // .. PCFG_POR_CNT_4K = 0
- // .. ==> 0XF8007000[29:29] = 0x00000000U
- // .. ==> MASK : 0x20000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
- // .. FINISH: PL POWER ON RESET REGISTERS
- // .. START: SMC TIMING CALCULATION REGISTER UPDATE
- // .. .. START: NAND SET CYCLE
- // .. .. FINISH: NAND SET CYCLE
- // .. .. START: OPMODE
- // .. .. FINISH: OPMODE
- // .. .. START: DIRECT COMMAND
- // .. .. FINISH: DIRECT COMMAND
- // .. .. START: SRAM/NOR CS0 SET CYCLE
- // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
- // .. .. START: DIRECT COMMAND
- // .. .. FINISH: DIRECT COMMAND
- // .. .. START: NOR CS0 BASE ADDRESS
- // .. .. FINISH: NOR CS0 BASE ADDRESS
- // .. .. START: SRAM/NOR CS1 SET CYCLE
- // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
- // .. .. START: DIRECT COMMAND
- // .. .. FINISH: DIRECT COMMAND
- // .. .. START: NOR CS1 BASE ADDRESS
- // .. .. FINISH: NOR CS1 BASE ADDRESS
- // .. .. START: USB RESET
- // .. .. .. START: USB0 RESET
- // .. .. .. .. START: DIR MODE BANK 0
- // .. .. .. .. DIRECTION_0 = 0x80
- // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U
- // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U),
- // .. .. .. .. FINISH: DIR MODE BANK 0
- // .. .. .. .. START: DIR MODE BANK 1
- // .. .. .. .. FINISH: DIR MODE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. MASK_0_LSW = 0xff7f
- // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
- // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U
- // .. .. .. .. DATA_0_LSW = 0x80
- // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
- // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. START: OUTPUT ENABLE BANK 0
- // .. .. .. .. OP_ENABLE_0 = 0x80
- // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U
- // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U),
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
- // .. .. .. .. START: OUTPUT ENABLE BANK 1
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. MASK_0_LSW = 0xff7f
- // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
- // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U
- // .. .. .. .. DATA_0_LSW = 0x0
- // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
- // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U),
- // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. START: ADD 1 MS DELAY
- // .. .. .. ..
- EMIT_MASKDELAY(0XF8F00200, 1),
- // .. .. .. .. FINISH: ADD 1 MS DELAY
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. MASK_0_LSW = 0xff7f
- // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
- // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U
- // .. .. .. .. DATA_0_LSW = 0x80
- // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
- // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: USB0 RESET
- // .. .. .. START: USB1 RESET
- // .. .. .. .. START: DIR MODE BANK 0
- // .. .. .. .. FINISH: DIR MODE BANK 0
- // .. .. .. .. START: DIR MODE BANK 1
- // .. .. .. .. FINISH: DIR MODE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. START: OUTPUT ENABLE BANK 0
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
- // .. .. .. .. START: OUTPUT ENABLE BANK 1
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. START: ADD 1 MS DELAY
- // .. .. .. ..
- EMIT_MASKDELAY(0XF8F00200, 1),
- // .. .. .. .. FINISH: ADD 1 MS DELAY
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: USB1 RESET
- // .. .. FINISH: USB RESET
- // .. .. START: ENET RESET
- // .. .. .. START: ENET0 RESET
- // .. .. .. .. START: DIR MODE BANK 0
- // .. .. .. .. FINISH: DIR MODE BANK 0
- // .. .. .. .. START: DIR MODE BANK 1
- // .. .. .. .. FINISH: DIR MODE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. START: OUTPUT ENABLE BANK 0
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
- // .. .. .. .. START: OUTPUT ENABLE BANK 1
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. START: ADD 1 MS DELAY
- // .. .. .. ..
- EMIT_MASKDELAY(0XF8F00200, 1),
- // .. .. .. .. FINISH: ADD 1 MS DELAY
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: ENET0 RESET
- // .. .. .. START: ENET1 RESET
- // .. .. .. .. START: DIR MODE BANK 0
- // .. .. .. .. FINISH: DIR MODE BANK 0
- // .. .. .. .. START: DIR MODE BANK 1
- // .. .. .. .. FINISH: DIR MODE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. START: OUTPUT ENABLE BANK 0
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
- // .. .. .. .. START: OUTPUT ENABLE BANK 1
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. START: ADD 1 MS DELAY
- // .. .. .. ..
- EMIT_MASKDELAY(0XF8F00200, 1),
- // .. .. .. .. FINISH: ADD 1 MS DELAY
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: ENET1 RESET
- // .. .. FINISH: ENET RESET
- // .. .. START: I2C RESET
- // .. .. .. START: I2C0 RESET
- // .. .. .. .. START: DIR MODE GPIO BANK0
- // .. .. .. .. FINISH: DIR MODE GPIO BANK0
- // .. .. .. .. START: DIR MODE GPIO BANK1
- // .. .. .. .. FINISH: DIR MODE GPIO BANK1
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. START: OUTPUT ENABLE
- // .. .. .. .. FINISH: OUTPUT ENABLE
- // .. .. .. .. START: OUTPUT ENABLE
- // .. .. .. .. FINISH: OUTPUT ENABLE
- // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. START: ADD 1 MS DELAY
- // .. .. .. ..
- EMIT_MASKDELAY(0XF8F00200, 1),
- // .. .. .. .. FINISH: ADD 1 MS DELAY
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: I2C0 RESET
- // .. .. .. START: I2C1 RESET
- // .. .. .. .. START: DIR MODE GPIO BANK0
- // .. .. .. .. FINISH: DIR MODE GPIO BANK0
- // .. .. .. .. START: DIR MODE GPIO BANK1
- // .. .. .. .. FINISH: DIR MODE GPIO BANK1
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. START: OUTPUT ENABLE
- // .. .. .. .. FINISH: OUTPUT ENABLE
- // .. .. .. .. START: OUTPUT ENABLE
- // .. .. .. .. FINISH: OUTPUT ENABLE
- // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. START: ADD 1 MS DELAY
- // .. .. .. ..
- EMIT_MASKDELAY(0XF8F00200, 1),
- // .. .. .. .. FINISH: ADD 1 MS DELAY
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: I2C1 RESET
- // .. .. FINISH: I2C RESET
- // .. .. START: NOR CHIP SELECT
- // .. .. .. START: DIR MODE BANK 0
- // .. .. .. FINISH: DIR MODE BANK 0
- // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. START: OUTPUT ENABLE BANK 0
- // .. .. .. FINISH: OUTPUT ENABLE BANK 0
- // .. .. FINISH: NOR CHIP SELECT
- // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_post_config_3_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: ENABLING LEVEL SHIFTER
- // .. USER_LVL_INP_EN_0 = 1
- // .. ==> 0XF8000900[3:3] = 0x00000001U
- // .. ==> MASK : 0x00000008U VAL : 0x00000008U
- // .. USER_LVL_OUT_EN_0 = 1
- // .. ==> 0XF8000900[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. USER_LVL_INP_EN_1 = 1
- // .. ==> 0XF8000900[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. USER_LVL_OUT_EN_1 = 1
- // .. ==> 0XF8000900[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // ..
- EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
- // .. FINISH: ENABLING LEVEL SHIFTER
- // .. START: FPGA RESETS TO 0
- // .. reserved_3 = 0
- // .. ==> 0XF8000240[31:25] = 0x00000000U
- // .. ==> MASK : 0xFE000000U VAL : 0x00000000U
- // .. reserved_FPGA_ACP_RST = 0
- // .. ==> 0XF8000240[24:24] = 0x00000000U
- // .. ==> MASK : 0x01000000U VAL : 0x00000000U
- // .. reserved_FPGA_AXDS3_RST = 0
- // .. ==> 0XF8000240[23:23] = 0x00000000U
- // .. ==> MASK : 0x00800000U VAL : 0x00000000U
- // .. reserved_FPGA_AXDS2_RST = 0
- // .. ==> 0XF8000240[22:22] = 0x00000000U
- // .. ==> MASK : 0x00400000U VAL : 0x00000000U
- // .. reserved_FPGA_AXDS1_RST = 0
- // .. ==> 0XF8000240[21:21] = 0x00000000U
- // .. ==> MASK : 0x00200000U VAL : 0x00000000U
- // .. reserved_FPGA_AXDS0_RST = 0
- // .. ==> 0XF8000240[20:20] = 0x00000000U
- // .. ==> MASK : 0x00100000U VAL : 0x00000000U
- // .. reserved_2 = 0
- // .. ==> 0XF8000240[19:18] = 0x00000000U
- // .. ==> MASK : 0x000C0000U VAL : 0x00000000U
- // .. reserved_FSSW1_FPGA_RST = 0
- // .. ==> 0XF8000240[17:17] = 0x00000000U
- // .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. reserved_FSSW0_FPGA_RST = 0
- // .. ==> 0XF8000240[16:16] = 0x00000000U
- // .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. reserved_1 = 0
- // .. ==> 0XF8000240[15:14] = 0x00000000U
- // .. ==> MASK : 0x0000C000U VAL : 0x00000000U
- // .. reserved_FPGA_FMSW1_RST = 0
- // .. ==> 0XF8000240[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // .. reserved_FPGA_FMSW0_RST = 0
- // .. ==> 0XF8000240[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. reserved_FPGA_DMA3_RST = 0
- // .. ==> 0XF8000240[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. reserved_FPGA_DMA2_RST = 0
- // .. ==> 0XF8000240[10:10] = 0x00000000U
- // .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. reserved_FPGA_DMA1_RST = 0
- // .. ==> 0XF8000240[9:9] = 0x00000000U
- // .. ==> MASK : 0x00000200U VAL : 0x00000000U
- // .. reserved_FPGA_DMA0_RST = 0
- // .. ==> 0XF8000240[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. reserved = 0
- // .. ==> 0XF8000240[7:4] = 0x00000000U
- // .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. FPGA3_OUT_RST = 0
- // .. ==> 0XF8000240[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. FPGA2_OUT_RST = 0
- // .. ==> 0XF8000240[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. FPGA1_OUT_RST = 0
- // .. ==> 0XF8000240[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. FPGA0_OUT_RST = 0
- // .. ==> 0XF8000240[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
- // .. FINISH: FPGA RESETS TO 0
- // .. START: AFI REGISTERS
- // .. .. START: AFI0 REGISTERS
- // .. .. FINISH: AFI0 REGISTERS
- // .. .. START: AFI1 REGISTERS
- // .. .. FINISH: AFI1 REGISTERS
- // .. .. START: AFI2 REGISTERS
- // .. .. FINISH: AFI2 REGISTERS
- // .. .. START: AFI3 REGISTERS
- // .. .. FINISH: AFI3 REGISTERS
- // .. FINISH: AFI REGISTERS
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_debug_3_0[] = {
- // START: top
- // .. START: CROSS TRIGGER CONFIGURATIONS
- // .. .. START: UNLOCKING CTI REGISTERS
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. FINISH: UNLOCKING CTI REGISTERS
- // .. .. START: ENABLING CTI MODULES AND CHANNELS
- // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
- // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. FINISH: CROSS TRIGGER CONFIGURATIONS
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_pll_init_data_2_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: PLL SLCR REGISTERS
- // .. .. START: ARM PLL INIT
- // .. .. PLL_RES = 0x2
- // .. .. ==> 0XF8000110[7:4] = 0x00000002U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
- // .. .. PLL_CP = 0x2
- // .. .. ==> 0XF8000110[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. LOCK_CNT = 0xfa
- // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
- // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U
- // .. ..
- EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
- // .. .. .. START: UPDATE FB_DIV
- // .. .. .. PLL_FDIV = 0x28
- // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
- // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
- // .. .. .. FINISH: UPDATE FB_DIV
- // .. .. .. START: BY PASS PLL
- // .. .. .. PLL_BYPASS_FORCE = 1
- // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
- // .. .. .. FINISH: BY PASS PLL
- // .. .. .. START: ASSERT RESET
- // .. .. .. PLL_RESET = 1
- // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
- // .. .. .. FINISH: ASSERT RESET
- // .. .. .. START: DEASSERT RESET
- // .. .. .. PLL_RESET = 0
- // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
- // .. .. .. FINISH: DEASSERT RESET
- // .. .. .. START: CHECK PLL STATUS
- // .. .. .. ARM_PLL_LOCK = 1
- // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ..
- EMIT_MASKPOLL(0XF800010C, 0x00000001U),
- // .. .. .. FINISH: CHECK PLL STATUS
- // .. .. .. START: REMOVE PLL BY PASS
- // .. .. .. PLL_BYPASS_FORCE = 0
- // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
- // .. .. .. FINISH: REMOVE PLL BY PASS
- // .. .. .. SRCSEL = 0x0
- // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. .. .. DIVISOR = 0x2
- // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
- // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U
- // .. .. .. CPU_6OR4XCLKACT = 0x1
- // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
- // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U
- // .. .. .. CPU_3OR2XCLKACT = 0x1
- // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
- // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U
- // .. .. .. CPU_2XCLKACT = 0x1
- // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
- // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U
- // .. .. .. CPU_1XCLKACT = 0x1
- // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
- // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U
- // .. .. .. CPU_PERI_CLKACT = 0x1
- // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
- // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
- // .. .. FINISH: ARM PLL INIT
- // .. .. START: DDR PLL INIT
- // .. .. PLL_RES = 0x2
- // .. .. ==> 0XF8000114[7:4] = 0x00000002U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
- // .. .. PLL_CP = 0x2
- // .. .. ==> 0XF8000114[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. LOCK_CNT = 0x12c
- // .. .. ==> 0XF8000114[21:12] = 0x0000012CU
- // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U
- // .. ..
- EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
- // .. .. .. START: UPDATE FB_DIV
- // .. .. .. PLL_FDIV = 0x20
- // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
- // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
- // .. .. .. FINISH: UPDATE FB_DIV
- // .. .. .. START: BY PASS PLL
- // .. .. .. PLL_BYPASS_FORCE = 1
- // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
- // .. .. .. FINISH: BY PASS PLL
- // .. .. .. START: ASSERT RESET
- // .. .. .. PLL_RESET = 1
- // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
- // .. .. .. FINISH: ASSERT RESET
- // .. .. .. START: DEASSERT RESET
- // .. .. .. PLL_RESET = 0
- // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
- // .. .. .. FINISH: DEASSERT RESET
- // .. .. .. START: CHECK PLL STATUS
- // .. .. .. DDR_PLL_LOCK = 1
- // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. .. ..
- EMIT_MASKPOLL(0XF800010C, 0x00000002U),
- // .. .. .. FINISH: CHECK PLL STATUS
- // .. .. .. START: REMOVE PLL BY PASS
- // .. .. .. PLL_BYPASS_FORCE = 0
- // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
- // .. .. .. FINISH: REMOVE PLL BY PASS
- // .. .. .. DDR_3XCLKACT = 0x1
- // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. .. DDR_2XCLKACT = 0x1
- // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. .. .. DDR_3XCLK_DIVISOR = 0x2
- // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
- // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U
- // .. .. .. DDR_2XCLK_DIVISOR = 0x3
- // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
- // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
- // .. .. FINISH: DDR PLL INIT
- // .. .. START: IO PLL INIT
- // .. .. PLL_RES = 0xc
- // .. .. ==> 0XF8000118[7:4] = 0x0000000CU
- // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U
- // .. .. PLL_CP = 0x2
- // .. .. ==> 0XF8000118[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. LOCK_CNT = 0x145
- // .. .. ==> 0XF8000118[21:12] = 0x00000145U
- // .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U
- // .. ..
- EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U),
- // .. .. .. START: UPDATE FB_DIV
- // .. .. .. PLL_FDIV = 0x1e
- // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU
- // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U),
- // .. .. .. FINISH: UPDATE FB_DIV
- // .. .. .. START: BY PASS PLL
- // .. .. .. PLL_BYPASS_FORCE = 1
- // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
- // .. .. .. FINISH: BY PASS PLL
- // .. .. .. START: ASSERT RESET
- // .. .. .. PLL_RESET = 1
- // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
- // .. .. .. FINISH: ASSERT RESET
- // .. .. .. START: DEASSERT RESET
- // .. .. .. PLL_RESET = 0
- // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
- // .. .. .. FINISH: DEASSERT RESET
- // .. .. .. START: CHECK PLL STATUS
- // .. .. .. IO_PLL_LOCK = 1
- // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. .. ..
- EMIT_MASKPOLL(0XF800010C, 0x00000004U),
- // .. .. .. FINISH: CHECK PLL STATUS
- // .. .. .. START: REMOVE PLL BY PASS
- // .. .. .. PLL_BYPASS_FORCE = 0
- // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
- // .. .. .. FINISH: REMOVE PLL BY PASS
- // .. .. FINISH: IO PLL INIT
- // .. FINISH: PLL SLCR REGISTERS
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_clock_init_data_2_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: CLOCK CONTROL SLCR REGISTERS
- // .. CLKACT = 0x1
- // .. ==> 0XF8000128[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. DIVISOR0 = 0x23
- // .. ==> 0XF8000128[13:8] = 0x00000023U
- // .. ==> MASK : 0x00003F00U VAL : 0x00002300U
- // .. DIVISOR1 = 0x3
- // .. ==> 0XF8000128[25:20] = 0x00000003U
- // .. ==> MASK : 0x03F00000U VAL : 0x00300000U
- // ..
- EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U),
- // .. CLKACT = 0x1
- // .. ==> 0XF8000138[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000138[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
- // .. CLKACT = 0x1
- // .. ==> 0XF8000140[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000140[6:4] = 0x00000000U
- // .. ==> MASK : 0x00000070U VAL : 0x00000000U
- // .. DIVISOR = 0x8
- // .. ==> 0XF8000140[13:8] = 0x00000008U
- // .. ==> MASK : 0x00003F00U VAL : 0x00000800U
- // .. DIVISOR1 = 0x1
- // .. ==> 0XF8000140[25:20] = 0x00000001U
- // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
- // ..
- EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U),
- // .. CLKACT = 0x1
- // .. ==> 0XF800014C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. SRCSEL = 0x0
- // .. ==> 0XF800014C[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR = 0x5
- // .. ==> 0XF800014C[13:8] = 0x00000005U
- // .. ==> MASK : 0x00003F00U VAL : 0x00000500U
- // ..
- EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
- // .. CLKACT0 = 0x1
- // .. ==> 0XF8000150[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. CLKACT1 = 0x0
- // .. ==> 0XF8000150[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000150[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR = 0x14
- // .. ==> 0XF8000150[13:8] = 0x00000014U
- // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
- // ..
- EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U),
- // .. CLKACT0 = 0x0
- // .. ==> 0XF8000154[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. CLKACT1 = 0x1
- // .. ==> 0XF8000154[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000154[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR = 0x14
- // .. ==> 0XF8000154[13:8] = 0x00000014U
- // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
- // ..
- EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U),
- // .. CLKACT = 0x1
- // .. ==> 0XF8000168[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000168[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR = 0x5
- // .. ==> 0XF8000168[13:8] = 0x00000005U
- // .. ==> MASK : 0x00003F00U VAL : 0x00000500U
- // ..
- EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000170[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR0 = 0xa
- // .. ==> 0XF8000170[13:8] = 0x0000000AU
- // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U
- // .. DIVISOR1 = 0x1
- // .. ==> 0XF8000170[25:20] = 0x00000001U
- // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
- // ..
- EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00100A00U),
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000180[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR0 = 0xa
- // .. ==> 0XF8000180[13:8] = 0x0000000AU
- // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U
- // .. DIVISOR1 = 0x1
- // .. ==> 0XF8000180[25:20] = 0x00000001U
- // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
- // ..
- EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00100A00U),
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000190[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR0 = 0x1e
- // .. ==> 0XF8000190[13:8] = 0x0000001EU
- // .. ==> MASK : 0x00003F00U VAL : 0x00001E00U
- // .. DIVISOR1 = 0x1
- // .. ==> 0XF8000190[25:20] = 0x00000001U
- // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
- // ..
- EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101E00U),
- // .. SRCSEL = 0x0
- // .. ==> 0XF80001A0[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR0 = 0x14
- // .. ==> 0XF80001A0[13:8] = 0x00000014U
- // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
- // .. DIVISOR1 = 0x1
- // .. ==> 0XF80001A0[25:20] = 0x00000001U
- // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
- // ..
- EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U),
- // .. CLK_621_TRUE = 0x1
- // .. ==> 0XF80001C4[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // ..
- EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
- // .. DMA_CPU_2XCLKACT = 0x1
- // .. ==> 0XF800012C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. USB0_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. USB1_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[3:3] = 0x00000001U
- // .. ==> MASK : 0x00000008U VAL : 0x00000008U
- // .. GEM0_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[6:6] = 0x00000001U
- // .. ==> MASK : 0x00000040U VAL : 0x00000040U
- // .. GEM1_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. SDI0_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[10:10] = 0x00000001U
- // .. ==> MASK : 0x00000400U VAL : 0x00000400U
- // .. SDI1_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. SPI0_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[14:14] = 0x00000000U
- // .. ==> MASK : 0x00004000U VAL : 0x00000000U
- // .. SPI1_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[15:15] = 0x00000000U
- // .. ==> MASK : 0x00008000U VAL : 0x00000000U
- // .. CAN0_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[16:16] = 0x00000000U
- // .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. CAN1_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[17:17] = 0x00000000U
- // .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. I2C0_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[18:18] = 0x00000001U
- // .. ==> MASK : 0x00040000U VAL : 0x00040000U
- // .. I2C1_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[19:19] = 0x00000001U
- // .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // .. UART0_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[20:20] = 0x00000000U
- // .. ==> MASK : 0x00100000U VAL : 0x00000000U
- // .. UART1_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[21:21] = 0x00000001U
- // .. ==> MASK : 0x00200000U VAL : 0x00200000U
- // .. GPIO_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[22:22] = 0x00000001U
- // .. ==> MASK : 0x00400000U VAL : 0x00400000U
- // .. LQSPI_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[23:23] = 0x00000001U
- // .. ==> MASK : 0x00800000U VAL : 0x00800000U
- // .. SMC_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[24:24] = 0x00000001U
- // .. ==> MASK : 0x01000000U VAL : 0x01000000U
- // ..
- EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC044DU),
- // .. FINISH: CLOCK CONTROL SLCR REGISTERS
- // .. START: THIS SHOULD BE BLANK
- // .. FINISH: THIS SHOULD BE BLANK
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_ddr_init_data_2_0[] = {
- // START: top
- // .. START: DDR INITIALIZATION
- // .. .. START: LOCK DDR
- // .. .. reg_ddrc_soft_rstb = 0
- // .. .. ==> 0XF8006000[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_powerdown_en = 0x0
- // .. .. ==> 0XF8006000[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_ddrc_data_bus_width = 0x0
- // .. .. ==> 0XF8006000[3:2] = 0x00000000U
- // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U
- // .. .. reg_ddrc_burst8_refresh = 0x0
- // .. .. ==> 0XF8006000[6:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U
- // .. .. reg_ddrc_rdwr_idle_gap = 0x1
- // .. .. ==> 0XF8006000[13:7] = 0x00000001U
- // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U
- // .. .. reg_ddrc_dis_rd_bypass = 0x0
- // .. .. ==> 0XF8006000[14:14] = 0x00000000U
- // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_act_bypass = 0x0
- // .. .. ==> 0XF8006000[15:15] = 0x00000000U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_auto_refresh = 0x0
- // .. .. ==> 0XF8006000[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
- // .. .. FINISH: LOCK DDR
- // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81
- // .. .. ==> 0XF8006004[11:0] = 0x00000081U
- // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U
- // .. .. reg_ddrc_active_ranks = 0x1
- // .. .. ==> 0XF8006004[13:12] = 0x00000001U
- // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U
- // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
- // .. .. ==> 0XF8006004[18:14] = 0x00000000U
- // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U
- // .. .. reg_ddrc_wr_odt_block = 0x1
- // .. .. ==> 0XF8006004[20:19] = 0x00000001U
- // .. .. ==> MASK : 0x00180000U VAL : 0x00080000U
- // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0
- // .. .. ==> 0XF8006004[21:21] = 0x00000000U
- // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0
- // .. .. ==> 0XF8006004[26:22] = 0x00000000U
- // .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_open_bank = 0x0
- // .. .. ==> 0XF8006004[27:27] = 0x00000000U
- // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_4bank_ram = 0x0
- // .. .. ==> 0XF8006004[28:28] = 0x00000000U
- // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U),
- // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
- // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
- // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU
- // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
- // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
- // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U
- // .. .. reg_ddrc_hpr_xact_run_length = 0xf
- // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
- // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U
- // .. ..
- EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
- // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
- // .. .. ==> 0XF800600C[10:0] = 0x00000001U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U
- // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
- // .. .. ==> 0XF800600C[21:11] = 0x00000002U
- // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U
- // .. .. reg_ddrc_lpr_xact_run_length = 0x8
- // .. .. ==> 0XF800600C[25:22] = 0x00000008U
- // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U
- // .. ..
- EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
- // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
- // .. .. ==> 0XF8006010[10:0] = 0x00000001U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U
- // .. .. reg_ddrc_w_xact_run_length = 0x8
- // .. .. ==> 0XF8006010[14:11] = 0x00000008U
- // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U
- // .. .. reg_ddrc_w_max_starve_x32 = 0x2
- // .. .. ==> 0XF8006010[25:15] = 0x00000002U
- // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U
- // .. ..
- EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
- // .. .. reg_ddrc_t_rc = 0x1a
- // .. .. ==> 0XF8006014[5:0] = 0x0000001AU
- // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001AU
- // .. .. reg_ddrc_t_rfc_min = 0xa0
- // .. .. ==> 0XF8006014[13:6] = 0x000000A0U
- // .. .. ==> MASK : 0x00003FC0U VAL : 0x00002800U
- // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
- // .. .. ==> 0XF8006014[20:14] = 0x00000010U
- // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U
- // .. ..
- EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281AU),
- // .. .. reg_ddrc_wr2pre = 0x12
- // .. .. ==> 0XF8006018[4:0] = 0x00000012U
- // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U
- // .. .. reg_ddrc_powerdown_to_x32 = 0x6
- // .. .. ==> 0XF8006018[9:5] = 0x00000006U
- // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U
- // .. .. reg_ddrc_t_faw = 0x16
- // .. .. ==> 0XF8006018[15:10] = 0x00000016U
- // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005800U
- // .. .. reg_ddrc_t_ras_max = 0x24
- // .. .. ==> 0XF8006018[21:16] = 0x00000024U
- // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U
- // .. .. reg_ddrc_t_ras_min = 0x13
- // .. .. ==> 0XF8006018[26:22] = 0x00000013U
- // .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U
- // .. .. reg_ddrc_t_cke = 0x4
- // .. .. ==> 0XF8006018[31:28] = 0x00000004U
- // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D2U),
- // .. .. reg_ddrc_write_latency = 0x5
- // .. .. ==> 0XF800601C[4:0] = 0x00000005U
- // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U
- // .. .. reg_ddrc_rd2wr = 0x7
- // .. .. ==> 0XF800601C[9:5] = 0x00000007U
- // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U
- // .. .. reg_ddrc_wr2rd = 0xe
- // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
- // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U
- // .. .. reg_ddrc_t_xp = 0x4
- // .. .. ==> 0XF800601C[19:15] = 0x00000004U
- // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U
- // .. .. reg_ddrc_pad_pd = 0x0
- // .. .. ==> 0XF800601C[22:20] = 0x00000000U
- // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U
- // .. .. reg_ddrc_rd2pre = 0x4
- // .. .. ==> 0XF800601C[27:23] = 0x00000004U
- // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U
- // .. .. reg_ddrc_t_rcd = 0x7
- // .. .. ==> 0XF800601C[31:28] = 0x00000007U
- // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U
- // .. ..
- EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
- // .. .. reg_ddrc_t_ccd = 0x4
- // .. .. ==> 0XF8006020[4:2] = 0x00000004U
- // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U
- // .. .. reg_ddrc_t_rrd = 0x6
- // .. .. ==> 0XF8006020[7:5] = 0x00000006U
- // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U
- // .. .. reg_ddrc_refresh_margin = 0x2
- // .. .. ==> 0XF8006020[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. reg_ddrc_t_rp = 0x7
- // .. .. ==> 0XF8006020[15:12] = 0x00000007U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U
- // .. .. reg_ddrc_refresh_to_x32 = 0x8
- // .. .. ==> 0XF8006020[20:16] = 0x00000008U
- // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U
- // .. .. reg_ddrc_sdram = 0x1
- // .. .. ==> 0XF8006020[21:21] = 0x00000001U
- // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U
- // .. .. reg_ddrc_mobile = 0x0
- // .. .. ==> 0XF8006020[22:22] = 0x00000000U
- // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U
- // .. .. reg_ddrc_clock_stop_en = 0x0
- // .. .. ==> 0XF8006020[23:23] = 0x00000000U
- // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U
- // .. .. reg_ddrc_read_latency = 0x7
- // .. .. ==> 0XF8006020[28:24] = 0x00000007U
- // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U
- // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
- // .. .. ==> 0XF8006020[29:29] = 0x00000001U
- // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U
- // .. .. reg_ddrc_dis_pad_pd = 0x0
- // .. .. ==> 0XF8006020[30:30] = 0x00000000U
- // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U
- // .. .. reg_ddrc_loopback = 0x0
- // .. .. ==> 0XF8006020[31:31] = 0x00000000U
- // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U),
- // .. .. reg_ddrc_en_2t_timing_mode = 0x0
- // .. .. ==> 0XF8006024[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_prefer_write = 0x0
- // .. .. ==> 0XF8006024[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_ddrc_max_rank_rd = 0xf
- // .. .. ==> 0XF8006024[5:2] = 0x0000000FU
- // .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU
- // .. .. reg_ddrc_mr_wr = 0x0
- // .. .. ==> 0XF8006024[6:6] = 0x00000000U
- // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_addr = 0x0
- // .. .. ==> 0XF8006024[8:7] = 0x00000000U
- // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_data = 0x0
- // .. .. ==> 0XF8006024[24:9] = 0x00000000U
- // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U
- // .. .. ddrc_reg_mr_wr_busy = 0x0
- // .. .. ==> 0XF8006024[25:25] = 0x00000000U
- // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_type = 0x0
- // .. .. ==> 0XF8006024[26:26] = 0x00000000U
- // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_rdata_valid = 0x0
- // .. .. ==> 0XF8006024[27:27] = 0x00000000U
- // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU),
- // .. .. reg_ddrc_final_wait_x32 = 0x7
- // .. .. ==> 0XF8006028[6:0] = 0x00000007U
- // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U
- // .. .. reg_ddrc_pre_ocd_x32 = 0x0
- // .. .. ==> 0XF8006028[10:7] = 0x00000000U
- // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U
- // .. .. reg_ddrc_t_mrd = 0x4
- // .. .. ==> 0XF8006028[13:11] = 0x00000004U
- // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U
- // .. ..
- EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
- // .. .. reg_ddrc_emr2 = 0x8
- // .. .. ==> 0XF800602C[15:0] = 0x00000008U
- // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U
- // .. .. reg_ddrc_emr3 = 0x0
- // .. .. ==> 0XF800602C[31:16] = 0x00000000U
- // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
- // .. .. reg_ddrc_mr = 0x930
- // .. .. ==> 0XF8006030[15:0] = 0x00000930U
- // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U
- // .. .. reg_ddrc_emr = 0x4
- // .. .. ==> 0XF8006030[31:16] = 0x00000004U
- // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U
- // .. ..
- EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
- // .. .. reg_ddrc_burst_rdwr = 0x4
- // .. .. ==> 0XF8006034[3:0] = 0x00000004U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U
- // .. .. reg_ddrc_pre_cke_x1024 = 0x105
- // .. .. ==> 0XF8006034[13:4] = 0x00000105U
- // .. .. ==> MASK : 0x00003FF0U VAL : 0x00001050U
- // .. .. reg_ddrc_post_cke_x1024 = 0x1
- // .. .. ==> 0XF8006034[25:16] = 0x00000001U
- // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U
- // .. .. reg_ddrc_burstchop = 0x0
- // .. .. ==> 0XF8006034[28:28] = 0x00000000U
- // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U),
- // .. .. reg_ddrc_force_low_pri_n = 0x0
- // .. .. ==> 0XF8006038[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_dq = 0x0
- // .. .. ==> 0XF8006038[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_debug_mode = 0x0
- // .. .. ==> 0XF8006038[6:6] = 0x00000000U
- // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U
- // .. .. reg_phy_wr_level_start = 0x0
- // .. .. ==> 0XF8006038[7:7] = 0x00000000U
- // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. .. reg_phy_rd_level_start = 0x0
- // .. .. ==> 0XF8006038[8:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. .. reg_phy_dq0_wait_t = 0x0
- // .. .. ==> 0XF8006038[12:9] = 0x00000000U
- // .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U),
- // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
- // .. .. ==> 0XF800603C[3:0] = 0x00000007U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U
- // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
- // .. .. ==> 0XF800603C[7:4] = 0x00000007U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U
- // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
- // .. .. ==> 0XF800603C[11:8] = 0x00000007U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U
- // .. .. reg_ddrc_addrmap_col_b5 = 0x0
- // .. .. ==> 0XF800603C[15:12] = 0x00000000U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b6 = 0x0
- // .. .. ==> 0XF800603C[19:16] = 0x00000000U
- // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
- // .. .. reg_ddrc_addrmap_col_b2 = 0x0
- // .. .. ==> 0XF8006040[3:0] = 0x00000000U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b3 = 0x0
- // .. .. ==> 0XF8006040[7:4] = 0x00000000U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b4 = 0x0
- // .. .. ==> 0XF8006040[11:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b7 = 0x0
- // .. .. ==> 0XF8006040[15:12] = 0x00000000U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b8 = 0x0
- // .. .. ==> 0XF8006040[19:16] = 0x00000000U
- // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b9 = 0xf
- // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
- // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U
- // .. .. reg_ddrc_addrmap_col_b10 = 0xf
- // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
- // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U
- // .. .. reg_ddrc_addrmap_col_b11 = 0xf
- // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
- // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
- // .. .. reg_ddrc_addrmap_row_b0 = 0x6
- // .. .. ==> 0XF8006044[3:0] = 0x00000006U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U
- // .. .. reg_ddrc_addrmap_row_b1 = 0x6
- // .. .. ==> 0XF8006044[7:4] = 0x00000006U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U
- // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
- // .. .. ==> 0XF8006044[11:8] = 0x00000006U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U
- // .. .. reg_ddrc_addrmap_row_b12 = 0x6
- // .. .. ==> 0XF8006044[15:12] = 0x00000006U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U
- // .. .. reg_ddrc_addrmap_row_b13 = 0x6
- // .. .. ==> 0XF8006044[19:16] = 0x00000006U
- // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U
- // .. .. reg_ddrc_addrmap_row_b14 = 0x6
- // .. .. ==> 0XF8006044[23:20] = 0x00000006U
- // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U
- // .. .. reg_ddrc_addrmap_row_b15 = 0xf
- // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
- // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U),
- // .. .. reg_ddrc_rank0_rd_odt = 0x0
- // .. .. ==> 0XF8006048[2:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U
- // .. .. reg_ddrc_rank0_wr_odt = 0x1
- // .. .. ==> 0XF8006048[5:3] = 0x00000001U
- // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U
- // .. .. reg_ddrc_rank1_rd_odt = 0x1
- // .. .. ==> 0XF8006048[8:6] = 0x00000001U
- // .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U
- // .. .. reg_ddrc_rank1_wr_odt = 0x1
- // .. .. ==> 0XF8006048[11:9] = 0x00000001U
- // .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. .. reg_phy_rd_local_odt = 0x0
- // .. .. ==> 0XF8006048[13:12] = 0x00000000U
- // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U
- // .. .. reg_phy_wr_local_odt = 0x3
- // .. .. ==> 0XF8006048[15:14] = 0x00000003U
- // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U
- // .. .. reg_phy_idle_local_odt = 0x3
- // .. .. ==> 0XF8006048[17:16] = 0x00000003U
- // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U
- // .. .. reg_ddrc_rank2_rd_odt = 0x0
- // .. .. ==> 0XF8006048[20:18] = 0x00000000U
- // .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U
- // .. .. reg_ddrc_rank2_wr_odt = 0x0
- // .. .. ==> 0XF8006048[23:21] = 0x00000000U
- // .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U
- // .. .. reg_ddrc_rank3_rd_odt = 0x0
- // .. .. ==> 0XF8006048[26:24] = 0x00000000U
- // .. .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. .. reg_ddrc_rank3_wr_odt = 0x0
- // .. .. ==> 0XF8006048[29:27] = 0x00000000U
- // .. .. ==> MASK : 0x38000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U),
- // .. .. reg_phy_rd_cmd_to_data = 0x0
- // .. .. ==> 0XF8006050[3:0] = 0x00000000U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
- // .. .. reg_phy_wr_cmd_to_data = 0x0
- // .. .. ==> 0XF8006050[7:4] = 0x00000000U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. .. reg_phy_rdc_we_to_re_delay = 0x8
- // .. .. ==> 0XF8006050[11:8] = 0x00000008U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U
- // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
- // .. .. ==> 0XF8006050[15:15] = 0x00000000U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
- // .. .. reg_phy_use_fixed_re = 0x1
- // .. .. ==> 0XF8006050[16:16] = 0x00000001U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U
- // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
- // .. .. ==> 0XF8006050[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
- // .. .. ==> 0XF8006050[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_phy_clk_stall_level = 0x0
- // .. .. ==> 0XF8006050[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
- // .. .. ==> 0XF8006050[27:24] = 0x00000007U
- // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U
- // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
- // .. .. ==> 0XF8006050[31:28] = 0x00000007U
- // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
- // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1
- // .. .. ==> 0XF8006058[7:0] = 0x00000001U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U
- // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1
- // .. .. ==> 0XF8006058[15:8] = 0x00000001U
- // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U
- // .. .. reg_ddrc_dis_dll_calib = 0x0
- // .. .. ==> 0XF8006058[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U),
- // .. .. reg_ddrc_rd_odt_delay = 0x3
- // .. .. ==> 0XF800605C[3:0] = 0x00000003U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U
- // .. .. reg_ddrc_wr_odt_delay = 0x0
- // .. .. ==> 0XF800605C[7:4] = 0x00000000U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. .. reg_ddrc_rd_odt_hold = 0x0
- // .. .. ==> 0XF800605C[11:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U
- // .. .. reg_ddrc_wr_odt_hold = 0x5
- // .. .. ==> 0XF800605C[15:12] = 0x00000005U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U
- // .. ..
- EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
- // .. .. reg_ddrc_pageclose = 0x0
- // .. .. ==> 0XF8006060[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_lpr_num_entries = 0x1f
- // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
- // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU
- // .. .. reg_ddrc_auto_pre_en = 0x0
- // .. .. ==> 0XF8006060[7:7] = 0x00000000U
- // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. .. reg_ddrc_refresh_update_level = 0x0
- // .. .. ==> 0XF8006060[8:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_wc = 0x0
- // .. .. ==> 0XF8006060[9:9] = 0x00000000U
- // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_collision_page_opt = 0x0
- // .. .. ==> 0XF8006060[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_ddrc_selfref_en = 0x0
- // .. .. ==> 0XF8006060[12:12] = 0x00000000U
- // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
- // .. .. reg_ddrc_go2critical_hysteresis = 0x0
- // .. .. ==> 0XF8006064[12:5] = 0x00000000U
- // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U
- // .. .. reg_arb_go2critical_en = 0x1
- // .. .. ==> 0XF8006064[17:17] = 0x00000001U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U
- // .. ..
- EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
- // .. .. reg_ddrc_wrlvl_ww = 0x41
- // .. .. ==> 0XF8006068[7:0] = 0x00000041U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U
- // .. .. reg_ddrc_rdlvl_rr = 0x41
- // .. .. ==> 0XF8006068[15:8] = 0x00000041U
- // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U
- // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
- // .. .. ==> 0XF8006068[25:16] = 0x00000028U
- // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U
- // .. ..
- EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
- // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
- // .. .. ==> 0XF800606C[7:0] = 0x00000010U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U
- // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
- // .. .. ==> 0XF800606C[15:8] = 0x00000016U
- // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U
- // .. ..
- EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
- // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1
- // .. .. ==> 0XF8006078[3:0] = 0x00000001U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U
- // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1
- // .. .. ==> 0XF8006078[7:4] = 0x00000001U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U
- // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1
- // .. .. ==> 0XF8006078[11:8] = 0x00000001U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U
- // .. .. reg_ddrc_t_cksre = 0x6
- // .. .. ==> 0XF8006078[15:12] = 0x00000006U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U
- // .. .. reg_ddrc_t_cksrx = 0x6
- // .. .. ==> 0XF8006078[19:16] = 0x00000006U
- // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U
- // .. .. reg_ddrc_t_ckesr = 0x4
- // .. .. ==> 0XF8006078[25:20] = 0x00000004U
- // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U
- // .. ..
- EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U),
- // .. .. reg_ddrc_t_ckpde = 0x2
- // .. .. ==> 0XF800607C[3:0] = 0x00000002U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U
- // .. .. reg_ddrc_t_ckpdx = 0x2
- // .. .. ==> 0XF800607C[7:4] = 0x00000002U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
- // .. .. reg_ddrc_t_ckdpde = 0x2
- // .. .. ==> 0XF800607C[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. reg_ddrc_t_ckdpdx = 0x2
- // .. .. ==> 0XF800607C[15:12] = 0x00000002U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U
- // .. .. reg_ddrc_t_ckcsx = 0x3
- // .. .. ==> 0XF800607C[19:16] = 0x00000003U
- // .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U
- // .. ..
- EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U),
- // .. .. refresh_timer0_start_value_x32 = 0x0
- // .. .. ==> 0XF80060A0[11:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U
- // .. .. refresh_timer1_start_value_x32 = 0x8
- // .. .. ==> 0XF80060A0[23:12] = 0x00000008U
- // .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U
- // .. ..
- EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U),
- // .. .. reg_ddrc_dis_auto_zq = 0x0
- // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_ddr3 = 0x1
- // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. .. reg_ddrc_t_mod = 0x200
- // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
- // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U
- // .. .. reg_ddrc_t_zq_long_nop = 0x200
- // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
- // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U
- // .. .. reg_ddrc_t_zq_short_nop = 0x40
- // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
- // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
- // .. .. t_zq_short_interval_x1024 = 0xcb73
- // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U
- // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U
- // .. .. dram_rstn_x1024 = 0x69
- // .. .. ==> 0XF80060A8[27:20] = 0x00000069U
- // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U
- // .. ..
- EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
- // .. .. deeppowerdown_en = 0x0
- // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. deeppowerdown_to_x1024 = 0xff
- // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
- // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU
- // .. ..
- EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
- // .. .. dfi_wrlvl_max_x1024 = 0xfff
- // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
- // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU
- // .. .. dfi_rdlvl_max_x1024 = 0xfff
- // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
- // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U
- // .. .. ddrc_reg_twrlvl_max_error = 0x0
- // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
- // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U
- // .. .. ddrc_reg_trdlvl_max_error = 0x0
- // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
- // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
- // .. .. reg_ddrc_dfi_wr_level_en = 0x1
- // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
- // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U
- // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
- // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
- // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U
- // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
- // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
- // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
- // .. .. reg_ddrc_2t_delay = 0x0
- // .. .. ==> 0XF80060B4[8:0] = 0x00000000U
- // .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U
- // .. .. reg_ddrc_skip_ocd = 0x1
- // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
- // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U
- // .. .. reg_ddrc_dis_pre_bypass = 0x0
- // .. .. ==> 0XF80060B4[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U),
- // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
- // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
- // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U
- // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
- // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
- // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U
- // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
- // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
- // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U
- // .. ..
- EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
- // .. .. START: RESET ECC ERROR
- // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1
- // .. .. ==> 0XF80060C4[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. Clear_Correctable_DRAM_ECC_error = 1
- // .. .. ==> 0XF80060C4[1:1] = 0x00000001U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. ..
- EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U),
- // .. .. FINISH: RESET ECC ERROR
- // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
- // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
- // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
- // .. .. CORR_ECC_LOG_VALID = 0x0
- // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. ECC_CORRECTED_BIT_NUM = 0x0
- // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
- // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
- // .. .. UNCORR_ECC_LOG_VALID = 0x0
- // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
- // .. .. STAT_NUM_CORR_ERR = 0x0
- // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
- // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U
- // .. .. STAT_NUM_UNCORR_ERR = 0x0
- // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
- // .. .. reg_ddrc_ecc_mode = 0x0
- // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_scrub = 0x1
- // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U
- // .. ..
- EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
- // .. .. reg_phy_dif_on = 0x0
- // .. .. ==> 0XF8006114[3:0] = 0x00000000U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
- // .. .. reg_phy_dif_off = 0x0
- // .. .. ==> 0XF8006114[7:4] = 0x00000000U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
- // .. .. reg_phy_data_slice_in_use = 0x1
- // .. .. ==> 0XF8006118[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_phy_rdlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006118[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_inc_mode = 0x0
- // .. .. ==> 0XF8006118[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_wrlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006118[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_tx = 0x0
- // .. .. ==> 0XF8006118[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_rx = 0x0
- // .. .. ==> 0XF8006118[5:5] = 0x00000000U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. .. reg_phy_bist_shift_dq = 0x0
- // .. .. ==> 0XF8006118[14:6] = 0x00000000U
- // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. .. reg_phy_bist_err_clr = 0x0
- // .. .. ==> 0XF8006118[23:15] = 0x00000000U
- // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. .. reg_phy_dq_offset = 0x40
- // .. .. ==> 0XF8006118[30:24] = 0x00000040U
- // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U),
- // .. .. reg_phy_data_slice_in_use = 0x1
- // .. .. ==> 0XF800611C[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_phy_rdlvl_inc_mode = 0x0
- // .. .. ==> 0XF800611C[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_inc_mode = 0x0
- // .. .. ==> 0XF800611C[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_wrlvl_inc_mode = 0x0
- // .. .. ==> 0XF800611C[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_tx = 0x0
- // .. .. ==> 0XF800611C[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_rx = 0x0
- // .. .. ==> 0XF800611C[5:5] = 0x00000000U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. .. reg_phy_bist_shift_dq = 0x0
- // .. .. ==> 0XF800611C[14:6] = 0x00000000U
- // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. .. reg_phy_bist_err_clr = 0x0
- // .. .. ==> 0XF800611C[23:15] = 0x00000000U
- // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. .. reg_phy_dq_offset = 0x40
- // .. .. ==> 0XF800611C[30:24] = 0x00000040U
- // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U),
- // .. .. reg_phy_data_slice_in_use = 0x1
- // .. .. ==> 0XF8006120[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_phy_rdlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006120[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_inc_mode = 0x0
- // .. .. ==> 0XF8006120[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_wrlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006120[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_tx = 0x0
- // .. .. ==> 0XF8006120[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_rx = 0x0
- // .. .. ==> 0XF8006120[5:5] = 0x00000000U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. .. reg_phy_bist_shift_dq = 0x0
- // .. .. ==> 0XF8006120[14:6] = 0x00000000U
- // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. .. reg_phy_bist_err_clr = 0x0
- // .. .. ==> 0XF8006120[23:15] = 0x00000000U
- // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. .. reg_phy_dq_offset = 0x40
- // .. .. ==> 0XF8006120[30:24] = 0x00000040U
- // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // .. .. reg_phy_data_slice_in_use = 0x1
- // .. .. ==> 0XF8006120[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_phy_rdlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006120[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_inc_mode = 0x0
- // .. .. ==> 0XF8006120[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_wrlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006120[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_tx = 0x0
- // .. .. ==> 0XF8006120[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_rx = 0x0
- // .. .. ==> 0XF8006120[5:5] = 0x00000000U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. .. reg_phy_bist_shift_dq = 0x0
- // .. .. ==> 0XF8006120[14:6] = 0x00000000U
- // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. .. reg_phy_bist_err_clr = 0x0
- // .. .. ==> 0XF8006120[23:15] = 0x00000000U
- // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. .. reg_phy_dq_offset = 0x40
- // .. .. ==> 0XF8006120[30:24] = 0x00000040U
- // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U),
- // .. .. reg_phy_data_slice_in_use = 0x1
- // .. .. ==> 0XF8006124[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_phy_rdlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006124[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_inc_mode = 0x0
- // .. .. ==> 0XF8006124[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_wrlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006124[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_tx = 0x0
- // .. .. ==> 0XF8006124[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_rx = 0x0
- // .. .. ==> 0XF8006124[5:5] = 0x00000000U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. .. reg_phy_bist_shift_dq = 0x0
- // .. .. ==> 0XF8006124[14:6] = 0x00000000U
- // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. .. reg_phy_bist_err_clr = 0x0
- // .. .. ==> 0XF8006124[23:15] = 0x00000000U
- // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. .. reg_phy_dq_offset = 0x40
- // .. .. ==> 0XF8006124[30:24] = 0x00000040U
- // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U),
- // .. .. reg_phy_wrlvl_init_ratio = 0x0
- // .. .. ==> 0XF800612C[9:0] = 0x00000000U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_init_ratio = 0xb0
- // .. .. ==> 0XF800612C[19:10] = 0x000000B0U
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002C000U
- // .. ..
- EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0002C000U),
- // .. .. reg_phy_wrlvl_init_ratio = 0x0
- // .. .. ==> 0XF8006130[9:0] = 0x00000000U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_init_ratio = 0xb1
- // .. .. ==> 0XF8006130[19:10] = 0x000000B1U
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002C400U
- // .. ..
- EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x0002C400U),
- // .. .. reg_phy_wrlvl_init_ratio = 0x3
- // .. .. ==> 0XF8006134[9:0] = 0x00000003U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000003U
- // .. .. reg_phy_gatelvl_init_ratio = 0xbc
- // .. .. ==> 0XF8006134[19:10] = 0x000000BCU
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002F000U
- // .. ..
- EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0002F003U),
- // .. .. reg_phy_wrlvl_init_ratio = 0x3
- // .. .. ==> 0XF8006138[9:0] = 0x00000003U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000003U
- // .. .. reg_phy_gatelvl_init_ratio = 0xbb
- // .. .. ==> 0XF8006138[19:10] = 0x000000BBU
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002EC00U
- // .. ..
- EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0002EC03U),
- // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. .. ==> 0XF8006140[9:0] = 0x00000035U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. .. reg_phy_rd_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006140[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006140[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
- // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. .. ==> 0XF8006144[9:0] = 0x00000035U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. .. reg_phy_rd_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006144[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006144[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
- // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. .. ==> 0XF8006148[9:0] = 0x00000035U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. .. reg_phy_rd_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006148[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006148[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
- // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. .. ==> 0XF800614C[9:0] = 0x00000035U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. .. reg_phy_rd_dqs_slave_force = 0x0
- // .. .. ==> 0XF800614C[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. .. ==> 0XF800614C[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
- // .. .. reg_phy_wr_dqs_slave_ratio = 0x77
- // .. .. ==> 0XF8006154[9:0] = 0x00000077U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000077U
- // .. .. reg_phy_wr_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006154[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006154[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000077U),
- // .. .. reg_phy_wr_dqs_slave_ratio = 0x77
- // .. .. ==> 0XF8006158[9:0] = 0x00000077U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000077U
- // .. .. reg_phy_wr_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006158[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006158[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000077U),
- // .. .. reg_phy_wr_dqs_slave_ratio = 0x83
- // .. .. ==> 0XF800615C[9:0] = 0x00000083U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000083U
- // .. .. reg_phy_wr_dqs_slave_force = 0x0
- // .. .. ==> 0XF800615C[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. .. ==> 0XF800615C[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000083U),
- // .. .. reg_phy_wr_dqs_slave_ratio = 0x83
- // .. .. ==> 0XF8006160[9:0] = 0x00000083U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000083U
- // .. .. reg_phy_wr_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006160[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006160[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000083U),
- // .. .. reg_phy_fifo_we_slave_ratio = 0x105
- // .. .. ==> 0XF8006168[10:0] = 0x00000105U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x00000105U
- // .. .. reg_phy_fifo_we_in_force = 0x0
- // .. .. ==> 0XF8006168[11:11] = 0x00000000U
- // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. .. reg_phy_fifo_we_in_delay = 0x0
- // .. .. ==> 0XF8006168[20:12] = 0x00000000U
- // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000105U),
- // .. .. reg_phy_fifo_we_slave_ratio = 0x106
- // .. .. ==> 0XF800616C[10:0] = 0x00000106U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x00000106U
- // .. .. reg_phy_fifo_we_in_force = 0x0
- // .. .. ==> 0XF800616C[11:11] = 0x00000000U
- // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. .. reg_phy_fifo_we_in_delay = 0x0
- // .. .. ==> 0XF800616C[20:12] = 0x00000000U
- // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x00000106U),
- // .. .. reg_phy_fifo_we_slave_ratio = 0x111
- // .. .. ==> 0XF8006170[10:0] = 0x00000111U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x00000111U
- // .. .. reg_phy_fifo_we_in_force = 0x0
- // .. .. ==> 0XF8006170[11:11] = 0x00000000U
- // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. .. reg_phy_fifo_we_in_delay = 0x0
- // .. .. ==> 0XF8006170[20:12] = 0x00000000U
- // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000111U),
- // .. .. reg_phy_fifo_we_slave_ratio = 0x110
- // .. .. ==> 0XF8006174[10:0] = 0x00000110U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x00000110U
- // .. .. reg_phy_fifo_we_in_force = 0x0
- // .. .. ==> 0XF8006174[11:11] = 0x00000000U
- // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. .. reg_phy_fifo_we_in_delay = 0x0
- // .. .. ==> 0XF8006174[20:12] = 0x00000000U
- // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000110U),
- // .. .. reg_phy_wr_data_slave_ratio = 0xb7
- // .. .. ==> 0XF800617C[9:0] = 0x000000B7U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000000B7U
- // .. .. reg_phy_wr_data_slave_force = 0x0
- // .. .. ==> 0XF800617C[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_data_slave_delay = 0x0
- // .. .. ==> 0XF800617C[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000B7U),
- // .. .. reg_phy_wr_data_slave_ratio = 0xb7
- // .. .. ==> 0XF8006180[9:0] = 0x000000B7U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000000B7U
- // .. .. reg_phy_wr_data_slave_force = 0x0
- // .. .. ==> 0XF8006180[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_data_slave_delay = 0x0
- // .. .. ==> 0XF8006180[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000B7U),
- // .. .. reg_phy_wr_data_slave_ratio = 0xc3
- // .. .. ==> 0XF8006184[9:0] = 0x000000C3U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C3U
- // .. .. reg_phy_wr_data_slave_force = 0x0
- // .. .. ==> 0XF8006184[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_data_slave_delay = 0x0
- // .. .. ==> 0XF8006184[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C3U),
- // .. .. reg_phy_wr_data_slave_ratio = 0xc3
- // .. .. ==> 0XF8006188[9:0] = 0x000000C3U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C3U
- // .. .. reg_phy_wr_data_slave_force = 0x0
- // .. .. ==> 0XF8006188[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_data_slave_delay = 0x0
- // .. .. ==> 0XF8006188[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C3U),
- // .. .. reg_phy_loopback = 0x0
- // .. .. ==> 0XF8006190[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_phy_bl2 = 0x0
- // .. .. ==> 0XF8006190[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_at_spd_atpg = 0x0
- // .. .. ==> 0XF8006190[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_bist_enable = 0x0
- // .. .. ==> 0XF8006190[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_bist_force_err = 0x0
- // .. .. ==> 0XF8006190[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. reg_phy_bist_mode = 0x0
- // .. .. ==> 0XF8006190[6:5] = 0x00000000U
- // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. .. reg_phy_invert_clkout = 0x1
- // .. .. ==> 0XF8006190[7:7] = 0x00000001U
- // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0
- // .. .. ==> 0XF8006190[8:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. .. reg_phy_sel_logic = 0x0
- // .. .. ==> 0XF8006190[9:9] = 0x00000000U
- // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U
- // .. .. reg_phy_ctrl_slave_ratio = 0x100
- // .. .. ==> 0XF8006190[19:10] = 0x00000100U
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U
- // .. .. reg_phy_ctrl_slave_force = 0x0
- // .. .. ==> 0XF8006190[20:20] = 0x00000000U
- // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U
- // .. .. reg_phy_ctrl_slave_delay = 0x0
- // .. .. ==> 0XF8006190[27:21] = 0x00000000U
- // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U
- // .. .. reg_phy_use_rank0_delays = 0x1
- // .. .. ==> 0XF8006190[28:28] = 0x00000001U
- // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
- // .. .. reg_phy_lpddr = 0x0
- // .. .. ==> 0XF8006190[29:29] = 0x00000000U
- // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U
- // .. .. reg_phy_cmd_latency = 0x0
- // .. .. ==> 0XF8006190[30:30] = 0x00000000U
- // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U
- // .. .. reg_phy_int_lpbk = 0x0
- // .. .. ==> 0XF8006190[31:31] = 0x00000000U
- // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U),
- // .. .. reg_phy_wr_rl_delay = 0x2
- // .. .. ==> 0XF8006194[4:0] = 0x00000002U
- // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U
- // .. .. reg_phy_rd_rl_delay = 0x4
- // .. .. ==> 0XF8006194[9:5] = 0x00000004U
- // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U
- // .. .. reg_phy_dll_lock_diff = 0xf
- // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
- // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U
- // .. .. reg_phy_use_wr_level = 0x1
- // .. .. ==> 0XF8006194[14:14] = 0x00000001U
- // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U
- // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
- // .. .. ==> 0XF8006194[15:15] = 0x00000001U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U
- // .. .. reg_phy_use_rd_data_eye_level = 0x1
- // .. .. ==> 0XF8006194[16:16] = 0x00000001U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U
- // .. .. reg_phy_dis_calib_rst = 0x0
- // .. .. ==> 0XF8006194[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_phy_ctrl_slave_delay = 0x0
- // .. .. ==> 0XF8006194[19:18] = 0x00000000U
- // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
- // .. .. reg_arb_page_addr_mask = 0x0
- // .. .. ==> 0XF8006204[31:0] = 0x00000000U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
- // .. .. reg_arb_pri_wr_portn = 0x3ff
- // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_wr_portn = 0x0
- // .. .. ==> 0XF8006208[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. .. ==> 0XF8006208[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. .. ==> 0XF8006208[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_dis_rmw_portn = 0x1
- // .. .. ==> 0XF8006208[19:19] = 0x00000001U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // .. ..
- EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU),
- // .. .. reg_arb_pri_wr_portn = 0x3ff
- // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_wr_portn = 0x0
- // .. .. ==> 0XF800620C[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. .. ==> 0XF800620C[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. .. ==> 0XF800620C[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_dis_rmw_portn = 0x1
- // .. .. ==> 0XF800620C[19:19] = 0x00000001U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // .. ..
- EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU),
- // .. .. reg_arb_pri_wr_portn = 0x3ff
- // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_wr_portn = 0x0
- // .. .. ==> 0XF8006210[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. .. ==> 0XF8006210[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. .. ==> 0XF8006210[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_dis_rmw_portn = 0x1
- // .. .. ==> 0XF8006210[19:19] = 0x00000001U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // .. ..
- EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU),
- // .. .. reg_arb_pri_wr_portn = 0x3ff
- // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_wr_portn = 0x0
- // .. .. ==> 0XF8006214[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. .. ==> 0XF8006214[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. .. ==> 0XF8006214[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_dis_rmw_portn = 0x1
- // .. .. ==> 0XF8006214[19:19] = 0x00000001U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // .. ..
- EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU),
- // .. .. reg_arb_pri_rd_portn = 0x3ff
- // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_rd_portn = 0x0
- // .. .. ==> 0XF8006218[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. .. ==> 0XF8006218[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. .. ==> 0XF8006218[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_set_hpr_rd_portn = 0x0
- // .. .. ==> 0XF8006218[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
- // .. .. reg_arb_pri_rd_portn = 0x3ff
- // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_rd_portn = 0x0
- // .. .. ==> 0XF800621C[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. .. ==> 0XF800621C[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. .. ==> 0XF800621C[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_set_hpr_rd_portn = 0x0
- // .. .. ==> 0XF800621C[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
- // .. .. reg_arb_pri_rd_portn = 0x3ff
- // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_rd_portn = 0x0
- // .. .. ==> 0XF8006220[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. .. ==> 0XF8006220[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. .. ==> 0XF8006220[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_set_hpr_rd_portn = 0x0
- // .. .. ==> 0XF8006220[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
- // .. .. reg_arb_pri_rd_portn = 0x3ff
- // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_rd_portn = 0x0
- // .. .. ==> 0XF8006224[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. .. ==> 0XF8006224[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. .. ==> 0XF8006224[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_set_hpr_rd_portn = 0x0
- // .. .. ==> 0XF8006224[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
- // .. .. reg_ddrc_lpddr2 = 0x0
- // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_per_bank_refresh = 0x0
- // .. .. ==> 0XF80062A8[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_ddrc_derate_enable = 0x0
- // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_ddrc_mr4_margin = 0x0
- // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U),
- // .. .. reg_ddrc_mr4_read_interval = 0x0
- // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
- // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
- // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U
- // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
- // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
- // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U
- // .. .. reg_ddrc_t_mrw = 0x5
- // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
- // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U
- // .. ..
- EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
- // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8
- // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U
- // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
- // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
- // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U
- // .. ..
- EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
- // .. .. START: POLL ON DCI STATUS
- // .. .. DONE = 1
- // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
- // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // .. ..
- EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
- // .. .. FINISH: POLL ON DCI STATUS
- // .. .. START: UNLOCK DDR
- // .. .. reg_ddrc_soft_rstb = 0x1
- // .. .. ==> 0XF8006000[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_ddrc_powerdown_en = 0x0
- // .. .. ==> 0XF8006000[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_ddrc_data_bus_width = 0x0
- // .. .. ==> 0XF8006000[3:2] = 0x00000000U
- // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U
- // .. .. reg_ddrc_burst8_refresh = 0x0
- // .. .. ==> 0XF8006000[6:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U
- // .. .. reg_ddrc_rdwr_idle_gap = 1
- // .. .. ==> 0XF8006000[13:7] = 0x00000001U
- // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U
- // .. .. reg_ddrc_dis_rd_bypass = 0x0
- // .. .. ==> 0XF8006000[14:14] = 0x00000000U
- // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_act_bypass = 0x0
- // .. .. ==> 0XF8006000[15:15] = 0x00000000U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_auto_refresh = 0x0
- // .. .. ==> 0XF8006000[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
- // .. .. FINISH: UNLOCK DDR
- // .. .. START: CHECK DDR STATUS
- // .. .. ddrc_reg_operating_mode = 1
- // .. .. ==> 0XF8006054[2:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U
- // .. ..
- EMIT_MASKPOLL(0XF8006054, 0x00000007U),
- // .. .. FINISH: CHECK DDR STATUS
- // .. FINISH: DDR INITIALIZATION
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_mio_init_data_2_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: OCM REMAPPING
- // .. FINISH: OCM REMAPPING
- // .. START: DDRIOB SETTINGS
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B40[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x0
- // .. ==> 0XF8000B40[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B40[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x0
- // .. ==> 0XF8000B40[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. DCR_TYPE = 0x0
- // .. ==> 0XF8000B40[6:5] = 0x00000000U
- // .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. IBUF_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B40[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B40[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B40[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B40[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B44[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x0
- // .. ==> 0XF8000B44[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B44[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x0
- // .. ==> 0XF8000B44[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. DCR_TYPE = 0x0
- // .. ==> 0XF8000B44[6:5] = 0x00000000U
- // .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. IBUF_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B44[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B44[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B44[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B44[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B48[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x1
- // .. ==> 0XF8000B48[2:1] = 0x00000001U
- // .. ==> MASK : 0x00000006U VAL : 0x00000002U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B48[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x1
- // .. ==> 0XF8000B48[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. DCR_TYPE = 0x3
- // .. ==> 0XF8000B48[6:5] = 0x00000003U
- // .. ==> MASK : 0x00000060U VAL : 0x00000060U
- // .. IBUF_DISABLE_MODE = 0
- // .. ==> 0XF8000B48[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0
- // .. ==> 0XF8000B48[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B48[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B48[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B4C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x1
- // .. ==> 0XF8000B4C[2:1] = 0x00000001U
- // .. ==> MASK : 0x00000006U VAL : 0x00000002U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B4C[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x1
- // .. ==> 0XF8000B4C[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. DCR_TYPE = 0x3
- // .. ==> 0XF8000B4C[6:5] = 0x00000003U
- // .. ==> MASK : 0x00000060U VAL : 0x00000060U
- // .. IBUF_DISABLE_MODE = 0
- // .. ==> 0XF8000B4C[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0
- // .. ==> 0XF8000B4C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B4C[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B4C[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B50[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x2
- // .. ==> 0XF8000B50[2:1] = 0x00000002U
- // .. ==> MASK : 0x00000006U VAL : 0x00000004U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B50[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x1
- // .. ==> 0XF8000B50[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. DCR_TYPE = 0x3
- // .. ==> 0XF8000B50[6:5] = 0x00000003U
- // .. ==> MASK : 0x00000060U VAL : 0x00000060U
- // .. IBUF_DISABLE_MODE = 0
- // .. ==> 0XF8000B50[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0
- // .. ==> 0XF8000B50[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B50[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B50[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B54[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x2
- // .. ==> 0XF8000B54[2:1] = 0x00000002U
- // .. ==> MASK : 0x00000006U VAL : 0x00000004U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B54[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x1
- // .. ==> 0XF8000B54[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. DCR_TYPE = 0x3
- // .. ==> 0XF8000B54[6:5] = 0x00000003U
- // .. ==> MASK : 0x00000060U VAL : 0x00000060U
- // .. IBUF_DISABLE_MODE = 0
- // .. ==> 0XF8000B54[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0
- // .. ==> 0XF8000B54[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B54[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B54[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B58[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x0
- // .. ==> 0XF8000B58[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B58[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x0
- // .. ==> 0XF8000B58[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. DCR_TYPE = 0x0
- // .. ==> 0XF8000B58[6:5] = 0x00000000U
- // .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. IBUF_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B58[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B58[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B58[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B58[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
- // .. DRIVE_P = 0x1c
- // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
- // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
- // .. DRIVE_N = 0xc
- // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
- // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
- // .. SLEW_P = 0x3
- // .. ==> 0XF8000B5C[18:14] = 0x00000003U
- // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U
- // .. SLEW_N = 0x3
- // .. ==> 0XF8000B5C[23:19] = 0x00000003U
- // .. ==> MASK : 0x00F80000U VAL : 0x00180000U
- // .. GTL = 0x0
- // .. ==> 0XF8000B5C[26:24] = 0x00000000U
- // .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. RTERM = 0x0
- // .. ==> 0XF8000B5C[31:27] = 0x00000000U
- // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
- // .. DRIVE_P = 0x1c
- // .. ==> 0XF8000B60[6:0] = 0x0000001CU
- // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
- // .. DRIVE_N = 0xc
- // .. ==> 0XF8000B60[13:7] = 0x0000000CU
- // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
- // .. SLEW_P = 0x6
- // .. ==> 0XF8000B60[18:14] = 0x00000006U
- // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
- // .. SLEW_N = 0x1f
- // .. ==> 0XF8000B60[23:19] = 0x0000001FU
- // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
- // .. GTL = 0x0
- // .. ==> 0XF8000B60[26:24] = 0x00000000U
- // .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. RTERM = 0x0
- // .. ==> 0XF8000B60[31:27] = 0x00000000U
- // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
- // .. DRIVE_P = 0x1c
- // .. ==> 0XF8000B64[6:0] = 0x0000001CU
- // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
- // .. DRIVE_N = 0xc
- // .. ==> 0XF8000B64[13:7] = 0x0000000CU
- // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
- // .. SLEW_P = 0x6
- // .. ==> 0XF8000B64[18:14] = 0x00000006U
- // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
- // .. SLEW_N = 0x1f
- // .. ==> 0XF8000B64[23:19] = 0x0000001FU
- // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
- // .. GTL = 0x0
- // .. ==> 0XF8000B64[26:24] = 0x00000000U
- // .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. RTERM = 0x0
- // .. ==> 0XF8000B64[31:27] = 0x00000000U
- // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
- // .. DRIVE_P = 0x1c
- // .. ==> 0XF8000B68[6:0] = 0x0000001CU
- // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
- // .. DRIVE_N = 0xc
- // .. ==> 0XF8000B68[13:7] = 0x0000000CU
- // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
- // .. SLEW_P = 0x6
- // .. ==> 0XF8000B68[18:14] = 0x00000006U
- // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
- // .. SLEW_N = 0x1f
- // .. ==> 0XF8000B68[23:19] = 0x0000001FU
- // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
- // .. GTL = 0x0
- // .. ==> 0XF8000B68[26:24] = 0x00000000U
- // .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. RTERM = 0x0
- // .. ==> 0XF8000B68[31:27] = 0x00000000U
- // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
- // .. VREF_INT_EN = 0x1
- // .. ==> 0XF8000B6C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. VREF_SEL = 0x4
- // .. ==> 0XF8000B6C[4:1] = 0x00000004U
- // .. ==> MASK : 0x0000001EU VAL : 0x00000008U
- // .. VREF_EXT_EN = 0x0
- // .. ==> 0XF8000B6C[6:5] = 0x00000000U
- // .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. VREF_PULLUP_EN = 0x0
- // .. ==> 0XF8000B6C[8:7] = 0x00000000U
- // .. ==> MASK : 0x00000180U VAL : 0x00000000U
- // .. REFIO_EN = 0x1
- // .. ==> 0XF8000B6C[9:9] = 0x00000001U
- // .. ==> MASK : 0x00000200U VAL : 0x00000200U
- // .. REFIO_TEST = 0x3
- // .. ==> 0XF8000B6C[11:10] = 0x00000003U
- // .. ==> MASK : 0x00000C00U VAL : 0x00000C00U
- // .. REFIO_PULLUP_EN = 0x0
- // .. ==> 0XF8000B6C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DRST_B_PULLUP_EN = 0x0
- // .. ==> 0XF8000B6C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // .. CKE_PULLUP_EN = 0x0
- // .. ==> 0XF8000B6C[14:14] = 0x00000000U
- // .. ==> MASK : 0x00004000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000E09U),
- // .. .. START: ASSERT RESET
- // .. .. RESET = 1
- // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. VRN_OUT = 0x1
- // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
- // .. ..
- EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U),
- // .. .. FINISH: ASSERT RESET
- // .. .. START: DEASSERT RESET
- // .. .. RESET = 0
- // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. VRN_OUT = 0x1
- // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
- // .. ..
- EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
- // .. .. FINISH: DEASSERT RESET
- // .. .. RESET = 0x1
- // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ENABLE = 0x1
- // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. .. VRP_TRI = 0x0
- // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. VRN_TRI = 0x0
- // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. VRP_OUT = 0x0
- // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. VRN_OUT = 0x1
- // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
- // .. .. NREF_OPT1 = 0x0
- // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
- // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U
- // .. .. NREF_OPT2 = 0x0
- // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U
- // .. .. NREF_OPT4 = 0x1
- // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
- // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U
- // .. .. PREF_OPT1 = 0x0
- // .. .. ==> 0XF8000B70[16:14] = 0x00000000U
- // .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U
- // .. .. PREF_OPT2 = 0x0
- // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
- // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U
- // .. .. UPDATE_CONTROL = 0x0
- // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
- // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U
- // .. .. INIT_COMPLETE = 0x0
- // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
- // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U
- // .. .. TST_CLK = 0x0
- // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
- // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U
- // .. .. TST_HLN = 0x0
- // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
- // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U
- // .. .. TST_HLP = 0x0
- // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
- // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U
- // .. .. TST_RST = 0x0
- // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
- // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
- // .. .. INT_DCI_EN = 0x0
- // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
- // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U),
- // .. FINISH: DDRIOB SETTINGS
- // .. START: MIO PROGRAMMING
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000700[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000700[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000700[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000700[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000700[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000700[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000700[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000700[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000700[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00000600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000704[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000704[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000704[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000704[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000704[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000704[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000704[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000704[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000704[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00000602U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000708[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000708[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000708[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000708[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000708[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000708[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000708[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000708[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000708[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000602U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800070C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF800070C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF800070C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800070C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800070C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800070C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF800070C[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF800070C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800070C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000602U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000710[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000710[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000710[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000710[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000710[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000710[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000710[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000710[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000710[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000602U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000714[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000714[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000714[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000714[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000714[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000714[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000714[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000714[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000714[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000602U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000718[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000718[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000718[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000718[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000718[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000718[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000718[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000718[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000718[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000602U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800071C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800071C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF800071C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800071C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800071C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800071C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF800071C[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF800071C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800071C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000720[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000720[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000720[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000720[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000720[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000720[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000720[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000720[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000720[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000602U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000724[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000724[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000724[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000724[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000724[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000724[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000724[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000724[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000724[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00000600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000728[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000728[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000728[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000728[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000728[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000728[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000728[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000728[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000728[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00000600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800072C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800072C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF800072C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800072C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800072C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800072C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF800072C[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF800072C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800072C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00000600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000730[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000730[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000730[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000730[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000730[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000730[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000730[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000730[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000730[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00000600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000734[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000734[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000734[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000734[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000734[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000734[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000734[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000734[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000734[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00000600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000738[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000738[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000738[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000738[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000738[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000738[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000738[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000738[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000738[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00000600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800073C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800073C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF800073C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800073C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800073C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800073C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF800073C[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF800073C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800073C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00000600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000740[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000740[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000740[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000740[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000740[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000740[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000740[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000740[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000740[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000202U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000744[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000744[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000744[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000744[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000744[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000744[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000744[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000744[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000744[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000202U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000748[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000748[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000748[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000748[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000748[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000748[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000748[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000748[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000748[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000202U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800074C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF800074C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF800074C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800074C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800074C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800074C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF800074C[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF800074C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800074C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000202U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000750[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000750[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000750[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000750[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000750[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000750[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000750[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000750[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000750[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000202U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000754[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000754[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000754[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000754[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000754[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000754[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000754[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000754[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000754[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000202U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000758[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF8000758[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000758[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000758[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000758[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000758[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000758[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000758[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000758[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000203U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF800075C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF800075C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF800075C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800075C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800075C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800075C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF800075C[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF800075C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800075C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000203U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000760[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF8000760[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000760[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000760[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000760[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000760[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000760[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000760[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000760[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000203U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000764[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF8000764[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000764[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000764[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000764[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000764[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000764[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000764[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000764[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000203U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000768[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF8000768[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000768[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000768[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000768[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000768[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000768[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000768[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000768[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000203U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF800076C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF800076C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF800076C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800076C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800076C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800076C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF800076C[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF800076C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800076C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000203U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000770[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000770[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000770[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000770[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000770[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000770[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000770[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000770[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000770[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000774[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF8000774[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000774[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000774[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000774[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000774[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000774[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000774[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000774[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000778[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000778[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000778[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000778[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000778[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000778[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000778[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000778[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000778[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF800077C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF800077C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF800077C[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF800077C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800077C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800077C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF800077C[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF800077C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800077C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000780[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000780[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000780[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000780[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000780[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000780[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000780[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000780[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000780[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000784[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000784[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000784[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000784[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000784[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000784[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000784[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000784[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000784[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000788[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000788[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000788[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000788[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000788[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000788[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000788[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000788[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000788[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800078C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800078C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF800078C[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF800078C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800078C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800078C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF800078C[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF800078C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800078C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000790[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF8000790[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000790[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000790[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000790[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000790[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000790[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000790[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000790[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000794[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000794[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000794[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000794[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000794[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000794[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000794[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000794[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000794[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000798[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000798[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000798[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000798[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000798[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000798[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000798[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000798[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000798[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800079C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800079C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF800079C[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF800079C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800079C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800079C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF800079C[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF800079C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800079C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007A0[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007A0[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007A0[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007A0[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007A0[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF80007A0[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007A0[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007A0[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007A0[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000280U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007A4[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007A4[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007A4[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007A4[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007A4[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF80007A4[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007A4[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007A4[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007A4[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000280U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007A8[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007A8[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007A8[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007A8[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007A8[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF80007A8[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007A8[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007A8[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007A8[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000280U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007AC[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007AC[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007AC[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007AC[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007AC[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF80007AC[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007AC[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007AC[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007AC[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000280U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007B0[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007B0[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007B0[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007B0[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007B0[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF80007B0[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007B0[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007B0[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007B0[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000280U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007B4[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007B4[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007B4[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007B4[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007B4[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF80007B4[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007B4[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007B4[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007B4[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000280U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF80007B8[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. Speed = 0
- // .. ==> 0XF80007B8[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007B8[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007B8[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007B8[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007B8, 0x00003F01U ,0x00000201U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007BC[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007BC[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007BC[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007BC[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF80007BC[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF80007BC[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007BC[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007BC[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007BC[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00000200U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007C0[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007C0[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007C0[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007C0[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 7
- // .. ==> 0XF80007C0[7:5] = 0x00000007U
- // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U
- // .. Speed = 0
- // .. ==> 0XF80007C0[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007C0[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007C0[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007C0[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF80007C4[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF80007C4[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007C4[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007C4[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 7
- // .. ==> 0XF80007C4[7:5] = 0x00000007U
- // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U
- // .. Speed = 0
- // .. ==> 0XF80007C4[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007C4[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007C4[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007C4[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF80007C8[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. Speed = 0
- // .. ==> 0XF80007C8[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007C8[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007C8[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007C8[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007C8, 0x00003F01U ,0x00000201U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007CC[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007CC[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007CC[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007CC[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF80007CC[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF80007CC[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007CC[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007CC[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007CC[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00000200U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007D0[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007D0[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007D0[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007D0[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007D0[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF80007D0[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007D0[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007D0[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007D0[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007D4[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007D4[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007D4[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007D4[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007D4[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF80007D4[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007D4[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007D4[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007D4[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U),
- // .. SDIO0_WP_SEL = 50
- // .. ==> 0XF8000830[5:0] = 0x00000032U
- // .. ==> MASK : 0x0000003FU VAL : 0x00000032U
- // .. SDIO0_CD_SEL = 46
- // .. ==> 0XF8000830[21:16] = 0x0000002EU
- // .. ==> MASK : 0x003F0000U VAL : 0x002E0000U
- // ..
- EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x002E0032U),
- // .. FINISH: MIO PROGRAMMING
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_peripherals_init_data_2_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
- // .. IBUF_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B48[7:7] = 0x00000001U
- // .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. TERM_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B48[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // ..
- EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
- // .. IBUF_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B4C[7:7] = 0x00000001U
- // .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. TERM_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B4C[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // ..
- EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
- // .. IBUF_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B50[7:7] = 0x00000001U
- // .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. TERM_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B50[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // ..
- EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
- // .. IBUF_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B54[7:7] = 0x00000001U
- // .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. TERM_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B54[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // ..
- EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
- // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // .. START: SRAM/NOR SET OPMODE
- // .. FINISH: SRAM/NOR SET OPMODE
- // .. START: UART REGISTERS
- // .. BDIV = 0x6
- // .. ==> 0XE0001034[7:0] = 0x00000006U
- // .. ==> MASK : 0x000000FFU VAL : 0x00000006U
- // ..
- EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
- // .. CD = 0x3e
- // .. ==> 0XE0001018[15:0] = 0x0000003EU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU
- // ..
- EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
- // .. STPBRK = 0x0
- // .. ==> 0XE0001000[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. STTBRK = 0x0
- // .. ==> 0XE0001000[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. RSTTO = 0x0
- // .. ==> 0XE0001000[6:6] = 0x00000000U
- // .. ==> MASK : 0x00000040U VAL : 0x00000000U
- // .. TXDIS = 0x0
- // .. ==> 0XE0001000[5:5] = 0x00000000U
- // .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. TXEN = 0x1
- // .. ==> 0XE0001000[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. RXDIS = 0x0
- // .. ==> 0XE0001000[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. RXEN = 0x1
- // .. ==> 0XE0001000[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. TXRES = 0x1
- // .. ==> 0XE0001000[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. RXRES = 0x1
- // .. ==> 0XE0001000[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // ..
- EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
- // .. IRMODE = 0x0
- // .. ==> 0XE0001004[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. UCLKEN = 0x0
- // .. ==> 0XE0001004[10:10] = 0x00000000U
- // .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. CHMODE = 0x0
- // .. ==> 0XE0001004[9:8] = 0x00000000U
- // .. ==> MASK : 0x00000300U VAL : 0x00000000U
- // .. NBSTOP = 0x0
- // .. ==> 0XE0001004[7:6] = 0x00000000U
- // .. ==> MASK : 0x000000C0U VAL : 0x00000000U
- // .. PAR = 0x4
- // .. ==> 0XE0001004[5:3] = 0x00000004U
- // .. ==> MASK : 0x00000038U VAL : 0x00000020U
- // .. CHRL = 0x0
- // .. ==> 0XE0001004[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. CLKS = 0x0
- // .. ==> 0XE0001004[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U),
- // .. FINISH: UART REGISTERS
- // .. START: QSPI REGISTERS
- // .. Holdb_dr = 1
- // .. ==> 0XE000D000[19:19] = 0x00000001U
- // .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // ..
- EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
- // .. FINISH: QSPI REGISTERS
- // .. START: PL POWER ON RESET REGISTERS
- // .. PCFG_POR_CNT_4K = 0
- // .. ==> 0XF8007000[29:29] = 0x00000000U
- // .. ==> MASK : 0x20000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
- // .. FINISH: PL POWER ON RESET REGISTERS
- // .. START: SMC TIMING CALCULATION REGISTER UPDATE
- // .. .. START: NAND SET CYCLE
- // .. .. FINISH: NAND SET CYCLE
- // .. .. START: OPMODE
- // .. .. FINISH: OPMODE
- // .. .. START: DIRECT COMMAND
- // .. .. FINISH: DIRECT COMMAND
- // .. .. START: SRAM/NOR CS0 SET CYCLE
- // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
- // .. .. START: DIRECT COMMAND
- // .. .. FINISH: DIRECT COMMAND
- // .. .. START: NOR CS0 BASE ADDRESS
- // .. .. FINISH: NOR CS0 BASE ADDRESS
- // .. .. START: SRAM/NOR CS1 SET CYCLE
- // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
- // .. .. START: DIRECT COMMAND
- // .. .. FINISH: DIRECT COMMAND
- // .. .. START: NOR CS1 BASE ADDRESS
- // .. .. FINISH: NOR CS1 BASE ADDRESS
- // .. .. START: USB RESET
- // .. .. .. START: USB0 RESET
- // .. .. .. .. START: DIR MODE BANK 0
- // .. .. .. .. DIRECTION_0 = 0x80
- // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U
- // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U),
- // .. .. .. .. FINISH: DIR MODE BANK 0
- // .. .. .. .. START: DIR MODE BANK 1
- // .. .. .. .. FINISH: DIR MODE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. MASK_0_LSW = 0xff7f
- // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
- // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U
- // .. .. .. .. DATA_0_LSW = 0x80
- // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
- // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. START: OUTPUT ENABLE BANK 0
- // .. .. .. .. OP_ENABLE_0 = 0x80
- // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U
- // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U),
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
- // .. .. .. .. START: OUTPUT ENABLE BANK 1
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. MASK_0_LSW = 0xff7f
- // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
- // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U
- // .. .. .. .. DATA_0_LSW = 0x0
- // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
- // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U),
- // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. START: ADD 1 MS DELAY
- // .. .. .. ..
- EMIT_MASKDELAY(0XF8F00200, 1),
- // .. .. .. .. FINISH: ADD 1 MS DELAY
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. MASK_0_LSW = 0xff7f
- // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
- // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U
- // .. .. .. .. DATA_0_LSW = 0x80
- // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
- // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: USB0 RESET
- // .. .. .. START: USB1 RESET
- // .. .. .. .. START: DIR MODE BANK 0
- // .. .. .. .. FINISH: DIR MODE BANK 0
- // .. .. .. .. START: DIR MODE BANK 1
- // .. .. .. .. FINISH: DIR MODE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. START: OUTPUT ENABLE BANK 0
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
- // .. .. .. .. START: OUTPUT ENABLE BANK 1
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. START: ADD 1 MS DELAY
- // .. .. .. ..
- EMIT_MASKDELAY(0XF8F00200, 1),
- // .. .. .. .. FINISH: ADD 1 MS DELAY
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: USB1 RESET
- // .. .. FINISH: USB RESET
- // .. .. START: ENET RESET
- // .. .. .. START: ENET0 RESET
- // .. .. .. .. START: DIR MODE BANK 0
- // .. .. .. .. FINISH: DIR MODE BANK 0
- // .. .. .. .. START: DIR MODE BANK 1
- // .. .. .. .. FINISH: DIR MODE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. START: OUTPUT ENABLE BANK 0
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
- // .. .. .. .. START: OUTPUT ENABLE BANK 1
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. START: ADD 1 MS DELAY
- // .. .. .. ..
- EMIT_MASKDELAY(0XF8F00200, 1),
- // .. .. .. .. FINISH: ADD 1 MS DELAY
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: ENET0 RESET
- // .. .. .. START: ENET1 RESET
- // .. .. .. .. START: DIR MODE BANK 0
- // .. .. .. .. FINISH: DIR MODE BANK 0
- // .. .. .. .. START: DIR MODE BANK 1
- // .. .. .. .. FINISH: DIR MODE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. START: OUTPUT ENABLE BANK 0
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
- // .. .. .. .. START: OUTPUT ENABLE BANK 1
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. START: ADD 1 MS DELAY
- // .. .. .. ..
- EMIT_MASKDELAY(0XF8F00200, 1),
- // .. .. .. .. FINISH: ADD 1 MS DELAY
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: ENET1 RESET
- // .. .. FINISH: ENET RESET
- // .. .. START: I2C RESET
- // .. .. .. START: I2C0 RESET
- // .. .. .. .. START: DIR MODE GPIO BANK0
- // .. .. .. .. FINISH: DIR MODE GPIO BANK0
- // .. .. .. .. START: DIR MODE GPIO BANK1
- // .. .. .. .. FINISH: DIR MODE GPIO BANK1
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. START: OUTPUT ENABLE
- // .. .. .. .. FINISH: OUTPUT ENABLE
- // .. .. .. .. START: OUTPUT ENABLE
- // .. .. .. .. FINISH: OUTPUT ENABLE
- // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. START: ADD 1 MS DELAY
- // .. .. .. ..
- EMIT_MASKDELAY(0XF8F00200, 1),
- // .. .. .. .. FINISH: ADD 1 MS DELAY
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: I2C0 RESET
- // .. .. .. START: I2C1 RESET
- // .. .. .. .. START: DIR MODE GPIO BANK0
- // .. .. .. .. FINISH: DIR MODE GPIO BANK0
- // .. .. .. .. START: DIR MODE GPIO BANK1
- // .. .. .. .. FINISH: DIR MODE GPIO BANK1
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. START: OUTPUT ENABLE
- // .. .. .. .. FINISH: OUTPUT ENABLE
- // .. .. .. .. START: OUTPUT ENABLE
- // .. .. .. .. FINISH: OUTPUT ENABLE
- // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. START: ADD 1 MS DELAY
- // .. .. .. ..
- EMIT_MASKDELAY(0XF8F00200, 1),
- // .. .. .. .. FINISH: ADD 1 MS DELAY
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: I2C1 RESET
- // .. .. FINISH: I2C RESET
- // .. .. START: NOR CHIP SELECT
- // .. .. .. START: DIR MODE BANK 0
- // .. .. .. FINISH: DIR MODE BANK 0
- // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. START: OUTPUT ENABLE BANK 0
- // .. .. .. FINISH: OUTPUT ENABLE BANK 0
- // .. .. FINISH: NOR CHIP SELECT
- // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_post_config_2_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: ENABLING LEVEL SHIFTER
- // .. USER_INP_ICT_EN_0 = 3
- // .. ==> 0XF8000900[1:0] = 0x00000003U
- // .. ==> MASK : 0x00000003U VAL : 0x00000003U
- // .. USER_INP_ICT_EN_1 = 3
- // .. ==> 0XF8000900[3:2] = 0x00000003U
- // .. ==> MASK : 0x0000000CU VAL : 0x0000000CU
- // ..
- EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
- // .. FINISH: ENABLING LEVEL SHIFTER
- // .. START: FPGA RESETS TO 0
- // .. reserved_3 = 0
- // .. ==> 0XF8000240[31:25] = 0x00000000U
- // .. ==> MASK : 0xFE000000U VAL : 0x00000000U
- // .. FPGA_ACP_RST = 0
- // .. ==> 0XF8000240[24:24] = 0x00000000U
- // .. ==> MASK : 0x01000000U VAL : 0x00000000U
- // .. FPGA_AXDS3_RST = 0
- // .. ==> 0XF8000240[23:23] = 0x00000000U
- // .. ==> MASK : 0x00800000U VAL : 0x00000000U
- // .. FPGA_AXDS2_RST = 0
- // .. ==> 0XF8000240[22:22] = 0x00000000U
- // .. ==> MASK : 0x00400000U VAL : 0x00000000U
- // .. FPGA_AXDS1_RST = 0
- // .. ==> 0XF8000240[21:21] = 0x00000000U
- // .. ==> MASK : 0x00200000U VAL : 0x00000000U
- // .. FPGA_AXDS0_RST = 0
- // .. ==> 0XF8000240[20:20] = 0x00000000U
- // .. ==> MASK : 0x00100000U VAL : 0x00000000U
- // .. reserved_2 = 0
- // .. ==> 0XF8000240[19:18] = 0x00000000U
- // .. ==> MASK : 0x000C0000U VAL : 0x00000000U
- // .. FSSW1_FPGA_RST = 0
- // .. ==> 0XF8000240[17:17] = 0x00000000U
- // .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. FSSW0_FPGA_RST = 0
- // .. ==> 0XF8000240[16:16] = 0x00000000U
- // .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. reserved_1 = 0
- // .. ==> 0XF8000240[15:14] = 0x00000000U
- // .. ==> MASK : 0x0000C000U VAL : 0x00000000U
- // .. FPGA_FMSW1_RST = 0
- // .. ==> 0XF8000240[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // .. FPGA_FMSW0_RST = 0
- // .. ==> 0XF8000240[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. FPGA_DMA3_RST = 0
- // .. ==> 0XF8000240[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. FPGA_DMA2_RST = 0
- // .. ==> 0XF8000240[10:10] = 0x00000000U
- // .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. FPGA_DMA1_RST = 0
- // .. ==> 0XF8000240[9:9] = 0x00000000U
- // .. ==> MASK : 0x00000200U VAL : 0x00000000U
- // .. FPGA_DMA0_RST = 0
- // .. ==> 0XF8000240[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. reserved = 0
- // .. ==> 0XF8000240[7:4] = 0x00000000U
- // .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. FPGA3_OUT_RST = 0
- // .. ==> 0XF8000240[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. FPGA2_OUT_RST = 0
- // .. ==> 0XF8000240[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. FPGA1_OUT_RST = 0
- // .. ==> 0XF8000240[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. FPGA0_OUT_RST = 0
- // .. ==> 0XF8000240[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
- // .. FINISH: FPGA RESETS TO 0
- // .. START: AFI REGISTERS
- // .. .. START: AFI0 REGISTERS
- // .. .. FINISH: AFI0 REGISTERS
- // .. .. START: AFI1 REGISTERS
- // .. .. FINISH: AFI1 REGISTERS
- // .. .. START: AFI2 REGISTERS
- // .. .. FINISH: AFI2 REGISTERS
- // .. .. START: AFI3 REGISTERS
- // .. .. FINISH: AFI3 REGISTERS
- // .. FINISH: AFI REGISTERS
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_debug_2_0[] = {
- // START: top
- // .. START: CROSS TRIGGER CONFIGURATIONS
- // .. .. START: UNLOCKING CTI REGISTERS
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. FINISH: UNLOCKING CTI REGISTERS
- // .. .. START: ENABLING CTI MODULES AND CHANNELS
- // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
- // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. FINISH: CROSS TRIGGER CONFIGURATIONS
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_pll_init_data_1_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: PLL SLCR REGISTERS
- // .. .. START: ARM PLL INIT
- // .. .. PLL_RES = 0x2
- // .. .. ==> 0XF8000110[7:4] = 0x00000002U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
- // .. .. PLL_CP = 0x2
- // .. .. ==> 0XF8000110[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. LOCK_CNT = 0xfa
- // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
- // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U
- // .. ..
- EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
- // .. .. .. START: UPDATE FB_DIV
- // .. .. .. PLL_FDIV = 0x28
- // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
- // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
- // .. .. .. FINISH: UPDATE FB_DIV
- // .. .. .. START: BY PASS PLL
- // .. .. .. PLL_BYPASS_FORCE = 1
- // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
- // .. .. .. FINISH: BY PASS PLL
- // .. .. .. START: ASSERT RESET
- // .. .. .. PLL_RESET = 1
- // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
- // .. .. .. FINISH: ASSERT RESET
- // .. .. .. START: DEASSERT RESET
- // .. .. .. PLL_RESET = 0
- // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
- // .. .. .. FINISH: DEASSERT RESET
- // .. .. .. START: CHECK PLL STATUS
- // .. .. .. ARM_PLL_LOCK = 1
- // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ..
- EMIT_MASKPOLL(0XF800010C, 0x00000001U),
- // .. .. .. FINISH: CHECK PLL STATUS
- // .. .. .. START: REMOVE PLL BY PASS
- // .. .. .. PLL_BYPASS_FORCE = 0
- // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
- // .. .. .. FINISH: REMOVE PLL BY PASS
- // .. .. .. SRCSEL = 0x0
- // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. .. .. DIVISOR = 0x2
- // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
- // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U
- // .. .. .. CPU_6OR4XCLKACT = 0x1
- // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
- // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U
- // .. .. .. CPU_3OR2XCLKACT = 0x1
- // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
- // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U
- // .. .. .. CPU_2XCLKACT = 0x1
- // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
- // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U
- // .. .. .. CPU_1XCLKACT = 0x1
- // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
- // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U
- // .. .. .. CPU_PERI_CLKACT = 0x1
- // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
- // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
- // .. .. FINISH: ARM PLL INIT
- // .. .. START: DDR PLL INIT
- // .. .. PLL_RES = 0x2
- // .. .. ==> 0XF8000114[7:4] = 0x00000002U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
- // .. .. PLL_CP = 0x2
- // .. .. ==> 0XF8000114[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. LOCK_CNT = 0x12c
- // .. .. ==> 0XF8000114[21:12] = 0x0000012CU
- // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U
- // .. ..
- EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
- // .. .. .. START: UPDATE FB_DIV
- // .. .. .. PLL_FDIV = 0x20
- // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
- // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
- // .. .. .. FINISH: UPDATE FB_DIV
- // .. .. .. START: BY PASS PLL
- // .. .. .. PLL_BYPASS_FORCE = 1
- // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
- // .. .. .. FINISH: BY PASS PLL
- // .. .. .. START: ASSERT RESET
- // .. .. .. PLL_RESET = 1
- // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
- // .. .. .. FINISH: ASSERT RESET
- // .. .. .. START: DEASSERT RESET
- // .. .. .. PLL_RESET = 0
- // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
- // .. .. .. FINISH: DEASSERT RESET
- // .. .. .. START: CHECK PLL STATUS
- // .. .. .. DDR_PLL_LOCK = 1
- // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. .. ..
- EMIT_MASKPOLL(0XF800010C, 0x00000002U),
- // .. .. .. FINISH: CHECK PLL STATUS
- // .. .. .. START: REMOVE PLL BY PASS
- // .. .. .. PLL_BYPASS_FORCE = 0
- // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
- // .. .. .. FINISH: REMOVE PLL BY PASS
- // .. .. .. DDR_3XCLKACT = 0x1
- // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. .. DDR_2XCLKACT = 0x1
- // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. .. .. DDR_3XCLK_DIVISOR = 0x2
- // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
- // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U
- // .. .. .. DDR_2XCLK_DIVISOR = 0x3
- // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
- // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
- // .. .. FINISH: DDR PLL INIT
- // .. .. START: IO PLL INIT
- // .. .. PLL_RES = 0xc
- // .. .. ==> 0XF8000118[7:4] = 0x0000000CU
- // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U
- // .. .. PLL_CP = 0x2
- // .. .. ==> 0XF8000118[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. LOCK_CNT = 0x145
- // .. .. ==> 0XF8000118[21:12] = 0x00000145U
- // .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U
- // .. ..
- EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U),
- // .. .. .. START: UPDATE FB_DIV
- // .. .. .. PLL_FDIV = 0x1e
- // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU
- // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U),
- // .. .. .. FINISH: UPDATE FB_DIV
- // .. .. .. START: BY PASS PLL
- // .. .. .. PLL_BYPASS_FORCE = 1
- // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
- // .. .. .. FINISH: BY PASS PLL
- // .. .. .. START: ASSERT RESET
- // .. .. .. PLL_RESET = 1
- // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
- // .. .. .. FINISH: ASSERT RESET
- // .. .. .. START: DEASSERT RESET
- // .. .. .. PLL_RESET = 0
- // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
- // .. .. .. FINISH: DEASSERT RESET
- // .. .. .. START: CHECK PLL STATUS
- // .. .. .. IO_PLL_LOCK = 1
- // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. .. ..
- EMIT_MASKPOLL(0XF800010C, 0x00000004U),
- // .. .. .. FINISH: CHECK PLL STATUS
- // .. .. .. START: REMOVE PLL BY PASS
- // .. .. .. PLL_BYPASS_FORCE = 0
- // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
- // .. .. .. FINISH: REMOVE PLL BY PASS
- // .. .. FINISH: IO PLL INIT
- // .. FINISH: PLL SLCR REGISTERS
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_clock_init_data_1_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: CLOCK CONTROL SLCR REGISTERS
- // .. CLKACT = 0x1
- // .. ==> 0XF8000128[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. DIVISOR0 = 0x23
- // .. ==> 0XF8000128[13:8] = 0x00000023U
- // .. ==> MASK : 0x00003F00U VAL : 0x00002300U
- // .. DIVISOR1 = 0x3
- // .. ==> 0XF8000128[25:20] = 0x00000003U
- // .. ==> MASK : 0x03F00000U VAL : 0x00300000U
- // ..
- EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U),
- // .. CLKACT = 0x1
- // .. ==> 0XF8000138[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000138[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
- // .. CLKACT = 0x1
- // .. ==> 0XF8000140[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000140[6:4] = 0x00000000U
- // .. ==> MASK : 0x00000070U VAL : 0x00000000U
- // .. DIVISOR = 0x8
- // .. ==> 0XF8000140[13:8] = 0x00000008U
- // .. ==> MASK : 0x00003F00U VAL : 0x00000800U
- // .. DIVISOR1 = 0x1
- // .. ==> 0XF8000140[25:20] = 0x00000001U
- // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
- // ..
- EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U),
- // .. CLKACT = 0x1
- // .. ==> 0XF800014C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. SRCSEL = 0x0
- // .. ==> 0XF800014C[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR = 0x5
- // .. ==> 0XF800014C[13:8] = 0x00000005U
- // .. ==> MASK : 0x00003F00U VAL : 0x00000500U
- // ..
- EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
- // .. CLKACT0 = 0x1
- // .. ==> 0XF8000150[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. CLKACT1 = 0x0
- // .. ==> 0XF8000150[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000150[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR = 0x14
- // .. ==> 0XF8000150[13:8] = 0x00000014U
- // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
- // ..
- EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U),
- // .. CLKACT0 = 0x0
- // .. ==> 0XF8000154[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. CLKACT1 = 0x1
- // .. ==> 0XF8000154[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000154[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR = 0x14
- // .. ==> 0XF8000154[13:8] = 0x00000014U
- // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
- // ..
- EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U),
- // .. CLKACT = 0x1
- // .. ==> 0XF8000168[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000168[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR = 0x5
- // .. ==> 0XF8000168[13:8] = 0x00000005U
- // .. ==> MASK : 0x00003F00U VAL : 0x00000500U
- // ..
- EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000170[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR0 = 0xa
- // .. ==> 0XF8000170[13:8] = 0x0000000AU
- // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U
- // .. DIVISOR1 = 0x1
- // .. ==> 0XF8000170[25:20] = 0x00000001U
- // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
- // ..
- EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00100A00U),
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000180[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR0 = 0xa
- // .. ==> 0XF8000180[13:8] = 0x0000000AU
- // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U
- // .. DIVISOR1 = 0x1
- // .. ==> 0XF8000180[25:20] = 0x00000001U
- // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
- // ..
- EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00100A00U),
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000190[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR0 = 0x1e
- // .. ==> 0XF8000190[13:8] = 0x0000001EU
- // .. ==> MASK : 0x00003F00U VAL : 0x00001E00U
- // .. DIVISOR1 = 0x1
- // .. ==> 0XF8000190[25:20] = 0x00000001U
- // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
- // ..
- EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101E00U),
- // .. SRCSEL = 0x0
- // .. ==> 0XF80001A0[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR0 = 0x14
- // .. ==> 0XF80001A0[13:8] = 0x00000014U
- // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
- // .. DIVISOR1 = 0x1
- // .. ==> 0XF80001A0[25:20] = 0x00000001U
- // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
- // ..
- EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U),
- // .. CLK_621_TRUE = 0x1
- // .. ==> 0XF80001C4[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // ..
- EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
- // .. DMA_CPU_2XCLKACT = 0x1
- // .. ==> 0XF800012C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. USB0_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. USB1_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[3:3] = 0x00000001U
- // .. ==> MASK : 0x00000008U VAL : 0x00000008U
- // .. GEM0_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[6:6] = 0x00000001U
- // .. ==> MASK : 0x00000040U VAL : 0x00000040U
- // .. GEM1_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. SDI0_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[10:10] = 0x00000001U
- // .. ==> MASK : 0x00000400U VAL : 0x00000400U
- // .. SDI1_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. SPI0_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[14:14] = 0x00000000U
- // .. ==> MASK : 0x00004000U VAL : 0x00000000U
- // .. SPI1_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[15:15] = 0x00000000U
- // .. ==> MASK : 0x00008000U VAL : 0x00000000U
- // .. CAN0_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[16:16] = 0x00000000U
- // .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. CAN1_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[17:17] = 0x00000000U
- // .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. I2C0_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[18:18] = 0x00000001U
- // .. ==> MASK : 0x00040000U VAL : 0x00040000U
- // .. I2C1_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[19:19] = 0x00000001U
- // .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // .. UART0_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[20:20] = 0x00000000U
- // .. ==> MASK : 0x00100000U VAL : 0x00000000U
- // .. UART1_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[21:21] = 0x00000001U
- // .. ==> MASK : 0x00200000U VAL : 0x00200000U
- // .. GPIO_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[22:22] = 0x00000001U
- // .. ==> MASK : 0x00400000U VAL : 0x00400000U
- // .. LQSPI_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[23:23] = 0x00000001U
- // .. ==> MASK : 0x00800000U VAL : 0x00800000U
- // .. SMC_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[24:24] = 0x00000001U
- // .. ==> MASK : 0x01000000U VAL : 0x01000000U
- // ..
- EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC044DU),
- // .. FINISH: CLOCK CONTROL SLCR REGISTERS
- // .. START: THIS SHOULD BE BLANK
- // .. FINISH: THIS SHOULD BE BLANK
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_ddr_init_data_1_0[] = {
- // START: top
- // .. START: DDR INITIALIZATION
- // .. .. START: LOCK DDR
- // .. .. reg_ddrc_soft_rstb = 0
- // .. .. ==> 0XF8006000[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_powerdown_en = 0x0
- // .. .. ==> 0XF8006000[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_ddrc_data_bus_width = 0x0
- // .. .. ==> 0XF8006000[3:2] = 0x00000000U
- // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U
- // .. .. reg_ddrc_burst8_refresh = 0x0
- // .. .. ==> 0XF8006000[6:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U
- // .. .. reg_ddrc_rdwr_idle_gap = 0x1
- // .. .. ==> 0XF8006000[13:7] = 0x00000001U
- // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U
- // .. .. reg_ddrc_dis_rd_bypass = 0x0
- // .. .. ==> 0XF8006000[14:14] = 0x00000000U
- // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_act_bypass = 0x0
- // .. .. ==> 0XF8006000[15:15] = 0x00000000U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_auto_refresh = 0x0
- // .. .. ==> 0XF8006000[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
- // .. .. FINISH: LOCK DDR
- // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81
- // .. .. ==> 0XF8006004[11:0] = 0x00000081U
- // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U
- // .. .. reg_ddrc_active_ranks = 0x1
- // .. .. ==> 0XF8006004[13:12] = 0x00000001U
- // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U
- // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
- // .. .. ==> 0XF8006004[18:14] = 0x00000000U
- // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U
- // .. .. reg_ddrc_wr_odt_block = 0x1
- // .. .. ==> 0XF8006004[20:19] = 0x00000001U
- // .. .. ==> MASK : 0x00180000U VAL : 0x00080000U
- // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0
- // .. .. ==> 0XF8006004[21:21] = 0x00000000U
- // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0
- // .. .. ==> 0XF8006004[26:22] = 0x00000000U
- // .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_open_bank = 0x0
- // .. .. ==> 0XF8006004[27:27] = 0x00000000U
- // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_4bank_ram = 0x0
- // .. .. ==> 0XF8006004[28:28] = 0x00000000U
- // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U),
- // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
- // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
- // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU
- // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
- // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
- // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U
- // .. .. reg_ddrc_hpr_xact_run_length = 0xf
- // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
- // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U
- // .. ..
- EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
- // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
- // .. .. ==> 0XF800600C[10:0] = 0x00000001U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U
- // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
- // .. .. ==> 0XF800600C[21:11] = 0x00000002U
- // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U
- // .. .. reg_ddrc_lpr_xact_run_length = 0x8
- // .. .. ==> 0XF800600C[25:22] = 0x00000008U
- // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U
- // .. ..
- EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
- // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
- // .. .. ==> 0XF8006010[10:0] = 0x00000001U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U
- // .. .. reg_ddrc_w_xact_run_length = 0x8
- // .. .. ==> 0XF8006010[14:11] = 0x00000008U
- // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U
- // .. .. reg_ddrc_w_max_starve_x32 = 0x2
- // .. .. ==> 0XF8006010[25:15] = 0x00000002U
- // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U
- // .. ..
- EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
- // .. .. reg_ddrc_t_rc = 0x1a
- // .. .. ==> 0XF8006014[5:0] = 0x0000001AU
- // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001AU
- // .. .. reg_ddrc_t_rfc_min = 0xa0
- // .. .. ==> 0XF8006014[13:6] = 0x000000A0U
- // .. .. ==> MASK : 0x00003FC0U VAL : 0x00002800U
- // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
- // .. .. ==> 0XF8006014[20:14] = 0x00000010U
- // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U
- // .. ..
- EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281AU),
- // .. .. reg_ddrc_wr2pre = 0x12
- // .. .. ==> 0XF8006018[4:0] = 0x00000012U
- // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U
- // .. .. reg_ddrc_powerdown_to_x32 = 0x6
- // .. .. ==> 0XF8006018[9:5] = 0x00000006U
- // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U
- // .. .. reg_ddrc_t_faw = 0x16
- // .. .. ==> 0XF8006018[15:10] = 0x00000016U
- // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005800U
- // .. .. reg_ddrc_t_ras_max = 0x24
- // .. .. ==> 0XF8006018[21:16] = 0x00000024U
- // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U
- // .. .. reg_ddrc_t_ras_min = 0x13
- // .. .. ==> 0XF8006018[26:22] = 0x00000013U
- // .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U
- // .. .. reg_ddrc_t_cke = 0x4
- // .. .. ==> 0XF8006018[31:28] = 0x00000004U
- // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D2U),
- // .. .. reg_ddrc_write_latency = 0x5
- // .. .. ==> 0XF800601C[4:0] = 0x00000005U
- // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U
- // .. .. reg_ddrc_rd2wr = 0x7
- // .. .. ==> 0XF800601C[9:5] = 0x00000007U
- // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U
- // .. .. reg_ddrc_wr2rd = 0xe
- // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
- // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U
- // .. .. reg_ddrc_t_xp = 0x4
- // .. .. ==> 0XF800601C[19:15] = 0x00000004U
- // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U
- // .. .. reg_ddrc_pad_pd = 0x0
- // .. .. ==> 0XF800601C[22:20] = 0x00000000U
- // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U
- // .. .. reg_ddrc_rd2pre = 0x4
- // .. .. ==> 0XF800601C[27:23] = 0x00000004U
- // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U
- // .. .. reg_ddrc_t_rcd = 0x7
- // .. .. ==> 0XF800601C[31:28] = 0x00000007U
- // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U
- // .. ..
- EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
- // .. .. reg_ddrc_t_ccd = 0x4
- // .. .. ==> 0XF8006020[4:2] = 0x00000004U
- // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U
- // .. .. reg_ddrc_t_rrd = 0x6
- // .. .. ==> 0XF8006020[7:5] = 0x00000006U
- // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U
- // .. .. reg_ddrc_refresh_margin = 0x2
- // .. .. ==> 0XF8006020[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. reg_ddrc_t_rp = 0x7
- // .. .. ==> 0XF8006020[15:12] = 0x00000007U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U
- // .. .. reg_ddrc_refresh_to_x32 = 0x8
- // .. .. ==> 0XF8006020[20:16] = 0x00000008U
- // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U
- // .. .. reg_ddrc_sdram = 0x1
- // .. .. ==> 0XF8006020[21:21] = 0x00000001U
- // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U
- // .. .. reg_ddrc_mobile = 0x0
- // .. .. ==> 0XF8006020[22:22] = 0x00000000U
- // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U
- // .. .. reg_ddrc_clock_stop_en = 0x0
- // .. .. ==> 0XF8006020[23:23] = 0x00000000U
- // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U
- // .. .. reg_ddrc_read_latency = 0x7
- // .. .. ==> 0XF8006020[28:24] = 0x00000007U
- // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U
- // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
- // .. .. ==> 0XF8006020[29:29] = 0x00000001U
- // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U
- // .. .. reg_ddrc_dis_pad_pd = 0x0
- // .. .. ==> 0XF8006020[30:30] = 0x00000000U
- // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U
- // .. .. reg_ddrc_loopback = 0x0
- // .. .. ==> 0XF8006020[31:31] = 0x00000000U
- // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U),
- // .. .. reg_ddrc_en_2t_timing_mode = 0x0
- // .. .. ==> 0XF8006024[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_prefer_write = 0x0
- // .. .. ==> 0XF8006024[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_ddrc_max_rank_rd = 0xf
- // .. .. ==> 0XF8006024[5:2] = 0x0000000FU
- // .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU
- // .. .. reg_ddrc_mr_wr = 0x0
- // .. .. ==> 0XF8006024[6:6] = 0x00000000U
- // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_addr = 0x0
- // .. .. ==> 0XF8006024[8:7] = 0x00000000U
- // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_data = 0x0
- // .. .. ==> 0XF8006024[24:9] = 0x00000000U
- // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U
- // .. .. ddrc_reg_mr_wr_busy = 0x0
- // .. .. ==> 0XF8006024[25:25] = 0x00000000U
- // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_type = 0x0
- // .. .. ==> 0XF8006024[26:26] = 0x00000000U
- // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_rdata_valid = 0x0
- // .. .. ==> 0XF8006024[27:27] = 0x00000000U
- // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU),
- // .. .. reg_ddrc_final_wait_x32 = 0x7
- // .. .. ==> 0XF8006028[6:0] = 0x00000007U
- // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U
- // .. .. reg_ddrc_pre_ocd_x32 = 0x0
- // .. .. ==> 0XF8006028[10:7] = 0x00000000U
- // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U
- // .. .. reg_ddrc_t_mrd = 0x4
- // .. .. ==> 0XF8006028[13:11] = 0x00000004U
- // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U
- // .. ..
- EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
- // .. .. reg_ddrc_emr2 = 0x8
- // .. .. ==> 0XF800602C[15:0] = 0x00000008U
- // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U
- // .. .. reg_ddrc_emr3 = 0x0
- // .. .. ==> 0XF800602C[31:16] = 0x00000000U
- // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
- // .. .. reg_ddrc_mr = 0x930
- // .. .. ==> 0XF8006030[15:0] = 0x00000930U
- // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U
- // .. .. reg_ddrc_emr = 0x4
- // .. .. ==> 0XF8006030[31:16] = 0x00000004U
- // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U
- // .. ..
- EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
- // .. .. reg_ddrc_burst_rdwr = 0x4
- // .. .. ==> 0XF8006034[3:0] = 0x00000004U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U
- // .. .. reg_ddrc_pre_cke_x1024 = 0x105
- // .. .. ==> 0XF8006034[13:4] = 0x00000105U
- // .. .. ==> MASK : 0x00003FF0U VAL : 0x00001050U
- // .. .. reg_ddrc_post_cke_x1024 = 0x1
- // .. .. ==> 0XF8006034[25:16] = 0x00000001U
- // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U
- // .. .. reg_ddrc_burstchop = 0x0
- // .. .. ==> 0XF8006034[28:28] = 0x00000000U
- // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U),
- // .. .. reg_ddrc_force_low_pri_n = 0x0
- // .. .. ==> 0XF8006038[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_dq = 0x0
- // .. .. ==> 0XF8006038[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_debug_mode = 0x0
- // .. .. ==> 0XF8006038[6:6] = 0x00000000U
- // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U
- // .. .. reg_phy_wr_level_start = 0x0
- // .. .. ==> 0XF8006038[7:7] = 0x00000000U
- // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. .. reg_phy_rd_level_start = 0x0
- // .. .. ==> 0XF8006038[8:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. .. reg_phy_dq0_wait_t = 0x0
- // .. .. ==> 0XF8006038[12:9] = 0x00000000U
- // .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U),
- // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
- // .. .. ==> 0XF800603C[3:0] = 0x00000007U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U
- // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
- // .. .. ==> 0XF800603C[7:4] = 0x00000007U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U
- // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
- // .. .. ==> 0XF800603C[11:8] = 0x00000007U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U
- // .. .. reg_ddrc_addrmap_col_b5 = 0x0
- // .. .. ==> 0XF800603C[15:12] = 0x00000000U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b6 = 0x0
- // .. .. ==> 0XF800603C[19:16] = 0x00000000U
- // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
- // .. .. reg_ddrc_addrmap_col_b2 = 0x0
- // .. .. ==> 0XF8006040[3:0] = 0x00000000U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b3 = 0x0
- // .. .. ==> 0XF8006040[7:4] = 0x00000000U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b4 = 0x0
- // .. .. ==> 0XF8006040[11:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b7 = 0x0
- // .. .. ==> 0XF8006040[15:12] = 0x00000000U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b8 = 0x0
- // .. .. ==> 0XF8006040[19:16] = 0x00000000U
- // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b9 = 0xf
- // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
- // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U
- // .. .. reg_ddrc_addrmap_col_b10 = 0xf
- // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
- // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U
- // .. .. reg_ddrc_addrmap_col_b11 = 0xf
- // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
- // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
- // .. .. reg_ddrc_addrmap_row_b0 = 0x6
- // .. .. ==> 0XF8006044[3:0] = 0x00000006U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U
- // .. .. reg_ddrc_addrmap_row_b1 = 0x6
- // .. .. ==> 0XF8006044[7:4] = 0x00000006U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U
- // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
- // .. .. ==> 0XF8006044[11:8] = 0x00000006U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U
- // .. .. reg_ddrc_addrmap_row_b12 = 0x6
- // .. .. ==> 0XF8006044[15:12] = 0x00000006U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U
- // .. .. reg_ddrc_addrmap_row_b13 = 0x6
- // .. .. ==> 0XF8006044[19:16] = 0x00000006U
- // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U
- // .. .. reg_ddrc_addrmap_row_b14 = 0x6
- // .. .. ==> 0XF8006044[23:20] = 0x00000006U
- // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U
- // .. .. reg_ddrc_addrmap_row_b15 = 0xf
- // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
- // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U),
- // .. .. reg_ddrc_rank0_rd_odt = 0x0
- // .. .. ==> 0XF8006048[2:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U
- // .. .. reg_ddrc_rank0_wr_odt = 0x1
- // .. .. ==> 0XF8006048[5:3] = 0x00000001U
- // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U
- // .. .. reg_ddrc_rank1_rd_odt = 0x1
- // .. .. ==> 0XF8006048[8:6] = 0x00000001U
- // .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U
- // .. .. reg_ddrc_rank1_wr_odt = 0x1
- // .. .. ==> 0XF8006048[11:9] = 0x00000001U
- // .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. .. reg_phy_rd_local_odt = 0x0
- // .. .. ==> 0XF8006048[13:12] = 0x00000000U
- // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U
- // .. .. reg_phy_wr_local_odt = 0x3
- // .. .. ==> 0XF8006048[15:14] = 0x00000003U
- // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U
- // .. .. reg_phy_idle_local_odt = 0x3
- // .. .. ==> 0XF8006048[17:16] = 0x00000003U
- // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U
- // .. .. reg_ddrc_rank2_rd_odt = 0x0
- // .. .. ==> 0XF8006048[20:18] = 0x00000000U
- // .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U
- // .. .. reg_ddrc_rank2_wr_odt = 0x0
- // .. .. ==> 0XF8006048[23:21] = 0x00000000U
- // .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U
- // .. .. reg_ddrc_rank3_rd_odt = 0x0
- // .. .. ==> 0XF8006048[26:24] = 0x00000000U
- // .. .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. .. reg_ddrc_rank3_wr_odt = 0x0
- // .. .. ==> 0XF8006048[29:27] = 0x00000000U
- // .. .. ==> MASK : 0x38000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U),
- // .. .. reg_phy_rd_cmd_to_data = 0x0
- // .. .. ==> 0XF8006050[3:0] = 0x00000000U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
- // .. .. reg_phy_wr_cmd_to_data = 0x0
- // .. .. ==> 0XF8006050[7:4] = 0x00000000U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. .. reg_phy_rdc_we_to_re_delay = 0x8
- // .. .. ==> 0XF8006050[11:8] = 0x00000008U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U
- // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
- // .. .. ==> 0XF8006050[15:15] = 0x00000000U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
- // .. .. reg_phy_use_fixed_re = 0x1
- // .. .. ==> 0XF8006050[16:16] = 0x00000001U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U
- // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
- // .. .. ==> 0XF8006050[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
- // .. .. ==> 0XF8006050[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_phy_clk_stall_level = 0x0
- // .. .. ==> 0XF8006050[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
- // .. .. ==> 0XF8006050[27:24] = 0x00000007U
- // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U
- // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
- // .. .. ==> 0XF8006050[31:28] = 0x00000007U
- // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
- // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1
- // .. .. ==> 0XF8006058[7:0] = 0x00000001U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U
- // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1
- // .. .. ==> 0XF8006058[15:8] = 0x00000001U
- // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U
- // .. .. reg_ddrc_dis_dll_calib = 0x0
- // .. .. ==> 0XF8006058[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U),
- // .. .. reg_ddrc_rd_odt_delay = 0x3
- // .. .. ==> 0XF800605C[3:0] = 0x00000003U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U
- // .. .. reg_ddrc_wr_odt_delay = 0x0
- // .. .. ==> 0XF800605C[7:4] = 0x00000000U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. .. reg_ddrc_rd_odt_hold = 0x0
- // .. .. ==> 0XF800605C[11:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U
- // .. .. reg_ddrc_wr_odt_hold = 0x5
- // .. .. ==> 0XF800605C[15:12] = 0x00000005U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U
- // .. ..
- EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
- // .. .. reg_ddrc_pageclose = 0x0
- // .. .. ==> 0XF8006060[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_lpr_num_entries = 0x1f
- // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
- // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU
- // .. .. reg_ddrc_auto_pre_en = 0x0
- // .. .. ==> 0XF8006060[7:7] = 0x00000000U
- // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. .. reg_ddrc_refresh_update_level = 0x0
- // .. .. ==> 0XF8006060[8:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_wc = 0x0
- // .. .. ==> 0XF8006060[9:9] = 0x00000000U
- // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_collision_page_opt = 0x0
- // .. .. ==> 0XF8006060[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_ddrc_selfref_en = 0x0
- // .. .. ==> 0XF8006060[12:12] = 0x00000000U
- // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
- // .. .. reg_ddrc_go2critical_hysteresis = 0x0
- // .. .. ==> 0XF8006064[12:5] = 0x00000000U
- // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U
- // .. .. reg_arb_go2critical_en = 0x1
- // .. .. ==> 0XF8006064[17:17] = 0x00000001U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U
- // .. ..
- EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
- // .. .. reg_ddrc_wrlvl_ww = 0x41
- // .. .. ==> 0XF8006068[7:0] = 0x00000041U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U
- // .. .. reg_ddrc_rdlvl_rr = 0x41
- // .. .. ==> 0XF8006068[15:8] = 0x00000041U
- // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U
- // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
- // .. .. ==> 0XF8006068[25:16] = 0x00000028U
- // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U
- // .. ..
- EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
- // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
- // .. .. ==> 0XF800606C[7:0] = 0x00000010U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U
- // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
- // .. .. ==> 0XF800606C[15:8] = 0x00000016U
- // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U
- // .. ..
- EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
- // .. .. refresh_timer0_start_value_x32 = 0x0
- // .. .. ==> 0XF80060A0[11:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U
- // .. .. refresh_timer1_start_value_x32 = 0x8
- // .. .. ==> 0XF80060A0[23:12] = 0x00000008U
- // .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U
- // .. ..
- EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U),
- // .. .. reg_ddrc_dis_auto_zq = 0x0
- // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_ddr3 = 0x1
- // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. .. reg_ddrc_t_mod = 0x200
- // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
- // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U
- // .. .. reg_ddrc_t_zq_long_nop = 0x200
- // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
- // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U
- // .. .. reg_ddrc_t_zq_short_nop = 0x40
- // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
- // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
- // .. .. t_zq_short_interval_x1024 = 0xcb73
- // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U
- // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U
- // .. .. dram_rstn_x1024 = 0x69
- // .. .. ==> 0XF80060A8[27:20] = 0x00000069U
- // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U
- // .. ..
- EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
- // .. .. deeppowerdown_en = 0x0
- // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. deeppowerdown_to_x1024 = 0xff
- // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
- // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU
- // .. ..
- EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
- // .. .. dfi_wrlvl_max_x1024 = 0xfff
- // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
- // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU
- // .. .. dfi_rdlvl_max_x1024 = 0xfff
- // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
- // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U
- // .. .. ddrc_reg_twrlvl_max_error = 0x0
- // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
- // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U
- // .. .. ddrc_reg_trdlvl_max_error = 0x0
- // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
- // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
- // .. .. reg_ddrc_dfi_wr_level_en = 0x1
- // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
- // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U
- // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
- // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
- // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U
- // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
- // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
- // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
- // .. .. reg_ddrc_2t_delay = 0x0
- // .. .. ==> 0XF80060B4[8:0] = 0x00000000U
- // .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U
- // .. .. reg_ddrc_skip_ocd = 0x1
- // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
- // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U
- // .. .. reg_ddrc_dis_pre_bypass = 0x0
- // .. .. ==> 0XF80060B4[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U),
- // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
- // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
- // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U
- // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
- // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
- // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U
- // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
- // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
- // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U
- // .. ..
- EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
- // .. .. START: RESET ECC ERROR
- // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1
- // .. .. ==> 0XF80060C4[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. Clear_Correctable_DRAM_ECC_error = 1
- // .. .. ==> 0XF80060C4[1:1] = 0x00000001U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. ..
- EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U),
- // .. .. FINISH: RESET ECC ERROR
- // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
- // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
- // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
- // .. .. CORR_ECC_LOG_VALID = 0x0
- // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. ECC_CORRECTED_BIT_NUM = 0x0
- // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
- // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
- // .. .. UNCORR_ECC_LOG_VALID = 0x0
- // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
- // .. .. STAT_NUM_CORR_ERR = 0x0
- // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
- // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U
- // .. .. STAT_NUM_UNCORR_ERR = 0x0
- // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
- // .. .. reg_ddrc_ecc_mode = 0x0
- // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_scrub = 0x1
- // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U
- // .. ..
- EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
- // .. .. reg_phy_dif_on = 0x0
- // .. .. ==> 0XF8006114[3:0] = 0x00000000U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
- // .. .. reg_phy_dif_off = 0x0
- // .. .. ==> 0XF8006114[7:4] = 0x00000000U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
- // .. .. reg_phy_data_slice_in_use = 0x1
- // .. .. ==> 0XF8006118[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_phy_rdlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006118[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_inc_mode = 0x0
- // .. .. ==> 0XF8006118[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_wrlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006118[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_tx = 0x0
- // .. .. ==> 0XF8006118[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_rx = 0x0
- // .. .. ==> 0XF8006118[5:5] = 0x00000000U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. .. reg_phy_bist_shift_dq = 0x0
- // .. .. ==> 0XF8006118[14:6] = 0x00000000U
- // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. .. reg_phy_bist_err_clr = 0x0
- // .. .. ==> 0XF8006118[23:15] = 0x00000000U
- // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. .. reg_phy_dq_offset = 0x40
- // .. .. ==> 0XF8006118[30:24] = 0x00000040U
- // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U),
- // .. .. reg_phy_data_slice_in_use = 0x1
- // .. .. ==> 0XF800611C[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_phy_rdlvl_inc_mode = 0x0
- // .. .. ==> 0XF800611C[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_inc_mode = 0x0
- // .. .. ==> 0XF800611C[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_wrlvl_inc_mode = 0x0
- // .. .. ==> 0XF800611C[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_tx = 0x0
- // .. .. ==> 0XF800611C[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_rx = 0x0
- // .. .. ==> 0XF800611C[5:5] = 0x00000000U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. .. reg_phy_bist_shift_dq = 0x0
- // .. .. ==> 0XF800611C[14:6] = 0x00000000U
- // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. .. reg_phy_bist_err_clr = 0x0
- // .. .. ==> 0XF800611C[23:15] = 0x00000000U
- // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. .. reg_phy_dq_offset = 0x40
- // .. .. ==> 0XF800611C[30:24] = 0x00000040U
- // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U),
- // .. .. reg_phy_data_slice_in_use = 0x1
- // .. .. ==> 0XF8006120[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_phy_rdlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006120[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_inc_mode = 0x0
- // .. .. ==> 0XF8006120[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_wrlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006120[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_tx = 0x0
- // .. .. ==> 0XF8006120[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_rx = 0x0
- // .. .. ==> 0XF8006120[5:5] = 0x00000000U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. .. reg_phy_bist_shift_dq = 0x0
- // .. .. ==> 0XF8006120[14:6] = 0x00000000U
- // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. .. reg_phy_bist_err_clr = 0x0
- // .. .. ==> 0XF8006120[23:15] = 0x00000000U
- // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. .. reg_phy_dq_offset = 0x40
- // .. .. ==> 0XF8006120[30:24] = 0x00000040U
- // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U),
- // .. .. reg_phy_data_slice_in_use = 0x1
- // .. .. ==> 0XF8006124[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_phy_rdlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006124[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_inc_mode = 0x0
- // .. .. ==> 0XF8006124[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_wrlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006124[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_tx = 0x0
- // .. .. ==> 0XF8006124[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_rx = 0x0
- // .. .. ==> 0XF8006124[5:5] = 0x00000000U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. .. reg_phy_bist_shift_dq = 0x0
- // .. .. ==> 0XF8006124[14:6] = 0x00000000U
- // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. .. reg_phy_bist_err_clr = 0x0
- // .. .. ==> 0XF8006124[23:15] = 0x00000000U
- // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. .. reg_phy_dq_offset = 0x40
- // .. .. ==> 0XF8006124[30:24] = 0x00000040U
- // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U),
- // .. .. reg_phy_wrlvl_init_ratio = 0x0
- // .. .. ==> 0XF800612C[9:0] = 0x00000000U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_init_ratio = 0xb0
- // .. .. ==> 0XF800612C[19:10] = 0x000000B0U
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002C000U
- // .. ..
- EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0002C000U),
- // .. .. reg_phy_wrlvl_init_ratio = 0x0
- // .. .. ==> 0XF8006130[9:0] = 0x00000000U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_init_ratio = 0xb1
- // .. .. ==> 0XF8006130[19:10] = 0x000000B1U
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002C400U
- // .. ..
- EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x0002C400U),
- // .. .. reg_phy_wrlvl_init_ratio = 0x3
- // .. .. ==> 0XF8006134[9:0] = 0x00000003U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000003U
- // .. .. reg_phy_gatelvl_init_ratio = 0xbc
- // .. .. ==> 0XF8006134[19:10] = 0x000000BCU
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002F000U
- // .. ..
- EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0002F003U),
- // .. .. reg_phy_wrlvl_init_ratio = 0x3
- // .. .. ==> 0XF8006138[9:0] = 0x00000003U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000003U
- // .. .. reg_phy_gatelvl_init_ratio = 0xbb
- // .. .. ==> 0XF8006138[19:10] = 0x000000BBU
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002EC00U
- // .. ..
- EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0002EC03U),
- // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. .. ==> 0XF8006140[9:0] = 0x00000035U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. .. reg_phy_rd_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006140[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006140[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
- // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. .. ==> 0XF8006144[9:0] = 0x00000035U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. .. reg_phy_rd_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006144[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006144[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
- // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. .. ==> 0XF8006148[9:0] = 0x00000035U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. .. reg_phy_rd_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006148[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006148[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
- // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. .. ==> 0XF800614C[9:0] = 0x00000035U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. .. reg_phy_rd_dqs_slave_force = 0x0
- // .. .. ==> 0XF800614C[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. .. ==> 0XF800614C[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
- // .. .. reg_phy_wr_dqs_slave_ratio = 0x77
- // .. .. ==> 0XF8006154[9:0] = 0x00000077U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000077U
- // .. .. reg_phy_wr_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006154[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006154[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000077U),
- // .. .. reg_phy_wr_dqs_slave_ratio = 0x77
- // .. .. ==> 0XF8006158[9:0] = 0x00000077U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000077U
- // .. .. reg_phy_wr_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006158[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006158[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000077U),
- // .. .. reg_phy_wr_dqs_slave_ratio = 0x83
- // .. .. ==> 0XF800615C[9:0] = 0x00000083U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000083U
- // .. .. reg_phy_wr_dqs_slave_force = 0x0
- // .. .. ==> 0XF800615C[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. .. ==> 0XF800615C[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000083U),
- // .. .. reg_phy_wr_dqs_slave_ratio = 0x83
- // .. .. ==> 0XF8006160[9:0] = 0x00000083U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000083U
- // .. .. reg_phy_wr_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006160[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006160[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000083U),
- // .. .. reg_phy_fifo_we_slave_ratio = 0x105
- // .. .. ==> 0XF8006168[10:0] = 0x00000105U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x00000105U
- // .. .. reg_phy_fifo_we_in_force = 0x0
- // .. .. ==> 0XF8006168[11:11] = 0x00000000U
- // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. .. reg_phy_fifo_we_in_delay = 0x0
- // .. .. ==> 0XF8006168[20:12] = 0x00000000U
- // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000105U),
- // .. .. reg_phy_fifo_we_slave_ratio = 0x106
- // .. .. ==> 0XF800616C[10:0] = 0x00000106U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x00000106U
- // .. .. reg_phy_fifo_we_in_force = 0x0
- // .. .. ==> 0XF800616C[11:11] = 0x00000000U
- // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. .. reg_phy_fifo_we_in_delay = 0x0
- // .. .. ==> 0XF800616C[20:12] = 0x00000000U
- // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x00000106U),
- // .. .. reg_phy_fifo_we_slave_ratio = 0x111
- // .. .. ==> 0XF8006170[10:0] = 0x00000111U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x00000111U
- // .. .. reg_phy_fifo_we_in_force = 0x0
- // .. .. ==> 0XF8006170[11:11] = 0x00000000U
- // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. .. reg_phy_fifo_we_in_delay = 0x0
- // .. .. ==> 0XF8006170[20:12] = 0x00000000U
- // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000111U),
- // .. .. reg_phy_fifo_we_slave_ratio = 0x110
- // .. .. ==> 0XF8006174[10:0] = 0x00000110U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x00000110U
- // .. .. reg_phy_fifo_we_in_force = 0x0
- // .. .. ==> 0XF8006174[11:11] = 0x00000000U
- // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. .. reg_phy_fifo_we_in_delay = 0x0
- // .. .. ==> 0XF8006174[20:12] = 0x00000000U
- // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000110U),
- // .. .. reg_phy_wr_data_slave_ratio = 0xb7
- // .. .. ==> 0XF800617C[9:0] = 0x000000B7U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000000B7U
- // .. .. reg_phy_wr_data_slave_force = 0x0
- // .. .. ==> 0XF800617C[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_data_slave_delay = 0x0
- // .. .. ==> 0XF800617C[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000B7U),
- // .. .. reg_phy_wr_data_slave_ratio = 0xb7
- // .. .. ==> 0XF8006180[9:0] = 0x000000B7U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000000B7U
- // .. .. reg_phy_wr_data_slave_force = 0x0
- // .. .. ==> 0XF8006180[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_data_slave_delay = 0x0
- // .. .. ==> 0XF8006180[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000B7U),
- // .. .. reg_phy_wr_data_slave_ratio = 0xc3
- // .. .. ==> 0XF8006184[9:0] = 0x000000C3U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C3U
- // .. .. reg_phy_wr_data_slave_force = 0x0
- // .. .. ==> 0XF8006184[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_data_slave_delay = 0x0
- // .. .. ==> 0XF8006184[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C3U),
- // .. .. reg_phy_wr_data_slave_ratio = 0xc3
- // .. .. ==> 0XF8006188[9:0] = 0x000000C3U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C3U
- // .. .. reg_phy_wr_data_slave_force = 0x0
- // .. .. ==> 0XF8006188[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_data_slave_delay = 0x0
- // .. .. ==> 0XF8006188[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C3U),
- // .. .. reg_phy_loopback = 0x0
- // .. .. ==> 0XF8006190[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_phy_bl2 = 0x0
- // .. .. ==> 0XF8006190[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_at_spd_atpg = 0x0
- // .. .. ==> 0XF8006190[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_bist_enable = 0x0
- // .. .. ==> 0XF8006190[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_bist_force_err = 0x0
- // .. .. ==> 0XF8006190[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. reg_phy_bist_mode = 0x0
- // .. .. ==> 0XF8006190[6:5] = 0x00000000U
- // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. .. reg_phy_invert_clkout = 0x1
- // .. .. ==> 0XF8006190[7:7] = 0x00000001U
- // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0
- // .. .. ==> 0XF8006190[8:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. .. reg_phy_sel_logic = 0x0
- // .. .. ==> 0XF8006190[9:9] = 0x00000000U
- // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U
- // .. .. reg_phy_ctrl_slave_ratio = 0x100
- // .. .. ==> 0XF8006190[19:10] = 0x00000100U
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U
- // .. .. reg_phy_ctrl_slave_force = 0x0
- // .. .. ==> 0XF8006190[20:20] = 0x00000000U
- // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U
- // .. .. reg_phy_ctrl_slave_delay = 0x0
- // .. .. ==> 0XF8006190[27:21] = 0x00000000U
- // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U
- // .. .. reg_phy_use_rank0_delays = 0x1
- // .. .. ==> 0XF8006190[28:28] = 0x00000001U
- // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
- // .. .. reg_phy_lpddr = 0x0
- // .. .. ==> 0XF8006190[29:29] = 0x00000000U
- // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U
- // .. .. reg_phy_cmd_latency = 0x0
- // .. .. ==> 0XF8006190[30:30] = 0x00000000U
- // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U
- // .. .. reg_phy_int_lpbk = 0x0
- // .. .. ==> 0XF8006190[31:31] = 0x00000000U
- // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U),
- // .. .. reg_phy_wr_rl_delay = 0x2
- // .. .. ==> 0XF8006194[4:0] = 0x00000002U
- // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U
- // .. .. reg_phy_rd_rl_delay = 0x4
- // .. .. ==> 0XF8006194[9:5] = 0x00000004U
- // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U
- // .. .. reg_phy_dll_lock_diff = 0xf
- // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
- // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U
- // .. .. reg_phy_use_wr_level = 0x1
- // .. .. ==> 0XF8006194[14:14] = 0x00000001U
- // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U
- // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
- // .. .. ==> 0XF8006194[15:15] = 0x00000001U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U
- // .. .. reg_phy_use_rd_data_eye_level = 0x1
- // .. .. ==> 0XF8006194[16:16] = 0x00000001U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U
- // .. .. reg_phy_dis_calib_rst = 0x0
- // .. .. ==> 0XF8006194[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_phy_ctrl_slave_delay = 0x0
- // .. .. ==> 0XF8006194[19:18] = 0x00000000U
- // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
- // .. .. reg_arb_page_addr_mask = 0x0
- // .. .. ==> 0XF8006204[31:0] = 0x00000000U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
- // .. .. reg_arb_pri_wr_portn = 0x3ff
- // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_wr_portn = 0x0
- // .. .. ==> 0XF8006208[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. .. ==> 0XF8006208[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. .. ==> 0XF8006208[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_dis_rmw_portn = 0x1
- // .. .. ==> 0XF8006208[19:19] = 0x00000001U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // .. ..
- EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU),
- // .. .. reg_arb_pri_wr_portn = 0x3ff
- // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_wr_portn = 0x0
- // .. .. ==> 0XF800620C[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. .. ==> 0XF800620C[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. .. ==> 0XF800620C[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_dis_rmw_portn = 0x1
- // .. .. ==> 0XF800620C[19:19] = 0x00000001U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // .. ..
- EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU),
- // .. .. reg_arb_pri_wr_portn = 0x3ff
- // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_wr_portn = 0x0
- // .. .. ==> 0XF8006210[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. .. ==> 0XF8006210[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. .. ==> 0XF8006210[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_dis_rmw_portn = 0x1
- // .. .. ==> 0XF8006210[19:19] = 0x00000001U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // .. ..
- EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU),
- // .. .. reg_arb_pri_wr_portn = 0x3ff
- // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_wr_portn = 0x0
- // .. .. ==> 0XF8006214[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. .. ==> 0XF8006214[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. .. ==> 0XF8006214[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_dis_rmw_portn = 0x1
- // .. .. ==> 0XF8006214[19:19] = 0x00000001U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // .. ..
- EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU),
- // .. .. reg_arb_pri_rd_portn = 0x3ff
- // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_rd_portn = 0x0
- // .. .. ==> 0XF8006218[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. .. ==> 0XF8006218[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. .. ==> 0XF8006218[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_set_hpr_rd_portn = 0x0
- // .. .. ==> 0XF8006218[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
- // .. .. reg_arb_pri_rd_portn = 0x3ff
- // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_rd_portn = 0x0
- // .. .. ==> 0XF800621C[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. .. ==> 0XF800621C[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. .. ==> 0XF800621C[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_set_hpr_rd_portn = 0x0
- // .. .. ==> 0XF800621C[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
- // .. .. reg_arb_pri_rd_portn = 0x3ff
- // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_rd_portn = 0x0
- // .. .. ==> 0XF8006220[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. .. ==> 0XF8006220[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. .. ==> 0XF8006220[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_set_hpr_rd_portn = 0x0
- // .. .. ==> 0XF8006220[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
- // .. .. reg_arb_pri_rd_portn = 0x3ff
- // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_rd_portn = 0x0
- // .. .. ==> 0XF8006224[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. .. ==> 0XF8006224[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. .. ==> 0XF8006224[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_set_hpr_rd_portn = 0x0
- // .. .. ==> 0XF8006224[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
- // .. .. reg_ddrc_lpddr2 = 0x0
- // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_per_bank_refresh = 0x0
- // .. .. ==> 0XF80062A8[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_ddrc_derate_enable = 0x0
- // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_ddrc_mr4_margin = 0x0
- // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U),
- // .. .. reg_ddrc_mr4_read_interval = 0x0
- // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
- // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
- // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U
- // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
- // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
- // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U
- // .. .. reg_ddrc_t_mrw = 0x5
- // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
- // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U
- // .. ..
- EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
- // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8
- // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U
- // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
- // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
- // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U
- // .. ..
- EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
- // .. .. START: POLL ON DCI STATUS
- // .. .. DONE = 1
- // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
- // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // .. ..
- EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
- // .. .. FINISH: POLL ON DCI STATUS
- // .. .. START: UNLOCK DDR
- // .. .. reg_ddrc_soft_rstb = 0x1
- // .. .. ==> 0XF8006000[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_ddrc_powerdown_en = 0x0
- // .. .. ==> 0XF8006000[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_ddrc_data_bus_width = 0x0
- // .. .. ==> 0XF8006000[3:2] = 0x00000000U
- // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U
- // .. .. reg_ddrc_burst8_refresh = 0x0
- // .. .. ==> 0XF8006000[6:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U
- // .. .. reg_ddrc_rdwr_idle_gap = 1
- // .. .. ==> 0XF8006000[13:7] = 0x00000001U
- // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U
- // .. .. reg_ddrc_dis_rd_bypass = 0x0
- // .. .. ==> 0XF8006000[14:14] = 0x00000000U
- // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_act_bypass = 0x0
- // .. .. ==> 0XF8006000[15:15] = 0x00000000U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_auto_refresh = 0x0
- // .. .. ==> 0XF8006000[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
- // .. .. FINISH: UNLOCK DDR
- // .. .. START: CHECK DDR STATUS
- // .. .. ddrc_reg_operating_mode = 1
- // .. .. ==> 0XF8006054[2:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U
- // .. ..
- EMIT_MASKPOLL(0XF8006054, 0x00000007U),
- // .. .. FINISH: CHECK DDR STATUS
- // .. FINISH: DDR INITIALIZATION
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_mio_init_data_1_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: OCM REMAPPING
- // .. FINISH: OCM REMAPPING
- // .. START: DDRIOB SETTINGS
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B40[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x0
- // .. ==> 0XF8000B40[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B40[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x0
- // .. ==> 0XF8000B40[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. DCR_TYPE = 0x0
- // .. ==> 0XF8000B40[6:5] = 0x00000000U
- // .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. IBUF_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B40[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B40[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B40[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B40[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B44[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x0
- // .. ==> 0XF8000B44[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B44[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x0
- // .. ==> 0XF8000B44[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. DCR_TYPE = 0x0
- // .. ==> 0XF8000B44[6:5] = 0x00000000U
- // .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. IBUF_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B44[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B44[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B44[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B44[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B48[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x1
- // .. ==> 0XF8000B48[2:1] = 0x00000001U
- // .. ==> MASK : 0x00000006U VAL : 0x00000002U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B48[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x1
- // .. ==> 0XF8000B48[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. DCR_TYPE = 0x3
- // .. ==> 0XF8000B48[6:5] = 0x00000003U
- // .. ==> MASK : 0x00000060U VAL : 0x00000060U
- // .. IBUF_DISABLE_MODE = 0
- // .. ==> 0XF8000B48[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0
- // .. ==> 0XF8000B48[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B48[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B48[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B4C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x1
- // .. ==> 0XF8000B4C[2:1] = 0x00000001U
- // .. ==> MASK : 0x00000006U VAL : 0x00000002U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B4C[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x1
- // .. ==> 0XF8000B4C[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. DCR_TYPE = 0x3
- // .. ==> 0XF8000B4C[6:5] = 0x00000003U
- // .. ==> MASK : 0x00000060U VAL : 0x00000060U
- // .. IBUF_DISABLE_MODE = 0
- // .. ==> 0XF8000B4C[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0
- // .. ==> 0XF8000B4C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B4C[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B4C[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B50[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x2
- // .. ==> 0XF8000B50[2:1] = 0x00000002U
- // .. ==> MASK : 0x00000006U VAL : 0x00000004U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B50[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x1
- // .. ==> 0XF8000B50[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. DCR_TYPE = 0x3
- // .. ==> 0XF8000B50[6:5] = 0x00000003U
- // .. ==> MASK : 0x00000060U VAL : 0x00000060U
- // .. IBUF_DISABLE_MODE = 0
- // .. ==> 0XF8000B50[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0
- // .. ==> 0XF8000B50[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B50[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B50[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B54[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x2
- // .. ==> 0XF8000B54[2:1] = 0x00000002U
- // .. ==> MASK : 0x00000006U VAL : 0x00000004U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B54[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x1
- // .. ==> 0XF8000B54[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. DCR_TYPE = 0x3
- // .. ==> 0XF8000B54[6:5] = 0x00000003U
- // .. ==> MASK : 0x00000060U VAL : 0x00000060U
- // .. IBUF_DISABLE_MODE = 0
- // .. ==> 0XF8000B54[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0
- // .. ==> 0XF8000B54[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B54[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B54[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B58[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x0
- // .. ==> 0XF8000B58[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B58[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x0
- // .. ==> 0XF8000B58[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. DCR_TYPE = 0x0
- // .. ==> 0XF8000B58[6:5] = 0x00000000U
- // .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. IBUF_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B58[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B58[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B58[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B58[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
- // .. DRIVE_P = 0x1c
- // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
- // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
- // .. DRIVE_N = 0xc
- // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
- // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
- // .. SLEW_P = 0x3
- // .. ==> 0XF8000B5C[18:14] = 0x00000003U
- // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U
- // .. SLEW_N = 0x3
- // .. ==> 0XF8000B5C[23:19] = 0x00000003U
- // .. ==> MASK : 0x00F80000U VAL : 0x00180000U
- // .. GTL = 0x0
- // .. ==> 0XF8000B5C[26:24] = 0x00000000U
- // .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. RTERM = 0x0
- // .. ==> 0XF8000B5C[31:27] = 0x00000000U
- // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
- // .. DRIVE_P = 0x1c
- // .. ==> 0XF8000B60[6:0] = 0x0000001CU
- // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
- // .. DRIVE_N = 0xc
- // .. ==> 0XF8000B60[13:7] = 0x0000000CU
- // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
- // .. SLEW_P = 0x6
- // .. ==> 0XF8000B60[18:14] = 0x00000006U
- // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
- // .. SLEW_N = 0x1f
- // .. ==> 0XF8000B60[23:19] = 0x0000001FU
- // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
- // .. GTL = 0x0
- // .. ==> 0XF8000B60[26:24] = 0x00000000U
- // .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. RTERM = 0x0
- // .. ==> 0XF8000B60[31:27] = 0x00000000U
- // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
- // .. DRIVE_P = 0x1c
- // .. ==> 0XF8000B64[6:0] = 0x0000001CU
- // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
- // .. DRIVE_N = 0xc
- // .. ==> 0XF8000B64[13:7] = 0x0000000CU
- // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
- // .. SLEW_P = 0x6
- // .. ==> 0XF8000B64[18:14] = 0x00000006U
- // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
- // .. SLEW_N = 0x1f
- // .. ==> 0XF8000B64[23:19] = 0x0000001FU
- // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
- // .. GTL = 0x0
- // .. ==> 0XF8000B64[26:24] = 0x00000000U
- // .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. RTERM = 0x0
- // .. ==> 0XF8000B64[31:27] = 0x00000000U
- // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
- // .. DRIVE_P = 0x1c
- // .. ==> 0XF8000B68[6:0] = 0x0000001CU
- // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
- // .. DRIVE_N = 0xc
- // .. ==> 0XF8000B68[13:7] = 0x0000000CU
- // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
- // .. SLEW_P = 0x6
- // .. ==> 0XF8000B68[18:14] = 0x00000006U
- // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
- // .. SLEW_N = 0x1f
- // .. ==> 0XF8000B68[23:19] = 0x0000001FU
- // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
- // .. GTL = 0x0
- // .. ==> 0XF8000B68[26:24] = 0x00000000U
- // .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. RTERM = 0x0
- // .. ==> 0XF8000B68[31:27] = 0x00000000U
- // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
- // .. VREF_INT_EN = 0x1
- // .. ==> 0XF8000B6C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. VREF_SEL = 0x4
- // .. ==> 0XF8000B6C[4:1] = 0x00000004U
- // .. ==> MASK : 0x0000001EU VAL : 0x00000008U
- // .. VREF_EXT_EN = 0x0
- // .. ==> 0XF8000B6C[6:5] = 0x00000000U
- // .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. VREF_PULLUP_EN = 0x0
- // .. ==> 0XF8000B6C[8:7] = 0x00000000U
- // .. ==> MASK : 0x00000180U VAL : 0x00000000U
- // .. REFIO_EN = 0x1
- // .. ==> 0XF8000B6C[9:9] = 0x00000001U
- // .. ==> MASK : 0x00000200U VAL : 0x00000200U
- // .. REFIO_PULLUP_EN = 0x0
- // .. ==> 0XF8000B6C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DRST_B_PULLUP_EN = 0x0
- // .. ==> 0XF8000B6C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // .. CKE_PULLUP_EN = 0x0
- // .. ==> 0XF8000B6C[14:14] = 0x00000000U
- // .. ==> MASK : 0x00004000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B6C, 0x000073FFU ,0x00000209U),
- // .. .. START: ASSERT RESET
- // .. .. RESET = 1
- // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. VRN_OUT = 0x1
- // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
- // .. ..
- EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U),
- // .. .. FINISH: ASSERT RESET
- // .. .. START: DEASSERT RESET
- // .. .. RESET = 0
- // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. VRN_OUT = 0x1
- // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
- // .. ..
- EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
- // .. .. FINISH: DEASSERT RESET
- // .. .. RESET = 0x1
- // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ENABLE = 0x1
- // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. .. VRP_TRI = 0x0
- // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. VRN_TRI = 0x0
- // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. VRP_OUT = 0x0
- // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. VRN_OUT = 0x1
- // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
- // .. .. NREF_OPT1 = 0x0
- // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
- // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U
- // .. .. NREF_OPT2 = 0x0
- // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U
- // .. .. NREF_OPT4 = 0x1
- // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
- // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U
- // .. .. PREF_OPT1 = 0x0
- // .. .. ==> 0XF8000B70[16:14] = 0x00000000U
- // .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U
- // .. .. PREF_OPT2 = 0x0
- // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
- // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U
- // .. .. UPDATE_CONTROL = 0x0
- // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
- // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U
- // .. .. INIT_COMPLETE = 0x0
- // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
- // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U
- // .. .. TST_CLK = 0x0
- // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
- // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U
- // .. .. TST_HLN = 0x0
- // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
- // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U
- // .. .. TST_HLP = 0x0
- // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
- // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U
- // .. .. TST_RST = 0x0
- // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
- // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
- // .. .. INT_DCI_EN = 0x0
- // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
- // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U),
- // .. FINISH: DDRIOB SETTINGS
- // .. START: MIO PROGRAMMING
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000700[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000700[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000700[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000700[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000700[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000700[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000700[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000700[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000700[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00000600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000704[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000704[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000704[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000704[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000704[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000704[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000704[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000704[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000704[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00000602U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000708[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000708[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000708[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000708[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000708[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000708[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000708[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000708[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000708[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000602U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800070C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF800070C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF800070C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800070C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800070C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800070C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF800070C[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF800070C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800070C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000602U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000710[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000710[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000710[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000710[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000710[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000710[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000710[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000710[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000710[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000602U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000714[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000714[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000714[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000714[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000714[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000714[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000714[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000714[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000714[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000602U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000718[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000718[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000718[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000718[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000718[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000718[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000718[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000718[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000718[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000602U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800071C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800071C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF800071C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800071C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800071C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800071C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF800071C[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF800071C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800071C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000720[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000720[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000720[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000720[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000720[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000720[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000720[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000720[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000720[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000602U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000724[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000724[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000724[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000724[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000724[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000724[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000724[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000724[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000724[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00000600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000728[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000728[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000728[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000728[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000728[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000728[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000728[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000728[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000728[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00000600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800072C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800072C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF800072C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800072C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800072C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800072C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF800072C[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF800072C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800072C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00000600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000730[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000730[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000730[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000730[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000730[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000730[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000730[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000730[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000730[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00000600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000734[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000734[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000734[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000734[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000734[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000734[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000734[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000734[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000734[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00000600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000738[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000738[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000738[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000738[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000738[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000738[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000738[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000738[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000738[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00000600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800073C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800073C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF800073C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800073C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800073C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800073C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF800073C[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF800073C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800073C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00000600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000740[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000740[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000740[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000740[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000740[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000740[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000740[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000740[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000740[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000202U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000744[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000744[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000744[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000744[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000744[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000744[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000744[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000744[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000744[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000202U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000748[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000748[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000748[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000748[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000748[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000748[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000748[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000748[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000748[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000202U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800074C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF800074C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF800074C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800074C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800074C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800074C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF800074C[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF800074C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800074C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000202U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000750[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000750[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000750[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000750[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000750[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000750[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000750[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000750[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000750[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000202U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000754[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000754[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000754[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000754[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000754[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000754[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000754[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000754[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000754[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000202U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000758[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF8000758[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000758[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000758[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000758[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000758[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000758[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000758[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000758[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000203U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF800075C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF800075C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF800075C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800075C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800075C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800075C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF800075C[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF800075C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800075C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000203U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000760[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF8000760[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000760[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000760[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000760[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000760[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000760[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000760[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000760[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000203U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000764[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF8000764[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000764[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000764[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000764[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000764[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000764[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000764[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000764[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000203U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000768[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF8000768[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000768[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000768[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000768[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000768[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000768[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000768[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000768[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000203U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF800076C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF800076C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF800076C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800076C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800076C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800076C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF800076C[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF800076C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800076C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000203U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000770[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000770[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000770[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000770[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000770[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000770[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000770[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000770[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000770[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000774[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF8000774[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000774[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000774[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000774[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000774[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000774[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000774[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000774[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000778[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000778[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000778[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000778[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000778[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000778[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000778[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000778[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000778[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF800077C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF800077C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF800077C[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF800077C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800077C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800077C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF800077C[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF800077C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800077C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000780[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000780[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000780[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000780[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000780[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000780[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000780[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000780[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000780[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000784[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000784[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000784[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000784[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000784[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000784[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000784[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000784[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000784[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000788[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000788[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000788[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000788[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000788[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000788[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000788[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000788[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000788[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800078C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800078C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF800078C[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF800078C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800078C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800078C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF800078C[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF800078C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800078C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000790[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF8000790[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000790[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000790[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000790[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000790[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000790[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000790[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000790[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000794[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000794[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000794[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000794[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000794[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000794[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000794[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000794[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000794[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000798[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000798[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000798[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000798[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000798[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000798[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000798[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000798[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000798[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800079C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800079C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF800079C[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF800079C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800079C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800079C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF800079C[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF800079C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800079C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007A0[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007A0[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007A0[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007A0[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007A0[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF80007A0[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007A0[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007A0[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007A0[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000280U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007A4[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007A4[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007A4[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007A4[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007A4[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF80007A4[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007A4[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007A4[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007A4[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000280U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007A8[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007A8[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007A8[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007A8[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007A8[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF80007A8[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007A8[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007A8[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007A8[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000280U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007AC[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007AC[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007AC[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007AC[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007AC[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF80007AC[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007AC[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007AC[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007AC[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000280U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007B0[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007B0[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007B0[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007B0[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007B0[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF80007B0[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007B0[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007B0[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007B0[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000280U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007B4[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007B4[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007B4[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007B4[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007B4[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF80007B4[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007B4[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007B4[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007B4[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000280U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF80007B8[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. Speed = 0
- // .. ==> 0XF80007B8[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007B8[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007B8[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007B8[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007B8, 0x00003F01U ,0x00000201U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007BC[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007BC[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007BC[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007BC[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF80007BC[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF80007BC[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007BC[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007BC[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007BC[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00000200U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007C0[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007C0[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007C0[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007C0[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 7
- // .. ==> 0XF80007C0[7:5] = 0x00000007U
- // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U
- // .. Speed = 0
- // .. ==> 0XF80007C0[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007C0[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007C0[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007C0[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF80007C4[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF80007C4[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007C4[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007C4[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 7
- // .. ==> 0XF80007C4[7:5] = 0x00000007U
- // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U
- // .. Speed = 0
- // .. ==> 0XF80007C4[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007C4[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007C4[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007C4[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF80007C8[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. Speed = 0
- // .. ==> 0XF80007C8[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007C8[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007C8[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007C8[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007C8, 0x00003F01U ,0x00000201U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007CC[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007CC[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007CC[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007CC[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF80007CC[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF80007CC[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007CC[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007CC[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007CC[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00000200U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007D0[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007D0[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007D0[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007D0[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007D0[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF80007D0[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007D0[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007D0[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007D0[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007D4[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007D4[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007D4[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007D4[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007D4[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF80007D4[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007D4[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007D4[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007D4[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U),
- // .. SDIO0_WP_SEL = 50
- // .. ==> 0XF8000830[5:0] = 0x00000032U
- // .. ==> MASK : 0x0000003FU VAL : 0x00000032U
- // .. SDIO0_CD_SEL = 46
- // .. ==> 0XF8000830[21:16] = 0x0000002EU
- // .. ==> MASK : 0x003F0000U VAL : 0x002E0000U
- // ..
- EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x002E0032U),
- // .. FINISH: MIO PROGRAMMING
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_peripherals_init_data_1_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
- // .. IBUF_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B48[7:7] = 0x00000001U
- // .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. TERM_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B48[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // ..
- EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
- // .. IBUF_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B4C[7:7] = 0x00000001U
- // .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. TERM_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B4C[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // ..
- EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
- // .. IBUF_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B50[7:7] = 0x00000001U
- // .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. TERM_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B50[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // ..
- EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
- // .. IBUF_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B54[7:7] = 0x00000001U
- // .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. TERM_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B54[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // ..
- EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
- // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // .. START: SRAM/NOR SET OPMODE
- // .. FINISH: SRAM/NOR SET OPMODE
- // .. START: UART REGISTERS
- // .. BDIV = 0x6
- // .. ==> 0XE0001034[7:0] = 0x00000006U
- // .. ==> MASK : 0x000000FFU VAL : 0x00000006U
- // ..
- EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
- // .. CD = 0x3e
- // .. ==> 0XE0001018[15:0] = 0x0000003EU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU
- // ..
- EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
- // .. STPBRK = 0x0
- // .. ==> 0XE0001000[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. STTBRK = 0x0
- // .. ==> 0XE0001000[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. RSTTO = 0x0
- // .. ==> 0XE0001000[6:6] = 0x00000000U
- // .. ==> MASK : 0x00000040U VAL : 0x00000000U
- // .. TXDIS = 0x0
- // .. ==> 0XE0001000[5:5] = 0x00000000U
- // .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. TXEN = 0x1
- // .. ==> 0XE0001000[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. RXDIS = 0x0
- // .. ==> 0XE0001000[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. RXEN = 0x1
- // .. ==> 0XE0001000[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. TXRES = 0x1
- // .. ==> 0XE0001000[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. RXRES = 0x1
- // .. ==> 0XE0001000[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // ..
- EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
- // .. IRMODE = 0x0
- // .. ==> 0XE0001004[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. UCLKEN = 0x0
- // .. ==> 0XE0001004[10:10] = 0x00000000U
- // .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. CHMODE = 0x0
- // .. ==> 0XE0001004[9:8] = 0x00000000U
- // .. ==> MASK : 0x00000300U VAL : 0x00000000U
- // .. NBSTOP = 0x0
- // .. ==> 0XE0001004[7:6] = 0x00000000U
- // .. ==> MASK : 0x000000C0U VAL : 0x00000000U
- // .. PAR = 0x4
- // .. ==> 0XE0001004[5:3] = 0x00000004U
- // .. ==> MASK : 0x00000038U VAL : 0x00000020U
- // .. CHRL = 0x0
- // .. ==> 0XE0001004[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. CLKS = 0x0
- // .. ==> 0XE0001004[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U),
- // .. FINISH: UART REGISTERS
- // .. START: QSPI REGISTERS
- // .. Holdb_dr = 1
- // .. ==> 0XE000D000[19:19] = 0x00000001U
- // .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // ..
- EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
- // .. FINISH: QSPI REGISTERS
- // .. START: PL POWER ON RESET REGISTERS
- // .. PCFG_POR_CNT_4K = 0
- // .. ==> 0XF8007000[29:29] = 0x00000000U
- // .. ==> MASK : 0x20000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
- // .. FINISH: PL POWER ON RESET REGISTERS
- // .. START: SMC TIMING CALCULATION REGISTER UPDATE
- // .. .. START: NAND SET CYCLE
- // .. .. FINISH: NAND SET CYCLE
- // .. .. START: OPMODE
- // .. .. FINISH: OPMODE
- // .. .. START: DIRECT COMMAND
- // .. .. FINISH: DIRECT COMMAND
- // .. .. START: SRAM/NOR CS0 SET CYCLE
- // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
- // .. .. START: DIRECT COMMAND
- // .. .. FINISH: DIRECT COMMAND
- // .. .. START: NOR CS0 BASE ADDRESS
- // .. .. FINISH: NOR CS0 BASE ADDRESS
- // .. .. START: SRAM/NOR CS1 SET CYCLE
- // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
- // .. .. START: DIRECT COMMAND
- // .. .. FINISH: DIRECT COMMAND
- // .. .. START: NOR CS1 BASE ADDRESS
- // .. .. FINISH: NOR CS1 BASE ADDRESS
- // .. .. START: USB RESET
- // .. .. .. START: USB0 RESET
- // .. .. .. .. START: DIR MODE BANK 0
- // .. .. .. .. DIRECTION_0 = 0x80
- // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U
- // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U),
- // .. .. .. .. FINISH: DIR MODE BANK 0
- // .. .. .. .. START: DIR MODE BANK 1
- // .. .. .. .. FINISH: DIR MODE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. MASK_0_LSW = 0xff7f
- // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
- // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U
- // .. .. .. .. DATA_0_LSW = 0x80
- // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
- // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. START: OUTPUT ENABLE BANK 0
- // .. .. .. .. OP_ENABLE_0 = 0x80
- // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U
- // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U),
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
- // .. .. .. .. START: OUTPUT ENABLE BANK 1
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. MASK_0_LSW = 0xff7f
- // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
- // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U
- // .. .. .. .. DATA_0_LSW = 0x0
- // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
- // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U),
- // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. START: ADD 1 MS DELAY
- // .. .. .. ..
- EMIT_MASKDELAY(0XF8F00200, 1),
- // .. .. .. .. FINISH: ADD 1 MS DELAY
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. MASK_0_LSW = 0xff7f
- // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
- // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U
- // .. .. .. .. DATA_0_LSW = 0x80
- // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
- // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: USB0 RESET
- // .. .. .. START: USB1 RESET
- // .. .. .. .. START: DIR MODE BANK 0
- // .. .. .. .. FINISH: DIR MODE BANK 0
- // .. .. .. .. START: DIR MODE BANK 1
- // .. .. .. .. FINISH: DIR MODE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. START: OUTPUT ENABLE BANK 0
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
- // .. .. .. .. START: OUTPUT ENABLE BANK 1
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. START: ADD 1 MS DELAY
- // .. .. .. ..
- EMIT_MASKDELAY(0XF8F00200, 1),
- // .. .. .. .. FINISH: ADD 1 MS DELAY
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: USB1 RESET
- // .. .. FINISH: USB RESET
- // .. .. START: ENET RESET
- // .. .. .. START: ENET0 RESET
- // .. .. .. .. START: DIR MODE BANK 0
- // .. .. .. .. FINISH: DIR MODE BANK 0
- // .. .. .. .. START: DIR MODE BANK 1
- // .. .. .. .. FINISH: DIR MODE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. START: OUTPUT ENABLE BANK 0
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
- // .. .. .. .. START: OUTPUT ENABLE BANK 1
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. START: ADD 1 MS DELAY
- // .. .. .. ..
- EMIT_MASKDELAY(0XF8F00200, 1),
- // .. .. .. .. FINISH: ADD 1 MS DELAY
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: ENET0 RESET
- // .. .. .. START: ENET1 RESET
- // .. .. .. .. START: DIR MODE BANK 0
- // .. .. .. .. FINISH: DIR MODE BANK 0
- // .. .. .. .. START: DIR MODE BANK 1
- // .. .. .. .. FINISH: DIR MODE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. START: OUTPUT ENABLE BANK 0
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
- // .. .. .. .. START: OUTPUT ENABLE BANK 1
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. START: ADD 1 MS DELAY
- // .. .. .. ..
- EMIT_MASKDELAY(0XF8F00200, 1),
- // .. .. .. .. FINISH: ADD 1 MS DELAY
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: ENET1 RESET
- // .. .. FINISH: ENET RESET
- // .. .. START: I2C RESET
- // .. .. .. START: I2C0 RESET
- // .. .. .. .. START: DIR MODE GPIO BANK0
- // .. .. .. .. FINISH: DIR MODE GPIO BANK0
- // .. .. .. .. START: DIR MODE GPIO BANK1
- // .. .. .. .. FINISH: DIR MODE GPIO BANK1
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. START: OUTPUT ENABLE
- // .. .. .. .. FINISH: OUTPUT ENABLE
- // .. .. .. .. START: OUTPUT ENABLE
- // .. .. .. .. FINISH: OUTPUT ENABLE
- // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. START: ADD 1 MS DELAY
- // .. .. .. ..
- EMIT_MASKDELAY(0XF8F00200, 1),
- // .. .. .. .. FINISH: ADD 1 MS DELAY
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: I2C0 RESET
- // .. .. .. START: I2C1 RESET
- // .. .. .. .. START: DIR MODE GPIO BANK0
- // .. .. .. .. FINISH: DIR MODE GPIO BANK0
- // .. .. .. .. START: DIR MODE GPIO BANK1
- // .. .. .. .. FINISH: DIR MODE GPIO BANK1
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. START: OUTPUT ENABLE
- // .. .. .. .. FINISH: OUTPUT ENABLE
- // .. .. .. .. START: OUTPUT ENABLE
- // .. .. .. .. FINISH: OUTPUT ENABLE
- // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. START: ADD 1 MS DELAY
- // .. .. .. ..
- EMIT_MASKDELAY(0XF8F00200, 1),
- // .. .. .. .. FINISH: ADD 1 MS DELAY
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: I2C1 RESET
- // .. .. FINISH: I2C RESET
- // .. .. START: NOR CHIP SELECT
- // .. .. .. START: DIR MODE BANK 0
- // .. .. .. FINISH: DIR MODE BANK 0
- // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. START: OUTPUT ENABLE BANK 0
- // .. .. .. FINISH: OUTPUT ENABLE BANK 0
- // .. .. FINISH: NOR CHIP SELECT
- // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_post_config_1_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: ENABLING LEVEL SHIFTER
- // .. USER_INP_ICT_EN_0 = 3
- // .. ==> 0XF8000900[1:0] = 0x00000003U
- // .. ==> MASK : 0x00000003U VAL : 0x00000003U
- // .. USER_INP_ICT_EN_1 = 3
- // .. ==> 0XF8000900[3:2] = 0x00000003U
- // .. ==> MASK : 0x0000000CU VAL : 0x0000000CU
- // ..
- EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
- // .. FINISH: ENABLING LEVEL SHIFTER
- // .. START: FPGA RESETS TO 0
- // .. reserved_3 = 0
- // .. ==> 0XF8000240[31:25] = 0x00000000U
- // .. ==> MASK : 0xFE000000U VAL : 0x00000000U
- // .. FPGA_ACP_RST = 0
- // .. ==> 0XF8000240[24:24] = 0x00000000U
- // .. ==> MASK : 0x01000000U VAL : 0x00000000U
- // .. FPGA_AXDS3_RST = 0
- // .. ==> 0XF8000240[23:23] = 0x00000000U
- // .. ==> MASK : 0x00800000U VAL : 0x00000000U
- // .. FPGA_AXDS2_RST = 0
- // .. ==> 0XF8000240[22:22] = 0x00000000U
- // .. ==> MASK : 0x00400000U VAL : 0x00000000U
- // .. FPGA_AXDS1_RST = 0
- // .. ==> 0XF8000240[21:21] = 0x00000000U
- // .. ==> MASK : 0x00200000U VAL : 0x00000000U
- // .. FPGA_AXDS0_RST = 0
- // .. ==> 0XF8000240[20:20] = 0x00000000U
- // .. ==> MASK : 0x00100000U VAL : 0x00000000U
- // .. reserved_2 = 0
- // .. ==> 0XF8000240[19:18] = 0x00000000U
- // .. ==> MASK : 0x000C0000U VAL : 0x00000000U
- // .. FSSW1_FPGA_RST = 0
- // .. ==> 0XF8000240[17:17] = 0x00000000U
- // .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. FSSW0_FPGA_RST = 0
- // .. ==> 0XF8000240[16:16] = 0x00000000U
- // .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. reserved_1 = 0
- // .. ==> 0XF8000240[15:14] = 0x00000000U
- // .. ==> MASK : 0x0000C000U VAL : 0x00000000U
- // .. FPGA_FMSW1_RST = 0
- // .. ==> 0XF8000240[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // .. FPGA_FMSW0_RST = 0
- // .. ==> 0XF8000240[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. FPGA_DMA3_RST = 0
- // .. ==> 0XF8000240[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. FPGA_DMA2_RST = 0
- // .. ==> 0XF8000240[10:10] = 0x00000000U
- // .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. FPGA_DMA1_RST = 0
- // .. ==> 0XF8000240[9:9] = 0x00000000U
- // .. ==> MASK : 0x00000200U VAL : 0x00000000U
- // .. FPGA_DMA0_RST = 0
- // .. ==> 0XF8000240[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. reserved = 0
- // .. ==> 0XF8000240[7:4] = 0x00000000U
- // .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. FPGA3_OUT_RST = 0
- // .. ==> 0XF8000240[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. FPGA2_OUT_RST = 0
- // .. ==> 0XF8000240[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. FPGA1_OUT_RST = 0
- // .. ==> 0XF8000240[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. FPGA0_OUT_RST = 0
- // .. ==> 0XF8000240[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
- // .. FINISH: FPGA RESETS TO 0
- // .. START: AFI REGISTERS
- // .. .. START: AFI0 REGISTERS
- // .. .. FINISH: AFI0 REGISTERS
- // .. .. START: AFI1 REGISTERS
- // .. .. FINISH: AFI1 REGISTERS
- // .. .. START: AFI2 REGISTERS
- // .. .. FINISH: AFI2 REGISTERS
- // .. .. START: AFI3 REGISTERS
- // .. .. FINISH: AFI3 REGISTERS
- // .. FINISH: AFI REGISTERS
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_debug_1_0[] = {
- // START: top
- // .. START: CROSS TRIGGER CONFIGURATIONS
- // .. .. START: UNLOCKING CTI REGISTERS
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. FINISH: UNLOCKING CTI REGISTERS
- // .. .. START: ENABLING CTI MODULES AND CHANNELS
- // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
- // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. FINISH: CROSS TRIGGER CONFIGURATIONS
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-
-#include "xil_io.h"
-#define PS7_MASK_POLL_TIME 100000000
-
-char*
-getPS7MessageInfo(unsigned key) {
-
- char* err_msg = "";
- switch (key) {
- case PS7_INIT_SUCCESS: err_msg = "PS7 initialization successful"; break;
- case PS7_INIT_CORRUPT: err_msg = "PS7 init Data Corrupted"; break;
- case PS7_INIT_TIMEOUT: err_msg = "PS7 init mask poll timeout"; break;
- case PS7_POLL_FAILED_DDR_INIT: err_msg = "Mask Poll failed for DDR Init"; break;
- case PS7_POLL_FAILED_DMA: err_msg = "Mask Poll failed for PLL Init"; break;
- case PS7_POLL_FAILED_PLL: err_msg = "Mask Poll failed for DMA done bit"; break;
- default: err_msg = "Undefined error status"; break;
- }
-
- return err_msg;
-}
-
-unsigned long
-ps7GetSiliconVersion () {
- // Read PS version from MCTRL register [31:28]
- unsigned long mask = 0xF0000000;
- unsigned long *addr = (unsigned long*) 0XF8007080;
- unsigned long ps_version = (*addr & mask) >> 28;
- return ps_version;
-}
-
-void mask_write (unsigned long add , unsigned long mask, unsigned long val ) {
- unsigned long *addr = (unsigned long*) add;
- *addr = ( val & mask ) | ( *addr & ~mask);
- //xil_printf("MaskWrite : 0x%x--> 0x%x \n \r" ,add, *addr);
-}
-
-
-int mask_poll(unsigned long add , unsigned long mask ) {
- volatile unsigned long *addr = (volatile unsigned long*) add;
- int i = 0;
- while (!(*addr & mask)) {
- if (i == PS7_MASK_POLL_TIME) {
- return -1;
- }
- i++;
- }
- return 1;
- //xil_printf("MaskPoll : 0x%x --> 0x%x \n \r" , add, *addr);
-}
-
-unsigned long mask_read(unsigned long add , unsigned long mask ) {
- unsigned long *addr = (unsigned long*) add;
- unsigned long val = (*addr & mask);
- //xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val);
- return val;
-}
-
-
-
-int
-ps7_config(unsigned long * ps7_config_init)
-{
- unsigned long *ptr = ps7_config_init;
-
- unsigned long opcode; // current instruction ..
- unsigned long args[16]; // no opcode has so many args ...
- int numargs; // number of arguments of this instruction
- int j; // general purpose index
-
- volatile unsigned long *addr; // some variable to make code readable
- unsigned long val,mask; // some variable to make code readable
-
- int finish = -1 ; // loop while this is negative !
- int i = 0; // Timeout variable
-
- while( finish < 0 ) {
- numargs = ptr[0] & 0xF;
- opcode = ptr[0] >> 4;
-
- for( j = 0 ; j < numargs ; j ++ )
- args[j] = ptr[j+1];
- ptr += numargs + 1;
-
-
- switch ( opcode ) {
-
- case OPCODE_EXIT:
- finish = PS7_INIT_SUCCESS;
- break;
-
- case OPCODE_CLEAR:
- addr = (unsigned long*) args[0];
- *addr = 0;
- break;
-
- case OPCODE_WRITE:
- addr = (unsigned long*) args[0];
- val = args[1];
- *addr = val;
- break;
-
- case OPCODE_MASKWRITE:
- addr = (unsigned long*) args[0];
- mask = args[1];
- val = args[2];
- *addr = ( val & mask ) | ( *addr & ~mask);
- break;
-
- case OPCODE_MASKPOLL:
- addr = (unsigned long*) args[0];
- mask = args[1];
- i = 0;
- while (!(*addr & mask)) {
- if (i == PS7_MASK_POLL_TIME) {
- finish = PS7_INIT_TIMEOUT;
- break;
- }
- i++;
- }
- break;
- case OPCODE_MASKDELAY:
- addr = (unsigned long*) args[0];
- mask = args[1];
- int delay = get_number_of_cycles_for_delay(mask);
- perf_reset_and_start_timer();
- while ((*addr < delay)) {
- }
- break;
- default:
- finish = PS7_INIT_CORRUPT;
- break;
- }
- }
- return finish;
-}
-
-unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0;
-unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0;
-unsigned long *ps7_clock_init_data = ps7_clock_init_data_3_0;
-unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0;
-unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
-
-int
-ps7_post_config()
-{
- // Get the PS_VERSION on run time
- unsigned long si_ver = ps7GetSiliconVersion ();
- int ret = -1;
- if (si_ver == PCW_SILICON_VERSION_1) {
- ret = ps7_config (ps7_post_config_1_0);
- if (ret != PS7_INIT_SUCCESS) return ret;
- } else if (si_ver == PCW_SILICON_VERSION_2) {
- ret = ps7_config (ps7_post_config_2_0);
- if (ret != PS7_INIT_SUCCESS) return ret;
- } else {
- ret = ps7_config (ps7_post_config_3_0);
- if (ret != PS7_INIT_SUCCESS) return ret;
- }
- return PS7_INIT_SUCCESS;
-}
-
-int
-ps7_debug()
-{
- // Get the PS_VERSION on run time
- unsigned long si_ver = ps7GetSiliconVersion ();
- int ret = -1;
- if (si_ver == PCW_SILICON_VERSION_1) {
- ret = ps7_config (ps7_debug_1_0);
- if (ret != PS7_INIT_SUCCESS) return ret;
- } else if (si_ver == PCW_SILICON_VERSION_2) {
- ret = ps7_config (ps7_debug_2_0);
- if (ret != PS7_INIT_SUCCESS) return ret;
- } else {
- ret = ps7_config (ps7_debug_3_0);
- if (ret != PS7_INIT_SUCCESS) return ret;
- }
- return PS7_INIT_SUCCESS;
-}
-
-int
-ps7_init()
-{
- // Get the PS_VERSION on run time
- unsigned long si_ver = ps7GetSiliconVersion ();
- int ret;
- //int pcw_ver = 0;
-
- if (si_ver == PCW_SILICON_VERSION_1) {
- ps7_mio_init_data = ps7_mio_init_data_1_0;
- ps7_pll_init_data = ps7_pll_init_data_1_0;
- ps7_clock_init_data = ps7_clock_init_data_1_0;
- ps7_ddr_init_data = ps7_ddr_init_data_1_0;
- ps7_peripherals_init_data = ps7_peripherals_init_data_1_0;
- //pcw_ver = 1;
-
- } else if (si_ver == PCW_SILICON_VERSION_2) {
- ps7_mio_init_data = ps7_mio_init_data_2_0;
- ps7_pll_init_data = ps7_pll_init_data_2_0;
- ps7_clock_init_data = ps7_clock_init_data_2_0;
- ps7_ddr_init_data = ps7_ddr_init_data_2_0;
- ps7_peripherals_init_data = ps7_peripherals_init_data_2_0;
- //pcw_ver = 2;
-
- } else {
- ps7_mio_init_data = ps7_mio_init_data_3_0;
- ps7_pll_init_data = ps7_pll_init_data_3_0;
- ps7_clock_init_data = ps7_clock_init_data_3_0;
- ps7_ddr_init_data = ps7_ddr_init_data_3_0;
- ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
- //pcw_ver = 3;
- }
-
- // MIO init
- ret = ps7_config (ps7_mio_init_data);
- if (ret != PS7_INIT_SUCCESS) return ret;
-
- // PLL init
- ret = ps7_config (ps7_pll_init_data);
- if (ret != PS7_INIT_SUCCESS) return ret;
-
- // Clock init
- ret = ps7_config (ps7_clock_init_data);
- if (ret != PS7_INIT_SUCCESS) return ret;
-
- // DDR init
- ret = ps7_config (ps7_ddr_init_data);
- if (ret != PS7_INIT_SUCCESS) return ret;
-
-
-
- // Peripherals init
- ret = ps7_config (ps7_peripherals_init_data);
- if (ret != PS7_INIT_SUCCESS) return ret;
- //xil_printf ("\n PCW Silicon Version : %d.0", pcw_ver);
- return PS7_INIT_SUCCESS;
-}
-
-
-
-
-/* For delay calculation using global timer */
-
-/* start timer */
- void perf_start_clock(void)
-{
- *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) | // Timer Enable
- (1 << 3) | // Auto-increment
- (0 << 8) // Pre-scale
- );
-}
-
-/* stop timer and reset timer count regs */
- void perf_reset_clock(void)
-{
- perf_disable_clock();
- *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_L32 = 0;
- *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_U32 = 0;
-}
-
-/* Compute mask for given delay in miliseconds*/
-int get_number_of_cycles_for_delay(unsigned int delay)
-{
- // GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x)
- return (APU_FREQ*delay/(2*1000));
-
-}
-
-/* stop timer */
- void perf_disable_clock(void)
-{
- *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = 0;
-}
-
-void perf_reset_and_start_timer()
-{
- perf_reset_clock();
- perf_start_clock();
-}
+++ /dev/null
-
-/******************************************************************************
-*
-* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
-*
-* SPDX-License-Identifier: GPL-2.0+
-*
-*
-*******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file ps7_init.h
-*
-* This file can be included in FSBL code
-* to get prototype of ps7_init() function
-* and error codes
-*
-*****************************************************************************/
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-//typedef unsigned int u32;
-
-
-/** do we need to make this name more unique ? **/
-//extern u32 ps7_init_data[];
-extern unsigned long * ps7_ddr_init_data;
-extern unsigned long * ps7_mio_init_data;
-extern unsigned long * ps7_pll_init_data;
-extern unsigned long * ps7_clock_init_data;
-extern unsigned long * ps7_peripherals_init_data;
-
-
-
-#define OPCODE_EXIT 0U
-#define OPCODE_CLEAR 1U
-#define OPCODE_WRITE 2U
-#define OPCODE_MASKWRITE 3U
-#define OPCODE_MASKPOLL 4U
-#define OPCODE_MASKDELAY 5U
-#define NEW_PS7_ERR_CODE 1
-
-/* Encode number of arguments in last nibble */
-#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 )
-#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr
-#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val
-#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
-#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask
-#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
-
-/* Returns codes of PS7_Init */
-#define PS7_INIT_SUCCESS (0) // 0 is success in good old C
-#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now
-#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out
-#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init
-#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit
-#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init
-
-
-/* Silicon Versions */
-#define PCW_SILICON_VERSION_1 0
-#define PCW_SILICON_VERSION_2 1
-#define PCW_SILICON_VERSION_3 2
-
-/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
-#define PS7_POST_CONFIG
-
-/* Freq of all peripherals */
-
-#define APU_FREQ 666666687
-#define DDR_FREQ 533333374
-#define DCI_FREQ 10158731
-#define QSPI_FREQ 200000000
-#define SMC_FREQ 10000000
-#define ENET0_FREQ 125000000
-#define ENET1_FREQ 10000000
-#define USB0_FREQ 60000000
-#define USB1_FREQ 60000000
-#define SDIO_FREQ 50000000
-#define UART_FREQ 50000000
-#define SPI_FREQ 10000000
-#define I2C_FREQ 111111115
-#define WDT_FREQ 111111115
-#define TTC_FREQ 50000000
-#define CAN_FREQ 10000000
-#define PCAP_FREQ 200000000
-#define TPIU_FREQ 200000000
-#define FPGA0_FREQ 100000000
-#define FPGA1_FREQ 100000000
-#define FPGA2_FREQ 33333336
-#define FPGA3_FREQ 50000000
-
-
-/* For delay calculation using global registers*/
-#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
-#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204
-#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208
-#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218
-
-int ps7_config( unsigned long*);
-int ps7_init();
-int ps7_post_config();
-int ps7_debug();
-char* getPS7MessageInfo(unsigned key);
-
-void perf_start_clock(void);
-void perf_disable_clock(void);
-void perf_reset_clock(void);
-void perf_reset_and_start_timer();
-int get_number_of_cycles_for_delay(unsigned int delay);
-#ifdef __cplusplus
-}
-#endif
+++ /dev/null
-/******************************************************************************
-* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
-*
-* SPDX-License-Identifier: GPL-2.0+
-*
-*
-******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file ps7_init_gpl.c
-*
-* This file is automatically generated
-*
-*****************************************************************************/
-
-#include "ps7_init_gpl.h"
-
-unsigned long ps7_pll_init_data_3_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: PLL SLCR REGISTERS
- // .. .. START: ARM PLL INIT
- // .. .. PLL_RES = 0x2
- // .. .. ==> 0XF8000110[7:4] = 0x00000002U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
- // .. .. PLL_CP = 0x2
- // .. .. ==> 0XF8000110[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. LOCK_CNT = 0xfa
- // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
- // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U
- // .. ..
- EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
- // .. .. .. START: UPDATE FB_DIV
- // .. .. .. PLL_FDIV = 0x28
- // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
- // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
- // .. .. .. FINISH: UPDATE FB_DIV
- // .. .. .. START: BY PASS PLL
- // .. .. .. PLL_BYPASS_FORCE = 1
- // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
- // .. .. .. FINISH: BY PASS PLL
- // .. .. .. START: ASSERT RESET
- // .. .. .. PLL_RESET = 1
- // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
- // .. .. .. FINISH: ASSERT RESET
- // .. .. .. START: DEASSERT RESET
- // .. .. .. PLL_RESET = 0
- // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
- // .. .. .. FINISH: DEASSERT RESET
- // .. .. .. START: CHECK PLL STATUS
- // .. .. .. ARM_PLL_LOCK = 1
- // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ..
- EMIT_MASKPOLL(0XF800010C, 0x00000001U),
- // .. .. .. FINISH: CHECK PLL STATUS
- // .. .. .. START: REMOVE PLL BY PASS
- // .. .. .. PLL_BYPASS_FORCE = 0
- // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
- // .. .. .. FINISH: REMOVE PLL BY PASS
- // .. .. .. SRCSEL = 0x0
- // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. .. .. DIVISOR = 0x2
- // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
- // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U
- // .. .. .. CPU_6OR4XCLKACT = 0x1
- // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
- // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U
- // .. .. .. CPU_3OR2XCLKACT = 0x1
- // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
- // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U
- // .. .. .. CPU_2XCLKACT = 0x1
- // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
- // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U
- // .. .. .. CPU_1XCLKACT = 0x1
- // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
- // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U
- // .. .. .. CPU_PERI_CLKACT = 0x1
- // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
- // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
- // .. .. FINISH: ARM PLL INIT
- // .. .. START: DDR PLL INIT
- // .. .. PLL_RES = 0x2
- // .. .. ==> 0XF8000114[7:4] = 0x00000002U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
- // .. .. PLL_CP = 0x2
- // .. .. ==> 0XF8000114[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. LOCK_CNT = 0x12c
- // .. .. ==> 0XF8000114[21:12] = 0x0000012CU
- // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U
- // .. ..
- EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
- // .. .. .. START: UPDATE FB_DIV
- // .. .. .. PLL_FDIV = 0x20
- // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
- // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
- // .. .. .. FINISH: UPDATE FB_DIV
- // .. .. .. START: BY PASS PLL
- // .. .. .. PLL_BYPASS_FORCE = 1
- // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
- // .. .. .. FINISH: BY PASS PLL
- // .. .. .. START: ASSERT RESET
- // .. .. .. PLL_RESET = 1
- // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
- // .. .. .. FINISH: ASSERT RESET
- // .. .. .. START: DEASSERT RESET
- // .. .. .. PLL_RESET = 0
- // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
- // .. .. .. FINISH: DEASSERT RESET
- // .. .. .. START: CHECK PLL STATUS
- // .. .. .. DDR_PLL_LOCK = 1
- // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. .. ..
- EMIT_MASKPOLL(0XF800010C, 0x00000002U),
- // .. .. .. FINISH: CHECK PLL STATUS
- // .. .. .. START: REMOVE PLL BY PASS
- // .. .. .. PLL_BYPASS_FORCE = 0
- // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
- // .. .. .. FINISH: REMOVE PLL BY PASS
- // .. .. .. DDR_3XCLKACT = 0x1
- // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. .. DDR_2XCLKACT = 0x1
- // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. .. .. DDR_3XCLK_DIVISOR = 0x2
- // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
- // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U
- // .. .. .. DDR_2XCLK_DIVISOR = 0x3
- // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
- // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
- // .. .. FINISH: DDR PLL INIT
- // .. .. START: IO PLL INIT
- // .. .. PLL_RES = 0xc
- // .. .. ==> 0XF8000118[7:4] = 0x0000000CU
- // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U
- // .. .. PLL_CP = 0x2
- // .. .. ==> 0XF8000118[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. LOCK_CNT = 0x145
- // .. .. ==> 0XF8000118[21:12] = 0x00000145U
- // .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U
- // .. ..
- EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U),
- // .. .. .. START: UPDATE FB_DIV
- // .. .. .. PLL_FDIV = 0x1e
- // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU
- // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U),
- // .. .. .. FINISH: UPDATE FB_DIV
- // .. .. .. START: BY PASS PLL
- // .. .. .. PLL_BYPASS_FORCE = 1
- // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
- // .. .. .. FINISH: BY PASS PLL
- // .. .. .. START: ASSERT RESET
- // .. .. .. PLL_RESET = 1
- // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
- // .. .. .. FINISH: ASSERT RESET
- // .. .. .. START: DEASSERT RESET
- // .. .. .. PLL_RESET = 0
- // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
- // .. .. .. FINISH: DEASSERT RESET
- // .. .. .. START: CHECK PLL STATUS
- // .. .. .. IO_PLL_LOCK = 1
- // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. .. ..
- EMIT_MASKPOLL(0XF800010C, 0x00000004U),
- // .. .. .. FINISH: CHECK PLL STATUS
- // .. .. .. START: REMOVE PLL BY PASS
- // .. .. .. PLL_BYPASS_FORCE = 0
- // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
- // .. .. .. FINISH: REMOVE PLL BY PASS
- // .. .. FINISH: IO PLL INIT
- // .. FINISH: PLL SLCR REGISTERS
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_clock_init_data_3_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: CLOCK CONTROL SLCR REGISTERS
- // .. CLKACT = 0x1
- // .. ==> 0XF8000128[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. DIVISOR0 = 0x23
- // .. ==> 0XF8000128[13:8] = 0x00000023U
- // .. ==> MASK : 0x00003F00U VAL : 0x00002300U
- // .. DIVISOR1 = 0x3
- // .. ==> 0XF8000128[25:20] = 0x00000003U
- // .. ==> MASK : 0x03F00000U VAL : 0x00300000U
- // ..
- EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U),
- // .. CLKACT = 0x1
- // .. ==> 0XF8000138[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000138[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
- // .. CLKACT = 0x1
- // .. ==> 0XF8000140[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000140[6:4] = 0x00000000U
- // .. ==> MASK : 0x00000070U VAL : 0x00000000U
- // .. DIVISOR = 0x8
- // .. ==> 0XF8000140[13:8] = 0x00000008U
- // .. ==> MASK : 0x00003F00U VAL : 0x00000800U
- // .. DIVISOR1 = 0x5
- // .. ==> 0XF8000140[25:20] = 0x00000005U
- // .. ==> MASK : 0x03F00000U VAL : 0x00500000U
- // ..
- EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00500801U),
- // .. CLKACT = 0x1
- // .. ==> 0XF800014C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. SRCSEL = 0x0
- // .. ==> 0XF800014C[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR = 0x5
- // .. ==> 0XF800014C[13:8] = 0x00000005U
- // .. ==> MASK : 0x00003F00U VAL : 0x00000500U
- // ..
- EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
- // .. CLKACT0 = 0x1
- // .. ==> 0XF8000150[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. CLKACT1 = 0x0
- // .. ==> 0XF8000150[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000150[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR = 0x14
- // .. ==> 0XF8000150[13:8] = 0x00000014U
- // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
- // ..
- EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U),
- // .. CLKACT0 = 0x0
- // .. ==> 0XF8000154[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. CLKACT1 = 0x1
- // .. ==> 0XF8000154[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000154[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR = 0x14
- // .. ==> 0XF8000154[13:8] = 0x00000014U
- // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
- // ..
- EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U),
- // .. CLKACT0 = 0x1
- // .. ==> 0XF800015C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. CLKACT1 = 0x0
- // .. ==> 0XF800015C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. SRCSEL = 0x0
- // .. ==> 0XF800015C[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR0 = 0xe
- // .. ==> 0XF800015C[13:8] = 0x0000000EU
- // .. ==> MASK : 0x00003F00U VAL : 0x00000E00U
- // .. DIVISOR1 = 0x3
- // .. ==> 0XF800015C[25:20] = 0x00000003U
- // .. ==> MASK : 0x03F00000U VAL : 0x00300000U
- // ..
- EMIT_MASKWRITE(0XF800015C, 0x03F03F33U ,0x00300E01U),
- // .. CAN0_MUX = 0x0
- // .. ==> 0XF8000160[5:0] = 0x00000000U
- // .. ==> MASK : 0x0000003FU VAL : 0x00000000U
- // .. CAN0_REF_SEL = 0x0
- // .. ==> 0XF8000160[6:6] = 0x00000000U
- // .. ==> MASK : 0x00000040U VAL : 0x00000000U
- // .. CAN1_MUX = 0x0
- // .. ==> 0XF8000160[21:16] = 0x00000000U
- // .. ==> MASK : 0x003F0000U VAL : 0x00000000U
- // .. CAN1_REF_SEL = 0x0
- // .. ==> 0XF8000160[22:22] = 0x00000000U
- // .. ==> MASK : 0x00400000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000160, 0x007F007FU ,0x00000000U),
- // .. CLKACT = 0x1
- // .. ==> 0XF8000168[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000168[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR = 0x5
- // .. ==> 0XF8000168[13:8] = 0x00000005U
- // .. ==> MASK : 0x00003F00U VAL : 0x00000500U
- // ..
- EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000170[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR0 = 0x14
- // .. ==> 0XF8000170[13:8] = 0x00000014U
- // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
- // .. DIVISOR1 = 0x1
- // .. ==> 0XF8000170[25:20] = 0x00000001U
- // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
- // ..
- EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00101400U),
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000180[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR0 = 0x14
- // .. ==> 0XF8000180[13:8] = 0x00000014U
- // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
- // .. DIVISOR1 = 0x1
- // .. ==> 0XF8000180[25:20] = 0x00000001U
- // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
- // ..
- EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00101400U),
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000190[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR0 = 0x14
- // .. ==> 0XF8000190[13:8] = 0x00000014U
- // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
- // .. DIVISOR1 = 0x1
- // .. ==> 0XF8000190[25:20] = 0x00000001U
- // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
- // ..
- EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101400U),
- // .. SRCSEL = 0x0
- // .. ==> 0XF80001A0[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR0 = 0x14
- // .. ==> 0XF80001A0[13:8] = 0x00000014U
- // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
- // .. DIVISOR1 = 0x1
- // .. ==> 0XF80001A0[25:20] = 0x00000001U
- // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
- // ..
- EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U),
- // .. CLK_621_TRUE = 0x1
- // .. ==> 0XF80001C4[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // ..
- EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
- // .. DMA_CPU_2XCLKACT = 0x1
- // .. ==> 0XF800012C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. USB0_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. USB1_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[3:3] = 0x00000001U
- // .. ==> MASK : 0x00000008U VAL : 0x00000008U
- // .. GEM0_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[6:6] = 0x00000001U
- // .. ==> MASK : 0x00000040U VAL : 0x00000040U
- // .. GEM1_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. SDI0_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[10:10] = 0x00000001U
- // .. ==> MASK : 0x00000400U VAL : 0x00000400U
- // .. SDI1_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. SPI0_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[14:14] = 0x00000000U
- // .. ==> MASK : 0x00004000U VAL : 0x00000000U
- // .. SPI1_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[15:15] = 0x00000000U
- // .. ==> MASK : 0x00008000U VAL : 0x00000000U
- // .. CAN0_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[16:16] = 0x00000001U
- // .. ==> MASK : 0x00010000U VAL : 0x00010000U
- // .. CAN1_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[17:17] = 0x00000000U
- // .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. I2C0_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[18:18] = 0x00000001U
- // .. ==> MASK : 0x00040000U VAL : 0x00040000U
- // .. I2C1_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[19:19] = 0x00000001U
- // .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // .. UART0_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[20:20] = 0x00000000U
- // .. ==> MASK : 0x00100000U VAL : 0x00000000U
- // .. UART1_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[21:21] = 0x00000001U
- // .. ==> MASK : 0x00200000U VAL : 0x00200000U
- // .. GPIO_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[22:22] = 0x00000001U
- // .. ==> MASK : 0x00400000U VAL : 0x00400000U
- // .. LQSPI_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[23:23] = 0x00000001U
- // .. ==> MASK : 0x00800000U VAL : 0x00800000U
- // .. SMC_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[24:24] = 0x00000001U
- // .. ==> MASK : 0x01000000U VAL : 0x01000000U
- // ..
- EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01ED044DU),
- // .. FINISH: CLOCK CONTROL SLCR REGISTERS
- // .. START: THIS SHOULD BE BLANK
- // .. FINISH: THIS SHOULD BE BLANK
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_ddr_init_data_3_0[] = {
- // START: top
- // .. START: DDR INITIALIZATION
- // .. .. START: LOCK DDR
- // .. .. reg_ddrc_soft_rstb = 0
- // .. .. ==> 0XF8006000[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_powerdown_en = 0x0
- // .. .. ==> 0XF8006000[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_ddrc_data_bus_width = 0x0
- // .. .. ==> 0XF8006000[3:2] = 0x00000000U
- // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U
- // .. .. reg_ddrc_burst8_refresh = 0x0
- // .. .. ==> 0XF8006000[6:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U
- // .. .. reg_ddrc_rdwr_idle_gap = 0x1
- // .. .. ==> 0XF8006000[13:7] = 0x00000001U
- // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U
- // .. .. reg_ddrc_dis_rd_bypass = 0x0
- // .. .. ==> 0XF8006000[14:14] = 0x00000000U
- // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_act_bypass = 0x0
- // .. .. ==> 0XF8006000[15:15] = 0x00000000U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_auto_refresh = 0x0
- // .. .. ==> 0XF8006000[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
- // .. .. FINISH: LOCK DDR
- // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81
- // .. .. ==> 0XF8006004[11:0] = 0x00000081U
- // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U
- // .. .. reserved_reg_ddrc_active_ranks = 0x1
- // .. .. ==> 0XF8006004[13:12] = 0x00000001U
- // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U
- // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
- // .. .. ==> 0XF8006004[18:14] = 0x00000000U
- // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU ,0x00001081U),
- // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
- // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
- // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU
- // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
- // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
- // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U
- // .. .. reg_ddrc_hpr_xact_run_length = 0xf
- // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
- // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U
- // .. ..
- EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
- // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
- // .. .. ==> 0XF800600C[10:0] = 0x00000001U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U
- // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
- // .. .. ==> 0XF800600C[21:11] = 0x00000002U
- // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U
- // .. .. reg_ddrc_lpr_xact_run_length = 0x8
- // .. .. ==> 0XF800600C[25:22] = 0x00000008U
- // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U
- // .. ..
- EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
- // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
- // .. .. ==> 0XF8006010[10:0] = 0x00000001U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U
- // .. .. reg_ddrc_w_xact_run_length = 0x8
- // .. .. ==> 0XF8006010[14:11] = 0x00000008U
- // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U
- // .. .. reg_ddrc_w_max_starve_x32 = 0x2
- // .. .. ==> 0XF8006010[25:15] = 0x00000002U
- // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U
- // .. ..
- EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
- // .. .. reg_ddrc_t_rc = 0x1b
- // .. .. ==> 0XF8006014[5:0] = 0x0000001BU
- // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001BU
- // .. .. reg_ddrc_t_rfc_min = 0x56
- // .. .. ==> 0XF8006014[13:6] = 0x00000056U
- // .. .. ==> MASK : 0x00003FC0U VAL : 0x00001580U
- // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
- // .. .. ==> 0XF8006014[20:14] = 0x00000010U
- // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U
- // .. ..
- EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004159BU),
- // .. .. reg_ddrc_wr2pre = 0x12
- // .. .. ==> 0XF8006018[4:0] = 0x00000012U
- // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U
- // .. .. reg_ddrc_powerdown_to_x32 = 0x6
- // .. .. ==> 0XF8006018[9:5] = 0x00000006U
- // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U
- // .. .. reg_ddrc_t_faw = 0x10
- // .. .. ==> 0XF8006018[15:10] = 0x00000010U
- // .. .. ==> MASK : 0x0000FC00U VAL : 0x00004000U
- // .. .. reg_ddrc_t_ras_max = 0x24
- // .. .. ==> 0XF8006018[21:16] = 0x00000024U
- // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U
- // .. .. reg_ddrc_t_ras_min = 0x14
- // .. .. ==> 0XF8006018[26:22] = 0x00000014U
- // .. .. ==> MASK : 0x07C00000U VAL : 0x05000000U
- // .. .. reg_ddrc_t_cke = 0x4
- // .. .. ==> 0XF8006018[31:28] = 0x00000004U
- // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x452440D2U),
- // .. .. reg_ddrc_write_latency = 0x5
- // .. .. ==> 0XF800601C[4:0] = 0x00000005U
- // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U
- // .. .. reg_ddrc_rd2wr = 0x7
- // .. .. ==> 0XF800601C[9:5] = 0x00000007U
- // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U
- // .. .. reg_ddrc_wr2rd = 0xe
- // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
- // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U
- // .. .. reg_ddrc_t_xp = 0x4
- // .. .. ==> 0XF800601C[19:15] = 0x00000004U
- // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U
- // .. .. reg_ddrc_pad_pd = 0x0
- // .. .. ==> 0XF800601C[22:20] = 0x00000000U
- // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U
- // .. .. reg_ddrc_rd2pre = 0x4
- // .. .. ==> 0XF800601C[27:23] = 0x00000004U
- // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U
- // .. .. reg_ddrc_t_rcd = 0x7
- // .. .. ==> 0XF800601C[31:28] = 0x00000007U
- // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U
- // .. ..
- EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
- // .. .. reg_ddrc_t_ccd = 0x4
- // .. .. ==> 0XF8006020[4:2] = 0x00000004U
- // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U
- // .. .. reg_ddrc_t_rrd = 0x4
- // .. .. ==> 0XF8006020[7:5] = 0x00000004U
- // .. .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. .. reg_ddrc_refresh_margin = 0x2
- // .. .. ==> 0XF8006020[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. reg_ddrc_t_rp = 0x7
- // .. .. ==> 0XF8006020[15:12] = 0x00000007U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U
- // .. .. reg_ddrc_refresh_to_x32 = 0x8
- // .. .. ==> 0XF8006020[20:16] = 0x00000008U
- // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U
- // .. .. reg_ddrc_mobile = 0x0
- // .. .. ==> 0XF8006020[22:22] = 0x00000000U
- // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U
- // .. .. reg_ddrc_en_dfi_dram_clk_disable = 0x0
- // .. .. ==> 0XF8006020[23:23] = 0x00000000U
- // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U
- // .. .. reg_ddrc_read_latency = 0x7
- // .. .. ==> 0XF8006020[28:24] = 0x00000007U
- // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U
- // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
- // .. .. ==> 0XF8006020[29:29] = 0x00000001U
- // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U
- // .. .. reg_ddrc_dis_pad_pd = 0x0
- // .. .. ==> 0XF8006020[30:30] = 0x00000000U
- // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU ,0x27087290U),
- // .. .. reg_ddrc_en_2t_timing_mode = 0x0
- // .. .. ==> 0XF8006024[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_prefer_write = 0x0
- // .. .. ==> 0XF8006024[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_wr = 0x0
- // .. .. ==> 0XF8006024[6:6] = 0x00000000U
- // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_addr = 0x0
- // .. .. ==> 0XF8006024[8:7] = 0x00000000U
- // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_data = 0x0
- // .. .. ==> 0XF8006024[24:9] = 0x00000000U
- // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U
- // .. .. ddrc_reg_mr_wr_busy = 0x0
- // .. .. ==> 0XF8006024[25:25] = 0x00000000U
- // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_type = 0x0
- // .. .. ==> 0XF8006024[26:26] = 0x00000000U
- // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_rdata_valid = 0x0
- // .. .. ==> 0XF8006024[27:27] = 0x00000000U
- // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U ,0x00000000U),
- // .. .. reg_ddrc_final_wait_x32 = 0x7
- // .. .. ==> 0XF8006028[6:0] = 0x00000007U
- // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U
- // .. .. reg_ddrc_pre_ocd_x32 = 0x0
- // .. .. ==> 0XF8006028[10:7] = 0x00000000U
- // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U
- // .. .. reg_ddrc_t_mrd = 0x4
- // .. .. ==> 0XF8006028[13:11] = 0x00000004U
- // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U
- // .. ..
- EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
- // .. .. reg_ddrc_emr2 = 0x8
- // .. .. ==> 0XF800602C[15:0] = 0x00000008U
- // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U
- // .. .. reg_ddrc_emr3 = 0x0
- // .. .. ==> 0XF800602C[31:16] = 0x00000000U
- // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
- // .. .. reg_ddrc_mr = 0x930
- // .. .. ==> 0XF8006030[15:0] = 0x00000930U
- // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U
- // .. .. reg_ddrc_emr = 0x4
- // .. .. ==> 0XF8006030[31:16] = 0x00000004U
- // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U
- // .. ..
- EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
- // .. .. reg_ddrc_burst_rdwr = 0x4
- // .. .. ==> 0XF8006034[3:0] = 0x00000004U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U
- // .. .. reg_ddrc_pre_cke_x1024 = 0x105
- // .. .. ==> 0XF8006034[13:4] = 0x00000105U
- // .. .. ==> MASK : 0x00003FF0U VAL : 0x00001050U
- // .. .. reg_ddrc_post_cke_x1024 = 0x1
- // .. .. ==> 0XF8006034[25:16] = 0x00000001U
- // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U
- // .. .. reg_ddrc_burstchop = 0x0
- // .. .. ==> 0XF8006034[28:28] = 0x00000000U
- // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U),
- // .. .. reg_ddrc_force_low_pri_n = 0x0
- // .. .. ==> 0XF8006038[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_dq = 0x0
- // .. .. ==> 0XF8006038[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006038, 0x00000003U ,0x00000000U),
- // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
- // .. .. ==> 0XF800603C[3:0] = 0x00000007U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U
- // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
- // .. .. ==> 0XF800603C[7:4] = 0x00000007U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U
- // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
- // .. .. ==> 0XF800603C[11:8] = 0x00000007U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U
- // .. .. reg_ddrc_addrmap_col_b5 = 0x0
- // .. .. ==> 0XF800603C[15:12] = 0x00000000U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b6 = 0x0
- // .. .. ==> 0XF800603C[19:16] = 0x00000000U
- // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
- // .. .. reg_ddrc_addrmap_col_b2 = 0x0
- // .. .. ==> 0XF8006040[3:0] = 0x00000000U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b3 = 0x0
- // .. .. ==> 0XF8006040[7:4] = 0x00000000U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b4 = 0x0
- // .. .. ==> 0XF8006040[11:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b7 = 0x0
- // .. .. ==> 0XF8006040[15:12] = 0x00000000U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b8 = 0x0
- // .. .. ==> 0XF8006040[19:16] = 0x00000000U
- // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b9 = 0xf
- // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
- // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U
- // .. .. reg_ddrc_addrmap_col_b10 = 0xf
- // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
- // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U
- // .. .. reg_ddrc_addrmap_col_b11 = 0xf
- // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
- // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
- // .. .. reg_ddrc_addrmap_row_b0 = 0x6
- // .. .. ==> 0XF8006044[3:0] = 0x00000006U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U
- // .. .. reg_ddrc_addrmap_row_b1 = 0x6
- // .. .. ==> 0XF8006044[7:4] = 0x00000006U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U
- // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
- // .. .. ==> 0XF8006044[11:8] = 0x00000006U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U
- // .. .. reg_ddrc_addrmap_row_b12 = 0x6
- // .. .. ==> 0XF8006044[15:12] = 0x00000006U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U
- // .. .. reg_ddrc_addrmap_row_b13 = 0x6
- // .. .. ==> 0XF8006044[19:16] = 0x00000006U
- // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U
- // .. .. reg_ddrc_addrmap_row_b14 = 0x6
- // .. .. ==> 0XF8006044[23:20] = 0x00000006U
- // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U
- // .. .. reg_ddrc_addrmap_row_b15 = 0xf
- // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
- // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U),
- // .. .. reg_phy_rd_local_odt = 0x0
- // .. .. ==> 0XF8006048[13:12] = 0x00000000U
- // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U
- // .. .. reg_phy_wr_local_odt = 0x3
- // .. .. ==> 0XF8006048[15:14] = 0x00000003U
- // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U
- // .. .. reg_phy_idle_local_odt = 0x3
- // .. .. ==> 0XF8006048[17:16] = 0x00000003U
- // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U
- // .. ..
- EMIT_MASKWRITE(0XF8006048, 0x0003F000U ,0x0003C000U),
- // .. .. reg_phy_rd_cmd_to_data = 0x0
- // .. .. ==> 0XF8006050[3:0] = 0x00000000U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
- // .. .. reg_phy_wr_cmd_to_data = 0x0
- // .. .. ==> 0XF8006050[7:4] = 0x00000000U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. .. reg_phy_rdc_we_to_re_delay = 0x8
- // .. .. ==> 0XF8006050[11:8] = 0x00000008U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U
- // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
- // .. .. ==> 0XF8006050[15:15] = 0x00000000U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
- // .. .. reg_phy_use_fixed_re = 0x1
- // .. .. ==> 0XF8006050[16:16] = 0x00000001U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U
- // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
- // .. .. ==> 0XF8006050[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
- // .. .. ==> 0XF8006050[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_phy_clk_stall_level = 0x0
- // .. .. ==> 0XF8006050[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
- // .. .. ==> 0XF8006050[27:24] = 0x00000007U
- // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U
- // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
- // .. .. ==> 0XF8006050[31:28] = 0x00000007U
- // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
- // .. .. reg_ddrc_dis_dll_calib = 0x0
- // .. .. ==> 0XF8006058[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006058, 0x00010000U ,0x00000000U),
- // .. .. reg_ddrc_rd_odt_delay = 0x3
- // .. .. ==> 0XF800605C[3:0] = 0x00000003U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U
- // .. .. reg_ddrc_wr_odt_delay = 0x0
- // .. .. ==> 0XF800605C[7:4] = 0x00000000U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. .. reg_ddrc_rd_odt_hold = 0x0
- // .. .. ==> 0XF800605C[11:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U
- // .. .. reg_ddrc_wr_odt_hold = 0x5
- // .. .. ==> 0XF800605C[15:12] = 0x00000005U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U
- // .. ..
- EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
- // .. .. reg_ddrc_pageclose = 0x0
- // .. .. ==> 0XF8006060[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_lpr_num_entries = 0x1f
- // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
- // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU
- // .. .. reg_ddrc_auto_pre_en = 0x0
- // .. .. ==> 0XF8006060[7:7] = 0x00000000U
- // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. .. reg_ddrc_refresh_update_level = 0x0
- // .. .. ==> 0XF8006060[8:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_wc = 0x0
- // .. .. ==> 0XF8006060[9:9] = 0x00000000U
- // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_collision_page_opt = 0x0
- // .. .. ==> 0XF8006060[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_ddrc_selfref_en = 0x0
- // .. .. ==> 0XF8006060[12:12] = 0x00000000U
- // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
- // .. .. reg_ddrc_go2critical_hysteresis = 0x0
- // .. .. ==> 0XF8006064[12:5] = 0x00000000U
- // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U
- // .. .. reg_arb_go2critical_en = 0x1
- // .. .. ==> 0XF8006064[17:17] = 0x00000001U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U
- // .. ..
- EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
- // .. .. reg_ddrc_wrlvl_ww = 0x41
- // .. .. ==> 0XF8006068[7:0] = 0x00000041U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U
- // .. .. reg_ddrc_rdlvl_rr = 0x41
- // .. .. ==> 0XF8006068[15:8] = 0x00000041U
- // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U
- // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
- // .. .. ==> 0XF8006068[25:16] = 0x00000028U
- // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U
- // .. ..
- EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
- // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
- // .. .. ==> 0XF800606C[7:0] = 0x00000010U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U
- // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
- // .. .. ==> 0XF800606C[15:8] = 0x00000016U
- // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U
- // .. ..
- EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
- // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1
- // .. .. ==> 0XF8006078[3:0] = 0x00000001U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U
- // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1
- // .. .. ==> 0XF8006078[7:4] = 0x00000001U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U
- // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1
- // .. .. ==> 0XF8006078[11:8] = 0x00000001U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U
- // .. .. reg_ddrc_t_cksre = 0x6
- // .. .. ==> 0XF8006078[15:12] = 0x00000006U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U
- // .. .. reg_ddrc_t_cksrx = 0x6
- // .. .. ==> 0XF8006078[19:16] = 0x00000006U
- // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U
- // .. .. reg_ddrc_t_ckesr = 0x4
- // .. .. ==> 0XF8006078[25:20] = 0x00000004U
- // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U
- // .. ..
- EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U),
- // .. .. reg_ddrc_t_ckpde = 0x2
- // .. .. ==> 0XF800607C[3:0] = 0x00000002U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U
- // .. .. reg_ddrc_t_ckpdx = 0x2
- // .. .. ==> 0XF800607C[7:4] = 0x00000002U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
- // .. .. reg_ddrc_t_ckdpde = 0x2
- // .. .. ==> 0XF800607C[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. reg_ddrc_t_ckdpdx = 0x2
- // .. .. ==> 0XF800607C[15:12] = 0x00000002U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U
- // .. .. reg_ddrc_t_ckcsx = 0x3
- // .. .. ==> 0XF800607C[19:16] = 0x00000003U
- // .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U
- // .. ..
- EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U),
- // .. .. reg_ddrc_dis_auto_zq = 0x0
- // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_ddr3 = 0x1
- // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. .. reg_ddrc_t_mod = 0x200
- // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
- // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U
- // .. .. reg_ddrc_t_zq_long_nop = 0x200
- // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
- // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U
- // .. .. reg_ddrc_t_zq_short_nop = 0x40
- // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
- // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
- // .. .. t_zq_short_interval_x1024 = 0xcb73
- // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U
- // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U
- // .. .. dram_rstn_x1024 = 0x69
- // .. .. ==> 0XF80060A8[27:20] = 0x00000069U
- // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U
- // .. ..
- EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
- // .. .. deeppowerdown_en = 0x0
- // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. deeppowerdown_to_x1024 = 0xff
- // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
- // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU
- // .. ..
- EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
- // .. .. dfi_wrlvl_max_x1024 = 0xfff
- // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
- // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU
- // .. .. dfi_rdlvl_max_x1024 = 0xfff
- // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
- // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U
- // .. .. ddrc_reg_twrlvl_max_error = 0x0
- // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
- // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U
- // .. .. ddrc_reg_trdlvl_max_error = 0x0
- // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
- // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
- // .. .. reg_ddrc_dfi_wr_level_en = 0x1
- // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
- // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U
- // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
- // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
- // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U
- // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
- // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
- // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
- // .. .. reg_ddrc_skip_ocd = 0x1
- // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
- // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U
- // .. ..
- EMIT_MASKWRITE(0XF80060B4, 0x00000200U ,0x00000200U),
- // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
- // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
- // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U
- // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
- // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
- // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U
- // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
- // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
- // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U
- // .. ..
- EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
- // .. .. START: RESET ECC ERROR
- // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1
- // .. .. ==> 0XF80060C4[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. Clear_Correctable_DRAM_ECC_error = 1
- // .. .. ==> 0XF80060C4[1:1] = 0x00000001U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. ..
- EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U),
- // .. .. FINISH: RESET ECC ERROR
- // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
- // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
- // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
- // .. .. CORR_ECC_LOG_VALID = 0x0
- // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. ECC_CORRECTED_BIT_NUM = 0x0
- // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
- // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
- // .. .. UNCORR_ECC_LOG_VALID = 0x0
- // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
- // .. .. STAT_NUM_CORR_ERR = 0x0
- // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
- // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U
- // .. .. STAT_NUM_UNCORR_ERR = 0x0
- // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
- // .. .. reg_ddrc_ecc_mode = 0x0
- // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_scrub = 0x1
- // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U
- // .. ..
- EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
- // .. .. reg_phy_dif_on = 0x0
- // .. .. ==> 0XF8006114[3:0] = 0x00000000U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
- // .. .. reg_phy_dif_off = 0x0
- // .. .. ==> 0XF8006114[7:4] = 0x00000000U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
- // .. .. reg_phy_data_slice_in_use = 0x1
- // .. .. ==> 0XF8006118[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_phy_rdlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006118[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_inc_mode = 0x0
- // .. .. ==> 0XF8006118[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_wrlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006118[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_bist_shift_dq = 0x0
- // .. .. ==> 0XF8006118[14:6] = 0x00000000U
- // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. .. reg_phy_bist_err_clr = 0x0
- // .. .. ==> 0XF8006118[23:15] = 0x00000000U
- // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. .. reg_phy_dq_offset = 0x40
- // .. .. ==> 0XF8006118[30:24] = 0x00000040U
- // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU ,0x40000001U),
- // .. .. reg_phy_data_slice_in_use = 0x1
- // .. .. ==> 0XF800611C[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_phy_rdlvl_inc_mode = 0x0
- // .. .. ==> 0XF800611C[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_inc_mode = 0x0
- // .. .. ==> 0XF800611C[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_wrlvl_inc_mode = 0x0
- // .. .. ==> 0XF800611C[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_bist_shift_dq = 0x0
- // .. .. ==> 0XF800611C[14:6] = 0x00000000U
- // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. .. reg_phy_bist_err_clr = 0x0
- // .. .. ==> 0XF800611C[23:15] = 0x00000000U
- // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. .. reg_phy_dq_offset = 0x40
- // .. .. ==> 0XF800611C[30:24] = 0x00000040U
- // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU ,0x40000001U),
- // .. .. reg_phy_data_slice_in_use = 0x1
- // .. .. ==> 0XF8006120[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_phy_rdlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006120[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_inc_mode = 0x0
- // .. .. ==> 0XF8006120[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_wrlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006120[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_bist_shift_dq = 0x0
- // .. .. ==> 0XF8006120[14:6] = 0x00000000U
- // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. .. reg_phy_bist_err_clr = 0x0
- // .. .. ==> 0XF8006120[23:15] = 0x00000000U
- // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. .. reg_phy_dq_offset = 0x40
- // .. .. ==> 0XF8006120[30:24] = 0x00000040U
- // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU ,0x40000001U),
- // .. .. reg_phy_data_slice_in_use = 0x1
- // .. .. ==> 0XF8006124[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_phy_rdlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006124[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_inc_mode = 0x0
- // .. .. ==> 0XF8006124[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_wrlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006124[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_bist_shift_dq = 0x0
- // .. .. ==> 0XF8006124[14:6] = 0x00000000U
- // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. .. reg_phy_bist_err_clr = 0x0
- // .. .. ==> 0XF8006124[23:15] = 0x00000000U
- // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. .. reg_phy_dq_offset = 0x40
- // .. .. ==> 0XF8006124[30:24] = 0x00000040U
- // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU ,0x40000001U),
- // .. .. reg_phy_wrlvl_init_ratio = 0x1d
- // .. .. ==> 0XF800612C[9:0] = 0x0000001DU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x0000001DU
- // .. .. reg_phy_gatelvl_init_ratio = 0xf2
- // .. .. ==> 0XF800612C[19:10] = 0x000000F2U
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x0003C800U
- // .. ..
- EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0003C81DU),
- // .. .. reg_phy_wrlvl_init_ratio = 0x12
- // .. .. ==> 0XF8006130[9:0] = 0x00000012U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000012U
- // .. .. reg_phy_gatelvl_init_ratio = 0xd8
- // .. .. ==> 0XF8006130[19:10] = 0x000000D8U
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x00036000U
- // .. ..
- EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00036012U),
- // .. .. reg_phy_wrlvl_init_ratio = 0xc
- // .. .. ==> 0XF8006134[9:0] = 0x0000000CU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x0000000CU
- // .. .. reg_phy_gatelvl_init_ratio = 0xde
- // .. .. ==> 0XF8006134[19:10] = 0x000000DEU
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x00037800U
- // .. ..
- EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0003780CU),
- // .. .. reg_phy_wrlvl_init_ratio = 0x21
- // .. .. ==> 0XF8006138[9:0] = 0x00000021U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000021U
- // .. .. reg_phy_gatelvl_init_ratio = 0xee
- // .. .. ==> 0XF8006138[19:10] = 0x000000EEU
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x0003B800U
- // .. ..
- EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0003B821U),
- // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. .. ==> 0XF8006140[9:0] = 0x00000035U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. .. reg_phy_rd_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006140[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006140[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
- // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. .. ==> 0XF8006144[9:0] = 0x00000035U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. .. reg_phy_rd_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006144[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006144[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
- // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. .. ==> 0XF8006148[9:0] = 0x00000035U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. .. reg_phy_rd_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006148[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006148[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
- // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. .. ==> 0XF800614C[9:0] = 0x00000035U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. .. reg_phy_rd_dqs_slave_force = 0x0
- // .. .. ==> 0XF800614C[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. .. ==> 0XF800614C[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
- // .. .. reg_phy_wr_dqs_slave_ratio = 0x9d
- // .. .. ==> 0XF8006154[9:0] = 0x0000009DU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x0000009DU
- // .. .. reg_phy_wr_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006154[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006154[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x0000009DU),
- // .. .. reg_phy_wr_dqs_slave_ratio = 0x92
- // .. .. ==> 0XF8006158[9:0] = 0x00000092U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000092U
- // .. .. reg_phy_wr_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006158[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006158[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000092U),
- // .. .. reg_phy_wr_dqs_slave_ratio = 0x8c
- // .. .. ==> 0XF800615C[9:0] = 0x0000008CU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x0000008CU
- // .. .. reg_phy_wr_dqs_slave_force = 0x0
- // .. .. ==> 0XF800615C[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. .. ==> 0XF800615C[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x0000008CU),
- // .. .. reg_phy_wr_dqs_slave_ratio = 0xa1
- // .. .. ==> 0XF8006160[9:0] = 0x000000A1U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000000A1U
- // .. .. reg_phy_wr_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006160[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006160[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x000000A1U),
- // .. .. reg_phy_fifo_we_slave_ratio = 0x147
- // .. .. ==> 0XF8006168[10:0] = 0x00000147U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x00000147U
- // .. .. reg_phy_fifo_we_in_force = 0x0
- // .. .. ==> 0XF8006168[11:11] = 0x00000000U
- // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. .. reg_phy_fifo_we_in_delay = 0x0
- // .. .. ==> 0XF8006168[20:12] = 0x00000000U
- // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000147U),
- // .. .. reg_phy_fifo_we_slave_ratio = 0x12d
- // .. .. ==> 0XF800616C[10:0] = 0x0000012DU
- // .. .. ==> MASK : 0x000007FFU VAL : 0x0000012DU
- // .. .. reg_phy_fifo_we_in_force = 0x0
- // .. .. ==> 0XF800616C[11:11] = 0x00000000U
- // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. .. reg_phy_fifo_we_in_delay = 0x0
- // .. .. ==> 0XF800616C[20:12] = 0x00000000U
- // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x0000012DU),
- // .. .. reg_phy_fifo_we_slave_ratio = 0x133
- // .. .. ==> 0XF8006170[10:0] = 0x00000133U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x00000133U
- // .. .. reg_phy_fifo_we_in_force = 0x0
- // .. .. ==> 0XF8006170[11:11] = 0x00000000U
- // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. .. reg_phy_fifo_we_in_delay = 0x0
- // .. .. ==> 0XF8006170[20:12] = 0x00000000U
- // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000133U),
- // .. .. reg_phy_fifo_we_slave_ratio = 0x143
- // .. .. ==> 0XF8006174[10:0] = 0x00000143U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x00000143U
- // .. .. reg_phy_fifo_we_in_force = 0x0
- // .. .. ==> 0XF8006174[11:11] = 0x00000000U
- // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. .. reg_phy_fifo_we_in_delay = 0x0
- // .. .. ==> 0XF8006174[20:12] = 0x00000000U
- // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000143U),
- // .. .. reg_phy_wr_data_slave_ratio = 0xdd
- // .. .. ==> 0XF800617C[9:0] = 0x000000DDU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000000DDU
- // .. .. reg_phy_wr_data_slave_force = 0x0
- // .. .. ==> 0XF800617C[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_data_slave_delay = 0x0
- // .. .. ==> 0XF800617C[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000DDU),
- // .. .. reg_phy_wr_data_slave_ratio = 0xd2
- // .. .. ==> 0XF8006180[9:0] = 0x000000D2U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000000D2U
- // .. .. reg_phy_wr_data_slave_force = 0x0
- // .. .. ==> 0XF8006180[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_data_slave_delay = 0x0
- // .. .. ==> 0XF8006180[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000D2U),
- // .. .. reg_phy_wr_data_slave_ratio = 0xcc
- // .. .. ==> 0XF8006184[9:0] = 0x000000CCU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000000CCU
- // .. .. reg_phy_wr_data_slave_force = 0x0
- // .. .. ==> 0XF8006184[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_data_slave_delay = 0x0
- // .. .. ==> 0XF8006184[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000CCU),
- // .. .. reg_phy_wr_data_slave_ratio = 0xe1
- // .. .. ==> 0XF8006188[9:0] = 0x000000E1U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000000E1U
- // .. .. reg_phy_wr_data_slave_force = 0x0
- // .. .. ==> 0XF8006188[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_data_slave_delay = 0x0
- // .. .. ==> 0XF8006188[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000E1U),
- // .. .. reg_phy_bl2 = 0x0
- // .. .. ==> 0XF8006190[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_at_spd_atpg = 0x0
- // .. .. ==> 0XF8006190[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_bist_enable = 0x0
- // .. .. ==> 0XF8006190[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_bist_force_err = 0x0
- // .. .. ==> 0XF8006190[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. reg_phy_bist_mode = 0x0
- // .. .. ==> 0XF8006190[6:5] = 0x00000000U
- // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. .. reg_phy_invert_clkout = 0x1
- // .. .. ==> 0XF8006190[7:7] = 0x00000001U
- // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. .. reg_phy_sel_logic = 0x0
- // .. .. ==> 0XF8006190[9:9] = 0x00000000U
- // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U
- // .. .. reg_phy_ctrl_slave_ratio = 0x100
- // .. .. ==> 0XF8006190[19:10] = 0x00000100U
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U
- // .. .. reg_phy_ctrl_slave_force = 0x0
- // .. .. ==> 0XF8006190[20:20] = 0x00000000U
- // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U
- // .. .. reg_phy_ctrl_slave_delay = 0x0
- // .. .. ==> 0XF8006190[27:21] = 0x00000000U
- // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U
- // .. .. reg_phy_lpddr = 0x0
- // .. .. ==> 0XF8006190[29:29] = 0x00000000U
- // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U
- // .. .. reg_phy_cmd_latency = 0x0
- // .. .. ==> 0XF8006190[30:30] = 0x00000000U
- // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU ,0x00040080U),
- // .. .. reg_phy_wr_rl_delay = 0x2
- // .. .. ==> 0XF8006194[4:0] = 0x00000002U
- // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U
- // .. .. reg_phy_rd_rl_delay = 0x4
- // .. .. ==> 0XF8006194[9:5] = 0x00000004U
- // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U
- // .. .. reg_phy_dll_lock_diff = 0xf
- // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
- // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U
- // .. .. reg_phy_use_wr_level = 0x1
- // .. .. ==> 0XF8006194[14:14] = 0x00000001U
- // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U
- // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
- // .. .. ==> 0XF8006194[15:15] = 0x00000001U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U
- // .. .. reg_phy_use_rd_data_eye_level = 0x1
- // .. .. ==> 0XF8006194[16:16] = 0x00000001U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U
- // .. .. reg_phy_dis_calib_rst = 0x0
- // .. .. ==> 0XF8006194[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_phy_ctrl_slave_delay = 0x0
- // .. .. ==> 0XF8006194[19:18] = 0x00000000U
- // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
- // .. .. reg_arb_page_addr_mask = 0x0
- // .. .. ==> 0XF8006204[31:0] = 0x00000000U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
- // .. .. reg_arb_pri_wr_portn = 0x3ff
- // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_wr_portn = 0x0
- // .. .. ==> 0XF8006208[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. .. ==> 0XF8006208[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. .. ==> 0XF8006208[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006208, 0x000703FFU ,0x000003FFU),
- // .. .. reg_arb_pri_wr_portn = 0x3ff
- // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_wr_portn = 0x0
- // .. .. ==> 0XF800620C[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. .. ==> 0XF800620C[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. .. ==> 0XF800620C[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800620C, 0x000703FFU ,0x000003FFU),
- // .. .. reg_arb_pri_wr_portn = 0x3ff
- // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_wr_portn = 0x0
- // .. .. ==> 0XF8006210[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. .. ==> 0XF8006210[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. .. ==> 0XF8006210[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006210, 0x000703FFU ,0x000003FFU),
- // .. .. reg_arb_pri_wr_portn = 0x3ff
- // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_wr_portn = 0x0
- // .. .. ==> 0XF8006214[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. .. ==> 0XF8006214[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. .. ==> 0XF8006214[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006214, 0x000703FFU ,0x000003FFU),
- // .. .. reg_arb_pri_rd_portn = 0x3ff
- // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_rd_portn = 0x0
- // .. .. ==> 0XF8006218[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. .. ==> 0XF8006218[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. .. ==> 0XF8006218[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_set_hpr_rd_portn = 0x0
- // .. .. ==> 0XF8006218[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
- // .. .. reg_arb_pri_rd_portn = 0x3ff
- // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_rd_portn = 0x0
- // .. .. ==> 0XF800621C[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. .. ==> 0XF800621C[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. .. ==> 0XF800621C[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_set_hpr_rd_portn = 0x0
- // .. .. ==> 0XF800621C[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
- // .. .. reg_arb_pri_rd_portn = 0x3ff
- // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_rd_portn = 0x0
- // .. .. ==> 0XF8006220[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. .. ==> 0XF8006220[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. .. ==> 0XF8006220[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_set_hpr_rd_portn = 0x0
- // .. .. ==> 0XF8006220[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
- // .. .. reg_arb_pri_rd_portn = 0x3ff
- // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_rd_portn = 0x0
- // .. .. ==> 0XF8006224[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. .. ==> 0XF8006224[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. .. ==> 0XF8006224[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_set_hpr_rd_portn = 0x0
- // .. .. ==> 0XF8006224[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
- // .. .. reg_ddrc_lpddr2 = 0x0
- // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_derate_enable = 0x0
- // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_ddrc_mr4_margin = 0x0
- // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U ,0x00000000U),
- // .. .. reg_ddrc_mr4_read_interval = 0x0
- // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
- // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
- // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U
- // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
- // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
- // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U
- // .. .. reg_ddrc_t_mrw = 0x5
- // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
- // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U
- // .. ..
- EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
- // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8
- // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U
- // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
- // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
- // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U
- // .. ..
- EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
- // .. .. START: POLL ON DCI STATUS
- // .. .. DONE = 1
- // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
- // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // .. ..
- EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
- // .. .. FINISH: POLL ON DCI STATUS
- // .. .. START: UNLOCK DDR
- // .. .. reg_ddrc_soft_rstb = 0x1
- // .. .. ==> 0XF8006000[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_ddrc_powerdown_en = 0x0
- // .. .. ==> 0XF8006000[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_ddrc_data_bus_width = 0x0
- // .. .. ==> 0XF8006000[3:2] = 0x00000000U
- // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U
- // .. .. reg_ddrc_burst8_refresh = 0x0
- // .. .. ==> 0XF8006000[6:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U
- // .. .. reg_ddrc_rdwr_idle_gap = 1
- // .. .. ==> 0XF8006000[13:7] = 0x00000001U
- // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U
- // .. .. reg_ddrc_dis_rd_bypass = 0x0
- // .. .. ==> 0XF8006000[14:14] = 0x00000000U
- // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_act_bypass = 0x0
- // .. .. ==> 0XF8006000[15:15] = 0x00000000U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_auto_refresh = 0x0
- // .. .. ==> 0XF8006000[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
- // .. .. FINISH: UNLOCK DDR
- // .. .. START: CHECK DDR STATUS
- // .. .. ddrc_reg_operating_mode = 1
- // .. .. ==> 0XF8006054[2:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U
- // .. ..
- EMIT_MASKPOLL(0XF8006054, 0x00000007U),
- // .. .. FINISH: CHECK DDR STATUS
- // .. FINISH: DDR INITIALIZATION
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_mio_init_data_3_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: OCM REMAPPING
- // .. VREF_EN = 0x1
- // .. ==> 0XF8000B00[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. VREF_SEL = 0x0
- // .. ==> 0XF8000B00[6:4] = 0x00000000U
- // .. ==> MASK : 0x00000070U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B00, 0x00000071U ,0x00000001U),
- // .. FINISH: OCM REMAPPING
- // .. START: DDRIOB SETTINGS
- // .. reserved_INP_POWER = 0x0
- // .. ==> 0XF8000B40[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x0
- // .. ==> 0XF8000B40[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. DCI_UPDATE_B = 0x0
- // .. ==> 0XF8000B40[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x0
- // .. ==> 0XF8000B40[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. DCI_TYPE = 0x0
- // .. ==> 0XF8000B40[6:5] = 0x00000000U
- // .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. IBUF_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B40[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B40[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B40[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B40[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
- // .. reserved_INP_POWER = 0x0
- // .. ==> 0XF8000B44[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x0
- // .. ==> 0XF8000B44[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. DCI_UPDATE_B = 0x0
- // .. ==> 0XF8000B44[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x0
- // .. ==> 0XF8000B44[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. DCI_TYPE = 0x0
- // .. ==> 0XF8000B44[6:5] = 0x00000000U
- // .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. IBUF_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B44[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B44[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B44[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B44[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
- // .. reserved_INP_POWER = 0x0
- // .. ==> 0XF8000B48[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x1
- // .. ==> 0XF8000B48[2:1] = 0x00000001U
- // .. ==> MASK : 0x00000006U VAL : 0x00000002U
- // .. DCI_UPDATE_B = 0x0
- // .. ==> 0XF8000B48[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x1
- // .. ==> 0XF8000B48[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. DCI_TYPE = 0x3
- // .. ==> 0XF8000B48[6:5] = 0x00000003U
- // .. ==> MASK : 0x00000060U VAL : 0x00000060U
- // .. IBUF_DISABLE_MODE = 0
- // .. ==> 0XF8000B48[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0
- // .. ==> 0XF8000B48[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B48[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B48[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
- // .. reserved_INP_POWER = 0x0
- // .. ==> 0XF8000B4C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x1
- // .. ==> 0XF8000B4C[2:1] = 0x00000001U
- // .. ==> MASK : 0x00000006U VAL : 0x00000002U
- // .. DCI_UPDATE_B = 0x0
- // .. ==> 0XF8000B4C[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x1
- // .. ==> 0XF8000B4C[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. DCI_TYPE = 0x3
- // .. ==> 0XF8000B4C[6:5] = 0x00000003U
- // .. ==> MASK : 0x00000060U VAL : 0x00000060U
- // .. IBUF_DISABLE_MODE = 0
- // .. ==> 0XF8000B4C[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0
- // .. ==> 0XF8000B4C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B4C[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B4C[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
- // .. reserved_INP_POWER = 0x0
- // .. ==> 0XF8000B50[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x2
- // .. ==> 0XF8000B50[2:1] = 0x00000002U
- // .. ==> MASK : 0x00000006U VAL : 0x00000004U
- // .. DCI_UPDATE_B = 0x0
- // .. ==> 0XF8000B50[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x1
- // .. ==> 0XF8000B50[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. DCI_TYPE = 0x3
- // .. ==> 0XF8000B50[6:5] = 0x00000003U
- // .. ==> MASK : 0x00000060U VAL : 0x00000060U
- // .. IBUF_DISABLE_MODE = 0
- // .. ==> 0XF8000B50[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0
- // .. ==> 0XF8000B50[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B50[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B50[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
- // .. reserved_INP_POWER = 0x0
- // .. ==> 0XF8000B54[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x2
- // .. ==> 0XF8000B54[2:1] = 0x00000002U
- // .. ==> MASK : 0x00000006U VAL : 0x00000004U
- // .. DCI_UPDATE_B = 0x0
- // .. ==> 0XF8000B54[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x1
- // .. ==> 0XF8000B54[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. DCI_TYPE = 0x3
- // .. ==> 0XF8000B54[6:5] = 0x00000003U
- // .. ==> MASK : 0x00000060U VAL : 0x00000060U
- // .. IBUF_DISABLE_MODE = 0
- // .. ==> 0XF8000B54[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0
- // .. ==> 0XF8000B54[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B54[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B54[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
- // .. reserved_INP_POWER = 0x0
- // .. ==> 0XF8000B58[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x0
- // .. ==> 0XF8000B58[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. DCI_UPDATE_B = 0x0
- // .. ==> 0XF8000B58[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x0
- // .. ==> 0XF8000B58[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. DCI_TYPE = 0x0
- // .. ==> 0XF8000B58[6:5] = 0x00000000U
- // .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. IBUF_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B58[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B58[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B58[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B58[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
- // .. reserved_DRIVE_P = 0x1c
- // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
- // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
- // .. reserved_DRIVE_N = 0xc
- // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
- // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
- // .. reserved_SLEW_P = 0x3
- // .. ==> 0XF8000B5C[18:14] = 0x00000003U
- // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U
- // .. reserved_SLEW_N = 0x3
- // .. ==> 0XF8000B5C[23:19] = 0x00000003U
- // .. ==> MASK : 0x00F80000U VAL : 0x00180000U
- // .. reserved_GTL = 0x0
- // .. ==> 0XF8000B5C[26:24] = 0x00000000U
- // .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. reserved_RTERM = 0x0
- // .. ==> 0XF8000B5C[31:27] = 0x00000000U
- // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
- // .. reserved_DRIVE_P = 0x1c
- // .. ==> 0XF8000B60[6:0] = 0x0000001CU
- // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
- // .. reserved_DRIVE_N = 0xc
- // .. ==> 0XF8000B60[13:7] = 0x0000000CU
- // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
- // .. reserved_SLEW_P = 0x6
- // .. ==> 0XF8000B60[18:14] = 0x00000006U
- // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
- // .. reserved_SLEW_N = 0x1f
- // .. ==> 0XF8000B60[23:19] = 0x0000001FU
- // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
- // .. reserved_GTL = 0x0
- // .. ==> 0XF8000B60[26:24] = 0x00000000U
- // .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. reserved_RTERM = 0x0
- // .. ==> 0XF8000B60[31:27] = 0x00000000U
- // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
- // .. reserved_DRIVE_P = 0x1c
- // .. ==> 0XF8000B64[6:0] = 0x0000001CU
- // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
- // .. reserved_DRIVE_N = 0xc
- // .. ==> 0XF8000B64[13:7] = 0x0000000CU
- // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
- // .. reserved_SLEW_P = 0x6
- // .. ==> 0XF8000B64[18:14] = 0x00000006U
- // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
- // .. reserved_SLEW_N = 0x1f
- // .. ==> 0XF8000B64[23:19] = 0x0000001FU
- // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
- // .. reserved_GTL = 0x0
- // .. ==> 0XF8000B64[26:24] = 0x00000000U
- // .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. reserved_RTERM = 0x0
- // .. ==> 0XF8000B64[31:27] = 0x00000000U
- // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
- // .. reserved_DRIVE_P = 0x1c
- // .. ==> 0XF8000B68[6:0] = 0x0000001CU
- // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
- // .. reserved_DRIVE_N = 0xc
- // .. ==> 0XF8000B68[13:7] = 0x0000000CU
- // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
- // .. reserved_SLEW_P = 0x6
- // .. ==> 0XF8000B68[18:14] = 0x00000006U
- // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
- // .. reserved_SLEW_N = 0x1f
- // .. ==> 0XF8000B68[23:19] = 0x0000001FU
- // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
- // .. reserved_GTL = 0x0
- // .. ==> 0XF8000B68[26:24] = 0x00000000U
- // .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. reserved_RTERM = 0x0
- // .. ==> 0XF8000B68[31:27] = 0x00000000U
- // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
- // .. VREF_INT_EN = 0x1
- // .. ==> 0XF8000B6C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. VREF_SEL = 0x4
- // .. ==> 0XF8000B6C[4:1] = 0x00000004U
- // .. ==> MASK : 0x0000001EU VAL : 0x00000008U
- // .. VREF_EXT_EN = 0x0
- // .. ==> 0XF8000B6C[6:5] = 0x00000000U
- // .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. reserved_VREF_PULLUP_EN = 0x0
- // .. ==> 0XF8000B6C[8:7] = 0x00000000U
- // .. ==> MASK : 0x00000180U VAL : 0x00000000U
- // .. REFIO_EN = 0x1
- // .. ==> 0XF8000B6C[9:9] = 0x00000001U
- // .. ==> MASK : 0x00000200U VAL : 0x00000200U
- // .. reserved_REFIO_TEST = 0x3
- // .. ==> 0XF8000B6C[11:10] = 0x00000003U
- // .. ==> MASK : 0x00000C00U VAL : 0x00000C00U
- // .. reserved_REFIO_PULLUP_EN = 0x0
- // .. ==> 0XF8000B6C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. reserved_DRST_B_PULLUP_EN = 0x0
- // .. ==> 0XF8000B6C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // .. reserved_CKE_PULLUP_EN = 0x0
- // .. ==> 0XF8000B6C[14:14] = 0x00000000U
- // .. ==> MASK : 0x00004000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000E09U),
- // .. .. START: ASSERT RESET
- // .. .. RESET = 1
- // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. ..
- EMIT_MASKWRITE(0XF8000B70, 0x00000001U ,0x00000001U),
- // .. .. FINISH: ASSERT RESET
- // .. .. START: DEASSERT RESET
- // .. .. RESET = 0
- // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reserved_VRN_OUT = 0x1
- // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
- // .. ..
- EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
- // .. .. FINISH: DEASSERT RESET
- // .. .. RESET = 0x1
- // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ENABLE = 0x1
- // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. .. reserved_VRP_TRI = 0x0
- // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reserved_VRN_TRI = 0x0
- // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reserved_VRP_OUT = 0x0
- // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. reserved_VRN_OUT = 0x1
- // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
- // .. .. NREF_OPT1 = 0x0
- // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
- // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U
- // .. .. NREF_OPT2 = 0x0
- // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U
- // .. .. NREF_OPT4 = 0x1
- // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
- // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U
- // .. .. PREF_OPT1 = 0x0
- // .. .. ==> 0XF8000B70[15:14] = 0x00000000U
- // .. .. ==> MASK : 0x0000C000U VAL : 0x00000000U
- // .. .. PREF_OPT2 = 0x0
- // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
- // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U
- // .. .. UPDATE_CONTROL = 0x0
- // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
- // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U
- // .. .. reserved_INIT_COMPLETE = 0x0
- // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
- // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U
- // .. .. reserved_TST_CLK = 0x0
- // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
- // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U
- // .. .. reserved_TST_HLN = 0x0
- // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
- // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U
- // .. .. reserved_TST_HLP = 0x0
- // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
- // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U
- // .. .. reserved_TST_RST = 0x0
- // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
- // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
- // .. .. reserved_INT_DCI_EN = 0x0
- // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
- // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU ,0x00000823U),
- // .. FINISH: DDRIOB SETTINGS
- // .. START: MIO PROGRAMMING
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000700[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. Speed = 0
- // .. ==> 0XF8000700[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000700[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 1
- // .. ==> 0XF8000700[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000700[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000700, 0x00003F01U ,0x00001201U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000704[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000704[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000704[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000704[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000704[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000704[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000704[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 1
- // .. ==> 0XF8000704[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000704[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001202U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000708[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000708[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000708[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000708[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000708[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000708[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000708[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000708[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000708[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000202U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800070C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF800070C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF800070C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800070C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800070C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800070C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF800070C[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF800070C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800070C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000202U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000710[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000710[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000710[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000710[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000710[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000710[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000710[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000710[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000710[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000202U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000714[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000714[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000714[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000714[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000714[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000714[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000714[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000714[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000714[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000202U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000718[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000718[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000718[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000718[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000718[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000718[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000718[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000718[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000718[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000202U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800071C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800071C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF800071C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800071C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800071C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800071C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF800071C[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF800071C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800071C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000200U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000720[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000720[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000720[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000720[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000720[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000720[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000720[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000720[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000720[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000202U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000724[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000724[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000724[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000724[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000724[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000724[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000724[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 1
- // .. ==> 0XF8000724[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000724[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001200U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000728[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000728[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000728[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000728[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000728[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000728[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000728[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 1
- // .. ==> 0XF8000728[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000728[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001200U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800072C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800072C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF800072C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800072C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800072C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800072C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF800072C[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 1
- // .. ==> 0XF800072C[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800072C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001200U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000730[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000730[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000730[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000730[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000730[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000730[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000730[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 1
- // .. ==> 0XF8000730[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000730[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001200U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000734[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000734[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000734[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000734[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000734[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000734[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000734[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 1
- // .. ==> 0XF8000734[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000734[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001200U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000738[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000738[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000738[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000738[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000738[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000738[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000738[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 1
- // .. ==> 0XF8000738[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000738[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00001200U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF800073C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. Speed = 0
- // .. ==> 0XF800073C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF800073C[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 1
- // .. ==> 0XF800073C[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800073C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800073C, 0x00003F01U ,0x00001201U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000740[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000740[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000740[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000740[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000740[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000740[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 4
- // .. ==> 0XF8000740[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000740[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 1
- // .. ==> 0XF8000740[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // ..
- EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00002802U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000744[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000744[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000744[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000744[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000744[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000744[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 4
- // .. ==> 0XF8000744[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000744[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 1
- // .. ==> 0XF8000744[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // ..
- EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00002802U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000748[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000748[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000748[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000748[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000748[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000748[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 4
- // .. ==> 0XF8000748[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000748[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 1
- // .. ==> 0XF8000748[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // ..
- EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00002802U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800074C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF800074C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF800074C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800074C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800074C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800074C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 4
- // .. ==> 0XF800074C[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF800074C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 1
- // .. ==> 0XF800074C[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // ..
- EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00002802U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000750[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000750[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000750[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000750[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000750[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000750[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 4
- // .. ==> 0XF8000750[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000750[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 1
- // .. ==> 0XF8000750[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // ..
- EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00002802U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000754[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000754[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000754[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000754[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000754[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000754[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 4
- // .. ==> 0XF8000754[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000754[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 1
- // .. ==> 0XF8000754[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // ..
- EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00002802U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000758[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF8000758[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000758[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000758[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000758[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000758[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 4
- // .. ==> 0XF8000758[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000758[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000758[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000803U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF800075C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF800075C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF800075C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800075C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800075C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800075C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 4
- // .. ==> 0XF800075C[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF800075C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800075C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000803U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000760[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF8000760[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000760[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000760[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000760[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000760[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 4
- // .. ==> 0XF8000760[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000760[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000760[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000803U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000764[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF8000764[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000764[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000764[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000764[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000764[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 4
- // .. ==> 0XF8000764[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000764[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000764[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000803U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000768[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF8000768[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000768[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000768[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000768[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000768[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 4
- // .. ==> 0XF8000768[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000768[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000768[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000803U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF800076C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF800076C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF800076C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800076C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800076C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800076C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 4
- // .. ==> 0XF800076C[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF800076C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800076C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000803U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000770[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000770[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000770[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000770[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000770[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000770[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000770[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000770[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000770[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000774[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF8000774[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000774[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000774[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000774[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000774[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000774[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000774[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000774[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000778[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000778[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000778[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000778[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000778[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000778[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000778[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000778[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000778[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF800077C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF800077C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF800077C[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF800077C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800077C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800077C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF800077C[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF800077C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800077C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000780[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000780[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000780[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000780[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000780[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000780[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000780[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000780[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000780[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000784[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000784[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000784[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000784[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000784[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000784[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000784[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000784[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000784[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000788[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000788[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000788[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000788[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000788[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000788[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000788[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000788[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000788[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800078C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800078C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF800078C[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF800078C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800078C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800078C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF800078C[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF800078C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800078C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000790[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF8000790[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000790[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000790[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000790[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000790[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000790[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000790[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000790[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000794[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000794[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000794[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000794[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000794[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000794[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000794[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000794[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000794[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000798[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000798[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000798[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000798[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000798[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000798[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000798[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000798[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000798[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800079C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800079C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF800079C[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF800079C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800079C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800079C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF800079C[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF800079C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800079C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007A0[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007A0[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007A0[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007A0[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007A0[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF80007A0[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007A0[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007A0[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007A0[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000280U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007A4[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007A4[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007A4[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007A4[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007A4[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF80007A4[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007A4[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007A4[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007A4[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000280U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007A8[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007A8[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007A8[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007A8[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007A8[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF80007A8[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007A8[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007A8[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007A8[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000280U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007AC[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007AC[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007AC[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007AC[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007AC[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF80007AC[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007AC[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007AC[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007AC[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000280U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007B0[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007B0[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007B0[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007B0[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007B0[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF80007B0[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007B0[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007B0[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007B0[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000280U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007B4[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007B4[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007B4[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007B4[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007B4[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF80007B4[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007B4[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007B4[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007B4[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000280U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF80007B8[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF80007B8[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007B8[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007B8[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 1
- // .. ==> 0XF80007B8[7:5] = 0x00000001U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000020U
- // .. Speed = 0
- // .. ==> 0XF80007B8[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007B8[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 1
- // .. ==> 0XF80007B8[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007B8[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001221U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007BC[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007BC[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007BC[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007BC[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 1
- // .. ==> 0XF80007BC[7:5] = 0x00000001U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000020U
- // .. Speed = 0
- // .. ==> 0XF80007BC[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007BC[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 1
- // .. ==> 0XF80007BC[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007BC[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00001220U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007C0[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007C0[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007C0[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007C0[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 7
- // .. ==> 0XF80007C0[7:5] = 0x00000007U
- // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U
- // .. Speed = 0
- // .. ==> 0XF80007C0[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007C0[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007C0[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007C0[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF80007C4[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF80007C4[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007C4[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007C4[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 7
- // .. ==> 0XF80007C4[7:5] = 0x00000007U
- // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U
- // .. Speed = 0
- // .. ==> 0XF80007C4[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007C4[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007C4[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007C4[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007C8[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007C8[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007C8[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007C8[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 2
- // .. ==> 0XF80007C8[7:5] = 0x00000002U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000040U
- // .. Speed = 0
- // .. ==> 0XF80007C8[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007C8[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 1
- // .. ==> 0XF80007C8[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007C8[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001240U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007CC[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007CC[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007CC[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007CC[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 2
- // .. ==> 0XF80007CC[7:5] = 0x00000002U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000040U
- // .. Speed = 0
- // .. ==> 0XF80007CC[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007CC[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 1
- // .. ==> 0XF80007CC[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007CC[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001240U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007D0[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007D0[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007D0[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007D0[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007D0[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF80007D0[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007D0[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007D0[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007D0[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007D4[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007D4[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007D4[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007D4[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007D4[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF80007D4[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007D4[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007D4[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007D4[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U),
- // .. SDIO0_WP_SEL = 15
- // .. ==> 0XF8000830[5:0] = 0x0000000FU
- // .. ==> MASK : 0x0000003FU VAL : 0x0000000FU
- // .. SDIO0_CD_SEL = 0
- // .. ==> 0XF8000830[21:16] = 0x00000000U
- // .. ==> MASK : 0x003F0000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x0000000FU),
- // .. FINISH: MIO PROGRAMMING
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_peripherals_init_data_3_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
- // .. IBUF_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B48[7:7] = 0x00000001U
- // .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. TERM_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B48[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // ..
- EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
- // .. IBUF_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B4C[7:7] = 0x00000001U
- // .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. TERM_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B4C[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // ..
- EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
- // .. IBUF_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B50[7:7] = 0x00000001U
- // .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. TERM_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B50[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // ..
- EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
- // .. IBUF_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B54[7:7] = 0x00000001U
- // .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. TERM_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B54[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // ..
- EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
- // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // .. START: SRAM/NOR SET OPMODE
- // .. FINISH: SRAM/NOR SET OPMODE
- // .. START: UART REGISTERS
- // .. BDIV = 0x6
- // .. ==> 0XE0001034[7:0] = 0x00000006U
- // .. ==> MASK : 0x000000FFU VAL : 0x00000006U
- // ..
- EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
- // .. CD = 0x3e
- // .. ==> 0XE0001018[15:0] = 0x0000003EU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU
- // ..
- EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
- // .. STPBRK = 0x0
- // .. ==> 0XE0001000[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. STTBRK = 0x0
- // .. ==> 0XE0001000[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. RSTTO = 0x0
- // .. ==> 0XE0001000[6:6] = 0x00000000U
- // .. ==> MASK : 0x00000040U VAL : 0x00000000U
- // .. TXDIS = 0x0
- // .. ==> 0XE0001000[5:5] = 0x00000000U
- // .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. TXEN = 0x1
- // .. ==> 0XE0001000[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. RXDIS = 0x0
- // .. ==> 0XE0001000[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. RXEN = 0x1
- // .. ==> 0XE0001000[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. TXRES = 0x1
- // .. ==> 0XE0001000[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. RXRES = 0x1
- // .. ==> 0XE0001000[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // ..
- EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
- // .. CHMODE = 0x0
- // .. ==> 0XE0001004[9:8] = 0x00000000U
- // .. ==> MASK : 0x00000300U VAL : 0x00000000U
- // .. NBSTOP = 0x0
- // .. ==> 0XE0001004[7:6] = 0x00000000U
- // .. ==> MASK : 0x000000C0U VAL : 0x00000000U
- // .. PAR = 0x4
- // .. ==> 0XE0001004[5:3] = 0x00000004U
- // .. ==> MASK : 0x00000038U VAL : 0x00000020U
- // .. CHRL = 0x0
- // .. ==> 0XE0001004[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. CLKS = 0x0
- // .. ==> 0XE0001004[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XE0001004, 0x000003FFU ,0x00000020U),
- // .. FINISH: UART REGISTERS
- // .. START: QSPI REGISTERS
- // .. Holdb_dr = 1
- // .. ==> 0XE000D000[19:19] = 0x00000001U
- // .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // ..
- EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
- // .. FINISH: QSPI REGISTERS
- // .. START: PL POWER ON RESET REGISTERS
- // .. PCFG_POR_CNT_4K = 0
- // .. ==> 0XF8007000[29:29] = 0x00000000U
- // .. ==> MASK : 0x20000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
- // .. FINISH: PL POWER ON RESET REGISTERS
- // .. START: SMC TIMING CALCULATION REGISTER UPDATE
- // .. .. START: NAND SET CYCLE
- // .. .. FINISH: NAND SET CYCLE
- // .. .. START: OPMODE
- // .. .. FINISH: OPMODE
- // .. .. START: DIRECT COMMAND
- // .. .. FINISH: DIRECT COMMAND
- // .. .. START: SRAM/NOR CS0 SET CYCLE
- // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
- // .. .. START: DIRECT COMMAND
- // .. .. FINISH: DIRECT COMMAND
- // .. .. START: NOR CS0 BASE ADDRESS
- // .. .. FINISH: NOR CS0 BASE ADDRESS
- // .. .. START: SRAM/NOR CS1 SET CYCLE
- // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
- // .. .. START: DIRECT COMMAND
- // .. .. FINISH: DIRECT COMMAND
- // .. .. START: NOR CS1 BASE ADDRESS
- // .. .. FINISH: NOR CS1 BASE ADDRESS
- // .. .. START: USB RESET
- // .. .. .. START: USB0 RESET
- // .. .. .. .. START: DIR MODE BANK 0
- // .. .. .. .. DIRECTION_0 = 0x80
- // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U
- // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U),
- // .. .. .. .. FINISH: DIR MODE BANK 0
- // .. .. .. .. START: DIR MODE BANK 1
- // .. .. .. .. FINISH: DIR MODE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. MASK_0_LSW = 0xff7f
- // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
- // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U
- // .. .. .. .. DATA_0_LSW = 0x80
- // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
- // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. START: OUTPUT ENABLE BANK 0
- // .. .. .. .. OP_ENABLE_0 = 0x80
- // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U
- // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U),
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
- // .. .. .. .. START: OUTPUT ENABLE BANK 1
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. MASK_0_LSW = 0xff7f
- // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
- // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U
- // .. .. .. .. DATA_0_LSW = 0x0
- // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
- // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U),
- // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. START: ADD 1 MS DELAY
- // .. .. .. ..
- EMIT_MASKDELAY(0XF8F00200, 1),
- // .. .. .. .. FINISH: ADD 1 MS DELAY
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. MASK_0_LSW = 0xff7f
- // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
- // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U
- // .. .. .. .. DATA_0_LSW = 0x80
- // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
- // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: USB0 RESET
- // .. .. .. START: USB1 RESET
- // .. .. .. .. START: DIR MODE BANK 0
- // .. .. .. .. FINISH: DIR MODE BANK 0
- // .. .. .. .. START: DIR MODE BANK 1
- // .. .. .. .. FINISH: DIR MODE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. START: OUTPUT ENABLE BANK 0
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
- // .. .. .. .. START: OUTPUT ENABLE BANK 1
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. START: ADD 1 MS DELAY
- // .. .. .. ..
- EMIT_MASKDELAY(0XF8F00200, 1),
- // .. .. .. .. FINISH: ADD 1 MS DELAY
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: USB1 RESET
- // .. .. FINISH: USB RESET
- // .. .. START: ENET RESET
- // .. .. .. START: ENET0 RESET
- // .. .. .. .. START: DIR MODE BANK 0
- // .. .. .. .. DIRECTION_0 = 0x800
- // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000800U
- // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000800U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000800U),
- // .. .. .. .. FINISH: DIR MODE BANK 0
- // .. .. .. .. START: DIR MODE BANK 1
- // .. .. .. .. FINISH: DIR MODE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. MASK_0_LSW = 0xf7ff
- // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU
- // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xF7FF0000U
- // .. .. .. .. DATA_0_LSW = 0x800
- // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000800U
- // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000800U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0800U),
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. START: OUTPUT ENABLE BANK 0
- // .. .. .. .. OP_ENABLE_0 = 0x800
- // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000800U
- // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000800U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000800U),
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
- // .. .. .. .. START: OUTPUT ENABLE BANK 1
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. MASK_0_LSW = 0xf7ff
- // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU
- // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xF7FF0000U
- // .. .. .. .. DATA_0_LSW = 0x0
- // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
- // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0000U),
- // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. START: ADD 1 MS DELAY
- // .. .. .. ..
- EMIT_MASKDELAY(0XF8F00200, 1),
- // .. .. .. .. FINISH: ADD 1 MS DELAY
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. MASK_0_LSW = 0xf7ff
- // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU
- // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xF7FF0000U
- // .. .. .. .. DATA_0_LSW = 0x800
- // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000800U
- // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000800U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0800U),
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: ENET0 RESET
- // .. .. .. START: ENET1 RESET
- // .. .. .. .. START: DIR MODE BANK 0
- // .. .. .. .. FINISH: DIR MODE BANK 0
- // .. .. .. .. START: DIR MODE BANK 1
- // .. .. .. .. FINISH: DIR MODE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. START: OUTPUT ENABLE BANK 0
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
- // .. .. .. .. START: OUTPUT ENABLE BANK 1
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. START: ADD 1 MS DELAY
- // .. .. .. ..
- EMIT_MASKDELAY(0XF8F00200, 1),
- // .. .. .. .. FINISH: ADD 1 MS DELAY
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: ENET1 RESET
- // .. .. FINISH: ENET RESET
- // .. .. START: I2C RESET
- // .. .. .. START: I2C0 RESET
- // .. .. .. .. START: DIR MODE GPIO BANK0
- // .. .. .. .. DIRECTION_0 = 0x2000
- // .. .. .. .. ==> 0XE000A204[31:0] = 0x00002000U
- // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002000U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002000U),
- // .. .. .. .. FINISH: DIR MODE GPIO BANK0
- // .. .. .. .. START: DIR MODE GPIO BANK1
- // .. .. .. .. FINISH: DIR MODE GPIO BANK1
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. MASK_0_LSW = 0xdfff
- // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU
- // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xDFFF0000U
- // .. .. .. .. DATA_0_LSW = 0x2000
- // .. .. .. .. ==> 0XE000A000[15:0] = 0x00002000U
- // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00002000U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF2000U),
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. START: OUTPUT ENABLE
- // .. .. .. .. OP_ENABLE_0 = 0x2000
- // .. .. .. .. ==> 0XE000A208[31:0] = 0x00002000U
- // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002000U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002000U),
- // .. .. .. .. FINISH: OUTPUT ENABLE
- // .. .. .. .. START: OUTPUT ENABLE
- // .. .. .. .. FINISH: OUTPUT ENABLE
- // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. MASK_0_LSW = 0xdfff
- // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU
- // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xDFFF0000U
- // .. .. .. .. DATA_0_LSW = 0x0
- // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
- // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF0000U),
- // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. START: ADD 1 MS DELAY
- // .. .. .. ..
- EMIT_MASKDELAY(0XF8F00200, 1),
- // .. .. .. .. FINISH: ADD 1 MS DELAY
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. MASK_0_LSW = 0xdfff
- // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU
- // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xDFFF0000U
- // .. .. .. .. DATA_0_LSW = 0x2000
- // .. .. .. .. ==> 0XE000A000[15:0] = 0x00002000U
- // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00002000U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF2000U),
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: I2C0 RESET
- // .. .. .. START: I2C1 RESET
- // .. .. .. .. START: DIR MODE GPIO BANK0
- // .. .. .. .. FINISH: DIR MODE GPIO BANK0
- // .. .. .. .. START: DIR MODE GPIO BANK1
- // .. .. .. .. FINISH: DIR MODE GPIO BANK1
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. START: OUTPUT ENABLE
- // .. .. .. .. FINISH: OUTPUT ENABLE
- // .. .. .. .. START: OUTPUT ENABLE
- // .. .. .. .. FINISH: OUTPUT ENABLE
- // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. START: ADD 1 MS DELAY
- // .. .. .. ..
- EMIT_MASKDELAY(0XF8F00200, 1),
- // .. .. .. .. FINISH: ADD 1 MS DELAY
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: I2C1 RESET
- // .. .. FINISH: I2C RESET
- // .. .. START: NOR CHIP SELECT
- // .. .. .. START: DIR MODE BANK 0
- // .. .. .. FINISH: DIR MODE BANK 0
- // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. START: OUTPUT ENABLE BANK 0
- // .. .. .. FINISH: OUTPUT ENABLE BANK 0
- // .. .. FINISH: NOR CHIP SELECT
- // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_post_config_3_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: ENABLING LEVEL SHIFTER
- // .. USER_LVL_INP_EN_0 = 1
- // .. ==> 0XF8000900[3:3] = 0x00000001U
- // .. ==> MASK : 0x00000008U VAL : 0x00000008U
- // .. USER_LVL_OUT_EN_0 = 1
- // .. ==> 0XF8000900[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. USER_LVL_INP_EN_1 = 1
- // .. ==> 0XF8000900[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. USER_LVL_OUT_EN_1 = 1
- // .. ==> 0XF8000900[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // ..
- EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
- // .. FINISH: ENABLING LEVEL SHIFTER
- // .. START: FPGA RESETS TO 0
- // .. reserved_3 = 0
- // .. ==> 0XF8000240[31:25] = 0x00000000U
- // .. ==> MASK : 0xFE000000U VAL : 0x00000000U
- // .. reserved_FPGA_ACP_RST = 0
- // .. ==> 0XF8000240[24:24] = 0x00000000U
- // .. ==> MASK : 0x01000000U VAL : 0x00000000U
- // .. reserved_FPGA_AXDS3_RST = 0
- // .. ==> 0XF8000240[23:23] = 0x00000000U
- // .. ==> MASK : 0x00800000U VAL : 0x00000000U
- // .. reserved_FPGA_AXDS2_RST = 0
- // .. ==> 0XF8000240[22:22] = 0x00000000U
- // .. ==> MASK : 0x00400000U VAL : 0x00000000U
- // .. reserved_FPGA_AXDS1_RST = 0
- // .. ==> 0XF8000240[21:21] = 0x00000000U
- // .. ==> MASK : 0x00200000U VAL : 0x00000000U
- // .. reserved_FPGA_AXDS0_RST = 0
- // .. ==> 0XF8000240[20:20] = 0x00000000U
- // .. ==> MASK : 0x00100000U VAL : 0x00000000U
- // .. reserved_2 = 0
- // .. ==> 0XF8000240[19:18] = 0x00000000U
- // .. ==> MASK : 0x000C0000U VAL : 0x00000000U
- // .. reserved_FSSW1_FPGA_RST = 0
- // .. ==> 0XF8000240[17:17] = 0x00000000U
- // .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. reserved_FSSW0_FPGA_RST = 0
- // .. ==> 0XF8000240[16:16] = 0x00000000U
- // .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. reserved_1 = 0
- // .. ==> 0XF8000240[15:14] = 0x00000000U
- // .. ==> MASK : 0x0000C000U VAL : 0x00000000U
- // .. reserved_FPGA_FMSW1_RST = 0
- // .. ==> 0XF8000240[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // .. reserved_FPGA_FMSW0_RST = 0
- // .. ==> 0XF8000240[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. reserved_FPGA_DMA3_RST = 0
- // .. ==> 0XF8000240[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. reserved_FPGA_DMA2_RST = 0
- // .. ==> 0XF8000240[10:10] = 0x00000000U
- // .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. reserved_FPGA_DMA1_RST = 0
- // .. ==> 0XF8000240[9:9] = 0x00000000U
- // .. ==> MASK : 0x00000200U VAL : 0x00000000U
- // .. reserved_FPGA_DMA0_RST = 0
- // .. ==> 0XF8000240[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. reserved = 0
- // .. ==> 0XF8000240[7:4] = 0x00000000U
- // .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. FPGA3_OUT_RST = 0
- // .. ==> 0XF8000240[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. FPGA2_OUT_RST = 0
- // .. ==> 0XF8000240[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. FPGA1_OUT_RST = 0
- // .. ==> 0XF8000240[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. FPGA0_OUT_RST = 0
- // .. ==> 0XF8000240[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
- // .. FINISH: FPGA RESETS TO 0
- // .. START: AFI REGISTERS
- // .. .. START: AFI0 REGISTERS
- // .. .. FINISH: AFI0 REGISTERS
- // .. .. START: AFI1 REGISTERS
- // .. .. FINISH: AFI1 REGISTERS
- // .. .. START: AFI2 REGISTERS
- // .. .. FINISH: AFI2 REGISTERS
- // .. .. START: AFI3 REGISTERS
- // .. .. FINISH: AFI3 REGISTERS
- // .. FINISH: AFI REGISTERS
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_debug_3_0[] = {
- // START: top
- // .. START: CROSS TRIGGER CONFIGURATIONS
- // .. .. START: UNLOCKING CTI REGISTERS
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. FINISH: UNLOCKING CTI REGISTERS
- // .. .. START: ENABLING CTI MODULES AND CHANNELS
- // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
- // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. FINISH: CROSS TRIGGER CONFIGURATIONS
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_pll_init_data_2_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: PLL SLCR REGISTERS
- // .. .. START: ARM PLL INIT
- // .. .. PLL_RES = 0x2
- // .. .. ==> 0XF8000110[7:4] = 0x00000002U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
- // .. .. PLL_CP = 0x2
- // .. .. ==> 0XF8000110[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. LOCK_CNT = 0xfa
- // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
- // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U
- // .. ..
- EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
- // .. .. .. START: UPDATE FB_DIV
- // .. .. .. PLL_FDIV = 0x28
- // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
- // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
- // .. .. .. FINISH: UPDATE FB_DIV
- // .. .. .. START: BY PASS PLL
- // .. .. .. PLL_BYPASS_FORCE = 1
- // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
- // .. .. .. FINISH: BY PASS PLL
- // .. .. .. START: ASSERT RESET
- // .. .. .. PLL_RESET = 1
- // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
- // .. .. .. FINISH: ASSERT RESET
- // .. .. .. START: DEASSERT RESET
- // .. .. .. PLL_RESET = 0
- // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
- // .. .. .. FINISH: DEASSERT RESET
- // .. .. .. START: CHECK PLL STATUS
- // .. .. .. ARM_PLL_LOCK = 1
- // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ..
- EMIT_MASKPOLL(0XF800010C, 0x00000001U),
- // .. .. .. FINISH: CHECK PLL STATUS
- // .. .. .. START: REMOVE PLL BY PASS
- // .. .. .. PLL_BYPASS_FORCE = 0
- // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
- // .. .. .. FINISH: REMOVE PLL BY PASS
- // .. .. .. SRCSEL = 0x0
- // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. .. .. DIVISOR = 0x2
- // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
- // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U
- // .. .. .. CPU_6OR4XCLKACT = 0x1
- // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
- // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U
- // .. .. .. CPU_3OR2XCLKACT = 0x1
- // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
- // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U
- // .. .. .. CPU_2XCLKACT = 0x1
- // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
- // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U
- // .. .. .. CPU_1XCLKACT = 0x1
- // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
- // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U
- // .. .. .. CPU_PERI_CLKACT = 0x1
- // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
- // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
- // .. .. FINISH: ARM PLL INIT
- // .. .. START: DDR PLL INIT
- // .. .. PLL_RES = 0x2
- // .. .. ==> 0XF8000114[7:4] = 0x00000002U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
- // .. .. PLL_CP = 0x2
- // .. .. ==> 0XF8000114[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. LOCK_CNT = 0x12c
- // .. .. ==> 0XF8000114[21:12] = 0x0000012CU
- // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U
- // .. ..
- EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
- // .. .. .. START: UPDATE FB_DIV
- // .. .. .. PLL_FDIV = 0x20
- // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
- // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
- // .. .. .. FINISH: UPDATE FB_DIV
- // .. .. .. START: BY PASS PLL
- // .. .. .. PLL_BYPASS_FORCE = 1
- // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
- // .. .. .. FINISH: BY PASS PLL
- // .. .. .. START: ASSERT RESET
- // .. .. .. PLL_RESET = 1
- // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
- // .. .. .. FINISH: ASSERT RESET
- // .. .. .. START: DEASSERT RESET
- // .. .. .. PLL_RESET = 0
- // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
- // .. .. .. FINISH: DEASSERT RESET
- // .. .. .. START: CHECK PLL STATUS
- // .. .. .. DDR_PLL_LOCK = 1
- // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. .. ..
- EMIT_MASKPOLL(0XF800010C, 0x00000002U),
- // .. .. .. FINISH: CHECK PLL STATUS
- // .. .. .. START: REMOVE PLL BY PASS
- // .. .. .. PLL_BYPASS_FORCE = 0
- // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
- // .. .. .. FINISH: REMOVE PLL BY PASS
- // .. .. .. DDR_3XCLKACT = 0x1
- // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. .. DDR_2XCLKACT = 0x1
- // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. .. .. DDR_3XCLK_DIVISOR = 0x2
- // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
- // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U
- // .. .. .. DDR_2XCLK_DIVISOR = 0x3
- // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
- // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
- // .. .. FINISH: DDR PLL INIT
- // .. .. START: IO PLL INIT
- // .. .. PLL_RES = 0xc
- // .. .. ==> 0XF8000118[7:4] = 0x0000000CU
- // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U
- // .. .. PLL_CP = 0x2
- // .. .. ==> 0XF8000118[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. LOCK_CNT = 0x145
- // .. .. ==> 0XF8000118[21:12] = 0x00000145U
- // .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U
- // .. ..
- EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U),
- // .. .. .. START: UPDATE FB_DIV
- // .. .. .. PLL_FDIV = 0x1e
- // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU
- // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U),
- // .. .. .. FINISH: UPDATE FB_DIV
- // .. .. .. START: BY PASS PLL
- // .. .. .. PLL_BYPASS_FORCE = 1
- // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
- // .. .. .. FINISH: BY PASS PLL
- // .. .. .. START: ASSERT RESET
- // .. .. .. PLL_RESET = 1
- // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
- // .. .. .. FINISH: ASSERT RESET
- // .. .. .. START: DEASSERT RESET
- // .. .. .. PLL_RESET = 0
- // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
- // .. .. .. FINISH: DEASSERT RESET
- // .. .. .. START: CHECK PLL STATUS
- // .. .. .. IO_PLL_LOCK = 1
- // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. .. ..
- EMIT_MASKPOLL(0XF800010C, 0x00000004U),
- // .. .. .. FINISH: CHECK PLL STATUS
- // .. .. .. START: REMOVE PLL BY PASS
- // .. .. .. PLL_BYPASS_FORCE = 0
- // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
- // .. .. .. FINISH: REMOVE PLL BY PASS
- // .. .. FINISH: IO PLL INIT
- // .. FINISH: PLL SLCR REGISTERS
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_clock_init_data_2_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: CLOCK CONTROL SLCR REGISTERS
- // .. CLKACT = 0x1
- // .. ==> 0XF8000128[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. DIVISOR0 = 0x23
- // .. ==> 0XF8000128[13:8] = 0x00000023U
- // .. ==> MASK : 0x00003F00U VAL : 0x00002300U
- // .. DIVISOR1 = 0x3
- // .. ==> 0XF8000128[25:20] = 0x00000003U
- // .. ==> MASK : 0x03F00000U VAL : 0x00300000U
- // ..
- EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U),
- // .. CLKACT = 0x1
- // .. ==> 0XF8000138[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000138[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
- // .. CLKACT = 0x1
- // .. ==> 0XF8000140[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000140[6:4] = 0x00000000U
- // .. ==> MASK : 0x00000070U VAL : 0x00000000U
- // .. DIVISOR = 0x8
- // .. ==> 0XF8000140[13:8] = 0x00000008U
- // .. ==> MASK : 0x00003F00U VAL : 0x00000800U
- // .. DIVISOR1 = 0x5
- // .. ==> 0XF8000140[25:20] = 0x00000005U
- // .. ==> MASK : 0x03F00000U VAL : 0x00500000U
- // ..
- EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00500801U),
- // .. CLKACT = 0x1
- // .. ==> 0XF800014C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. SRCSEL = 0x0
- // .. ==> 0XF800014C[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR = 0x5
- // .. ==> 0XF800014C[13:8] = 0x00000005U
- // .. ==> MASK : 0x00003F00U VAL : 0x00000500U
- // ..
- EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
- // .. CLKACT0 = 0x1
- // .. ==> 0XF8000150[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. CLKACT1 = 0x0
- // .. ==> 0XF8000150[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000150[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR = 0x14
- // .. ==> 0XF8000150[13:8] = 0x00000014U
- // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
- // ..
- EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U),
- // .. CLKACT0 = 0x0
- // .. ==> 0XF8000154[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. CLKACT1 = 0x1
- // .. ==> 0XF8000154[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000154[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR = 0x14
- // .. ==> 0XF8000154[13:8] = 0x00000014U
- // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
- // ..
- EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U),
- // .. CLKACT0 = 0x1
- // .. ==> 0XF800015C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. CLKACT1 = 0x0
- // .. ==> 0XF800015C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. SRCSEL = 0x0
- // .. ==> 0XF800015C[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR0 = 0xe
- // .. ==> 0XF800015C[13:8] = 0x0000000EU
- // .. ==> MASK : 0x00003F00U VAL : 0x00000E00U
- // .. DIVISOR1 = 0x3
- // .. ==> 0XF800015C[25:20] = 0x00000003U
- // .. ==> MASK : 0x03F00000U VAL : 0x00300000U
- // ..
- EMIT_MASKWRITE(0XF800015C, 0x03F03F33U ,0x00300E01U),
- // .. CAN0_MUX = 0x0
- // .. ==> 0XF8000160[5:0] = 0x00000000U
- // .. ==> MASK : 0x0000003FU VAL : 0x00000000U
- // .. CAN0_REF_SEL = 0x0
- // .. ==> 0XF8000160[6:6] = 0x00000000U
- // .. ==> MASK : 0x00000040U VAL : 0x00000000U
- // .. CAN1_MUX = 0x0
- // .. ==> 0XF8000160[21:16] = 0x00000000U
- // .. ==> MASK : 0x003F0000U VAL : 0x00000000U
- // .. CAN1_REF_SEL = 0x0
- // .. ==> 0XF8000160[22:22] = 0x00000000U
- // .. ==> MASK : 0x00400000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000160, 0x007F007FU ,0x00000000U),
- // .. CLKACT = 0x1
- // .. ==> 0XF8000168[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000168[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR = 0x5
- // .. ==> 0XF8000168[13:8] = 0x00000005U
- // .. ==> MASK : 0x00003F00U VAL : 0x00000500U
- // ..
- EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000170[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR0 = 0x14
- // .. ==> 0XF8000170[13:8] = 0x00000014U
- // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
- // .. DIVISOR1 = 0x1
- // .. ==> 0XF8000170[25:20] = 0x00000001U
- // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
- // ..
- EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00101400U),
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000180[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR0 = 0x14
- // .. ==> 0XF8000180[13:8] = 0x00000014U
- // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
- // .. DIVISOR1 = 0x1
- // .. ==> 0XF8000180[25:20] = 0x00000001U
- // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
- // ..
- EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00101400U),
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000190[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR0 = 0x14
- // .. ==> 0XF8000190[13:8] = 0x00000014U
- // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
- // .. DIVISOR1 = 0x1
- // .. ==> 0XF8000190[25:20] = 0x00000001U
- // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
- // ..
- EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101400U),
- // .. SRCSEL = 0x0
- // .. ==> 0XF80001A0[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR0 = 0x14
- // .. ==> 0XF80001A0[13:8] = 0x00000014U
- // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
- // .. DIVISOR1 = 0x1
- // .. ==> 0XF80001A0[25:20] = 0x00000001U
- // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
- // ..
- EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U),
- // .. CLK_621_TRUE = 0x1
- // .. ==> 0XF80001C4[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // ..
- EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
- // .. DMA_CPU_2XCLKACT = 0x1
- // .. ==> 0XF800012C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. USB0_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. USB1_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[3:3] = 0x00000001U
- // .. ==> MASK : 0x00000008U VAL : 0x00000008U
- // .. GEM0_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[6:6] = 0x00000001U
- // .. ==> MASK : 0x00000040U VAL : 0x00000040U
- // .. GEM1_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. SDI0_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[10:10] = 0x00000001U
- // .. ==> MASK : 0x00000400U VAL : 0x00000400U
- // .. SDI1_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. SPI0_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[14:14] = 0x00000000U
- // .. ==> MASK : 0x00004000U VAL : 0x00000000U
- // .. SPI1_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[15:15] = 0x00000000U
- // .. ==> MASK : 0x00008000U VAL : 0x00000000U
- // .. CAN0_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[16:16] = 0x00000001U
- // .. ==> MASK : 0x00010000U VAL : 0x00010000U
- // .. CAN1_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[17:17] = 0x00000000U
- // .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. I2C0_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[18:18] = 0x00000001U
- // .. ==> MASK : 0x00040000U VAL : 0x00040000U
- // .. I2C1_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[19:19] = 0x00000001U
- // .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // .. UART0_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[20:20] = 0x00000000U
- // .. ==> MASK : 0x00100000U VAL : 0x00000000U
- // .. UART1_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[21:21] = 0x00000001U
- // .. ==> MASK : 0x00200000U VAL : 0x00200000U
- // .. GPIO_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[22:22] = 0x00000001U
- // .. ==> MASK : 0x00400000U VAL : 0x00400000U
- // .. LQSPI_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[23:23] = 0x00000001U
- // .. ==> MASK : 0x00800000U VAL : 0x00800000U
- // .. SMC_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[24:24] = 0x00000001U
- // .. ==> MASK : 0x01000000U VAL : 0x01000000U
- // ..
- EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01ED044DU),
- // .. FINISH: CLOCK CONTROL SLCR REGISTERS
- // .. START: THIS SHOULD BE BLANK
- // .. FINISH: THIS SHOULD BE BLANK
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_ddr_init_data_2_0[] = {
- // START: top
- // .. START: DDR INITIALIZATION
- // .. .. START: LOCK DDR
- // .. .. reg_ddrc_soft_rstb = 0
- // .. .. ==> 0XF8006000[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_powerdown_en = 0x0
- // .. .. ==> 0XF8006000[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_ddrc_data_bus_width = 0x0
- // .. .. ==> 0XF8006000[3:2] = 0x00000000U
- // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U
- // .. .. reg_ddrc_burst8_refresh = 0x0
- // .. .. ==> 0XF8006000[6:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U
- // .. .. reg_ddrc_rdwr_idle_gap = 0x1
- // .. .. ==> 0XF8006000[13:7] = 0x00000001U
- // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U
- // .. .. reg_ddrc_dis_rd_bypass = 0x0
- // .. .. ==> 0XF8006000[14:14] = 0x00000000U
- // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_act_bypass = 0x0
- // .. .. ==> 0XF8006000[15:15] = 0x00000000U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_auto_refresh = 0x0
- // .. .. ==> 0XF8006000[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
- // .. .. FINISH: LOCK DDR
- // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81
- // .. .. ==> 0XF8006004[11:0] = 0x00000081U
- // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U
- // .. .. reg_ddrc_active_ranks = 0x1
- // .. .. ==> 0XF8006004[13:12] = 0x00000001U
- // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U
- // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
- // .. .. ==> 0XF8006004[18:14] = 0x00000000U
- // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U
- // .. .. reg_ddrc_wr_odt_block = 0x1
- // .. .. ==> 0XF8006004[20:19] = 0x00000001U
- // .. .. ==> MASK : 0x00180000U VAL : 0x00080000U
- // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0
- // .. .. ==> 0XF8006004[21:21] = 0x00000000U
- // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0
- // .. .. ==> 0XF8006004[26:22] = 0x00000000U
- // .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_open_bank = 0x0
- // .. .. ==> 0XF8006004[27:27] = 0x00000000U
- // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_4bank_ram = 0x0
- // .. .. ==> 0XF8006004[28:28] = 0x00000000U
- // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U),
- // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
- // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
- // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU
- // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
- // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
- // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U
- // .. .. reg_ddrc_hpr_xact_run_length = 0xf
- // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
- // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U
- // .. ..
- EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
- // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
- // .. .. ==> 0XF800600C[10:0] = 0x00000001U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U
- // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
- // .. .. ==> 0XF800600C[21:11] = 0x00000002U
- // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U
- // .. .. reg_ddrc_lpr_xact_run_length = 0x8
- // .. .. ==> 0XF800600C[25:22] = 0x00000008U
- // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U
- // .. ..
- EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
- // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
- // .. .. ==> 0XF8006010[10:0] = 0x00000001U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U
- // .. .. reg_ddrc_w_xact_run_length = 0x8
- // .. .. ==> 0XF8006010[14:11] = 0x00000008U
- // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U
- // .. .. reg_ddrc_w_max_starve_x32 = 0x2
- // .. .. ==> 0XF8006010[25:15] = 0x00000002U
- // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U
- // .. ..
- EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
- // .. .. reg_ddrc_t_rc = 0x1b
- // .. .. ==> 0XF8006014[5:0] = 0x0000001BU
- // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001BU
- // .. .. reg_ddrc_t_rfc_min = 0x56
- // .. .. ==> 0XF8006014[13:6] = 0x00000056U
- // .. .. ==> MASK : 0x00003FC0U VAL : 0x00001580U
- // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
- // .. .. ==> 0XF8006014[20:14] = 0x00000010U
- // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U
- // .. ..
- EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004159BU),
- // .. .. reg_ddrc_wr2pre = 0x12
- // .. .. ==> 0XF8006018[4:0] = 0x00000012U
- // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U
- // .. .. reg_ddrc_powerdown_to_x32 = 0x6
- // .. .. ==> 0XF8006018[9:5] = 0x00000006U
- // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U
- // .. .. reg_ddrc_t_faw = 0x10
- // .. .. ==> 0XF8006018[15:10] = 0x00000010U
- // .. .. ==> MASK : 0x0000FC00U VAL : 0x00004000U
- // .. .. reg_ddrc_t_ras_max = 0x24
- // .. .. ==> 0XF8006018[21:16] = 0x00000024U
- // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U
- // .. .. reg_ddrc_t_ras_min = 0x14
- // .. .. ==> 0XF8006018[26:22] = 0x00000014U
- // .. .. ==> MASK : 0x07C00000U VAL : 0x05000000U
- // .. .. reg_ddrc_t_cke = 0x4
- // .. .. ==> 0XF8006018[31:28] = 0x00000004U
- // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x452440D2U),
- // .. .. reg_ddrc_write_latency = 0x5
- // .. .. ==> 0XF800601C[4:0] = 0x00000005U
- // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U
- // .. .. reg_ddrc_rd2wr = 0x7
- // .. .. ==> 0XF800601C[9:5] = 0x00000007U
- // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U
- // .. .. reg_ddrc_wr2rd = 0xe
- // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
- // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U
- // .. .. reg_ddrc_t_xp = 0x4
- // .. .. ==> 0XF800601C[19:15] = 0x00000004U
- // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U
- // .. .. reg_ddrc_pad_pd = 0x0
- // .. .. ==> 0XF800601C[22:20] = 0x00000000U
- // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U
- // .. .. reg_ddrc_rd2pre = 0x4
- // .. .. ==> 0XF800601C[27:23] = 0x00000004U
- // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U
- // .. .. reg_ddrc_t_rcd = 0x7
- // .. .. ==> 0XF800601C[31:28] = 0x00000007U
- // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U
- // .. ..
- EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
- // .. .. reg_ddrc_t_ccd = 0x4
- // .. .. ==> 0XF8006020[4:2] = 0x00000004U
- // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U
- // .. .. reg_ddrc_t_rrd = 0x4
- // .. .. ==> 0XF8006020[7:5] = 0x00000004U
- // .. .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. .. reg_ddrc_refresh_margin = 0x2
- // .. .. ==> 0XF8006020[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. reg_ddrc_t_rp = 0x7
- // .. .. ==> 0XF8006020[15:12] = 0x00000007U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U
- // .. .. reg_ddrc_refresh_to_x32 = 0x8
- // .. .. ==> 0XF8006020[20:16] = 0x00000008U
- // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U
- // .. .. reg_ddrc_sdram = 0x1
- // .. .. ==> 0XF8006020[21:21] = 0x00000001U
- // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U
- // .. .. reg_ddrc_mobile = 0x0
- // .. .. ==> 0XF8006020[22:22] = 0x00000000U
- // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U
- // .. .. reg_ddrc_clock_stop_en = 0x0
- // .. .. ==> 0XF8006020[23:23] = 0x00000000U
- // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U
- // .. .. reg_ddrc_read_latency = 0x7
- // .. .. ==> 0XF8006020[28:24] = 0x00000007U
- // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U
- // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
- // .. .. ==> 0XF8006020[29:29] = 0x00000001U
- // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U
- // .. .. reg_ddrc_dis_pad_pd = 0x0
- // .. .. ==> 0XF8006020[30:30] = 0x00000000U
- // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U
- // .. .. reg_ddrc_loopback = 0x0
- // .. .. ==> 0XF8006020[31:31] = 0x00000000U
- // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x27287290U),
- // .. .. reg_ddrc_en_2t_timing_mode = 0x0
- // .. .. ==> 0XF8006024[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_prefer_write = 0x0
- // .. .. ==> 0XF8006024[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_ddrc_max_rank_rd = 0xf
- // .. .. ==> 0XF8006024[5:2] = 0x0000000FU
- // .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU
- // .. .. reg_ddrc_mr_wr = 0x0
- // .. .. ==> 0XF8006024[6:6] = 0x00000000U
- // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_addr = 0x0
- // .. .. ==> 0XF8006024[8:7] = 0x00000000U
- // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_data = 0x0
- // .. .. ==> 0XF8006024[24:9] = 0x00000000U
- // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U
- // .. .. ddrc_reg_mr_wr_busy = 0x0
- // .. .. ==> 0XF8006024[25:25] = 0x00000000U
- // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_type = 0x0
- // .. .. ==> 0XF8006024[26:26] = 0x00000000U
- // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_rdata_valid = 0x0
- // .. .. ==> 0XF8006024[27:27] = 0x00000000U
- // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU),
- // .. .. reg_ddrc_final_wait_x32 = 0x7
- // .. .. ==> 0XF8006028[6:0] = 0x00000007U
- // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U
- // .. .. reg_ddrc_pre_ocd_x32 = 0x0
- // .. .. ==> 0XF8006028[10:7] = 0x00000000U
- // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U
- // .. .. reg_ddrc_t_mrd = 0x4
- // .. .. ==> 0XF8006028[13:11] = 0x00000004U
- // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U
- // .. ..
- EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
- // .. .. reg_ddrc_emr2 = 0x8
- // .. .. ==> 0XF800602C[15:0] = 0x00000008U
- // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U
- // .. .. reg_ddrc_emr3 = 0x0
- // .. .. ==> 0XF800602C[31:16] = 0x00000000U
- // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
- // .. .. reg_ddrc_mr = 0x930
- // .. .. ==> 0XF8006030[15:0] = 0x00000930U
- // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U
- // .. .. reg_ddrc_emr = 0x4
- // .. .. ==> 0XF8006030[31:16] = 0x00000004U
- // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U
- // .. ..
- EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
- // .. .. reg_ddrc_burst_rdwr = 0x4
- // .. .. ==> 0XF8006034[3:0] = 0x00000004U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U
- // .. .. reg_ddrc_pre_cke_x1024 = 0x105
- // .. .. ==> 0XF8006034[13:4] = 0x00000105U
- // .. .. ==> MASK : 0x00003FF0U VAL : 0x00001050U
- // .. .. reg_ddrc_post_cke_x1024 = 0x1
- // .. .. ==> 0XF8006034[25:16] = 0x00000001U
- // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U
- // .. .. reg_ddrc_burstchop = 0x0
- // .. .. ==> 0XF8006034[28:28] = 0x00000000U
- // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U),
- // .. .. reg_ddrc_force_low_pri_n = 0x0
- // .. .. ==> 0XF8006038[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_dq = 0x0
- // .. .. ==> 0XF8006038[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_debug_mode = 0x0
- // .. .. ==> 0XF8006038[6:6] = 0x00000000U
- // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U
- // .. .. reg_phy_wr_level_start = 0x0
- // .. .. ==> 0XF8006038[7:7] = 0x00000000U
- // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. .. reg_phy_rd_level_start = 0x0
- // .. .. ==> 0XF8006038[8:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. .. reg_phy_dq0_wait_t = 0x0
- // .. .. ==> 0XF8006038[12:9] = 0x00000000U
- // .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U),
- // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
- // .. .. ==> 0XF800603C[3:0] = 0x00000007U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U
- // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
- // .. .. ==> 0XF800603C[7:4] = 0x00000007U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U
- // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
- // .. .. ==> 0XF800603C[11:8] = 0x00000007U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U
- // .. .. reg_ddrc_addrmap_col_b5 = 0x0
- // .. .. ==> 0XF800603C[15:12] = 0x00000000U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b6 = 0x0
- // .. .. ==> 0XF800603C[19:16] = 0x00000000U
- // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
- // .. .. reg_ddrc_addrmap_col_b2 = 0x0
- // .. .. ==> 0XF8006040[3:0] = 0x00000000U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b3 = 0x0
- // .. .. ==> 0XF8006040[7:4] = 0x00000000U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b4 = 0x0
- // .. .. ==> 0XF8006040[11:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b7 = 0x0
- // .. .. ==> 0XF8006040[15:12] = 0x00000000U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b8 = 0x0
- // .. .. ==> 0XF8006040[19:16] = 0x00000000U
- // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b9 = 0xf
- // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
- // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U
- // .. .. reg_ddrc_addrmap_col_b10 = 0xf
- // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
- // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U
- // .. .. reg_ddrc_addrmap_col_b11 = 0xf
- // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
- // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
- // .. .. reg_ddrc_addrmap_row_b0 = 0x6
- // .. .. ==> 0XF8006044[3:0] = 0x00000006U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U
- // .. .. reg_ddrc_addrmap_row_b1 = 0x6
- // .. .. ==> 0XF8006044[7:4] = 0x00000006U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U
- // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
- // .. .. ==> 0XF8006044[11:8] = 0x00000006U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U
- // .. .. reg_ddrc_addrmap_row_b12 = 0x6
- // .. .. ==> 0XF8006044[15:12] = 0x00000006U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U
- // .. .. reg_ddrc_addrmap_row_b13 = 0x6
- // .. .. ==> 0XF8006044[19:16] = 0x00000006U
- // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U
- // .. .. reg_ddrc_addrmap_row_b14 = 0x6
- // .. .. ==> 0XF8006044[23:20] = 0x00000006U
- // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U
- // .. .. reg_ddrc_addrmap_row_b15 = 0xf
- // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
- // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U),
- // .. .. reg_ddrc_rank0_rd_odt = 0x0
- // .. .. ==> 0XF8006048[2:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U
- // .. .. reg_ddrc_rank0_wr_odt = 0x1
- // .. .. ==> 0XF8006048[5:3] = 0x00000001U
- // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U
- // .. .. reg_ddrc_rank1_rd_odt = 0x1
- // .. .. ==> 0XF8006048[8:6] = 0x00000001U
- // .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U
- // .. .. reg_ddrc_rank1_wr_odt = 0x1
- // .. .. ==> 0XF8006048[11:9] = 0x00000001U
- // .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. .. reg_phy_rd_local_odt = 0x0
- // .. .. ==> 0XF8006048[13:12] = 0x00000000U
- // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U
- // .. .. reg_phy_wr_local_odt = 0x3
- // .. .. ==> 0XF8006048[15:14] = 0x00000003U
- // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U
- // .. .. reg_phy_idle_local_odt = 0x3
- // .. .. ==> 0XF8006048[17:16] = 0x00000003U
- // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U
- // .. .. reg_ddrc_rank2_rd_odt = 0x0
- // .. .. ==> 0XF8006048[20:18] = 0x00000000U
- // .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U
- // .. .. reg_ddrc_rank2_wr_odt = 0x0
- // .. .. ==> 0XF8006048[23:21] = 0x00000000U
- // .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U
- // .. .. reg_ddrc_rank3_rd_odt = 0x0
- // .. .. ==> 0XF8006048[26:24] = 0x00000000U
- // .. .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. .. reg_ddrc_rank3_wr_odt = 0x0
- // .. .. ==> 0XF8006048[29:27] = 0x00000000U
- // .. .. ==> MASK : 0x38000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U),
- // .. .. reg_phy_rd_cmd_to_data = 0x0
- // .. .. ==> 0XF8006050[3:0] = 0x00000000U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
- // .. .. reg_phy_wr_cmd_to_data = 0x0
- // .. .. ==> 0XF8006050[7:4] = 0x00000000U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. .. reg_phy_rdc_we_to_re_delay = 0x8
- // .. .. ==> 0XF8006050[11:8] = 0x00000008U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U
- // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
- // .. .. ==> 0XF8006050[15:15] = 0x00000000U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
- // .. .. reg_phy_use_fixed_re = 0x1
- // .. .. ==> 0XF8006050[16:16] = 0x00000001U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U
- // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
- // .. .. ==> 0XF8006050[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
- // .. .. ==> 0XF8006050[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_phy_clk_stall_level = 0x0
- // .. .. ==> 0XF8006050[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
- // .. .. ==> 0XF8006050[27:24] = 0x00000007U
- // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U
- // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
- // .. .. ==> 0XF8006050[31:28] = 0x00000007U
- // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
- // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1
- // .. .. ==> 0XF8006058[7:0] = 0x00000001U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U
- // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1
- // .. .. ==> 0XF8006058[15:8] = 0x00000001U
- // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U
- // .. .. reg_ddrc_dis_dll_calib = 0x0
- // .. .. ==> 0XF8006058[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U),
- // .. .. reg_ddrc_rd_odt_delay = 0x3
- // .. .. ==> 0XF800605C[3:0] = 0x00000003U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U
- // .. .. reg_ddrc_wr_odt_delay = 0x0
- // .. .. ==> 0XF800605C[7:4] = 0x00000000U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. .. reg_ddrc_rd_odt_hold = 0x0
- // .. .. ==> 0XF800605C[11:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U
- // .. .. reg_ddrc_wr_odt_hold = 0x5
- // .. .. ==> 0XF800605C[15:12] = 0x00000005U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U
- // .. ..
- EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
- // .. .. reg_ddrc_pageclose = 0x0
- // .. .. ==> 0XF8006060[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_lpr_num_entries = 0x1f
- // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
- // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU
- // .. .. reg_ddrc_auto_pre_en = 0x0
- // .. .. ==> 0XF8006060[7:7] = 0x00000000U
- // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. .. reg_ddrc_refresh_update_level = 0x0
- // .. .. ==> 0XF8006060[8:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_wc = 0x0
- // .. .. ==> 0XF8006060[9:9] = 0x00000000U
- // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_collision_page_opt = 0x0
- // .. .. ==> 0XF8006060[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_ddrc_selfref_en = 0x0
- // .. .. ==> 0XF8006060[12:12] = 0x00000000U
- // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
- // .. .. reg_ddrc_go2critical_hysteresis = 0x0
- // .. .. ==> 0XF8006064[12:5] = 0x00000000U
- // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U
- // .. .. reg_arb_go2critical_en = 0x1
- // .. .. ==> 0XF8006064[17:17] = 0x00000001U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U
- // .. ..
- EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
- // .. .. reg_ddrc_wrlvl_ww = 0x41
- // .. .. ==> 0XF8006068[7:0] = 0x00000041U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U
- // .. .. reg_ddrc_rdlvl_rr = 0x41
- // .. .. ==> 0XF8006068[15:8] = 0x00000041U
- // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U
- // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
- // .. .. ==> 0XF8006068[25:16] = 0x00000028U
- // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U
- // .. ..
- EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
- // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
- // .. .. ==> 0XF800606C[7:0] = 0x00000010U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U
- // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
- // .. .. ==> 0XF800606C[15:8] = 0x00000016U
- // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U
- // .. ..
- EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
- // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1
- // .. .. ==> 0XF8006078[3:0] = 0x00000001U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U
- // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1
- // .. .. ==> 0XF8006078[7:4] = 0x00000001U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U
- // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1
- // .. .. ==> 0XF8006078[11:8] = 0x00000001U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U
- // .. .. reg_ddrc_t_cksre = 0x6
- // .. .. ==> 0XF8006078[15:12] = 0x00000006U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U
- // .. .. reg_ddrc_t_cksrx = 0x6
- // .. .. ==> 0XF8006078[19:16] = 0x00000006U
- // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U
- // .. .. reg_ddrc_t_ckesr = 0x4
- // .. .. ==> 0XF8006078[25:20] = 0x00000004U
- // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U
- // .. ..
- EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U),
- // .. .. reg_ddrc_t_ckpde = 0x2
- // .. .. ==> 0XF800607C[3:0] = 0x00000002U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U
- // .. .. reg_ddrc_t_ckpdx = 0x2
- // .. .. ==> 0XF800607C[7:4] = 0x00000002U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
- // .. .. reg_ddrc_t_ckdpde = 0x2
- // .. .. ==> 0XF800607C[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. reg_ddrc_t_ckdpdx = 0x2
- // .. .. ==> 0XF800607C[15:12] = 0x00000002U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U
- // .. .. reg_ddrc_t_ckcsx = 0x3
- // .. .. ==> 0XF800607C[19:16] = 0x00000003U
- // .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U
- // .. ..
- EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U),
- // .. .. refresh_timer0_start_value_x32 = 0x0
- // .. .. ==> 0XF80060A0[11:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U
- // .. .. refresh_timer1_start_value_x32 = 0x8
- // .. .. ==> 0XF80060A0[23:12] = 0x00000008U
- // .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U
- // .. ..
- EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U),
- // .. .. reg_ddrc_dis_auto_zq = 0x0
- // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_ddr3 = 0x1
- // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. .. reg_ddrc_t_mod = 0x200
- // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
- // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U
- // .. .. reg_ddrc_t_zq_long_nop = 0x200
- // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
- // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U
- // .. .. reg_ddrc_t_zq_short_nop = 0x40
- // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
- // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
- // .. .. t_zq_short_interval_x1024 = 0xcb73
- // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U
- // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U
- // .. .. dram_rstn_x1024 = 0x69
- // .. .. ==> 0XF80060A8[27:20] = 0x00000069U
- // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U
- // .. ..
- EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
- // .. .. deeppowerdown_en = 0x0
- // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. deeppowerdown_to_x1024 = 0xff
- // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
- // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU
- // .. ..
- EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
- // .. .. dfi_wrlvl_max_x1024 = 0xfff
- // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
- // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU
- // .. .. dfi_rdlvl_max_x1024 = 0xfff
- // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
- // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U
- // .. .. ddrc_reg_twrlvl_max_error = 0x0
- // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
- // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U
- // .. .. ddrc_reg_trdlvl_max_error = 0x0
- // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
- // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
- // .. .. reg_ddrc_dfi_wr_level_en = 0x1
- // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
- // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U
- // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
- // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
- // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U
- // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
- // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
- // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
- // .. .. reg_ddrc_2t_delay = 0x0
- // .. .. ==> 0XF80060B4[8:0] = 0x00000000U
- // .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U
- // .. .. reg_ddrc_skip_ocd = 0x1
- // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
- // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U
- // .. .. reg_ddrc_dis_pre_bypass = 0x0
- // .. .. ==> 0XF80060B4[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U),
- // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
- // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
- // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U
- // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
- // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
- // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U
- // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
- // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
- // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U
- // .. ..
- EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
- // .. .. START: RESET ECC ERROR
- // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1
- // .. .. ==> 0XF80060C4[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. Clear_Correctable_DRAM_ECC_error = 1
- // .. .. ==> 0XF80060C4[1:1] = 0x00000001U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. ..
- EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U),
- // .. .. FINISH: RESET ECC ERROR
- // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
- // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
- // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
- // .. .. CORR_ECC_LOG_VALID = 0x0
- // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. ECC_CORRECTED_BIT_NUM = 0x0
- // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
- // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
- // .. .. UNCORR_ECC_LOG_VALID = 0x0
- // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
- // .. .. STAT_NUM_CORR_ERR = 0x0
- // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
- // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U
- // .. .. STAT_NUM_UNCORR_ERR = 0x0
- // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
- // .. .. reg_ddrc_ecc_mode = 0x0
- // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_scrub = 0x1
- // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U
- // .. ..
- EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
- // .. .. reg_phy_dif_on = 0x0
- // .. .. ==> 0XF8006114[3:0] = 0x00000000U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
- // .. .. reg_phy_dif_off = 0x0
- // .. .. ==> 0XF8006114[7:4] = 0x00000000U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
- // .. .. reg_phy_data_slice_in_use = 0x1
- // .. .. ==> 0XF8006118[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_phy_rdlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006118[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_inc_mode = 0x0
- // .. .. ==> 0XF8006118[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_wrlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006118[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_tx = 0x0
- // .. .. ==> 0XF8006118[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_rx = 0x0
- // .. .. ==> 0XF8006118[5:5] = 0x00000000U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. .. reg_phy_bist_shift_dq = 0x0
- // .. .. ==> 0XF8006118[14:6] = 0x00000000U
- // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. .. reg_phy_bist_err_clr = 0x0
- // .. .. ==> 0XF8006118[23:15] = 0x00000000U
- // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. .. reg_phy_dq_offset = 0x40
- // .. .. ==> 0XF8006118[30:24] = 0x00000040U
- // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U),
- // .. .. reg_phy_data_slice_in_use = 0x1
- // .. .. ==> 0XF800611C[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_phy_rdlvl_inc_mode = 0x0
- // .. .. ==> 0XF800611C[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_inc_mode = 0x0
- // .. .. ==> 0XF800611C[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_wrlvl_inc_mode = 0x0
- // .. .. ==> 0XF800611C[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_tx = 0x0
- // .. .. ==> 0XF800611C[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_rx = 0x0
- // .. .. ==> 0XF800611C[5:5] = 0x00000000U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. .. reg_phy_bist_shift_dq = 0x0
- // .. .. ==> 0XF800611C[14:6] = 0x00000000U
- // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. .. reg_phy_bist_err_clr = 0x0
- // .. .. ==> 0XF800611C[23:15] = 0x00000000U
- // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. .. reg_phy_dq_offset = 0x40
- // .. .. ==> 0XF800611C[30:24] = 0x00000040U
- // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U),
- // .. .. reg_phy_data_slice_in_use = 0x1
- // .. .. ==> 0XF8006120[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_phy_rdlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006120[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_inc_mode = 0x0
- // .. .. ==> 0XF8006120[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_wrlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006120[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_tx = 0x0
- // .. .. ==> 0XF8006120[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_rx = 0x0
- // .. .. ==> 0XF8006120[5:5] = 0x00000000U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. .. reg_phy_bist_shift_dq = 0x0
- // .. .. ==> 0XF8006120[14:6] = 0x00000000U
- // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. .. reg_phy_bist_err_clr = 0x0
- // .. .. ==> 0XF8006120[23:15] = 0x00000000U
- // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. .. reg_phy_dq_offset = 0x40
- // .. .. ==> 0XF8006120[30:24] = 0x00000040U
- // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // .. .. reg_phy_data_slice_in_use = 0x1
- // .. .. ==> 0XF8006120[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_phy_rdlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006120[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_inc_mode = 0x0
- // .. .. ==> 0XF8006120[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_wrlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006120[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_tx = 0x0
- // .. .. ==> 0XF8006120[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_rx = 0x0
- // .. .. ==> 0XF8006120[5:5] = 0x00000000U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. .. reg_phy_bist_shift_dq = 0x0
- // .. .. ==> 0XF8006120[14:6] = 0x00000000U
- // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. .. reg_phy_bist_err_clr = 0x0
- // .. .. ==> 0XF8006120[23:15] = 0x00000000U
- // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. .. reg_phy_dq_offset = 0x40
- // .. .. ==> 0XF8006120[30:24] = 0x00000040U
- // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U),
- // .. .. reg_phy_data_slice_in_use = 0x1
- // .. .. ==> 0XF8006124[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_phy_rdlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006124[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_inc_mode = 0x0
- // .. .. ==> 0XF8006124[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_wrlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006124[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_tx = 0x0
- // .. .. ==> 0XF8006124[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_rx = 0x0
- // .. .. ==> 0XF8006124[5:5] = 0x00000000U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. .. reg_phy_bist_shift_dq = 0x0
- // .. .. ==> 0XF8006124[14:6] = 0x00000000U
- // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. .. reg_phy_bist_err_clr = 0x0
- // .. .. ==> 0XF8006124[23:15] = 0x00000000U
- // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. .. reg_phy_dq_offset = 0x40
- // .. .. ==> 0XF8006124[30:24] = 0x00000040U
- // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U),
- // .. .. reg_phy_wrlvl_init_ratio = 0x1d
- // .. .. ==> 0XF800612C[9:0] = 0x0000001DU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x0000001DU
- // .. .. reg_phy_gatelvl_init_ratio = 0xf2
- // .. .. ==> 0XF800612C[19:10] = 0x000000F2U
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x0003C800U
- // .. ..
- EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0003C81DU),
- // .. .. reg_phy_wrlvl_init_ratio = 0x12
- // .. .. ==> 0XF8006130[9:0] = 0x00000012U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000012U
- // .. .. reg_phy_gatelvl_init_ratio = 0xd8
- // .. .. ==> 0XF8006130[19:10] = 0x000000D8U
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x00036000U
- // .. ..
- EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00036012U),
- // .. .. reg_phy_wrlvl_init_ratio = 0xc
- // .. .. ==> 0XF8006134[9:0] = 0x0000000CU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x0000000CU
- // .. .. reg_phy_gatelvl_init_ratio = 0xde
- // .. .. ==> 0XF8006134[19:10] = 0x000000DEU
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x00037800U
- // .. ..
- EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0003780CU),
- // .. .. reg_phy_wrlvl_init_ratio = 0x21
- // .. .. ==> 0XF8006138[9:0] = 0x00000021U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000021U
- // .. .. reg_phy_gatelvl_init_ratio = 0xee
- // .. .. ==> 0XF8006138[19:10] = 0x000000EEU
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x0003B800U
- // .. ..
- EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0003B821U),
- // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. .. ==> 0XF8006140[9:0] = 0x00000035U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. .. reg_phy_rd_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006140[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006140[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
- // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. .. ==> 0XF8006144[9:0] = 0x00000035U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. .. reg_phy_rd_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006144[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006144[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
- // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. .. ==> 0XF8006148[9:0] = 0x00000035U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. .. reg_phy_rd_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006148[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006148[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
- // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. .. ==> 0XF800614C[9:0] = 0x00000035U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. .. reg_phy_rd_dqs_slave_force = 0x0
- // .. .. ==> 0XF800614C[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. .. ==> 0XF800614C[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
- // .. .. reg_phy_wr_dqs_slave_ratio = 0x9d
- // .. .. ==> 0XF8006154[9:0] = 0x0000009DU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x0000009DU
- // .. .. reg_phy_wr_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006154[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006154[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x0000009DU),
- // .. .. reg_phy_wr_dqs_slave_ratio = 0x92
- // .. .. ==> 0XF8006158[9:0] = 0x00000092U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000092U
- // .. .. reg_phy_wr_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006158[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006158[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000092U),
- // .. .. reg_phy_wr_dqs_slave_ratio = 0x8c
- // .. .. ==> 0XF800615C[9:0] = 0x0000008CU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x0000008CU
- // .. .. reg_phy_wr_dqs_slave_force = 0x0
- // .. .. ==> 0XF800615C[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. .. ==> 0XF800615C[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x0000008CU),
- // .. .. reg_phy_wr_dqs_slave_ratio = 0xa1
- // .. .. ==> 0XF8006160[9:0] = 0x000000A1U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000000A1U
- // .. .. reg_phy_wr_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006160[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006160[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x000000A1U),
- // .. .. reg_phy_fifo_we_slave_ratio = 0x147
- // .. .. ==> 0XF8006168[10:0] = 0x00000147U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x00000147U
- // .. .. reg_phy_fifo_we_in_force = 0x0
- // .. .. ==> 0XF8006168[11:11] = 0x00000000U
- // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. .. reg_phy_fifo_we_in_delay = 0x0
- // .. .. ==> 0XF8006168[20:12] = 0x00000000U
- // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000147U),
- // .. .. reg_phy_fifo_we_slave_ratio = 0x12d
- // .. .. ==> 0XF800616C[10:0] = 0x0000012DU
- // .. .. ==> MASK : 0x000007FFU VAL : 0x0000012DU
- // .. .. reg_phy_fifo_we_in_force = 0x0
- // .. .. ==> 0XF800616C[11:11] = 0x00000000U
- // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. .. reg_phy_fifo_we_in_delay = 0x0
- // .. .. ==> 0XF800616C[20:12] = 0x00000000U
- // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x0000012DU),
- // .. .. reg_phy_fifo_we_slave_ratio = 0x133
- // .. .. ==> 0XF8006170[10:0] = 0x00000133U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x00000133U
- // .. .. reg_phy_fifo_we_in_force = 0x0
- // .. .. ==> 0XF8006170[11:11] = 0x00000000U
- // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. .. reg_phy_fifo_we_in_delay = 0x0
- // .. .. ==> 0XF8006170[20:12] = 0x00000000U
- // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000133U),
- // .. .. reg_phy_fifo_we_slave_ratio = 0x143
- // .. .. ==> 0XF8006174[10:0] = 0x00000143U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x00000143U
- // .. .. reg_phy_fifo_we_in_force = 0x0
- // .. .. ==> 0XF8006174[11:11] = 0x00000000U
- // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. .. reg_phy_fifo_we_in_delay = 0x0
- // .. .. ==> 0XF8006174[20:12] = 0x00000000U
- // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000143U),
- // .. .. reg_phy_wr_data_slave_ratio = 0xdd
- // .. .. ==> 0XF800617C[9:0] = 0x000000DDU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000000DDU
- // .. .. reg_phy_wr_data_slave_force = 0x0
- // .. .. ==> 0XF800617C[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_data_slave_delay = 0x0
- // .. .. ==> 0XF800617C[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000DDU),
- // .. .. reg_phy_wr_data_slave_ratio = 0xd2
- // .. .. ==> 0XF8006180[9:0] = 0x000000D2U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000000D2U
- // .. .. reg_phy_wr_data_slave_force = 0x0
- // .. .. ==> 0XF8006180[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_data_slave_delay = 0x0
- // .. .. ==> 0XF8006180[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000D2U),
- // .. .. reg_phy_wr_data_slave_ratio = 0xcc
- // .. .. ==> 0XF8006184[9:0] = 0x000000CCU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000000CCU
- // .. .. reg_phy_wr_data_slave_force = 0x0
- // .. .. ==> 0XF8006184[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_data_slave_delay = 0x0
- // .. .. ==> 0XF8006184[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000CCU),
- // .. .. reg_phy_wr_data_slave_ratio = 0xe1
- // .. .. ==> 0XF8006188[9:0] = 0x000000E1U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000000E1U
- // .. .. reg_phy_wr_data_slave_force = 0x0
- // .. .. ==> 0XF8006188[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_data_slave_delay = 0x0
- // .. .. ==> 0XF8006188[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000E1U),
- // .. .. reg_phy_loopback = 0x0
- // .. .. ==> 0XF8006190[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_phy_bl2 = 0x0
- // .. .. ==> 0XF8006190[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_at_spd_atpg = 0x0
- // .. .. ==> 0XF8006190[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_bist_enable = 0x0
- // .. .. ==> 0XF8006190[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_bist_force_err = 0x0
- // .. .. ==> 0XF8006190[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. reg_phy_bist_mode = 0x0
- // .. .. ==> 0XF8006190[6:5] = 0x00000000U
- // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. .. reg_phy_invert_clkout = 0x1
- // .. .. ==> 0XF8006190[7:7] = 0x00000001U
- // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0
- // .. .. ==> 0XF8006190[8:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. .. reg_phy_sel_logic = 0x0
- // .. .. ==> 0XF8006190[9:9] = 0x00000000U
- // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U
- // .. .. reg_phy_ctrl_slave_ratio = 0x100
- // .. .. ==> 0XF8006190[19:10] = 0x00000100U
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U
- // .. .. reg_phy_ctrl_slave_force = 0x0
- // .. .. ==> 0XF8006190[20:20] = 0x00000000U
- // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U
- // .. .. reg_phy_ctrl_slave_delay = 0x0
- // .. .. ==> 0XF8006190[27:21] = 0x00000000U
- // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U
- // .. .. reg_phy_use_rank0_delays = 0x1
- // .. .. ==> 0XF8006190[28:28] = 0x00000001U
- // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
- // .. .. reg_phy_lpddr = 0x0
- // .. .. ==> 0XF8006190[29:29] = 0x00000000U
- // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U
- // .. .. reg_phy_cmd_latency = 0x0
- // .. .. ==> 0XF8006190[30:30] = 0x00000000U
- // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U
- // .. .. reg_phy_int_lpbk = 0x0
- // .. .. ==> 0XF8006190[31:31] = 0x00000000U
- // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U),
- // .. .. reg_phy_wr_rl_delay = 0x2
- // .. .. ==> 0XF8006194[4:0] = 0x00000002U
- // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U
- // .. .. reg_phy_rd_rl_delay = 0x4
- // .. .. ==> 0XF8006194[9:5] = 0x00000004U
- // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U
- // .. .. reg_phy_dll_lock_diff = 0xf
- // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
- // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U
- // .. .. reg_phy_use_wr_level = 0x1
- // .. .. ==> 0XF8006194[14:14] = 0x00000001U
- // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U
- // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
- // .. .. ==> 0XF8006194[15:15] = 0x00000001U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U
- // .. .. reg_phy_use_rd_data_eye_level = 0x1
- // .. .. ==> 0XF8006194[16:16] = 0x00000001U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U
- // .. .. reg_phy_dis_calib_rst = 0x0
- // .. .. ==> 0XF8006194[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_phy_ctrl_slave_delay = 0x0
- // .. .. ==> 0XF8006194[19:18] = 0x00000000U
- // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
- // .. .. reg_arb_page_addr_mask = 0x0
- // .. .. ==> 0XF8006204[31:0] = 0x00000000U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
- // .. .. reg_arb_pri_wr_portn = 0x3ff
- // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_wr_portn = 0x0
- // .. .. ==> 0XF8006208[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. .. ==> 0XF8006208[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. .. ==> 0XF8006208[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_dis_rmw_portn = 0x1
- // .. .. ==> 0XF8006208[19:19] = 0x00000001U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // .. ..
- EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU),
- // .. .. reg_arb_pri_wr_portn = 0x3ff
- // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_wr_portn = 0x0
- // .. .. ==> 0XF800620C[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. .. ==> 0XF800620C[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. .. ==> 0XF800620C[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_dis_rmw_portn = 0x1
- // .. .. ==> 0XF800620C[19:19] = 0x00000001U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // .. ..
- EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU),
- // .. .. reg_arb_pri_wr_portn = 0x3ff
- // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_wr_portn = 0x0
- // .. .. ==> 0XF8006210[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. .. ==> 0XF8006210[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. .. ==> 0XF8006210[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_dis_rmw_portn = 0x1
- // .. .. ==> 0XF8006210[19:19] = 0x00000001U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // .. ..
- EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU),
- // .. .. reg_arb_pri_wr_portn = 0x3ff
- // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_wr_portn = 0x0
- // .. .. ==> 0XF8006214[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. .. ==> 0XF8006214[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. .. ==> 0XF8006214[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_dis_rmw_portn = 0x1
- // .. .. ==> 0XF8006214[19:19] = 0x00000001U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // .. ..
- EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU),
- // .. .. reg_arb_pri_rd_portn = 0x3ff
- // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_rd_portn = 0x0
- // .. .. ==> 0XF8006218[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. .. ==> 0XF8006218[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. .. ==> 0XF8006218[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_set_hpr_rd_portn = 0x0
- // .. .. ==> 0XF8006218[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
- // .. .. reg_arb_pri_rd_portn = 0x3ff
- // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_rd_portn = 0x0
- // .. .. ==> 0XF800621C[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. .. ==> 0XF800621C[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. .. ==> 0XF800621C[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_set_hpr_rd_portn = 0x0
- // .. .. ==> 0XF800621C[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
- // .. .. reg_arb_pri_rd_portn = 0x3ff
- // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_rd_portn = 0x0
- // .. .. ==> 0XF8006220[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. .. ==> 0XF8006220[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. .. ==> 0XF8006220[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_set_hpr_rd_portn = 0x0
- // .. .. ==> 0XF8006220[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
- // .. .. reg_arb_pri_rd_portn = 0x3ff
- // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_rd_portn = 0x0
- // .. .. ==> 0XF8006224[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. .. ==> 0XF8006224[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. .. ==> 0XF8006224[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_set_hpr_rd_portn = 0x0
- // .. .. ==> 0XF8006224[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
- // .. .. reg_ddrc_lpddr2 = 0x0
- // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_per_bank_refresh = 0x0
- // .. .. ==> 0XF80062A8[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_ddrc_derate_enable = 0x0
- // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_ddrc_mr4_margin = 0x0
- // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U),
- // .. .. reg_ddrc_mr4_read_interval = 0x0
- // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
- // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
- // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U
- // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
- // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
- // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U
- // .. .. reg_ddrc_t_mrw = 0x5
- // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
- // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U
- // .. ..
- EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
- // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8
- // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U
- // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
- // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
- // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U
- // .. ..
- EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
- // .. .. START: POLL ON DCI STATUS
- // .. .. DONE = 1
- // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
- // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // .. ..
- EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
- // .. .. FINISH: POLL ON DCI STATUS
- // .. .. START: UNLOCK DDR
- // .. .. reg_ddrc_soft_rstb = 0x1
- // .. .. ==> 0XF8006000[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_ddrc_powerdown_en = 0x0
- // .. .. ==> 0XF8006000[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_ddrc_data_bus_width = 0x0
- // .. .. ==> 0XF8006000[3:2] = 0x00000000U
- // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U
- // .. .. reg_ddrc_burst8_refresh = 0x0
- // .. .. ==> 0XF8006000[6:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U
- // .. .. reg_ddrc_rdwr_idle_gap = 1
- // .. .. ==> 0XF8006000[13:7] = 0x00000001U
- // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U
- // .. .. reg_ddrc_dis_rd_bypass = 0x0
- // .. .. ==> 0XF8006000[14:14] = 0x00000000U
- // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_act_bypass = 0x0
- // .. .. ==> 0XF8006000[15:15] = 0x00000000U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_auto_refresh = 0x0
- // .. .. ==> 0XF8006000[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
- // .. .. FINISH: UNLOCK DDR
- // .. .. START: CHECK DDR STATUS
- // .. .. ddrc_reg_operating_mode = 1
- // .. .. ==> 0XF8006054[2:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U
- // .. ..
- EMIT_MASKPOLL(0XF8006054, 0x00000007U),
- // .. .. FINISH: CHECK DDR STATUS
- // .. FINISH: DDR INITIALIZATION
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_mio_init_data_2_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: OCM REMAPPING
- // .. VREF_EN = 0x1
- // .. ==> 0XF8000B00[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. VREF_PULLUP_EN = 0x0
- // .. ==> 0XF8000B00[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. CLK_PULLUP_EN = 0x0
- // .. ==> 0XF8000B00[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. SRSTN_PULLUP_EN = 0x0
- // .. ==> 0XF8000B00[9:9] = 0x00000000U
- // .. ==> MASK : 0x00000200U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B00, 0x00000303U ,0x00000001U),
- // .. FINISH: OCM REMAPPING
- // .. START: DDRIOB SETTINGS
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B40[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x0
- // .. ==> 0XF8000B40[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B40[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x0
- // .. ==> 0XF8000B40[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. DCR_TYPE = 0x0
- // .. ==> 0XF8000B40[6:5] = 0x00000000U
- // .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. IBUF_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B40[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B40[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B40[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B40[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B44[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x0
- // .. ==> 0XF8000B44[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B44[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x0
- // .. ==> 0XF8000B44[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. DCR_TYPE = 0x0
- // .. ==> 0XF8000B44[6:5] = 0x00000000U
- // .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. IBUF_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B44[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B44[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B44[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B44[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B48[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x1
- // .. ==> 0XF8000B48[2:1] = 0x00000001U
- // .. ==> MASK : 0x00000006U VAL : 0x00000002U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B48[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x1
- // .. ==> 0XF8000B48[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. DCR_TYPE = 0x3
- // .. ==> 0XF8000B48[6:5] = 0x00000003U
- // .. ==> MASK : 0x00000060U VAL : 0x00000060U
- // .. IBUF_DISABLE_MODE = 0
- // .. ==> 0XF8000B48[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0
- // .. ==> 0XF8000B48[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B48[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B48[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B4C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x1
- // .. ==> 0XF8000B4C[2:1] = 0x00000001U
- // .. ==> MASK : 0x00000006U VAL : 0x00000002U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B4C[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x1
- // .. ==> 0XF8000B4C[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. DCR_TYPE = 0x3
- // .. ==> 0XF8000B4C[6:5] = 0x00000003U
- // .. ==> MASK : 0x00000060U VAL : 0x00000060U
- // .. IBUF_DISABLE_MODE = 0
- // .. ==> 0XF8000B4C[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0
- // .. ==> 0XF8000B4C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B4C[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B4C[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B50[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x2
- // .. ==> 0XF8000B50[2:1] = 0x00000002U
- // .. ==> MASK : 0x00000006U VAL : 0x00000004U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B50[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x1
- // .. ==> 0XF8000B50[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. DCR_TYPE = 0x3
- // .. ==> 0XF8000B50[6:5] = 0x00000003U
- // .. ==> MASK : 0x00000060U VAL : 0x00000060U
- // .. IBUF_DISABLE_MODE = 0
- // .. ==> 0XF8000B50[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0
- // .. ==> 0XF8000B50[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B50[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B50[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B54[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x2
- // .. ==> 0XF8000B54[2:1] = 0x00000002U
- // .. ==> MASK : 0x00000006U VAL : 0x00000004U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B54[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x1
- // .. ==> 0XF8000B54[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. DCR_TYPE = 0x3
- // .. ==> 0XF8000B54[6:5] = 0x00000003U
- // .. ==> MASK : 0x00000060U VAL : 0x00000060U
- // .. IBUF_DISABLE_MODE = 0
- // .. ==> 0XF8000B54[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0
- // .. ==> 0XF8000B54[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B54[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B54[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B58[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x0
- // .. ==> 0XF8000B58[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B58[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x0
- // .. ==> 0XF8000B58[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. DCR_TYPE = 0x0
- // .. ==> 0XF8000B58[6:5] = 0x00000000U
- // .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. IBUF_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B58[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B58[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B58[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B58[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
- // .. DRIVE_P = 0x1c
- // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
- // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
- // .. DRIVE_N = 0xc
- // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
- // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
- // .. SLEW_P = 0x3
- // .. ==> 0XF8000B5C[18:14] = 0x00000003U
- // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U
- // .. SLEW_N = 0x3
- // .. ==> 0XF8000B5C[23:19] = 0x00000003U
- // .. ==> MASK : 0x00F80000U VAL : 0x00180000U
- // .. GTL = 0x0
- // .. ==> 0XF8000B5C[26:24] = 0x00000000U
- // .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. RTERM = 0x0
- // .. ==> 0XF8000B5C[31:27] = 0x00000000U
- // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
- // .. DRIVE_P = 0x1c
- // .. ==> 0XF8000B60[6:0] = 0x0000001CU
- // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
- // .. DRIVE_N = 0xc
- // .. ==> 0XF8000B60[13:7] = 0x0000000CU
- // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
- // .. SLEW_P = 0x6
- // .. ==> 0XF8000B60[18:14] = 0x00000006U
- // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
- // .. SLEW_N = 0x1f
- // .. ==> 0XF8000B60[23:19] = 0x0000001FU
- // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
- // .. GTL = 0x0
- // .. ==> 0XF8000B60[26:24] = 0x00000000U
- // .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. RTERM = 0x0
- // .. ==> 0XF8000B60[31:27] = 0x00000000U
- // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
- // .. DRIVE_P = 0x1c
- // .. ==> 0XF8000B64[6:0] = 0x0000001CU
- // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
- // .. DRIVE_N = 0xc
- // .. ==> 0XF8000B64[13:7] = 0x0000000CU
- // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
- // .. SLEW_P = 0x6
- // .. ==> 0XF8000B64[18:14] = 0x00000006U
- // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
- // .. SLEW_N = 0x1f
- // .. ==> 0XF8000B64[23:19] = 0x0000001FU
- // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
- // .. GTL = 0x0
- // .. ==> 0XF8000B64[26:24] = 0x00000000U
- // .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. RTERM = 0x0
- // .. ==> 0XF8000B64[31:27] = 0x00000000U
- // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
- // .. DRIVE_P = 0x1c
- // .. ==> 0XF8000B68[6:0] = 0x0000001CU
- // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
- // .. DRIVE_N = 0xc
- // .. ==> 0XF8000B68[13:7] = 0x0000000CU
- // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
- // .. SLEW_P = 0x6
- // .. ==> 0XF8000B68[18:14] = 0x00000006U
- // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
- // .. SLEW_N = 0x1f
- // .. ==> 0XF8000B68[23:19] = 0x0000001FU
- // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
- // .. GTL = 0x0
- // .. ==> 0XF8000B68[26:24] = 0x00000000U
- // .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. RTERM = 0x0
- // .. ==> 0XF8000B68[31:27] = 0x00000000U
- // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
- // .. VREF_INT_EN = 0x1
- // .. ==> 0XF8000B6C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. VREF_SEL = 0x4
- // .. ==> 0XF8000B6C[4:1] = 0x00000004U
- // .. ==> MASK : 0x0000001EU VAL : 0x00000008U
- // .. VREF_EXT_EN = 0x0
- // .. ==> 0XF8000B6C[6:5] = 0x00000000U
- // .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. VREF_PULLUP_EN = 0x0
- // .. ==> 0XF8000B6C[8:7] = 0x00000000U
- // .. ==> MASK : 0x00000180U VAL : 0x00000000U
- // .. REFIO_EN = 0x1
- // .. ==> 0XF8000B6C[9:9] = 0x00000001U
- // .. ==> MASK : 0x00000200U VAL : 0x00000200U
- // .. REFIO_TEST = 0x3
- // .. ==> 0XF8000B6C[11:10] = 0x00000003U
- // .. ==> MASK : 0x00000C00U VAL : 0x00000C00U
- // .. REFIO_PULLUP_EN = 0x0
- // .. ==> 0XF8000B6C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DRST_B_PULLUP_EN = 0x0
- // .. ==> 0XF8000B6C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // .. CKE_PULLUP_EN = 0x0
- // .. ==> 0XF8000B6C[14:14] = 0x00000000U
- // .. ==> MASK : 0x00004000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000E09U),
- // .. .. START: ASSERT RESET
- // .. .. RESET = 1
- // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. VRN_OUT = 0x1
- // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
- // .. ..
- EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U),
- // .. .. FINISH: ASSERT RESET
- // .. .. START: DEASSERT RESET
- // .. .. RESET = 0
- // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. VRN_OUT = 0x1
- // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
- // .. ..
- EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
- // .. .. FINISH: DEASSERT RESET
- // .. .. RESET = 0x1
- // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ENABLE = 0x1
- // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. .. VRP_TRI = 0x0
- // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. VRN_TRI = 0x0
- // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. VRP_OUT = 0x0
- // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. VRN_OUT = 0x1
- // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
- // .. .. NREF_OPT1 = 0x0
- // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
- // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U
- // .. .. NREF_OPT2 = 0x0
- // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U
- // .. .. NREF_OPT4 = 0x1
- // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
- // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U
- // .. .. PREF_OPT1 = 0x0
- // .. .. ==> 0XF8000B70[16:14] = 0x00000000U
- // .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U
- // .. .. PREF_OPT2 = 0x0
- // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
- // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U
- // .. .. UPDATE_CONTROL = 0x0
- // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
- // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U
- // .. .. INIT_COMPLETE = 0x0
- // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
- // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U
- // .. .. TST_CLK = 0x0
- // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
- // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U
- // .. .. TST_HLN = 0x0
- // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
- // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U
- // .. .. TST_HLP = 0x0
- // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
- // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U
- // .. .. TST_RST = 0x0
- // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
- // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
- // .. .. INT_DCI_EN = 0x0
- // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
- // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U),
- // .. FINISH: DDRIOB SETTINGS
- // .. START: MIO PROGRAMMING
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000700[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. Speed = 0
- // .. ==> 0XF8000700[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000700[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 1
- // .. ==> 0XF8000700[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000700[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000700, 0x00003F01U ,0x00001201U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000704[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000704[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000704[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000704[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000704[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000704[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000704[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 1
- // .. ==> 0XF8000704[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000704[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001202U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000708[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000708[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000708[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000708[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000708[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000708[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000708[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000708[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000708[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000202U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800070C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF800070C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF800070C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800070C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800070C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800070C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF800070C[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF800070C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800070C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000202U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000710[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000710[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000710[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000710[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000710[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000710[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000710[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000710[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000710[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000202U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000714[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000714[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000714[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000714[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000714[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000714[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000714[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000714[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000714[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000202U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000718[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000718[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000718[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000718[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000718[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000718[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000718[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000718[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000718[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000202U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800071C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800071C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF800071C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800071C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800071C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800071C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF800071C[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF800071C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800071C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000200U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000720[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000720[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000720[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000720[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000720[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000720[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000720[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000720[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000720[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000202U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000724[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000724[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000724[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000724[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000724[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000724[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000724[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 1
- // .. ==> 0XF8000724[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000724[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001200U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000728[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000728[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000728[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000728[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000728[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000728[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000728[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 1
- // .. ==> 0XF8000728[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000728[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001200U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800072C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800072C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF800072C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800072C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800072C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800072C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF800072C[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 1
- // .. ==> 0XF800072C[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800072C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001200U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000730[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000730[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000730[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000730[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000730[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000730[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000730[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 1
- // .. ==> 0XF8000730[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000730[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001200U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000734[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000734[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000734[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000734[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000734[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000734[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000734[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 1
- // .. ==> 0XF8000734[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000734[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001200U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000738[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000738[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000738[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000738[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000738[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000738[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000738[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 1
- // .. ==> 0XF8000738[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000738[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00001200U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF800073C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. Speed = 0
- // .. ==> 0XF800073C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF800073C[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 1
- // .. ==> 0XF800073C[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800073C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800073C, 0x00003F01U ,0x00001201U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000740[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000740[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000740[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000740[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000740[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000740[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 4
- // .. ==> 0XF8000740[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000740[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 1
- // .. ==> 0XF8000740[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // ..
- EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00002802U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000744[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000744[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000744[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000744[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000744[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000744[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 4
- // .. ==> 0XF8000744[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000744[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 1
- // .. ==> 0XF8000744[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // ..
- EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00002802U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000748[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000748[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000748[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000748[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000748[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000748[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 4
- // .. ==> 0XF8000748[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000748[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 1
- // .. ==> 0XF8000748[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // ..
- EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00002802U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800074C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF800074C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF800074C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800074C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800074C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800074C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 4
- // .. ==> 0XF800074C[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF800074C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 1
- // .. ==> 0XF800074C[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // ..
- EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00002802U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000750[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000750[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000750[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000750[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000750[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000750[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 4
- // .. ==> 0XF8000750[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000750[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 1
- // .. ==> 0XF8000750[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // ..
- EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00002802U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000754[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000754[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000754[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000754[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000754[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000754[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 4
- // .. ==> 0XF8000754[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000754[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 1
- // .. ==> 0XF8000754[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // ..
- EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00002802U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000758[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF8000758[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000758[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000758[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000758[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000758[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 4
- // .. ==> 0XF8000758[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000758[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000758[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000803U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF800075C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF800075C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF800075C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800075C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800075C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800075C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 4
- // .. ==> 0XF800075C[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF800075C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800075C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000803U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000760[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF8000760[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000760[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000760[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000760[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000760[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 4
- // .. ==> 0XF8000760[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000760[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000760[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000803U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000764[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF8000764[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000764[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000764[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000764[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000764[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 4
- // .. ==> 0XF8000764[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000764[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000764[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000803U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000768[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF8000768[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000768[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000768[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000768[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000768[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 4
- // .. ==> 0XF8000768[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000768[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000768[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000803U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF800076C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF800076C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF800076C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800076C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800076C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800076C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 4
- // .. ==> 0XF800076C[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF800076C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800076C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000803U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000770[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000770[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000770[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000770[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000770[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000770[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000770[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000770[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000770[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000774[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF8000774[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000774[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000774[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000774[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000774[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000774[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000774[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000774[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000778[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000778[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000778[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000778[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000778[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000778[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000778[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000778[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000778[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF800077C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF800077C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF800077C[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF800077C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800077C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800077C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF800077C[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF800077C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800077C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000780[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000780[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000780[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000780[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000780[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000780[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000780[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000780[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000780[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000784[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000784[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000784[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000784[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000784[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000784[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000784[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000784[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000784[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000788[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000788[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000788[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000788[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000788[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000788[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000788[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000788[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000788[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800078C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800078C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF800078C[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF800078C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800078C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800078C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF800078C[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF800078C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800078C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000790[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF8000790[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000790[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000790[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000790[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000790[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000790[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000790[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000790[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000794[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000794[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000794[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000794[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000794[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000794[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000794[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000794[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000794[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000798[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000798[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000798[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000798[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000798[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000798[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000798[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000798[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000798[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800079C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800079C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF800079C[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF800079C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800079C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800079C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF800079C[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF800079C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800079C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007A0[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007A0[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007A0[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007A0[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007A0[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF80007A0[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007A0[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007A0[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007A0[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000280U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007A4[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007A4[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007A4[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007A4[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007A4[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF80007A4[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007A4[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007A4[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007A4[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000280U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007A8[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007A8[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007A8[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007A8[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007A8[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF80007A8[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007A8[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007A8[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007A8[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000280U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007AC[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007AC[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007AC[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007AC[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007AC[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF80007AC[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007AC[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007AC[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007AC[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000280U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007B0[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007B0[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007B0[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007B0[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007B0[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF80007B0[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007B0[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007B0[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007B0[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000280U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007B4[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007B4[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007B4[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007B4[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007B4[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF80007B4[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007B4[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007B4[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007B4[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000280U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF80007B8[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF80007B8[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007B8[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007B8[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 1
- // .. ==> 0XF80007B8[7:5] = 0x00000001U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000020U
- // .. Speed = 0
- // .. ==> 0XF80007B8[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007B8[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 1
- // .. ==> 0XF80007B8[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007B8[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001221U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007BC[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007BC[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007BC[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007BC[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 1
- // .. ==> 0XF80007BC[7:5] = 0x00000001U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000020U
- // .. Speed = 0
- // .. ==> 0XF80007BC[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007BC[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 1
- // .. ==> 0XF80007BC[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007BC[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00001220U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007C0[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007C0[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007C0[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007C0[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 7
- // .. ==> 0XF80007C0[7:5] = 0x00000007U
- // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U
- // .. Speed = 0
- // .. ==> 0XF80007C0[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007C0[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007C0[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007C0[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF80007C4[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF80007C4[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007C4[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007C4[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 7
- // .. ==> 0XF80007C4[7:5] = 0x00000007U
- // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U
- // .. Speed = 0
- // .. ==> 0XF80007C4[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007C4[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007C4[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007C4[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007C8[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007C8[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007C8[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007C8[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 2
- // .. ==> 0XF80007C8[7:5] = 0x00000002U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000040U
- // .. Speed = 0
- // .. ==> 0XF80007C8[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007C8[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 1
- // .. ==> 0XF80007C8[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007C8[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001240U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007CC[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007CC[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007CC[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007CC[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 2
- // .. ==> 0XF80007CC[7:5] = 0x00000002U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000040U
- // .. Speed = 0
- // .. ==> 0XF80007CC[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007CC[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 1
- // .. ==> 0XF80007CC[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007CC[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001240U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007D0[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007D0[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007D0[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007D0[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007D0[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF80007D0[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007D0[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007D0[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007D0[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007D4[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007D4[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007D4[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007D4[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007D4[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF80007D4[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007D4[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007D4[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007D4[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U),
- // .. SDIO0_WP_SEL = 15
- // .. ==> 0XF8000830[5:0] = 0x0000000FU
- // .. ==> MASK : 0x0000003FU VAL : 0x0000000FU
- // .. SDIO0_CD_SEL = 0
- // .. ==> 0XF8000830[21:16] = 0x00000000U
- // .. ==> MASK : 0x003F0000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x0000000FU),
- // .. FINISH: MIO PROGRAMMING
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_peripherals_init_data_2_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
- // .. IBUF_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B48[7:7] = 0x00000001U
- // .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. TERM_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B48[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // ..
- EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
- // .. IBUF_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B4C[7:7] = 0x00000001U
- // .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. TERM_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B4C[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // ..
- EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
- // .. IBUF_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B50[7:7] = 0x00000001U
- // .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. TERM_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B50[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // ..
- EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
- // .. IBUF_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B54[7:7] = 0x00000001U
- // .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. TERM_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B54[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // ..
- EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
- // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // .. START: SRAM/NOR SET OPMODE
- // .. FINISH: SRAM/NOR SET OPMODE
- // .. START: UART REGISTERS
- // .. BDIV = 0x6
- // .. ==> 0XE0001034[7:0] = 0x00000006U
- // .. ==> MASK : 0x000000FFU VAL : 0x00000006U
- // ..
- EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
- // .. CD = 0x3e
- // .. ==> 0XE0001018[15:0] = 0x0000003EU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU
- // ..
- EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
- // .. STPBRK = 0x0
- // .. ==> 0XE0001000[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. STTBRK = 0x0
- // .. ==> 0XE0001000[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. RSTTO = 0x0
- // .. ==> 0XE0001000[6:6] = 0x00000000U
- // .. ==> MASK : 0x00000040U VAL : 0x00000000U
- // .. TXDIS = 0x0
- // .. ==> 0XE0001000[5:5] = 0x00000000U
- // .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. TXEN = 0x1
- // .. ==> 0XE0001000[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. RXDIS = 0x0
- // .. ==> 0XE0001000[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. RXEN = 0x1
- // .. ==> 0XE0001000[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. TXRES = 0x1
- // .. ==> 0XE0001000[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. RXRES = 0x1
- // .. ==> 0XE0001000[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // ..
- EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
- // .. IRMODE = 0x0
- // .. ==> 0XE0001004[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. UCLKEN = 0x0
- // .. ==> 0XE0001004[10:10] = 0x00000000U
- // .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. CHMODE = 0x0
- // .. ==> 0XE0001004[9:8] = 0x00000000U
- // .. ==> MASK : 0x00000300U VAL : 0x00000000U
- // .. NBSTOP = 0x0
- // .. ==> 0XE0001004[7:6] = 0x00000000U
- // .. ==> MASK : 0x000000C0U VAL : 0x00000000U
- // .. PAR = 0x4
- // .. ==> 0XE0001004[5:3] = 0x00000004U
- // .. ==> MASK : 0x00000038U VAL : 0x00000020U
- // .. CHRL = 0x0
- // .. ==> 0XE0001004[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. CLKS = 0x0
- // .. ==> 0XE0001004[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U),
- // .. FINISH: UART REGISTERS
- // .. START: QSPI REGISTERS
- // .. Holdb_dr = 1
- // .. ==> 0XE000D000[19:19] = 0x00000001U
- // .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // ..
- EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
- // .. FINISH: QSPI REGISTERS
- // .. START: PL POWER ON RESET REGISTERS
- // .. PCFG_POR_CNT_4K = 0
- // .. ==> 0XF8007000[29:29] = 0x00000000U
- // .. ==> MASK : 0x20000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
- // .. FINISH: PL POWER ON RESET REGISTERS
- // .. START: SMC TIMING CALCULATION REGISTER UPDATE
- // .. .. START: NAND SET CYCLE
- // .. .. FINISH: NAND SET CYCLE
- // .. .. START: OPMODE
- // .. .. FINISH: OPMODE
- // .. .. START: DIRECT COMMAND
- // .. .. FINISH: DIRECT COMMAND
- // .. .. START: SRAM/NOR CS0 SET CYCLE
- // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
- // .. .. START: DIRECT COMMAND
- // .. .. FINISH: DIRECT COMMAND
- // .. .. START: NOR CS0 BASE ADDRESS
- // .. .. FINISH: NOR CS0 BASE ADDRESS
- // .. .. START: SRAM/NOR CS1 SET CYCLE
- // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
- // .. .. START: DIRECT COMMAND
- // .. .. FINISH: DIRECT COMMAND
- // .. .. START: NOR CS1 BASE ADDRESS
- // .. .. FINISH: NOR CS1 BASE ADDRESS
- // .. .. START: USB RESET
- // .. .. .. START: USB0 RESET
- // .. .. .. .. START: DIR MODE BANK 0
- // .. .. .. .. DIRECTION_0 = 0x80
- // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U
- // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U),
- // .. .. .. .. FINISH: DIR MODE BANK 0
- // .. .. .. .. START: DIR MODE BANK 1
- // .. .. .. .. FINISH: DIR MODE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. MASK_0_LSW = 0xff7f
- // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
- // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U
- // .. .. .. .. DATA_0_LSW = 0x80
- // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
- // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. START: OUTPUT ENABLE BANK 0
- // .. .. .. .. OP_ENABLE_0 = 0x80
- // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U
- // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U),
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
- // .. .. .. .. START: OUTPUT ENABLE BANK 1
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. MASK_0_LSW = 0xff7f
- // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
- // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U
- // .. .. .. .. DATA_0_LSW = 0x0
- // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
- // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U),
- // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. START: ADD 1 MS DELAY
- // .. .. .. ..
- EMIT_MASKDELAY(0XF8F00200, 1),
- // .. .. .. .. FINISH: ADD 1 MS DELAY
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. MASK_0_LSW = 0xff7f
- // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
- // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U
- // .. .. .. .. DATA_0_LSW = 0x80
- // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
- // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: USB0 RESET
- // .. .. .. START: USB1 RESET
- // .. .. .. .. START: DIR MODE BANK 0
- // .. .. .. .. FINISH: DIR MODE BANK 0
- // .. .. .. .. START: DIR MODE BANK 1
- // .. .. .. .. FINISH: DIR MODE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. START: OUTPUT ENABLE BANK 0
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
- // .. .. .. .. START: OUTPUT ENABLE BANK 1
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. START: ADD 1 MS DELAY
- // .. .. .. ..
- EMIT_MASKDELAY(0XF8F00200, 1),
- // .. .. .. .. FINISH: ADD 1 MS DELAY
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: USB1 RESET
- // .. .. FINISH: USB RESET
- // .. .. START: ENET RESET
- // .. .. .. START: ENET0 RESET
- // .. .. .. .. START: DIR MODE BANK 0
- // .. .. .. .. DIRECTION_0 = 0x800
- // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000800U
- // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000800U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000800U),
- // .. .. .. .. FINISH: DIR MODE BANK 0
- // .. .. .. .. START: DIR MODE BANK 1
- // .. .. .. .. FINISH: DIR MODE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. MASK_0_LSW = 0xf7ff
- // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU
- // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xF7FF0000U
- // .. .. .. .. DATA_0_LSW = 0x800
- // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000800U
- // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000800U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0800U),
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. START: OUTPUT ENABLE BANK 0
- // .. .. .. .. OP_ENABLE_0 = 0x800
- // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000800U
- // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000800U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000800U),
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
- // .. .. .. .. START: OUTPUT ENABLE BANK 1
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. MASK_0_LSW = 0xf7ff
- // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU
- // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xF7FF0000U
- // .. .. .. .. DATA_0_LSW = 0x0
- // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
- // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0000U),
- // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. START: ADD 1 MS DELAY
- // .. .. .. ..
- EMIT_MASKDELAY(0XF8F00200, 1),
- // .. .. .. .. FINISH: ADD 1 MS DELAY
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. MASK_0_LSW = 0xf7ff
- // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU
- // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xF7FF0000U
- // .. .. .. .. DATA_0_LSW = 0x800
- // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000800U
- // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000800U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0800U),
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: ENET0 RESET
- // .. .. .. START: ENET1 RESET
- // .. .. .. .. START: DIR MODE BANK 0
- // .. .. .. .. FINISH: DIR MODE BANK 0
- // .. .. .. .. START: DIR MODE BANK 1
- // .. .. .. .. FINISH: DIR MODE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. START: OUTPUT ENABLE BANK 0
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
- // .. .. .. .. START: OUTPUT ENABLE BANK 1
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. START: ADD 1 MS DELAY
- // .. .. .. ..
- EMIT_MASKDELAY(0XF8F00200, 1),
- // .. .. .. .. FINISH: ADD 1 MS DELAY
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: ENET1 RESET
- // .. .. FINISH: ENET RESET
- // .. .. START: I2C RESET
- // .. .. .. START: I2C0 RESET
- // .. .. .. .. START: DIR MODE GPIO BANK0
- // .. .. .. .. DIRECTION_0 = 0x2000
- // .. .. .. .. ==> 0XE000A204[31:0] = 0x00002000U
- // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002000U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002000U),
- // .. .. .. .. FINISH: DIR MODE GPIO BANK0
- // .. .. .. .. START: DIR MODE GPIO BANK1
- // .. .. .. .. FINISH: DIR MODE GPIO BANK1
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. MASK_0_LSW = 0xdfff
- // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU
- // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xDFFF0000U
- // .. .. .. .. DATA_0_LSW = 0x2000
- // .. .. .. .. ==> 0XE000A000[15:0] = 0x00002000U
- // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00002000U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF2000U),
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. START: OUTPUT ENABLE
- // .. .. .. .. OP_ENABLE_0 = 0x2000
- // .. .. .. .. ==> 0XE000A208[31:0] = 0x00002000U
- // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002000U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002000U),
- // .. .. .. .. FINISH: OUTPUT ENABLE
- // .. .. .. .. START: OUTPUT ENABLE
- // .. .. .. .. FINISH: OUTPUT ENABLE
- // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. MASK_0_LSW = 0xdfff
- // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU
- // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xDFFF0000U
- // .. .. .. .. DATA_0_LSW = 0x0
- // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
- // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF0000U),
- // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. START: ADD 1 MS DELAY
- // .. .. .. ..
- EMIT_MASKDELAY(0XF8F00200, 1),
- // .. .. .. .. FINISH: ADD 1 MS DELAY
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. MASK_0_LSW = 0xdfff
- // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU
- // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xDFFF0000U
- // .. .. .. .. DATA_0_LSW = 0x2000
- // .. .. .. .. ==> 0XE000A000[15:0] = 0x00002000U
- // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00002000U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF2000U),
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: I2C0 RESET
- // .. .. .. START: I2C1 RESET
- // .. .. .. .. START: DIR MODE GPIO BANK0
- // .. .. .. .. FINISH: DIR MODE GPIO BANK0
- // .. .. .. .. START: DIR MODE GPIO BANK1
- // .. .. .. .. FINISH: DIR MODE GPIO BANK1
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. START: OUTPUT ENABLE
- // .. .. .. .. FINISH: OUTPUT ENABLE
- // .. .. .. .. START: OUTPUT ENABLE
- // .. .. .. .. FINISH: OUTPUT ENABLE
- // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. START: ADD 1 MS DELAY
- // .. .. .. ..
- EMIT_MASKDELAY(0XF8F00200, 1),
- // .. .. .. .. FINISH: ADD 1 MS DELAY
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: I2C1 RESET
- // .. .. FINISH: I2C RESET
- // .. .. START: NOR CHIP SELECT
- // .. .. .. START: DIR MODE BANK 0
- // .. .. .. FINISH: DIR MODE BANK 0
- // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. START: OUTPUT ENABLE BANK 0
- // .. .. .. FINISH: OUTPUT ENABLE BANK 0
- // .. .. FINISH: NOR CHIP SELECT
- // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_post_config_2_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: ENABLING LEVEL SHIFTER
- // .. USER_INP_ICT_EN_0 = 3
- // .. ==> 0XF8000900[1:0] = 0x00000003U
- // .. ==> MASK : 0x00000003U VAL : 0x00000003U
- // .. USER_INP_ICT_EN_1 = 3
- // .. ==> 0XF8000900[3:2] = 0x00000003U
- // .. ==> MASK : 0x0000000CU VAL : 0x0000000CU
- // ..
- EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
- // .. FINISH: ENABLING LEVEL SHIFTER
- // .. START: FPGA RESETS TO 0
- // .. reserved_3 = 0
- // .. ==> 0XF8000240[31:25] = 0x00000000U
- // .. ==> MASK : 0xFE000000U VAL : 0x00000000U
- // .. FPGA_ACP_RST = 0
- // .. ==> 0XF8000240[24:24] = 0x00000000U
- // .. ==> MASK : 0x01000000U VAL : 0x00000000U
- // .. FPGA_AXDS3_RST = 0
- // .. ==> 0XF8000240[23:23] = 0x00000000U
- // .. ==> MASK : 0x00800000U VAL : 0x00000000U
- // .. FPGA_AXDS2_RST = 0
- // .. ==> 0XF8000240[22:22] = 0x00000000U
- // .. ==> MASK : 0x00400000U VAL : 0x00000000U
- // .. FPGA_AXDS1_RST = 0
- // .. ==> 0XF8000240[21:21] = 0x00000000U
- // .. ==> MASK : 0x00200000U VAL : 0x00000000U
- // .. FPGA_AXDS0_RST = 0
- // .. ==> 0XF8000240[20:20] = 0x00000000U
- // .. ==> MASK : 0x00100000U VAL : 0x00000000U
- // .. reserved_2 = 0
- // .. ==> 0XF8000240[19:18] = 0x00000000U
- // .. ==> MASK : 0x000C0000U VAL : 0x00000000U
- // .. FSSW1_FPGA_RST = 0
- // .. ==> 0XF8000240[17:17] = 0x00000000U
- // .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. FSSW0_FPGA_RST = 0
- // .. ==> 0XF8000240[16:16] = 0x00000000U
- // .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. reserved_1 = 0
- // .. ==> 0XF8000240[15:14] = 0x00000000U
- // .. ==> MASK : 0x0000C000U VAL : 0x00000000U
- // .. FPGA_FMSW1_RST = 0
- // .. ==> 0XF8000240[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // .. FPGA_FMSW0_RST = 0
- // .. ==> 0XF8000240[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. FPGA_DMA3_RST = 0
- // .. ==> 0XF8000240[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. FPGA_DMA2_RST = 0
- // .. ==> 0XF8000240[10:10] = 0x00000000U
- // .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. FPGA_DMA1_RST = 0
- // .. ==> 0XF8000240[9:9] = 0x00000000U
- // .. ==> MASK : 0x00000200U VAL : 0x00000000U
- // .. FPGA_DMA0_RST = 0
- // .. ==> 0XF8000240[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. reserved = 0
- // .. ==> 0XF8000240[7:4] = 0x00000000U
- // .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. FPGA3_OUT_RST = 0
- // .. ==> 0XF8000240[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. FPGA2_OUT_RST = 0
- // .. ==> 0XF8000240[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. FPGA1_OUT_RST = 0
- // .. ==> 0XF8000240[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. FPGA0_OUT_RST = 0
- // .. ==> 0XF8000240[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
- // .. FINISH: FPGA RESETS TO 0
- // .. START: AFI REGISTERS
- // .. .. START: AFI0 REGISTERS
- // .. .. FINISH: AFI0 REGISTERS
- // .. .. START: AFI1 REGISTERS
- // .. .. FINISH: AFI1 REGISTERS
- // .. .. START: AFI2 REGISTERS
- // .. .. FINISH: AFI2 REGISTERS
- // .. .. START: AFI3 REGISTERS
- // .. .. FINISH: AFI3 REGISTERS
- // .. FINISH: AFI REGISTERS
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_debug_2_0[] = {
- // START: top
- // .. START: CROSS TRIGGER CONFIGURATIONS
- // .. .. START: UNLOCKING CTI REGISTERS
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. FINISH: UNLOCKING CTI REGISTERS
- // .. .. START: ENABLING CTI MODULES AND CHANNELS
- // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
- // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. FINISH: CROSS TRIGGER CONFIGURATIONS
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_pll_init_data_1_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: PLL SLCR REGISTERS
- // .. .. START: ARM PLL INIT
- // .. .. PLL_RES = 0x2
- // .. .. ==> 0XF8000110[7:4] = 0x00000002U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
- // .. .. PLL_CP = 0x2
- // .. .. ==> 0XF8000110[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. LOCK_CNT = 0xfa
- // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
- // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U
- // .. ..
- EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
- // .. .. .. START: UPDATE FB_DIV
- // .. .. .. PLL_FDIV = 0x28
- // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
- // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
- // .. .. .. FINISH: UPDATE FB_DIV
- // .. .. .. START: BY PASS PLL
- // .. .. .. PLL_BYPASS_FORCE = 1
- // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
- // .. .. .. FINISH: BY PASS PLL
- // .. .. .. START: ASSERT RESET
- // .. .. .. PLL_RESET = 1
- // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
- // .. .. .. FINISH: ASSERT RESET
- // .. .. .. START: DEASSERT RESET
- // .. .. .. PLL_RESET = 0
- // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
- // .. .. .. FINISH: DEASSERT RESET
- // .. .. .. START: CHECK PLL STATUS
- // .. .. .. ARM_PLL_LOCK = 1
- // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ..
- EMIT_MASKPOLL(0XF800010C, 0x00000001U),
- // .. .. .. FINISH: CHECK PLL STATUS
- // .. .. .. START: REMOVE PLL BY PASS
- // .. .. .. PLL_BYPASS_FORCE = 0
- // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
- // .. .. .. FINISH: REMOVE PLL BY PASS
- // .. .. .. SRCSEL = 0x0
- // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. .. .. DIVISOR = 0x2
- // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
- // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U
- // .. .. .. CPU_6OR4XCLKACT = 0x1
- // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
- // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U
- // .. .. .. CPU_3OR2XCLKACT = 0x1
- // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
- // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U
- // .. .. .. CPU_2XCLKACT = 0x1
- // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
- // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U
- // .. .. .. CPU_1XCLKACT = 0x1
- // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
- // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U
- // .. .. .. CPU_PERI_CLKACT = 0x1
- // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
- // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
- // .. .. FINISH: ARM PLL INIT
- // .. .. START: DDR PLL INIT
- // .. .. PLL_RES = 0x2
- // .. .. ==> 0XF8000114[7:4] = 0x00000002U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
- // .. .. PLL_CP = 0x2
- // .. .. ==> 0XF8000114[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. LOCK_CNT = 0x12c
- // .. .. ==> 0XF8000114[21:12] = 0x0000012CU
- // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U
- // .. ..
- EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
- // .. .. .. START: UPDATE FB_DIV
- // .. .. .. PLL_FDIV = 0x20
- // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
- // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
- // .. .. .. FINISH: UPDATE FB_DIV
- // .. .. .. START: BY PASS PLL
- // .. .. .. PLL_BYPASS_FORCE = 1
- // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
- // .. .. .. FINISH: BY PASS PLL
- // .. .. .. START: ASSERT RESET
- // .. .. .. PLL_RESET = 1
- // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
- // .. .. .. FINISH: ASSERT RESET
- // .. .. .. START: DEASSERT RESET
- // .. .. .. PLL_RESET = 0
- // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
- // .. .. .. FINISH: DEASSERT RESET
- // .. .. .. START: CHECK PLL STATUS
- // .. .. .. DDR_PLL_LOCK = 1
- // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. .. ..
- EMIT_MASKPOLL(0XF800010C, 0x00000002U),
- // .. .. .. FINISH: CHECK PLL STATUS
- // .. .. .. START: REMOVE PLL BY PASS
- // .. .. .. PLL_BYPASS_FORCE = 0
- // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
- // .. .. .. FINISH: REMOVE PLL BY PASS
- // .. .. .. DDR_3XCLKACT = 0x1
- // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. .. DDR_2XCLKACT = 0x1
- // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. .. .. DDR_3XCLK_DIVISOR = 0x2
- // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
- // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U
- // .. .. .. DDR_2XCLK_DIVISOR = 0x3
- // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
- // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
- // .. .. FINISH: DDR PLL INIT
- // .. .. START: IO PLL INIT
- // .. .. PLL_RES = 0xc
- // .. .. ==> 0XF8000118[7:4] = 0x0000000CU
- // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U
- // .. .. PLL_CP = 0x2
- // .. .. ==> 0XF8000118[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. LOCK_CNT = 0x145
- // .. .. ==> 0XF8000118[21:12] = 0x00000145U
- // .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U
- // .. ..
- EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U),
- // .. .. .. START: UPDATE FB_DIV
- // .. .. .. PLL_FDIV = 0x1e
- // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU
- // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U),
- // .. .. .. FINISH: UPDATE FB_DIV
- // .. .. .. START: BY PASS PLL
- // .. .. .. PLL_BYPASS_FORCE = 1
- // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
- // .. .. .. FINISH: BY PASS PLL
- // .. .. .. START: ASSERT RESET
- // .. .. .. PLL_RESET = 1
- // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
- // .. .. .. FINISH: ASSERT RESET
- // .. .. .. START: DEASSERT RESET
- // .. .. .. PLL_RESET = 0
- // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
- // .. .. .. FINISH: DEASSERT RESET
- // .. .. .. START: CHECK PLL STATUS
- // .. .. .. IO_PLL_LOCK = 1
- // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. .. ..
- EMIT_MASKPOLL(0XF800010C, 0x00000004U),
- // .. .. .. FINISH: CHECK PLL STATUS
- // .. .. .. START: REMOVE PLL BY PASS
- // .. .. .. PLL_BYPASS_FORCE = 0
- // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
- // .. .. .. FINISH: REMOVE PLL BY PASS
- // .. .. FINISH: IO PLL INIT
- // .. FINISH: PLL SLCR REGISTERS
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_clock_init_data_1_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: CLOCK CONTROL SLCR REGISTERS
- // .. CLKACT = 0x1
- // .. ==> 0XF8000128[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. DIVISOR0 = 0x23
- // .. ==> 0XF8000128[13:8] = 0x00000023U
- // .. ==> MASK : 0x00003F00U VAL : 0x00002300U
- // .. DIVISOR1 = 0x3
- // .. ==> 0XF8000128[25:20] = 0x00000003U
- // .. ==> MASK : 0x03F00000U VAL : 0x00300000U
- // ..
- EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U),
- // .. CLKACT = 0x1
- // .. ==> 0XF8000138[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000138[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
- // .. CLKACT = 0x1
- // .. ==> 0XF8000140[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000140[6:4] = 0x00000000U
- // .. ==> MASK : 0x00000070U VAL : 0x00000000U
- // .. DIVISOR = 0x8
- // .. ==> 0XF8000140[13:8] = 0x00000008U
- // .. ==> MASK : 0x00003F00U VAL : 0x00000800U
- // .. DIVISOR1 = 0x5
- // .. ==> 0XF8000140[25:20] = 0x00000005U
- // .. ==> MASK : 0x03F00000U VAL : 0x00500000U
- // ..
- EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00500801U),
- // .. CLKACT = 0x1
- // .. ==> 0XF800014C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. SRCSEL = 0x0
- // .. ==> 0XF800014C[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR = 0x5
- // .. ==> 0XF800014C[13:8] = 0x00000005U
- // .. ==> MASK : 0x00003F00U VAL : 0x00000500U
- // ..
- EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
- // .. CLKACT0 = 0x1
- // .. ==> 0XF8000150[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. CLKACT1 = 0x0
- // .. ==> 0XF8000150[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000150[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR = 0x14
- // .. ==> 0XF8000150[13:8] = 0x00000014U
- // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
- // ..
- EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U),
- // .. CLKACT0 = 0x0
- // .. ==> 0XF8000154[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. CLKACT1 = 0x1
- // .. ==> 0XF8000154[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000154[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR = 0x14
- // .. ==> 0XF8000154[13:8] = 0x00000014U
- // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
- // ..
- EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U),
- // .. CLKACT0 = 0x1
- // .. ==> 0XF800015C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. CLKACT1 = 0x0
- // .. ==> 0XF800015C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. SRCSEL = 0x0
- // .. ==> 0XF800015C[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR0 = 0xe
- // .. ==> 0XF800015C[13:8] = 0x0000000EU
- // .. ==> MASK : 0x00003F00U VAL : 0x00000E00U
- // .. DIVISOR1 = 0x3
- // .. ==> 0XF800015C[25:20] = 0x00000003U
- // .. ==> MASK : 0x03F00000U VAL : 0x00300000U
- // ..
- EMIT_MASKWRITE(0XF800015C, 0x03F03F33U ,0x00300E01U),
- // .. CAN0_MUX = 0x0
- // .. ==> 0XF8000160[5:0] = 0x00000000U
- // .. ==> MASK : 0x0000003FU VAL : 0x00000000U
- // .. CAN0_REF_SEL = 0x0
- // .. ==> 0XF8000160[6:6] = 0x00000000U
- // .. ==> MASK : 0x00000040U VAL : 0x00000000U
- // .. CAN1_MUX = 0x0
- // .. ==> 0XF8000160[21:16] = 0x00000000U
- // .. ==> MASK : 0x003F0000U VAL : 0x00000000U
- // .. CAN1_REF_SEL = 0x0
- // .. ==> 0XF8000160[22:22] = 0x00000000U
- // .. ==> MASK : 0x00400000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000160, 0x007F007FU ,0x00000000U),
- // .. CLKACT = 0x1
- // .. ==> 0XF8000168[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000168[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR = 0x5
- // .. ==> 0XF8000168[13:8] = 0x00000005U
- // .. ==> MASK : 0x00003F00U VAL : 0x00000500U
- // ..
- EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000170[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR0 = 0x14
- // .. ==> 0XF8000170[13:8] = 0x00000014U
- // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
- // .. DIVISOR1 = 0x1
- // .. ==> 0XF8000170[25:20] = 0x00000001U
- // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
- // ..
- EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00101400U),
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000180[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR0 = 0x14
- // .. ==> 0XF8000180[13:8] = 0x00000014U
- // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
- // .. DIVISOR1 = 0x1
- // .. ==> 0XF8000180[25:20] = 0x00000001U
- // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
- // ..
- EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00101400U),
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000190[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR0 = 0x14
- // .. ==> 0XF8000190[13:8] = 0x00000014U
- // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
- // .. DIVISOR1 = 0x1
- // .. ==> 0XF8000190[25:20] = 0x00000001U
- // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
- // ..
- EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101400U),
- // .. SRCSEL = 0x0
- // .. ==> 0XF80001A0[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR0 = 0x14
- // .. ==> 0XF80001A0[13:8] = 0x00000014U
- // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
- // .. DIVISOR1 = 0x1
- // .. ==> 0XF80001A0[25:20] = 0x00000001U
- // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
- // ..
- EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U),
- // .. CLK_621_TRUE = 0x1
- // .. ==> 0XF80001C4[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // ..
- EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
- // .. DMA_CPU_2XCLKACT = 0x1
- // .. ==> 0XF800012C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. USB0_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. USB1_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[3:3] = 0x00000001U
- // .. ==> MASK : 0x00000008U VAL : 0x00000008U
- // .. GEM0_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[6:6] = 0x00000001U
- // .. ==> MASK : 0x00000040U VAL : 0x00000040U
- // .. GEM1_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. SDI0_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[10:10] = 0x00000001U
- // .. ==> MASK : 0x00000400U VAL : 0x00000400U
- // .. SDI1_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. SPI0_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[14:14] = 0x00000000U
- // .. ==> MASK : 0x00004000U VAL : 0x00000000U
- // .. SPI1_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[15:15] = 0x00000000U
- // .. ==> MASK : 0x00008000U VAL : 0x00000000U
- // .. CAN0_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[16:16] = 0x00000001U
- // .. ==> MASK : 0x00010000U VAL : 0x00010000U
- // .. CAN1_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[17:17] = 0x00000000U
- // .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. I2C0_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[18:18] = 0x00000001U
- // .. ==> MASK : 0x00040000U VAL : 0x00040000U
- // .. I2C1_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[19:19] = 0x00000001U
- // .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // .. UART0_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[20:20] = 0x00000000U
- // .. ==> MASK : 0x00100000U VAL : 0x00000000U
- // .. UART1_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[21:21] = 0x00000001U
- // .. ==> MASK : 0x00200000U VAL : 0x00200000U
- // .. GPIO_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[22:22] = 0x00000001U
- // .. ==> MASK : 0x00400000U VAL : 0x00400000U
- // .. LQSPI_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[23:23] = 0x00000001U
- // .. ==> MASK : 0x00800000U VAL : 0x00800000U
- // .. SMC_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[24:24] = 0x00000001U
- // .. ==> MASK : 0x01000000U VAL : 0x01000000U
- // ..
- EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01ED044DU),
- // .. FINISH: CLOCK CONTROL SLCR REGISTERS
- // .. START: THIS SHOULD BE BLANK
- // .. FINISH: THIS SHOULD BE BLANK
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_ddr_init_data_1_0[] = {
- // START: top
- // .. START: DDR INITIALIZATION
- // .. .. START: LOCK DDR
- // .. .. reg_ddrc_soft_rstb = 0
- // .. .. ==> 0XF8006000[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_powerdown_en = 0x0
- // .. .. ==> 0XF8006000[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_ddrc_data_bus_width = 0x0
- // .. .. ==> 0XF8006000[3:2] = 0x00000000U
- // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U
- // .. .. reg_ddrc_burst8_refresh = 0x0
- // .. .. ==> 0XF8006000[6:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U
- // .. .. reg_ddrc_rdwr_idle_gap = 0x1
- // .. .. ==> 0XF8006000[13:7] = 0x00000001U
- // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U
- // .. .. reg_ddrc_dis_rd_bypass = 0x0
- // .. .. ==> 0XF8006000[14:14] = 0x00000000U
- // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_act_bypass = 0x0
- // .. .. ==> 0XF8006000[15:15] = 0x00000000U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_auto_refresh = 0x0
- // .. .. ==> 0XF8006000[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
- // .. .. FINISH: LOCK DDR
- // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81
- // .. .. ==> 0XF8006004[11:0] = 0x00000081U
- // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U
- // .. .. reg_ddrc_active_ranks = 0x1
- // .. .. ==> 0XF8006004[13:12] = 0x00000001U
- // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U
- // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
- // .. .. ==> 0XF8006004[18:14] = 0x00000000U
- // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U
- // .. .. reg_ddrc_wr_odt_block = 0x1
- // .. .. ==> 0XF8006004[20:19] = 0x00000001U
- // .. .. ==> MASK : 0x00180000U VAL : 0x00080000U
- // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0
- // .. .. ==> 0XF8006004[21:21] = 0x00000000U
- // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0
- // .. .. ==> 0XF8006004[26:22] = 0x00000000U
- // .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_open_bank = 0x0
- // .. .. ==> 0XF8006004[27:27] = 0x00000000U
- // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_4bank_ram = 0x0
- // .. .. ==> 0XF8006004[28:28] = 0x00000000U
- // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U),
- // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
- // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
- // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU
- // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
- // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
- // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U
- // .. .. reg_ddrc_hpr_xact_run_length = 0xf
- // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
- // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U
- // .. ..
- EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
- // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
- // .. .. ==> 0XF800600C[10:0] = 0x00000001U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U
- // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
- // .. .. ==> 0XF800600C[21:11] = 0x00000002U
- // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U
- // .. .. reg_ddrc_lpr_xact_run_length = 0x8
- // .. .. ==> 0XF800600C[25:22] = 0x00000008U
- // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U
- // .. ..
- EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
- // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
- // .. .. ==> 0XF8006010[10:0] = 0x00000001U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U
- // .. .. reg_ddrc_w_xact_run_length = 0x8
- // .. .. ==> 0XF8006010[14:11] = 0x00000008U
- // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U
- // .. .. reg_ddrc_w_max_starve_x32 = 0x2
- // .. .. ==> 0XF8006010[25:15] = 0x00000002U
- // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U
- // .. ..
- EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
- // .. .. reg_ddrc_t_rc = 0x1b
- // .. .. ==> 0XF8006014[5:0] = 0x0000001BU
- // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001BU
- // .. .. reg_ddrc_t_rfc_min = 0x56
- // .. .. ==> 0XF8006014[13:6] = 0x00000056U
- // .. .. ==> MASK : 0x00003FC0U VAL : 0x00001580U
- // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
- // .. .. ==> 0XF8006014[20:14] = 0x00000010U
- // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U
- // .. ..
- EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004159BU),
- // .. .. reg_ddrc_wr2pre = 0x12
- // .. .. ==> 0XF8006018[4:0] = 0x00000012U
- // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U
- // .. .. reg_ddrc_powerdown_to_x32 = 0x6
- // .. .. ==> 0XF8006018[9:5] = 0x00000006U
- // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U
- // .. .. reg_ddrc_t_faw = 0x10
- // .. .. ==> 0XF8006018[15:10] = 0x00000010U
- // .. .. ==> MASK : 0x0000FC00U VAL : 0x00004000U
- // .. .. reg_ddrc_t_ras_max = 0x24
- // .. .. ==> 0XF8006018[21:16] = 0x00000024U
- // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U
- // .. .. reg_ddrc_t_ras_min = 0x14
- // .. .. ==> 0XF8006018[26:22] = 0x00000014U
- // .. .. ==> MASK : 0x07C00000U VAL : 0x05000000U
- // .. .. reg_ddrc_t_cke = 0x4
- // .. .. ==> 0XF8006018[31:28] = 0x00000004U
- // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x452440D2U),
- // .. .. reg_ddrc_write_latency = 0x5
- // .. .. ==> 0XF800601C[4:0] = 0x00000005U
- // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U
- // .. .. reg_ddrc_rd2wr = 0x7
- // .. .. ==> 0XF800601C[9:5] = 0x00000007U
- // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U
- // .. .. reg_ddrc_wr2rd = 0xe
- // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
- // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U
- // .. .. reg_ddrc_t_xp = 0x4
- // .. .. ==> 0XF800601C[19:15] = 0x00000004U
- // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U
- // .. .. reg_ddrc_pad_pd = 0x0
- // .. .. ==> 0XF800601C[22:20] = 0x00000000U
- // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U
- // .. .. reg_ddrc_rd2pre = 0x4
- // .. .. ==> 0XF800601C[27:23] = 0x00000004U
- // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U
- // .. .. reg_ddrc_t_rcd = 0x7
- // .. .. ==> 0XF800601C[31:28] = 0x00000007U
- // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U
- // .. ..
- EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
- // .. .. reg_ddrc_t_ccd = 0x4
- // .. .. ==> 0XF8006020[4:2] = 0x00000004U
- // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U
- // .. .. reg_ddrc_t_rrd = 0x4
- // .. .. ==> 0XF8006020[7:5] = 0x00000004U
- // .. .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. .. reg_ddrc_refresh_margin = 0x2
- // .. .. ==> 0XF8006020[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. reg_ddrc_t_rp = 0x7
- // .. .. ==> 0XF8006020[15:12] = 0x00000007U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U
- // .. .. reg_ddrc_refresh_to_x32 = 0x8
- // .. .. ==> 0XF8006020[20:16] = 0x00000008U
- // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U
- // .. .. reg_ddrc_sdram = 0x1
- // .. .. ==> 0XF8006020[21:21] = 0x00000001U
- // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U
- // .. .. reg_ddrc_mobile = 0x0
- // .. .. ==> 0XF8006020[22:22] = 0x00000000U
- // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U
- // .. .. reg_ddrc_clock_stop_en = 0x0
- // .. .. ==> 0XF8006020[23:23] = 0x00000000U
- // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U
- // .. .. reg_ddrc_read_latency = 0x7
- // .. .. ==> 0XF8006020[28:24] = 0x00000007U
- // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U
- // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
- // .. .. ==> 0XF8006020[29:29] = 0x00000001U
- // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U
- // .. .. reg_ddrc_dis_pad_pd = 0x0
- // .. .. ==> 0XF8006020[30:30] = 0x00000000U
- // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U
- // .. .. reg_ddrc_loopback = 0x0
- // .. .. ==> 0XF8006020[31:31] = 0x00000000U
- // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x27287290U),
- // .. .. reg_ddrc_en_2t_timing_mode = 0x0
- // .. .. ==> 0XF8006024[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_prefer_write = 0x0
- // .. .. ==> 0XF8006024[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_ddrc_max_rank_rd = 0xf
- // .. .. ==> 0XF8006024[5:2] = 0x0000000FU
- // .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU
- // .. .. reg_ddrc_mr_wr = 0x0
- // .. .. ==> 0XF8006024[6:6] = 0x00000000U
- // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_addr = 0x0
- // .. .. ==> 0XF8006024[8:7] = 0x00000000U
- // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_data = 0x0
- // .. .. ==> 0XF8006024[24:9] = 0x00000000U
- // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U
- // .. .. ddrc_reg_mr_wr_busy = 0x0
- // .. .. ==> 0XF8006024[25:25] = 0x00000000U
- // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_type = 0x0
- // .. .. ==> 0XF8006024[26:26] = 0x00000000U
- // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_rdata_valid = 0x0
- // .. .. ==> 0XF8006024[27:27] = 0x00000000U
- // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU),
- // .. .. reg_ddrc_final_wait_x32 = 0x7
- // .. .. ==> 0XF8006028[6:0] = 0x00000007U
- // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U
- // .. .. reg_ddrc_pre_ocd_x32 = 0x0
- // .. .. ==> 0XF8006028[10:7] = 0x00000000U
- // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U
- // .. .. reg_ddrc_t_mrd = 0x4
- // .. .. ==> 0XF8006028[13:11] = 0x00000004U
- // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U
- // .. ..
- EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
- // .. .. reg_ddrc_emr2 = 0x8
- // .. .. ==> 0XF800602C[15:0] = 0x00000008U
- // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U
- // .. .. reg_ddrc_emr3 = 0x0
- // .. .. ==> 0XF800602C[31:16] = 0x00000000U
- // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
- // .. .. reg_ddrc_mr = 0x930
- // .. .. ==> 0XF8006030[15:0] = 0x00000930U
- // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U
- // .. .. reg_ddrc_emr = 0x4
- // .. .. ==> 0XF8006030[31:16] = 0x00000004U
- // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U
- // .. ..
- EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
- // .. .. reg_ddrc_burst_rdwr = 0x4
- // .. .. ==> 0XF8006034[3:0] = 0x00000004U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U
- // .. .. reg_ddrc_pre_cke_x1024 = 0x105
- // .. .. ==> 0XF8006034[13:4] = 0x00000105U
- // .. .. ==> MASK : 0x00003FF0U VAL : 0x00001050U
- // .. .. reg_ddrc_post_cke_x1024 = 0x1
- // .. .. ==> 0XF8006034[25:16] = 0x00000001U
- // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U
- // .. .. reg_ddrc_burstchop = 0x0
- // .. .. ==> 0XF8006034[28:28] = 0x00000000U
- // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U),
- // .. .. reg_ddrc_force_low_pri_n = 0x0
- // .. .. ==> 0XF8006038[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_dq = 0x0
- // .. .. ==> 0XF8006038[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_debug_mode = 0x0
- // .. .. ==> 0XF8006038[6:6] = 0x00000000U
- // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U
- // .. .. reg_phy_wr_level_start = 0x0
- // .. .. ==> 0XF8006038[7:7] = 0x00000000U
- // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. .. reg_phy_rd_level_start = 0x0
- // .. .. ==> 0XF8006038[8:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. .. reg_phy_dq0_wait_t = 0x0
- // .. .. ==> 0XF8006038[12:9] = 0x00000000U
- // .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U),
- // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
- // .. .. ==> 0XF800603C[3:0] = 0x00000007U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U
- // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
- // .. .. ==> 0XF800603C[7:4] = 0x00000007U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U
- // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
- // .. .. ==> 0XF800603C[11:8] = 0x00000007U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U
- // .. .. reg_ddrc_addrmap_col_b5 = 0x0
- // .. .. ==> 0XF800603C[15:12] = 0x00000000U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b6 = 0x0
- // .. .. ==> 0XF800603C[19:16] = 0x00000000U
- // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
- // .. .. reg_ddrc_addrmap_col_b2 = 0x0
- // .. .. ==> 0XF8006040[3:0] = 0x00000000U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b3 = 0x0
- // .. .. ==> 0XF8006040[7:4] = 0x00000000U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b4 = 0x0
- // .. .. ==> 0XF8006040[11:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b7 = 0x0
- // .. .. ==> 0XF8006040[15:12] = 0x00000000U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b8 = 0x0
- // .. .. ==> 0XF8006040[19:16] = 0x00000000U
- // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b9 = 0xf
- // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
- // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U
- // .. .. reg_ddrc_addrmap_col_b10 = 0xf
- // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
- // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U
- // .. .. reg_ddrc_addrmap_col_b11 = 0xf
- // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
- // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
- // .. .. reg_ddrc_addrmap_row_b0 = 0x6
- // .. .. ==> 0XF8006044[3:0] = 0x00000006U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U
- // .. .. reg_ddrc_addrmap_row_b1 = 0x6
- // .. .. ==> 0XF8006044[7:4] = 0x00000006U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U
- // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
- // .. .. ==> 0XF8006044[11:8] = 0x00000006U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U
- // .. .. reg_ddrc_addrmap_row_b12 = 0x6
- // .. .. ==> 0XF8006044[15:12] = 0x00000006U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U
- // .. .. reg_ddrc_addrmap_row_b13 = 0x6
- // .. .. ==> 0XF8006044[19:16] = 0x00000006U
- // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U
- // .. .. reg_ddrc_addrmap_row_b14 = 0x6
- // .. .. ==> 0XF8006044[23:20] = 0x00000006U
- // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U
- // .. .. reg_ddrc_addrmap_row_b15 = 0xf
- // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
- // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U),
- // .. .. reg_ddrc_rank0_rd_odt = 0x0
- // .. .. ==> 0XF8006048[2:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U
- // .. .. reg_ddrc_rank0_wr_odt = 0x1
- // .. .. ==> 0XF8006048[5:3] = 0x00000001U
- // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U
- // .. .. reg_ddrc_rank1_rd_odt = 0x1
- // .. .. ==> 0XF8006048[8:6] = 0x00000001U
- // .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U
- // .. .. reg_ddrc_rank1_wr_odt = 0x1
- // .. .. ==> 0XF8006048[11:9] = 0x00000001U
- // .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. .. reg_phy_rd_local_odt = 0x0
- // .. .. ==> 0XF8006048[13:12] = 0x00000000U
- // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U
- // .. .. reg_phy_wr_local_odt = 0x3
- // .. .. ==> 0XF8006048[15:14] = 0x00000003U
- // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U
- // .. .. reg_phy_idle_local_odt = 0x3
- // .. .. ==> 0XF8006048[17:16] = 0x00000003U
- // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U
- // .. .. reg_ddrc_rank2_rd_odt = 0x0
- // .. .. ==> 0XF8006048[20:18] = 0x00000000U
- // .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U
- // .. .. reg_ddrc_rank2_wr_odt = 0x0
- // .. .. ==> 0XF8006048[23:21] = 0x00000000U
- // .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U
- // .. .. reg_ddrc_rank3_rd_odt = 0x0
- // .. .. ==> 0XF8006048[26:24] = 0x00000000U
- // .. .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. .. reg_ddrc_rank3_wr_odt = 0x0
- // .. .. ==> 0XF8006048[29:27] = 0x00000000U
- // .. .. ==> MASK : 0x38000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U),
- // .. .. reg_phy_rd_cmd_to_data = 0x0
- // .. .. ==> 0XF8006050[3:0] = 0x00000000U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
- // .. .. reg_phy_wr_cmd_to_data = 0x0
- // .. .. ==> 0XF8006050[7:4] = 0x00000000U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. .. reg_phy_rdc_we_to_re_delay = 0x8
- // .. .. ==> 0XF8006050[11:8] = 0x00000008U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U
- // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
- // .. .. ==> 0XF8006050[15:15] = 0x00000000U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
- // .. .. reg_phy_use_fixed_re = 0x1
- // .. .. ==> 0XF8006050[16:16] = 0x00000001U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U
- // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
- // .. .. ==> 0XF8006050[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
- // .. .. ==> 0XF8006050[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_phy_clk_stall_level = 0x0
- // .. .. ==> 0XF8006050[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
- // .. .. ==> 0XF8006050[27:24] = 0x00000007U
- // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U
- // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
- // .. .. ==> 0XF8006050[31:28] = 0x00000007U
- // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
- // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1
- // .. .. ==> 0XF8006058[7:0] = 0x00000001U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U
- // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1
- // .. .. ==> 0XF8006058[15:8] = 0x00000001U
- // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U
- // .. .. reg_ddrc_dis_dll_calib = 0x0
- // .. .. ==> 0XF8006058[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U),
- // .. .. reg_ddrc_rd_odt_delay = 0x3
- // .. .. ==> 0XF800605C[3:0] = 0x00000003U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U
- // .. .. reg_ddrc_wr_odt_delay = 0x0
- // .. .. ==> 0XF800605C[7:4] = 0x00000000U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. .. reg_ddrc_rd_odt_hold = 0x0
- // .. .. ==> 0XF800605C[11:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U
- // .. .. reg_ddrc_wr_odt_hold = 0x5
- // .. .. ==> 0XF800605C[15:12] = 0x00000005U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U
- // .. ..
- EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
- // .. .. reg_ddrc_pageclose = 0x0
- // .. .. ==> 0XF8006060[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_lpr_num_entries = 0x1f
- // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
- // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU
- // .. .. reg_ddrc_auto_pre_en = 0x0
- // .. .. ==> 0XF8006060[7:7] = 0x00000000U
- // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. .. reg_ddrc_refresh_update_level = 0x0
- // .. .. ==> 0XF8006060[8:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_wc = 0x0
- // .. .. ==> 0XF8006060[9:9] = 0x00000000U
- // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_collision_page_opt = 0x0
- // .. .. ==> 0XF8006060[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_ddrc_selfref_en = 0x0
- // .. .. ==> 0XF8006060[12:12] = 0x00000000U
- // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
- // .. .. reg_ddrc_go2critical_hysteresis = 0x0
- // .. .. ==> 0XF8006064[12:5] = 0x00000000U
- // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U
- // .. .. reg_arb_go2critical_en = 0x1
- // .. .. ==> 0XF8006064[17:17] = 0x00000001U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U
- // .. ..
- EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
- // .. .. reg_ddrc_wrlvl_ww = 0x41
- // .. .. ==> 0XF8006068[7:0] = 0x00000041U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U
- // .. .. reg_ddrc_rdlvl_rr = 0x41
- // .. .. ==> 0XF8006068[15:8] = 0x00000041U
- // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U
- // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
- // .. .. ==> 0XF8006068[25:16] = 0x00000028U
- // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U
- // .. ..
- EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
- // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
- // .. .. ==> 0XF800606C[7:0] = 0x00000010U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U
- // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
- // .. .. ==> 0XF800606C[15:8] = 0x00000016U
- // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U
- // .. ..
- EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
- // .. .. refresh_timer0_start_value_x32 = 0x0
- // .. .. ==> 0XF80060A0[11:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U
- // .. .. refresh_timer1_start_value_x32 = 0x8
- // .. .. ==> 0XF80060A0[23:12] = 0x00000008U
- // .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U
- // .. ..
- EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U),
- // .. .. reg_ddrc_dis_auto_zq = 0x0
- // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_ddr3 = 0x1
- // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. .. reg_ddrc_t_mod = 0x200
- // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
- // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U
- // .. .. reg_ddrc_t_zq_long_nop = 0x200
- // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
- // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U
- // .. .. reg_ddrc_t_zq_short_nop = 0x40
- // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
- // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
- // .. .. t_zq_short_interval_x1024 = 0xcb73
- // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U
- // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U
- // .. .. dram_rstn_x1024 = 0x69
- // .. .. ==> 0XF80060A8[27:20] = 0x00000069U
- // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U
- // .. ..
- EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
- // .. .. deeppowerdown_en = 0x0
- // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. deeppowerdown_to_x1024 = 0xff
- // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
- // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU
- // .. ..
- EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
- // .. .. dfi_wrlvl_max_x1024 = 0xfff
- // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
- // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU
- // .. .. dfi_rdlvl_max_x1024 = 0xfff
- // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
- // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U
- // .. .. ddrc_reg_twrlvl_max_error = 0x0
- // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
- // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U
- // .. .. ddrc_reg_trdlvl_max_error = 0x0
- // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
- // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
- // .. .. reg_ddrc_dfi_wr_level_en = 0x1
- // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
- // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U
- // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
- // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
- // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U
- // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
- // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
- // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
- // .. .. reg_ddrc_2t_delay = 0x0
- // .. .. ==> 0XF80060B4[8:0] = 0x00000000U
- // .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U
- // .. .. reg_ddrc_skip_ocd = 0x1
- // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
- // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U
- // .. .. reg_ddrc_dis_pre_bypass = 0x0
- // .. .. ==> 0XF80060B4[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U),
- // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
- // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
- // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U
- // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
- // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
- // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U
- // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
- // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
- // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U
- // .. ..
- EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
- // .. .. START: RESET ECC ERROR
- // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1
- // .. .. ==> 0XF80060C4[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. Clear_Correctable_DRAM_ECC_error = 1
- // .. .. ==> 0XF80060C4[1:1] = 0x00000001U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. ..
- EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U),
- // .. .. FINISH: RESET ECC ERROR
- // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
- // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
- // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
- // .. .. CORR_ECC_LOG_VALID = 0x0
- // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. ECC_CORRECTED_BIT_NUM = 0x0
- // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
- // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
- // .. .. UNCORR_ECC_LOG_VALID = 0x0
- // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
- // .. .. STAT_NUM_CORR_ERR = 0x0
- // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
- // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U
- // .. .. STAT_NUM_UNCORR_ERR = 0x0
- // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
- // .. .. reg_ddrc_ecc_mode = 0x0
- // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_scrub = 0x1
- // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U
- // .. ..
- EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
- // .. .. reg_phy_dif_on = 0x0
- // .. .. ==> 0XF8006114[3:0] = 0x00000000U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
- // .. .. reg_phy_dif_off = 0x0
- // .. .. ==> 0XF8006114[7:4] = 0x00000000U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
- // .. .. reg_phy_data_slice_in_use = 0x1
- // .. .. ==> 0XF8006118[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_phy_rdlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006118[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_inc_mode = 0x0
- // .. .. ==> 0XF8006118[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_wrlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006118[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_tx = 0x0
- // .. .. ==> 0XF8006118[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_rx = 0x0
- // .. .. ==> 0XF8006118[5:5] = 0x00000000U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. .. reg_phy_bist_shift_dq = 0x0
- // .. .. ==> 0XF8006118[14:6] = 0x00000000U
- // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. .. reg_phy_bist_err_clr = 0x0
- // .. .. ==> 0XF8006118[23:15] = 0x00000000U
- // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. .. reg_phy_dq_offset = 0x40
- // .. .. ==> 0XF8006118[30:24] = 0x00000040U
- // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U),
- // .. .. reg_phy_data_slice_in_use = 0x1
- // .. .. ==> 0XF800611C[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_phy_rdlvl_inc_mode = 0x0
- // .. .. ==> 0XF800611C[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_inc_mode = 0x0
- // .. .. ==> 0XF800611C[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_wrlvl_inc_mode = 0x0
- // .. .. ==> 0XF800611C[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_tx = 0x0
- // .. .. ==> 0XF800611C[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_rx = 0x0
- // .. .. ==> 0XF800611C[5:5] = 0x00000000U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. .. reg_phy_bist_shift_dq = 0x0
- // .. .. ==> 0XF800611C[14:6] = 0x00000000U
- // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. .. reg_phy_bist_err_clr = 0x0
- // .. .. ==> 0XF800611C[23:15] = 0x00000000U
- // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. .. reg_phy_dq_offset = 0x40
- // .. .. ==> 0XF800611C[30:24] = 0x00000040U
- // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U),
- // .. .. reg_phy_data_slice_in_use = 0x1
- // .. .. ==> 0XF8006120[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_phy_rdlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006120[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_inc_mode = 0x0
- // .. .. ==> 0XF8006120[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_wrlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006120[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_tx = 0x0
- // .. .. ==> 0XF8006120[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_rx = 0x0
- // .. .. ==> 0XF8006120[5:5] = 0x00000000U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. .. reg_phy_bist_shift_dq = 0x0
- // .. .. ==> 0XF8006120[14:6] = 0x00000000U
- // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. .. reg_phy_bist_err_clr = 0x0
- // .. .. ==> 0XF8006120[23:15] = 0x00000000U
- // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. .. reg_phy_dq_offset = 0x40
- // .. .. ==> 0XF8006120[30:24] = 0x00000040U
- // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U),
- // .. .. reg_phy_data_slice_in_use = 0x1
- // .. .. ==> 0XF8006124[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_phy_rdlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006124[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_inc_mode = 0x0
- // .. .. ==> 0XF8006124[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_wrlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006124[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_tx = 0x0
- // .. .. ==> 0XF8006124[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_rx = 0x0
- // .. .. ==> 0XF8006124[5:5] = 0x00000000U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. .. reg_phy_bist_shift_dq = 0x0
- // .. .. ==> 0XF8006124[14:6] = 0x00000000U
- // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. .. reg_phy_bist_err_clr = 0x0
- // .. .. ==> 0XF8006124[23:15] = 0x00000000U
- // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. .. reg_phy_dq_offset = 0x40
- // .. .. ==> 0XF8006124[30:24] = 0x00000040U
- // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U),
- // .. .. reg_phy_wrlvl_init_ratio = 0x1d
- // .. .. ==> 0XF800612C[9:0] = 0x0000001DU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x0000001DU
- // .. .. reg_phy_gatelvl_init_ratio = 0xf2
- // .. .. ==> 0XF800612C[19:10] = 0x000000F2U
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x0003C800U
- // .. ..
- EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0003C81DU),
- // .. .. reg_phy_wrlvl_init_ratio = 0x12
- // .. .. ==> 0XF8006130[9:0] = 0x00000012U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000012U
- // .. .. reg_phy_gatelvl_init_ratio = 0xd8
- // .. .. ==> 0XF8006130[19:10] = 0x000000D8U
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x00036000U
- // .. ..
- EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00036012U),
- // .. .. reg_phy_wrlvl_init_ratio = 0xc
- // .. .. ==> 0XF8006134[9:0] = 0x0000000CU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x0000000CU
- // .. .. reg_phy_gatelvl_init_ratio = 0xde
- // .. .. ==> 0XF8006134[19:10] = 0x000000DEU
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x00037800U
- // .. ..
- EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0003780CU),
- // .. .. reg_phy_wrlvl_init_ratio = 0x21
- // .. .. ==> 0XF8006138[9:0] = 0x00000021U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000021U
- // .. .. reg_phy_gatelvl_init_ratio = 0xee
- // .. .. ==> 0XF8006138[19:10] = 0x000000EEU
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x0003B800U
- // .. ..
- EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0003B821U),
- // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. .. ==> 0XF8006140[9:0] = 0x00000035U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. .. reg_phy_rd_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006140[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006140[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
- // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. .. ==> 0XF8006144[9:0] = 0x00000035U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. .. reg_phy_rd_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006144[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006144[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
- // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. .. ==> 0XF8006148[9:0] = 0x00000035U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. .. reg_phy_rd_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006148[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006148[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
- // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. .. ==> 0XF800614C[9:0] = 0x00000035U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. .. reg_phy_rd_dqs_slave_force = 0x0
- // .. .. ==> 0XF800614C[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. .. ==> 0XF800614C[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
- // .. .. reg_phy_wr_dqs_slave_ratio = 0x9d
- // .. .. ==> 0XF8006154[9:0] = 0x0000009DU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x0000009DU
- // .. .. reg_phy_wr_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006154[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006154[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x0000009DU),
- // .. .. reg_phy_wr_dqs_slave_ratio = 0x92
- // .. .. ==> 0XF8006158[9:0] = 0x00000092U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000092U
- // .. .. reg_phy_wr_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006158[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006158[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000092U),
- // .. .. reg_phy_wr_dqs_slave_ratio = 0x8c
- // .. .. ==> 0XF800615C[9:0] = 0x0000008CU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x0000008CU
- // .. .. reg_phy_wr_dqs_slave_force = 0x0
- // .. .. ==> 0XF800615C[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. .. ==> 0XF800615C[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x0000008CU),
- // .. .. reg_phy_wr_dqs_slave_ratio = 0xa1
- // .. .. ==> 0XF8006160[9:0] = 0x000000A1U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000000A1U
- // .. .. reg_phy_wr_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006160[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006160[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x000000A1U),
- // .. .. reg_phy_fifo_we_slave_ratio = 0x147
- // .. .. ==> 0XF8006168[10:0] = 0x00000147U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x00000147U
- // .. .. reg_phy_fifo_we_in_force = 0x0
- // .. .. ==> 0XF8006168[11:11] = 0x00000000U
- // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. .. reg_phy_fifo_we_in_delay = 0x0
- // .. .. ==> 0XF8006168[20:12] = 0x00000000U
- // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000147U),
- // .. .. reg_phy_fifo_we_slave_ratio = 0x12d
- // .. .. ==> 0XF800616C[10:0] = 0x0000012DU
- // .. .. ==> MASK : 0x000007FFU VAL : 0x0000012DU
- // .. .. reg_phy_fifo_we_in_force = 0x0
- // .. .. ==> 0XF800616C[11:11] = 0x00000000U
- // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. .. reg_phy_fifo_we_in_delay = 0x0
- // .. .. ==> 0XF800616C[20:12] = 0x00000000U
- // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x0000012DU),
- // .. .. reg_phy_fifo_we_slave_ratio = 0x133
- // .. .. ==> 0XF8006170[10:0] = 0x00000133U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x00000133U
- // .. .. reg_phy_fifo_we_in_force = 0x0
- // .. .. ==> 0XF8006170[11:11] = 0x00000000U
- // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. .. reg_phy_fifo_we_in_delay = 0x0
- // .. .. ==> 0XF8006170[20:12] = 0x00000000U
- // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000133U),
- // .. .. reg_phy_fifo_we_slave_ratio = 0x143
- // .. .. ==> 0XF8006174[10:0] = 0x00000143U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x00000143U
- // .. .. reg_phy_fifo_we_in_force = 0x0
- // .. .. ==> 0XF8006174[11:11] = 0x00000000U
- // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. .. reg_phy_fifo_we_in_delay = 0x0
- // .. .. ==> 0XF8006174[20:12] = 0x00000000U
- // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000143U),
- // .. .. reg_phy_wr_data_slave_ratio = 0xdd
- // .. .. ==> 0XF800617C[9:0] = 0x000000DDU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000000DDU
- // .. .. reg_phy_wr_data_slave_force = 0x0
- // .. .. ==> 0XF800617C[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_data_slave_delay = 0x0
- // .. .. ==> 0XF800617C[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000DDU),
- // .. .. reg_phy_wr_data_slave_ratio = 0xd2
- // .. .. ==> 0XF8006180[9:0] = 0x000000D2U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000000D2U
- // .. .. reg_phy_wr_data_slave_force = 0x0
- // .. .. ==> 0XF8006180[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_data_slave_delay = 0x0
- // .. .. ==> 0XF8006180[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000D2U),
- // .. .. reg_phy_wr_data_slave_ratio = 0xcc
- // .. .. ==> 0XF8006184[9:0] = 0x000000CCU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000000CCU
- // .. .. reg_phy_wr_data_slave_force = 0x0
- // .. .. ==> 0XF8006184[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_data_slave_delay = 0x0
- // .. .. ==> 0XF8006184[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000CCU),
- // .. .. reg_phy_wr_data_slave_ratio = 0xe1
- // .. .. ==> 0XF8006188[9:0] = 0x000000E1U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000000E1U
- // .. .. reg_phy_wr_data_slave_force = 0x0
- // .. .. ==> 0XF8006188[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_data_slave_delay = 0x0
- // .. .. ==> 0XF8006188[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000E1U),
- // .. .. reg_phy_loopback = 0x0
- // .. .. ==> 0XF8006190[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_phy_bl2 = 0x0
- // .. .. ==> 0XF8006190[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_at_spd_atpg = 0x0
- // .. .. ==> 0XF8006190[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_bist_enable = 0x0
- // .. .. ==> 0XF8006190[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_bist_force_err = 0x0
- // .. .. ==> 0XF8006190[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. reg_phy_bist_mode = 0x0
- // .. .. ==> 0XF8006190[6:5] = 0x00000000U
- // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. .. reg_phy_invert_clkout = 0x1
- // .. .. ==> 0XF8006190[7:7] = 0x00000001U
- // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0
- // .. .. ==> 0XF8006190[8:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. .. reg_phy_sel_logic = 0x0
- // .. .. ==> 0XF8006190[9:9] = 0x00000000U
- // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U
- // .. .. reg_phy_ctrl_slave_ratio = 0x100
- // .. .. ==> 0XF8006190[19:10] = 0x00000100U
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U
- // .. .. reg_phy_ctrl_slave_force = 0x0
- // .. .. ==> 0XF8006190[20:20] = 0x00000000U
- // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U
- // .. .. reg_phy_ctrl_slave_delay = 0x0
- // .. .. ==> 0XF8006190[27:21] = 0x00000000U
- // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U
- // .. .. reg_phy_use_rank0_delays = 0x1
- // .. .. ==> 0XF8006190[28:28] = 0x00000001U
- // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
- // .. .. reg_phy_lpddr = 0x0
- // .. .. ==> 0XF8006190[29:29] = 0x00000000U
- // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U
- // .. .. reg_phy_cmd_latency = 0x0
- // .. .. ==> 0XF8006190[30:30] = 0x00000000U
- // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U
- // .. .. reg_phy_int_lpbk = 0x0
- // .. .. ==> 0XF8006190[31:31] = 0x00000000U
- // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U),
- // .. .. reg_phy_wr_rl_delay = 0x2
- // .. .. ==> 0XF8006194[4:0] = 0x00000002U
- // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U
- // .. .. reg_phy_rd_rl_delay = 0x4
- // .. .. ==> 0XF8006194[9:5] = 0x00000004U
- // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U
- // .. .. reg_phy_dll_lock_diff = 0xf
- // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
- // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U
- // .. .. reg_phy_use_wr_level = 0x1
- // .. .. ==> 0XF8006194[14:14] = 0x00000001U
- // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U
- // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
- // .. .. ==> 0XF8006194[15:15] = 0x00000001U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U
- // .. .. reg_phy_use_rd_data_eye_level = 0x1
- // .. .. ==> 0XF8006194[16:16] = 0x00000001U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U
- // .. .. reg_phy_dis_calib_rst = 0x0
- // .. .. ==> 0XF8006194[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_phy_ctrl_slave_delay = 0x0
- // .. .. ==> 0XF8006194[19:18] = 0x00000000U
- // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
- // .. .. reg_arb_page_addr_mask = 0x0
- // .. .. ==> 0XF8006204[31:0] = 0x00000000U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
- // .. .. reg_arb_pri_wr_portn = 0x3ff
- // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_wr_portn = 0x0
- // .. .. ==> 0XF8006208[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. .. ==> 0XF8006208[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. .. ==> 0XF8006208[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_dis_rmw_portn = 0x1
- // .. .. ==> 0XF8006208[19:19] = 0x00000001U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // .. ..
- EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU),
- // .. .. reg_arb_pri_wr_portn = 0x3ff
- // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_wr_portn = 0x0
- // .. .. ==> 0XF800620C[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. .. ==> 0XF800620C[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. .. ==> 0XF800620C[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_dis_rmw_portn = 0x1
- // .. .. ==> 0XF800620C[19:19] = 0x00000001U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // .. ..
- EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU),
- // .. .. reg_arb_pri_wr_portn = 0x3ff
- // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_wr_portn = 0x0
- // .. .. ==> 0XF8006210[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. .. ==> 0XF8006210[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. .. ==> 0XF8006210[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_dis_rmw_portn = 0x1
- // .. .. ==> 0XF8006210[19:19] = 0x00000001U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // .. ..
- EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU),
- // .. .. reg_arb_pri_wr_portn = 0x3ff
- // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_wr_portn = 0x0
- // .. .. ==> 0XF8006214[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. .. ==> 0XF8006214[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. .. ==> 0XF8006214[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_dis_rmw_portn = 0x1
- // .. .. ==> 0XF8006214[19:19] = 0x00000001U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // .. ..
- EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU),
- // .. .. reg_arb_pri_rd_portn = 0x3ff
- // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_rd_portn = 0x0
- // .. .. ==> 0XF8006218[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. .. ==> 0XF8006218[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. .. ==> 0XF8006218[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_set_hpr_rd_portn = 0x0
- // .. .. ==> 0XF8006218[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
- // .. .. reg_arb_pri_rd_portn = 0x3ff
- // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_rd_portn = 0x0
- // .. .. ==> 0XF800621C[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. .. ==> 0XF800621C[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. .. ==> 0XF800621C[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_set_hpr_rd_portn = 0x0
- // .. .. ==> 0XF800621C[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
- // .. .. reg_arb_pri_rd_portn = 0x3ff
- // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_rd_portn = 0x0
- // .. .. ==> 0XF8006220[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. .. ==> 0XF8006220[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. .. ==> 0XF8006220[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_set_hpr_rd_portn = 0x0
- // .. .. ==> 0XF8006220[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
- // .. .. reg_arb_pri_rd_portn = 0x3ff
- // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_rd_portn = 0x0
- // .. .. ==> 0XF8006224[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. .. ==> 0XF8006224[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. .. ==> 0XF8006224[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_set_hpr_rd_portn = 0x0
- // .. .. ==> 0XF8006224[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
- // .. .. reg_ddrc_lpddr2 = 0x0
- // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_per_bank_refresh = 0x0
- // .. .. ==> 0XF80062A8[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_ddrc_derate_enable = 0x0
- // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_ddrc_mr4_margin = 0x0
- // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U),
- // .. .. reg_ddrc_mr4_read_interval = 0x0
- // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
- // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
- // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U
- // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
- // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
- // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U
- // .. .. reg_ddrc_t_mrw = 0x5
- // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
- // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U
- // .. ..
- EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
- // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8
- // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U
- // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
- // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
- // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U
- // .. ..
- EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
- // .. .. START: POLL ON DCI STATUS
- // .. .. DONE = 1
- // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
- // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // .. ..
- EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
- // .. .. FINISH: POLL ON DCI STATUS
- // .. .. START: UNLOCK DDR
- // .. .. reg_ddrc_soft_rstb = 0x1
- // .. .. ==> 0XF8006000[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_ddrc_powerdown_en = 0x0
- // .. .. ==> 0XF8006000[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_ddrc_data_bus_width = 0x0
- // .. .. ==> 0XF8006000[3:2] = 0x00000000U
- // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U
- // .. .. reg_ddrc_burst8_refresh = 0x0
- // .. .. ==> 0XF8006000[6:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U
- // .. .. reg_ddrc_rdwr_idle_gap = 1
- // .. .. ==> 0XF8006000[13:7] = 0x00000001U
- // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U
- // .. .. reg_ddrc_dis_rd_bypass = 0x0
- // .. .. ==> 0XF8006000[14:14] = 0x00000000U
- // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_act_bypass = 0x0
- // .. .. ==> 0XF8006000[15:15] = 0x00000000U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_auto_refresh = 0x0
- // .. .. ==> 0XF8006000[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
- // .. .. FINISH: UNLOCK DDR
- // .. .. START: CHECK DDR STATUS
- // .. .. ddrc_reg_operating_mode = 1
- // .. .. ==> 0XF8006054[2:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U
- // .. ..
- EMIT_MASKPOLL(0XF8006054, 0x00000007U),
- // .. .. FINISH: CHECK DDR STATUS
- // .. FINISH: DDR INITIALIZATION
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_mio_init_data_1_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: OCM REMAPPING
- // .. VREF_EN = 0x1
- // .. ==> 0XF8000B00[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. VREF_PULLUP_EN = 0x0
- // .. ==> 0XF8000B00[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. CLK_PULLUP_EN = 0x0
- // .. ==> 0XF8000B00[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. SRSTN_PULLUP_EN = 0x0
- // .. ==> 0XF8000B00[9:9] = 0x00000000U
- // .. ==> MASK : 0x00000200U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B00, 0x00000303U ,0x00000001U),
- // .. FINISH: OCM REMAPPING
- // .. START: DDRIOB SETTINGS
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B40[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x0
- // .. ==> 0XF8000B40[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B40[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x0
- // .. ==> 0XF8000B40[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. DCR_TYPE = 0x0
- // .. ==> 0XF8000B40[6:5] = 0x00000000U
- // .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. IBUF_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B40[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B40[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B40[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B40[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B44[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x0
- // .. ==> 0XF8000B44[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B44[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x0
- // .. ==> 0XF8000B44[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. DCR_TYPE = 0x0
- // .. ==> 0XF8000B44[6:5] = 0x00000000U
- // .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. IBUF_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B44[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B44[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B44[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B44[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B48[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x1
- // .. ==> 0XF8000B48[2:1] = 0x00000001U
- // .. ==> MASK : 0x00000006U VAL : 0x00000002U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B48[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x1
- // .. ==> 0XF8000B48[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. DCR_TYPE = 0x3
- // .. ==> 0XF8000B48[6:5] = 0x00000003U
- // .. ==> MASK : 0x00000060U VAL : 0x00000060U
- // .. IBUF_DISABLE_MODE = 0
- // .. ==> 0XF8000B48[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0
- // .. ==> 0XF8000B48[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B48[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B48[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B4C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x1
- // .. ==> 0XF8000B4C[2:1] = 0x00000001U
- // .. ==> MASK : 0x00000006U VAL : 0x00000002U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B4C[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x1
- // .. ==> 0XF8000B4C[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. DCR_TYPE = 0x3
- // .. ==> 0XF8000B4C[6:5] = 0x00000003U
- // .. ==> MASK : 0x00000060U VAL : 0x00000060U
- // .. IBUF_DISABLE_MODE = 0
- // .. ==> 0XF8000B4C[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0
- // .. ==> 0XF8000B4C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B4C[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B4C[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B50[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x2
- // .. ==> 0XF8000B50[2:1] = 0x00000002U
- // .. ==> MASK : 0x00000006U VAL : 0x00000004U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B50[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x1
- // .. ==> 0XF8000B50[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. DCR_TYPE = 0x3
- // .. ==> 0XF8000B50[6:5] = 0x00000003U
- // .. ==> MASK : 0x00000060U VAL : 0x00000060U
- // .. IBUF_DISABLE_MODE = 0
- // .. ==> 0XF8000B50[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0
- // .. ==> 0XF8000B50[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B50[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B50[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B54[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x2
- // .. ==> 0XF8000B54[2:1] = 0x00000002U
- // .. ==> MASK : 0x00000006U VAL : 0x00000004U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B54[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x1
- // .. ==> 0XF8000B54[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. DCR_TYPE = 0x3
- // .. ==> 0XF8000B54[6:5] = 0x00000003U
- // .. ==> MASK : 0x00000060U VAL : 0x00000060U
- // .. IBUF_DISABLE_MODE = 0
- // .. ==> 0XF8000B54[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0
- // .. ==> 0XF8000B54[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B54[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B54[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B58[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x0
- // .. ==> 0XF8000B58[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B58[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x0
- // .. ==> 0XF8000B58[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. DCR_TYPE = 0x0
- // .. ==> 0XF8000B58[6:5] = 0x00000000U
- // .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. IBUF_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B58[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B58[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B58[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B58[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
- // .. DRIVE_P = 0x1c
- // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
- // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
- // .. DRIVE_N = 0xc
- // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
- // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
- // .. SLEW_P = 0x3
- // .. ==> 0XF8000B5C[18:14] = 0x00000003U
- // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U
- // .. SLEW_N = 0x3
- // .. ==> 0XF8000B5C[23:19] = 0x00000003U
- // .. ==> MASK : 0x00F80000U VAL : 0x00180000U
- // .. GTL = 0x0
- // .. ==> 0XF8000B5C[26:24] = 0x00000000U
- // .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. RTERM = 0x0
- // .. ==> 0XF8000B5C[31:27] = 0x00000000U
- // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
- // .. DRIVE_P = 0x1c
- // .. ==> 0XF8000B60[6:0] = 0x0000001CU
- // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
- // .. DRIVE_N = 0xc
- // .. ==> 0XF8000B60[13:7] = 0x0000000CU
- // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
- // .. SLEW_P = 0x6
- // .. ==> 0XF8000B60[18:14] = 0x00000006U
- // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
- // .. SLEW_N = 0x1f
- // .. ==> 0XF8000B60[23:19] = 0x0000001FU
- // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
- // .. GTL = 0x0
- // .. ==> 0XF8000B60[26:24] = 0x00000000U
- // .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. RTERM = 0x0
- // .. ==> 0XF8000B60[31:27] = 0x00000000U
- // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
- // .. DRIVE_P = 0x1c
- // .. ==> 0XF8000B64[6:0] = 0x0000001CU
- // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
- // .. DRIVE_N = 0xc
- // .. ==> 0XF8000B64[13:7] = 0x0000000CU
- // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
- // .. SLEW_P = 0x6
- // .. ==> 0XF8000B64[18:14] = 0x00000006U
- // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
- // .. SLEW_N = 0x1f
- // .. ==> 0XF8000B64[23:19] = 0x0000001FU
- // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
- // .. GTL = 0x0
- // .. ==> 0XF8000B64[26:24] = 0x00000000U
- // .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. RTERM = 0x0
- // .. ==> 0XF8000B64[31:27] = 0x00000000U
- // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
- // .. DRIVE_P = 0x1c
- // .. ==> 0XF8000B68[6:0] = 0x0000001CU
- // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
- // .. DRIVE_N = 0xc
- // .. ==> 0XF8000B68[13:7] = 0x0000000CU
- // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
- // .. SLEW_P = 0x6
- // .. ==> 0XF8000B68[18:14] = 0x00000006U
- // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
- // .. SLEW_N = 0x1f
- // .. ==> 0XF8000B68[23:19] = 0x0000001FU
- // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
- // .. GTL = 0x0
- // .. ==> 0XF8000B68[26:24] = 0x00000000U
- // .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. RTERM = 0x0
- // .. ==> 0XF8000B68[31:27] = 0x00000000U
- // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
- // .. VREF_INT_EN = 0x1
- // .. ==> 0XF8000B6C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. VREF_SEL = 0x4
- // .. ==> 0XF8000B6C[4:1] = 0x00000004U
- // .. ==> MASK : 0x0000001EU VAL : 0x00000008U
- // .. VREF_EXT_EN = 0x0
- // .. ==> 0XF8000B6C[6:5] = 0x00000000U
- // .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. VREF_PULLUP_EN = 0x0
- // .. ==> 0XF8000B6C[8:7] = 0x00000000U
- // .. ==> MASK : 0x00000180U VAL : 0x00000000U
- // .. REFIO_EN = 0x1
- // .. ==> 0XF8000B6C[9:9] = 0x00000001U
- // .. ==> MASK : 0x00000200U VAL : 0x00000200U
- // .. REFIO_PULLUP_EN = 0x0
- // .. ==> 0XF8000B6C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DRST_B_PULLUP_EN = 0x0
- // .. ==> 0XF8000B6C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // .. CKE_PULLUP_EN = 0x0
- // .. ==> 0XF8000B6C[14:14] = 0x00000000U
- // .. ==> MASK : 0x00004000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B6C, 0x000073FFU ,0x00000209U),
- // .. .. START: ASSERT RESET
- // .. .. RESET = 1
- // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. VRN_OUT = 0x1
- // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
- // .. ..
- EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U),
- // .. .. FINISH: ASSERT RESET
- // .. .. START: DEASSERT RESET
- // .. .. RESET = 0
- // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. VRN_OUT = 0x1
- // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
- // .. ..
- EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
- // .. .. FINISH: DEASSERT RESET
- // .. .. RESET = 0x1
- // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ENABLE = 0x1
- // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. .. VRP_TRI = 0x0
- // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. VRN_TRI = 0x0
- // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. VRP_OUT = 0x0
- // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. VRN_OUT = 0x1
- // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
- // .. .. NREF_OPT1 = 0x0
- // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
- // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U
- // .. .. NREF_OPT2 = 0x0
- // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U
- // .. .. NREF_OPT4 = 0x1
- // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
- // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U
- // .. .. PREF_OPT1 = 0x0
- // .. .. ==> 0XF8000B70[16:14] = 0x00000000U
- // .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U
- // .. .. PREF_OPT2 = 0x0
- // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
- // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U
- // .. .. UPDATE_CONTROL = 0x0
- // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
- // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U
- // .. .. INIT_COMPLETE = 0x0
- // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
- // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U
- // .. .. TST_CLK = 0x0
- // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
- // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U
- // .. .. TST_HLN = 0x0
- // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
- // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U
- // .. .. TST_HLP = 0x0
- // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
- // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U
- // .. .. TST_RST = 0x0
- // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
- // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
- // .. .. INT_DCI_EN = 0x0
- // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
- // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U),
- // .. FINISH: DDRIOB SETTINGS
- // .. START: MIO PROGRAMMING
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000700[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. Speed = 0
- // .. ==> 0XF8000700[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000700[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 1
- // .. ==> 0XF8000700[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000700[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000700, 0x00003F01U ,0x00001201U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000704[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000704[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000704[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000704[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000704[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000704[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000704[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 1
- // .. ==> 0XF8000704[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000704[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001202U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000708[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000708[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000708[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000708[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000708[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000708[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000708[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000708[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000708[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000202U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800070C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF800070C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF800070C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800070C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800070C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800070C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF800070C[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF800070C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800070C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000202U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000710[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000710[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000710[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000710[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000710[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000710[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000710[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000710[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000710[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000202U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000714[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000714[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000714[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000714[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000714[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000714[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000714[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000714[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000714[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000202U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000718[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000718[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000718[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000718[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000718[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000718[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000718[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000718[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000718[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000202U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800071C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800071C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF800071C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800071C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800071C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800071C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF800071C[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF800071C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800071C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000200U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000720[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000720[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000720[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000720[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000720[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000720[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000720[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000720[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000720[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000202U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000724[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000724[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000724[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000724[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000724[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000724[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000724[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 1
- // .. ==> 0XF8000724[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000724[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001200U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000728[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000728[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000728[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000728[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000728[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000728[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000728[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 1
- // .. ==> 0XF8000728[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000728[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001200U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800072C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800072C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF800072C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800072C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800072C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800072C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF800072C[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 1
- // .. ==> 0XF800072C[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800072C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001200U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000730[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000730[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000730[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000730[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000730[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000730[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000730[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 1
- // .. ==> 0XF8000730[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000730[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001200U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000734[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000734[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000734[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000734[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000734[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000734[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000734[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 1
- // .. ==> 0XF8000734[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000734[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001200U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000738[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000738[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000738[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000738[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000738[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000738[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000738[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 1
- // .. ==> 0XF8000738[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000738[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00001200U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF800073C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. Speed = 0
- // .. ==> 0XF800073C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF800073C[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 1
- // .. ==> 0XF800073C[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800073C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800073C, 0x00003F01U ,0x00001201U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000740[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000740[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000740[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000740[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000740[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000740[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 4
- // .. ==> 0XF8000740[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000740[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 1
- // .. ==> 0XF8000740[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // ..
- EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00002802U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000744[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000744[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000744[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000744[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000744[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000744[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 4
- // .. ==> 0XF8000744[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000744[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 1
- // .. ==> 0XF8000744[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // ..
- EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00002802U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000748[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000748[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000748[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000748[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000748[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000748[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 4
- // .. ==> 0XF8000748[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000748[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 1
- // .. ==> 0XF8000748[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // ..
- EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00002802U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800074C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF800074C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF800074C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800074C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800074C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800074C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 4
- // .. ==> 0XF800074C[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF800074C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 1
- // .. ==> 0XF800074C[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // ..
- EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00002802U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000750[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000750[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000750[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000750[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000750[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000750[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 4
- // .. ==> 0XF8000750[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000750[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 1
- // .. ==> 0XF8000750[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // ..
- EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00002802U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000754[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000754[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000754[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000754[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000754[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000754[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 4
- // .. ==> 0XF8000754[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000754[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 1
- // .. ==> 0XF8000754[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // ..
- EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00002802U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000758[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF8000758[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000758[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000758[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000758[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000758[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 4
- // .. ==> 0XF8000758[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000758[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000758[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000803U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF800075C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF800075C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF800075C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800075C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800075C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800075C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 4
- // .. ==> 0XF800075C[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF800075C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800075C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000803U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000760[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF8000760[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000760[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000760[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000760[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000760[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 4
- // .. ==> 0XF8000760[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000760[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000760[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000803U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000764[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF8000764[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000764[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000764[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000764[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000764[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 4
- // .. ==> 0XF8000764[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000764[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000764[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000803U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000768[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF8000768[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000768[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000768[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000768[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000768[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 4
- // .. ==> 0XF8000768[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000768[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000768[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000803U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF800076C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF800076C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF800076C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800076C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800076C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800076C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 4
- // .. ==> 0XF800076C[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF800076C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800076C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000803U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000770[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000770[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000770[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000770[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000770[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000770[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000770[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000770[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000770[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000774[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF8000774[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000774[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000774[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000774[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000774[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000774[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000774[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000774[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000778[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000778[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000778[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000778[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000778[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000778[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000778[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000778[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000778[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF800077C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF800077C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF800077C[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF800077C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800077C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800077C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF800077C[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF800077C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800077C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000780[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000780[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000780[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000780[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000780[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000780[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000780[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000780[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000780[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000784[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000784[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000784[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000784[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000784[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000784[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000784[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000784[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000784[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000788[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000788[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000788[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000788[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000788[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000788[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000788[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000788[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000788[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800078C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800078C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF800078C[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF800078C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800078C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800078C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF800078C[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF800078C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800078C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000790[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF8000790[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000790[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000790[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000790[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000790[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000790[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000790[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000790[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000794[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000794[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000794[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000794[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000794[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000794[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000794[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000794[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000794[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000798[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000798[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000798[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000798[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000798[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000798[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000798[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000798[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000798[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800079C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800079C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF800079C[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF800079C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800079C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800079C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF800079C[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF800079C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800079C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007A0[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007A0[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007A0[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007A0[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007A0[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF80007A0[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007A0[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007A0[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007A0[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000280U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007A4[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007A4[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007A4[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007A4[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007A4[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF80007A4[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007A4[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007A4[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007A4[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000280U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007A8[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007A8[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007A8[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007A8[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007A8[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF80007A8[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007A8[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007A8[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007A8[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000280U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007AC[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007AC[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007AC[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007AC[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007AC[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF80007AC[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007AC[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007AC[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007AC[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000280U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007B0[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007B0[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007B0[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007B0[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007B0[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF80007B0[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007B0[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007B0[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007B0[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000280U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007B4[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007B4[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007B4[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007B4[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007B4[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF80007B4[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007B4[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007B4[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007B4[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000280U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF80007B8[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF80007B8[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007B8[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007B8[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 1
- // .. ==> 0XF80007B8[7:5] = 0x00000001U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000020U
- // .. Speed = 0
- // .. ==> 0XF80007B8[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007B8[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 1
- // .. ==> 0XF80007B8[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007B8[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001221U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007BC[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007BC[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007BC[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007BC[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 1
- // .. ==> 0XF80007BC[7:5] = 0x00000001U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000020U
- // .. Speed = 0
- // .. ==> 0XF80007BC[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007BC[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 1
- // .. ==> 0XF80007BC[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007BC[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00001220U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007C0[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007C0[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007C0[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007C0[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 7
- // .. ==> 0XF80007C0[7:5] = 0x00000007U
- // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U
- // .. Speed = 0
- // .. ==> 0XF80007C0[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007C0[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007C0[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007C0[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF80007C4[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF80007C4[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007C4[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007C4[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 7
- // .. ==> 0XF80007C4[7:5] = 0x00000007U
- // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U
- // .. Speed = 0
- // .. ==> 0XF80007C4[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007C4[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007C4[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007C4[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007C8[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007C8[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007C8[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007C8[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 2
- // .. ==> 0XF80007C8[7:5] = 0x00000002U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000040U
- // .. Speed = 0
- // .. ==> 0XF80007C8[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007C8[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 1
- // .. ==> 0XF80007C8[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007C8[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001240U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007CC[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007CC[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007CC[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007CC[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 2
- // .. ==> 0XF80007CC[7:5] = 0x00000002U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000040U
- // .. Speed = 0
- // .. ==> 0XF80007CC[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007CC[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 1
- // .. ==> 0XF80007CC[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007CC[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001240U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007D0[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007D0[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007D0[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007D0[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007D0[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF80007D0[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007D0[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007D0[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007D0[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007D4[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007D4[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007D4[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007D4[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007D4[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF80007D4[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007D4[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007D4[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007D4[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U),
- // .. SDIO0_WP_SEL = 15
- // .. ==> 0XF8000830[5:0] = 0x0000000FU
- // .. ==> MASK : 0x0000003FU VAL : 0x0000000FU
- // .. SDIO0_CD_SEL = 0
- // .. ==> 0XF8000830[21:16] = 0x00000000U
- // .. ==> MASK : 0x003F0000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x0000000FU),
- // .. FINISH: MIO PROGRAMMING
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_peripherals_init_data_1_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
- // .. IBUF_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B48[7:7] = 0x00000001U
- // .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. TERM_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B48[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // ..
- EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
- // .. IBUF_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B4C[7:7] = 0x00000001U
- // .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. TERM_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B4C[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // ..
- EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
- // .. IBUF_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B50[7:7] = 0x00000001U
- // .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. TERM_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B50[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // ..
- EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
- // .. IBUF_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B54[7:7] = 0x00000001U
- // .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. TERM_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B54[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // ..
- EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
- // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // .. START: SRAM/NOR SET OPMODE
- // .. FINISH: SRAM/NOR SET OPMODE
- // .. START: UART REGISTERS
- // .. BDIV = 0x6
- // .. ==> 0XE0001034[7:0] = 0x00000006U
- // .. ==> MASK : 0x000000FFU VAL : 0x00000006U
- // ..
- EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
- // .. CD = 0x3e
- // .. ==> 0XE0001018[15:0] = 0x0000003EU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU
- // ..
- EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
- // .. STPBRK = 0x0
- // .. ==> 0XE0001000[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. STTBRK = 0x0
- // .. ==> 0XE0001000[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. RSTTO = 0x0
- // .. ==> 0XE0001000[6:6] = 0x00000000U
- // .. ==> MASK : 0x00000040U VAL : 0x00000000U
- // .. TXDIS = 0x0
- // .. ==> 0XE0001000[5:5] = 0x00000000U
- // .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. TXEN = 0x1
- // .. ==> 0XE0001000[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. RXDIS = 0x0
- // .. ==> 0XE0001000[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. RXEN = 0x1
- // .. ==> 0XE0001000[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. TXRES = 0x1
- // .. ==> 0XE0001000[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. RXRES = 0x1
- // .. ==> 0XE0001000[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // ..
- EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
- // .. IRMODE = 0x0
- // .. ==> 0XE0001004[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. UCLKEN = 0x0
- // .. ==> 0XE0001004[10:10] = 0x00000000U
- // .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. CHMODE = 0x0
- // .. ==> 0XE0001004[9:8] = 0x00000000U
- // .. ==> MASK : 0x00000300U VAL : 0x00000000U
- // .. NBSTOP = 0x0
- // .. ==> 0XE0001004[7:6] = 0x00000000U
- // .. ==> MASK : 0x000000C0U VAL : 0x00000000U
- // .. PAR = 0x4
- // .. ==> 0XE0001004[5:3] = 0x00000004U
- // .. ==> MASK : 0x00000038U VAL : 0x00000020U
- // .. CHRL = 0x0
- // .. ==> 0XE0001004[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. CLKS = 0x0
- // .. ==> 0XE0001004[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U),
- // .. FINISH: UART REGISTERS
- // .. START: QSPI REGISTERS
- // .. Holdb_dr = 1
- // .. ==> 0XE000D000[19:19] = 0x00000001U
- // .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // ..
- EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
- // .. FINISH: QSPI REGISTERS
- // .. START: PL POWER ON RESET REGISTERS
- // .. PCFG_POR_CNT_4K = 0
- // .. ==> 0XF8007000[29:29] = 0x00000000U
- // .. ==> MASK : 0x20000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
- // .. FINISH: PL POWER ON RESET REGISTERS
- // .. START: SMC TIMING CALCULATION REGISTER UPDATE
- // .. .. START: NAND SET CYCLE
- // .. .. FINISH: NAND SET CYCLE
- // .. .. START: OPMODE
- // .. .. FINISH: OPMODE
- // .. .. START: DIRECT COMMAND
- // .. .. FINISH: DIRECT COMMAND
- // .. .. START: SRAM/NOR CS0 SET CYCLE
- // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
- // .. .. START: DIRECT COMMAND
- // .. .. FINISH: DIRECT COMMAND
- // .. .. START: NOR CS0 BASE ADDRESS
- // .. .. FINISH: NOR CS0 BASE ADDRESS
- // .. .. START: SRAM/NOR CS1 SET CYCLE
- // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
- // .. .. START: DIRECT COMMAND
- // .. .. FINISH: DIRECT COMMAND
- // .. .. START: NOR CS1 BASE ADDRESS
- // .. .. FINISH: NOR CS1 BASE ADDRESS
- // .. .. START: USB RESET
- // .. .. .. START: USB0 RESET
- // .. .. .. .. START: DIR MODE BANK 0
- // .. .. .. .. DIRECTION_0 = 0x80
- // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U
- // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U),
- // .. .. .. .. FINISH: DIR MODE BANK 0
- // .. .. .. .. START: DIR MODE BANK 1
- // .. .. .. .. FINISH: DIR MODE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. MASK_0_LSW = 0xff7f
- // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
- // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U
- // .. .. .. .. DATA_0_LSW = 0x80
- // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
- // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. START: OUTPUT ENABLE BANK 0
- // .. .. .. .. OP_ENABLE_0 = 0x80
- // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U
- // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U),
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
- // .. .. .. .. START: OUTPUT ENABLE BANK 1
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. MASK_0_LSW = 0xff7f
- // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
- // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U
- // .. .. .. .. DATA_0_LSW = 0x0
- // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
- // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U),
- // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. START: ADD 1 MS DELAY
- // .. .. .. ..
- EMIT_MASKDELAY(0XF8F00200, 1),
- // .. .. .. .. FINISH: ADD 1 MS DELAY
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. MASK_0_LSW = 0xff7f
- // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
- // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U
- // .. .. .. .. DATA_0_LSW = 0x80
- // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
- // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: USB0 RESET
- // .. .. .. START: USB1 RESET
- // .. .. .. .. START: DIR MODE BANK 0
- // .. .. .. .. FINISH: DIR MODE BANK 0
- // .. .. .. .. START: DIR MODE BANK 1
- // .. .. .. .. FINISH: DIR MODE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. START: OUTPUT ENABLE BANK 0
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
- // .. .. .. .. START: OUTPUT ENABLE BANK 1
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. START: ADD 1 MS DELAY
- // .. .. .. ..
- EMIT_MASKDELAY(0XF8F00200, 1),
- // .. .. .. .. FINISH: ADD 1 MS DELAY
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: USB1 RESET
- // .. .. FINISH: USB RESET
- // .. .. START: ENET RESET
- // .. .. .. START: ENET0 RESET
- // .. .. .. .. START: DIR MODE BANK 0
- // .. .. .. .. DIRECTION_0 = 0x800
- // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000800U
- // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000800U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000800U),
- // .. .. .. .. FINISH: DIR MODE BANK 0
- // .. .. .. .. START: DIR MODE BANK 1
- // .. .. .. .. FINISH: DIR MODE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. MASK_0_LSW = 0xf7ff
- // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU
- // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xF7FF0000U
- // .. .. .. .. DATA_0_LSW = 0x800
- // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000800U
- // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000800U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0800U),
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. START: OUTPUT ENABLE BANK 0
- // .. .. .. .. OP_ENABLE_0 = 0x800
- // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000800U
- // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000800U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000800U),
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
- // .. .. .. .. START: OUTPUT ENABLE BANK 1
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. MASK_0_LSW = 0xf7ff
- // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU
- // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xF7FF0000U
- // .. .. .. .. DATA_0_LSW = 0x0
- // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
- // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0000U),
- // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. START: ADD 1 MS DELAY
- // .. .. .. ..
- EMIT_MASKDELAY(0XF8F00200, 1),
- // .. .. .. .. FINISH: ADD 1 MS DELAY
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. MASK_0_LSW = 0xf7ff
- // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU
- // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xF7FF0000U
- // .. .. .. .. DATA_0_LSW = 0x800
- // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000800U
- // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000800U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0800U),
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: ENET0 RESET
- // .. .. .. START: ENET1 RESET
- // .. .. .. .. START: DIR MODE BANK 0
- // .. .. .. .. FINISH: DIR MODE BANK 0
- // .. .. .. .. START: DIR MODE BANK 1
- // .. .. .. .. FINISH: DIR MODE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. START: OUTPUT ENABLE BANK 0
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
- // .. .. .. .. START: OUTPUT ENABLE BANK 1
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. START: ADD 1 MS DELAY
- // .. .. .. ..
- EMIT_MASKDELAY(0XF8F00200, 1),
- // .. .. .. .. FINISH: ADD 1 MS DELAY
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: ENET1 RESET
- // .. .. FINISH: ENET RESET
- // .. .. START: I2C RESET
- // .. .. .. START: I2C0 RESET
- // .. .. .. .. START: DIR MODE GPIO BANK0
- // .. .. .. .. DIRECTION_0 = 0x2000
- // .. .. .. .. ==> 0XE000A204[31:0] = 0x00002000U
- // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002000U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002000U),
- // .. .. .. .. FINISH: DIR MODE GPIO BANK0
- // .. .. .. .. START: DIR MODE GPIO BANK1
- // .. .. .. .. FINISH: DIR MODE GPIO BANK1
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. MASK_0_LSW = 0xdfff
- // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU
- // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xDFFF0000U
- // .. .. .. .. DATA_0_LSW = 0x2000
- // .. .. .. .. ==> 0XE000A000[15:0] = 0x00002000U
- // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00002000U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF2000U),
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. START: OUTPUT ENABLE
- // .. .. .. .. OP_ENABLE_0 = 0x2000
- // .. .. .. .. ==> 0XE000A208[31:0] = 0x00002000U
- // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002000U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002000U),
- // .. .. .. .. FINISH: OUTPUT ENABLE
- // .. .. .. .. START: OUTPUT ENABLE
- // .. .. .. .. FINISH: OUTPUT ENABLE
- // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. MASK_0_LSW = 0xdfff
- // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU
- // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xDFFF0000U
- // .. .. .. .. DATA_0_LSW = 0x0
- // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
- // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF0000U),
- // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. START: ADD 1 MS DELAY
- // .. .. .. ..
- EMIT_MASKDELAY(0XF8F00200, 1),
- // .. .. .. .. FINISH: ADD 1 MS DELAY
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. MASK_0_LSW = 0xdfff
- // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU
- // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xDFFF0000U
- // .. .. .. .. DATA_0_LSW = 0x2000
- // .. .. .. .. ==> 0XE000A000[15:0] = 0x00002000U
- // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00002000U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF2000U),
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: I2C0 RESET
- // .. .. .. START: I2C1 RESET
- // .. .. .. .. START: DIR MODE GPIO BANK0
- // .. .. .. .. FINISH: DIR MODE GPIO BANK0
- // .. .. .. .. START: DIR MODE GPIO BANK1
- // .. .. .. .. FINISH: DIR MODE GPIO BANK1
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. START: OUTPUT ENABLE
- // .. .. .. .. FINISH: OUTPUT ENABLE
- // .. .. .. .. START: OUTPUT ENABLE
- // .. .. .. .. FINISH: OUTPUT ENABLE
- // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. START: ADD 1 MS DELAY
- // .. .. .. ..
- EMIT_MASKDELAY(0XF8F00200, 1),
- // .. .. .. .. FINISH: ADD 1 MS DELAY
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: I2C1 RESET
- // .. .. FINISH: I2C RESET
- // .. .. START: NOR CHIP SELECT
- // .. .. .. START: DIR MODE BANK 0
- // .. .. .. FINISH: DIR MODE BANK 0
- // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. START: OUTPUT ENABLE BANK 0
- // .. .. .. FINISH: OUTPUT ENABLE BANK 0
- // .. .. FINISH: NOR CHIP SELECT
- // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_post_config_1_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: ENABLING LEVEL SHIFTER
- // .. USER_INP_ICT_EN_0 = 3
- // .. ==> 0XF8000900[1:0] = 0x00000003U
- // .. ==> MASK : 0x00000003U VAL : 0x00000003U
- // .. USER_INP_ICT_EN_1 = 3
- // .. ==> 0XF8000900[3:2] = 0x00000003U
- // .. ==> MASK : 0x0000000CU VAL : 0x0000000CU
- // ..
- EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
- // .. FINISH: ENABLING LEVEL SHIFTER
- // .. START: FPGA RESETS TO 0
- // .. reserved_3 = 0
- // .. ==> 0XF8000240[31:25] = 0x00000000U
- // .. ==> MASK : 0xFE000000U VAL : 0x00000000U
- // .. FPGA_ACP_RST = 0
- // .. ==> 0XF8000240[24:24] = 0x00000000U
- // .. ==> MASK : 0x01000000U VAL : 0x00000000U
- // .. FPGA_AXDS3_RST = 0
- // .. ==> 0XF8000240[23:23] = 0x00000000U
- // .. ==> MASK : 0x00800000U VAL : 0x00000000U
- // .. FPGA_AXDS2_RST = 0
- // .. ==> 0XF8000240[22:22] = 0x00000000U
- // .. ==> MASK : 0x00400000U VAL : 0x00000000U
- // .. FPGA_AXDS1_RST = 0
- // .. ==> 0XF8000240[21:21] = 0x00000000U
- // .. ==> MASK : 0x00200000U VAL : 0x00000000U
- // .. FPGA_AXDS0_RST = 0
- // .. ==> 0XF8000240[20:20] = 0x00000000U
- // .. ==> MASK : 0x00100000U VAL : 0x00000000U
- // .. reserved_2 = 0
- // .. ==> 0XF8000240[19:18] = 0x00000000U
- // .. ==> MASK : 0x000C0000U VAL : 0x00000000U
- // .. FSSW1_FPGA_RST = 0
- // .. ==> 0XF8000240[17:17] = 0x00000000U
- // .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. FSSW0_FPGA_RST = 0
- // .. ==> 0XF8000240[16:16] = 0x00000000U
- // .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. reserved_1 = 0
- // .. ==> 0XF8000240[15:14] = 0x00000000U
- // .. ==> MASK : 0x0000C000U VAL : 0x00000000U
- // .. FPGA_FMSW1_RST = 0
- // .. ==> 0XF8000240[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // .. FPGA_FMSW0_RST = 0
- // .. ==> 0XF8000240[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. FPGA_DMA3_RST = 0
- // .. ==> 0XF8000240[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. FPGA_DMA2_RST = 0
- // .. ==> 0XF8000240[10:10] = 0x00000000U
- // .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. FPGA_DMA1_RST = 0
- // .. ==> 0XF8000240[9:9] = 0x00000000U
- // .. ==> MASK : 0x00000200U VAL : 0x00000000U
- // .. FPGA_DMA0_RST = 0
- // .. ==> 0XF8000240[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. reserved = 0
- // .. ==> 0XF8000240[7:4] = 0x00000000U
- // .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. FPGA3_OUT_RST = 0
- // .. ==> 0XF8000240[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. FPGA2_OUT_RST = 0
- // .. ==> 0XF8000240[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. FPGA1_OUT_RST = 0
- // .. ==> 0XF8000240[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. FPGA0_OUT_RST = 0
- // .. ==> 0XF8000240[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
- // .. FINISH: FPGA RESETS TO 0
- // .. START: AFI REGISTERS
- // .. .. START: AFI0 REGISTERS
- // .. .. FINISH: AFI0 REGISTERS
- // .. .. START: AFI1 REGISTERS
- // .. .. FINISH: AFI1 REGISTERS
- // .. .. START: AFI2 REGISTERS
- // .. .. FINISH: AFI2 REGISTERS
- // .. .. START: AFI3 REGISTERS
- // .. .. FINISH: AFI3 REGISTERS
- // .. FINISH: AFI REGISTERS
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_debug_1_0[] = {
- // START: top
- // .. START: CROSS TRIGGER CONFIGURATIONS
- // .. .. START: UNLOCKING CTI REGISTERS
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. FINISH: UNLOCKING CTI REGISTERS
- // .. .. START: ENABLING CTI MODULES AND CHANNELS
- // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
- // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. FINISH: CROSS TRIGGER CONFIGURATIONS
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-
-#include "xil_io.h"
-#define PS7_MASK_POLL_TIME 100000000
-
-char*
-getPS7MessageInfo(unsigned key) {
-
- char* err_msg = "";
- switch (key) {
- case PS7_INIT_SUCCESS: err_msg = "PS7 initialization successful"; break;
- case PS7_INIT_CORRUPT: err_msg = "PS7 init Data Corrupted"; break;
- case PS7_INIT_TIMEOUT: err_msg = "PS7 init mask poll timeout"; break;
- case PS7_POLL_FAILED_DDR_INIT: err_msg = "Mask Poll failed for DDR Init"; break;
- case PS7_POLL_FAILED_DMA: err_msg = "Mask Poll failed for PLL Init"; break;
- case PS7_POLL_FAILED_PLL: err_msg = "Mask Poll failed for DMA done bit"; break;
- default: err_msg = "Undefined error status"; break;
- }
-
- return err_msg;
-}
-
-unsigned long
-ps7GetSiliconVersion () {
- // Read PS version from MCTRL register [31:28]
- unsigned long mask = 0xF0000000;
- unsigned long *addr = (unsigned long*) 0XF8007080;
- unsigned long ps_version = (*addr & mask) >> 28;
- return ps_version;
-}
-
-void mask_write (unsigned long add , unsigned long mask, unsigned long val ) {
- unsigned long *addr = (unsigned long*) add;
- *addr = ( val & mask ) | ( *addr & ~mask);
- //xil_printf("MaskWrite : 0x%x--> 0x%x \n \r" ,add, *addr);
-}
-
-
-int mask_poll(unsigned long add , unsigned long mask ) {
- volatile unsigned long *addr = (volatile unsigned long*) add;
- int i = 0;
- while (!(*addr & mask)) {
- if (i == PS7_MASK_POLL_TIME) {
- return -1;
- }
- i++;
- }
- return 1;
- //xil_printf("MaskPoll : 0x%x --> 0x%x \n \r" , add, *addr);
-}
-
-unsigned long mask_read(unsigned long add , unsigned long mask ) {
- unsigned long *addr = (unsigned long*) add;
- unsigned long val = (*addr & mask);
- //xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val);
- return val;
-}
-
-
-
-int
-ps7_config(unsigned long * ps7_config_init)
-{
- unsigned long *ptr = ps7_config_init;
-
- unsigned long opcode; // current instruction ..
- unsigned long args[16]; // no opcode has so many args ...
- int numargs; // number of arguments of this instruction
- int j; // general purpose index
-
- volatile unsigned long *addr; // some variable to make code readable
- unsigned long val,mask; // some variable to make code readable
-
- int finish = -1 ; // loop while this is negative !
- int i = 0; // Timeout variable
-
- while( finish < 0 ) {
- numargs = ptr[0] & 0xF;
- opcode = ptr[0] >> 4;
-
- for( j = 0 ; j < numargs ; j ++ )
- args[j] = ptr[j+1];
- ptr += numargs + 1;
-
-
- switch ( opcode ) {
-
- case OPCODE_EXIT:
- finish = PS7_INIT_SUCCESS;
- break;
-
- case OPCODE_CLEAR:
- addr = (unsigned long*) args[0];
- *addr = 0;
- break;
-
- case OPCODE_WRITE:
- addr = (unsigned long*) args[0];
- val = args[1];
- *addr = val;
- break;
-
- case OPCODE_MASKWRITE:
- addr = (unsigned long*) args[0];
- mask = args[1];
- val = args[2];
- *addr = ( val & mask ) | ( *addr & ~mask);
- break;
-
- case OPCODE_MASKPOLL:
- addr = (unsigned long*) args[0];
- mask = args[1];
- i = 0;
- while (!(*addr & mask)) {
- if (i == PS7_MASK_POLL_TIME) {
- finish = PS7_INIT_TIMEOUT;
- break;
- }
- i++;
- }
- break;
- case OPCODE_MASKDELAY:
- addr = (unsigned long*) args[0];
- mask = args[1];
- int delay = get_number_of_cycles_for_delay(mask);
- perf_reset_and_start_timer();
- while ((*addr < delay)) {
- }
- break;
- default:
- finish = PS7_INIT_CORRUPT;
- break;
- }
- }
- return finish;
-}
-
-unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0;
-unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0;
-unsigned long *ps7_clock_init_data = ps7_clock_init_data_3_0;
-unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0;
-unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
-
-int
-ps7_post_config()
-{
- // Get the PS_VERSION on run time
- unsigned long si_ver = ps7GetSiliconVersion ();
- int ret = -1;
- if (si_ver == PCW_SILICON_VERSION_1) {
- ret = ps7_config (ps7_post_config_1_0);
- if (ret != PS7_INIT_SUCCESS) return ret;
- } else if (si_ver == PCW_SILICON_VERSION_2) {
- ret = ps7_config (ps7_post_config_2_0);
- if (ret != PS7_INIT_SUCCESS) return ret;
- } else {
- ret = ps7_config (ps7_post_config_3_0);
- if (ret != PS7_INIT_SUCCESS) return ret;
- }
- return PS7_INIT_SUCCESS;
-}
-
-int
-ps7_debug()
-{
- // Get the PS_VERSION on run time
- unsigned long si_ver = ps7GetSiliconVersion ();
- int ret = -1;
- if (si_ver == PCW_SILICON_VERSION_1) {
- ret = ps7_config (ps7_debug_1_0);
- if (ret != PS7_INIT_SUCCESS) return ret;
- } else if (si_ver == PCW_SILICON_VERSION_2) {
- ret = ps7_config (ps7_debug_2_0);
- if (ret != PS7_INIT_SUCCESS) return ret;
- } else {
- ret = ps7_config (ps7_debug_3_0);
- if (ret != PS7_INIT_SUCCESS) return ret;
- }
- return PS7_INIT_SUCCESS;
-}
-
-int
-ps7_init()
-{
- // Get the PS_VERSION on run time
- unsigned long si_ver = ps7GetSiliconVersion ();
- int ret;
- //int pcw_ver = 0;
-
- if (si_ver == PCW_SILICON_VERSION_1) {
- ps7_mio_init_data = ps7_mio_init_data_1_0;
- ps7_pll_init_data = ps7_pll_init_data_1_0;
- ps7_clock_init_data = ps7_clock_init_data_1_0;
- ps7_ddr_init_data = ps7_ddr_init_data_1_0;
- ps7_peripherals_init_data = ps7_peripherals_init_data_1_0;
- //pcw_ver = 1;
-
- } else if (si_ver == PCW_SILICON_VERSION_2) {
- ps7_mio_init_data = ps7_mio_init_data_2_0;
- ps7_pll_init_data = ps7_pll_init_data_2_0;
- ps7_clock_init_data = ps7_clock_init_data_2_0;
- ps7_ddr_init_data = ps7_ddr_init_data_2_0;
- ps7_peripherals_init_data = ps7_peripherals_init_data_2_0;
- //pcw_ver = 2;
-
- } else {
- ps7_mio_init_data = ps7_mio_init_data_3_0;
- ps7_pll_init_data = ps7_pll_init_data_3_0;
- ps7_clock_init_data = ps7_clock_init_data_3_0;
- ps7_ddr_init_data = ps7_ddr_init_data_3_0;
- ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
- //pcw_ver = 3;
- }
-
- // MIO init
- ret = ps7_config (ps7_mio_init_data);
- if (ret != PS7_INIT_SUCCESS) return ret;
-
- // PLL init
- ret = ps7_config (ps7_pll_init_data);
- if (ret != PS7_INIT_SUCCESS) return ret;
-
- // Clock init
- ret = ps7_config (ps7_clock_init_data);
- if (ret != PS7_INIT_SUCCESS) return ret;
-
- // DDR init
- ret = ps7_config (ps7_ddr_init_data);
- if (ret != PS7_INIT_SUCCESS) return ret;
-
-
-
- // Peripherals init
- ret = ps7_config (ps7_peripherals_init_data);
- if (ret != PS7_INIT_SUCCESS) return ret;
- //xil_printf ("\n PCW Silicon Version : %d.0", pcw_ver);
- return PS7_INIT_SUCCESS;
-}
-
-
-
-
-/* For delay calculation using global timer */
-
-/* start timer */
- void perf_start_clock(void)
-{
- *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) | // Timer Enable
- (1 << 3) | // Auto-increment
- (0 << 8) // Pre-scale
- );
-}
-
-/* stop timer and reset timer count regs */
- void perf_reset_clock(void)
-{
- perf_disable_clock();
- *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_L32 = 0;
- *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_U32 = 0;
-}
-
-/* Compute mask for given delay in miliseconds*/
-int get_number_of_cycles_for_delay(unsigned int delay)
-{
- // GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x)
- return (APU_FREQ*delay/(2*1000));
-
-}
-
-/* stop timer */
- void perf_disable_clock(void)
-{
- *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = 0;
-}
-
-void perf_reset_and_start_timer()
-{
- perf_reset_clock();
- perf_start_clock();
-}
+++ /dev/null
-
-/******************************************************************************
-*
-* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
-*
-* SPDX-License-Identifier: GPL-2.0+
-*
-*
-*******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file ps7_init.h
-*
-* This file can be included in FSBL code
-* to get prototype of ps7_init() function
-* and error codes
-*
-*****************************************************************************/
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-//typedef unsigned int u32;
-
-
-/** do we need to make this name more unique ? **/
-//extern u32 ps7_init_data[];
-extern unsigned long * ps7_ddr_init_data;
-extern unsigned long * ps7_mio_init_data;
-extern unsigned long * ps7_pll_init_data;
-extern unsigned long * ps7_clock_init_data;
-extern unsigned long * ps7_peripherals_init_data;
-
-
-
-#define OPCODE_EXIT 0U
-#define OPCODE_CLEAR 1U
-#define OPCODE_WRITE 2U
-#define OPCODE_MASKWRITE 3U
-#define OPCODE_MASKPOLL 4U
-#define OPCODE_MASKDELAY 5U
-#define NEW_PS7_ERR_CODE 1
-
-/* Encode number of arguments in last nibble */
-#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 )
-#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr
-#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val
-#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
-#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask
-#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
-
-/* Returns codes of PS7_Init */
-#define PS7_INIT_SUCCESS (0) // 0 is success in good old C
-#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now
-#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out
-#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init
-#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit
-#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init
-
-
-/* Silicon Versions */
-#define PCW_SILICON_VERSION_1 0
-#define PCW_SILICON_VERSION_2 1
-#define PCW_SILICON_VERSION_3 2
-
-/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
-#define PS7_POST_CONFIG
-
-/* Freq of all peripherals */
-
-#define APU_FREQ 666666687
-#define DDR_FREQ 533333374
-#define DCI_FREQ 10158731
-#define QSPI_FREQ 200000000
-#define SMC_FREQ 10000000
-#define ENET0_FREQ 25000000
-#define ENET1_FREQ 10000000
-#define USB0_FREQ 60000000
-#define USB1_FREQ 60000000
-#define SDIO_FREQ 50000000
-#define UART_FREQ 50000000
-#define SPI_FREQ 10000000
-#define I2C_FREQ 111111115
-#define WDT_FREQ 111111115
-#define TTC_FREQ 50000000
-#define CAN_FREQ 23809523
-#define PCAP_FREQ 200000000
-#define TPIU_FREQ 200000000
-#define FPGA0_FREQ 50000000
-#define FPGA1_FREQ 50000000
-#define FPGA2_FREQ 50000000
-#define FPGA3_FREQ 50000000
-
-
-/* For delay calculation using global registers*/
-#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
-#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204
-#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208
-#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218
-
-int ps7_config( unsigned long*);
-int ps7_init();
-int ps7_post_config();
-int ps7_debug();
-char* getPS7MessageInfo(unsigned key);
-
-void perf_start_clock(void);
-void perf_disable_clock(void);
-void perf_reset_clock(void);
-void perf_reset_and_start_timer();
-int get_number_of_cycles_for_delay(unsigned int delay);
-#ifdef __cplusplus
-}
-#endif
+++ /dev/null
-/******************************************************************************
-* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
-*
-* SPDX-License-Identifier: GPL-2.0+
-*
-*
-******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file ps7_init_gpl.c
-*
-* This file is automatically generated
-*
-*****************************************************************************/
-
-#include "ps7_init_gpl.h"
-
-unsigned long ps7_pll_init_data_3_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: PLL SLCR REGISTERS
- // .. .. START: ARM PLL INIT
- // .. .. PLL_RES = 0x2
- // .. .. ==> 0XF8000110[7:4] = 0x00000002U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
- // .. .. PLL_CP = 0x2
- // .. .. ==> 0XF8000110[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. LOCK_CNT = 0xfa
- // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
- // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U
- // .. ..
- EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
- // .. .. .. START: UPDATE FB_DIV
- // .. .. .. PLL_FDIV = 0x28
- // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
- // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
- // .. .. .. FINISH: UPDATE FB_DIV
- // .. .. .. START: BY PASS PLL
- // .. .. .. PLL_BYPASS_FORCE = 1
- // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
- // .. .. .. FINISH: BY PASS PLL
- // .. .. .. START: ASSERT RESET
- // .. .. .. PLL_RESET = 1
- // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
- // .. .. .. FINISH: ASSERT RESET
- // .. .. .. START: DEASSERT RESET
- // .. .. .. PLL_RESET = 0
- // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
- // .. .. .. FINISH: DEASSERT RESET
- // .. .. .. START: CHECK PLL STATUS
- // .. .. .. ARM_PLL_LOCK = 1
- // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ..
- EMIT_MASKPOLL(0XF800010C, 0x00000001U),
- // .. .. .. FINISH: CHECK PLL STATUS
- // .. .. .. START: REMOVE PLL BY PASS
- // .. .. .. PLL_BYPASS_FORCE = 0
- // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
- // .. .. .. FINISH: REMOVE PLL BY PASS
- // .. .. .. SRCSEL = 0x0
- // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. .. .. DIVISOR = 0x2
- // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
- // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U
- // .. .. .. CPU_6OR4XCLKACT = 0x1
- // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
- // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U
- // .. .. .. CPU_3OR2XCLKACT = 0x1
- // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
- // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U
- // .. .. .. CPU_2XCLKACT = 0x1
- // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
- // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U
- // .. .. .. CPU_1XCLKACT = 0x1
- // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
- // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U
- // .. .. .. CPU_PERI_CLKACT = 0x1
- // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
- // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
- // .. .. FINISH: ARM PLL INIT
- // .. .. START: DDR PLL INIT
- // .. .. PLL_RES = 0x2
- // .. .. ==> 0XF8000114[7:4] = 0x00000002U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
- // .. .. PLL_CP = 0x2
- // .. .. ==> 0XF8000114[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. LOCK_CNT = 0x12c
- // .. .. ==> 0XF8000114[21:12] = 0x0000012CU
- // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U
- // .. ..
- EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
- // .. .. .. START: UPDATE FB_DIV
- // .. .. .. PLL_FDIV = 0x20
- // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
- // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
- // .. .. .. FINISH: UPDATE FB_DIV
- // .. .. .. START: BY PASS PLL
- // .. .. .. PLL_BYPASS_FORCE = 1
- // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
- // .. .. .. FINISH: BY PASS PLL
- // .. .. .. START: ASSERT RESET
- // .. .. .. PLL_RESET = 1
- // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
- // .. .. .. FINISH: ASSERT RESET
- // .. .. .. START: DEASSERT RESET
- // .. .. .. PLL_RESET = 0
- // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
- // .. .. .. FINISH: DEASSERT RESET
- // .. .. .. START: CHECK PLL STATUS
- // .. .. .. DDR_PLL_LOCK = 1
- // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. .. ..
- EMIT_MASKPOLL(0XF800010C, 0x00000002U),
- // .. .. .. FINISH: CHECK PLL STATUS
- // .. .. .. START: REMOVE PLL BY PASS
- // .. .. .. PLL_BYPASS_FORCE = 0
- // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
- // .. .. .. FINISH: REMOVE PLL BY PASS
- // .. .. .. DDR_3XCLKACT = 0x1
- // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. .. DDR_2XCLKACT = 0x1
- // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. .. .. DDR_3XCLK_DIVISOR = 0x2
- // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
- // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U
- // .. .. .. DDR_2XCLK_DIVISOR = 0x3
- // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
- // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
- // .. .. FINISH: DDR PLL INIT
- // .. .. START: IO PLL INIT
- // .. .. PLL_RES = 0xc
- // .. .. ==> 0XF8000118[7:4] = 0x0000000CU
- // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U
- // .. .. PLL_CP = 0x2
- // .. .. ==> 0XF8000118[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. LOCK_CNT = 0x145
- // .. .. ==> 0XF8000118[21:12] = 0x00000145U
- // .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U
- // .. ..
- EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U),
- // .. .. .. START: UPDATE FB_DIV
- // .. .. .. PLL_FDIV = 0x1e
- // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU
- // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U),
- // .. .. .. FINISH: UPDATE FB_DIV
- // .. .. .. START: BY PASS PLL
- // .. .. .. PLL_BYPASS_FORCE = 1
- // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
- // .. .. .. FINISH: BY PASS PLL
- // .. .. .. START: ASSERT RESET
- // .. .. .. PLL_RESET = 1
- // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
- // .. .. .. FINISH: ASSERT RESET
- // .. .. .. START: DEASSERT RESET
- // .. .. .. PLL_RESET = 0
- // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
- // .. .. .. FINISH: DEASSERT RESET
- // .. .. .. START: CHECK PLL STATUS
- // .. .. .. IO_PLL_LOCK = 1
- // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. .. ..
- EMIT_MASKPOLL(0XF800010C, 0x00000004U),
- // .. .. .. FINISH: CHECK PLL STATUS
- // .. .. .. START: REMOVE PLL BY PASS
- // .. .. .. PLL_BYPASS_FORCE = 0
- // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
- // .. .. .. FINISH: REMOVE PLL BY PASS
- // .. .. FINISH: IO PLL INIT
- // .. FINISH: PLL SLCR REGISTERS
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_clock_init_data_3_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: CLOCK CONTROL SLCR REGISTERS
- // .. CLKACT = 0x1
- // .. ==> 0XF8000128[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. DIVISOR0 = 0x23
- // .. ==> 0XF8000128[13:8] = 0x00000023U
- // .. ==> MASK : 0x00003F00U VAL : 0x00002300U
- // .. DIVISOR1 = 0x3
- // .. ==> 0XF8000128[25:20] = 0x00000003U
- // .. ==> MASK : 0x03F00000U VAL : 0x00300000U
- // ..
- EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U),
- // .. CLKACT = 0x1
- // .. ==> 0XF8000138[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000138[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
- // .. CLKACT = 0x1
- // .. ==> 0XF8000140[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000140[6:4] = 0x00000000U
- // .. ==> MASK : 0x00000070U VAL : 0x00000000U
- // .. DIVISOR = 0x8
- // .. ==> 0XF8000140[13:8] = 0x00000008U
- // .. ==> MASK : 0x00003F00U VAL : 0x00000800U
- // .. DIVISOR1 = 0x5
- // .. ==> 0XF8000140[25:20] = 0x00000005U
- // .. ==> MASK : 0x03F00000U VAL : 0x00500000U
- // ..
- EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00500801U),
- // .. CLKACT = 0x1
- // .. ==> 0XF800014C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. SRCSEL = 0x0
- // .. ==> 0XF800014C[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR = 0x5
- // .. ==> 0XF800014C[13:8] = 0x00000005U
- // .. ==> MASK : 0x00003F00U VAL : 0x00000500U
- // ..
- EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
- // .. CLKACT0 = 0x1
- // .. ==> 0XF8000150[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. CLKACT1 = 0x0
- // .. ==> 0XF8000150[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000150[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR = 0x14
- // .. ==> 0XF8000150[13:8] = 0x00000014U
- // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
- // ..
- EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U),
- // .. CLKACT0 = 0x0
- // .. ==> 0XF8000154[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. CLKACT1 = 0x1
- // .. ==> 0XF8000154[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000154[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR = 0x14
- // .. ==> 0XF8000154[13:8] = 0x00000014U
- // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
- // ..
- EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U),
- // .. CLKACT = 0x1
- // .. ==> 0XF8000168[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000168[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR = 0x5
- // .. ==> 0XF8000168[13:8] = 0x00000005U
- // .. ==> MASK : 0x00003F00U VAL : 0x00000500U
- // ..
- EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000170[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR0 = 0x14
- // .. ==> 0XF8000170[13:8] = 0x00000014U
- // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
- // .. DIVISOR1 = 0x1
- // .. ==> 0XF8000170[25:20] = 0x00000001U
- // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
- // ..
- EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00101400U),
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000180[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR0 = 0x14
- // .. ==> 0XF8000180[13:8] = 0x00000014U
- // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
- // .. DIVISOR1 = 0x1
- // .. ==> 0XF8000180[25:20] = 0x00000001U
- // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
- // ..
- EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00101400U),
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000190[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR0 = 0x14
- // .. ==> 0XF8000190[13:8] = 0x00000014U
- // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
- // .. DIVISOR1 = 0x1
- // .. ==> 0XF8000190[25:20] = 0x00000001U
- // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
- // ..
- EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101400U),
- // .. SRCSEL = 0x0
- // .. ==> 0XF80001A0[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR0 = 0x14
- // .. ==> 0XF80001A0[13:8] = 0x00000014U
- // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
- // .. DIVISOR1 = 0x1
- // .. ==> 0XF80001A0[25:20] = 0x00000001U
- // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
- // ..
- EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U),
- // .. CLK_621_TRUE = 0x1
- // .. ==> 0XF80001C4[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // ..
- EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
- // .. DMA_CPU_2XCLKACT = 0x1
- // .. ==> 0XF800012C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. USB0_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. USB1_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[3:3] = 0x00000001U
- // .. ==> MASK : 0x00000008U VAL : 0x00000008U
- // .. GEM0_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[6:6] = 0x00000001U
- // .. ==> MASK : 0x00000040U VAL : 0x00000040U
- // .. GEM1_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. SDI0_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[10:10] = 0x00000001U
- // .. ==> MASK : 0x00000400U VAL : 0x00000400U
- // .. SDI1_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. SPI0_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[14:14] = 0x00000000U
- // .. ==> MASK : 0x00004000U VAL : 0x00000000U
- // .. SPI1_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[15:15] = 0x00000000U
- // .. ==> MASK : 0x00008000U VAL : 0x00000000U
- // .. CAN0_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[16:16] = 0x00000000U
- // .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. CAN1_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[17:17] = 0x00000000U
- // .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. I2C0_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[18:18] = 0x00000001U
- // .. ==> MASK : 0x00040000U VAL : 0x00040000U
- // .. I2C1_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[19:19] = 0x00000001U
- // .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // .. UART0_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[20:20] = 0x00000000U
- // .. ==> MASK : 0x00100000U VAL : 0x00000000U
- // .. UART1_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[21:21] = 0x00000001U
- // .. ==> MASK : 0x00200000U VAL : 0x00200000U
- // .. GPIO_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[22:22] = 0x00000001U
- // .. ==> MASK : 0x00400000U VAL : 0x00400000U
- // .. LQSPI_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[23:23] = 0x00000001U
- // .. ==> MASK : 0x00800000U VAL : 0x00800000U
- // .. SMC_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[24:24] = 0x00000001U
- // .. ==> MASK : 0x01000000U VAL : 0x01000000U
- // ..
- EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC044DU),
- // .. FINISH: CLOCK CONTROL SLCR REGISTERS
- // .. START: THIS SHOULD BE BLANK
- // .. FINISH: THIS SHOULD BE BLANK
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_ddr_init_data_3_0[] = {
- // START: top
- // .. START: DDR INITIALIZATION
- // .. .. START: LOCK DDR
- // .. .. reg_ddrc_soft_rstb = 0
- // .. .. ==> 0XF8006000[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_powerdown_en = 0x0
- // .. .. ==> 0XF8006000[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_ddrc_data_bus_width = 0x0
- // .. .. ==> 0XF8006000[3:2] = 0x00000000U
- // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U
- // .. .. reg_ddrc_burst8_refresh = 0x0
- // .. .. ==> 0XF8006000[6:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U
- // .. .. reg_ddrc_rdwr_idle_gap = 0x1
- // .. .. ==> 0XF8006000[13:7] = 0x00000001U
- // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U
- // .. .. reg_ddrc_dis_rd_bypass = 0x0
- // .. .. ==> 0XF8006000[14:14] = 0x00000000U
- // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_act_bypass = 0x0
- // .. .. ==> 0XF8006000[15:15] = 0x00000000U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_auto_refresh = 0x0
- // .. .. ==> 0XF8006000[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
- // .. .. FINISH: LOCK DDR
- // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81
- // .. .. ==> 0XF8006004[11:0] = 0x00000081U
- // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U
- // .. .. reserved_reg_ddrc_active_ranks = 0x1
- // .. .. ==> 0XF8006004[13:12] = 0x00000001U
- // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U
- // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
- // .. .. ==> 0XF8006004[18:14] = 0x00000000U
- // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU ,0x00001081U),
- // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
- // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
- // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU
- // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
- // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
- // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U
- // .. .. reg_ddrc_hpr_xact_run_length = 0xf
- // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
- // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U
- // .. ..
- EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
- // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
- // .. .. ==> 0XF800600C[10:0] = 0x00000001U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U
- // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
- // .. .. ==> 0XF800600C[21:11] = 0x00000002U
- // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U
- // .. .. reg_ddrc_lpr_xact_run_length = 0x8
- // .. .. ==> 0XF800600C[25:22] = 0x00000008U
- // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U
- // .. ..
- EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
- // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
- // .. .. ==> 0XF8006010[10:0] = 0x00000001U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U
- // .. .. reg_ddrc_w_xact_run_length = 0x8
- // .. .. ==> 0XF8006010[14:11] = 0x00000008U
- // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U
- // .. .. reg_ddrc_w_max_starve_x32 = 0x2
- // .. .. ==> 0XF8006010[25:15] = 0x00000002U
- // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U
- // .. ..
- EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
- // .. .. reg_ddrc_t_rc = 0x1b
- // .. .. ==> 0XF8006014[5:0] = 0x0000001BU
- // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001BU
- // .. .. reg_ddrc_t_rfc_min = 0x56
- // .. .. ==> 0XF8006014[13:6] = 0x00000056U
- // .. .. ==> MASK : 0x00003FC0U VAL : 0x00001580U
- // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
- // .. .. ==> 0XF8006014[20:14] = 0x00000010U
- // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U
- // .. ..
- EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004159BU),
- // .. .. reg_ddrc_wr2pre = 0x12
- // .. .. ==> 0XF8006018[4:0] = 0x00000012U
- // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U
- // .. .. reg_ddrc_powerdown_to_x32 = 0x6
- // .. .. ==> 0XF8006018[9:5] = 0x00000006U
- // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U
- // .. .. reg_ddrc_t_faw = 0x10
- // .. .. ==> 0XF8006018[15:10] = 0x00000010U
- // .. .. ==> MASK : 0x0000FC00U VAL : 0x00004000U
- // .. .. reg_ddrc_t_ras_max = 0x24
- // .. .. ==> 0XF8006018[21:16] = 0x00000024U
- // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U
- // .. .. reg_ddrc_t_ras_min = 0x14
- // .. .. ==> 0XF8006018[26:22] = 0x00000014U
- // .. .. ==> MASK : 0x07C00000U VAL : 0x05000000U
- // .. .. reg_ddrc_t_cke = 0x4
- // .. .. ==> 0XF8006018[31:28] = 0x00000004U
- // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x452440D2U),
- // .. .. reg_ddrc_write_latency = 0x5
- // .. .. ==> 0XF800601C[4:0] = 0x00000005U
- // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U
- // .. .. reg_ddrc_rd2wr = 0x7
- // .. .. ==> 0XF800601C[9:5] = 0x00000007U
- // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U
- // .. .. reg_ddrc_wr2rd = 0xe
- // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
- // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U
- // .. .. reg_ddrc_t_xp = 0x4
- // .. .. ==> 0XF800601C[19:15] = 0x00000004U
- // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U
- // .. .. reg_ddrc_pad_pd = 0x0
- // .. .. ==> 0XF800601C[22:20] = 0x00000000U
- // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U
- // .. .. reg_ddrc_rd2pre = 0x4
- // .. .. ==> 0XF800601C[27:23] = 0x00000004U
- // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U
- // .. .. reg_ddrc_t_rcd = 0x7
- // .. .. ==> 0XF800601C[31:28] = 0x00000007U
- // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U
- // .. ..
- EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
- // .. .. reg_ddrc_t_ccd = 0x4
- // .. .. ==> 0XF8006020[4:2] = 0x00000004U
- // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U
- // .. .. reg_ddrc_t_rrd = 0x4
- // .. .. ==> 0XF8006020[7:5] = 0x00000004U
- // .. .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. .. reg_ddrc_refresh_margin = 0x2
- // .. .. ==> 0XF8006020[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. reg_ddrc_t_rp = 0x7
- // .. .. ==> 0XF8006020[15:12] = 0x00000007U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U
- // .. .. reg_ddrc_refresh_to_x32 = 0x8
- // .. .. ==> 0XF8006020[20:16] = 0x00000008U
- // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U
- // .. .. reg_ddrc_mobile = 0x0
- // .. .. ==> 0XF8006020[22:22] = 0x00000000U
- // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U
- // .. .. reg_ddrc_en_dfi_dram_clk_disable = 0x0
- // .. .. ==> 0XF8006020[23:23] = 0x00000000U
- // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U
- // .. .. reg_ddrc_read_latency = 0x7
- // .. .. ==> 0XF8006020[28:24] = 0x00000007U
- // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U
- // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
- // .. .. ==> 0XF8006020[29:29] = 0x00000001U
- // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U
- // .. .. reg_ddrc_dis_pad_pd = 0x0
- // .. .. ==> 0XF8006020[30:30] = 0x00000000U
- // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU ,0x27087290U),
- // .. .. reg_ddrc_en_2t_timing_mode = 0x0
- // .. .. ==> 0XF8006024[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_prefer_write = 0x0
- // .. .. ==> 0XF8006024[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_wr = 0x0
- // .. .. ==> 0XF8006024[6:6] = 0x00000000U
- // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_addr = 0x0
- // .. .. ==> 0XF8006024[8:7] = 0x00000000U
- // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_data = 0x0
- // .. .. ==> 0XF8006024[24:9] = 0x00000000U
- // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U
- // .. .. ddrc_reg_mr_wr_busy = 0x0
- // .. .. ==> 0XF8006024[25:25] = 0x00000000U
- // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_type = 0x0
- // .. .. ==> 0XF8006024[26:26] = 0x00000000U
- // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_rdata_valid = 0x0
- // .. .. ==> 0XF8006024[27:27] = 0x00000000U
- // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U ,0x00000000U),
- // .. .. reg_ddrc_final_wait_x32 = 0x7
- // .. .. ==> 0XF8006028[6:0] = 0x00000007U
- // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U
- // .. .. reg_ddrc_pre_ocd_x32 = 0x0
- // .. .. ==> 0XF8006028[10:7] = 0x00000000U
- // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U
- // .. .. reg_ddrc_t_mrd = 0x4
- // .. .. ==> 0XF8006028[13:11] = 0x00000004U
- // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U
- // .. ..
- EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
- // .. .. reg_ddrc_emr2 = 0x8
- // .. .. ==> 0XF800602C[15:0] = 0x00000008U
- // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U
- // .. .. reg_ddrc_emr3 = 0x0
- // .. .. ==> 0XF800602C[31:16] = 0x00000000U
- // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
- // .. .. reg_ddrc_mr = 0x930
- // .. .. ==> 0XF8006030[15:0] = 0x00000930U
- // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U
- // .. .. reg_ddrc_emr = 0x4
- // .. .. ==> 0XF8006030[31:16] = 0x00000004U
- // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U
- // .. ..
- EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
- // .. .. reg_ddrc_burst_rdwr = 0x4
- // .. .. ==> 0XF8006034[3:0] = 0x00000004U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U
- // .. .. reg_ddrc_pre_cke_x1024 = 0x105
- // .. .. ==> 0XF8006034[13:4] = 0x00000105U
- // .. .. ==> MASK : 0x00003FF0U VAL : 0x00001050U
- // .. .. reg_ddrc_post_cke_x1024 = 0x1
- // .. .. ==> 0XF8006034[25:16] = 0x00000001U
- // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U
- // .. .. reg_ddrc_burstchop = 0x0
- // .. .. ==> 0XF8006034[28:28] = 0x00000000U
- // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U),
- // .. .. reg_ddrc_force_low_pri_n = 0x0
- // .. .. ==> 0XF8006038[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_dq = 0x0
- // .. .. ==> 0XF8006038[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006038, 0x00000003U ,0x00000000U),
- // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
- // .. .. ==> 0XF800603C[3:0] = 0x00000007U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U
- // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
- // .. .. ==> 0XF800603C[7:4] = 0x00000007U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U
- // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
- // .. .. ==> 0XF800603C[11:8] = 0x00000007U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U
- // .. .. reg_ddrc_addrmap_col_b5 = 0x0
- // .. .. ==> 0XF800603C[15:12] = 0x00000000U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b6 = 0x0
- // .. .. ==> 0XF800603C[19:16] = 0x00000000U
- // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
- // .. .. reg_ddrc_addrmap_col_b2 = 0x0
- // .. .. ==> 0XF8006040[3:0] = 0x00000000U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b3 = 0x0
- // .. .. ==> 0XF8006040[7:4] = 0x00000000U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b4 = 0x0
- // .. .. ==> 0XF8006040[11:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b7 = 0x0
- // .. .. ==> 0XF8006040[15:12] = 0x00000000U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b8 = 0x0
- // .. .. ==> 0XF8006040[19:16] = 0x00000000U
- // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b9 = 0xf
- // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
- // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U
- // .. .. reg_ddrc_addrmap_col_b10 = 0xf
- // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
- // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U
- // .. .. reg_ddrc_addrmap_col_b11 = 0xf
- // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
- // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
- // .. .. reg_ddrc_addrmap_row_b0 = 0x6
- // .. .. ==> 0XF8006044[3:0] = 0x00000006U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U
- // .. .. reg_ddrc_addrmap_row_b1 = 0x6
- // .. .. ==> 0XF8006044[7:4] = 0x00000006U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U
- // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
- // .. .. ==> 0XF8006044[11:8] = 0x00000006U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U
- // .. .. reg_ddrc_addrmap_row_b12 = 0x6
- // .. .. ==> 0XF8006044[15:12] = 0x00000006U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U
- // .. .. reg_ddrc_addrmap_row_b13 = 0x6
- // .. .. ==> 0XF8006044[19:16] = 0x00000006U
- // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U
- // .. .. reg_ddrc_addrmap_row_b14 = 0x6
- // .. .. ==> 0XF8006044[23:20] = 0x00000006U
- // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U
- // .. .. reg_ddrc_addrmap_row_b15 = 0xf
- // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
- // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U),
- // .. .. reg_phy_rd_local_odt = 0x0
- // .. .. ==> 0XF8006048[13:12] = 0x00000000U
- // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U
- // .. .. reg_phy_wr_local_odt = 0x3
- // .. .. ==> 0XF8006048[15:14] = 0x00000003U
- // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U
- // .. .. reg_phy_idle_local_odt = 0x3
- // .. .. ==> 0XF8006048[17:16] = 0x00000003U
- // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U
- // .. ..
- EMIT_MASKWRITE(0XF8006048, 0x0003F000U ,0x0003C000U),
- // .. .. reg_phy_rd_cmd_to_data = 0x0
- // .. .. ==> 0XF8006050[3:0] = 0x00000000U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
- // .. .. reg_phy_wr_cmd_to_data = 0x0
- // .. .. ==> 0XF8006050[7:4] = 0x00000000U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. .. reg_phy_rdc_we_to_re_delay = 0x8
- // .. .. ==> 0XF8006050[11:8] = 0x00000008U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U
- // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
- // .. .. ==> 0XF8006050[15:15] = 0x00000000U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
- // .. .. reg_phy_use_fixed_re = 0x1
- // .. .. ==> 0XF8006050[16:16] = 0x00000001U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U
- // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
- // .. .. ==> 0XF8006050[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
- // .. .. ==> 0XF8006050[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_phy_clk_stall_level = 0x0
- // .. .. ==> 0XF8006050[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
- // .. .. ==> 0XF8006050[27:24] = 0x00000007U
- // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U
- // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
- // .. .. ==> 0XF8006050[31:28] = 0x00000007U
- // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
- // .. .. reg_ddrc_dis_dll_calib = 0x0
- // .. .. ==> 0XF8006058[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006058, 0x00010000U ,0x00000000U),
- // .. .. reg_ddrc_rd_odt_delay = 0x3
- // .. .. ==> 0XF800605C[3:0] = 0x00000003U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U
- // .. .. reg_ddrc_wr_odt_delay = 0x0
- // .. .. ==> 0XF800605C[7:4] = 0x00000000U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. .. reg_ddrc_rd_odt_hold = 0x0
- // .. .. ==> 0XF800605C[11:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U
- // .. .. reg_ddrc_wr_odt_hold = 0x5
- // .. .. ==> 0XF800605C[15:12] = 0x00000005U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U
- // .. ..
- EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
- // .. .. reg_ddrc_pageclose = 0x0
- // .. .. ==> 0XF8006060[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_lpr_num_entries = 0x1f
- // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
- // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU
- // .. .. reg_ddrc_auto_pre_en = 0x0
- // .. .. ==> 0XF8006060[7:7] = 0x00000000U
- // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. .. reg_ddrc_refresh_update_level = 0x0
- // .. .. ==> 0XF8006060[8:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_wc = 0x0
- // .. .. ==> 0XF8006060[9:9] = 0x00000000U
- // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_collision_page_opt = 0x0
- // .. .. ==> 0XF8006060[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_ddrc_selfref_en = 0x0
- // .. .. ==> 0XF8006060[12:12] = 0x00000000U
- // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
- // .. .. reg_ddrc_go2critical_hysteresis = 0x0
- // .. .. ==> 0XF8006064[12:5] = 0x00000000U
- // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U
- // .. .. reg_arb_go2critical_en = 0x1
- // .. .. ==> 0XF8006064[17:17] = 0x00000001U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U
- // .. ..
- EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
- // .. .. reg_ddrc_wrlvl_ww = 0x41
- // .. .. ==> 0XF8006068[7:0] = 0x00000041U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U
- // .. .. reg_ddrc_rdlvl_rr = 0x41
- // .. .. ==> 0XF8006068[15:8] = 0x00000041U
- // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U
- // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
- // .. .. ==> 0XF8006068[25:16] = 0x00000028U
- // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U
- // .. ..
- EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
- // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
- // .. .. ==> 0XF800606C[7:0] = 0x00000010U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U
- // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
- // .. .. ==> 0XF800606C[15:8] = 0x00000016U
- // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U
- // .. ..
- EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
- // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1
- // .. .. ==> 0XF8006078[3:0] = 0x00000001U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U
- // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1
- // .. .. ==> 0XF8006078[7:4] = 0x00000001U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U
- // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1
- // .. .. ==> 0XF8006078[11:8] = 0x00000001U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U
- // .. .. reg_ddrc_t_cksre = 0x6
- // .. .. ==> 0XF8006078[15:12] = 0x00000006U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U
- // .. .. reg_ddrc_t_cksrx = 0x6
- // .. .. ==> 0XF8006078[19:16] = 0x00000006U
- // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U
- // .. .. reg_ddrc_t_ckesr = 0x4
- // .. .. ==> 0XF8006078[25:20] = 0x00000004U
- // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U
- // .. ..
- EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U),
- // .. .. reg_ddrc_t_ckpde = 0x2
- // .. .. ==> 0XF800607C[3:0] = 0x00000002U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U
- // .. .. reg_ddrc_t_ckpdx = 0x2
- // .. .. ==> 0XF800607C[7:4] = 0x00000002U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
- // .. .. reg_ddrc_t_ckdpde = 0x2
- // .. .. ==> 0XF800607C[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. reg_ddrc_t_ckdpdx = 0x2
- // .. .. ==> 0XF800607C[15:12] = 0x00000002U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U
- // .. .. reg_ddrc_t_ckcsx = 0x3
- // .. .. ==> 0XF800607C[19:16] = 0x00000003U
- // .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U
- // .. ..
- EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U),
- // .. .. reg_ddrc_dis_auto_zq = 0x0
- // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_ddr3 = 0x1
- // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. .. reg_ddrc_t_mod = 0x200
- // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
- // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U
- // .. .. reg_ddrc_t_zq_long_nop = 0x200
- // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
- // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U
- // .. .. reg_ddrc_t_zq_short_nop = 0x40
- // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
- // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
- // .. .. t_zq_short_interval_x1024 = 0xcb73
- // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U
- // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U
- // .. .. dram_rstn_x1024 = 0x69
- // .. .. ==> 0XF80060A8[27:20] = 0x00000069U
- // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U
- // .. ..
- EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
- // .. .. deeppowerdown_en = 0x0
- // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. deeppowerdown_to_x1024 = 0xff
- // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
- // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU
- // .. ..
- EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
- // .. .. dfi_wrlvl_max_x1024 = 0xfff
- // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
- // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU
- // .. .. dfi_rdlvl_max_x1024 = 0xfff
- // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
- // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U
- // .. .. ddrc_reg_twrlvl_max_error = 0x0
- // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
- // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U
- // .. .. ddrc_reg_trdlvl_max_error = 0x0
- // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
- // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
- // .. .. reg_ddrc_dfi_wr_level_en = 0x1
- // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
- // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U
- // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
- // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
- // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U
- // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
- // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
- // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
- // .. .. reg_ddrc_skip_ocd = 0x1
- // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
- // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U
- // .. ..
- EMIT_MASKWRITE(0XF80060B4, 0x00000200U ,0x00000200U),
- // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
- // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
- // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U
- // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
- // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
- // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U
- // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
- // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
- // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U
- // .. ..
- EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
- // .. .. START: RESET ECC ERROR
- // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1
- // .. .. ==> 0XF80060C4[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. Clear_Correctable_DRAM_ECC_error = 1
- // .. .. ==> 0XF80060C4[1:1] = 0x00000001U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. ..
- EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U),
- // .. .. FINISH: RESET ECC ERROR
- // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
- // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
- // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
- // .. .. CORR_ECC_LOG_VALID = 0x0
- // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. ECC_CORRECTED_BIT_NUM = 0x0
- // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
- // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
- // .. .. UNCORR_ECC_LOG_VALID = 0x0
- // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
- // .. .. STAT_NUM_CORR_ERR = 0x0
- // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
- // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U
- // .. .. STAT_NUM_UNCORR_ERR = 0x0
- // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
- // .. .. reg_ddrc_ecc_mode = 0x0
- // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_scrub = 0x1
- // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U
- // .. ..
- EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
- // .. .. reg_phy_dif_on = 0x0
- // .. .. ==> 0XF8006114[3:0] = 0x00000000U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
- // .. .. reg_phy_dif_off = 0x0
- // .. .. ==> 0XF8006114[7:4] = 0x00000000U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
- // .. .. reg_phy_data_slice_in_use = 0x1
- // .. .. ==> 0XF8006118[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_phy_rdlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006118[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_inc_mode = 0x0
- // .. .. ==> 0XF8006118[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_wrlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006118[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_bist_shift_dq = 0x0
- // .. .. ==> 0XF8006118[14:6] = 0x00000000U
- // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. .. reg_phy_bist_err_clr = 0x0
- // .. .. ==> 0XF8006118[23:15] = 0x00000000U
- // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. .. reg_phy_dq_offset = 0x40
- // .. .. ==> 0XF8006118[30:24] = 0x00000040U
- // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU ,0x40000001U),
- // .. .. reg_phy_data_slice_in_use = 0x1
- // .. .. ==> 0XF800611C[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_phy_rdlvl_inc_mode = 0x0
- // .. .. ==> 0XF800611C[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_inc_mode = 0x0
- // .. .. ==> 0XF800611C[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_wrlvl_inc_mode = 0x0
- // .. .. ==> 0XF800611C[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_bist_shift_dq = 0x0
- // .. .. ==> 0XF800611C[14:6] = 0x00000000U
- // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. .. reg_phy_bist_err_clr = 0x0
- // .. .. ==> 0XF800611C[23:15] = 0x00000000U
- // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. .. reg_phy_dq_offset = 0x40
- // .. .. ==> 0XF800611C[30:24] = 0x00000040U
- // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU ,0x40000001U),
- // .. .. reg_phy_data_slice_in_use = 0x1
- // .. .. ==> 0XF8006120[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_phy_rdlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006120[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_inc_mode = 0x0
- // .. .. ==> 0XF8006120[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_wrlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006120[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_bist_shift_dq = 0x0
- // .. .. ==> 0XF8006120[14:6] = 0x00000000U
- // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. .. reg_phy_bist_err_clr = 0x0
- // .. .. ==> 0XF8006120[23:15] = 0x00000000U
- // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. .. reg_phy_dq_offset = 0x40
- // .. .. ==> 0XF8006120[30:24] = 0x00000040U
- // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU ,0x40000001U),
- // .. .. reg_phy_data_slice_in_use = 0x1
- // .. .. ==> 0XF8006124[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_phy_rdlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006124[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_inc_mode = 0x0
- // .. .. ==> 0XF8006124[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_wrlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006124[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_bist_shift_dq = 0x0
- // .. .. ==> 0XF8006124[14:6] = 0x00000000U
- // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. .. reg_phy_bist_err_clr = 0x0
- // .. .. ==> 0XF8006124[23:15] = 0x00000000U
- // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. .. reg_phy_dq_offset = 0x40
- // .. .. ==> 0XF8006124[30:24] = 0x00000040U
- // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU ,0x40000001U),
- // .. .. reg_phy_wrlvl_init_ratio = 0x1e
- // .. .. ==> 0XF800612C[9:0] = 0x0000001EU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x0000001EU
- // .. .. reg_phy_gatelvl_init_ratio = 0xee
- // .. .. ==> 0XF800612C[19:10] = 0x000000EEU
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x0003B800U
- // .. ..
- EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0003B81EU),
- // .. .. reg_phy_wrlvl_init_ratio = 0x25
- // .. .. ==> 0XF8006130[9:0] = 0x00000025U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000025U
- // .. .. reg_phy_gatelvl_init_ratio = 0x10d
- // .. .. ==> 0XF8006130[19:10] = 0x0000010DU
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x00043400U
- // .. ..
- EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00043425U),
- // .. .. reg_phy_wrlvl_init_ratio = 0x19
- // .. .. ==> 0XF8006134[9:0] = 0x00000019U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000019U
- // .. .. reg_phy_gatelvl_init_ratio = 0xf3
- // .. .. ==> 0XF8006134[19:10] = 0x000000F3U
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x0003CC00U
- // .. ..
- EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0003CC19U),
- // .. .. reg_phy_wrlvl_init_ratio = 0x2a
- // .. .. ==> 0XF8006138[9:0] = 0x0000002AU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x0000002AU
- // .. .. reg_phy_gatelvl_init_ratio = 0x109
- // .. .. ==> 0XF8006138[19:10] = 0x00000109U
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x00042400U
- // .. ..
- EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0004242AU),
- // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. .. ==> 0XF8006140[9:0] = 0x00000035U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. .. reg_phy_rd_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006140[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006140[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
- // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. .. ==> 0XF8006144[9:0] = 0x00000035U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. .. reg_phy_rd_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006144[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006144[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
- // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. .. ==> 0XF8006148[9:0] = 0x00000035U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. .. reg_phy_rd_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006148[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006148[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
- // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. .. ==> 0XF800614C[9:0] = 0x00000035U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. .. reg_phy_rd_dqs_slave_force = 0x0
- // .. .. ==> 0XF800614C[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. .. ==> 0XF800614C[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
- // .. .. reg_phy_wr_dqs_slave_ratio = 0x9e
- // .. .. ==> 0XF8006154[9:0] = 0x0000009EU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x0000009EU
- // .. .. reg_phy_wr_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006154[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006154[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x0000009EU),
- // .. .. reg_phy_wr_dqs_slave_ratio = 0xa5
- // .. .. ==> 0XF8006158[9:0] = 0x000000A5U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000000A5U
- // .. .. reg_phy_wr_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006158[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006158[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x000000A5U),
- // .. .. reg_phy_wr_dqs_slave_ratio = 0x99
- // .. .. ==> 0XF800615C[9:0] = 0x00000099U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000099U
- // .. .. reg_phy_wr_dqs_slave_force = 0x0
- // .. .. ==> 0XF800615C[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. .. ==> 0XF800615C[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000099U),
- // .. .. reg_phy_wr_dqs_slave_ratio = 0xaa
- // .. .. ==> 0XF8006160[9:0] = 0x000000AAU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000000AAU
- // .. .. reg_phy_wr_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006160[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006160[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x000000AAU),
- // .. .. reg_phy_fifo_we_slave_ratio = 0x143
- // .. .. ==> 0XF8006168[10:0] = 0x00000143U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x00000143U
- // .. .. reg_phy_fifo_we_in_force = 0x0
- // .. .. ==> 0XF8006168[11:11] = 0x00000000U
- // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. .. reg_phy_fifo_we_in_delay = 0x0
- // .. .. ==> 0XF8006168[20:12] = 0x00000000U
- // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000143U),
- // .. .. reg_phy_fifo_we_slave_ratio = 0x162
- // .. .. ==> 0XF800616C[10:0] = 0x00000162U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x00000162U
- // .. .. reg_phy_fifo_we_in_force = 0x0
- // .. .. ==> 0XF800616C[11:11] = 0x00000000U
- // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. .. reg_phy_fifo_we_in_delay = 0x0
- // .. .. ==> 0XF800616C[20:12] = 0x00000000U
- // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x00000162U),
- // .. .. reg_phy_fifo_we_slave_ratio = 0x148
- // .. .. ==> 0XF8006170[10:0] = 0x00000148U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x00000148U
- // .. .. reg_phy_fifo_we_in_force = 0x0
- // .. .. ==> 0XF8006170[11:11] = 0x00000000U
- // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. .. reg_phy_fifo_we_in_delay = 0x0
- // .. .. ==> 0XF8006170[20:12] = 0x00000000U
- // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000148U),
- // .. .. reg_phy_fifo_we_slave_ratio = 0x15e
- // .. .. ==> 0XF8006174[10:0] = 0x0000015EU
- // .. .. ==> MASK : 0x000007FFU VAL : 0x0000015EU
- // .. .. reg_phy_fifo_we_in_force = 0x0
- // .. .. ==> 0XF8006174[11:11] = 0x00000000U
- // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. .. reg_phy_fifo_we_in_delay = 0x0
- // .. .. ==> 0XF8006174[20:12] = 0x00000000U
- // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x0000015EU),
- // .. .. reg_phy_wr_data_slave_ratio = 0xde
- // .. .. ==> 0XF800617C[9:0] = 0x000000DEU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000000DEU
- // .. .. reg_phy_wr_data_slave_force = 0x0
- // .. .. ==> 0XF800617C[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_data_slave_delay = 0x0
- // .. .. ==> 0XF800617C[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000DEU),
- // .. .. reg_phy_wr_data_slave_ratio = 0xe5
- // .. .. ==> 0XF8006180[9:0] = 0x000000E5U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000000E5U
- // .. .. reg_phy_wr_data_slave_force = 0x0
- // .. .. ==> 0XF8006180[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_data_slave_delay = 0x0
- // .. .. ==> 0XF8006180[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000E5U),
- // .. .. reg_phy_wr_data_slave_ratio = 0xd9
- // .. .. ==> 0XF8006184[9:0] = 0x000000D9U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000000D9U
- // .. .. reg_phy_wr_data_slave_force = 0x0
- // .. .. ==> 0XF8006184[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_data_slave_delay = 0x0
- // .. .. ==> 0XF8006184[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000D9U),
- // .. .. reg_phy_wr_data_slave_ratio = 0xea
- // .. .. ==> 0XF8006188[9:0] = 0x000000EAU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000000EAU
- // .. .. reg_phy_wr_data_slave_force = 0x0
- // .. .. ==> 0XF8006188[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_data_slave_delay = 0x0
- // .. .. ==> 0XF8006188[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000EAU),
- // .. .. reg_phy_bl2 = 0x0
- // .. .. ==> 0XF8006190[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_at_spd_atpg = 0x0
- // .. .. ==> 0XF8006190[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_bist_enable = 0x0
- // .. .. ==> 0XF8006190[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_bist_force_err = 0x0
- // .. .. ==> 0XF8006190[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. reg_phy_bist_mode = 0x0
- // .. .. ==> 0XF8006190[6:5] = 0x00000000U
- // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. .. reg_phy_invert_clkout = 0x1
- // .. .. ==> 0XF8006190[7:7] = 0x00000001U
- // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. .. reg_phy_sel_logic = 0x0
- // .. .. ==> 0XF8006190[9:9] = 0x00000000U
- // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U
- // .. .. reg_phy_ctrl_slave_ratio = 0x100
- // .. .. ==> 0XF8006190[19:10] = 0x00000100U
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U
- // .. .. reg_phy_ctrl_slave_force = 0x0
- // .. .. ==> 0XF8006190[20:20] = 0x00000000U
- // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U
- // .. .. reg_phy_ctrl_slave_delay = 0x0
- // .. .. ==> 0XF8006190[27:21] = 0x00000000U
- // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U
- // .. .. reg_phy_lpddr = 0x0
- // .. .. ==> 0XF8006190[29:29] = 0x00000000U
- // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U
- // .. .. reg_phy_cmd_latency = 0x0
- // .. .. ==> 0XF8006190[30:30] = 0x00000000U
- // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU ,0x00040080U),
- // .. .. reg_phy_wr_rl_delay = 0x2
- // .. .. ==> 0XF8006194[4:0] = 0x00000002U
- // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U
- // .. .. reg_phy_rd_rl_delay = 0x4
- // .. .. ==> 0XF8006194[9:5] = 0x00000004U
- // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U
- // .. .. reg_phy_dll_lock_diff = 0xf
- // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
- // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U
- // .. .. reg_phy_use_wr_level = 0x1
- // .. .. ==> 0XF8006194[14:14] = 0x00000001U
- // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U
- // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
- // .. .. ==> 0XF8006194[15:15] = 0x00000001U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U
- // .. .. reg_phy_use_rd_data_eye_level = 0x1
- // .. .. ==> 0XF8006194[16:16] = 0x00000001U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U
- // .. .. reg_phy_dis_calib_rst = 0x0
- // .. .. ==> 0XF8006194[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_phy_ctrl_slave_delay = 0x0
- // .. .. ==> 0XF8006194[19:18] = 0x00000000U
- // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
- // .. .. reg_arb_page_addr_mask = 0x0
- // .. .. ==> 0XF8006204[31:0] = 0x00000000U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
- // .. .. reg_arb_pri_wr_portn = 0x3ff
- // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_wr_portn = 0x0
- // .. .. ==> 0XF8006208[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. .. ==> 0XF8006208[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. .. ==> 0XF8006208[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006208, 0x000703FFU ,0x000003FFU),
- // .. .. reg_arb_pri_wr_portn = 0x3ff
- // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_wr_portn = 0x0
- // .. .. ==> 0XF800620C[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. .. ==> 0XF800620C[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. .. ==> 0XF800620C[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800620C, 0x000703FFU ,0x000003FFU),
- // .. .. reg_arb_pri_wr_portn = 0x3ff
- // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_wr_portn = 0x0
- // .. .. ==> 0XF8006210[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. .. ==> 0XF8006210[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. .. ==> 0XF8006210[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006210, 0x000703FFU ,0x000003FFU),
- // .. .. reg_arb_pri_wr_portn = 0x3ff
- // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_wr_portn = 0x0
- // .. .. ==> 0XF8006214[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. .. ==> 0XF8006214[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. .. ==> 0XF8006214[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006214, 0x000703FFU ,0x000003FFU),
- // .. .. reg_arb_pri_rd_portn = 0x3ff
- // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_rd_portn = 0x0
- // .. .. ==> 0XF8006218[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. .. ==> 0XF8006218[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. .. ==> 0XF8006218[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_set_hpr_rd_portn = 0x0
- // .. .. ==> 0XF8006218[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
- // .. .. reg_arb_pri_rd_portn = 0x3ff
- // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_rd_portn = 0x0
- // .. .. ==> 0XF800621C[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. .. ==> 0XF800621C[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. .. ==> 0XF800621C[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_set_hpr_rd_portn = 0x0
- // .. .. ==> 0XF800621C[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
- // .. .. reg_arb_pri_rd_portn = 0x3ff
- // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_rd_portn = 0x0
- // .. .. ==> 0XF8006220[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. .. ==> 0XF8006220[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. .. ==> 0XF8006220[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_set_hpr_rd_portn = 0x0
- // .. .. ==> 0XF8006220[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
- // .. .. reg_arb_pri_rd_portn = 0x3ff
- // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_rd_portn = 0x0
- // .. .. ==> 0XF8006224[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. .. ==> 0XF8006224[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. .. ==> 0XF8006224[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_set_hpr_rd_portn = 0x0
- // .. .. ==> 0XF8006224[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
- // .. .. reg_ddrc_lpddr2 = 0x0
- // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_derate_enable = 0x0
- // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_ddrc_mr4_margin = 0x0
- // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U ,0x00000000U),
- // .. .. reg_ddrc_mr4_read_interval = 0x0
- // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
- // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
- // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U
- // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
- // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
- // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U
- // .. .. reg_ddrc_t_mrw = 0x5
- // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
- // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U
- // .. ..
- EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
- // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8
- // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U
- // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
- // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
- // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U
- // .. ..
- EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
- // .. .. START: POLL ON DCI STATUS
- // .. .. DONE = 1
- // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
- // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // .. ..
- EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
- // .. .. FINISH: POLL ON DCI STATUS
- // .. .. START: UNLOCK DDR
- // .. .. reg_ddrc_soft_rstb = 0x1
- // .. .. ==> 0XF8006000[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_ddrc_powerdown_en = 0x0
- // .. .. ==> 0XF8006000[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_ddrc_data_bus_width = 0x0
- // .. .. ==> 0XF8006000[3:2] = 0x00000000U
- // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U
- // .. .. reg_ddrc_burst8_refresh = 0x0
- // .. .. ==> 0XF8006000[6:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U
- // .. .. reg_ddrc_rdwr_idle_gap = 1
- // .. .. ==> 0XF8006000[13:7] = 0x00000001U
- // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U
- // .. .. reg_ddrc_dis_rd_bypass = 0x0
- // .. .. ==> 0XF8006000[14:14] = 0x00000000U
- // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_act_bypass = 0x0
- // .. .. ==> 0XF8006000[15:15] = 0x00000000U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_auto_refresh = 0x0
- // .. .. ==> 0XF8006000[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
- // .. .. FINISH: UNLOCK DDR
- // .. .. START: CHECK DDR STATUS
- // .. .. ddrc_reg_operating_mode = 1
- // .. .. ==> 0XF8006054[2:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U
- // .. ..
- EMIT_MASKPOLL(0XF8006054, 0x00000007U),
- // .. .. FINISH: CHECK DDR STATUS
- // .. FINISH: DDR INITIALIZATION
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_mio_init_data_3_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: OCM REMAPPING
- // .. VREF_EN = 0x1
- // .. ==> 0XF8000B00[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. VREF_SEL = 0x0
- // .. ==> 0XF8000B00[6:4] = 0x00000000U
- // .. ==> MASK : 0x00000070U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B00, 0x00000071U ,0x00000001U),
- // .. FINISH: OCM REMAPPING
- // .. START: DDRIOB SETTINGS
- // .. reserved_INP_POWER = 0x0
- // .. ==> 0XF8000B40[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x0
- // .. ==> 0XF8000B40[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. DCI_UPDATE_B = 0x0
- // .. ==> 0XF8000B40[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x0
- // .. ==> 0XF8000B40[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. DCI_TYPE = 0x0
- // .. ==> 0XF8000B40[6:5] = 0x00000000U
- // .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. IBUF_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B40[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B40[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B40[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B40[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
- // .. reserved_INP_POWER = 0x0
- // .. ==> 0XF8000B44[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x0
- // .. ==> 0XF8000B44[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. DCI_UPDATE_B = 0x0
- // .. ==> 0XF8000B44[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x0
- // .. ==> 0XF8000B44[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. DCI_TYPE = 0x0
- // .. ==> 0XF8000B44[6:5] = 0x00000000U
- // .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. IBUF_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B44[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B44[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B44[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B44[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
- // .. reserved_INP_POWER = 0x0
- // .. ==> 0XF8000B48[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x1
- // .. ==> 0XF8000B48[2:1] = 0x00000001U
- // .. ==> MASK : 0x00000006U VAL : 0x00000002U
- // .. DCI_UPDATE_B = 0x0
- // .. ==> 0XF8000B48[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x1
- // .. ==> 0XF8000B48[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. DCI_TYPE = 0x3
- // .. ==> 0XF8000B48[6:5] = 0x00000003U
- // .. ==> MASK : 0x00000060U VAL : 0x00000060U
- // .. IBUF_DISABLE_MODE = 0
- // .. ==> 0XF8000B48[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0
- // .. ==> 0XF8000B48[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B48[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B48[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
- // .. reserved_INP_POWER = 0x0
- // .. ==> 0XF8000B4C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x1
- // .. ==> 0XF8000B4C[2:1] = 0x00000001U
- // .. ==> MASK : 0x00000006U VAL : 0x00000002U
- // .. DCI_UPDATE_B = 0x0
- // .. ==> 0XF8000B4C[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x1
- // .. ==> 0XF8000B4C[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. DCI_TYPE = 0x3
- // .. ==> 0XF8000B4C[6:5] = 0x00000003U
- // .. ==> MASK : 0x00000060U VAL : 0x00000060U
- // .. IBUF_DISABLE_MODE = 0
- // .. ==> 0XF8000B4C[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0
- // .. ==> 0XF8000B4C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B4C[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B4C[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
- // .. reserved_INP_POWER = 0x0
- // .. ==> 0XF8000B50[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x2
- // .. ==> 0XF8000B50[2:1] = 0x00000002U
- // .. ==> MASK : 0x00000006U VAL : 0x00000004U
- // .. DCI_UPDATE_B = 0x0
- // .. ==> 0XF8000B50[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x1
- // .. ==> 0XF8000B50[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. DCI_TYPE = 0x3
- // .. ==> 0XF8000B50[6:5] = 0x00000003U
- // .. ==> MASK : 0x00000060U VAL : 0x00000060U
- // .. IBUF_DISABLE_MODE = 0
- // .. ==> 0XF8000B50[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0
- // .. ==> 0XF8000B50[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B50[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B50[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
- // .. reserved_INP_POWER = 0x0
- // .. ==> 0XF8000B54[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x2
- // .. ==> 0XF8000B54[2:1] = 0x00000002U
- // .. ==> MASK : 0x00000006U VAL : 0x00000004U
- // .. DCI_UPDATE_B = 0x0
- // .. ==> 0XF8000B54[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x1
- // .. ==> 0XF8000B54[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. DCI_TYPE = 0x3
- // .. ==> 0XF8000B54[6:5] = 0x00000003U
- // .. ==> MASK : 0x00000060U VAL : 0x00000060U
- // .. IBUF_DISABLE_MODE = 0
- // .. ==> 0XF8000B54[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0
- // .. ==> 0XF8000B54[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B54[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B54[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
- // .. reserved_INP_POWER = 0x0
- // .. ==> 0XF8000B58[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x0
- // .. ==> 0XF8000B58[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. DCI_UPDATE_B = 0x0
- // .. ==> 0XF8000B58[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x0
- // .. ==> 0XF8000B58[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. DCI_TYPE = 0x0
- // .. ==> 0XF8000B58[6:5] = 0x00000000U
- // .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. IBUF_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B58[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B58[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B58[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B58[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
- // .. reserved_DRIVE_P = 0x1c
- // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
- // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
- // .. reserved_DRIVE_N = 0xc
- // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
- // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
- // .. reserved_SLEW_P = 0x3
- // .. ==> 0XF8000B5C[18:14] = 0x00000003U
- // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U
- // .. reserved_SLEW_N = 0x3
- // .. ==> 0XF8000B5C[23:19] = 0x00000003U
- // .. ==> MASK : 0x00F80000U VAL : 0x00180000U
- // .. reserved_GTL = 0x0
- // .. ==> 0XF8000B5C[26:24] = 0x00000000U
- // .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. reserved_RTERM = 0x0
- // .. ==> 0XF8000B5C[31:27] = 0x00000000U
- // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
- // .. reserved_DRIVE_P = 0x1c
- // .. ==> 0XF8000B60[6:0] = 0x0000001CU
- // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
- // .. reserved_DRIVE_N = 0xc
- // .. ==> 0XF8000B60[13:7] = 0x0000000CU
- // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
- // .. reserved_SLEW_P = 0x6
- // .. ==> 0XF8000B60[18:14] = 0x00000006U
- // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
- // .. reserved_SLEW_N = 0x1f
- // .. ==> 0XF8000B60[23:19] = 0x0000001FU
- // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
- // .. reserved_GTL = 0x0
- // .. ==> 0XF8000B60[26:24] = 0x00000000U
- // .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. reserved_RTERM = 0x0
- // .. ==> 0XF8000B60[31:27] = 0x00000000U
- // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
- // .. reserved_DRIVE_P = 0x1c
- // .. ==> 0XF8000B64[6:0] = 0x0000001CU
- // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
- // .. reserved_DRIVE_N = 0xc
- // .. ==> 0XF8000B64[13:7] = 0x0000000CU
- // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
- // .. reserved_SLEW_P = 0x6
- // .. ==> 0XF8000B64[18:14] = 0x00000006U
- // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
- // .. reserved_SLEW_N = 0x1f
- // .. ==> 0XF8000B64[23:19] = 0x0000001FU
- // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
- // .. reserved_GTL = 0x0
- // .. ==> 0XF8000B64[26:24] = 0x00000000U
- // .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. reserved_RTERM = 0x0
- // .. ==> 0XF8000B64[31:27] = 0x00000000U
- // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
- // .. reserved_DRIVE_P = 0x1c
- // .. ==> 0XF8000B68[6:0] = 0x0000001CU
- // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
- // .. reserved_DRIVE_N = 0xc
- // .. ==> 0XF8000B68[13:7] = 0x0000000CU
- // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
- // .. reserved_SLEW_P = 0x6
- // .. ==> 0XF8000B68[18:14] = 0x00000006U
- // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
- // .. reserved_SLEW_N = 0x1f
- // .. ==> 0XF8000B68[23:19] = 0x0000001FU
- // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
- // .. reserved_GTL = 0x0
- // .. ==> 0XF8000B68[26:24] = 0x00000000U
- // .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. reserved_RTERM = 0x0
- // .. ==> 0XF8000B68[31:27] = 0x00000000U
- // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
- // .. VREF_INT_EN = 0x1
- // .. ==> 0XF8000B6C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. VREF_SEL = 0x4
- // .. ==> 0XF8000B6C[4:1] = 0x00000004U
- // .. ==> MASK : 0x0000001EU VAL : 0x00000008U
- // .. VREF_EXT_EN = 0x0
- // .. ==> 0XF8000B6C[6:5] = 0x00000000U
- // .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. reserved_VREF_PULLUP_EN = 0x0
- // .. ==> 0XF8000B6C[8:7] = 0x00000000U
- // .. ==> MASK : 0x00000180U VAL : 0x00000000U
- // .. REFIO_EN = 0x1
- // .. ==> 0XF8000B6C[9:9] = 0x00000001U
- // .. ==> MASK : 0x00000200U VAL : 0x00000200U
- // .. reserved_REFIO_TEST = 0x3
- // .. ==> 0XF8000B6C[11:10] = 0x00000003U
- // .. ==> MASK : 0x00000C00U VAL : 0x00000C00U
- // .. reserved_REFIO_PULLUP_EN = 0x0
- // .. ==> 0XF8000B6C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. reserved_DRST_B_PULLUP_EN = 0x0
- // .. ==> 0XF8000B6C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // .. reserved_CKE_PULLUP_EN = 0x0
- // .. ==> 0XF8000B6C[14:14] = 0x00000000U
- // .. ==> MASK : 0x00004000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000E09U),
- // .. .. START: ASSERT RESET
- // .. .. RESET = 1
- // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. ..
- EMIT_MASKWRITE(0XF8000B70, 0x00000001U ,0x00000001U),
- // .. .. FINISH: ASSERT RESET
- // .. .. START: DEASSERT RESET
- // .. .. RESET = 0
- // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reserved_VRN_OUT = 0x1
- // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
- // .. ..
- EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
- // .. .. FINISH: DEASSERT RESET
- // .. .. RESET = 0x1
- // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ENABLE = 0x1
- // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. .. reserved_VRP_TRI = 0x0
- // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reserved_VRN_TRI = 0x0
- // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reserved_VRP_OUT = 0x0
- // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. reserved_VRN_OUT = 0x1
- // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
- // .. .. NREF_OPT1 = 0x0
- // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
- // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U
- // .. .. NREF_OPT2 = 0x0
- // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U
- // .. .. NREF_OPT4 = 0x1
- // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
- // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U
- // .. .. PREF_OPT1 = 0x0
- // .. .. ==> 0XF8000B70[15:14] = 0x00000000U
- // .. .. ==> MASK : 0x0000C000U VAL : 0x00000000U
- // .. .. PREF_OPT2 = 0x0
- // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
- // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U
- // .. .. UPDATE_CONTROL = 0x0
- // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
- // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U
- // .. .. reserved_INIT_COMPLETE = 0x0
- // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
- // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U
- // .. .. reserved_TST_CLK = 0x0
- // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
- // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U
- // .. .. reserved_TST_HLN = 0x0
- // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
- // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U
- // .. .. reserved_TST_HLP = 0x0
- // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
- // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U
- // .. .. reserved_TST_RST = 0x0
- // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
- // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
- // .. .. reserved_INT_DCI_EN = 0x0
- // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
- // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU ,0x00000823U),
- // .. FINISH: DDRIOB SETTINGS
- // .. START: MIO PROGRAMMING
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000700[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000700[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000700[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000700[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000700[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000700[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000700[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 1
- // .. ==> 0XF8000700[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000700[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001202U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000704[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000704[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000704[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000704[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000704[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000704[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000704[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 1
- // .. ==> 0XF8000704[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000704[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001202U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000708[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000708[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000708[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000708[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000708[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000708[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000708[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000708[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000708[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000202U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800070C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF800070C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF800070C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800070C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800070C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800070C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF800070C[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF800070C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800070C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000202U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000710[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000710[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000710[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000710[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000710[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000710[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000710[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000710[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000710[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000202U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000714[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000714[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000714[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000714[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000714[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000714[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000714[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000714[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000714[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000202U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000718[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000718[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000718[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000718[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000718[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000718[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000718[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000718[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000718[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000202U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800071C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800071C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF800071C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800071C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800071C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800071C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF800071C[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF800071C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800071C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000200U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000720[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000720[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000720[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000720[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000720[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000720[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000720[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000720[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000720[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000202U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000724[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000724[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000724[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000724[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000724[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000724[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000724[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 1
- // .. ==> 0XF8000724[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000724[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001202U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000728[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000728[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000728[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000728[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000728[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000728[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000728[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 1
- // .. ==> 0XF8000728[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000728[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001202U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800072C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF800072C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF800072C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800072C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800072C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800072C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF800072C[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 1
- // .. ==> 0XF800072C[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800072C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001202U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000730[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000730[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000730[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000730[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000730[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000730[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000730[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 1
- // .. ==> 0XF8000730[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000730[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001202U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000734[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000734[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000734[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000734[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000734[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000734[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000734[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 1
- // .. ==> 0XF8000734[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000734[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001202U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000738[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. Speed = 0
- // .. ==> 0XF8000738[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000738[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 1
- // .. ==> 0XF8000738[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000738[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000738, 0x00003F01U ,0x00001201U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF800073C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. Speed = 0
- // .. ==> 0XF800073C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF800073C[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 1
- // .. ==> 0XF800073C[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800073C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800073C, 0x00003F01U ,0x00001201U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000740[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000740[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000740[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000740[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000740[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000740[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 4
- // .. ==> 0XF8000740[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000740[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 1
- // .. ==> 0XF8000740[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // ..
- EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00002802U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000744[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000744[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000744[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000744[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000744[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000744[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 4
- // .. ==> 0XF8000744[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000744[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 1
- // .. ==> 0XF8000744[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // ..
- EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00002802U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000748[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000748[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000748[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000748[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000748[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000748[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 4
- // .. ==> 0XF8000748[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000748[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 1
- // .. ==> 0XF8000748[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // ..
- EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00002802U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800074C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF800074C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF800074C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800074C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800074C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800074C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 4
- // .. ==> 0XF800074C[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF800074C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 1
- // .. ==> 0XF800074C[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // ..
- EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00002802U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000750[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000750[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000750[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000750[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000750[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000750[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 4
- // .. ==> 0XF8000750[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000750[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 1
- // .. ==> 0XF8000750[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // ..
- EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00002802U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000754[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000754[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000754[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000754[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000754[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000754[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 4
- // .. ==> 0XF8000754[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000754[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 1
- // .. ==> 0XF8000754[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // ..
- EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00002802U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000758[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF8000758[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000758[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000758[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000758[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000758[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 4
- // .. ==> 0XF8000758[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000758[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000758[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000803U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF800075C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF800075C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF800075C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800075C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800075C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800075C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 4
- // .. ==> 0XF800075C[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF800075C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800075C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000803U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000760[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF8000760[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000760[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000760[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000760[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000760[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 4
- // .. ==> 0XF8000760[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000760[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000760[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000803U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000764[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF8000764[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000764[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000764[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000764[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000764[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 4
- // .. ==> 0XF8000764[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000764[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000764[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000803U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000768[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF8000768[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000768[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000768[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000768[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000768[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 4
- // .. ==> 0XF8000768[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000768[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000768[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000803U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF800076C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF800076C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF800076C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800076C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800076C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800076C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 4
- // .. ==> 0XF800076C[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF800076C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800076C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000803U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000770[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000770[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000770[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000770[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000770[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000770[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000770[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000770[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000770[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000774[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF8000774[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000774[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000774[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000774[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000774[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000774[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000774[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000774[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000778[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000778[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000778[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000778[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000778[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000778[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000778[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000778[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000778[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF800077C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF800077C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF800077C[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF800077C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800077C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800077C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF800077C[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF800077C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800077C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000780[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000780[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000780[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000780[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000780[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000780[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000780[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000780[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000780[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000784[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000784[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000784[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000784[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000784[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000784[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000784[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000784[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000784[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000788[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000788[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000788[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000788[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000788[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000788[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000788[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000788[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000788[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800078C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800078C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF800078C[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF800078C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800078C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800078C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF800078C[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF800078C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800078C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000790[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF8000790[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000790[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000790[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000790[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000790[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000790[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000790[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000790[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000794[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000794[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000794[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000794[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000794[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000794[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000794[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000794[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000794[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000798[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000798[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000798[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000798[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000798[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000798[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000798[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000798[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000798[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800079C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800079C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF800079C[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF800079C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800079C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800079C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF800079C[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF800079C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800079C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007A0[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007A0[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007A0[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007A0[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007A0[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF80007A0[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007A0[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007A0[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007A0[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000280U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007A4[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007A4[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007A4[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007A4[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007A4[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF80007A4[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007A4[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007A4[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007A4[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000280U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007A8[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007A8[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007A8[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007A8[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007A8[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF80007A8[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007A8[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007A8[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007A8[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000280U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007AC[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007AC[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007AC[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007AC[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007AC[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF80007AC[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007AC[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007AC[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007AC[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000280U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007B0[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007B0[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007B0[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007B0[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007B0[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF80007B0[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007B0[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007B0[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007B0[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000280U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007B4[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007B4[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007B4[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007B4[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007B4[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF80007B4[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007B4[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007B4[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007B4[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000280U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007B8[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007B8[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007B8[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007B8[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF80007B8[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF80007B8[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007B8[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 1
- // .. ==> 0XF80007B8[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007B8[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001200U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007BC[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007BC[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007BC[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007BC[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF80007BC[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF80007BC[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007BC[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 1
- // .. ==> 0XF80007BC[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007BC[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00001200U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007C0[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007C0[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007C0[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007C0[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 7
- // .. ==> 0XF80007C0[7:5] = 0x00000007U
- // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U
- // .. Speed = 0
- // .. ==> 0XF80007C0[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007C0[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007C0[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007C0[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF80007C4[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF80007C4[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007C4[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007C4[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 7
- // .. ==> 0XF80007C4[7:5] = 0x00000007U
- // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U
- // .. Speed = 0
- // .. ==> 0XF80007C4[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007C4[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007C4[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007C4[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007C8[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007C8[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007C8[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007C8[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 2
- // .. ==> 0XF80007C8[7:5] = 0x00000002U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000040U
- // .. Speed = 0
- // .. ==> 0XF80007C8[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007C8[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 1
- // .. ==> 0XF80007C8[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007C8[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001240U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007CC[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007CC[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007CC[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007CC[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 2
- // .. ==> 0XF80007CC[7:5] = 0x00000002U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000040U
- // .. Speed = 0
- // .. ==> 0XF80007CC[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007CC[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 1
- // .. ==> 0XF80007CC[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007CC[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001240U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007D0[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007D0[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007D0[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007D0[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007D0[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF80007D0[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007D0[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007D0[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007D0[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007D4[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007D4[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007D4[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007D4[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007D4[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF80007D4[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007D4[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007D4[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007D4[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U),
- // .. SDIO0_WP_SEL = 15
- // .. ==> 0XF8000830[5:0] = 0x0000000FU
- // .. ==> MASK : 0x0000003FU VAL : 0x0000000FU
- // .. SDIO0_CD_SEL = 14
- // .. ==> 0XF8000830[21:16] = 0x0000000EU
- // .. ==> MASK : 0x003F0000U VAL : 0x000E0000U
- // ..
- EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x000E000FU),
- // .. FINISH: MIO PROGRAMMING
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_peripherals_init_data_3_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
- // .. IBUF_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B48[7:7] = 0x00000001U
- // .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. TERM_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B48[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // ..
- EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
- // .. IBUF_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B4C[7:7] = 0x00000001U
- // .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. TERM_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B4C[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // ..
- EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
- // .. IBUF_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B50[7:7] = 0x00000001U
- // .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. TERM_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B50[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // ..
- EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
- // .. IBUF_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B54[7:7] = 0x00000001U
- // .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. TERM_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B54[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // ..
- EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
- // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // .. START: SRAM/NOR SET OPMODE
- // .. FINISH: SRAM/NOR SET OPMODE
- // .. START: UART REGISTERS
- // .. BDIV = 0x6
- // .. ==> 0XE0001034[7:0] = 0x00000006U
- // .. ==> MASK : 0x000000FFU VAL : 0x00000006U
- // ..
- EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
- // .. CD = 0x3e
- // .. ==> 0XE0001018[15:0] = 0x0000003EU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU
- // ..
- EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
- // .. STPBRK = 0x0
- // .. ==> 0XE0001000[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. STTBRK = 0x0
- // .. ==> 0XE0001000[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. RSTTO = 0x0
- // .. ==> 0XE0001000[6:6] = 0x00000000U
- // .. ==> MASK : 0x00000040U VAL : 0x00000000U
- // .. TXDIS = 0x0
- // .. ==> 0XE0001000[5:5] = 0x00000000U
- // .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. TXEN = 0x1
- // .. ==> 0XE0001000[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. RXDIS = 0x0
- // .. ==> 0XE0001000[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. RXEN = 0x1
- // .. ==> 0XE0001000[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. TXRES = 0x1
- // .. ==> 0XE0001000[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. RXRES = 0x1
- // .. ==> 0XE0001000[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // ..
- EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
- // .. CHMODE = 0x0
- // .. ==> 0XE0001004[9:8] = 0x00000000U
- // .. ==> MASK : 0x00000300U VAL : 0x00000000U
- // .. NBSTOP = 0x0
- // .. ==> 0XE0001004[7:6] = 0x00000000U
- // .. ==> MASK : 0x000000C0U VAL : 0x00000000U
- // .. PAR = 0x4
- // .. ==> 0XE0001004[5:3] = 0x00000004U
- // .. ==> MASK : 0x00000038U VAL : 0x00000020U
- // .. CHRL = 0x0
- // .. ==> 0XE0001004[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. CLKS = 0x0
- // .. ==> 0XE0001004[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XE0001004, 0x000003FFU ,0x00000020U),
- // .. FINISH: UART REGISTERS
- // .. START: QSPI REGISTERS
- // .. Holdb_dr = 1
- // .. ==> 0XE000D000[19:19] = 0x00000001U
- // .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // ..
- EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
- // .. FINISH: QSPI REGISTERS
- // .. START: PL POWER ON RESET REGISTERS
- // .. PCFG_POR_CNT_4K = 0
- // .. ==> 0XF8007000[29:29] = 0x00000000U
- // .. ==> MASK : 0x20000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
- // .. FINISH: PL POWER ON RESET REGISTERS
- // .. START: SMC TIMING CALCULATION REGISTER UPDATE
- // .. .. START: NAND SET CYCLE
- // .. .. FINISH: NAND SET CYCLE
- // .. .. START: OPMODE
- // .. .. FINISH: OPMODE
- // .. .. START: DIRECT COMMAND
- // .. .. FINISH: DIRECT COMMAND
- // .. .. START: SRAM/NOR CS0 SET CYCLE
- // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
- // .. .. START: DIRECT COMMAND
- // .. .. FINISH: DIRECT COMMAND
- // .. .. START: NOR CS0 BASE ADDRESS
- // .. .. FINISH: NOR CS0 BASE ADDRESS
- // .. .. START: SRAM/NOR CS1 SET CYCLE
- // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
- // .. .. START: DIRECT COMMAND
- // .. .. FINISH: DIRECT COMMAND
- // .. .. START: NOR CS1 BASE ADDRESS
- // .. .. FINISH: NOR CS1 BASE ADDRESS
- // .. .. START: USB RESET
- // .. .. .. START: USB0 RESET
- // .. .. .. .. START: DIR MODE BANK 0
- // .. .. .. .. DIRECTION_0 = 0x80
- // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U
- // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U),
- // .. .. .. .. FINISH: DIR MODE BANK 0
- // .. .. .. .. START: DIR MODE BANK 1
- // .. .. .. .. FINISH: DIR MODE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. MASK_0_LSW = 0xff7f
- // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
- // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U
- // .. .. .. .. DATA_0_LSW = 0x80
- // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
- // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. START: OUTPUT ENABLE BANK 0
- // .. .. .. .. OP_ENABLE_0 = 0x80
- // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U
- // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U),
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
- // .. .. .. .. START: OUTPUT ENABLE BANK 1
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. MASK_0_LSW = 0xff7f
- // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
- // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U
- // .. .. .. .. DATA_0_LSW = 0x0
- // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
- // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U),
- // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. START: ADD 1 MS DELAY
- // .. .. .. ..
- EMIT_MASKDELAY(0XF8F00200, 1),
- // .. .. .. .. FINISH: ADD 1 MS DELAY
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. MASK_0_LSW = 0xff7f
- // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
- // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U
- // .. .. .. .. DATA_0_LSW = 0x80
- // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
- // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: USB0 RESET
- // .. .. .. START: USB1 RESET
- // .. .. .. .. START: DIR MODE BANK 0
- // .. .. .. .. FINISH: DIR MODE BANK 0
- // .. .. .. .. START: DIR MODE BANK 1
- // .. .. .. .. FINISH: DIR MODE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. START: OUTPUT ENABLE BANK 0
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
- // .. .. .. .. START: OUTPUT ENABLE BANK 1
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. START: ADD 1 MS DELAY
- // .. .. .. ..
- EMIT_MASKDELAY(0XF8F00200, 1),
- // .. .. .. .. FINISH: ADD 1 MS DELAY
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: USB1 RESET
- // .. .. FINISH: USB RESET
- // .. .. START: ENET RESET
- // .. .. .. START: ENET0 RESET
- // .. .. .. .. START: DIR MODE BANK 0
- // .. .. .. .. FINISH: DIR MODE BANK 0
- // .. .. .. .. START: DIR MODE BANK 1
- // .. .. .. .. DIRECTION_1 = 0x8000
- // .. .. .. .. ==> 0XE000A244[21:0] = 0x00008000U
- // .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00008000U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x00008000U),
- // .. .. .. .. FINISH: DIR MODE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. MASK_1_LSW = 0x7fff
- // .. .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU
- // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0x7FFF0000U
- // .. .. .. .. DATA_1_LSW = 0x8000
- // .. .. .. .. ==> 0XE000A008[15:0] = 0x00008000U
- // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00008000U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF8000U),
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. START: OUTPUT ENABLE BANK 0
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
- // .. .. .. .. START: OUTPUT ENABLE BANK 1
- // .. .. .. .. OP_ENABLE_1 = 0x8000
- // .. .. .. .. ==> 0XE000A248[21:0] = 0x00008000U
- // .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00008000U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x00008000U),
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. MASK_1_LSW = 0x7fff
- // .. .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU
- // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0x7FFF0000U
- // .. .. .. .. DATA_1_LSW = 0x0
- // .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U
- // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF0000U),
- // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. START: ADD 1 MS DELAY
- // .. .. .. ..
- EMIT_MASKDELAY(0XF8F00200, 1),
- // .. .. .. .. FINISH: ADD 1 MS DELAY
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. MASK_1_LSW = 0x7fff
- // .. .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU
- // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0x7FFF0000U
- // .. .. .. .. DATA_1_LSW = 0x8000
- // .. .. .. .. ==> 0XE000A008[15:0] = 0x00008000U
- // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00008000U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF8000U),
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: ENET0 RESET
- // .. .. .. START: ENET1 RESET
- // .. .. .. .. START: DIR MODE BANK 0
- // .. .. .. .. FINISH: DIR MODE BANK 0
- // .. .. .. .. START: DIR MODE BANK 1
- // .. .. .. .. FINISH: DIR MODE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. START: OUTPUT ENABLE BANK 0
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
- // .. .. .. .. START: OUTPUT ENABLE BANK 1
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. START: ADD 1 MS DELAY
- // .. .. .. ..
- EMIT_MASKDELAY(0XF8F00200, 1),
- // .. .. .. .. FINISH: ADD 1 MS DELAY
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: ENET1 RESET
- // .. .. FINISH: ENET RESET
- // .. .. START: I2C RESET
- // .. .. .. START: I2C0 RESET
- // .. .. .. .. START: DIR MODE GPIO BANK0
- // .. .. .. .. FINISH: DIR MODE GPIO BANK0
- // .. .. .. .. START: DIR MODE GPIO BANK1
- // .. .. .. .. DIRECTION_1 = 0x4000
- // .. .. .. .. ==> 0XE000A244[21:0] = 0x00004000U
- // .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x00004000U),
- // .. .. .. .. FINISH: DIR MODE GPIO BANK1
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. MASK_1_LSW = 0xbfff
- // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
- // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U
- // .. .. .. .. DATA_1_LSW = 0x4000
- // .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U
- // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U),
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. START: OUTPUT ENABLE
- // .. .. .. .. FINISH: OUTPUT ENABLE
- // .. .. .. .. START: OUTPUT ENABLE
- // .. .. .. .. OP_ENABLE_1 = 0x4000
- // .. .. .. .. ==> 0XE000A248[21:0] = 0x00004000U
- // .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x00004000U),
- // .. .. .. .. FINISH: OUTPUT ENABLE
- // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. MASK_1_LSW = 0xbfff
- // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
- // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U
- // .. .. .. .. DATA_1_LSW = 0x0
- // .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U
- // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF0000U),
- // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. START: ADD 1 MS DELAY
- // .. .. .. ..
- EMIT_MASKDELAY(0XF8F00200, 1),
- // .. .. .. .. FINISH: ADD 1 MS DELAY
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. MASK_1_LSW = 0xbfff
- // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
- // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U
- // .. .. .. .. DATA_1_LSW = 0x4000
- // .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U
- // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U),
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: I2C0 RESET
- // .. .. .. START: I2C1 RESET
- // .. .. .. .. START: DIR MODE GPIO BANK0
- // .. .. .. .. FINISH: DIR MODE GPIO BANK0
- // .. .. .. .. START: DIR MODE GPIO BANK1
- // .. .. .. .. FINISH: DIR MODE GPIO BANK1
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. START: OUTPUT ENABLE
- // .. .. .. .. FINISH: OUTPUT ENABLE
- // .. .. .. .. START: OUTPUT ENABLE
- // .. .. .. .. FINISH: OUTPUT ENABLE
- // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. START: ADD 1 MS DELAY
- // .. .. .. ..
- EMIT_MASKDELAY(0XF8F00200, 1),
- // .. .. .. .. FINISH: ADD 1 MS DELAY
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: I2C1 RESET
- // .. .. FINISH: I2C RESET
- // .. .. START: NOR CHIP SELECT
- // .. .. .. START: DIR MODE BANK 0
- // .. .. .. FINISH: DIR MODE BANK 0
- // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. START: OUTPUT ENABLE BANK 0
- // .. .. .. FINISH: OUTPUT ENABLE BANK 0
- // .. .. FINISH: NOR CHIP SELECT
- // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_post_config_3_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: ENABLING LEVEL SHIFTER
- // .. USER_LVL_INP_EN_0 = 1
- // .. ==> 0XF8000900[3:3] = 0x00000001U
- // .. ==> MASK : 0x00000008U VAL : 0x00000008U
- // .. USER_LVL_OUT_EN_0 = 1
- // .. ==> 0XF8000900[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. USER_LVL_INP_EN_1 = 1
- // .. ==> 0XF8000900[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. USER_LVL_OUT_EN_1 = 1
- // .. ==> 0XF8000900[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // ..
- EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
- // .. FINISH: ENABLING LEVEL SHIFTER
- // .. START: FPGA RESETS TO 0
- // .. reserved_3 = 0
- // .. ==> 0XF8000240[31:25] = 0x00000000U
- // .. ==> MASK : 0xFE000000U VAL : 0x00000000U
- // .. reserved_FPGA_ACP_RST = 0
- // .. ==> 0XF8000240[24:24] = 0x00000000U
- // .. ==> MASK : 0x01000000U VAL : 0x00000000U
- // .. reserved_FPGA_AXDS3_RST = 0
- // .. ==> 0XF8000240[23:23] = 0x00000000U
- // .. ==> MASK : 0x00800000U VAL : 0x00000000U
- // .. reserved_FPGA_AXDS2_RST = 0
- // .. ==> 0XF8000240[22:22] = 0x00000000U
- // .. ==> MASK : 0x00400000U VAL : 0x00000000U
- // .. reserved_FPGA_AXDS1_RST = 0
- // .. ==> 0XF8000240[21:21] = 0x00000000U
- // .. ==> MASK : 0x00200000U VAL : 0x00000000U
- // .. reserved_FPGA_AXDS0_RST = 0
- // .. ==> 0XF8000240[20:20] = 0x00000000U
- // .. ==> MASK : 0x00100000U VAL : 0x00000000U
- // .. reserved_2 = 0
- // .. ==> 0XF8000240[19:18] = 0x00000000U
- // .. ==> MASK : 0x000C0000U VAL : 0x00000000U
- // .. reserved_FSSW1_FPGA_RST = 0
- // .. ==> 0XF8000240[17:17] = 0x00000000U
- // .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. reserved_FSSW0_FPGA_RST = 0
- // .. ==> 0XF8000240[16:16] = 0x00000000U
- // .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. reserved_1 = 0
- // .. ==> 0XF8000240[15:14] = 0x00000000U
- // .. ==> MASK : 0x0000C000U VAL : 0x00000000U
- // .. reserved_FPGA_FMSW1_RST = 0
- // .. ==> 0XF8000240[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // .. reserved_FPGA_FMSW0_RST = 0
- // .. ==> 0XF8000240[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. reserved_FPGA_DMA3_RST = 0
- // .. ==> 0XF8000240[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. reserved_FPGA_DMA2_RST = 0
- // .. ==> 0XF8000240[10:10] = 0x00000000U
- // .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. reserved_FPGA_DMA1_RST = 0
- // .. ==> 0XF8000240[9:9] = 0x00000000U
- // .. ==> MASK : 0x00000200U VAL : 0x00000000U
- // .. reserved_FPGA_DMA0_RST = 0
- // .. ==> 0XF8000240[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. reserved = 0
- // .. ==> 0XF8000240[7:4] = 0x00000000U
- // .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. FPGA3_OUT_RST = 0
- // .. ==> 0XF8000240[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. FPGA2_OUT_RST = 0
- // .. ==> 0XF8000240[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. FPGA1_OUT_RST = 0
- // .. ==> 0XF8000240[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. FPGA0_OUT_RST = 0
- // .. ==> 0XF8000240[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
- // .. FINISH: FPGA RESETS TO 0
- // .. START: AFI REGISTERS
- // .. .. START: AFI0 REGISTERS
- // .. .. FINISH: AFI0 REGISTERS
- // .. .. START: AFI1 REGISTERS
- // .. .. FINISH: AFI1 REGISTERS
- // .. .. START: AFI2 REGISTERS
- // .. .. FINISH: AFI2 REGISTERS
- // .. .. START: AFI3 REGISTERS
- // .. .. FINISH: AFI3 REGISTERS
- // .. FINISH: AFI REGISTERS
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_debug_3_0[] = {
- // START: top
- // .. START: CROSS TRIGGER CONFIGURATIONS
- // .. .. START: UNLOCKING CTI REGISTERS
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. FINISH: UNLOCKING CTI REGISTERS
- // .. .. START: ENABLING CTI MODULES AND CHANNELS
- // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
- // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. FINISH: CROSS TRIGGER CONFIGURATIONS
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_pll_init_data_2_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: PLL SLCR REGISTERS
- // .. .. START: ARM PLL INIT
- // .. .. PLL_RES = 0x2
- // .. .. ==> 0XF8000110[7:4] = 0x00000002U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
- // .. .. PLL_CP = 0x2
- // .. .. ==> 0XF8000110[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. LOCK_CNT = 0xfa
- // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
- // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U
- // .. ..
- EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
- // .. .. .. START: UPDATE FB_DIV
- // .. .. .. PLL_FDIV = 0x28
- // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
- // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
- // .. .. .. FINISH: UPDATE FB_DIV
- // .. .. .. START: BY PASS PLL
- // .. .. .. PLL_BYPASS_FORCE = 1
- // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
- // .. .. .. FINISH: BY PASS PLL
- // .. .. .. START: ASSERT RESET
- // .. .. .. PLL_RESET = 1
- // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
- // .. .. .. FINISH: ASSERT RESET
- // .. .. .. START: DEASSERT RESET
- // .. .. .. PLL_RESET = 0
- // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
- // .. .. .. FINISH: DEASSERT RESET
- // .. .. .. START: CHECK PLL STATUS
- // .. .. .. ARM_PLL_LOCK = 1
- // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ..
- EMIT_MASKPOLL(0XF800010C, 0x00000001U),
- // .. .. .. FINISH: CHECK PLL STATUS
- // .. .. .. START: REMOVE PLL BY PASS
- // .. .. .. PLL_BYPASS_FORCE = 0
- // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
- // .. .. .. FINISH: REMOVE PLL BY PASS
- // .. .. .. SRCSEL = 0x0
- // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. .. .. DIVISOR = 0x2
- // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
- // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U
- // .. .. .. CPU_6OR4XCLKACT = 0x1
- // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
- // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U
- // .. .. .. CPU_3OR2XCLKACT = 0x1
- // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
- // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U
- // .. .. .. CPU_2XCLKACT = 0x1
- // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
- // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U
- // .. .. .. CPU_1XCLKACT = 0x1
- // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
- // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U
- // .. .. .. CPU_PERI_CLKACT = 0x1
- // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
- // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
- // .. .. FINISH: ARM PLL INIT
- // .. .. START: DDR PLL INIT
- // .. .. PLL_RES = 0x2
- // .. .. ==> 0XF8000114[7:4] = 0x00000002U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
- // .. .. PLL_CP = 0x2
- // .. .. ==> 0XF8000114[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. LOCK_CNT = 0x12c
- // .. .. ==> 0XF8000114[21:12] = 0x0000012CU
- // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U
- // .. ..
- EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
- // .. .. .. START: UPDATE FB_DIV
- // .. .. .. PLL_FDIV = 0x20
- // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
- // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
- // .. .. .. FINISH: UPDATE FB_DIV
- // .. .. .. START: BY PASS PLL
- // .. .. .. PLL_BYPASS_FORCE = 1
- // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
- // .. .. .. FINISH: BY PASS PLL
- // .. .. .. START: ASSERT RESET
- // .. .. .. PLL_RESET = 1
- // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
- // .. .. .. FINISH: ASSERT RESET
- // .. .. .. START: DEASSERT RESET
- // .. .. .. PLL_RESET = 0
- // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
- // .. .. .. FINISH: DEASSERT RESET
- // .. .. .. START: CHECK PLL STATUS
- // .. .. .. DDR_PLL_LOCK = 1
- // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. .. ..
- EMIT_MASKPOLL(0XF800010C, 0x00000002U),
- // .. .. .. FINISH: CHECK PLL STATUS
- // .. .. .. START: REMOVE PLL BY PASS
- // .. .. .. PLL_BYPASS_FORCE = 0
- // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
- // .. .. .. FINISH: REMOVE PLL BY PASS
- // .. .. .. DDR_3XCLKACT = 0x1
- // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. .. DDR_2XCLKACT = 0x1
- // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. .. .. DDR_3XCLK_DIVISOR = 0x2
- // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
- // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U
- // .. .. .. DDR_2XCLK_DIVISOR = 0x3
- // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
- // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
- // .. .. FINISH: DDR PLL INIT
- // .. .. START: IO PLL INIT
- // .. .. PLL_RES = 0xc
- // .. .. ==> 0XF8000118[7:4] = 0x0000000CU
- // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U
- // .. .. PLL_CP = 0x2
- // .. .. ==> 0XF8000118[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. LOCK_CNT = 0x145
- // .. .. ==> 0XF8000118[21:12] = 0x00000145U
- // .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U
- // .. ..
- EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U),
- // .. .. .. START: UPDATE FB_DIV
- // .. .. .. PLL_FDIV = 0x1e
- // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU
- // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U),
- // .. .. .. FINISH: UPDATE FB_DIV
- // .. .. .. START: BY PASS PLL
- // .. .. .. PLL_BYPASS_FORCE = 1
- // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
- // .. .. .. FINISH: BY PASS PLL
- // .. .. .. START: ASSERT RESET
- // .. .. .. PLL_RESET = 1
- // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
- // .. .. .. FINISH: ASSERT RESET
- // .. .. .. START: DEASSERT RESET
- // .. .. .. PLL_RESET = 0
- // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
- // .. .. .. FINISH: DEASSERT RESET
- // .. .. .. START: CHECK PLL STATUS
- // .. .. .. IO_PLL_LOCK = 1
- // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. .. ..
- EMIT_MASKPOLL(0XF800010C, 0x00000004U),
- // .. .. .. FINISH: CHECK PLL STATUS
- // .. .. .. START: REMOVE PLL BY PASS
- // .. .. .. PLL_BYPASS_FORCE = 0
- // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
- // .. .. .. FINISH: REMOVE PLL BY PASS
- // .. .. FINISH: IO PLL INIT
- // .. FINISH: PLL SLCR REGISTERS
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_clock_init_data_2_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: CLOCK CONTROL SLCR REGISTERS
- // .. CLKACT = 0x1
- // .. ==> 0XF8000128[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. DIVISOR0 = 0x23
- // .. ==> 0XF8000128[13:8] = 0x00000023U
- // .. ==> MASK : 0x00003F00U VAL : 0x00002300U
- // .. DIVISOR1 = 0x3
- // .. ==> 0XF8000128[25:20] = 0x00000003U
- // .. ==> MASK : 0x03F00000U VAL : 0x00300000U
- // ..
- EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U),
- // .. CLKACT = 0x1
- // .. ==> 0XF8000138[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000138[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
- // .. CLKACT = 0x1
- // .. ==> 0XF8000140[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000140[6:4] = 0x00000000U
- // .. ==> MASK : 0x00000070U VAL : 0x00000000U
- // .. DIVISOR = 0x8
- // .. ==> 0XF8000140[13:8] = 0x00000008U
- // .. ==> MASK : 0x00003F00U VAL : 0x00000800U
- // .. DIVISOR1 = 0x5
- // .. ==> 0XF8000140[25:20] = 0x00000005U
- // .. ==> MASK : 0x03F00000U VAL : 0x00500000U
- // ..
- EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00500801U),
- // .. CLKACT = 0x1
- // .. ==> 0XF800014C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. SRCSEL = 0x0
- // .. ==> 0XF800014C[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR = 0x5
- // .. ==> 0XF800014C[13:8] = 0x00000005U
- // .. ==> MASK : 0x00003F00U VAL : 0x00000500U
- // ..
- EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
- // .. CLKACT0 = 0x1
- // .. ==> 0XF8000150[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. CLKACT1 = 0x0
- // .. ==> 0XF8000150[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000150[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR = 0x14
- // .. ==> 0XF8000150[13:8] = 0x00000014U
- // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
- // ..
- EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U),
- // .. CLKACT0 = 0x0
- // .. ==> 0XF8000154[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. CLKACT1 = 0x1
- // .. ==> 0XF8000154[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000154[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR = 0x14
- // .. ==> 0XF8000154[13:8] = 0x00000014U
- // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
- // ..
- EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U),
- // .. CLKACT = 0x1
- // .. ==> 0XF8000168[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000168[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR = 0x5
- // .. ==> 0XF8000168[13:8] = 0x00000005U
- // .. ==> MASK : 0x00003F00U VAL : 0x00000500U
- // ..
- EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000170[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR0 = 0x14
- // .. ==> 0XF8000170[13:8] = 0x00000014U
- // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
- // .. DIVISOR1 = 0x1
- // .. ==> 0XF8000170[25:20] = 0x00000001U
- // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
- // ..
- EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00101400U),
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000180[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR0 = 0x14
- // .. ==> 0XF8000180[13:8] = 0x00000014U
- // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
- // .. DIVISOR1 = 0x1
- // .. ==> 0XF8000180[25:20] = 0x00000001U
- // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
- // ..
- EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00101400U),
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000190[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR0 = 0x14
- // .. ==> 0XF8000190[13:8] = 0x00000014U
- // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
- // .. DIVISOR1 = 0x1
- // .. ==> 0XF8000190[25:20] = 0x00000001U
- // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
- // ..
- EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101400U),
- // .. SRCSEL = 0x0
- // .. ==> 0XF80001A0[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR0 = 0x14
- // .. ==> 0XF80001A0[13:8] = 0x00000014U
- // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
- // .. DIVISOR1 = 0x1
- // .. ==> 0XF80001A0[25:20] = 0x00000001U
- // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
- // ..
- EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U),
- // .. CLK_621_TRUE = 0x1
- // .. ==> 0XF80001C4[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // ..
- EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
- // .. DMA_CPU_2XCLKACT = 0x1
- // .. ==> 0XF800012C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. USB0_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. USB1_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[3:3] = 0x00000001U
- // .. ==> MASK : 0x00000008U VAL : 0x00000008U
- // .. GEM0_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[6:6] = 0x00000001U
- // .. ==> MASK : 0x00000040U VAL : 0x00000040U
- // .. GEM1_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. SDI0_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[10:10] = 0x00000001U
- // .. ==> MASK : 0x00000400U VAL : 0x00000400U
- // .. SDI1_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. SPI0_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[14:14] = 0x00000000U
- // .. ==> MASK : 0x00004000U VAL : 0x00000000U
- // .. SPI1_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[15:15] = 0x00000000U
- // .. ==> MASK : 0x00008000U VAL : 0x00000000U
- // .. CAN0_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[16:16] = 0x00000000U
- // .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. CAN1_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[17:17] = 0x00000000U
- // .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. I2C0_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[18:18] = 0x00000001U
- // .. ==> MASK : 0x00040000U VAL : 0x00040000U
- // .. I2C1_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[19:19] = 0x00000001U
- // .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // .. UART0_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[20:20] = 0x00000000U
- // .. ==> MASK : 0x00100000U VAL : 0x00000000U
- // .. UART1_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[21:21] = 0x00000001U
- // .. ==> MASK : 0x00200000U VAL : 0x00200000U
- // .. GPIO_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[22:22] = 0x00000001U
- // .. ==> MASK : 0x00400000U VAL : 0x00400000U
- // .. LQSPI_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[23:23] = 0x00000001U
- // .. ==> MASK : 0x00800000U VAL : 0x00800000U
- // .. SMC_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[24:24] = 0x00000001U
- // .. ==> MASK : 0x01000000U VAL : 0x01000000U
- // ..
- EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC044DU),
- // .. FINISH: CLOCK CONTROL SLCR REGISTERS
- // .. START: THIS SHOULD BE BLANK
- // .. FINISH: THIS SHOULD BE BLANK
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_ddr_init_data_2_0[] = {
- // START: top
- // .. START: DDR INITIALIZATION
- // .. .. START: LOCK DDR
- // .. .. reg_ddrc_soft_rstb = 0
- // .. .. ==> 0XF8006000[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_powerdown_en = 0x0
- // .. .. ==> 0XF8006000[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_ddrc_data_bus_width = 0x0
- // .. .. ==> 0XF8006000[3:2] = 0x00000000U
- // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U
- // .. .. reg_ddrc_burst8_refresh = 0x0
- // .. .. ==> 0XF8006000[6:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U
- // .. .. reg_ddrc_rdwr_idle_gap = 0x1
- // .. .. ==> 0XF8006000[13:7] = 0x00000001U
- // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U
- // .. .. reg_ddrc_dis_rd_bypass = 0x0
- // .. .. ==> 0XF8006000[14:14] = 0x00000000U
- // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_act_bypass = 0x0
- // .. .. ==> 0XF8006000[15:15] = 0x00000000U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_auto_refresh = 0x0
- // .. .. ==> 0XF8006000[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
- // .. .. FINISH: LOCK DDR
- // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81
- // .. .. ==> 0XF8006004[11:0] = 0x00000081U
- // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U
- // .. .. reg_ddrc_active_ranks = 0x1
- // .. .. ==> 0XF8006004[13:12] = 0x00000001U
- // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U
- // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
- // .. .. ==> 0XF8006004[18:14] = 0x00000000U
- // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U
- // .. .. reg_ddrc_wr_odt_block = 0x1
- // .. .. ==> 0XF8006004[20:19] = 0x00000001U
- // .. .. ==> MASK : 0x00180000U VAL : 0x00080000U
- // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0
- // .. .. ==> 0XF8006004[21:21] = 0x00000000U
- // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0
- // .. .. ==> 0XF8006004[26:22] = 0x00000000U
- // .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_open_bank = 0x0
- // .. .. ==> 0XF8006004[27:27] = 0x00000000U
- // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_4bank_ram = 0x0
- // .. .. ==> 0XF8006004[28:28] = 0x00000000U
- // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U),
- // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
- // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
- // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU
- // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
- // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
- // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U
- // .. .. reg_ddrc_hpr_xact_run_length = 0xf
- // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
- // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U
- // .. ..
- EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
- // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
- // .. .. ==> 0XF800600C[10:0] = 0x00000001U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U
- // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
- // .. .. ==> 0XF800600C[21:11] = 0x00000002U
- // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U
- // .. .. reg_ddrc_lpr_xact_run_length = 0x8
- // .. .. ==> 0XF800600C[25:22] = 0x00000008U
- // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U
- // .. ..
- EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
- // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
- // .. .. ==> 0XF8006010[10:0] = 0x00000001U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U
- // .. .. reg_ddrc_w_xact_run_length = 0x8
- // .. .. ==> 0XF8006010[14:11] = 0x00000008U
- // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U
- // .. .. reg_ddrc_w_max_starve_x32 = 0x2
- // .. .. ==> 0XF8006010[25:15] = 0x00000002U
- // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U
- // .. ..
- EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
- // .. .. reg_ddrc_t_rc = 0x1b
- // .. .. ==> 0XF8006014[5:0] = 0x0000001BU
- // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001BU
- // .. .. reg_ddrc_t_rfc_min = 0x56
- // .. .. ==> 0XF8006014[13:6] = 0x00000056U
- // .. .. ==> MASK : 0x00003FC0U VAL : 0x00001580U
- // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
- // .. .. ==> 0XF8006014[20:14] = 0x00000010U
- // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U
- // .. ..
- EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004159BU),
- // .. .. reg_ddrc_wr2pre = 0x12
- // .. .. ==> 0XF8006018[4:0] = 0x00000012U
- // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U
- // .. .. reg_ddrc_powerdown_to_x32 = 0x6
- // .. .. ==> 0XF8006018[9:5] = 0x00000006U
- // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U
- // .. .. reg_ddrc_t_faw = 0x10
- // .. .. ==> 0XF8006018[15:10] = 0x00000010U
- // .. .. ==> MASK : 0x0000FC00U VAL : 0x00004000U
- // .. .. reg_ddrc_t_ras_max = 0x24
- // .. .. ==> 0XF8006018[21:16] = 0x00000024U
- // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U
- // .. .. reg_ddrc_t_ras_min = 0x14
- // .. .. ==> 0XF8006018[26:22] = 0x00000014U
- // .. .. ==> MASK : 0x07C00000U VAL : 0x05000000U
- // .. .. reg_ddrc_t_cke = 0x4
- // .. .. ==> 0XF8006018[31:28] = 0x00000004U
- // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x452440D2U),
- // .. .. reg_ddrc_write_latency = 0x5
- // .. .. ==> 0XF800601C[4:0] = 0x00000005U
- // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U
- // .. .. reg_ddrc_rd2wr = 0x7
- // .. .. ==> 0XF800601C[9:5] = 0x00000007U
- // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U
- // .. .. reg_ddrc_wr2rd = 0xe
- // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
- // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U
- // .. .. reg_ddrc_t_xp = 0x4
- // .. .. ==> 0XF800601C[19:15] = 0x00000004U
- // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U
- // .. .. reg_ddrc_pad_pd = 0x0
- // .. .. ==> 0XF800601C[22:20] = 0x00000000U
- // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U
- // .. .. reg_ddrc_rd2pre = 0x4
- // .. .. ==> 0XF800601C[27:23] = 0x00000004U
- // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U
- // .. .. reg_ddrc_t_rcd = 0x7
- // .. .. ==> 0XF800601C[31:28] = 0x00000007U
- // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U
- // .. ..
- EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
- // .. .. reg_ddrc_t_ccd = 0x4
- // .. .. ==> 0XF8006020[4:2] = 0x00000004U
- // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U
- // .. .. reg_ddrc_t_rrd = 0x4
- // .. .. ==> 0XF8006020[7:5] = 0x00000004U
- // .. .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. .. reg_ddrc_refresh_margin = 0x2
- // .. .. ==> 0XF8006020[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. reg_ddrc_t_rp = 0x7
- // .. .. ==> 0XF8006020[15:12] = 0x00000007U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U
- // .. .. reg_ddrc_refresh_to_x32 = 0x8
- // .. .. ==> 0XF8006020[20:16] = 0x00000008U
- // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U
- // .. .. reg_ddrc_sdram = 0x1
- // .. .. ==> 0XF8006020[21:21] = 0x00000001U
- // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U
- // .. .. reg_ddrc_mobile = 0x0
- // .. .. ==> 0XF8006020[22:22] = 0x00000000U
- // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U
- // .. .. reg_ddrc_clock_stop_en = 0x0
- // .. .. ==> 0XF8006020[23:23] = 0x00000000U
- // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U
- // .. .. reg_ddrc_read_latency = 0x7
- // .. .. ==> 0XF8006020[28:24] = 0x00000007U
- // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U
- // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
- // .. .. ==> 0XF8006020[29:29] = 0x00000001U
- // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U
- // .. .. reg_ddrc_dis_pad_pd = 0x0
- // .. .. ==> 0XF8006020[30:30] = 0x00000000U
- // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U
- // .. .. reg_ddrc_loopback = 0x0
- // .. .. ==> 0XF8006020[31:31] = 0x00000000U
- // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x27287290U),
- // .. .. reg_ddrc_en_2t_timing_mode = 0x0
- // .. .. ==> 0XF8006024[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_prefer_write = 0x0
- // .. .. ==> 0XF8006024[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_ddrc_max_rank_rd = 0xf
- // .. .. ==> 0XF8006024[5:2] = 0x0000000FU
- // .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU
- // .. .. reg_ddrc_mr_wr = 0x0
- // .. .. ==> 0XF8006024[6:6] = 0x00000000U
- // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_addr = 0x0
- // .. .. ==> 0XF8006024[8:7] = 0x00000000U
- // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_data = 0x0
- // .. .. ==> 0XF8006024[24:9] = 0x00000000U
- // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U
- // .. .. ddrc_reg_mr_wr_busy = 0x0
- // .. .. ==> 0XF8006024[25:25] = 0x00000000U
- // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_type = 0x0
- // .. .. ==> 0XF8006024[26:26] = 0x00000000U
- // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_rdata_valid = 0x0
- // .. .. ==> 0XF8006024[27:27] = 0x00000000U
- // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU),
- // .. .. reg_ddrc_final_wait_x32 = 0x7
- // .. .. ==> 0XF8006028[6:0] = 0x00000007U
- // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U
- // .. .. reg_ddrc_pre_ocd_x32 = 0x0
- // .. .. ==> 0XF8006028[10:7] = 0x00000000U
- // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U
- // .. .. reg_ddrc_t_mrd = 0x4
- // .. .. ==> 0XF8006028[13:11] = 0x00000004U
- // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U
- // .. ..
- EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
- // .. .. reg_ddrc_emr2 = 0x8
- // .. .. ==> 0XF800602C[15:0] = 0x00000008U
- // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U
- // .. .. reg_ddrc_emr3 = 0x0
- // .. .. ==> 0XF800602C[31:16] = 0x00000000U
- // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
- // .. .. reg_ddrc_mr = 0x930
- // .. .. ==> 0XF8006030[15:0] = 0x00000930U
- // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U
- // .. .. reg_ddrc_emr = 0x4
- // .. .. ==> 0XF8006030[31:16] = 0x00000004U
- // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U
- // .. ..
- EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
- // .. .. reg_ddrc_burst_rdwr = 0x4
- // .. .. ==> 0XF8006034[3:0] = 0x00000004U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U
- // .. .. reg_ddrc_pre_cke_x1024 = 0x105
- // .. .. ==> 0XF8006034[13:4] = 0x00000105U
- // .. .. ==> MASK : 0x00003FF0U VAL : 0x00001050U
- // .. .. reg_ddrc_post_cke_x1024 = 0x1
- // .. .. ==> 0XF8006034[25:16] = 0x00000001U
- // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U
- // .. .. reg_ddrc_burstchop = 0x0
- // .. .. ==> 0XF8006034[28:28] = 0x00000000U
- // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U),
- // .. .. reg_ddrc_force_low_pri_n = 0x0
- // .. .. ==> 0XF8006038[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_dq = 0x0
- // .. .. ==> 0XF8006038[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_debug_mode = 0x0
- // .. .. ==> 0XF8006038[6:6] = 0x00000000U
- // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U
- // .. .. reg_phy_wr_level_start = 0x0
- // .. .. ==> 0XF8006038[7:7] = 0x00000000U
- // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. .. reg_phy_rd_level_start = 0x0
- // .. .. ==> 0XF8006038[8:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. .. reg_phy_dq0_wait_t = 0x0
- // .. .. ==> 0XF8006038[12:9] = 0x00000000U
- // .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U),
- // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
- // .. .. ==> 0XF800603C[3:0] = 0x00000007U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U
- // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
- // .. .. ==> 0XF800603C[7:4] = 0x00000007U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U
- // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
- // .. .. ==> 0XF800603C[11:8] = 0x00000007U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U
- // .. .. reg_ddrc_addrmap_col_b5 = 0x0
- // .. .. ==> 0XF800603C[15:12] = 0x00000000U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b6 = 0x0
- // .. .. ==> 0XF800603C[19:16] = 0x00000000U
- // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
- // .. .. reg_ddrc_addrmap_col_b2 = 0x0
- // .. .. ==> 0XF8006040[3:0] = 0x00000000U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b3 = 0x0
- // .. .. ==> 0XF8006040[7:4] = 0x00000000U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b4 = 0x0
- // .. .. ==> 0XF8006040[11:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b7 = 0x0
- // .. .. ==> 0XF8006040[15:12] = 0x00000000U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b8 = 0x0
- // .. .. ==> 0XF8006040[19:16] = 0x00000000U
- // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b9 = 0xf
- // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
- // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U
- // .. .. reg_ddrc_addrmap_col_b10 = 0xf
- // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
- // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U
- // .. .. reg_ddrc_addrmap_col_b11 = 0xf
- // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
- // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
- // .. .. reg_ddrc_addrmap_row_b0 = 0x6
- // .. .. ==> 0XF8006044[3:0] = 0x00000006U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U
- // .. .. reg_ddrc_addrmap_row_b1 = 0x6
- // .. .. ==> 0XF8006044[7:4] = 0x00000006U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U
- // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
- // .. .. ==> 0XF8006044[11:8] = 0x00000006U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U
- // .. .. reg_ddrc_addrmap_row_b12 = 0x6
- // .. .. ==> 0XF8006044[15:12] = 0x00000006U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U
- // .. .. reg_ddrc_addrmap_row_b13 = 0x6
- // .. .. ==> 0XF8006044[19:16] = 0x00000006U
- // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U
- // .. .. reg_ddrc_addrmap_row_b14 = 0x6
- // .. .. ==> 0XF8006044[23:20] = 0x00000006U
- // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U
- // .. .. reg_ddrc_addrmap_row_b15 = 0xf
- // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
- // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U),
- // .. .. reg_ddrc_rank0_rd_odt = 0x0
- // .. .. ==> 0XF8006048[2:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U
- // .. .. reg_ddrc_rank0_wr_odt = 0x1
- // .. .. ==> 0XF8006048[5:3] = 0x00000001U
- // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U
- // .. .. reg_ddrc_rank1_rd_odt = 0x1
- // .. .. ==> 0XF8006048[8:6] = 0x00000001U
- // .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U
- // .. .. reg_ddrc_rank1_wr_odt = 0x1
- // .. .. ==> 0XF8006048[11:9] = 0x00000001U
- // .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. .. reg_phy_rd_local_odt = 0x0
- // .. .. ==> 0XF8006048[13:12] = 0x00000000U
- // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U
- // .. .. reg_phy_wr_local_odt = 0x3
- // .. .. ==> 0XF8006048[15:14] = 0x00000003U
- // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U
- // .. .. reg_phy_idle_local_odt = 0x3
- // .. .. ==> 0XF8006048[17:16] = 0x00000003U
- // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U
- // .. .. reg_ddrc_rank2_rd_odt = 0x0
- // .. .. ==> 0XF8006048[20:18] = 0x00000000U
- // .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U
- // .. .. reg_ddrc_rank2_wr_odt = 0x0
- // .. .. ==> 0XF8006048[23:21] = 0x00000000U
- // .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U
- // .. .. reg_ddrc_rank3_rd_odt = 0x0
- // .. .. ==> 0XF8006048[26:24] = 0x00000000U
- // .. .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. .. reg_ddrc_rank3_wr_odt = 0x0
- // .. .. ==> 0XF8006048[29:27] = 0x00000000U
- // .. .. ==> MASK : 0x38000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U),
- // .. .. reg_phy_rd_cmd_to_data = 0x0
- // .. .. ==> 0XF8006050[3:0] = 0x00000000U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
- // .. .. reg_phy_wr_cmd_to_data = 0x0
- // .. .. ==> 0XF8006050[7:4] = 0x00000000U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. .. reg_phy_rdc_we_to_re_delay = 0x8
- // .. .. ==> 0XF8006050[11:8] = 0x00000008U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U
- // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
- // .. .. ==> 0XF8006050[15:15] = 0x00000000U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
- // .. .. reg_phy_use_fixed_re = 0x1
- // .. .. ==> 0XF8006050[16:16] = 0x00000001U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U
- // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
- // .. .. ==> 0XF8006050[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
- // .. .. ==> 0XF8006050[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_phy_clk_stall_level = 0x0
- // .. .. ==> 0XF8006050[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
- // .. .. ==> 0XF8006050[27:24] = 0x00000007U
- // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U
- // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
- // .. .. ==> 0XF8006050[31:28] = 0x00000007U
- // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
- // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1
- // .. .. ==> 0XF8006058[7:0] = 0x00000001U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U
- // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1
- // .. .. ==> 0XF8006058[15:8] = 0x00000001U
- // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U
- // .. .. reg_ddrc_dis_dll_calib = 0x0
- // .. .. ==> 0XF8006058[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U),
- // .. .. reg_ddrc_rd_odt_delay = 0x3
- // .. .. ==> 0XF800605C[3:0] = 0x00000003U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U
- // .. .. reg_ddrc_wr_odt_delay = 0x0
- // .. .. ==> 0XF800605C[7:4] = 0x00000000U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. .. reg_ddrc_rd_odt_hold = 0x0
- // .. .. ==> 0XF800605C[11:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U
- // .. .. reg_ddrc_wr_odt_hold = 0x5
- // .. .. ==> 0XF800605C[15:12] = 0x00000005U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U
- // .. ..
- EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
- // .. .. reg_ddrc_pageclose = 0x0
- // .. .. ==> 0XF8006060[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_lpr_num_entries = 0x1f
- // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
- // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU
- // .. .. reg_ddrc_auto_pre_en = 0x0
- // .. .. ==> 0XF8006060[7:7] = 0x00000000U
- // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. .. reg_ddrc_refresh_update_level = 0x0
- // .. .. ==> 0XF8006060[8:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_wc = 0x0
- // .. .. ==> 0XF8006060[9:9] = 0x00000000U
- // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_collision_page_opt = 0x0
- // .. .. ==> 0XF8006060[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_ddrc_selfref_en = 0x0
- // .. .. ==> 0XF8006060[12:12] = 0x00000000U
- // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
- // .. .. reg_ddrc_go2critical_hysteresis = 0x0
- // .. .. ==> 0XF8006064[12:5] = 0x00000000U
- // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U
- // .. .. reg_arb_go2critical_en = 0x1
- // .. .. ==> 0XF8006064[17:17] = 0x00000001U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U
- // .. ..
- EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
- // .. .. reg_ddrc_wrlvl_ww = 0x41
- // .. .. ==> 0XF8006068[7:0] = 0x00000041U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U
- // .. .. reg_ddrc_rdlvl_rr = 0x41
- // .. .. ==> 0XF8006068[15:8] = 0x00000041U
- // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U
- // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
- // .. .. ==> 0XF8006068[25:16] = 0x00000028U
- // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U
- // .. ..
- EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
- // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
- // .. .. ==> 0XF800606C[7:0] = 0x00000010U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U
- // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
- // .. .. ==> 0XF800606C[15:8] = 0x00000016U
- // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U
- // .. ..
- EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
- // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1
- // .. .. ==> 0XF8006078[3:0] = 0x00000001U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U
- // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1
- // .. .. ==> 0XF8006078[7:4] = 0x00000001U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U
- // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1
- // .. .. ==> 0XF8006078[11:8] = 0x00000001U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U
- // .. .. reg_ddrc_t_cksre = 0x6
- // .. .. ==> 0XF8006078[15:12] = 0x00000006U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U
- // .. .. reg_ddrc_t_cksrx = 0x6
- // .. .. ==> 0XF8006078[19:16] = 0x00000006U
- // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U
- // .. .. reg_ddrc_t_ckesr = 0x4
- // .. .. ==> 0XF8006078[25:20] = 0x00000004U
- // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U
- // .. ..
- EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U),
- // .. .. reg_ddrc_t_ckpde = 0x2
- // .. .. ==> 0XF800607C[3:0] = 0x00000002U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U
- // .. .. reg_ddrc_t_ckpdx = 0x2
- // .. .. ==> 0XF800607C[7:4] = 0x00000002U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
- // .. .. reg_ddrc_t_ckdpde = 0x2
- // .. .. ==> 0XF800607C[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. reg_ddrc_t_ckdpdx = 0x2
- // .. .. ==> 0XF800607C[15:12] = 0x00000002U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U
- // .. .. reg_ddrc_t_ckcsx = 0x3
- // .. .. ==> 0XF800607C[19:16] = 0x00000003U
- // .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U
- // .. ..
- EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U),
- // .. .. refresh_timer0_start_value_x32 = 0x0
- // .. .. ==> 0XF80060A0[11:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U
- // .. .. refresh_timer1_start_value_x32 = 0x8
- // .. .. ==> 0XF80060A0[23:12] = 0x00000008U
- // .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U
- // .. ..
- EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U),
- // .. .. reg_ddrc_dis_auto_zq = 0x0
- // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_ddr3 = 0x1
- // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. .. reg_ddrc_t_mod = 0x200
- // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
- // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U
- // .. .. reg_ddrc_t_zq_long_nop = 0x200
- // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
- // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U
- // .. .. reg_ddrc_t_zq_short_nop = 0x40
- // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
- // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
- // .. .. t_zq_short_interval_x1024 = 0xcb73
- // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U
- // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U
- // .. .. dram_rstn_x1024 = 0x69
- // .. .. ==> 0XF80060A8[27:20] = 0x00000069U
- // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U
- // .. ..
- EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
- // .. .. deeppowerdown_en = 0x0
- // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. deeppowerdown_to_x1024 = 0xff
- // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
- // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU
- // .. ..
- EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
- // .. .. dfi_wrlvl_max_x1024 = 0xfff
- // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
- // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU
- // .. .. dfi_rdlvl_max_x1024 = 0xfff
- // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
- // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U
- // .. .. ddrc_reg_twrlvl_max_error = 0x0
- // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
- // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U
- // .. .. ddrc_reg_trdlvl_max_error = 0x0
- // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
- // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
- // .. .. reg_ddrc_dfi_wr_level_en = 0x1
- // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
- // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U
- // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
- // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
- // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U
- // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
- // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
- // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
- // .. .. reg_ddrc_2t_delay = 0x0
- // .. .. ==> 0XF80060B4[8:0] = 0x00000000U
- // .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U
- // .. .. reg_ddrc_skip_ocd = 0x1
- // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
- // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U
- // .. .. reg_ddrc_dis_pre_bypass = 0x0
- // .. .. ==> 0XF80060B4[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U),
- // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
- // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
- // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U
- // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
- // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
- // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U
- // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
- // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
- // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U
- // .. ..
- EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
- // .. .. START: RESET ECC ERROR
- // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1
- // .. .. ==> 0XF80060C4[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. Clear_Correctable_DRAM_ECC_error = 1
- // .. .. ==> 0XF80060C4[1:1] = 0x00000001U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. ..
- EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U),
- // .. .. FINISH: RESET ECC ERROR
- // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
- // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
- // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
- // .. .. CORR_ECC_LOG_VALID = 0x0
- // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. ECC_CORRECTED_BIT_NUM = 0x0
- // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
- // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
- // .. .. UNCORR_ECC_LOG_VALID = 0x0
- // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
- // .. .. STAT_NUM_CORR_ERR = 0x0
- // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
- // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U
- // .. .. STAT_NUM_UNCORR_ERR = 0x0
- // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
- // .. .. reg_ddrc_ecc_mode = 0x0
- // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_scrub = 0x1
- // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U
- // .. ..
- EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
- // .. .. reg_phy_dif_on = 0x0
- // .. .. ==> 0XF8006114[3:0] = 0x00000000U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
- // .. .. reg_phy_dif_off = 0x0
- // .. .. ==> 0XF8006114[7:4] = 0x00000000U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
- // .. .. reg_phy_data_slice_in_use = 0x1
- // .. .. ==> 0XF8006118[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_phy_rdlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006118[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_inc_mode = 0x0
- // .. .. ==> 0XF8006118[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_wrlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006118[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_tx = 0x0
- // .. .. ==> 0XF8006118[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_rx = 0x0
- // .. .. ==> 0XF8006118[5:5] = 0x00000000U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. .. reg_phy_bist_shift_dq = 0x0
- // .. .. ==> 0XF8006118[14:6] = 0x00000000U
- // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. .. reg_phy_bist_err_clr = 0x0
- // .. .. ==> 0XF8006118[23:15] = 0x00000000U
- // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. .. reg_phy_dq_offset = 0x40
- // .. .. ==> 0XF8006118[30:24] = 0x00000040U
- // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U),
- // .. .. reg_phy_data_slice_in_use = 0x1
- // .. .. ==> 0XF800611C[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_phy_rdlvl_inc_mode = 0x0
- // .. .. ==> 0XF800611C[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_inc_mode = 0x0
- // .. .. ==> 0XF800611C[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_wrlvl_inc_mode = 0x0
- // .. .. ==> 0XF800611C[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_tx = 0x0
- // .. .. ==> 0XF800611C[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_rx = 0x0
- // .. .. ==> 0XF800611C[5:5] = 0x00000000U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. .. reg_phy_bist_shift_dq = 0x0
- // .. .. ==> 0XF800611C[14:6] = 0x00000000U
- // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. .. reg_phy_bist_err_clr = 0x0
- // .. .. ==> 0XF800611C[23:15] = 0x00000000U
- // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. .. reg_phy_dq_offset = 0x40
- // .. .. ==> 0XF800611C[30:24] = 0x00000040U
- // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U),
- // .. .. reg_phy_data_slice_in_use = 0x1
- // .. .. ==> 0XF8006120[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_phy_rdlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006120[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_inc_mode = 0x0
- // .. .. ==> 0XF8006120[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_wrlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006120[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_tx = 0x0
- // .. .. ==> 0XF8006120[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_rx = 0x0
- // .. .. ==> 0XF8006120[5:5] = 0x00000000U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. .. reg_phy_bist_shift_dq = 0x0
- // .. .. ==> 0XF8006120[14:6] = 0x00000000U
- // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. .. reg_phy_bist_err_clr = 0x0
- // .. .. ==> 0XF8006120[23:15] = 0x00000000U
- // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. .. reg_phy_dq_offset = 0x40
- // .. .. ==> 0XF8006120[30:24] = 0x00000040U
- // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // .. .. reg_phy_data_slice_in_use = 0x1
- // .. .. ==> 0XF8006120[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_phy_rdlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006120[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_inc_mode = 0x0
- // .. .. ==> 0XF8006120[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_wrlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006120[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_tx = 0x0
- // .. .. ==> 0XF8006120[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_rx = 0x0
- // .. .. ==> 0XF8006120[5:5] = 0x00000000U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. .. reg_phy_bist_shift_dq = 0x0
- // .. .. ==> 0XF8006120[14:6] = 0x00000000U
- // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. .. reg_phy_bist_err_clr = 0x0
- // .. .. ==> 0XF8006120[23:15] = 0x00000000U
- // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. .. reg_phy_dq_offset = 0x40
- // .. .. ==> 0XF8006120[30:24] = 0x00000040U
- // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U),
- // .. .. reg_phy_data_slice_in_use = 0x1
- // .. .. ==> 0XF8006124[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_phy_rdlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006124[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_inc_mode = 0x0
- // .. .. ==> 0XF8006124[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_wrlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006124[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_tx = 0x0
- // .. .. ==> 0XF8006124[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_rx = 0x0
- // .. .. ==> 0XF8006124[5:5] = 0x00000000U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. .. reg_phy_bist_shift_dq = 0x0
- // .. .. ==> 0XF8006124[14:6] = 0x00000000U
- // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. .. reg_phy_bist_err_clr = 0x0
- // .. .. ==> 0XF8006124[23:15] = 0x00000000U
- // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. .. reg_phy_dq_offset = 0x40
- // .. .. ==> 0XF8006124[30:24] = 0x00000040U
- // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U),
- // .. .. reg_phy_wrlvl_init_ratio = 0x1e
- // .. .. ==> 0XF800612C[9:0] = 0x0000001EU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x0000001EU
- // .. .. reg_phy_gatelvl_init_ratio = 0xee
- // .. .. ==> 0XF800612C[19:10] = 0x000000EEU
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x0003B800U
- // .. ..
- EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0003B81EU),
- // .. .. reg_phy_wrlvl_init_ratio = 0x25
- // .. .. ==> 0XF8006130[9:0] = 0x00000025U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000025U
- // .. .. reg_phy_gatelvl_init_ratio = 0x10d
- // .. .. ==> 0XF8006130[19:10] = 0x0000010DU
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x00043400U
- // .. ..
- EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00043425U),
- // .. .. reg_phy_wrlvl_init_ratio = 0x19
- // .. .. ==> 0XF8006134[9:0] = 0x00000019U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000019U
- // .. .. reg_phy_gatelvl_init_ratio = 0xf3
- // .. .. ==> 0XF8006134[19:10] = 0x000000F3U
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x0003CC00U
- // .. ..
- EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0003CC19U),
- // .. .. reg_phy_wrlvl_init_ratio = 0x2a
- // .. .. ==> 0XF8006138[9:0] = 0x0000002AU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x0000002AU
- // .. .. reg_phy_gatelvl_init_ratio = 0x109
- // .. .. ==> 0XF8006138[19:10] = 0x00000109U
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x00042400U
- // .. ..
- EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0004242AU),
- // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. .. ==> 0XF8006140[9:0] = 0x00000035U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. .. reg_phy_rd_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006140[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006140[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
- // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. .. ==> 0XF8006144[9:0] = 0x00000035U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. .. reg_phy_rd_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006144[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006144[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
- // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. .. ==> 0XF8006148[9:0] = 0x00000035U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. .. reg_phy_rd_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006148[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006148[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
- // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. .. ==> 0XF800614C[9:0] = 0x00000035U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. .. reg_phy_rd_dqs_slave_force = 0x0
- // .. .. ==> 0XF800614C[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. .. ==> 0XF800614C[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
- // .. .. reg_phy_wr_dqs_slave_ratio = 0x9e
- // .. .. ==> 0XF8006154[9:0] = 0x0000009EU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x0000009EU
- // .. .. reg_phy_wr_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006154[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006154[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x0000009EU),
- // .. .. reg_phy_wr_dqs_slave_ratio = 0xa5
- // .. .. ==> 0XF8006158[9:0] = 0x000000A5U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000000A5U
- // .. .. reg_phy_wr_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006158[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006158[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x000000A5U),
- // .. .. reg_phy_wr_dqs_slave_ratio = 0x99
- // .. .. ==> 0XF800615C[9:0] = 0x00000099U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000099U
- // .. .. reg_phy_wr_dqs_slave_force = 0x0
- // .. .. ==> 0XF800615C[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. .. ==> 0XF800615C[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000099U),
- // .. .. reg_phy_wr_dqs_slave_ratio = 0xaa
- // .. .. ==> 0XF8006160[9:0] = 0x000000AAU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000000AAU
- // .. .. reg_phy_wr_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006160[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006160[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x000000AAU),
- // .. .. reg_phy_fifo_we_slave_ratio = 0x143
- // .. .. ==> 0XF8006168[10:0] = 0x00000143U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x00000143U
- // .. .. reg_phy_fifo_we_in_force = 0x0
- // .. .. ==> 0XF8006168[11:11] = 0x00000000U
- // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. .. reg_phy_fifo_we_in_delay = 0x0
- // .. .. ==> 0XF8006168[20:12] = 0x00000000U
- // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000143U),
- // .. .. reg_phy_fifo_we_slave_ratio = 0x162
- // .. .. ==> 0XF800616C[10:0] = 0x00000162U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x00000162U
- // .. .. reg_phy_fifo_we_in_force = 0x0
- // .. .. ==> 0XF800616C[11:11] = 0x00000000U
- // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. .. reg_phy_fifo_we_in_delay = 0x0
- // .. .. ==> 0XF800616C[20:12] = 0x00000000U
- // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x00000162U),
- // .. .. reg_phy_fifo_we_slave_ratio = 0x148
- // .. .. ==> 0XF8006170[10:0] = 0x00000148U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x00000148U
- // .. .. reg_phy_fifo_we_in_force = 0x0
- // .. .. ==> 0XF8006170[11:11] = 0x00000000U
- // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. .. reg_phy_fifo_we_in_delay = 0x0
- // .. .. ==> 0XF8006170[20:12] = 0x00000000U
- // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000148U),
- // .. .. reg_phy_fifo_we_slave_ratio = 0x15e
- // .. .. ==> 0XF8006174[10:0] = 0x0000015EU
- // .. .. ==> MASK : 0x000007FFU VAL : 0x0000015EU
- // .. .. reg_phy_fifo_we_in_force = 0x0
- // .. .. ==> 0XF8006174[11:11] = 0x00000000U
- // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. .. reg_phy_fifo_we_in_delay = 0x0
- // .. .. ==> 0XF8006174[20:12] = 0x00000000U
- // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x0000015EU),
- // .. .. reg_phy_wr_data_slave_ratio = 0xde
- // .. .. ==> 0XF800617C[9:0] = 0x000000DEU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000000DEU
- // .. .. reg_phy_wr_data_slave_force = 0x0
- // .. .. ==> 0XF800617C[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_data_slave_delay = 0x0
- // .. .. ==> 0XF800617C[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000DEU),
- // .. .. reg_phy_wr_data_slave_ratio = 0xe5
- // .. .. ==> 0XF8006180[9:0] = 0x000000E5U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000000E5U
- // .. .. reg_phy_wr_data_slave_force = 0x0
- // .. .. ==> 0XF8006180[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_data_slave_delay = 0x0
- // .. .. ==> 0XF8006180[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000E5U),
- // .. .. reg_phy_wr_data_slave_ratio = 0xd9
- // .. .. ==> 0XF8006184[9:0] = 0x000000D9U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000000D9U
- // .. .. reg_phy_wr_data_slave_force = 0x0
- // .. .. ==> 0XF8006184[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_data_slave_delay = 0x0
- // .. .. ==> 0XF8006184[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000D9U),
- // .. .. reg_phy_wr_data_slave_ratio = 0xea
- // .. .. ==> 0XF8006188[9:0] = 0x000000EAU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000000EAU
- // .. .. reg_phy_wr_data_slave_force = 0x0
- // .. .. ==> 0XF8006188[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_data_slave_delay = 0x0
- // .. .. ==> 0XF8006188[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000EAU),
- // .. .. reg_phy_loopback = 0x0
- // .. .. ==> 0XF8006190[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_phy_bl2 = 0x0
- // .. .. ==> 0XF8006190[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_at_spd_atpg = 0x0
- // .. .. ==> 0XF8006190[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_bist_enable = 0x0
- // .. .. ==> 0XF8006190[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_bist_force_err = 0x0
- // .. .. ==> 0XF8006190[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. reg_phy_bist_mode = 0x0
- // .. .. ==> 0XF8006190[6:5] = 0x00000000U
- // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. .. reg_phy_invert_clkout = 0x1
- // .. .. ==> 0XF8006190[7:7] = 0x00000001U
- // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0
- // .. .. ==> 0XF8006190[8:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. .. reg_phy_sel_logic = 0x0
- // .. .. ==> 0XF8006190[9:9] = 0x00000000U
- // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U
- // .. .. reg_phy_ctrl_slave_ratio = 0x100
- // .. .. ==> 0XF8006190[19:10] = 0x00000100U
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U
- // .. .. reg_phy_ctrl_slave_force = 0x0
- // .. .. ==> 0XF8006190[20:20] = 0x00000000U
- // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U
- // .. .. reg_phy_ctrl_slave_delay = 0x0
- // .. .. ==> 0XF8006190[27:21] = 0x00000000U
- // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U
- // .. .. reg_phy_use_rank0_delays = 0x1
- // .. .. ==> 0XF8006190[28:28] = 0x00000001U
- // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
- // .. .. reg_phy_lpddr = 0x0
- // .. .. ==> 0XF8006190[29:29] = 0x00000000U
- // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U
- // .. .. reg_phy_cmd_latency = 0x0
- // .. .. ==> 0XF8006190[30:30] = 0x00000000U
- // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U
- // .. .. reg_phy_int_lpbk = 0x0
- // .. .. ==> 0XF8006190[31:31] = 0x00000000U
- // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U),
- // .. .. reg_phy_wr_rl_delay = 0x2
- // .. .. ==> 0XF8006194[4:0] = 0x00000002U
- // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U
- // .. .. reg_phy_rd_rl_delay = 0x4
- // .. .. ==> 0XF8006194[9:5] = 0x00000004U
- // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U
- // .. .. reg_phy_dll_lock_diff = 0xf
- // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
- // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U
- // .. .. reg_phy_use_wr_level = 0x1
- // .. .. ==> 0XF8006194[14:14] = 0x00000001U
- // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U
- // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
- // .. .. ==> 0XF8006194[15:15] = 0x00000001U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U
- // .. .. reg_phy_use_rd_data_eye_level = 0x1
- // .. .. ==> 0XF8006194[16:16] = 0x00000001U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U
- // .. .. reg_phy_dis_calib_rst = 0x0
- // .. .. ==> 0XF8006194[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_phy_ctrl_slave_delay = 0x0
- // .. .. ==> 0XF8006194[19:18] = 0x00000000U
- // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
- // .. .. reg_arb_page_addr_mask = 0x0
- // .. .. ==> 0XF8006204[31:0] = 0x00000000U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
- // .. .. reg_arb_pri_wr_portn = 0x3ff
- // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_wr_portn = 0x0
- // .. .. ==> 0XF8006208[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. .. ==> 0XF8006208[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. .. ==> 0XF8006208[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_dis_rmw_portn = 0x1
- // .. .. ==> 0XF8006208[19:19] = 0x00000001U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // .. ..
- EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU),
- // .. .. reg_arb_pri_wr_portn = 0x3ff
- // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_wr_portn = 0x0
- // .. .. ==> 0XF800620C[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. .. ==> 0XF800620C[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. .. ==> 0XF800620C[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_dis_rmw_portn = 0x1
- // .. .. ==> 0XF800620C[19:19] = 0x00000001U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // .. ..
- EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU),
- // .. .. reg_arb_pri_wr_portn = 0x3ff
- // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_wr_portn = 0x0
- // .. .. ==> 0XF8006210[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. .. ==> 0XF8006210[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. .. ==> 0XF8006210[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_dis_rmw_portn = 0x1
- // .. .. ==> 0XF8006210[19:19] = 0x00000001U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // .. ..
- EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU),
- // .. .. reg_arb_pri_wr_portn = 0x3ff
- // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_wr_portn = 0x0
- // .. .. ==> 0XF8006214[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. .. ==> 0XF8006214[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. .. ==> 0XF8006214[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_dis_rmw_portn = 0x1
- // .. .. ==> 0XF8006214[19:19] = 0x00000001U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // .. ..
- EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU),
- // .. .. reg_arb_pri_rd_portn = 0x3ff
- // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_rd_portn = 0x0
- // .. .. ==> 0XF8006218[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. .. ==> 0XF8006218[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. .. ==> 0XF8006218[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_set_hpr_rd_portn = 0x0
- // .. .. ==> 0XF8006218[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
- // .. .. reg_arb_pri_rd_portn = 0x3ff
- // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_rd_portn = 0x0
- // .. .. ==> 0XF800621C[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. .. ==> 0XF800621C[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. .. ==> 0XF800621C[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_set_hpr_rd_portn = 0x0
- // .. .. ==> 0XF800621C[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
- // .. .. reg_arb_pri_rd_portn = 0x3ff
- // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_rd_portn = 0x0
- // .. .. ==> 0XF8006220[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. .. ==> 0XF8006220[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. .. ==> 0XF8006220[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_set_hpr_rd_portn = 0x0
- // .. .. ==> 0XF8006220[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
- // .. .. reg_arb_pri_rd_portn = 0x3ff
- // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_rd_portn = 0x0
- // .. .. ==> 0XF8006224[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. .. ==> 0XF8006224[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. .. ==> 0XF8006224[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_set_hpr_rd_portn = 0x0
- // .. .. ==> 0XF8006224[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
- // .. .. reg_ddrc_lpddr2 = 0x0
- // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_per_bank_refresh = 0x0
- // .. .. ==> 0XF80062A8[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_ddrc_derate_enable = 0x0
- // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_ddrc_mr4_margin = 0x0
- // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U),
- // .. .. reg_ddrc_mr4_read_interval = 0x0
- // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
- // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
- // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U
- // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
- // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
- // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U
- // .. .. reg_ddrc_t_mrw = 0x5
- // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
- // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U
- // .. ..
- EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
- // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8
- // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U
- // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
- // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
- // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U
- // .. ..
- EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
- // .. .. START: POLL ON DCI STATUS
- // .. .. DONE = 1
- // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
- // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // .. ..
- EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
- // .. .. FINISH: POLL ON DCI STATUS
- // .. .. START: UNLOCK DDR
- // .. .. reg_ddrc_soft_rstb = 0x1
- // .. .. ==> 0XF8006000[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_ddrc_powerdown_en = 0x0
- // .. .. ==> 0XF8006000[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_ddrc_data_bus_width = 0x0
- // .. .. ==> 0XF8006000[3:2] = 0x00000000U
- // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U
- // .. .. reg_ddrc_burst8_refresh = 0x0
- // .. .. ==> 0XF8006000[6:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U
- // .. .. reg_ddrc_rdwr_idle_gap = 1
- // .. .. ==> 0XF8006000[13:7] = 0x00000001U
- // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U
- // .. .. reg_ddrc_dis_rd_bypass = 0x0
- // .. .. ==> 0XF8006000[14:14] = 0x00000000U
- // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_act_bypass = 0x0
- // .. .. ==> 0XF8006000[15:15] = 0x00000000U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_auto_refresh = 0x0
- // .. .. ==> 0XF8006000[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
- // .. .. FINISH: UNLOCK DDR
- // .. .. START: CHECK DDR STATUS
- // .. .. ddrc_reg_operating_mode = 1
- // .. .. ==> 0XF8006054[2:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U
- // .. ..
- EMIT_MASKPOLL(0XF8006054, 0x00000007U),
- // .. .. FINISH: CHECK DDR STATUS
- // .. FINISH: DDR INITIALIZATION
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_mio_init_data_2_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: OCM REMAPPING
- // .. VREF_EN = 0x1
- // .. ==> 0XF8000B00[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. VREF_PULLUP_EN = 0x0
- // .. ==> 0XF8000B00[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. CLK_PULLUP_EN = 0x0
- // .. ==> 0XF8000B00[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. SRSTN_PULLUP_EN = 0x0
- // .. ==> 0XF8000B00[9:9] = 0x00000000U
- // .. ==> MASK : 0x00000200U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B00, 0x00000303U ,0x00000001U),
- // .. FINISH: OCM REMAPPING
- // .. START: DDRIOB SETTINGS
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B40[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x0
- // .. ==> 0XF8000B40[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B40[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x0
- // .. ==> 0XF8000B40[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. DCR_TYPE = 0x0
- // .. ==> 0XF8000B40[6:5] = 0x00000000U
- // .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. IBUF_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B40[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B40[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B40[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B40[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B44[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x0
- // .. ==> 0XF8000B44[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B44[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x0
- // .. ==> 0XF8000B44[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. DCR_TYPE = 0x0
- // .. ==> 0XF8000B44[6:5] = 0x00000000U
- // .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. IBUF_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B44[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B44[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B44[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B44[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B48[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x1
- // .. ==> 0XF8000B48[2:1] = 0x00000001U
- // .. ==> MASK : 0x00000006U VAL : 0x00000002U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B48[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x1
- // .. ==> 0XF8000B48[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. DCR_TYPE = 0x3
- // .. ==> 0XF8000B48[6:5] = 0x00000003U
- // .. ==> MASK : 0x00000060U VAL : 0x00000060U
- // .. IBUF_DISABLE_MODE = 0
- // .. ==> 0XF8000B48[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0
- // .. ==> 0XF8000B48[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B48[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B48[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B4C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x1
- // .. ==> 0XF8000B4C[2:1] = 0x00000001U
- // .. ==> MASK : 0x00000006U VAL : 0x00000002U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B4C[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x1
- // .. ==> 0XF8000B4C[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. DCR_TYPE = 0x3
- // .. ==> 0XF8000B4C[6:5] = 0x00000003U
- // .. ==> MASK : 0x00000060U VAL : 0x00000060U
- // .. IBUF_DISABLE_MODE = 0
- // .. ==> 0XF8000B4C[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0
- // .. ==> 0XF8000B4C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B4C[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B4C[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B50[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x2
- // .. ==> 0XF8000B50[2:1] = 0x00000002U
- // .. ==> MASK : 0x00000006U VAL : 0x00000004U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B50[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x1
- // .. ==> 0XF8000B50[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. DCR_TYPE = 0x3
- // .. ==> 0XF8000B50[6:5] = 0x00000003U
- // .. ==> MASK : 0x00000060U VAL : 0x00000060U
- // .. IBUF_DISABLE_MODE = 0
- // .. ==> 0XF8000B50[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0
- // .. ==> 0XF8000B50[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B50[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B50[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B54[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x2
- // .. ==> 0XF8000B54[2:1] = 0x00000002U
- // .. ==> MASK : 0x00000006U VAL : 0x00000004U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B54[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x1
- // .. ==> 0XF8000B54[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. DCR_TYPE = 0x3
- // .. ==> 0XF8000B54[6:5] = 0x00000003U
- // .. ==> MASK : 0x00000060U VAL : 0x00000060U
- // .. IBUF_DISABLE_MODE = 0
- // .. ==> 0XF8000B54[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0
- // .. ==> 0XF8000B54[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B54[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B54[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B58[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x0
- // .. ==> 0XF8000B58[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B58[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x0
- // .. ==> 0XF8000B58[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. DCR_TYPE = 0x0
- // .. ==> 0XF8000B58[6:5] = 0x00000000U
- // .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. IBUF_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B58[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B58[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B58[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B58[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
- // .. DRIVE_P = 0x1c
- // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
- // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
- // .. DRIVE_N = 0xc
- // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
- // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
- // .. SLEW_P = 0x3
- // .. ==> 0XF8000B5C[18:14] = 0x00000003U
- // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U
- // .. SLEW_N = 0x3
- // .. ==> 0XF8000B5C[23:19] = 0x00000003U
- // .. ==> MASK : 0x00F80000U VAL : 0x00180000U
- // .. GTL = 0x0
- // .. ==> 0XF8000B5C[26:24] = 0x00000000U
- // .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. RTERM = 0x0
- // .. ==> 0XF8000B5C[31:27] = 0x00000000U
- // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
- // .. DRIVE_P = 0x1c
- // .. ==> 0XF8000B60[6:0] = 0x0000001CU
- // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
- // .. DRIVE_N = 0xc
- // .. ==> 0XF8000B60[13:7] = 0x0000000CU
- // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
- // .. SLEW_P = 0x6
- // .. ==> 0XF8000B60[18:14] = 0x00000006U
- // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
- // .. SLEW_N = 0x1f
- // .. ==> 0XF8000B60[23:19] = 0x0000001FU
- // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
- // .. GTL = 0x0
- // .. ==> 0XF8000B60[26:24] = 0x00000000U
- // .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. RTERM = 0x0
- // .. ==> 0XF8000B60[31:27] = 0x00000000U
- // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
- // .. DRIVE_P = 0x1c
- // .. ==> 0XF8000B64[6:0] = 0x0000001CU
- // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
- // .. DRIVE_N = 0xc
- // .. ==> 0XF8000B64[13:7] = 0x0000000CU
- // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
- // .. SLEW_P = 0x6
- // .. ==> 0XF8000B64[18:14] = 0x00000006U
- // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
- // .. SLEW_N = 0x1f
- // .. ==> 0XF8000B64[23:19] = 0x0000001FU
- // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
- // .. GTL = 0x0
- // .. ==> 0XF8000B64[26:24] = 0x00000000U
- // .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. RTERM = 0x0
- // .. ==> 0XF8000B64[31:27] = 0x00000000U
- // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
- // .. DRIVE_P = 0x1c
- // .. ==> 0XF8000B68[6:0] = 0x0000001CU
- // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
- // .. DRIVE_N = 0xc
- // .. ==> 0XF8000B68[13:7] = 0x0000000CU
- // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
- // .. SLEW_P = 0x6
- // .. ==> 0XF8000B68[18:14] = 0x00000006U
- // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
- // .. SLEW_N = 0x1f
- // .. ==> 0XF8000B68[23:19] = 0x0000001FU
- // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
- // .. GTL = 0x0
- // .. ==> 0XF8000B68[26:24] = 0x00000000U
- // .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. RTERM = 0x0
- // .. ==> 0XF8000B68[31:27] = 0x00000000U
- // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
- // .. VREF_INT_EN = 0x1
- // .. ==> 0XF8000B6C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. VREF_SEL = 0x4
- // .. ==> 0XF8000B6C[4:1] = 0x00000004U
- // .. ==> MASK : 0x0000001EU VAL : 0x00000008U
- // .. VREF_EXT_EN = 0x0
- // .. ==> 0XF8000B6C[6:5] = 0x00000000U
- // .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. VREF_PULLUP_EN = 0x0
- // .. ==> 0XF8000B6C[8:7] = 0x00000000U
- // .. ==> MASK : 0x00000180U VAL : 0x00000000U
- // .. REFIO_EN = 0x1
- // .. ==> 0XF8000B6C[9:9] = 0x00000001U
- // .. ==> MASK : 0x00000200U VAL : 0x00000200U
- // .. REFIO_TEST = 0x3
- // .. ==> 0XF8000B6C[11:10] = 0x00000003U
- // .. ==> MASK : 0x00000C00U VAL : 0x00000C00U
- // .. REFIO_PULLUP_EN = 0x0
- // .. ==> 0XF8000B6C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DRST_B_PULLUP_EN = 0x0
- // .. ==> 0XF8000B6C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // .. CKE_PULLUP_EN = 0x0
- // .. ==> 0XF8000B6C[14:14] = 0x00000000U
- // .. ==> MASK : 0x00004000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000E09U),
- // .. .. START: ASSERT RESET
- // .. .. RESET = 1
- // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. VRN_OUT = 0x1
- // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
- // .. ..
- EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U),
- // .. .. FINISH: ASSERT RESET
- // .. .. START: DEASSERT RESET
- // .. .. RESET = 0
- // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. VRN_OUT = 0x1
- // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
- // .. ..
- EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
- // .. .. FINISH: DEASSERT RESET
- // .. .. RESET = 0x1
- // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ENABLE = 0x1
- // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. .. VRP_TRI = 0x0
- // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. VRN_TRI = 0x0
- // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. VRP_OUT = 0x0
- // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. VRN_OUT = 0x1
- // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
- // .. .. NREF_OPT1 = 0x0
- // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
- // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U
- // .. .. NREF_OPT2 = 0x0
- // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U
- // .. .. NREF_OPT4 = 0x1
- // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
- // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U
- // .. .. PREF_OPT1 = 0x0
- // .. .. ==> 0XF8000B70[16:14] = 0x00000000U
- // .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U
- // .. .. PREF_OPT2 = 0x0
- // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
- // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U
- // .. .. UPDATE_CONTROL = 0x0
- // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
- // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U
- // .. .. INIT_COMPLETE = 0x0
- // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
- // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U
- // .. .. TST_CLK = 0x0
- // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
- // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U
- // .. .. TST_HLN = 0x0
- // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
- // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U
- // .. .. TST_HLP = 0x0
- // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
- // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U
- // .. .. TST_RST = 0x0
- // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
- // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
- // .. .. INT_DCI_EN = 0x0
- // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
- // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U),
- // .. FINISH: DDRIOB SETTINGS
- // .. START: MIO PROGRAMMING
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000700[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000700[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000700[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000700[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000700[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000700[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000700[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 1
- // .. ==> 0XF8000700[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000700[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001202U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000704[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000704[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000704[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000704[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000704[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000704[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000704[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 1
- // .. ==> 0XF8000704[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000704[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001202U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000708[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000708[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000708[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000708[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000708[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000708[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000708[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000708[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000708[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000202U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800070C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF800070C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF800070C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800070C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800070C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800070C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF800070C[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF800070C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800070C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000202U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000710[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000710[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000710[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000710[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000710[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000710[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000710[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000710[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000710[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000202U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000714[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000714[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000714[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000714[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000714[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000714[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000714[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000714[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000714[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000202U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000718[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000718[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000718[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000718[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000718[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000718[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000718[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000718[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000718[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000202U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800071C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800071C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF800071C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800071C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800071C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800071C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF800071C[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF800071C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800071C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000200U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000720[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000720[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000720[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000720[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000720[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000720[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000720[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000720[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000720[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000202U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000724[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000724[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000724[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000724[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000724[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000724[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000724[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 1
- // .. ==> 0XF8000724[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000724[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001202U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000728[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000728[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000728[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000728[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000728[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000728[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000728[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 1
- // .. ==> 0XF8000728[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000728[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001202U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800072C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF800072C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF800072C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800072C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800072C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800072C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF800072C[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 1
- // .. ==> 0XF800072C[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800072C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001202U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000730[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000730[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000730[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000730[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000730[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000730[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000730[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 1
- // .. ==> 0XF8000730[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000730[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001202U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000734[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000734[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000734[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000734[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000734[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000734[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000734[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 1
- // .. ==> 0XF8000734[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000734[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001202U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000738[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. Speed = 0
- // .. ==> 0XF8000738[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000738[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 1
- // .. ==> 0XF8000738[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000738[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000738, 0x00003F01U ,0x00001201U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF800073C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. Speed = 0
- // .. ==> 0XF800073C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF800073C[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 1
- // .. ==> 0XF800073C[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800073C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800073C, 0x00003F01U ,0x00001201U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000740[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000740[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000740[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000740[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000740[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000740[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 4
- // .. ==> 0XF8000740[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000740[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 1
- // .. ==> 0XF8000740[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // ..
- EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00002802U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000744[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000744[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000744[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000744[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000744[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000744[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 4
- // .. ==> 0XF8000744[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000744[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 1
- // .. ==> 0XF8000744[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // ..
- EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00002802U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000748[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000748[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000748[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000748[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000748[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000748[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 4
- // .. ==> 0XF8000748[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000748[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 1
- // .. ==> 0XF8000748[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // ..
- EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00002802U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800074C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF800074C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF800074C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800074C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800074C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800074C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 4
- // .. ==> 0XF800074C[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF800074C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 1
- // .. ==> 0XF800074C[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // ..
- EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00002802U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000750[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000750[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000750[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000750[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000750[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000750[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 4
- // .. ==> 0XF8000750[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000750[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 1
- // .. ==> 0XF8000750[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // ..
- EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00002802U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000754[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000754[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000754[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000754[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000754[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000754[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 4
- // .. ==> 0XF8000754[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000754[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 1
- // .. ==> 0XF8000754[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // ..
- EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00002802U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000758[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF8000758[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000758[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000758[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000758[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000758[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 4
- // .. ==> 0XF8000758[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000758[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000758[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000803U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF800075C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF800075C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF800075C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800075C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800075C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800075C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 4
- // .. ==> 0XF800075C[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF800075C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800075C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000803U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000760[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF8000760[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000760[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000760[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000760[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000760[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 4
- // .. ==> 0XF8000760[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000760[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000760[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000803U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000764[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF8000764[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000764[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000764[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000764[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000764[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 4
- // .. ==> 0XF8000764[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000764[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000764[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000803U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000768[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF8000768[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000768[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000768[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000768[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000768[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 4
- // .. ==> 0XF8000768[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000768[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000768[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000803U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF800076C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF800076C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF800076C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800076C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800076C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800076C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 4
- // .. ==> 0XF800076C[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF800076C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800076C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000803U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000770[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000770[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000770[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000770[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000770[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000770[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000770[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000770[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000770[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000774[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF8000774[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000774[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000774[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000774[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000774[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000774[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000774[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000774[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000778[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000778[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000778[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000778[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000778[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000778[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000778[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000778[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000778[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF800077C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF800077C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF800077C[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF800077C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800077C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800077C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF800077C[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF800077C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800077C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000780[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000780[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000780[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000780[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000780[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000780[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000780[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000780[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000780[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000784[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000784[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000784[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000784[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000784[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000784[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000784[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000784[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000784[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000788[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000788[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000788[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000788[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000788[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000788[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000788[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000788[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000788[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800078C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800078C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF800078C[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF800078C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800078C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800078C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF800078C[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF800078C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800078C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000790[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF8000790[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000790[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000790[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000790[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000790[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000790[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000790[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000790[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000794[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000794[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000794[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000794[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000794[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000794[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000794[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000794[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000794[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000798[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000798[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000798[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000798[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000798[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000798[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000798[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000798[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000798[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800079C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800079C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF800079C[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF800079C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800079C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800079C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF800079C[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF800079C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800079C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007A0[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007A0[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007A0[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007A0[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007A0[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF80007A0[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007A0[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007A0[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007A0[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000280U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007A4[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007A4[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007A4[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007A4[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007A4[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF80007A4[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007A4[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007A4[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007A4[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000280U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007A8[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007A8[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007A8[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007A8[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007A8[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF80007A8[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007A8[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007A8[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007A8[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000280U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007AC[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007AC[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007AC[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007AC[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007AC[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF80007AC[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007AC[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007AC[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007AC[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000280U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007B0[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007B0[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007B0[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007B0[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007B0[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF80007B0[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007B0[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007B0[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007B0[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000280U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007B4[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007B4[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007B4[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007B4[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007B4[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF80007B4[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007B4[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007B4[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007B4[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000280U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007B8[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007B8[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007B8[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007B8[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF80007B8[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF80007B8[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007B8[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 1
- // .. ==> 0XF80007B8[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007B8[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001200U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007BC[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007BC[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007BC[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007BC[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF80007BC[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF80007BC[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007BC[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 1
- // .. ==> 0XF80007BC[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007BC[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00001200U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007C0[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007C0[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007C0[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007C0[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 7
- // .. ==> 0XF80007C0[7:5] = 0x00000007U
- // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U
- // .. Speed = 0
- // .. ==> 0XF80007C0[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007C0[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007C0[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007C0[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF80007C4[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF80007C4[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007C4[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007C4[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 7
- // .. ==> 0XF80007C4[7:5] = 0x00000007U
- // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U
- // .. Speed = 0
- // .. ==> 0XF80007C4[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007C4[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007C4[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007C4[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007C8[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007C8[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007C8[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007C8[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 2
- // .. ==> 0XF80007C8[7:5] = 0x00000002U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000040U
- // .. Speed = 0
- // .. ==> 0XF80007C8[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007C8[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 1
- // .. ==> 0XF80007C8[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007C8[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001240U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007CC[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007CC[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007CC[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007CC[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 2
- // .. ==> 0XF80007CC[7:5] = 0x00000002U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000040U
- // .. Speed = 0
- // .. ==> 0XF80007CC[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007CC[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 1
- // .. ==> 0XF80007CC[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007CC[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001240U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007D0[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007D0[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007D0[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007D0[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007D0[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF80007D0[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007D0[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007D0[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007D0[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007D4[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007D4[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007D4[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007D4[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007D4[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF80007D4[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007D4[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007D4[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007D4[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U),
- // .. SDIO0_WP_SEL = 15
- // .. ==> 0XF8000830[5:0] = 0x0000000FU
- // .. ==> MASK : 0x0000003FU VAL : 0x0000000FU
- // .. SDIO0_CD_SEL = 14
- // .. ==> 0XF8000830[21:16] = 0x0000000EU
- // .. ==> MASK : 0x003F0000U VAL : 0x000E0000U
- // ..
- EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x000E000FU),
- // .. FINISH: MIO PROGRAMMING
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_peripherals_init_data_2_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
- // .. IBUF_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B48[7:7] = 0x00000001U
- // .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. TERM_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B48[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // ..
- EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
- // .. IBUF_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B4C[7:7] = 0x00000001U
- // .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. TERM_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B4C[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // ..
- EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
- // .. IBUF_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B50[7:7] = 0x00000001U
- // .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. TERM_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B50[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // ..
- EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
- // .. IBUF_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B54[7:7] = 0x00000001U
- // .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. TERM_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B54[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // ..
- EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
- // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // .. START: SRAM/NOR SET OPMODE
- // .. FINISH: SRAM/NOR SET OPMODE
- // .. START: UART REGISTERS
- // .. BDIV = 0x6
- // .. ==> 0XE0001034[7:0] = 0x00000006U
- // .. ==> MASK : 0x000000FFU VAL : 0x00000006U
- // ..
- EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
- // .. CD = 0x3e
- // .. ==> 0XE0001018[15:0] = 0x0000003EU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU
- // ..
- EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
- // .. STPBRK = 0x0
- // .. ==> 0XE0001000[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. STTBRK = 0x0
- // .. ==> 0XE0001000[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. RSTTO = 0x0
- // .. ==> 0XE0001000[6:6] = 0x00000000U
- // .. ==> MASK : 0x00000040U VAL : 0x00000000U
- // .. TXDIS = 0x0
- // .. ==> 0XE0001000[5:5] = 0x00000000U
- // .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. TXEN = 0x1
- // .. ==> 0XE0001000[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. RXDIS = 0x0
- // .. ==> 0XE0001000[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. RXEN = 0x1
- // .. ==> 0XE0001000[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. TXRES = 0x1
- // .. ==> 0XE0001000[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. RXRES = 0x1
- // .. ==> 0XE0001000[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // ..
- EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
- // .. IRMODE = 0x0
- // .. ==> 0XE0001004[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. UCLKEN = 0x0
- // .. ==> 0XE0001004[10:10] = 0x00000000U
- // .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. CHMODE = 0x0
- // .. ==> 0XE0001004[9:8] = 0x00000000U
- // .. ==> MASK : 0x00000300U VAL : 0x00000000U
- // .. NBSTOP = 0x0
- // .. ==> 0XE0001004[7:6] = 0x00000000U
- // .. ==> MASK : 0x000000C0U VAL : 0x00000000U
- // .. PAR = 0x4
- // .. ==> 0XE0001004[5:3] = 0x00000004U
- // .. ==> MASK : 0x00000038U VAL : 0x00000020U
- // .. CHRL = 0x0
- // .. ==> 0XE0001004[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. CLKS = 0x0
- // .. ==> 0XE0001004[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U),
- // .. FINISH: UART REGISTERS
- // .. START: QSPI REGISTERS
- // .. Holdb_dr = 1
- // .. ==> 0XE000D000[19:19] = 0x00000001U
- // .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // ..
- EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
- // .. FINISH: QSPI REGISTERS
- // .. START: PL POWER ON RESET REGISTERS
- // .. PCFG_POR_CNT_4K = 0
- // .. ==> 0XF8007000[29:29] = 0x00000000U
- // .. ==> MASK : 0x20000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
- // .. FINISH: PL POWER ON RESET REGISTERS
- // .. START: SMC TIMING CALCULATION REGISTER UPDATE
- // .. .. START: NAND SET CYCLE
- // .. .. FINISH: NAND SET CYCLE
- // .. .. START: OPMODE
- // .. .. FINISH: OPMODE
- // .. .. START: DIRECT COMMAND
- // .. .. FINISH: DIRECT COMMAND
- // .. .. START: SRAM/NOR CS0 SET CYCLE
- // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
- // .. .. START: DIRECT COMMAND
- // .. .. FINISH: DIRECT COMMAND
- // .. .. START: NOR CS0 BASE ADDRESS
- // .. .. FINISH: NOR CS0 BASE ADDRESS
- // .. .. START: SRAM/NOR CS1 SET CYCLE
- // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
- // .. .. START: DIRECT COMMAND
- // .. .. FINISH: DIRECT COMMAND
- // .. .. START: NOR CS1 BASE ADDRESS
- // .. .. FINISH: NOR CS1 BASE ADDRESS
- // .. .. START: USB RESET
- // .. .. .. START: USB0 RESET
- // .. .. .. .. START: DIR MODE BANK 0
- // .. .. .. .. DIRECTION_0 = 0x80
- // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U
- // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U),
- // .. .. .. .. FINISH: DIR MODE BANK 0
- // .. .. .. .. START: DIR MODE BANK 1
- // .. .. .. .. FINISH: DIR MODE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. MASK_0_LSW = 0xff7f
- // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
- // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U
- // .. .. .. .. DATA_0_LSW = 0x80
- // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
- // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. START: OUTPUT ENABLE BANK 0
- // .. .. .. .. OP_ENABLE_0 = 0x80
- // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U
- // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U),
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
- // .. .. .. .. START: OUTPUT ENABLE BANK 1
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. MASK_0_LSW = 0xff7f
- // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
- // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U
- // .. .. .. .. DATA_0_LSW = 0x0
- // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
- // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U),
- // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. START: ADD 1 MS DELAY
- // .. .. .. ..
- EMIT_MASKDELAY(0XF8F00200, 1),
- // .. .. .. .. FINISH: ADD 1 MS DELAY
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. MASK_0_LSW = 0xff7f
- // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
- // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U
- // .. .. .. .. DATA_0_LSW = 0x80
- // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
- // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: USB0 RESET
- // .. .. .. START: USB1 RESET
- // .. .. .. .. START: DIR MODE BANK 0
- // .. .. .. .. FINISH: DIR MODE BANK 0
- // .. .. .. .. START: DIR MODE BANK 1
- // .. .. .. .. FINISH: DIR MODE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. START: OUTPUT ENABLE BANK 0
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
- // .. .. .. .. START: OUTPUT ENABLE BANK 1
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. START: ADD 1 MS DELAY
- // .. .. .. ..
- EMIT_MASKDELAY(0XF8F00200, 1),
- // .. .. .. .. FINISH: ADD 1 MS DELAY
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: USB1 RESET
- // .. .. FINISH: USB RESET
- // .. .. START: ENET RESET
- // .. .. .. START: ENET0 RESET
- // .. .. .. .. START: DIR MODE BANK 0
- // .. .. .. .. FINISH: DIR MODE BANK 0
- // .. .. .. .. START: DIR MODE BANK 1
- // .. .. .. .. DIRECTION_1 = 0x8000
- // .. .. .. .. ==> 0XE000A244[21:0] = 0x00008000U
- // .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00008000U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x00008000U),
- // .. .. .. .. FINISH: DIR MODE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. MASK_1_LSW = 0x7fff
- // .. .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU
- // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0x7FFF0000U
- // .. .. .. .. DATA_1_LSW = 0x8000
- // .. .. .. .. ==> 0XE000A008[15:0] = 0x00008000U
- // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00008000U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF8000U),
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. START: OUTPUT ENABLE BANK 0
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
- // .. .. .. .. START: OUTPUT ENABLE BANK 1
- // .. .. .. .. OP_ENABLE_1 = 0x8000
- // .. .. .. .. ==> 0XE000A248[21:0] = 0x00008000U
- // .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00008000U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x00008000U),
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. MASK_1_LSW = 0x7fff
- // .. .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU
- // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0x7FFF0000U
- // .. .. .. .. DATA_1_LSW = 0x0
- // .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U
- // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF0000U),
- // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. START: ADD 1 MS DELAY
- // .. .. .. ..
- EMIT_MASKDELAY(0XF8F00200, 1),
- // .. .. .. .. FINISH: ADD 1 MS DELAY
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. MASK_1_LSW = 0x7fff
- // .. .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU
- // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0x7FFF0000U
- // .. .. .. .. DATA_1_LSW = 0x8000
- // .. .. .. .. ==> 0XE000A008[15:0] = 0x00008000U
- // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00008000U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF8000U),
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: ENET0 RESET
- // .. .. .. START: ENET1 RESET
- // .. .. .. .. START: DIR MODE BANK 0
- // .. .. .. .. FINISH: DIR MODE BANK 0
- // .. .. .. .. START: DIR MODE BANK 1
- // .. .. .. .. FINISH: DIR MODE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. START: OUTPUT ENABLE BANK 0
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
- // .. .. .. .. START: OUTPUT ENABLE BANK 1
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. START: ADD 1 MS DELAY
- // .. .. .. ..
- EMIT_MASKDELAY(0XF8F00200, 1),
- // .. .. .. .. FINISH: ADD 1 MS DELAY
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: ENET1 RESET
- // .. .. FINISH: ENET RESET
- // .. .. START: I2C RESET
- // .. .. .. START: I2C0 RESET
- // .. .. .. .. START: DIR MODE GPIO BANK0
- // .. .. .. .. FINISH: DIR MODE GPIO BANK0
- // .. .. .. .. START: DIR MODE GPIO BANK1
- // .. .. .. .. DIRECTION_1 = 0x4000
- // .. .. .. .. ==> 0XE000A244[21:0] = 0x00004000U
- // .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x00004000U),
- // .. .. .. .. FINISH: DIR MODE GPIO BANK1
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. MASK_1_LSW = 0xbfff
- // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
- // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U
- // .. .. .. .. DATA_1_LSW = 0x4000
- // .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U
- // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U),
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. START: OUTPUT ENABLE
- // .. .. .. .. FINISH: OUTPUT ENABLE
- // .. .. .. .. START: OUTPUT ENABLE
- // .. .. .. .. OP_ENABLE_1 = 0x4000
- // .. .. .. .. ==> 0XE000A248[21:0] = 0x00004000U
- // .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x00004000U),
- // .. .. .. .. FINISH: OUTPUT ENABLE
- // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. MASK_1_LSW = 0xbfff
- // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
- // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U
- // .. .. .. .. DATA_1_LSW = 0x0
- // .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U
- // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF0000U),
- // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. START: ADD 1 MS DELAY
- // .. .. .. ..
- EMIT_MASKDELAY(0XF8F00200, 1),
- // .. .. .. .. FINISH: ADD 1 MS DELAY
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. MASK_1_LSW = 0xbfff
- // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
- // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U
- // .. .. .. .. DATA_1_LSW = 0x4000
- // .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U
- // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U),
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: I2C0 RESET
- // .. .. .. START: I2C1 RESET
- // .. .. .. .. START: DIR MODE GPIO BANK0
- // .. .. .. .. FINISH: DIR MODE GPIO BANK0
- // .. .. .. .. START: DIR MODE GPIO BANK1
- // .. .. .. .. FINISH: DIR MODE GPIO BANK1
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. START: OUTPUT ENABLE
- // .. .. .. .. FINISH: OUTPUT ENABLE
- // .. .. .. .. START: OUTPUT ENABLE
- // .. .. .. .. FINISH: OUTPUT ENABLE
- // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. START: ADD 1 MS DELAY
- // .. .. .. ..
- EMIT_MASKDELAY(0XF8F00200, 1),
- // .. .. .. .. FINISH: ADD 1 MS DELAY
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: I2C1 RESET
- // .. .. FINISH: I2C RESET
- // .. .. START: NOR CHIP SELECT
- // .. .. .. START: DIR MODE BANK 0
- // .. .. .. FINISH: DIR MODE BANK 0
- // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. START: OUTPUT ENABLE BANK 0
- // .. .. .. FINISH: OUTPUT ENABLE BANK 0
- // .. .. FINISH: NOR CHIP SELECT
- // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_post_config_2_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: ENABLING LEVEL SHIFTER
- // .. USER_INP_ICT_EN_0 = 3
- // .. ==> 0XF8000900[1:0] = 0x00000003U
- // .. ==> MASK : 0x00000003U VAL : 0x00000003U
- // .. USER_INP_ICT_EN_1 = 3
- // .. ==> 0XF8000900[3:2] = 0x00000003U
- // .. ==> MASK : 0x0000000CU VAL : 0x0000000CU
- // ..
- EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
- // .. FINISH: ENABLING LEVEL SHIFTER
- // .. START: FPGA RESETS TO 0
- // .. reserved_3 = 0
- // .. ==> 0XF8000240[31:25] = 0x00000000U
- // .. ==> MASK : 0xFE000000U VAL : 0x00000000U
- // .. FPGA_ACP_RST = 0
- // .. ==> 0XF8000240[24:24] = 0x00000000U
- // .. ==> MASK : 0x01000000U VAL : 0x00000000U
- // .. FPGA_AXDS3_RST = 0
- // .. ==> 0XF8000240[23:23] = 0x00000000U
- // .. ==> MASK : 0x00800000U VAL : 0x00000000U
- // .. FPGA_AXDS2_RST = 0
- // .. ==> 0XF8000240[22:22] = 0x00000000U
- // .. ==> MASK : 0x00400000U VAL : 0x00000000U
- // .. FPGA_AXDS1_RST = 0
- // .. ==> 0XF8000240[21:21] = 0x00000000U
- // .. ==> MASK : 0x00200000U VAL : 0x00000000U
- // .. FPGA_AXDS0_RST = 0
- // .. ==> 0XF8000240[20:20] = 0x00000000U
- // .. ==> MASK : 0x00100000U VAL : 0x00000000U
- // .. reserved_2 = 0
- // .. ==> 0XF8000240[19:18] = 0x00000000U
- // .. ==> MASK : 0x000C0000U VAL : 0x00000000U
- // .. FSSW1_FPGA_RST = 0
- // .. ==> 0XF8000240[17:17] = 0x00000000U
- // .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. FSSW0_FPGA_RST = 0
- // .. ==> 0XF8000240[16:16] = 0x00000000U
- // .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. reserved_1 = 0
- // .. ==> 0XF8000240[15:14] = 0x00000000U
- // .. ==> MASK : 0x0000C000U VAL : 0x00000000U
- // .. FPGA_FMSW1_RST = 0
- // .. ==> 0XF8000240[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // .. FPGA_FMSW0_RST = 0
- // .. ==> 0XF8000240[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. FPGA_DMA3_RST = 0
- // .. ==> 0XF8000240[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. FPGA_DMA2_RST = 0
- // .. ==> 0XF8000240[10:10] = 0x00000000U
- // .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. FPGA_DMA1_RST = 0
- // .. ==> 0XF8000240[9:9] = 0x00000000U
- // .. ==> MASK : 0x00000200U VAL : 0x00000000U
- // .. FPGA_DMA0_RST = 0
- // .. ==> 0XF8000240[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. reserved = 0
- // .. ==> 0XF8000240[7:4] = 0x00000000U
- // .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. FPGA3_OUT_RST = 0
- // .. ==> 0XF8000240[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. FPGA2_OUT_RST = 0
- // .. ==> 0XF8000240[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. FPGA1_OUT_RST = 0
- // .. ==> 0XF8000240[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. FPGA0_OUT_RST = 0
- // .. ==> 0XF8000240[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
- // .. FINISH: FPGA RESETS TO 0
- // .. START: AFI REGISTERS
- // .. .. START: AFI0 REGISTERS
- // .. .. FINISH: AFI0 REGISTERS
- // .. .. START: AFI1 REGISTERS
- // .. .. FINISH: AFI1 REGISTERS
- // .. .. START: AFI2 REGISTERS
- // .. .. FINISH: AFI2 REGISTERS
- // .. .. START: AFI3 REGISTERS
- // .. .. FINISH: AFI3 REGISTERS
- // .. FINISH: AFI REGISTERS
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_debug_2_0[] = {
- // START: top
- // .. START: CROSS TRIGGER CONFIGURATIONS
- // .. .. START: UNLOCKING CTI REGISTERS
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. FINISH: UNLOCKING CTI REGISTERS
- // .. .. START: ENABLING CTI MODULES AND CHANNELS
- // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
- // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. FINISH: CROSS TRIGGER CONFIGURATIONS
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_pll_init_data_1_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: PLL SLCR REGISTERS
- // .. .. START: ARM PLL INIT
- // .. .. PLL_RES = 0x2
- // .. .. ==> 0XF8000110[7:4] = 0x00000002U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
- // .. .. PLL_CP = 0x2
- // .. .. ==> 0XF8000110[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. LOCK_CNT = 0xfa
- // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
- // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U
- // .. ..
- EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
- // .. .. .. START: UPDATE FB_DIV
- // .. .. .. PLL_FDIV = 0x28
- // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
- // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
- // .. .. .. FINISH: UPDATE FB_DIV
- // .. .. .. START: BY PASS PLL
- // .. .. .. PLL_BYPASS_FORCE = 1
- // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
- // .. .. .. FINISH: BY PASS PLL
- // .. .. .. START: ASSERT RESET
- // .. .. .. PLL_RESET = 1
- // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
- // .. .. .. FINISH: ASSERT RESET
- // .. .. .. START: DEASSERT RESET
- // .. .. .. PLL_RESET = 0
- // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
- // .. .. .. FINISH: DEASSERT RESET
- // .. .. .. START: CHECK PLL STATUS
- // .. .. .. ARM_PLL_LOCK = 1
- // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ..
- EMIT_MASKPOLL(0XF800010C, 0x00000001U),
- // .. .. .. FINISH: CHECK PLL STATUS
- // .. .. .. START: REMOVE PLL BY PASS
- // .. .. .. PLL_BYPASS_FORCE = 0
- // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
- // .. .. .. FINISH: REMOVE PLL BY PASS
- // .. .. .. SRCSEL = 0x0
- // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. .. .. DIVISOR = 0x2
- // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
- // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U
- // .. .. .. CPU_6OR4XCLKACT = 0x1
- // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
- // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U
- // .. .. .. CPU_3OR2XCLKACT = 0x1
- // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
- // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U
- // .. .. .. CPU_2XCLKACT = 0x1
- // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
- // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U
- // .. .. .. CPU_1XCLKACT = 0x1
- // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
- // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U
- // .. .. .. CPU_PERI_CLKACT = 0x1
- // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
- // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
- // .. .. FINISH: ARM PLL INIT
- // .. .. START: DDR PLL INIT
- // .. .. PLL_RES = 0x2
- // .. .. ==> 0XF8000114[7:4] = 0x00000002U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
- // .. .. PLL_CP = 0x2
- // .. .. ==> 0XF8000114[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. LOCK_CNT = 0x12c
- // .. .. ==> 0XF8000114[21:12] = 0x0000012CU
- // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U
- // .. ..
- EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
- // .. .. .. START: UPDATE FB_DIV
- // .. .. .. PLL_FDIV = 0x20
- // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
- // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
- // .. .. .. FINISH: UPDATE FB_DIV
- // .. .. .. START: BY PASS PLL
- // .. .. .. PLL_BYPASS_FORCE = 1
- // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
- // .. .. .. FINISH: BY PASS PLL
- // .. .. .. START: ASSERT RESET
- // .. .. .. PLL_RESET = 1
- // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
- // .. .. .. FINISH: ASSERT RESET
- // .. .. .. START: DEASSERT RESET
- // .. .. .. PLL_RESET = 0
- // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
- // .. .. .. FINISH: DEASSERT RESET
- // .. .. .. START: CHECK PLL STATUS
- // .. .. .. DDR_PLL_LOCK = 1
- // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. .. ..
- EMIT_MASKPOLL(0XF800010C, 0x00000002U),
- // .. .. .. FINISH: CHECK PLL STATUS
- // .. .. .. START: REMOVE PLL BY PASS
- // .. .. .. PLL_BYPASS_FORCE = 0
- // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
- // .. .. .. FINISH: REMOVE PLL BY PASS
- // .. .. .. DDR_3XCLKACT = 0x1
- // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. .. DDR_2XCLKACT = 0x1
- // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. .. .. DDR_3XCLK_DIVISOR = 0x2
- // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
- // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U
- // .. .. .. DDR_2XCLK_DIVISOR = 0x3
- // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
- // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
- // .. .. FINISH: DDR PLL INIT
- // .. .. START: IO PLL INIT
- // .. .. PLL_RES = 0xc
- // .. .. ==> 0XF8000118[7:4] = 0x0000000CU
- // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U
- // .. .. PLL_CP = 0x2
- // .. .. ==> 0XF8000118[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. LOCK_CNT = 0x145
- // .. .. ==> 0XF8000118[21:12] = 0x00000145U
- // .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U
- // .. ..
- EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U),
- // .. .. .. START: UPDATE FB_DIV
- // .. .. .. PLL_FDIV = 0x1e
- // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU
- // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U),
- // .. .. .. FINISH: UPDATE FB_DIV
- // .. .. .. START: BY PASS PLL
- // .. .. .. PLL_BYPASS_FORCE = 1
- // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
- // .. .. .. FINISH: BY PASS PLL
- // .. .. .. START: ASSERT RESET
- // .. .. .. PLL_RESET = 1
- // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
- // .. .. .. FINISH: ASSERT RESET
- // .. .. .. START: DEASSERT RESET
- // .. .. .. PLL_RESET = 0
- // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
- // .. .. .. FINISH: DEASSERT RESET
- // .. .. .. START: CHECK PLL STATUS
- // .. .. .. IO_PLL_LOCK = 1
- // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. .. ..
- EMIT_MASKPOLL(0XF800010C, 0x00000004U),
- // .. .. .. FINISH: CHECK PLL STATUS
- // .. .. .. START: REMOVE PLL BY PASS
- // .. .. .. PLL_BYPASS_FORCE = 0
- // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
- // .. .. .. FINISH: REMOVE PLL BY PASS
- // .. .. FINISH: IO PLL INIT
- // .. FINISH: PLL SLCR REGISTERS
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_clock_init_data_1_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: CLOCK CONTROL SLCR REGISTERS
- // .. CLKACT = 0x1
- // .. ==> 0XF8000128[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. DIVISOR0 = 0x23
- // .. ==> 0XF8000128[13:8] = 0x00000023U
- // .. ==> MASK : 0x00003F00U VAL : 0x00002300U
- // .. DIVISOR1 = 0x3
- // .. ==> 0XF8000128[25:20] = 0x00000003U
- // .. ==> MASK : 0x03F00000U VAL : 0x00300000U
- // ..
- EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U),
- // .. CLKACT = 0x1
- // .. ==> 0XF8000138[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000138[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
- // .. CLKACT = 0x1
- // .. ==> 0XF8000140[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000140[6:4] = 0x00000000U
- // .. ==> MASK : 0x00000070U VAL : 0x00000000U
- // .. DIVISOR = 0x8
- // .. ==> 0XF8000140[13:8] = 0x00000008U
- // .. ==> MASK : 0x00003F00U VAL : 0x00000800U
- // .. DIVISOR1 = 0x5
- // .. ==> 0XF8000140[25:20] = 0x00000005U
- // .. ==> MASK : 0x03F00000U VAL : 0x00500000U
- // ..
- EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00500801U),
- // .. CLKACT = 0x1
- // .. ==> 0XF800014C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. SRCSEL = 0x0
- // .. ==> 0XF800014C[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR = 0x5
- // .. ==> 0XF800014C[13:8] = 0x00000005U
- // .. ==> MASK : 0x00003F00U VAL : 0x00000500U
- // ..
- EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
- // .. CLKACT0 = 0x1
- // .. ==> 0XF8000150[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. CLKACT1 = 0x0
- // .. ==> 0XF8000150[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000150[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR = 0x14
- // .. ==> 0XF8000150[13:8] = 0x00000014U
- // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
- // ..
- EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U),
- // .. CLKACT0 = 0x0
- // .. ==> 0XF8000154[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. CLKACT1 = 0x1
- // .. ==> 0XF8000154[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000154[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR = 0x14
- // .. ==> 0XF8000154[13:8] = 0x00000014U
- // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
- // ..
- EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U),
- // .. CLKACT = 0x1
- // .. ==> 0XF8000168[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000168[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR = 0x5
- // .. ==> 0XF8000168[13:8] = 0x00000005U
- // .. ==> MASK : 0x00003F00U VAL : 0x00000500U
- // ..
- EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000170[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR0 = 0x14
- // .. ==> 0XF8000170[13:8] = 0x00000014U
- // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
- // .. DIVISOR1 = 0x1
- // .. ==> 0XF8000170[25:20] = 0x00000001U
- // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
- // ..
- EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00101400U),
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000180[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR0 = 0x14
- // .. ==> 0XF8000180[13:8] = 0x00000014U
- // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
- // .. DIVISOR1 = 0x1
- // .. ==> 0XF8000180[25:20] = 0x00000001U
- // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
- // ..
- EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00101400U),
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000190[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR0 = 0x14
- // .. ==> 0XF8000190[13:8] = 0x00000014U
- // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
- // .. DIVISOR1 = 0x1
- // .. ==> 0XF8000190[25:20] = 0x00000001U
- // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
- // ..
- EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101400U),
- // .. SRCSEL = 0x0
- // .. ==> 0XF80001A0[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR0 = 0x14
- // .. ==> 0XF80001A0[13:8] = 0x00000014U
- // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
- // .. DIVISOR1 = 0x1
- // .. ==> 0XF80001A0[25:20] = 0x00000001U
- // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
- // ..
- EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U),
- // .. CLK_621_TRUE = 0x1
- // .. ==> 0XF80001C4[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // ..
- EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
- // .. DMA_CPU_2XCLKACT = 0x1
- // .. ==> 0XF800012C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. USB0_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. USB1_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[3:3] = 0x00000001U
- // .. ==> MASK : 0x00000008U VAL : 0x00000008U
- // .. GEM0_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[6:6] = 0x00000001U
- // .. ==> MASK : 0x00000040U VAL : 0x00000040U
- // .. GEM1_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. SDI0_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[10:10] = 0x00000001U
- // .. ==> MASK : 0x00000400U VAL : 0x00000400U
- // .. SDI1_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. SPI0_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[14:14] = 0x00000000U
- // .. ==> MASK : 0x00004000U VAL : 0x00000000U
- // .. SPI1_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[15:15] = 0x00000000U
- // .. ==> MASK : 0x00008000U VAL : 0x00000000U
- // .. CAN0_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[16:16] = 0x00000000U
- // .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. CAN1_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[17:17] = 0x00000000U
- // .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. I2C0_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[18:18] = 0x00000001U
- // .. ==> MASK : 0x00040000U VAL : 0x00040000U
- // .. I2C1_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[19:19] = 0x00000001U
- // .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // .. UART0_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[20:20] = 0x00000000U
- // .. ==> MASK : 0x00100000U VAL : 0x00000000U
- // .. UART1_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[21:21] = 0x00000001U
- // .. ==> MASK : 0x00200000U VAL : 0x00200000U
- // .. GPIO_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[22:22] = 0x00000001U
- // .. ==> MASK : 0x00400000U VAL : 0x00400000U
- // .. LQSPI_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[23:23] = 0x00000001U
- // .. ==> MASK : 0x00800000U VAL : 0x00800000U
- // .. SMC_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[24:24] = 0x00000001U
- // .. ==> MASK : 0x01000000U VAL : 0x01000000U
- // ..
- EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC044DU),
- // .. FINISH: CLOCK CONTROL SLCR REGISTERS
- // .. START: THIS SHOULD BE BLANK
- // .. FINISH: THIS SHOULD BE BLANK
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_ddr_init_data_1_0[] = {
- // START: top
- // .. START: DDR INITIALIZATION
- // .. .. START: LOCK DDR
- // .. .. reg_ddrc_soft_rstb = 0
- // .. .. ==> 0XF8006000[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_powerdown_en = 0x0
- // .. .. ==> 0XF8006000[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_ddrc_data_bus_width = 0x0
- // .. .. ==> 0XF8006000[3:2] = 0x00000000U
- // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U
- // .. .. reg_ddrc_burst8_refresh = 0x0
- // .. .. ==> 0XF8006000[6:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U
- // .. .. reg_ddrc_rdwr_idle_gap = 0x1
- // .. .. ==> 0XF8006000[13:7] = 0x00000001U
- // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U
- // .. .. reg_ddrc_dis_rd_bypass = 0x0
- // .. .. ==> 0XF8006000[14:14] = 0x00000000U
- // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_act_bypass = 0x0
- // .. .. ==> 0XF8006000[15:15] = 0x00000000U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_auto_refresh = 0x0
- // .. .. ==> 0XF8006000[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
- // .. .. FINISH: LOCK DDR
- // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81
- // .. .. ==> 0XF8006004[11:0] = 0x00000081U
- // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U
- // .. .. reg_ddrc_active_ranks = 0x1
- // .. .. ==> 0XF8006004[13:12] = 0x00000001U
- // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U
- // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
- // .. .. ==> 0XF8006004[18:14] = 0x00000000U
- // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U
- // .. .. reg_ddrc_wr_odt_block = 0x1
- // .. .. ==> 0XF8006004[20:19] = 0x00000001U
- // .. .. ==> MASK : 0x00180000U VAL : 0x00080000U
- // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0
- // .. .. ==> 0XF8006004[21:21] = 0x00000000U
- // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0
- // .. .. ==> 0XF8006004[26:22] = 0x00000000U
- // .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_open_bank = 0x0
- // .. .. ==> 0XF8006004[27:27] = 0x00000000U
- // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_4bank_ram = 0x0
- // .. .. ==> 0XF8006004[28:28] = 0x00000000U
- // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U),
- // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
- // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
- // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU
- // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
- // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
- // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U
- // .. .. reg_ddrc_hpr_xact_run_length = 0xf
- // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
- // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U
- // .. ..
- EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
- // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
- // .. .. ==> 0XF800600C[10:0] = 0x00000001U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U
- // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
- // .. .. ==> 0XF800600C[21:11] = 0x00000002U
- // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U
- // .. .. reg_ddrc_lpr_xact_run_length = 0x8
- // .. .. ==> 0XF800600C[25:22] = 0x00000008U
- // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U
- // .. ..
- EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
- // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
- // .. .. ==> 0XF8006010[10:0] = 0x00000001U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U
- // .. .. reg_ddrc_w_xact_run_length = 0x8
- // .. .. ==> 0XF8006010[14:11] = 0x00000008U
- // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U
- // .. .. reg_ddrc_w_max_starve_x32 = 0x2
- // .. .. ==> 0XF8006010[25:15] = 0x00000002U
- // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U
- // .. ..
- EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
- // .. .. reg_ddrc_t_rc = 0x1b
- // .. .. ==> 0XF8006014[5:0] = 0x0000001BU
- // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001BU
- // .. .. reg_ddrc_t_rfc_min = 0x56
- // .. .. ==> 0XF8006014[13:6] = 0x00000056U
- // .. .. ==> MASK : 0x00003FC0U VAL : 0x00001580U
- // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
- // .. .. ==> 0XF8006014[20:14] = 0x00000010U
- // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U
- // .. ..
- EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004159BU),
- // .. .. reg_ddrc_wr2pre = 0x12
- // .. .. ==> 0XF8006018[4:0] = 0x00000012U
- // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U
- // .. .. reg_ddrc_powerdown_to_x32 = 0x6
- // .. .. ==> 0XF8006018[9:5] = 0x00000006U
- // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U
- // .. .. reg_ddrc_t_faw = 0x10
- // .. .. ==> 0XF8006018[15:10] = 0x00000010U
- // .. .. ==> MASK : 0x0000FC00U VAL : 0x00004000U
- // .. .. reg_ddrc_t_ras_max = 0x24
- // .. .. ==> 0XF8006018[21:16] = 0x00000024U
- // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U
- // .. .. reg_ddrc_t_ras_min = 0x14
- // .. .. ==> 0XF8006018[26:22] = 0x00000014U
- // .. .. ==> MASK : 0x07C00000U VAL : 0x05000000U
- // .. .. reg_ddrc_t_cke = 0x4
- // .. .. ==> 0XF8006018[31:28] = 0x00000004U
- // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x452440D2U),
- // .. .. reg_ddrc_write_latency = 0x5
- // .. .. ==> 0XF800601C[4:0] = 0x00000005U
- // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U
- // .. .. reg_ddrc_rd2wr = 0x7
- // .. .. ==> 0XF800601C[9:5] = 0x00000007U
- // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U
- // .. .. reg_ddrc_wr2rd = 0xe
- // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
- // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U
- // .. .. reg_ddrc_t_xp = 0x4
- // .. .. ==> 0XF800601C[19:15] = 0x00000004U
- // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U
- // .. .. reg_ddrc_pad_pd = 0x0
- // .. .. ==> 0XF800601C[22:20] = 0x00000000U
- // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U
- // .. .. reg_ddrc_rd2pre = 0x4
- // .. .. ==> 0XF800601C[27:23] = 0x00000004U
- // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U
- // .. .. reg_ddrc_t_rcd = 0x7
- // .. .. ==> 0XF800601C[31:28] = 0x00000007U
- // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U
- // .. ..
- EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
- // .. .. reg_ddrc_t_ccd = 0x4
- // .. .. ==> 0XF8006020[4:2] = 0x00000004U
- // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U
- // .. .. reg_ddrc_t_rrd = 0x4
- // .. .. ==> 0XF8006020[7:5] = 0x00000004U
- // .. .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. .. reg_ddrc_refresh_margin = 0x2
- // .. .. ==> 0XF8006020[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. reg_ddrc_t_rp = 0x7
- // .. .. ==> 0XF8006020[15:12] = 0x00000007U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U
- // .. .. reg_ddrc_refresh_to_x32 = 0x8
- // .. .. ==> 0XF8006020[20:16] = 0x00000008U
- // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U
- // .. .. reg_ddrc_sdram = 0x1
- // .. .. ==> 0XF8006020[21:21] = 0x00000001U
- // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U
- // .. .. reg_ddrc_mobile = 0x0
- // .. .. ==> 0XF8006020[22:22] = 0x00000000U
- // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U
- // .. .. reg_ddrc_clock_stop_en = 0x0
- // .. .. ==> 0XF8006020[23:23] = 0x00000000U
- // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U
- // .. .. reg_ddrc_read_latency = 0x7
- // .. .. ==> 0XF8006020[28:24] = 0x00000007U
- // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U
- // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
- // .. .. ==> 0XF8006020[29:29] = 0x00000001U
- // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U
- // .. .. reg_ddrc_dis_pad_pd = 0x0
- // .. .. ==> 0XF8006020[30:30] = 0x00000000U
- // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U
- // .. .. reg_ddrc_loopback = 0x0
- // .. .. ==> 0XF8006020[31:31] = 0x00000000U
- // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x27287290U),
- // .. .. reg_ddrc_en_2t_timing_mode = 0x0
- // .. .. ==> 0XF8006024[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_prefer_write = 0x0
- // .. .. ==> 0XF8006024[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_ddrc_max_rank_rd = 0xf
- // .. .. ==> 0XF8006024[5:2] = 0x0000000FU
- // .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU
- // .. .. reg_ddrc_mr_wr = 0x0
- // .. .. ==> 0XF8006024[6:6] = 0x00000000U
- // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_addr = 0x0
- // .. .. ==> 0XF8006024[8:7] = 0x00000000U
- // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_data = 0x0
- // .. .. ==> 0XF8006024[24:9] = 0x00000000U
- // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U
- // .. .. ddrc_reg_mr_wr_busy = 0x0
- // .. .. ==> 0XF8006024[25:25] = 0x00000000U
- // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_type = 0x0
- // .. .. ==> 0XF8006024[26:26] = 0x00000000U
- // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_rdata_valid = 0x0
- // .. .. ==> 0XF8006024[27:27] = 0x00000000U
- // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU),
- // .. .. reg_ddrc_final_wait_x32 = 0x7
- // .. .. ==> 0XF8006028[6:0] = 0x00000007U
- // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U
- // .. .. reg_ddrc_pre_ocd_x32 = 0x0
- // .. .. ==> 0XF8006028[10:7] = 0x00000000U
- // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U
- // .. .. reg_ddrc_t_mrd = 0x4
- // .. .. ==> 0XF8006028[13:11] = 0x00000004U
- // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U
- // .. ..
- EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
- // .. .. reg_ddrc_emr2 = 0x8
- // .. .. ==> 0XF800602C[15:0] = 0x00000008U
- // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U
- // .. .. reg_ddrc_emr3 = 0x0
- // .. .. ==> 0XF800602C[31:16] = 0x00000000U
- // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
- // .. .. reg_ddrc_mr = 0x930
- // .. .. ==> 0XF8006030[15:0] = 0x00000930U
- // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U
- // .. .. reg_ddrc_emr = 0x4
- // .. .. ==> 0XF8006030[31:16] = 0x00000004U
- // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U
- // .. ..
- EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
- // .. .. reg_ddrc_burst_rdwr = 0x4
- // .. .. ==> 0XF8006034[3:0] = 0x00000004U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U
- // .. .. reg_ddrc_pre_cke_x1024 = 0x105
- // .. .. ==> 0XF8006034[13:4] = 0x00000105U
- // .. .. ==> MASK : 0x00003FF0U VAL : 0x00001050U
- // .. .. reg_ddrc_post_cke_x1024 = 0x1
- // .. .. ==> 0XF8006034[25:16] = 0x00000001U
- // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U
- // .. .. reg_ddrc_burstchop = 0x0
- // .. .. ==> 0XF8006034[28:28] = 0x00000000U
- // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U),
- // .. .. reg_ddrc_force_low_pri_n = 0x0
- // .. .. ==> 0XF8006038[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_dq = 0x0
- // .. .. ==> 0XF8006038[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_debug_mode = 0x0
- // .. .. ==> 0XF8006038[6:6] = 0x00000000U
- // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U
- // .. .. reg_phy_wr_level_start = 0x0
- // .. .. ==> 0XF8006038[7:7] = 0x00000000U
- // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. .. reg_phy_rd_level_start = 0x0
- // .. .. ==> 0XF8006038[8:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. .. reg_phy_dq0_wait_t = 0x0
- // .. .. ==> 0XF8006038[12:9] = 0x00000000U
- // .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U),
- // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
- // .. .. ==> 0XF800603C[3:0] = 0x00000007U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U
- // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
- // .. .. ==> 0XF800603C[7:4] = 0x00000007U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U
- // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
- // .. .. ==> 0XF800603C[11:8] = 0x00000007U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U
- // .. .. reg_ddrc_addrmap_col_b5 = 0x0
- // .. .. ==> 0XF800603C[15:12] = 0x00000000U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b6 = 0x0
- // .. .. ==> 0XF800603C[19:16] = 0x00000000U
- // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
- // .. .. reg_ddrc_addrmap_col_b2 = 0x0
- // .. .. ==> 0XF8006040[3:0] = 0x00000000U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b3 = 0x0
- // .. .. ==> 0XF8006040[7:4] = 0x00000000U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b4 = 0x0
- // .. .. ==> 0XF8006040[11:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b7 = 0x0
- // .. .. ==> 0XF8006040[15:12] = 0x00000000U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b8 = 0x0
- // .. .. ==> 0XF8006040[19:16] = 0x00000000U
- // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b9 = 0xf
- // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
- // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U
- // .. .. reg_ddrc_addrmap_col_b10 = 0xf
- // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
- // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U
- // .. .. reg_ddrc_addrmap_col_b11 = 0xf
- // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
- // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
- // .. .. reg_ddrc_addrmap_row_b0 = 0x6
- // .. .. ==> 0XF8006044[3:0] = 0x00000006U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U
- // .. .. reg_ddrc_addrmap_row_b1 = 0x6
- // .. .. ==> 0XF8006044[7:4] = 0x00000006U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U
- // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
- // .. .. ==> 0XF8006044[11:8] = 0x00000006U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U
- // .. .. reg_ddrc_addrmap_row_b12 = 0x6
- // .. .. ==> 0XF8006044[15:12] = 0x00000006U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U
- // .. .. reg_ddrc_addrmap_row_b13 = 0x6
- // .. .. ==> 0XF8006044[19:16] = 0x00000006U
- // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U
- // .. .. reg_ddrc_addrmap_row_b14 = 0x6
- // .. .. ==> 0XF8006044[23:20] = 0x00000006U
- // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U
- // .. .. reg_ddrc_addrmap_row_b15 = 0xf
- // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
- // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U),
- // .. .. reg_ddrc_rank0_rd_odt = 0x0
- // .. .. ==> 0XF8006048[2:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U
- // .. .. reg_ddrc_rank0_wr_odt = 0x1
- // .. .. ==> 0XF8006048[5:3] = 0x00000001U
- // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U
- // .. .. reg_ddrc_rank1_rd_odt = 0x1
- // .. .. ==> 0XF8006048[8:6] = 0x00000001U
- // .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U
- // .. .. reg_ddrc_rank1_wr_odt = 0x1
- // .. .. ==> 0XF8006048[11:9] = 0x00000001U
- // .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. .. reg_phy_rd_local_odt = 0x0
- // .. .. ==> 0XF8006048[13:12] = 0x00000000U
- // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U
- // .. .. reg_phy_wr_local_odt = 0x3
- // .. .. ==> 0XF8006048[15:14] = 0x00000003U
- // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U
- // .. .. reg_phy_idle_local_odt = 0x3
- // .. .. ==> 0XF8006048[17:16] = 0x00000003U
- // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U
- // .. .. reg_ddrc_rank2_rd_odt = 0x0
- // .. .. ==> 0XF8006048[20:18] = 0x00000000U
- // .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U
- // .. .. reg_ddrc_rank2_wr_odt = 0x0
- // .. .. ==> 0XF8006048[23:21] = 0x00000000U
- // .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U
- // .. .. reg_ddrc_rank3_rd_odt = 0x0
- // .. .. ==> 0XF8006048[26:24] = 0x00000000U
- // .. .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. .. reg_ddrc_rank3_wr_odt = 0x0
- // .. .. ==> 0XF8006048[29:27] = 0x00000000U
- // .. .. ==> MASK : 0x38000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U),
- // .. .. reg_phy_rd_cmd_to_data = 0x0
- // .. .. ==> 0XF8006050[3:0] = 0x00000000U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
- // .. .. reg_phy_wr_cmd_to_data = 0x0
- // .. .. ==> 0XF8006050[7:4] = 0x00000000U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. .. reg_phy_rdc_we_to_re_delay = 0x8
- // .. .. ==> 0XF8006050[11:8] = 0x00000008U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U
- // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
- // .. .. ==> 0XF8006050[15:15] = 0x00000000U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
- // .. .. reg_phy_use_fixed_re = 0x1
- // .. .. ==> 0XF8006050[16:16] = 0x00000001U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U
- // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
- // .. .. ==> 0XF8006050[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
- // .. .. ==> 0XF8006050[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_phy_clk_stall_level = 0x0
- // .. .. ==> 0XF8006050[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
- // .. .. ==> 0XF8006050[27:24] = 0x00000007U
- // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U
- // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
- // .. .. ==> 0XF8006050[31:28] = 0x00000007U
- // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
- // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1
- // .. .. ==> 0XF8006058[7:0] = 0x00000001U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U
- // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1
- // .. .. ==> 0XF8006058[15:8] = 0x00000001U
- // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U
- // .. .. reg_ddrc_dis_dll_calib = 0x0
- // .. .. ==> 0XF8006058[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U),
- // .. .. reg_ddrc_rd_odt_delay = 0x3
- // .. .. ==> 0XF800605C[3:0] = 0x00000003U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U
- // .. .. reg_ddrc_wr_odt_delay = 0x0
- // .. .. ==> 0XF800605C[7:4] = 0x00000000U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. .. reg_ddrc_rd_odt_hold = 0x0
- // .. .. ==> 0XF800605C[11:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U
- // .. .. reg_ddrc_wr_odt_hold = 0x5
- // .. .. ==> 0XF800605C[15:12] = 0x00000005U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U
- // .. ..
- EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
- // .. .. reg_ddrc_pageclose = 0x0
- // .. .. ==> 0XF8006060[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_lpr_num_entries = 0x1f
- // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
- // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU
- // .. .. reg_ddrc_auto_pre_en = 0x0
- // .. .. ==> 0XF8006060[7:7] = 0x00000000U
- // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. .. reg_ddrc_refresh_update_level = 0x0
- // .. .. ==> 0XF8006060[8:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_wc = 0x0
- // .. .. ==> 0XF8006060[9:9] = 0x00000000U
- // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_collision_page_opt = 0x0
- // .. .. ==> 0XF8006060[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_ddrc_selfref_en = 0x0
- // .. .. ==> 0XF8006060[12:12] = 0x00000000U
- // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
- // .. .. reg_ddrc_go2critical_hysteresis = 0x0
- // .. .. ==> 0XF8006064[12:5] = 0x00000000U
- // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U
- // .. .. reg_arb_go2critical_en = 0x1
- // .. .. ==> 0XF8006064[17:17] = 0x00000001U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U
- // .. ..
- EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
- // .. .. reg_ddrc_wrlvl_ww = 0x41
- // .. .. ==> 0XF8006068[7:0] = 0x00000041U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U
- // .. .. reg_ddrc_rdlvl_rr = 0x41
- // .. .. ==> 0XF8006068[15:8] = 0x00000041U
- // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U
- // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
- // .. .. ==> 0XF8006068[25:16] = 0x00000028U
- // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U
- // .. ..
- EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
- // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
- // .. .. ==> 0XF800606C[7:0] = 0x00000010U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U
- // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
- // .. .. ==> 0XF800606C[15:8] = 0x00000016U
- // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U
- // .. ..
- EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
- // .. .. refresh_timer0_start_value_x32 = 0x0
- // .. .. ==> 0XF80060A0[11:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U
- // .. .. refresh_timer1_start_value_x32 = 0x8
- // .. .. ==> 0XF80060A0[23:12] = 0x00000008U
- // .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U
- // .. ..
- EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U),
- // .. .. reg_ddrc_dis_auto_zq = 0x0
- // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_ddr3 = 0x1
- // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. .. reg_ddrc_t_mod = 0x200
- // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
- // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U
- // .. .. reg_ddrc_t_zq_long_nop = 0x200
- // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
- // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U
- // .. .. reg_ddrc_t_zq_short_nop = 0x40
- // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
- // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
- // .. .. t_zq_short_interval_x1024 = 0xcb73
- // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U
- // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U
- // .. .. dram_rstn_x1024 = 0x69
- // .. .. ==> 0XF80060A8[27:20] = 0x00000069U
- // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U
- // .. ..
- EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
- // .. .. deeppowerdown_en = 0x0
- // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. deeppowerdown_to_x1024 = 0xff
- // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
- // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU
- // .. ..
- EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
- // .. .. dfi_wrlvl_max_x1024 = 0xfff
- // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
- // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU
- // .. .. dfi_rdlvl_max_x1024 = 0xfff
- // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
- // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U
- // .. .. ddrc_reg_twrlvl_max_error = 0x0
- // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
- // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U
- // .. .. ddrc_reg_trdlvl_max_error = 0x0
- // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
- // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
- // .. .. reg_ddrc_dfi_wr_level_en = 0x1
- // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
- // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U
- // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
- // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
- // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U
- // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
- // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
- // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
- // .. .. reg_ddrc_2t_delay = 0x0
- // .. .. ==> 0XF80060B4[8:0] = 0x00000000U
- // .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U
- // .. .. reg_ddrc_skip_ocd = 0x1
- // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
- // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U
- // .. .. reg_ddrc_dis_pre_bypass = 0x0
- // .. .. ==> 0XF80060B4[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U),
- // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
- // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
- // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U
- // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
- // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
- // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U
- // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
- // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
- // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U
- // .. ..
- EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
- // .. .. START: RESET ECC ERROR
- // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1
- // .. .. ==> 0XF80060C4[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. Clear_Correctable_DRAM_ECC_error = 1
- // .. .. ==> 0XF80060C4[1:1] = 0x00000001U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. ..
- EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U),
- // .. .. FINISH: RESET ECC ERROR
- // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
- // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
- // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
- // .. .. CORR_ECC_LOG_VALID = 0x0
- // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. ECC_CORRECTED_BIT_NUM = 0x0
- // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
- // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
- // .. .. UNCORR_ECC_LOG_VALID = 0x0
- // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
- // .. .. STAT_NUM_CORR_ERR = 0x0
- // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
- // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U
- // .. .. STAT_NUM_UNCORR_ERR = 0x0
- // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
- // .. .. reg_ddrc_ecc_mode = 0x0
- // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_scrub = 0x1
- // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U
- // .. ..
- EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
- // .. .. reg_phy_dif_on = 0x0
- // .. .. ==> 0XF8006114[3:0] = 0x00000000U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
- // .. .. reg_phy_dif_off = 0x0
- // .. .. ==> 0XF8006114[7:4] = 0x00000000U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
- // .. .. reg_phy_data_slice_in_use = 0x1
- // .. .. ==> 0XF8006118[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_phy_rdlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006118[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_inc_mode = 0x0
- // .. .. ==> 0XF8006118[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_wrlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006118[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_tx = 0x0
- // .. .. ==> 0XF8006118[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_rx = 0x0
- // .. .. ==> 0XF8006118[5:5] = 0x00000000U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. .. reg_phy_bist_shift_dq = 0x0
- // .. .. ==> 0XF8006118[14:6] = 0x00000000U
- // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. .. reg_phy_bist_err_clr = 0x0
- // .. .. ==> 0XF8006118[23:15] = 0x00000000U
- // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. .. reg_phy_dq_offset = 0x40
- // .. .. ==> 0XF8006118[30:24] = 0x00000040U
- // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U),
- // .. .. reg_phy_data_slice_in_use = 0x1
- // .. .. ==> 0XF800611C[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_phy_rdlvl_inc_mode = 0x0
- // .. .. ==> 0XF800611C[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_inc_mode = 0x0
- // .. .. ==> 0XF800611C[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_wrlvl_inc_mode = 0x0
- // .. .. ==> 0XF800611C[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_tx = 0x0
- // .. .. ==> 0XF800611C[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_rx = 0x0
- // .. .. ==> 0XF800611C[5:5] = 0x00000000U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. .. reg_phy_bist_shift_dq = 0x0
- // .. .. ==> 0XF800611C[14:6] = 0x00000000U
- // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. .. reg_phy_bist_err_clr = 0x0
- // .. .. ==> 0XF800611C[23:15] = 0x00000000U
- // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. .. reg_phy_dq_offset = 0x40
- // .. .. ==> 0XF800611C[30:24] = 0x00000040U
- // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U),
- // .. .. reg_phy_data_slice_in_use = 0x1
- // .. .. ==> 0XF8006120[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_phy_rdlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006120[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_inc_mode = 0x0
- // .. .. ==> 0XF8006120[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_wrlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006120[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_tx = 0x0
- // .. .. ==> 0XF8006120[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_rx = 0x0
- // .. .. ==> 0XF8006120[5:5] = 0x00000000U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. .. reg_phy_bist_shift_dq = 0x0
- // .. .. ==> 0XF8006120[14:6] = 0x00000000U
- // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. .. reg_phy_bist_err_clr = 0x0
- // .. .. ==> 0XF8006120[23:15] = 0x00000000U
- // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. .. reg_phy_dq_offset = 0x40
- // .. .. ==> 0XF8006120[30:24] = 0x00000040U
- // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U),
- // .. .. reg_phy_data_slice_in_use = 0x1
- // .. .. ==> 0XF8006124[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_phy_rdlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006124[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_inc_mode = 0x0
- // .. .. ==> 0XF8006124[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_wrlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006124[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_tx = 0x0
- // .. .. ==> 0XF8006124[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_rx = 0x0
- // .. .. ==> 0XF8006124[5:5] = 0x00000000U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. .. reg_phy_bist_shift_dq = 0x0
- // .. .. ==> 0XF8006124[14:6] = 0x00000000U
- // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. .. reg_phy_bist_err_clr = 0x0
- // .. .. ==> 0XF8006124[23:15] = 0x00000000U
- // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. .. reg_phy_dq_offset = 0x40
- // .. .. ==> 0XF8006124[30:24] = 0x00000040U
- // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U),
- // .. .. reg_phy_wrlvl_init_ratio = 0x1e
- // .. .. ==> 0XF800612C[9:0] = 0x0000001EU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x0000001EU
- // .. .. reg_phy_gatelvl_init_ratio = 0xee
- // .. .. ==> 0XF800612C[19:10] = 0x000000EEU
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x0003B800U
- // .. ..
- EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0003B81EU),
- // .. .. reg_phy_wrlvl_init_ratio = 0x25
- // .. .. ==> 0XF8006130[9:0] = 0x00000025U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000025U
- // .. .. reg_phy_gatelvl_init_ratio = 0x10d
- // .. .. ==> 0XF8006130[19:10] = 0x0000010DU
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x00043400U
- // .. ..
- EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00043425U),
- // .. .. reg_phy_wrlvl_init_ratio = 0x19
- // .. .. ==> 0XF8006134[9:0] = 0x00000019U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000019U
- // .. .. reg_phy_gatelvl_init_ratio = 0xf3
- // .. .. ==> 0XF8006134[19:10] = 0x000000F3U
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x0003CC00U
- // .. ..
- EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0003CC19U),
- // .. .. reg_phy_wrlvl_init_ratio = 0x2a
- // .. .. ==> 0XF8006138[9:0] = 0x0000002AU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x0000002AU
- // .. .. reg_phy_gatelvl_init_ratio = 0x109
- // .. .. ==> 0XF8006138[19:10] = 0x00000109U
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x00042400U
- // .. ..
- EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0004242AU),
- // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. .. ==> 0XF8006140[9:0] = 0x00000035U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. .. reg_phy_rd_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006140[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006140[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
- // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. .. ==> 0XF8006144[9:0] = 0x00000035U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. .. reg_phy_rd_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006144[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006144[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
- // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. .. ==> 0XF8006148[9:0] = 0x00000035U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. .. reg_phy_rd_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006148[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006148[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
- // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. .. ==> 0XF800614C[9:0] = 0x00000035U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. .. reg_phy_rd_dqs_slave_force = 0x0
- // .. .. ==> 0XF800614C[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. .. ==> 0XF800614C[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
- // .. .. reg_phy_wr_dqs_slave_ratio = 0x9e
- // .. .. ==> 0XF8006154[9:0] = 0x0000009EU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x0000009EU
- // .. .. reg_phy_wr_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006154[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006154[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x0000009EU),
- // .. .. reg_phy_wr_dqs_slave_ratio = 0xa5
- // .. .. ==> 0XF8006158[9:0] = 0x000000A5U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000000A5U
- // .. .. reg_phy_wr_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006158[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006158[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x000000A5U),
- // .. .. reg_phy_wr_dqs_slave_ratio = 0x99
- // .. .. ==> 0XF800615C[9:0] = 0x00000099U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000099U
- // .. .. reg_phy_wr_dqs_slave_force = 0x0
- // .. .. ==> 0XF800615C[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. .. ==> 0XF800615C[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000099U),
- // .. .. reg_phy_wr_dqs_slave_ratio = 0xaa
- // .. .. ==> 0XF8006160[9:0] = 0x000000AAU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000000AAU
- // .. .. reg_phy_wr_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006160[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006160[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x000000AAU),
- // .. .. reg_phy_fifo_we_slave_ratio = 0x143
- // .. .. ==> 0XF8006168[10:0] = 0x00000143U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x00000143U
- // .. .. reg_phy_fifo_we_in_force = 0x0
- // .. .. ==> 0XF8006168[11:11] = 0x00000000U
- // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. .. reg_phy_fifo_we_in_delay = 0x0
- // .. .. ==> 0XF8006168[20:12] = 0x00000000U
- // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000143U),
- // .. .. reg_phy_fifo_we_slave_ratio = 0x162
- // .. .. ==> 0XF800616C[10:0] = 0x00000162U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x00000162U
- // .. .. reg_phy_fifo_we_in_force = 0x0
- // .. .. ==> 0XF800616C[11:11] = 0x00000000U
- // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. .. reg_phy_fifo_we_in_delay = 0x0
- // .. .. ==> 0XF800616C[20:12] = 0x00000000U
- // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x00000162U),
- // .. .. reg_phy_fifo_we_slave_ratio = 0x148
- // .. .. ==> 0XF8006170[10:0] = 0x00000148U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x00000148U
- // .. .. reg_phy_fifo_we_in_force = 0x0
- // .. .. ==> 0XF8006170[11:11] = 0x00000000U
- // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. .. reg_phy_fifo_we_in_delay = 0x0
- // .. .. ==> 0XF8006170[20:12] = 0x00000000U
- // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000148U),
- // .. .. reg_phy_fifo_we_slave_ratio = 0x15e
- // .. .. ==> 0XF8006174[10:0] = 0x0000015EU
- // .. .. ==> MASK : 0x000007FFU VAL : 0x0000015EU
- // .. .. reg_phy_fifo_we_in_force = 0x0
- // .. .. ==> 0XF8006174[11:11] = 0x00000000U
- // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. .. reg_phy_fifo_we_in_delay = 0x0
- // .. .. ==> 0XF8006174[20:12] = 0x00000000U
- // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x0000015EU),
- // .. .. reg_phy_wr_data_slave_ratio = 0xde
- // .. .. ==> 0XF800617C[9:0] = 0x000000DEU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000000DEU
- // .. .. reg_phy_wr_data_slave_force = 0x0
- // .. .. ==> 0XF800617C[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_data_slave_delay = 0x0
- // .. .. ==> 0XF800617C[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000DEU),
- // .. .. reg_phy_wr_data_slave_ratio = 0xe5
- // .. .. ==> 0XF8006180[9:0] = 0x000000E5U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000000E5U
- // .. .. reg_phy_wr_data_slave_force = 0x0
- // .. .. ==> 0XF8006180[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_data_slave_delay = 0x0
- // .. .. ==> 0XF8006180[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000E5U),
- // .. .. reg_phy_wr_data_slave_ratio = 0xd9
- // .. .. ==> 0XF8006184[9:0] = 0x000000D9U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000000D9U
- // .. .. reg_phy_wr_data_slave_force = 0x0
- // .. .. ==> 0XF8006184[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_data_slave_delay = 0x0
- // .. .. ==> 0XF8006184[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000D9U),
- // .. .. reg_phy_wr_data_slave_ratio = 0xea
- // .. .. ==> 0XF8006188[9:0] = 0x000000EAU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000000EAU
- // .. .. reg_phy_wr_data_slave_force = 0x0
- // .. .. ==> 0XF8006188[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_data_slave_delay = 0x0
- // .. .. ==> 0XF8006188[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000EAU),
- // .. .. reg_phy_loopback = 0x0
- // .. .. ==> 0XF8006190[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_phy_bl2 = 0x0
- // .. .. ==> 0XF8006190[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_at_spd_atpg = 0x0
- // .. .. ==> 0XF8006190[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_bist_enable = 0x0
- // .. .. ==> 0XF8006190[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_bist_force_err = 0x0
- // .. .. ==> 0XF8006190[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. reg_phy_bist_mode = 0x0
- // .. .. ==> 0XF8006190[6:5] = 0x00000000U
- // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. .. reg_phy_invert_clkout = 0x1
- // .. .. ==> 0XF8006190[7:7] = 0x00000001U
- // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0
- // .. .. ==> 0XF8006190[8:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. .. reg_phy_sel_logic = 0x0
- // .. .. ==> 0XF8006190[9:9] = 0x00000000U
- // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U
- // .. .. reg_phy_ctrl_slave_ratio = 0x100
- // .. .. ==> 0XF8006190[19:10] = 0x00000100U
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U
- // .. .. reg_phy_ctrl_slave_force = 0x0
- // .. .. ==> 0XF8006190[20:20] = 0x00000000U
- // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U
- // .. .. reg_phy_ctrl_slave_delay = 0x0
- // .. .. ==> 0XF8006190[27:21] = 0x00000000U
- // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U
- // .. .. reg_phy_use_rank0_delays = 0x1
- // .. .. ==> 0XF8006190[28:28] = 0x00000001U
- // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
- // .. .. reg_phy_lpddr = 0x0
- // .. .. ==> 0XF8006190[29:29] = 0x00000000U
- // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U
- // .. .. reg_phy_cmd_latency = 0x0
- // .. .. ==> 0XF8006190[30:30] = 0x00000000U
- // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U
- // .. .. reg_phy_int_lpbk = 0x0
- // .. .. ==> 0XF8006190[31:31] = 0x00000000U
- // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U),
- // .. .. reg_phy_wr_rl_delay = 0x2
- // .. .. ==> 0XF8006194[4:0] = 0x00000002U
- // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U
- // .. .. reg_phy_rd_rl_delay = 0x4
- // .. .. ==> 0XF8006194[9:5] = 0x00000004U
- // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U
- // .. .. reg_phy_dll_lock_diff = 0xf
- // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
- // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U
- // .. .. reg_phy_use_wr_level = 0x1
- // .. .. ==> 0XF8006194[14:14] = 0x00000001U
- // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U
- // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
- // .. .. ==> 0XF8006194[15:15] = 0x00000001U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U
- // .. .. reg_phy_use_rd_data_eye_level = 0x1
- // .. .. ==> 0XF8006194[16:16] = 0x00000001U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U
- // .. .. reg_phy_dis_calib_rst = 0x0
- // .. .. ==> 0XF8006194[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_phy_ctrl_slave_delay = 0x0
- // .. .. ==> 0XF8006194[19:18] = 0x00000000U
- // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
- // .. .. reg_arb_page_addr_mask = 0x0
- // .. .. ==> 0XF8006204[31:0] = 0x00000000U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
- // .. .. reg_arb_pri_wr_portn = 0x3ff
- // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_wr_portn = 0x0
- // .. .. ==> 0XF8006208[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. .. ==> 0XF8006208[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. .. ==> 0XF8006208[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_dis_rmw_portn = 0x1
- // .. .. ==> 0XF8006208[19:19] = 0x00000001U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // .. ..
- EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU),
- // .. .. reg_arb_pri_wr_portn = 0x3ff
- // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_wr_portn = 0x0
- // .. .. ==> 0XF800620C[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. .. ==> 0XF800620C[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. .. ==> 0XF800620C[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_dis_rmw_portn = 0x1
- // .. .. ==> 0XF800620C[19:19] = 0x00000001U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // .. ..
- EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU),
- // .. .. reg_arb_pri_wr_portn = 0x3ff
- // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_wr_portn = 0x0
- // .. .. ==> 0XF8006210[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. .. ==> 0XF8006210[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. .. ==> 0XF8006210[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_dis_rmw_portn = 0x1
- // .. .. ==> 0XF8006210[19:19] = 0x00000001U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // .. ..
- EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU),
- // .. .. reg_arb_pri_wr_portn = 0x3ff
- // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_wr_portn = 0x0
- // .. .. ==> 0XF8006214[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. .. ==> 0XF8006214[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. .. ==> 0XF8006214[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_dis_rmw_portn = 0x1
- // .. .. ==> 0XF8006214[19:19] = 0x00000001U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // .. ..
- EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU),
- // .. .. reg_arb_pri_rd_portn = 0x3ff
- // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_rd_portn = 0x0
- // .. .. ==> 0XF8006218[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. .. ==> 0XF8006218[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. .. ==> 0XF8006218[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_set_hpr_rd_portn = 0x0
- // .. .. ==> 0XF8006218[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
- // .. .. reg_arb_pri_rd_portn = 0x3ff
- // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_rd_portn = 0x0
- // .. .. ==> 0XF800621C[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. .. ==> 0XF800621C[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. .. ==> 0XF800621C[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_set_hpr_rd_portn = 0x0
- // .. .. ==> 0XF800621C[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
- // .. .. reg_arb_pri_rd_portn = 0x3ff
- // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_rd_portn = 0x0
- // .. .. ==> 0XF8006220[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. .. ==> 0XF8006220[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. .. ==> 0XF8006220[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_set_hpr_rd_portn = 0x0
- // .. .. ==> 0XF8006220[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
- // .. .. reg_arb_pri_rd_portn = 0x3ff
- // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_rd_portn = 0x0
- // .. .. ==> 0XF8006224[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. .. ==> 0XF8006224[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. .. ==> 0XF8006224[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_set_hpr_rd_portn = 0x0
- // .. .. ==> 0XF8006224[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
- // .. .. reg_ddrc_lpddr2 = 0x0
- // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_per_bank_refresh = 0x0
- // .. .. ==> 0XF80062A8[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_ddrc_derate_enable = 0x0
- // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_ddrc_mr4_margin = 0x0
- // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U),
- // .. .. reg_ddrc_mr4_read_interval = 0x0
- // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
- // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
- // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U
- // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
- // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
- // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U
- // .. .. reg_ddrc_t_mrw = 0x5
- // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
- // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U
- // .. ..
- EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
- // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8
- // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U
- // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
- // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
- // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U
- // .. ..
- EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
- // .. .. START: POLL ON DCI STATUS
- // .. .. DONE = 1
- // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
- // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // .. ..
- EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
- // .. .. FINISH: POLL ON DCI STATUS
- // .. .. START: UNLOCK DDR
- // .. .. reg_ddrc_soft_rstb = 0x1
- // .. .. ==> 0XF8006000[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_ddrc_powerdown_en = 0x0
- // .. .. ==> 0XF8006000[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_ddrc_data_bus_width = 0x0
- // .. .. ==> 0XF8006000[3:2] = 0x00000000U
- // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U
- // .. .. reg_ddrc_burst8_refresh = 0x0
- // .. .. ==> 0XF8006000[6:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U
- // .. .. reg_ddrc_rdwr_idle_gap = 1
- // .. .. ==> 0XF8006000[13:7] = 0x00000001U
- // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U
- // .. .. reg_ddrc_dis_rd_bypass = 0x0
- // .. .. ==> 0XF8006000[14:14] = 0x00000000U
- // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_act_bypass = 0x0
- // .. .. ==> 0XF8006000[15:15] = 0x00000000U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_auto_refresh = 0x0
- // .. .. ==> 0XF8006000[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
- // .. .. FINISH: UNLOCK DDR
- // .. .. START: CHECK DDR STATUS
- // .. .. ddrc_reg_operating_mode = 1
- // .. .. ==> 0XF8006054[2:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U
- // .. ..
- EMIT_MASKPOLL(0XF8006054, 0x00000007U),
- // .. .. FINISH: CHECK DDR STATUS
- // .. FINISH: DDR INITIALIZATION
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_mio_init_data_1_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: OCM REMAPPING
- // .. VREF_EN = 0x1
- // .. ==> 0XF8000B00[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. VREF_PULLUP_EN = 0x0
- // .. ==> 0XF8000B00[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. CLK_PULLUP_EN = 0x0
- // .. ==> 0XF8000B00[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. SRSTN_PULLUP_EN = 0x0
- // .. ==> 0XF8000B00[9:9] = 0x00000000U
- // .. ==> MASK : 0x00000200U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B00, 0x00000303U ,0x00000001U),
- // .. FINISH: OCM REMAPPING
- // .. START: DDRIOB SETTINGS
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B40[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x0
- // .. ==> 0XF8000B40[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B40[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x0
- // .. ==> 0XF8000B40[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. DCR_TYPE = 0x0
- // .. ==> 0XF8000B40[6:5] = 0x00000000U
- // .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. IBUF_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B40[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B40[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B40[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B40[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B44[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x0
- // .. ==> 0XF8000B44[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B44[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x0
- // .. ==> 0XF8000B44[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. DCR_TYPE = 0x0
- // .. ==> 0XF8000B44[6:5] = 0x00000000U
- // .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. IBUF_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B44[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B44[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B44[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B44[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B48[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x1
- // .. ==> 0XF8000B48[2:1] = 0x00000001U
- // .. ==> MASK : 0x00000006U VAL : 0x00000002U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B48[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x1
- // .. ==> 0XF8000B48[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. DCR_TYPE = 0x3
- // .. ==> 0XF8000B48[6:5] = 0x00000003U
- // .. ==> MASK : 0x00000060U VAL : 0x00000060U
- // .. IBUF_DISABLE_MODE = 0
- // .. ==> 0XF8000B48[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0
- // .. ==> 0XF8000B48[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B48[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B48[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B4C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x1
- // .. ==> 0XF8000B4C[2:1] = 0x00000001U
- // .. ==> MASK : 0x00000006U VAL : 0x00000002U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B4C[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x1
- // .. ==> 0XF8000B4C[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. DCR_TYPE = 0x3
- // .. ==> 0XF8000B4C[6:5] = 0x00000003U
- // .. ==> MASK : 0x00000060U VAL : 0x00000060U
- // .. IBUF_DISABLE_MODE = 0
- // .. ==> 0XF8000B4C[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0
- // .. ==> 0XF8000B4C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B4C[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B4C[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B50[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x2
- // .. ==> 0XF8000B50[2:1] = 0x00000002U
- // .. ==> MASK : 0x00000006U VAL : 0x00000004U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B50[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x1
- // .. ==> 0XF8000B50[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. DCR_TYPE = 0x3
- // .. ==> 0XF8000B50[6:5] = 0x00000003U
- // .. ==> MASK : 0x00000060U VAL : 0x00000060U
- // .. IBUF_DISABLE_MODE = 0
- // .. ==> 0XF8000B50[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0
- // .. ==> 0XF8000B50[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B50[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B50[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B54[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x2
- // .. ==> 0XF8000B54[2:1] = 0x00000002U
- // .. ==> MASK : 0x00000006U VAL : 0x00000004U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B54[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x1
- // .. ==> 0XF8000B54[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. DCR_TYPE = 0x3
- // .. ==> 0XF8000B54[6:5] = 0x00000003U
- // .. ==> MASK : 0x00000060U VAL : 0x00000060U
- // .. IBUF_DISABLE_MODE = 0
- // .. ==> 0XF8000B54[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0
- // .. ==> 0XF8000B54[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B54[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B54[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B58[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x0
- // .. ==> 0XF8000B58[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B58[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x0
- // .. ==> 0XF8000B58[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. DCR_TYPE = 0x0
- // .. ==> 0XF8000B58[6:5] = 0x00000000U
- // .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. IBUF_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B58[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B58[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B58[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B58[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
- // .. DRIVE_P = 0x1c
- // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
- // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
- // .. DRIVE_N = 0xc
- // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
- // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
- // .. SLEW_P = 0x3
- // .. ==> 0XF8000B5C[18:14] = 0x00000003U
- // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U
- // .. SLEW_N = 0x3
- // .. ==> 0XF8000B5C[23:19] = 0x00000003U
- // .. ==> MASK : 0x00F80000U VAL : 0x00180000U
- // .. GTL = 0x0
- // .. ==> 0XF8000B5C[26:24] = 0x00000000U
- // .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. RTERM = 0x0
- // .. ==> 0XF8000B5C[31:27] = 0x00000000U
- // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
- // .. DRIVE_P = 0x1c
- // .. ==> 0XF8000B60[6:0] = 0x0000001CU
- // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
- // .. DRIVE_N = 0xc
- // .. ==> 0XF8000B60[13:7] = 0x0000000CU
- // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
- // .. SLEW_P = 0x6
- // .. ==> 0XF8000B60[18:14] = 0x00000006U
- // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
- // .. SLEW_N = 0x1f
- // .. ==> 0XF8000B60[23:19] = 0x0000001FU
- // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
- // .. GTL = 0x0
- // .. ==> 0XF8000B60[26:24] = 0x00000000U
- // .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. RTERM = 0x0
- // .. ==> 0XF8000B60[31:27] = 0x00000000U
- // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
- // .. DRIVE_P = 0x1c
- // .. ==> 0XF8000B64[6:0] = 0x0000001CU
- // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
- // .. DRIVE_N = 0xc
- // .. ==> 0XF8000B64[13:7] = 0x0000000CU
- // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
- // .. SLEW_P = 0x6
- // .. ==> 0XF8000B64[18:14] = 0x00000006U
- // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
- // .. SLEW_N = 0x1f
- // .. ==> 0XF8000B64[23:19] = 0x0000001FU
- // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
- // .. GTL = 0x0
- // .. ==> 0XF8000B64[26:24] = 0x00000000U
- // .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. RTERM = 0x0
- // .. ==> 0XF8000B64[31:27] = 0x00000000U
- // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
- // .. DRIVE_P = 0x1c
- // .. ==> 0XF8000B68[6:0] = 0x0000001CU
- // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
- // .. DRIVE_N = 0xc
- // .. ==> 0XF8000B68[13:7] = 0x0000000CU
- // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
- // .. SLEW_P = 0x6
- // .. ==> 0XF8000B68[18:14] = 0x00000006U
- // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
- // .. SLEW_N = 0x1f
- // .. ==> 0XF8000B68[23:19] = 0x0000001FU
- // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
- // .. GTL = 0x0
- // .. ==> 0XF8000B68[26:24] = 0x00000000U
- // .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. RTERM = 0x0
- // .. ==> 0XF8000B68[31:27] = 0x00000000U
- // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
- // .. VREF_INT_EN = 0x1
- // .. ==> 0XF8000B6C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. VREF_SEL = 0x4
- // .. ==> 0XF8000B6C[4:1] = 0x00000004U
- // .. ==> MASK : 0x0000001EU VAL : 0x00000008U
- // .. VREF_EXT_EN = 0x0
- // .. ==> 0XF8000B6C[6:5] = 0x00000000U
- // .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. VREF_PULLUP_EN = 0x0
- // .. ==> 0XF8000B6C[8:7] = 0x00000000U
- // .. ==> MASK : 0x00000180U VAL : 0x00000000U
- // .. REFIO_EN = 0x1
- // .. ==> 0XF8000B6C[9:9] = 0x00000001U
- // .. ==> MASK : 0x00000200U VAL : 0x00000200U
- // .. REFIO_PULLUP_EN = 0x0
- // .. ==> 0XF8000B6C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DRST_B_PULLUP_EN = 0x0
- // .. ==> 0XF8000B6C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // .. CKE_PULLUP_EN = 0x0
- // .. ==> 0XF8000B6C[14:14] = 0x00000000U
- // .. ==> MASK : 0x00004000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B6C, 0x000073FFU ,0x00000209U),
- // .. .. START: ASSERT RESET
- // .. .. RESET = 1
- // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. VRN_OUT = 0x1
- // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
- // .. ..
- EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U),
- // .. .. FINISH: ASSERT RESET
- // .. .. START: DEASSERT RESET
- // .. .. RESET = 0
- // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. VRN_OUT = 0x1
- // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
- // .. ..
- EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
- // .. .. FINISH: DEASSERT RESET
- // .. .. RESET = 0x1
- // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ENABLE = 0x1
- // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. .. VRP_TRI = 0x0
- // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. VRN_TRI = 0x0
- // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. VRP_OUT = 0x0
- // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. VRN_OUT = 0x1
- // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
- // .. .. NREF_OPT1 = 0x0
- // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
- // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U
- // .. .. NREF_OPT2 = 0x0
- // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U
- // .. .. NREF_OPT4 = 0x1
- // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
- // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U
- // .. .. PREF_OPT1 = 0x0
- // .. .. ==> 0XF8000B70[16:14] = 0x00000000U
- // .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U
- // .. .. PREF_OPT2 = 0x0
- // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
- // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U
- // .. .. UPDATE_CONTROL = 0x0
- // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
- // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U
- // .. .. INIT_COMPLETE = 0x0
- // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
- // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U
- // .. .. TST_CLK = 0x0
- // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
- // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U
- // .. .. TST_HLN = 0x0
- // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
- // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U
- // .. .. TST_HLP = 0x0
- // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
- // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U
- // .. .. TST_RST = 0x0
- // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
- // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
- // .. .. INT_DCI_EN = 0x0
- // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
- // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U),
- // .. FINISH: DDRIOB SETTINGS
- // .. START: MIO PROGRAMMING
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000700[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000700[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000700[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000700[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000700[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000700[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000700[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 1
- // .. ==> 0XF8000700[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000700[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001202U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000704[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000704[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000704[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000704[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000704[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000704[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000704[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 1
- // .. ==> 0XF8000704[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000704[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001202U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000708[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000708[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000708[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000708[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000708[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000708[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000708[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000708[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000708[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000202U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800070C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF800070C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF800070C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800070C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800070C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800070C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF800070C[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF800070C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800070C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000202U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000710[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000710[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000710[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000710[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000710[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000710[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000710[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000710[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000710[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000202U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000714[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000714[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000714[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000714[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000714[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000714[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000714[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000714[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000714[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000202U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000718[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000718[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000718[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000718[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000718[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000718[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000718[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000718[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000718[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000202U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800071C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800071C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF800071C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800071C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800071C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800071C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF800071C[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF800071C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800071C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000200U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000720[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000720[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000720[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000720[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000720[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000720[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000720[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000720[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000720[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000202U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000724[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000724[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000724[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000724[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000724[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000724[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000724[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 1
- // .. ==> 0XF8000724[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000724[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001202U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000728[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000728[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000728[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000728[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000728[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000728[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000728[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 1
- // .. ==> 0XF8000728[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000728[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001202U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800072C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF800072C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF800072C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800072C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800072C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800072C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF800072C[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 1
- // .. ==> 0XF800072C[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800072C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001202U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000730[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000730[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000730[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000730[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000730[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000730[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000730[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 1
- // .. ==> 0XF8000730[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000730[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001202U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000734[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000734[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000734[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000734[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000734[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000734[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000734[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 1
- // .. ==> 0XF8000734[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000734[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001202U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000738[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. Speed = 0
- // .. ==> 0XF8000738[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000738[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 1
- // .. ==> 0XF8000738[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000738[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000738, 0x00003F01U ,0x00001201U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF800073C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. Speed = 0
- // .. ==> 0XF800073C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF800073C[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 1
- // .. ==> 0XF800073C[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800073C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800073C, 0x00003F01U ,0x00001201U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000740[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000740[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000740[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000740[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000740[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000740[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 4
- // .. ==> 0XF8000740[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000740[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 1
- // .. ==> 0XF8000740[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // ..
- EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00002802U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000744[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000744[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000744[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000744[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000744[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000744[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 4
- // .. ==> 0XF8000744[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000744[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 1
- // .. ==> 0XF8000744[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // ..
- EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00002802U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000748[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000748[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000748[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000748[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000748[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000748[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 4
- // .. ==> 0XF8000748[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000748[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 1
- // .. ==> 0XF8000748[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // ..
- EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00002802U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800074C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF800074C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF800074C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800074C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800074C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800074C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 4
- // .. ==> 0XF800074C[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF800074C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 1
- // .. ==> 0XF800074C[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // ..
- EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00002802U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000750[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000750[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000750[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000750[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000750[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000750[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 4
- // .. ==> 0XF8000750[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000750[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 1
- // .. ==> 0XF8000750[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // ..
- EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00002802U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000754[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000754[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000754[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000754[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000754[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000754[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 4
- // .. ==> 0XF8000754[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000754[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 1
- // .. ==> 0XF8000754[13:13] = 0x00000001U
- // .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // ..
- EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00002802U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000758[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF8000758[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000758[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000758[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000758[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000758[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 4
- // .. ==> 0XF8000758[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000758[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000758[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000803U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF800075C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF800075C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF800075C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800075C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800075C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800075C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 4
- // .. ==> 0XF800075C[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF800075C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800075C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000803U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000760[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF8000760[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000760[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000760[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000760[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000760[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 4
- // .. ==> 0XF8000760[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000760[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000760[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000803U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000764[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF8000764[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000764[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000764[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000764[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000764[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 4
- // .. ==> 0XF8000764[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000764[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000764[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000803U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000768[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF8000768[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000768[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000768[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000768[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000768[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 4
- // .. ==> 0XF8000768[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF8000768[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000768[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000803U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF800076C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF800076C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF800076C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800076C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800076C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800076C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 4
- // .. ==> 0XF800076C[11:9] = 0x00000004U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
- // .. PULLUP = 0
- // .. ==> 0XF800076C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800076C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000803U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000770[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000770[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000770[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000770[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000770[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000770[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000770[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000770[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000770[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000774[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF8000774[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000774[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000774[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000774[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000774[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000774[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000774[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000774[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000778[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000778[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000778[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000778[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000778[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000778[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000778[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000778[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000778[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF800077C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF800077C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF800077C[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF800077C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800077C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800077C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF800077C[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF800077C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800077C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000780[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000780[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000780[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000780[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000780[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000780[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000780[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000780[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000780[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000784[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000784[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000784[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000784[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000784[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000784[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000784[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000784[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000784[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000788[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000788[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000788[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000788[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000788[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000788[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000788[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000788[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000788[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800078C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800078C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF800078C[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF800078C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800078C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800078C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF800078C[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF800078C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800078C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000790[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF8000790[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000790[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000790[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000790[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000790[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000790[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000790[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000790[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000794[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000794[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000794[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000794[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000794[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000794[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000794[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000794[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000794[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000798[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000798[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000798[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000798[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000798[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000798[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF8000798[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000798[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000798[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800079C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800079C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF800079C[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF800079C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800079C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800079C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF800079C[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF800079C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800079C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007A0[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007A0[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007A0[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007A0[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007A0[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF80007A0[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007A0[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007A0[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007A0[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000280U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007A4[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007A4[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007A4[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007A4[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007A4[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF80007A4[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007A4[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007A4[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007A4[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000280U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007A8[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007A8[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007A8[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007A8[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007A8[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF80007A8[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007A8[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007A8[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007A8[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000280U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007AC[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007AC[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007AC[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007AC[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007AC[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF80007AC[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007AC[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007AC[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007AC[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000280U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007B0[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007B0[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007B0[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007B0[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007B0[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF80007B0[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007B0[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007B0[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007B0[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000280U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007B4[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007B4[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007B4[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007B4[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007B4[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF80007B4[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007B4[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007B4[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007B4[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000280U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007B8[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007B8[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007B8[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007B8[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF80007B8[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF80007B8[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007B8[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 1
- // .. ==> 0XF80007B8[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007B8[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001200U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007BC[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007BC[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007BC[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007BC[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF80007BC[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF80007BC[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007BC[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 1
- // .. ==> 0XF80007BC[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007BC[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00001200U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007C0[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007C0[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007C0[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007C0[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 7
- // .. ==> 0XF80007C0[7:5] = 0x00000007U
- // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U
- // .. Speed = 0
- // .. ==> 0XF80007C0[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007C0[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007C0[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007C0[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF80007C4[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF80007C4[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007C4[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007C4[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 7
- // .. ==> 0XF80007C4[7:5] = 0x00000007U
- // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U
- // .. Speed = 0
- // .. ==> 0XF80007C4[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007C4[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007C4[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007C4[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007C8[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007C8[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007C8[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007C8[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 2
- // .. ==> 0XF80007C8[7:5] = 0x00000002U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000040U
- // .. Speed = 0
- // .. ==> 0XF80007C8[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007C8[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 1
- // .. ==> 0XF80007C8[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007C8[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001240U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007CC[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007CC[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007CC[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007CC[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 2
- // .. ==> 0XF80007CC[7:5] = 0x00000002U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000040U
- // .. Speed = 0
- // .. ==> 0XF80007CC[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007CC[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 1
- // .. ==> 0XF80007CC[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007CC[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001240U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007D0[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007D0[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007D0[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007D0[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007D0[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF80007D0[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007D0[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007D0[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007D0[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007D4[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007D4[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007D4[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007D4[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007D4[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF80007D4[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007D4[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007D4[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007D4[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U),
- // .. SDIO0_WP_SEL = 15
- // .. ==> 0XF8000830[5:0] = 0x0000000FU
- // .. ==> MASK : 0x0000003FU VAL : 0x0000000FU
- // .. SDIO0_CD_SEL = 14
- // .. ==> 0XF8000830[21:16] = 0x0000000EU
- // .. ==> MASK : 0x003F0000U VAL : 0x000E0000U
- // ..
- EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x000E000FU),
- // .. FINISH: MIO PROGRAMMING
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_peripherals_init_data_1_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
- // .. IBUF_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B48[7:7] = 0x00000001U
- // .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. TERM_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B48[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // ..
- EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
- // .. IBUF_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B4C[7:7] = 0x00000001U
- // .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. TERM_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B4C[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // ..
- EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
- // .. IBUF_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B50[7:7] = 0x00000001U
- // .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. TERM_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B50[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // ..
- EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
- // .. IBUF_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B54[7:7] = 0x00000001U
- // .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. TERM_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B54[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // ..
- EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
- // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // .. START: SRAM/NOR SET OPMODE
- // .. FINISH: SRAM/NOR SET OPMODE
- // .. START: UART REGISTERS
- // .. BDIV = 0x6
- // .. ==> 0XE0001034[7:0] = 0x00000006U
- // .. ==> MASK : 0x000000FFU VAL : 0x00000006U
- // ..
- EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
- // .. CD = 0x3e
- // .. ==> 0XE0001018[15:0] = 0x0000003EU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU
- // ..
- EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
- // .. STPBRK = 0x0
- // .. ==> 0XE0001000[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. STTBRK = 0x0
- // .. ==> 0XE0001000[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. RSTTO = 0x0
- // .. ==> 0XE0001000[6:6] = 0x00000000U
- // .. ==> MASK : 0x00000040U VAL : 0x00000000U
- // .. TXDIS = 0x0
- // .. ==> 0XE0001000[5:5] = 0x00000000U
- // .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. TXEN = 0x1
- // .. ==> 0XE0001000[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. RXDIS = 0x0
- // .. ==> 0XE0001000[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. RXEN = 0x1
- // .. ==> 0XE0001000[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. TXRES = 0x1
- // .. ==> 0XE0001000[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. RXRES = 0x1
- // .. ==> 0XE0001000[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // ..
- EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
- // .. IRMODE = 0x0
- // .. ==> 0XE0001004[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. UCLKEN = 0x0
- // .. ==> 0XE0001004[10:10] = 0x00000000U
- // .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. CHMODE = 0x0
- // .. ==> 0XE0001004[9:8] = 0x00000000U
- // .. ==> MASK : 0x00000300U VAL : 0x00000000U
- // .. NBSTOP = 0x0
- // .. ==> 0XE0001004[7:6] = 0x00000000U
- // .. ==> MASK : 0x000000C0U VAL : 0x00000000U
- // .. PAR = 0x4
- // .. ==> 0XE0001004[5:3] = 0x00000004U
- // .. ==> MASK : 0x00000038U VAL : 0x00000020U
- // .. CHRL = 0x0
- // .. ==> 0XE0001004[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. CLKS = 0x0
- // .. ==> 0XE0001004[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U),
- // .. FINISH: UART REGISTERS
- // .. START: QSPI REGISTERS
- // .. Holdb_dr = 1
- // .. ==> 0XE000D000[19:19] = 0x00000001U
- // .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // ..
- EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
- // .. FINISH: QSPI REGISTERS
- // .. START: PL POWER ON RESET REGISTERS
- // .. PCFG_POR_CNT_4K = 0
- // .. ==> 0XF8007000[29:29] = 0x00000000U
- // .. ==> MASK : 0x20000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
- // .. FINISH: PL POWER ON RESET REGISTERS
- // .. START: SMC TIMING CALCULATION REGISTER UPDATE
- // .. .. START: NAND SET CYCLE
- // .. .. FINISH: NAND SET CYCLE
- // .. .. START: OPMODE
- // .. .. FINISH: OPMODE
- // .. .. START: DIRECT COMMAND
- // .. .. FINISH: DIRECT COMMAND
- // .. .. START: SRAM/NOR CS0 SET CYCLE
- // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
- // .. .. START: DIRECT COMMAND
- // .. .. FINISH: DIRECT COMMAND
- // .. .. START: NOR CS0 BASE ADDRESS
- // .. .. FINISH: NOR CS0 BASE ADDRESS
- // .. .. START: SRAM/NOR CS1 SET CYCLE
- // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
- // .. .. START: DIRECT COMMAND
- // .. .. FINISH: DIRECT COMMAND
- // .. .. START: NOR CS1 BASE ADDRESS
- // .. .. FINISH: NOR CS1 BASE ADDRESS
- // .. .. START: USB RESET
- // .. .. .. START: USB0 RESET
- // .. .. .. .. START: DIR MODE BANK 0
- // .. .. .. .. DIRECTION_0 = 0x80
- // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U
- // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U),
- // .. .. .. .. FINISH: DIR MODE BANK 0
- // .. .. .. .. START: DIR MODE BANK 1
- // .. .. .. .. FINISH: DIR MODE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. MASK_0_LSW = 0xff7f
- // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
- // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U
- // .. .. .. .. DATA_0_LSW = 0x80
- // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
- // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. START: OUTPUT ENABLE BANK 0
- // .. .. .. .. OP_ENABLE_0 = 0x80
- // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U
- // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U),
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
- // .. .. .. .. START: OUTPUT ENABLE BANK 1
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. MASK_0_LSW = 0xff7f
- // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
- // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U
- // .. .. .. .. DATA_0_LSW = 0x0
- // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
- // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U),
- // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. START: ADD 1 MS DELAY
- // .. .. .. ..
- EMIT_MASKDELAY(0XF8F00200, 1),
- // .. .. .. .. FINISH: ADD 1 MS DELAY
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. MASK_0_LSW = 0xff7f
- // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
- // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U
- // .. .. .. .. DATA_0_LSW = 0x80
- // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
- // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: USB0 RESET
- // .. .. .. START: USB1 RESET
- // .. .. .. .. START: DIR MODE BANK 0
- // .. .. .. .. FINISH: DIR MODE BANK 0
- // .. .. .. .. START: DIR MODE BANK 1
- // .. .. .. .. FINISH: DIR MODE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. START: OUTPUT ENABLE BANK 0
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
- // .. .. .. .. START: OUTPUT ENABLE BANK 1
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. START: ADD 1 MS DELAY
- // .. .. .. ..
- EMIT_MASKDELAY(0XF8F00200, 1),
- // .. .. .. .. FINISH: ADD 1 MS DELAY
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: USB1 RESET
- // .. .. FINISH: USB RESET
- // .. .. START: ENET RESET
- // .. .. .. START: ENET0 RESET
- // .. .. .. .. START: DIR MODE BANK 0
- // .. .. .. .. FINISH: DIR MODE BANK 0
- // .. .. .. .. START: DIR MODE BANK 1
- // .. .. .. .. DIRECTION_1 = 0x8000
- // .. .. .. .. ==> 0XE000A244[21:0] = 0x00008000U
- // .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00008000U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x00008000U),
- // .. .. .. .. FINISH: DIR MODE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. MASK_1_LSW = 0x7fff
- // .. .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU
- // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0x7FFF0000U
- // .. .. .. .. DATA_1_LSW = 0x8000
- // .. .. .. .. ==> 0XE000A008[15:0] = 0x00008000U
- // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00008000U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF8000U),
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. START: OUTPUT ENABLE BANK 0
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
- // .. .. .. .. START: OUTPUT ENABLE BANK 1
- // .. .. .. .. OP_ENABLE_1 = 0x8000
- // .. .. .. .. ==> 0XE000A248[21:0] = 0x00008000U
- // .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00008000U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x00008000U),
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. MASK_1_LSW = 0x7fff
- // .. .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU
- // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0x7FFF0000U
- // .. .. .. .. DATA_1_LSW = 0x0
- // .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U
- // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF0000U),
- // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. START: ADD 1 MS DELAY
- // .. .. .. ..
- EMIT_MASKDELAY(0XF8F00200, 1),
- // .. .. .. .. FINISH: ADD 1 MS DELAY
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. MASK_1_LSW = 0x7fff
- // .. .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU
- // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0x7FFF0000U
- // .. .. .. .. DATA_1_LSW = 0x8000
- // .. .. .. .. ==> 0XE000A008[15:0] = 0x00008000U
- // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00008000U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF8000U),
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: ENET0 RESET
- // .. .. .. START: ENET1 RESET
- // .. .. .. .. START: DIR MODE BANK 0
- // .. .. .. .. FINISH: DIR MODE BANK 0
- // .. .. .. .. START: DIR MODE BANK 1
- // .. .. .. .. FINISH: DIR MODE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. START: OUTPUT ENABLE BANK 0
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
- // .. .. .. .. START: OUTPUT ENABLE BANK 1
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. START: ADD 1 MS DELAY
- // .. .. .. ..
- EMIT_MASKDELAY(0XF8F00200, 1),
- // .. .. .. .. FINISH: ADD 1 MS DELAY
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: ENET1 RESET
- // .. .. FINISH: ENET RESET
- // .. .. START: I2C RESET
- // .. .. .. START: I2C0 RESET
- // .. .. .. .. START: DIR MODE GPIO BANK0
- // .. .. .. .. FINISH: DIR MODE GPIO BANK0
- // .. .. .. .. START: DIR MODE GPIO BANK1
- // .. .. .. .. DIRECTION_1 = 0x4000
- // .. .. .. .. ==> 0XE000A244[21:0] = 0x00004000U
- // .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x00004000U),
- // .. .. .. .. FINISH: DIR MODE GPIO BANK1
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. MASK_1_LSW = 0xbfff
- // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
- // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U
- // .. .. .. .. DATA_1_LSW = 0x4000
- // .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U
- // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U),
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. START: OUTPUT ENABLE
- // .. .. .. .. FINISH: OUTPUT ENABLE
- // .. .. .. .. START: OUTPUT ENABLE
- // .. .. .. .. OP_ENABLE_1 = 0x4000
- // .. .. .. .. ==> 0XE000A248[21:0] = 0x00004000U
- // .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x00004000U),
- // .. .. .. .. FINISH: OUTPUT ENABLE
- // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. MASK_1_LSW = 0xbfff
- // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
- // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U
- // .. .. .. .. DATA_1_LSW = 0x0
- // .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U
- // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF0000U),
- // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. START: ADD 1 MS DELAY
- // .. .. .. ..
- EMIT_MASKDELAY(0XF8F00200, 1),
- // .. .. .. .. FINISH: ADD 1 MS DELAY
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. MASK_1_LSW = 0xbfff
- // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
- // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U
- // .. .. .. .. DATA_1_LSW = 0x4000
- // .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U
- // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U
- // .. .. .. ..
- EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U),
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: I2C0 RESET
- // .. .. .. START: I2C1 RESET
- // .. .. .. .. START: DIR MODE GPIO BANK0
- // .. .. .. .. FINISH: DIR MODE GPIO BANK0
- // .. .. .. .. START: DIR MODE GPIO BANK1
- // .. .. .. .. FINISH: DIR MODE GPIO BANK1
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. START: OUTPUT ENABLE
- // .. .. .. .. FINISH: OUTPUT ENABLE
- // .. .. .. .. START: OUTPUT ENABLE
- // .. .. .. .. FINISH: OUTPUT ENABLE
- // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. START: ADD 1 MS DELAY
- // .. .. .. ..
- EMIT_MASKDELAY(0XF8F00200, 1),
- // .. .. .. .. FINISH: ADD 1 MS DELAY
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: I2C1 RESET
- // .. .. FINISH: I2C RESET
- // .. .. START: NOR CHIP SELECT
- // .. .. .. START: DIR MODE BANK 0
- // .. .. .. FINISH: DIR MODE BANK 0
- // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. START: OUTPUT ENABLE BANK 0
- // .. .. .. FINISH: OUTPUT ENABLE BANK 0
- // .. .. FINISH: NOR CHIP SELECT
- // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_post_config_1_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: ENABLING LEVEL SHIFTER
- // .. USER_INP_ICT_EN_0 = 3
- // .. ==> 0XF8000900[1:0] = 0x00000003U
- // .. ==> MASK : 0x00000003U VAL : 0x00000003U
- // .. USER_INP_ICT_EN_1 = 3
- // .. ==> 0XF8000900[3:2] = 0x00000003U
- // .. ==> MASK : 0x0000000CU VAL : 0x0000000CU
- // ..
- EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
- // .. FINISH: ENABLING LEVEL SHIFTER
- // .. START: FPGA RESETS TO 0
- // .. reserved_3 = 0
- // .. ==> 0XF8000240[31:25] = 0x00000000U
- // .. ==> MASK : 0xFE000000U VAL : 0x00000000U
- // .. FPGA_ACP_RST = 0
- // .. ==> 0XF8000240[24:24] = 0x00000000U
- // .. ==> MASK : 0x01000000U VAL : 0x00000000U
- // .. FPGA_AXDS3_RST = 0
- // .. ==> 0XF8000240[23:23] = 0x00000000U
- // .. ==> MASK : 0x00800000U VAL : 0x00000000U
- // .. FPGA_AXDS2_RST = 0
- // .. ==> 0XF8000240[22:22] = 0x00000000U
- // .. ==> MASK : 0x00400000U VAL : 0x00000000U
- // .. FPGA_AXDS1_RST = 0
- // .. ==> 0XF8000240[21:21] = 0x00000000U
- // .. ==> MASK : 0x00200000U VAL : 0x00000000U
- // .. FPGA_AXDS0_RST = 0
- // .. ==> 0XF8000240[20:20] = 0x00000000U
- // .. ==> MASK : 0x00100000U VAL : 0x00000000U
- // .. reserved_2 = 0
- // .. ==> 0XF8000240[19:18] = 0x00000000U
- // .. ==> MASK : 0x000C0000U VAL : 0x00000000U
- // .. FSSW1_FPGA_RST = 0
- // .. ==> 0XF8000240[17:17] = 0x00000000U
- // .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. FSSW0_FPGA_RST = 0
- // .. ==> 0XF8000240[16:16] = 0x00000000U
- // .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. reserved_1 = 0
- // .. ==> 0XF8000240[15:14] = 0x00000000U
- // .. ==> MASK : 0x0000C000U VAL : 0x00000000U
- // .. FPGA_FMSW1_RST = 0
- // .. ==> 0XF8000240[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // .. FPGA_FMSW0_RST = 0
- // .. ==> 0XF8000240[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. FPGA_DMA3_RST = 0
- // .. ==> 0XF8000240[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. FPGA_DMA2_RST = 0
- // .. ==> 0XF8000240[10:10] = 0x00000000U
- // .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. FPGA_DMA1_RST = 0
- // .. ==> 0XF8000240[9:9] = 0x00000000U
- // .. ==> MASK : 0x00000200U VAL : 0x00000000U
- // .. FPGA_DMA0_RST = 0
- // .. ==> 0XF8000240[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. reserved = 0
- // .. ==> 0XF8000240[7:4] = 0x00000000U
- // .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. FPGA3_OUT_RST = 0
- // .. ==> 0XF8000240[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. FPGA2_OUT_RST = 0
- // .. ==> 0XF8000240[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. FPGA1_OUT_RST = 0
- // .. ==> 0XF8000240[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. FPGA0_OUT_RST = 0
- // .. ==> 0XF8000240[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
- // .. FINISH: FPGA RESETS TO 0
- // .. START: AFI REGISTERS
- // .. .. START: AFI0 REGISTERS
- // .. .. FINISH: AFI0 REGISTERS
- // .. .. START: AFI1 REGISTERS
- // .. .. FINISH: AFI1 REGISTERS
- // .. .. START: AFI2 REGISTERS
- // .. .. FINISH: AFI2 REGISTERS
- // .. .. START: AFI3 REGISTERS
- // .. .. FINISH: AFI3 REGISTERS
- // .. FINISH: AFI REGISTERS
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_debug_1_0[] = {
- // START: top
- // .. START: CROSS TRIGGER CONFIGURATIONS
- // .. .. START: UNLOCKING CTI REGISTERS
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. FINISH: UNLOCKING CTI REGISTERS
- // .. .. START: ENABLING CTI MODULES AND CHANNELS
- // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
- // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. FINISH: CROSS TRIGGER CONFIGURATIONS
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-
-#include "xil_io.h"
-#define PS7_MASK_POLL_TIME 100000000
-
-char*
-getPS7MessageInfo(unsigned key) {
-
- char* err_msg = "";
- switch (key) {
- case PS7_INIT_SUCCESS: err_msg = "PS7 initialization successful"; break;
- case PS7_INIT_CORRUPT: err_msg = "PS7 init Data Corrupted"; break;
- case PS7_INIT_TIMEOUT: err_msg = "PS7 init mask poll timeout"; break;
- case PS7_POLL_FAILED_DDR_INIT: err_msg = "Mask Poll failed for DDR Init"; break;
- case PS7_POLL_FAILED_DMA: err_msg = "Mask Poll failed for PLL Init"; break;
- case PS7_POLL_FAILED_PLL: err_msg = "Mask Poll failed for DMA done bit"; break;
- default: err_msg = "Undefined error status"; break;
- }
-
- return err_msg;
-}
-
-unsigned long
-ps7GetSiliconVersion () {
- // Read PS version from MCTRL register [31:28]
- unsigned long mask = 0xF0000000;
- unsigned long *addr = (unsigned long*) 0XF8007080;
- unsigned long ps_version = (*addr & mask) >> 28;
- return ps_version;
-}
-
-void mask_write (unsigned long add , unsigned long mask, unsigned long val ) {
- unsigned long *addr = (unsigned long*) add;
- *addr = ( val & mask ) | ( *addr & ~mask);
- //xil_printf("MaskWrite : 0x%x--> 0x%x \n \r" ,add, *addr);
-}
-
-
-int mask_poll(unsigned long add , unsigned long mask ) {
- volatile unsigned long *addr = (volatile unsigned long*) add;
- int i = 0;
- while (!(*addr & mask)) {
- if (i == PS7_MASK_POLL_TIME) {
- return -1;
- }
- i++;
- }
- return 1;
- //xil_printf("MaskPoll : 0x%x --> 0x%x \n \r" , add, *addr);
-}
-
-unsigned long mask_read(unsigned long add , unsigned long mask ) {
- unsigned long *addr = (unsigned long*) add;
- unsigned long val = (*addr & mask);
- //xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val);
- return val;
-}
-
-
-
-int
-ps7_config(unsigned long * ps7_config_init)
-{
- unsigned long *ptr = ps7_config_init;
-
- unsigned long opcode; // current instruction ..
- unsigned long args[16]; // no opcode has so many args ...
- int numargs; // number of arguments of this instruction
- int j; // general purpose index
-
- volatile unsigned long *addr; // some variable to make code readable
- unsigned long val,mask; // some variable to make code readable
-
- int finish = -1 ; // loop while this is negative !
- int i = 0; // Timeout variable
-
- while( finish < 0 ) {
- numargs = ptr[0] & 0xF;
- opcode = ptr[0] >> 4;
-
- for( j = 0 ; j < numargs ; j ++ )
- args[j] = ptr[j+1];
- ptr += numargs + 1;
-
-
- switch ( opcode ) {
-
- case OPCODE_EXIT:
- finish = PS7_INIT_SUCCESS;
- break;
-
- case OPCODE_CLEAR:
- addr = (unsigned long*) args[0];
- *addr = 0;
- break;
-
- case OPCODE_WRITE:
- addr = (unsigned long*) args[0];
- val = args[1];
- *addr = val;
- break;
-
- case OPCODE_MASKWRITE:
- addr = (unsigned long*) args[0];
- mask = args[1];
- val = args[2];
- *addr = ( val & mask ) | ( *addr & ~mask);
- break;
-
- case OPCODE_MASKPOLL:
- addr = (unsigned long*) args[0];
- mask = args[1];
- i = 0;
- while (!(*addr & mask)) {
- if (i == PS7_MASK_POLL_TIME) {
- finish = PS7_INIT_TIMEOUT;
- break;
- }
- i++;
- }
- break;
- case OPCODE_MASKDELAY:
- addr = (unsigned long*) args[0];
- mask = args[1];
- int delay = get_number_of_cycles_for_delay(mask);
- perf_reset_and_start_timer();
- while ((*addr < delay)) {
- }
- break;
- default:
- finish = PS7_INIT_CORRUPT;
- break;
- }
- }
- return finish;
-}
-
-unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0;
-unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0;
-unsigned long *ps7_clock_init_data = ps7_clock_init_data_3_0;
-unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0;
-unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
-
-int
-ps7_post_config()
-{
- // Get the PS_VERSION on run time
- unsigned long si_ver = ps7GetSiliconVersion ();
- int ret = -1;
- if (si_ver == PCW_SILICON_VERSION_1) {
- ret = ps7_config (ps7_post_config_1_0);
- if (ret != PS7_INIT_SUCCESS) return ret;
- } else if (si_ver == PCW_SILICON_VERSION_2) {
- ret = ps7_config (ps7_post_config_2_0);
- if (ret != PS7_INIT_SUCCESS) return ret;
- } else {
- ret = ps7_config (ps7_post_config_3_0);
- if (ret != PS7_INIT_SUCCESS) return ret;
- }
- return PS7_INIT_SUCCESS;
-}
-
-int
-ps7_debug()
-{
- // Get the PS_VERSION on run time
- unsigned long si_ver = ps7GetSiliconVersion ();
- int ret = -1;
- if (si_ver == PCW_SILICON_VERSION_1) {
- ret = ps7_config (ps7_debug_1_0);
- if (ret != PS7_INIT_SUCCESS) return ret;
- } else if (si_ver == PCW_SILICON_VERSION_2) {
- ret = ps7_config (ps7_debug_2_0);
- if (ret != PS7_INIT_SUCCESS) return ret;
- } else {
- ret = ps7_config (ps7_debug_3_0);
- if (ret != PS7_INIT_SUCCESS) return ret;
- }
- return PS7_INIT_SUCCESS;
-}
-
-int
-ps7_init()
-{
- // Get the PS_VERSION on run time
- unsigned long si_ver = ps7GetSiliconVersion ();
- int ret;
- //int pcw_ver = 0;
-
- if (si_ver == PCW_SILICON_VERSION_1) {
- ps7_mio_init_data = ps7_mio_init_data_1_0;
- ps7_pll_init_data = ps7_pll_init_data_1_0;
- ps7_clock_init_data = ps7_clock_init_data_1_0;
- ps7_ddr_init_data = ps7_ddr_init_data_1_0;
- ps7_peripherals_init_data = ps7_peripherals_init_data_1_0;
- //pcw_ver = 1;
-
- } else if (si_ver == PCW_SILICON_VERSION_2) {
- ps7_mio_init_data = ps7_mio_init_data_2_0;
- ps7_pll_init_data = ps7_pll_init_data_2_0;
- ps7_clock_init_data = ps7_clock_init_data_2_0;
- ps7_ddr_init_data = ps7_ddr_init_data_2_0;
- ps7_peripherals_init_data = ps7_peripherals_init_data_2_0;
- //pcw_ver = 2;
-
- } else {
- ps7_mio_init_data = ps7_mio_init_data_3_0;
- ps7_pll_init_data = ps7_pll_init_data_3_0;
- ps7_clock_init_data = ps7_clock_init_data_3_0;
- ps7_ddr_init_data = ps7_ddr_init_data_3_0;
- ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
- //pcw_ver = 3;
- }
-
- // MIO init
- ret = ps7_config (ps7_mio_init_data);
- if (ret != PS7_INIT_SUCCESS) return ret;
-
- // PLL init
- ret = ps7_config (ps7_pll_init_data);
- if (ret != PS7_INIT_SUCCESS) return ret;
-
- // Clock init
- ret = ps7_config (ps7_clock_init_data);
- if (ret != PS7_INIT_SUCCESS) return ret;
-
- // DDR init
- ret = ps7_config (ps7_ddr_init_data);
- if (ret != PS7_INIT_SUCCESS) return ret;
-
-
-
- // Peripherals init
- ret = ps7_config (ps7_peripherals_init_data);
- if (ret != PS7_INIT_SUCCESS) return ret;
- //xil_printf ("\n PCW Silicon Version : %d.0", pcw_ver);
- return PS7_INIT_SUCCESS;
-}
-
-
-
-
-/* For delay calculation using global timer */
-
-/* start timer */
- void perf_start_clock(void)
-{
- *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) | // Timer Enable
- (1 << 3) | // Auto-increment
- (0 << 8) // Pre-scale
- );
-}
-
-/* stop timer and reset timer count regs */
- void perf_reset_clock(void)
-{
- perf_disable_clock();
- *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_L32 = 0;
- *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_U32 = 0;
-}
-
-/* Compute mask for given delay in miliseconds*/
-int get_number_of_cycles_for_delay(unsigned int delay)
-{
- // GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x)
- return (APU_FREQ*delay/(2*1000));
-
-}
-
-/* stop timer */
- void perf_disable_clock(void)
-{
- *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = 0;
-}
-
-void perf_reset_and_start_timer()
-{
- perf_reset_clock();
- perf_start_clock();
-}
+++ /dev/null
-
-/******************************************************************************
-*
-* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
-*
-* SPDX-License-Identifier: GPL-2.0+
-*
-*
-*******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file ps7_init.h
-*
-* This file can be included in FSBL code
-* to get prototype of ps7_init() function
-* and error codes
-*
-*****************************************************************************/
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-//typedef unsigned int u32;
-
-
-/** do we need to make this name more unique ? **/
-//extern u32 ps7_init_data[];
-extern unsigned long * ps7_ddr_init_data;
-extern unsigned long * ps7_mio_init_data;
-extern unsigned long * ps7_pll_init_data;
-extern unsigned long * ps7_clock_init_data;
-extern unsigned long * ps7_peripherals_init_data;
-
-
-
-#define OPCODE_EXIT 0U
-#define OPCODE_CLEAR 1U
-#define OPCODE_WRITE 2U
-#define OPCODE_MASKWRITE 3U
-#define OPCODE_MASKPOLL 4U
-#define OPCODE_MASKDELAY 5U
-#define NEW_PS7_ERR_CODE 1
-
-/* Encode number of arguments in last nibble */
-#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 )
-#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr
-#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val
-#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
-#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask
-#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
-
-/* Returns codes of PS7_Init */
-#define PS7_INIT_SUCCESS (0) // 0 is success in good old C
-#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now
-#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out
-#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init
-#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit
-#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init
-
-
-/* Silicon Versions */
-#define PCW_SILICON_VERSION_1 0
-#define PCW_SILICON_VERSION_2 1
-#define PCW_SILICON_VERSION_3 2
-
-/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
-#define PS7_POST_CONFIG
-
-/* Freq of all peripherals */
-
-#define APU_FREQ 666666687
-#define DDR_FREQ 533333374
-#define DCI_FREQ 10158731
-#define QSPI_FREQ 200000000
-#define SMC_FREQ 10000000
-#define ENET0_FREQ 25000000
-#define ENET1_FREQ 10000000
-#define USB0_FREQ 60000000
-#define USB1_FREQ 60000000
-#define SDIO_FREQ 50000000
-#define UART_FREQ 50000000
-#define SPI_FREQ 10000000
-#define I2C_FREQ 111111115
-#define WDT_FREQ 111111115
-#define TTC_FREQ 50000000
-#define CAN_FREQ 10000000
-#define PCAP_FREQ 200000000
-#define TPIU_FREQ 200000000
-#define FPGA0_FREQ 50000000
-#define FPGA1_FREQ 50000000
-#define FPGA2_FREQ 50000000
-#define FPGA3_FREQ 50000000
-
-
-/* For delay calculation using global registers*/
-#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
-#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204
-#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208
-#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218
-
-int ps7_config( unsigned long*);
-int ps7_init();
-int ps7_post_config();
-int ps7_debug();
-char* getPS7MessageInfo(unsigned key);
-
-void perf_start_clock(void);
-void perf_disable_clock(void);
-void perf_reset_clock(void);
-void perf_reset_and_start_timer();
-int get_number_of_cycles_for_delay(unsigned int delay);
-#ifdef __cplusplus
-}
-#endif
+++ /dev/null
-ps7_init_gpl.[ch]
+++ /dev/null
-/******************************************************************************
-* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
-*
-* SPDX-License-Identifier: GPL-2.0+
-*
-*
-******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file ps7_init_gpl.c
-*
-* This file is automatically generated
-*
-*****************************************************************************/
-
-#include "ps7_init_gpl.h"
-
-unsigned long ps7_pll_init_data_3_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: PLL SLCR REGISTERS
- // .. .. START: ARM PLL INIT
- // .. .. PLL_RES = 0x2
- // .. .. ==> 0XF8000110[7:4] = 0x00000002U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
- // .. .. PLL_CP = 0x2
- // .. .. ==> 0XF8000110[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. LOCK_CNT = 0xfa
- // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
- // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U
- // .. ..
- EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
- // .. .. .. START: UPDATE FB_DIV
- // .. .. .. PLL_FDIV = 0x28
- // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
- // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
- // .. .. .. FINISH: UPDATE FB_DIV
- // .. .. .. START: BY PASS PLL
- // .. .. .. PLL_BYPASS_FORCE = 1
- // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
- // .. .. .. FINISH: BY PASS PLL
- // .. .. .. START: ASSERT RESET
- // .. .. .. PLL_RESET = 1
- // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
- // .. .. .. FINISH: ASSERT RESET
- // .. .. .. START: DEASSERT RESET
- // .. .. .. PLL_RESET = 0
- // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
- // .. .. .. FINISH: DEASSERT RESET
- // .. .. .. START: CHECK PLL STATUS
- // .. .. .. ARM_PLL_LOCK = 1
- // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ..
- EMIT_MASKPOLL(0XF800010C, 0x00000001U),
- // .. .. .. FINISH: CHECK PLL STATUS
- // .. .. .. START: REMOVE PLL BY PASS
- // .. .. .. PLL_BYPASS_FORCE = 0
- // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
- // .. .. .. FINISH: REMOVE PLL BY PASS
- // .. .. .. SRCSEL = 0x0
- // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. .. .. DIVISOR = 0x2
- // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
- // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U
- // .. .. .. CPU_6OR4XCLKACT = 0x1
- // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
- // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U
- // .. .. .. CPU_3OR2XCLKACT = 0x1
- // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
- // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U
- // .. .. .. CPU_2XCLKACT = 0x1
- // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
- // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U
- // .. .. .. CPU_1XCLKACT = 0x1
- // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
- // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U
- // .. .. .. CPU_PERI_CLKACT = 0x1
- // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
- // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
- // .. .. FINISH: ARM PLL INIT
- // .. .. START: DDR PLL INIT
- // .. .. PLL_RES = 0x2
- // .. .. ==> 0XF8000114[7:4] = 0x00000002U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
- // .. .. PLL_CP = 0x2
- // .. .. ==> 0XF8000114[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. LOCK_CNT = 0x12c
- // .. .. ==> 0XF8000114[21:12] = 0x0000012CU
- // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U
- // .. ..
- EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
- // .. .. .. START: UPDATE FB_DIV
- // .. .. .. PLL_FDIV = 0x20
- // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
- // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
- // .. .. .. FINISH: UPDATE FB_DIV
- // .. .. .. START: BY PASS PLL
- // .. .. .. PLL_BYPASS_FORCE = 1
- // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
- // .. .. .. FINISH: BY PASS PLL
- // .. .. .. START: ASSERT RESET
- // .. .. .. PLL_RESET = 1
- // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
- // .. .. .. FINISH: ASSERT RESET
- // .. .. .. START: DEASSERT RESET
- // .. .. .. PLL_RESET = 0
- // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
- // .. .. .. FINISH: DEASSERT RESET
- // .. .. .. START: CHECK PLL STATUS
- // .. .. .. DDR_PLL_LOCK = 1
- // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. .. ..
- EMIT_MASKPOLL(0XF800010C, 0x00000002U),
- // .. .. .. FINISH: CHECK PLL STATUS
- // .. .. .. START: REMOVE PLL BY PASS
- // .. .. .. PLL_BYPASS_FORCE = 0
- // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
- // .. .. .. FINISH: REMOVE PLL BY PASS
- // .. .. .. DDR_3XCLKACT = 0x1
- // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. .. DDR_2XCLKACT = 0x1
- // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. .. .. DDR_3XCLK_DIVISOR = 0x2
- // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
- // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U
- // .. .. .. DDR_2XCLK_DIVISOR = 0x3
- // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
- // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
- // .. .. FINISH: DDR PLL INIT
- // .. .. START: IO PLL INIT
- // .. .. PLL_RES = 0xc
- // .. .. ==> 0XF8000118[7:4] = 0x0000000CU
- // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U
- // .. .. PLL_CP = 0x2
- // .. .. ==> 0XF8000118[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. LOCK_CNT = 0x145
- // .. .. ==> 0XF8000118[21:12] = 0x00000145U
- // .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U
- // .. ..
- EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U),
- // .. .. .. START: UPDATE FB_DIV
- // .. .. .. PLL_FDIV = 0x1e
- // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU
- // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U),
- // .. .. .. FINISH: UPDATE FB_DIV
- // .. .. .. START: BY PASS PLL
- // .. .. .. PLL_BYPASS_FORCE = 1
- // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
- // .. .. .. FINISH: BY PASS PLL
- // .. .. .. START: ASSERT RESET
- // .. .. .. PLL_RESET = 1
- // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
- // .. .. .. FINISH: ASSERT RESET
- // .. .. .. START: DEASSERT RESET
- // .. .. .. PLL_RESET = 0
- // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
- // .. .. .. FINISH: DEASSERT RESET
- // .. .. .. START: CHECK PLL STATUS
- // .. .. .. IO_PLL_LOCK = 1
- // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. .. ..
- EMIT_MASKPOLL(0XF800010C, 0x00000004U),
- // .. .. .. FINISH: CHECK PLL STATUS
- // .. .. .. START: REMOVE PLL BY PASS
- // .. .. .. PLL_BYPASS_FORCE = 0
- // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
- // .. .. .. FINISH: REMOVE PLL BY PASS
- // .. .. FINISH: IO PLL INIT
- // .. FINISH: PLL SLCR REGISTERS
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_clock_init_data_3_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: CLOCK CONTROL SLCR REGISTERS
- // .. CLKACT = 0x1
- // .. ==> 0XF8000128[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. DIVISOR0 = 0x23
- // .. ==> 0XF8000128[13:8] = 0x00000023U
- // .. ==> MASK : 0x00003F00U VAL : 0x00002300U
- // .. DIVISOR1 = 0x3
- // .. ==> 0XF8000128[25:20] = 0x00000003U
- // .. ==> MASK : 0x03F00000U VAL : 0x00300000U
- // ..
- EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U),
- // .. CLKACT = 0x1
- // .. ==> 0XF8000138[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000138[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
- // .. CLKACT = 0x1
- // .. ==> 0XF8000140[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000140[6:4] = 0x00000000U
- // .. ==> MASK : 0x00000070U VAL : 0x00000000U
- // .. DIVISOR = 0x8
- // .. ==> 0XF8000140[13:8] = 0x00000008U
- // .. ==> MASK : 0x00003F00U VAL : 0x00000800U
- // .. DIVISOR1 = 0x1
- // .. ==> 0XF8000140[25:20] = 0x00000001U
- // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
- // ..
- EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U),
- // .. CLKACT = 0x1
- // .. ==> 0XF800014C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. SRCSEL = 0x0
- // .. ==> 0XF800014C[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR = 0x5
- // .. ==> 0XF800014C[13:8] = 0x00000005U
- // .. ==> MASK : 0x00003F00U VAL : 0x00000500U
- // ..
- EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
- // .. CLKACT0 = 0x1
- // .. ==> 0XF8000150[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. CLKACT1 = 0x0
- // .. ==> 0XF8000150[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000150[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR = 0x14
- // .. ==> 0XF8000150[13:8] = 0x00000014U
- // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
- // ..
- EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U),
- // .. CLKACT0 = 0x0
- // .. ==> 0XF8000154[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. CLKACT1 = 0x1
- // .. ==> 0XF8000154[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000154[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR = 0x14
- // .. ==> 0XF8000154[13:8] = 0x00000014U
- // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
- // ..
- EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U),
- // .. CLKACT = 0x1
- // .. ==> 0XF8000168[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000168[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR = 0x5
- // .. ==> 0XF8000168[13:8] = 0x00000005U
- // .. ==> MASK : 0x00003F00U VAL : 0x00000500U
- // ..
- EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000170[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR0 = 0xa
- // .. ==> 0XF8000170[13:8] = 0x0000000AU
- // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U
- // .. DIVISOR1 = 0x1
- // .. ==> 0XF8000170[25:20] = 0x00000001U
- // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
- // ..
- EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00100A00U),
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000180[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR0 = 0x7
- // .. ==> 0XF8000180[13:8] = 0x00000007U
- // .. ==> MASK : 0x00003F00U VAL : 0x00000700U
- // .. DIVISOR1 = 0x1
- // .. ==> 0XF8000180[25:20] = 0x00000001U
- // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
- // ..
- EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00100700U),
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000190[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR0 = 0x14
- // .. ==> 0XF8000190[13:8] = 0x00000014U
- // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
- // .. DIVISOR1 = 0x1
- // .. ==> 0XF8000190[25:20] = 0x00000001U
- // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
- // ..
- EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101400U),
- // .. SRCSEL = 0x0
- // .. ==> 0XF80001A0[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR0 = 0x14
- // .. ==> 0XF80001A0[13:8] = 0x00000014U
- // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
- // .. DIVISOR1 = 0x1
- // .. ==> 0XF80001A0[25:20] = 0x00000001U
- // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
- // ..
- EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U),
- // .. CLK_621_TRUE = 0x1
- // .. ==> 0XF80001C4[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // ..
- EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
- // .. DMA_CPU_2XCLKACT = 0x1
- // .. ==> 0XF800012C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. USB0_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. USB1_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[3:3] = 0x00000001U
- // .. ==> MASK : 0x00000008U VAL : 0x00000008U
- // .. GEM0_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[6:6] = 0x00000001U
- // .. ==> MASK : 0x00000040U VAL : 0x00000040U
- // .. GEM1_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. SDI0_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[10:10] = 0x00000001U
- // .. ==> MASK : 0x00000400U VAL : 0x00000400U
- // .. SDI1_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. SPI0_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[14:14] = 0x00000000U
- // .. ==> MASK : 0x00004000U VAL : 0x00000000U
- // .. SPI1_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[15:15] = 0x00000000U
- // .. ==> MASK : 0x00008000U VAL : 0x00000000U
- // .. CAN0_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[16:16] = 0x00000000U
- // .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. CAN1_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[17:17] = 0x00000000U
- // .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. I2C0_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[18:18] = 0x00000001U
- // .. ==> MASK : 0x00040000U VAL : 0x00040000U
- // .. I2C1_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[19:19] = 0x00000001U
- // .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // .. UART0_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[20:20] = 0x00000000U
- // .. ==> MASK : 0x00100000U VAL : 0x00000000U
- // .. UART1_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[21:21] = 0x00000001U
- // .. ==> MASK : 0x00200000U VAL : 0x00200000U
- // .. GPIO_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[22:22] = 0x00000001U
- // .. ==> MASK : 0x00400000U VAL : 0x00400000U
- // .. LQSPI_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[23:23] = 0x00000001U
- // .. ==> MASK : 0x00800000U VAL : 0x00800000U
- // .. SMC_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[24:24] = 0x00000001U
- // .. ==> MASK : 0x01000000U VAL : 0x01000000U
- // ..
- EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC044DU),
- // .. FINISH: CLOCK CONTROL SLCR REGISTERS
- // .. START: THIS SHOULD BE BLANK
- // .. FINISH: THIS SHOULD BE BLANK
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_ddr_init_data_3_0[] = {
- // START: top
- // .. START: DDR INITIALIZATION
- // .. .. START: LOCK DDR
- // .. .. reg_ddrc_soft_rstb = 0
- // .. .. ==> 0XF8006000[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_powerdown_en = 0x0
- // .. .. ==> 0XF8006000[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_ddrc_data_bus_width = 0x0
- // .. .. ==> 0XF8006000[3:2] = 0x00000000U
- // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U
- // .. .. reg_ddrc_burst8_refresh = 0x0
- // .. .. ==> 0XF8006000[6:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U
- // .. .. reg_ddrc_rdwr_idle_gap = 0x1
- // .. .. ==> 0XF8006000[13:7] = 0x00000001U
- // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U
- // .. .. reg_ddrc_dis_rd_bypass = 0x0
- // .. .. ==> 0XF8006000[14:14] = 0x00000000U
- // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_act_bypass = 0x0
- // .. .. ==> 0XF8006000[15:15] = 0x00000000U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_auto_refresh = 0x0
- // .. .. ==> 0XF8006000[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
- // .. .. FINISH: LOCK DDR
- // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81
- // .. .. ==> 0XF8006004[11:0] = 0x00000081U
- // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U
- // .. .. reserved_reg_ddrc_active_ranks = 0x1
- // .. .. ==> 0XF8006004[13:12] = 0x00000001U
- // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U
- // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
- // .. .. ==> 0XF8006004[18:14] = 0x00000000U
- // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU ,0x00001081U),
- // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
- // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
- // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU
- // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
- // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
- // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U
- // .. .. reg_ddrc_hpr_xact_run_length = 0xf
- // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
- // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U
- // .. ..
- EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
- // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
- // .. .. ==> 0XF800600C[10:0] = 0x00000001U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U
- // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
- // .. .. ==> 0XF800600C[21:11] = 0x00000002U
- // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U
- // .. .. reg_ddrc_lpr_xact_run_length = 0x8
- // .. .. ==> 0XF800600C[25:22] = 0x00000008U
- // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U
- // .. ..
- EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
- // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
- // .. .. ==> 0XF8006010[10:0] = 0x00000001U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U
- // .. .. reg_ddrc_w_xact_run_length = 0x8
- // .. .. ==> 0XF8006010[14:11] = 0x00000008U
- // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U
- // .. .. reg_ddrc_w_max_starve_x32 = 0x2
- // .. .. ==> 0XF8006010[25:15] = 0x00000002U
- // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U
- // .. ..
- EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
- // .. .. reg_ddrc_t_rc = 0x1b
- // .. .. ==> 0XF8006014[5:0] = 0x0000001BU
- // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001BU
- // .. .. reg_ddrc_t_rfc_min = 0x56
- // .. .. ==> 0XF8006014[13:6] = 0x00000056U
- // .. .. ==> MASK : 0x00003FC0U VAL : 0x00001580U
- // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
- // .. .. ==> 0XF8006014[20:14] = 0x00000010U
- // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U
- // .. ..
- EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004159BU),
- // .. .. reg_ddrc_wr2pre = 0x12
- // .. .. ==> 0XF8006018[4:0] = 0x00000012U
- // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U
- // .. .. reg_ddrc_powerdown_to_x32 = 0x6
- // .. .. ==> 0XF8006018[9:5] = 0x00000006U
- // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U
- // .. .. reg_ddrc_t_faw = 0x18
- // .. .. ==> 0XF8006018[15:10] = 0x00000018U
- // .. .. ==> MASK : 0x0000FC00U VAL : 0x00006000U
- // .. .. reg_ddrc_t_ras_max = 0x24
- // .. .. ==> 0XF8006018[21:16] = 0x00000024U
- // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U
- // .. .. reg_ddrc_t_ras_min = 0x14
- // .. .. ==> 0XF8006018[26:22] = 0x00000014U
- // .. .. ==> MASK : 0x07C00000U VAL : 0x05000000U
- // .. .. reg_ddrc_t_cke = 0x4
- // .. .. ==> 0XF8006018[31:28] = 0x00000004U
- // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x452460D2U),
- // .. .. reg_ddrc_write_latency = 0x5
- // .. .. ==> 0XF800601C[4:0] = 0x00000005U
- // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U
- // .. .. reg_ddrc_rd2wr = 0x7
- // .. .. ==> 0XF800601C[9:5] = 0x00000007U
- // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U
- // .. .. reg_ddrc_wr2rd = 0xe
- // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
- // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U
- // .. .. reg_ddrc_t_xp = 0x4
- // .. .. ==> 0XF800601C[19:15] = 0x00000004U
- // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U
- // .. .. reg_ddrc_pad_pd = 0x0
- // .. .. ==> 0XF800601C[22:20] = 0x00000000U
- // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U
- // .. .. reg_ddrc_rd2pre = 0x4
- // .. .. ==> 0XF800601C[27:23] = 0x00000004U
- // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U
- // .. .. reg_ddrc_t_rcd = 0x7
- // .. .. ==> 0XF800601C[31:28] = 0x00000007U
- // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U
- // .. ..
- EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
- // .. .. reg_ddrc_t_ccd = 0x4
- // .. .. ==> 0XF8006020[4:2] = 0x00000004U
- // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U
- // .. .. reg_ddrc_t_rrd = 0x6
- // .. .. ==> 0XF8006020[7:5] = 0x00000006U
- // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U
- // .. .. reg_ddrc_refresh_margin = 0x2
- // .. .. ==> 0XF8006020[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. reg_ddrc_t_rp = 0x7
- // .. .. ==> 0XF8006020[15:12] = 0x00000007U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U
- // .. .. reg_ddrc_refresh_to_x32 = 0x8
- // .. .. ==> 0XF8006020[20:16] = 0x00000008U
- // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U
- // .. .. reg_ddrc_mobile = 0x0
- // .. .. ==> 0XF8006020[22:22] = 0x00000000U
- // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U
- // .. .. reg_ddrc_en_dfi_dram_clk_disable = 0x0
- // .. .. ==> 0XF8006020[23:23] = 0x00000000U
- // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U
- // .. .. reg_ddrc_read_latency = 0x7
- // .. .. ==> 0XF8006020[28:24] = 0x00000007U
- // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U
- // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
- // .. .. ==> 0XF8006020[29:29] = 0x00000001U
- // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U
- // .. .. reg_ddrc_dis_pad_pd = 0x0
- // .. .. ==> 0XF8006020[30:30] = 0x00000000U
- // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU ,0x270872D0U),
- // .. .. reg_ddrc_en_2t_timing_mode = 0x0
- // .. .. ==> 0XF8006024[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_prefer_write = 0x0
- // .. .. ==> 0XF8006024[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_wr = 0x0
- // .. .. ==> 0XF8006024[6:6] = 0x00000000U
- // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_addr = 0x0
- // .. .. ==> 0XF8006024[8:7] = 0x00000000U
- // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_data = 0x0
- // .. .. ==> 0XF8006024[24:9] = 0x00000000U
- // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U
- // .. .. ddrc_reg_mr_wr_busy = 0x0
- // .. .. ==> 0XF8006024[25:25] = 0x00000000U
- // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_type = 0x0
- // .. .. ==> 0XF8006024[26:26] = 0x00000000U
- // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_rdata_valid = 0x0
- // .. .. ==> 0XF8006024[27:27] = 0x00000000U
- // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U ,0x00000000U),
- // .. .. reg_ddrc_final_wait_x32 = 0x7
- // .. .. ==> 0XF8006028[6:0] = 0x00000007U
- // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U
- // .. .. reg_ddrc_pre_ocd_x32 = 0x0
- // .. .. ==> 0XF8006028[10:7] = 0x00000000U
- // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U
- // .. .. reg_ddrc_t_mrd = 0x4
- // .. .. ==> 0XF8006028[13:11] = 0x00000004U
- // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U
- // .. ..
- EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
- // .. .. reg_ddrc_emr2 = 0x8
- // .. .. ==> 0XF800602C[15:0] = 0x00000008U
- // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U
- // .. .. reg_ddrc_emr3 = 0x0
- // .. .. ==> 0XF800602C[31:16] = 0x00000000U
- // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
- // .. .. reg_ddrc_mr = 0x930
- // .. .. ==> 0XF8006030[15:0] = 0x00000930U
- // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U
- // .. .. reg_ddrc_emr = 0x4
- // .. .. ==> 0XF8006030[31:16] = 0x00000004U
- // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U
- // .. ..
- EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
- // .. .. reg_ddrc_burst_rdwr = 0x4
- // .. .. ==> 0XF8006034[3:0] = 0x00000004U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U
- // .. .. reg_ddrc_pre_cke_x1024 = 0x105
- // .. .. ==> 0XF8006034[13:4] = 0x00000105U
- // .. .. ==> MASK : 0x00003FF0U VAL : 0x00001050U
- // .. .. reg_ddrc_post_cke_x1024 = 0x1
- // .. .. ==> 0XF8006034[25:16] = 0x00000001U
- // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U
- // .. .. reg_ddrc_burstchop = 0x0
- // .. .. ==> 0XF8006034[28:28] = 0x00000000U
- // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U),
- // .. .. reg_ddrc_force_low_pri_n = 0x0
- // .. .. ==> 0XF8006038[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_dq = 0x0
- // .. .. ==> 0XF8006038[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006038, 0x00000003U ,0x00000000U),
- // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
- // .. .. ==> 0XF800603C[3:0] = 0x00000007U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U
- // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
- // .. .. ==> 0XF800603C[7:4] = 0x00000007U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U
- // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
- // .. .. ==> 0XF800603C[11:8] = 0x00000007U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U
- // .. .. reg_ddrc_addrmap_col_b5 = 0x0
- // .. .. ==> 0XF800603C[15:12] = 0x00000000U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b6 = 0x0
- // .. .. ==> 0XF800603C[19:16] = 0x00000000U
- // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
- // .. .. reg_ddrc_addrmap_col_b2 = 0x0
- // .. .. ==> 0XF8006040[3:0] = 0x00000000U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b3 = 0x0
- // .. .. ==> 0XF8006040[7:4] = 0x00000000U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b4 = 0x0
- // .. .. ==> 0XF8006040[11:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b7 = 0x0
- // .. .. ==> 0XF8006040[15:12] = 0x00000000U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b8 = 0x0
- // .. .. ==> 0XF8006040[19:16] = 0x00000000U
- // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b9 = 0xf
- // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
- // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U
- // .. .. reg_ddrc_addrmap_col_b10 = 0xf
- // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
- // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U
- // .. .. reg_ddrc_addrmap_col_b11 = 0xf
- // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
- // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
- // .. .. reg_ddrc_addrmap_row_b0 = 0x6
- // .. .. ==> 0XF8006044[3:0] = 0x00000006U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U
- // .. .. reg_ddrc_addrmap_row_b1 = 0x6
- // .. .. ==> 0XF8006044[7:4] = 0x00000006U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U
- // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
- // .. .. ==> 0XF8006044[11:8] = 0x00000006U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U
- // .. .. reg_ddrc_addrmap_row_b12 = 0x6
- // .. .. ==> 0XF8006044[15:12] = 0x00000006U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U
- // .. .. reg_ddrc_addrmap_row_b13 = 0x6
- // .. .. ==> 0XF8006044[19:16] = 0x00000006U
- // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U
- // .. .. reg_ddrc_addrmap_row_b14 = 0xf
- // .. .. ==> 0XF8006044[23:20] = 0x0000000FU
- // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U
- // .. .. reg_ddrc_addrmap_row_b15 = 0xf
- // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
- // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0FF66666U),
- // .. .. reg_phy_rd_local_odt = 0x0
- // .. .. ==> 0XF8006048[13:12] = 0x00000000U
- // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U
- // .. .. reg_phy_wr_local_odt = 0x3
- // .. .. ==> 0XF8006048[15:14] = 0x00000003U
- // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U
- // .. .. reg_phy_idle_local_odt = 0x3
- // .. .. ==> 0XF8006048[17:16] = 0x00000003U
- // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U
- // .. ..
- EMIT_MASKWRITE(0XF8006048, 0x0003F000U ,0x0003C000U),
- // .. .. reg_phy_rd_cmd_to_data = 0x0
- // .. .. ==> 0XF8006050[3:0] = 0x00000000U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
- // .. .. reg_phy_wr_cmd_to_data = 0x0
- // .. .. ==> 0XF8006050[7:4] = 0x00000000U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. .. reg_phy_rdc_we_to_re_delay = 0x8
- // .. .. ==> 0XF8006050[11:8] = 0x00000008U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U
- // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
- // .. .. ==> 0XF8006050[15:15] = 0x00000000U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
- // .. .. reg_phy_use_fixed_re = 0x1
- // .. .. ==> 0XF8006050[16:16] = 0x00000001U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U
- // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
- // .. .. ==> 0XF8006050[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
- // .. .. ==> 0XF8006050[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_phy_clk_stall_level = 0x0
- // .. .. ==> 0XF8006050[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
- // .. .. ==> 0XF8006050[27:24] = 0x00000007U
- // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U
- // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
- // .. .. ==> 0XF8006050[31:28] = 0x00000007U
- // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
- // .. .. reg_ddrc_dis_dll_calib = 0x0
- // .. .. ==> 0XF8006058[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006058, 0x00010000U ,0x00000000U),
- // .. .. reg_ddrc_rd_odt_delay = 0x3
- // .. .. ==> 0XF800605C[3:0] = 0x00000003U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U
- // .. .. reg_ddrc_wr_odt_delay = 0x0
- // .. .. ==> 0XF800605C[7:4] = 0x00000000U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. .. reg_ddrc_rd_odt_hold = 0x0
- // .. .. ==> 0XF800605C[11:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U
- // .. .. reg_ddrc_wr_odt_hold = 0x5
- // .. .. ==> 0XF800605C[15:12] = 0x00000005U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U
- // .. ..
- EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
- // .. .. reg_ddrc_pageclose = 0x0
- // .. .. ==> 0XF8006060[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_lpr_num_entries = 0x1f
- // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
- // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU
- // .. .. reg_ddrc_auto_pre_en = 0x0
- // .. .. ==> 0XF8006060[7:7] = 0x00000000U
- // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. .. reg_ddrc_refresh_update_level = 0x0
- // .. .. ==> 0XF8006060[8:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_wc = 0x0
- // .. .. ==> 0XF8006060[9:9] = 0x00000000U
- // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_collision_page_opt = 0x0
- // .. .. ==> 0XF8006060[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_ddrc_selfref_en = 0x0
- // .. .. ==> 0XF8006060[12:12] = 0x00000000U
- // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
- // .. .. reg_ddrc_go2critical_hysteresis = 0x0
- // .. .. ==> 0XF8006064[12:5] = 0x00000000U
- // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U
- // .. .. reg_arb_go2critical_en = 0x1
- // .. .. ==> 0XF8006064[17:17] = 0x00000001U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U
- // .. ..
- EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
- // .. .. reg_ddrc_wrlvl_ww = 0x41
- // .. .. ==> 0XF8006068[7:0] = 0x00000041U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U
- // .. .. reg_ddrc_rdlvl_rr = 0x41
- // .. .. ==> 0XF8006068[15:8] = 0x00000041U
- // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U
- // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
- // .. .. ==> 0XF8006068[25:16] = 0x00000028U
- // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U
- // .. ..
- EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
- // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
- // .. .. ==> 0XF800606C[7:0] = 0x00000010U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U
- // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
- // .. .. ==> 0XF800606C[15:8] = 0x00000016U
- // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U
- // .. ..
- EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
- // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1
- // .. .. ==> 0XF8006078[3:0] = 0x00000001U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U
- // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1
- // .. .. ==> 0XF8006078[7:4] = 0x00000001U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U
- // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1
- // .. .. ==> 0XF8006078[11:8] = 0x00000001U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U
- // .. .. reg_ddrc_t_cksre = 0x6
- // .. .. ==> 0XF8006078[15:12] = 0x00000006U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U
- // .. .. reg_ddrc_t_cksrx = 0x6
- // .. .. ==> 0XF8006078[19:16] = 0x00000006U
- // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U
- // .. .. reg_ddrc_t_ckesr = 0x4
- // .. .. ==> 0XF8006078[25:20] = 0x00000004U
- // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U
- // .. ..
- EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U),
- // .. .. reg_ddrc_t_ckpde = 0x2
- // .. .. ==> 0XF800607C[3:0] = 0x00000002U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U
- // .. .. reg_ddrc_t_ckpdx = 0x2
- // .. .. ==> 0XF800607C[7:4] = 0x00000002U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
- // .. .. reg_ddrc_t_ckdpde = 0x2
- // .. .. ==> 0XF800607C[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. reg_ddrc_t_ckdpdx = 0x2
- // .. .. ==> 0XF800607C[15:12] = 0x00000002U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U
- // .. .. reg_ddrc_t_ckcsx = 0x3
- // .. .. ==> 0XF800607C[19:16] = 0x00000003U
- // .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U
- // .. ..
- EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U),
- // .. .. reg_ddrc_dis_auto_zq = 0x0
- // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_ddr3 = 0x1
- // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. .. reg_ddrc_t_mod = 0x200
- // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
- // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U
- // .. .. reg_ddrc_t_zq_long_nop = 0x200
- // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
- // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U
- // .. .. reg_ddrc_t_zq_short_nop = 0x40
- // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
- // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
- // .. .. t_zq_short_interval_x1024 = 0xcb73
- // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U
- // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U
- // .. .. dram_rstn_x1024 = 0x69
- // .. .. ==> 0XF80060A8[27:20] = 0x00000069U
- // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U
- // .. ..
- EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
- // .. .. deeppowerdown_en = 0x0
- // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. deeppowerdown_to_x1024 = 0xff
- // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
- // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU
- // .. ..
- EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
- // .. .. dfi_wrlvl_max_x1024 = 0xfff
- // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
- // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU
- // .. .. dfi_rdlvl_max_x1024 = 0xfff
- // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
- // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U
- // .. .. ddrc_reg_twrlvl_max_error = 0x0
- // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
- // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U
- // .. .. ddrc_reg_trdlvl_max_error = 0x0
- // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
- // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
- // .. .. reg_ddrc_dfi_wr_level_en = 0x1
- // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
- // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U
- // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
- // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
- // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U
- // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
- // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
- // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
- // .. .. reg_ddrc_skip_ocd = 0x1
- // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
- // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U
- // .. ..
- EMIT_MASKWRITE(0XF80060B4, 0x00000200U ,0x00000200U),
- // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
- // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
- // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U
- // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
- // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
- // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U
- // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
- // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
- // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U
- // .. ..
- EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
- // .. .. START: RESET ECC ERROR
- // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1
- // .. .. ==> 0XF80060C4[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. Clear_Correctable_DRAM_ECC_error = 1
- // .. .. ==> 0XF80060C4[1:1] = 0x00000001U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. ..
- EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U),
- // .. .. FINISH: RESET ECC ERROR
- // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
- // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
- // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
- // .. .. CORR_ECC_LOG_VALID = 0x0
- // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. ECC_CORRECTED_BIT_NUM = 0x0
- // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
- // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
- // .. .. UNCORR_ECC_LOG_VALID = 0x0
- // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
- // .. .. STAT_NUM_CORR_ERR = 0x0
- // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
- // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U
- // .. .. STAT_NUM_UNCORR_ERR = 0x0
- // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
- // .. .. reg_ddrc_ecc_mode = 0x0
- // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_scrub = 0x1
- // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U
- // .. ..
- EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
- // .. .. reg_phy_dif_on = 0x0
- // .. .. ==> 0XF8006114[3:0] = 0x00000000U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
- // .. .. reg_phy_dif_off = 0x0
- // .. .. ==> 0XF8006114[7:4] = 0x00000000U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
- // .. .. reg_phy_data_slice_in_use = 0x1
- // .. .. ==> 0XF8006118[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_phy_rdlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006118[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_inc_mode = 0x0
- // .. .. ==> 0XF8006118[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_wrlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006118[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_bist_shift_dq = 0x0
- // .. .. ==> 0XF8006118[14:6] = 0x00000000U
- // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. .. reg_phy_bist_err_clr = 0x0
- // .. .. ==> 0XF8006118[23:15] = 0x00000000U
- // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. .. reg_phy_dq_offset = 0x40
- // .. .. ==> 0XF8006118[30:24] = 0x00000040U
- // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU ,0x40000001U),
- // .. .. reg_phy_data_slice_in_use = 0x1
- // .. .. ==> 0XF800611C[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_phy_rdlvl_inc_mode = 0x0
- // .. .. ==> 0XF800611C[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_inc_mode = 0x0
- // .. .. ==> 0XF800611C[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_wrlvl_inc_mode = 0x0
- // .. .. ==> 0XF800611C[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_bist_shift_dq = 0x0
- // .. .. ==> 0XF800611C[14:6] = 0x00000000U
- // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. .. reg_phy_bist_err_clr = 0x0
- // .. .. ==> 0XF800611C[23:15] = 0x00000000U
- // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. .. reg_phy_dq_offset = 0x40
- // .. .. ==> 0XF800611C[30:24] = 0x00000040U
- // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU ,0x40000001U),
- // .. .. reg_phy_data_slice_in_use = 0x1
- // .. .. ==> 0XF8006120[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_phy_rdlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006120[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_inc_mode = 0x0
- // .. .. ==> 0XF8006120[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_wrlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006120[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_bist_shift_dq = 0x0
- // .. .. ==> 0XF8006120[14:6] = 0x00000000U
- // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. .. reg_phy_bist_err_clr = 0x0
- // .. .. ==> 0XF8006120[23:15] = 0x00000000U
- // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. .. reg_phy_dq_offset = 0x40
- // .. .. ==> 0XF8006120[30:24] = 0x00000040U
- // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU ,0x40000001U),
- // .. .. reg_phy_data_slice_in_use = 0x1
- // .. .. ==> 0XF8006124[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_phy_rdlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006124[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_inc_mode = 0x0
- // .. .. ==> 0XF8006124[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_wrlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006124[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_bist_shift_dq = 0x0
- // .. .. ==> 0XF8006124[14:6] = 0x00000000U
- // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. .. reg_phy_bist_err_clr = 0x0
- // .. .. ==> 0XF8006124[23:15] = 0x00000000U
- // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. .. reg_phy_dq_offset = 0x40
- // .. .. ==> 0XF8006124[30:24] = 0x00000040U
- // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU ,0x40000001U),
- // .. .. reg_phy_wrlvl_init_ratio = 0x3
- // .. .. ==> 0XF800612C[9:0] = 0x00000003U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000003U
- // .. .. reg_phy_gatelvl_init_ratio = 0xcf
- // .. .. ==> 0XF800612C[19:10] = 0x000000CFU
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x00033C00U
- // .. ..
- EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00033C03U),
- // .. .. reg_phy_wrlvl_init_ratio = 0x3
- // .. .. ==> 0XF8006130[9:0] = 0x00000003U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000003U
- // .. .. reg_phy_gatelvl_init_ratio = 0xd0
- // .. .. ==> 0XF8006130[19:10] = 0x000000D0U
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x00034000U
- // .. ..
- EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00034003U),
- // .. .. reg_phy_wrlvl_init_ratio = 0x0
- // .. .. ==> 0XF8006134[9:0] = 0x00000000U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_init_ratio = 0xbd
- // .. .. ==> 0XF8006134[19:10] = 0x000000BDU
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002F400U
- // .. ..
- EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0002F400U),
- // .. .. reg_phy_wrlvl_init_ratio = 0x0
- // .. .. ==> 0XF8006138[9:0] = 0x00000000U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_init_ratio = 0xc1
- // .. .. ==> 0XF8006138[19:10] = 0x000000C1U
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x00030400U
- // .. ..
- EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x00030400U),
- // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. .. ==> 0XF8006140[9:0] = 0x00000035U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. .. reg_phy_rd_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006140[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006140[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
- // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. .. ==> 0XF8006144[9:0] = 0x00000035U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. .. reg_phy_rd_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006144[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006144[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
- // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. .. ==> 0XF8006148[9:0] = 0x00000035U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. .. reg_phy_rd_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006148[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006148[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
- // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. .. ==> 0XF800614C[9:0] = 0x00000035U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. .. reg_phy_rd_dqs_slave_force = 0x0
- // .. .. ==> 0XF800614C[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. .. ==> 0XF800614C[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
- // .. .. reg_phy_wr_dqs_slave_ratio = 0x83
- // .. .. ==> 0XF8006154[9:0] = 0x00000083U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000083U
- // .. .. reg_phy_wr_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006154[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006154[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000083U),
- // .. .. reg_phy_wr_dqs_slave_ratio = 0x83
- // .. .. ==> 0XF8006158[9:0] = 0x00000083U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000083U
- // .. .. reg_phy_wr_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006158[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006158[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000083U),
- // .. .. reg_phy_wr_dqs_slave_ratio = 0x7f
- // .. .. ==> 0XF800615C[9:0] = 0x0000007FU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x0000007FU
- // .. .. reg_phy_wr_dqs_slave_force = 0x0
- // .. .. ==> 0XF800615C[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. .. ==> 0XF800615C[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x0000007FU),
- // .. .. reg_phy_wr_dqs_slave_ratio = 0x78
- // .. .. ==> 0XF8006160[9:0] = 0x00000078U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000078U
- // .. .. reg_phy_wr_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006160[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006160[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000078U),
- // .. .. reg_phy_fifo_we_slave_ratio = 0x124
- // .. .. ==> 0XF8006168[10:0] = 0x00000124U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x00000124U
- // .. .. reg_phy_fifo_we_in_force = 0x0
- // .. .. ==> 0XF8006168[11:11] = 0x00000000U
- // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. .. reg_phy_fifo_we_in_delay = 0x0
- // .. .. ==> 0XF8006168[20:12] = 0x00000000U
- // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000124U),
- // .. .. reg_phy_fifo_we_slave_ratio = 0x125
- // .. .. ==> 0XF800616C[10:0] = 0x00000125U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x00000125U
- // .. .. reg_phy_fifo_we_in_force = 0x0
- // .. .. ==> 0XF800616C[11:11] = 0x00000000U
- // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. .. reg_phy_fifo_we_in_delay = 0x0
- // .. .. ==> 0XF800616C[20:12] = 0x00000000U
- // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x00000125U),
- // .. .. reg_phy_fifo_we_slave_ratio = 0x112
- // .. .. ==> 0XF8006170[10:0] = 0x00000112U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x00000112U
- // .. .. reg_phy_fifo_we_in_force = 0x0
- // .. .. ==> 0XF8006170[11:11] = 0x00000000U
- // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. .. reg_phy_fifo_we_in_delay = 0x0
- // .. .. ==> 0XF8006170[20:12] = 0x00000000U
- // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000112U),
- // .. .. reg_phy_fifo_we_slave_ratio = 0x116
- // .. .. ==> 0XF8006174[10:0] = 0x00000116U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x00000116U
- // .. .. reg_phy_fifo_we_in_force = 0x0
- // .. .. ==> 0XF8006174[11:11] = 0x00000000U
- // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. .. reg_phy_fifo_we_in_delay = 0x0
- // .. .. ==> 0XF8006174[20:12] = 0x00000000U
- // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000116U),
- // .. .. reg_phy_wr_data_slave_ratio = 0xc3
- // .. .. ==> 0XF800617C[9:0] = 0x000000C3U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C3U
- // .. .. reg_phy_wr_data_slave_force = 0x0
- // .. .. ==> 0XF800617C[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_data_slave_delay = 0x0
- // .. .. ==> 0XF800617C[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000C3U),
- // .. .. reg_phy_wr_data_slave_ratio = 0xc3
- // .. .. ==> 0XF8006180[9:0] = 0x000000C3U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C3U
- // .. .. reg_phy_wr_data_slave_force = 0x0
- // .. .. ==> 0XF8006180[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_data_slave_delay = 0x0
- // .. .. ==> 0XF8006180[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000C3U),
- // .. .. reg_phy_wr_data_slave_ratio = 0xbf
- // .. .. ==> 0XF8006184[9:0] = 0x000000BFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000000BFU
- // .. .. reg_phy_wr_data_slave_force = 0x0
- // .. .. ==> 0XF8006184[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_data_slave_delay = 0x0
- // .. .. ==> 0XF8006184[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000BFU),
- // .. .. reg_phy_wr_data_slave_ratio = 0xb8
- // .. .. ==> 0XF8006188[9:0] = 0x000000B8U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000000B8U
- // .. .. reg_phy_wr_data_slave_force = 0x0
- // .. .. ==> 0XF8006188[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_data_slave_delay = 0x0
- // .. .. ==> 0XF8006188[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000B8U),
- // .. .. reg_phy_bl2 = 0x0
- // .. .. ==> 0XF8006190[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_at_spd_atpg = 0x0
- // .. .. ==> 0XF8006190[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_bist_enable = 0x0
- // .. .. ==> 0XF8006190[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_bist_force_err = 0x0
- // .. .. ==> 0XF8006190[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. reg_phy_bist_mode = 0x0
- // .. .. ==> 0XF8006190[6:5] = 0x00000000U
- // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. .. reg_phy_invert_clkout = 0x1
- // .. .. ==> 0XF8006190[7:7] = 0x00000001U
- // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. .. reg_phy_sel_logic = 0x0
- // .. .. ==> 0XF8006190[9:9] = 0x00000000U
- // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U
- // .. .. reg_phy_ctrl_slave_ratio = 0x100
- // .. .. ==> 0XF8006190[19:10] = 0x00000100U
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U
- // .. .. reg_phy_ctrl_slave_force = 0x0
- // .. .. ==> 0XF8006190[20:20] = 0x00000000U
- // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U
- // .. .. reg_phy_ctrl_slave_delay = 0x0
- // .. .. ==> 0XF8006190[27:21] = 0x00000000U
- // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U
- // .. .. reg_phy_lpddr = 0x0
- // .. .. ==> 0XF8006190[29:29] = 0x00000000U
- // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U
- // .. .. reg_phy_cmd_latency = 0x0
- // .. .. ==> 0XF8006190[30:30] = 0x00000000U
- // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU ,0x00040080U),
- // .. .. reg_phy_wr_rl_delay = 0x2
- // .. .. ==> 0XF8006194[4:0] = 0x00000002U
- // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U
- // .. .. reg_phy_rd_rl_delay = 0x4
- // .. .. ==> 0XF8006194[9:5] = 0x00000004U
- // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U
- // .. .. reg_phy_dll_lock_diff = 0xf
- // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
- // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U
- // .. .. reg_phy_use_wr_level = 0x1
- // .. .. ==> 0XF8006194[14:14] = 0x00000001U
- // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U
- // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
- // .. .. ==> 0XF8006194[15:15] = 0x00000001U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U
- // .. .. reg_phy_use_rd_data_eye_level = 0x1
- // .. .. ==> 0XF8006194[16:16] = 0x00000001U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U
- // .. .. reg_phy_dis_calib_rst = 0x0
- // .. .. ==> 0XF8006194[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_phy_ctrl_slave_delay = 0x0
- // .. .. ==> 0XF8006194[19:18] = 0x00000000U
- // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
- // .. .. reg_arb_page_addr_mask = 0x0
- // .. .. ==> 0XF8006204[31:0] = 0x00000000U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
- // .. .. reg_arb_pri_wr_portn = 0x3ff
- // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_wr_portn = 0x0
- // .. .. ==> 0XF8006208[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. .. ==> 0XF8006208[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. .. ==> 0XF8006208[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006208, 0x000703FFU ,0x000003FFU),
- // .. .. reg_arb_pri_wr_portn = 0x3ff
- // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_wr_portn = 0x0
- // .. .. ==> 0XF800620C[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. .. ==> 0XF800620C[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. .. ==> 0XF800620C[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800620C, 0x000703FFU ,0x000003FFU),
- // .. .. reg_arb_pri_wr_portn = 0x3ff
- // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_wr_portn = 0x0
- // .. .. ==> 0XF8006210[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. .. ==> 0XF8006210[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. .. ==> 0XF8006210[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006210, 0x000703FFU ,0x000003FFU),
- // .. .. reg_arb_pri_wr_portn = 0x3ff
- // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_wr_portn = 0x0
- // .. .. ==> 0XF8006214[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. .. ==> 0XF8006214[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. .. ==> 0XF8006214[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006214, 0x000703FFU ,0x000003FFU),
- // .. .. reg_arb_pri_rd_portn = 0x3ff
- // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_rd_portn = 0x0
- // .. .. ==> 0XF8006218[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. .. ==> 0XF8006218[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. .. ==> 0XF8006218[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_set_hpr_rd_portn = 0x0
- // .. .. ==> 0XF8006218[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
- // .. .. reg_arb_pri_rd_portn = 0x3ff
- // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_rd_portn = 0x0
- // .. .. ==> 0XF800621C[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. .. ==> 0XF800621C[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. .. ==> 0XF800621C[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_set_hpr_rd_portn = 0x0
- // .. .. ==> 0XF800621C[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
- // .. .. reg_arb_pri_rd_portn = 0x3ff
- // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_rd_portn = 0x0
- // .. .. ==> 0XF8006220[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. .. ==> 0XF8006220[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. .. ==> 0XF8006220[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_set_hpr_rd_portn = 0x0
- // .. .. ==> 0XF8006220[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
- // .. .. reg_arb_pri_rd_portn = 0x3ff
- // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_rd_portn = 0x0
- // .. .. ==> 0XF8006224[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. .. ==> 0XF8006224[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. .. ==> 0XF8006224[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_set_hpr_rd_portn = 0x0
- // .. .. ==> 0XF8006224[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
- // .. .. reg_ddrc_lpddr2 = 0x0
- // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_derate_enable = 0x0
- // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_ddrc_mr4_margin = 0x0
- // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U ,0x00000000U),
- // .. .. reg_ddrc_mr4_read_interval = 0x0
- // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
- // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
- // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U
- // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
- // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
- // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U
- // .. .. reg_ddrc_t_mrw = 0x5
- // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
- // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U
- // .. ..
- EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
- // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8
- // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U
- // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
- // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
- // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U
- // .. ..
- EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
- // .. .. START: POLL ON DCI STATUS
- // .. .. DONE = 1
- // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
- // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // .. ..
- EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
- // .. .. FINISH: POLL ON DCI STATUS
- // .. .. START: UNLOCK DDR
- // .. .. reg_ddrc_soft_rstb = 0x1
- // .. .. ==> 0XF8006000[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_ddrc_powerdown_en = 0x0
- // .. .. ==> 0XF8006000[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_ddrc_data_bus_width = 0x0
- // .. .. ==> 0XF8006000[3:2] = 0x00000000U
- // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U
- // .. .. reg_ddrc_burst8_refresh = 0x0
- // .. .. ==> 0XF8006000[6:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U
- // .. .. reg_ddrc_rdwr_idle_gap = 1
- // .. .. ==> 0XF8006000[13:7] = 0x00000001U
- // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U
- // .. .. reg_ddrc_dis_rd_bypass = 0x0
- // .. .. ==> 0XF8006000[14:14] = 0x00000000U
- // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_act_bypass = 0x0
- // .. .. ==> 0XF8006000[15:15] = 0x00000000U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_auto_refresh = 0x0
- // .. .. ==> 0XF8006000[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
- // .. .. FINISH: UNLOCK DDR
- // .. .. START: CHECK DDR STATUS
- // .. .. ddrc_reg_operating_mode = 1
- // .. .. ==> 0XF8006054[2:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U
- // .. ..
- EMIT_MASKPOLL(0XF8006054, 0x00000007U),
- // .. .. FINISH: CHECK DDR STATUS
- // .. FINISH: DDR INITIALIZATION
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_mio_init_data_3_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: OCM REMAPPING
- // .. FINISH: OCM REMAPPING
- // .. START: DDRIOB SETTINGS
- // .. reserved_INP_POWER = 0x0
- // .. ==> 0XF8000B40[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x0
- // .. ==> 0XF8000B40[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. DCI_UPDATE_B = 0x0
- // .. ==> 0XF8000B40[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x0
- // .. ==> 0XF8000B40[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. DCI_TYPE = 0x0
- // .. ==> 0XF8000B40[6:5] = 0x00000000U
- // .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. IBUF_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B40[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B40[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B40[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B40[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
- // .. reserved_INP_POWER = 0x0
- // .. ==> 0XF8000B44[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x0
- // .. ==> 0XF8000B44[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. DCI_UPDATE_B = 0x0
- // .. ==> 0XF8000B44[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x0
- // .. ==> 0XF8000B44[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. DCI_TYPE = 0x0
- // .. ==> 0XF8000B44[6:5] = 0x00000000U
- // .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. IBUF_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B44[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B44[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B44[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B44[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
- // .. reserved_INP_POWER = 0x0
- // .. ==> 0XF8000B48[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x1
- // .. ==> 0XF8000B48[2:1] = 0x00000001U
- // .. ==> MASK : 0x00000006U VAL : 0x00000002U
- // .. DCI_UPDATE_B = 0x0
- // .. ==> 0XF8000B48[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x1
- // .. ==> 0XF8000B48[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. DCI_TYPE = 0x3
- // .. ==> 0XF8000B48[6:5] = 0x00000003U
- // .. ==> MASK : 0x00000060U VAL : 0x00000060U
- // .. IBUF_DISABLE_MODE = 0
- // .. ==> 0XF8000B48[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0
- // .. ==> 0XF8000B48[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B48[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B48[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
- // .. reserved_INP_POWER = 0x0
- // .. ==> 0XF8000B4C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x1
- // .. ==> 0XF8000B4C[2:1] = 0x00000001U
- // .. ==> MASK : 0x00000006U VAL : 0x00000002U
- // .. DCI_UPDATE_B = 0x0
- // .. ==> 0XF8000B4C[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x1
- // .. ==> 0XF8000B4C[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. DCI_TYPE = 0x3
- // .. ==> 0XF8000B4C[6:5] = 0x00000003U
- // .. ==> MASK : 0x00000060U VAL : 0x00000060U
- // .. IBUF_DISABLE_MODE = 0
- // .. ==> 0XF8000B4C[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0
- // .. ==> 0XF8000B4C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B4C[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B4C[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
- // .. reserved_INP_POWER = 0x0
- // .. ==> 0XF8000B50[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x2
- // .. ==> 0XF8000B50[2:1] = 0x00000002U
- // .. ==> MASK : 0x00000006U VAL : 0x00000004U
- // .. DCI_UPDATE_B = 0x0
- // .. ==> 0XF8000B50[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x1
- // .. ==> 0XF8000B50[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. DCI_TYPE = 0x3
- // .. ==> 0XF8000B50[6:5] = 0x00000003U
- // .. ==> MASK : 0x00000060U VAL : 0x00000060U
- // .. IBUF_DISABLE_MODE = 0
- // .. ==> 0XF8000B50[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0
- // .. ==> 0XF8000B50[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B50[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B50[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
- // .. reserved_INP_POWER = 0x0
- // .. ==> 0XF8000B54[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x2
- // .. ==> 0XF8000B54[2:1] = 0x00000002U
- // .. ==> MASK : 0x00000006U VAL : 0x00000004U
- // .. DCI_UPDATE_B = 0x0
- // .. ==> 0XF8000B54[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x1
- // .. ==> 0XF8000B54[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. DCI_TYPE = 0x3
- // .. ==> 0XF8000B54[6:5] = 0x00000003U
- // .. ==> MASK : 0x00000060U VAL : 0x00000060U
- // .. IBUF_DISABLE_MODE = 0
- // .. ==> 0XF8000B54[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0
- // .. ==> 0XF8000B54[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B54[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B54[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
- // .. reserved_INP_POWER = 0x0
- // .. ==> 0XF8000B58[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x0
- // .. ==> 0XF8000B58[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. DCI_UPDATE_B = 0x0
- // .. ==> 0XF8000B58[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x0
- // .. ==> 0XF8000B58[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. DCI_TYPE = 0x0
- // .. ==> 0XF8000B58[6:5] = 0x00000000U
- // .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. IBUF_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B58[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B58[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B58[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B58[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
- // .. reserved_DRIVE_P = 0x1c
- // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
- // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
- // .. reserved_DRIVE_N = 0xc
- // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
- // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
- // .. reserved_SLEW_P = 0x3
- // .. ==> 0XF8000B5C[18:14] = 0x00000003U
- // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U
- // .. reserved_SLEW_N = 0x3
- // .. ==> 0XF8000B5C[23:19] = 0x00000003U
- // .. ==> MASK : 0x00F80000U VAL : 0x00180000U
- // .. reserved_GTL = 0x0
- // .. ==> 0XF8000B5C[26:24] = 0x00000000U
- // .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. reserved_RTERM = 0x0
- // .. ==> 0XF8000B5C[31:27] = 0x00000000U
- // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
- // .. reserved_DRIVE_P = 0x1c
- // .. ==> 0XF8000B60[6:0] = 0x0000001CU
- // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
- // .. reserved_DRIVE_N = 0xc
- // .. ==> 0XF8000B60[13:7] = 0x0000000CU
- // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
- // .. reserved_SLEW_P = 0x6
- // .. ==> 0XF8000B60[18:14] = 0x00000006U
- // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
- // .. reserved_SLEW_N = 0x1f
- // .. ==> 0XF8000B60[23:19] = 0x0000001FU
- // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
- // .. reserved_GTL = 0x0
- // .. ==> 0XF8000B60[26:24] = 0x00000000U
- // .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. reserved_RTERM = 0x0
- // .. ==> 0XF8000B60[31:27] = 0x00000000U
- // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
- // .. reserved_DRIVE_P = 0x1c
- // .. ==> 0XF8000B64[6:0] = 0x0000001CU
- // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
- // .. reserved_DRIVE_N = 0xc
- // .. ==> 0XF8000B64[13:7] = 0x0000000CU
- // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
- // .. reserved_SLEW_P = 0x6
- // .. ==> 0XF8000B64[18:14] = 0x00000006U
- // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
- // .. reserved_SLEW_N = 0x1f
- // .. ==> 0XF8000B64[23:19] = 0x0000001FU
- // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
- // .. reserved_GTL = 0x0
- // .. ==> 0XF8000B64[26:24] = 0x00000000U
- // .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. reserved_RTERM = 0x0
- // .. ==> 0XF8000B64[31:27] = 0x00000000U
- // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
- // .. reserved_DRIVE_P = 0x1c
- // .. ==> 0XF8000B68[6:0] = 0x0000001CU
- // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
- // .. reserved_DRIVE_N = 0xc
- // .. ==> 0XF8000B68[13:7] = 0x0000000CU
- // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
- // .. reserved_SLEW_P = 0x6
- // .. ==> 0XF8000B68[18:14] = 0x00000006U
- // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
- // .. reserved_SLEW_N = 0x1f
- // .. ==> 0XF8000B68[23:19] = 0x0000001FU
- // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
- // .. reserved_GTL = 0x0
- // .. ==> 0XF8000B68[26:24] = 0x00000000U
- // .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. reserved_RTERM = 0x0
- // .. ==> 0XF8000B68[31:27] = 0x00000000U
- // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
- // .. VREF_INT_EN = 0x1
- // .. ==> 0XF8000B6C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. VREF_SEL = 0x4
- // .. ==> 0XF8000B6C[4:1] = 0x00000004U
- // .. ==> MASK : 0x0000001EU VAL : 0x00000008U
- // .. VREF_EXT_EN = 0x0
- // .. ==> 0XF8000B6C[6:5] = 0x00000000U
- // .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. reserved_VREF_PULLUP_EN = 0x0
- // .. ==> 0XF8000B6C[8:7] = 0x00000000U
- // .. ==> MASK : 0x00000180U VAL : 0x00000000U
- // .. REFIO_EN = 0x1
- // .. ==> 0XF8000B6C[9:9] = 0x00000001U
- // .. ==> MASK : 0x00000200U VAL : 0x00000200U
- // .. reserved_REFIO_TEST = 0x3
- // .. ==> 0XF8000B6C[11:10] = 0x00000003U
- // .. ==> MASK : 0x00000C00U VAL : 0x00000C00U
- // .. reserved_REFIO_PULLUP_EN = 0x0
- // .. ==> 0XF8000B6C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. reserved_DRST_B_PULLUP_EN = 0x0
- // .. ==> 0XF8000B6C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // .. reserved_CKE_PULLUP_EN = 0x0
- // .. ==> 0XF8000B6C[14:14] = 0x00000000U
- // .. ==> MASK : 0x00004000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000E09U),
- // .. .. START: ASSERT RESET
- // .. .. RESET = 1
- // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. ..
- EMIT_MASKWRITE(0XF8000B70, 0x00000001U ,0x00000001U),
- // .. .. FINISH: ASSERT RESET
- // .. .. START: DEASSERT RESET
- // .. .. RESET = 0
- // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reserved_VRN_OUT = 0x1
- // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
- // .. ..
- EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
- // .. .. FINISH: DEASSERT RESET
- // .. .. RESET = 0x1
- // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ENABLE = 0x1
- // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. .. reserved_VRP_TRI = 0x0
- // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reserved_VRN_TRI = 0x0
- // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reserved_VRP_OUT = 0x0
- // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. reserved_VRN_OUT = 0x1
- // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
- // .. .. NREF_OPT1 = 0x0
- // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
- // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U
- // .. .. NREF_OPT2 = 0x0
- // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U
- // .. .. NREF_OPT4 = 0x1
- // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
- // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U
- // .. .. PREF_OPT1 = 0x0
- // .. .. ==> 0XF8000B70[15:14] = 0x00000000U
- // .. .. ==> MASK : 0x0000C000U VAL : 0x00000000U
- // .. .. PREF_OPT2 = 0x0
- // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
- // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U
- // .. .. UPDATE_CONTROL = 0x0
- // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
- // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U
- // .. .. reserved_INIT_COMPLETE = 0x0
- // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
- // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U
- // .. .. reserved_TST_CLK = 0x0
- // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
- // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U
- // .. .. reserved_TST_HLN = 0x0
- // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
- // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U
- // .. .. reserved_TST_HLP = 0x0
- // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
- // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U
- // .. .. reserved_TST_RST = 0x0
- // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
- // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
- // .. .. reserved_INT_DCI_EN = 0x0
- // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
- // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU ,0x00000823U),
- // .. FINISH: DDRIOB SETTINGS
- // .. START: MIO PROGRAMMING
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000700[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000700[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000700[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000700[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000700[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000700[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000700[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000700[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000700[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00000600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000704[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000704[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000704[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000704[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000704[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000704[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 3
- // .. ==> 0XF8000704[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000704[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000704[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00000702U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000708[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000708[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000708[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000708[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000708[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000708[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 3
- // .. ==> 0XF8000708[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000708[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000708[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000702U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800070C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF800070C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF800070C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800070C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800070C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF800070C[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 3
- // .. ==> 0XF800070C[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF800070C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800070C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000702U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000710[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000710[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000710[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000710[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000710[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000710[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 3
- // .. ==> 0XF8000710[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000710[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000710[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000702U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000714[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000714[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000714[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000714[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000714[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000714[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 3
- // .. ==> 0XF8000714[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000714[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000714[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000702U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000718[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000718[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000718[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000718[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000718[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000718[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 3
- // .. ==> 0XF8000718[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000718[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000718[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000702U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800071C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800071C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF800071C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800071C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800071C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800071C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF800071C[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF800071C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800071C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000720[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000720[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000720[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000720[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000720[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000720[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 3
- // .. ==> 0XF8000720[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000720[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000720[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000700U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000724[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000724[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000724[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000724[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000724[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000724[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000724[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000724[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000724[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00000600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000728[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000728[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000728[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000728[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000728[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000728[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000728[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000728[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000728[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00000600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800072C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800072C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF800072C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800072C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800072C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800072C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF800072C[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF800072C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800072C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00000600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000730[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000730[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000730[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000730[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000730[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000730[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000730[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000730[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000730[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00000600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000734[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000734[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000734[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000734[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000734[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000734[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000734[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000734[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000734[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00000600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000738[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000738[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000738[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000738[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000738[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000738[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000738[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000738[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000738[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00000600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800073C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800073C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF800073C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800073C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800073C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800073C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF800073C[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF800073C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800073C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00000600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000740[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000740[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000740[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000740[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000740[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000740[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000740[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000740[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000740[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000302U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000744[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000744[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000744[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000744[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000744[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000744[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000744[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000744[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000744[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000302U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000748[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000748[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000748[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000748[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000748[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000748[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000748[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000748[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000748[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000302U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800074C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF800074C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF800074C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800074C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800074C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF800074C[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF800074C[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF800074C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800074C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000302U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000750[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000750[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000750[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000750[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000750[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000750[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000750[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000750[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000750[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000302U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000754[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000754[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000754[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000754[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000754[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000754[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000754[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000754[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000754[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000302U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000758[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF8000758[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000758[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000758[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000758[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000758[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000758[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000758[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000758[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000303U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF800075C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF800075C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF800075C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800075C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800075C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF800075C[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF800075C[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF800075C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800075C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000303U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000760[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF8000760[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000760[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000760[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000760[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000760[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000760[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000760[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000760[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000303U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000764[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF8000764[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000764[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000764[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000764[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000764[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000764[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000764[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000764[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000303U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000768[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF8000768[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000768[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000768[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000768[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000768[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000768[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000768[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000768[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000303U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF800076C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF800076C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF800076C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800076C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800076C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF800076C[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF800076C[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF800076C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800076C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000303U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000770[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000770[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000770[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000770[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000770[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000770[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000770[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000770[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000770[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000304U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000774[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF8000774[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000774[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000774[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000774[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000774[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000774[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000774[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000774[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000305U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000778[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000778[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000778[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000778[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000778[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000778[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000778[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000778[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000778[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000304U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF800077C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF800077C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF800077C[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF800077C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800077C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF800077C[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF800077C[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF800077C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800077C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000305U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000780[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000780[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000780[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000780[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000780[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000780[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000780[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000780[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000780[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000304U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000784[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000784[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000784[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000784[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000784[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000784[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000784[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000784[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000784[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000304U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000788[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000788[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000788[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000788[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000788[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000788[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000788[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000788[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000788[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000304U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800078C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800078C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF800078C[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF800078C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800078C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF800078C[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF800078C[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF800078C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800078C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000304U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000790[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF8000790[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000790[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000790[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000790[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000790[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000790[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000790[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000790[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000305U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000794[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000794[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000794[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000794[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000794[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000794[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000794[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000794[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000794[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000304U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000798[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000798[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000798[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000798[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000798[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000798[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000798[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000798[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000798[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000304U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800079C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800079C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF800079C[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF800079C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800079C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF800079C[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF800079C[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF800079C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800079C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000304U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007A0[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007A0[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007A0[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007A0[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007A0[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 1
- // .. ==> 0XF80007A0[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF80007A0[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007A0[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007A0[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000380U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007A4[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007A4[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007A4[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007A4[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007A4[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 1
- // .. ==> 0XF80007A4[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF80007A4[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007A4[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007A4[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000380U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007A8[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007A8[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007A8[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007A8[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007A8[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 1
- // .. ==> 0XF80007A8[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF80007A8[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007A8[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007A8[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000380U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007AC[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007AC[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007AC[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007AC[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007AC[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 1
- // .. ==> 0XF80007AC[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF80007AC[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007AC[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007AC[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000380U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007B0[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007B0[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007B0[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007B0[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007B0[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 1
- // .. ==> 0XF80007B0[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF80007B0[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007B0[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007B0[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000380U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007B4[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007B4[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007B4[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007B4[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007B4[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 1
- // .. ==> 0XF80007B4[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF80007B4[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007B4[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007B4[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000380U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF80007B8[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. Speed = 0
- // .. ==> 0XF80007B8[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007B8[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007B8[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007B8[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007B8, 0x00003F01U ,0x00000201U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF80007BC[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. Speed = 0
- // .. ==> 0XF80007BC[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007BC[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007BC[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007BC[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007BC, 0x00003F01U ,0x00000201U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007C0[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007C0[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007C0[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007C0[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 7
- // .. ==> 0XF80007C0[7:5] = 0x00000007U
- // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U
- // .. Speed = 0
- // .. ==> 0XF80007C0[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007C0[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007C0[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007C0[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF80007C4[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF80007C4[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007C4[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007C4[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 7
- // .. ==> 0XF80007C4[7:5] = 0x00000007U
- // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U
- // .. Speed = 0
- // .. ==> 0XF80007C4[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007C4[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007C4[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007C4[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF80007C8[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF80007C8[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007C8[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007C8[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF80007C8[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF80007C8[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007C8[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007C8[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007C8[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00000201U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF80007CC[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF80007CC[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007CC[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007CC[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF80007CC[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF80007CC[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007CC[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007CC[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007CC[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00000201U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007D0[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007D0[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007D0[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007D0[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007D0[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF80007D0[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007D0[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007D0[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007D0[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007D4[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007D4[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007D4[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007D4[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007D4[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF80007D4[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007D4[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007D4[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007D4[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U),
- // .. SDIO0_WP_SEL = 46
- // .. ==> 0XF8000830[5:0] = 0x0000002EU
- // .. ==> MASK : 0x0000003FU VAL : 0x0000002EU
- // .. SDIO0_CD_SEL = 47
- // .. ==> 0XF8000830[21:16] = 0x0000002FU
- // .. ==> MASK : 0x003F0000U VAL : 0x002F0000U
- // ..
- EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x002F002EU),
- // .. FINISH: MIO PROGRAMMING
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_peripherals_init_data_3_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
- // .. IBUF_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B48[7:7] = 0x00000001U
- // .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. TERM_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B48[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // ..
- EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
- // .. IBUF_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B4C[7:7] = 0x00000001U
- // .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. TERM_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B4C[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // ..
- EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
- // .. IBUF_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B50[7:7] = 0x00000001U
- // .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. TERM_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B50[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // ..
- EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
- // .. IBUF_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B54[7:7] = 0x00000001U
- // .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. TERM_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B54[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // ..
- EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
- // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // .. START: SRAM/NOR SET OPMODE
- // .. FINISH: SRAM/NOR SET OPMODE
- // .. START: UART REGISTERS
- // .. BDIV = 0x6
- // .. ==> 0XE0001034[7:0] = 0x00000006U
- // .. ==> MASK : 0x000000FFU VAL : 0x00000006U
- // ..
- EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
- // .. CD = 0x3e
- // .. ==> 0XE0001018[15:0] = 0x0000003EU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU
- // ..
- EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
- // .. STPBRK = 0x0
- // .. ==> 0XE0001000[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. STTBRK = 0x0
- // .. ==> 0XE0001000[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. RSTTO = 0x0
- // .. ==> 0XE0001000[6:6] = 0x00000000U
- // .. ==> MASK : 0x00000040U VAL : 0x00000000U
- // .. TXDIS = 0x0
- // .. ==> 0XE0001000[5:5] = 0x00000000U
- // .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. TXEN = 0x1
- // .. ==> 0XE0001000[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. RXDIS = 0x0
- // .. ==> 0XE0001000[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. RXEN = 0x1
- // .. ==> 0XE0001000[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. TXRES = 0x1
- // .. ==> 0XE0001000[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. RXRES = 0x1
- // .. ==> 0XE0001000[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // ..
- EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
- // .. CHMODE = 0x0
- // .. ==> 0XE0001004[9:8] = 0x00000000U
- // .. ==> MASK : 0x00000300U VAL : 0x00000000U
- // .. NBSTOP = 0x0
- // .. ==> 0XE0001004[7:6] = 0x00000000U
- // .. ==> MASK : 0x000000C0U VAL : 0x00000000U
- // .. PAR = 0x4
- // .. ==> 0XE0001004[5:3] = 0x00000004U
- // .. ==> MASK : 0x00000038U VAL : 0x00000020U
- // .. CHRL = 0x0
- // .. ==> 0XE0001004[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. CLKS = 0x0
- // .. ==> 0XE0001004[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XE0001004, 0x000003FFU ,0x00000020U),
- // .. FINISH: UART REGISTERS
- // .. START: QSPI REGISTERS
- // .. Holdb_dr = 1
- // .. ==> 0XE000D000[19:19] = 0x00000001U
- // .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // ..
- EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
- // .. FINISH: QSPI REGISTERS
- // .. START: PL POWER ON RESET REGISTERS
- // .. PCFG_POR_CNT_4K = 0
- // .. ==> 0XF8007000[29:29] = 0x00000000U
- // .. ==> MASK : 0x20000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
- // .. FINISH: PL POWER ON RESET REGISTERS
- // .. START: SMC TIMING CALCULATION REGISTER UPDATE
- // .. .. START: NAND SET CYCLE
- // .. .. FINISH: NAND SET CYCLE
- // .. .. START: OPMODE
- // .. .. FINISH: OPMODE
- // .. .. START: DIRECT COMMAND
- // .. .. FINISH: DIRECT COMMAND
- // .. .. START: SRAM/NOR CS0 SET CYCLE
- // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
- // .. .. START: DIRECT COMMAND
- // .. .. FINISH: DIRECT COMMAND
- // .. .. START: NOR CS0 BASE ADDRESS
- // .. .. FINISH: NOR CS0 BASE ADDRESS
- // .. .. START: SRAM/NOR CS1 SET CYCLE
- // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
- // .. .. START: DIRECT COMMAND
- // .. .. FINISH: DIRECT COMMAND
- // .. .. START: NOR CS1 BASE ADDRESS
- // .. .. FINISH: NOR CS1 BASE ADDRESS
- // .. .. START: USB RESET
- // .. .. .. START: USB0 RESET
- // .. .. .. .. START: DIR MODE BANK 0
- // .. .. .. .. FINISH: DIR MODE BANK 0
- // .. .. .. .. START: DIR MODE BANK 1
- // .. .. .. .. FINISH: DIR MODE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. START: OUTPUT ENABLE BANK 0
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
- // .. .. .. .. START: OUTPUT ENABLE BANK 1
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. START: ADD 1 MS DELAY
- // .. .. .. ..
- EMIT_MASKDELAY(0XF8F00200, 1),
- // .. .. .. .. FINISH: ADD 1 MS DELAY
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: USB0 RESET
- // .. .. .. START: USB1 RESET
- // .. .. .. .. START: DIR MODE BANK 0
- // .. .. .. .. FINISH: DIR MODE BANK 0
- // .. .. .. .. START: DIR MODE BANK 1
- // .. .. .. .. FINISH: DIR MODE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. START: OUTPUT ENABLE BANK 0
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
- // .. .. .. .. START: OUTPUT ENABLE BANK 1
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. START: ADD 1 MS DELAY
- // .. .. .. ..
- EMIT_MASKDELAY(0XF8F00200, 1),
- // .. .. .. .. FINISH: ADD 1 MS DELAY
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: USB1 RESET
- // .. .. FINISH: USB RESET
- // .. .. START: ENET RESET
- // .. .. .. START: ENET0 RESET
- // .. .. .. .. START: DIR MODE BANK 0
- // .. .. .. .. FINISH: DIR MODE BANK 0
- // .. .. .. .. START: DIR MODE BANK 1
- // .. .. .. .. FINISH: DIR MODE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. START: OUTPUT ENABLE BANK 0
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
- // .. .. .. .. START: OUTPUT ENABLE BANK 1
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. START: ADD 1 MS DELAY
- // .. .. .. ..
- EMIT_MASKDELAY(0XF8F00200, 1),
- // .. .. .. .. FINISH: ADD 1 MS DELAY
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: ENET0 RESET
- // .. .. .. START: ENET1 RESET
- // .. .. .. .. START: DIR MODE BANK 0
- // .. .. .. .. FINISH: DIR MODE BANK 0
- // .. .. .. .. START: DIR MODE BANK 1
- // .. .. .. .. FINISH: DIR MODE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. START: OUTPUT ENABLE BANK 0
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
- // .. .. .. .. START: OUTPUT ENABLE BANK 1
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. START: ADD 1 MS DELAY
- // .. .. .. ..
- EMIT_MASKDELAY(0XF8F00200, 1),
- // .. .. .. .. FINISH: ADD 1 MS DELAY
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: ENET1 RESET
- // .. .. FINISH: ENET RESET
- // .. .. START: I2C RESET
- // .. .. .. START: I2C0 RESET
- // .. .. .. .. START: DIR MODE GPIO BANK0
- // .. .. .. .. FINISH: DIR MODE GPIO BANK0
- // .. .. .. .. START: DIR MODE GPIO BANK1
- // .. .. .. .. FINISH: DIR MODE GPIO BANK1
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. START: OUTPUT ENABLE
- // .. .. .. .. FINISH: OUTPUT ENABLE
- // .. .. .. .. START: OUTPUT ENABLE
- // .. .. .. .. FINISH: OUTPUT ENABLE
- // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. START: ADD 1 MS DELAY
- // .. .. .. ..
- EMIT_MASKDELAY(0XF8F00200, 1),
- // .. .. .. .. FINISH: ADD 1 MS DELAY
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: I2C0 RESET
- // .. .. .. START: I2C1 RESET
- // .. .. .. .. START: DIR MODE GPIO BANK0
- // .. .. .. .. FINISH: DIR MODE GPIO BANK0
- // .. .. .. .. START: DIR MODE GPIO BANK1
- // .. .. .. .. FINISH: DIR MODE GPIO BANK1
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. START: OUTPUT ENABLE
- // .. .. .. .. FINISH: OUTPUT ENABLE
- // .. .. .. .. START: OUTPUT ENABLE
- // .. .. .. .. FINISH: OUTPUT ENABLE
- // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. START: ADD 1 MS DELAY
- // .. .. .. ..
- EMIT_MASKDELAY(0XF8F00200, 1),
- // .. .. .. .. FINISH: ADD 1 MS DELAY
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: I2C1 RESET
- // .. .. FINISH: I2C RESET
- // .. .. START: NOR CHIP SELECT
- // .. .. .. START: DIR MODE BANK 0
- // .. .. .. FINISH: DIR MODE BANK 0
- // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. START: OUTPUT ENABLE BANK 0
- // .. .. .. FINISH: OUTPUT ENABLE BANK 0
- // .. .. FINISH: NOR CHIP SELECT
- // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_post_config_3_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: ENABLING LEVEL SHIFTER
- // .. USER_LVL_INP_EN_0 = 1
- // .. ==> 0XF8000900[3:3] = 0x00000001U
- // .. ==> MASK : 0x00000008U VAL : 0x00000008U
- // .. USER_LVL_OUT_EN_0 = 1
- // .. ==> 0XF8000900[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. USER_LVL_INP_EN_1 = 1
- // .. ==> 0XF8000900[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. USER_LVL_OUT_EN_1 = 1
- // .. ==> 0XF8000900[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // ..
- EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
- // .. FINISH: ENABLING LEVEL SHIFTER
- // .. START: FPGA RESETS TO 0
- // .. reserved_3 = 0
- // .. ==> 0XF8000240[31:25] = 0x00000000U
- // .. ==> MASK : 0xFE000000U VAL : 0x00000000U
- // .. reserved_FPGA_ACP_RST = 0
- // .. ==> 0XF8000240[24:24] = 0x00000000U
- // .. ==> MASK : 0x01000000U VAL : 0x00000000U
- // .. reserved_FPGA_AXDS3_RST = 0
- // .. ==> 0XF8000240[23:23] = 0x00000000U
- // .. ==> MASK : 0x00800000U VAL : 0x00000000U
- // .. reserved_FPGA_AXDS2_RST = 0
- // .. ==> 0XF8000240[22:22] = 0x00000000U
- // .. ==> MASK : 0x00400000U VAL : 0x00000000U
- // .. reserved_FPGA_AXDS1_RST = 0
- // .. ==> 0XF8000240[21:21] = 0x00000000U
- // .. ==> MASK : 0x00200000U VAL : 0x00000000U
- // .. reserved_FPGA_AXDS0_RST = 0
- // .. ==> 0XF8000240[20:20] = 0x00000000U
- // .. ==> MASK : 0x00100000U VAL : 0x00000000U
- // .. reserved_2 = 0
- // .. ==> 0XF8000240[19:18] = 0x00000000U
- // .. ==> MASK : 0x000C0000U VAL : 0x00000000U
- // .. reserved_FSSW1_FPGA_RST = 0
- // .. ==> 0XF8000240[17:17] = 0x00000000U
- // .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. reserved_FSSW0_FPGA_RST = 0
- // .. ==> 0XF8000240[16:16] = 0x00000000U
- // .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. reserved_1 = 0
- // .. ==> 0XF8000240[15:14] = 0x00000000U
- // .. ==> MASK : 0x0000C000U VAL : 0x00000000U
- // .. reserved_FPGA_FMSW1_RST = 0
- // .. ==> 0XF8000240[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // .. reserved_FPGA_FMSW0_RST = 0
- // .. ==> 0XF8000240[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. reserved_FPGA_DMA3_RST = 0
- // .. ==> 0XF8000240[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. reserved_FPGA_DMA2_RST = 0
- // .. ==> 0XF8000240[10:10] = 0x00000000U
- // .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. reserved_FPGA_DMA1_RST = 0
- // .. ==> 0XF8000240[9:9] = 0x00000000U
- // .. ==> MASK : 0x00000200U VAL : 0x00000000U
- // .. reserved_FPGA_DMA0_RST = 0
- // .. ==> 0XF8000240[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. reserved = 0
- // .. ==> 0XF8000240[7:4] = 0x00000000U
- // .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. FPGA3_OUT_RST = 0
- // .. ==> 0XF8000240[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. FPGA2_OUT_RST = 0
- // .. ==> 0XF8000240[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. FPGA1_OUT_RST = 0
- // .. ==> 0XF8000240[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. FPGA0_OUT_RST = 0
- // .. ==> 0XF8000240[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
- // .. FINISH: FPGA RESETS TO 0
- // .. START: AFI REGISTERS
- // .. .. START: AFI0 REGISTERS
- // .. .. FINISH: AFI0 REGISTERS
- // .. .. START: AFI1 REGISTERS
- // .. .. FINISH: AFI1 REGISTERS
- // .. .. START: AFI2 REGISTERS
- // .. .. FINISH: AFI2 REGISTERS
- // .. .. START: AFI3 REGISTERS
- // .. .. FINISH: AFI3 REGISTERS
- // .. FINISH: AFI REGISTERS
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_debug_3_0[] = {
- // START: top
- // .. START: CROSS TRIGGER CONFIGURATIONS
- // .. .. START: UNLOCKING CTI REGISTERS
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. FINISH: UNLOCKING CTI REGISTERS
- // .. .. START: ENABLING CTI MODULES AND CHANNELS
- // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
- // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. FINISH: CROSS TRIGGER CONFIGURATIONS
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_pll_init_data_2_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: PLL SLCR REGISTERS
- // .. .. START: ARM PLL INIT
- // .. .. PLL_RES = 0x2
- // .. .. ==> 0XF8000110[7:4] = 0x00000002U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
- // .. .. PLL_CP = 0x2
- // .. .. ==> 0XF8000110[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. LOCK_CNT = 0xfa
- // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
- // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U
- // .. ..
- EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
- // .. .. .. START: UPDATE FB_DIV
- // .. .. .. PLL_FDIV = 0x28
- // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
- // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
- // .. .. .. FINISH: UPDATE FB_DIV
- // .. .. .. START: BY PASS PLL
- // .. .. .. PLL_BYPASS_FORCE = 1
- // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
- // .. .. .. FINISH: BY PASS PLL
- // .. .. .. START: ASSERT RESET
- // .. .. .. PLL_RESET = 1
- // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
- // .. .. .. FINISH: ASSERT RESET
- // .. .. .. START: DEASSERT RESET
- // .. .. .. PLL_RESET = 0
- // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
- // .. .. .. FINISH: DEASSERT RESET
- // .. .. .. START: CHECK PLL STATUS
- // .. .. .. ARM_PLL_LOCK = 1
- // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ..
- EMIT_MASKPOLL(0XF800010C, 0x00000001U),
- // .. .. .. FINISH: CHECK PLL STATUS
- // .. .. .. START: REMOVE PLL BY PASS
- // .. .. .. PLL_BYPASS_FORCE = 0
- // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
- // .. .. .. FINISH: REMOVE PLL BY PASS
- // .. .. .. SRCSEL = 0x0
- // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. .. .. DIVISOR = 0x2
- // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
- // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U
- // .. .. .. CPU_6OR4XCLKACT = 0x1
- // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
- // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U
- // .. .. .. CPU_3OR2XCLKACT = 0x1
- // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
- // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U
- // .. .. .. CPU_2XCLKACT = 0x1
- // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
- // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U
- // .. .. .. CPU_1XCLKACT = 0x1
- // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
- // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U
- // .. .. .. CPU_PERI_CLKACT = 0x1
- // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
- // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
- // .. .. FINISH: ARM PLL INIT
- // .. .. START: DDR PLL INIT
- // .. .. PLL_RES = 0x2
- // .. .. ==> 0XF8000114[7:4] = 0x00000002U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
- // .. .. PLL_CP = 0x2
- // .. .. ==> 0XF8000114[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. LOCK_CNT = 0x12c
- // .. .. ==> 0XF8000114[21:12] = 0x0000012CU
- // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U
- // .. ..
- EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
- // .. .. .. START: UPDATE FB_DIV
- // .. .. .. PLL_FDIV = 0x20
- // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
- // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
- // .. .. .. FINISH: UPDATE FB_DIV
- // .. .. .. START: BY PASS PLL
- // .. .. .. PLL_BYPASS_FORCE = 1
- // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
- // .. .. .. FINISH: BY PASS PLL
- // .. .. .. START: ASSERT RESET
- // .. .. .. PLL_RESET = 1
- // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
- // .. .. .. FINISH: ASSERT RESET
- // .. .. .. START: DEASSERT RESET
- // .. .. .. PLL_RESET = 0
- // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
- // .. .. .. FINISH: DEASSERT RESET
- // .. .. .. START: CHECK PLL STATUS
- // .. .. .. DDR_PLL_LOCK = 1
- // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. .. ..
- EMIT_MASKPOLL(0XF800010C, 0x00000002U),
- // .. .. .. FINISH: CHECK PLL STATUS
- // .. .. .. START: REMOVE PLL BY PASS
- // .. .. .. PLL_BYPASS_FORCE = 0
- // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
- // .. .. .. FINISH: REMOVE PLL BY PASS
- // .. .. .. DDR_3XCLKACT = 0x1
- // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. .. DDR_2XCLKACT = 0x1
- // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. .. .. DDR_3XCLK_DIVISOR = 0x2
- // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
- // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U
- // .. .. .. DDR_2XCLK_DIVISOR = 0x3
- // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
- // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
- // .. .. FINISH: DDR PLL INIT
- // .. .. START: IO PLL INIT
- // .. .. PLL_RES = 0xc
- // .. .. ==> 0XF8000118[7:4] = 0x0000000CU
- // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U
- // .. .. PLL_CP = 0x2
- // .. .. ==> 0XF8000118[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. LOCK_CNT = 0x145
- // .. .. ==> 0XF8000118[21:12] = 0x00000145U
- // .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U
- // .. ..
- EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U),
- // .. .. .. START: UPDATE FB_DIV
- // .. .. .. PLL_FDIV = 0x1e
- // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU
- // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U),
- // .. .. .. FINISH: UPDATE FB_DIV
- // .. .. .. START: BY PASS PLL
- // .. .. .. PLL_BYPASS_FORCE = 1
- // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
- // .. .. .. FINISH: BY PASS PLL
- // .. .. .. START: ASSERT RESET
- // .. .. .. PLL_RESET = 1
- // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
- // .. .. .. FINISH: ASSERT RESET
- // .. .. .. START: DEASSERT RESET
- // .. .. .. PLL_RESET = 0
- // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
- // .. .. .. FINISH: DEASSERT RESET
- // .. .. .. START: CHECK PLL STATUS
- // .. .. .. IO_PLL_LOCK = 1
- // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. .. ..
- EMIT_MASKPOLL(0XF800010C, 0x00000004U),
- // .. .. .. FINISH: CHECK PLL STATUS
- // .. .. .. START: REMOVE PLL BY PASS
- // .. .. .. PLL_BYPASS_FORCE = 0
- // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
- // .. .. .. FINISH: REMOVE PLL BY PASS
- // .. .. FINISH: IO PLL INIT
- // .. FINISH: PLL SLCR REGISTERS
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_clock_init_data_2_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: CLOCK CONTROL SLCR REGISTERS
- // .. CLKACT = 0x1
- // .. ==> 0XF8000128[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. DIVISOR0 = 0x23
- // .. ==> 0XF8000128[13:8] = 0x00000023U
- // .. ==> MASK : 0x00003F00U VAL : 0x00002300U
- // .. DIVISOR1 = 0x3
- // .. ==> 0XF8000128[25:20] = 0x00000003U
- // .. ==> MASK : 0x03F00000U VAL : 0x00300000U
- // ..
- EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U),
- // .. CLKACT = 0x1
- // .. ==> 0XF8000138[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000138[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
- // .. CLKACT = 0x1
- // .. ==> 0XF8000140[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000140[6:4] = 0x00000000U
- // .. ==> MASK : 0x00000070U VAL : 0x00000000U
- // .. DIVISOR = 0x8
- // .. ==> 0XF8000140[13:8] = 0x00000008U
- // .. ==> MASK : 0x00003F00U VAL : 0x00000800U
- // .. DIVISOR1 = 0x1
- // .. ==> 0XF8000140[25:20] = 0x00000001U
- // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
- // ..
- EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U),
- // .. CLKACT = 0x1
- // .. ==> 0XF800014C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. SRCSEL = 0x0
- // .. ==> 0XF800014C[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR = 0x5
- // .. ==> 0XF800014C[13:8] = 0x00000005U
- // .. ==> MASK : 0x00003F00U VAL : 0x00000500U
- // ..
- EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
- // .. CLKACT0 = 0x1
- // .. ==> 0XF8000150[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. CLKACT1 = 0x0
- // .. ==> 0XF8000150[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000150[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR = 0x14
- // .. ==> 0XF8000150[13:8] = 0x00000014U
- // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
- // ..
- EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U),
- // .. CLKACT0 = 0x0
- // .. ==> 0XF8000154[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. CLKACT1 = 0x1
- // .. ==> 0XF8000154[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000154[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR = 0x14
- // .. ==> 0XF8000154[13:8] = 0x00000014U
- // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
- // ..
- EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U),
- // .. CLKACT = 0x1
- // .. ==> 0XF8000168[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000168[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR = 0x5
- // .. ==> 0XF8000168[13:8] = 0x00000005U
- // .. ==> MASK : 0x00003F00U VAL : 0x00000500U
- // ..
- EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000170[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR0 = 0xa
- // .. ==> 0XF8000170[13:8] = 0x0000000AU
- // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U
- // .. DIVISOR1 = 0x1
- // .. ==> 0XF8000170[25:20] = 0x00000001U
- // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
- // ..
- EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00100A00U),
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000180[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR0 = 0x7
- // .. ==> 0XF8000180[13:8] = 0x00000007U
- // .. ==> MASK : 0x00003F00U VAL : 0x00000700U
- // .. DIVISOR1 = 0x1
- // .. ==> 0XF8000180[25:20] = 0x00000001U
- // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
- // ..
- EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00100700U),
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000190[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR0 = 0x14
- // .. ==> 0XF8000190[13:8] = 0x00000014U
- // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
- // .. DIVISOR1 = 0x1
- // .. ==> 0XF8000190[25:20] = 0x00000001U
- // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
- // ..
- EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101400U),
- // .. SRCSEL = 0x0
- // .. ==> 0XF80001A0[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR0 = 0x14
- // .. ==> 0XF80001A0[13:8] = 0x00000014U
- // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
- // .. DIVISOR1 = 0x1
- // .. ==> 0XF80001A0[25:20] = 0x00000001U
- // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
- // ..
- EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U),
- // .. CLK_621_TRUE = 0x1
- // .. ==> 0XF80001C4[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // ..
- EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
- // .. DMA_CPU_2XCLKACT = 0x1
- // .. ==> 0XF800012C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. USB0_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. USB1_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[3:3] = 0x00000001U
- // .. ==> MASK : 0x00000008U VAL : 0x00000008U
- // .. GEM0_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[6:6] = 0x00000001U
- // .. ==> MASK : 0x00000040U VAL : 0x00000040U
- // .. GEM1_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. SDI0_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[10:10] = 0x00000001U
- // .. ==> MASK : 0x00000400U VAL : 0x00000400U
- // .. SDI1_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. SPI0_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[14:14] = 0x00000000U
- // .. ==> MASK : 0x00004000U VAL : 0x00000000U
- // .. SPI1_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[15:15] = 0x00000000U
- // .. ==> MASK : 0x00008000U VAL : 0x00000000U
- // .. CAN0_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[16:16] = 0x00000000U
- // .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. CAN1_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[17:17] = 0x00000000U
- // .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. I2C0_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[18:18] = 0x00000001U
- // .. ==> MASK : 0x00040000U VAL : 0x00040000U
- // .. I2C1_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[19:19] = 0x00000001U
- // .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // .. UART0_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[20:20] = 0x00000000U
- // .. ==> MASK : 0x00100000U VAL : 0x00000000U
- // .. UART1_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[21:21] = 0x00000001U
- // .. ==> MASK : 0x00200000U VAL : 0x00200000U
- // .. GPIO_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[22:22] = 0x00000001U
- // .. ==> MASK : 0x00400000U VAL : 0x00400000U
- // .. LQSPI_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[23:23] = 0x00000001U
- // .. ==> MASK : 0x00800000U VAL : 0x00800000U
- // .. SMC_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[24:24] = 0x00000001U
- // .. ==> MASK : 0x01000000U VAL : 0x01000000U
- // ..
- EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC044DU),
- // .. FINISH: CLOCK CONTROL SLCR REGISTERS
- // .. START: THIS SHOULD BE BLANK
- // .. FINISH: THIS SHOULD BE BLANK
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_ddr_init_data_2_0[] = {
- // START: top
- // .. START: DDR INITIALIZATION
- // .. .. START: LOCK DDR
- // .. .. reg_ddrc_soft_rstb = 0
- // .. .. ==> 0XF8006000[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_powerdown_en = 0x0
- // .. .. ==> 0XF8006000[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_ddrc_data_bus_width = 0x0
- // .. .. ==> 0XF8006000[3:2] = 0x00000000U
- // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U
- // .. .. reg_ddrc_burst8_refresh = 0x0
- // .. .. ==> 0XF8006000[6:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U
- // .. .. reg_ddrc_rdwr_idle_gap = 0x1
- // .. .. ==> 0XF8006000[13:7] = 0x00000001U
- // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U
- // .. .. reg_ddrc_dis_rd_bypass = 0x0
- // .. .. ==> 0XF8006000[14:14] = 0x00000000U
- // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_act_bypass = 0x0
- // .. .. ==> 0XF8006000[15:15] = 0x00000000U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_auto_refresh = 0x0
- // .. .. ==> 0XF8006000[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
- // .. .. FINISH: LOCK DDR
- // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81
- // .. .. ==> 0XF8006004[11:0] = 0x00000081U
- // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U
- // .. .. reg_ddrc_active_ranks = 0x1
- // .. .. ==> 0XF8006004[13:12] = 0x00000001U
- // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U
- // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
- // .. .. ==> 0XF8006004[18:14] = 0x00000000U
- // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U
- // .. .. reg_ddrc_wr_odt_block = 0x1
- // .. .. ==> 0XF8006004[20:19] = 0x00000001U
- // .. .. ==> MASK : 0x00180000U VAL : 0x00080000U
- // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0
- // .. .. ==> 0XF8006004[21:21] = 0x00000000U
- // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0
- // .. .. ==> 0XF8006004[26:22] = 0x00000000U
- // .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_open_bank = 0x0
- // .. .. ==> 0XF8006004[27:27] = 0x00000000U
- // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_4bank_ram = 0x0
- // .. .. ==> 0XF8006004[28:28] = 0x00000000U
- // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U),
- // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
- // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
- // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU
- // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
- // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
- // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U
- // .. .. reg_ddrc_hpr_xact_run_length = 0xf
- // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
- // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U
- // .. ..
- EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
- // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
- // .. .. ==> 0XF800600C[10:0] = 0x00000001U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U
- // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
- // .. .. ==> 0XF800600C[21:11] = 0x00000002U
- // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U
- // .. .. reg_ddrc_lpr_xact_run_length = 0x8
- // .. .. ==> 0XF800600C[25:22] = 0x00000008U
- // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U
- // .. ..
- EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
- // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
- // .. .. ==> 0XF8006010[10:0] = 0x00000001U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U
- // .. .. reg_ddrc_w_xact_run_length = 0x8
- // .. .. ==> 0XF8006010[14:11] = 0x00000008U
- // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U
- // .. .. reg_ddrc_w_max_starve_x32 = 0x2
- // .. .. ==> 0XF8006010[25:15] = 0x00000002U
- // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U
- // .. ..
- EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
- // .. .. reg_ddrc_t_rc = 0x1b
- // .. .. ==> 0XF8006014[5:0] = 0x0000001BU
- // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001BU
- // .. .. reg_ddrc_t_rfc_min = 0x56
- // .. .. ==> 0XF8006014[13:6] = 0x00000056U
- // .. .. ==> MASK : 0x00003FC0U VAL : 0x00001580U
- // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
- // .. .. ==> 0XF8006014[20:14] = 0x00000010U
- // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U
- // .. ..
- EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004159BU),
- // .. .. reg_ddrc_wr2pre = 0x12
- // .. .. ==> 0XF8006018[4:0] = 0x00000012U
- // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U
- // .. .. reg_ddrc_powerdown_to_x32 = 0x6
- // .. .. ==> 0XF8006018[9:5] = 0x00000006U
- // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U
- // .. .. reg_ddrc_t_faw = 0x18
- // .. .. ==> 0XF8006018[15:10] = 0x00000018U
- // .. .. ==> MASK : 0x0000FC00U VAL : 0x00006000U
- // .. .. reg_ddrc_t_ras_max = 0x24
- // .. .. ==> 0XF8006018[21:16] = 0x00000024U
- // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U
- // .. .. reg_ddrc_t_ras_min = 0x14
- // .. .. ==> 0XF8006018[26:22] = 0x00000014U
- // .. .. ==> MASK : 0x07C00000U VAL : 0x05000000U
- // .. .. reg_ddrc_t_cke = 0x4
- // .. .. ==> 0XF8006018[31:28] = 0x00000004U
- // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x452460D2U),
- // .. .. reg_ddrc_write_latency = 0x5
- // .. .. ==> 0XF800601C[4:0] = 0x00000005U
- // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U
- // .. .. reg_ddrc_rd2wr = 0x7
- // .. .. ==> 0XF800601C[9:5] = 0x00000007U
- // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U
- // .. .. reg_ddrc_wr2rd = 0xe
- // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
- // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U
- // .. .. reg_ddrc_t_xp = 0x4
- // .. .. ==> 0XF800601C[19:15] = 0x00000004U
- // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U
- // .. .. reg_ddrc_pad_pd = 0x0
- // .. .. ==> 0XF800601C[22:20] = 0x00000000U
- // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U
- // .. .. reg_ddrc_rd2pre = 0x4
- // .. .. ==> 0XF800601C[27:23] = 0x00000004U
- // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U
- // .. .. reg_ddrc_t_rcd = 0x7
- // .. .. ==> 0XF800601C[31:28] = 0x00000007U
- // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U
- // .. ..
- EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
- // .. .. reg_ddrc_t_ccd = 0x4
- // .. .. ==> 0XF8006020[4:2] = 0x00000004U
- // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U
- // .. .. reg_ddrc_t_rrd = 0x6
- // .. .. ==> 0XF8006020[7:5] = 0x00000006U
- // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U
- // .. .. reg_ddrc_refresh_margin = 0x2
- // .. .. ==> 0XF8006020[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. reg_ddrc_t_rp = 0x7
- // .. .. ==> 0XF8006020[15:12] = 0x00000007U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U
- // .. .. reg_ddrc_refresh_to_x32 = 0x8
- // .. .. ==> 0XF8006020[20:16] = 0x00000008U
- // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U
- // .. .. reg_ddrc_sdram = 0x1
- // .. .. ==> 0XF8006020[21:21] = 0x00000001U
- // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U
- // .. .. reg_ddrc_mobile = 0x0
- // .. .. ==> 0XF8006020[22:22] = 0x00000000U
- // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U
- // .. .. reg_ddrc_clock_stop_en = 0x0
- // .. .. ==> 0XF8006020[23:23] = 0x00000000U
- // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U
- // .. .. reg_ddrc_read_latency = 0x7
- // .. .. ==> 0XF8006020[28:24] = 0x00000007U
- // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U
- // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
- // .. .. ==> 0XF8006020[29:29] = 0x00000001U
- // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U
- // .. .. reg_ddrc_dis_pad_pd = 0x0
- // .. .. ==> 0XF8006020[30:30] = 0x00000000U
- // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U
- // .. .. reg_ddrc_loopback = 0x0
- // .. .. ==> 0XF8006020[31:31] = 0x00000000U
- // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U),
- // .. .. reg_ddrc_en_2t_timing_mode = 0x0
- // .. .. ==> 0XF8006024[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_prefer_write = 0x0
- // .. .. ==> 0XF8006024[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_ddrc_max_rank_rd = 0xf
- // .. .. ==> 0XF8006024[5:2] = 0x0000000FU
- // .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU
- // .. .. reg_ddrc_mr_wr = 0x0
- // .. .. ==> 0XF8006024[6:6] = 0x00000000U
- // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_addr = 0x0
- // .. .. ==> 0XF8006024[8:7] = 0x00000000U
- // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_data = 0x0
- // .. .. ==> 0XF8006024[24:9] = 0x00000000U
- // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U
- // .. .. ddrc_reg_mr_wr_busy = 0x0
- // .. .. ==> 0XF8006024[25:25] = 0x00000000U
- // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_type = 0x0
- // .. .. ==> 0XF8006024[26:26] = 0x00000000U
- // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_rdata_valid = 0x0
- // .. .. ==> 0XF8006024[27:27] = 0x00000000U
- // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU),
- // .. .. reg_ddrc_final_wait_x32 = 0x7
- // .. .. ==> 0XF8006028[6:0] = 0x00000007U
- // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U
- // .. .. reg_ddrc_pre_ocd_x32 = 0x0
- // .. .. ==> 0XF8006028[10:7] = 0x00000000U
- // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U
- // .. .. reg_ddrc_t_mrd = 0x4
- // .. .. ==> 0XF8006028[13:11] = 0x00000004U
- // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U
- // .. ..
- EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
- // .. .. reg_ddrc_emr2 = 0x8
- // .. .. ==> 0XF800602C[15:0] = 0x00000008U
- // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U
- // .. .. reg_ddrc_emr3 = 0x0
- // .. .. ==> 0XF800602C[31:16] = 0x00000000U
- // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
- // .. .. reg_ddrc_mr = 0x930
- // .. .. ==> 0XF8006030[15:0] = 0x00000930U
- // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U
- // .. .. reg_ddrc_emr = 0x4
- // .. .. ==> 0XF8006030[31:16] = 0x00000004U
- // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U
- // .. ..
- EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
- // .. .. reg_ddrc_burst_rdwr = 0x4
- // .. .. ==> 0XF8006034[3:0] = 0x00000004U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U
- // .. .. reg_ddrc_pre_cke_x1024 = 0x105
- // .. .. ==> 0XF8006034[13:4] = 0x00000105U
- // .. .. ==> MASK : 0x00003FF0U VAL : 0x00001050U
- // .. .. reg_ddrc_post_cke_x1024 = 0x1
- // .. .. ==> 0XF8006034[25:16] = 0x00000001U
- // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U
- // .. .. reg_ddrc_burstchop = 0x0
- // .. .. ==> 0XF8006034[28:28] = 0x00000000U
- // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U),
- // .. .. reg_ddrc_force_low_pri_n = 0x0
- // .. .. ==> 0XF8006038[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_dq = 0x0
- // .. .. ==> 0XF8006038[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_debug_mode = 0x0
- // .. .. ==> 0XF8006038[6:6] = 0x00000000U
- // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U
- // .. .. reg_phy_wr_level_start = 0x0
- // .. .. ==> 0XF8006038[7:7] = 0x00000000U
- // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. .. reg_phy_rd_level_start = 0x0
- // .. .. ==> 0XF8006038[8:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. .. reg_phy_dq0_wait_t = 0x0
- // .. .. ==> 0XF8006038[12:9] = 0x00000000U
- // .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U),
- // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
- // .. .. ==> 0XF800603C[3:0] = 0x00000007U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U
- // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
- // .. .. ==> 0XF800603C[7:4] = 0x00000007U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U
- // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
- // .. .. ==> 0XF800603C[11:8] = 0x00000007U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U
- // .. .. reg_ddrc_addrmap_col_b5 = 0x0
- // .. .. ==> 0XF800603C[15:12] = 0x00000000U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b6 = 0x0
- // .. .. ==> 0XF800603C[19:16] = 0x00000000U
- // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
- // .. .. reg_ddrc_addrmap_col_b2 = 0x0
- // .. .. ==> 0XF8006040[3:0] = 0x00000000U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b3 = 0x0
- // .. .. ==> 0XF8006040[7:4] = 0x00000000U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b4 = 0x0
- // .. .. ==> 0XF8006040[11:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b7 = 0x0
- // .. .. ==> 0XF8006040[15:12] = 0x00000000U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b8 = 0x0
- // .. .. ==> 0XF8006040[19:16] = 0x00000000U
- // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b9 = 0xf
- // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
- // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U
- // .. .. reg_ddrc_addrmap_col_b10 = 0xf
- // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
- // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U
- // .. .. reg_ddrc_addrmap_col_b11 = 0xf
- // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
- // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
- // .. .. reg_ddrc_addrmap_row_b0 = 0x6
- // .. .. ==> 0XF8006044[3:0] = 0x00000006U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U
- // .. .. reg_ddrc_addrmap_row_b1 = 0x6
- // .. .. ==> 0XF8006044[7:4] = 0x00000006U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U
- // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
- // .. .. ==> 0XF8006044[11:8] = 0x00000006U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U
- // .. .. reg_ddrc_addrmap_row_b12 = 0x6
- // .. .. ==> 0XF8006044[15:12] = 0x00000006U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U
- // .. .. reg_ddrc_addrmap_row_b13 = 0x6
- // .. .. ==> 0XF8006044[19:16] = 0x00000006U
- // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U
- // .. .. reg_ddrc_addrmap_row_b14 = 0xf
- // .. .. ==> 0XF8006044[23:20] = 0x0000000FU
- // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U
- // .. .. reg_ddrc_addrmap_row_b15 = 0xf
- // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
- // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0FF66666U),
- // .. .. reg_ddrc_rank0_rd_odt = 0x0
- // .. .. ==> 0XF8006048[2:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U
- // .. .. reg_ddrc_rank0_wr_odt = 0x1
- // .. .. ==> 0XF8006048[5:3] = 0x00000001U
- // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U
- // .. .. reg_ddrc_rank1_rd_odt = 0x1
- // .. .. ==> 0XF8006048[8:6] = 0x00000001U
- // .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U
- // .. .. reg_ddrc_rank1_wr_odt = 0x1
- // .. .. ==> 0XF8006048[11:9] = 0x00000001U
- // .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. .. reg_phy_rd_local_odt = 0x0
- // .. .. ==> 0XF8006048[13:12] = 0x00000000U
- // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U
- // .. .. reg_phy_wr_local_odt = 0x3
- // .. .. ==> 0XF8006048[15:14] = 0x00000003U
- // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U
- // .. .. reg_phy_idle_local_odt = 0x3
- // .. .. ==> 0XF8006048[17:16] = 0x00000003U
- // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U
- // .. .. reg_ddrc_rank2_rd_odt = 0x0
- // .. .. ==> 0XF8006048[20:18] = 0x00000000U
- // .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U
- // .. .. reg_ddrc_rank2_wr_odt = 0x0
- // .. .. ==> 0XF8006048[23:21] = 0x00000000U
- // .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U
- // .. .. reg_ddrc_rank3_rd_odt = 0x0
- // .. .. ==> 0XF8006048[26:24] = 0x00000000U
- // .. .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. .. reg_ddrc_rank3_wr_odt = 0x0
- // .. .. ==> 0XF8006048[29:27] = 0x00000000U
- // .. .. ==> MASK : 0x38000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U),
- // .. .. reg_phy_rd_cmd_to_data = 0x0
- // .. .. ==> 0XF8006050[3:0] = 0x00000000U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
- // .. .. reg_phy_wr_cmd_to_data = 0x0
- // .. .. ==> 0XF8006050[7:4] = 0x00000000U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. .. reg_phy_rdc_we_to_re_delay = 0x8
- // .. .. ==> 0XF8006050[11:8] = 0x00000008U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U
- // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
- // .. .. ==> 0XF8006050[15:15] = 0x00000000U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
- // .. .. reg_phy_use_fixed_re = 0x1
- // .. .. ==> 0XF8006050[16:16] = 0x00000001U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U
- // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
- // .. .. ==> 0XF8006050[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
- // .. .. ==> 0XF8006050[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_phy_clk_stall_level = 0x0
- // .. .. ==> 0XF8006050[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
- // .. .. ==> 0XF8006050[27:24] = 0x00000007U
- // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U
- // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
- // .. .. ==> 0XF8006050[31:28] = 0x00000007U
- // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
- // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1
- // .. .. ==> 0XF8006058[7:0] = 0x00000001U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U
- // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1
- // .. .. ==> 0XF8006058[15:8] = 0x00000001U
- // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U
- // .. .. reg_ddrc_dis_dll_calib = 0x0
- // .. .. ==> 0XF8006058[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U),
- // .. .. reg_ddrc_rd_odt_delay = 0x3
- // .. .. ==> 0XF800605C[3:0] = 0x00000003U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U
- // .. .. reg_ddrc_wr_odt_delay = 0x0
- // .. .. ==> 0XF800605C[7:4] = 0x00000000U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. .. reg_ddrc_rd_odt_hold = 0x0
- // .. .. ==> 0XF800605C[11:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U
- // .. .. reg_ddrc_wr_odt_hold = 0x5
- // .. .. ==> 0XF800605C[15:12] = 0x00000005U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U
- // .. ..
- EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
- // .. .. reg_ddrc_pageclose = 0x0
- // .. .. ==> 0XF8006060[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_lpr_num_entries = 0x1f
- // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
- // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU
- // .. .. reg_ddrc_auto_pre_en = 0x0
- // .. .. ==> 0XF8006060[7:7] = 0x00000000U
- // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. .. reg_ddrc_refresh_update_level = 0x0
- // .. .. ==> 0XF8006060[8:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_wc = 0x0
- // .. .. ==> 0XF8006060[9:9] = 0x00000000U
- // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_collision_page_opt = 0x0
- // .. .. ==> 0XF8006060[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_ddrc_selfref_en = 0x0
- // .. .. ==> 0XF8006060[12:12] = 0x00000000U
- // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
- // .. .. reg_ddrc_go2critical_hysteresis = 0x0
- // .. .. ==> 0XF8006064[12:5] = 0x00000000U
- // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U
- // .. .. reg_arb_go2critical_en = 0x1
- // .. .. ==> 0XF8006064[17:17] = 0x00000001U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U
- // .. ..
- EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
- // .. .. reg_ddrc_wrlvl_ww = 0x41
- // .. .. ==> 0XF8006068[7:0] = 0x00000041U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U
- // .. .. reg_ddrc_rdlvl_rr = 0x41
- // .. .. ==> 0XF8006068[15:8] = 0x00000041U
- // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U
- // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
- // .. .. ==> 0XF8006068[25:16] = 0x00000028U
- // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U
- // .. ..
- EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
- // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
- // .. .. ==> 0XF800606C[7:0] = 0x00000010U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U
- // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
- // .. .. ==> 0XF800606C[15:8] = 0x00000016U
- // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U
- // .. ..
- EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
- // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1
- // .. .. ==> 0XF8006078[3:0] = 0x00000001U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U
- // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1
- // .. .. ==> 0XF8006078[7:4] = 0x00000001U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U
- // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1
- // .. .. ==> 0XF8006078[11:8] = 0x00000001U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U
- // .. .. reg_ddrc_t_cksre = 0x6
- // .. .. ==> 0XF8006078[15:12] = 0x00000006U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U
- // .. .. reg_ddrc_t_cksrx = 0x6
- // .. .. ==> 0XF8006078[19:16] = 0x00000006U
- // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U
- // .. .. reg_ddrc_t_ckesr = 0x4
- // .. .. ==> 0XF8006078[25:20] = 0x00000004U
- // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U
- // .. ..
- EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U),
- // .. .. reg_ddrc_t_ckpde = 0x2
- // .. .. ==> 0XF800607C[3:0] = 0x00000002U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U
- // .. .. reg_ddrc_t_ckpdx = 0x2
- // .. .. ==> 0XF800607C[7:4] = 0x00000002U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
- // .. .. reg_ddrc_t_ckdpde = 0x2
- // .. .. ==> 0XF800607C[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. reg_ddrc_t_ckdpdx = 0x2
- // .. .. ==> 0XF800607C[15:12] = 0x00000002U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U
- // .. .. reg_ddrc_t_ckcsx = 0x3
- // .. .. ==> 0XF800607C[19:16] = 0x00000003U
- // .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U
- // .. ..
- EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U),
- // .. .. refresh_timer0_start_value_x32 = 0x0
- // .. .. ==> 0XF80060A0[11:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U
- // .. .. refresh_timer1_start_value_x32 = 0x8
- // .. .. ==> 0XF80060A0[23:12] = 0x00000008U
- // .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U
- // .. ..
- EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U),
- // .. .. reg_ddrc_dis_auto_zq = 0x0
- // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_ddr3 = 0x1
- // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. .. reg_ddrc_t_mod = 0x200
- // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
- // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U
- // .. .. reg_ddrc_t_zq_long_nop = 0x200
- // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
- // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U
- // .. .. reg_ddrc_t_zq_short_nop = 0x40
- // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
- // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
- // .. .. t_zq_short_interval_x1024 = 0xcb73
- // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U
- // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U
- // .. .. dram_rstn_x1024 = 0x69
- // .. .. ==> 0XF80060A8[27:20] = 0x00000069U
- // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U
- // .. ..
- EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
- // .. .. deeppowerdown_en = 0x0
- // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. deeppowerdown_to_x1024 = 0xff
- // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
- // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU
- // .. ..
- EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
- // .. .. dfi_wrlvl_max_x1024 = 0xfff
- // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
- // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU
- // .. .. dfi_rdlvl_max_x1024 = 0xfff
- // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
- // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U
- // .. .. ddrc_reg_twrlvl_max_error = 0x0
- // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
- // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U
- // .. .. ddrc_reg_trdlvl_max_error = 0x0
- // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
- // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
- // .. .. reg_ddrc_dfi_wr_level_en = 0x1
- // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
- // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U
- // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
- // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
- // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U
- // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
- // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
- // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
- // .. .. reg_ddrc_2t_delay = 0x0
- // .. .. ==> 0XF80060B4[8:0] = 0x00000000U
- // .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U
- // .. .. reg_ddrc_skip_ocd = 0x1
- // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
- // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U
- // .. .. reg_ddrc_dis_pre_bypass = 0x0
- // .. .. ==> 0XF80060B4[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U),
- // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
- // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
- // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U
- // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
- // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
- // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U
- // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
- // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
- // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U
- // .. ..
- EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
- // .. .. START: RESET ECC ERROR
- // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1
- // .. .. ==> 0XF80060C4[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. Clear_Correctable_DRAM_ECC_error = 1
- // .. .. ==> 0XF80060C4[1:1] = 0x00000001U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. ..
- EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U),
- // .. .. FINISH: RESET ECC ERROR
- // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
- // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
- // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
- // .. .. CORR_ECC_LOG_VALID = 0x0
- // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. ECC_CORRECTED_BIT_NUM = 0x0
- // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
- // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
- // .. .. UNCORR_ECC_LOG_VALID = 0x0
- // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
- // .. .. STAT_NUM_CORR_ERR = 0x0
- // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
- // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U
- // .. .. STAT_NUM_UNCORR_ERR = 0x0
- // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
- // .. .. reg_ddrc_ecc_mode = 0x0
- // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_scrub = 0x1
- // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U
- // .. ..
- EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
- // .. .. reg_phy_dif_on = 0x0
- // .. .. ==> 0XF8006114[3:0] = 0x00000000U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
- // .. .. reg_phy_dif_off = 0x0
- // .. .. ==> 0XF8006114[7:4] = 0x00000000U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
- // .. .. reg_phy_data_slice_in_use = 0x1
- // .. .. ==> 0XF8006118[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_phy_rdlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006118[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_inc_mode = 0x0
- // .. .. ==> 0XF8006118[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_wrlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006118[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_tx = 0x0
- // .. .. ==> 0XF8006118[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_rx = 0x0
- // .. .. ==> 0XF8006118[5:5] = 0x00000000U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. .. reg_phy_bist_shift_dq = 0x0
- // .. .. ==> 0XF8006118[14:6] = 0x00000000U
- // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. .. reg_phy_bist_err_clr = 0x0
- // .. .. ==> 0XF8006118[23:15] = 0x00000000U
- // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. .. reg_phy_dq_offset = 0x40
- // .. .. ==> 0XF8006118[30:24] = 0x00000040U
- // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U),
- // .. .. reg_phy_data_slice_in_use = 0x1
- // .. .. ==> 0XF800611C[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_phy_rdlvl_inc_mode = 0x0
- // .. .. ==> 0XF800611C[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_inc_mode = 0x0
- // .. .. ==> 0XF800611C[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_wrlvl_inc_mode = 0x0
- // .. .. ==> 0XF800611C[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_tx = 0x0
- // .. .. ==> 0XF800611C[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_rx = 0x0
- // .. .. ==> 0XF800611C[5:5] = 0x00000000U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. .. reg_phy_bist_shift_dq = 0x0
- // .. .. ==> 0XF800611C[14:6] = 0x00000000U
- // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. .. reg_phy_bist_err_clr = 0x0
- // .. .. ==> 0XF800611C[23:15] = 0x00000000U
- // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. .. reg_phy_dq_offset = 0x40
- // .. .. ==> 0XF800611C[30:24] = 0x00000040U
- // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U),
- // .. .. reg_phy_data_slice_in_use = 0x1
- // .. .. ==> 0XF8006120[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_phy_rdlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006120[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_inc_mode = 0x0
- // .. .. ==> 0XF8006120[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_wrlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006120[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_tx = 0x0
- // .. .. ==> 0XF8006120[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_rx = 0x0
- // .. .. ==> 0XF8006120[5:5] = 0x00000000U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. .. reg_phy_bist_shift_dq = 0x0
- // .. .. ==> 0XF8006120[14:6] = 0x00000000U
- // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. .. reg_phy_bist_err_clr = 0x0
- // .. .. ==> 0XF8006120[23:15] = 0x00000000U
- // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. .. reg_phy_dq_offset = 0x40
- // .. .. ==> 0XF8006120[30:24] = 0x00000040U
- // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // .. .. reg_phy_data_slice_in_use = 0x1
- // .. .. ==> 0XF8006120[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_phy_rdlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006120[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_inc_mode = 0x0
- // .. .. ==> 0XF8006120[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_wrlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006120[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_tx = 0x0
- // .. .. ==> 0XF8006120[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_rx = 0x0
- // .. .. ==> 0XF8006120[5:5] = 0x00000000U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. .. reg_phy_bist_shift_dq = 0x0
- // .. .. ==> 0XF8006120[14:6] = 0x00000000U
- // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. .. reg_phy_bist_err_clr = 0x0
- // .. .. ==> 0XF8006120[23:15] = 0x00000000U
- // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. .. reg_phy_dq_offset = 0x40
- // .. .. ==> 0XF8006120[30:24] = 0x00000040U
- // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U),
- // .. .. reg_phy_data_slice_in_use = 0x1
- // .. .. ==> 0XF8006124[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_phy_rdlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006124[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_inc_mode = 0x0
- // .. .. ==> 0XF8006124[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_wrlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006124[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_tx = 0x0
- // .. .. ==> 0XF8006124[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_rx = 0x0
- // .. .. ==> 0XF8006124[5:5] = 0x00000000U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. .. reg_phy_bist_shift_dq = 0x0
- // .. .. ==> 0XF8006124[14:6] = 0x00000000U
- // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. .. reg_phy_bist_err_clr = 0x0
- // .. .. ==> 0XF8006124[23:15] = 0x00000000U
- // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. .. reg_phy_dq_offset = 0x40
- // .. .. ==> 0XF8006124[30:24] = 0x00000040U
- // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U),
- // .. .. reg_phy_wrlvl_init_ratio = 0x3
- // .. .. ==> 0XF800612C[9:0] = 0x00000003U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000003U
- // .. .. reg_phy_gatelvl_init_ratio = 0xcf
- // .. .. ==> 0XF800612C[19:10] = 0x000000CFU
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x00033C00U
- // .. ..
- EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00033C03U),
- // .. .. reg_phy_wrlvl_init_ratio = 0x3
- // .. .. ==> 0XF8006130[9:0] = 0x00000003U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000003U
- // .. .. reg_phy_gatelvl_init_ratio = 0xd0
- // .. .. ==> 0XF8006130[19:10] = 0x000000D0U
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x00034000U
- // .. ..
- EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00034003U),
- // .. .. reg_phy_wrlvl_init_ratio = 0x0
- // .. .. ==> 0XF8006134[9:0] = 0x00000000U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_init_ratio = 0xbd
- // .. .. ==> 0XF8006134[19:10] = 0x000000BDU
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002F400U
- // .. ..
- EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0002F400U),
- // .. .. reg_phy_wrlvl_init_ratio = 0x0
- // .. .. ==> 0XF8006138[9:0] = 0x00000000U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_init_ratio = 0xc1
- // .. .. ==> 0XF8006138[19:10] = 0x000000C1U
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x00030400U
- // .. ..
- EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x00030400U),
- // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. .. ==> 0XF8006140[9:0] = 0x00000035U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. .. reg_phy_rd_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006140[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006140[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
- // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. .. ==> 0XF8006144[9:0] = 0x00000035U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. .. reg_phy_rd_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006144[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006144[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
- // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. .. ==> 0XF8006148[9:0] = 0x00000035U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. .. reg_phy_rd_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006148[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006148[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
- // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. .. ==> 0XF800614C[9:0] = 0x00000035U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. .. reg_phy_rd_dqs_slave_force = 0x0
- // .. .. ==> 0XF800614C[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. .. ==> 0XF800614C[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
- // .. .. reg_phy_wr_dqs_slave_ratio = 0x83
- // .. .. ==> 0XF8006154[9:0] = 0x00000083U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000083U
- // .. .. reg_phy_wr_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006154[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006154[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000083U),
- // .. .. reg_phy_wr_dqs_slave_ratio = 0x83
- // .. .. ==> 0XF8006158[9:0] = 0x00000083U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000083U
- // .. .. reg_phy_wr_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006158[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006158[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000083U),
- // .. .. reg_phy_wr_dqs_slave_ratio = 0x7f
- // .. .. ==> 0XF800615C[9:0] = 0x0000007FU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x0000007FU
- // .. .. reg_phy_wr_dqs_slave_force = 0x0
- // .. .. ==> 0XF800615C[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. .. ==> 0XF800615C[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x0000007FU),
- // .. .. reg_phy_wr_dqs_slave_ratio = 0x78
- // .. .. ==> 0XF8006160[9:0] = 0x00000078U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000078U
- // .. .. reg_phy_wr_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006160[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006160[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000078U),
- // .. .. reg_phy_fifo_we_slave_ratio = 0x124
- // .. .. ==> 0XF8006168[10:0] = 0x00000124U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x00000124U
- // .. .. reg_phy_fifo_we_in_force = 0x0
- // .. .. ==> 0XF8006168[11:11] = 0x00000000U
- // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. .. reg_phy_fifo_we_in_delay = 0x0
- // .. .. ==> 0XF8006168[20:12] = 0x00000000U
- // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000124U),
- // .. .. reg_phy_fifo_we_slave_ratio = 0x125
- // .. .. ==> 0XF800616C[10:0] = 0x00000125U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x00000125U
- // .. .. reg_phy_fifo_we_in_force = 0x0
- // .. .. ==> 0XF800616C[11:11] = 0x00000000U
- // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. .. reg_phy_fifo_we_in_delay = 0x0
- // .. .. ==> 0XF800616C[20:12] = 0x00000000U
- // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x00000125U),
- // .. .. reg_phy_fifo_we_slave_ratio = 0x112
- // .. .. ==> 0XF8006170[10:0] = 0x00000112U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x00000112U
- // .. .. reg_phy_fifo_we_in_force = 0x0
- // .. .. ==> 0XF8006170[11:11] = 0x00000000U
- // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. .. reg_phy_fifo_we_in_delay = 0x0
- // .. .. ==> 0XF8006170[20:12] = 0x00000000U
- // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000112U),
- // .. .. reg_phy_fifo_we_slave_ratio = 0x116
- // .. .. ==> 0XF8006174[10:0] = 0x00000116U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x00000116U
- // .. .. reg_phy_fifo_we_in_force = 0x0
- // .. .. ==> 0XF8006174[11:11] = 0x00000000U
- // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. .. reg_phy_fifo_we_in_delay = 0x0
- // .. .. ==> 0XF8006174[20:12] = 0x00000000U
- // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000116U),
- // .. .. reg_phy_wr_data_slave_ratio = 0xc3
- // .. .. ==> 0XF800617C[9:0] = 0x000000C3U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C3U
- // .. .. reg_phy_wr_data_slave_force = 0x0
- // .. .. ==> 0XF800617C[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_data_slave_delay = 0x0
- // .. .. ==> 0XF800617C[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000C3U),
- // .. .. reg_phy_wr_data_slave_ratio = 0xc3
- // .. .. ==> 0XF8006180[9:0] = 0x000000C3U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C3U
- // .. .. reg_phy_wr_data_slave_force = 0x0
- // .. .. ==> 0XF8006180[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_data_slave_delay = 0x0
- // .. .. ==> 0XF8006180[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000C3U),
- // .. .. reg_phy_wr_data_slave_ratio = 0xbf
- // .. .. ==> 0XF8006184[9:0] = 0x000000BFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000000BFU
- // .. .. reg_phy_wr_data_slave_force = 0x0
- // .. .. ==> 0XF8006184[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_data_slave_delay = 0x0
- // .. .. ==> 0XF8006184[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000BFU),
- // .. .. reg_phy_wr_data_slave_ratio = 0xb8
- // .. .. ==> 0XF8006188[9:0] = 0x000000B8U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000000B8U
- // .. .. reg_phy_wr_data_slave_force = 0x0
- // .. .. ==> 0XF8006188[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_data_slave_delay = 0x0
- // .. .. ==> 0XF8006188[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000B8U),
- // .. .. reg_phy_loopback = 0x0
- // .. .. ==> 0XF8006190[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_phy_bl2 = 0x0
- // .. .. ==> 0XF8006190[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_at_spd_atpg = 0x0
- // .. .. ==> 0XF8006190[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_bist_enable = 0x0
- // .. .. ==> 0XF8006190[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_bist_force_err = 0x0
- // .. .. ==> 0XF8006190[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. reg_phy_bist_mode = 0x0
- // .. .. ==> 0XF8006190[6:5] = 0x00000000U
- // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. .. reg_phy_invert_clkout = 0x1
- // .. .. ==> 0XF8006190[7:7] = 0x00000001U
- // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0
- // .. .. ==> 0XF8006190[8:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. .. reg_phy_sel_logic = 0x0
- // .. .. ==> 0XF8006190[9:9] = 0x00000000U
- // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U
- // .. .. reg_phy_ctrl_slave_ratio = 0x100
- // .. .. ==> 0XF8006190[19:10] = 0x00000100U
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U
- // .. .. reg_phy_ctrl_slave_force = 0x0
- // .. .. ==> 0XF8006190[20:20] = 0x00000000U
- // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U
- // .. .. reg_phy_ctrl_slave_delay = 0x0
- // .. .. ==> 0XF8006190[27:21] = 0x00000000U
- // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U
- // .. .. reg_phy_use_rank0_delays = 0x1
- // .. .. ==> 0XF8006190[28:28] = 0x00000001U
- // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
- // .. .. reg_phy_lpddr = 0x0
- // .. .. ==> 0XF8006190[29:29] = 0x00000000U
- // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U
- // .. .. reg_phy_cmd_latency = 0x0
- // .. .. ==> 0XF8006190[30:30] = 0x00000000U
- // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U
- // .. .. reg_phy_int_lpbk = 0x0
- // .. .. ==> 0XF8006190[31:31] = 0x00000000U
- // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U),
- // .. .. reg_phy_wr_rl_delay = 0x2
- // .. .. ==> 0XF8006194[4:0] = 0x00000002U
- // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U
- // .. .. reg_phy_rd_rl_delay = 0x4
- // .. .. ==> 0XF8006194[9:5] = 0x00000004U
- // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U
- // .. .. reg_phy_dll_lock_diff = 0xf
- // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
- // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U
- // .. .. reg_phy_use_wr_level = 0x1
- // .. .. ==> 0XF8006194[14:14] = 0x00000001U
- // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U
- // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
- // .. .. ==> 0XF8006194[15:15] = 0x00000001U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U
- // .. .. reg_phy_use_rd_data_eye_level = 0x1
- // .. .. ==> 0XF8006194[16:16] = 0x00000001U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U
- // .. .. reg_phy_dis_calib_rst = 0x0
- // .. .. ==> 0XF8006194[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_phy_ctrl_slave_delay = 0x0
- // .. .. ==> 0XF8006194[19:18] = 0x00000000U
- // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
- // .. .. reg_arb_page_addr_mask = 0x0
- // .. .. ==> 0XF8006204[31:0] = 0x00000000U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
- // .. .. reg_arb_pri_wr_portn = 0x3ff
- // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_wr_portn = 0x0
- // .. .. ==> 0XF8006208[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. .. ==> 0XF8006208[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. .. ==> 0XF8006208[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_dis_rmw_portn = 0x1
- // .. .. ==> 0XF8006208[19:19] = 0x00000001U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // .. ..
- EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU),
- // .. .. reg_arb_pri_wr_portn = 0x3ff
- // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_wr_portn = 0x0
- // .. .. ==> 0XF800620C[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. .. ==> 0XF800620C[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. .. ==> 0XF800620C[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_dis_rmw_portn = 0x1
- // .. .. ==> 0XF800620C[19:19] = 0x00000001U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // .. ..
- EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU),
- // .. .. reg_arb_pri_wr_portn = 0x3ff
- // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_wr_portn = 0x0
- // .. .. ==> 0XF8006210[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. .. ==> 0XF8006210[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. .. ==> 0XF8006210[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_dis_rmw_portn = 0x1
- // .. .. ==> 0XF8006210[19:19] = 0x00000001U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // .. ..
- EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU),
- // .. .. reg_arb_pri_wr_portn = 0x3ff
- // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_wr_portn = 0x0
- // .. .. ==> 0XF8006214[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. .. ==> 0XF8006214[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. .. ==> 0XF8006214[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_dis_rmw_portn = 0x1
- // .. .. ==> 0XF8006214[19:19] = 0x00000001U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // .. ..
- EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU),
- // .. .. reg_arb_pri_rd_portn = 0x3ff
- // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_rd_portn = 0x0
- // .. .. ==> 0XF8006218[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. .. ==> 0XF8006218[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. .. ==> 0XF8006218[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_set_hpr_rd_portn = 0x0
- // .. .. ==> 0XF8006218[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
- // .. .. reg_arb_pri_rd_portn = 0x3ff
- // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_rd_portn = 0x0
- // .. .. ==> 0XF800621C[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. .. ==> 0XF800621C[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. .. ==> 0XF800621C[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_set_hpr_rd_portn = 0x0
- // .. .. ==> 0XF800621C[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
- // .. .. reg_arb_pri_rd_portn = 0x3ff
- // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_rd_portn = 0x0
- // .. .. ==> 0XF8006220[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. .. ==> 0XF8006220[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. .. ==> 0XF8006220[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_set_hpr_rd_portn = 0x0
- // .. .. ==> 0XF8006220[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
- // .. .. reg_arb_pri_rd_portn = 0x3ff
- // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_rd_portn = 0x0
- // .. .. ==> 0XF8006224[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. .. ==> 0XF8006224[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. .. ==> 0XF8006224[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_set_hpr_rd_portn = 0x0
- // .. .. ==> 0XF8006224[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
- // .. .. reg_ddrc_lpddr2 = 0x0
- // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_per_bank_refresh = 0x0
- // .. .. ==> 0XF80062A8[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_ddrc_derate_enable = 0x0
- // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_ddrc_mr4_margin = 0x0
- // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U),
- // .. .. reg_ddrc_mr4_read_interval = 0x0
- // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
- // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
- // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U
- // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
- // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
- // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U
- // .. .. reg_ddrc_t_mrw = 0x5
- // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
- // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U
- // .. ..
- EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
- // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8
- // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U
- // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
- // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
- // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U
- // .. ..
- EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
- // .. .. START: POLL ON DCI STATUS
- // .. .. DONE = 1
- // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
- // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // .. ..
- EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
- // .. .. FINISH: POLL ON DCI STATUS
- // .. .. START: UNLOCK DDR
- // .. .. reg_ddrc_soft_rstb = 0x1
- // .. .. ==> 0XF8006000[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_ddrc_powerdown_en = 0x0
- // .. .. ==> 0XF8006000[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_ddrc_data_bus_width = 0x0
- // .. .. ==> 0XF8006000[3:2] = 0x00000000U
- // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U
- // .. .. reg_ddrc_burst8_refresh = 0x0
- // .. .. ==> 0XF8006000[6:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U
- // .. .. reg_ddrc_rdwr_idle_gap = 1
- // .. .. ==> 0XF8006000[13:7] = 0x00000001U
- // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U
- // .. .. reg_ddrc_dis_rd_bypass = 0x0
- // .. .. ==> 0XF8006000[14:14] = 0x00000000U
- // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_act_bypass = 0x0
- // .. .. ==> 0XF8006000[15:15] = 0x00000000U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_auto_refresh = 0x0
- // .. .. ==> 0XF8006000[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
- // .. .. FINISH: UNLOCK DDR
- // .. .. START: CHECK DDR STATUS
- // .. .. ddrc_reg_operating_mode = 1
- // .. .. ==> 0XF8006054[2:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U
- // .. ..
- EMIT_MASKPOLL(0XF8006054, 0x00000007U),
- // .. .. FINISH: CHECK DDR STATUS
- // .. FINISH: DDR INITIALIZATION
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_mio_init_data_2_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: OCM REMAPPING
- // .. FINISH: OCM REMAPPING
- // .. START: DDRIOB SETTINGS
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B40[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x0
- // .. ==> 0XF8000B40[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B40[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x0
- // .. ==> 0XF8000B40[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. DCR_TYPE = 0x0
- // .. ==> 0XF8000B40[6:5] = 0x00000000U
- // .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. IBUF_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B40[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B40[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B40[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B40[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B44[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x0
- // .. ==> 0XF8000B44[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B44[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x0
- // .. ==> 0XF8000B44[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. DCR_TYPE = 0x0
- // .. ==> 0XF8000B44[6:5] = 0x00000000U
- // .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. IBUF_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B44[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B44[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B44[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B44[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B48[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x1
- // .. ==> 0XF8000B48[2:1] = 0x00000001U
- // .. ==> MASK : 0x00000006U VAL : 0x00000002U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B48[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x1
- // .. ==> 0XF8000B48[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. DCR_TYPE = 0x3
- // .. ==> 0XF8000B48[6:5] = 0x00000003U
- // .. ==> MASK : 0x00000060U VAL : 0x00000060U
- // .. IBUF_DISABLE_MODE = 0
- // .. ==> 0XF8000B48[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0
- // .. ==> 0XF8000B48[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B48[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B48[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B4C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x1
- // .. ==> 0XF8000B4C[2:1] = 0x00000001U
- // .. ==> MASK : 0x00000006U VAL : 0x00000002U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B4C[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x1
- // .. ==> 0XF8000B4C[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. DCR_TYPE = 0x3
- // .. ==> 0XF8000B4C[6:5] = 0x00000003U
- // .. ==> MASK : 0x00000060U VAL : 0x00000060U
- // .. IBUF_DISABLE_MODE = 0
- // .. ==> 0XF8000B4C[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0
- // .. ==> 0XF8000B4C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B4C[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B4C[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B50[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x2
- // .. ==> 0XF8000B50[2:1] = 0x00000002U
- // .. ==> MASK : 0x00000006U VAL : 0x00000004U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B50[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x1
- // .. ==> 0XF8000B50[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. DCR_TYPE = 0x3
- // .. ==> 0XF8000B50[6:5] = 0x00000003U
- // .. ==> MASK : 0x00000060U VAL : 0x00000060U
- // .. IBUF_DISABLE_MODE = 0
- // .. ==> 0XF8000B50[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0
- // .. ==> 0XF8000B50[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B50[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B50[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B54[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x2
- // .. ==> 0XF8000B54[2:1] = 0x00000002U
- // .. ==> MASK : 0x00000006U VAL : 0x00000004U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B54[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x1
- // .. ==> 0XF8000B54[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. DCR_TYPE = 0x3
- // .. ==> 0XF8000B54[6:5] = 0x00000003U
- // .. ==> MASK : 0x00000060U VAL : 0x00000060U
- // .. IBUF_DISABLE_MODE = 0
- // .. ==> 0XF8000B54[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0
- // .. ==> 0XF8000B54[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B54[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B54[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B58[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x0
- // .. ==> 0XF8000B58[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B58[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x0
- // .. ==> 0XF8000B58[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. DCR_TYPE = 0x0
- // .. ==> 0XF8000B58[6:5] = 0x00000000U
- // .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. IBUF_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B58[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B58[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B58[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B58[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
- // .. DRIVE_P = 0x1c
- // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
- // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
- // .. DRIVE_N = 0xc
- // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
- // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
- // .. SLEW_P = 0x3
- // .. ==> 0XF8000B5C[18:14] = 0x00000003U
- // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U
- // .. SLEW_N = 0x3
- // .. ==> 0XF8000B5C[23:19] = 0x00000003U
- // .. ==> MASK : 0x00F80000U VAL : 0x00180000U
- // .. GTL = 0x0
- // .. ==> 0XF8000B5C[26:24] = 0x00000000U
- // .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. RTERM = 0x0
- // .. ==> 0XF8000B5C[31:27] = 0x00000000U
- // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
- // .. DRIVE_P = 0x1c
- // .. ==> 0XF8000B60[6:0] = 0x0000001CU
- // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
- // .. DRIVE_N = 0xc
- // .. ==> 0XF8000B60[13:7] = 0x0000000CU
- // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
- // .. SLEW_P = 0x6
- // .. ==> 0XF8000B60[18:14] = 0x00000006U
- // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
- // .. SLEW_N = 0x1f
- // .. ==> 0XF8000B60[23:19] = 0x0000001FU
- // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
- // .. GTL = 0x0
- // .. ==> 0XF8000B60[26:24] = 0x00000000U
- // .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. RTERM = 0x0
- // .. ==> 0XF8000B60[31:27] = 0x00000000U
- // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
- // .. DRIVE_P = 0x1c
- // .. ==> 0XF8000B64[6:0] = 0x0000001CU
- // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
- // .. DRIVE_N = 0xc
- // .. ==> 0XF8000B64[13:7] = 0x0000000CU
- // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
- // .. SLEW_P = 0x6
- // .. ==> 0XF8000B64[18:14] = 0x00000006U
- // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
- // .. SLEW_N = 0x1f
- // .. ==> 0XF8000B64[23:19] = 0x0000001FU
- // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
- // .. GTL = 0x0
- // .. ==> 0XF8000B64[26:24] = 0x00000000U
- // .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. RTERM = 0x0
- // .. ==> 0XF8000B64[31:27] = 0x00000000U
- // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
- // .. DRIVE_P = 0x1c
- // .. ==> 0XF8000B68[6:0] = 0x0000001CU
- // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
- // .. DRIVE_N = 0xc
- // .. ==> 0XF8000B68[13:7] = 0x0000000CU
- // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
- // .. SLEW_P = 0x6
- // .. ==> 0XF8000B68[18:14] = 0x00000006U
- // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
- // .. SLEW_N = 0x1f
- // .. ==> 0XF8000B68[23:19] = 0x0000001FU
- // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
- // .. GTL = 0x0
- // .. ==> 0XF8000B68[26:24] = 0x00000000U
- // .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. RTERM = 0x0
- // .. ==> 0XF8000B68[31:27] = 0x00000000U
- // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
- // .. VREF_INT_EN = 0x1
- // .. ==> 0XF8000B6C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. VREF_SEL = 0x4
- // .. ==> 0XF8000B6C[4:1] = 0x00000004U
- // .. ==> MASK : 0x0000001EU VAL : 0x00000008U
- // .. VREF_EXT_EN = 0x0
- // .. ==> 0XF8000B6C[6:5] = 0x00000000U
- // .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. VREF_PULLUP_EN = 0x0
- // .. ==> 0XF8000B6C[8:7] = 0x00000000U
- // .. ==> MASK : 0x00000180U VAL : 0x00000000U
- // .. REFIO_EN = 0x1
- // .. ==> 0XF8000B6C[9:9] = 0x00000001U
- // .. ==> MASK : 0x00000200U VAL : 0x00000200U
- // .. REFIO_TEST = 0x3
- // .. ==> 0XF8000B6C[11:10] = 0x00000003U
- // .. ==> MASK : 0x00000C00U VAL : 0x00000C00U
- // .. REFIO_PULLUP_EN = 0x0
- // .. ==> 0XF8000B6C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DRST_B_PULLUP_EN = 0x0
- // .. ==> 0XF8000B6C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // .. CKE_PULLUP_EN = 0x0
- // .. ==> 0XF8000B6C[14:14] = 0x00000000U
- // .. ==> MASK : 0x00004000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000E09U),
- // .. .. START: ASSERT RESET
- // .. .. RESET = 1
- // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. VRN_OUT = 0x1
- // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
- // .. ..
- EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U),
- // .. .. FINISH: ASSERT RESET
- // .. .. START: DEASSERT RESET
- // .. .. RESET = 0
- // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. VRN_OUT = 0x1
- // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
- // .. ..
- EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
- // .. .. FINISH: DEASSERT RESET
- // .. .. RESET = 0x1
- // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ENABLE = 0x1
- // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. .. VRP_TRI = 0x0
- // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. VRN_TRI = 0x0
- // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. VRP_OUT = 0x0
- // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. VRN_OUT = 0x1
- // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
- // .. .. NREF_OPT1 = 0x0
- // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
- // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U
- // .. .. NREF_OPT2 = 0x0
- // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U
- // .. .. NREF_OPT4 = 0x1
- // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
- // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U
- // .. .. PREF_OPT1 = 0x0
- // .. .. ==> 0XF8000B70[16:14] = 0x00000000U
- // .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U
- // .. .. PREF_OPT2 = 0x0
- // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
- // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U
- // .. .. UPDATE_CONTROL = 0x0
- // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
- // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U
- // .. .. INIT_COMPLETE = 0x0
- // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
- // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U
- // .. .. TST_CLK = 0x0
- // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
- // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U
- // .. .. TST_HLN = 0x0
- // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
- // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U
- // .. .. TST_HLP = 0x0
- // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
- // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U
- // .. .. TST_RST = 0x0
- // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
- // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
- // .. .. INT_DCI_EN = 0x0
- // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
- // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U),
- // .. FINISH: DDRIOB SETTINGS
- // .. START: MIO PROGRAMMING
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000700[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000700[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000700[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000700[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000700[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000700[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000700[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000700[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000700[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00000600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000704[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000704[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000704[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000704[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000704[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000704[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 3
- // .. ==> 0XF8000704[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000704[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000704[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00000702U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000708[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000708[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000708[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000708[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000708[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000708[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 3
- // .. ==> 0XF8000708[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000708[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000708[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000702U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800070C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF800070C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF800070C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800070C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800070C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF800070C[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 3
- // .. ==> 0XF800070C[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF800070C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800070C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000702U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000710[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000710[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000710[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000710[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000710[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000710[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 3
- // .. ==> 0XF8000710[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000710[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000710[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000702U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000714[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000714[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000714[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000714[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000714[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000714[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 3
- // .. ==> 0XF8000714[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000714[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000714[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000702U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000718[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000718[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000718[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000718[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000718[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000718[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 3
- // .. ==> 0XF8000718[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000718[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000718[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000702U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800071C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800071C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF800071C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800071C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800071C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800071C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF800071C[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF800071C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800071C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000720[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000720[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000720[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000720[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000720[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000720[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 3
- // .. ==> 0XF8000720[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000720[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000720[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000700U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000724[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000724[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000724[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000724[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000724[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000724[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000724[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000724[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000724[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00000600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000728[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000728[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000728[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000728[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000728[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000728[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000728[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000728[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000728[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00000600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800072C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800072C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF800072C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800072C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800072C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800072C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF800072C[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF800072C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800072C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00000600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000730[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000730[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000730[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000730[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000730[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000730[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000730[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000730[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000730[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00000600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000734[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000734[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000734[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000734[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000734[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000734[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000734[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000734[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000734[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00000600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000738[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000738[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000738[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000738[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000738[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000738[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000738[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000738[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000738[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00000600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800073C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800073C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF800073C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800073C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800073C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800073C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF800073C[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF800073C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800073C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00000600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000740[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000740[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000740[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000740[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000740[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000740[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000740[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000740[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000740[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000302U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000744[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000744[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000744[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000744[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000744[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000744[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000744[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000744[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000744[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000302U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000748[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000748[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000748[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000748[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000748[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000748[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000748[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000748[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000748[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000302U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800074C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF800074C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF800074C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800074C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800074C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF800074C[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF800074C[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF800074C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800074C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000302U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000750[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000750[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000750[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000750[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000750[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000750[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000750[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000750[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000750[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000302U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000754[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000754[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000754[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000754[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000754[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000754[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000754[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000754[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000754[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000302U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000758[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF8000758[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000758[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000758[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000758[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000758[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000758[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000758[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000758[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000303U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF800075C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF800075C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF800075C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800075C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800075C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF800075C[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF800075C[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF800075C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800075C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000303U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000760[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF8000760[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000760[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000760[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000760[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000760[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000760[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000760[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000760[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000303U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000764[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF8000764[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000764[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000764[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000764[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000764[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000764[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000764[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000764[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000303U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000768[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF8000768[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000768[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000768[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000768[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000768[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000768[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000768[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000768[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000303U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF800076C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF800076C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF800076C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800076C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800076C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF800076C[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF800076C[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF800076C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800076C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000303U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000770[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000770[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000770[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000770[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000770[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000770[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000770[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000770[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000770[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000304U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000774[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF8000774[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000774[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000774[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000774[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000774[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000774[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000774[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000774[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000305U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000778[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000778[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000778[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000778[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000778[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000778[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000778[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000778[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000778[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000304U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF800077C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF800077C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF800077C[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF800077C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800077C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF800077C[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF800077C[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF800077C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800077C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000305U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000780[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000780[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000780[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000780[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000780[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000780[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000780[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000780[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000780[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000304U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000784[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000784[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000784[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000784[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000784[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000784[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000784[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000784[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000784[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000304U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000788[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000788[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000788[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000788[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000788[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000788[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000788[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000788[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000788[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000304U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800078C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800078C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF800078C[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF800078C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800078C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF800078C[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF800078C[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF800078C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800078C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000304U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000790[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF8000790[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000790[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000790[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000790[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000790[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000790[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000790[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000790[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000305U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000794[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000794[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000794[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000794[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000794[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000794[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000794[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000794[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000794[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000304U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000798[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000798[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000798[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000798[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000798[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000798[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000798[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000798[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000798[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000304U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800079C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800079C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF800079C[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF800079C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800079C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF800079C[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF800079C[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF800079C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800079C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000304U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007A0[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007A0[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007A0[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007A0[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007A0[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 1
- // .. ==> 0XF80007A0[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF80007A0[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007A0[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007A0[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000380U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007A4[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007A4[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007A4[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007A4[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007A4[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 1
- // .. ==> 0XF80007A4[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF80007A4[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007A4[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007A4[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000380U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007A8[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007A8[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007A8[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007A8[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007A8[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 1
- // .. ==> 0XF80007A8[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF80007A8[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007A8[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007A8[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000380U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007AC[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007AC[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007AC[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007AC[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007AC[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 1
- // .. ==> 0XF80007AC[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF80007AC[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007AC[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007AC[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000380U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007B0[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007B0[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007B0[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007B0[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007B0[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 1
- // .. ==> 0XF80007B0[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF80007B0[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007B0[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007B0[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000380U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007B4[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007B4[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007B4[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007B4[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007B4[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 1
- // .. ==> 0XF80007B4[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF80007B4[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007B4[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007B4[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000380U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF80007B8[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. Speed = 0
- // .. ==> 0XF80007B8[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007B8[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007B8[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007B8[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007B8, 0x00003F01U ,0x00000201U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF80007BC[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. Speed = 0
- // .. ==> 0XF80007BC[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007BC[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007BC[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007BC[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007BC, 0x00003F01U ,0x00000201U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007C0[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007C0[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007C0[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007C0[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 7
- // .. ==> 0XF80007C0[7:5] = 0x00000007U
- // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U
- // .. Speed = 0
- // .. ==> 0XF80007C0[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007C0[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007C0[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007C0[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF80007C4[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF80007C4[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007C4[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007C4[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 7
- // .. ==> 0XF80007C4[7:5] = 0x00000007U
- // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U
- // .. Speed = 0
- // .. ==> 0XF80007C4[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007C4[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007C4[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007C4[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF80007C8[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF80007C8[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007C8[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007C8[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF80007C8[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF80007C8[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007C8[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007C8[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007C8[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00000201U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF80007CC[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF80007CC[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007CC[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007CC[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF80007CC[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF80007CC[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007CC[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007CC[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007CC[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00000201U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007D0[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007D0[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007D0[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007D0[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007D0[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF80007D0[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007D0[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007D0[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007D0[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007D4[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007D4[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007D4[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007D4[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007D4[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF80007D4[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007D4[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007D4[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007D4[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U),
- // .. SDIO0_WP_SEL = 46
- // .. ==> 0XF8000830[5:0] = 0x0000002EU
- // .. ==> MASK : 0x0000003FU VAL : 0x0000002EU
- // .. SDIO0_CD_SEL = 47
- // .. ==> 0XF8000830[21:16] = 0x0000002FU
- // .. ==> MASK : 0x003F0000U VAL : 0x002F0000U
- // ..
- EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x002F002EU),
- // .. FINISH: MIO PROGRAMMING
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_peripherals_init_data_2_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
- // .. IBUF_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B48[7:7] = 0x00000001U
- // .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. TERM_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B48[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // ..
- EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
- // .. IBUF_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B4C[7:7] = 0x00000001U
- // .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. TERM_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B4C[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // ..
- EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
- // .. IBUF_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B50[7:7] = 0x00000001U
- // .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. TERM_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B50[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // ..
- EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
- // .. IBUF_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B54[7:7] = 0x00000001U
- // .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. TERM_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B54[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // ..
- EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
- // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // .. START: SRAM/NOR SET OPMODE
- // .. FINISH: SRAM/NOR SET OPMODE
- // .. START: UART REGISTERS
- // .. BDIV = 0x6
- // .. ==> 0XE0001034[7:0] = 0x00000006U
- // .. ==> MASK : 0x000000FFU VAL : 0x00000006U
- // ..
- EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
- // .. CD = 0x3e
- // .. ==> 0XE0001018[15:0] = 0x0000003EU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU
- // ..
- EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
- // .. STPBRK = 0x0
- // .. ==> 0XE0001000[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. STTBRK = 0x0
- // .. ==> 0XE0001000[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. RSTTO = 0x0
- // .. ==> 0XE0001000[6:6] = 0x00000000U
- // .. ==> MASK : 0x00000040U VAL : 0x00000000U
- // .. TXDIS = 0x0
- // .. ==> 0XE0001000[5:5] = 0x00000000U
- // .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. TXEN = 0x1
- // .. ==> 0XE0001000[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. RXDIS = 0x0
- // .. ==> 0XE0001000[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. RXEN = 0x1
- // .. ==> 0XE0001000[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. TXRES = 0x1
- // .. ==> 0XE0001000[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. RXRES = 0x1
- // .. ==> 0XE0001000[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // ..
- EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
- // .. IRMODE = 0x0
- // .. ==> 0XE0001004[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. UCLKEN = 0x0
- // .. ==> 0XE0001004[10:10] = 0x00000000U
- // .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. CHMODE = 0x0
- // .. ==> 0XE0001004[9:8] = 0x00000000U
- // .. ==> MASK : 0x00000300U VAL : 0x00000000U
- // .. NBSTOP = 0x0
- // .. ==> 0XE0001004[7:6] = 0x00000000U
- // .. ==> MASK : 0x000000C0U VAL : 0x00000000U
- // .. PAR = 0x4
- // .. ==> 0XE0001004[5:3] = 0x00000004U
- // .. ==> MASK : 0x00000038U VAL : 0x00000020U
- // .. CHRL = 0x0
- // .. ==> 0XE0001004[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. CLKS = 0x0
- // .. ==> 0XE0001004[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U),
- // .. FINISH: UART REGISTERS
- // .. START: QSPI REGISTERS
- // .. Holdb_dr = 1
- // .. ==> 0XE000D000[19:19] = 0x00000001U
- // .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // ..
- EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
- // .. FINISH: QSPI REGISTERS
- // .. START: PL POWER ON RESET REGISTERS
- // .. PCFG_POR_CNT_4K = 0
- // .. ==> 0XF8007000[29:29] = 0x00000000U
- // .. ==> MASK : 0x20000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
- // .. FINISH: PL POWER ON RESET REGISTERS
- // .. START: SMC TIMING CALCULATION REGISTER UPDATE
- // .. .. START: NAND SET CYCLE
- // .. .. FINISH: NAND SET CYCLE
- // .. .. START: OPMODE
- // .. .. FINISH: OPMODE
- // .. .. START: DIRECT COMMAND
- // .. .. FINISH: DIRECT COMMAND
- // .. .. START: SRAM/NOR CS0 SET CYCLE
- // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
- // .. .. START: DIRECT COMMAND
- // .. .. FINISH: DIRECT COMMAND
- // .. .. START: NOR CS0 BASE ADDRESS
- // .. .. FINISH: NOR CS0 BASE ADDRESS
- // .. .. START: SRAM/NOR CS1 SET CYCLE
- // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
- // .. .. START: DIRECT COMMAND
- // .. .. FINISH: DIRECT COMMAND
- // .. .. START: NOR CS1 BASE ADDRESS
- // .. .. FINISH: NOR CS1 BASE ADDRESS
- // .. .. START: USB RESET
- // .. .. .. START: USB0 RESET
- // .. .. .. .. START: DIR MODE BANK 0
- // .. .. .. .. FINISH: DIR MODE BANK 0
- // .. .. .. .. START: DIR MODE BANK 1
- // .. .. .. .. FINISH: DIR MODE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. START: OUTPUT ENABLE BANK 0
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
- // .. .. .. .. START: OUTPUT ENABLE BANK 1
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. START: ADD 1 MS DELAY
- // .. .. .. ..
- EMIT_MASKDELAY(0XF8F00200, 1),
- // .. .. .. .. FINISH: ADD 1 MS DELAY
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: USB0 RESET
- // .. .. .. START: USB1 RESET
- // .. .. .. .. START: DIR MODE BANK 0
- // .. .. .. .. FINISH: DIR MODE BANK 0
- // .. .. .. .. START: DIR MODE BANK 1
- // .. .. .. .. FINISH: DIR MODE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. START: OUTPUT ENABLE BANK 0
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
- // .. .. .. .. START: OUTPUT ENABLE BANK 1
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. START: ADD 1 MS DELAY
- // .. .. .. ..
- EMIT_MASKDELAY(0XF8F00200, 1),
- // .. .. .. .. FINISH: ADD 1 MS DELAY
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: USB1 RESET
- // .. .. FINISH: USB RESET
- // .. .. START: ENET RESET
- // .. .. .. START: ENET0 RESET
- // .. .. .. .. START: DIR MODE BANK 0
- // .. .. .. .. FINISH: DIR MODE BANK 0
- // .. .. .. .. START: DIR MODE BANK 1
- // .. .. .. .. FINISH: DIR MODE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. START: OUTPUT ENABLE BANK 0
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
- // .. .. .. .. START: OUTPUT ENABLE BANK 1
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. START: ADD 1 MS DELAY
- // .. .. .. ..
- EMIT_MASKDELAY(0XF8F00200, 1),
- // .. .. .. .. FINISH: ADD 1 MS DELAY
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: ENET0 RESET
- // .. .. .. START: ENET1 RESET
- // .. .. .. .. START: DIR MODE BANK 0
- // .. .. .. .. FINISH: DIR MODE BANK 0
- // .. .. .. .. START: DIR MODE BANK 1
- // .. .. .. .. FINISH: DIR MODE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. START: OUTPUT ENABLE BANK 0
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
- // .. .. .. .. START: OUTPUT ENABLE BANK 1
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. START: ADD 1 MS DELAY
- // .. .. .. ..
- EMIT_MASKDELAY(0XF8F00200, 1),
- // .. .. .. .. FINISH: ADD 1 MS DELAY
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: ENET1 RESET
- // .. .. FINISH: ENET RESET
- // .. .. START: I2C RESET
- // .. .. .. START: I2C0 RESET
- // .. .. .. .. START: DIR MODE GPIO BANK0
- // .. .. .. .. FINISH: DIR MODE GPIO BANK0
- // .. .. .. .. START: DIR MODE GPIO BANK1
- // .. .. .. .. FINISH: DIR MODE GPIO BANK1
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. START: OUTPUT ENABLE
- // .. .. .. .. FINISH: OUTPUT ENABLE
- // .. .. .. .. START: OUTPUT ENABLE
- // .. .. .. .. FINISH: OUTPUT ENABLE
- // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. START: ADD 1 MS DELAY
- // .. .. .. ..
- EMIT_MASKDELAY(0XF8F00200, 1),
- // .. .. .. .. FINISH: ADD 1 MS DELAY
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: I2C0 RESET
- // .. .. .. START: I2C1 RESET
- // .. .. .. .. START: DIR MODE GPIO BANK0
- // .. .. .. .. FINISH: DIR MODE GPIO BANK0
- // .. .. .. .. START: DIR MODE GPIO BANK1
- // .. .. .. .. FINISH: DIR MODE GPIO BANK1
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. START: OUTPUT ENABLE
- // .. .. .. .. FINISH: OUTPUT ENABLE
- // .. .. .. .. START: OUTPUT ENABLE
- // .. .. .. .. FINISH: OUTPUT ENABLE
- // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. START: ADD 1 MS DELAY
- // .. .. .. ..
- EMIT_MASKDELAY(0XF8F00200, 1),
- // .. .. .. .. FINISH: ADD 1 MS DELAY
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: I2C1 RESET
- // .. .. FINISH: I2C RESET
- // .. .. START: NOR CHIP SELECT
- // .. .. .. START: DIR MODE BANK 0
- // .. .. .. FINISH: DIR MODE BANK 0
- // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. START: OUTPUT ENABLE BANK 0
- // .. .. .. FINISH: OUTPUT ENABLE BANK 0
- // .. .. FINISH: NOR CHIP SELECT
- // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_post_config_2_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: ENABLING LEVEL SHIFTER
- // .. USER_INP_ICT_EN_0 = 3
- // .. ==> 0XF8000900[1:0] = 0x00000003U
- // .. ==> MASK : 0x00000003U VAL : 0x00000003U
- // .. USER_INP_ICT_EN_1 = 3
- // .. ==> 0XF8000900[3:2] = 0x00000003U
- // .. ==> MASK : 0x0000000CU VAL : 0x0000000CU
- // ..
- EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
- // .. FINISH: ENABLING LEVEL SHIFTER
- // .. START: FPGA RESETS TO 0
- // .. reserved_3 = 0
- // .. ==> 0XF8000240[31:25] = 0x00000000U
- // .. ==> MASK : 0xFE000000U VAL : 0x00000000U
- // .. FPGA_ACP_RST = 0
- // .. ==> 0XF8000240[24:24] = 0x00000000U
- // .. ==> MASK : 0x01000000U VAL : 0x00000000U
- // .. FPGA_AXDS3_RST = 0
- // .. ==> 0XF8000240[23:23] = 0x00000000U
- // .. ==> MASK : 0x00800000U VAL : 0x00000000U
- // .. FPGA_AXDS2_RST = 0
- // .. ==> 0XF8000240[22:22] = 0x00000000U
- // .. ==> MASK : 0x00400000U VAL : 0x00000000U
- // .. FPGA_AXDS1_RST = 0
- // .. ==> 0XF8000240[21:21] = 0x00000000U
- // .. ==> MASK : 0x00200000U VAL : 0x00000000U
- // .. FPGA_AXDS0_RST = 0
- // .. ==> 0XF8000240[20:20] = 0x00000000U
- // .. ==> MASK : 0x00100000U VAL : 0x00000000U
- // .. reserved_2 = 0
- // .. ==> 0XF8000240[19:18] = 0x00000000U
- // .. ==> MASK : 0x000C0000U VAL : 0x00000000U
- // .. FSSW1_FPGA_RST = 0
- // .. ==> 0XF8000240[17:17] = 0x00000000U
- // .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. FSSW0_FPGA_RST = 0
- // .. ==> 0XF8000240[16:16] = 0x00000000U
- // .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. reserved_1 = 0
- // .. ==> 0XF8000240[15:14] = 0x00000000U
- // .. ==> MASK : 0x0000C000U VAL : 0x00000000U
- // .. FPGA_FMSW1_RST = 0
- // .. ==> 0XF8000240[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // .. FPGA_FMSW0_RST = 0
- // .. ==> 0XF8000240[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. FPGA_DMA3_RST = 0
- // .. ==> 0XF8000240[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. FPGA_DMA2_RST = 0
- // .. ==> 0XF8000240[10:10] = 0x00000000U
- // .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. FPGA_DMA1_RST = 0
- // .. ==> 0XF8000240[9:9] = 0x00000000U
- // .. ==> MASK : 0x00000200U VAL : 0x00000000U
- // .. FPGA_DMA0_RST = 0
- // .. ==> 0XF8000240[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. reserved = 0
- // .. ==> 0XF8000240[7:4] = 0x00000000U
- // .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. FPGA3_OUT_RST = 0
- // .. ==> 0XF8000240[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. FPGA2_OUT_RST = 0
- // .. ==> 0XF8000240[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. FPGA1_OUT_RST = 0
- // .. ==> 0XF8000240[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. FPGA0_OUT_RST = 0
- // .. ==> 0XF8000240[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
- // .. FINISH: FPGA RESETS TO 0
- // .. START: AFI REGISTERS
- // .. .. START: AFI0 REGISTERS
- // .. .. FINISH: AFI0 REGISTERS
- // .. .. START: AFI1 REGISTERS
- // .. .. FINISH: AFI1 REGISTERS
- // .. .. START: AFI2 REGISTERS
- // .. .. FINISH: AFI2 REGISTERS
- // .. .. START: AFI3 REGISTERS
- // .. .. FINISH: AFI3 REGISTERS
- // .. FINISH: AFI REGISTERS
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_debug_2_0[] = {
- // START: top
- // .. START: CROSS TRIGGER CONFIGURATIONS
- // .. .. START: UNLOCKING CTI REGISTERS
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. FINISH: UNLOCKING CTI REGISTERS
- // .. .. START: ENABLING CTI MODULES AND CHANNELS
- // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
- // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. FINISH: CROSS TRIGGER CONFIGURATIONS
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_pll_init_data_1_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: PLL SLCR REGISTERS
- // .. .. START: ARM PLL INIT
- // .. .. PLL_RES = 0x2
- // .. .. ==> 0XF8000110[7:4] = 0x00000002U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
- // .. .. PLL_CP = 0x2
- // .. .. ==> 0XF8000110[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. LOCK_CNT = 0xfa
- // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
- // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U
- // .. ..
- EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
- // .. .. .. START: UPDATE FB_DIV
- // .. .. .. PLL_FDIV = 0x28
- // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
- // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
- // .. .. .. FINISH: UPDATE FB_DIV
- // .. .. .. START: BY PASS PLL
- // .. .. .. PLL_BYPASS_FORCE = 1
- // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
- // .. .. .. FINISH: BY PASS PLL
- // .. .. .. START: ASSERT RESET
- // .. .. .. PLL_RESET = 1
- // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
- // .. .. .. FINISH: ASSERT RESET
- // .. .. .. START: DEASSERT RESET
- // .. .. .. PLL_RESET = 0
- // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
- // .. .. .. FINISH: DEASSERT RESET
- // .. .. .. START: CHECK PLL STATUS
- // .. .. .. ARM_PLL_LOCK = 1
- // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ..
- EMIT_MASKPOLL(0XF800010C, 0x00000001U),
- // .. .. .. FINISH: CHECK PLL STATUS
- // .. .. .. START: REMOVE PLL BY PASS
- // .. .. .. PLL_BYPASS_FORCE = 0
- // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
- // .. .. .. FINISH: REMOVE PLL BY PASS
- // .. .. .. SRCSEL = 0x0
- // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. .. .. DIVISOR = 0x2
- // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
- // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U
- // .. .. .. CPU_6OR4XCLKACT = 0x1
- // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
- // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U
- // .. .. .. CPU_3OR2XCLKACT = 0x1
- // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
- // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U
- // .. .. .. CPU_2XCLKACT = 0x1
- // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
- // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U
- // .. .. .. CPU_1XCLKACT = 0x1
- // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
- // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U
- // .. .. .. CPU_PERI_CLKACT = 0x1
- // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
- // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
- // .. .. FINISH: ARM PLL INIT
- // .. .. START: DDR PLL INIT
- // .. .. PLL_RES = 0x2
- // .. .. ==> 0XF8000114[7:4] = 0x00000002U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
- // .. .. PLL_CP = 0x2
- // .. .. ==> 0XF8000114[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. LOCK_CNT = 0x12c
- // .. .. ==> 0XF8000114[21:12] = 0x0000012CU
- // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U
- // .. ..
- EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
- // .. .. .. START: UPDATE FB_DIV
- // .. .. .. PLL_FDIV = 0x20
- // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
- // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
- // .. .. .. FINISH: UPDATE FB_DIV
- // .. .. .. START: BY PASS PLL
- // .. .. .. PLL_BYPASS_FORCE = 1
- // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
- // .. .. .. FINISH: BY PASS PLL
- // .. .. .. START: ASSERT RESET
- // .. .. .. PLL_RESET = 1
- // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
- // .. .. .. FINISH: ASSERT RESET
- // .. .. .. START: DEASSERT RESET
- // .. .. .. PLL_RESET = 0
- // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
- // .. .. .. FINISH: DEASSERT RESET
- // .. .. .. START: CHECK PLL STATUS
- // .. .. .. DDR_PLL_LOCK = 1
- // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. .. ..
- EMIT_MASKPOLL(0XF800010C, 0x00000002U),
- // .. .. .. FINISH: CHECK PLL STATUS
- // .. .. .. START: REMOVE PLL BY PASS
- // .. .. .. PLL_BYPASS_FORCE = 0
- // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
- // .. .. .. FINISH: REMOVE PLL BY PASS
- // .. .. .. DDR_3XCLKACT = 0x1
- // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. .. DDR_2XCLKACT = 0x1
- // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. .. .. DDR_3XCLK_DIVISOR = 0x2
- // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
- // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U
- // .. .. .. DDR_2XCLK_DIVISOR = 0x3
- // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
- // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
- // .. .. FINISH: DDR PLL INIT
- // .. .. START: IO PLL INIT
- // .. .. PLL_RES = 0xc
- // .. .. ==> 0XF8000118[7:4] = 0x0000000CU
- // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U
- // .. .. PLL_CP = 0x2
- // .. .. ==> 0XF8000118[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. LOCK_CNT = 0x145
- // .. .. ==> 0XF8000118[21:12] = 0x00000145U
- // .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U
- // .. ..
- EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U),
- // .. .. .. START: UPDATE FB_DIV
- // .. .. .. PLL_FDIV = 0x1e
- // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU
- // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U),
- // .. .. .. FINISH: UPDATE FB_DIV
- // .. .. .. START: BY PASS PLL
- // .. .. .. PLL_BYPASS_FORCE = 1
- // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
- // .. .. .. FINISH: BY PASS PLL
- // .. .. .. START: ASSERT RESET
- // .. .. .. PLL_RESET = 1
- // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
- // .. .. .. FINISH: ASSERT RESET
- // .. .. .. START: DEASSERT RESET
- // .. .. .. PLL_RESET = 0
- // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
- // .. .. .. FINISH: DEASSERT RESET
- // .. .. .. START: CHECK PLL STATUS
- // .. .. .. IO_PLL_LOCK = 1
- // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. .. ..
- EMIT_MASKPOLL(0XF800010C, 0x00000004U),
- // .. .. .. FINISH: CHECK PLL STATUS
- // .. .. .. START: REMOVE PLL BY PASS
- // .. .. .. PLL_BYPASS_FORCE = 0
- // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
- // .. .. .. FINISH: REMOVE PLL BY PASS
- // .. .. FINISH: IO PLL INIT
- // .. FINISH: PLL SLCR REGISTERS
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_clock_init_data_1_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: CLOCK CONTROL SLCR REGISTERS
- // .. CLKACT = 0x1
- // .. ==> 0XF8000128[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. DIVISOR0 = 0x23
- // .. ==> 0XF8000128[13:8] = 0x00000023U
- // .. ==> MASK : 0x00003F00U VAL : 0x00002300U
- // .. DIVISOR1 = 0x3
- // .. ==> 0XF8000128[25:20] = 0x00000003U
- // .. ==> MASK : 0x03F00000U VAL : 0x00300000U
- // ..
- EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U),
- // .. CLKACT = 0x1
- // .. ==> 0XF8000138[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000138[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
- // .. CLKACT = 0x1
- // .. ==> 0XF8000140[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000140[6:4] = 0x00000000U
- // .. ==> MASK : 0x00000070U VAL : 0x00000000U
- // .. DIVISOR = 0x8
- // .. ==> 0XF8000140[13:8] = 0x00000008U
- // .. ==> MASK : 0x00003F00U VAL : 0x00000800U
- // .. DIVISOR1 = 0x1
- // .. ==> 0XF8000140[25:20] = 0x00000001U
- // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
- // ..
- EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U),
- // .. CLKACT = 0x1
- // .. ==> 0XF800014C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. SRCSEL = 0x0
- // .. ==> 0XF800014C[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR = 0x5
- // .. ==> 0XF800014C[13:8] = 0x00000005U
- // .. ==> MASK : 0x00003F00U VAL : 0x00000500U
- // ..
- EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
- // .. CLKACT0 = 0x1
- // .. ==> 0XF8000150[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. CLKACT1 = 0x0
- // .. ==> 0XF8000150[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000150[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR = 0x14
- // .. ==> 0XF8000150[13:8] = 0x00000014U
- // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
- // ..
- EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U),
- // .. CLKACT0 = 0x0
- // .. ==> 0XF8000154[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. CLKACT1 = 0x1
- // .. ==> 0XF8000154[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000154[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR = 0x14
- // .. ==> 0XF8000154[13:8] = 0x00000014U
- // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
- // ..
- EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U),
- // .. CLKACT = 0x1
- // .. ==> 0XF8000168[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000168[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR = 0x5
- // .. ==> 0XF8000168[13:8] = 0x00000005U
- // .. ==> MASK : 0x00003F00U VAL : 0x00000500U
- // ..
- EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000170[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR0 = 0xa
- // .. ==> 0XF8000170[13:8] = 0x0000000AU
- // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U
- // .. DIVISOR1 = 0x1
- // .. ==> 0XF8000170[25:20] = 0x00000001U
- // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
- // ..
- EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00100A00U),
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000180[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR0 = 0x7
- // .. ==> 0XF8000180[13:8] = 0x00000007U
- // .. ==> MASK : 0x00003F00U VAL : 0x00000700U
- // .. DIVISOR1 = 0x1
- // .. ==> 0XF8000180[25:20] = 0x00000001U
- // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
- // ..
- EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00100700U),
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000190[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR0 = 0x14
- // .. ==> 0XF8000190[13:8] = 0x00000014U
- // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
- // .. DIVISOR1 = 0x1
- // .. ==> 0XF8000190[25:20] = 0x00000001U
- // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
- // ..
- EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101400U),
- // .. SRCSEL = 0x0
- // .. ==> 0XF80001A0[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR0 = 0x14
- // .. ==> 0XF80001A0[13:8] = 0x00000014U
- // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
- // .. DIVISOR1 = 0x1
- // .. ==> 0XF80001A0[25:20] = 0x00000001U
- // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
- // ..
- EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U),
- // .. CLK_621_TRUE = 0x1
- // .. ==> 0XF80001C4[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // ..
- EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
- // .. DMA_CPU_2XCLKACT = 0x1
- // .. ==> 0XF800012C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. USB0_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. USB1_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[3:3] = 0x00000001U
- // .. ==> MASK : 0x00000008U VAL : 0x00000008U
- // .. GEM0_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[6:6] = 0x00000001U
- // .. ==> MASK : 0x00000040U VAL : 0x00000040U
- // .. GEM1_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. SDI0_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[10:10] = 0x00000001U
- // .. ==> MASK : 0x00000400U VAL : 0x00000400U
- // .. SDI1_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. SPI0_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[14:14] = 0x00000000U
- // .. ==> MASK : 0x00004000U VAL : 0x00000000U
- // .. SPI1_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[15:15] = 0x00000000U
- // .. ==> MASK : 0x00008000U VAL : 0x00000000U
- // .. CAN0_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[16:16] = 0x00000000U
- // .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. CAN1_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[17:17] = 0x00000000U
- // .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. I2C0_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[18:18] = 0x00000001U
- // .. ==> MASK : 0x00040000U VAL : 0x00040000U
- // .. I2C1_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[19:19] = 0x00000001U
- // .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // .. UART0_CPU_1XCLKACT = 0x0
- // .. ==> 0XF800012C[20:20] = 0x00000000U
- // .. ==> MASK : 0x00100000U VAL : 0x00000000U
- // .. UART1_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[21:21] = 0x00000001U
- // .. ==> MASK : 0x00200000U VAL : 0x00200000U
- // .. GPIO_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[22:22] = 0x00000001U
- // .. ==> MASK : 0x00400000U VAL : 0x00400000U
- // .. LQSPI_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[23:23] = 0x00000001U
- // .. ==> MASK : 0x00800000U VAL : 0x00800000U
- // .. SMC_CPU_1XCLKACT = 0x1
- // .. ==> 0XF800012C[24:24] = 0x00000001U
- // .. ==> MASK : 0x01000000U VAL : 0x01000000U
- // ..
- EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC044DU),
- // .. FINISH: CLOCK CONTROL SLCR REGISTERS
- // .. START: THIS SHOULD BE BLANK
- // .. FINISH: THIS SHOULD BE BLANK
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_ddr_init_data_1_0[] = {
- // START: top
- // .. START: DDR INITIALIZATION
- // .. .. START: LOCK DDR
- // .. .. reg_ddrc_soft_rstb = 0
- // .. .. ==> 0XF8006000[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_powerdown_en = 0x0
- // .. .. ==> 0XF8006000[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_ddrc_data_bus_width = 0x0
- // .. .. ==> 0XF8006000[3:2] = 0x00000000U
- // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U
- // .. .. reg_ddrc_burst8_refresh = 0x0
- // .. .. ==> 0XF8006000[6:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U
- // .. .. reg_ddrc_rdwr_idle_gap = 0x1
- // .. .. ==> 0XF8006000[13:7] = 0x00000001U
- // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U
- // .. .. reg_ddrc_dis_rd_bypass = 0x0
- // .. .. ==> 0XF8006000[14:14] = 0x00000000U
- // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_act_bypass = 0x0
- // .. .. ==> 0XF8006000[15:15] = 0x00000000U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_auto_refresh = 0x0
- // .. .. ==> 0XF8006000[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
- // .. .. FINISH: LOCK DDR
- // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81
- // .. .. ==> 0XF8006004[11:0] = 0x00000081U
- // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U
- // .. .. reg_ddrc_active_ranks = 0x1
- // .. .. ==> 0XF8006004[13:12] = 0x00000001U
- // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U
- // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
- // .. .. ==> 0XF8006004[18:14] = 0x00000000U
- // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U
- // .. .. reg_ddrc_wr_odt_block = 0x1
- // .. .. ==> 0XF8006004[20:19] = 0x00000001U
- // .. .. ==> MASK : 0x00180000U VAL : 0x00080000U
- // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0
- // .. .. ==> 0XF8006004[21:21] = 0x00000000U
- // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0
- // .. .. ==> 0XF8006004[26:22] = 0x00000000U
- // .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_open_bank = 0x0
- // .. .. ==> 0XF8006004[27:27] = 0x00000000U
- // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_4bank_ram = 0x0
- // .. .. ==> 0XF8006004[28:28] = 0x00000000U
- // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U),
- // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
- // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
- // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU
- // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
- // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
- // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U
- // .. .. reg_ddrc_hpr_xact_run_length = 0xf
- // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
- // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U
- // .. ..
- EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
- // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
- // .. .. ==> 0XF800600C[10:0] = 0x00000001U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U
- // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
- // .. .. ==> 0XF800600C[21:11] = 0x00000002U
- // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U
- // .. .. reg_ddrc_lpr_xact_run_length = 0x8
- // .. .. ==> 0XF800600C[25:22] = 0x00000008U
- // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U
- // .. ..
- EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
- // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
- // .. .. ==> 0XF8006010[10:0] = 0x00000001U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U
- // .. .. reg_ddrc_w_xact_run_length = 0x8
- // .. .. ==> 0XF8006010[14:11] = 0x00000008U
- // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U
- // .. .. reg_ddrc_w_max_starve_x32 = 0x2
- // .. .. ==> 0XF8006010[25:15] = 0x00000002U
- // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U
- // .. ..
- EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
- // .. .. reg_ddrc_t_rc = 0x1b
- // .. .. ==> 0XF8006014[5:0] = 0x0000001BU
- // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001BU
- // .. .. reg_ddrc_t_rfc_min = 0x56
- // .. .. ==> 0XF8006014[13:6] = 0x00000056U
- // .. .. ==> MASK : 0x00003FC0U VAL : 0x00001580U
- // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
- // .. .. ==> 0XF8006014[20:14] = 0x00000010U
- // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U
- // .. ..
- EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004159BU),
- // .. .. reg_ddrc_wr2pre = 0x12
- // .. .. ==> 0XF8006018[4:0] = 0x00000012U
- // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U
- // .. .. reg_ddrc_powerdown_to_x32 = 0x6
- // .. .. ==> 0XF8006018[9:5] = 0x00000006U
- // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U
- // .. .. reg_ddrc_t_faw = 0x18
- // .. .. ==> 0XF8006018[15:10] = 0x00000018U
- // .. .. ==> MASK : 0x0000FC00U VAL : 0x00006000U
- // .. .. reg_ddrc_t_ras_max = 0x24
- // .. .. ==> 0XF8006018[21:16] = 0x00000024U
- // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U
- // .. .. reg_ddrc_t_ras_min = 0x14
- // .. .. ==> 0XF8006018[26:22] = 0x00000014U
- // .. .. ==> MASK : 0x07C00000U VAL : 0x05000000U
- // .. .. reg_ddrc_t_cke = 0x4
- // .. .. ==> 0XF8006018[31:28] = 0x00000004U
- // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x452460D2U),
- // .. .. reg_ddrc_write_latency = 0x5
- // .. .. ==> 0XF800601C[4:0] = 0x00000005U
- // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U
- // .. .. reg_ddrc_rd2wr = 0x7
- // .. .. ==> 0XF800601C[9:5] = 0x00000007U
- // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U
- // .. .. reg_ddrc_wr2rd = 0xe
- // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
- // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U
- // .. .. reg_ddrc_t_xp = 0x4
- // .. .. ==> 0XF800601C[19:15] = 0x00000004U
- // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U
- // .. .. reg_ddrc_pad_pd = 0x0
- // .. .. ==> 0XF800601C[22:20] = 0x00000000U
- // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U
- // .. .. reg_ddrc_rd2pre = 0x4
- // .. .. ==> 0XF800601C[27:23] = 0x00000004U
- // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U
- // .. .. reg_ddrc_t_rcd = 0x7
- // .. .. ==> 0XF800601C[31:28] = 0x00000007U
- // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U
- // .. ..
- EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
- // .. .. reg_ddrc_t_ccd = 0x4
- // .. .. ==> 0XF8006020[4:2] = 0x00000004U
- // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U
- // .. .. reg_ddrc_t_rrd = 0x6
- // .. .. ==> 0XF8006020[7:5] = 0x00000006U
- // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U
- // .. .. reg_ddrc_refresh_margin = 0x2
- // .. .. ==> 0XF8006020[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. reg_ddrc_t_rp = 0x7
- // .. .. ==> 0XF8006020[15:12] = 0x00000007U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U
- // .. .. reg_ddrc_refresh_to_x32 = 0x8
- // .. .. ==> 0XF8006020[20:16] = 0x00000008U
- // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U
- // .. .. reg_ddrc_sdram = 0x1
- // .. .. ==> 0XF8006020[21:21] = 0x00000001U
- // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U
- // .. .. reg_ddrc_mobile = 0x0
- // .. .. ==> 0XF8006020[22:22] = 0x00000000U
- // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U
- // .. .. reg_ddrc_clock_stop_en = 0x0
- // .. .. ==> 0XF8006020[23:23] = 0x00000000U
- // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U
- // .. .. reg_ddrc_read_latency = 0x7
- // .. .. ==> 0XF8006020[28:24] = 0x00000007U
- // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U
- // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
- // .. .. ==> 0XF8006020[29:29] = 0x00000001U
- // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U
- // .. .. reg_ddrc_dis_pad_pd = 0x0
- // .. .. ==> 0XF8006020[30:30] = 0x00000000U
- // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U
- // .. .. reg_ddrc_loopback = 0x0
- // .. .. ==> 0XF8006020[31:31] = 0x00000000U
- // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U),
- // .. .. reg_ddrc_en_2t_timing_mode = 0x0
- // .. .. ==> 0XF8006024[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_prefer_write = 0x0
- // .. .. ==> 0XF8006024[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_ddrc_max_rank_rd = 0xf
- // .. .. ==> 0XF8006024[5:2] = 0x0000000FU
- // .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU
- // .. .. reg_ddrc_mr_wr = 0x0
- // .. .. ==> 0XF8006024[6:6] = 0x00000000U
- // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_addr = 0x0
- // .. .. ==> 0XF8006024[8:7] = 0x00000000U
- // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_data = 0x0
- // .. .. ==> 0XF8006024[24:9] = 0x00000000U
- // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U
- // .. .. ddrc_reg_mr_wr_busy = 0x0
- // .. .. ==> 0XF8006024[25:25] = 0x00000000U
- // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_type = 0x0
- // .. .. ==> 0XF8006024[26:26] = 0x00000000U
- // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_rdata_valid = 0x0
- // .. .. ==> 0XF8006024[27:27] = 0x00000000U
- // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU),
- // .. .. reg_ddrc_final_wait_x32 = 0x7
- // .. .. ==> 0XF8006028[6:0] = 0x00000007U
- // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U
- // .. .. reg_ddrc_pre_ocd_x32 = 0x0
- // .. .. ==> 0XF8006028[10:7] = 0x00000000U
- // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U
- // .. .. reg_ddrc_t_mrd = 0x4
- // .. .. ==> 0XF8006028[13:11] = 0x00000004U
- // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U
- // .. ..
- EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
- // .. .. reg_ddrc_emr2 = 0x8
- // .. .. ==> 0XF800602C[15:0] = 0x00000008U
- // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U
- // .. .. reg_ddrc_emr3 = 0x0
- // .. .. ==> 0XF800602C[31:16] = 0x00000000U
- // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
- // .. .. reg_ddrc_mr = 0x930
- // .. .. ==> 0XF8006030[15:0] = 0x00000930U
- // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U
- // .. .. reg_ddrc_emr = 0x4
- // .. .. ==> 0XF8006030[31:16] = 0x00000004U
- // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U
- // .. ..
- EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
- // .. .. reg_ddrc_burst_rdwr = 0x4
- // .. .. ==> 0XF8006034[3:0] = 0x00000004U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U
- // .. .. reg_ddrc_pre_cke_x1024 = 0x105
- // .. .. ==> 0XF8006034[13:4] = 0x00000105U
- // .. .. ==> MASK : 0x00003FF0U VAL : 0x00001050U
- // .. .. reg_ddrc_post_cke_x1024 = 0x1
- // .. .. ==> 0XF8006034[25:16] = 0x00000001U
- // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U
- // .. .. reg_ddrc_burstchop = 0x0
- // .. .. ==> 0XF8006034[28:28] = 0x00000000U
- // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U),
- // .. .. reg_ddrc_force_low_pri_n = 0x0
- // .. .. ==> 0XF8006038[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_dq = 0x0
- // .. .. ==> 0XF8006038[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_debug_mode = 0x0
- // .. .. ==> 0XF8006038[6:6] = 0x00000000U
- // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U
- // .. .. reg_phy_wr_level_start = 0x0
- // .. .. ==> 0XF8006038[7:7] = 0x00000000U
- // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. .. reg_phy_rd_level_start = 0x0
- // .. .. ==> 0XF8006038[8:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. .. reg_phy_dq0_wait_t = 0x0
- // .. .. ==> 0XF8006038[12:9] = 0x00000000U
- // .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U),
- // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
- // .. .. ==> 0XF800603C[3:0] = 0x00000007U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U
- // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
- // .. .. ==> 0XF800603C[7:4] = 0x00000007U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U
- // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
- // .. .. ==> 0XF800603C[11:8] = 0x00000007U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U
- // .. .. reg_ddrc_addrmap_col_b5 = 0x0
- // .. .. ==> 0XF800603C[15:12] = 0x00000000U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b6 = 0x0
- // .. .. ==> 0XF800603C[19:16] = 0x00000000U
- // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
- // .. .. reg_ddrc_addrmap_col_b2 = 0x0
- // .. .. ==> 0XF8006040[3:0] = 0x00000000U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b3 = 0x0
- // .. .. ==> 0XF8006040[7:4] = 0x00000000U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b4 = 0x0
- // .. .. ==> 0XF8006040[11:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b7 = 0x0
- // .. .. ==> 0XF8006040[15:12] = 0x00000000U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b8 = 0x0
- // .. .. ==> 0XF8006040[19:16] = 0x00000000U
- // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b9 = 0xf
- // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
- // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U
- // .. .. reg_ddrc_addrmap_col_b10 = 0xf
- // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
- // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U
- // .. .. reg_ddrc_addrmap_col_b11 = 0xf
- // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
- // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
- // .. .. reg_ddrc_addrmap_row_b0 = 0x6
- // .. .. ==> 0XF8006044[3:0] = 0x00000006U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U
- // .. .. reg_ddrc_addrmap_row_b1 = 0x6
- // .. .. ==> 0XF8006044[7:4] = 0x00000006U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U
- // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
- // .. .. ==> 0XF8006044[11:8] = 0x00000006U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U
- // .. .. reg_ddrc_addrmap_row_b12 = 0x6
- // .. .. ==> 0XF8006044[15:12] = 0x00000006U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U
- // .. .. reg_ddrc_addrmap_row_b13 = 0x6
- // .. .. ==> 0XF8006044[19:16] = 0x00000006U
- // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U
- // .. .. reg_ddrc_addrmap_row_b14 = 0xf
- // .. .. ==> 0XF8006044[23:20] = 0x0000000FU
- // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U
- // .. .. reg_ddrc_addrmap_row_b15 = 0xf
- // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
- // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0FF66666U),
- // .. .. reg_ddrc_rank0_rd_odt = 0x0
- // .. .. ==> 0XF8006048[2:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U
- // .. .. reg_ddrc_rank0_wr_odt = 0x1
- // .. .. ==> 0XF8006048[5:3] = 0x00000001U
- // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U
- // .. .. reg_ddrc_rank1_rd_odt = 0x1
- // .. .. ==> 0XF8006048[8:6] = 0x00000001U
- // .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U
- // .. .. reg_ddrc_rank1_wr_odt = 0x1
- // .. .. ==> 0XF8006048[11:9] = 0x00000001U
- // .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. .. reg_phy_rd_local_odt = 0x0
- // .. .. ==> 0XF8006048[13:12] = 0x00000000U
- // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U
- // .. .. reg_phy_wr_local_odt = 0x3
- // .. .. ==> 0XF8006048[15:14] = 0x00000003U
- // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U
- // .. .. reg_phy_idle_local_odt = 0x3
- // .. .. ==> 0XF8006048[17:16] = 0x00000003U
- // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U
- // .. .. reg_ddrc_rank2_rd_odt = 0x0
- // .. .. ==> 0XF8006048[20:18] = 0x00000000U
- // .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U
- // .. .. reg_ddrc_rank2_wr_odt = 0x0
- // .. .. ==> 0XF8006048[23:21] = 0x00000000U
- // .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U
- // .. .. reg_ddrc_rank3_rd_odt = 0x0
- // .. .. ==> 0XF8006048[26:24] = 0x00000000U
- // .. .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. .. reg_ddrc_rank3_wr_odt = 0x0
- // .. .. ==> 0XF8006048[29:27] = 0x00000000U
- // .. .. ==> MASK : 0x38000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U),
- // .. .. reg_phy_rd_cmd_to_data = 0x0
- // .. .. ==> 0XF8006050[3:0] = 0x00000000U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
- // .. .. reg_phy_wr_cmd_to_data = 0x0
- // .. .. ==> 0XF8006050[7:4] = 0x00000000U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. .. reg_phy_rdc_we_to_re_delay = 0x8
- // .. .. ==> 0XF8006050[11:8] = 0x00000008U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U
- // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
- // .. .. ==> 0XF8006050[15:15] = 0x00000000U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
- // .. .. reg_phy_use_fixed_re = 0x1
- // .. .. ==> 0XF8006050[16:16] = 0x00000001U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U
- // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
- // .. .. ==> 0XF8006050[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
- // .. .. ==> 0XF8006050[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_phy_clk_stall_level = 0x0
- // .. .. ==> 0XF8006050[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
- // .. .. ==> 0XF8006050[27:24] = 0x00000007U
- // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U
- // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
- // .. .. ==> 0XF8006050[31:28] = 0x00000007U
- // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
- // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1
- // .. .. ==> 0XF8006058[7:0] = 0x00000001U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U
- // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1
- // .. .. ==> 0XF8006058[15:8] = 0x00000001U
- // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U
- // .. .. reg_ddrc_dis_dll_calib = 0x0
- // .. .. ==> 0XF8006058[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U),
- // .. .. reg_ddrc_rd_odt_delay = 0x3
- // .. .. ==> 0XF800605C[3:0] = 0x00000003U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U
- // .. .. reg_ddrc_wr_odt_delay = 0x0
- // .. .. ==> 0XF800605C[7:4] = 0x00000000U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. .. reg_ddrc_rd_odt_hold = 0x0
- // .. .. ==> 0XF800605C[11:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U
- // .. .. reg_ddrc_wr_odt_hold = 0x5
- // .. .. ==> 0XF800605C[15:12] = 0x00000005U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U
- // .. ..
- EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
- // .. .. reg_ddrc_pageclose = 0x0
- // .. .. ==> 0XF8006060[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_lpr_num_entries = 0x1f
- // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
- // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU
- // .. .. reg_ddrc_auto_pre_en = 0x0
- // .. .. ==> 0XF8006060[7:7] = 0x00000000U
- // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. .. reg_ddrc_refresh_update_level = 0x0
- // .. .. ==> 0XF8006060[8:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_wc = 0x0
- // .. .. ==> 0XF8006060[9:9] = 0x00000000U
- // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_collision_page_opt = 0x0
- // .. .. ==> 0XF8006060[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_ddrc_selfref_en = 0x0
- // .. .. ==> 0XF8006060[12:12] = 0x00000000U
- // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
- // .. .. reg_ddrc_go2critical_hysteresis = 0x0
- // .. .. ==> 0XF8006064[12:5] = 0x00000000U
- // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U
- // .. .. reg_arb_go2critical_en = 0x1
- // .. .. ==> 0XF8006064[17:17] = 0x00000001U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U
- // .. ..
- EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
- // .. .. reg_ddrc_wrlvl_ww = 0x41
- // .. .. ==> 0XF8006068[7:0] = 0x00000041U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U
- // .. .. reg_ddrc_rdlvl_rr = 0x41
- // .. .. ==> 0XF8006068[15:8] = 0x00000041U
- // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U
- // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
- // .. .. ==> 0XF8006068[25:16] = 0x00000028U
- // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U
- // .. ..
- EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
- // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
- // .. .. ==> 0XF800606C[7:0] = 0x00000010U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U
- // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
- // .. .. ==> 0XF800606C[15:8] = 0x00000016U
- // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U
- // .. ..
- EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
- // .. .. refresh_timer0_start_value_x32 = 0x0
- // .. .. ==> 0XF80060A0[11:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U
- // .. .. refresh_timer1_start_value_x32 = 0x8
- // .. .. ==> 0XF80060A0[23:12] = 0x00000008U
- // .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U
- // .. ..
- EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U),
- // .. .. reg_ddrc_dis_auto_zq = 0x0
- // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_ddr3 = 0x1
- // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. .. reg_ddrc_t_mod = 0x200
- // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
- // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U
- // .. .. reg_ddrc_t_zq_long_nop = 0x200
- // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
- // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U
- // .. .. reg_ddrc_t_zq_short_nop = 0x40
- // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
- // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
- // .. .. t_zq_short_interval_x1024 = 0xcb73
- // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U
- // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U
- // .. .. dram_rstn_x1024 = 0x69
- // .. .. ==> 0XF80060A8[27:20] = 0x00000069U
- // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U
- // .. ..
- EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
- // .. .. deeppowerdown_en = 0x0
- // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. deeppowerdown_to_x1024 = 0xff
- // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
- // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU
- // .. ..
- EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
- // .. .. dfi_wrlvl_max_x1024 = 0xfff
- // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
- // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU
- // .. .. dfi_rdlvl_max_x1024 = 0xfff
- // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
- // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U
- // .. .. ddrc_reg_twrlvl_max_error = 0x0
- // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
- // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U
- // .. .. ddrc_reg_trdlvl_max_error = 0x0
- // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
- // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
- // .. .. reg_ddrc_dfi_wr_level_en = 0x1
- // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
- // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U
- // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
- // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
- // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U
- // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
- // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
- // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
- // .. .. reg_ddrc_2t_delay = 0x0
- // .. .. ==> 0XF80060B4[8:0] = 0x00000000U
- // .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U
- // .. .. reg_ddrc_skip_ocd = 0x1
- // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
- // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U
- // .. .. reg_ddrc_dis_pre_bypass = 0x0
- // .. .. ==> 0XF80060B4[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U),
- // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
- // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
- // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U
- // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
- // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
- // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U
- // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
- // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
- // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U
- // .. ..
- EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
- // .. .. START: RESET ECC ERROR
- // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1
- // .. .. ==> 0XF80060C4[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. Clear_Correctable_DRAM_ECC_error = 1
- // .. .. ==> 0XF80060C4[1:1] = 0x00000001U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. ..
- EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U),
- // .. .. FINISH: RESET ECC ERROR
- // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
- // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
- // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
- // .. .. CORR_ECC_LOG_VALID = 0x0
- // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. ECC_CORRECTED_BIT_NUM = 0x0
- // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
- // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
- // .. .. UNCORR_ECC_LOG_VALID = 0x0
- // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
- // .. .. STAT_NUM_CORR_ERR = 0x0
- // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
- // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U
- // .. .. STAT_NUM_UNCORR_ERR = 0x0
- // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
- // .. .. reg_ddrc_ecc_mode = 0x0
- // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_scrub = 0x1
- // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U
- // .. ..
- EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
- // .. .. reg_phy_dif_on = 0x0
- // .. .. ==> 0XF8006114[3:0] = 0x00000000U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
- // .. .. reg_phy_dif_off = 0x0
- // .. .. ==> 0XF8006114[7:4] = 0x00000000U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
- // .. .. reg_phy_data_slice_in_use = 0x1
- // .. .. ==> 0XF8006118[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_phy_rdlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006118[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_inc_mode = 0x0
- // .. .. ==> 0XF8006118[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_wrlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006118[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_tx = 0x0
- // .. .. ==> 0XF8006118[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_rx = 0x0
- // .. .. ==> 0XF8006118[5:5] = 0x00000000U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. .. reg_phy_bist_shift_dq = 0x0
- // .. .. ==> 0XF8006118[14:6] = 0x00000000U
- // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. .. reg_phy_bist_err_clr = 0x0
- // .. .. ==> 0XF8006118[23:15] = 0x00000000U
- // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. .. reg_phy_dq_offset = 0x40
- // .. .. ==> 0XF8006118[30:24] = 0x00000040U
- // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U),
- // .. .. reg_phy_data_slice_in_use = 0x1
- // .. .. ==> 0XF800611C[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_phy_rdlvl_inc_mode = 0x0
- // .. .. ==> 0XF800611C[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_inc_mode = 0x0
- // .. .. ==> 0XF800611C[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_wrlvl_inc_mode = 0x0
- // .. .. ==> 0XF800611C[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_tx = 0x0
- // .. .. ==> 0XF800611C[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_rx = 0x0
- // .. .. ==> 0XF800611C[5:5] = 0x00000000U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. .. reg_phy_bist_shift_dq = 0x0
- // .. .. ==> 0XF800611C[14:6] = 0x00000000U
- // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. .. reg_phy_bist_err_clr = 0x0
- // .. .. ==> 0XF800611C[23:15] = 0x00000000U
- // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. .. reg_phy_dq_offset = 0x40
- // .. .. ==> 0XF800611C[30:24] = 0x00000040U
- // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U),
- // .. .. reg_phy_data_slice_in_use = 0x1
- // .. .. ==> 0XF8006120[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_phy_rdlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006120[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_inc_mode = 0x0
- // .. .. ==> 0XF8006120[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_wrlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006120[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_tx = 0x0
- // .. .. ==> 0XF8006120[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_rx = 0x0
- // .. .. ==> 0XF8006120[5:5] = 0x00000000U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. .. reg_phy_bist_shift_dq = 0x0
- // .. .. ==> 0XF8006120[14:6] = 0x00000000U
- // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. .. reg_phy_bist_err_clr = 0x0
- // .. .. ==> 0XF8006120[23:15] = 0x00000000U
- // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. .. reg_phy_dq_offset = 0x40
- // .. .. ==> 0XF8006120[30:24] = 0x00000040U
- // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U),
- // .. .. reg_phy_data_slice_in_use = 0x1
- // .. .. ==> 0XF8006124[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_phy_rdlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006124[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_inc_mode = 0x0
- // .. .. ==> 0XF8006124[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_wrlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006124[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_tx = 0x0
- // .. .. ==> 0XF8006124[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_rx = 0x0
- // .. .. ==> 0XF8006124[5:5] = 0x00000000U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. .. reg_phy_bist_shift_dq = 0x0
- // .. .. ==> 0XF8006124[14:6] = 0x00000000U
- // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. .. reg_phy_bist_err_clr = 0x0
- // .. .. ==> 0XF8006124[23:15] = 0x00000000U
- // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. .. reg_phy_dq_offset = 0x40
- // .. .. ==> 0XF8006124[30:24] = 0x00000040U
- // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U),
- // .. .. reg_phy_wrlvl_init_ratio = 0x3
- // .. .. ==> 0XF800612C[9:0] = 0x00000003U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000003U
- // .. .. reg_phy_gatelvl_init_ratio = 0xcf
- // .. .. ==> 0XF800612C[19:10] = 0x000000CFU
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x00033C00U
- // .. ..
- EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00033C03U),
- // .. .. reg_phy_wrlvl_init_ratio = 0x3
- // .. .. ==> 0XF8006130[9:0] = 0x00000003U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000003U
- // .. .. reg_phy_gatelvl_init_ratio = 0xd0
- // .. .. ==> 0XF8006130[19:10] = 0x000000D0U
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x00034000U
- // .. ..
- EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00034003U),
- // .. .. reg_phy_wrlvl_init_ratio = 0x0
- // .. .. ==> 0XF8006134[9:0] = 0x00000000U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_init_ratio = 0xbd
- // .. .. ==> 0XF8006134[19:10] = 0x000000BDU
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002F400U
- // .. ..
- EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0002F400U),
- // .. .. reg_phy_wrlvl_init_ratio = 0x0
- // .. .. ==> 0XF8006138[9:0] = 0x00000000U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_init_ratio = 0xc1
- // .. .. ==> 0XF8006138[19:10] = 0x000000C1U
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x00030400U
- // .. ..
- EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x00030400U),
- // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. .. ==> 0XF8006140[9:0] = 0x00000035U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. .. reg_phy_rd_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006140[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006140[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
- // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. .. ==> 0XF8006144[9:0] = 0x00000035U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. .. reg_phy_rd_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006144[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006144[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
- // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. .. ==> 0XF8006148[9:0] = 0x00000035U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. .. reg_phy_rd_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006148[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006148[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
- // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. .. ==> 0XF800614C[9:0] = 0x00000035U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. .. reg_phy_rd_dqs_slave_force = 0x0
- // .. .. ==> 0XF800614C[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. .. ==> 0XF800614C[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
- // .. .. reg_phy_wr_dqs_slave_ratio = 0x83
- // .. .. ==> 0XF8006154[9:0] = 0x00000083U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000083U
- // .. .. reg_phy_wr_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006154[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006154[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000083U),
- // .. .. reg_phy_wr_dqs_slave_ratio = 0x83
- // .. .. ==> 0XF8006158[9:0] = 0x00000083U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000083U
- // .. .. reg_phy_wr_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006158[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006158[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000083U),
- // .. .. reg_phy_wr_dqs_slave_ratio = 0x7f
- // .. .. ==> 0XF800615C[9:0] = 0x0000007FU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x0000007FU
- // .. .. reg_phy_wr_dqs_slave_force = 0x0
- // .. .. ==> 0XF800615C[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. .. ==> 0XF800615C[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x0000007FU),
- // .. .. reg_phy_wr_dqs_slave_ratio = 0x78
- // .. .. ==> 0XF8006160[9:0] = 0x00000078U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000078U
- // .. .. reg_phy_wr_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006160[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006160[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000078U),
- // .. .. reg_phy_fifo_we_slave_ratio = 0x124
- // .. .. ==> 0XF8006168[10:0] = 0x00000124U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x00000124U
- // .. .. reg_phy_fifo_we_in_force = 0x0
- // .. .. ==> 0XF8006168[11:11] = 0x00000000U
- // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. .. reg_phy_fifo_we_in_delay = 0x0
- // .. .. ==> 0XF8006168[20:12] = 0x00000000U
- // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000124U),
- // .. .. reg_phy_fifo_we_slave_ratio = 0x125
- // .. .. ==> 0XF800616C[10:0] = 0x00000125U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x00000125U
- // .. .. reg_phy_fifo_we_in_force = 0x0
- // .. .. ==> 0XF800616C[11:11] = 0x00000000U
- // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. .. reg_phy_fifo_we_in_delay = 0x0
- // .. .. ==> 0XF800616C[20:12] = 0x00000000U
- // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x00000125U),
- // .. .. reg_phy_fifo_we_slave_ratio = 0x112
- // .. .. ==> 0XF8006170[10:0] = 0x00000112U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x00000112U
- // .. .. reg_phy_fifo_we_in_force = 0x0
- // .. .. ==> 0XF8006170[11:11] = 0x00000000U
- // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. .. reg_phy_fifo_we_in_delay = 0x0
- // .. .. ==> 0XF8006170[20:12] = 0x00000000U
- // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000112U),
- // .. .. reg_phy_fifo_we_slave_ratio = 0x116
- // .. .. ==> 0XF8006174[10:0] = 0x00000116U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x00000116U
- // .. .. reg_phy_fifo_we_in_force = 0x0
- // .. .. ==> 0XF8006174[11:11] = 0x00000000U
- // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. .. reg_phy_fifo_we_in_delay = 0x0
- // .. .. ==> 0XF8006174[20:12] = 0x00000000U
- // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000116U),
- // .. .. reg_phy_wr_data_slave_ratio = 0xc3
- // .. .. ==> 0XF800617C[9:0] = 0x000000C3U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C3U
- // .. .. reg_phy_wr_data_slave_force = 0x0
- // .. .. ==> 0XF800617C[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_data_slave_delay = 0x0
- // .. .. ==> 0XF800617C[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000C3U),
- // .. .. reg_phy_wr_data_slave_ratio = 0xc3
- // .. .. ==> 0XF8006180[9:0] = 0x000000C3U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C3U
- // .. .. reg_phy_wr_data_slave_force = 0x0
- // .. .. ==> 0XF8006180[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_data_slave_delay = 0x0
- // .. .. ==> 0XF8006180[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000C3U),
- // .. .. reg_phy_wr_data_slave_ratio = 0xbf
- // .. .. ==> 0XF8006184[9:0] = 0x000000BFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000000BFU
- // .. .. reg_phy_wr_data_slave_force = 0x0
- // .. .. ==> 0XF8006184[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_data_slave_delay = 0x0
- // .. .. ==> 0XF8006184[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000BFU),
- // .. .. reg_phy_wr_data_slave_ratio = 0xb8
- // .. .. ==> 0XF8006188[9:0] = 0x000000B8U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000000B8U
- // .. .. reg_phy_wr_data_slave_force = 0x0
- // .. .. ==> 0XF8006188[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_data_slave_delay = 0x0
- // .. .. ==> 0XF8006188[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000B8U),
- // .. .. reg_phy_loopback = 0x0
- // .. .. ==> 0XF8006190[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_phy_bl2 = 0x0
- // .. .. ==> 0XF8006190[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_at_spd_atpg = 0x0
- // .. .. ==> 0XF8006190[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_bist_enable = 0x0
- // .. .. ==> 0XF8006190[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_bist_force_err = 0x0
- // .. .. ==> 0XF8006190[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. reg_phy_bist_mode = 0x0
- // .. .. ==> 0XF8006190[6:5] = 0x00000000U
- // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. .. reg_phy_invert_clkout = 0x1
- // .. .. ==> 0XF8006190[7:7] = 0x00000001U
- // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0
- // .. .. ==> 0XF8006190[8:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. .. reg_phy_sel_logic = 0x0
- // .. .. ==> 0XF8006190[9:9] = 0x00000000U
- // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U
- // .. .. reg_phy_ctrl_slave_ratio = 0x100
- // .. .. ==> 0XF8006190[19:10] = 0x00000100U
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U
- // .. .. reg_phy_ctrl_slave_force = 0x0
- // .. .. ==> 0XF8006190[20:20] = 0x00000000U
- // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U
- // .. .. reg_phy_ctrl_slave_delay = 0x0
- // .. .. ==> 0XF8006190[27:21] = 0x00000000U
- // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U
- // .. .. reg_phy_use_rank0_delays = 0x1
- // .. .. ==> 0XF8006190[28:28] = 0x00000001U
- // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
- // .. .. reg_phy_lpddr = 0x0
- // .. .. ==> 0XF8006190[29:29] = 0x00000000U
- // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U
- // .. .. reg_phy_cmd_latency = 0x0
- // .. .. ==> 0XF8006190[30:30] = 0x00000000U
- // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U
- // .. .. reg_phy_int_lpbk = 0x0
- // .. .. ==> 0XF8006190[31:31] = 0x00000000U
- // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U),
- // .. .. reg_phy_wr_rl_delay = 0x2
- // .. .. ==> 0XF8006194[4:0] = 0x00000002U
- // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U
- // .. .. reg_phy_rd_rl_delay = 0x4
- // .. .. ==> 0XF8006194[9:5] = 0x00000004U
- // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U
- // .. .. reg_phy_dll_lock_diff = 0xf
- // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
- // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U
- // .. .. reg_phy_use_wr_level = 0x1
- // .. .. ==> 0XF8006194[14:14] = 0x00000001U
- // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U
- // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
- // .. .. ==> 0XF8006194[15:15] = 0x00000001U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U
- // .. .. reg_phy_use_rd_data_eye_level = 0x1
- // .. .. ==> 0XF8006194[16:16] = 0x00000001U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U
- // .. .. reg_phy_dis_calib_rst = 0x0
- // .. .. ==> 0XF8006194[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_phy_ctrl_slave_delay = 0x0
- // .. .. ==> 0XF8006194[19:18] = 0x00000000U
- // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
- // .. .. reg_arb_page_addr_mask = 0x0
- // .. .. ==> 0XF8006204[31:0] = 0x00000000U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
- // .. .. reg_arb_pri_wr_portn = 0x3ff
- // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_wr_portn = 0x0
- // .. .. ==> 0XF8006208[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. .. ==> 0XF8006208[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. .. ==> 0XF8006208[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_dis_rmw_portn = 0x1
- // .. .. ==> 0XF8006208[19:19] = 0x00000001U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // .. ..
- EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU),
- // .. .. reg_arb_pri_wr_portn = 0x3ff
- // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_wr_portn = 0x0
- // .. .. ==> 0XF800620C[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. .. ==> 0XF800620C[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. .. ==> 0XF800620C[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_dis_rmw_portn = 0x1
- // .. .. ==> 0XF800620C[19:19] = 0x00000001U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // .. ..
- EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU),
- // .. .. reg_arb_pri_wr_portn = 0x3ff
- // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_wr_portn = 0x0
- // .. .. ==> 0XF8006210[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. .. ==> 0XF8006210[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. .. ==> 0XF8006210[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_dis_rmw_portn = 0x1
- // .. .. ==> 0XF8006210[19:19] = 0x00000001U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // .. ..
- EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU),
- // .. .. reg_arb_pri_wr_portn = 0x3ff
- // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_wr_portn = 0x0
- // .. .. ==> 0XF8006214[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. .. ==> 0XF8006214[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. .. ==> 0XF8006214[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_dis_rmw_portn = 0x1
- // .. .. ==> 0XF8006214[19:19] = 0x00000001U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // .. ..
- EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU),
- // .. .. reg_arb_pri_rd_portn = 0x3ff
- // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_rd_portn = 0x0
- // .. .. ==> 0XF8006218[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. .. ==> 0XF8006218[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. .. ==> 0XF8006218[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_set_hpr_rd_portn = 0x0
- // .. .. ==> 0XF8006218[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
- // .. .. reg_arb_pri_rd_portn = 0x3ff
- // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_rd_portn = 0x0
- // .. .. ==> 0XF800621C[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. .. ==> 0XF800621C[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. .. ==> 0XF800621C[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_set_hpr_rd_portn = 0x0
- // .. .. ==> 0XF800621C[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
- // .. .. reg_arb_pri_rd_portn = 0x3ff
- // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_rd_portn = 0x0
- // .. .. ==> 0XF8006220[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. .. ==> 0XF8006220[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. .. ==> 0XF8006220[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_set_hpr_rd_portn = 0x0
- // .. .. ==> 0XF8006220[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
- // .. .. reg_arb_pri_rd_portn = 0x3ff
- // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_rd_portn = 0x0
- // .. .. ==> 0XF8006224[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. .. ==> 0XF8006224[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. .. ==> 0XF8006224[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_set_hpr_rd_portn = 0x0
- // .. .. ==> 0XF8006224[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
- // .. .. reg_ddrc_lpddr2 = 0x0
- // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_per_bank_refresh = 0x0
- // .. .. ==> 0XF80062A8[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_ddrc_derate_enable = 0x0
- // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_ddrc_mr4_margin = 0x0
- // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U),
- // .. .. reg_ddrc_mr4_read_interval = 0x0
- // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
- // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
- // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U
- // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
- // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
- // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U
- // .. .. reg_ddrc_t_mrw = 0x5
- // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
- // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U
- // .. ..
- EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
- // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8
- // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U
- // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
- // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
- // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U
- // .. ..
- EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
- // .. .. START: POLL ON DCI STATUS
- // .. .. DONE = 1
- // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
- // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // .. ..
- EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
- // .. .. FINISH: POLL ON DCI STATUS
- // .. .. START: UNLOCK DDR
- // .. .. reg_ddrc_soft_rstb = 0x1
- // .. .. ==> 0XF8006000[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_ddrc_powerdown_en = 0x0
- // .. .. ==> 0XF8006000[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_ddrc_data_bus_width = 0x0
- // .. .. ==> 0XF8006000[3:2] = 0x00000000U
- // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U
- // .. .. reg_ddrc_burst8_refresh = 0x0
- // .. .. ==> 0XF8006000[6:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U
- // .. .. reg_ddrc_rdwr_idle_gap = 1
- // .. .. ==> 0XF8006000[13:7] = 0x00000001U
- // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U
- // .. .. reg_ddrc_dis_rd_bypass = 0x0
- // .. .. ==> 0XF8006000[14:14] = 0x00000000U
- // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_act_bypass = 0x0
- // .. .. ==> 0XF8006000[15:15] = 0x00000000U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_auto_refresh = 0x0
- // .. .. ==> 0XF8006000[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
- // .. .. FINISH: UNLOCK DDR
- // .. .. START: CHECK DDR STATUS
- // .. .. ddrc_reg_operating_mode = 1
- // .. .. ==> 0XF8006054[2:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U
- // .. ..
- EMIT_MASKPOLL(0XF8006054, 0x00000007U),
- // .. .. FINISH: CHECK DDR STATUS
- // .. FINISH: DDR INITIALIZATION
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_mio_init_data_1_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: OCM REMAPPING
- // .. FINISH: OCM REMAPPING
- // .. START: DDRIOB SETTINGS
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B40[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x0
- // .. ==> 0XF8000B40[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B40[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x0
- // .. ==> 0XF8000B40[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. DCR_TYPE = 0x0
- // .. ==> 0XF8000B40[6:5] = 0x00000000U
- // .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. IBUF_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B40[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B40[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B40[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B40[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B44[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x0
- // .. ==> 0XF8000B44[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B44[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x0
- // .. ==> 0XF8000B44[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. DCR_TYPE = 0x0
- // .. ==> 0XF8000B44[6:5] = 0x00000000U
- // .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. IBUF_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B44[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B44[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B44[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B44[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B48[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x1
- // .. ==> 0XF8000B48[2:1] = 0x00000001U
- // .. ==> MASK : 0x00000006U VAL : 0x00000002U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B48[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x1
- // .. ==> 0XF8000B48[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. DCR_TYPE = 0x3
- // .. ==> 0XF8000B48[6:5] = 0x00000003U
- // .. ==> MASK : 0x00000060U VAL : 0x00000060U
- // .. IBUF_DISABLE_MODE = 0
- // .. ==> 0XF8000B48[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0
- // .. ==> 0XF8000B48[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B48[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B48[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B4C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x1
- // .. ==> 0XF8000B4C[2:1] = 0x00000001U
- // .. ==> MASK : 0x00000006U VAL : 0x00000002U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B4C[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x1
- // .. ==> 0XF8000B4C[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. DCR_TYPE = 0x3
- // .. ==> 0XF8000B4C[6:5] = 0x00000003U
- // .. ==> MASK : 0x00000060U VAL : 0x00000060U
- // .. IBUF_DISABLE_MODE = 0
- // .. ==> 0XF8000B4C[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0
- // .. ==> 0XF8000B4C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B4C[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B4C[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B50[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x2
- // .. ==> 0XF8000B50[2:1] = 0x00000002U
- // .. ==> MASK : 0x00000006U VAL : 0x00000004U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B50[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x1
- // .. ==> 0XF8000B50[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. DCR_TYPE = 0x3
- // .. ==> 0XF8000B50[6:5] = 0x00000003U
- // .. ==> MASK : 0x00000060U VAL : 0x00000060U
- // .. IBUF_DISABLE_MODE = 0
- // .. ==> 0XF8000B50[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0
- // .. ==> 0XF8000B50[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B50[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B50[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B54[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x2
- // .. ==> 0XF8000B54[2:1] = 0x00000002U
- // .. ==> MASK : 0x00000006U VAL : 0x00000004U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B54[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x1
- // .. ==> 0XF8000B54[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. DCR_TYPE = 0x3
- // .. ==> 0XF8000B54[6:5] = 0x00000003U
- // .. ==> MASK : 0x00000060U VAL : 0x00000060U
- // .. IBUF_DISABLE_MODE = 0
- // .. ==> 0XF8000B54[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0
- // .. ==> 0XF8000B54[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B54[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B54[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B58[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x0
- // .. ==> 0XF8000B58[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B58[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x0
- // .. ==> 0XF8000B58[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. DCR_TYPE = 0x0
- // .. ==> 0XF8000B58[6:5] = 0x00000000U
- // .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. IBUF_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B58[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B58[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B58[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B58[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
- // .. DRIVE_P = 0x1c
- // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
- // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
- // .. DRIVE_N = 0xc
- // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
- // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
- // .. SLEW_P = 0x3
- // .. ==> 0XF8000B5C[18:14] = 0x00000003U
- // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U
- // .. SLEW_N = 0x3
- // .. ==> 0XF8000B5C[23:19] = 0x00000003U
- // .. ==> MASK : 0x00F80000U VAL : 0x00180000U
- // .. GTL = 0x0
- // .. ==> 0XF8000B5C[26:24] = 0x00000000U
- // .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. RTERM = 0x0
- // .. ==> 0XF8000B5C[31:27] = 0x00000000U
- // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
- // .. DRIVE_P = 0x1c
- // .. ==> 0XF8000B60[6:0] = 0x0000001CU
- // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
- // .. DRIVE_N = 0xc
- // .. ==> 0XF8000B60[13:7] = 0x0000000CU
- // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
- // .. SLEW_P = 0x6
- // .. ==> 0XF8000B60[18:14] = 0x00000006U
- // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
- // .. SLEW_N = 0x1f
- // .. ==> 0XF8000B60[23:19] = 0x0000001FU
- // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
- // .. GTL = 0x0
- // .. ==> 0XF8000B60[26:24] = 0x00000000U
- // .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. RTERM = 0x0
- // .. ==> 0XF8000B60[31:27] = 0x00000000U
- // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
- // .. DRIVE_P = 0x1c
- // .. ==> 0XF8000B64[6:0] = 0x0000001CU
- // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
- // .. DRIVE_N = 0xc
- // .. ==> 0XF8000B64[13:7] = 0x0000000CU
- // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
- // .. SLEW_P = 0x6
- // .. ==> 0XF8000B64[18:14] = 0x00000006U
- // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
- // .. SLEW_N = 0x1f
- // .. ==> 0XF8000B64[23:19] = 0x0000001FU
- // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
- // .. GTL = 0x0
- // .. ==> 0XF8000B64[26:24] = 0x00000000U
- // .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. RTERM = 0x0
- // .. ==> 0XF8000B64[31:27] = 0x00000000U
- // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
- // .. DRIVE_P = 0x1c
- // .. ==> 0XF8000B68[6:0] = 0x0000001CU
- // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
- // .. DRIVE_N = 0xc
- // .. ==> 0XF8000B68[13:7] = 0x0000000CU
- // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
- // .. SLEW_P = 0x6
- // .. ==> 0XF8000B68[18:14] = 0x00000006U
- // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
- // .. SLEW_N = 0x1f
- // .. ==> 0XF8000B68[23:19] = 0x0000001FU
- // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
- // .. GTL = 0x0
- // .. ==> 0XF8000B68[26:24] = 0x00000000U
- // .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. RTERM = 0x0
- // .. ==> 0XF8000B68[31:27] = 0x00000000U
- // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
- // .. VREF_INT_EN = 0x1
- // .. ==> 0XF8000B6C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. VREF_SEL = 0x4
- // .. ==> 0XF8000B6C[4:1] = 0x00000004U
- // .. ==> MASK : 0x0000001EU VAL : 0x00000008U
- // .. VREF_EXT_EN = 0x0
- // .. ==> 0XF8000B6C[6:5] = 0x00000000U
- // .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. VREF_PULLUP_EN = 0x0
- // .. ==> 0XF8000B6C[8:7] = 0x00000000U
- // .. ==> MASK : 0x00000180U VAL : 0x00000000U
- // .. REFIO_EN = 0x1
- // .. ==> 0XF8000B6C[9:9] = 0x00000001U
- // .. ==> MASK : 0x00000200U VAL : 0x00000200U
- // .. REFIO_PULLUP_EN = 0x0
- // .. ==> 0XF8000B6C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DRST_B_PULLUP_EN = 0x0
- // .. ==> 0XF8000B6C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // .. CKE_PULLUP_EN = 0x0
- // .. ==> 0XF8000B6C[14:14] = 0x00000000U
- // .. ==> MASK : 0x00004000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B6C, 0x000073FFU ,0x00000209U),
- // .. .. START: ASSERT RESET
- // .. .. RESET = 1
- // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. VRN_OUT = 0x1
- // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
- // .. ..
- EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U),
- // .. .. FINISH: ASSERT RESET
- // .. .. START: DEASSERT RESET
- // .. .. RESET = 0
- // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. VRN_OUT = 0x1
- // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
- // .. ..
- EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
- // .. .. FINISH: DEASSERT RESET
- // .. .. RESET = 0x1
- // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ENABLE = 0x1
- // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. .. VRP_TRI = 0x0
- // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. VRN_TRI = 0x0
- // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. VRP_OUT = 0x0
- // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. VRN_OUT = 0x1
- // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
- // .. .. NREF_OPT1 = 0x0
- // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
- // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U
- // .. .. NREF_OPT2 = 0x0
- // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U
- // .. .. NREF_OPT4 = 0x1
- // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
- // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U
- // .. .. PREF_OPT1 = 0x0
- // .. .. ==> 0XF8000B70[16:14] = 0x00000000U
- // .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U
- // .. .. PREF_OPT2 = 0x0
- // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
- // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U
- // .. .. UPDATE_CONTROL = 0x0
- // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
- // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U
- // .. .. INIT_COMPLETE = 0x0
- // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
- // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U
- // .. .. TST_CLK = 0x0
- // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
- // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U
- // .. .. TST_HLN = 0x0
- // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
- // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U
- // .. .. TST_HLP = 0x0
- // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
- // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U
- // .. .. TST_RST = 0x0
- // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
- // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
- // .. .. INT_DCI_EN = 0x0
- // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
- // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U),
- // .. FINISH: DDRIOB SETTINGS
- // .. START: MIO PROGRAMMING
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000700[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000700[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000700[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000700[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000700[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000700[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000700[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000700[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000700[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00000600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000704[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000704[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000704[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000704[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000704[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000704[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 3
- // .. ==> 0XF8000704[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000704[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000704[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00000702U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000708[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000708[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000708[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000708[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000708[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000708[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 3
- // .. ==> 0XF8000708[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000708[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000708[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000702U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800070C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF800070C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF800070C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800070C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800070C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF800070C[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 3
- // .. ==> 0XF800070C[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF800070C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800070C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000702U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000710[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000710[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000710[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000710[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000710[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000710[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 3
- // .. ==> 0XF8000710[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000710[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000710[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000702U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000714[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000714[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000714[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000714[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000714[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000714[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 3
- // .. ==> 0XF8000714[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000714[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000714[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000702U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000718[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000718[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000718[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000718[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000718[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000718[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 3
- // .. ==> 0XF8000718[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000718[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000718[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000702U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800071C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800071C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF800071C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800071C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800071C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800071C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF800071C[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF800071C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800071C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000720[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000720[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000720[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000720[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000720[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000720[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 3
- // .. ==> 0XF8000720[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000720[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000720[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000700U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000724[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000724[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000724[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000724[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000724[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000724[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000724[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000724[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000724[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00000600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000728[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000728[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000728[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000728[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000728[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000728[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000728[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000728[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000728[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00000600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800072C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800072C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF800072C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800072C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800072C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800072C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF800072C[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF800072C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800072C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00000600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000730[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000730[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000730[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000730[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000730[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000730[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000730[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000730[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000730[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00000600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000734[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000734[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000734[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000734[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000734[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000734[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000734[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000734[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000734[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00000600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000738[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000738[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000738[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000738[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000738[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000738[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000738[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000738[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000738[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00000600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800073C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800073C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF800073C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800073C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800073C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800073C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF800073C[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF800073C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800073C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00000600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000740[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000740[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000740[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000740[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000740[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000740[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000740[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000740[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000740[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000302U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000744[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000744[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000744[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000744[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000744[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000744[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000744[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000744[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000744[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000302U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000748[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000748[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000748[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000748[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000748[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000748[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000748[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000748[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000748[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000302U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800074C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF800074C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF800074C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800074C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800074C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF800074C[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF800074C[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF800074C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800074C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000302U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000750[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000750[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000750[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000750[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000750[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000750[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000750[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000750[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000750[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000302U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000754[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000754[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000754[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000754[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000754[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000754[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000754[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000754[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000754[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000302U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000758[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF8000758[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000758[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000758[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000758[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000758[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000758[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000758[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000758[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000303U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF800075C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF800075C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF800075C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800075C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800075C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF800075C[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF800075C[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF800075C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800075C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000303U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000760[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF8000760[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000760[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000760[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000760[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000760[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000760[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000760[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000760[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000303U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000764[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF8000764[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000764[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000764[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000764[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000764[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000764[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000764[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000764[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000303U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000768[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF8000768[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000768[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000768[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000768[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000768[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000768[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000768[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000768[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000303U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF800076C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF800076C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF800076C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800076C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800076C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF800076C[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF800076C[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF800076C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800076C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000303U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000770[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000770[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000770[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000770[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000770[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000770[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000770[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000770[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000770[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000304U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000774[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF8000774[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000774[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000774[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000774[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000774[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000774[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000774[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000774[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000305U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000778[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000778[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000778[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000778[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000778[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000778[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000778[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000778[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000778[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000304U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF800077C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF800077C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF800077C[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF800077C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800077C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF800077C[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF800077C[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF800077C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800077C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000305U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000780[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000780[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000780[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000780[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000780[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000780[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000780[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000780[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000780[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000304U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000784[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000784[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000784[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000784[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000784[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000784[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000784[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000784[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000784[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000304U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000788[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000788[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000788[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000788[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000788[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000788[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000788[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000788[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000788[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000304U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800078C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800078C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF800078C[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF800078C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800078C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF800078C[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF800078C[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF800078C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800078C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000304U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000790[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF8000790[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000790[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000790[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000790[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000790[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000790[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000790[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000790[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000305U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000794[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000794[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000794[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000794[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000794[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000794[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000794[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000794[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000794[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000304U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000798[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000798[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000798[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000798[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000798[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF8000798[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF8000798[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF8000798[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000798[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000304U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800079C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800079C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF800079C[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF800079C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800079C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 1
- // .. ==> 0XF800079C[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF800079C[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF800079C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800079C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000304U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007A0[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007A0[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007A0[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007A0[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007A0[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 1
- // .. ==> 0XF80007A0[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF80007A0[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007A0[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007A0[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000380U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007A4[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007A4[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007A4[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007A4[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007A4[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 1
- // .. ==> 0XF80007A4[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF80007A4[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007A4[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007A4[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000380U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007A8[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007A8[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007A8[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007A8[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007A8[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 1
- // .. ==> 0XF80007A8[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF80007A8[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007A8[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007A8[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000380U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007AC[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007AC[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007AC[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007AC[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007AC[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 1
- // .. ==> 0XF80007AC[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF80007AC[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007AC[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007AC[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000380U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007B0[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007B0[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007B0[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007B0[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007B0[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 1
- // .. ==> 0XF80007B0[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF80007B0[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007B0[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007B0[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000380U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007B4[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007B4[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007B4[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007B4[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007B4[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 1
- // .. ==> 0XF80007B4[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // .. IO_Type = 1
- // .. ==> 0XF80007B4[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007B4[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007B4[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000380U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF80007B8[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. Speed = 0
- // .. ==> 0XF80007B8[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007B8[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007B8[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007B8[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007B8, 0x00003F01U ,0x00000201U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF80007BC[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. Speed = 0
- // .. ==> 0XF80007BC[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007BC[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007BC[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007BC[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007BC, 0x00003F01U ,0x00000201U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007C0[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007C0[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007C0[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007C0[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 7
- // .. ==> 0XF80007C0[7:5] = 0x00000007U
- // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U
- // .. Speed = 0
- // .. ==> 0XF80007C0[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007C0[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007C0[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007C0[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF80007C4[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF80007C4[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007C4[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007C4[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 7
- // .. ==> 0XF80007C4[7:5] = 0x00000007U
- // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U
- // .. Speed = 0
- // .. ==> 0XF80007C4[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007C4[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007C4[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007C4[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF80007C8[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF80007C8[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007C8[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007C8[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF80007C8[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF80007C8[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007C8[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007C8[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007C8[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00000201U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF80007CC[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF80007CC[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007CC[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007CC[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF80007CC[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF80007CC[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007CC[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007CC[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007CC[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00000201U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007D0[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007D0[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007D0[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007D0[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007D0[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF80007D0[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007D0[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007D0[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007D0[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007D4[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007D4[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007D4[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007D4[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF80007D4[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF80007D4[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 1
- // .. ==> 0XF80007D4[11:9] = 0x00000001U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. PULLUP = 0
- // .. ==> 0XF80007D4[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007D4[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U),
- // .. SDIO0_WP_SEL = 46
- // .. ==> 0XF8000830[5:0] = 0x0000002EU
- // .. ==> MASK : 0x0000003FU VAL : 0x0000002EU
- // .. SDIO0_CD_SEL = 47
- // .. ==> 0XF8000830[21:16] = 0x0000002FU
- // .. ==> MASK : 0x003F0000U VAL : 0x002F0000U
- // ..
- EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x002F002EU),
- // .. FINISH: MIO PROGRAMMING
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_peripherals_init_data_1_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
- // .. IBUF_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B48[7:7] = 0x00000001U
- // .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. TERM_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B48[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // ..
- EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
- // .. IBUF_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B4C[7:7] = 0x00000001U
- // .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. TERM_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B4C[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // ..
- EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
- // .. IBUF_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B50[7:7] = 0x00000001U
- // .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. TERM_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B50[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // ..
- EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
- // .. IBUF_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B54[7:7] = 0x00000001U
- // .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. TERM_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B54[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // ..
- EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
- // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // .. START: SRAM/NOR SET OPMODE
- // .. FINISH: SRAM/NOR SET OPMODE
- // .. START: UART REGISTERS
- // .. BDIV = 0x6
- // .. ==> 0XE0001034[7:0] = 0x00000006U
- // .. ==> MASK : 0x000000FFU VAL : 0x00000006U
- // ..
- EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
- // .. CD = 0x3e
- // .. ==> 0XE0001018[15:0] = 0x0000003EU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU
- // ..
- EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
- // .. STPBRK = 0x0
- // .. ==> 0XE0001000[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. STTBRK = 0x0
- // .. ==> 0XE0001000[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. RSTTO = 0x0
- // .. ==> 0XE0001000[6:6] = 0x00000000U
- // .. ==> MASK : 0x00000040U VAL : 0x00000000U
- // .. TXDIS = 0x0
- // .. ==> 0XE0001000[5:5] = 0x00000000U
- // .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. TXEN = 0x1
- // .. ==> 0XE0001000[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. RXDIS = 0x0
- // .. ==> 0XE0001000[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. RXEN = 0x1
- // .. ==> 0XE0001000[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. TXRES = 0x1
- // .. ==> 0XE0001000[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. RXRES = 0x1
- // .. ==> 0XE0001000[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // ..
- EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
- // .. IRMODE = 0x0
- // .. ==> 0XE0001004[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. UCLKEN = 0x0
- // .. ==> 0XE0001004[10:10] = 0x00000000U
- // .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. CHMODE = 0x0
- // .. ==> 0XE0001004[9:8] = 0x00000000U
- // .. ==> MASK : 0x00000300U VAL : 0x00000000U
- // .. NBSTOP = 0x0
- // .. ==> 0XE0001004[7:6] = 0x00000000U
- // .. ==> MASK : 0x000000C0U VAL : 0x00000000U
- // .. PAR = 0x4
- // .. ==> 0XE0001004[5:3] = 0x00000004U
- // .. ==> MASK : 0x00000038U VAL : 0x00000020U
- // .. CHRL = 0x0
- // .. ==> 0XE0001004[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. CLKS = 0x0
- // .. ==> 0XE0001004[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U),
- // .. FINISH: UART REGISTERS
- // .. START: QSPI REGISTERS
- // .. Holdb_dr = 1
- // .. ==> 0XE000D000[19:19] = 0x00000001U
- // .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // ..
- EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
- // .. FINISH: QSPI REGISTERS
- // .. START: PL POWER ON RESET REGISTERS
- // .. PCFG_POR_CNT_4K = 0
- // .. ==> 0XF8007000[29:29] = 0x00000000U
- // .. ==> MASK : 0x20000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
- // .. FINISH: PL POWER ON RESET REGISTERS
- // .. START: SMC TIMING CALCULATION REGISTER UPDATE
- // .. .. START: NAND SET CYCLE
- // .. .. FINISH: NAND SET CYCLE
- // .. .. START: OPMODE
- // .. .. FINISH: OPMODE
- // .. .. START: DIRECT COMMAND
- // .. .. FINISH: DIRECT COMMAND
- // .. .. START: SRAM/NOR CS0 SET CYCLE
- // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
- // .. .. START: DIRECT COMMAND
- // .. .. FINISH: DIRECT COMMAND
- // .. .. START: NOR CS0 BASE ADDRESS
- // .. .. FINISH: NOR CS0 BASE ADDRESS
- // .. .. START: SRAM/NOR CS1 SET CYCLE
- // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
- // .. .. START: DIRECT COMMAND
- // .. .. FINISH: DIRECT COMMAND
- // .. .. START: NOR CS1 BASE ADDRESS
- // .. .. FINISH: NOR CS1 BASE ADDRESS
- // .. .. START: USB RESET
- // .. .. .. START: USB0 RESET
- // .. .. .. .. START: DIR MODE BANK 0
- // .. .. .. .. FINISH: DIR MODE BANK 0
- // .. .. .. .. START: DIR MODE BANK 1
- // .. .. .. .. FINISH: DIR MODE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. START: OUTPUT ENABLE BANK 0
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
- // .. .. .. .. START: OUTPUT ENABLE BANK 1
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. START: ADD 1 MS DELAY
- // .. .. .. ..
- EMIT_MASKDELAY(0XF8F00200, 1),
- // .. .. .. .. FINISH: ADD 1 MS DELAY
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: USB0 RESET
- // .. .. .. START: USB1 RESET
- // .. .. .. .. START: DIR MODE BANK 0
- // .. .. .. .. FINISH: DIR MODE BANK 0
- // .. .. .. .. START: DIR MODE BANK 1
- // .. .. .. .. FINISH: DIR MODE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. START: OUTPUT ENABLE BANK 0
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
- // .. .. .. .. START: OUTPUT ENABLE BANK 1
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. START: ADD 1 MS DELAY
- // .. .. .. ..
- EMIT_MASKDELAY(0XF8F00200, 1),
- // .. .. .. .. FINISH: ADD 1 MS DELAY
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: USB1 RESET
- // .. .. FINISH: USB RESET
- // .. .. START: ENET RESET
- // .. .. .. START: ENET0 RESET
- // .. .. .. .. START: DIR MODE BANK 0
- // .. .. .. .. FINISH: DIR MODE BANK 0
- // .. .. .. .. START: DIR MODE BANK 1
- // .. .. .. .. FINISH: DIR MODE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. START: OUTPUT ENABLE BANK 0
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
- // .. .. .. .. START: OUTPUT ENABLE BANK 1
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. START: ADD 1 MS DELAY
- // .. .. .. ..
- EMIT_MASKDELAY(0XF8F00200, 1),
- // .. .. .. .. FINISH: ADD 1 MS DELAY
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: ENET0 RESET
- // .. .. .. START: ENET1 RESET
- // .. .. .. .. START: DIR MODE BANK 0
- // .. .. .. .. FINISH: DIR MODE BANK 0
- // .. .. .. .. START: DIR MODE BANK 1
- // .. .. .. .. FINISH: DIR MODE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. START: OUTPUT ENABLE BANK 0
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
- // .. .. .. .. START: OUTPUT ENABLE BANK 1
- // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
- // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. START: ADD 1 MS DELAY
- // .. .. .. ..
- EMIT_MASKDELAY(0XF8F00200, 1),
- // .. .. .. .. FINISH: ADD 1 MS DELAY
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: ENET1 RESET
- // .. .. FINISH: ENET RESET
- // .. .. START: I2C RESET
- // .. .. .. START: I2C0 RESET
- // .. .. .. .. START: DIR MODE GPIO BANK0
- // .. .. .. .. FINISH: DIR MODE GPIO BANK0
- // .. .. .. .. START: DIR MODE GPIO BANK1
- // .. .. .. .. FINISH: DIR MODE GPIO BANK1
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. START: OUTPUT ENABLE
- // .. .. .. .. FINISH: OUTPUT ENABLE
- // .. .. .. .. START: OUTPUT ENABLE
- // .. .. .. .. FINISH: OUTPUT ENABLE
- // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. START: ADD 1 MS DELAY
- // .. .. .. ..
- EMIT_MASKDELAY(0XF8F00200, 1),
- // .. .. .. .. FINISH: ADD 1 MS DELAY
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: I2C0 RESET
- // .. .. .. START: I2C1 RESET
- // .. .. .. .. START: DIR MODE GPIO BANK0
- // .. .. .. .. FINISH: DIR MODE GPIO BANK0
- // .. .. .. .. START: DIR MODE GPIO BANK1
- // .. .. .. .. FINISH: DIR MODE GPIO BANK1
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. START: OUTPUT ENABLE
- // .. .. .. .. FINISH: OUTPUT ENABLE
- // .. .. .. .. START: OUTPUT ENABLE
- // .. .. .. .. FINISH: OUTPUT ENABLE
- // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
- // .. .. .. .. START: ADD 1 MS DELAY
- // .. .. .. ..
- EMIT_MASKDELAY(0XF8F00200, 1),
- // .. .. .. .. FINISH: ADD 1 MS DELAY
- // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
- // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
- // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
- // .. .. .. FINISH: I2C1 RESET
- // .. .. FINISH: I2C RESET
- // .. .. START: NOR CHIP SELECT
- // .. .. .. START: DIR MODE BANK 0
- // .. .. .. FINISH: DIR MODE BANK 0
- // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. START: OUTPUT ENABLE BANK 0
- // .. .. .. FINISH: OUTPUT ENABLE BANK 0
- // .. .. FINISH: NOR CHIP SELECT
- // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_post_config_1_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: ENABLING LEVEL SHIFTER
- // .. USER_INP_ICT_EN_0 = 3
- // .. ==> 0XF8000900[1:0] = 0x00000003U
- // .. ==> MASK : 0x00000003U VAL : 0x00000003U
- // .. USER_INP_ICT_EN_1 = 3
- // .. ==> 0XF8000900[3:2] = 0x00000003U
- // .. ==> MASK : 0x0000000CU VAL : 0x0000000CU
- // ..
- EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
- // .. FINISH: ENABLING LEVEL SHIFTER
- // .. START: FPGA RESETS TO 0
- // .. reserved_3 = 0
- // .. ==> 0XF8000240[31:25] = 0x00000000U
- // .. ==> MASK : 0xFE000000U VAL : 0x00000000U
- // .. FPGA_ACP_RST = 0
- // .. ==> 0XF8000240[24:24] = 0x00000000U
- // .. ==> MASK : 0x01000000U VAL : 0x00000000U
- // .. FPGA_AXDS3_RST = 0
- // .. ==> 0XF8000240[23:23] = 0x00000000U
- // .. ==> MASK : 0x00800000U VAL : 0x00000000U
- // .. FPGA_AXDS2_RST = 0
- // .. ==> 0XF8000240[22:22] = 0x00000000U
- // .. ==> MASK : 0x00400000U VAL : 0x00000000U
- // .. FPGA_AXDS1_RST = 0
- // .. ==> 0XF8000240[21:21] = 0x00000000U
- // .. ==> MASK : 0x00200000U VAL : 0x00000000U
- // .. FPGA_AXDS0_RST = 0
- // .. ==> 0XF8000240[20:20] = 0x00000000U
- // .. ==> MASK : 0x00100000U VAL : 0x00000000U
- // .. reserved_2 = 0
- // .. ==> 0XF8000240[19:18] = 0x00000000U
- // .. ==> MASK : 0x000C0000U VAL : 0x00000000U
- // .. FSSW1_FPGA_RST = 0
- // .. ==> 0XF8000240[17:17] = 0x00000000U
- // .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. FSSW0_FPGA_RST = 0
- // .. ==> 0XF8000240[16:16] = 0x00000000U
- // .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. reserved_1 = 0
- // .. ==> 0XF8000240[15:14] = 0x00000000U
- // .. ==> MASK : 0x0000C000U VAL : 0x00000000U
- // .. FPGA_FMSW1_RST = 0
- // .. ==> 0XF8000240[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // .. FPGA_FMSW0_RST = 0
- // .. ==> 0XF8000240[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. FPGA_DMA3_RST = 0
- // .. ==> 0XF8000240[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. FPGA_DMA2_RST = 0
- // .. ==> 0XF8000240[10:10] = 0x00000000U
- // .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. FPGA_DMA1_RST = 0
- // .. ==> 0XF8000240[9:9] = 0x00000000U
- // .. ==> MASK : 0x00000200U VAL : 0x00000000U
- // .. FPGA_DMA0_RST = 0
- // .. ==> 0XF8000240[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. reserved = 0
- // .. ==> 0XF8000240[7:4] = 0x00000000U
- // .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. FPGA3_OUT_RST = 0
- // .. ==> 0XF8000240[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. FPGA2_OUT_RST = 0
- // .. ==> 0XF8000240[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. FPGA1_OUT_RST = 0
- // .. ==> 0XF8000240[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. FPGA0_OUT_RST = 0
- // .. ==> 0XF8000240[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
- // .. FINISH: FPGA RESETS TO 0
- // .. START: AFI REGISTERS
- // .. .. START: AFI0 REGISTERS
- // .. .. FINISH: AFI0 REGISTERS
- // .. .. START: AFI1 REGISTERS
- // .. .. FINISH: AFI1 REGISTERS
- // .. .. START: AFI2 REGISTERS
- // .. .. FINISH: AFI2 REGISTERS
- // .. .. START: AFI3 REGISTERS
- // .. .. FINISH: AFI3 REGISTERS
- // .. FINISH: AFI REGISTERS
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_debug_1_0[] = {
- // START: top
- // .. START: CROSS TRIGGER CONFIGURATIONS
- // .. .. START: UNLOCKING CTI REGISTERS
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. FINISH: UNLOCKING CTI REGISTERS
- // .. .. START: ENABLING CTI MODULES AND CHANNELS
- // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
- // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. FINISH: CROSS TRIGGER CONFIGURATIONS
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-
-#include "xil_io.h"
-#define PS7_MASK_POLL_TIME 100000000
-
-char*
-getPS7MessageInfo(unsigned key) {
-
- char* err_msg = "";
- switch (key) {
- case PS7_INIT_SUCCESS: err_msg = "PS7 initialization successful"; break;
- case PS7_INIT_CORRUPT: err_msg = "PS7 init Data Corrupted"; break;
- case PS7_INIT_TIMEOUT: err_msg = "PS7 init mask poll timeout"; break;
- case PS7_POLL_FAILED_DDR_INIT: err_msg = "Mask Poll failed for DDR Init"; break;
- case PS7_POLL_FAILED_DMA: err_msg = "Mask Poll failed for PLL Init"; break;
- case PS7_POLL_FAILED_PLL: err_msg = "Mask Poll failed for DMA done bit"; break;
- default: err_msg = "Undefined error status"; break;
- }
-
- return err_msg;
-}
-
-unsigned long
-ps7GetSiliconVersion () {
- // Read PS version from MCTRL register [31:28]
- unsigned long mask = 0xF0000000;
- unsigned long *addr = (unsigned long*) 0XF8007080;
- unsigned long ps_version = (*addr & mask) >> 28;
- return ps_version;
-}
-
-void mask_write (unsigned long add , unsigned long mask, unsigned long val ) {
- unsigned long *addr = (unsigned long*) add;
- *addr = ( val & mask ) | ( *addr & ~mask);
- //xil_printf("MaskWrite : 0x%x--> 0x%x \n \r" ,add, *addr);
-}
-
-
-int mask_poll(unsigned long add , unsigned long mask ) {
- volatile unsigned long *addr = (volatile unsigned long*) add;
- int i = 0;
- while (!(*addr & mask)) {
- if (i == PS7_MASK_POLL_TIME) {
- return -1;
- }
- i++;
- }
- return 1;
- //xil_printf("MaskPoll : 0x%x --> 0x%x \n \r" , add, *addr);
-}
-
-unsigned long mask_read(unsigned long add , unsigned long mask ) {
- unsigned long *addr = (unsigned long*) add;
- unsigned long val = (*addr & mask);
- //xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val);
- return val;
-}
-
-
-
-int
-ps7_config(unsigned long * ps7_config_init)
-{
- unsigned long *ptr = ps7_config_init;
-
- unsigned long opcode; // current instruction ..
- unsigned long args[16]; // no opcode has so many args ...
- int numargs; // number of arguments of this instruction
- int j; // general purpose index
-
- volatile unsigned long *addr; // some variable to make code readable
- unsigned long val,mask; // some variable to make code readable
-
- int finish = -1 ; // loop while this is negative !
- int i = 0; // Timeout variable
-
- while( finish < 0 ) {
- numargs = ptr[0] & 0xF;
- opcode = ptr[0] >> 4;
-
- for( j = 0 ; j < numargs ; j ++ )
- args[j] = ptr[j+1];
- ptr += numargs + 1;
-
-
- switch ( opcode ) {
-
- case OPCODE_EXIT:
- finish = PS7_INIT_SUCCESS;
- break;
-
- case OPCODE_CLEAR:
- addr = (unsigned long*) args[0];
- *addr = 0;
- break;
-
- case OPCODE_WRITE:
- addr = (unsigned long*) args[0];
- val = args[1];
- *addr = val;
- break;
-
- case OPCODE_MASKWRITE:
- addr = (unsigned long*) args[0];
- mask = args[1];
- val = args[2];
- *addr = ( val & mask ) | ( *addr & ~mask);
- break;
-
- case OPCODE_MASKPOLL:
- addr = (unsigned long*) args[0];
- mask = args[1];
- i = 0;
- while (!(*addr & mask)) {
- if (i == PS7_MASK_POLL_TIME) {
- finish = PS7_INIT_TIMEOUT;
- break;
- }
- i++;
- }
- break;
- case OPCODE_MASKDELAY:
- addr = (unsigned long*) args[0];
- mask = args[1];
- int delay = get_number_of_cycles_for_delay(mask);
- perf_reset_and_start_timer();
- while ((*addr < delay)) {
- }
- break;
- default:
- finish = PS7_INIT_CORRUPT;
- break;
- }
- }
- return finish;
-}
-
-unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0;
-unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0;
-unsigned long *ps7_clock_init_data = ps7_clock_init_data_3_0;
-unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0;
-unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
-
-int
-ps7_post_config()
-{
- // Get the PS_VERSION on run time
- unsigned long si_ver = ps7GetSiliconVersion ();
- int ret = -1;
- if (si_ver == PCW_SILICON_VERSION_1) {
- ret = ps7_config (ps7_post_config_1_0);
- if (ret != PS7_INIT_SUCCESS) return ret;
- } else if (si_ver == PCW_SILICON_VERSION_2) {
- ret = ps7_config (ps7_post_config_2_0);
- if (ret != PS7_INIT_SUCCESS) return ret;
- } else {
- ret = ps7_config (ps7_post_config_3_0);
- if (ret != PS7_INIT_SUCCESS) return ret;
- }
- return PS7_INIT_SUCCESS;
-}
-
-int
-ps7_debug()
-{
- // Get the PS_VERSION on run time
- unsigned long si_ver = ps7GetSiliconVersion ();
- int ret = -1;
- if (si_ver == PCW_SILICON_VERSION_1) {
- ret = ps7_config (ps7_debug_1_0);
- if (ret != PS7_INIT_SUCCESS) return ret;
- } else if (si_ver == PCW_SILICON_VERSION_2) {
- ret = ps7_config (ps7_debug_2_0);
- if (ret != PS7_INIT_SUCCESS) return ret;
- } else {
- ret = ps7_config (ps7_debug_3_0);
- if (ret != PS7_INIT_SUCCESS) return ret;
- }
- return PS7_INIT_SUCCESS;
-}
-
-int
-ps7_init()
-{
- // Get the PS_VERSION on run time
- unsigned long si_ver = ps7GetSiliconVersion ();
- int ret;
- //int pcw_ver = 0;
-
- if (si_ver == PCW_SILICON_VERSION_1) {
- ps7_mio_init_data = ps7_mio_init_data_1_0;
- ps7_pll_init_data = ps7_pll_init_data_1_0;
- ps7_clock_init_data = ps7_clock_init_data_1_0;
- ps7_ddr_init_data = ps7_ddr_init_data_1_0;
- ps7_peripherals_init_data = ps7_peripherals_init_data_1_0;
- //pcw_ver = 1;
-
- } else if (si_ver == PCW_SILICON_VERSION_2) {
- ps7_mio_init_data = ps7_mio_init_data_2_0;
- ps7_pll_init_data = ps7_pll_init_data_2_0;
- ps7_clock_init_data = ps7_clock_init_data_2_0;
- ps7_ddr_init_data = ps7_ddr_init_data_2_0;
- ps7_peripherals_init_data = ps7_peripherals_init_data_2_0;
- //pcw_ver = 2;
-
- } else {
- ps7_mio_init_data = ps7_mio_init_data_3_0;
- ps7_pll_init_data = ps7_pll_init_data_3_0;
- ps7_clock_init_data = ps7_clock_init_data_3_0;
- ps7_ddr_init_data = ps7_ddr_init_data_3_0;
- ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
- //pcw_ver = 3;
- }
-
- // MIO init
- ret = ps7_config (ps7_mio_init_data);
- if (ret != PS7_INIT_SUCCESS) return ret;
-
- // PLL init
- ret = ps7_config (ps7_pll_init_data);
- if (ret != PS7_INIT_SUCCESS) return ret;
-
- // Clock init
- ret = ps7_config (ps7_clock_init_data);
- if (ret != PS7_INIT_SUCCESS) return ret;
-
- // DDR init
- ret = ps7_config (ps7_ddr_init_data);
- if (ret != PS7_INIT_SUCCESS) return ret;
-
-
-
- // Peripherals init
- ret = ps7_config (ps7_peripherals_init_data);
- if (ret != PS7_INIT_SUCCESS) return ret;
- //xil_printf ("\n PCW Silicon Version : %d.0", pcw_ver);
- return PS7_INIT_SUCCESS;
-}
-
-
-
-
-/* For delay calculation using global timer */
-
-/* start timer */
- void perf_start_clock(void)
-{
- *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) | // Timer Enable
- (1 << 3) | // Auto-increment
- (0 << 8) // Pre-scale
- );
-}
-
-/* stop timer and reset timer count regs */
- void perf_reset_clock(void)
-{
- perf_disable_clock();
- *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_L32 = 0;
- *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_U32 = 0;
-}
-
-/* Compute mask for given delay in miliseconds*/
-int get_number_of_cycles_for_delay(unsigned int delay)
-{
- // GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x)
- return (APU_FREQ*delay/(2*1000));
-
-}
-
-/* stop timer */
- void perf_disable_clock(void)
-{
- *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = 0;
-}
-
-void perf_reset_and_start_timer()
-{
- perf_reset_clock();
- perf_start_clock();
-}
+++ /dev/null
-
-/******************************************************************************
-*
-* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
-*
-* SPDX-License-Identifier: GPL-2.0+
-*
-*
-*******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file ps7_init.h
-*
-* This file can be included in FSBL code
-* to get prototype of ps7_init() function
-* and error codes
-*
-*****************************************************************************/
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-//typedef unsigned int u32;
-
-
-/** do we need to make this name more unique ? **/
-//extern u32 ps7_init_data[];
-extern unsigned long * ps7_ddr_init_data;
-extern unsigned long * ps7_mio_init_data;
-extern unsigned long * ps7_pll_init_data;
-extern unsigned long * ps7_clock_init_data;
-extern unsigned long * ps7_peripherals_init_data;
-
-
-
-#define OPCODE_EXIT 0U
-#define OPCODE_CLEAR 1U
-#define OPCODE_WRITE 2U
-#define OPCODE_MASKWRITE 3U
-#define OPCODE_MASKPOLL 4U
-#define OPCODE_MASKDELAY 5U
-#define NEW_PS7_ERR_CODE 1
-
-/* Encode number of arguments in last nibble */
-#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 )
-#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr
-#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val
-#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
-#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask
-#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
-
-/* Returns codes of PS7_Init */
-#define PS7_INIT_SUCCESS (0) // 0 is success in good old C
-#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now
-#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out
-#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init
-#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit
-#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init
-
-
-/* Silicon Versions */
-#define PCW_SILICON_VERSION_1 0
-#define PCW_SILICON_VERSION_2 1
-#define PCW_SILICON_VERSION_3 2
-
-/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
-#define PS7_POST_CONFIG
-
-/* Freq of all peripherals */
-
-#define APU_FREQ 666666687
-#define DDR_FREQ 533333374
-#define DCI_FREQ 10158731
-#define QSPI_FREQ 200000000
-#define SMC_FREQ 10000000
-#define ENET0_FREQ 125000000
-#define ENET1_FREQ 10000000
-#define USB0_FREQ 60000000
-#define USB1_FREQ 60000000
-#define SDIO_FREQ 50000000
-#define UART_FREQ 50000000
-#define SPI_FREQ 10000000
-#define I2C_FREQ 111111115
-#define WDT_FREQ 111111115
-#define TTC_FREQ 50000000
-#define CAN_FREQ 10000000
-#define PCAP_FREQ 200000000
-#define TPIU_FREQ 200000000
-#define FPGA0_FREQ 100000000
-#define FPGA1_FREQ 142857132
-#define FPGA2_FREQ 50000000
-#define FPGA3_FREQ 50000000
-
-
-/* For delay calculation using global registers*/
-#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
-#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204
-#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208
-#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218
-
-int ps7_config( unsigned long*);
-int ps7_init();
-int ps7_post_config();
-int ps7_debug();
-char* getPS7MessageInfo(unsigned key);
-
-void perf_start_clock(void);
-void perf_disable_clock(void);
-void perf_reset_clock(void);
-void perf_reset_and_start_timer();
-int get_number_of_cycles_for_delay(unsigned int delay);
-#ifdef __cplusplus
-}
-#endif
+++ /dev/null
-/*
- * Copyright (c) Xilinx, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include "ps7_init_gpl.h"
-
-unsigned long ps7_pll_init_data_3_0[] = {
- /* START: top */
- /* .. START: SLCR SETTINGS */
- /* .. UNLOCK_KEY = 0XDF0D */
- /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
- /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */
- /* .. */
- EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
- /* .. FINISH: SLCR SETTINGS */
- /* .. START: PLL SLCR REGISTERS */
- /* .. .. START: ARM PLL INIT */
- /* .. .. PLL_RES = 0xc */
- /* .. .. ==> 0XF8000110[7:4] = 0x0000000CU */
- /* .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U */
- /* .. .. PLL_CP = 0x2 */
- /* .. .. ==> 0XF8000110[11:8] = 0x00000002U */
- /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */
- /* .. .. LOCK_CNT = 0x177 */
- /* .. .. ==> 0XF8000110[21:12] = 0x00000177U */
- /* .. .. ==> MASK : 0x003FF000U VAL : 0x00177000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x001772C0U),
- /* .. .. .. START: UPDATE FB_DIV */
- /* .. .. .. PLL_FDIV = 0x1a */
- /* .. .. .. ==> 0XF8000100[18:12] = 0x0000001AU */
- /* .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001A000U */
- /* .. .. .. */
- EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x0001A000U),
- /* .. .. .. FINISH: UPDATE FB_DIV */
- /* .. .. .. START: BY PASS PLL */
- /* .. .. .. PLL_BYPASS_FORCE = 1 */
- /* .. .. .. ==> 0XF8000100[4:4] = 0x00000001U */
- /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U */
- /* .. .. .. */
- EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U),
- /* .. .. .. FINISH: BY PASS PLL */
- /* .. .. .. START: ASSERT RESET */
- /* .. .. .. PLL_RESET = 1 */
- /* .. .. .. ==> 0XF8000100[0:0] = 0x00000001U */
- /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
- /* .. .. .. */
- EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U),
- /* .. .. .. FINISH: ASSERT RESET */
- /* .. .. .. START: DEASSERT RESET */
- /* .. .. .. PLL_RESET = 0 */
- /* .. .. .. ==> 0XF8000100[0:0] = 0x00000000U */
- /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. .. .. */
- EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U),
- /* .. .. .. FINISH: DEASSERT RESET */
- /* .. .. .. START: CHECK PLL STATUS */
- /* .. .. .. ARM_PLL_LOCK = 1 */
- /* .. .. .. ==> 0XF800010C[0:0] = 0x00000001U */
- /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
- /* .. .. .. */
- EMIT_MASKPOLL(0XF800010C, 0x00000001U),
- /* .. .. .. FINISH: CHECK PLL STATUS */
- /* .. .. .. START: REMOVE PLL BY PASS */
- /* .. .. .. PLL_BYPASS_FORCE = 0 */
- /* .. .. .. ==> 0XF8000100[4:4] = 0x00000000U */
- /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
- /* .. .. .. */
- EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U),
- /* .. .. .. FINISH: REMOVE PLL BY PASS */
- /* .. .. .. SRCSEL = 0x0 */
- /* .. .. .. ==> 0XF8000120[5:4] = 0x00000000U */
- /* .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
- /* .. .. .. DIVISOR = 0x2 */
- /* .. .. .. ==> 0XF8000120[13:8] = 0x00000002U */
- /* .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U */
- /* .. .. .. CPU_6OR4XCLKACT = 0x1 */
- /* .. .. .. ==> 0XF8000120[24:24] = 0x00000001U */
- /* .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U */
- /* .. .. .. CPU_3OR2XCLKACT = 0x1 */
- /* .. .. .. ==> 0XF8000120[25:25] = 0x00000001U */
- /* .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U */
- /* .. .. .. CPU_2XCLKACT = 0x1 */
- /* .. .. .. ==> 0XF8000120[26:26] = 0x00000001U */
- /* .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U */
- /* .. .. .. CPU_1XCLKACT = 0x1 */
- /* .. .. .. ==> 0XF8000120[27:27] = 0x00000001U */
- /* .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U */
- /* .. .. .. CPU_PERI_CLKACT = 0x1 */
- /* .. .. .. ==> 0XF8000120[28:28] = 0x00000001U */
- /* .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U */
- /* .. .. .. */
- EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000200U),
- /* .. .. FINISH: ARM PLL INIT */
- /* .. .. START: DDR PLL INIT */
- /* .. .. PLL_RES = 0xc */
- /* .. .. ==> 0XF8000114[7:4] = 0x0000000CU */
- /* .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U */
- /* .. .. PLL_CP = 0x2 */
- /* .. .. ==> 0XF8000114[11:8] = 0x00000002U */
- /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */
- /* .. .. LOCK_CNT = 0x1db */
- /* .. .. ==> 0XF8000114[21:12] = 0x000001DBU */
- /* .. .. ==> MASK : 0x003FF000U VAL : 0x001DB000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x001DB2C0U),
- /* .. .. .. START: UPDATE FB_DIV */
- /* .. .. .. PLL_FDIV = 0x15 */
- /* .. .. .. ==> 0XF8000104[18:12] = 0x00000015U */
- /* .. .. .. ==> MASK : 0x0007F000U VAL : 0x00015000U */
- /* .. .. .. */
- EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x00015000U),
- /* .. .. .. FINISH: UPDATE FB_DIV */
- /* .. .. .. START: BY PASS PLL */
- /* .. .. .. PLL_BYPASS_FORCE = 1 */
- /* .. .. .. ==> 0XF8000104[4:4] = 0x00000001U */
- /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U */
- /* .. .. .. */
- EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000010U),
- /* .. .. .. FINISH: BY PASS PLL */
- /* .. .. .. START: ASSERT RESET */
- /* .. .. .. PLL_RESET = 1 */
- /* .. .. .. ==> 0XF8000104[0:0] = 0x00000001U */
- /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
- /* .. .. .. */
- EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000001U),
- /* .. .. .. FINISH: ASSERT RESET */
- /* .. .. .. START: DEASSERT RESET */
- /* .. .. .. PLL_RESET = 0 */
- /* .. .. .. ==> 0XF8000104[0:0] = 0x00000000U */
- /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. .. .. */
- EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000000U),
- /* .. .. .. FINISH: DEASSERT RESET */
- /* .. .. .. START: CHECK PLL STATUS */
- /* .. .. .. DDR_PLL_LOCK = 1 */
- /* .. .. .. ==> 0XF800010C[1:1] = 0x00000001U */
- /* .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */
- /* .. .. .. */
- EMIT_MASKPOLL(0XF800010C, 0x00000002U),
- /* .. .. .. FINISH: CHECK PLL STATUS */
- /* .. .. .. START: REMOVE PLL BY PASS */
- /* .. .. .. PLL_BYPASS_FORCE = 0 */
- /* .. .. .. ==> 0XF8000104[4:4] = 0x00000000U */
- /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
- /* .. .. .. */
- EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U),
- /* .. .. .. FINISH: REMOVE PLL BY PASS */
- /* .. .. .. DDR_3XCLKACT = 0x1 */
- /* .. .. .. ==> 0XF8000124[0:0] = 0x00000001U */
- /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
- /* .. .. .. DDR_2XCLKACT = 0x1 */
- /* .. .. .. ==> 0XF8000124[1:1] = 0x00000001U */
- /* .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */
- /* .. .. .. DDR_3XCLK_DIVISOR = 0x2 */
- /* .. .. .. ==> 0XF8000124[25:20] = 0x00000002U */
- /* .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U */
- /* .. .. .. DDR_2XCLK_DIVISOR = 0x3 */
- /* .. .. .. ==> 0XF8000124[31:26] = 0x00000003U */
- /* .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U */
- /* .. .. .. */
- EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U),
- /* .. .. FINISH: DDR PLL INIT */
- /* .. .. START: IO PLL INIT */
- /* .. .. PLL_RES = 0xc */
- /* .. .. ==> 0XF8000118[7:4] = 0x0000000CU */
- /* .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U */
- /* .. .. PLL_CP = 0x2 */
- /* .. .. ==> 0XF8000118[11:8] = 0x00000002U */
- /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */
- /* .. .. LOCK_CNT = 0x1f4 */
- /* .. .. ==> 0XF8000118[21:12] = 0x000001F4U */
- /* .. .. ==> MASK : 0x003FF000U VAL : 0x001F4000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x001F42C0U),
- /* .. .. .. START: UPDATE FB_DIV */
- /* .. .. .. PLL_FDIV = 0x14 */
- /* .. .. .. ==> 0XF8000108[18:12] = 0x00000014U */
- /* .. .. .. ==> MASK : 0x0007F000U VAL : 0x00014000U */
- /* .. .. .. */
- EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x00014000U),
- /* .. .. .. FINISH: UPDATE FB_DIV */
- /* .. .. .. START: BY PASS PLL */
- /* .. .. .. PLL_BYPASS_FORCE = 1 */
- /* .. .. .. ==> 0XF8000108[4:4] = 0x00000001U */
- /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U */
- /* .. .. .. */
- EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U),
- /* .. .. .. FINISH: BY PASS PLL */
- /* .. .. .. START: ASSERT RESET */
- /* .. .. .. PLL_RESET = 1 */
- /* .. .. .. ==> 0XF8000108[0:0] = 0x00000001U */
- /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
- /* .. .. .. */
- EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U),
- /* .. .. .. FINISH: ASSERT RESET */
- /* .. .. .. START: DEASSERT RESET */
- /* .. .. .. PLL_RESET = 0 */
- /* .. .. .. ==> 0XF8000108[0:0] = 0x00000000U */
- /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. .. .. */
- EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U),
- /* .. .. .. FINISH: DEASSERT RESET */
- /* .. .. .. START: CHECK PLL STATUS */
- /* .. .. .. IO_PLL_LOCK = 1 */
- /* .. .. .. ==> 0XF800010C[2:2] = 0x00000001U */
- /* .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U */
- /* .. .. .. */
- EMIT_MASKPOLL(0XF800010C, 0x00000004U),
- /* .. .. .. FINISH: CHECK PLL STATUS */
- /* .. .. .. START: REMOVE PLL BY PASS */
- /* .. .. .. PLL_BYPASS_FORCE = 0 */
- /* .. .. .. ==> 0XF8000108[4:4] = 0x00000000U */
- /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
- /* .. .. .. */
- EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000000U),
- /* .. .. .. FINISH: REMOVE PLL BY PASS */
- /* .. .. FINISH: IO PLL INIT */
- /* .. FINISH: PLL SLCR REGISTERS */
- /* .. START: LOCK IT BACK */
- /* .. LOCK_KEY = 0X767B */
- /* .. ==> 0XF8000004[15:0] = 0x0000767BU */
- /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */
- /* .. */
- EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
- /* .. FINISH: LOCK IT BACK */
- /* FINISH: top */
- /* */
- EMIT_EXIT(),
-
- /* */
-};
-
-unsigned long ps7_clock_init_data_3_0[] = {
- /* START: top */
- /* .. START: SLCR SETTINGS */
- /* .. UNLOCK_KEY = 0XDF0D */
- /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
- /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */
- /* .. */
- EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
- /* .. FINISH: SLCR SETTINGS */
- /* .. START: CLOCK CONTROL SLCR REGISTERS */
- /* .. CLKACT = 0x1 */
- /* .. ==> 0XF8000128[0:0] = 0x00000001U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
- /* .. DIVISOR0 = 0x34 */
- /* .. ==> 0XF8000128[13:8] = 0x00000034U */
- /* .. ==> MASK : 0x00003F00U VAL : 0x00003400U */
- /* .. DIVISOR1 = 0x2 */
- /* .. ==> 0XF8000128[25:20] = 0x00000002U */
- /* .. ==> MASK : 0x03F00000U VAL : 0x00200000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00203401U),
- /* .. CLKACT = 0x1 */
- /* .. ==> 0XF8000138[0:0] = 0x00000001U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
- /* .. SRCSEL = 0x0 */
- /* .. ==> 0XF8000138[4:4] = 0x00000000U */
- /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000001U),
- /* .. CLKACT = 0x1 */
- /* .. ==> 0XF8000140[0:0] = 0x00000001U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
- /* .. SRCSEL = 0x0 */
- /* .. ==> 0XF8000140[6:4] = 0x00000000U */
- /* .. ==> MASK : 0x00000070U VAL : 0x00000000U */
- /* .. DIVISOR = 0x8 */
- /* .. ==> 0XF8000140[13:8] = 0x00000008U */
- /* .. ==> MASK : 0x00003F00U VAL : 0x00000800U */
- /* .. DIVISOR1 = 0x1 */
- /* .. ==> 0XF8000140[25:20] = 0x00000001U */
- /* .. ==> MASK : 0x03F00000U VAL : 0x00100000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00100801U),
- /* .. CLKACT = 0x1 */
- /* .. ==> 0XF800014C[0:0] = 0x00000001U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
- /* .. SRCSEL = 0x0 */
- /* .. ==> 0XF800014C[5:4] = 0x00000000U */
- /* .. ==> MASK : 0x00000030U VAL : 0x00000000U */
- /* .. DIVISOR = 0x5 */
- /* .. ==> 0XF800014C[13:8] = 0x00000005U */
- /* .. ==> MASK : 0x00003F00U VAL : 0x00000500U */
- /* .. */
- EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000501U),
- /* .. CLKACT0 = 0x1 */
- /* .. ==> 0XF8000150[0:0] = 0x00000001U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
- /* .. CLKACT1 = 0x0 */
- /* .. ==> 0XF8000150[1:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. SRCSEL = 0x0 */
- /* .. ==> 0XF8000150[5:4] = 0x00000000U */
- /* .. ==> MASK : 0x00000030U VAL : 0x00000000U */
- /* .. DIVISOR = 0x14 */
- /* .. ==> 0XF8000150[13:8] = 0x00000014U */
- /* .. ==> MASK : 0x00003F00U VAL : 0x00001400U */
- /* .. */
- EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00001401U),
- /* .. CLKACT0 = 0x0 */
- /* .. ==> 0XF8000154[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. CLKACT1 = 0x1 */
- /* .. ==> 0XF8000154[1:1] = 0x00000001U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
- /* .. SRCSEL = 0x0 */
- /* .. ==> 0XF8000154[5:4] = 0x00000000U */
- /* .. ==> MASK : 0x00000030U VAL : 0x00000000U */
- /* .. DIVISOR = 0xa */
- /* .. ==> 0XF8000154[13:8] = 0x0000000AU */
- /* .. ==> MASK : 0x00003F00U VAL : 0x00000A00U */
- /* .. */
- EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00000A02U),
- /* .. .. START: TRACE CLOCK */
- /* .. .. FINISH: TRACE CLOCK */
- /* .. .. CLKACT = 0x1 */
- /* .. .. ==> 0XF8000168[0:0] = 0x00000001U */
- /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
- /* .. .. SRCSEL = 0x0 */
- /* .. .. ==> 0XF8000168[5:4] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
- /* .. .. DIVISOR = 0x5 */
- /* .. .. ==> 0XF8000168[13:8] = 0x00000005U */
- /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000501U),
- /* .. .. SRCSEL = 0x0 */
- /* .. .. ==> 0XF8000170[5:4] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
- /* .. .. DIVISOR0 = 0xa */
- /* .. .. ==> 0XF8000170[13:8] = 0x0000000AU */
- /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U */
- /* .. .. DIVISOR1 = 0x1 */
- /* .. .. ==> 0XF8000170[25:20] = 0x00000001U */
- /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00100A00U),
- /* .. .. SRCSEL = 0x0 */
- /* .. .. ==> 0XF8000180[5:4] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
- /* .. .. DIVISOR0 = 0x7 */
- /* .. .. ==> 0XF8000180[13:8] = 0x00000007U */
- /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000700U */
- /* .. .. DIVISOR1 = 0x1 */
- /* .. .. ==> 0XF8000180[25:20] = 0x00000001U */
- /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00100700U),
- /* .. .. SRCSEL = 0x0 */
- /* .. .. ==> 0XF8000190[5:4] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
- /* .. .. DIVISOR0 = 0x5 */
- /* .. .. ==> 0XF8000190[13:8] = 0x00000005U */
- /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U */
- /* .. .. DIVISOR1 = 0x1 */
- /* .. .. ==> 0XF8000190[25:20] = 0x00000001U */
- /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00100500U),
- /* .. .. SRCSEL = 0x0 */
- /* .. .. ==> 0XF80001A0[5:4] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
- /* .. .. DIVISOR0 = 0x14 */
- /* .. .. ==> 0XF80001A0[13:8] = 0x00000014U */
- /* .. .. ==> MASK : 0x00003F00U VAL : 0x00001400U */
- /* .. .. DIVISOR1 = 0x1 */
- /* .. .. ==> 0XF80001A0[25:20] = 0x00000001U */
- /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00101400U),
- /* .. .. CLK_621_TRUE = 0x1 */
- /* .. .. ==> 0XF80001C4[0:0] = 0x00000001U */
- /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
- /* .. .. */
- EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U),
- /* .. .. DMA_CPU_2XCLKACT = 0x1 */
- /* .. .. ==> 0XF800012C[0:0] = 0x00000001U */
- /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
- /* .. .. USB0_CPU_1XCLKACT = 0x1 */
- /* .. .. ==> 0XF800012C[2:2] = 0x00000001U */
- /* .. .. ==> MASK : 0x00000004U VAL : 0x00000004U */
- /* .. .. USB1_CPU_1XCLKACT = 0x1 */
- /* .. .. ==> 0XF800012C[3:3] = 0x00000001U */
- /* .. .. ==> MASK : 0x00000008U VAL : 0x00000008U */
- /* .. .. GEM0_CPU_1XCLKACT = 0x1 */
- /* .. .. ==> 0XF800012C[6:6] = 0x00000001U */
- /* .. .. ==> MASK : 0x00000040U VAL : 0x00000040U */
- /* .. .. GEM1_CPU_1XCLKACT = 0x0 */
- /* .. .. ==> 0XF800012C[7:7] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000080U VAL : 0x00000000U */
- /* .. .. SDI0_CPU_1XCLKACT = 0x1 */
- /* .. .. ==> 0XF800012C[10:10] = 0x00000001U */
- /* .. .. ==> MASK : 0x00000400U VAL : 0x00000400U */
- /* .. .. SDI1_CPU_1XCLKACT = 0x0 */
- /* .. .. ==> 0XF800012C[11:11] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */
- /* .. .. SPI0_CPU_1XCLKACT = 0x0 */
- /* .. .. ==> 0XF800012C[14:14] = 0x00000000U */
- /* .. .. ==> MASK : 0x00004000U VAL : 0x00000000U */
- /* .. .. SPI1_CPU_1XCLKACT = 0x0 */
- /* .. .. ==> 0XF800012C[15:15] = 0x00000000U */
- /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */
- /* .. .. CAN0_CPU_1XCLKACT = 0x0 */
- /* .. .. ==> 0XF800012C[16:16] = 0x00000000U */
- /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
- /* .. .. CAN1_CPU_1XCLKACT = 0x0 */
- /* .. .. ==> 0XF800012C[17:17] = 0x00000000U */
- /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
- /* .. .. I2C0_CPU_1XCLKACT = 0x1 */
- /* .. .. ==> 0XF800012C[18:18] = 0x00000001U */
- /* .. .. ==> MASK : 0x00040000U VAL : 0x00040000U */
- /* .. .. I2C1_CPU_1XCLKACT = 0x1 */
- /* .. .. ==> 0XF800012C[19:19] = 0x00000001U */
- /* .. .. ==> MASK : 0x00080000U VAL : 0x00080000U */
- /* .. .. UART0_CPU_1XCLKACT = 0x0 */
- /* .. .. ==> 0XF800012C[20:20] = 0x00000000U */
- /* .. .. ==> MASK : 0x00100000U VAL : 0x00000000U */
- /* .. .. UART1_CPU_1XCLKACT = 0x1 */
- /* .. .. ==> 0XF800012C[21:21] = 0x00000001U */
- /* .. .. ==> MASK : 0x00200000U VAL : 0x00200000U */
- /* .. .. GPIO_CPU_1XCLKACT = 0x1 */
- /* .. .. ==> 0XF800012C[22:22] = 0x00000001U */
- /* .. .. ==> MASK : 0x00400000U VAL : 0x00400000U */
- /* .. .. LQSPI_CPU_1XCLKACT = 0x1 */
- /* .. .. ==> 0XF800012C[23:23] = 0x00000001U */
- /* .. .. ==> MASK : 0x00800000U VAL : 0x00800000U */
- /* .. .. SMC_CPU_1XCLKACT = 0x1 */
- /* .. .. ==> 0XF800012C[24:24] = 0x00000001U */
- /* .. .. ==> MASK : 0x01000000U VAL : 0x01000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01EC044DU),
- /* .. FINISH: CLOCK CONTROL SLCR REGISTERS */
- /* .. START: THIS SHOULD BE BLANK */
- /* .. FINISH: THIS SHOULD BE BLANK */
- /* .. START: LOCK IT BACK */
- /* .. LOCK_KEY = 0X767B */
- /* .. ==> 0XF8000004[15:0] = 0x0000767BU */
- /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */
- /* .. */
- EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
- /* .. FINISH: LOCK IT BACK */
- /* FINISH: top */
- /* */
- EMIT_EXIT(),
-
- /* */
-};
-
-unsigned long ps7_ddr_init_data_3_0[] = {
- /* START: top */
- /* .. START: DDR INITIALIZATION */
- /* .. .. START: LOCK DDR */
- /* .. .. reg_ddrc_soft_rstb = 0 */
- /* .. .. ==> 0XF8006000[0:0] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. .. reg_ddrc_powerdown_en = 0x0 */
- /* .. .. ==> 0XF8006000[1:1] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. .. reg_ddrc_data_bus_width = 0x0 */
- /* .. .. ==> 0XF8006000[3:2] = 0x00000000U */
- /* .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U */
- /* .. .. reg_ddrc_burst8_refresh = 0x0 */
- /* .. .. ==> 0XF8006000[6:4] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000070U VAL : 0x00000000U */
- /* .. .. reg_ddrc_rdwr_idle_gap = 0x1 */
- /* .. .. ==> 0XF8006000[13:7] = 0x00000001U */
- /* .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U */
- /* .. .. reg_ddrc_dis_rd_bypass = 0x0 */
- /* .. .. ==> 0XF8006000[14:14] = 0x00000000U */
- /* .. .. ==> MASK : 0x00004000U VAL : 0x00000000U */
- /* .. .. reg_ddrc_dis_act_bypass = 0x0 */
- /* .. .. ==> 0XF8006000[15:15] = 0x00000000U */
- /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */
- /* .. .. reg_ddrc_dis_auto_refresh = 0x0 */
- /* .. .. ==> 0XF8006000[16:16] = 0x00000000U */
- /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000080U),
- /* .. .. FINISH: LOCK DDR */
- /* .. .. reg_ddrc_t_rfc_nom_x32 = 0x7f */
- /* .. .. ==> 0XF8006004[11:0] = 0x0000007FU */
- /* .. .. ==> MASK : 0x00000FFFU VAL : 0x0000007FU */
- /* .. .. reserved_reg_ddrc_active_ranks = 0x1 */
- /* .. .. ==> 0XF8006004[13:12] = 0x00000001U */
- /* .. .. ==> MASK : 0x00003000U VAL : 0x00001000U */
- /* .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 */
- /* .. .. ==> 0XF8006004[18:14] = 0x00000000U */
- /* .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU, 0x0000107FU),
- /* .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf */
- /* .. .. ==> 0XF8006008[10:0] = 0x0000000FU */
- /* .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU */
- /* .. .. reg_ddrc_hpr_max_starve_x32 = 0xf */
- /* .. .. ==> 0XF8006008[21:11] = 0x0000000FU */
- /* .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U */
- /* .. .. reg_ddrc_hpr_xact_run_length = 0xf */
- /* .. .. ==> 0XF8006008[25:22] = 0x0000000FU */
- /* .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU, 0x03C0780FU),
- /* .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 */
- /* .. .. ==> 0XF800600C[10:0] = 0x00000001U */
- /* .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U */
- /* .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 */
- /* .. .. ==> 0XF800600C[21:11] = 0x00000002U */
- /* .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U */
- /* .. .. reg_ddrc_lpr_xact_run_length = 0x8 */
- /* .. .. ==> 0XF800600C[25:22] = 0x00000008U */
- /* .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU, 0x02001001U),
- /* .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 */
- /* .. .. ==> 0XF8006010[10:0] = 0x00000001U */
- /* .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U */
- /* .. .. reg_ddrc_w_xact_run_length = 0x8 */
- /* .. .. ==> 0XF8006010[14:11] = 0x00000008U */
- /* .. .. ==> MASK : 0x00007800U VAL : 0x00004000U */
- /* .. .. reg_ddrc_w_max_starve_x32 = 0x2 */
- /* .. .. ==> 0XF8006010[25:15] = 0x00000002U */
- /* .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU, 0x00014001U),
- /* .. .. reg_ddrc_t_rc = 0x1a */
- /* .. .. ==> 0XF8006014[5:0] = 0x0000001AU */
- /* .. .. ==> MASK : 0x0000003FU VAL : 0x0000001AU */
- /* .. .. reg_ddrc_t_rfc_min = 0x54 */
- /* .. .. ==> 0XF8006014[13:6] = 0x00000054U */
- /* .. .. ==> MASK : 0x00003FC0U VAL : 0x00001500U */
- /* .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 */
- /* .. .. ==> 0XF8006014[20:14] = 0x00000010U */
- /* .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU, 0x0004151AU),
- /* .. .. reg_ddrc_wr2pre = 0x12 */
- /* .. .. ==> 0XF8006018[4:0] = 0x00000012U */
- /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U */
- /* .. .. reg_ddrc_powerdown_to_x32 = 0x6 */
- /* .. .. ==> 0XF8006018[9:5] = 0x00000006U */
- /* .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U */
- /* .. .. reg_ddrc_t_faw = 0x15 */
- /* .. .. ==> 0XF8006018[15:10] = 0x00000015U */
- /* .. .. ==> MASK : 0x0000FC00U VAL : 0x00005400U */
- /* .. .. reg_ddrc_t_ras_max = 0x23 */
- /* .. .. ==> 0XF8006018[21:16] = 0x00000023U */
- /* .. .. ==> MASK : 0x003F0000U VAL : 0x00230000U */
- /* .. .. reg_ddrc_t_ras_min = 0x13 */
- /* .. .. ==> 0XF8006018[26:22] = 0x00000013U */
- /* .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U */
- /* .. .. reg_ddrc_t_cke = 0x4 */
- /* .. .. ==> 0XF8006018[31:28] = 0x00000004U */
- /* .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU, 0x44E354D2U),
- /* .. .. reg_ddrc_write_latency = 0x5 */
- /* .. .. ==> 0XF800601C[4:0] = 0x00000005U */
- /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U */
- /* .. .. reg_ddrc_rd2wr = 0x7 */
- /* .. .. ==> 0XF800601C[9:5] = 0x00000007U */
- /* .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U */
- /* .. .. reg_ddrc_wr2rd = 0xe */
- /* .. .. ==> 0XF800601C[14:10] = 0x0000000EU */
- /* .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U */
- /* .. .. reg_ddrc_t_xp = 0x4 */
- /* .. .. ==> 0XF800601C[19:15] = 0x00000004U */
- /* .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U */
- /* .. .. reg_ddrc_pad_pd = 0x0 */
- /* .. .. ==> 0XF800601C[22:20] = 0x00000000U */
- /* .. .. ==> MASK : 0x00700000U VAL : 0x00000000U */
- /* .. .. reg_ddrc_rd2pre = 0x4 */
- /* .. .. ==> 0XF800601C[27:23] = 0x00000004U */
- /* .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U */
- /* .. .. reg_ddrc_t_rcd = 0x7 */
- /* .. .. ==> 0XF800601C[31:28] = 0x00000007U */
- /* .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU, 0x720238E5U),
- /* .. .. reg_ddrc_t_ccd = 0x4 */
- /* .. .. ==> 0XF8006020[4:2] = 0x00000004U */
- /* .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U */
- /* .. .. reg_ddrc_t_rrd = 0x6 */
- /* .. .. ==> 0XF8006020[7:5] = 0x00000006U */
- /* .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U */
- /* .. .. reg_ddrc_refresh_margin = 0x2 */
- /* .. .. ==> 0XF8006020[11:8] = 0x00000002U */
- /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */
- /* .. .. reg_ddrc_t_rp = 0x7 */
- /* .. .. ==> 0XF8006020[15:12] = 0x00000007U */
- /* .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U */
- /* .. .. reg_ddrc_refresh_to_x32 = 0x8 */
- /* .. .. ==> 0XF8006020[20:16] = 0x00000008U */
- /* .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U */
- /* .. .. reg_ddrc_mobile = 0x0 */
- /* .. .. ==> 0XF8006020[22:22] = 0x00000000U */
- /* .. .. ==> MASK : 0x00400000U VAL : 0x00000000U */
- /* .. .. reg_ddrc_en_dfi_dram_clk_disable = 0x0 */
- /* .. .. ==> 0XF8006020[23:23] = 0x00000000U */
- /* .. .. ==> MASK : 0x00800000U VAL : 0x00000000U */
- /* .. .. reg_ddrc_read_latency = 0x7 */
- /* .. .. ==> 0XF8006020[28:24] = 0x00000007U */
- /* .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U */
- /* .. .. reg_phy_mode_ddr1_ddr2 = 0x1 */
- /* .. .. ==> 0XF8006020[29:29] = 0x00000001U */
- /* .. .. ==> MASK : 0x20000000U VAL : 0x20000000U */
- /* .. .. reg_ddrc_dis_pad_pd = 0x0 */
- /* .. .. ==> 0XF8006020[30:30] = 0x00000000U */
- /* .. .. ==> MASK : 0x40000000U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU, 0x270872D0U),
- /* .. .. reg_ddrc_en_2t_timing_mode = 0x0 */
- /* .. .. ==> 0XF8006024[0:0] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. .. reg_ddrc_prefer_write = 0x0 */
- /* .. .. ==> 0XF8006024[1:1] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. .. reg_ddrc_mr_wr = 0x0 */
- /* .. .. ==> 0XF8006024[6:6] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000040U VAL : 0x00000000U */
- /* .. .. reg_ddrc_mr_addr = 0x0 */
- /* .. .. ==> 0XF8006024[8:7] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000180U VAL : 0x00000000U */
- /* .. .. reg_ddrc_mr_data = 0x0 */
- /* .. .. ==> 0XF8006024[24:9] = 0x00000000U */
- /* .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U */
- /* .. .. ddrc_reg_mr_wr_busy = 0x0 */
- /* .. .. ==> 0XF8006024[25:25] = 0x00000000U */
- /* .. .. ==> MASK : 0x02000000U VAL : 0x00000000U */
- /* .. .. reg_ddrc_mr_type = 0x0 */
- /* .. .. ==> 0XF8006024[26:26] = 0x00000000U */
- /* .. .. ==> MASK : 0x04000000U VAL : 0x00000000U */
- /* .. .. reg_ddrc_mr_rdata_valid = 0x0 */
- /* .. .. ==> 0XF8006024[27:27] = 0x00000000U */
- /* .. .. ==> MASK : 0x08000000U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U, 0x00000000U),
- /* .. .. reg_ddrc_final_wait_x32 = 0x7 */
- /* .. .. ==> 0XF8006028[6:0] = 0x00000007U */
- /* .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U */
- /* .. .. reg_ddrc_pre_ocd_x32 = 0x0 */
- /* .. .. ==> 0XF8006028[10:7] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000780U VAL : 0x00000000U */
- /* .. .. reg_ddrc_t_mrd = 0x4 */
- /* .. .. ==> 0XF8006028[13:11] = 0x00000004U */
- /* .. .. ==> MASK : 0x00003800U VAL : 0x00002000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006028, 0x00003FFFU, 0x00002007U),
- /* .. .. reg_ddrc_emr2 = 0x8 */
- /* .. .. ==> 0XF800602C[15:0] = 0x00000008U */
- /* .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U */
- /* .. .. reg_ddrc_emr3 = 0x0 */
- /* .. .. ==> 0XF800602C[31:16] = 0x00000000U */
- /* .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU, 0x00000008U),
- /* .. .. reg_ddrc_mr = 0x930 */
- /* .. .. ==> 0XF8006030[15:0] = 0x00000930U */
- /* .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U */
- /* .. .. reg_ddrc_emr = 0x4 */
- /* .. .. ==> 0XF8006030[31:16] = 0x00000004U */
- /* .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU, 0x00040930U),
- /* .. .. reg_ddrc_burst_rdwr = 0x4 */
- /* .. .. ==> 0XF8006034[3:0] = 0x00000004U */
- /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U */
- /* .. .. reg_ddrc_pre_cke_x1024 = 0x167 */
- /* .. .. ==> 0XF8006034[13:4] = 0x00000167U */
- /* .. .. ==> MASK : 0x00003FF0U VAL : 0x00001670U */
- /* .. .. reg_ddrc_post_cke_x1024 = 0x1 */
- /* .. .. ==> 0XF8006034[25:16] = 0x00000001U */
- /* .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U */
- /* .. .. reg_ddrc_burstchop = 0x0 */
- /* .. .. ==> 0XF8006034[28:28] = 0x00000000U */
- /* .. .. ==> MASK : 0x10000000U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x00011674U),
- /* .. .. reg_ddrc_force_low_pri_n = 0x0 */
- /* .. .. ==> 0XF8006038[0:0] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. .. reg_ddrc_dis_dq = 0x0 */
- /* .. .. ==> 0XF8006038[1:1] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006038, 0x00000003U, 0x00000000U),
- /* .. .. reg_ddrc_addrmap_bank_b0 = 0x7 */
- /* .. .. ==> 0XF800603C[3:0] = 0x00000007U */
- /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U */
- /* .. .. reg_ddrc_addrmap_bank_b1 = 0x7 */
- /* .. .. ==> 0XF800603C[7:4] = 0x00000007U */
- /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U */
- /* .. .. reg_ddrc_addrmap_bank_b2 = 0x7 */
- /* .. .. ==> 0XF800603C[11:8] = 0x00000007U */
- /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U */
- /* .. .. reg_ddrc_addrmap_col_b5 = 0x0 */
- /* .. .. ==> 0XF800603C[15:12] = 0x00000000U */
- /* .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U */
- /* .. .. reg_ddrc_addrmap_col_b6 = 0x0 */
- /* .. .. ==> 0XF800603C[19:16] = 0x00000000U */
- /* .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU, 0x00000777U),
- /* .. .. reg_ddrc_addrmap_col_b2 = 0x0 */
- /* .. .. ==> 0XF8006040[3:0] = 0x00000000U */
- /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U */
- /* .. .. reg_ddrc_addrmap_col_b3 = 0x0 */
- /* .. .. ==> 0XF8006040[7:4] = 0x00000000U */
- /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */
- /* .. .. reg_ddrc_addrmap_col_b4 = 0x0 */
- /* .. .. ==> 0XF8006040[11:8] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U */
- /* .. .. reg_ddrc_addrmap_col_b7 = 0x0 */
- /* .. .. ==> 0XF8006040[15:12] = 0x00000000U */
- /* .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U */
- /* .. .. reg_ddrc_addrmap_col_b8 = 0x0 */
- /* .. .. ==> 0XF8006040[19:16] = 0x00000000U */
- /* .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U */
- /* .. .. reg_ddrc_addrmap_col_b9 = 0xf */
- /* .. .. ==> 0XF8006040[23:20] = 0x0000000FU */
- /* .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U */
- /* .. .. reg_ddrc_addrmap_col_b10 = 0xf */
- /* .. .. ==> 0XF8006040[27:24] = 0x0000000FU */
- /* .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U */
- /* .. .. reg_ddrc_addrmap_col_b11 = 0xf */
- /* .. .. ==> 0XF8006040[31:28] = 0x0000000FU */
- /* .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU, 0xFFF00000U),
- /* .. .. reg_ddrc_addrmap_row_b0 = 0x6 */
- /* .. .. ==> 0XF8006044[3:0] = 0x00000006U */
- /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U */
- /* .. .. reg_ddrc_addrmap_row_b1 = 0x6 */
- /* .. .. ==> 0XF8006044[7:4] = 0x00000006U */
- /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U */
- /* .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 */
- /* .. .. ==> 0XF8006044[11:8] = 0x00000006U */
- /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U */
- /* .. .. reg_ddrc_addrmap_row_b12 = 0x6 */
- /* .. .. ==> 0XF8006044[15:12] = 0x00000006U */
- /* .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U */
- /* .. .. reg_ddrc_addrmap_row_b13 = 0x6 */
- /* .. .. ==> 0XF8006044[19:16] = 0x00000006U */
- /* .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U */
- /* .. .. reg_ddrc_addrmap_row_b14 = 0xf */
- /* .. .. ==> 0XF8006044[23:20] = 0x0000000FU */
- /* .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U */
- /* .. .. reg_ddrc_addrmap_row_b15 = 0xf */
- /* .. .. ==> 0XF8006044[27:24] = 0x0000000FU */
- /* .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU, 0x0FF66666U),
- /* .. .. reg_phy_rd_local_odt = 0x0 */
- /* .. .. ==> 0XF8006048[13:12] = 0x00000000U */
- /* .. .. ==> MASK : 0x00003000U VAL : 0x00000000U */
- /* .. .. reg_phy_wr_local_odt = 0x3 */
- /* .. .. ==> 0XF8006048[15:14] = 0x00000003U */
- /* .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U */
- /* .. .. reg_phy_idle_local_odt = 0x3 */
- /* .. .. ==> 0XF8006048[17:16] = 0x00000003U */
- /* .. .. ==> MASK : 0x00030000U VAL : 0x00030000U */
- /* .. .. reserved_reg_ddrc_rank0_wr_odt = 0x1 */
- /* .. .. ==> 0XF8006048[5:3] = 0x00000001U */
- /* .. .. ==> MASK : 0x00000038U VAL : 0x00000008U */
- /* .. .. reserved_reg_ddrc_rank0_rd_odt = 0x0 */
- /* .. .. ==> 0XF8006048[2:0] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000007U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006048, 0x0003F03FU, 0x0003C008U),
- /* .. .. reg_phy_rd_cmd_to_data = 0x0 */
- /* .. .. ==> 0XF8006050[3:0] = 0x00000000U */
- /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U */
- /* .. .. reg_phy_wr_cmd_to_data = 0x0 */
- /* .. .. ==> 0XF8006050[7:4] = 0x00000000U */
- /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */
- /* .. .. reg_phy_rdc_we_to_re_delay = 0x8 */
- /* .. .. ==> 0XF8006050[11:8] = 0x00000008U */
- /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U */
- /* .. .. reg_phy_rdc_fifo_rst_disable = 0x0 */
- /* .. .. ==> 0XF8006050[15:15] = 0x00000000U */
- /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */
- /* .. .. reg_phy_use_fixed_re = 0x1 */
- /* .. .. ==> 0XF8006050[16:16] = 0x00000001U */
- /* .. .. ==> MASK : 0x00010000U VAL : 0x00010000U */
- /* .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 */
- /* .. .. ==> 0XF8006050[17:17] = 0x00000000U */
- /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
- /* .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 */
- /* .. .. ==> 0XF8006050[18:18] = 0x00000000U */
- /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
- /* .. .. reg_phy_clk_stall_level = 0x0 */
- /* .. .. ==> 0XF8006050[19:19] = 0x00000000U */
- /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */
- /* .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 */
- /* .. .. ==> 0XF8006050[27:24] = 0x00000007U */
- /* .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U */
- /* .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 */
- /* .. .. ==> 0XF8006050[31:28] = 0x00000007U */
- /* .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU, 0x77010800U),
- /* .. .. reg_ddrc_dis_dll_calib = 0x0 */
- /* .. .. ==> 0XF8006058[16:16] = 0x00000000U */
- /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006058, 0x00010000U, 0x00000000U),
- /* .. .. reg_ddrc_rd_odt_delay = 0x3 */
- /* .. .. ==> 0XF800605C[3:0] = 0x00000003U */
- /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U */
- /* .. .. reg_ddrc_wr_odt_delay = 0x0 */
- /* .. .. ==> 0XF800605C[7:4] = 0x00000000U */
- /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */
- /* .. .. reg_ddrc_rd_odt_hold = 0x0 */
- /* .. .. ==> 0XF800605C[11:8] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U */
- /* .. .. reg_ddrc_wr_odt_hold = 0x5 */
- /* .. .. ==> 0XF800605C[15:12] = 0x00000005U */
- /* .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU, 0x00005003U),
- /* .. .. reg_ddrc_pageclose = 0x0 */
- /* .. .. ==> 0XF8006060[0:0] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. .. reg_ddrc_lpr_num_entries = 0x1f */
- /* .. .. ==> 0XF8006060[6:1] = 0x0000001FU */
- /* .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU */
- /* .. .. reg_ddrc_auto_pre_en = 0x0 */
- /* .. .. ==> 0XF8006060[7:7] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000080U VAL : 0x00000000U */
- /* .. .. reg_ddrc_refresh_update_level = 0x0 */
- /* .. .. ==> 0XF8006060[8:8] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000100U VAL : 0x00000000U */
- /* .. .. reg_ddrc_dis_wc = 0x0 */
- /* .. .. ==> 0XF8006060[9:9] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000200U VAL : 0x00000000U */
- /* .. .. reg_ddrc_dis_collision_page_opt = 0x0 */
- /* .. .. ==> 0XF8006060[10:10] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
- /* .. .. reg_ddrc_selfref_en = 0x0 */
- /* .. .. ==> 0XF8006060[12:12] = 0x00000000U */
- /* .. .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006060, 0x000017FFU, 0x0000003EU),
- /* .. .. reg_ddrc_go2critical_hysteresis = 0x0 */
- /* .. .. ==> 0XF8006064[12:5] = 0x00000000U */
- /* .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U */
- /* .. .. reg_arb_go2critical_en = 0x1 */
- /* .. .. ==> 0XF8006064[17:17] = 0x00000001U */
- /* .. .. ==> MASK : 0x00020000U VAL : 0x00020000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006064, 0x00021FE0U, 0x00020000U),
- /* .. .. reg_ddrc_wrlvl_ww = 0x41 */
- /* .. .. ==> 0XF8006068[7:0] = 0x00000041U */
- /* .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U */
- /* .. .. reg_ddrc_rdlvl_rr = 0x41 */
- /* .. .. ==> 0XF8006068[15:8] = 0x00000041U */
- /* .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U */
- /* .. .. reg_ddrc_dfi_t_wlmrd = 0x28 */
- /* .. .. ==> 0XF8006068[25:16] = 0x00000028U */
- /* .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU, 0x00284141U),
- /* .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 */
- /* .. .. ==> 0XF800606C[7:0] = 0x00000010U */
- /* .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U */
- /* .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 */
- /* .. .. ==> 0XF800606C[15:8] = 0x00000016U */
- /* .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U */
- /* .. .. */
- EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU, 0x00001610U),
- /* .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1 */
- /* .. .. ==> 0XF8006078[3:0] = 0x00000001U */
- /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U */
- /* .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1 */
- /* .. .. ==> 0XF8006078[7:4] = 0x00000001U */
- /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U */
- /* .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1 */
- /* .. .. ==> 0XF8006078[11:8] = 0x00000001U */
- /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U */
- /* .. .. reg_ddrc_t_cksre = 0x6 */
- /* .. .. ==> 0XF8006078[15:12] = 0x00000006U */
- /* .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U */
- /* .. .. reg_ddrc_t_cksrx = 0x6 */
- /* .. .. ==> 0XF8006078[19:16] = 0x00000006U */
- /* .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U */
- /* .. .. reg_ddrc_t_ckesr = 0x4 */
- /* .. .. ==> 0XF8006078[25:20] = 0x00000004U */
- /* .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU, 0x00466111U),
- /* .. .. reg_ddrc_t_ckpde = 0x2 */
- /* .. .. ==> 0XF800607C[3:0] = 0x00000002U */
- /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U */
- /* .. .. reg_ddrc_t_ckpdx = 0x2 */
- /* .. .. ==> 0XF800607C[7:4] = 0x00000002U */
- /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U */
- /* .. .. reg_ddrc_t_ckdpde = 0x2 */
- /* .. .. ==> 0XF800607C[11:8] = 0x00000002U */
- /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */
- /* .. .. reg_ddrc_t_ckdpdx = 0x2 */
- /* .. .. ==> 0XF800607C[15:12] = 0x00000002U */
- /* .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U */
- /* .. .. reg_ddrc_t_ckcsx = 0x3 */
- /* .. .. ==> 0XF800607C[19:16] = 0x00000003U */
- /* .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU, 0x00032222U),
- /* .. .. reg_ddrc_dis_auto_zq = 0x0 */
- /* .. .. ==> 0XF80060A4[0:0] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. .. reg_ddrc_ddr3 = 0x1 */
- /* .. .. ==> 0XF80060A4[1:1] = 0x00000001U */
- /* .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */
- /* .. .. reg_ddrc_t_mod = 0x200 */
- /* .. .. ==> 0XF80060A4[11:2] = 0x00000200U */
- /* .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U */
- /* .. .. reg_ddrc_t_zq_long_nop = 0x200 */
- /* .. .. ==> 0XF80060A4[21:12] = 0x00000200U */
- /* .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U */
- /* .. .. reg_ddrc_t_zq_short_nop = 0x40 */
- /* .. .. ==> 0XF80060A4[31:22] = 0x00000040U */
- /* .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U),
- /* .. .. t_zq_short_interval_x1024 = 0xc845 */
- /* .. .. ==> 0XF80060A8[19:0] = 0x0000C845U */
- /* .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000C845U */
- /* .. .. dram_rstn_x1024 = 0x67 */
- /* .. .. ==> 0XF80060A8[27:20] = 0x00000067U */
- /* .. .. ==> MASK : 0x0FF00000U VAL : 0x06700000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0670C845U),
- /* .. .. deeppowerdown_en = 0x0 */
- /* .. .. ==> 0XF80060AC[0:0] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. .. deeppowerdown_to_x1024 = 0xff */
- /* .. .. ==> 0XF80060AC[8:1] = 0x000000FFU */
- /* .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU */
- /* .. .. */
- EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU),
- /* .. .. dfi_wrlvl_max_x1024 = 0xfff */
- /* .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU */
- /* .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU */
- /* .. .. dfi_rdlvl_max_x1024 = 0xfff */
- /* .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU */
- /* .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U */
- /* .. .. ddrc_reg_twrlvl_max_error = 0x0 */
- /* .. .. ==> 0XF80060B0[24:24] = 0x00000000U */
- /* .. .. ==> MASK : 0x01000000U VAL : 0x00000000U */
- /* .. .. ddrc_reg_trdlvl_max_error = 0x0 */
- /* .. .. ==> 0XF80060B0[25:25] = 0x00000000U */
- /* .. .. ==> MASK : 0x02000000U VAL : 0x00000000U */
- /* .. .. reg_ddrc_dfi_wr_level_en = 0x1 */
- /* .. .. ==> 0XF80060B0[26:26] = 0x00000001U */
- /* .. .. ==> MASK : 0x04000000U VAL : 0x04000000U */
- /* .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 */
- /* .. .. ==> 0XF80060B0[27:27] = 0x00000001U */
- /* .. .. ==> MASK : 0x08000000U VAL : 0x08000000U */
- /* .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 */
- /* .. .. ==> 0XF80060B0[28:28] = 0x00000001U */
- /* .. .. ==> MASK : 0x10000000U VAL : 0x10000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
- /* .. .. reg_ddrc_skip_ocd = 0x1 */
- /* .. .. ==> 0XF80060B4[9:9] = 0x00000001U */
- /* .. .. ==> MASK : 0x00000200U VAL : 0x00000200U */
- /* .. .. */
- EMIT_MASKWRITE(0XF80060B4, 0x00000200U, 0x00000200U),
- /* .. .. reg_ddrc_dfi_t_rddata_en = 0x6 */
- /* .. .. ==> 0XF80060B8[4:0] = 0x00000006U */
- /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U */
- /* .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 */
- /* .. .. ==> 0XF80060B8[14:5] = 0x00000003U */
- /* .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U */
- /* .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 */
- /* .. .. ==> 0XF80060B8[24:15] = 0x00000040U */
- /* .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU, 0x00200066U),
- /* .. .. START: RESET ECC ERROR */
- /* .. .. Clear_Uncorrectable_DRAM_ECC_error = 1 */
- /* .. .. ==> 0XF80060C4[0:0] = 0x00000001U */
- /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
- /* .. .. Clear_Correctable_DRAM_ECC_error = 1 */
- /* .. .. ==> 0XF80060C4[1:1] = 0x00000001U */
- /* .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */
- /* .. .. */
- EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000003U),
- /* .. .. FINISH: RESET ECC ERROR */
- /* .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 */
- /* .. .. ==> 0XF80060C4[0:0] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. .. Clear_Correctable_DRAM_ECC_error = 0x0 */
- /* .. .. ==> 0XF80060C4[1:1] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000000U),
- /* .. .. CORR_ECC_LOG_VALID = 0x0 */
- /* .. .. ==> 0XF80060C8[0:0] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. .. ECC_CORRECTED_BIT_NUM = 0x0 */
- /* .. .. ==> 0XF80060C8[7:1] = 0x00000000U */
- /* .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF80060C8, 0x000000FFU, 0x00000000U),
- /* .. .. UNCORR_ECC_LOG_VALID = 0x0 */
- /* .. .. ==> 0XF80060DC[0:0] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF80060DC, 0x00000001U, 0x00000000U),
- /* .. .. STAT_NUM_CORR_ERR = 0x0 */
- /* .. .. ==> 0XF80060F0[15:8] = 0x00000000U */
- /* .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U */
- /* .. .. STAT_NUM_UNCORR_ERR = 0x0 */
- /* .. .. ==> 0XF80060F0[7:0] = 0x00000000U */
- /* .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU, 0x00000000U),
- /* .. .. reg_ddrc_ecc_mode = 0x0 */
- /* .. .. ==> 0XF80060F4[2:0] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000007U VAL : 0x00000000U */
- /* .. .. reg_ddrc_dis_scrub = 0x1 */
- /* .. .. ==> 0XF80060F4[3:3] = 0x00000001U */
- /* .. .. ==> MASK : 0x00000008U VAL : 0x00000008U */
- /* .. .. */
- EMIT_MASKWRITE(0XF80060F4, 0x0000000FU, 0x00000008U),
- /* .. .. reg_phy_dif_on = 0x0 */
- /* .. .. ==> 0XF8006114[3:0] = 0x00000000U */
- /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U */
- /* .. .. reg_phy_dif_off = 0x0 */
- /* .. .. ==> 0XF8006114[7:4] = 0x00000000U */
- /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006114, 0x000000FFU, 0x00000000U),
- /* .. .. reg_phy_data_slice_in_use = 0x1 */
- /* .. .. ==> 0XF8006118[0:0] = 0x00000001U */
- /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
- /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
- /* .. .. ==> 0XF8006118[1:1] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
- /* .. .. ==> 0XF8006118[2:2] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
- /* .. .. ==> 0XF8006118[3:3] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */
- /* .. .. reg_phy_bist_shift_dq = 0x0 */
- /* .. .. ==> 0XF8006118[14:6] = 0x00000000U */
- /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */
- /* .. .. reg_phy_bist_err_clr = 0x0 */
- /* .. .. ==> 0XF8006118[23:15] = 0x00000000U */
- /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */
- /* .. .. reg_phy_dq_offset = 0x40 */
- /* .. .. ==> 0XF8006118[30:24] = 0x00000040U */
- /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU, 0x40000001U),
- /* .. .. reg_phy_data_slice_in_use = 0x1 */
- /* .. .. ==> 0XF800611C[0:0] = 0x00000001U */
- /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
- /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
- /* .. .. ==> 0XF800611C[1:1] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
- /* .. .. ==> 0XF800611C[2:2] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
- /* .. .. ==> 0XF800611C[3:3] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */
- /* .. .. reg_phy_bist_shift_dq = 0x0 */
- /* .. .. ==> 0XF800611C[14:6] = 0x00000000U */
- /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */
- /* .. .. reg_phy_bist_err_clr = 0x0 */
- /* .. .. ==> 0XF800611C[23:15] = 0x00000000U */
- /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */
- /* .. .. reg_phy_dq_offset = 0x40 */
- /* .. .. ==> 0XF800611C[30:24] = 0x00000040U */
- /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU, 0x40000001U),
- /* .. .. reg_phy_data_slice_in_use = 0x1 */
- /* .. .. ==> 0XF8006120[0:0] = 0x00000001U */
- /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
- /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
- /* .. .. ==> 0XF8006120[1:1] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
- /* .. .. ==> 0XF8006120[2:2] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
- /* .. .. ==> 0XF8006120[3:3] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */
- /* .. .. reg_phy_bist_shift_dq = 0x0 */
- /* .. .. ==> 0XF8006120[14:6] = 0x00000000U */
- /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */
- /* .. .. reg_phy_bist_err_clr = 0x0 */
- /* .. .. ==> 0XF8006120[23:15] = 0x00000000U */
- /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */
- /* .. .. reg_phy_dq_offset = 0x40 */
- /* .. .. ==> 0XF8006120[30:24] = 0x00000040U */
- /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU, 0x40000001U),
- /* .. .. reg_phy_data_slice_in_use = 0x1 */
- /* .. .. ==> 0XF8006124[0:0] = 0x00000001U */
- /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
- /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
- /* .. .. ==> 0XF8006124[1:1] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
- /* .. .. ==> 0XF8006124[2:2] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
- /* .. .. ==> 0XF8006124[3:3] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */
- /* .. .. reg_phy_bist_shift_dq = 0x0 */
- /* .. .. ==> 0XF8006124[14:6] = 0x00000000U */
- /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */
- /* .. .. reg_phy_bist_err_clr = 0x0 */
- /* .. .. ==> 0XF8006124[23:15] = 0x00000000U */
- /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */
- /* .. .. reg_phy_dq_offset = 0x40 */
- /* .. .. ==> 0XF8006124[30:24] = 0x00000040U */
- /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU, 0x40000001U),
- /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
- /* .. .. ==> 0XF800612C[9:0] = 0x00000000U */
- /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */
- /* .. .. reg_phy_gatelvl_init_ratio = 0x8f */
- /* .. .. ==> 0XF800612C[19:10] = 0x0000008FU */
- /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00023C00U */
- /* .. .. */
- EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU, 0x00023C00U),
- /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
- /* .. .. ==> 0XF8006130[9:0] = 0x00000000U */
- /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */
- /* .. .. reg_phy_gatelvl_init_ratio = 0x8a */
- /* .. .. ==> 0XF8006130[19:10] = 0x0000008AU */
- /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00022800U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU, 0x00022800U),
- /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
- /* .. .. ==> 0XF8006134[9:0] = 0x00000000U */
- /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */
- /* .. .. reg_phy_gatelvl_init_ratio = 0x8b */
- /* .. .. ==> 0XF8006134[19:10] = 0x0000008BU */
- /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00022C00U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU, 0x00022C00U),
- /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
- /* .. .. ==> 0XF8006138[9:0] = 0x00000000U */
- /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */
- /* .. .. reg_phy_gatelvl_init_ratio = 0x92 */
- /* .. .. ==> 0XF8006138[19:10] = 0x00000092U */
- /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00024800U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU, 0x00024800U),
- /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
- /* .. .. ==> 0XF8006140[9:0] = 0x00000035U */
- /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */
- /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
- /* .. .. ==> 0XF8006140[10:10] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
- /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
- /* .. .. ==> 0XF8006140[19:11] = 0x00000000U */
- /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU, 0x00000035U),
- /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
- /* .. .. ==> 0XF8006144[9:0] = 0x00000035U */
- /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */
- /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
- /* .. .. ==> 0XF8006144[10:10] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
- /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
- /* .. .. ==> 0XF8006144[19:11] = 0x00000000U */
- /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU, 0x00000035U),
- /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
- /* .. .. ==> 0XF8006148[9:0] = 0x00000035U */
- /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */
- /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
- /* .. .. ==> 0XF8006148[10:10] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
- /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
- /* .. .. ==> 0XF8006148[19:11] = 0x00000000U */
- /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU, 0x00000035U),
- /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
- /* .. .. ==> 0XF800614C[9:0] = 0x00000035U */
- /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */
- /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
- /* .. .. ==> 0XF800614C[10:10] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
- /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
- /* .. .. ==> 0XF800614C[19:11] = 0x00000000U */
- /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU, 0x00000035U),
- /* .. .. reg_phy_wr_dqs_slave_ratio = 0x77 */
- /* .. .. ==> 0XF8006154[9:0] = 0x00000077U */
- /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000077U */
- /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
- /* .. .. ==> 0XF8006154[10:10] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
- /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
- /* .. .. ==> 0XF8006154[19:11] = 0x00000000U */
- /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU, 0x00000077U),
- /* .. .. reg_phy_wr_dqs_slave_ratio = 0x7c */
- /* .. .. ==> 0XF8006158[9:0] = 0x0000007CU */
- /* .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU */
- /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
- /* .. .. ==> 0XF8006158[10:10] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
- /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
- /* .. .. ==> 0XF8006158[19:11] = 0x00000000U */
- /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU, 0x0000007CU),
- /* .. .. reg_phy_wr_dqs_slave_ratio = 0x7c */
- /* .. .. ==> 0XF800615C[9:0] = 0x0000007CU */
- /* .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU */
- /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
- /* .. .. ==> 0XF800615C[10:10] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
- /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
- /* .. .. ==> 0XF800615C[19:11] = 0x00000000U */
- /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU, 0x0000007CU),
- /* .. .. reg_phy_wr_dqs_slave_ratio = 0x75 */
- /* .. .. ==> 0XF8006160[9:0] = 0x00000075U */
- /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000075U */
- /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
- /* .. .. ==> 0XF8006160[10:10] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
- /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
- /* .. .. ==> 0XF8006160[19:11] = 0x00000000U */
- /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU, 0x00000075U),
- /* .. .. reg_phy_fifo_we_slave_ratio = 0xe4 */
- /* .. .. ==> 0XF8006168[10:0] = 0x000000E4U */
- /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000E4U */
- /* .. .. reg_phy_fifo_we_in_force = 0x0 */
- /* .. .. ==> 0XF8006168[11:11] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */
- /* .. .. reg_phy_fifo_we_in_delay = 0x0 */
- /* .. .. ==> 0XF8006168[20:12] = 0x00000000U */
- /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU, 0x000000E4U),
- /* .. .. reg_phy_fifo_we_slave_ratio = 0xdf */
- /* .. .. ==> 0XF800616C[10:0] = 0x000000DFU */
- /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000DFU */
- /* .. .. reg_phy_fifo_we_in_force = 0x0 */
- /* .. .. ==> 0XF800616C[11:11] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */
- /* .. .. reg_phy_fifo_we_in_delay = 0x0 */
- /* .. .. ==> 0XF800616C[20:12] = 0x00000000U */
- /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU, 0x000000DFU),
- /* .. .. reg_phy_fifo_we_slave_ratio = 0xe0 */
- /* .. .. ==> 0XF8006170[10:0] = 0x000000E0U */
- /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000E0U */
- /* .. .. reg_phy_fifo_we_in_force = 0x0 */
- /* .. .. ==> 0XF8006170[11:11] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */
- /* .. .. reg_phy_fifo_we_in_delay = 0x0 */
- /* .. .. ==> 0XF8006170[20:12] = 0x00000000U */
- /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU, 0x000000E0U),
- /* .. .. reg_phy_fifo_we_slave_ratio = 0xe7 */
- /* .. .. ==> 0XF8006174[10:0] = 0x000000E7U */
- /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000E7U */
- /* .. .. reg_phy_fifo_we_in_force = 0x0 */
- /* .. .. ==> 0XF8006174[11:11] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */
- /* .. .. reg_phy_fifo_we_in_delay = 0x0 */
- /* .. .. ==> 0XF8006174[20:12] = 0x00000000U */
- /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU, 0x000000E7U),
- /* .. .. reg_phy_wr_data_slave_ratio = 0xb7 */
- /* .. .. ==> 0XF800617C[9:0] = 0x000000B7U */
- /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000B7U */
- /* .. .. reg_phy_wr_data_slave_force = 0x0 */
- /* .. .. ==> 0XF800617C[10:10] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
- /* .. .. reg_phy_wr_data_slave_delay = 0x0 */
- /* .. .. ==> 0XF800617C[19:11] = 0x00000000U */
- /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU, 0x000000B7U),
- /* .. .. reg_phy_wr_data_slave_ratio = 0xbc */
- /* .. .. ==> 0XF8006180[9:0] = 0x000000BCU */
- /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU */
- /* .. .. reg_phy_wr_data_slave_force = 0x0 */
- /* .. .. ==> 0XF8006180[10:10] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
- /* .. .. reg_phy_wr_data_slave_delay = 0x0 */
- /* .. .. ==> 0XF8006180[19:11] = 0x00000000U */
- /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU, 0x000000BCU),
- /* .. .. reg_phy_wr_data_slave_ratio = 0xbc */
- /* .. .. ==> 0XF8006184[9:0] = 0x000000BCU */
- /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU */
- /* .. .. reg_phy_wr_data_slave_force = 0x0 */
- /* .. .. ==> 0XF8006184[10:10] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
- /* .. .. reg_phy_wr_data_slave_delay = 0x0 */
- /* .. .. ==> 0XF8006184[19:11] = 0x00000000U */
- /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU, 0x000000BCU),
- /* .. .. reg_phy_wr_data_slave_ratio = 0xb5 */
- /* .. .. ==> 0XF8006188[9:0] = 0x000000B5U */
- /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000B5U */
- /* .. .. reg_phy_wr_data_slave_force = 0x0 */
- /* .. .. ==> 0XF8006188[10:10] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
- /* .. .. reg_phy_wr_data_slave_delay = 0x0 */
- /* .. .. ==> 0XF8006188[19:11] = 0x00000000U */
- /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU, 0x000000B5U),
- /* .. .. reg_phy_bl2 = 0x0 */
- /* .. .. ==> 0XF8006190[1:1] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. .. reg_phy_at_spd_atpg = 0x0 */
- /* .. .. ==> 0XF8006190[2:2] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. .. reg_phy_bist_enable = 0x0 */
- /* .. .. ==> 0XF8006190[3:3] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */
- /* .. .. reg_phy_bist_force_err = 0x0 */
- /* .. .. ==> 0XF8006190[4:4] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
- /* .. .. reg_phy_bist_mode = 0x0 */
- /* .. .. ==> 0XF8006190[6:5] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000060U VAL : 0x00000000U */
- /* .. .. reg_phy_invert_clkout = 0x1 */
- /* .. .. ==> 0XF8006190[7:7] = 0x00000001U */
- /* .. .. ==> MASK : 0x00000080U VAL : 0x00000080U */
- /* .. .. reg_phy_sel_logic = 0x0 */
- /* .. .. ==> 0XF8006190[9:9] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000200U VAL : 0x00000000U */
- /* .. .. reg_phy_ctrl_slave_ratio = 0x100 */
- /* .. .. ==> 0XF8006190[19:10] = 0x00000100U */
- /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U */
- /* .. .. reg_phy_ctrl_slave_force = 0x0 */
- /* .. .. ==> 0XF8006190[20:20] = 0x00000000U */
- /* .. .. ==> MASK : 0x00100000U VAL : 0x00000000U */
- /* .. .. reg_phy_ctrl_slave_delay = 0x0 */
- /* .. .. ==> 0XF8006190[27:21] = 0x00000000U */
- /* .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U */
- /* .. .. reg_phy_lpddr = 0x0 */
- /* .. .. ==> 0XF8006190[29:29] = 0x00000000U */
- /* .. .. ==> MASK : 0x20000000U VAL : 0x00000000U */
- /* .. .. reg_phy_cmd_latency = 0x0 */
- /* .. .. ==> 0XF8006190[30:30] = 0x00000000U */
- /* .. .. ==> MASK : 0x40000000U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU, 0x00040080U),
- /* .. .. reg_phy_wr_rl_delay = 0x2 */
- /* .. .. ==> 0XF8006194[4:0] = 0x00000002U */
- /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U */
- /* .. .. reg_phy_rd_rl_delay = 0x4 */
- /* .. .. ==> 0XF8006194[9:5] = 0x00000004U */
- /* .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U */
- /* .. .. reg_phy_dll_lock_diff = 0xf */
- /* .. .. ==> 0XF8006194[13:10] = 0x0000000FU */
- /* .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U */
- /* .. .. reg_phy_use_wr_level = 0x1 */
- /* .. .. ==> 0XF8006194[14:14] = 0x00000001U */
- /* .. .. ==> MASK : 0x00004000U VAL : 0x00004000U */
- /* .. .. reg_phy_use_rd_dqs_gate_level = 0x1 */
- /* .. .. ==> 0XF8006194[15:15] = 0x00000001U */
- /* .. .. ==> MASK : 0x00008000U VAL : 0x00008000U */
- /* .. .. reg_phy_use_rd_data_eye_level = 0x1 */
- /* .. .. ==> 0XF8006194[16:16] = 0x00000001U */
- /* .. .. ==> MASK : 0x00010000U VAL : 0x00010000U */
- /* .. .. reg_phy_dis_calib_rst = 0x0 */
- /* .. .. ==> 0XF8006194[17:17] = 0x00000000U */
- /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
- /* .. .. reg_phy_ctrl_slave_delay = 0x0 */
- /* .. .. ==> 0XF8006194[19:18] = 0x00000000U */
- /* .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU, 0x0001FC82U),
- /* .. .. reg_arb_page_addr_mask = 0x0 */
- /* .. .. ==> 0XF8006204[31:0] = 0x00000000U */
- /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU, 0x00000000U),
- /* .. .. reg_arb_pri_wr_portn = 0x3ff */
- /* .. .. ==> 0XF8006208[9:0] = 0x000003FFU */
- /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
- /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
- /* .. .. ==> 0XF8006208[16:16] = 0x00000000U */
- /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
- /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
- /* .. .. ==> 0XF8006208[17:17] = 0x00000000U */
- /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
- /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
- /* .. .. ==> 0XF8006208[18:18] = 0x00000000U */
- /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006208, 0x000703FFU, 0x000003FFU),
- /* .. .. reg_arb_pri_wr_portn = 0x3ff */
- /* .. .. ==> 0XF800620C[9:0] = 0x000003FFU */
- /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
- /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
- /* .. .. ==> 0XF800620C[16:16] = 0x00000000U */
- /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
- /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
- /* .. .. ==> 0XF800620C[17:17] = 0x00000000U */
- /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
- /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
- /* .. .. ==> 0XF800620C[18:18] = 0x00000000U */
- /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF800620C, 0x000703FFU, 0x000003FFU),
- /* .. .. reg_arb_pri_wr_portn = 0x3ff */
- /* .. .. ==> 0XF8006210[9:0] = 0x000003FFU */
- /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
- /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
- /* .. .. ==> 0XF8006210[16:16] = 0x00000000U */
- /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
- /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
- /* .. .. ==> 0XF8006210[17:17] = 0x00000000U */
- /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
- /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
- /* .. .. ==> 0XF8006210[18:18] = 0x00000000U */
- /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006210, 0x000703FFU, 0x000003FFU),
- /* .. .. reg_arb_pri_wr_portn = 0x3ff */
- /* .. .. ==> 0XF8006214[9:0] = 0x000003FFU */
- /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
- /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
- /* .. .. ==> 0XF8006214[16:16] = 0x00000000U */
- /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
- /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
- /* .. .. ==> 0XF8006214[17:17] = 0x00000000U */
- /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
- /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
- /* .. .. ==> 0XF8006214[18:18] = 0x00000000U */
- /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006214, 0x000703FFU, 0x000003FFU),
- /* .. .. reg_arb_pri_rd_portn = 0x3ff */
- /* .. .. ==> 0XF8006218[9:0] = 0x000003FFU */
- /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
- /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
- /* .. .. ==> 0XF8006218[16:16] = 0x00000000U */
- /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
- /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
- /* .. .. ==> 0XF8006218[17:17] = 0x00000000U */
- /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
- /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
- /* .. .. ==> 0XF8006218[18:18] = 0x00000000U */
- /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
- /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
- /* .. .. ==> 0XF8006218[19:19] = 0x00000000U */
- /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006218, 0x000F03FFU, 0x000003FFU),
- /* .. .. reg_arb_pri_rd_portn = 0x3ff */
- /* .. .. ==> 0XF800621C[9:0] = 0x000003FFU */
- /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
- /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
- /* .. .. ==> 0XF800621C[16:16] = 0x00000000U */
- /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
- /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
- /* .. .. ==> 0XF800621C[17:17] = 0x00000000U */
- /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
- /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
- /* .. .. ==> 0XF800621C[18:18] = 0x00000000U */
- /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
- /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
- /* .. .. ==> 0XF800621C[19:19] = 0x00000000U */
- /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF800621C, 0x000F03FFU, 0x000003FFU),
- /* .. .. reg_arb_pri_rd_portn = 0x3ff */
- /* .. .. ==> 0XF8006220[9:0] = 0x000003FFU */
- /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
- /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
- /* .. .. ==> 0XF8006220[16:16] = 0x00000000U */
- /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
- /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
- /* .. .. ==> 0XF8006220[17:17] = 0x00000000U */
- /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
- /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
- /* .. .. ==> 0XF8006220[18:18] = 0x00000000U */
- /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
- /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
- /* .. .. ==> 0XF8006220[19:19] = 0x00000000U */
- /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006220, 0x000F03FFU, 0x000003FFU),
- /* .. .. reg_arb_pri_rd_portn = 0x3ff */
- /* .. .. ==> 0XF8006224[9:0] = 0x000003FFU */
- /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
- /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
- /* .. .. ==> 0XF8006224[16:16] = 0x00000000U */
- /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
- /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
- /* .. .. ==> 0XF8006224[17:17] = 0x00000000U */
- /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
- /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
- /* .. .. ==> 0XF8006224[18:18] = 0x00000000U */
- /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
- /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
- /* .. .. ==> 0XF8006224[19:19] = 0x00000000U */
- /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006224, 0x000F03FFU, 0x000003FFU),
- /* .. .. reg_ddrc_lpddr2 = 0x0 */
- /* .. .. ==> 0XF80062A8[0:0] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. .. reg_ddrc_derate_enable = 0x0 */
- /* .. .. ==> 0XF80062A8[2:2] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. .. reg_ddrc_mr4_margin = 0x0 */
- /* .. .. ==> 0XF80062A8[11:4] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U, 0x00000000U),
- /* .. .. reg_ddrc_mr4_read_interval = 0x0 */
- /* .. .. ==> 0XF80062AC[31:0] = 0x00000000U */
- /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU, 0x00000000U),
- /* .. .. reg_ddrc_min_stable_clock_x1 = 0x5 */
- /* .. .. ==> 0XF80062B0[3:0] = 0x00000005U */
- /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U */
- /* .. .. reg_ddrc_idle_after_reset_x32 = 0x12 */
- /* .. .. ==> 0XF80062B0[11:4] = 0x00000012U */
- /* .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U */
- /* .. .. reg_ddrc_t_mrw = 0x5 */
- /* .. .. ==> 0XF80062B0[21:12] = 0x00000005U */
- /* .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU, 0x00005125U),
- /* .. .. reg_ddrc_max_auto_init_x1024 = 0xa6 */
- /* .. .. ==> 0XF80062B4[7:0] = 0x000000A6U */
- /* .. .. ==> MASK : 0x000000FFU VAL : 0x000000A6U */
- /* .. .. reg_ddrc_dev_zqinit_x32 = 0x12 */
- /* .. .. ==> 0XF80062B4[17:8] = 0x00000012U */
- /* .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U */
- /* .. .. */
- EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU, 0x000012A6U),
- /* .. .. START: POLL ON DCI STATUS */
- /* .. .. DONE = 1 */
- /* .. .. ==> 0XF8000B74[13:13] = 0x00000001U */
- /* .. .. ==> MASK : 0x00002000U VAL : 0x00002000U */
- /* .. .. */
- EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
- /* .. .. FINISH: POLL ON DCI STATUS */
- /* .. .. START: UNLOCK DDR */
- /* .. .. reg_ddrc_soft_rstb = 0x1 */
- /* .. .. ==> 0XF8006000[0:0] = 0x00000001U */
- /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
- /* .. .. reg_ddrc_powerdown_en = 0x0 */
- /* .. .. ==> 0XF8006000[1:1] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. .. reg_ddrc_data_bus_width = 0x0 */
- /* .. .. ==> 0XF8006000[3:2] = 0x00000000U */
- /* .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U */
- /* .. .. reg_ddrc_burst8_refresh = 0x0 */
- /* .. .. ==> 0XF8006000[6:4] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000070U VAL : 0x00000000U */
- /* .. .. reg_ddrc_rdwr_idle_gap = 1 */
- /* .. .. ==> 0XF8006000[13:7] = 0x00000001U */
- /* .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U */
- /* .. .. reg_ddrc_dis_rd_bypass = 0x0 */
- /* .. .. ==> 0XF8006000[14:14] = 0x00000000U */
- /* .. .. ==> MASK : 0x00004000U VAL : 0x00000000U */
- /* .. .. reg_ddrc_dis_act_bypass = 0x0 */
- /* .. .. ==> 0XF8006000[15:15] = 0x00000000U */
- /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */
- /* .. .. reg_ddrc_dis_auto_refresh = 0x0 */
- /* .. .. ==> 0XF8006000[16:16] = 0x00000000U */
- /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000081U),
- /* .. .. FINISH: UNLOCK DDR */
- /* .. .. START: CHECK DDR STATUS */
- /* .. .. ddrc_reg_operating_mode = 1 */
- /* .. .. ==> 0XF8006054[2:0] = 0x00000001U */
- /* .. .. ==> MASK : 0x00000007U VAL : 0x00000001U */
- /* .. .. */
- EMIT_MASKPOLL(0XF8006054, 0x00000007U),
- /* .. .. FINISH: CHECK DDR STATUS */
- /* .. FINISH: DDR INITIALIZATION */
- /* FINISH: top */
- /* */
- EMIT_EXIT(),
-
- /* */
-};
-
-unsigned long ps7_mio_init_data_3_0[] = {
- /* START: top */
- /* .. START: SLCR SETTINGS */
- /* .. UNLOCK_KEY = 0XDF0D */
- /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
- /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */
- /* .. */
- EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
- /* .. FINISH: SLCR SETTINGS */
- /* .. START: OCM REMAPPING */
- /* .. VREF_EN = 0x1 */
- /* .. ==> 0XF8000B00[0:0] = 0x00000001U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
- /* .. VREF_SEL = 0x0 */
- /* .. ==> 0XF8000B00[6:4] = 0x00000000U */
- /* .. ==> MASK : 0x00000070U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000B00, 0x00000071U, 0x00000001U),
- /* .. FINISH: OCM REMAPPING */
- /* .. START: DDRIOB SETTINGS */
- /* .. reserved_INP_POWER = 0x0 */
- /* .. ==> 0XF8000B40[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. INP_TYPE = 0x0 */
- /* .. ==> 0XF8000B40[2:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */
- /* .. DCI_UPDATE_B = 0x0 */
- /* .. ==> 0XF8000B40[3:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
- /* .. TERM_EN = 0x0 */
- /* .. ==> 0XF8000B40[4:4] = 0x00000000U */
- /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */
- /* .. DCI_TYPE = 0x0 */
- /* .. ==> 0XF8000B40[6:5] = 0x00000000U */
- /* .. ==> MASK : 0x00000060U VAL : 0x00000000U */
- /* .. IBUF_DISABLE_MODE = 0x0 */
- /* .. ==> 0XF8000B40[7:7] = 0x00000000U */
- /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
- /* .. TERM_DISABLE_MODE = 0x0 */
- /* .. ==> 0XF8000B40[8:8] = 0x00000000U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
- /* .. OUTPUT_EN = 0x3 */
- /* .. ==> 0XF8000B40[10:9] = 0x00000003U */
- /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
- /* .. PULLUP_EN = 0x0 */
- /* .. ==> 0XF8000B40[11:11] = 0x00000000U */
- /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU, 0x00000600U),
- /* .. reserved_INP_POWER = 0x0 */
- /* .. ==> 0XF8000B44[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. INP_TYPE = 0x0 */
- /* .. ==> 0XF8000B44[2:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */
- /* .. DCI_UPDATE_B = 0x0 */
- /* .. ==> 0XF8000B44[3:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
- /* .. TERM_EN = 0x0 */
- /* .. ==> 0XF8000B44[4:4] = 0x00000000U */
- /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */
- /* .. DCI_TYPE = 0x0 */
- /* .. ==> 0XF8000B44[6:5] = 0x00000000U */
- /* .. ==> MASK : 0x00000060U VAL : 0x00000000U */
- /* .. IBUF_DISABLE_MODE = 0x0 */
- /* .. ==> 0XF8000B44[7:7] = 0x00000000U */
- /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
- /* .. TERM_DISABLE_MODE = 0x0 */
- /* .. ==> 0XF8000B44[8:8] = 0x00000000U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
- /* .. OUTPUT_EN = 0x3 */
- /* .. ==> 0XF8000B44[10:9] = 0x00000003U */
- /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
- /* .. PULLUP_EN = 0x0 */
- /* .. ==> 0XF8000B44[11:11] = 0x00000000U */
- /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU, 0x00000600U),
- /* .. reserved_INP_POWER = 0x0 */
- /* .. ==> 0XF8000B48[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. INP_TYPE = 0x1 */
- /* .. ==> 0XF8000B48[2:1] = 0x00000001U */
- /* .. ==> MASK : 0x00000006U VAL : 0x00000002U */
- /* .. DCI_UPDATE_B = 0x0 */
- /* .. ==> 0XF8000B48[3:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
- /* .. TERM_EN = 0x1 */
- /* .. ==> 0XF8000B48[4:4] = 0x00000001U */
- /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */
- /* .. DCI_TYPE = 0x3 */
- /* .. ==> 0XF8000B48[6:5] = 0x00000003U */
- /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */
- /* .. IBUF_DISABLE_MODE = 0 */
- /* .. ==> 0XF8000B48[7:7] = 0x00000000U */
- /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
- /* .. TERM_DISABLE_MODE = 0 */
- /* .. ==> 0XF8000B48[8:8] = 0x00000000U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
- /* .. OUTPUT_EN = 0x3 */
- /* .. ==> 0XF8000B48[10:9] = 0x00000003U */
- /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
- /* .. PULLUP_EN = 0x0 */
- /* .. ==> 0XF8000B48[11:11] = 0x00000000U */
- /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU, 0x00000672U),
- /* .. reserved_INP_POWER = 0x0 */
- /* .. ==> 0XF8000B4C[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. INP_TYPE = 0x1 */
- /* .. ==> 0XF8000B4C[2:1] = 0x00000001U */
- /* .. ==> MASK : 0x00000006U VAL : 0x00000002U */
- /* .. DCI_UPDATE_B = 0x0 */
- /* .. ==> 0XF8000B4C[3:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
- /* .. TERM_EN = 0x1 */
- /* .. ==> 0XF8000B4C[4:4] = 0x00000001U */
- /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */
- /* .. DCI_TYPE = 0x3 */
- /* .. ==> 0XF8000B4C[6:5] = 0x00000003U */
- /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */
- /* .. IBUF_DISABLE_MODE = 0 */
- /* .. ==> 0XF8000B4C[7:7] = 0x00000000U */
- /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
- /* .. TERM_DISABLE_MODE = 0 */
- /* .. ==> 0XF8000B4C[8:8] = 0x00000000U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
- /* .. OUTPUT_EN = 0x3 */
- /* .. ==> 0XF8000B4C[10:9] = 0x00000003U */
- /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
- /* .. PULLUP_EN = 0x0 */
- /* .. ==> 0XF8000B4C[11:11] = 0x00000000U */
- /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU, 0x00000672U),
- /* .. reserved_INP_POWER = 0x0 */
- /* .. ==> 0XF8000B50[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. INP_TYPE = 0x2 */
- /* .. ==> 0XF8000B50[2:1] = 0x00000002U */
- /* .. ==> MASK : 0x00000006U VAL : 0x00000004U */
- /* .. DCI_UPDATE_B = 0x0 */
- /* .. ==> 0XF8000B50[3:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
- /* .. TERM_EN = 0x1 */
- /* .. ==> 0XF8000B50[4:4] = 0x00000001U */
- /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */
- /* .. DCI_TYPE = 0x3 */
- /* .. ==> 0XF8000B50[6:5] = 0x00000003U */
- /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */
- /* .. IBUF_DISABLE_MODE = 0 */
- /* .. ==> 0XF8000B50[7:7] = 0x00000000U */
- /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
- /* .. TERM_DISABLE_MODE = 0 */
- /* .. ==> 0XF8000B50[8:8] = 0x00000000U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
- /* .. OUTPUT_EN = 0x3 */
- /* .. ==> 0XF8000B50[10:9] = 0x00000003U */
- /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
- /* .. PULLUP_EN = 0x0 */
- /* .. ==> 0XF8000B50[11:11] = 0x00000000U */
- /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU, 0x00000674U),
- /* .. reserved_INP_POWER = 0x0 */
- /* .. ==> 0XF8000B54[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. INP_TYPE = 0x2 */
- /* .. ==> 0XF8000B54[2:1] = 0x00000002U */
- /* .. ==> MASK : 0x00000006U VAL : 0x00000004U */
- /* .. DCI_UPDATE_B = 0x0 */
- /* .. ==> 0XF8000B54[3:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
- /* .. TERM_EN = 0x1 */
- /* .. ==> 0XF8000B54[4:4] = 0x00000001U */
- /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */
- /* .. DCI_TYPE = 0x3 */
- /* .. ==> 0XF8000B54[6:5] = 0x00000003U */
- /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */
- /* .. IBUF_DISABLE_MODE = 0 */
- /* .. ==> 0XF8000B54[7:7] = 0x00000000U */
- /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
- /* .. TERM_DISABLE_MODE = 0 */
- /* .. ==> 0XF8000B54[8:8] = 0x00000000U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
- /* .. OUTPUT_EN = 0x3 */
- /* .. ==> 0XF8000B54[10:9] = 0x00000003U */
- /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
- /* .. PULLUP_EN = 0x0 */
- /* .. ==> 0XF8000B54[11:11] = 0x00000000U */
- /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU, 0x00000674U),
- /* .. reserved_INP_POWER = 0x0 */
- /* .. ==> 0XF8000B58[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. INP_TYPE = 0x0 */
- /* .. ==> 0XF8000B58[2:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */
- /* .. DCI_UPDATE_B = 0x0 */
- /* .. ==> 0XF8000B58[3:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
- /* .. TERM_EN = 0x0 */
- /* .. ==> 0XF8000B58[4:4] = 0x00000000U */
- /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */
- /* .. DCI_TYPE = 0x0 */
- /* .. ==> 0XF8000B58[6:5] = 0x00000000U */
- /* .. ==> MASK : 0x00000060U VAL : 0x00000000U */
- /* .. IBUF_DISABLE_MODE = 0x0 */
- /* .. ==> 0XF8000B58[7:7] = 0x00000000U */
- /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
- /* .. TERM_DISABLE_MODE = 0x0 */
- /* .. ==> 0XF8000B58[8:8] = 0x00000000U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
- /* .. OUTPUT_EN = 0x3 */
- /* .. ==> 0XF8000B58[10:9] = 0x00000003U */
- /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
- /* .. PULLUP_EN = 0x0 */
- /* .. ==> 0XF8000B58[11:11] = 0x00000000U */
- /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU, 0x00000600U),
- /* .. reserved_DRIVE_P = 0x1c */
- /* .. ==> 0XF8000B5C[6:0] = 0x0000001CU */
- /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */
- /* .. reserved_DRIVE_N = 0xc */
- /* .. ==> 0XF8000B5C[13:7] = 0x0000000CU */
- /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */
- /* .. reserved_SLEW_P = 0x3 */
- /* .. ==> 0XF8000B5C[18:14] = 0x00000003U */
- /* .. ==> MASK : 0x0007C000U VAL : 0x0000C000U */
- /* .. reserved_SLEW_N = 0x3 */
- /* .. ==> 0XF8000B5C[23:19] = 0x00000003U */
- /* .. ==> MASK : 0x00F80000U VAL : 0x00180000U */
- /* .. reserved_GTL = 0x0 */
- /* .. ==> 0XF8000B5C[26:24] = 0x00000000U */
- /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */
- /* .. reserved_RTERM = 0x0 */
- /* .. ==> 0XF8000B5C[31:27] = 0x00000000U */
- /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU, 0x0018C61CU),
- /* .. reserved_DRIVE_P = 0x1c */
- /* .. ==> 0XF8000B60[6:0] = 0x0000001CU */
- /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */
- /* .. reserved_DRIVE_N = 0xc */
- /* .. ==> 0XF8000B60[13:7] = 0x0000000CU */
- /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */
- /* .. reserved_SLEW_P = 0x6 */
- /* .. ==> 0XF8000B60[18:14] = 0x00000006U */
- /* .. ==> MASK : 0x0007C000U VAL : 0x00018000U */
- /* .. reserved_SLEW_N = 0x1f */
- /* .. ==> 0XF8000B60[23:19] = 0x0000001FU */
- /* .. ==> MASK : 0x00F80000U VAL : 0x00F80000U */
- /* .. reserved_GTL = 0x0 */
- /* .. ==> 0XF8000B60[26:24] = 0x00000000U */
- /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */
- /* .. reserved_RTERM = 0x0 */
- /* .. ==> 0XF8000B60[31:27] = 0x00000000U */
- /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU, 0x00F9861CU),
- /* .. reserved_DRIVE_P = 0x1c */
- /* .. ==> 0XF8000B64[6:0] = 0x0000001CU */
- /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */
- /* .. reserved_DRIVE_N = 0xc */
- /* .. ==> 0XF8000B64[13:7] = 0x0000000CU */
- /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */
- /* .. reserved_SLEW_P = 0x6 */
- /* .. ==> 0XF8000B64[18:14] = 0x00000006U */
- /* .. ==> MASK : 0x0007C000U VAL : 0x00018000U */
- /* .. reserved_SLEW_N = 0x1f */
- /* .. ==> 0XF8000B64[23:19] = 0x0000001FU */
- /* .. ==> MASK : 0x00F80000U VAL : 0x00F80000U */
- /* .. reserved_GTL = 0x0 */
- /* .. ==> 0XF8000B64[26:24] = 0x00000000U */
- /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */
- /* .. reserved_RTERM = 0x0 */
- /* .. ==> 0XF8000B64[31:27] = 0x00000000U */
- /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU, 0x00F9861CU),
- /* .. reserved_DRIVE_P = 0x1c */
- /* .. ==> 0XF8000B68[6:0] = 0x0000001CU */
- /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */
- /* .. reserved_DRIVE_N = 0xc */
- /* .. ==> 0XF8000B68[13:7] = 0x0000000CU */
- /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */
- /* .. reserved_SLEW_P = 0x6 */
- /* .. ==> 0XF8000B68[18:14] = 0x00000006U */
- /* .. ==> MASK : 0x0007C000U VAL : 0x00018000U */
- /* .. reserved_SLEW_N = 0x1f */
- /* .. ==> 0XF8000B68[23:19] = 0x0000001FU */
- /* .. ==> MASK : 0x00F80000U VAL : 0x00F80000U */
- /* .. reserved_GTL = 0x0 */
- /* .. ==> 0XF8000B68[26:24] = 0x00000000U */
- /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */
- /* .. reserved_RTERM = 0x0 */
- /* .. ==> 0XF8000B68[31:27] = 0x00000000U */
- /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU, 0x00F9861CU),
- /* .. VREF_INT_EN = 0x0 */
- /* .. ==> 0XF8000B6C[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. VREF_SEL = 0x0 */
- /* .. ==> 0XF8000B6C[4:1] = 0x00000000U */
- /* .. ==> MASK : 0x0000001EU VAL : 0x00000000U */
- /* .. VREF_EXT_EN = 0x3 */
- /* .. ==> 0XF8000B6C[6:5] = 0x00000003U */
- /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */
- /* .. reserved_VREF_PULLUP_EN = 0x0 */
- /* .. ==> 0XF8000B6C[8:7] = 0x00000000U */
- /* .. ==> MASK : 0x00000180U VAL : 0x00000000U */
- /* .. REFIO_EN = 0x1 */
- /* .. ==> 0XF8000B6C[9:9] = 0x00000001U */
- /* .. ==> MASK : 0x00000200U VAL : 0x00000200U */
- /* .. reserved_REFIO_TEST = 0x0 */
- /* .. ==> 0XF8000B6C[11:10] = 0x00000000U */
- /* .. ==> MASK : 0x00000C00U VAL : 0x00000000U */
- /* .. reserved_REFIO_PULLUP_EN = 0x0 */
- /* .. ==> 0XF8000B6C[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. reserved_DRST_B_PULLUP_EN = 0x0 */
- /* .. ==> 0XF8000B6C[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. reserved_CKE_PULLUP_EN = 0x0 */
- /* .. ==> 0XF8000B6C[14:14] = 0x00000000U */
- /* .. ==> MASK : 0x00004000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU, 0x00000260U),
- /* .. .. START: ASSERT RESET */
- /* .. .. RESET = 1 */
- /* .. .. ==> 0XF8000B70[0:0] = 0x00000001U */
- /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8000B70, 0x00000001U, 0x00000001U),
- /* .. .. FINISH: ASSERT RESET */
- /* .. .. START: DEASSERT RESET */
- /* .. .. RESET = 0 */
- /* .. .. ==> 0XF8000B70[0:0] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. .. reserved_VRN_OUT = 0x1 */
- /* .. .. ==> 0XF8000B70[5:5] = 0x00000001U */
- /* .. .. ==> MASK : 0x00000020U VAL : 0x00000020U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000020U),
- /* .. .. FINISH: DEASSERT RESET */
- /* .. .. RESET = 0x1 */
- /* .. .. ==> 0XF8000B70[0:0] = 0x00000001U */
- /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
- /* .. .. ENABLE = 0x1 */
- /* .. .. ==> 0XF8000B70[1:1] = 0x00000001U */
- /* .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */
- /* .. .. reserved_VRP_TRI = 0x0 */
- /* .. .. ==> 0XF8000B70[2:2] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. .. reserved_VRN_TRI = 0x0 */
- /* .. .. ==> 0XF8000B70[3:3] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */
- /* .. .. reserved_VRP_OUT = 0x0 */
- /* .. .. ==> 0XF8000B70[4:4] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
- /* .. .. reserved_VRN_OUT = 0x1 */
- /* .. .. ==> 0XF8000B70[5:5] = 0x00000001U */
- /* .. .. ==> MASK : 0x00000020U VAL : 0x00000020U */
- /* .. .. NREF_OPT1 = 0x0 */
- /* .. .. ==> 0XF8000B70[7:6] = 0x00000000U */
- /* .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U */
- /* .. .. NREF_OPT2 = 0x0 */
- /* .. .. ==> 0XF8000B70[10:8] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000700U VAL : 0x00000000U */
- /* .. .. NREF_OPT4 = 0x1 */
- /* .. .. ==> 0XF8000B70[13:11] = 0x00000001U */
- /* .. .. ==> MASK : 0x00003800U VAL : 0x00000800U */
- /* .. .. PREF_OPT1 = 0x0 */
- /* .. .. ==> 0XF8000B70[15:14] = 0x00000000U */
- /* .. .. ==> MASK : 0x0000C000U VAL : 0x00000000U */
- /* .. .. PREF_OPT2 = 0x0 */
- /* .. .. ==> 0XF8000B70[19:17] = 0x00000000U */
- /* .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U */
- /* .. .. UPDATE_CONTROL = 0x0 */
- /* .. .. ==> 0XF8000B70[20:20] = 0x00000000U */
- /* .. .. ==> MASK : 0x00100000U VAL : 0x00000000U */
- /* .. .. reserved_INIT_COMPLETE = 0x0 */
- /* .. .. ==> 0XF8000B70[21:21] = 0x00000000U */
- /* .. .. ==> MASK : 0x00200000U VAL : 0x00000000U */
- /* .. .. reserved_TST_CLK = 0x0 */
- /* .. .. ==> 0XF8000B70[22:22] = 0x00000000U */
- /* .. .. ==> MASK : 0x00400000U VAL : 0x00000000U */
- /* .. .. reserved_TST_HLN = 0x0 */
- /* .. .. ==> 0XF8000B70[23:23] = 0x00000000U */
- /* .. .. ==> MASK : 0x00800000U VAL : 0x00000000U */
- /* .. .. reserved_TST_HLP = 0x0 */
- /* .. .. ==> 0XF8000B70[24:24] = 0x00000000U */
- /* .. .. ==> MASK : 0x01000000U VAL : 0x00000000U */
- /* .. .. reserved_TST_RST = 0x0 */
- /* .. .. ==> 0XF8000B70[25:25] = 0x00000000U */
- /* .. .. ==> MASK : 0x02000000U VAL : 0x00000000U */
- /* .. .. reserved_INT_DCI_EN = 0x0 */
- /* .. .. ==> 0XF8000B70[26:26] = 0x00000000U */
- /* .. .. ==> MASK : 0x04000000U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU, 0x00000823U),
- /* .. FINISH: DDRIOB SETTINGS */
- /* .. START: MIO PROGRAMMING */
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF8000700[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 0 */
- /* .. ==> 0XF8000700[1:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF8000700[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF8000700[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF8000700[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 0 */
- /* .. ==> 0XF8000700[8:8] = 0x00000000U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
- /* .. IO_Type = 3 */
- /* .. ==> 0XF8000700[11:9] = 0x00000003U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
- /* .. PULLUP = 1 */
- /* .. ==> 0XF8000700[12:12] = 0x00000001U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF8000700[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000700, 0x00003FFFU, 0x00001600U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF8000704[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 1 */
- /* .. ==> 0XF8000704[1:1] = 0x00000001U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF8000704[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF8000704[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF8000704[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 1 */
- /* .. ==> 0XF8000704[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. IO_Type = 3 */
- /* .. ==> 0XF8000704[11:9] = 0x00000003U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF8000704[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF8000704[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000704, 0x00003FFFU, 0x00000702U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF8000708[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 1 */
- /* .. ==> 0XF8000708[1:1] = 0x00000001U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF8000708[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF8000708[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF8000708[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 1 */
- /* .. ==> 0XF8000708[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. IO_Type = 3 */
- /* .. ==> 0XF8000708[11:9] = 0x00000003U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF8000708[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF8000708[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000708, 0x00003FFFU, 0x00000702U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF800070C[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 1 */
- /* .. ==> 0XF800070C[1:1] = 0x00000001U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF800070C[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF800070C[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF800070C[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 1 */
- /* .. ==> 0XF800070C[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. IO_Type = 3 */
- /* .. ==> 0XF800070C[11:9] = 0x00000003U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF800070C[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF800070C[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF800070C, 0x00003FFFU, 0x00000702U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF8000710[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 1 */
- /* .. ==> 0XF8000710[1:1] = 0x00000001U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF8000710[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF8000710[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF8000710[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 1 */
- /* .. ==> 0XF8000710[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. IO_Type = 3 */
- /* .. ==> 0XF8000710[11:9] = 0x00000003U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF8000710[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF8000710[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000710, 0x00003FFFU, 0x00000702U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF8000714[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 1 */
- /* .. ==> 0XF8000714[1:1] = 0x00000001U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF8000714[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF8000714[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF8000714[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 1 */
- /* .. ==> 0XF8000714[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. IO_Type = 3 */
- /* .. ==> 0XF8000714[11:9] = 0x00000003U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF8000714[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF8000714[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000714, 0x00003FFFU, 0x00000702U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF8000718[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 1 */
- /* .. ==> 0XF8000718[1:1] = 0x00000001U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF8000718[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF8000718[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF8000718[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 1 */
- /* .. ==> 0XF8000718[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. IO_Type = 3 */
- /* .. ==> 0XF8000718[11:9] = 0x00000003U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF8000718[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF8000718[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000702U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF800071C[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 0 */
- /* .. ==> 0XF800071C[1:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF800071C[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF800071C[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF800071C[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 0 */
- /* .. ==> 0XF800071C[8:8] = 0x00000000U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
- /* .. IO_Type = 3 */
- /* .. ==> 0XF800071C[11:9] = 0x00000003U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF800071C[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF800071C[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF800071C, 0x00003FFFU, 0x00000600U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF8000720[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 1 */
- /* .. ==> 0XF8000720[1:1] = 0x00000001U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF8000720[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF8000720[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF8000720[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 1 */
- /* .. ==> 0XF8000720[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. IO_Type = 3 */
- /* .. ==> 0XF8000720[11:9] = 0x00000003U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF8000720[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF8000720[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000720, 0x00003FFFU, 0x00000702U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF8000724[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 0 */
- /* .. ==> 0XF8000724[1:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF8000724[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF8000724[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF8000724[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 0 */
- /* .. ==> 0XF8000724[8:8] = 0x00000000U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
- /* .. IO_Type = 3 */
- /* .. ==> 0XF8000724[11:9] = 0x00000003U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
- /* .. PULLUP = 1 */
- /* .. ==> 0XF8000724[12:12] = 0x00000001U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF8000724[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000724, 0x00003FFFU, 0x00001600U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF8000728[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 0 */
- /* .. ==> 0XF8000728[1:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF8000728[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF8000728[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF8000728[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 0 */
- /* .. ==> 0XF8000728[8:8] = 0x00000000U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
- /* .. IO_Type = 3 */
- /* .. ==> 0XF8000728[11:9] = 0x00000003U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
- /* .. PULLUP = 1 */
- /* .. ==> 0XF8000728[12:12] = 0x00000001U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF8000728[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000728, 0x00003FFFU, 0x00001600U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF800072C[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 0 */
- /* .. ==> 0XF800072C[1:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF800072C[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF800072C[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF800072C[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 0 */
- /* .. ==> 0XF800072C[8:8] = 0x00000000U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
- /* .. IO_Type = 3 */
- /* .. ==> 0XF800072C[11:9] = 0x00000003U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
- /* .. PULLUP = 1 */
- /* .. ==> 0XF800072C[12:12] = 0x00000001U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF800072C[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF800072C, 0x00003FFFU, 0x00001600U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF8000730[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 0 */
- /* .. ==> 0XF8000730[1:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF8000730[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF8000730[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF8000730[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 0 */
- /* .. ==> 0XF8000730[8:8] = 0x00000000U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
- /* .. IO_Type = 3 */
- /* .. ==> 0XF8000730[11:9] = 0x00000003U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
- /* .. PULLUP = 1 */
- /* .. ==> 0XF8000730[12:12] = 0x00000001U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF8000730[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000730, 0x00003FFFU, 0x00001600U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF8000734[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 0 */
- /* .. ==> 0XF8000734[1:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF8000734[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF8000734[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF8000734[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 0 */
- /* .. ==> 0XF8000734[8:8] = 0x00000000U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
- /* .. IO_Type = 3 */
- /* .. ==> 0XF8000734[11:9] = 0x00000003U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
- /* .. PULLUP = 1 */
- /* .. ==> 0XF8000734[12:12] = 0x00000001U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF8000734[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000734, 0x00003FFFU, 0x00001600U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF8000738[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 0 */
- /* .. ==> 0XF8000738[1:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF8000738[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF8000738[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF8000738[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 0 */
- /* .. ==> 0XF8000738[8:8] = 0x00000000U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
- /* .. IO_Type = 3 */
- /* .. ==> 0XF8000738[11:9] = 0x00000003U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
- /* .. PULLUP = 1 */
- /* .. ==> 0XF8000738[12:12] = 0x00000001U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF8000738[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000738, 0x00003FFFU, 0x00001600U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF800073C[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 0 */
- /* .. ==> 0XF800073C[1:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF800073C[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF800073C[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF800073C[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 0 */
- /* .. ==> 0XF800073C[8:8] = 0x00000000U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
- /* .. IO_Type = 3 */
- /* .. ==> 0XF800073C[11:9] = 0x00000003U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
- /* .. PULLUP = 1 */
- /* .. ==> 0XF800073C[12:12] = 0x00000001U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF800073C[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF800073C, 0x00003FFFU, 0x00001600U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF8000740[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 1 */
- /* .. ==> 0XF8000740[1:1] = 0x00000001U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF8000740[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF8000740[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF8000740[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 1 */
- /* .. ==> 0XF8000740[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. IO_Type = 4 */
- /* .. ==> 0XF8000740[11:9] = 0x00000004U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF8000740[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 1 */
- /* .. ==> 0XF8000740[13:13] = 0x00000001U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000740, 0x00003FFFU, 0x00002902U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF8000744[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 1 */
- /* .. ==> 0XF8000744[1:1] = 0x00000001U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF8000744[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF8000744[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF8000744[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 1 */
- /* .. ==> 0XF8000744[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. IO_Type = 4 */
- /* .. ==> 0XF8000744[11:9] = 0x00000004U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF8000744[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 1 */
- /* .. ==> 0XF8000744[13:13] = 0x00000001U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000744, 0x00003FFFU, 0x00002902U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF8000748[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 1 */
- /* .. ==> 0XF8000748[1:1] = 0x00000001U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF8000748[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF8000748[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF8000748[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 1 */
- /* .. ==> 0XF8000748[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. IO_Type = 4 */
- /* .. ==> 0XF8000748[11:9] = 0x00000004U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF8000748[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 1 */
- /* .. ==> 0XF8000748[13:13] = 0x00000001U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000748, 0x00003FFFU, 0x00002902U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF800074C[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 1 */
- /* .. ==> 0XF800074C[1:1] = 0x00000001U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF800074C[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF800074C[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF800074C[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 1 */
- /* .. ==> 0XF800074C[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. IO_Type = 4 */
- /* .. ==> 0XF800074C[11:9] = 0x00000004U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF800074C[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 1 */
- /* .. ==> 0XF800074C[13:13] = 0x00000001U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */
- /* .. */
- EMIT_MASKWRITE(0XF800074C, 0x00003FFFU, 0x00002902U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF8000750[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 1 */
- /* .. ==> 0XF8000750[1:1] = 0x00000001U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF8000750[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF8000750[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF8000750[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 1 */
- /* .. ==> 0XF8000750[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. IO_Type = 4 */
- /* .. ==> 0XF8000750[11:9] = 0x00000004U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF8000750[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 1 */
- /* .. ==> 0XF8000750[13:13] = 0x00000001U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000750, 0x00003FFFU, 0x00002902U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF8000754[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 1 */
- /* .. ==> 0XF8000754[1:1] = 0x00000001U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF8000754[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF8000754[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF8000754[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 1 */
- /* .. ==> 0XF8000754[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. IO_Type = 4 */
- /* .. ==> 0XF8000754[11:9] = 0x00000004U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF8000754[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 1 */
- /* .. ==> 0XF8000754[13:13] = 0x00000001U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000754, 0x00003FFFU, 0x00002902U),
- /* .. TRI_ENABLE = 1 */
- /* .. ==> 0XF8000758[0:0] = 0x00000001U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
- /* .. L0_SEL = 1 */
- /* .. ==> 0XF8000758[1:1] = 0x00000001U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF8000758[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF8000758[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF8000758[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 1 */
- /* .. ==> 0XF8000758[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. IO_Type = 4 */
- /* .. ==> 0XF8000758[11:9] = 0x00000004U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF8000758[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF8000758[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000758, 0x00003FFFU, 0x00000903U),
- /* .. TRI_ENABLE = 1 */
- /* .. ==> 0XF800075C[0:0] = 0x00000001U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
- /* .. L0_SEL = 1 */
- /* .. ==> 0XF800075C[1:1] = 0x00000001U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF800075C[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF800075C[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF800075C[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 1 */
- /* .. ==> 0XF800075C[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. IO_Type = 4 */
- /* .. ==> 0XF800075C[11:9] = 0x00000004U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF800075C[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF800075C[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF800075C, 0x00003FFFU, 0x00000903U),
- /* .. TRI_ENABLE = 1 */
- /* .. ==> 0XF8000760[0:0] = 0x00000001U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
- /* .. L0_SEL = 1 */
- /* .. ==> 0XF8000760[1:1] = 0x00000001U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF8000760[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF8000760[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF8000760[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 1 */
- /* .. ==> 0XF8000760[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. IO_Type = 4 */
- /* .. ==> 0XF8000760[11:9] = 0x00000004U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF8000760[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF8000760[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000760, 0x00003FFFU, 0x00000903U),
- /* .. TRI_ENABLE = 1 */
- /* .. ==> 0XF8000764[0:0] = 0x00000001U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
- /* .. L0_SEL = 1 */
- /* .. ==> 0XF8000764[1:1] = 0x00000001U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF8000764[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF8000764[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF8000764[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 1 */
- /* .. ==> 0XF8000764[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. IO_Type = 4 */
- /* .. ==> 0XF8000764[11:9] = 0x00000004U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF8000764[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF8000764[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000764, 0x00003FFFU, 0x00000903U),
- /* .. TRI_ENABLE = 1 */
- /* .. ==> 0XF8000768[0:0] = 0x00000001U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
- /* .. L0_SEL = 1 */
- /* .. ==> 0XF8000768[1:1] = 0x00000001U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF8000768[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF8000768[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF8000768[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 1 */
- /* .. ==> 0XF8000768[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. IO_Type = 4 */
- /* .. ==> 0XF8000768[11:9] = 0x00000004U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF8000768[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF8000768[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000768, 0x00003FFFU, 0x00000903U),
- /* .. TRI_ENABLE = 1 */
- /* .. ==> 0XF800076C[0:0] = 0x00000001U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
- /* .. L0_SEL = 1 */
- /* .. ==> 0XF800076C[1:1] = 0x00000001U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF800076C[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF800076C[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF800076C[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 1 */
- /* .. ==> 0XF800076C[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. IO_Type = 4 */
- /* .. ==> 0XF800076C[11:9] = 0x00000004U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF800076C[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF800076C[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF800076C, 0x00003FFFU, 0x00000903U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF8000770[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 0 */
- /* .. ==> 0XF8000770[1:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. L1_SEL = 1 */
- /* .. ==> 0XF8000770[2:2] = 0x00000001U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF8000770[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF8000770[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 1 */
- /* .. ==> 0XF8000770[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. IO_Type = 1 */
- /* .. ==> 0XF8000770[11:9] = 0x00000001U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF8000770[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF8000770[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000770, 0x00003FFFU, 0x00000304U),
- /* .. TRI_ENABLE = 1 */
- /* .. ==> 0XF8000774[0:0] = 0x00000001U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
- /* .. L0_SEL = 0 */
- /* .. ==> 0XF8000774[1:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. L1_SEL = 1 */
- /* .. ==> 0XF8000774[2:2] = 0x00000001U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF8000774[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF8000774[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 1 */
- /* .. ==> 0XF8000774[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. IO_Type = 1 */
- /* .. ==> 0XF8000774[11:9] = 0x00000001U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF8000774[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF8000774[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000774, 0x00003FFFU, 0x00000305U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF8000778[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 0 */
- /* .. ==> 0XF8000778[1:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. L1_SEL = 1 */
- /* .. ==> 0XF8000778[2:2] = 0x00000001U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF8000778[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF8000778[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 1 */
- /* .. ==> 0XF8000778[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. IO_Type = 1 */
- /* .. ==> 0XF8000778[11:9] = 0x00000001U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF8000778[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF8000778[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000778, 0x00003FFFU, 0x00000304U),
- /* .. TRI_ENABLE = 1 */
- /* .. ==> 0XF800077C[0:0] = 0x00000001U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
- /* .. L0_SEL = 0 */
- /* .. ==> 0XF800077C[1:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. L1_SEL = 1 */
- /* .. ==> 0XF800077C[2:2] = 0x00000001U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF800077C[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF800077C[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 1 */
- /* .. ==> 0XF800077C[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. IO_Type = 1 */
- /* .. ==> 0XF800077C[11:9] = 0x00000001U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF800077C[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF800077C[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF800077C, 0x00003FFFU, 0x00000305U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF8000780[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 0 */
- /* .. ==> 0XF8000780[1:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. L1_SEL = 1 */
- /* .. ==> 0XF8000780[2:2] = 0x00000001U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF8000780[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF8000780[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 1 */
- /* .. ==> 0XF8000780[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. IO_Type = 1 */
- /* .. ==> 0XF8000780[11:9] = 0x00000001U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF8000780[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF8000780[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000780, 0x00003FFFU, 0x00000304U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF8000784[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 0 */
- /* .. ==> 0XF8000784[1:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. L1_SEL = 1 */
- /* .. ==> 0XF8000784[2:2] = 0x00000001U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF8000784[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF8000784[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 1 */
- /* .. ==> 0XF8000784[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. IO_Type = 1 */
- /* .. ==> 0XF8000784[11:9] = 0x00000001U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF8000784[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF8000784[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000784, 0x00003FFFU, 0x00000304U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF8000788[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 0 */
- /* .. ==> 0XF8000788[1:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. L1_SEL = 1 */
- /* .. ==> 0XF8000788[2:2] = 0x00000001U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF8000788[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF8000788[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 1 */
- /* .. ==> 0XF8000788[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. IO_Type = 1 */
- /* .. ==> 0XF8000788[11:9] = 0x00000001U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF8000788[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF8000788[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000788, 0x00003FFFU, 0x00000304U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF800078C[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 0 */
- /* .. ==> 0XF800078C[1:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. L1_SEL = 1 */
- /* .. ==> 0XF800078C[2:2] = 0x00000001U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF800078C[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF800078C[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 1 */
- /* .. ==> 0XF800078C[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. IO_Type = 1 */
- /* .. ==> 0XF800078C[11:9] = 0x00000001U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF800078C[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF800078C[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF800078C, 0x00003FFFU, 0x00000304U),
- /* .. TRI_ENABLE = 1 */
- /* .. ==> 0XF8000790[0:0] = 0x00000001U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
- /* .. L0_SEL = 0 */
- /* .. ==> 0XF8000790[1:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. L1_SEL = 1 */
- /* .. ==> 0XF8000790[2:2] = 0x00000001U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF8000790[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF8000790[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 1 */
- /* .. ==> 0XF8000790[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. IO_Type = 1 */
- /* .. ==> 0XF8000790[11:9] = 0x00000001U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF8000790[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF8000790[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000790, 0x00003FFFU, 0x00000305U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF8000794[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 0 */
- /* .. ==> 0XF8000794[1:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. L1_SEL = 1 */
- /* .. ==> 0XF8000794[2:2] = 0x00000001U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF8000794[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF8000794[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 1 */
- /* .. ==> 0XF8000794[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. IO_Type = 1 */
- /* .. ==> 0XF8000794[11:9] = 0x00000001U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF8000794[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF8000794[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000794, 0x00003FFFU, 0x00000304U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF8000798[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 0 */
- /* .. ==> 0XF8000798[1:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. L1_SEL = 1 */
- /* .. ==> 0XF8000798[2:2] = 0x00000001U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF8000798[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF8000798[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 1 */
- /* .. ==> 0XF8000798[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. IO_Type = 1 */
- /* .. ==> 0XF8000798[11:9] = 0x00000001U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF8000798[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF8000798[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000798, 0x00003FFFU, 0x00000304U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF800079C[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 0 */
- /* .. ==> 0XF800079C[1:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. L1_SEL = 1 */
- /* .. ==> 0XF800079C[2:2] = 0x00000001U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF800079C[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF800079C[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 1 */
- /* .. ==> 0XF800079C[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. IO_Type = 1 */
- /* .. ==> 0XF800079C[11:9] = 0x00000001U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF800079C[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF800079C[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF800079C, 0x00003FFFU, 0x00000304U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF80007A0[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 0 */
- /* .. ==> 0XF80007A0[1:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF80007A0[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF80007A0[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 4 */
- /* .. ==> 0XF80007A0[7:5] = 0x00000004U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
- /* .. Speed = 1 */
- /* .. ==> 0XF80007A0[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. IO_Type = 1 */
- /* .. ==> 0XF80007A0[11:9] = 0x00000001U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF80007A0[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF80007A0[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU, 0x00000380U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF80007A4[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 0 */
- /* .. ==> 0XF80007A4[1:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF80007A4[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF80007A4[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 4 */
- /* .. ==> 0XF80007A4[7:5] = 0x00000004U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
- /* .. Speed = 1 */
- /* .. ==> 0XF80007A4[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. IO_Type = 1 */
- /* .. ==> 0XF80007A4[11:9] = 0x00000001U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF80007A4[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF80007A4[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU, 0x00000380U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF80007A8[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 0 */
- /* .. ==> 0XF80007A8[1:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF80007A8[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF80007A8[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 4 */
- /* .. ==> 0XF80007A8[7:5] = 0x00000004U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
- /* .. Speed = 1 */
- /* .. ==> 0XF80007A8[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. IO_Type = 1 */
- /* .. ==> 0XF80007A8[11:9] = 0x00000001U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF80007A8[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF80007A8[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU, 0x00000380U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF80007AC[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 0 */
- /* .. ==> 0XF80007AC[1:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF80007AC[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF80007AC[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 4 */
- /* .. ==> 0XF80007AC[7:5] = 0x00000004U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
- /* .. Speed = 1 */
- /* .. ==> 0XF80007AC[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. IO_Type = 1 */
- /* .. ==> 0XF80007AC[11:9] = 0x00000001U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF80007AC[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF80007AC[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU, 0x00000380U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF80007B0[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 0 */
- /* .. ==> 0XF80007B0[1:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF80007B0[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF80007B0[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 4 */
- /* .. ==> 0XF80007B0[7:5] = 0x00000004U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
- /* .. Speed = 1 */
- /* .. ==> 0XF80007B0[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. IO_Type = 1 */
- /* .. ==> 0XF80007B0[11:9] = 0x00000001U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF80007B0[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF80007B0[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU, 0x00000380U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF80007B4[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 0 */
- /* .. ==> 0XF80007B4[1:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF80007B4[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF80007B4[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 4 */
- /* .. ==> 0XF80007B4[7:5] = 0x00000004U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
- /* .. Speed = 1 */
- /* .. ==> 0XF80007B4[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. IO_Type = 1 */
- /* .. ==> 0XF80007B4[11:9] = 0x00000001U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF80007B4[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF80007B4[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00000380U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF80007B8[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 0 */
- /* .. ==> 0XF80007B8[1:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF80007B8[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF80007B8[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF80007B8[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 0 */
- /* .. ==> 0XF80007B8[8:8] = 0x00000000U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
- /* .. IO_Type = 1 */
- /* .. ==> 0XF80007B8[11:9] = 0x00000001U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
- /* .. PULLUP = 1 */
- /* .. ==> 0XF80007B8[12:12] = 0x00000001U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF80007B8[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU, 0x00001200U),
- /* .. TRI_ENABLE = 1 */
- /* .. ==> 0XF80007BC[0:0] = 0x00000001U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
- /* .. Speed = 0 */
- /* .. ==> 0XF80007BC[8:8] = 0x00000000U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
- /* .. IO_Type = 1 */
- /* .. ==> 0XF80007BC[11:9] = 0x00000001U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF80007BC[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF80007BC[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF80007BC, 0x00003F01U, 0x00000201U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF80007C0[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 0 */
- /* .. ==> 0XF80007C0[1:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF80007C0[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF80007C0[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 7 */
- /* .. ==> 0XF80007C0[7:5] = 0x00000007U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x000000E0U */
- /* .. Speed = 0 */
- /* .. ==> 0XF80007C0[8:8] = 0x00000000U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
- /* .. IO_Type = 1 */
- /* .. ==> 0XF80007C0[11:9] = 0x00000001U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF80007C0[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF80007C0[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU, 0x000002E0U),
- /* .. TRI_ENABLE = 1 */
- /* .. ==> 0XF80007C4[0:0] = 0x00000001U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
- /* .. L0_SEL = 0 */
- /* .. ==> 0XF80007C4[1:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF80007C4[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF80007C4[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 7 */
- /* .. ==> 0XF80007C4[7:5] = 0x00000007U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x000000E0U */
- /* .. Speed = 0 */
- /* .. ==> 0XF80007C4[8:8] = 0x00000000U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
- /* .. IO_Type = 1 */
- /* .. ==> 0XF80007C4[11:9] = 0x00000001U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF80007C4[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF80007C4[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x000002E1U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF80007C8[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 0 */
- /* .. ==> 0XF80007C8[1:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF80007C8[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF80007C8[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF80007C8[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 0 */
- /* .. ==> 0XF80007C8[8:8] = 0x00000000U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
- /* .. IO_Type = 1 */
- /* .. ==> 0XF80007C8[11:9] = 0x00000001U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF80007C8[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF80007C8[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU, 0x00000200U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF80007CC[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 0 */
- /* .. ==> 0XF80007CC[1:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF80007CC[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF80007CC[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF80007CC[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 0 */
- /* .. ==> 0XF80007CC[8:8] = 0x00000000U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
- /* .. IO_Type = 1 */
- /* .. ==> 0XF80007CC[11:9] = 0x00000001U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF80007CC[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF80007CC[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU, 0x00000200U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF80007D0[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 0 */
- /* .. ==> 0XF80007D0[1:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF80007D0[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF80007D0[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 4 */
- /* .. ==> 0XF80007D0[7:5] = 0x00000004U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
- /* .. Speed = 0 */
- /* .. ==> 0XF80007D0[8:8] = 0x00000000U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
- /* .. IO_Type = 1 */
- /* .. ==> 0XF80007D0[11:9] = 0x00000001U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF80007D0[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF80007D0[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU, 0x00000280U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF80007D4[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 0 */
- /* .. ==> 0XF80007D4[1:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF80007D4[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF80007D4[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 4 */
- /* .. ==> 0XF80007D4[7:5] = 0x00000004U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
- /* .. Speed = 0 */
- /* .. ==> 0XF80007D4[8:8] = 0x00000000U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
- /* .. IO_Type = 1 */
- /* .. ==> 0XF80007D4[11:9] = 0x00000001U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF80007D4[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF80007D4[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU, 0x00000280U),
- /* .. SDIO0_WP_SEL = 55 */
- /* .. ==> 0XF8000830[5:0] = 0x00000037U */
- /* .. ==> MASK : 0x0000003FU VAL : 0x00000037U */
- /* .. SDIO0_CD_SEL = 47 */
- /* .. ==> 0XF8000830[21:16] = 0x0000002FU */
- /* .. ==> MASK : 0x003F0000U VAL : 0x002F0000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000830, 0x003F003FU, 0x002F0037U),
- /* .. FINISH: MIO PROGRAMMING */
- /* .. START: LOCK IT BACK */
- /* .. LOCK_KEY = 0X767B */
- /* .. ==> 0XF8000004[15:0] = 0x0000767BU */
- /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */
- /* .. */
- EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
- /* .. FINISH: LOCK IT BACK */
- /* FINISH: top */
- /* */
- EMIT_EXIT(),
-
- /* */
-};
-
-unsigned long ps7_peripherals_init_data_3_0[] = {
- /* START: top */
- /* .. START: SLCR SETTINGS */
- /* .. UNLOCK_KEY = 0XDF0D */
- /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
- /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */
- /* .. */
- EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
- /* .. FINISH: SLCR SETTINGS */
- /* .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS */
- /* .. IBUF_DISABLE_MODE = 0x1 */
- /* .. ==> 0XF8000B48[7:7] = 0x00000001U */
- /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */
- /* .. TERM_DISABLE_MODE = 0x1 */
- /* .. ==> 0XF8000B48[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. */
- EMIT_MASKWRITE(0XF8000B48, 0x00000180U, 0x00000180U),
- /* .. IBUF_DISABLE_MODE = 0x1 */
- /* .. ==> 0XF8000B4C[7:7] = 0x00000001U */
- /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */
- /* .. TERM_DISABLE_MODE = 0x1 */
- /* .. ==> 0XF8000B4C[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. */
- EMIT_MASKWRITE(0XF8000B4C, 0x00000180U, 0x00000180U),
- /* .. IBUF_DISABLE_MODE = 0x1 */
- /* .. ==> 0XF8000B50[7:7] = 0x00000001U */
- /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */
- /* .. TERM_DISABLE_MODE = 0x1 */
- /* .. ==> 0XF8000B50[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. */
- EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U),
- /* .. IBUF_DISABLE_MODE = 0x1 */
- /* .. ==> 0XF8000B54[7:7] = 0x00000001U */
- /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */
- /* .. TERM_DISABLE_MODE = 0x1 */
- /* .. ==> 0XF8000B54[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. */
- EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U),
- /* .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS */
- /* .. START: LOCK IT BACK */
- /* .. LOCK_KEY = 0X767B */
- /* .. ==> 0XF8000004[15:0] = 0x0000767BU */
- /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */
- /* .. */
- EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
- /* .. FINISH: LOCK IT BACK */
- /* .. START: SRAM/NOR SET OPMODE */
- /* .. FINISH: SRAM/NOR SET OPMODE */
- /* .. START: UART REGISTERS */
- /* .. BDIV = 0x6 */
- /* .. ==> 0XE0001034[7:0] = 0x00000006U */
- /* .. ==> MASK : 0x000000FFU VAL : 0x00000006U */
- /* .. */
- EMIT_MASKWRITE(0XE0001034, 0x000000FFU, 0x00000006U),
- /* .. CD = 0x7c */
- /* .. ==> 0XE0001018[15:0] = 0x0000007CU */
- /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU */
- /* .. */
- EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU, 0x0000007CU),
- /* .. STPBRK = 0x0 */
- /* .. ==> 0XE0001000[8:8] = 0x00000000U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
- /* .. STTBRK = 0x0 */
- /* .. ==> 0XE0001000[7:7] = 0x00000000U */
- /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
- /* .. RSTTO = 0x0 */
- /* .. ==> 0XE0001000[6:6] = 0x00000000U */
- /* .. ==> MASK : 0x00000040U VAL : 0x00000000U */
- /* .. TXDIS = 0x0 */
- /* .. ==> 0XE0001000[5:5] = 0x00000000U */
- /* .. ==> MASK : 0x00000020U VAL : 0x00000000U */
- /* .. TXEN = 0x1 */
- /* .. ==> 0XE0001000[4:4] = 0x00000001U */
- /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */
- /* .. RXDIS = 0x0 */
- /* .. ==> 0XE0001000[3:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
- /* .. RXEN = 0x1 */
- /* .. ==> 0XE0001000[2:2] = 0x00000001U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
- /* .. TXRES = 0x1 */
- /* .. ==> 0XE0001000[1:1] = 0x00000001U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
- /* .. RXRES = 0x1 */
- /* .. ==> 0XE0001000[0:0] = 0x00000001U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
- /* .. */
- EMIT_MASKWRITE(0XE0001000, 0x000001FFU, 0x00000017U),
- /* .. CHMODE = 0x0 */
- /* .. ==> 0XE0001004[9:8] = 0x00000000U */
- /* .. ==> MASK : 0x00000300U VAL : 0x00000000U */
- /* .. NBSTOP = 0x0 */
- /* .. ==> 0XE0001004[7:6] = 0x00000000U */
- /* .. ==> MASK : 0x000000C0U VAL : 0x00000000U */
- /* .. PAR = 0x4 */
- /* .. ==> 0XE0001004[5:3] = 0x00000004U */
- /* .. ==> MASK : 0x00000038U VAL : 0x00000020U */
- /* .. CHRL = 0x0 */
- /* .. ==> 0XE0001004[2:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */
- /* .. CLKS = 0x0 */
- /* .. ==> 0XE0001004[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XE0001004, 0x000003FFU, 0x00000020U),
- /* .. FINISH: UART REGISTERS */
- /* .. START: QSPI REGISTERS */
- /* .. Holdb_dr = 1 */
- /* .. ==> 0XE000D000[19:19] = 0x00000001U */
- /* .. ==> MASK : 0x00080000U VAL : 0x00080000U */
- /* .. */
- EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U),
- /* .. FINISH: QSPI REGISTERS */
- /* .. START: PL POWER ON RESET REGISTERS */
- /* .. PCFG_POR_CNT_4K = 0 */
- /* .. ==> 0XF8007000[29:29] = 0x00000000U */
- /* .. ==> MASK : 0x20000000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U),
- /* .. FINISH: PL POWER ON RESET REGISTERS */
- /* .. START: SMC TIMING CALCULATION REGISTER UPDATE */
- /* .. .. START: NAND SET CYCLE */
- /* .. .. FINISH: NAND SET CYCLE */
- /* .. .. START: OPMODE */
- /* .. .. FINISH: OPMODE */
- /* .. .. START: DIRECT COMMAND */
- /* .. .. FINISH: DIRECT COMMAND */
- /* .. .. START: SRAM/NOR CS0 SET CYCLE */
- /* .. .. FINISH: SRAM/NOR CS0 SET CYCLE */
- /* .. .. START: DIRECT COMMAND */
- /* .. .. FINISH: DIRECT COMMAND */
- /* .. .. START: NOR CS0 BASE ADDRESS */
- /* .. .. FINISH: NOR CS0 BASE ADDRESS */
- /* .. .. START: SRAM/NOR CS1 SET CYCLE */
- /* .. .. FINISH: SRAM/NOR CS1 SET CYCLE */
- /* .. .. START: DIRECT COMMAND */
- /* .. .. FINISH: DIRECT COMMAND */
- /* .. .. START: NOR CS1 BASE ADDRESS */
- /* .. .. FINISH: NOR CS1 BASE ADDRESS */
- /* .. .. START: USB RESET */
- /* .. .. .. START: USB0 RESET */
- /* .. .. .. .. START: DIR MODE BANK 0 */
- /* .. .. .. .. FINISH: DIR MODE BANK 0 */
- /* .. .. .. .. START: DIR MODE BANK 1 */
- /* .. .. .. .. DIRECTION_1 = 0x4000 */
- /* .. .. .. .. ==> 0XE000A244[21:0] = 0x00004000U */
- /* .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U */
- /* .. .. .. .. */
- EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU, 0x00004000U),
- /* .. .. .. .. FINISH: DIR MODE BANK 1 */
- /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
- /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
- /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
- /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
- /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
- /* .. .. .. .. MASK_1_LSW = 0xbfff */
- /* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */
- /* .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U */
- /* .. .. .. .. DATA_1_LSW = 0x4000 */
- /* .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U */
- /* .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U */
- /* .. .. .. .. */
- EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF4000U),
- /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
- /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
- /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
- /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
- /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
- /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
- /* .. .. .. .. OP_ENABLE_1 = 0x4000 */
- /* .. .. .. .. ==> 0XE000A248[21:0] = 0x00004000U */
- /* .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U */
- /* .. .. .. .. */
- EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU, 0x00004000U),
- /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
- /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
- /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
- /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
- /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
- /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
- /* .. .. .. .. MASK_1_LSW = 0xbfff */
- /* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */
- /* .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U */
- /* .. .. .. .. DATA_1_LSW = 0x0 */
- /* .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U */
- /* .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U */
- /* .. .. .. .. */
- EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF0000U),
- /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
- /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
- /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
- /* .. .. .. .. START: ADD 1 MS DELAY */
- /* .. .. .. .. */
- EMIT_MASKDELAY(0XF8F00200, 1),
- /* .. .. .. .. FINISH: ADD 1 MS DELAY */
- /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
- /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
- /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
- /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
- /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
- /* .. .. .. .. MASK_1_LSW = 0xbfff */
- /* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */
- /* .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U */
- /* .. .. .. .. DATA_1_LSW = 0x4000 */
- /* .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U */
- /* .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U */
- /* .. .. .. .. */
- EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF4000U),
- /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
- /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
- /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
- /* .. .. .. FINISH: USB0 RESET */
- /* .. .. .. START: USB1 RESET */
- /* .. .. .. .. START: DIR MODE BANK 0 */
- /* .. .. .. .. FINISH: DIR MODE BANK 0 */
- /* .. .. .. .. START: DIR MODE BANK 1 */
- /* .. .. .. .. FINISH: DIR MODE BANK 1 */
- /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
- /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
- /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
- /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
- /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
- /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
- /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
- /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
- /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
- /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
- /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
- /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
- /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
- /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
- /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
- /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
- /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
- /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
- /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
- /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
- /* .. .. .. .. START: ADD 1 MS DELAY */
- /* .. .. .. .. */
- EMIT_MASKDELAY(0XF8F00200, 1),
- /* .. .. .. .. FINISH: ADD 1 MS DELAY */
- /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
- /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
- /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
- /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
- /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
- /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
- /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
- /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
- /* .. .. .. FINISH: USB1 RESET */
- /* .. .. FINISH: USB RESET */
- /* .. .. START: ENET RESET */
- /* .. .. .. START: ENET0 RESET */
- /* .. .. .. .. START: DIR MODE BANK 0 */
- /* .. .. .. .. FINISH: DIR MODE BANK 0 */
- /* .. .. .. .. START: DIR MODE BANK 1 */
- /* .. .. .. .. FINISH: DIR MODE BANK 1 */
- /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
- /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
- /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
- /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
- /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
- /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
- /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
- /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
- /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
- /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
- /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
- /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
- /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
- /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
- /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
- /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
- /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
- /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
- /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
- /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
- /* .. .. .. .. START: ADD 1 MS DELAY */
- /* .. .. .. .. */
- EMIT_MASKDELAY(0XF8F00200, 1),
- /* .. .. .. .. FINISH: ADD 1 MS DELAY */
- /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
- /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
- /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
- /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
- /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
- /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
- /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
- /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
- /* .. .. .. FINISH: ENET0 RESET */
- /* .. .. .. START: ENET1 RESET */
- /* .. .. .. .. START: DIR MODE BANK 0 */
- /* .. .. .. .. FINISH: DIR MODE BANK 0 */
- /* .. .. .. .. START: DIR MODE BANK 1 */
- /* .. .. .. .. FINISH: DIR MODE BANK 1 */
- /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
- /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
- /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
- /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
- /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
- /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
- /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
- /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
- /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
- /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
- /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
- /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
- /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
- /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
- /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
- /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
- /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
- /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
- /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
- /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
- /* .. .. .. .. START: ADD 1 MS DELAY */
- /* .. .. .. .. */
- EMIT_MASKDELAY(0XF8F00200, 1),
- /* .. .. .. .. FINISH: ADD 1 MS DELAY */
- /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
- /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
- /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
- /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
- /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
- /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
- /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
- /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
- /* .. .. .. FINISH: ENET1 RESET */
- /* .. .. FINISH: ENET RESET */
- /* .. .. START: I2C RESET */
- /* .. .. .. START: I2C0 RESET */
- /* .. .. .. .. START: DIR MODE GPIO BANK0 */
- /* .. .. .. .. FINISH: DIR MODE GPIO BANK0 */
- /* .. .. .. .. START: DIR MODE GPIO BANK1 */
- /* .. .. .. .. FINISH: DIR MODE GPIO BANK1 */
- /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
- /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
- /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
- /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
- /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
- /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
- /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
- /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
- /* .. .. .. .. START: OUTPUT ENABLE */
- /* .. .. .. .. FINISH: OUTPUT ENABLE */
- /* .. .. .. .. START: OUTPUT ENABLE */
- /* .. .. .. .. FINISH: OUTPUT ENABLE */
- /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
- /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
- /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
- /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
- /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
- /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
- /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
- /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
- /* .. .. .. .. START: ADD 1 MS DELAY */
- /* .. .. .. .. */
- EMIT_MASKDELAY(0XF8F00200, 1),
- /* .. .. .. .. FINISH: ADD 1 MS DELAY */
- /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
- /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
- /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
- /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
- /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
- /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
- /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
- /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
- /* .. .. .. FINISH: I2C0 RESET */
- /* .. .. .. START: I2C1 RESET */
- /* .. .. .. .. START: DIR MODE GPIO BANK0 */
- /* .. .. .. .. FINISH: DIR MODE GPIO BANK0 */
- /* .. .. .. .. START: DIR MODE GPIO BANK1 */
- /* .. .. .. .. FINISH: DIR MODE GPIO BANK1 */
- /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
- /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
- /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
- /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
- /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
- /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
- /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
- /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
- /* .. .. .. .. START: OUTPUT ENABLE */
- /* .. .. .. .. FINISH: OUTPUT ENABLE */
- /* .. .. .. .. START: OUTPUT ENABLE */
- /* .. .. .. .. FINISH: OUTPUT ENABLE */
- /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
- /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
- /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
- /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
- /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
- /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
- /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
- /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
- /* .. .. .. .. START: ADD 1 MS DELAY */
- /* .. .. .. .. */
- EMIT_MASKDELAY(0XF8F00200, 1),
- /* .. .. .. .. FINISH: ADD 1 MS DELAY */
- /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
- /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
- /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
- /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
- /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
- /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
- /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
- /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
- /* .. .. .. FINISH: I2C1 RESET */
- /* .. .. FINISH: I2C RESET */
- /* .. .. START: NOR CHIP SELECT */
- /* .. .. .. START: DIR MODE BANK 0 */
- /* .. .. .. FINISH: DIR MODE BANK 0 */
- /* .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
- /* .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
- /* .. .. .. START: OUTPUT ENABLE BANK 0 */
- /* .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
- /* .. .. FINISH: NOR CHIP SELECT */
- /* .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE */
- /* FINISH: top */
- /* */
- EMIT_EXIT(),
-
- /* */
-};
-
-unsigned long ps7_post_config_3_0[] = {
- /* START: top */
- /* .. START: SLCR SETTINGS */
- /* .. UNLOCK_KEY = 0XDF0D */
- /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
- /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */
- /* .. */
- EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
- /* .. FINISH: SLCR SETTINGS */
- /* .. START: ENABLING LEVEL SHIFTER */
- /* .. USER_LVL_INP_EN_0 = 1 */
- /* .. ==> 0XF8000900[3:3] = 0x00000001U */
- /* .. ==> MASK : 0x00000008U VAL : 0x00000008U */
- /* .. USER_LVL_OUT_EN_0 = 1 */
- /* .. ==> 0XF8000900[2:2] = 0x00000001U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
- /* .. USER_LVL_INP_EN_1 = 1 */
- /* .. ==> 0XF8000900[1:1] = 0x00000001U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
- /* .. USER_LVL_OUT_EN_1 = 1 */
- /* .. ==> 0XF8000900[0:0] = 0x00000001U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
- /* .. */
- EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU),
- /* .. FINISH: ENABLING LEVEL SHIFTER */
- /* .. START: FPGA RESETS TO 0 */
- /* .. reserved_3 = 0 */
- /* .. ==> 0XF8000240[31:25] = 0x00000000U */
- /* .. ==> MASK : 0xFE000000U VAL : 0x00000000U */
- /* .. reserved_FPGA_ACP_RST = 0 */
- /* .. ==> 0XF8000240[24:24] = 0x00000000U */
- /* .. ==> MASK : 0x01000000U VAL : 0x00000000U */
- /* .. reserved_FPGA_AXDS3_RST = 0 */
- /* .. ==> 0XF8000240[23:23] = 0x00000000U */
- /* .. ==> MASK : 0x00800000U VAL : 0x00000000U */
- /* .. reserved_FPGA_AXDS2_RST = 0 */
- /* .. ==> 0XF8000240[22:22] = 0x00000000U */
- /* .. ==> MASK : 0x00400000U VAL : 0x00000000U */
- /* .. reserved_FPGA_AXDS1_RST = 0 */
- /* .. ==> 0XF8000240[21:21] = 0x00000000U */
- /* .. ==> MASK : 0x00200000U VAL : 0x00000000U */
- /* .. reserved_FPGA_AXDS0_RST = 0 */
- /* .. ==> 0XF8000240[20:20] = 0x00000000U */
- /* .. ==> MASK : 0x00100000U VAL : 0x00000000U */
- /* .. reserved_2 = 0 */
- /* .. ==> 0XF8000240[19:18] = 0x00000000U */
- /* .. ==> MASK : 0x000C0000U VAL : 0x00000000U */
- /* .. reserved_FSSW1_FPGA_RST = 0 */
- /* .. ==> 0XF8000240[17:17] = 0x00000000U */
- /* .. ==> MASK : 0x00020000U VAL : 0x00000000U */
- /* .. reserved_FSSW0_FPGA_RST = 0 */
- /* .. ==> 0XF8000240[16:16] = 0x00000000U */
- /* .. ==> MASK : 0x00010000U VAL : 0x00000000U */
- /* .. reserved_1 = 0 */
- /* .. ==> 0XF8000240[15:14] = 0x00000000U */
- /* .. ==> MASK : 0x0000C000U VAL : 0x00000000U */
- /* .. reserved_FPGA_FMSW1_RST = 0 */
- /* .. ==> 0XF8000240[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. reserved_FPGA_FMSW0_RST = 0 */
- /* .. ==> 0XF8000240[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. reserved_FPGA_DMA3_RST = 0 */
- /* .. ==> 0XF8000240[11:11] = 0x00000000U */
- /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
- /* .. reserved_FPGA_DMA2_RST = 0 */
- /* .. ==> 0XF8000240[10:10] = 0x00000000U */
- /* .. ==> MASK : 0x00000400U VAL : 0x00000000U */
- /* .. reserved_FPGA_DMA1_RST = 0 */
- /* .. ==> 0XF8000240[9:9] = 0x00000000U */
- /* .. ==> MASK : 0x00000200U VAL : 0x00000000U */
- /* .. reserved_FPGA_DMA0_RST = 0 */
- /* .. ==> 0XF8000240[8:8] = 0x00000000U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
- /* .. reserved = 0 */
- /* .. ==> 0XF8000240[7:4] = 0x00000000U */
- /* .. ==> MASK : 0x000000F0U VAL : 0x00000000U */
- /* .. FPGA3_OUT_RST = 0 */
- /* .. ==> 0XF8000240[3:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
- /* .. FPGA2_OUT_RST = 0 */
- /* .. ==> 0XF8000240[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. FPGA1_OUT_RST = 0 */
- /* .. ==> 0XF8000240[1:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. FPGA0_OUT_RST = 0 */
- /* .. ==> 0XF8000240[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU, 0x00000000U),
- /* .. FINISH: FPGA RESETS TO 0 */
- /* .. START: AFI REGISTERS */
- /* .. .. START: AFI0 REGISTERS */
- /* .. .. FINISH: AFI0 REGISTERS */
- /* .. .. START: AFI1 REGISTERS */
- /* .. .. FINISH: AFI1 REGISTERS */
- /* .. .. START: AFI2 REGISTERS */
- /* .. .. FINISH: AFI2 REGISTERS */
- /* .. .. START: AFI3 REGISTERS */
- /* .. .. FINISH: AFI3 REGISTERS */
- /* .. .. START: AFI2 SECURE REGISTER */
- /* .. .. FINISH: AFI2 SECURE REGISTER */
- /* .. FINISH: AFI REGISTERS */
- /* .. START: LOCK IT BACK */
- /* .. LOCK_KEY = 0X767B */
- /* .. ==> 0XF8000004[15:0] = 0x0000767BU */
- /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */
- /* .. */
- EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
- /* .. FINISH: LOCK IT BACK */
- /* FINISH: top */
- /* */
- EMIT_EXIT(),
-
- /* */
-};
-
-unsigned long ps7_debug_3_0[] = {
- /* START: top */
- /* .. START: CROSS TRIGGER CONFIGURATIONS */
- /* .. .. START: UNLOCKING CTI REGISTERS */
- /* .. .. KEY = 0XC5ACCE55 */
- /* .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U */
- /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU, 0xC5ACCE55U),
- /* .. .. KEY = 0XC5ACCE55 */
- /* .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U */
- /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU, 0xC5ACCE55U),
- /* .. .. KEY = 0XC5ACCE55 */
- /* .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U */
- /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU, 0xC5ACCE55U),
- /* .. .. FINISH: UNLOCKING CTI REGISTERS */
- /* .. .. START: ENABLING CTI MODULES AND CHANNELS */
- /* .. .. FINISH: ENABLING CTI MODULES AND CHANNELS */
- /* .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS */
- /* .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS */
- /* .. FINISH: CROSS TRIGGER CONFIGURATIONS */
- /* FINISH: top */
- /* */
- EMIT_EXIT(),
-
- /* */
-};
-
-unsigned long ps7_pll_init_data_2_0[] = {
- /* START: top */
- /* .. START: SLCR SETTINGS */
- /* .. UNLOCK_KEY = 0XDF0D */
- /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
- /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */
- /* .. */
- EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
- /* .. FINISH: SLCR SETTINGS */
- /* .. START: PLL SLCR REGISTERS */
- /* .. .. START: ARM PLL INIT */
- /* .. .. PLL_RES = 0xc */
- /* .. .. ==> 0XF8000110[7:4] = 0x0000000CU */
- /* .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U */
- /* .. .. PLL_CP = 0x2 */
- /* .. .. ==> 0XF8000110[11:8] = 0x00000002U */
- /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */
- /* .. .. LOCK_CNT = 0x177 */
- /* .. .. ==> 0XF8000110[21:12] = 0x00000177U */
- /* .. .. ==> MASK : 0x003FF000U VAL : 0x00177000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x001772C0U),
- /* .. .. .. START: UPDATE FB_DIV */
- /* .. .. .. PLL_FDIV = 0x1a */
- /* .. .. .. ==> 0XF8000100[18:12] = 0x0000001AU */
- /* .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001A000U */
- /* .. .. .. */
- EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x0001A000U),
- /* .. .. .. FINISH: UPDATE FB_DIV */
- /* .. .. .. START: BY PASS PLL */
- /* .. .. .. PLL_BYPASS_FORCE = 1 */
- /* .. .. .. ==> 0XF8000100[4:4] = 0x00000001U */
- /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U */
- /* .. .. .. */
- EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U),
- /* .. .. .. FINISH: BY PASS PLL */
- /* .. .. .. START: ASSERT RESET */
- /* .. .. .. PLL_RESET = 1 */
- /* .. .. .. ==> 0XF8000100[0:0] = 0x00000001U */
- /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
- /* .. .. .. */
- EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U),
- /* .. .. .. FINISH: ASSERT RESET */
- /* .. .. .. START: DEASSERT RESET */
- /* .. .. .. PLL_RESET = 0 */
- /* .. .. .. ==> 0XF8000100[0:0] = 0x00000000U */
- /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. .. .. */
- EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U),
- /* .. .. .. FINISH: DEASSERT RESET */
- /* .. .. .. START: CHECK PLL STATUS */
- /* .. .. .. ARM_PLL_LOCK = 1 */
- /* .. .. .. ==> 0XF800010C[0:0] = 0x00000001U */
- /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
- /* .. .. .. */
- EMIT_MASKPOLL(0XF800010C, 0x00000001U),
- /* .. .. .. FINISH: CHECK PLL STATUS */
- /* .. .. .. START: REMOVE PLL BY PASS */
- /* .. .. .. PLL_BYPASS_FORCE = 0 */
- /* .. .. .. ==> 0XF8000100[4:4] = 0x00000000U */
- /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
- /* .. .. .. */
- EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U),
- /* .. .. .. FINISH: REMOVE PLL BY PASS */
- /* .. .. .. SRCSEL = 0x0 */
- /* .. .. .. ==> 0XF8000120[5:4] = 0x00000000U */
- /* .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
- /* .. .. .. DIVISOR = 0x2 */
- /* .. .. .. ==> 0XF8000120[13:8] = 0x00000002U */
- /* .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U */
- /* .. .. .. CPU_6OR4XCLKACT = 0x1 */
- /* .. .. .. ==> 0XF8000120[24:24] = 0x00000001U */
- /* .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U */
- /* .. .. .. CPU_3OR2XCLKACT = 0x1 */
- /* .. .. .. ==> 0XF8000120[25:25] = 0x00000001U */
- /* .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U */
- /* .. .. .. CPU_2XCLKACT = 0x1 */
- /* .. .. .. ==> 0XF8000120[26:26] = 0x00000001U */
- /* .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U */
- /* .. .. .. CPU_1XCLKACT = 0x1 */
- /* .. .. .. ==> 0XF8000120[27:27] = 0x00000001U */
- /* .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U */
- /* .. .. .. CPU_PERI_CLKACT = 0x1 */
- /* .. .. .. ==> 0XF8000120[28:28] = 0x00000001U */
- /* .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U */
- /* .. .. .. */
- EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000200U),
- /* .. .. FINISH: ARM PLL INIT */
- /* .. .. START: DDR PLL INIT */
- /* .. .. PLL_RES = 0xc */
- /* .. .. ==> 0XF8000114[7:4] = 0x0000000CU */
- /* .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U */
- /* .. .. PLL_CP = 0x2 */
- /* .. .. ==> 0XF8000114[11:8] = 0x00000002U */
- /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */
- /* .. .. LOCK_CNT = 0x1db */
- /* .. .. ==> 0XF8000114[21:12] = 0x000001DBU */
- /* .. .. ==> MASK : 0x003FF000U VAL : 0x001DB000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x001DB2C0U),
- /* .. .. .. START: UPDATE FB_DIV */
- /* .. .. .. PLL_FDIV = 0x15 */
- /* .. .. .. ==> 0XF8000104[18:12] = 0x00000015U */
- /* .. .. .. ==> MASK : 0x0007F000U VAL : 0x00015000U */
- /* .. .. .. */
- EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x00015000U),
- /* .. .. .. FINISH: UPDATE FB_DIV */
- /* .. .. .. START: BY PASS PLL */
- /* .. .. .. PLL_BYPASS_FORCE = 1 */
- /* .. .. .. ==> 0XF8000104[4:4] = 0x00000001U */
- /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U */
- /* .. .. .. */
- EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000010U),
- /* .. .. .. FINISH: BY PASS PLL */
- /* .. .. .. START: ASSERT RESET */
- /* .. .. .. PLL_RESET = 1 */
- /* .. .. .. ==> 0XF8000104[0:0] = 0x00000001U */
- /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
- /* .. .. .. */
- EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000001U),
- /* .. .. .. FINISH: ASSERT RESET */
- /* .. .. .. START: DEASSERT RESET */
- /* .. .. .. PLL_RESET = 0 */
- /* .. .. .. ==> 0XF8000104[0:0] = 0x00000000U */
- /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. .. .. */
- EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000000U),
- /* .. .. .. FINISH: DEASSERT RESET */
- /* .. .. .. START: CHECK PLL STATUS */
- /* .. .. .. DDR_PLL_LOCK = 1 */
- /* .. .. .. ==> 0XF800010C[1:1] = 0x00000001U */
- /* .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */
- /* .. .. .. */
- EMIT_MASKPOLL(0XF800010C, 0x00000002U),
- /* .. .. .. FINISH: CHECK PLL STATUS */
- /* .. .. .. START: REMOVE PLL BY PASS */
- /* .. .. .. PLL_BYPASS_FORCE = 0 */
- /* .. .. .. ==> 0XF8000104[4:4] = 0x00000000U */
- /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
- /* .. .. .. */
- EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U),
- /* .. .. .. FINISH: REMOVE PLL BY PASS */
- /* .. .. .. DDR_3XCLKACT = 0x1 */
- /* .. .. .. ==> 0XF8000124[0:0] = 0x00000001U */
- /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
- /* .. .. .. DDR_2XCLKACT = 0x1 */
- /* .. .. .. ==> 0XF8000124[1:1] = 0x00000001U */
- /* .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */
- /* .. .. .. DDR_3XCLK_DIVISOR = 0x2 */
- /* .. .. .. ==> 0XF8000124[25:20] = 0x00000002U */
- /* .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U */
- /* .. .. .. DDR_2XCLK_DIVISOR = 0x3 */
- /* .. .. .. ==> 0XF8000124[31:26] = 0x00000003U */
- /* .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U */
- /* .. .. .. */
- EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U),
- /* .. .. FINISH: DDR PLL INIT */
- /* .. .. START: IO PLL INIT */
- /* .. .. PLL_RES = 0xc */
- /* .. .. ==> 0XF8000118[7:4] = 0x0000000CU */
- /* .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U */
- /* .. .. PLL_CP = 0x2 */
- /* .. .. ==> 0XF8000118[11:8] = 0x00000002U */
- /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */
- /* .. .. LOCK_CNT = 0x1f4 */
- /* .. .. ==> 0XF8000118[21:12] = 0x000001F4U */
- /* .. .. ==> MASK : 0x003FF000U VAL : 0x001F4000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x001F42C0U),
- /* .. .. .. START: UPDATE FB_DIV */
- /* .. .. .. PLL_FDIV = 0x14 */
- /* .. .. .. ==> 0XF8000108[18:12] = 0x00000014U */
- /* .. .. .. ==> MASK : 0x0007F000U VAL : 0x00014000U */
- /* .. .. .. */
- EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x00014000U),
- /* .. .. .. FINISH: UPDATE FB_DIV */
- /* .. .. .. START: BY PASS PLL */
- /* .. .. .. PLL_BYPASS_FORCE = 1 */
- /* .. .. .. ==> 0XF8000108[4:4] = 0x00000001U */
- /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U */
- /* .. .. .. */
- EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U),
- /* .. .. .. FINISH: BY PASS PLL */
- /* .. .. .. START: ASSERT RESET */
- /* .. .. .. PLL_RESET = 1 */
- /* .. .. .. ==> 0XF8000108[0:0] = 0x00000001U */
- /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
- /* .. .. .. */
- EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U),
- /* .. .. .. FINISH: ASSERT RESET */
- /* .. .. .. START: DEASSERT RESET */
- /* .. .. .. PLL_RESET = 0 */
- /* .. .. .. ==> 0XF8000108[0:0] = 0x00000000U */
- /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. .. .. */
- EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U),
- /* .. .. .. FINISH: DEASSERT RESET */
- /* .. .. .. START: CHECK PLL STATUS */
- /* .. .. .. IO_PLL_LOCK = 1 */
- /* .. .. .. ==> 0XF800010C[2:2] = 0x00000001U */
- /* .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U */
- /* .. .. .. */
- EMIT_MASKPOLL(0XF800010C, 0x00000004U),
- /* .. .. .. FINISH: CHECK PLL STATUS */
- /* .. .. .. START: REMOVE PLL BY PASS */
- /* .. .. .. PLL_BYPASS_FORCE = 0 */
- /* .. .. .. ==> 0XF8000108[4:4] = 0x00000000U */
- /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
- /* .. .. .. */
- EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000000U),
- /* .. .. .. FINISH: REMOVE PLL BY PASS */
- /* .. .. FINISH: IO PLL INIT */
- /* .. FINISH: PLL SLCR REGISTERS */
- /* .. START: LOCK IT BACK */
- /* .. LOCK_KEY = 0X767B */
- /* .. ==> 0XF8000004[15:0] = 0x0000767BU */
- /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */
- /* .. */
- EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
- /* .. FINISH: LOCK IT BACK */
- /* FINISH: top */
- /* */
- EMIT_EXIT(),
-
- /* */
-};
-
-unsigned long ps7_clock_init_data_2_0[] = {
- /* START: top */
- /* .. START: SLCR SETTINGS */
- /* .. UNLOCK_KEY = 0XDF0D */
- /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
- /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */
- /* .. */
- EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
- /* .. FINISH: SLCR SETTINGS */
- /* .. START: CLOCK CONTROL SLCR REGISTERS */
- /* .. CLKACT = 0x1 */
- /* .. ==> 0XF8000128[0:0] = 0x00000001U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
- /* .. DIVISOR0 = 0x34 */
- /* .. ==> 0XF8000128[13:8] = 0x00000034U */
- /* .. ==> MASK : 0x00003F00U VAL : 0x00003400U */
- /* .. DIVISOR1 = 0x2 */
- /* .. ==> 0XF8000128[25:20] = 0x00000002U */
- /* .. ==> MASK : 0x03F00000U VAL : 0x00200000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00203401U),
- /* .. CLKACT = 0x1 */
- /* .. ==> 0XF8000138[0:0] = 0x00000001U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
- /* .. SRCSEL = 0x0 */
- /* .. ==> 0XF8000138[4:4] = 0x00000000U */
- /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000001U),
- /* .. CLKACT = 0x1 */
- /* .. ==> 0XF8000140[0:0] = 0x00000001U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
- /* .. SRCSEL = 0x0 */
- /* .. ==> 0XF8000140[6:4] = 0x00000000U */
- /* .. ==> MASK : 0x00000070U VAL : 0x00000000U */
- /* .. DIVISOR = 0x8 */
- /* .. ==> 0XF8000140[13:8] = 0x00000008U */
- /* .. ==> MASK : 0x00003F00U VAL : 0x00000800U */
- /* .. DIVISOR1 = 0x1 */
- /* .. ==> 0XF8000140[25:20] = 0x00000001U */
- /* .. ==> MASK : 0x03F00000U VAL : 0x00100000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00100801U),
- /* .. CLKACT = 0x1 */
- /* .. ==> 0XF800014C[0:0] = 0x00000001U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
- /* .. SRCSEL = 0x0 */
- /* .. ==> 0XF800014C[5:4] = 0x00000000U */
- /* .. ==> MASK : 0x00000030U VAL : 0x00000000U */
- /* .. DIVISOR = 0x5 */
- /* .. ==> 0XF800014C[13:8] = 0x00000005U */
- /* .. ==> MASK : 0x00003F00U VAL : 0x00000500U */
- /* .. */
- EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000501U),
- /* .. CLKACT0 = 0x1 */
- /* .. ==> 0XF8000150[0:0] = 0x00000001U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
- /* .. CLKACT1 = 0x0 */
- /* .. ==> 0XF8000150[1:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. SRCSEL = 0x0 */
- /* .. ==> 0XF8000150[5:4] = 0x00000000U */
- /* .. ==> MASK : 0x00000030U VAL : 0x00000000U */
- /* .. DIVISOR = 0x14 */
- /* .. ==> 0XF8000150[13:8] = 0x00000014U */
- /* .. ==> MASK : 0x00003F00U VAL : 0x00001400U */
- /* .. */
- EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00001401U),
- /* .. CLKACT0 = 0x0 */
- /* .. ==> 0XF8000154[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. CLKACT1 = 0x1 */
- /* .. ==> 0XF8000154[1:1] = 0x00000001U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
- /* .. SRCSEL = 0x0 */
- /* .. ==> 0XF8000154[5:4] = 0x00000000U */
- /* .. ==> MASK : 0x00000030U VAL : 0x00000000U */
- /* .. DIVISOR = 0xa */
- /* .. ==> 0XF8000154[13:8] = 0x0000000AU */
- /* .. ==> MASK : 0x00003F00U VAL : 0x00000A00U */
- /* .. */
- EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00000A02U),
- /* .. .. START: TRACE CLOCK */
- /* .. .. FINISH: TRACE CLOCK */
- /* .. .. CLKACT = 0x1 */
- /* .. .. ==> 0XF8000168[0:0] = 0x00000001U */
- /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
- /* .. .. SRCSEL = 0x0 */
- /* .. .. ==> 0XF8000168[5:4] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
- /* .. .. DIVISOR = 0x5 */
- /* .. .. ==> 0XF8000168[13:8] = 0x00000005U */
- /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000501U),
- /* .. .. SRCSEL = 0x0 */
- /* .. .. ==> 0XF8000170[5:4] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
- /* .. .. DIVISOR0 = 0xa */
- /* .. .. ==> 0XF8000170[13:8] = 0x0000000AU */
- /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U */
- /* .. .. DIVISOR1 = 0x1 */
- /* .. .. ==> 0XF8000170[25:20] = 0x00000001U */
- /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00100A00U),
- /* .. .. SRCSEL = 0x0 */
- /* .. .. ==> 0XF8000180[5:4] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
- /* .. .. DIVISOR0 = 0x7 */
- /* .. .. ==> 0XF8000180[13:8] = 0x00000007U */
- /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000700U */
- /* .. .. DIVISOR1 = 0x1 */
- /* .. .. ==> 0XF8000180[25:20] = 0x00000001U */
- /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00100700U),
- /* .. .. SRCSEL = 0x0 */
- /* .. .. ==> 0XF8000190[5:4] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
- /* .. .. DIVISOR0 = 0x5 */
- /* .. .. ==> 0XF8000190[13:8] = 0x00000005U */
- /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U */
- /* .. .. DIVISOR1 = 0x1 */
- /* .. .. ==> 0XF8000190[25:20] = 0x00000001U */
- /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00100500U),
- /* .. .. SRCSEL = 0x0 */
- /* .. .. ==> 0XF80001A0[5:4] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
- /* .. .. DIVISOR0 = 0x14 */
- /* .. .. ==> 0XF80001A0[13:8] = 0x00000014U */
- /* .. .. ==> MASK : 0x00003F00U VAL : 0x00001400U */
- /* .. .. DIVISOR1 = 0x1 */
- /* .. .. ==> 0XF80001A0[25:20] = 0x00000001U */
- /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00101400U),
- /* .. .. CLK_621_TRUE = 0x1 */
- /* .. .. ==> 0XF80001C4[0:0] = 0x00000001U */
- /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
- /* .. .. */
- EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U),
- /* .. .. DMA_CPU_2XCLKACT = 0x1 */
- /* .. .. ==> 0XF800012C[0:0] = 0x00000001U */
- /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
- /* .. .. USB0_CPU_1XCLKACT = 0x1 */
- /* .. .. ==> 0XF800012C[2:2] = 0x00000001U */
- /* .. .. ==> MASK : 0x00000004U VAL : 0x00000004U */
- /* .. .. USB1_CPU_1XCLKACT = 0x1 */
- /* .. .. ==> 0XF800012C[3:3] = 0x00000001U */
- /* .. .. ==> MASK : 0x00000008U VAL : 0x00000008U */
- /* .. .. GEM0_CPU_1XCLKACT = 0x1 */
- /* .. .. ==> 0XF800012C[6:6] = 0x00000001U */
- /* .. .. ==> MASK : 0x00000040U VAL : 0x00000040U */
- /* .. .. GEM1_CPU_1XCLKACT = 0x0 */
- /* .. .. ==> 0XF800012C[7:7] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000080U VAL : 0x00000000U */
- /* .. .. SDI0_CPU_1XCLKACT = 0x1 */
- /* .. .. ==> 0XF800012C[10:10] = 0x00000001U */
- /* .. .. ==> MASK : 0x00000400U VAL : 0x00000400U */
- /* .. .. SDI1_CPU_1XCLKACT = 0x0 */
- /* .. .. ==> 0XF800012C[11:11] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */
- /* .. .. SPI0_CPU_1XCLKACT = 0x0 */
- /* .. .. ==> 0XF800012C[14:14] = 0x00000000U */
- /* .. .. ==> MASK : 0x00004000U VAL : 0x00000000U */
- /* .. .. SPI1_CPU_1XCLKACT = 0x0 */
- /* .. .. ==> 0XF800012C[15:15] = 0x00000000U */
- /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */
- /* .. .. CAN0_CPU_1XCLKACT = 0x0 */
- /* .. .. ==> 0XF800012C[16:16] = 0x00000000U */
- /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
- /* .. .. CAN1_CPU_1XCLKACT = 0x0 */
- /* .. .. ==> 0XF800012C[17:17] = 0x00000000U */
- /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
- /* .. .. I2C0_CPU_1XCLKACT = 0x1 */
- /* .. .. ==> 0XF800012C[18:18] = 0x00000001U */
- /* .. .. ==> MASK : 0x00040000U VAL : 0x00040000U */
- /* .. .. I2C1_CPU_1XCLKACT = 0x1 */
- /* .. .. ==> 0XF800012C[19:19] = 0x00000001U */
- /* .. .. ==> MASK : 0x00080000U VAL : 0x00080000U */
- /* .. .. UART0_CPU_1XCLKACT = 0x0 */
- /* .. .. ==> 0XF800012C[20:20] = 0x00000000U */
- /* .. .. ==> MASK : 0x00100000U VAL : 0x00000000U */
- /* .. .. UART1_CPU_1XCLKACT = 0x1 */
- /* .. .. ==> 0XF800012C[21:21] = 0x00000001U */
- /* .. .. ==> MASK : 0x00200000U VAL : 0x00200000U */
- /* .. .. GPIO_CPU_1XCLKACT = 0x1 */
- /* .. .. ==> 0XF800012C[22:22] = 0x00000001U */
- /* .. .. ==> MASK : 0x00400000U VAL : 0x00400000U */
- /* .. .. LQSPI_CPU_1XCLKACT = 0x1 */
- /* .. .. ==> 0XF800012C[23:23] = 0x00000001U */
- /* .. .. ==> MASK : 0x00800000U VAL : 0x00800000U */
- /* .. .. SMC_CPU_1XCLKACT = 0x1 */
- /* .. .. ==> 0XF800012C[24:24] = 0x00000001U */
- /* .. .. ==> MASK : 0x01000000U VAL : 0x01000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01EC044DU),
- /* .. FINISH: CLOCK CONTROL SLCR REGISTERS */
- /* .. START: THIS SHOULD BE BLANK */
- /* .. FINISH: THIS SHOULD BE BLANK */
- /* .. START: LOCK IT BACK */
- /* .. LOCK_KEY = 0X767B */
- /* .. ==> 0XF8000004[15:0] = 0x0000767BU */
- /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */
- /* .. */
- EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
- /* .. FINISH: LOCK IT BACK */
- /* FINISH: top */
- /* */
- EMIT_EXIT(),
-
- /* */
-};
-
-unsigned long ps7_ddr_init_data_2_0[] = {
- /* START: top */
- /* .. START: DDR INITIALIZATION */
- /* .. .. START: LOCK DDR */
- /* .. .. reg_ddrc_soft_rstb = 0 */
- /* .. .. ==> 0XF8006000[0:0] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. .. reg_ddrc_powerdown_en = 0x0 */
- /* .. .. ==> 0XF8006000[1:1] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. .. reg_ddrc_data_bus_width = 0x0 */
- /* .. .. ==> 0XF8006000[3:2] = 0x00000000U */
- /* .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U */
- /* .. .. reg_ddrc_burst8_refresh = 0x0 */
- /* .. .. ==> 0XF8006000[6:4] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000070U VAL : 0x00000000U */
- /* .. .. reg_ddrc_rdwr_idle_gap = 0x1 */
- /* .. .. ==> 0XF8006000[13:7] = 0x00000001U */
- /* .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U */
- /* .. .. reg_ddrc_dis_rd_bypass = 0x0 */
- /* .. .. ==> 0XF8006000[14:14] = 0x00000000U */
- /* .. .. ==> MASK : 0x00004000U VAL : 0x00000000U */
- /* .. .. reg_ddrc_dis_act_bypass = 0x0 */
- /* .. .. ==> 0XF8006000[15:15] = 0x00000000U */
- /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */
- /* .. .. reg_ddrc_dis_auto_refresh = 0x0 */
- /* .. .. ==> 0XF8006000[16:16] = 0x00000000U */
- /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000080U),
- /* .. .. FINISH: LOCK DDR */
- /* .. .. reg_ddrc_t_rfc_nom_x32 = 0x7f */
- /* .. .. ==> 0XF8006004[11:0] = 0x0000007FU */
- /* .. .. ==> MASK : 0x00000FFFU VAL : 0x0000007FU */
- /* .. .. reg_ddrc_active_ranks = 0x1 */
- /* .. .. ==> 0XF8006004[13:12] = 0x00000001U */
- /* .. .. ==> MASK : 0x00003000U VAL : 0x00001000U */
- /* .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 */
- /* .. .. ==> 0XF8006004[18:14] = 0x00000000U */
- /* .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U */
- /* .. .. reg_ddrc_wr_odt_block = 0x1 */
- /* .. .. ==> 0XF8006004[20:19] = 0x00000001U */
- /* .. .. ==> MASK : 0x00180000U VAL : 0x00080000U */
- /* .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0 */
- /* .. .. ==> 0XF8006004[21:21] = 0x00000000U */
- /* .. .. ==> MASK : 0x00200000U VAL : 0x00000000U */
- /* .. .. reg_ddrc_addrmap_cs_bit1 = 0x0 */
- /* .. .. ==> 0XF8006004[26:22] = 0x00000000U */
- /* .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U */
- /* .. .. reg_ddrc_addrmap_open_bank = 0x0 */
- /* .. .. ==> 0XF8006004[27:27] = 0x00000000U */
- /* .. .. ==> MASK : 0x08000000U VAL : 0x00000000U */
- /* .. .. reg_ddrc_addrmap_4bank_ram = 0x0 */
- /* .. .. ==> 0XF8006004[28:28] = 0x00000000U */
- /* .. .. ==> MASK : 0x10000000U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU, 0x0008107FU),
- /* .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf */
- /* .. .. ==> 0XF8006008[10:0] = 0x0000000FU */
- /* .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU */
- /* .. .. reg_ddrc_hpr_max_starve_x32 = 0xf */
- /* .. .. ==> 0XF8006008[21:11] = 0x0000000FU */
- /* .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U */
- /* .. .. reg_ddrc_hpr_xact_run_length = 0xf */
- /* .. .. ==> 0XF8006008[25:22] = 0x0000000FU */
- /* .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU, 0x03C0780FU),
- /* .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 */
- /* .. .. ==> 0XF800600C[10:0] = 0x00000001U */
- /* .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U */
- /* .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 */
- /* .. .. ==> 0XF800600C[21:11] = 0x00000002U */
- /* .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U */
- /* .. .. reg_ddrc_lpr_xact_run_length = 0x8 */
- /* .. .. ==> 0XF800600C[25:22] = 0x00000008U */
- /* .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU, 0x02001001U),
- /* .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 */
- /* .. .. ==> 0XF8006010[10:0] = 0x00000001U */
- /* .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U */
- /* .. .. reg_ddrc_w_xact_run_length = 0x8 */
- /* .. .. ==> 0XF8006010[14:11] = 0x00000008U */
- /* .. .. ==> MASK : 0x00007800U VAL : 0x00004000U */
- /* .. .. reg_ddrc_w_max_starve_x32 = 0x2 */
- /* .. .. ==> 0XF8006010[25:15] = 0x00000002U */
- /* .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU, 0x00014001U),
- /* .. .. reg_ddrc_t_rc = 0x1a */
- /* .. .. ==> 0XF8006014[5:0] = 0x0000001AU */
- /* .. .. ==> MASK : 0x0000003FU VAL : 0x0000001AU */
- /* .. .. reg_ddrc_t_rfc_min = 0x54 */
- /* .. .. ==> 0XF8006014[13:6] = 0x00000054U */
- /* .. .. ==> MASK : 0x00003FC0U VAL : 0x00001500U */
- /* .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 */
- /* .. .. ==> 0XF8006014[20:14] = 0x00000010U */
- /* .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU, 0x0004151AU),
- /* .. .. reg_ddrc_wr2pre = 0x12 */
- /* .. .. ==> 0XF8006018[4:0] = 0x00000012U */
- /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U */
- /* .. .. reg_ddrc_powerdown_to_x32 = 0x6 */
- /* .. .. ==> 0XF8006018[9:5] = 0x00000006U */
- /* .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U */
- /* .. .. reg_ddrc_t_faw = 0x15 */
- /* .. .. ==> 0XF8006018[15:10] = 0x00000015U */
- /* .. .. ==> MASK : 0x0000FC00U VAL : 0x00005400U */
- /* .. .. reg_ddrc_t_ras_max = 0x23 */
- /* .. .. ==> 0XF8006018[21:16] = 0x00000023U */
- /* .. .. ==> MASK : 0x003F0000U VAL : 0x00230000U */
- /* .. .. reg_ddrc_t_ras_min = 0x13 */
- /* .. .. ==> 0XF8006018[26:22] = 0x00000013U */
- /* .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U */
- /* .. .. reg_ddrc_t_cke = 0x4 */
- /* .. .. ==> 0XF8006018[31:28] = 0x00000004U */
- /* .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU, 0x44E354D2U),
- /* .. .. reg_ddrc_write_latency = 0x5 */
- /* .. .. ==> 0XF800601C[4:0] = 0x00000005U */
- /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U */
- /* .. .. reg_ddrc_rd2wr = 0x7 */
- /* .. .. ==> 0XF800601C[9:5] = 0x00000007U */
- /* .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U */
- /* .. .. reg_ddrc_wr2rd = 0xe */
- /* .. .. ==> 0XF800601C[14:10] = 0x0000000EU */
- /* .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U */
- /* .. .. reg_ddrc_t_xp = 0x4 */
- /* .. .. ==> 0XF800601C[19:15] = 0x00000004U */
- /* .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U */
- /* .. .. reg_ddrc_pad_pd = 0x0 */
- /* .. .. ==> 0XF800601C[22:20] = 0x00000000U */
- /* .. .. ==> MASK : 0x00700000U VAL : 0x00000000U */
- /* .. .. reg_ddrc_rd2pre = 0x4 */
- /* .. .. ==> 0XF800601C[27:23] = 0x00000004U */
- /* .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U */
- /* .. .. reg_ddrc_t_rcd = 0x7 */
- /* .. .. ==> 0XF800601C[31:28] = 0x00000007U */
- /* .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU, 0x720238E5U),
- /* .. .. reg_ddrc_t_ccd = 0x4 */
- /* .. .. ==> 0XF8006020[4:2] = 0x00000004U */
- /* .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U */
- /* .. .. reg_ddrc_t_rrd = 0x6 */
- /* .. .. ==> 0XF8006020[7:5] = 0x00000006U */
- /* .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U */
- /* .. .. reg_ddrc_refresh_margin = 0x2 */
- /* .. .. ==> 0XF8006020[11:8] = 0x00000002U */
- /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */
- /* .. .. reg_ddrc_t_rp = 0x7 */
- /* .. .. ==> 0XF8006020[15:12] = 0x00000007U */
- /* .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U */
- /* .. .. reg_ddrc_refresh_to_x32 = 0x8 */
- /* .. .. ==> 0XF8006020[20:16] = 0x00000008U */
- /* .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U */
- /* .. .. reg_ddrc_sdram = 0x1 */
- /* .. .. ==> 0XF8006020[21:21] = 0x00000001U */
- /* .. .. ==> MASK : 0x00200000U VAL : 0x00200000U */
- /* .. .. reg_ddrc_mobile = 0x0 */
- /* .. .. ==> 0XF8006020[22:22] = 0x00000000U */
- /* .. .. ==> MASK : 0x00400000U VAL : 0x00000000U */
- /* .. .. reg_ddrc_clock_stop_en = 0x0 */
- /* .. .. ==> 0XF8006020[23:23] = 0x00000000U */
- /* .. .. ==> MASK : 0x00800000U VAL : 0x00000000U */
- /* .. .. reg_ddrc_read_latency = 0x7 */
- /* .. .. ==> 0XF8006020[28:24] = 0x00000007U */
- /* .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U */
- /* .. .. reg_phy_mode_ddr1_ddr2 = 0x1 */
- /* .. .. ==> 0XF8006020[29:29] = 0x00000001U */
- /* .. .. ==> MASK : 0x20000000U VAL : 0x20000000U */
- /* .. .. reg_ddrc_dis_pad_pd = 0x0 */
- /* .. .. ==> 0XF8006020[30:30] = 0x00000000U */
- /* .. .. ==> MASK : 0x40000000U VAL : 0x00000000U */
- /* .. .. reg_ddrc_loopback = 0x0 */
- /* .. .. ==> 0XF8006020[31:31] = 0x00000000U */
- /* .. .. ==> MASK : 0x80000000U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU, 0x272872D0U),
- /* .. .. reg_ddrc_en_2t_timing_mode = 0x0 */
- /* .. .. ==> 0XF8006024[0:0] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. .. reg_ddrc_prefer_write = 0x0 */
- /* .. .. ==> 0XF8006024[1:1] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. .. reg_ddrc_max_rank_rd = 0xf */
- /* .. .. ==> 0XF8006024[5:2] = 0x0000000FU */
- /* .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU */
- /* .. .. reg_ddrc_mr_wr = 0x0 */
- /* .. .. ==> 0XF8006024[6:6] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000040U VAL : 0x00000000U */
- /* .. .. reg_ddrc_mr_addr = 0x0 */
- /* .. .. ==> 0XF8006024[8:7] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000180U VAL : 0x00000000U */
- /* .. .. reg_ddrc_mr_data = 0x0 */
- /* .. .. ==> 0XF8006024[24:9] = 0x00000000U */
- /* .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U */
- /* .. .. ddrc_reg_mr_wr_busy = 0x0 */
- /* .. .. ==> 0XF8006024[25:25] = 0x00000000U */
- /* .. .. ==> MASK : 0x02000000U VAL : 0x00000000U */
- /* .. .. reg_ddrc_mr_type = 0x0 */
- /* .. .. ==> 0XF8006024[26:26] = 0x00000000U */
- /* .. .. ==> MASK : 0x04000000U VAL : 0x00000000U */
- /* .. .. reg_ddrc_mr_rdata_valid = 0x0 */
- /* .. .. ==> 0XF8006024[27:27] = 0x00000000U */
- /* .. .. ==> MASK : 0x08000000U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU, 0x0000003CU),
- /* .. .. reg_ddrc_final_wait_x32 = 0x7 */
- /* .. .. ==> 0XF8006028[6:0] = 0x00000007U */
- /* .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U */
- /* .. .. reg_ddrc_pre_ocd_x32 = 0x0 */
- /* .. .. ==> 0XF8006028[10:7] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000780U VAL : 0x00000000U */
- /* .. .. reg_ddrc_t_mrd = 0x4 */
- /* .. .. ==> 0XF8006028[13:11] = 0x00000004U */
- /* .. .. ==> MASK : 0x00003800U VAL : 0x00002000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006028, 0x00003FFFU, 0x00002007U),
- /* .. .. reg_ddrc_emr2 = 0x8 */
- /* .. .. ==> 0XF800602C[15:0] = 0x00000008U */
- /* .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U */
- /* .. .. reg_ddrc_emr3 = 0x0 */
- /* .. .. ==> 0XF800602C[31:16] = 0x00000000U */
- /* .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU, 0x00000008U),
- /* .. .. reg_ddrc_mr = 0x930 */
- /* .. .. ==> 0XF8006030[15:0] = 0x00000930U */
- /* .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U */
- /* .. .. reg_ddrc_emr = 0x4 */
- /* .. .. ==> 0XF8006030[31:16] = 0x00000004U */
- /* .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU, 0x00040930U),
- /* .. .. reg_ddrc_burst_rdwr = 0x4 */
- /* .. .. ==> 0XF8006034[3:0] = 0x00000004U */
- /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U */
- /* .. .. reg_ddrc_pre_cke_x1024 = 0x167 */
- /* .. .. ==> 0XF8006034[13:4] = 0x00000167U */
- /* .. .. ==> MASK : 0x00003FF0U VAL : 0x00001670U */
- /* .. .. reg_ddrc_post_cke_x1024 = 0x1 */
- /* .. .. ==> 0XF8006034[25:16] = 0x00000001U */
- /* .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U */
- /* .. .. reg_ddrc_burstchop = 0x0 */
- /* .. .. ==> 0XF8006034[28:28] = 0x00000000U */
- /* .. .. ==> MASK : 0x10000000U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x00011674U),
- /* .. .. reg_ddrc_force_low_pri_n = 0x0 */
- /* .. .. ==> 0XF8006038[0:0] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. .. reg_ddrc_dis_dq = 0x0 */
- /* .. .. ==> 0XF8006038[1:1] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. .. reg_phy_debug_mode = 0x0 */
- /* .. .. ==> 0XF8006038[6:6] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000040U VAL : 0x00000000U */
- /* .. .. reg_phy_wr_level_start = 0x0 */
- /* .. .. ==> 0XF8006038[7:7] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000080U VAL : 0x00000000U */
- /* .. .. reg_phy_rd_level_start = 0x0 */
- /* .. .. ==> 0XF8006038[8:8] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000100U VAL : 0x00000000U */
- /* .. .. reg_phy_dq0_wait_t = 0x0 */
- /* .. .. ==> 0XF8006038[12:9] = 0x00000000U */
- /* .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006038, 0x00001FC3U, 0x00000000U),
- /* .. .. reg_ddrc_addrmap_bank_b0 = 0x7 */
- /* .. .. ==> 0XF800603C[3:0] = 0x00000007U */
- /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U */
- /* .. .. reg_ddrc_addrmap_bank_b1 = 0x7 */
- /* .. .. ==> 0XF800603C[7:4] = 0x00000007U */
- /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U */
- /* .. .. reg_ddrc_addrmap_bank_b2 = 0x7 */
- /* .. .. ==> 0XF800603C[11:8] = 0x00000007U */
- /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U */
- /* .. .. reg_ddrc_addrmap_col_b5 = 0x0 */
- /* .. .. ==> 0XF800603C[15:12] = 0x00000000U */
- /* .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U */
- /* .. .. reg_ddrc_addrmap_col_b6 = 0x0 */
- /* .. .. ==> 0XF800603C[19:16] = 0x00000000U */
- /* .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU, 0x00000777U),
- /* .. .. reg_ddrc_addrmap_col_b2 = 0x0 */
- /* .. .. ==> 0XF8006040[3:0] = 0x00000000U */
- /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U */
- /* .. .. reg_ddrc_addrmap_col_b3 = 0x0 */
- /* .. .. ==> 0XF8006040[7:4] = 0x00000000U */
- /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */
- /* .. .. reg_ddrc_addrmap_col_b4 = 0x0 */
- /* .. .. ==> 0XF8006040[11:8] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U */
- /* .. .. reg_ddrc_addrmap_col_b7 = 0x0 */
- /* .. .. ==> 0XF8006040[15:12] = 0x00000000U */
- /* .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U */
- /* .. .. reg_ddrc_addrmap_col_b8 = 0x0 */
- /* .. .. ==> 0XF8006040[19:16] = 0x00000000U */
- /* .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U */
- /* .. .. reg_ddrc_addrmap_col_b9 = 0xf */
- /* .. .. ==> 0XF8006040[23:20] = 0x0000000FU */
- /* .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U */
- /* .. .. reg_ddrc_addrmap_col_b10 = 0xf */
- /* .. .. ==> 0XF8006040[27:24] = 0x0000000FU */
- /* .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U */
- /* .. .. reg_ddrc_addrmap_col_b11 = 0xf */
- /* .. .. ==> 0XF8006040[31:28] = 0x0000000FU */
- /* .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU, 0xFFF00000U),
- /* .. .. reg_ddrc_addrmap_row_b0 = 0x6 */
- /* .. .. ==> 0XF8006044[3:0] = 0x00000006U */
- /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U */
- /* .. .. reg_ddrc_addrmap_row_b1 = 0x6 */
- /* .. .. ==> 0XF8006044[7:4] = 0x00000006U */
- /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U */
- /* .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 */
- /* .. .. ==> 0XF8006044[11:8] = 0x00000006U */
- /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U */
- /* .. .. reg_ddrc_addrmap_row_b12 = 0x6 */
- /* .. .. ==> 0XF8006044[15:12] = 0x00000006U */
- /* .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U */
- /* .. .. reg_ddrc_addrmap_row_b13 = 0x6 */
- /* .. .. ==> 0XF8006044[19:16] = 0x00000006U */
- /* .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U */
- /* .. .. reg_ddrc_addrmap_row_b14 = 0xf */
- /* .. .. ==> 0XF8006044[23:20] = 0x0000000FU */
- /* .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U */
- /* .. .. reg_ddrc_addrmap_row_b15 = 0xf */
- /* .. .. ==> 0XF8006044[27:24] = 0x0000000FU */
- /* .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU, 0x0FF66666U),
- /* .. .. reg_ddrc_rank0_rd_odt = 0x0 */
- /* .. .. ==> 0XF8006048[2:0] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000007U VAL : 0x00000000U */
- /* .. .. reg_ddrc_rank0_wr_odt = 0x1 */
- /* .. .. ==> 0XF8006048[5:3] = 0x00000001U */
- /* .. .. ==> MASK : 0x00000038U VAL : 0x00000008U */
- /* .. .. reg_ddrc_rank1_rd_odt = 0x1 */
- /* .. .. ==> 0XF8006048[8:6] = 0x00000001U */
- /* .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U */
- /* .. .. reg_ddrc_rank1_wr_odt = 0x1 */
- /* .. .. ==> 0XF8006048[11:9] = 0x00000001U */
- /* .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
- /* .. .. reg_phy_rd_local_odt = 0x0 */
- /* .. .. ==> 0XF8006048[13:12] = 0x00000000U */
- /* .. .. ==> MASK : 0x00003000U VAL : 0x00000000U */
- /* .. .. reg_phy_wr_local_odt = 0x3 */
- /* .. .. ==> 0XF8006048[15:14] = 0x00000003U */
- /* .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U */
- /* .. .. reg_phy_idle_local_odt = 0x3 */
- /* .. .. ==> 0XF8006048[17:16] = 0x00000003U */
- /* .. .. ==> MASK : 0x00030000U VAL : 0x00030000U */
- /* .. .. reg_ddrc_rank2_rd_odt = 0x0 */
- /* .. .. ==> 0XF8006048[20:18] = 0x00000000U */
- /* .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U */
- /* .. .. reg_ddrc_rank2_wr_odt = 0x0 */
- /* .. .. ==> 0XF8006048[23:21] = 0x00000000U */
- /* .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U */
- /* .. .. reg_ddrc_rank3_rd_odt = 0x0 */
- /* .. .. ==> 0XF8006048[26:24] = 0x00000000U */
- /* .. .. ==> MASK : 0x07000000U VAL : 0x00000000U */
- /* .. .. reg_ddrc_rank3_wr_odt = 0x0 */
- /* .. .. ==> 0XF8006048[29:27] = 0x00000000U */
- /* .. .. ==> MASK : 0x38000000U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU, 0x0003C248U),
- /* .. .. reg_phy_rd_cmd_to_data = 0x0 */
- /* .. .. ==> 0XF8006050[3:0] = 0x00000000U */
- /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U */
- /* .. .. reg_phy_wr_cmd_to_data = 0x0 */
- /* .. .. ==> 0XF8006050[7:4] = 0x00000000U */
- /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */
- /* .. .. reg_phy_rdc_we_to_re_delay = 0x8 */
- /* .. .. ==> 0XF8006050[11:8] = 0x00000008U */
- /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U */
- /* .. .. reg_phy_rdc_fifo_rst_disable = 0x0 */
- /* .. .. ==> 0XF8006050[15:15] = 0x00000000U */
- /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */
- /* .. .. reg_phy_use_fixed_re = 0x1 */
- /* .. .. ==> 0XF8006050[16:16] = 0x00000001U */
- /* .. .. ==> MASK : 0x00010000U VAL : 0x00010000U */
- /* .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 */
- /* .. .. ==> 0XF8006050[17:17] = 0x00000000U */
- /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
- /* .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 */
- /* .. .. ==> 0XF8006050[18:18] = 0x00000000U */
- /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
- /* .. .. reg_phy_clk_stall_level = 0x0 */
- /* .. .. ==> 0XF8006050[19:19] = 0x00000000U */
- /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */
- /* .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 */
- /* .. .. ==> 0XF8006050[27:24] = 0x00000007U */
- /* .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U */
- /* .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 */
- /* .. .. ==> 0XF8006050[31:28] = 0x00000007U */
- /* .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU, 0x77010800U),
- /* .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1 */
- /* .. .. ==> 0XF8006058[7:0] = 0x00000001U */
- /* .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U */
- /* .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1 */
- /* .. .. ==> 0XF8006058[15:8] = 0x00000001U */
- /* .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U */
- /* .. .. reg_ddrc_dis_dll_calib = 0x0 */
- /* .. .. ==> 0XF8006058[16:16] = 0x00000000U */
- /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU, 0x00000101U),
- /* .. .. reg_ddrc_rd_odt_delay = 0x3 */
- /* .. .. ==> 0XF800605C[3:0] = 0x00000003U */
- /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U */
- /* .. .. reg_ddrc_wr_odt_delay = 0x0 */
- /* .. .. ==> 0XF800605C[7:4] = 0x00000000U */
- /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */
- /* .. .. reg_ddrc_rd_odt_hold = 0x0 */
- /* .. .. ==> 0XF800605C[11:8] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U */
- /* .. .. reg_ddrc_wr_odt_hold = 0x5 */
- /* .. .. ==> 0XF800605C[15:12] = 0x00000005U */
- /* .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU, 0x00005003U),
- /* .. .. reg_ddrc_pageclose = 0x0 */
- /* .. .. ==> 0XF8006060[0:0] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. .. reg_ddrc_lpr_num_entries = 0x1f */
- /* .. .. ==> 0XF8006060[6:1] = 0x0000001FU */
- /* .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU */
- /* .. .. reg_ddrc_auto_pre_en = 0x0 */
- /* .. .. ==> 0XF8006060[7:7] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000080U VAL : 0x00000000U */
- /* .. .. reg_ddrc_refresh_update_level = 0x0 */
- /* .. .. ==> 0XF8006060[8:8] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000100U VAL : 0x00000000U */
- /* .. .. reg_ddrc_dis_wc = 0x0 */
- /* .. .. ==> 0XF8006060[9:9] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000200U VAL : 0x00000000U */
- /* .. .. reg_ddrc_dis_collision_page_opt = 0x0 */
- /* .. .. ==> 0XF8006060[10:10] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
- /* .. .. reg_ddrc_selfref_en = 0x0 */
- /* .. .. ==> 0XF8006060[12:12] = 0x00000000U */
- /* .. .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006060, 0x000017FFU, 0x0000003EU),
- /* .. .. reg_ddrc_go2critical_hysteresis = 0x0 */
- /* .. .. ==> 0XF8006064[12:5] = 0x00000000U */
- /* .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U */
- /* .. .. reg_arb_go2critical_en = 0x1 */
- /* .. .. ==> 0XF8006064[17:17] = 0x00000001U */
- /* .. .. ==> MASK : 0x00020000U VAL : 0x00020000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006064, 0x00021FE0U, 0x00020000U),
- /* .. .. reg_ddrc_wrlvl_ww = 0x41 */
- /* .. .. ==> 0XF8006068[7:0] = 0x00000041U */
- /* .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U */
- /* .. .. reg_ddrc_rdlvl_rr = 0x41 */
- /* .. .. ==> 0XF8006068[15:8] = 0x00000041U */
- /* .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U */
- /* .. .. reg_ddrc_dfi_t_wlmrd = 0x28 */
- /* .. .. ==> 0XF8006068[25:16] = 0x00000028U */
- /* .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU, 0x00284141U),
- /* .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 */
- /* .. .. ==> 0XF800606C[7:0] = 0x00000010U */
- /* .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U */
- /* .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 */
- /* .. .. ==> 0XF800606C[15:8] = 0x00000016U */
- /* .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U */
- /* .. .. */
- EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU, 0x00001610U),
- /* .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1 */
- /* .. .. ==> 0XF8006078[3:0] = 0x00000001U */
- /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U */
- /* .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1 */
- /* .. .. ==> 0XF8006078[7:4] = 0x00000001U */
- /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U */
- /* .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1 */
- /* .. .. ==> 0XF8006078[11:8] = 0x00000001U */
- /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U */
- /* .. .. reg_ddrc_t_cksre = 0x6 */
- /* .. .. ==> 0XF8006078[15:12] = 0x00000006U */
- /* .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U */
- /* .. .. reg_ddrc_t_cksrx = 0x6 */
- /* .. .. ==> 0XF8006078[19:16] = 0x00000006U */
- /* .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U */
- /* .. .. reg_ddrc_t_ckesr = 0x4 */
- /* .. .. ==> 0XF8006078[25:20] = 0x00000004U */
- /* .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU, 0x00466111U),
- /* .. .. reg_ddrc_t_ckpde = 0x2 */
- /* .. .. ==> 0XF800607C[3:0] = 0x00000002U */
- /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U */
- /* .. .. reg_ddrc_t_ckpdx = 0x2 */
- /* .. .. ==> 0XF800607C[7:4] = 0x00000002U */
- /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U */
- /* .. .. reg_ddrc_t_ckdpde = 0x2 */
- /* .. .. ==> 0XF800607C[11:8] = 0x00000002U */
- /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */
- /* .. .. reg_ddrc_t_ckdpdx = 0x2 */
- /* .. .. ==> 0XF800607C[15:12] = 0x00000002U */
- /* .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U */
- /* .. .. reg_ddrc_t_ckcsx = 0x3 */
- /* .. .. ==> 0XF800607C[19:16] = 0x00000003U */
- /* .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU, 0x00032222U),
- /* .. .. refresh_timer0_start_value_x32 = 0x0 */
- /* .. .. ==> 0XF80060A0[11:0] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U */
- /* .. .. refresh_timer1_start_value_x32 = 0x8 */
- /* .. .. ==> 0XF80060A0[23:12] = 0x00000008U */
- /* .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU, 0x00008000U),
- /* .. .. reg_ddrc_dis_auto_zq = 0x0 */
- /* .. .. ==> 0XF80060A4[0:0] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. .. reg_ddrc_ddr3 = 0x1 */
- /* .. .. ==> 0XF80060A4[1:1] = 0x00000001U */
- /* .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */
- /* .. .. reg_ddrc_t_mod = 0x200 */
- /* .. .. ==> 0XF80060A4[11:2] = 0x00000200U */
- /* .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U */
- /* .. .. reg_ddrc_t_zq_long_nop = 0x200 */
- /* .. .. ==> 0XF80060A4[21:12] = 0x00000200U */
- /* .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U */
- /* .. .. reg_ddrc_t_zq_short_nop = 0x40 */
- /* .. .. ==> 0XF80060A4[31:22] = 0x00000040U */
- /* .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U),
- /* .. .. t_zq_short_interval_x1024 = 0xc845 */
- /* .. .. ==> 0XF80060A8[19:0] = 0x0000C845U */
- /* .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000C845U */
- /* .. .. dram_rstn_x1024 = 0x67 */
- /* .. .. ==> 0XF80060A8[27:20] = 0x00000067U */
- /* .. .. ==> MASK : 0x0FF00000U VAL : 0x06700000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0670C845U),
- /* .. .. deeppowerdown_en = 0x0 */
- /* .. .. ==> 0XF80060AC[0:0] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. .. deeppowerdown_to_x1024 = 0xff */
- /* .. .. ==> 0XF80060AC[8:1] = 0x000000FFU */
- /* .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU */
- /* .. .. */
- EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU),
- /* .. .. dfi_wrlvl_max_x1024 = 0xfff */
- /* .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU */
- /* .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU */
- /* .. .. dfi_rdlvl_max_x1024 = 0xfff */
- /* .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU */
- /* .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U */
- /* .. .. ddrc_reg_twrlvl_max_error = 0x0 */
- /* .. .. ==> 0XF80060B0[24:24] = 0x00000000U */
- /* .. .. ==> MASK : 0x01000000U VAL : 0x00000000U */
- /* .. .. ddrc_reg_trdlvl_max_error = 0x0 */
- /* .. .. ==> 0XF80060B0[25:25] = 0x00000000U */
- /* .. .. ==> MASK : 0x02000000U VAL : 0x00000000U */
- /* .. .. reg_ddrc_dfi_wr_level_en = 0x1 */
- /* .. .. ==> 0XF80060B0[26:26] = 0x00000001U */
- /* .. .. ==> MASK : 0x04000000U VAL : 0x04000000U */
- /* .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 */
- /* .. .. ==> 0XF80060B0[27:27] = 0x00000001U */
- /* .. .. ==> MASK : 0x08000000U VAL : 0x08000000U */
- /* .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 */
- /* .. .. ==> 0XF80060B0[28:28] = 0x00000001U */
- /* .. .. ==> MASK : 0x10000000U VAL : 0x10000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
- /* .. .. reg_ddrc_2t_delay = 0x0 */
- /* .. .. ==> 0XF80060B4[8:0] = 0x00000000U */
- /* .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U */
- /* .. .. reg_ddrc_skip_ocd = 0x1 */
- /* .. .. ==> 0XF80060B4[9:9] = 0x00000001U */
- /* .. .. ==> MASK : 0x00000200U VAL : 0x00000200U */
- /* .. .. reg_ddrc_dis_pre_bypass = 0x0 */
- /* .. .. ==> 0XF80060B4[10:10] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF80060B4, 0x000007FFU, 0x00000200U),
- /* .. .. reg_ddrc_dfi_t_rddata_en = 0x6 */
- /* .. .. ==> 0XF80060B8[4:0] = 0x00000006U */
- /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U */
- /* .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 */
- /* .. .. ==> 0XF80060B8[14:5] = 0x00000003U */
- /* .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U */
- /* .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 */
- /* .. .. ==> 0XF80060B8[24:15] = 0x00000040U */
- /* .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU, 0x00200066U),
- /* .. .. START: RESET ECC ERROR */
- /* .. .. Clear_Uncorrectable_DRAM_ECC_error = 1 */
- /* .. .. ==> 0XF80060C4[0:0] = 0x00000001U */
- /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
- /* .. .. Clear_Correctable_DRAM_ECC_error = 1 */
- /* .. .. ==> 0XF80060C4[1:1] = 0x00000001U */
- /* .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */
- /* .. .. */
- EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000003U),
- /* .. .. FINISH: RESET ECC ERROR */
- /* .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 */
- /* .. .. ==> 0XF80060C4[0:0] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. .. Clear_Correctable_DRAM_ECC_error = 0x0 */
- /* .. .. ==> 0XF80060C4[1:1] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000000U),
- /* .. .. CORR_ECC_LOG_VALID = 0x0 */
- /* .. .. ==> 0XF80060C8[0:0] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. .. ECC_CORRECTED_BIT_NUM = 0x0 */
- /* .. .. ==> 0XF80060C8[7:1] = 0x00000000U */
- /* .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF80060C8, 0x000000FFU, 0x00000000U),
- /* .. .. UNCORR_ECC_LOG_VALID = 0x0 */
- /* .. .. ==> 0XF80060DC[0:0] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF80060DC, 0x00000001U, 0x00000000U),
- /* .. .. STAT_NUM_CORR_ERR = 0x0 */
- /* .. .. ==> 0XF80060F0[15:8] = 0x00000000U */
- /* .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U */
- /* .. .. STAT_NUM_UNCORR_ERR = 0x0 */
- /* .. .. ==> 0XF80060F0[7:0] = 0x00000000U */
- /* .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU, 0x00000000U),
- /* .. .. reg_ddrc_ecc_mode = 0x0 */
- /* .. .. ==> 0XF80060F4[2:0] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000007U VAL : 0x00000000U */
- /* .. .. reg_ddrc_dis_scrub = 0x1 */
- /* .. .. ==> 0XF80060F4[3:3] = 0x00000001U */
- /* .. .. ==> MASK : 0x00000008U VAL : 0x00000008U */
- /* .. .. */
- EMIT_MASKWRITE(0XF80060F4, 0x0000000FU, 0x00000008U),
- /* .. .. reg_phy_dif_on = 0x0 */
- /* .. .. ==> 0XF8006114[3:0] = 0x00000000U */
- /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U */
- /* .. .. reg_phy_dif_off = 0x0 */
- /* .. .. ==> 0XF8006114[7:4] = 0x00000000U */
- /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006114, 0x000000FFU, 0x00000000U),
- /* .. .. reg_phy_data_slice_in_use = 0x1 */
- /* .. .. ==> 0XF8006118[0:0] = 0x00000001U */
- /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
- /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
- /* .. .. ==> 0XF8006118[1:1] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
- /* .. .. ==> 0XF8006118[2:2] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
- /* .. .. ==> 0XF8006118[3:3] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */
- /* .. .. reg_phy_board_lpbk_tx = 0x0 */
- /* .. .. ==> 0XF8006118[4:4] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
- /* .. .. reg_phy_board_lpbk_rx = 0x0 */
- /* .. .. ==> 0XF8006118[5:5] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000020U VAL : 0x00000000U */
- /* .. .. reg_phy_bist_shift_dq = 0x0 */
- /* .. .. ==> 0XF8006118[14:6] = 0x00000000U */
- /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */
- /* .. .. reg_phy_bist_err_clr = 0x0 */
- /* .. .. ==> 0XF8006118[23:15] = 0x00000000U */
- /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */
- /* .. .. reg_phy_dq_offset = 0x40 */
- /* .. .. ==> 0XF8006118[30:24] = 0x00000040U */
- /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU, 0x40000001U),
- /* .. .. reg_phy_data_slice_in_use = 0x1 */
- /* .. .. ==> 0XF800611C[0:0] = 0x00000001U */
- /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
- /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
- /* .. .. ==> 0XF800611C[1:1] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
- /* .. .. ==> 0XF800611C[2:2] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
- /* .. .. ==> 0XF800611C[3:3] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */
- /* .. .. reg_phy_board_lpbk_tx = 0x0 */
- /* .. .. ==> 0XF800611C[4:4] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
- /* .. .. reg_phy_board_lpbk_rx = 0x0 */
- /* .. .. ==> 0XF800611C[5:5] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000020U VAL : 0x00000000U */
- /* .. .. reg_phy_bist_shift_dq = 0x0 */
- /* .. .. ==> 0XF800611C[14:6] = 0x00000000U */
- /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */
- /* .. .. reg_phy_bist_err_clr = 0x0 */
- /* .. .. ==> 0XF800611C[23:15] = 0x00000000U */
- /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */
- /* .. .. reg_phy_dq_offset = 0x40 */
- /* .. .. ==> 0XF800611C[30:24] = 0x00000040U */
- /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU, 0x40000001U),
- /* .. .. reg_phy_data_slice_in_use = 0x1 */
- /* .. .. ==> 0XF8006120[0:0] = 0x00000001U */
- /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
- /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
- /* .. .. ==> 0XF8006120[1:1] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
- /* .. .. ==> 0XF8006120[2:2] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
- /* .. .. ==> 0XF8006120[3:3] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */
- /* .. .. reg_phy_board_lpbk_tx = 0x0 */
- /* .. .. ==> 0XF8006120[4:4] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
- /* .. .. reg_phy_board_lpbk_rx = 0x0 */
- /* .. .. ==> 0XF8006120[5:5] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000020U VAL : 0x00000000U */
- /* .. .. reg_phy_bist_shift_dq = 0x0 */
- /* .. .. ==> 0XF8006120[14:6] = 0x00000000U */
- /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */
- /* .. .. reg_phy_bist_err_clr = 0x0 */
- /* .. .. ==> 0XF8006120[23:15] = 0x00000000U */
- /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */
- /* .. .. reg_phy_dq_offset = 0x40 */
- /* .. .. ==> 0XF8006120[30:24] = 0x00000040U */
- /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */
- /* .. .. reg_phy_data_slice_in_use = 0x1 */
- /* .. .. ==> 0XF8006120[0:0] = 0x00000001U */
- /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
- /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
- /* .. .. ==> 0XF8006120[1:1] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
- /* .. .. ==> 0XF8006120[2:2] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
- /* .. .. ==> 0XF8006120[3:3] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */
- /* .. .. reg_phy_board_lpbk_tx = 0x0 */
- /* .. .. ==> 0XF8006120[4:4] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
- /* .. .. reg_phy_board_lpbk_rx = 0x0 */
- /* .. .. ==> 0XF8006120[5:5] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000020U VAL : 0x00000000U */
- /* .. .. reg_phy_bist_shift_dq = 0x0 */
- /* .. .. ==> 0XF8006120[14:6] = 0x00000000U */
- /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */
- /* .. .. reg_phy_bist_err_clr = 0x0 */
- /* .. .. ==> 0XF8006120[23:15] = 0x00000000U */
- /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */
- /* .. .. reg_phy_dq_offset = 0x40 */
- /* .. .. ==> 0XF8006120[30:24] = 0x00000040U */
- /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU, 0x40000001U),
- /* .. .. reg_phy_data_slice_in_use = 0x1 */
- /* .. .. ==> 0XF8006124[0:0] = 0x00000001U */
- /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
- /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
- /* .. .. ==> 0XF8006124[1:1] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
- /* .. .. ==> 0XF8006124[2:2] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
- /* .. .. ==> 0XF8006124[3:3] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */
- /* .. .. reg_phy_board_lpbk_tx = 0x0 */
- /* .. .. ==> 0XF8006124[4:4] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
- /* .. .. reg_phy_board_lpbk_rx = 0x0 */
- /* .. .. ==> 0XF8006124[5:5] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000020U VAL : 0x00000000U */
- /* .. .. reg_phy_bist_shift_dq = 0x0 */
- /* .. .. ==> 0XF8006124[14:6] = 0x00000000U */
- /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */
- /* .. .. reg_phy_bist_err_clr = 0x0 */
- /* .. .. ==> 0XF8006124[23:15] = 0x00000000U */
- /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */
- /* .. .. reg_phy_dq_offset = 0x40 */
- /* .. .. ==> 0XF8006124[30:24] = 0x00000040U */
- /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU, 0x40000001U),
- /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
- /* .. .. ==> 0XF800612C[9:0] = 0x00000000U */
- /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */
- /* .. .. reg_phy_gatelvl_init_ratio = 0x8f */
- /* .. .. ==> 0XF800612C[19:10] = 0x0000008FU */
- /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00023C00U */
- /* .. .. */
- EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU, 0x00023C00U),
- /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
- /* .. .. ==> 0XF8006130[9:0] = 0x00000000U */
- /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */
- /* .. .. reg_phy_gatelvl_init_ratio = 0x8a */
- /* .. .. ==> 0XF8006130[19:10] = 0x0000008AU */
- /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00022800U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU, 0x00022800U),
- /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
- /* .. .. ==> 0XF8006134[9:0] = 0x00000000U */
- /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */
- /* .. .. reg_phy_gatelvl_init_ratio = 0x8b */
- /* .. .. ==> 0XF8006134[19:10] = 0x0000008BU */
- /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00022C00U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU, 0x00022C00U),
- /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
- /* .. .. ==> 0XF8006138[9:0] = 0x00000000U */
- /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */
- /* .. .. reg_phy_gatelvl_init_ratio = 0x92 */
- /* .. .. ==> 0XF8006138[19:10] = 0x00000092U */
- /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00024800U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU, 0x00024800U),
- /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
- /* .. .. ==> 0XF8006140[9:0] = 0x00000035U */
- /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */
- /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
- /* .. .. ==> 0XF8006140[10:10] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
- /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
- /* .. .. ==> 0XF8006140[19:11] = 0x00000000U */
- /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU, 0x00000035U),
- /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
- /* .. .. ==> 0XF8006144[9:0] = 0x00000035U */
- /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */
- /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
- /* .. .. ==> 0XF8006144[10:10] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
- /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
- /* .. .. ==> 0XF8006144[19:11] = 0x00000000U */
- /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU, 0x00000035U),
- /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
- /* .. .. ==> 0XF8006148[9:0] = 0x00000035U */
- /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */
- /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
- /* .. .. ==> 0XF8006148[10:10] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
- /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
- /* .. .. ==> 0XF8006148[19:11] = 0x00000000U */
- /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU, 0x00000035U),
- /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
- /* .. .. ==> 0XF800614C[9:0] = 0x00000035U */
- /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */
- /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
- /* .. .. ==> 0XF800614C[10:10] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
- /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
- /* .. .. ==> 0XF800614C[19:11] = 0x00000000U */
- /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU, 0x00000035U),
- /* .. .. reg_phy_wr_dqs_slave_ratio = 0x77 */
- /* .. .. ==> 0XF8006154[9:0] = 0x00000077U */
- /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000077U */
- /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
- /* .. .. ==> 0XF8006154[10:10] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
- /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
- /* .. .. ==> 0XF8006154[19:11] = 0x00000000U */
- /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU, 0x00000077U),
- /* .. .. reg_phy_wr_dqs_slave_ratio = 0x7c */
- /* .. .. ==> 0XF8006158[9:0] = 0x0000007CU */
- /* .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU */
- /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
- /* .. .. ==> 0XF8006158[10:10] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
- /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
- /* .. .. ==> 0XF8006158[19:11] = 0x00000000U */
- /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU, 0x0000007CU),
- /* .. .. reg_phy_wr_dqs_slave_ratio = 0x7c */
- /* .. .. ==> 0XF800615C[9:0] = 0x0000007CU */
- /* .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU */
- /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
- /* .. .. ==> 0XF800615C[10:10] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
- /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
- /* .. .. ==> 0XF800615C[19:11] = 0x00000000U */
- /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU, 0x0000007CU),
- /* .. .. reg_phy_wr_dqs_slave_ratio = 0x75 */
- /* .. .. ==> 0XF8006160[9:0] = 0x00000075U */
- /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000075U */
- /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
- /* .. .. ==> 0XF8006160[10:10] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
- /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
- /* .. .. ==> 0XF8006160[19:11] = 0x00000000U */
- /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU, 0x00000075U),
- /* .. .. reg_phy_fifo_we_slave_ratio = 0xe4 */
- /* .. .. ==> 0XF8006168[10:0] = 0x000000E4U */
- /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000E4U */
- /* .. .. reg_phy_fifo_we_in_force = 0x0 */
- /* .. .. ==> 0XF8006168[11:11] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */
- /* .. .. reg_phy_fifo_we_in_delay = 0x0 */
- /* .. .. ==> 0XF8006168[20:12] = 0x00000000U */
- /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU, 0x000000E4U),
- /* .. .. reg_phy_fifo_we_slave_ratio = 0xdf */
- /* .. .. ==> 0XF800616C[10:0] = 0x000000DFU */
- /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000DFU */
- /* .. .. reg_phy_fifo_we_in_force = 0x0 */
- /* .. .. ==> 0XF800616C[11:11] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */
- /* .. .. reg_phy_fifo_we_in_delay = 0x0 */
- /* .. .. ==> 0XF800616C[20:12] = 0x00000000U */
- /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU, 0x000000DFU),
- /* .. .. reg_phy_fifo_we_slave_ratio = 0xe0 */
- /* .. .. ==> 0XF8006170[10:0] = 0x000000E0U */
- /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000E0U */
- /* .. .. reg_phy_fifo_we_in_force = 0x0 */
- /* .. .. ==> 0XF8006170[11:11] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */
- /* .. .. reg_phy_fifo_we_in_delay = 0x0 */
- /* .. .. ==> 0XF8006170[20:12] = 0x00000000U */
- /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU, 0x000000E0U),
- /* .. .. reg_phy_fifo_we_slave_ratio = 0xe7 */
- /* .. .. ==> 0XF8006174[10:0] = 0x000000E7U */
- /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000E7U */
- /* .. .. reg_phy_fifo_we_in_force = 0x0 */
- /* .. .. ==> 0XF8006174[11:11] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */
- /* .. .. reg_phy_fifo_we_in_delay = 0x0 */
- /* .. .. ==> 0XF8006174[20:12] = 0x00000000U */
- /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU, 0x000000E7U),
- /* .. .. reg_phy_wr_data_slave_ratio = 0xb7 */
- /* .. .. ==> 0XF800617C[9:0] = 0x000000B7U */
- /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000B7U */
- /* .. .. reg_phy_wr_data_slave_force = 0x0 */
- /* .. .. ==> 0XF800617C[10:10] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
- /* .. .. reg_phy_wr_data_slave_delay = 0x0 */
- /* .. .. ==> 0XF800617C[19:11] = 0x00000000U */
- /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU, 0x000000B7U),
- /* .. .. reg_phy_wr_data_slave_ratio = 0xbc */
- /* .. .. ==> 0XF8006180[9:0] = 0x000000BCU */
- /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU */
- /* .. .. reg_phy_wr_data_slave_force = 0x0 */
- /* .. .. ==> 0XF8006180[10:10] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
- /* .. .. reg_phy_wr_data_slave_delay = 0x0 */
- /* .. .. ==> 0XF8006180[19:11] = 0x00000000U */
- /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU, 0x000000BCU),
- /* .. .. reg_phy_wr_data_slave_ratio = 0xbc */
- /* .. .. ==> 0XF8006184[9:0] = 0x000000BCU */
- /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU */
- /* .. .. reg_phy_wr_data_slave_force = 0x0 */
- /* .. .. ==> 0XF8006184[10:10] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
- /* .. .. reg_phy_wr_data_slave_delay = 0x0 */
- /* .. .. ==> 0XF8006184[19:11] = 0x00000000U */
- /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU, 0x000000BCU),
- /* .. .. reg_phy_wr_data_slave_ratio = 0xb5 */
- /* .. .. ==> 0XF8006188[9:0] = 0x000000B5U */
- /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000B5U */
- /* .. .. reg_phy_wr_data_slave_force = 0x0 */
- /* .. .. ==> 0XF8006188[10:10] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
- /* .. .. reg_phy_wr_data_slave_delay = 0x0 */
- /* .. .. ==> 0XF8006188[19:11] = 0x00000000U */
- /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU, 0x000000B5U),
- /* .. .. reg_phy_loopback = 0x0 */
- /* .. .. ==> 0XF8006190[0:0] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. .. reg_phy_bl2 = 0x0 */
- /* .. .. ==> 0XF8006190[1:1] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. .. reg_phy_at_spd_atpg = 0x0 */
- /* .. .. ==> 0XF8006190[2:2] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. .. reg_phy_bist_enable = 0x0 */
- /* .. .. ==> 0XF8006190[3:3] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */
- /* .. .. reg_phy_bist_force_err = 0x0 */
- /* .. .. ==> 0XF8006190[4:4] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
- /* .. .. reg_phy_bist_mode = 0x0 */
- /* .. .. ==> 0XF8006190[6:5] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000060U VAL : 0x00000000U */
- /* .. .. reg_phy_invert_clkout = 0x1 */
- /* .. .. ==> 0XF8006190[7:7] = 0x00000001U */
- /* .. .. ==> MASK : 0x00000080U VAL : 0x00000080U */
- /* .. .. reg_phy_all_dq_mpr_rd_resp = 0x0 */
- /* .. .. ==> 0XF8006190[8:8] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000100U VAL : 0x00000000U */
- /* .. .. reg_phy_sel_logic = 0x0 */
- /* .. .. ==> 0XF8006190[9:9] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000200U VAL : 0x00000000U */
- /* .. .. reg_phy_ctrl_slave_ratio = 0x100 */
- /* .. .. ==> 0XF8006190[19:10] = 0x00000100U */
- /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U */
- /* .. .. reg_phy_ctrl_slave_force = 0x0 */
- /* .. .. ==> 0XF8006190[20:20] = 0x00000000U */
- /* .. .. ==> MASK : 0x00100000U VAL : 0x00000000U */
- /* .. .. reg_phy_ctrl_slave_delay = 0x0 */
- /* .. .. ==> 0XF8006190[27:21] = 0x00000000U */
- /* .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U */
- /* .. .. reg_phy_use_rank0_delays = 0x1 */
- /* .. .. ==> 0XF8006190[28:28] = 0x00000001U */
- /* .. .. ==> MASK : 0x10000000U VAL : 0x10000000U */
- /* .. .. reg_phy_lpddr = 0x0 */
- /* .. .. ==> 0XF8006190[29:29] = 0x00000000U */
- /* .. .. ==> MASK : 0x20000000U VAL : 0x00000000U */
- /* .. .. reg_phy_cmd_latency = 0x0 */
- /* .. .. ==> 0XF8006190[30:30] = 0x00000000U */
- /* .. .. ==> MASK : 0x40000000U VAL : 0x00000000U */
- /* .. .. reg_phy_int_lpbk = 0x0 */
- /* .. .. ==> 0XF8006190[31:31] = 0x00000000U */
- /* .. .. ==> MASK : 0x80000000U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU, 0x10040080U),
- /* .. .. reg_phy_wr_rl_delay = 0x2 */
- /* .. .. ==> 0XF8006194[4:0] = 0x00000002U */
- /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U */
- /* .. .. reg_phy_rd_rl_delay = 0x4 */
- /* .. .. ==> 0XF8006194[9:5] = 0x00000004U */
- /* .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U */
- /* .. .. reg_phy_dll_lock_diff = 0xf */
- /* .. .. ==> 0XF8006194[13:10] = 0x0000000FU */
- /* .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U */
- /* .. .. reg_phy_use_wr_level = 0x1 */
- /* .. .. ==> 0XF8006194[14:14] = 0x00000001U */
- /* .. .. ==> MASK : 0x00004000U VAL : 0x00004000U */
- /* .. .. reg_phy_use_rd_dqs_gate_level = 0x1 */
- /* .. .. ==> 0XF8006194[15:15] = 0x00000001U */
- /* .. .. ==> MASK : 0x00008000U VAL : 0x00008000U */
- /* .. .. reg_phy_use_rd_data_eye_level = 0x1 */
- /* .. .. ==> 0XF8006194[16:16] = 0x00000001U */
- /* .. .. ==> MASK : 0x00010000U VAL : 0x00010000U */
- /* .. .. reg_phy_dis_calib_rst = 0x0 */
- /* .. .. ==> 0XF8006194[17:17] = 0x00000000U */
- /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
- /* .. .. reg_phy_ctrl_slave_delay = 0x0 */
- /* .. .. ==> 0XF8006194[19:18] = 0x00000000U */
- /* .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU, 0x0001FC82U),
- /* .. .. reg_arb_page_addr_mask = 0x0 */
- /* .. .. ==> 0XF8006204[31:0] = 0x00000000U */
- /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU, 0x00000000U),
- /* .. .. reg_arb_pri_wr_portn = 0x3ff */
- /* .. .. ==> 0XF8006208[9:0] = 0x000003FFU */
- /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
- /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
- /* .. .. ==> 0XF8006208[16:16] = 0x00000000U */
- /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
- /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
- /* .. .. ==> 0XF8006208[17:17] = 0x00000000U */
- /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
- /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
- /* .. .. ==> 0XF8006208[18:18] = 0x00000000U */
- /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
- /* .. .. reg_arb_dis_rmw_portn = 0x1 */
- /* .. .. ==> 0XF8006208[19:19] = 0x00000001U */
- /* .. .. ==> MASK : 0x00080000U VAL : 0x00080000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006208, 0x000F03FFU, 0x000803FFU),
- /* .. .. reg_arb_pri_wr_portn = 0x3ff */
- /* .. .. ==> 0XF800620C[9:0] = 0x000003FFU */
- /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
- /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
- /* .. .. ==> 0XF800620C[16:16] = 0x00000000U */
- /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
- /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
- /* .. .. ==> 0XF800620C[17:17] = 0x00000000U */
- /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
- /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
- /* .. .. ==> 0XF800620C[18:18] = 0x00000000U */
- /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
- /* .. .. reg_arb_dis_rmw_portn = 0x1 */
- /* .. .. ==> 0XF800620C[19:19] = 0x00000001U */
- /* .. .. ==> MASK : 0x00080000U VAL : 0x00080000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF800620C, 0x000F03FFU, 0x000803FFU),
- /* .. .. reg_arb_pri_wr_portn = 0x3ff */
- /* .. .. ==> 0XF8006210[9:0] = 0x000003FFU */
- /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
- /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
- /* .. .. ==> 0XF8006210[16:16] = 0x00000000U */
- /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
- /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
- /* .. .. ==> 0XF8006210[17:17] = 0x00000000U */
- /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
- /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
- /* .. .. ==> 0XF8006210[18:18] = 0x00000000U */
- /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
- /* .. .. reg_arb_dis_rmw_portn = 0x1 */
- /* .. .. ==> 0XF8006210[19:19] = 0x00000001U */
- /* .. .. ==> MASK : 0x00080000U VAL : 0x00080000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006210, 0x000F03FFU, 0x000803FFU),
- /* .. .. reg_arb_pri_wr_portn = 0x3ff */
- /* .. .. ==> 0XF8006214[9:0] = 0x000003FFU */
- /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
- /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
- /* .. .. ==> 0XF8006214[16:16] = 0x00000000U */
- /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
- /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
- /* .. .. ==> 0XF8006214[17:17] = 0x00000000U */
- /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
- /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
- /* .. .. ==> 0XF8006214[18:18] = 0x00000000U */
- /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
- /* .. .. reg_arb_dis_rmw_portn = 0x1 */
- /* .. .. ==> 0XF8006214[19:19] = 0x00000001U */
- /* .. .. ==> MASK : 0x00080000U VAL : 0x00080000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006214, 0x000F03FFU, 0x000803FFU),
- /* .. .. reg_arb_pri_rd_portn = 0x3ff */
- /* .. .. ==> 0XF8006218[9:0] = 0x000003FFU */
- /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
- /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
- /* .. .. ==> 0XF8006218[16:16] = 0x00000000U */
- /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
- /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
- /* .. .. ==> 0XF8006218[17:17] = 0x00000000U */
- /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
- /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
- /* .. .. ==> 0XF8006218[18:18] = 0x00000000U */
- /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
- /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
- /* .. .. ==> 0XF8006218[19:19] = 0x00000000U */
- /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006218, 0x000F03FFU, 0x000003FFU),
- /* .. .. reg_arb_pri_rd_portn = 0x3ff */
- /* .. .. ==> 0XF800621C[9:0] = 0x000003FFU */
- /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
- /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
- /* .. .. ==> 0XF800621C[16:16] = 0x00000000U */
- /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
- /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
- /* .. .. ==> 0XF800621C[17:17] = 0x00000000U */
- /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
- /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
- /* .. .. ==> 0XF800621C[18:18] = 0x00000000U */
- /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
- /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
- /* .. .. ==> 0XF800621C[19:19] = 0x00000000U */
- /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF800621C, 0x000F03FFU, 0x000003FFU),
- /* .. .. reg_arb_pri_rd_portn = 0x3ff */
- /* .. .. ==> 0XF8006220[9:0] = 0x000003FFU */
- /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
- /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
- /* .. .. ==> 0XF8006220[16:16] = 0x00000000U */
- /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
- /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
- /* .. .. ==> 0XF8006220[17:17] = 0x00000000U */
- /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
- /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
- /* .. .. ==> 0XF8006220[18:18] = 0x00000000U */
- /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
- /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
- /* .. .. ==> 0XF8006220[19:19] = 0x00000000U */
- /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006220, 0x000F03FFU, 0x000003FFU),
- /* .. .. reg_arb_pri_rd_portn = 0x3ff */
- /* .. .. ==> 0XF8006224[9:0] = 0x000003FFU */
- /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
- /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
- /* .. .. ==> 0XF8006224[16:16] = 0x00000000U */
- /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
- /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
- /* .. .. ==> 0XF8006224[17:17] = 0x00000000U */
- /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
- /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
- /* .. .. ==> 0XF8006224[18:18] = 0x00000000U */
- /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
- /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
- /* .. .. ==> 0XF8006224[19:19] = 0x00000000U */
- /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006224, 0x000F03FFU, 0x000003FFU),
- /* .. .. reg_ddrc_lpddr2 = 0x0 */
- /* .. .. ==> 0XF80062A8[0:0] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. .. reg_ddrc_per_bank_refresh = 0x0 */
- /* .. .. ==> 0XF80062A8[1:1] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. .. reg_ddrc_derate_enable = 0x0 */
- /* .. .. ==> 0XF80062A8[2:2] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. .. reg_ddrc_mr4_margin = 0x0 */
- /* .. .. ==> 0XF80062A8[11:4] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U, 0x00000000U),
- /* .. .. reg_ddrc_mr4_read_interval = 0x0 */
- /* .. .. ==> 0XF80062AC[31:0] = 0x00000000U */
- /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU, 0x00000000U),
- /* .. .. reg_ddrc_min_stable_clock_x1 = 0x5 */
- /* .. .. ==> 0XF80062B0[3:0] = 0x00000005U */
- /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U */
- /* .. .. reg_ddrc_idle_after_reset_x32 = 0x12 */
- /* .. .. ==> 0XF80062B0[11:4] = 0x00000012U */
- /* .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U */
- /* .. .. reg_ddrc_t_mrw = 0x5 */
- /* .. .. ==> 0XF80062B0[21:12] = 0x00000005U */
- /* .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU, 0x00005125U),
- /* .. .. reg_ddrc_max_auto_init_x1024 = 0xa6 */
- /* .. .. ==> 0XF80062B4[7:0] = 0x000000A6U */
- /* .. .. ==> MASK : 0x000000FFU VAL : 0x000000A6U */
- /* .. .. reg_ddrc_dev_zqinit_x32 = 0x12 */
- /* .. .. ==> 0XF80062B4[17:8] = 0x00000012U */
- /* .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U */
- /* .. .. */
- EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU, 0x000012A6U),
- /* .. .. START: POLL ON DCI STATUS */
- /* .. .. DONE = 1 */
- /* .. .. ==> 0XF8000B74[13:13] = 0x00000001U */
- /* .. .. ==> MASK : 0x00002000U VAL : 0x00002000U */
- /* .. .. */
- EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
- /* .. .. FINISH: POLL ON DCI STATUS */
- /* .. .. START: UNLOCK DDR */
- /* .. .. reg_ddrc_soft_rstb = 0x1 */
- /* .. .. ==> 0XF8006000[0:0] = 0x00000001U */
- /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
- /* .. .. reg_ddrc_powerdown_en = 0x0 */
- /* .. .. ==> 0XF8006000[1:1] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. .. reg_ddrc_data_bus_width = 0x0 */
- /* .. .. ==> 0XF8006000[3:2] = 0x00000000U */
- /* .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U */
- /* .. .. reg_ddrc_burst8_refresh = 0x0 */
- /* .. .. ==> 0XF8006000[6:4] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000070U VAL : 0x00000000U */
- /* .. .. reg_ddrc_rdwr_idle_gap = 1 */
- /* .. .. ==> 0XF8006000[13:7] = 0x00000001U */
- /* .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U */
- /* .. .. reg_ddrc_dis_rd_bypass = 0x0 */
- /* .. .. ==> 0XF8006000[14:14] = 0x00000000U */
- /* .. .. ==> MASK : 0x00004000U VAL : 0x00000000U */
- /* .. .. reg_ddrc_dis_act_bypass = 0x0 */
- /* .. .. ==> 0XF8006000[15:15] = 0x00000000U */
- /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */
- /* .. .. reg_ddrc_dis_auto_refresh = 0x0 */
- /* .. .. ==> 0XF8006000[16:16] = 0x00000000U */
- /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000081U),
- /* .. .. FINISH: UNLOCK DDR */
- /* .. .. START: CHECK DDR STATUS */
- /* .. .. ddrc_reg_operating_mode = 1 */
- /* .. .. ==> 0XF8006054[2:0] = 0x00000001U */
- /* .. .. ==> MASK : 0x00000007U VAL : 0x00000001U */
- /* .. .. */
- EMIT_MASKPOLL(0XF8006054, 0x00000007U),
- /* .. .. FINISH: CHECK DDR STATUS */
- /* .. FINISH: DDR INITIALIZATION */
- /* FINISH: top */
- /* */
- EMIT_EXIT(),
-
- /* */
-};
-
-unsigned long ps7_mio_init_data_2_0[] = {
- /* START: top */
- /* .. START: SLCR SETTINGS */
- /* .. UNLOCK_KEY = 0XDF0D */
- /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
- /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */
- /* .. */
- EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
- /* .. FINISH: SLCR SETTINGS */
- /* .. START: OCM REMAPPING */
- /* .. VREF_EN = 0x1 */
- /* .. ==> 0XF8000B00[0:0] = 0x00000001U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
- /* .. VREF_PULLUP_EN = 0x0 */
- /* .. ==> 0XF8000B00[1:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. CLK_PULLUP_EN = 0x0 */
- /* .. ==> 0XF8000B00[8:8] = 0x00000000U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
- /* .. SRSTN_PULLUP_EN = 0x0 */
- /* .. ==> 0XF8000B00[9:9] = 0x00000000U */
- /* .. ==> MASK : 0x00000200U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000B00, 0x00000303U, 0x00000001U),
- /* .. FINISH: OCM REMAPPING */
- /* .. START: DDRIOB SETTINGS */
- /* .. INP_POWER = 0x0 */
- /* .. ==> 0XF8000B40[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. INP_TYPE = 0x0 */
- /* .. ==> 0XF8000B40[2:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */
- /* .. DCI_UPDATE = 0x0 */
- /* .. ==> 0XF8000B40[3:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
- /* .. TERM_EN = 0x0 */
- /* .. ==> 0XF8000B40[4:4] = 0x00000000U */
- /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */
- /* .. DCR_TYPE = 0x0 */
- /* .. ==> 0XF8000B40[6:5] = 0x00000000U */
- /* .. ==> MASK : 0x00000060U VAL : 0x00000000U */
- /* .. IBUF_DISABLE_MODE = 0x0 */
- /* .. ==> 0XF8000B40[7:7] = 0x00000000U */
- /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
- /* .. TERM_DISABLE_MODE = 0x0 */
- /* .. ==> 0XF8000B40[8:8] = 0x00000000U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
- /* .. OUTPUT_EN = 0x3 */
- /* .. ==> 0XF8000B40[10:9] = 0x00000003U */
- /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
- /* .. PULLUP_EN = 0x0 */
- /* .. ==> 0XF8000B40[11:11] = 0x00000000U */
- /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU, 0x00000600U),
- /* .. INP_POWER = 0x0 */
- /* .. ==> 0XF8000B44[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. INP_TYPE = 0x0 */
- /* .. ==> 0XF8000B44[2:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */
- /* .. DCI_UPDATE = 0x0 */
- /* .. ==> 0XF8000B44[3:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
- /* .. TERM_EN = 0x0 */
- /* .. ==> 0XF8000B44[4:4] = 0x00000000U */
- /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */
- /* .. DCR_TYPE = 0x0 */
- /* .. ==> 0XF8000B44[6:5] = 0x00000000U */
- /* .. ==> MASK : 0x00000060U VAL : 0x00000000U */
- /* .. IBUF_DISABLE_MODE = 0x0 */
- /* .. ==> 0XF8000B44[7:7] = 0x00000000U */
- /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
- /* .. TERM_DISABLE_MODE = 0x0 */
- /* .. ==> 0XF8000B44[8:8] = 0x00000000U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
- /* .. OUTPUT_EN = 0x3 */
- /* .. ==> 0XF8000B44[10:9] = 0x00000003U */
- /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
- /* .. PULLUP_EN = 0x0 */
- /* .. ==> 0XF8000B44[11:11] = 0x00000000U */
- /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU, 0x00000600U),
- /* .. INP_POWER = 0x0 */
- /* .. ==> 0XF8000B48[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. INP_TYPE = 0x1 */
- /* .. ==> 0XF8000B48[2:1] = 0x00000001U */
- /* .. ==> MASK : 0x00000006U VAL : 0x00000002U */
- /* .. DCI_UPDATE = 0x0 */
- /* .. ==> 0XF8000B48[3:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
- /* .. TERM_EN = 0x1 */
- /* .. ==> 0XF8000B48[4:4] = 0x00000001U */
- /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */
- /* .. DCR_TYPE = 0x3 */
- /* .. ==> 0XF8000B48[6:5] = 0x00000003U */
- /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */
- /* .. IBUF_DISABLE_MODE = 0 */
- /* .. ==> 0XF8000B48[7:7] = 0x00000000U */
- /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
- /* .. TERM_DISABLE_MODE = 0 */
- /* .. ==> 0XF8000B48[8:8] = 0x00000000U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
- /* .. OUTPUT_EN = 0x3 */
- /* .. ==> 0XF8000B48[10:9] = 0x00000003U */
- /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
- /* .. PULLUP_EN = 0x0 */
- /* .. ==> 0XF8000B48[11:11] = 0x00000000U */
- /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU, 0x00000672U),
- /* .. INP_POWER = 0x0 */
- /* .. ==> 0XF8000B4C[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. INP_TYPE = 0x1 */
- /* .. ==> 0XF8000B4C[2:1] = 0x00000001U */
- /* .. ==> MASK : 0x00000006U VAL : 0x00000002U */
- /* .. DCI_UPDATE = 0x0 */
- /* .. ==> 0XF8000B4C[3:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
- /* .. TERM_EN = 0x1 */
- /* .. ==> 0XF8000B4C[4:4] = 0x00000001U */
- /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */
- /* .. DCR_TYPE = 0x3 */
- /* .. ==> 0XF8000B4C[6:5] = 0x00000003U */
- /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */
- /* .. IBUF_DISABLE_MODE = 0 */
- /* .. ==> 0XF8000B4C[7:7] = 0x00000000U */
- /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
- /* .. TERM_DISABLE_MODE = 0 */
- /* .. ==> 0XF8000B4C[8:8] = 0x00000000U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
- /* .. OUTPUT_EN = 0x3 */
- /* .. ==> 0XF8000B4C[10:9] = 0x00000003U */
- /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
- /* .. PULLUP_EN = 0x0 */
- /* .. ==> 0XF8000B4C[11:11] = 0x00000000U */
- /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU, 0x00000672U),
- /* .. INP_POWER = 0x0 */
- /* .. ==> 0XF8000B50[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. INP_TYPE = 0x2 */
- /* .. ==> 0XF8000B50[2:1] = 0x00000002U */
- /* .. ==> MASK : 0x00000006U VAL : 0x00000004U */
- /* .. DCI_UPDATE = 0x0 */
- /* .. ==> 0XF8000B50[3:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
- /* .. TERM_EN = 0x1 */
- /* .. ==> 0XF8000B50[4:4] = 0x00000001U */
- /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */
- /* .. DCR_TYPE = 0x3 */
- /* .. ==> 0XF8000B50[6:5] = 0x00000003U */
- /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */
- /* .. IBUF_DISABLE_MODE = 0 */
- /* .. ==> 0XF8000B50[7:7] = 0x00000000U */
- /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
- /* .. TERM_DISABLE_MODE = 0 */
- /* .. ==> 0XF8000B50[8:8] = 0x00000000U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
- /* .. OUTPUT_EN = 0x3 */
- /* .. ==> 0XF8000B50[10:9] = 0x00000003U */
- /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
- /* .. PULLUP_EN = 0x0 */
- /* .. ==> 0XF8000B50[11:11] = 0x00000000U */
- /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU, 0x00000674U),
- /* .. INP_POWER = 0x0 */
- /* .. ==> 0XF8000B54[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. INP_TYPE = 0x2 */
- /* .. ==> 0XF8000B54[2:1] = 0x00000002U */
- /* .. ==> MASK : 0x00000006U VAL : 0x00000004U */
- /* .. DCI_UPDATE = 0x0 */
- /* .. ==> 0XF8000B54[3:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
- /* .. TERM_EN = 0x1 */
- /* .. ==> 0XF8000B54[4:4] = 0x00000001U */
- /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */
- /* .. DCR_TYPE = 0x3 */
- /* .. ==> 0XF8000B54[6:5] = 0x00000003U */
- /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */
- /* .. IBUF_DISABLE_MODE = 0 */
- /* .. ==> 0XF8000B54[7:7] = 0x00000000U */
- /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
- /* .. TERM_DISABLE_MODE = 0 */
- /* .. ==> 0XF8000B54[8:8] = 0x00000000U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
- /* .. OUTPUT_EN = 0x3 */
- /* .. ==> 0XF8000B54[10:9] = 0x00000003U */
- /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
- /* .. PULLUP_EN = 0x0 */
- /* .. ==> 0XF8000B54[11:11] = 0x00000000U */
- /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU, 0x00000674U),
- /* .. INP_POWER = 0x0 */
- /* .. ==> 0XF8000B58[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. INP_TYPE = 0x0 */
- /* .. ==> 0XF8000B58[2:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */
- /* .. DCI_UPDATE = 0x0 */
- /* .. ==> 0XF8000B58[3:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
- /* .. TERM_EN = 0x0 */
- /* .. ==> 0XF8000B58[4:4] = 0x00000000U */
- /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */
- /* .. DCR_TYPE = 0x0 */
- /* .. ==> 0XF8000B58[6:5] = 0x00000000U */
- /* .. ==> MASK : 0x00000060U VAL : 0x00000000U */
- /* .. IBUF_DISABLE_MODE = 0x0 */
- /* .. ==> 0XF8000B58[7:7] = 0x00000000U */
- /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
- /* .. TERM_DISABLE_MODE = 0x0 */
- /* .. ==> 0XF8000B58[8:8] = 0x00000000U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
- /* .. OUTPUT_EN = 0x3 */
- /* .. ==> 0XF8000B58[10:9] = 0x00000003U */
- /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
- /* .. PULLUP_EN = 0x0 */
- /* .. ==> 0XF8000B58[11:11] = 0x00000000U */
- /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU, 0x00000600U),
- /* .. DRIVE_P = 0x1c */
- /* .. ==> 0XF8000B5C[6:0] = 0x0000001CU */
- /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */
- /* .. DRIVE_N = 0xc */
- /* .. ==> 0XF8000B5C[13:7] = 0x0000000CU */
- /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */
- /* .. SLEW_P = 0x3 */
- /* .. ==> 0XF8000B5C[18:14] = 0x00000003U */
- /* .. ==> MASK : 0x0007C000U VAL : 0x0000C000U */
- /* .. SLEW_N = 0x3 */
- /* .. ==> 0XF8000B5C[23:19] = 0x00000003U */
- /* .. ==> MASK : 0x00F80000U VAL : 0x00180000U */
- /* .. GTL = 0x0 */
- /* .. ==> 0XF8000B5C[26:24] = 0x00000000U */
- /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */
- /* .. RTERM = 0x0 */
- /* .. ==> 0XF8000B5C[31:27] = 0x00000000U */
- /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU, 0x0018C61CU),
- /* .. DRIVE_P = 0x1c */
- /* .. ==> 0XF8000B60[6:0] = 0x0000001CU */
- /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */
- /* .. DRIVE_N = 0xc */
- /* .. ==> 0XF8000B60[13:7] = 0x0000000CU */
- /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */
- /* .. SLEW_P = 0x6 */
- /* .. ==> 0XF8000B60[18:14] = 0x00000006U */
- /* .. ==> MASK : 0x0007C000U VAL : 0x00018000U */
- /* .. SLEW_N = 0x1f */
- /* .. ==> 0XF8000B60[23:19] = 0x0000001FU */
- /* .. ==> MASK : 0x00F80000U VAL : 0x00F80000U */
- /* .. GTL = 0x0 */
- /* .. ==> 0XF8000B60[26:24] = 0x00000000U */
- /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */
- /* .. RTERM = 0x0 */
- /* .. ==> 0XF8000B60[31:27] = 0x00000000U */
- /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU, 0x00F9861CU),
- /* .. DRIVE_P = 0x1c */
- /* .. ==> 0XF8000B64[6:0] = 0x0000001CU */
- /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */
- /* .. DRIVE_N = 0xc */
- /* .. ==> 0XF8000B64[13:7] = 0x0000000CU */
- /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */
- /* .. SLEW_P = 0x6 */
- /* .. ==> 0XF8000B64[18:14] = 0x00000006U */
- /* .. ==> MASK : 0x0007C000U VAL : 0x00018000U */
- /* .. SLEW_N = 0x1f */
- /* .. ==> 0XF8000B64[23:19] = 0x0000001FU */
- /* .. ==> MASK : 0x00F80000U VAL : 0x00F80000U */
- /* .. GTL = 0x0 */
- /* .. ==> 0XF8000B64[26:24] = 0x00000000U */
- /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */
- /* .. RTERM = 0x0 */
- /* .. ==> 0XF8000B64[31:27] = 0x00000000U */
- /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU, 0x00F9861CU),
- /* .. DRIVE_P = 0x1c */
- /* .. ==> 0XF8000B68[6:0] = 0x0000001CU */
- /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */
- /* .. DRIVE_N = 0xc */
- /* .. ==> 0XF8000B68[13:7] = 0x0000000CU */
- /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */
- /* .. SLEW_P = 0x6 */
- /* .. ==> 0XF8000B68[18:14] = 0x00000006U */
- /* .. ==> MASK : 0x0007C000U VAL : 0x00018000U */
- /* .. SLEW_N = 0x1f */
- /* .. ==> 0XF8000B68[23:19] = 0x0000001FU */
- /* .. ==> MASK : 0x00F80000U VAL : 0x00F80000U */
- /* .. GTL = 0x0 */
- /* .. ==> 0XF8000B68[26:24] = 0x00000000U */
- /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */
- /* .. RTERM = 0x0 */
- /* .. ==> 0XF8000B68[31:27] = 0x00000000U */
- /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU, 0x00F9861CU),
- /* .. VREF_INT_EN = 0x0 */
- /* .. ==> 0XF8000B6C[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. VREF_SEL = 0x0 */
- /* .. ==> 0XF8000B6C[4:1] = 0x00000000U */
- /* .. ==> MASK : 0x0000001EU VAL : 0x00000000U */
- /* .. VREF_EXT_EN = 0x3 */
- /* .. ==> 0XF8000B6C[6:5] = 0x00000003U */
- /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */
- /* .. VREF_PULLUP_EN = 0x0 */
- /* .. ==> 0XF8000B6C[8:7] = 0x00000000U */
- /* .. ==> MASK : 0x00000180U VAL : 0x00000000U */
- /* .. REFIO_EN = 0x1 */
- /* .. ==> 0XF8000B6C[9:9] = 0x00000001U */
- /* .. ==> MASK : 0x00000200U VAL : 0x00000200U */
- /* .. REFIO_TEST = 0x0 */
- /* .. ==> 0XF8000B6C[11:10] = 0x00000000U */
- /* .. ==> MASK : 0x00000C00U VAL : 0x00000000U */
- /* .. REFIO_PULLUP_EN = 0x0 */
- /* .. ==> 0XF8000B6C[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DRST_B_PULLUP_EN = 0x0 */
- /* .. ==> 0XF8000B6C[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. CKE_PULLUP_EN = 0x0 */
- /* .. ==> 0XF8000B6C[14:14] = 0x00000000U */
- /* .. ==> MASK : 0x00004000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU, 0x00000260U),
- /* .. .. START: ASSERT RESET */
- /* .. .. RESET = 1 */
- /* .. .. ==> 0XF8000B70[0:0] = 0x00000001U */
- /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
- /* .. .. VRN_OUT = 0x1 */
- /* .. .. ==> 0XF8000B70[5:5] = 0x00000001U */
- /* .. .. ==> MASK : 0x00000020U VAL : 0x00000020U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000021U),
- /* .. .. FINISH: ASSERT RESET */
- /* .. .. START: DEASSERT RESET */
- /* .. .. RESET = 0 */
- /* .. .. ==> 0XF8000B70[0:0] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. .. VRN_OUT = 0x1 */
- /* .. .. ==> 0XF8000B70[5:5] = 0x00000001U */
- /* .. .. ==> MASK : 0x00000020U VAL : 0x00000020U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000020U),
- /* .. .. FINISH: DEASSERT RESET */
- /* .. .. RESET = 0x1 */
- /* .. .. ==> 0XF8000B70[0:0] = 0x00000001U */
- /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
- /* .. .. ENABLE = 0x1 */
- /* .. .. ==> 0XF8000B70[1:1] = 0x00000001U */
- /* .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */
- /* .. .. VRP_TRI = 0x0 */
- /* .. .. ==> 0XF8000B70[2:2] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. .. VRN_TRI = 0x0 */
- /* .. .. ==> 0XF8000B70[3:3] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */
- /* .. .. VRP_OUT = 0x0 */
- /* .. .. ==> 0XF8000B70[4:4] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
- /* .. .. VRN_OUT = 0x1 */
- /* .. .. ==> 0XF8000B70[5:5] = 0x00000001U */
- /* .. .. ==> MASK : 0x00000020U VAL : 0x00000020U */
- /* .. .. NREF_OPT1 = 0x0 */
- /* .. .. ==> 0XF8000B70[7:6] = 0x00000000U */
- /* .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U */
- /* .. .. NREF_OPT2 = 0x0 */
- /* .. .. ==> 0XF8000B70[10:8] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000700U VAL : 0x00000000U */
- /* .. .. NREF_OPT4 = 0x1 */
- /* .. .. ==> 0XF8000B70[13:11] = 0x00000001U */
- /* .. .. ==> MASK : 0x00003800U VAL : 0x00000800U */
- /* .. .. PREF_OPT1 = 0x0 */
- /* .. .. ==> 0XF8000B70[16:14] = 0x00000000U */
- /* .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U */
- /* .. .. PREF_OPT2 = 0x0 */
- /* .. .. ==> 0XF8000B70[19:17] = 0x00000000U */
- /* .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U */
- /* .. .. UPDATE_CONTROL = 0x0 */
- /* .. .. ==> 0XF8000B70[20:20] = 0x00000000U */
- /* .. .. ==> MASK : 0x00100000U VAL : 0x00000000U */
- /* .. .. INIT_COMPLETE = 0x0 */
- /* .. .. ==> 0XF8000B70[21:21] = 0x00000000U */
- /* .. .. ==> MASK : 0x00200000U VAL : 0x00000000U */
- /* .. .. TST_CLK = 0x0 */
- /* .. .. ==> 0XF8000B70[22:22] = 0x00000000U */
- /* .. .. ==> MASK : 0x00400000U VAL : 0x00000000U */
- /* .. .. TST_HLN = 0x0 */
- /* .. .. ==> 0XF8000B70[23:23] = 0x00000000U */
- /* .. .. ==> MASK : 0x00800000U VAL : 0x00000000U */
- /* .. .. TST_HLP = 0x0 */
- /* .. .. ==> 0XF8000B70[24:24] = 0x00000000U */
- /* .. .. ==> MASK : 0x01000000U VAL : 0x00000000U */
- /* .. .. TST_RST = 0x0 */
- /* .. .. ==> 0XF8000B70[25:25] = 0x00000000U */
- /* .. .. ==> MASK : 0x02000000U VAL : 0x00000000U */
- /* .. .. INT_DCI_EN = 0x0 */
- /* .. .. ==> 0XF8000B70[26:26] = 0x00000000U */
- /* .. .. ==> MASK : 0x04000000U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU, 0x00000823U),
- /* .. FINISH: DDRIOB SETTINGS */
- /* .. START: MIO PROGRAMMING */
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF8000700[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 0 */
- /* .. ==> 0XF8000700[1:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF8000700[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF8000700[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF8000700[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 0 */
- /* .. ==> 0XF8000700[8:8] = 0x00000000U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
- /* .. IO_Type = 3 */
- /* .. ==> 0XF8000700[11:9] = 0x00000003U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
- /* .. PULLUP = 1 */
- /* .. ==> 0XF8000700[12:12] = 0x00000001U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF8000700[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000700, 0x00003FFFU, 0x00001600U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF8000704[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 1 */
- /* .. ==> 0XF8000704[1:1] = 0x00000001U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF8000704[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF8000704[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF8000704[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 1 */
- /* .. ==> 0XF8000704[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. IO_Type = 3 */
- /* .. ==> 0XF8000704[11:9] = 0x00000003U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF8000704[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF8000704[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000704, 0x00003FFFU, 0x00000702U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF8000708[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 1 */
- /* .. ==> 0XF8000708[1:1] = 0x00000001U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF8000708[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF8000708[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF8000708[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 1 */
- /* .. ==> 0XF8000708[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. IO_Type = 3 */
- /* .. ==> 0XF8000708[11:9] = 0x00000003U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF8000708[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF8000708[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000708, 0x00003FFFU, 0x00000702U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF800070C[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 1 */
- /* .. ==> 0XF800070C[1:1] = 0x00000001U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF800070C[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF800070C[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF800070C[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 1 */
- /* .. ==> 0XF800070C[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. IO_Type = 3 */
- /* .. ==> 0XF800070C[11:9] = 0x00000003U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF800070C[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF800070C[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF800070C, 0x00003FFFU, 0x00000702U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF8000710[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 1 */
- /* .. ==> 0XF8000710[1:1] = 0x00000001U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF8000710[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF8000710[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF8000710[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 1 */
- /* .. ==> 0XF8000710[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. IO_Type = 3 */
- /* .. ==> 0XF8000710[11:9] = 0x00000003U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF8000710[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF8000710[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000710, 0x00003FFFU, 0x00000702U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF8000714[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 1 */
- /* .. ==> 0XF8000714[1:1] = 0x00000001U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF8000714[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF8000714[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF8000714[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 1 */
- /* .. ==> 0XF8000714[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. IO_Type = 3 */
- /* .. ==> 0XF8000714[11:9] = 0x00000003U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF8000714[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF8000714[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000714, 0x00003FFFU, 0x00000702U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF8000718[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 1 */
- /* .. ==> 0XF8000718[1:1] = 0x00000001U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF8000718[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF8000718[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF8000718[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 1 */
- /* .. ==> 0XF8000718[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. IO_Type = 3 */
- /* .. ==> 0XF8000718[11:9] = 0x00000003U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF8000718[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF8000718[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000702U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF800071C[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 0 */
- /* .. ==> 0XF800071C[1:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF800071C[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF800071C[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF800071C[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 0 */
- /* .. ==> 0XF800071C[8:8] = 0x00000000U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
- /* .. IO_Type = 3 */
- /* .. ==> 0XF800071C[11:9] = 0x00000003U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF800071C[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF800071C[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF800071C, 0x00003FFFU, 0x00000600U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF8000720[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 1 */
- /* .. ==> 0XF8000720[1:1] = 0x00000001U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF8000720[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF8000720[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF8000720[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 1 */
- /* .. ==> 0XF8000720[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. IO_Type = 3 */
- /* .. ==> 0XF8000720[11:9] = 0x00000003U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF8000720[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF8000720[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000720, 0x00003FFFU, 0x00000702U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF8000724[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 0 */
- /* .. ==> 0XF8000724[1:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF8000724[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF8000724[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF8000724[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 0 */
- /* .. ==> 0XF8000724[8:8] = 0x00000000U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
- /* .. IO_Type = 3 */
- /* .. ==> 0XF8000724[11:9] = 0x00000003U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
- /* .. PULLUP = 1 */
- /* .. ==> 0XF8000724[12:12] = 0x00000001U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF8000724[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000724, 0x00003FFFU, 0x00001600U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF8000728[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 0 */
- /* .. ==> 0XF8000728[1:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF8000728[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF8000728[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF8000728[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 0 */
- /* .. ==> 0XF8000728[8:8] = 0x00000000U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
- /* .. IO_Type = 3 */
- /* .. ==> 0XF8000728[11:9] = 0x00000003U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
- /* .. PULLUP = 1 */
- /* .. ==> 0XF8000728[12:12] = 0x00000001U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF8000728[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000728, 0x00003FFFU, 0x00001600U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF800072C[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 0 */
- /* .. ==> 0XF800072C[1:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF800072C[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF800072C[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF800072C[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 0 */
- /* .. ==> 0XF800072C[8:8] = 0x00000000U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
- /* .. IO_Type = 3 */
- /* .. ==> 0XF800072C[11:9] = 0x00000003U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
- /* .. PULLUP = 1 */
- /* .. ==> 0XF800072C[12:12] = 0x00000001U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF800072C[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF800072C, 0x00003FFFU, 0x00001600U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF8000730[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 0 */
- /* .. ==> 0XF8000730[1:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF8000730[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF8000730[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF8000730[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 0 */
- /* .. ==> 0XF8000730[8:8] = 0x00000000U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
- /* .. IO_Type = 3 */
- /* .. ==> 0XF8000730[11:9] = 0x00000003U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
- /* .. PULLUP = 1 */
- /* .. ==> 0XF8000730[12:12] = 0x00000001U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF8000730[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000730, 0x00003FFFU, 0x00001600U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF8000734[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 0 */
- /* .. ==> 0XF8000734[1:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF8000734[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF8000734[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF8000734[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 0 */
- /* .. ==> 0XF8000734[8:8] = 0x00000000U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
- /* .. IO_Type = 3 */
- /* .. ==> 0XF8000734[11:9] = 0x00000003U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
- /* .. PULLUP = 1 */
- /* .. ==> 0XF8000734[12:12] = 0x00000001U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF8000734[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000734, 0x00003FFFU, 0x00001600U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF8000738[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 0 */
- /* .. ==> 0XF8000738[1:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF8000738[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF8000738[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF8000738[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 0 */
- /* .. ==> 0XF8000738[8:8] = 0x00000000U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
- /* .. IO_Type = 3 */
- /* .. ==> 0XF8000738[11:9] = 0x00000003U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
- /* .. PULLUP = 1 */
- /* .. ==> 0XF8000738[12:12] = 0x00000001U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF8000738[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000738, 0x00003FFFU, 0x00001600U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF800073C[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 0 */
- /* .. ==> 0XF800073C[1:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF800073C[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF800073C[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF800073C[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 0 */
- /* .. ==> 0XF800073C[8:8] = 0x00000000U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
- /* .. IO_Type = 3 */
- /* .. ==> 0XF800073C[11:9] = 0x00000003U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
- /* .. PULLUP = 1 */
- /* .. ==> 0XF800073C[12:12] = 0x00000001U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF800073C[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF800073C, 0x00003FFFU, 0x00001600U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF8000740[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 1 */
- /* .. ==> 0XF8000740[1:1] = 0x00000001U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF8000740[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF8000740[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF8000740[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 1 */
- /* .. ==> 0XF8000740[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. IO_Type = 4 */
- /* .. ==> 0XF8000740[11:9] = 0x00000004U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF8000740[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 1 */
- /* .. ==> 0XF8000740[13:13] = 0x00000001U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000740, 0x00003FFFU, 0x00002902U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF8000744[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 1 */
- /* .. ==> 0XF8000744[1:1] = 0x00000001U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF8000744[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF8000744[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF8000744[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 1 */
- /* .. ==> 0XF8000744[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. IO_Type = 4 */
- /* .. ==> 0XF8000744[11:9] = 0x00000004U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF8000744[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 1 */
- /* .. ==> 0XF8000744[13:13] = 0x00000001U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000744, 0x00003FFFU, 0x00002902U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF8000748[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 1 */
- /* .. ==> 0XF8000748[1:1] = 0x00000001U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF8000748[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF8000748[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF8000748[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 1 */
- /* .. ==> 0XF8000748[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. IO_Type = 4 */
- /* .. ==> 0XF8000748[11:9] = 0x00000004U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF8000748[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 1 */
- /* .. ==> 0XF8000748[13:13] = 0x00000001U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000748, 0x00003FFFU, 0x00002902U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF800074C[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 1 */
- /* .. ==> 0XF800074C[1:1] = 0x00000001U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF800074C[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF800074C[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF800074C[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 1 */
- /* .. ==> 0XF800074C[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. IO_Type = 4 */
- /* .. ==> 0XF800074C[11:9] = 0x00000004U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF800074C[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 1 */
- /* .. ==> 0XF800074C[13:13] = 0x00000001U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */
- /* .. */
- EMIT_MASKWRITE(0XF800074C, 0x00003FFFU, 0x00002902U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF8000750[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 1 */
- /* .. ==> 0XF8000750[1:1] = 0x00000001U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF8000750[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF8000750[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF8000750[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 1 */
- /* .. ==> 0XF8000750[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. IO_Type = 4 */
- /* .. ==> 0XF8000750[11:9] = 0x00000004U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF8000750[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 1 */
- /* .. ==> 0XF8000750[13:13] = 0x00000001U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000750, 0x00003FFFU, 0x00002902U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF8000754[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 1 */
- /* .. ==> 0XF8000754[1:1] = 0x00000001U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF8000754[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF8000754[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF8000754[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 1 */
- /* .. ==> 0XF8000754[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. IO_Type = 4 */
- /* .. ==> 0XF8000754[11:9] = 0x00000004U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF8000754[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 1 */
- /* .. ==> 0XF8000754[13:13] = 0x00000001U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000754, 0x00003FFFU, 0x00002902U),
- /* .. TRI_ENABLE = 1 */
- /* .. ==> 0XF8000758[0:0] = 0x00000001U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
- /* .. L0_SEL = 1 */
- /* .. ==> 0XF8000758[1:1] = 0x00000001U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF8000758[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF8000758[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF8000758[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 1 */
- /* .. ==> 0XF8000758[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. IO_Type = 4 */
- /* .. ==> 0XF8000758[11:9] = 0x00000004U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF8000758[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF8000758[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000758, 0x00003FFFU, 0x00000903U),
- /* .. TRI_ENABLE = 1 */
- /* .. ==> 0XF800075C[0:0] = 0x00000001U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
- /* .. L0_SEL = 1 */
- /* .. ==> 0XF800075C[1:1] = 0x00000001U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF800075C[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF800075C[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF800075C[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 1 */
- /* .. ==> 0XF800075C[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. IO_Type = 4 */
- /* .. ==> 0XF800075C[11:9] = 0x00000004U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF800075C[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF800075C[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF800075C, 0x00003FFFU, 0x00000903U),
- /* .. TRI_ENABLE = 1 */
- /* .. ==> 0XF8000760[0:0] = 0x00000001U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
- /* .. L0_SEL = 1 */
- /* .. ==> 0XF8000760[1:1] = 0x00000001U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF8000760[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF8000760[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF8000760[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 1 */
- /* .. ==> 0XF8000760[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. IO_Type = 4 */
- /* .. ==> 0XF8000760[11:9] = 0x00000004U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF8000760[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF8000760[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000760, 0x00003FFFU, 0x00000903U),
- /* .. TRI_ENABLE = 1 */
- /* .. ==> 0XF8000764[0:0] = 0x00000001U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
- /* .. L0_SEL = 1 */
- /* .. ==> 0XF8000764[1:1] = 0x00000001U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF8000764[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF8000764[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF8000764[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 1 */
- /* .. ==> 0XF8000764[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. IO_Type = 4 */
- /* .. ==> 0XF8000764[11:9] = 0x00000004U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF8000764[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF8000764[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000764, 0x00003FFFU, 0x00000903U),
- /* .. TRI_ENABLE = 1 */
- /* .. ==> 0XF8000768[0:0] = 0x00000001U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
- /* .. L0_SEL = 1 */
- /* .. ==> 0XF8000768[1:1] = 0x00000001U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF8000768[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF8000768[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF8000768[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 1 */
- /* .. ==> 0XF8000768[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. IO_Type = 4 */
- /* .. ==> 0XF8000768[11:9] = 0x00000004U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF8000768[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF8000768[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000768, 0x00003FFFU, 0x00000903U),
- /* .. TRI_ENABLE = 1 */
- /* .. ==> 0XF800076C[0:0] = 0x00000001U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
- /* .. L0_SEL = 1 */
- /* .. ==> 0XF800076C[1:1] = 0x00000001U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF800076C[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF800076C[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF800076C[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 1 */
- /* .. ==> 0XF800076C[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. IO_Type = 4 */
- /* .. ==> 0XF800076C[11:9] = 0x00000004U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF800076C[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF800076C[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF800076C, 0x00003FFFU, 0x00000903U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF8000770[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 0 */
- /* .. ==> 0XF8000770[1:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. L1_SEL = 1 */
- /* .. ==> 0XF8000770[2:2] = 0x00000001U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF8000770[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF8000770[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 1 */
- /* .. ==> 0XF8000770[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. IO_Type = 1 */
- /* .. ==> 0XF8000770[11:9] = 0x00000001U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF8000770[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF8000770[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000770, 0x00003FFFU, 0x00000304U),
- /* .. TRI_ENABLE = 1 */
- /* .. ==> 0XF8000774[0:0] = 0x00000001U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
- /* .. L0_SEL = 0 */
- /* .. ==> 0XF8000774[1:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. L1_SEL = 1 */
- /* .. ==> 0XF8000774[2:2] = 0x00000001U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF8000774[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF8000774[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 1 */
- /* .. ==> 0XF8000774[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. IO_Type = 1 */
- /* .. ==> 0XF8000774[11:9] = 0x00000001U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF8000774[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF8000774[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000774, 0x00003FFFU, 0x00000305U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF8000778[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 0 */
- /* .. ==> 0XF8000778[1:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. L1_SEL = 1 */
- /* .. ==> 0XF8000778[2:2] = 0x00000001U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF8000778[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF8000778[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 1 */
- /* .. ==> 0XF8000778[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. IO_Type = 1 */
- /* .. ==> 0XF8000778[11:9] = 0x00000001U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF8000778[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF8000778[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000778, 0x00003FFFU, 0x00000304U),
- /* .. TRI_ENABLE = 1 */
- /* .. ==> 0XF800077C[0:0] = 0x00000001U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
- /* .. L0_SEL = 0 */
- /* .. ==> 0XF800077C[1:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. L1_SEL = 1 */
- /* .. ==> 0XF800077C[2:2] = 0x00000001U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF800077C[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF800077C[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 1 */
- /* .. ==> 0XF800077C[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. IO_Type = 1 */
- /* .. ==> 0XF800077C[11:9] = 0x00000001U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF800077C[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF800077C[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF800077C, 0x00003FFFU, 0x00000305U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF8000780[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 0 */
- /* .. ==> 0XF8000780[1:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. L1_SEL = 1 */
- /* .. ==> 0XF8000780[2:2] = 0x00000001U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF8000780[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF8000780[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 1 */
- /* .. ==> 0XF8000780[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. IO_Type = 1 */
- /* .. ==> 0XF8000780[11:9] = 0x00000001U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF8000780[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF8000780[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000780, 0x00003FFFU, 0x00000304U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF8000784[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 0 */
- /* .. ==> 0XF8000784[1:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. L1_SEL = 1 */
- /* .. ==> 0XF8000784[2:2] = 0x00000001U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF8000784[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF8000784[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 1 */
- /* .. ==> 0XF8000784[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. IO_Type = 1 */
- /* .. ==> 0XF8000784[11:9] = 0x00000001U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF8000784[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF8000784[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000784, 0x00003FFFU, 0x00000304U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF8000788[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 0 */
- /* .. ==> 0XF8000788[1:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. L1_SEL = 1 */
- /* .. ==> 0XF8000788[2:2] = 0x00000001U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF8000788[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF8000788[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 1 */
- /* .. ==> 0XF8000788[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. IO_Type = 1 */
- /* .. ==> 0XF8000788[11:9] = 0x00000001U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF8000788[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF8000788[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000788, 0x00003FFFU, 0x00000304U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF800078C[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 0 */
- /* .. ==> 0XF800078C[1:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. L1_SEL = 1 */
- /* .. ==> 0XF800078C[2:2] = 0x00000001U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF800078C[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF800078C[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 1 */
- /* .. ==> 0XF800078C[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. IO_Type = 1 */
- /* .. ==> 0XF800078C[11:9] = 0x00000001U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF800078C[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF800078C[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF800078C, 0x00003FFFU, 0x00000304U),
- /* .. TRI_ENABLE = 1 */
- /* .. ==> 0XF8000790[0:0] = 0x00000001U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
- /* .. L0_SEL = 0 */
- /* .. ==> 0XF8000790[1:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. L1_SEL = 1 */
- /* .. ==> 0XF8000790[2:2] = 0x00000001U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF8000790[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF8000790[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 1 */
- /* .. ==> 0XF8000790[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. IO_Type = 1 */
- /* .. ==> 0XF8000790[11:9] = 0x00000001U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF8000790[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF8000790[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000790, 0x00003FFFU, 0x00000305U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF8000794[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 0 */
- /* .. ==> 0XF8000794[1:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. L1_SEL = 1 */
- /* .. ==> 0XF8000794[2:2] = 0x00000001U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF8000794[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF8000794[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 1 */
- /* .. ==> 0XF8000794[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. IO_Type = 1 */
- /* .. ==> 0XF8000794[11:9] = 0x00000001U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF8000794[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF8000794[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000794, 0x00003FFFU, 0x00000304U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF8000798[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 0 */
- /* .. ==> 0XF8000798[1:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. L1_SEL = 1 */
- /* .. ==> 0XF8000798[2:2] = 0x00000001U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF8000798[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF8000798[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 1 */
- /* .. ==> 0XF8000798[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. IO_Type = 1 */
- /* .. ==> 0XF8000798[11:9] = 0x00000001U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF8000798[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF8000798[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000798, 0x00003FFFU, 0x00000304U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF800079C[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 0 */
- /* .. ==> 0XF800079C[1:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. L1_SEL = 1 */
- /* .. ==> 0XF800079C[2:2] = 0x00000001U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF800079C[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF800079C[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 1 */
- /* .. ==> 0XF800079C[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. IO_Type = 1 */
- /* .. ==> 0XF800079C[11:9] = 0x00000001U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF800079C[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF800079C[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF800079C, 0x00003FFFU, 0x00000304U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF80007A0[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 0 */
- /* .. ==> 0XF80007A0[1:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF80007A0[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF80007A0[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 4 */
- /* .. ==> 0XF80007A0[7:5] = 0x00000004U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
- /* .. Speed = 1 */
- /* .. ==> 0XF80007A0[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. IO_Type = 1 */
- /* .. ==> 0XF80007A0[11:9] = 0x00000001U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF80007A0[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF80007A0[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU, 0x00000380U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF80007A4[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 0 */
- /* .. ==> 0XF80007A4[1:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF80007A4[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF80007A4[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 4 */
- /* .. ==> 0XF80007A4[7:5] = 0x00000004U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
- /* .. Speed = 1 */
- /* .. ==> 0XF80007A4[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. IO_Type = 1 */
- /* .. ==> 0XF80007A4[11:9] = 0x00000001U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF80007A4[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF80007A4[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU, 0x00000380U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF80007A8[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 0 */
- /* .. ==> 0XF80007A8[1:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF80007A8[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF80007A8[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 4 */
- /* .. ==> 0XF80007A8[7:5] = 0x00000004U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
- /* .. Speed = 1 */
- /* .. ==> 0XF80007A8[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. IO_Type = 1 */
- /* .. ==> 0XF80007A8[11:9] = 0x00000001U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF80007A8[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF80007A8[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU, 0x00000380U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF80007AC[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 0 */
- /* .. ==> 0XF80007AC[1:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF80007AC[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF80007AC[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 4 */
- /* .. ==> 0XF80007AC[7:5] = 0x00000004U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
- /* .. Speed = 1 */
- /* .. ==> 0XF80007AC[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. IO_Type = 1 */
- /* .. ==> 0XF80007AC[11:9] = 0x00000001U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF80007AC[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF80007AC[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU, 0x00000380U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF80007B0[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 0 */
- /* .. ==> 0XF80007B0[1:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF80007B0[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF80007B0[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 4 */
- /* .. ==> 0XF80007B0[7:5] = 0x00000004U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
- /* .. Speed = 1 */
- /* .. ==> 0XF80007B0[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. IO_Type = 1 */
- /* .. ==> 0XF80007B0[11:9] = 0x00000001U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF80007B0[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF80007B0[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU, 0x00000380U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF80007B4[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 0 */
- /* .. ==> 0XF80007B4[1:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF80007B4[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF80007B4[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 4 */
- /* .. ==> 0XF80007B4[7:5] = 0x00000004U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
- /* .. Speed = 1 */
- /* .. ==> 0XF80007B4[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. IO_Type = 1 */
- /* .. ==> 0XF80007B4[11:9] = 0x00000001U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF80007B4[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF80007B4[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00000380U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF80007B8[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 0 */
- /* .. ==> 0XF80007B8[1:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF80007B8[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF80007B8[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF80007B8[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 0 */
- /* .. ==> 0XF80007B8[8:8] = 0x00000000U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
- /* .. IO_Type = 1 */
- /* .. ==> 0XF80007B8[11:9] = 0x00000001U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
- /* .. PULLUP = 1 */
- /* .. ==> 0XF80007B8[12:12] = 0x00000001U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF80007B8[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU, 0x00001200U),
- /* .. TRI_ENABLE = 1 */
- /* .. ==> 0XF80007BC[0:0] = 0x00000001U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
- /* .. Speed = 0 */
- /* .. ==> 0XF80007BC[8:8] = 0x00000000U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
- /* .. IO_Type = 1 */
- /* .. ==> 0XF80007BC[11:9] = 0x00000001U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF80007BC[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF80007BC[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF80007BC, 0x00003F01U, 0x00000201U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF80007C0[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 0 */
- /* .. ==> 0XF80007C0[1:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF80007C0[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF80007C0[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 7 */
- /* .. ==> 0XF80007C0[7:5] = 0x00000007U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x000000E0U */
- /* .. Speed = 0 */
- /* .. ==> 0XF80007C0[8:8] = 0x00000000U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
- /* .. IO_Type = 1 */
- /* .. ==> 0XF80007C0[11:9] = 0x00000001U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF80007C0[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF80007C0[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU, 0x000002E0U),
- /* .. TRI_ENABLE = 1 */
- /* .. ==> 0XF80007C4[0:0] = 0x00000001U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
- /* .. L0_SEL = 0 */
- /* .. ==> 0XF80007C4[1:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF80007C4[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF80007C4[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 7 */
- /* .. ==> 0XF80007C4[7:5] = 0x00000007U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x000000E0U */
- /* .. Speed = 0 */
- /* .. ==> 0XF80007C4[8:8] = 0x00000000U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
- /* .. IO_Type = 1 */
- /* .. ==> 0XF80007C4[11:9] = 0x00000001U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF80007C4[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF80007C4[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x000002E1U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF80007C8[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 0 */
- /* .. ==> 0XF80007C8[1:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF80007C8[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF80007C8[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF80007C8[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 0 */
- /* .. ==> 0XF80007C8[8:8] = 0x00000000U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
- /* .. IO_Type = 1 */
- /* .. ==> 0XF80007C8[11:9] = 0x00000001U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF80007C8[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF80007C8[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU, 0x00000200U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF80007CC[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 0 */
- /* .. ==> 0XF80007CC[1:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF80007CC[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF80007CC[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF80007CC[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 0 */
- /* .. ==> 0XF80007CC[8:8] = 0x00000000U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
- /* .. IO_Type = 1 */
- /* .. ==> 0XF80007CC[11:9] = 0x00000001U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF80007CC[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF80007CC[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU, 0x00000200U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF80007D0[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 0 */
- /* .. ==> 0XF80007D0[1:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF80007D0[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF80007D0[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 4 */
- /* .. ==> 0XF80007D0[7:5] = 0x00000004U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
- /* .. Speed = 0 */
- /* .. ==> 0XF80007D0[8:8] = 0x00000000U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
- /* .. IO_Type = 1 */
- /* .. ==> 0XF80007D0[11:9] = 0x00000001U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF80007D0[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF80007D0[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU, 0x00000280U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF80007D4[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 0 */
- /* .. ==> 0XF80007D4[1:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF80007D4[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF80007D4[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 4 */
- /* .. ==> 0XF80007D4[7:5] = 0x00000004U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
- /* .. Speed = 0 */
- /* .. ==> 0XF80007D4[8:8] = 0x00000000U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
- /* .. IO_Type = 1 */
- /* .. ==> 0XF80007D4[11:9] = 0x00000001U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF80007D4[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF80007D4[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU, 0x00000280U),
- /* .. SDIO0_WP_SEL = 55 */
- /* .. ==> 0XF8000830[5:0] = 0x00000037U */
- /* .. ==> MASK : 0x0000003FU VAL : 0x00000037U */
- /* .. SDIO0_CD_SEL = 47 */
- /* .. ==> 0XF8000830[21:16] = 0x0000002FU */
- /* .. ==> MASK : 0x003F0000U VAL : 0x002F0000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000830, 0x003F003FU, 0x002F0037U),
- /* .. FINISH: MIO PROGRAMMING */
- /* .. START: LOCK IT BACK */
- /* .. LOCK_KEY = 0X767B */
- /* .. ==> 0XF8000004[15:0] = 0x0000767BU */
- /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */
- /* .. */
- EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
- /* .. FINISH: LOCK IT BACK */
- /* FINISH: top */
- /* */
- EMIT_EXIT(),
-
- /* */
-};
-
-unsigned long ps7_peripherals_init_data_2_0[] = {
- /* START: top */
- /* .. START: SLCR SETTINGS */
- /* .. UNLOCK_KEY = 0XDF0D */
- /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
- /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */
- /* .. */
- EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
- /* .. FINISH: SLCR SETTINGS */
- /* .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS */
- /* .. IBUF_DISABLE_MODE = 0x1 */
- /* .. ==> 0XF8000B48[7:7] = 0x00000001U */
- /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */
- /* .. TERM_DISABLE_MODE = 0x1 */
- /* .. ==> 0XF8000B48[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. */
- EMIT_MASKWRITE(0XF8000B48, 0x00000180U, 0x00000180U),
- /* .. IBUF_DISABLE_MODE = 0x1 */
- /* .. ==> 0XF8000B4C[7:7] = 0x00000001U */
- /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */
- /* .. TERM_DISABLE_MODE = 0x1 */
- /* .. ==> 0XF8000B4C[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. */
- EMIT_MASKWRITE(0XF8000B4C, 0x00000180U, 0x00000180U),
- /* .. IBUF_DISABLE_MODE = 0x1 */
- /* .. ==> 0XF8000B50[7:7] = 0x00000001U */
- /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */
- /* .. TERM_DISABLE_MODE = 0x1 */
- /* .. ==> 0XF8000B50[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. */
- EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U),
- /* .. IBUF_DISABLE_MODE = 0x1 */
- /* .. ==> 0XF8000B54[7:7] = 0x00000001U */
- /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */
- /* .. TERM_DISABLE_MODE = 0x1 */
- /* .. ==> 0XF8000B54[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. */
- EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U),
- /* .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS */
- /* .. START: LOCK IT BACK */
- /* .. LOCK_KEY = 0X767B */
- /* .. ==> 0XF8000004[15:0] = 0x0000767BU */
- /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */
- /* .. */
- EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
- /* .. FINISH: LOCK IT BACK */
- /* .. START: SRAM/NOR SET OPMODE */
- /* .. FINISH: SRAM/NOR SET OPMODE */
- /* .. START: UART REGISTERS */
- /* .. BDIV = 0x6 */
- /* .. ==> 0XE0001034[7:0] = 0x00000006U */
- /* .. ==> MASK : 0x000000FFU VAL : 0x00000006U */
- /* .. */
- EMIT_MASKWRITE(0XE0001034, 0x000000FFU, 0x00000006U),
- /* .. CD = 0x7c */
- /* .. ==> 0XE0001018[15:0] = 0x0000007CU */
- /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU */
- /* .. */
- EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU, 0x0000007CU),
- /* .. STPBRK = 0x0 */
- /* .. ==> 0XE0001000[8:8] = 0x00000000U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
- /* .. STTBRK = 0x0 */
- /* .. ==> 0XE0001000[7:7] = 0x00000000U */
- /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
- /* .. RSTTO = 0x0 */
- /* .. ==> 0XE0001000[6:6] = 0x00000000U */
- /* .. ==> MASK : 0x00000040U VAL : 0x00000000U */
- /* .. TXDIS = 0x0 */
- /* .. ==> 0XE0001000[5:5] = 0x00000000U */
- /* .. ==> MASK : 0x00000020U VAL : 0x00000000U */
- /* .. TXEN = 0x1 */
- /* .. ==> 0XE0001000[4:4] = 0x00000001U */
- /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */
- /* .. RXDIS = 0x0 */
- /* .. ==> 0XE0001000[3:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
- /* .. RXEN = 0x1 */
- /* .. ==> 0XE0001000[2:2] = 0x00000001U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
- /* .. TXRES = 0x1 */
- /* .. ==> 0XE0001000[1:1] = 0x00000001U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
- /* .. RXRES = 0x1 */
- /* .. ==> 0XE0001000[0:0] = 0x00000001U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
- /* .. */
- EMIT_MASKWRITE(0XE0001000, 0x000001FFU, 0x00000017U),
- /* .. IRMODE = 0x0 */
- /* .. ==> 0XE0001004[11:11] = 0x00000000U */
- /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
- /* .. UCLKEN = 0x0 */
- /* .. ==> 0XE0001004[10:10] = 0x00000000U */
- /* .. ==> MASK : 0x00000400U VAL : 0x00000000U */
- /* .. CHMODE = 0x0 */
- /* .. ==> 0XE0001004[9:8] = 0x00000000U */
- /* .. ==> MASK : 0x00000300U VAL : 0x00000000U */
- /* .. NBSTOP = 0x0 */
- /* .. ==> 0XE0001004[7:6] = 0x00000000U */
- /* .. ==> MASK : 0x000000C0U VAL : 0x00000000U */
- /* .. PAR = 0x4 */
- /* .. ==> 0XE0001004[5:3] = 0x00000004U */
- /* .. ==> MASK : 0x00000038U VAL : 0x00000020U */
- /* .. CHRL = 0x0 */
- /* .. ==> 0XE0001004[2:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */
- /* .. CLKS = 0x0 */
- /* .. ==> 0XE0001004[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XE0001004, 0x00000FFFU, 0x00000020U),
- /* .. FINISH: UART REGISTERS */
- /* .. START: QSPI REGISTERS */
- /* .. Holdb_dr = 1 */
- /* .. ==> 0XE000D000[19:19] = 0x00000001U */
- /* .. ==> MASK : 0x00080000U VAL : 0x00080000U */
- /* .. */
- EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U),
- /* .. FINISH: QSPI REGISTERS */
- /* .. START: PL POWER ON RESET REGISTERS */
- /* .. PCFG_POR_CNT_4K = 0 */
- /* .. ==> 0XF8007000[29:29] = 0x00000000U */
- /* .. ==> MASK : 0x20000000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U),
- /* .. FINISH: PL POWER ON RESET REGISTERS */
- /* .. START: SMC TIMING CALCULATION REGISTER UPDATE */
- /* .. .. START: NAND SET CYCLE */
- /* .. .. FINISH: NAND SET CYCLE */
- /* .. .. START: OPMODE */
- /* .. .. FINISH: OPMODE */
- /* .. .. START: DIRECT COMMAND */
- /* .. .. FINISH: DIRECT COMMAND */
- /* .. .. START: SRAM/NOR CS0 SET CYCLE */
- /* .. .. FINISH: SRAM/NOR CS0 SET CYCLE */
- /* .. .. START: DIRECT COMMAND */
- /* .. .. FINISH: DIRECT COMMAND */
- /* .. .. START: NOR CS0 BASE ADDRESS */
- /* .. .. FINISH: NOR CS0 BASE ADDRESS */
- /* .. .. START: SRAM/NOR CS1 SET CYCLE */
- /* .. .. FINISH: SRAM/NOR CS1 SET CYCLE */
- /* .. .. START: DIRECT COMMAND */
- /* .. .. FINISH: DIRECT COMMAND */
- /* .. .. START: NOR CS1 BASE ADDRESS */
- /* .. .. FINISH: NOR CS1 BASE ADDRESS */
- /* .. .. START: USB RESET */
- /* .. .. .. START: USB0 RESET */
- /* .. .. .. .. START: DIR MODE BANK 0 */
- /* .. .. .. .. FINISH: DIR MODE BANK 0 */
- /* .. .. .. .. START: DIR MODE BANK 1 */
- /* .. .. .. .. DIRECTION_1 = 0x4000 */
- /* .. .. .. .. ==> 0XE000A244[21:0] = 0x00004000U */
- /* .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U */
- /* .. .. .. .. */
- EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU, 0x00004000U),
- /* .. .. .. .. FINISH: DIR MODE BANK 1 */
- /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
- /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
- /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
- /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
- /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
- /* .. .. .. .. MASK_1_LSW = 0xbfff */
- /* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */
- /* .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U */
- /* .. .. .. .. DATA_1_LSW = 0x4000 */
- /* .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U */
- /* .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U */
- /* .. .. .. .. */
- EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF4000U),
- /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
- /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
- /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
- /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
- /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
- /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
- /* .. .. .. .. OP_ENABLE_1 = 0x4000 */
- /* .. .. .. .. ==> 0XE000A248[21:0] = 0x00004000U */
- /* .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U */
- /* .. .. .. .. */
- EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU, 0x00004000U),
- /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
- /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
- /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
- /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
- /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
- /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
- /* .. .. .. .. MASK_1_LSW = 0xbfff */
- /* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */
- /* .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U */
- /* .. .. .. .. DATA_1_LSW = 0x0 */
- /* .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U */
- /* .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U */
- /* .. .. .. .. */
- EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF0000U),
- /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
- /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
- /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
- /* .. .. .. .. START: ADD 1 MS DELAY */
- /* .. .. .. .. */
- EMIT_MASKDELAY(0XF8F00200, 1),
- /* .. .. .. .. FINISH: ADD 1 MS DELAY */
- /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
- /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
- /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
- /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
- /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
- /* .. .. .. .. MASK_1_LSW = 0xbfff */
- /* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */
- /* .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U */
- /* .. .. .. .. DATA_1_LSW = 0x4000 */
- /* .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U */
- /* .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U */
- /* .. .. .. .. */
- EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF4000U),
- /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
- /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
- /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
- /* .. .. .. FINISH: USB0 RESET */
- /* .. .. .. START: USB1 RESET */
- /* .. .. .. .. START: DIR MODE BANK 0 */
- /* .. .. .. .. FINISH: DIR MODE BANK 0 */
- /* .. .. .. .. START: DIR MODE BANK 1 */
- /* .. .. .. .. FINISH: DIR MODE BANK 1 */
- /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
- /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
- /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
- /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
- /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
- /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
- /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
- /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
- /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
- /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
- /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
- /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
- /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
- /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
- /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
- /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
- /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
- /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
- /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
- /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
- /* .. .. .. .. START: ADD 1 MS DELAY */
- /* .. .. .. .. */
- EMIT_MASKDELAY(0XF8F00200, 1),
- /* .. .. .. .. FINISH: ADD 1 MS DELAY */
- /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
- /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
- /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
- /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
- /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
- /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
- /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
- /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
- /* .. .. .. FINISH: USB1 RESET */
- /* .. .. FINISH: USB RESET */
- /* .. .. START: ENET RESET */
- /* .. .. .. START: ENET0 RESET */
- /* .. .. .. .. START: DIR MODE BANK 0 */
- /* .. .. .. .. FINISH: DIR MODE BANK 0 */
- /* .. .. .. .. START: DIR MODE BANK 1 */
- /* .. .. .. .. FINISH: DIR MODE BANK 1 */
- /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
- /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
- /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
- /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
- /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
- /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
- /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
- /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
- /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
- /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
- /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
- /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
- /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
- /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
- /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
- /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
- /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
- /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
- /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
- /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
- /* .. .. .. .. START: ADD 1 MS DELAY */
- /* .. .. .. .. */
- EMIT_MASKDELAY(0XF8F00200, 1),
- /* .. .. .. .. FINISH: ADD 1 MS DELAY */
- /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
- /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
- /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
- /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
- /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
- /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
- /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
- /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
- /* .. .. .. FINISH: ENET0 RESET */
- /* .. .. .. START: ENET1 RESET */
- /* .. .. .. .. START: DIR MODE BANK 0 */
- /* .. .. .. .. FINISH: DIR MODE BANK 0 */
- /* .. .. .. .. START: DIR MODE BANK 1 */
- /* .. .. .. .. FINISH: DIR MODE BANK 1 */
- /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
- /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
- /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
- /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
- /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
- /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
- /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
- /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
- /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
- /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
- /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
- /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
- /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
- /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
- /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
- /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
- /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
- /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
- /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
- /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
- /* .. .. .. .. START: ADD 1 MS DELAY */
- /* .. .. .. .. */
- EMIT_MASKDELAY(0XF8F00200, 1),
- /* .. .. .. .. FINISH: ADD 1 MS DELAY */
- /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
- /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
- /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
- /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
- /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
- /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
- /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
- /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
- /* .. .. .. FINISH: ENET1 RESET */
- /* .. .. FINISH: ENET RESET */
- /* .. .. START: I2C RESET */
- /* .. .. .. START: I2C0 RESET */
- /* .. .. .. .. START: DIR MODE GPIO BANK0 */
- /* .. .. .. .. FINISH: DIR MODE GPIO BANK0 */
- /* .. .. .. .. START: DIR MODE GPIO BANK1 */
- /* .. .. .. .. FINISH: DIR MODE GPIO BANK1 */
- /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
- /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
- /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
- /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
- /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
- /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
- /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
- /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
- /* .. .. .. .. START: OUTPUT ENABLE */
- /* .. .. .. .. FINISH: OUTPUT ENABLE */
- /* .. .. .. .. START: OUTPUT ENABLE */
- /* .. .. .. .. FINISH: OUTPUT ENABLE */
- /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
- /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
- /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
- /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
- /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
- /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
- /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
- /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
- /* .. .. .. .. START: ADD 1 MS DELAY */
- /* .. .. .. .. */
- EMIT_MASKDELAY(0XF8F00200, 1),
- /* .. .. .. .. FINISH: ADD 1 MS DELAY */
- /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
- /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
- /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
- /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
- /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
- /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
- /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
- /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
- /* .. .. .. FINISH: I2C0 RESET */
- /* .. .. .. START: I2C1 RESET */
- /* .. .. .. .. START: DIR MODE GPIO BANK0 */
- /* .. .. .. .. FINISH: DIR MODE GPIO BANK0 */
- /* .. .. .. .. START: DIR MODE GPIO BANK1 */
- /* .. .. .. .. FINISH: DIR MODE GPIO BANK1 */
- /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
- /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
- /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
- /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
- /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
- /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
- /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
- /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
- /* .. .. .. .. START: OUTPUT ENABLE */
- /* .. .. .. .. FINISH: OUTPUT ENABLE */
- /* .. .. .. .. START: OUTPUT ENABLE */
- /* .. .. .. .. FINISH: OUTPUT ENABLE */
- /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
- /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
- /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
- /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
- /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
- /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
- /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
- /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
- /* .. .. .. .. START: ADD 1 MS DELAY */
- /* .. .. .. .. */
- EMIT_MASKDELAY(0XF8F00200, 1),
- /* .. .. .. .. FINISH: ADD 1 MS DELAY */
- /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
- /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
- /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
- /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
- /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
- /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
- /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
- /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
- /* .. .. .. FINISH: I2C1 RESET */
- /* .. .. FINISH: I2C RESET */
- /* .. .. START: NOR CHIP SELECT */
- /* .. .. .. START: DIR MODE BANK 0 */
- /* .. .. .. FINISH: DIR MODE BANK 0 */
- /* .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
- /* .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
- /* .. .. .. START: OUTPUT ENABLE BANK 0 */
- /* .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
- /* .. .. FINISH: NOR CHIP SELECT */
- /* .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE */
- /* FINISH: top */
- /* */
- EMIT_EXIT(),
-
- /* */
-};
-
-unsigned long ps7_post_config_2_0[] = {
- /* START: top */
- /* .. START: SLCR SETTINGS */
- /* .. UNLOCK_KEY = 0XDF0D */
- /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
- /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */
- /* .. */
- EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
- /* .. FINISH: SLCR SETTINGS */
- /* .. START: ENABLING LEVEL SHIFTER */
- /* .. USER_INP_ICT_EN_0 = 3 */
- /* .. ==> 0XF8000900[1:0] = 0x00000003U */
- /* .. ==> MASK : 0x00000003U VAL : 0x00000003U */
- /* .. USER_INP_ICT_EN_1 = 3 */
- /* .. ==> 0XF8000900[3:2] = 0x00000003U */
- /* .. ==> MASK : 0x0000000CU VAL : 0x0000000CU */
- /* .. */
- EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU),
- /* .. FINISH: ENABLING LEVEL SHIFTER */
- /* .. START: FPGA RESETS TO 0 */
- /* .. reserved_3 = 0 */
- /* .. ==> 0XF8000240[31:25] = 0x00000000U */
- /* .. ==> MASK : 0xFE000000U VAL : 0x00000000U */
- /* .. FPGA_ACP_RST = 0 */
- /* .. ==> 0XF8000240[24:24] = 0x00000000U */
- /* .. ==> MASK : 0x01000000U VAL : 0x00000000U */
- /* .. FPGA_AXDS3_RST = 0 */
- /* .. ==> 0XF8000240[23:23] = 0x00000000U */
- /* .. ==> MASK : 0x00800000U VAL : 0x00000000U */
- /* .. FPGA_AXDS2_RST = 0 */
- /* .. ==> 0XF8000240[22:22] = 0x00000000U */
- /* .. ==> MASK : 0x00400000U VAL : 0x00000000U */
- /* .. FPGA_AXDS1_RST = 0 */
- /* .. ==> 0XF8000240[21:21] = 0x00000000U */
- /* .. ==> MASK : 0x00200000U VAL : 0x00000000U */
- /* .. FPGA_AXDS0_RST = 0 */
- /* .. ==> 0XF8000240[20:20] = 0x00000000U */
- /* .. ==> MASK : 0x00100000U VAL : 0x00000000U */
- /* .. reserved_2 = 0 */
- /* .. ==> 0XF8000240[19:18] = 0x00000000U */
- /* .. ==> MASK : 0x000C0000U VAL : 0x00000000U */
- /* .. FSSW1_FPGA_RST = 0 */
- /* .. ==> 0XF8000240[17:17] = 0x00000000U */
- /* .. ==> MASK : 0x00020000U VAL : 0x00000000U */
- /* .. FSSW0_FPGA_RST = 0 */
- /* .. ==> 0XF8000240[16:16] = 0x00000000U */
- /* .. ==> MASK : 0x00010000U VAL : 0x00000000U */
- /* .. reserved_1 = 0 */
- /* .. ==> 0XF8000240[15:14] = 0x00000000U */
- /* .. ==> MASK : 0x0000C000U VAL : 0x00000000U */
- /* .. FPGA_FMSW1_RST = 0 */
- /* .. ==> 0XF8000240[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. FPGA_FMSW0_RST = 0 */
- /* .. ==> 0XF8000240[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. FPGA_DMA3_RST = 0 */
- /* .. ==> 0XF8000240[11:11] = 0x00000000U */
- /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
- /* .. FPGA_DMA2_RST = 0 */
- /* .. ==> 0XF8000240[10:10] = 0x00000000U */
- /* .. ==> MASK : 0x00000400U VAL : 0x00000000U */
- /* .. FPGA_DMA1_RST = 0 */
- /* .. ==> 0XF8000240[9:9] = 0x00000000U */
- /* .. ==> MASK : 0x00000200U VAL : 0x00000000U */
- /* .. FPGA_DMA0_RST = 0 */
- /* .. ==> 0XF8000240[8:8] = 0x00000000U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
- /* .. reserved = 0 */
- /* .. ==> 0XF8000240[7:4] = 0x00000000U */
- /* .. ==> MASK : 0x000000F0U VAL : 0x00000000U */
- /* .. FPGA3_OUT_RST = 0 */
- /* .. ==> 0XF8000240[3:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
- /* .. FPGA2_OUT_RST = 0 */
- /* .. ==> 0XF8000240[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. FPGA1_OUT_RST = 0 */
- /* .. ==> 0XF8000240[1:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. FPGA0_OUT_RST = 0 */
- /* .. ==> 0XF8000240[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU, 0x00000000U),
- /* .. FINISH: FPGA RESETS TO 0 */
- /* .. START: AFI REGISTERS */
- /* .. .. START: AFI0 REGISTERS */
- /* .. .. FINISH: AFI0 REGISTERS */
- /* .. .. START: AFI1 REGISTERS */
- /* .. .. FINISH: AFI1 REGISTERS */
- /* .. .. START: AFI2 REGISTERS */
- /* .. .. FINISH: AFI2 REGISTERS */
- /* .. .. START: AFI3 REGISTERS */
- /* .. .. FINISH: AFI3 REGISTERS */
- /* .. FINISH: AFI REGISTERS */
- /* .. START: LOCK IT BACK */
- /* .. LOCK_KEY = 0X767B */
- /* .. ==> 0XF8000004[15:0] = 0x0000767BU */
- /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */
- /* .. */
- EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
- /* .. FINISH: LOCK IT BACK */
- /* FINISH: top */
- /* */
- EMIT_EXIT(),
-
- /* */
-};
-
-unsigned long ps7_debug_2_0[] = {
- /* START: top */
- /* .. START: CROSS TRIGGER CONFIGURATIONS */
- /* .. .. START: UNLOCKING CTI REGISTERS */
- /* .. .. KEY = 0XC5ACCE55 */
- /* .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U */
- /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU, 0xC5ACCE55U),
- /* .. .. KEY = 0XC5ACCE55 */
- /* .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U */
- /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU, 0xC5ACCE55U),
- /* .. .. KEY = 0XC5ACCE55 */
- /* .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U */
- /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU, 0xC5ACCE55U),
- /* .. .. FINISH: UNLOCKING CTI REGISTERS */
- /* .. .. START: ENABLING CTI MODULES AND CHANNELS */
- /* .. .. FINISH: ENABLING CTI MODULES AND CHANNELS */
- /* .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS */
- /* .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS */
- /* .. FINISH: CROSS TRIGGER CONFIGURATIONS */
- /* FINISH: top */
- /* */
- EMIT_EXIT(),
-
- /* */
-};
-
-unsigned long ps7_pll_init_data_1_0[] = {
- /* START: top */
- /* .. START: SLCR SETTINGS */
- /* .. UNLOCK_KEY = 0XDF0D */
- /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
- /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */
- /* .. */
- EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
- /* .. FINISH: SLCR SETTINGS */
- /* .. START: PLL SLCR REGISTERS */
- /* .. .. START: ARM PLL INIT */
- /* .. .. PLL_RES = 0xc */
- /* .. .. ==> 0XF8000110[7:4] = 0x0000000CU */
- /* .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U */
- /* .. .. PLL_CP = 0x2 */
- /* .. .. ==> 0XF8000110[11:8] = 0x00000002U */
- /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */
- /* .. .. LOCK_CNT = 0x177 */
- /* .. .. ==> 0XF8000110[21:12] = 0x00000177U */
- /* .. .. ==> MASK : 0x003FF000U VAL : 0x00177000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x001772C0U),
- /* .. .. .. START: UPDATE FB_DIV */
- /* .. .. .. PLL_FDIV = 0x1a */
- /* .. .. .. ==> 0XF8000100[18:12] = 0x0000001AU */
- /* .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001A000U */
- /* .. .. .. */
- EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x0001A000U),
- /* .. .. .. FINISH: UPDATE FB_DIV */
- /* .. .. .. START: BY PASS PLL */
- /* .. .. .. PLL_BYPASS_FORCE = 1 */
- /* .. .. .. ==> 0XF8000100[4:4] = 0x00000001U */
- /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U */
- /* .. .. .. */
- EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U),
- /* .. .. .. FINISH: BY PASS PLL */
- /* .. .. .. START: ASSERT RESET */
- /* .. .. .. PLL_RESET = 1 */
- /* .. .. .. ==> 0XF8000100[0:0] = 0x00000001U */
- /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
- /* .. .. .. */
- EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U),
- /* .. .. .. FINISH: ASSERT RESET */
- /* .. .. .. START: DEASSERT RESET */
- /* .. .. .. PLL_RESET = 0 */
- /* .. .. .. ==> 0XF8000100[0:0] = 0x00000000U */
- /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. .. .. */
- EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U),
- /* .. .. .. FINISH: DEASSERT RESET */
- /* .. .. .. START: CHECK PLL STATUS */
- /* .. .. .. ARM_PLL_LOCK = 1 */
- /* .. .. .. ==> 0XF800010C[0:0] = 0x00000001U */
- /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
- /* .. .. .. */
- EMIT_MASKPOLL(0XF800010C, 0x00000001U),
- /* .. .. .. FINISH: CHECK PLL STATUS */
- /* .. .. .. START: REMOVE PLL BY PASS */
- /* .. .. .. PLL_BYPASS_FORCE = 0 */
- /* .. .. .. ==> 0XF8000100[4:4] = 0x00000000U */
- /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
- /* .. .. .. */
- EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U),
- /* .. .. .. FINISH: REMOVE PLL BY PASS */
- /* .. .. .. SRCSEL = 0x0 */
- /* .. .. .. ==> 0XF8000120[5:4] = 0x00000000U */
- /* .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
- /* .. .. .. DIVISOR = 0x2 */
- /* .. .. .. ==> 0XF8000120[13:8] = 0x00000002U */
- /* .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U */
- /* .. .. .. CPU_6OR4XCLKACT = 0x1 */
- /* .. .. .. ==> 0XF8000120[24:24] = 0x00000001U */
- /* .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U */
- /* .. .. .. CPU_3OR2XCLKACT = 0x1 */
- /* .. .. .. ==> 0XF8000120[25:25] = 0x00000001U */
- /* .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U */
- /* .. .. .. CPU_2XCLKACT = 0x1 */
- /* .. .. .. ==> 0XF8000120[26:26] = 0x00000001U */
- /* .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U */
- /* .. .. .. CPU_1XCLKACT = 0x1 */
- /* .. .. .. ==> 0XF8000120[27:27] = 0x00000001U */
- /* .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U */
- /* .. .. .. CPU_PERI_CLKACT = 0x1 */
- /* .. .. .. ==> 0XF8000120[28:28] = 0x00000001U */
- /* .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U */
- /* .. .. .. */
- EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000200U),
- /* .. .. FINISH: ARM PLL INIT */
- /* .. .. START: DDR PLL INIT */
- /* .. .. PLL_RES = 0xc */
- /* .. .. ==> 0XF8000114[7:4] = 0x0000000CU */
- /* .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U */
- /* .. .. PLL_CP = 0x2 */
- /* .. .. ==> 0XF8000114[11:8] = 0x00000002U */
- /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */
- /* .. .. LOCK_CNT = 0x1db */
- /* .. .. ==> 0XF8000114[21:12] = 0x000001DBU */
- /* .. .. ==> MASK : 0x003FF000U VAL : 0x001DB000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x001DB2C0U),
- /* .. .. .. START: UPDATE FB_DIV */
- /* .. .. .. PLL_FDIV = 0x15 */
- /* .. .. .. ==> 0XF8000104[18:12] = 0x00000015U */
- /* .. .. .. ==> MASK : 0x0007F000U VAL : 0x00015000U */
- /* .. .. .. */
- EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x00015000U),
- /* .. .. .. FINISH: UPDATE FB_DIV */
- /* .. .. .. START: BY PASS PLL */
- /* .. .. .. PLL_BYPASS_FORCE = 1 */
- /* .. .. .. ==> 0XF8000104[4:4] = 0x00000001U */
- /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U */
- /* .. .. .. */
- EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000010U),
- /* .. .. .. FINISH: BY PASS PLL */
- /* .. .. .. START: ASSERT RESET */
- /* .. .. .. PLL_RESET = 1 */
- /* .. .. .. ==> 0XF8000104[0:0] = 0x00000001U */
- /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
- /* .. .. .. */
- EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000001U),
- /* .. .. .. FINISH: ASSERT RESET */
- /* .. .. .. START: DEASSERT RESET */
- /* .. .. .. PLL_RESET = 0 */
- /* .. .. .. ==> 0XF8000104[0:0] = 0x00000000U */
- /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. .. .. */
- EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000000U),
- /* .. .. .. FINISH: DEASSERT RESET */
- /* .. .. .. START: CHECK PLL STATUS */
- /* .. .. .. DDR_PLL_LOCK = 1 */
- /* .. .. .. ==> 0XF800010C[1:1] = 0x00000001U */
- /* .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */
- /* .. .. .. */
- EMIT_MASKPOLL(0XF800010C, 0x00000002U),
- /* .. .. .. FINISH: CHECK PLL STATUS */
- /* .. .. .. START: REMOVE PLL BY PASS */
- /* .. .. .. PLL_BYPASS_FORCE = 0 */
- /* .. .. .. ==> 0XF8000104[4:4] = 0x00000000U */
- /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
- /* .. .. .. */
- EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U),
- /* .. .. .. FINISH: REMOVE PLL BY PASS */
- /* .. .. .. DDR_3XCLKACT = 0x1 */
- /* .. .. .. ==> 0XF8000124[0:0] = 0x00000001U */
- /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
- /* .. .. .. DDR_2XCLKACT = 0x1 */
- /* .. .. .. ==> 0XF8000124[1:1] = 0x00000001U */
- /* .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */
- /* .. .. .. DDR_3XCLK_DIVISOR = 0x2 */
- /* .. .. .. ==> 0XF8000124[25:20] = 0x00000002U */
- /* .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U */
- /* .. .. .. DDR_2XCLK_DIVISOR = 0x3 */
- /* .. .. .. ==> 0XF8000124[31:26] = 0x00000003U */
- /* .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U */
- /* .. .. .. */
- EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U),
- /* .. .. FINISH: DDR PLL INIT */
- /* .. .. START: IO PLL INIT */
- /* .. .. PLL_RES = 0xc */
- /* .. .. ==> 0XF8000118[7:4] = 0x0000000CU */
- /* .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U */
- /* .. .. PLL_CP = 0x2 */
- /* .. .. ==> 0XF8000118[11:8] = 0x00000002U */
- /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */
- /* .. .. LOCK_CNT = 0x1f4 */
- /* .. .. ==> 0XF8000118[21:12] = 0x000001F4U */
- /* .. .. ==> MASK : 0x003FF000U VAL : 0x001F4000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x001F42C0U),
- /* .. .. .. START: UPDATE FB_DIV */
- /* .. .. .. PLL_FDIV = 0x14 */
- /* .. .. .. ==> 0XF8000108[18:12] = 0x00000014U */
- /* .. .. .. ==> MASK : 0x0007F000U VAL : 0x00014000U */
- /* .. .. .. */
- EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x00014000U),
- /* .. .. .. FINISH: UPDATE FB_DIV */
- /* .. .. .. START: BY PASS PLL */
- /* .. .. .. PLL_BYPASS_FORCE = 1 */
- /* .. .. .. ==> 0XF8000108[4:4] = 0x00000001U */
- /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U */
- /* .. .. .. */
- EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U),
- /* .. .. .. FINISH: BY PASS PLL */
- /* .. .. .. START: ASSERT RESET */
- /* .. .. .. PLL_RESET = 1 */
- /* .. .. .. ==> 0XF8000108[0:0] = 0x00000001U */
- /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
- /* .. .. .. */
- EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U),
- /* .. .. .. FINISH: ASSERT RESET */
- /* .. .. .. START: DEASSERT RESET */
- /* .. .. .. PLL_RESET = 0 */
- /* .. .. .. ==> 0XF8000108[0:0] = 0x00000000U */
- /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. .. .. */
- EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U),
- /* .. .. .. FINISH: DEASSERT RESET */
- /* .. .. .. START: CHECK PLL STATUS */
- /* .. .. .. IO_PLL_LOCK = 1 */
- /* .. .. .. ==> 0XF800010C[2:2] = 0x00000001U */
- /* .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U */
- /* .. .. .. */
- EMIT_MASKPOLL(0XF800010C, 0x00000004U),
- /* .. .. .. FINISH: CHECK PLL STATUS */
- /* .. .. .. START: REMOVE PLL BY PASS */
- /* .. .. .. PLL_BYPASS_FORCE = 0 */
- /* .. .. .. ==> 0XF8000108[4:4] = 0x00000000U */
- /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
- /* .. .. .. */
- EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000000U),
- /* .. .. .. FINISH: REMOVE PLL BY PASS */
- /* .. .. FINISH: IO PLL INIT */
- /* .. FINISH: PLL SLCR REGISTERS */
- /* .. START: LOCK IT BACK */
- /* .. LOCK_KEY = 0X767B */
- /* .. ==> 0XF8000004[15:0] = 0x0000767BU */
- /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */
- /* .. */
- EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
- /* .. FINISH: LOCK IT BACK */
- /* FINISH: top */
- /* */
- EMIT_EXIT(),
-
- /* */
-};
-
-unsigned long ps7_clock_init_data_1_0[] = {
- /* START: top */
- /* .. START: SLCR SETTINGS */
- /* .. UNLOCK_KEY = 0XDF0D */
- /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
- /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */
- /* .. */
- EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
- /* .. FINISH: SLCR SETTINGS */
- /* .. START: CLOCK CONTROL SLCR REGISTERS */
- /* .. CLKACT = 0x1 */
- /* .. ==> 0XF8000128[0:0] = 0x00000001U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
- /* .. DIVISOR0 = 0x34 */
- /* .. ==> 0XF8000128[13:8] = 0x00000034U */
- /* .. ==> MASK : 0x00003F00U VAL : 0x00003400U */
- /* .. DIVISOR1 = 0x2 */
- /* .. ==> 0XF8000128[25:20] = 0x00000002U */
- /* .. ==> MASK : 0x03F00000U VAL : 0x00200000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00203401U),
- /* .. CLKACT = 0x1 */
- /* .. ==> 0XF8000138[0:0] = 0x00000001U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
- /* .. SRCSEL = 0x0 */
- /* .. ==> 0XF8000138[4:4] = 0x00000000U */
- /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000001U),
- /* .. CLKACT = 0x1 */
- /* .. ==> 0XF8000140[0:0] = 0x00000001U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
- /* .. SRCSEL = 0x0 */
- /* .. ==> 0XF8000140[6:4] = 0x00000000U */
- /* .. ==> MASK : 0x00000070U VAL : 0x00000000U */
- /* .. DIVISOR = 0x8 */
- /* .. ==> 0XF8000140[13:8] = 0x00000008U */
- /* .. ==> MASK : 0x00003F00U VAL : 0x00000800U */
- /* .. DIVISOR1 = 0x1 */
- /* .. ==> 0XF8000140[25:20] = 0x00000001U */
- /* .. ==> MASK : 0x03F00000U VAL : 0x00100000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00100801U),
- /* .. CLKACT = 0x1 */
- /* .. ==> 0XF800014C[0:0] = 0x00000001U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
- /* .. SRCSEL = 0x0 */
- /* .. ==> 0XF800014C[5:4] = 0x00000000U */
- /* .. ==> MASK : 0x00000030U VAL : 0x00000000U */
- /* .. DIVISOR = 0x5 */
- /* .. ==> 0XF800014C[13:8] = 0x00000005U */
- /* .. ==> MASK : 0x00003F00U VAL : 0x00000500U */
- /* .. */
- EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000501U),
- /* .. CLKACT0 = 0x1 */
- /* .. ==> 0XF8000150[0:0] = 0x00000001U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
- /* .. CLKACT1 = 0x0 */
- /* .. ==> 0XF8000150[1:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. SRCSEL = 0x0 */
- /* .. ==> 0XF8000150[5:4] = 0x00000000U */
- /* .. ==> MASK : 0x00000030U VAL : 0x00000000U */
- /* .. DIVISOR = 0x14 */
- /* .. ==> 0XF8000150[13:8] = 0x00000014U */
- /* .. ==> MASK : 0x00003F00U VAL : 0x00001400U */
- /* .. */
- EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00001401U),
- /* .. CLKACT0 = 0x0 */
- /* .. ==> 0XF8000154[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. CLKACT1 = 0x1 */
- /* .. ==> 0XF8000154[1:1] = 0x00000001U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
- /* .. SRCSEL = 0x0 */
- /* .. ==> 0XF8000154[5:4] = 0x00000000U */
- /* .. ==> MASK : 0x00000030U VAL : 0x00000000U */
- /* .. DIVISOR = 0xa */
- /* .. ==> 0XF8000154[13:8] = 0x0000000AU */
- /* .. ==> MASK : 0x00003F00U VAL : 0x00000A00U */
- /* .. */
- EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00000A02U),
- /* .. .. START: TRACE CLOCK */
- /* .. .. FINISH: TRACE CLOCK */
- /* .. .. CLKACT = 0x1 */
- /* .. .. ==> 0XF8000168[0:0] = 0x00000001U */
- /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
- /* .. .. SRCSEL = 0x0 */
- /* .. .. ==> 0XF8000168[5:4] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
- /* .. .. DIVISOR = 0x5 */
- /* .. .. ==> 0XF8000168[13:8] = 0x00000005U */
- /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000501U),
- /* .. .. SRCSEL = 0x0 */
- /* .. .. ==> 0XF8000170[5:4] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
- /* .. .. DIVISOR0 = 0xa */
- /* .. .. ==> 0XF8000170[13:8] = 0x0000000AU */
- /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U */
- /* .. .. DIVISOR1 = 0x1 */
- /* .. .. ==> 0XF8000170[25:20] = 0x00000001U */
- /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00100A00U),
- /* .. .. SRCSEL = 0x0 */
- /* .. .. ==> 0XF8000180[5:4] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
- /* .. .. DIVISOR0 = 0x7 */
- /* .. .. ==> 0XF8000180[13:8] = 0x00000007U */
- /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000700U */
- /* .. .. DIVISOR1 = 0x1 */
- /* .. .. ==> 0XF8000180[25:20] = 0x00000001U */
- /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00100700U),
- /* .. .. SRCSEL = 0x0 */
- /* .. .. ==> 0XF8000190[5:4] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
- /* .. .. DIVISOR0 = 0x5 */
- /* .. .. ==> 0XF8000190[13:8] = 0x00000005U */
- /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U */
- /* .. .. DIVISOR1 = 0x1 */
- /* .. .. ==> 0XF8000190[25:20] = 0x00000001U */
- /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00100500U),
- /* .. .. SRCSEL = 0x0 */
- /* .. .. ==> 0XF80001A0[5:4] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
- /* .. .. DIVISOR0 = 0x14 */
- /* .. .. ==> 0XF80001A0[13:8] = 0x00000014U */
- /* .. .. ==> MASK : 0x00003F00U VAL : 0x00001400U */
- /* .. .. DIVISOR1 = 0x1 */
- /* .. .. ==> 0XF80001A0[25:20] = 0x00000001U */
- /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00101400U),
- /* .. .. CLK_621_TRUE = 0x1 */
- /* .. .. ==> 0XF80001C4[0:0] = 0x00000001U */
- /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
- /* .. .. */
- EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U),
- /* .. .. DMA_CPU_2XCLKACT = 0x1 */
- /* .. .. ==> 0XF800012C[0:0] = 0x00000001U */
- /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
- /* .. .. USB0_CPU_1XCLKACT = 0x1 */
- /* .. .. ==> 0XF800012C[2:2] = 0x00000001U */
- /* .. .. ==> MASK : 0x00000004U VAL : 0x00000004U */
- /* .. .. USB1_CPU_1XCLKACT = 0x1 */
- /* .. .. ==> 0XF800012C[3:3] = 0x00000001U */
- /* .. .. ==> MASK : 0x00000008U VAL : 0x00000008U */
- /* .. .. GEM0_CPU_1XCLKACT = 0x1 */
- /* .. .. ==> 0XF800012C[6:6] = 0x00000001U */
- /* .. .. ==> MASK : 0x00000040U VAL : 0x00000040U */
- /* .. .. GEM1_CPU_1XCLKACT = 0x0 */
- /* .. .. ==> 0XF800012C[7:7] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000080U VAL : 0x00000000U */
- /* .. .. SDI0_CPU_1XCLKACT = 0x1 */
- /* .. .. ==> 0XF800012C[10:10] = 0x00000001U */
- /* .. .. ==> MASK : 0x00000400U VAL : 0x00000400U */
- /* .. .. SDI1_CPU_1XCLKACT = 0x0 */
- /* .. .. ==> 0XF800012C[11:11] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */
- /* .. .. SPI0_CPU_1XCLKACT = 0x0 */
- /* .. .. ==> 0XF800012C[14:14] = 0x00000000U */
- /* .. .. ==> MASK : 0x00004000U VAL : 0x00000000U */
- /* .. .. SPI1_CPU_1XCLKACT = 0x0 */
- /* .. .. ==> 0XF800012C[15:15] = 0x00000000U */
- /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */
- /* .. .. CAN0_CPU_1XCLKACT = 0x0 */
- /* .. .. ==> 0XF800012C[16:16] = 0x00000000U */
- /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
- /* .. .. CAN1_CPU_1XCLKACT = 0x0 */
- /* .. .. ==> 0XF800012C[17:17] = 0x00000000U */
- /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
- /* .. .. I2C0_CPU_1XCLKACT = 0x1 */
- /* .. .. ==> 0XF800012C[18:18] = 0x00000001U */
- /* .. .. ==> MASK : 0x00040000U VAL : 0x00040000U */
- /* .. .. I2C1_CPU_1XCLKACT = 0x1 */
- /* .. .. ==> 0XF800012C[19:19] = 0x00000001U */
- /* .. .. ==> MASK : 0x00080000U VAL : 0x00080000U */
- /* .. .. UART0_CPU_1XCLKACT = 0x0 */
- /* .. .. ==> 0XF800012C[20:20] = 0x00000000U */
- /* .. .. ==> MASK : 0x00100000U VAL : 0x00000000U */
- /* .. .. UART1_CPU_1XCLKACT = 0x1 */
- /* .. .. ==> 0XF800012C[21:21] = 0x00000001U */
- /* .. .. ==> MASK : 0x00200000U VAL : 0x00200000U */
- /* .. .. GPIO_CPU_1XCLKACT = 0x1 */
- /* .. .. ==> 0XF800012C[22:22] = 0x00000001U */
- /* .. .. ==> MASK : 0x00400000U VAL : 0x00400000U */
- /* .. .. LQSPI_CPU_1XCLKACT = 0x1 */
- /* .. .. ==> 0XF800012C[23:23] = 0x00000001U */
- /* .. .. ==> MASK : 0x00800000U VAL : 0x00800000U */
- /* .. .. SMC_CPU_1XCLKACT = 0x1 */
- /* .. .. ==> 0XF800012C[24:24] = 0x00000001U */
- /* .. .. ==> MASK : 0x01000000U VAL : 0x01000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01EC044DU),
- /* .. FINISH: CLOCK CONTROL SLCR REGISTERS */
- /* .. START: THIS SHOULD BE BLANK */
- /* .. FINISH: THIS SHOULD BE BLANK */
- /* .. START: LOCK IT BACK */
- /* .. LOCK_KEY = 0X767B */
- /* .. ==> 0XF8000004[15:0] = 0x0000767BU */
- /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */
- /* .. */
- EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
- /* .. FINISH: LOCK IT BACK */
- /* FINISH: top */
- /* */
- EMIT_EXIT(),
-
- /* */
-};
-
-unsigned long ps7_ddr_init_data_1_0[] = {
- /* START: top */
- /* .. START: DDR INITIALIZATION */
- /* .. .. START: LOCK DDR */
- /* .. .. reg_ddrc_soft_rstb = 0 */
- /* .. .. ==> 0XF8006000[0:0] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. .. reg_ddrc_powerdown_en = 0x0 */
- /* .. .. ==> 0XF8006000[1:1] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. .. reg_ddrc_data_bus_width = 0x0 */
- /* .. .. ==> 0XF8006000[3:2] = 0x00000000U */
- /* .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U */
- /* .. .. reg_ddrc_burst8_refresh = 0x0 */
- /* .. .. ==> 0XF8006000[6:4] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000070U VAL : 0x00000000U */
- /* .. .. reg_ddrc_rdwr_idle_gap = 0x1 */
- /* .. .. ==> 0XF8006000[13:7] = 0x00000001U */
- /* .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U */
- /* .. .. reg_ddrc_dis_rd_bypass = 0x0 */
- /* .. .. ==> 0XF8006000[14:14] = 0x00000000U */
- /* .. .. ==> MASK : 0x00004000U VAL : 0x00000000U */
- /* .. .. reg_ddrc_dis_act_bypass = 0x0 */
- /* .. .. ==> 0XF8006000[15:15] = 0x00000000U */
- /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */
- /* .. .. reg_ddrc_dis_auto_refresh = 0x0 */
- /* .. .. ==> 0XF8006000[16:16] = 0x00000000U */
- /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000080U),
- /* .. .. FINISH: LOCK DDR */
- /* .. .. reg_ddrc_t_rfc_nom_x32 = 0x7f */
- /* .. .. ==> 0XF8006004[11:0] = 0x0000007FU */
- /* .. .. ==> MASK : 0x00000FFFU VAL : 0x0000007FU */
- /* .. .. reg_ddrc_active_ranks = 0x1 */
- /* .. .. ==> 0XF8006004[13:12] = 0x00000001U */
- /* .. .. ==> MASK : 0x00003000U VAL : 0x00001000U */
- /* .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 */
- /* .. .. ==> 0XF8006004[18:14] = 0x00000000U */
- /* .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U */
- /* .. .. reg_ddrc_wr_odt_block = 0x1 */
- /* .. .. ==> 0XF8006004[20:19] = 0x00000001U */
- /* .. .. ==> MASK : 0x00180000U VAL : 0x00080000U */
- /* .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0 */
- /* .. .. ==> 0XF8006004[21:21] = 0x00000000U */
- /* .. .. ==> MASK : 0x00200000U VAL : 0x00000000U */
- /* .. .. reg_ddrc_addrmap_cs_bit1 = 0x0 */
- /* .. .. ==> 0XF8006004[26:22] = 0x00000000U */
- /* .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U */
- /* .. .. reg_ddrc_addrmap_open_bank = 0x0 */
- /* .. .. ==> 0XF8006004[27:27] = 0x00000000U */
- /* .. .. ==> MASK : 0x08000000U VAL : 0x00000000U */
- /* .. .. reg_ddrc_addrmap_4bank_ram = 0x0 */
- /* .. .. ==> 0XF8006004[28:28] = 0x00000000U */
- /* .. .. ==> MASK : 0x10000000U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU, 0x0008107FU),
- /* .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf */
- /* .. .. ==> 0XF8006008[10:0] = 0x0000000FU */
- /* .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU */
- /* .. .. reg_ddrc_hpr_max_starve_x32 = 0xf */
- /* .. .. ==> 0XF8006008[21:11] = 0x0000000FU */
- /* .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U */
- /* .. .. reg_ddrc_hpr_xact_run_length = 0xf */
- /* .. .. ==> 0XF8006008[25:22] = 0x0000000FU */
- /* .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU, 0x03C0780FU),
- /* .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 */
- /* .. .. ==> 0XF800600C[10:0] = 0x00000001U */
- /* .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U */
- /* .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 */
- /* .. .. ==> 0XF800600C[21:11] = 0x00000002U */
- /* .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U */
- /* .. .. reg_ddrc_lpr_xact_run_length = 0x8 */
- /* .. .. ==> 0XF800600C[25:22] = 0x00000008U */
- /* .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU, 0x02001001U),
- /* .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 */
- /* .. .. ==> 0XF8006010[10:0] = 0x00000001U */
- /* .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U */
- /* .. .. reg_ddrc_w_xact_run_length = 0x8 */
- /* .. .. ==> 0XF8006010[14:11] = 0x00000008U */
- /* .. .. ==> MASK : 0x00007800U VAL : 0x00004000U */
- /* .. .. reg_ddrc_w_max_starve_x32 = 0x2 */
- /* .. .. ==> 0XF8006010[25:15] = 0x00000002U */
- /* .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU, 0x00014001U),
- /* .. .. reg_ddrc_t_rc = 0x1a */
- /* .. .. ==> 0XF8006014[5:0] = 0x0000001AU */
- /* .. .. ==> MASK : 0x0000003FU VAL : 0x0000001AU */
- /* .. .. reg_ddrc_t_rfc_min = 0x54 */
- /* .. .. ==> 0XF8006014[13:6] = 0x00000054U */
- /* .. .. ==> MASK : 0x00003FC0U VAL : 0x00001500U */
- /* .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 */
- /* .. .. ==> 0XF8006014[20:14] = 0x00000010U */
- /* .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU, 0x0004151AU),
- /* .. .. reg_ddrc_wr2pre = 0x12 */
- /* .. .. ==> 0XF8006018[4:0] = 0x00000012U */
- /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U */
- /* .. .. reg_ddrc_powerdown_to_x32 = 0x6 */
- /* .. .. ==> 0XF8006018[9:5] = 0x00000006U */
- /* .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U */
- /* .. .. reg_ddrc_t_faw = 0x15 */
- /* .. .. ==> 0XF8006018[15:10] = 0x00000015U */
- /* .. .. ==> MASK : 0x0000FC00U VAL : 0x00005400U */
- /* .. .. reg_ddrc_t_ras_max = 0x23 */
- /* .. .. ==> 0XF8006018[21:16] = 0x00000023U */
- /* .. .. ==> MASK : 0x003F0000U VAL : 0x00230000U */
- /* .. .. reg_ddrc_t_ras_min = 0x13 */
- /* .. .. ==> 0XF8006018[26:22] = 0x00000013U */
- /* .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U */
- /* .. .. reg_ddrc_t_cke = 0x4 */
- /* .. .. ==> 0XF8006018[31:28] = 0x00000004U */
- /* .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU, 0x44E354D2U),
- /* .. .. reg_ddrc_write_latency = 0x5 */
- /* .. .. ==> 0XF800601C[4:0] = 0x00000005U */
- /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U */
- /* .. .. reg_ddrc_rd2wr = 0x7 */
- /* .. .. ==> 0XF800601C[9:5] = 0x00000007U */
- /* .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U */
- /* .. .. reg_ddrc_wr2rd = 0xe */
- /* .. .. ==> 0XF800601C[14:10] = 0x0000000EU */
- /* .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U */
- /* .. .. reg_ddrc_t_xp = 0x4 */
- /* .. .. ==> 0XF800601C[19:15] = 0x00000004U */
- /* .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U */
- /* .. .. reg_ddrc_pad_pd = 0x0 */
- /* .. .. ==> 0XF800601C[22:20] = 0x00000000U */
- /* .. .. ==> MASK : 0x00700000U VAL : 0x00000000U */
- /* .. .. reg_ddrc_rd2pre = 0x4 */
- /* .. .. ==> 0XF800601C[27:23] = 0x00000004U */
- /* .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U */
- /* .. .. reg_ddrc_t_rcd = 0x7 */
- /* .. .. ==> 0XF800601C[31:28] = 0x00000007U */
- /* .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU, 0x720238E5U),
- /* .. .. reg_ddrc_t_ccd = 0x4 */
- /* .. .. ==> 0XF8006020[4:2] = 0x00000004U */
- /* .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U */
- /* .. .. reg_ddrc_t_rrd = 0x6 */
- /* .. .. ==> 0XF8006020[7:5] = 0x00000006U */
- /* .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U */
- /* .. .. reg_ddrc_refresh_margin = 0x2 */
- /* .. .. ==> 0XF8006020[11:8] = 0x00000002U */
- /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */
- /* .. .. reg_ddrc_t_rp = 0x7 */
- /* .. .. ==> 0XF8006020[15:12] = 0x00000007U */
- /* .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U */
- /* .. .. reg_ddrc_refresh_to_x32 = 0x8 */
- /* .. .. ==> 0XF8006020[20:16] = 0x00000008U */
- /* .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U */
- /* .. .. reg_ddrc_sdram = 0x1 */
- /* .. .. ==> 0XF8006020[21:21] = 0x00000001U */
- /* .. .. ==> MASK : 0x00200000U VAL : 0x00200000U */
- /* .. .. reg_ddrc_mobile = 0x0 */
- /* .. .. ==> 0XF8006020[22:22] = 0x00000000U */
- /* .. .. ==> MASK : 0x00400000U VAL : 0x00000000U */
- /* .. .. reg_ddrc_clock_stop_en = 0x0 */
- /* .. .. ==> 0XF8006020[23:23] = 0x00000000U */
- /* .. .. ==> MASK : 0x00800000U VAL : 0x00000000U */
- /* .. .. reg_ddrc_read_latency = 0x7 */
- /* .. .. ==> 0XF8006020[28:24] = 0x00000007U */
- /* .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U */
- /* .. .. reg_phy_mode_ddr1_ddr2 = 0x1 */
- /* .. .. ==> 0XF8006020[29:29] = 0x00000001U */
- /* .. .. ==> MASK : 0x20000000U VAL : 0x20000000U */
- /* .. .. reg_ddrc_dis_pad_pd = 0x0 */
- /* .. .. ==> 0XF8006020[30:30] = 0x00000000U */
- /* .. .. ==> MASK : 0x40000000U VAL : 0x00000000U */
- /* .. .. reg_ddrc_loopback = 0x0 */
- /* .. .. ==> 0XF8006020[31:31] = 0x00000000U */
- /* .. .. ==> MASK : 0x80000000U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU, 0x272872D0U),
- /* .. .. reg_ddrc_en_2t_timing_mode = 0x0 */
- /* .. .. ==> 0XF8006024[0:0] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. .. reg_ddrc_prefer_write = 0x0 */
- /* .. .. ==> 0XF8006024[1:1] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. .. reg_ddrc_max_rank_rd = 0xf */
- /* .. .. ==> 0XF8006024[5:2] = 0x0000000FU */
- /* .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU */
- /* .. .. reg_ddrc_mr_wr = 0x0 */
- /* .. .. ==> 0XF8006024[6:6] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000040U VAL : 0x00000000U */
- /* .. .. reg_ddrc_mr_addr = 0x0 */
- /* .. .. ==> 0XF8006024[8:7] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000180U VAL : 0x00000000U */
- /* .. .. reg_ddrc_mr_data = 0x0 */
- /* .. .. ==> 0XF8006024[24:9] = 0x00000000U */
- /* .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U */
- /* .. .. ddrc_reg_mr_wr_busy = 0x0 */
- /* .. .. ==> 0XF8006024[25:25] = 0x00000000U */
- /* .. .. ==> MASK : 0x02000000U VAL : 0x00000000U */
- /* .. .. reg_ddrc_mr_type = 0x0 */
- /* .. .. ==> 0XF8006024[26:26] = 0x00000000U */
- /* .. .. ==> MASK : 0x04000000U VAL : 0x00000000U */
- /* .. .. reg_ddrc_mr_rdata_valid = 0x0 */
- /* .. .. ==> 0XF8006024[27:27] = 0x00000000U */
- /* .. .. ==> MASK : 0x08000000U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU, 0x0000003CU),
- /* .. .. reg_ddrc_final_wait_x32 = 0x7 */
- /* .. .. ==> 0XF8006028[6:0] = 0x00000007U */
- /* .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U */
- /* .. .. reg_ddrc_pre_ocd_x32 = 0x0 */
- /* .. .. ==> 0XF8006028[10:7] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000780U VAL : 0x00000000U */
- /* .. .. reg_ddrc_t_mrd = 0x4 */
- /* .. .. ==> 0XF8006028[13:11] = 0x00000004U */
- /* .. .. ==> MASK : 0x00003800U VAL : 0x00002000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006028, 0x00003FFFU, 0x00002007U),
- /* .. .. reg_ddrc_emr2 = 0x8 */
- /* .. .. ==> 0XF800602C[15:0] = 0x00000008U */
- /* .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U */
- /* .. .. reg_ddrc_emr3 = 0x0 */
- /* .. .. ==> 0XF800602C[31:16] = 0x00000000U */
- /* .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU, 0x00000008U),
- /* .. .. reg_ddrc_mr = 0x930 */
- /* .. .. ==> 0XF8006030[15:0] = 0x00000930U */
- /* .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U */
- /* .. .. reg_ddrc_emr = 0x4 */
- /* .. .. ==> 0XF8006030[31:16] = 0x00000004U */
- /* .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU, 0x00040930U),
- /* .. .. reg_ddrc_burst_rdwr = 0x4 */
- /* .. .. ==> 0XF8006034[3:0] = 0x00000004U */
- /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U */
- /* .. .. reg_ddrc_pre_cke_x1024 = 0x167 */
- /* .. .. ==> 0XF8006034[13:4] = 0x00000167U */
- /* .. .. ==> MASK : 0x00003FF0U VAL : 0x00001670U */
- /* .. .. reg_ddrc_post_cke_x1024 = 0x1 */
- /* .. .. ==> 0XF8006034[25:16] = 0x00000001U */
- /* .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U */
- /* .. .. reg_ddrc_burstchop = 0x0 */
- /* .. .. ==> 0XF8006034[28:28] = 0x00000000U */
- /* .. .. ==> MASK : 0x10000000U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x00011674U),
- /* .. .. reg_ddrc_force_low_pri_n = 0x0 */
- /* .. .. ==> 0XF8006038[0:0] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. .. reg_ddrc_dis_dq = 0x0 */
- /* .. .. ==> 0XF8006038[1:1] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. .. reg_phy_debug_mode = 0x0 */
- /* .. .. ==> 0XF8006038[6:6] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000040U VAL : 0x00000000U */
- /* .. .. reg_phy_wr_level_start = 0x0 */
- /* .. .. ==> 0XF8006038[7:7] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000080U VAL : 0x00000000U */
- /* .. .. reg_phy_rd_level_start = 0x0 */
- /* .. .. ==> 0XF8006038[8:8] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000100U VAL : 0x00000000U */
- /* .. .. reg_phy_dq0_wait_t = 0x0 */
- /* .. .. ==> 0XF8006038[12:9] = 0x00000000U */
- /* .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006038, 0x00001FC3U, 0x00000000U),
- /* .. .. reg_ddrc_addrmap_bank_b0 = 0x7 */
- /* .. .. ==> 0XF800603C[3:0] = 0x00000007U */
- /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U */
- /* .. .. reg_ddrc_addrmap_bank_b1 = 0x7 */
- /* .. .. ==> 0XF800603C[7:4] = 0x00000007U */
- /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U */
- /* .. .. reg_ddrc_addrmap_bank_b2 = 0x7 */
- /* .. .. ==> 0XF800603C[11:8] = 0x00000007U */
- /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U */
- /* .. .. reg_ddrc_addrmap_col_b5 = 0x0 */
- /* .. .. ==> 0XF800603C[15:12] = 0x00000000U */
- /* .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U */
- /* .. .. reg_ddrc_addrmap_col_b6 = 0x0 */
- /* .. .. ==> 0XF800603C[19:16] = 0x00000000U */
- /* .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU, 0x00000777U),
- /* .. .. reg_ddrc_addrmap_col_b2 = 0x0 */
- /* .. .. ==> 0XF8006040[3:0] = 0x00000000U */
- /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U */
- /* .. .. reg_ddrc_addrmap_col_b3 = 0x0 */
- /* .. .. ==> 0XF8006040[7:4] = 0x00000000U */
- /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */
- /* .. .. reg_ddrc_addrmap_col_b4 = 0x0 */
- /* .. .. ==> 0XF8006040[11:8] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U */
- /* .. .. reg_ddrc_addrmap_col_b7 = 0x0 */
- /* .. .. ==> 0XF8006040[15:12] = 0x00000000U */
- /* .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U */
- /* .. .. reg_ddrc_addrmap_col_b8 = 0x0 */
- /* .. .. ==> 0XF8006040[19:16] = 0x00000000U */
- /* .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U */
- /* .. .. reg_ddrc_addrmap_col_b9 = 0xf */
- /* .. .. ==> 0XF8006040[23:20] = 0x0000000FU */
- /* .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U */
- /* .. .. reg_ddrc_addrmap_col_b10 = 0xf */
- /* .. .. ==> 0XF8006040[27:24] = 0x0000000FU */
- /* .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U */
- /* .. .. reg_ddrc_addrmap_col_b11 = 0xf */
- /* .. .. ==> 0XF8006040[31:28] = 0x0000000FU */
- /* .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU, 0xFFF00000U),
- /* .. .. reg_ddrc_addrmap_row_b0 = 0x6 */
- /* .. .. ==> 0XF8006044[3:0] = 0x00000006U */
- /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U */
- /* .. .. reg_ddrc_addrmap_row_b1 = 0x6 */
- /* .. .. ==> 0XF8006044[7:4] = 0x00000006U */
- /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U */
- /* .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 */
- /* .. .. ==> 0XF8006044[11:8] = 0x00000006U */
- /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U */
- /* .. .. reg_ddrc_addrmap_row_b12 = 0x6 */
- /* .. .. ==> 0XF8006044[15:12] = 0x00000006U */
- /* .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U */
- /* .. .. reg_ddrc_addrmap_row_b13 = 0x6 */
- /* .. .. ==> 0XF8006044[19:16] = 0x00000006U */
- /* .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U */
- /* .. .. reg_ddrc_addrmap_row_b14 = 0xf */
- /* .. .. ==> 0XF8006044[23:20] = 0x0000000FU */
- /* .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U */
- /* .. .. reg_ddrc_addrmap_row_b15 = 0xf */
- /* .. .. ==> 0XF8006044[27:24] = 0x0000000FU */
- /* .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU, 0x0FF66666U),
- /* .. .. reg_ddrc_rank0_rd_odt = 0x0 */
- /* .. .. ==> 0XF8006048[2:0] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000007U VAL : 0x00000000U */
- /* .. .. reg_ddrc_rank0_wr_odt = 0x1 */
- /* .. .. ==> 0XF8006048[5:3] = 0x00000001U */
- /* .. .. ==> MASK : 0x00000038U VAL : 0x00000008U */
- /* .. .. reg_ddrc_rank1_rd_odt = 0x1 */
- /* .. .. ==> 0XF8006048[8:6] = 0x00000001U */
- /* .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U */
- /* .. .. reg_ddrc_rank1_wr_odt = 0x1 */
- /* .. .. ==> 0XF8006048[11:9] = 0x00000001U */
- /* .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
- /* .. .. reg_phy_rd_local_odt = 0x0 */
- /* .. .. ==> 0XF8006048[13:12] = 0x00000000U */
- /* .. .. ==> MASK : 0x00003000U VAL : 0x00000000U */
- /* .. .. reg_phy_wr_local_odt = 0x3 */
- /* .. .. ==> 0XF8006048[15:14] = 0x00000003U */
- /* .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U */
- /* .. .. reg_phy_idle_local_odt = 0x3 */
- /* .. .. ==> 0XF8006048[17:16] = 0x00000003U */
- /* .. .. ==> MASK : 0x00030000U VAL : 0x00030000U */
- /* .. .. reg_ddrc_rank2_rd_odt = 0x0 */
- /* .. .. ==> 0XF8006048[20:18] = 0x00000000U */
- /* .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U */
- /* .. .. reg_ddrc_rank2_wr_odt = 0x0 */
- /* .. .. ==> 0XF8006048[23:21] = 0x00000000U */
- /* .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U */
- /* .. .. reg_ddrc_rank3_rd_odt = 0x0 */
- /* .. .. ==> 0XF8006048[26:24] = 0x00000000U */
- /* .. .. ==> MASK : 0x07000000U VAL : 0x00000000U */
- /* .. .. reg_ddrc_rank3_wr_odt = 0x0 */
- /* .. .. ==> 0XF8006048[29:27] = 0x00000000U */
- /* .. .. ==> MASK : 0x38000000U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU, 0x0003C248U),
- /* .. .. reg_phy_rd_cmd_to_data = 0x0 */
- /* .. .. ==> 0XF8006050[3:0] = 0x00000000U */
- /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U */
- /* .. .. reg_phy_wr_cmd_to_data = 0x0 */
- /* .. .. ==> 0XF8006050[7:4] = 0x00000000U */
- /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */
- /* .. .. reg_phy_rdc_we_to_re_delay = 0x8 */
- /* .. .. ==> 0XF8006050[11:8] = 0x00000008U */
- /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U */
- /* .. .. reg_phy_rdc_fifo_rst_disable = 0x0 */
- /* .. .. ==> 0XF8006050[15:15] = 0x00000000U */
- /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */
- /* .. .. reg_phy_use_fixed_re = 0x1 */
- /* .. .. ==> 0XF8006050[16:16] = 0x00000001U */
- /* .. .. ==> MASK : 0x00010000U VAL : 0x00010000U */
- /* .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 */
- /* .. .. ==> 0XF8006050[17:17] = 0x00000000U */
- /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
- /* .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 */
- /* .. .. ==> 0XF8006050[18:18] = 0x00000000U */
- /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
- /* .. .. reg_phy_clk_stall_level = 0x0 */
- /* .. .. ==> 0XF8006050[19:19] = 0x00000000U */
- /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */
- /* .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 */
- /* .. .. ==> 0XF8006050[27:24] = 0x00000007U */
- /* .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U */
- /* .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 */
- /* .. .. ==> 0XF8006050[31:28] = 0x00000007U */
- /* .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU, 0x77010800U),
- /* .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1 */
- /* .. .. ==> 0XF8006058[7:0] = 0x00000001U */
- /* .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U */
- /* .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1 */
- /* .. .. ==> 0XF8006058[15:8] = 0x00000001U */
- /* .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U */
- /* .. .. reg_ddrc_dis_dll_calib = 0x0 */
- /* .. .. ==> 0XF8006058[16:16] = 0x00000000U */
- /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU, 0x00000101U),
- /* .. .. reg_ddrc_rd_odt_delay = 0x3 */
- /* .. .. ==> 0XF800605C[3:0] = 0x00000003U */
- /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U */
- /* .. .. reg_ddrc_wr_odt_delay = 0x0 */
- /* .. .. ==> 0XF800605C[7:4] = 0x00000000U */
- /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */
- /* .. .. reg_ddrc_rd_odt_hold = 0x0 */
- /* .. .. ==> 0XF800605C[11:8] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U */
- /* .. .. reg_ddrc_wr_odt_hold = 0x5 */
- /* .. .. ==> 0XF800605C[15:12] = 0x00000005U */
- /* .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU, 0x00005003U),
- /* .. .. reg_ddrc_pageclose = 0x0 */
- /* .. .. ==> 0XF8006060[0:0] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. .. reg_ddrc_lpr_num_entries = 0x1f */
- /* .. .. ==> 0XF8006060[6:1] = 0x0000001FU */
- /* .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU */
- /* .. .. reg_ddrc_auto_pre_en = 0x0 */
- /* .. .. ==> 0XF8006060[7:7] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000080U VAL : 0x00000000U */
- /* .. .. reg_ddrc_refresh_update_level = 0x0 */
- /* .. .. ==> 0XF8006060[8:8] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000100U VAL : 0x00000000U */
- /* .. .. reg_ddrc_dis_wc = 0x0 */
- /* .. .. ==> 0XF8006060[9:9] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000200U VAL : 0x00000000U */
- /* .. .. reg_ddrc_dis_collision_page_opt = 0x0 */
- /* .. .. ==> 0XF8006060[10:10] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
- /* .. .. reg_ddrc_selfref_en = 0x0 */
- /* .. .. ==> 0XF8006060[12:12] = 0x00000000U */
- /* .. .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006060, 0x000017FFU, 0x0000003EU),
- /* .. .. reg_ddrc_go2critical_hysteresis = 0x0 */
- /* .. .. ==> 0XF8006064[12:5] = 0x00000000U */
- /* .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U */
- /* .. .. reg_arb_go2critical_en = 0x1 */
- /* .. .. ==> 0XF8006064[17:17] = 0x00000001U */
- /* .. .. ==> MASK : 0x00020000U VAL : 0x00020000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006064, 0x00021FE0U, 0x00020000U),
- /* .. .. reg_ddrc_wrlvl_ww = 0x41 */
- /* .. .. ==> 0XF8006068[7:0] = 0x00000041U */
- /* .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U */
- /* .. .. reg_ddrc_rdlvl_rr = 0x41 */
- /* .. .. ==> 0XF8006068[15:8] = 0x00000041U */
- /* .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U */
- /* .. .. reg_ddrc_dfi_t_wlmrd = 0x28 */
- /* .. .. ==> 0XF8006068[25:16] = 0x00000028U */
- /* .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU, 0x00284141U),
- /* .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 */
- /* .. .. ==> 0XF800606C[7:0] = 0x00000010U */
- /* .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U */
- /* .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 */
- /* .. .. ==> 0XF800606C[15:8] = 0x00000016U */
- /* .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U */
- /* .. .. */
- EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU, 0x00001610U),
- /* .. .. refresh_timer0_start_value_x32 = 0x0 */
- /* .. .. ==> 0XF80060A0[11:0] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U */
- /* .. .. refresh_timer1_start_value_x32 = 0x8 */
- /* .. .. ==> 0XF80060A0[23:12] = 0x00000008U */
- /* .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU, 0x00008000U),
- /* .. .. reg_ddrc_dis_auto_zq = 0x0 */
- /* .. .. ==> 0XF80060A4[0:0] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. .. reg_ddrc_ddr3 = 0x1 */
- /* .. .. ==> 0XF80060A4[1:1] = 0x00000001U */
- /* .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */
- /* .. .. reg_ddrc_t_mod = 0x200 */
- /* .. .. ==> 0XF80060A4[11:2] = 0x00000200U */
- /* .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U */
- /* .. .. reg_ddrc_t_zq_long_nop = 0x200 */
- /* .. .. ==> 0XF80060A4[21:12] = 0x00000200U */
- /* .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U */
- /* .. .. reg_ddrc_t_zq_short_nop = 0x40 */
- /* .. .. ==> 0XF80060A4[31:22] = 0x00000040U */
- /* .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U),
- /* .. .. t_zq_short_interval_x1024 = 0xc845 */
- /* .. .. ==> 0XF80060A8[19:0] = 0x0000C845U */
- /* .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000C845U */
- /* .. .. dram_rstn_x1024 = 0x67 */
- /* .. .. ==> 0XF80060A8[27:20] = 0x00000067U */
- /* .. .. ==> MASK : 0x0FF00000U VAL : 0x06700000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0670C845U),
- /* .. .. deeppowerdown_en = 0x0 */
- /* .. .. ==> 0XF80060AC[0:0] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. .. deeppowerdown_to_x1024 = 0xff */
- /* .. .. ==> 0XF80060AC[8:1] = 0x000000FFU */
- /* .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU */
- /* .. .. */
- EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU),
- /* .. .. dfi_wrlvl_max_x1024 = 0xfff */
- /* .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU */
- /* .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU */
- /* .. .. dfi_rdlvl_max_x1024 = 0xfff */
- /* .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU */
- /* .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U */
- /* .. .. ddrc_reg_twrlvl_max_error = 0x0 */
- /* .. .. ==> 0XF80060B0[24:24] = 0x00000000U */
- /* .. .. ==> MASK : 0x01000000U VAL : 0x00000000U */
- /* .. .. ddrc_reg_trdlvl_max_error = 0x0 */
- /* .. .. ==> 0XF80060B0[25:25] = 0x00000000U */
- /* .. .. ==> MASK : 0x02000000U VAL : 0x00000000U */
- /* .. .. reg_ddrc_dfi_wr_level_en = 0x1 */
- /* .. .. ==> 0XF80060B0[26:26] = 0x00000001U */
- /* .. .. ==> MASK : 0x04000000U VAL : 0x04000000U */
- /* .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 */
- /* .. .. ==> 0XF80060B0[27:27] = 0x00000001U */
- /* .. .. ==> MASK : 0x08000000U VAL : 0x08000000U */
- /* .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 */
- /* .. .. ==> 0XF80060B0[28:28] = 0x00000001U */
- /* .. .. ==> MASK : 0x10000000U VAL : 0x10000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
- /* .. .. reg_ddrc_2t_delay = 0x0 */
- /* .. .. ==> 0XF80060B4[8:0] = 0x00000000U */
- /* .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U */
- /* .. .. reg_ddrc_skip_ocd = 0x1 */
- /* .. .. ==> 0XF80060B4[9:9] = 0x00000001U */
- /* .. .. ==> MASK : 0x00000200U VAL : 0x00000200U */
- /* .. .. reg_ddrc_dis_pre_bypass = 0x0 */
- /* .. .. ==> 0XF80060B4[10:10] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF80060B4, 0x000007FFU, 0x00000200U),
- /* .. .. reg_ddrc_dfi_t_rddata_en = 0x6 */
- /* .. .. ==> 0XF80060B8[4:0] = 0x00000006U */
- /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U */
- /* .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 */
- /* .. .. ==> 0XF80060B8[14:5] = 0x00000003U */
- /* .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U */
- /* .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 */
- /* .. .. ==> 0XF80060B8[24:15] = 0x00000040U */
- /* .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU, 0x00200066U),
- /* .. .. START: RESET ECC ERROR */
- /* .. .. Clear_Uncorrectable_DRAM_ECC_error = 1 */
- /* .. .. ==> 0XF80060C4[0:0] = 0x00000001U */
- /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
- /* .. .. Clear_Correctable_DRAM_ECC_error = 1 */
- /* .. .. ==> 0XF80060C4[1:1] = 0x00000001U */
- /* .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */
- /* .. .. */
- EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000003U),
- /* .. .. FINISH: RESET ECC ERROR */
- /* .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 */
- /* .. .. ==> 0XF80060C4[0:0] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. .. Clear_Correctable_DRAM_ECC_error = 0x0 */
- /* .. .. ==> 0XF80060C4[1:1] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000000U),
- /* .. .. CORR_ECC_LOG_VALID = 0x0 */
- /* .. .. ==> 0XF80060C8[0:0] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. .. ECC_CORRECTED_BIT_NUM = 0x0 */
- /* .. .. ==> 0XF80060C8[7:1] = 0x00000000U */
- /* .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF80060C8, 0x000000FFU, 0x00000000U),
- /* .. .. UNCORR_ECC_LOG_VALID = 0x0 */
- /* .. .. ==> 0XF80060DC[0:0] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF80060DC, 0x00000001U, 0x00000000U),
- /* .. .. STAT_NUM_CORR_ERR = 0x0 */
- /* .. .. ==> 0XF80060F0[15:8] = 0x00000000U */
- /* .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U */
- /* .. .. STAT_NUM_UNCORR_ERR = 0x0 */
- /* .. .. ==> 0XF80060F0[7:0] = 0x00000000U */
- /* .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU, 0x00000000U),
- /* .. .. reg_ddrc_ecc_mode = 0x0 */
- /* .. .. ==> 0XF80060F4[2:0] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000007U VAL : 0x00000000U */
- /* .. .. reg_ddrc_dis_scrub = 0x1 */
- /* .. .. ==> 0XF80060F4[3:3] = 0x00000001U */
- /* .. .. ==> MASK : 0x00000008U VAL : 0x00000008U */
- /* .. .. */
- EMIT_MASKWRITE(0XF80060F4, 0x0000000FU, 0x00000008U),
- /* .. .. reg_phy_dif_on = 0x0 */
- /* .. .. ==> 0XF8006114[3:0] = 0x00000000U */
- /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U */
- /* .. .. reg_phy_dif_off = 0x0 */
- /* .. .. ==> 0XF8006114[7:4] = 0x00000000U */
- /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006114, 0x000000FFU, 0x00000000U),
- /* .. .. reg_phy_data_slice_in_use = 0x1 */
- /* .. .. ==> 0XF8006118[0:0] = 0x00000001U */
- /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
- /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
- /* .. .. ==> 0XF8006118[1:1] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
- /* .. .. ==> 0XF8006118[2:2] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
- /* .. .. ==> 0XF8006118[3:3] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */
- /* .. .. reg_phy_board_lpbk_tx = 0x0 */
- /* .. .. ==> 0XF8006118[4:4] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
- /* .. .. reg_phy_board_lpbk_rx = 0x0 */
- /* .. .. ==> 0XF8006118[5:5] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000020U VAL : 0x00000000U */
- /* .. .. reg_phy_bist_shift_dq = 0x0 */
- /* .. .. ==> 0XF8006118[14:6] = 0x00000000U */
- /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */
- /* .. .. reg_phy_bist_err_clr = 0x0 */
- /* .. .. ==> 0XF8006118[23:15] = 0x00000000U */
- /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */
- /* .. .. reg_phy_dq_offset = 0x40 */
- /* .. .. ==> 0XF8006118[30:24] = 0x00000040U */
- /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU, 0x40000001U),
- /* .. .. reg_phy_data_slice_in_use = 0x1 */
- /* .. .. ==> 0XF800611C[0:0] = 0x00000001U */
- /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
- /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
- /* .. .. ==> 0XF800611C[1:1] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
- /* .. .. ==> 0XF800611C[2:2] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
- /* .. .. ==> 0XF800611C[3:3] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */
- /* .. .. reg_phy_board_lpbk_tx = 0x0 */
- /* .. .. ==> 0XF800611C[4:4] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
- /* .. .. reg_phy_board_lpbk_rx = 0x0 */
- /* .. .. ==> 0XF800611C[5:5] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000020U VAL : 0x00000000U */
- /* .. .. reg_phy_bist_shift_dq = 0x0 */
- /* .. .. ==> 0XF800611C[14:6] = 0x00000000U */
- /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */
- /* .. .. reg_phy_bist_err_clr = 0x0 */
- /* .. .. ==> 0XF800611C[23:15] = 0x00000000U */
- /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */
- /* .. .. reg_phy_dq_offset = 0x40 */
- /* .. .. ==> 0XF800611C[30:24] = 0x00000040U */
- /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU, 0x40000001U),
- /* .. .. reg_phy_data_slice_in_use = 0x1 */
- /* .. .. ==> 0XF8006120[0:0] = 0x00000001U */
- /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
- /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
- /* .. .. ==> 0XF8006120[1:1] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
- /* .. .. ==> 0XF8006120[2:2] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
- /* .. .. ==> 0XF8006120[3:3] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */
- /* .. .. reg_phy_board_lpbk_tx = 0x0 */
- /* .. .. ==> 0XF8006120[4:4] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
- /* .. .. reg_phy_board_lpbk_rx = 0x0 */
- /* .. .. ==> 0XF8006120[5:5] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000020U VAL : 0x00000000U */
- /* .. .. reg_phy_bist_shift_dq = 0x0 */
- /* .. .. ==> 0XF8006120[14:6] = 0x00000000U */
- /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */
- /* .. .. reg_phy_bist_err_clr = 0x0 */
- /* .. .. ==> 0XF8006120[23:15] = 0x00000000U */
- /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */
- /* .. .. reg_phy_dq_offset = 0x40 */
- /* .. .. ==> 0XF8006120[30:24] = 0x00000040U */
- /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU, 0x40000001U),
- /* .. .. reg_phy_data_slice_in_use = 0x1 */
- /* .. .. ==> 0XF8006124[0:0] = 0x00000001U */
- /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
- /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
- /* .. .. ==> 0XF8006124[1:1] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
- /* .. .. ==> 0XF8006124[2:2] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
- /* .. .. ==> 0XF8006124[3:3] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */
- /* .. .. reg_phy_board_lpbk_tx = 0x0 */
- /* .. .. ==> 0XF8006124[4:4] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
- /* .. .. reg_phy_board_lpbk_rx = 0x0 */
- /* .. .. ==> 0XF8006124[5:5] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000020U VAL : 0x00000000U */
- /* .. .. reg_phy_bist_shift_dq = 0x0 */
- /* .. .. ==> 0XF8006124[14:6] = 0x00000000U */
- /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */
- /* .. .. reg_phy_bist_err_clr = 0x0 */
- /* .. .. ==> 0XF8006124[23:15] = 0x00000000U */
- /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */
- /* .. .. reg_phy_dq_offset = 0x40 */
- /* .. .. ==> 0XF8006124[30:24] = 0x00000040U */
- /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU, 0x40000001U),
- /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
- /* .. .. ==> 0XF800612C[9:0] = 0x00000000U */
- /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */
- /* .. .. reg_phy_gatelvl_init_ratio = 0x8f */
- /* .. .. ==> 0XF800612C[19:10] = 0x0000008FU */
- /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00023C00U */
- /* .. .. */
- EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU, 0x00023C00U),
- /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
- /* .. .. ==> 0XF8006130[9:0] = 0x00000000U */
- /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */
- /* .. .. reg_phy_gatelvl_init_ratio = 0x8a */
- /* .. .. ==> 0XF8006130[19:10] = 0x0000008AU */
- /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00022800U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU, 0x00022800U),
- /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
- /* .. .. ==> 0XF8006134[9:0] = 0x00000000U */
- /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */
- /* .. .. reg_phy_gatelvl_init_ratio = 0x8b */
- /* .. .. ==> 0XF8006134[19:10] = 0x0000008BU */
- /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00022C00U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU, 0x00022C00U),
- /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
- /* .. .. ==> 0XF8006138[9:0] = 0x00000000U */
- /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */
- /* .. .. reg_phy_gatelvl_init_ratio = 0x92 */
- /* .. .. ==> 0XF8006138[19:10] = 0x00000092U */
- /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00024800U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU, 0x00024800U),
- /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
- /* .. .. ==> 0XF8006140[9:0] = 0x00000035U */
- /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */
- /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
- /* .. .. ==> 0XF8006140[10:10] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
- /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
- /* .. .. ==> 0XF8006140[19:11] = 0x00000000U */
- /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU, 0x00000035U),
- /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
- /* .. .. ==> 0XF8006144[9:0] = 0x00000035U */
- /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */
- /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
- /* .. .. ==> 0XF8006144[10:10] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
- /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
- /* .. .. ==> 0XF8006144[19:11] = 0x00000000U */
- /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU, 0x00000035U),
- /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
- /* .. .. ==> 0XF8006148[9:0] = 0x00000035U */
- /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */
- /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
- /* .. .. ==> 0XF8006148[10:10] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
- /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
- /* .. .. ==> 0XF8006148[19:11] = 0x00000000U */
- /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU, 0x00000035U),
- /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
- /* .. .. ==> 0XF800614C[9:0] = 0x00000035U */
- /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */
- /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
- /* .. .. ==> 0XF800614C[10:10] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
- /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
- /* .. .. ==> 0XF800614C[19:11] = 0x00000000U */
- /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU, 0x00000035U),
- /* .. .. reg_phy_wr_dqs_slave_ratio = 0x77 */
- /* .. .. ==> 0XF8006154[9:0] = 0x00000077U */
- /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000077U */
- /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
- /* .. .. ==> 0XF8006154[10:10] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
- /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
- /* .. .. ==> 0XF8006154[19:11] = 0x00000000U */
- /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU, 0x00000077U),
- /* .. .. reg_phy_wr_dqs_slave_ratio = 0x7c */
- /* .. .. ==> 0XF8006158[9:0] = 0x0000007CU */
- /* .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU */
- /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
- /* .. .. ==> 0XF8006158[10:10] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
- /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
- /* .. .. ==> 0XF8006158[19:11] = 0x00000000U */
- /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU, 0x0000007CU),
- /* .. .. reg_phy_wr_dqs_slave_ratio = 0x7c */
- /* .. .. ==> 0XF800615C[9:0] = 0x0000007CU */
- /* .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU */
- /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
- /* .. .. ==> 0XF800615C[10:10] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
- /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
- /* .. .. ==> 0XF800615C[19:11] = 0x00000000U */
- /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU, 0x0000007CU),
- /* .. .. reg_phy_wr_dqs_slave_ratio = 0x75 */
- /* .. .. ==> 0XF8006160[9:0] = 0x00000075U */
- /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000075U */
- /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
- /* .. .. ==> 0XF8006160[10:10] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
- /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
- /* .. .. ==> 0XF8006160[19:11] = 0x00000000U */
- /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU, 0x00000075U),
- /* .. .. reg_phy_fifo_we_slave_ratio = 0xe4 */
- /* .. .. ==> 0XF8006168[10:0] = 0x000000E4U */
- /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000E4U */
- /* .. .. reg_phy_fifo_we_in_force = 0x0 */
- /* .. .. ==> 0XF8006168[11:11] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */
- /* .. .. reg_phy_fifo_we_in_delay = 0x0 */
- /* .. .. ==> 0XF8006168[20:12] = 0x00000000U */
- /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU, 0x000000E4U),
- /* .. .. reg_phy_fifo_we_slave_ratio = 0xdf */
- /* .. .. ==> 0XF800616C[10:0] = 0x000000DFU */
- /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000DFU */
- /* .. .. reg_phy_fifo_we_in_force = 0x0 */
- /* .. .. ==> 0XF800616C[11:11] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */
- /* .. .. reg_phy_fifo_we_in_delay = 0x0 */
- /* .. .. ==> 0XF800616C[20:12] = 0x00000000U */
- /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU, 0x000000DFU),
- /* .. .. reg_phy_fifo_we_slave_ratio = 0xe0 */
- /* .. .. ==> 0XF8006170[10:0] = 0x000000E0U */
- /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000E0U */
- /* .. .. reg_phy_fifo_we_in_force = 0x0 */
- /* .. .. ==> 0XF8006170[11:11] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */
- /* .. .. reg_phy_fifo_we_in_delay = 0x0 */
- /* .. .. ==> 0XF8006170[20:12] = 0x00000000U */
- /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU, 0x000000E0U),
- /* .. .. reg_phy_fifo_we_slave_ratio = 0xe7 */
- /* .. .. ==> 0XF8006174[10:0] = 0x000000E7U */
- /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000E7U */
- /* .. .. reg_phy_fifo_we_in_force = 0x0 */
- /* .. .. ==> 0XF8006174[11:11] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */
- /* .. .. reg_phy_fifo_we_in_delay = 0x0 */
- /* .. .. ==> 0XF8006174[20:12] = 0x00000000U */
- /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU, 0x000000E7U),
- /* .. .. reg_phy_wr_data_slave_ratio = 0xb7 */
- /* .. .. ==> 0XF800617C[9:0] = 0x000000B7U */
- /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000B7U */
- /* .. .. reg_phy_wr_data_slave_force = 0x0 */
- /* .. .. ==> 0XF800617C[10:10] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
- /* .. .. reg_phy_wr_data_slave_delay = 0x0 */
- /* .. .. ==> 0XF800617C[19:11] = 0x00000000U */
- /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU, 0x000000B7U),
- /* .. .. reg_phy_wr_data_slave_ratio = 0xbc */
- /* .. .. ==> 0XF8006180[9:0] = 0x000000BCU */
- /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU */
- /* .. .. reg_phy_wr_data_slave_force = 0x0 */
- /* .. .. ==> 0XF8006180[10:10] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
- /* .. .. reg_phy_wr_data_slave_delay = 0x0 */
- /* .. .. ==> 0XF8006180[19:11] = 0x00000000U */
- /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU, 0x000000BCU),
- /* .. .. reg_phy_wr_data_slave_ratio = 0xbc */
- /* .. .. ==> 0XF8006184[9:0] = 0x000000BCU */
- /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU */
- /* .. .. reg_phy_wr_data_slave_force = 0x0 */
- /* .. .. ==> 0XF8006184[10:10] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
- /* .. .. reg_phy_wr_data_slave_delay = 0x0 */
- /* .. .. ==> 0XF8006184[19:11] = 0x00000000U */
- /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU, 0x000000BCU),
- /* .. .. reg_phy_wr_data_slave_ratio = 0xb5 */
- /* .. .. ==> 0XF8006188[9:0] = 0x000000B5U */
- /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000B5U */
- /* .. .. reg_phy_wr_data_slave_force = 0x0 */
- /* .. .. ==> 0XF8006188[10:10] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
- /* .. .. reg_phy_wr_data_slave_delay = 0x0 */
- /* .. .. ==> 0XF8006188[19:11] = 0x00000000U */
- /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU, 0x000000B5U),
- /* .. .. reg_phy_loopback = 0x0 */
- /* .. .. ==> 0XF8006190[0:0] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. .. reg_phy_bl2 = 0x0 */
- /* .. .. ==> 0XF8006190[1:1] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. .. reg_phy_at_spd_atpg = 0x0 */
- /* .. .. ==> 0XF8006190[2:2] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. .. reg_phy_bist_enable = 0x0 */
- /* .. .. ==> 0XF8006190[3:3] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */
- /* .. .. reg_phy_bist_force_err = 0x0 */
- /* .. .. ==> 0XF8006190[4:4] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
- /* .. .. reg_phy_bist_mode = 0x0 */
- /* .. .. ==> 0XF8006190[6:5] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000060U VAL : 0x00000000U */
- /* .. .. reg_phy_invert_clkout = 0x1 */
- /* .. .. ==> 0XF8006190[7:7] = 0x00000001U */
- /* .. .. ==> MASK : 0x00000080U VAL : 0x00000080U */
- /* .. .. reg_phy_all_dq_mpr_rd_resp = 0x0 */
- /* .. .. ==> 0XF8006190[8:8] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000100U VAL : 0x00000000U */
- /* .. .. reg_phy_sel_logic = 0x0 */
- /* .. .. ==> 0XF8006190[9:9] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000200U VAL : 0x00000000U */
- /* .. .. reg_phy_ctrl_slave_ratio = 0x100 */
- /* .. .. ==> 0XF8006190[19:10] = 0x00000100U */
- /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U */
- /* .. .. reg_phy_ctrl_slave_force = 0x0 */
- /* .. .. ==> 0XF8006190[20:20] = 0x00000000U */
- /* .. .. ==> MASK : 0x00100000U VAL : 0x00000000U */
- /* .. .. reg_phy_ctrl_slave_delay = 0x0 */
- /* .. .. ==> 0XF8006190[27:21] = 0x00000000U */
- /* .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U */
- /* .. .. reg_phy_use_rank0_delays = 0x1 */
- /* .. .. ==> 0XF8006190[28:28] = 0x00000001U */
- /* .. .. ==> MASK : 0x10000000U VAL : 0x10000000U */
- /* .. .. reg_phy_lpddr = 0x0 */
- /* .. .. ==> 0XF8006190[29:29] = 0x00000000U */
- /* .. .. ==> MASK : 0x20000000U VAL : 0x00000000U */
- /* .. .. reg_phy_cmd_latency = 0x0 */
- /* .. .. ==> 0XF8006190[30:30] = 0x00000000U */
- /* .. .. ==> MASK : 0x40000000U VAL : 0x00000000U */
- /* .. .. reg_phy_int_lpbk = 0x0 */
- /* .. .. ==> 0XF8006190[31:31] = 0x00000000U */
- /* .. .. ==> MASK : 0x80000000U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU, 0x10040080U),
- /* .. .. reg_phy_wr_rl_delay = 0x2 */
- /* .. .. ==> 0XF8006194[4:0] = 0x00000002U */
- /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U */
- /* .. .. reg_phy_rd_rl_delay = 0x4 */
- /* .. .. ==> 0XF8006194[9:5] = 0x00000004U */
- /* .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U */
- /* .. .. reg_phy_dll_lock_diff = 0xf */
- /* .. .. ==> 0XF8006194[13:10] = 0x0000000FU */
- /* .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U */
- /* .. .. reg_phy_use_wr_level = 0x1 */
- /* .. .. ==> 0XF8006194[14:14] = 0x00000001U */
- /* .. .. ==> MASK : 0x00004000U VAL : 0x00004000U */
- /* .. .. reg_phy_use_rd_dqs_gate_level = 0x1 */
- /* .. .. ==> 0XF8006194[15:15] = 0x00000001U */
- /* .. .. ==> MASK : 0x00008000U VAL : 0x00008000U */
- /* .. .. reg_phy_use_rd_data_eye_level = 0x1 */
- /* .. .. ==> 0XF8006194[16:16] = 0x00000001U */
- /* .. .. ==> MASK : 0x00010000U VAL : 0x00010000U */
- /* .. .. reg_phy_dis_calib_rst = 0x0 */
- /* .. .. ==> 0XF8006194[17:17] = 0x00000000U */
- /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
- /* .. .. reg_phy_ctrl_slave_delay = 0x0 */
- /* .. .. ==> 0XF8006194[19:18] = 0x00000000U */
- /* .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU, 0x0001FC82U),
- /* .. .. reg_arb_page_addr_mask = 0x0 */
- /* .. .. ==> 0XF8006204[31:0] = 0x00000000U */
- /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU, 0x00000000U),
- /* .. .. reg_arb_pri_wr_portn = 0x3ff */
- /* .. .. ==> 0XF8006208[9:0] = 0x000003FFU */
- /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
- /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
- /* .. .. ==> 0XF8006208[16:16] = 0x00000000U */
- /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
- /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
- /* .. .. ==> 0XF8006208[17:17] = 0x00000000U */
- /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
- /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
- /* .. .. ==> 0XF8006208[18:18] = 0x00000000U */
- /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
- /* .. .. reg_arb_dis_rmw_portn = 0x1 */
- /* .. .. ==> 0XF8006208[19:19] = 0x00000001U */
- /* .. .. ==> MASK : 0x00080000U VAL : 0x00080000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006208, 0x000F03FFU, 0x000803FFU),
- /* .. .. reg_arb_pri_wr_portn = 0x3ff */
- /* .. .. ==> 0XF800620C[9:0] = 0x000003FFU */
- /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
- /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
- /* .. .. ==> 0XF800620C[16:16] = 0x00000000U */
- /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
- /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
- /* .. .. ==> 0XF800620C[17:17] = 0x00000000U */
- /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
- /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
- /* .. .. ==> 0XF800620C[18:18] = 0x00000000U */
- /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
- /* .. .. reg_arb_dis_rmw_portn = 0x1 */
- /* .. .. ==> 0XF800620C[19:19] = 0x00000001U */
- /* .. .. ==> MASK : 0x00080000U VAL : 0x00080000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF800620C, 0x000F03FFU, 0x000803FFU),
- /* .. .. reg_arb_pri_wr_portn = 0x3ff */
- /* .. .. ==> 0XF8006210[9:0] = 0x000003FFU */
- /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
- /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
- /* .. .. ==> 0XF8006210[16:16] = 0x00000000U */
- /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
- /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
- /* .. .. ==> 0XF8006210[17:17] = 0x00000000U */
- /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
- /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
- /* .. .. ==> 0XF8006210[18:18] = 0x00000000U */
- /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
- /* .. .. reg_arb_dis_rmw_portn = 0x1 */
- /* .. .. ==> 0XF8006210[19:19] = 0x00000001U */
- /* .. .. ==> MASK : 0x00080000U VAL : 0x00080000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006210, 0x000F03FFU, 0x000803FFU),
- /* .. .. reg_arb_pri_wr_portn = 0x3ff */
- /* .. .. ==> 0XF8006214[9:0] = 0x000003FFU */
- /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
- /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
- /* .. .. ==> 0XF8006214[16:16] = 0x00000000U */
- /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
- /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
- /* .. .. ==> 0XF8006214[17:17] = 0x00000000U */
- /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
- /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
- /* .. .. ==> 0XF8006214[18:18] = 0x00000000U */
- /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
- /* .. .. reg_arb_dis_rmw_portn = 0x1 */
- /* .. .. ==> 0XF8006214[19:19] = 0x00000001U */
- /* .. .. ==> MASK : 0x00080000U VAL : 0x00080000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006214, 0x000F03FFU, 0x000803FFU),
- /* .. .. reg_arb_pri_rd_portn = 0x3ff */
- /* .. .. ==> 0XF8006218[9:0] = 0x000003FFU */
- /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
- /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
- /* .. .. ==> 0XF8006218[16:16] = 0x00000000U */
- /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
- /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
- /* .. .. ==> 0XF8006218[17:17] = 0x00000000U */
- /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
- /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
- /* .. .. ==> 0XF8006218[18:18] = 0x00000000U */
- /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
- /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
- /* .. .. ==> 0XF8006218[19:19] = 0x00000000U */
- /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006218, 0x000F03FFU, 0x000003FFU),
- /* .. .. reg_arb_pri_rd_portn = 0x3ff */
- /* .. .. ==> 0XF800621C[9:0] = 0x000003FFU */
- /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
- /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
- /* .. .. ==> 0XF800621C[16:16] = 0x00000000U */
- /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
- /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
- /* .. .. ==> 0XF800621C[17:17] = 0x00000000U */
- /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
- /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
- /* .. .. ==> 0XF800621C[18:18] = 0x00000000U */
- /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
- /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
- /* .. .. ==> 0XF800621C[19:19] = 0x00000000U */
- /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF800621C, 0x000F03FFU, 0x000003FFU),
- /* .. .. reg_arb_pri_rd_portn = 0x3ff */
- /* .. .. ==> 0XF8006220[9:0] = 0x000003FFU */
- /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
- /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
- /* .. .. ==> 0XF8006220[16:16] = 0x00000000U */
- /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
- /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
- /* .. .. ==> 0XF8006220[17:17] = 0x00000000U */
- /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
- /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
- /* .. .. ==> 0XF8006220[18:18] = 0x00000000U */
- /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
- /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
- /* .. .. ==> 0XF8006220[19:19] = 0x00000000U */
- /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006220, 0x000F03FFU, 0x000003FFU),
- /* .. .. reg_arb_pri_rd_portn = 0x3ff */
- /* .. .. ==> 0XF8006224[9:0] = 0x000003FFU */
- /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
- /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
- /* .. .. ==> 0XF8006224[16:16] = 0x00000000U */
- /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
- /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
- /* .. .. ==> 0XF8006224[17:17] = 0x00000000U */
- /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
- /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
- /* .. .. ==> 0XF8006224[18:18] = 0x00000000U */
- /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
- /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
- /* .. .. ==> 0XF8006224[19:19] = 0x00000000U */
- /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006224, 0x000F03FFU, 0x000003FFU),
- /* .. .. reg_ddrc_lpddr2 = 0x0 */
- /* .. .. ==> 0XF80062A8[0:0] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. .. reg_ddrc_per_bank_refresh = 0x0 */
- /* .. .. ==> 0XF80062A8[1:1] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. .. reg_ddrc_derate_enable = 0x0 */
- /* .. .. ==> 0XF80062A8[2:2] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. .. reg_ddrc_mr4_margin = 0x0 */
- /* .. .. ==> 0XF80062A8[11:4] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U, 0x00000000U),
- /* .. .. reg_ddrc_mr4_read_interval = 0x0 */
- /* .. .. ==> 0XF80062AC[31:0] = 0x00000000U */
- /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU, 0x00000000U),
- /* .. .. reg_ddrc_min_stable_clock_x1 = 0x5 */
- /* .. .. ==> 0XF80062B0[3:0] = 0x00000005U */
- /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U */
- /* .. .. reg_ddrc_idle_after_reset_x32 = 0x12 */
- /* .. .. ==> 0XF80062B0[11:4] = 0x00000012U */
- /* .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U */
- /* .. .. reg_ddrc_t_mrw = 0x5 */
- /* .. .. ==> 0XF80062B0[21:12] = 0x00000005U */
- /* .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU, 0x00005125U),
- /* .. .. reg_ddrc_max_auto_init_x1024 = 0xa6 */
- /* .. .. ==> 0XF80062B4[7:0] = 0x000000A6U */
- /* .. .. ==> MASK : 0x000000FFU VAL : 0x000000A6U */
- /* .. .. reg_ddrc_dev_zqinit_x32 = 0x12 */
- /* .. .. ==> 0XF80062B4[17:8] = 0x00000012U */
- /* .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U */
- /* .. .. */
- EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU, 0x000012A6U),
- /* .. .. START: POLL ON DCI STATUS */
- /* .. .. DONE = 1 */
- /* .. .. ==> 0XF8000B74[13:13] = 0x00000001U */
- /* .. .. ==> MASK : 0x00002000U VAL : 0x00002000U */
- /* .. .. */
- EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
- /* .. .. FINISH: POLL ON DCI STATUS */
- /* .. .. START: UNLOCK DDR */
- /* .. .. reg_ddrc_soft_rstb = 0x1 */
- /* .. .. ==> 0XF8006000[0:0] = 0x00000001U */
- /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
- /* .. .. reg_ddrc_powerdown_en = 0x0 */
- /* .. .. ==> 0XF8006000[1:1] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. .. reg_ddrc_data_bus_width = 0x0 */
- /* .. .. ==> 0XF8006000[3:2] = 0x00000000U */
- /* .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U */
- /* .. .. reg_ddrc_burst8_refresh = 0x0 */
- /* .. .. ==> 0XF8006000[6:4] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000070U VAL : 0x00000000U */
- /* .. .. reg_ddrc_rdwr_idle_gap = 1 */
- /* .. .. ==> 0XF8006000[13:7] = 0x00000001U */
- /* .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U */
- /* .. .. reg_ddrc_dis_rd_bypass = 0x0 */
- /* .. .. ==> 0XF8006000[14:14] = 0x00000000U */
- /* .. .. ==> MASK : 0x00004000U VAL : 0x00000000U */
- /* .. .. reg_ddrc_dis_act_bypass = 0x0 */
- /* .. .. ==> 0XF8006000[15:15] = 0x00000000U */
- /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */
- /* .. .. reg_ddrc_dis_auto_refresh = 0x0 */
- /* .. .. ==> 0XF8006000[16:16] = 0x00000000U */
- /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000081U),
- /* .. .. FINISH: UNLOCK DDR */
- /* .. .. START: CHECK DDR STATUS */
- /* .. .. ddrc_reg_operating_mode = 1 */
- /* .. .. ==> 0XF8006054[2:0] = 0x00000001U */
- /* .. .. ==> MASK : 0x00000007U VAL : 0x00000001U */
- /* .. .. */
- EMIT_MASKPOLL(0XF8006054, 0x00000007U),
- /* .. .. FINISH: CHECK DDR STATUS */
- /* .. FINISH: DDR INITIALIZATION */
- /* FINISH: top */
- /* */
- EMIT_EXIT(),
-
- /* */
-};
-
-unsigned long ps7_mio_init_data_1_0[] = {
- /* START: top */
- /* .. START: SLCR SETTINGS */
- /* .. UNLOCK_KEY = 0XDF0D */
- /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
- /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */
- /* .. */
- EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
- /* .. FINISH: SLCR SETTINGS */
- /* .. START: OCM REMAPPING */
- /* .. VREF_EN = 0x1 */
- /* .. ==> 0XF8000B00[0:0] = 0x00000001U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
- /* .. VREF_PULLUP_EN = 0x0 */
- /* .. ==> 0XF8000B00[1:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. CLK_PULLUP_EN = 0x0 */
- /* .. ==> 0XF8000B00[8:8] = 0x00000000U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
- /* .. SRSTN_PULLUP_EN = 0x0 */
- /* .. ==> 0XF8000B00[9:9] = 0x00000000U */
- /* .. ==> MASK : 0x00000200U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000B00, 0x00000303U, 0x00000001U),
- /* .. FINISH: OCM REMAPPING */
- /* .. START: DDRIOB SETTINGS */
- /* .. INP_POWER = 0x0 */
- /* .. ==> 0XF8000B40[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. INP_TYPE = 0x0 */
- /* .. ==> 0XF8000B40[2:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */
- /* .. DCI_UPDATE = 0x0 */
- /* .. ==> 0XF8000B40[3:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
- /* .. TERM_EN = 0x0 */
- /* .. ==> 0XF8000B40[4:4] = 0x00000000U */
- /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */
- /* .. DCR_TYPE = 0x0 */
- /* .. ==> 0XF8000B40[6:5] = 0x00000000U */
- /* .. ==> MASK : 0x00000060U VAL : 0x00000000U */
- /* .. IBUF_DISABLE_MODE = 0x0 */
- /* .. ==> 0XF8000B40[7:7] = 0x00000000U */
- /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
- /* .. TERM_DISABLE_MODE = 0x0 */
- /* .. ==> 0XF8000B40[8:8] = 0x00000000U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
- /* .. OUTPUT_EN = 0x3 */
- /* .. ==> 0XF8000B40[10:9] = 0x00000003U */
- /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
- /* .. PULLUP_EN = 0x0 */
- /* .. ==> 0XF8000B40[11:11] = 0x00000000U */
- /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU, 0x00000600U),
- /* .. INP_POWER = 0x0 */
- /* .. ==> 0XF8000B44[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. INP_TYPE = 0x0 */
- /* .. ==> 0XF8000B44[2:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */
- /* .. DCI_UPDATE = 0x0 */
- /* .. ==> 0XF8000B44[3:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
- /* .. TERM_EN = 0x0 */
- /* .. ==> 0XF8000B44[4:4] = 0x00000000U */
- /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */
- /* .. DCR_TYPE = 0x0 */
- /* .. ==> 0XF8000B44[6:5] = 0x00000000U */
- /* .. ==> MASK : 0x00000060U VAL : 0x00000000U */
- /* .. IBUF_DISABLE_MODE = 0x0 */
- /* .. ==> 0XF8000B44[7:7] = 0x00000000U */
- /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
- /* .. TERM_DISABLE_MODE = 0x0 */
- /* .. ==> 0XF8000B44[8:8] = 0x00000000U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
- /* .. OUTPUT_EN = 0x3 */
- /* .. ==> 0XF8000B44[10:9] = 0x00000003U */
- /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
- /* .. PULLUP_EN = 0x0 */
- /* .. ==> 0XF8000B44[11:11] = 0x00000000U */
- /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU, 0x00000600U),
- /* .. INP_POWER = 0x0 */
- /* .. ==> 0XF8000B48[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. INP_TYPE = 0x1 */
- /* .. ==> 0XF8000B48[2:1] = 0x00000001U */
- /* .. ==> MASK : 0x00000006U VAL : 0x00000002U */
- /* .. DCI_UPDATE = 0x0 */
- /* .. ==> 0XF8000B48[3:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
- /* .. TERM_EN = 0x1 */
- /* .. ==> 0XF8000B48[4:4] = 0x00000001U */
- /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */
- /* .. DCR_TYPE = 0x3 */
- /* .. ==> 0XF8000B48[6:5] = 0x00000003U */
- /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */
- /* .. IBUF_DISABLE_MODE = 0 */
- /* .. ==> 0XF8000B48[7:7] = 0x00000000U */
- /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
- /* .. TERM_DISABLE_MODE = 0 */
- /* .. ==> 0XF8000B48[8:8] = 0x00000000U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
- /* .. OUTPUT_EN = 0x3 */
- /* .. ==> 0XF8000B48[10:9] = 0x00000003U */
- /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
- /* .. PULLUP_EN = 0x0 */
- /* .. ==> 0XF8000B48[11:11] = 0x00000000U */
- /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU, 0x00000672U),
- /* .. INP_POWER = 0x0 */
- /* .. ==> 0XF8000B4C[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. INP_TYPE = 0x1 */
- /* .. ==> 0XF8000B4C[2:1] = 0x00000001U */
- /* .. ==> MASK : 0x00000006U VAL : 0x00000002U */
- /* .. DCI_UPDATE = 0x0 */
- /* .. ==> 0XF8000B4C[3:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
- /* .. TERM_EN = 0x1 */
- /* .. ==> 0XF8000B4C[4:4] = 0x00000001U */
- /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */
- /* .. DCR_TYPE = 0x3 */
- /* .. ==> 0XF8000B4C[6:5] = 0x00000003U */
- /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */
- /* .. IBUF_DISABLE_MODE = 0 */
- /* .. ==> 0XF8000B4C[7:7] = 0x00000000U */
- /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
- /* .. TERM_DISABLE_MODE = 0 */
- /* .. ==> 0XF8000B4C[8:8] = 0x00000000U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
- /* .. OUTPUT_EN = 0x3 */
- /* .. ==> 0XF8000B4C[10:9] = 0x00000003U */
- /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
- /* .. PULLUP_EN = 0x0 */
- /* .. ==> 0XF8000B4C[11:11] = 0x00000000U */
- /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU, 0x00000672U),
- /* .. INP_POWER = 0x0 */
- /* .. ==> 0XF8000B50[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. INP_TYPE = 0x2 */
- /* .. ==> 0XF8000B50[2:1] = 0x00000002U */
- /* .. ==> MASK : 0x00000006U VAL : 0x00000004U */
- /* .. DCI_UPDATE = 0x0 */
- /* .. ==> 0XF8000B50[3:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
- /* .. TERM_EN = 0x1 */
- /* .. ==> 0XF8000B50[4:4] = 0x00000001U */
- /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */
- /* .. DCR_TYPE = 0x3 */
- /* .. ==> 0XF8000B50[6:5] = 0x00000003U */
- /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */
- /* .. IBUF_DISABLE_MODE = 0 */
- /* .. ==> 0XF8000B50[7:7] = 0x00000000U */
- /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
- /* .. TERM_DISABLE_MODE = 0 */
- /* .. ==> 0XF8000B50[8:8] = 0x00000000U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
- /* .. OUTPUT_EN = 0x3 */
- /* .. ==> 0XF8000B50[10:9] = 0x00000003U */
- /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
- /* .. PULLUP_EN = 0x0 */
- /* .. ==> 0XF8000B50[11:11] = 0x00000000U */
- /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU, 0x00000674U),
- /* .. INP_POWER = 0x0 */
- /* .. ==> 0XF8000B54[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. INP_TYPE = 0x2 */
- /* .. ==> 0XF8000B54[2:1] = 0x00000002U */
- /* .. ==> MASK : 0x00000006U VAL : 0x00000004U */
- /* .. DCI_UPDATE = 0x0 */
- /* .. ==> 0XF8000B54[3:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
- /* .. TERM_EN = 0x1 */
- /* .. ==> 0XF8000B54[4:4] = 0x00000001U */
- /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */
- /* .. DCR_TYPE = 0x3 */
- /* .. ==> 0XF8000B54[6:5] = 0x00000003U */
- /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */
- /* .. IBUF_DISABLE_MODE = 0 */
- /* .. ==> 0XF8000B54[7:7] = 0x00000000U */
- /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
- /* .. TERM_DISABLE_MODE = 0 */
- /* .. ==> 0XF8000B54[8:8] = 0x00000000U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
- /* .. OUTPUT_EN = 0x3 */
- /* .. ==> 0XF8000B54[10:9] = 0x00000003U */
- /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
- /* .. PULLUP_EN = 0x0 */
- /* .. ==> 0XF8000B54[11:11] = 0x00000000U */
- /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU, 0x00000674U),
- /* .. INP_POWER = 0x0 */
- /* .. ==> 0XF8000B58[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. INP_TYPE = 0x0 */
- /* .. ==> 0XF8000B58[2:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */
- /* .. DCI_UPDATE = 0x0 */
- /* .. ==> 0XF8000B58[3:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
- /* .. TERM_EN = 0x0 */
- /* .. ==> 0XF8000B58[4:4] = 0x00000000U */
- /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */
- /* .. DCR_TYPE = 0x0 */
- /* .. ==> 0XF8000B58[6:5] = 0x00000000U */
- /* .. ==> MASK : 0x00000060U VAL : 0x00000000U */
- /* .. IBUF_DISABLE_MODE = 0x0 */
- /* .. ==> 0XF8000B58[7:7] = 0x00000000U */
- /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
- /* .. TERM_DISABLE_MODE = 0x0 */
- /* .. ==> 0XF8000B58[8:8] = 0x00000000U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
- /* .. OUTPUT_EN = 0x3 */
- /* .. ==> 0XF8000B58[10:9] = 0x00000003U */
- /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
- /* .. PULLUP_EN = 0x0 */
- /* .. ==> 0XF8000B58[11:11] = 0x00000000U */
- /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU, 0x00000600U),
- /* .. DRIVE_P = 0x1c */
- /* .. ==> 0XF8000B5C[6:0] = 0x0000001CU */
- /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */
- /* .. DRIVE_N = 0xc */
- /* .. ==> 0XF8000B5C[13:7] = 0x0000000CU */
- /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */
- /* .. SLEW_P = 0x3 */
- /* .. ==> 0XF8000B5C[18:14] = 0x00000003U */
- /* .. ==> MASK : 0x0007C000U VAL : 0x0000C000U */
- /* .. SLEW_N = 0x3 */
- /* .. ==> 0XF8000B5C[23:19] = 0x00000003U */
- /* .. ==> MASK : 0x00F80000U VAL : 0x00180000U */
- /* .. GTL = 0x0 */
- /* .. ==> 0XF8000B5C[26:24] = 0x00000000U */
- /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */
- /* .. RTERM = 0x0 */
- /* .. ==> 0XF8000B5C[31:27] = 0x00000000U */
- /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU, 0x0018C61CU),
- /* .. DRIVE_P = 0x1c */
- /* .. ==> 0XF8000B60[6:0] = 0x0000001CU */
- /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */
- /* .. DRIVE_N = 0xc */
- /* .. ==> 0XF8000B60[13:7] = 0x0000000CU */
- /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */
- /* .. SLEW_P = 0x6 */
- /* .. ==> 0XF8000B60[18:14] = 0x00000006U */
- /* .. ==> MASK : 0x0007C000U VAL : 0x00018000U */
- /* .. SLEW_N = 0x1f */
- /* .. ==> 0XF8000B60[23:19] = 0x0000001FU */
- /* .. ==> MASK : 0x00F80000U VAL : 0x00F80000U */
- /* .. GTL = 0x0 */
- /* .. ==> 0XF8000B60[26:24] = 0x00000000U */
- /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */
- /* .. RTERM = 0x0 */
- /* .. ==> 0XF8000B60[31:27] = 0x00000000U */
- /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU, 0x00F9861CU),
- /* .. DRIVE_P = 0x1c */
- /* .. ==> 0XF8000B64[6:0] = 0x0000001CU */
- /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */
- /* .. DRIVE_N = 0xc */
- /* .. ==> 0XF8000B64[13:7] = 0x0000000CU */
- /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */
- /* .. SLEW_P = 0x6 */
- /* .. ==> 0XF8000B64[18:14] = 0x00000006U */
- /* .. ==> MASK : 0x0007C000U VAL : 0x00018000U */
- /* .. SLEW_N = 0x1f */
- /* .. ==> 0XF8000B64[23:19] = 0x0000001FU */
- /* .. ==> MASK : 0x00F80000U VAL : 0x00F80000U */
- /* .. GTL = 0x0 */
- /* .. ==> 0XF8000B64[26:24] = 0x00000000U */
- /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */
- /* .. RTERM = 0x0 */
- /* .. ==> 0XF8000B64[31:27] = 0x00000000U */
- /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU, 0x00F9861CU),
- /* .. DRIVE_P = 0x1c */
- /* .. ==> 0XF8000B68[6:0] = 0x0000001CU */
- /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */
- /* .. DRIVE_N = 0xc */
- /* .. ==> 0XF8000B68[13:7] = 0x0000000CU */
- /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */
- /* .. SLEW_P = 0x6 */
- /* .. ==> 0XF8000B68[18:14] = 0x00000006U */
- /* .. ==> MASK : 0x0007C000U VAL : 0x00018000U */
- /* .. SLEW_N = 0x1f */
- /* .. ==> 0XF8000B68[23:19] = 0x0000001FU */
- /* .. ==> MASK : 0x00F80000U VAL : 0x00F80000U */
- /* .. GTL = 0x0 */
- /* .. ==> 0XF8000B68[26:24] = 0x00000000U */
- /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */
- /* .. RTERM = 0x0 */
- /* .. ==> 0XF8000B68[31:27] = 0x00000000U */
- /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU, 0x00F9861CU),
- /* .. VREF_INT_EN = 0x0 */
- /* .. ==> 0XF8000B6C[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. VREF_SEL = 0x0 */
- /* .. ==> 0XF8000B6C[4:1] = 0x00000000U */
- /* .. ==> MASK : 0x0000001EU VAL : 0x00000000U */
- /* .. VREF_EXT_EN = 0x3 */
- /* .. ==> 0XF8000B6C[6:5] = 0x00000003U */
- /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */
- /* .. VREF_PULLUP_EN = 0x0 */
- /* .. ==> 0XF8000B6C[8:7] = 0x00000000U */
- /* .. ==> MASK : 0x00000180U VAL : 0x00000000U */
- /* .. REFIO_EN = 0x1 */
- /* .. ==> 0XF8000B6C[9:9] = 0x00000001U */
- /* .. ==> MASK : 0x00000200U VAL : 0x00000200U */
- /* .. REFIO_PULLUP_EN = 0x0 */
- /* .. ==> 0XF8000B6C[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DRST_B_PULLUP_EN = 0x0 */
- /* .. ==> 0XF8000B6C[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. CKE_PULLUP_EN = 0x0 */
- /* .. ==> 0XF8000B6C[14:14] = 0x00000000U */
- /* .. ==> MASK : 0x00004000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000B6C, 0x000073FFU, 0x00000260U),
- /* .. .. START: ASSERT RESET */
- /* .. .. RESET = 1 */
- /* .. .. ==> 0XF8000B70[0:0] = 0x00000001U */
- /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
- /* .. .. VRN_OUT = 0x1 */
- /* .. .. ==> 0XF8000B70[5:5] = 0x00000001U */
- /* .. .. ==> MASK : 0x00000020U VAL : 0x00000020U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000021U),
- /* .. .. FINISH: ASSERT RESET */
- /* .. .. START: DEASSERT RESET */
- /* .. .. RESET = 0 */
- /* .. .. ==> 0XF8000B70[0:0] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. .. VRN_OUT = 0x1 */
- /* .. .. ==> 0XF8000B70[5:5] = 0x00000001U */
- /* .. .. ==> MASK : 0x00000020U VAL : 0x00000020U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000020U),
- /* .. .. FINISH: DEASSERT RESET */
- /* .. .. RESET = 0x1 */
- /* .. .. ==> 0XF8000B70[0:0] = 0x00000001U */
- /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
- /* .. .. ENABLE = 0x1 */
- /* .. .. ==> 0XF8000B70[1:1] = 0x00000001U */
- /* .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */
- /* .. .. VRP_TRI = 0x0 */
- /* .. .. ==> 0XF8000B70[2:2] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. .. VRN_TRI = 0x0 */
- /* .. .. ==> 0XF8000B70[3:3] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */
- /* .. .. VRP_OUT = 0x0 */
- /* .. .. ==> 0XF8000B70[4:4] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
- /* .. .. VRN_OUT = 0x1 */
- /* .. .. ==> 0XF8000B70[5:5] = 0x00000001U */
- /* .. .. ==> MASK : 0x00000020U VAL : 0x00000020U */
- /* .. .. NREF_OPT1 = 0x0 */
- /* .. .. ==> 0XF8000B70[7:6] = 0x00000000U */
- /* .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U */
- /* .. .. NREF_OPT2 = 0x0 */
- /* .. .. ==> 0XF8000B70[10:8] = 0x00000000U */
- /* .. .. ==> MASK : 0x00000700U VAL : 0x00000000U */
- /* .. .. NREF_OPT4 = 0x1 */
- /* .. .. ==> 0XF8000B70[13:11] = 0x00000001U */
- /* .. .. ==> MASK : 0x00003800U VAL : 0x00000800U */
- /* .. .. PREF_OPT1 = 0x0 */
- /* .. .. ==> 0XF8000B70[16:14] = 0x00000000U */
- /* .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U */
- /* .. .. PREF_OPT2 = 0x0 */
- /* .. .. ==> 0XF8000B70[19:17] = 0x00000000U */
- /* .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U */
- /* .. .. UPDATE_CONTROL = 0x0 */
- /* .. .. ==> 0XF8000B70[20:20] = 0x00000000U */
- /* .. .. ==> MASK : 0x00100000U VAL : 0x00000000U */
- /* .. .. INIT_COMPLETE = 0x0 */
- /* .. .. ==> 0XF8000B70[21:21] = 0x00000000U */
- /* .. .. ==> MASK : 0x00200000U VAL : 0x00000000U */
- /* .. .. TST_CLK = 0x0 */
- /* .. .. ==> 0XF8000B70[22:22] = 0x00000000U */
- /* .. .. ==> MASK : 0x00400000U VAL : 0x00000000U */
- /* .. .. TST_HLN = 0x0 */
- /* .. .. ==> 0XF8000B70[23:23] = 0x00000000U */
- /* .. .. ==> MASK : 0x00800000U VAL : 0x00000000U */
- /* .. .. TST_HLP = 0x0 */
- /* .. .. ==> 0XF8000B70[24:24] = 0x00000000U */
- /* .. .. ==> MASK : 0x01000000U VAL : 0x00000000U */
- /* .. .. TST_RST = 0x0 */
- /* .. .. ==> 0XF8000B70[25:25] = 0x00000000U */
- /* .. .. ==> MASK : 0x02000000U VAL : 0x00000000U */
- /* .. .. INT_DCI_EN = 0x0 */
- /* .. .. ==> 0XF8000B70[26:26] = 0x00000000U */
- /* .. .. ==> MASK : 0x04000000U VAL : 0x00000000U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU, 0x00000823U),
- /* .. FINISH: DDRIOB SETTINGS */
- /* .. START: MIO PROGRAMMING */
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF8000700[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 0 */
- /* .. ==> 0XF8000700[1:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF8000700[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF8000700[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF8000700[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 0 */
- /* .. ==> 0XF8000700[8:8] = 0x00000000U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
- /* .. IO_Type = 3 */
- /* .. ==> 0XF8000700[11:9] = 0x00000003U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
- /* .. PULLUP = 1 */
- /* .. ==> 0XF8000700[12:12] = 0x00000001U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF8000700[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000700, 0x00003FFFU, 0x00001600U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF8000704[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 1 */
- /* .. ==> 0XF8000704[1:1] = 0x00000001U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF8000704[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF8000704[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF8000704[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 1 */
- /* .. ==> 0XF8000704[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. IO_Type = 3 */
- /* .. ==> 0XF8000704[11:9] = 0x00000003U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF8000704[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF8000704[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000704, 0x00003FFFU, 0x00000702U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF8000708[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 1 */
- /* .. ==> 0XF8000708[1:1] = 0x00000001U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF8000708[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF8000708[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF8000708[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 1 */
- /* .. ==> 0XF8000708[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. IO_Type = 3 */
- /* .. ==> 0XF8000708[11:9] = 0x00000003U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF8000708[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF8000708[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000708, 0x00003FFFU, 0x00000702U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF800070C[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 1 */
- /* .. ==> 0XF800070C[1:1] = 0x00000001U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF800070C[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF800070C[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF800070C[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 1 */
- /* .. ==> 0XF800070C[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. IO_Type = 3 */
- /* .. ==> 0XF800070C[11:9] = 0x00000003U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF800070C[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF800070C[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF800070C, 0x00003FFFU, 0x00000702U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF8000710[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 1 */
- /* .. ==> 0XF8000710[1:1] = 0x00000001U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF8000710[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF8000710[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF8000710[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 1 */
- /* .. ==> 0XF8000710[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. IO_Type = 3 */
- /* .. ==> 0XF8000710[11:9] = 0x00000003U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF8000710[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF8000710[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000710, 0x00003FFFU, 0x00000702U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF8000714[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 1 */
- /* .. ==> 0XF8000714[1:1] = 0x00000001U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF8000714[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF8000714[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF8000714[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 1 */
- /* .. ==> 0XF8000714[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. IO_Type = 3 */
- /* .. ==> 0XF8000714[11:9] = 0x00000003U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF8000714[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF8000714[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000714, 0x00003FFFU, 0x00000702U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF8000718[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 1 */
- /* .. ==> 0XF8000718[1:1] = 0x00000001U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF8000718[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF8000718[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF8000718[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 1 */
- /* .. ==> 0XF8000718[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. IO_Type = 3 */
- /* .. ==> 0XF8000718[11:9] = 0x00000003U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF8000718[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF8000718[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000702U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF800071C[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 0 */
- /* .. ==> 0XF800071C[1:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF800071C[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF800071C[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF800071C[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 0 */
- /* .. ==> 0XF800071C[8:8] = 0x00000000U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
- /* .. IO_Type = 3 */
- /* .. ==> 0XF800071C[11:9] = 0x00000003U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF800071C[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF800071C[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF800071C, 0x00003FFFU, 0x00000600U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF8000720[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 1 */
- /* .. ==> 0XF8000720[1:1] = 0x00000001U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF8000720[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF8000720[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF8000720[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 1 */
- /* .. ==> 0XF8000720[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. IO_Type = 3 */
- /* .. ==> 0XF8000720[11:9] = 0x00000003U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF8000720[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF8000720[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000720, 0x00003FFFU, 0x00000702U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF8000724[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 0 */
- /* .. ==> 0XF8000724[1:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF8000724[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF8000724[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF8000724[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 0 */
- /* .. ==> 0XF8000724[8:8] = 0x00000000U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
- /* .. IO_Type = 3 */
- /* .. ==> 0XF8000724[11:9] = 0x00000003U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
- /* .. PULLUP = 1 */
- /* .. ==> 0XF8000724[12:12] = 0x00000001U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF8000724[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000724, 0x00003FFFU, 0x00001600U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF8000728[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 0 */
- /* .. ==> 0XF8000728[1:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF8000728[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF8000728[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF8000728[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 0 */
- /* .. ==> 0XF8000728[8:8] = 0x00000000U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
- /* .. IO_Type = 3 */
- /* .. ==> 0XF8000728[11:9] = 0x00000003U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
- /* .. PULLUP = 1 */
- /* .. ==> 0XF8000728[12:12] = 0x00000001U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF8000728[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000728, 0x00003FFFU, 0x00001600U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF800072C[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 0 */
- /* .. ==> 0XF800072C[1:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF800072C[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF800072C[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF800072C[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 0 */
- /* .. ==> 0XF800072C[8:8] = 0x00000000U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
- /* .. IO_Type = 3 */
- /* .. ==> 0XF800072C[11:9] = 0x00000003U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
- /* .. PULLUP = 1 */
- /* .. ==> 0XF800072C[12:12] = 0x00000001U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF800072C[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF800072C, 0x00003FFFU, 0x00001600U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF8000730[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 0 */
- /* .. ==> 0XF8000730[1:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF8000730[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF8000730[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF8000730[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 0 */
- /* .. ==> 0XF8000730[8:8] = 0x00000000U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
- /* .. IO_Type = 3 */
- /* .. ==> 0XF8000730[11:9] = 0x00000003U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
- /* .. PULLUP = 1 */
- /* .. ==> 0XF8000730[12:12] = 0x00000001U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF8000730[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000730, 0x00003FFFU, 0x00001600U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF8000734[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 0 */
- /* .. ==> 0XF8000734[1:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF8000734[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF8000734[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF8000734[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 0 */
- /* .. ==> 0XF8000734[8:8] = 0x00000000U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
- /* .. IO_Type = 3 */
- /* .. ==> 0XF8000734[11:9] = 0x00000003U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
- /* .. PULLUP = 1 */
- /* .. ==> 0XF8000734[12:12] = 0x00000001U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF8000734[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000734, 0x00003FFFU, 0x00001600U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF8000738[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 0 */
- /* .. ==> 0XF8000738[1:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF8000738[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF8000738[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF8000738[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 0 */
- /* .. ==> 0XF8000738[8:8] = 0x00000000U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
- /* .. IO_Type = 3 */
- /* .. ==> 0XF8000738[11:9] = 0x00000003U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
- /* .. PULLUP = 1 */
- /* .. ==> 0XF8000738[12:12] = 0x00000001U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF8000738[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000738, 0x00003FFFU, 0x00001600U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF800073C[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 0 */
- /* .. ==> 0XF800073C[1:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF800073C[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF800073C[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF800073C[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 0 */
- /* .. ==> 0XF800073C[8:8] = 0x00000000U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
- /* .. IO_Type = 3 */
- /* .. ==> 0XF800073C[11:9] = 0x00000003U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
- /* .. PULLUP = 1 */
- /* .. ==> 0XF800073C[12:12] = 0x00000001U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF800073C[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF800073C, 0x00003FFFU, 0x00001600U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF8000740[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 1 */
- /* .. ==> 0XF8000740[1:1] = 0x00000001U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF8000740[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF8000740[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF8000740[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 1 */
- /* .. ==> 0XF8000740[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. IO_Type = 4 */
- /* .. ==> 0XF8000740[11:9] = 0x00000004U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF8000740[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 1 */
- /* .. ==> 0XF8000740[13:13] = 0x00000001U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000740, 0x00003FFFU, 0x00002902U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF8000744[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 1 */
- /* .. ==> 0XF8000744[1:1] = 0x00000001U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF8000744[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF8000744[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF8000744[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 1 */
- /* .. ==> 0XF8000744[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. IO_Type = 4 */
- /* .. ==> 0XF8000744[11:9] = 0x00000004U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF8000744[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 1 */
- /* .. ==> 0XF8000744[13:13] = 0x00000001U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000744, 0x00003FFFU, 0x00002902U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF8000748[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 1 */
- /* .. ==> 0XF8000748[1:1] = 0x00000001U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF8000748[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF8000748[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF8000748[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 1 */
- /* .. ==> 0XF8000748[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. IO_Type = 4 */
- /* .. ==> 0XF8000748[11:9] = 0x00000004U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF8000748[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 1 */
- /* .. ==> 0XF8000748[13:13] = 0x00000001U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000748, 0x00003FFFU, 0x00002902U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF800074C[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 1 */
- /* .. ==> 0XF800074C[1:1] = 0x00000001U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF800074C[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF800074C[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF800074C[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 1 */
- /* .. ==> 0XF800074C[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. IO_Type = 4 */
- /* .. ==> 0XF800074C[11:9] = 0x00000004U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF800074C[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 1 */
- /* .. ==> 0XF800074C[13:13] = 0x00000001U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */
- /* .. */
- EMIT_MASKWRITE(0XF800074C, 0x00003FFFU, 0x00002902U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF8000750[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 1 */
- /* .. ==> 0XF8000750[1:1] = 0x00000001U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF8000750[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF8000750[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF8000750[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 1 */
- /* .. ==> 0XF8000750[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. IO_Type = 4 */
- /* .. ==> 0XF8000750[11:9] = 0x00000004U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF8000750[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 1 */
- /* .. ==> 0XF8000750[13:13] = 0x00000001U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000750, 0x00003FFFU, 0x00002902U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF8000754[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 1 */
- /* .. ==> 0XF8000754[1:1] = 0x00000001U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF8000754[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF8000754[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF8000754[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 1 */
- /* .. ==> 0XF8000754[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. IO_Type = 4 */
- /* .. ==> 0XF8000754[11:9] = 0x00000004U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF8000754[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 1 */
- /* .. ==> 0XF8000754[13:13] = 0x00000001U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000754, 0x00003FFFU, 0x00002902U),
- /* .. TRI_ENABLE = 1 */
- /* .. ==> 0XF8000758[0:0] = 0x00000001U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
- /* .. L0_SEL = 1 */
- /* .. ==> 0XF8000758[1:1] = 0x00000001U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF8000758[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF8000758[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF8000758[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 1 */
- /* .. ==> 0XF8000758[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. IO_Type = 4 */
- /* .. ==> 0XF8000758[11:9] = 0x00000004U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF8000758[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF8000758[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000758, 0x00003FFFU, 0x00000903U),
- /* .. TRI_ENABLE = 1 */
- /* .. ==> 0XF800075C[0:0] = 0x00000001U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
- /* .. L0_SEL = 1 */
- /* .. ==> 0XF800075C[1:1] = 0x00000001U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF800075C[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF800075C[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF800075C[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 1 */
- /* .. ==> 0XF800075C[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. IO_Type = 4 */
- /* .. ==> 0XF800075C[11:9] = 0x00000004U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF800075C[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF800075C[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF800075C, 0x00003FFFU, 0x00000903U),
- /* .. TRI_ENABLE = 1 */
- /* .. ==> 0XF8000760[0:0] = 0x00000001U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
- /* .. L0_SEL = 1 */
- /* .. ==> 0XF8000760[1:1] = 0x00000001U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF8000760[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF8000760[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF8000760[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 1 */
- /* .. ==> 0XF8000760[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. IO_Type = 4 */
- /* .. ==> 0XF8000760[11:9] = 0x00000004U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF8000760[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF8000760[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000760, 0x00003FFFU, 0x00000903U),
- /* .. TRI_ENABLE = 1 */
- /* .. ==> 0XF8000764[0:0] = 0x00000001U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
- /* .. L0_SEL = 1 */
- /* .. ==> 0XF8000764[1:1] = 0x00000001U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF8000764[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF8000764[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF8000764[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 1 */
- /* .. ==> 0XF8000764[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. IO_Type = 4 */
- /* .. ==> 0XF8000764[11:9] = 0x00000004U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF8000764[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF8000764[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000764, 0x00003FFFU, 0x00000903U),
- /* .. TRI_ENABLE = 1 */
- /* .. ==> 0XF8000768[0:0] = 0x00000001U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
- /* .. L0_SEL = 1 */
- /* .. ==> 0XF8000768[1:1] = 0x00000001U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF8000768[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF8000768[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF8000768[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 1 */
- /* .. ==> 0XF8000768[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. IO_Type = 4 */
- /* .. ==> 0XF8000768[11:9] = 0x00000004U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF8000768[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF8000768[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000768, 0x00003FFFU, 0x00000903U),
- /* .. TRI_ENABLE = 1 */
- /* .. ==> 0XF800076C[0:0] = 0x00000001U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
- /* .. L0_SEL = 1 */
- /* .. ==> 0XF800076C[1:1] = 0x00000001U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF800076C[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF800076C[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF800076C[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 1 */
- /* .. ==> 0XF800076C[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. IO_Type = 4 */
- /* .. ==> 0XF800076C[11:9] = 0x00000004U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF800076C[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF800076C[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF800076C, 0x00003FFFU, 0x00000903U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF8000770[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 0 */
- /* .. ==> 0XF8000770[1:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. L1_SEL = 1 */
- /* .. ==> 0XF8000770[2:2] = 0x00000001U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF8000770[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF8000770[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 1 */
- /* .. ==> 0XF8000770[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. IO_Type = 1 */
- /* .. ==> 0XF8000770[11:9] = 0x00000001U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF8000770[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF8000770[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000770, 0x00003FFFU, 0x00000304U),
- /* .. TRI_ENABLE = 1 */
- /* .. ==> 0XF8000774[0:0] = 0x00000001U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
- /* .. L0_SEL = 0 */
- /* .. ==> 0XF8000774[1:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. L1_SEL = 1 */
- /* .. ==> 0XF8000774[2:2] = 0x00000001U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF8000774[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF8000774[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 1 */
- /* .. ==> 0XF8000774[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. IO_Type = 1 */
- /* .. ==> 0XF8000774[11:9] = 0x00000001U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF8000774[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF8000774[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000774, 0x00003FFFU, 0x00000305U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF8000778[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 0 */
- /* .. ==> 0XF8000778[1:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. L1_SEL = 1 */
- /* .. ==> 0XF8000778[2:2] = 0x00000001U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF8000778[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF8000778[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 1 */
- /* .. ==> 0XF8000778[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. IO_Type = 1 */
- /* .. ==> 0XF8000778[11:9] = 0x00000001U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF8000778[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF8000778[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000778, 0x00003FFFU, 0x00000304U),
- /* .. TRI_ENABLE = 1 */
- /* .. ==> 0XF800077C[0:0] = 0x00000001U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
- /* .. L0_SEL = 0 */
- /* .. ==> 0XF800077C[1:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. L1_SEL = 1 */
- /* .. ==> 0XF800077C[2:2] = 0x00000001U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF800077C[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF800077C[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 1 */
- /* .. ==> 0XF800077C[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. IO_Type = 1 */
- /* .. ==> 0XF800077C[11:9] = 0x00000001U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF800077C[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF800077C[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF800077C, 0x00003FFFU, 0x00000305U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF8000780[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 0 */
- /* .. ==> 0XF8000780[1:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. L1_SEL = 1 */
- /* .. ==> 0XF8000780[2:2] = 0x00000001U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF8000780[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF8000780[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 1 */
- /* .. ==> 0XF8000780[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. IO_Type = 1 */
- /* .. ==> 0XF8000780[11:9] = 0x00000001U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF8000780[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF8000780[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000780, 0x00003FFFU, 0x00000304U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF8000784[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 0 */
- /* .. ==> 0XF8000784[1:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. L1_SEL = 1 */
- /* .. ==> 0XF8000784[2:2] = 0x00000001U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF8000784[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF8000784[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 1 */
- /* .. ==> 0XF8000784[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. IO_Type = 1 */
- /* .. ==> 0XF8000784[11:9] = 0x00000001U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF8000784[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF8000784[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000784, 0x00003FFFU, 0x00000304U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF8000788[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 0 */
- /* .. ==> 0XF8000788[1:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. L1_SEL = 1 */
- /* .. ==> 0XF8000788[2:2] = 0x00000001U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF8000788[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF8000788[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 1 */
- /* .. ==> 0XF8000788[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. IO_Type = 1 */
- /* .. ==> 0XF8000788[11:9] = 0x00000001U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF8000788[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF8000788[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000788, 0x00003FFFU, 0x00000304U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF800078C[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 0 */
- /* .. ==> 0XF800078C[1:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. L1_SEL = 1 */
- /* .. ==> 0XF800078C[2:2] = 0x00000001U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF800078C[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF800078C[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 1 */
- /* .. ==> 0XF800078C[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. IO_Type = 1 */
- /* .. ==> 0XF800078C[11:9] = 0x00000001U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF800078C[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF800078C[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF800078C, 0x00003FFFU, 0x00000304U),
- /* .. TRI_ENABLE = 1 */
- /* .. ==> 0XF8000790[0:0] = 0x00000001U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
- /* .. L0_SEL = 0 */
- /* .. ==> 0XF8000790[1:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. L1_SEL = 1 */
- /* .. ==> 0XF8000790[2:2] = 0x00000001U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF8000790[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF8000790[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 1 */
- /* .. ==> 0XF8000790[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. IO_Type = 1 */
- /* .. ==> 0XF8000790[11:9] = 0x00000001U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF8000790[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF8000790[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000790, 0x00003FFFU, 0x00000305U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF8000794[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 0 */
- /* .. ==> 0XF8000794[1:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. L1_SEL = 1 */
- /* .. ==> 0XF8000794[2:2] = 0x00000001U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF8000794[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF8000794[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 1 */
- /* .. ==> 0XF8000794[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. IO_Type = 1 */
- /* .. ==> 0XF8000794[11:9] = 0x00000001U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF8000794[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF8000794[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000794, 0x00003FFFU, 0x00000304U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF8000798[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 0 */
- /* .. ==> 0XF8000798[1:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. L1_SEL = 1 */
- /* .. ==> 0XF8000798[2:2] = 0x00000001U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF8000798[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF8000798[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 1 */
- /* .. ==> 0XF8000798[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. IO_Type = 1 */
- /* .. ==> 0XF8000798[11:9] = 0x00000001U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF8000798[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF8000798[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000798, 0x00003FFFU, 0x00000304U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF800079C[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 0 */
- /* .. ==> 0XF800079C[1:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. L1_SEL = 1 */
- /* .. ==> 0XF800079C[2:2] = 0x00000001U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF800079C[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF800079C[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 1 */
- /* .. ==> 0XF800079C[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. IO_Type = 1 */
- /* .. ==> 0XF800079C[11:9] = 0x00000001U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF800079C[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF800079C[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF800079C, 0x00003FFFU, 0x00000304U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF80007A0[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 0 */
- /* .. ==> 0XF80007A0[1:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF80007A0[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF80007A0[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 4 */
- /* .. ==> 0XF80007A0[7:5] = 0x00000004U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
- /* .. Speed = 1 */
- /* .. ==> 0XF80007A0[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. IO_Type = 1 */
- /* .. ==> 0XF80007A0[11:9] = 0x00000001U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF80007A0[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF80007A0[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU, 0x00000380U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF80007A4[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 0 */
- /* .. ==> 0XF80007A4[1:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF80007A4[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF80007A4[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 4 */
- /* .. ==> 0XF80007A4[7:5] = 0x00000004U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
- /* .. Speed = 1 */
- /* .. ==> 0XF80007A4[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. IO_Type = 1 */
- /* .. ==> 0XF80007A4[11:9] = 0x00000001U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF80007A4[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF80007A4[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU, 0x00000380U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF80007A8[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 0 */
- /* .. ==> 0XF80007A8[1:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF80007A8[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF80007A8[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 4 */
- /* .. ==> 0XF80007A8[7:5] = 0x00000004U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
- /* .. Speed = 1 */
- /* .. ==> 0XF80007A8[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. IO_Type = 1 */
- /* .. ==> 0XF80007A8[11:9] = 0x00000001U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF80007A8[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF80007A8[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU, 0x00000380U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF80007AC[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 0 */
- /* .. ==> 0XF80007AC[1:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF80007AC[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF80007AC[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 4 */
- /* .. ==> 0XF80007AC[7:5] = 0x00000004U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
- /* .. Speed = 1 */
- /* .. ==> 0XF80007AC[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. IO_Type = 1 */
- /* .. ==> 0XF80007AC[11:9] = 0x00000001U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF80007AC[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF80007AC[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU, 0x00000380U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF80007B0[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 0 */
- /* .. ==> 0XF80007B0[1:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF80007B0[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF80007B0[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 4 */
- /* .. ==> 0XF80007B0[7:5] = 0x00000004U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
- /* .. Speed = 1 */
- /* .. ==> 0XF80007B0[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. IO_Type = 1 */
- /* .. ==> 0XF80007B0[11:9] = 0x00000001U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF80007B0[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF80007B0[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU, 0x00000380U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF80007B4[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 0 */
- /* .. ==> 0XF80007B4[1:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF80007B4[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF80007B4[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 4 */
- /* .. ==> 0XF80007B4[7:5] = 0x00000004U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
- /* .. Speed = 1 */
- /* .. ==> 0XF80007B4[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. IO_Type = 1 */
- /* .. ==> 0XF80007B4[11:9] = 0x00000001U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF80007B4[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF80007B4[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00000380U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF80007B8[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 0 */
- /* .. ==> 0XF80007B8[1:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF80007B8[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF80007B8[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF80007B8[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 0 */
- /* .. ==> 0XF80007B8[8:8] = 0x00000000U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
- /* .. IO_Type = 1 */
- /* .. ==> 0XF80007B8[11:9] = 0x00000001U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
- /* .. PULLUP = 1 */
- /* .. ==> 0XF80007B8[12:12] = 0x00000001U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF80007B8[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU, 0x00001200U),
- /* .. TRI_ENABLE = 1 */
- /* .. ==> 0XF80007BC[0:0] = 0x00000001U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
- /* .. Speed = 0 */
- /* .. ==> 0XF80007BC[8:8] = 0x00000000U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
- /* .. IO_Type = 1 */
- /* .. ==> 0XF80007BC[11:9] = 0x00000001U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF80007BC[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF80007BC[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF80007BC, 0x00003F01U, 0x00000201U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF80007C0[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 0 */
- /* .. ==> 0XF80007C0[1:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF80007C0[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF80007C0[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 7 */
- /* .. ==> 0XF80007C0[7:5] = 0x00000007U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x000000E0U */
- /* .. Speed = 0 */
- /* .. ==> 0XF80007C0[8:8] = 0x00000000U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
- /* .. IO_Type = 1 */
- /* .. ==> 0XF80007C0[11:9] = 0x00000001U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF80007C0[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF80007C0[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU, 0x000002E0U),
- /* .. TRI_ENABLE = 1 */
- /* .. ==> 0XF80007C4[0:0] = 0x00000001U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
- /* .. L0_SEL = 0 */
- /* .. ==> 0XF80007C4[1:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF80007C4[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF80007C4[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 7 */
- /* .. ==> 0XF80007C4[7:5] = 0x00000007U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x000000E0U */
- /* .. Speed = 0 */
- /* .. ==> 0XF80007C4[8:8] = 0x00000000U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
- /* .. IO_Type = 1 */
- /* .. ==> 0XF80007C4[11:9] = 0x00000001U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF80007C4[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF80007C4[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x000002E1U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF80007C8[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 0 */
- /* .. ==> 0XF80007C8[1:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF80007C8[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF80007C8[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF80007C8[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 0 */
- /* .. ==> 0XF80007C8[8:8] = 0x00000000U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
- /* .. IO_Type = 1 */
- /* .. ==> 0XF80007C8[11:9] = 0x00000001U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF80007C8[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF80007C8[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU, 0x00000200U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF80007CC[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 0 */
- /* .. ==> 0XF80007CC[1:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF80007CC[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF80007CC[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 0 */
- /* .. ==> 0XF80007CC[7:5] = 0x00000000U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
- /* .. Speed = 0 */
- /* .. ==> 0XF80007CC[8:8] = 0x00000000U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
- /* .. IO_Type = 1 */
- /* .. ==> 0XF80007CC[11:9] = 0x00000001U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF80007CC[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF80007CC[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU, 0x00000200U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF80007D0[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 0 */
- /* .. ==> 0XF80007D0[1:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF80007D0[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF80007D0[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 4 */
- /* .. ==> 0XF80007D0[7:5] = 0x00000004U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
- /* .. Speed = 0 */
- /* .. ==> 0XF80007D0[8:8] = 0x00000000U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
- /* .. IO_Type = 1 */
- /* .. ==> 0XF80007D0[11:9] = 0x00000001U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF80007D0[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF80007D0[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU, 0x00000280U),
- /* .. TRI_ENABLE = 0 */
- /* .. ==> 0XF80007D4[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. L0_SEL = 0 */
- /* .. ==> 0XF80007D4[1:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. L1_SEL = 0 */
- /* .. ==> 0XF80007D4[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. L2_SEL = 0 */
- /* .. ==> 0XF80007D4[4:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
- /* .. L3_SEL = 4 */
- /* .. ==> 0XF80007D4[7:5] = 0x00000004U */
- /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
- /* .. Speed = 0 */
- /* .. ==> 0XF80007D4[8:8] = 0x00000000U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
- /* .. IO_Type = 1 */
- /* .. ==> 0XF80007D4[11:9] = 0x00000001U */
- /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
- /* .. PULLUP = 0 */
- /* .. ==> 0XF80007D4[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. DisableRcvr = 0 */
- /* .. ==> 0XF80007D4[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU, 0x00000280U),
- /* .. SDIO0_WP_SEL = 55 */
- /* .. ==> 0XF8000830[5:0] = 0x00000037U */
- /* .. ==> MASK : 0x0000003FU VAL : 0x00000037U */
- /* .. SDIO0_CD_SEL = 47 */
- /* .. ==> 0XF8000830[21:16] = 0x0000002FU */
- /* .. ==> MASK : 0x003F0000U VAL : 0x002F0000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000830, 0x003F003FU, 0x002F0037U),
- /* .. FINISH: MIO PROGRAMMING */
- /* .. START: LOCK IT BACK */
- /* .. LOCK_KEY = 0X767B */
- /* .. ==> 0XF8000004[15:0] = 0x0000767BU */
- /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */
- /* .. */
- EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
- /* .. FINISH: LOCK IT BACK */
- /* FINISH: top */
- /* */
- EMIT_EXIT(),
-
- /* */
-};
-
-unsigned long ps7_peripherals_init_data_1_0[] = {
- /* START: top */
- /* .. START: SLCR SETTINGS */
- /* .. UNLOCK_KEY = 0XDF0D */
- /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
- /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */
- /* .. */
- EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
- /* .. FINISH: SLCR SETTINGS */
- /* .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS */
- /* .. IBUF_DISABLE_MODE = 0x1 */
- /* .. ==> 0XF8000B48[7:7] = 0x00000001U */
- /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */
- /* .. TERM_DISABLE_MODE = 0x1 */
- /* .. ==> 0XF8000B48[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. */
- EMIT_MASKWRITE(0XF8000B48, 0x00000180U, 0x00000180U),
- /* .. IBUF_DISABLE_MODE = 0x1 */
- /* .. ==> 0XF8000B4C[7:7] = 0x00000001U */
- /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */
- /* .. TERM_DISABLE_MODE = 0x1 */
- /* .. ==> 0XF8000B4C[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. */
- EMIT_MASKWRITE(0XF8000B4C, 0x00000180U, 0x00000180U),
- /* .. IBUF_DISABLE_MODE = 0x1 */
- /* .. ==> 0XF8000B50[7:7] = 0x00000001U */
- /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */
- /* .. TERM_DISABLE_MODE = 0x1 */
- /* .. ==> 0XF8000B50[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. */
- EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U),
- /* .. IBUF_DISABLE_MODE = 0x1 */
- /* .. ==> 0XF8000B54[7:7] = 0x00000001U */
- /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */
- /* .. TERM_DISABLE_MODE = 0x1 */
- /* .. ==> 0XF8000B54[8:8] = 0x00000001U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
- /* .. */
- EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U),
- /* .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS */
- /* .. START: LOCK IT BACK */
- /* .. LOCK_KEY = 0X767B */
- /* .. ==> 0XF8000004[15:0] = 0x0000767BU */
- /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */
- /* .. */
- EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
- /* .. FINISH: LOCK IT BACK */
- /* .. START: SRAM/NOR SET OPMODE */
- /* .. FINISH: SRAM/NOR SET OPMODE */
- /* .. START: UART REGISTERS */
- /* .. BDIV = 0x6 */
- /* .. ==> 0XE0001034[7:0] = 0x00000006U */
- /* .. ==> MASK : 0x000000FFU VAL : 0x00000006U */
- /* .. */
- EMIT_MASKWRITE(0XE0001034, 0x000000FFU, 0x00000006U),
- /* .. CD = 0x7c */
- /* .. ==> 0XE0001018[15:0] = 0x0000007CU */
- /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU */
- /* .. */
- EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU, 0x0000007CU),
- /* .. STPBRK = 0x0 */
- /* .. ==> 0XE0001000[8:8] = 0x00000000U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
- /* .. STTBRK = 0x0 */
- /* .. ==> 0XE0001000[7:7] = 0x00000000U */
- /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
- /* .. RSTTO = 0x0 */
- /* .. ==> 0XE0001000[6:6] = 0x00000000U */
- /* .. ==> MASK : 0x00000040U VAL : 0x00000000U */
- /* .. TXDIS = 0x0 */
- /* .. ==> 0XE0001000[5:5] = 0x00000000U */
- /* .. ==> MASK : 0x00000020U VAL : 0x00000000U */
- /* .. TXEN = 0x1 */
- /* .. ==> 0XE0001000[4:4] = 0x00000001U */
- /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */
- /* .. RXDIS = 0x0 */
- /* .. ==> 0XE0001000[3:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
- /* .. RXEN = 0x1 */
- /* .. ==> 0XE0001000[2:2] = 0x00000001U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
- /* .. TXRES = 0x1 */
- /* .. ==> 0XE0001000[1:1] = 0x00000001U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
- /* .. RXRES = 0x1 */
- /* .. ==> 0XE0001000[0:0] = 0x00000001U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
- /* .. */
- EMIT_MASKWRITE(0XE0001000, 0x000001FFU, 0x00000017U),
- /* .. IRMODE = 0x0 */
- /* .. ==> 0XE0001004[11:11] = 0x00000000U */
- /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
- /* .. UCLKEN = 0x0 */
- /* .. ==> 0XE0001004[10:10] = 0x00000000U */
- /* .. ==> MASK : 0x00000400U VAL : 0x00000000U */
- /* .. CHMODE = 0x0 */
- /* .. ==> 0XE0001004[9:8] = 0x00000000U */
- /* .. ==> MASK : 0x00000300U VAL : 0x00000000U */
- /* .. NBSTOP = 0x0 */
- /* .. ==> 0XE0001004[7:6] = 0x00000000U */
- /* .. ==> MASK : 0x000000C0U VAL : 0x00000000U */
- /* .. PAR = 0x4 */
- /* .. ==> 0XE0001004[5:3] = 0x00000004U */
- /* .. ==> MASK : 0x00000038U VAL : 0x00000020U */
- /* .. CHRL = 0x0 */
- /* .. ==> 0XE0001004[2:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */
- /* .. CLKS = 0x0 */
- /* .. ==> 0XE0001004[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XE0001004, 0x00000FFFU, 0x00000020U),
- /* .. FINISH: UART REGISTERS */
- /* .. START: QSPI REGISTERS */
- /* .. Holdb_dr = 1 */
- /* .. ==> 0XE000D000[19:19] = 0x00000001U */
- /* .. ==> MASK : 0x00080000U VAL : 0x00080000U */
- /* .. */
- EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U),
- /* .. FINISH: QSPI REGISTERS */
- /* .. START: PL POWER ON RESET REGISTERS */
- /* .. PCFG_POR_CNT_4K = 0 */
- /* .. ==> 0XF8007000[29:29] = 0x00000000U */
- /* .. ==> MASK : 0x20000000U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U),
- /* .. FINISH: PL POWER ON RESET REGISTERS */
- /* .. START: SMC TIMING CALCULATION REGISTER UPDATE */
- /* .. .. START: NAND SET CYCLE */
- /* .. .. FINISH: NAND SET CYCLE */
- /* .. .. START: OPMODE */
- /* .. .. FINISH: OPMODE */
- /* .. .. START: DIRECT COMMAND */
- /* .. .. FINISH: DIRECT COMMAND */
- /* .. .. START: SRAM/NOR CS0 SET CYCLE */
- /* .. .. FINISH: SRAM/NOR CS0 SET CYCLE */
- /* .. .. START: DIRECT COMMAND */
- /* .. .. FINISH: DIRECT COMMAND */
- /* .. .. START: NOR CS0 BASE ADDRESS */
- /* .. .. FINISH: NOR CS0 BASE ADDRESS */
- /* .. .. START: SRAM/NOR CS1 SET CYCLE */
- /* .. .. FINISH: SRAM/NOR CS1 SET CYCLE */
- /* .. .. START: DIRECT COMMAND */
- /* .. .. FINISH: DIRECT COMMAND */
- /* .. .. START: NOR CS1 BASE ADDRESS */
- /* .. .. FINISH: NOR CS1 BASE ADDRESS */
- /* .. .. START: USB RESET */
- /* .. .. .. START: USB0 RESET */
- /* .. .. .. .. START: DIR MODE BANK 0 */
- /* .. .. .. .. FINISH: DIR MODE BANK 0 */
- /* .. .. .. .. START: DIR MODE BANK 1 */
- /* .. .. .. .. DIRECTION_1 = 0x4000 */
- /* .. .. .. .. ==> 0XE000A244[21:0] = 0x00004000U */
- /* .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U */
- /* .. .. .. .. */
- EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU, 0x00004000U),
- /* .. .. .. .. FINISH: DIR MODE BANK 1 */
- /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
- /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
- /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
- /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
- /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
- /* .. .. .. .. MASK_1_LSW = 0xbfff */
- /* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */
- /* .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U */
- /* .. .. .. .. DATA_1_LSW = 0x4000 */
- /* .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U */
- /* .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U */
- /* .. .. .. .. */
- EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF4000U),
- /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
- /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
- /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
- /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
- /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
- /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
- /* .. .. .. .. OP_ENABLE_1 = 0x4000 */
- /* .. .. .. .. ==> 0XE000A248[21:0] = 0x00004000U */
- /* .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U */
- /* .. .. .. .. */
- EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU, 0x00004000U),
- /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
- /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
- /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
- /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
- /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
- /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
- /* .. .. .. .. MASK_1_LSW = 0xbfff */
- /* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */
- /* .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U */
- /* .. .. .. .. DATA_1_LSW = 0x0 */
- /* .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U */
- /* .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U */
- /* .. .. .. .. */
- EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF0000U),
- /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
- /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
- /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
- /* .. .. .. .. START: ADD 1 MS DELAY */
- /* .. .. .. .. */
- EMIT_MASKDELAY(0XF8F00200, 1),
- /* .. .. .. .. FINISH: ADD 1 MS DELAY */
- /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
- /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
- /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
- /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
- /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
- /* .. .. .. .. MASK_1_LSW = 0xbfff */
- /* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */
- /* .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U */
- /* .. .. .. .. DATA_1_LSW = 0x4000 */
- /* .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U */
- /* .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U */
- /* .. .. .. .. */
- EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF4000U),
- /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
- /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
- /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
- /* .. .. .. FINISH: USB0 RESET */
- /* .. .. .. START: USB1 RESET */
- /* .. .. .. .. START: DIR MODE BANK 0 */
- /* .. .. .. .. FINISH: DIR MODE BANK 0 */
- /* .. .. .. .. START: DIR MODE BANK 1 */
- /* .. .. .. .. FINISH: DIR MODE BANK 1 */
- /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
- /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
- /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
- /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
- /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
- /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
- /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
- /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
- /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
- /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
- /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
- /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
- /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
- /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
- /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
- /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
- /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
- /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
- /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
- /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
- /* .. .. .. .. START: ADD 1 MS DELAY */
- /* .. .. .. .. */
- EMIT_MASKDELAY(0XF8F00200, 1),
- /* .. .. .. .. FINISH: ADD 1 MS DELAY */
- /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
- /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
- /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
- /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
- /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
- /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
- /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
- /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
- /* .. .. .. FINISH: USB1 RESET */
- /* .. .. FINISH: USB RESET */
- /* .. .. START: ENET RESET */
- /* .. .. .. START: ENET0 RESET */
- /* .. .. .. .. START: DIR MODE BANK 0 */
- /* .. .. .. .. FINISH: DIR MODE BANK 0 */
- /* .. .. .. .. START: DIR MODE BANK 1 */
- /* .. .. .. .. FINISH: DIR MODE BANK 1 */
- /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
- /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
- /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
- /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
- /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
- /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
- /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
- /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
- /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
- /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
- /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
- /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
- /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
- /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
- /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
- /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
- /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
- /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
- /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
- /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
- /* .. .. .. .. START: ADD 1 MS DELAY */
- /* .. .. .. .. */
- EMIT_MASKDELAY(0XF8F00200, 1),
- /* .. .. .. .. FINISH: ADD 1 MS DELAY */
- /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
- /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
- /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
- /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
- /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
- /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
- /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
- /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
- /* .. .. .. FINISH: ENET0 RESET */
- /* .. .. .. START: ENET1 RESET */
- /* .. .. .. .. START: DIR MODE BANK 0 */
- /* .. .. .. .. FINISH: DIR MODE BANK 0 */
- /* .. .. .. .. START: DIR MODE BANK 1 */
- /* .. .. .. .. FINISH: DIR MODE BANK 1 */
- /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
- /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
- /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
- /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
- /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
- /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
- /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
- /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
- /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
- /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
- /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
- /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
- /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
- /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
- /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
- /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
- /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
- /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
- /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
- /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
- /* .. .. .. .. START: ADD 1 MS DELAY */
- /* .. .. .. .. */
- EMIT_MASKDELAY(0XF8F00200, 1),
- /* .. .. .. .. FINISH: ADD 1 MS DELAY */
- /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
- /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
- /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
- /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
- /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
- /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
- /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
- /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
- /* .. .. .. FINISH: ENET1 RESET */
- /* .. .. FINISH: ENET RESET */
- /* .. .. START: I2C RESET */
- /* .. .. .. START: I2C0 RESET */
- /* .. .. .. .. START: DIR MODE GPIO BANK0 */
- /* .. .. .. .. FINISH: DIR MODE GPIO BANK0 */
- /* .. .. .. .. START: DIR MODE GPIO BANK1 */
- /* .. .. .. .. FINISH: DIR MODE GPIO BANK1 */
- /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
- /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
- /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
- /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
- /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
- /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
- /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
- /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
- /* .. .. .. .. START: OUTPUT ENABLE */
- /* .. .. .. .. FINISH: OUTPUT ENABLE */
- /* .. .. .. .. START: OUTPUT ENABLE */
- /* .. .. .. .. FINISH: OUTPUT ENABLE */
- /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
- /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
- /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
- /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
- /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
- /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
- /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
- /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
- /* .. .. .. .. START: ADD 1 MS DELAY */
- /* .. .. .. .. */
- EMIT_MASKDELAY(0XF8F00200, 1),
- /* .. .. .. .. FINISH: ADD 1 MS DELAY */
- /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
- /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
- /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
- /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
- /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
- /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
- /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
- /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
- /* .. .. .. FINISH: I2C0 RESET */
- /* .. .. .. START: I2C1 RESET */
- /* .. .. .. .. START: DIR MODE GPIO BANK0 */
- /* .. .. .. .. FINISH: DIR MODE GPIO BANK0 */
- /* .. .. .. .. START: DIR MODE GPIO BANK1 */
- /* .. .. .. .. FINISH: DIR MODE GPIO BANK1 */
- /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
- /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
- /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
- /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
- /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
- /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
- /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
- /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
- /* .. .. .. .. START: OUTPUT ENABLE */
- /* .. .. .. .. FINISH: OUTPUT ENABLE */
- /* .. .. .. .. START: OUTPUT ENABLE */
- /* .. .. .. .. FINISH: OUTPUT ENABLE */
- /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
- /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
- /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
- /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
- /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
- /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
- /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
- /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
- /* .. .. .. .. START: ADD 1 MS DELAY */
- /* .. .. .. .. */
- EMIT_MASKDELAY(0XF8F00200, 1),
- /* .. .. .. .. FINISH: ADD 1 MS DELAY */
- /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
- /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
- /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
- /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
- /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
- /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
- /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
- /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
- /* .. .. .. FINISH: I2C1 RESET */
- /* .. .. FINISH: I2C RESET */
- /* .. .. START: NOR CHIP SELECT */
- /* .. .. .. START: DIR MODE BANK 0 */
- /* .. .. .. FINISH: DIR MODE BANK 0 */
- /* .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
- /* .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
- /* .. .. .. START: OUTPUT ENABLE BANK 0 */
- /* .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
- /* .. .. FINISH: NOR CHIP SELECT */
- /* .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE */
- /* FINISH: top */
- /* */
- EMIT_EXIT(),
-
- /* */
-};
-
-unsigned long ps7_post_config_1_0[] = {
- /* START: top */
- /* .. START: SLCR SETTINGS */
- /* .. UNLOCK_KEY = 0XDF0D */
- /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
- /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */
- /* .. */
- EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
- /* .. FINISH: SLCR SETTINGS */
- /* .. START: ENABLING LEVEL SHIFTER */
- /* .. USER_INP_ICT_EN_0 = 3 */
- /* .. ==> 0XF8000900[1:0] = 0x00000003U */
- /* .. ==> MASK : 0x00000003U VAL : 0x00000003U */
- /* .. USER_INP_ICT_EN_1 = 3 */
- /* .. ==> 0XF8000900[3:2] = 0x00000003U */
- /* .. ==> MASK : 0x0000000CU VAL : 0x0000000CU */
- /* .. */
- EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU),
- /* .. FINISH: ENABLING LEVEL SHIFTER */
- /* .. START: FPGA RESETS TO 0 */
- /* .. reserved_3 = 0 */
- /* .. ==> 0XF8000240[31:25] = 0x00000000U */
- /* .. ==> MASK : 0xFE000000U VAL : 0x00000000U */
- /* .. FPGA_ACP_RST = 0 */
- /* .. ==> 0XF8000240[24:24] = 0x00000000U */
- /* .. ==> MASK : 0x01000000U VAL : 0x00000000U */
- /* .. FPGA_AXDS3_RST = 0 */
- /* .. ==> 0XF8000240[23:23] = 0x00000000U */
- /* .. ==> MASK : 0x00800000U VAL : 0x00000000U */
- /* .. FPGA_AXDS2_RST = 0 */
- /* .. ==> 0XF8000240[22:22] = 0x00000000U */
- /* .. ==> MASK : 0x00400000U VAL : 0x00000000U */
- /* .. FPGA_AXDS1_RST = 0 */
- /* .. ==> 0XF8000240[21:21] = 0x00000000U */
- /* .. ==> MASK : 0x00200000U VAL : 0x00000000U */
- /* .. FPGA_AXDS0_RST = 0 */
- /* .. ==> 0XF8000240[20:20] = 0x00000000U */
- /* .. ==> MASK : 0x00100000U VAL : 0x00000000U */
- /* .. reserved_2 = 0 */
- /* .. ==> 0XF8000240[19:18] = 0x00000000U */
- /* .. ==> MASK : 0x000C0000U VAL : 0x00000000U */
- /* .. FSSW1_FPGA_RST = 0 */
- /* .. ==> 0XF8000240[17:17] = 0x00000000U */
- /* .. ==> MASK : 0x00020000U VAL : 0x00000000U */
- /* .. FSSW0_FPGA_RST = 0 */
- /* .. ==> 0XF8000240[16:16] = 0x00000000U */
- /* .. ==> MASK : 0x00010000U VAL : 0x00000000U */
- /* .. reserved_1 = 0 */
- /* .. ==> 0XF8000240[15:14] = 0x00000000U */
- /* .. ==> MASK : 0x0000C000U VAL : 0x00000000U */
- /* .. FPGA_FMSW1_RST = 0 */
- /* .. ==> 0XF8000240[13:13] = 0x00000000U */
- /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
- /* .. FPGA_FMSW0_RST = 0 */
- /* .. ==> 0XF8000240[12:12] = 0x00000000U */
- /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
- /* .. FPGA_DMA3_RST = 0 */
- /* .. ==> 0XF8000240[11:11] = 0x00000000U */
- /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
- /* .. FPGA_DMA2_RST = 0 */
- /* .. ==> 0XF8000240[10:10] = 0x00000000U */
- /* .. ==> MASK : 0x00000400U VAL : 0x00000000U */
- /* .. FPGA_DMA1_RST = 0 */
- /* .. ==> 0XF8000240[9:9] = 0x00000000U */
- /* .. ==> MASK : 0x00000200U VAL : 0x00000000U */
- /* .. FPGA_DMA0_RST = 0 */
- /* .. ==> 0XF8000240[8:8] = 0x00000000U */
- /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
- /* .. reserved = 0 */
- /* .. ==> 0XF8000240[7:4] = 0x00000000U */
- /* .. ==> MASK : 0x000000F0U VAL : 0x00000000U */
- /* .. FPGA3_OUT_RST = 0 */
- /* .. ==> 0XF8000240[3:3] = 0x00000000U */
- /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
- /* .. FPGA2_OUT_RST = 0 */
- /* .. ==> 0XF8000240[2:2] = 0x00000000U */
- /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
- /* .. FPGA1_OUT_RST = 0 */
- /* .. ==> 0XF8000240[1:1] = 0x00000000U */
- /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
- /* .. FPGA0_OUT_RST = 0 */
- /* .. ==> 0XF8000240[0:0] = 0x00000000U */
- /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
- /* .. */
- EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU, 0x00000000U),
- /* .. FINISH: FPGA RESETS TO 0 */
- /* .. START: AFI REGISTERS */
- /* .. .. START: AFI0 REGISTERS */
- /* .. .. FINISH: AFI0 REGISTERS */
- /* .. .. START: AFI1 REGISTERS */
- /* .. .. FINISH: AFI1 REGISTERS */
- /* .. .. START: AFI2 REGISTERS */
- /* .. .. FINISH: AFI2 REGISTERS */
- /* .. .. START: AFI3 REGISTERS */
- /* .. .. FINISH: AFI3 REGISTERS */
- /* .. FINISH: AFI REGISTERS */
- /* .. START: LOCK IT BACK */
- /* .. LOCK_KEY = 0X767B */
- /* .. ==> 0XF8000004[15:0] = 0x0000767BU */
- /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */
- /* .. */
- EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
- /* .. FINISH: LOCK IT BACK */
- /* FINISH: top */
- /* */
- EMIT_EXIT(),
-
- /* */
-};
-
-unsigned long ps7_debug_1_0[] = {
- /* START: top */
- /* .. START: CROSS TRIGGER CONFIGURATIONS */
- /* .. .. START: UNLOCKING CTI REGISTERS */
- /* .. .. KEY = 0XC5ACCE55 */
- /* .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U */
- /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU, 0xC5ACCE55U),
- /* .. .. KEY = 0XC5ACCE55 */
- /* .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U */
- /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU, 0xC5ACCE55U),
- /* .. .. KEY = 0XC5ACCE55 */
- /* .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U */
- /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU, 0xC5ACCE55U),
- /* .. .. FINISH: UNLOCKING CTI REGISTERS */
- /* .. .. START: ENABLING CTI MODULES AND CHANNELS */
- /* .. .. FINISH: ENABLING CTI MODULES AND CHANNELS */
- /* .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS */
- /* .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS */
- /* .. FINISH: CROSS TRIGGER CONFIGURATIONS */
- /* FINISH: top */
- /* */
- EMIT_EXIT(),
-
- /* */
-};
-
-#include "xil_io.h"
-#define PS7_MASK_POLL_TIME 100000000
-
-char *getPS7MessageInfo(unsigned key)
-{
- char *err_msg = "";
- switch (key) {
- case PS7_INIT_SUCCESS:
- err_msg = "PS7 initialization successful";
- break;
- case PS7_INIT_CORRUPT:
- err_msg = "PS7 init Data Corrupted";
- break;
- case PS7_INIT_TIMEOUT:
- err_msg = "PS7 init mask poll timeout";
- break;
- case PS7_POLL_FAILED_DDR_INIT:
- err_msg = "Mask Poll failed for DDR Init";
- break;
- case PS7_POLL_FAILED_DMA:
- err_msg = "Mask Poll failed for PLL Init";
- break;
- case PS7_POLL_FAILED_PLL:
- err_msg = "Mask Poll failed for DMA done bit";
- break;
- default:
- err_msg = "Undefined error status";
- break;
- }
-
- return err_msg;
-}
-
-unsigned long ps7GetSiliconVersion(void)
-{
- /* Read PS version from MCTRL register [31:28] */
- unsigned long mask = 0xF0000000;
- unsigned long *addr = (unsigned long *)0XF8007080;
- unsigned long ps_version = (*addr & mask) >> 28;
- return ps_version;
-}
-
-void mask_write(unsigned long add, unsigned long mask, unsigned long val)
-{
- unsigned long *addr = (unsigned long *)add;
- *addr = (val & mask) | (*addr & ~mask);
-}
-
-int mask_poll(unsigned long add, unsigned long mask)
-{
- volatile unsigned long *addr = (volatile unsigned long *)add;
- int i = 0;
- while (!(*addr & mask)) {
- if (i == PS7_MASK_POLL_TIME)
- return -1;
- i++;
- }
- return 1;
-}
-
-unsigned long mask_read(unsigned long add, unsigned long mask)
-{
- unsigned long *addr = (unsigned long *)add;
- unsigned long val = (*addr & mask);
- return val;
-}
-
-int ps7_config(unsigned long *ps7_config_init)
-{
- unsigned long *ptr = ps7_config_init;
-
- unsigned long opcode; /* current instruction .. */
- unsigned long args[16]; /* no opcode has so many args ... */
- int numargs; /* number of arguments of this instruction */
- int j; /* general purpose index */
-
- volatile unsigned long *addr; /* some variable to make code readable */
- unsigned long val, mask; /* some variable to make code readable */
-
- int finish = -1; /* loop while this is negative ! */
- int i = 0; /* Timeout variable */
-
- while (finish < 0) {
- numargs = ptr[0] & 0xF;
- opcode = ptr[0] >> 4;
-
- for (j = 0; j < numargs; j++)
- args[j] = ptr[j + 1];
- ptr += numargs + 1;
-
- switch (opcode) {
- case OPCODE_EXIT:
- finish = PS7_INIT_SUCCESS;
- break;
-
- case OPCODE_CLEAR:
- addr = (unsigned long *)args[0];
- *addr = 0;
- break;
-
- case OPCODE_WRITE:
- addr = (unsigned long *)args[0];
- val = args[1];
- *addr = val;
- break;
-
- case OPCODE_MASKWRITE:
- addr = (unsigned long *)args[0];
- mask = args[1];
- val = args[2];
- *addr = (val & mask) | (*addr & ~mask);
- break;
-
- case OPCODE_MASKPOLL:
- addr = (unsigned long *)args[0];
- mask = args[1];
- i = 0;
- while (!(*addr & mask)) {
- if (i == PS7_MASK_POLL_TIME) {
- finish = PS7_INIT_TIMEOUT;
- break;
- }
- i++;
- }
- break;
- case OPCODE_MASKDELAY:
- addr = (unsigned long *)args[0];
- mask = args[1];
- int delay = get_number_of_cycles_for_delay(mask);
- perf_reset_and_start_timer();
- while ((*addr < delay))
- ;
- break;
- default:
- finish = PS7_INIT_CORRUPT;
- break;
- }
- }
- return finish;
-}
-
-unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0;
-unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0;
-unsigned long *ps7_clock_init_data = ps7_clock_init_data_3_0;
-unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0;
-unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
-
-int ps7_post_config(void)
-{
- /* Get the PS_VERSION on run time */
- unsigned long si_ver = ps7GetSiliconVersion();
- int ret = -1;
- if (si_ver == PCW_SILICON_VERSION_1) {
- ret = ps7_config(ps7_post_config_1_0);
- if (ret != PS7_INIT_SUCCESS)
- return ret;
- } else if (si_ver == PCW_SILICON_VERSION_2) {
- ret = ps7_config(ps7_post_config_2_0);
- if (ret != PS7_INIT_SUCCESS)
- return ret;
- } else {
- ret = ps7_config(ps7_post_config_3_0);
- if (ret != PS7_INIT_SUCCESS)
- return ret;
- }
- return PS7_INIT_SUCCESS;
-}
-
-int ps7_debug(void)
-{
- /* Get the PS_VERSION on run time */
- unsigned long si_ver = ps7GetSiliconVersion();
- int ret = -1;
- if (si_ver == PCW_SILICON_VERSION_1) {
- ret = ps7_config(ps7_debug_1_0);
- if (ret != PS7_INIT_SUCCESS)
- return ret;
- } else if (si_ver == PCW_SILICON_VERSION_2) {
- ret = ps7_config(ps7_debug_2_0);
- if (ret != PS7_INIT_SUCCESS)
- return ret;
- } else {
- ret = ps7_config(ps7_debug_3_0);
- if (ret != PS7_INIT_SUCCESS)
- return ret;
- }
- return PS7_INIT_SUCCESS;
-}
-
-int ps7_init(void)
-{
- /* Get the PS_VERSION on run time */
- unsigned long si_ver = ps7GetSiliconVersion();
- int ret;
- /*int pcw_ver = 0; */
-
- if (si_ver == PCW_SILICON_VERSION_1) {
- ps7_mio_init_data = ps7_mio_init_data_1_0;
- ps7_pll_init_data = ps7_pll_init_data_1_0;
- ps7_clock_init_data = ps7_clock_init_data_1_0;
- ps7_ddr_init_data = ps7_ddr_init_data_1_0;
- ps7_peripherals_init_data = ps7_peripherals_init_data_1_0;
- /*pcw_ver = 1; */
-
- } else if (si_ver == PCW_SILICON_VERSION_2) {
- ps7_mio_init_data = ps7_mio_init_data_2_0;
- ps7_pll_init_data = ps7_pll_init_data_2_0;
- ps7_clock_init_data = ps7_clock_init_data_2_0;
- ps7_ddr_init_data = ps7_ddr_init_data_2_0;
- ps7_peripherals_init_data = ps7_peripherals_init_data_2_0;
- /*pcw_ver = 2; */
-
- } else {
- ps7_mio_init_data = ps7_mio_init_data_3_0;
- ps7_pll_init_data = ps7_pll_init_data_3_0;
- ps7_clock_init_data = ps7_clock_init_data_3_0;
- ps7_ddr_init_data = ps7_ddr_init_data_3_0;
- ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
- /*pcw_ver = 3; */
- }
-
- /* MIO init */
- ret = ps7_config(ps7_mio_init_data);
- if (ret != PS7_INIT_SUCCESS)
- return ret;
-
- /* PLL init */
- ret = ps7_config(ps7_pll_init_data);
- if (ret != PS7_INIT_SUCCESS)
- return ret;
-
- /* Clock init */
- ret = ps7_config(ps7_clock_init_data);
- if (ret != PS7_INIT_SUCCESS)
- return ret;
-
- /* DDR init */
- ret = ps7_config(ps7_ddr_init_data);
- if (ret != PS7_INIT_SUCCESS)
- return ret;
-
- /* Peripherals init */
- ret = ps7_config(ps7_peripherals_init_data);
- if (ret != PS7_INIT_SUCCESS)
- return ret;
- return PS7_INIT_SUCCESS;
-}
-
-/* For delay calculation using global timer */
-
-/* start timer */
-void perf_start_clock(void)
-{
- *(volatile unsigned int *)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) | /* Timer Enable */
- (1 << 3) | /* Auto-increment */
- (0 << 8) /* Pre-scale */
- );
-}
-
-/* stop timer and reset timer count regs */
-void perf_reset_clock(void)
-{
- perf_disable_clock();
- *(volatile unsigned int *)SCU_GLOBAL_TIMER_COUNT_L32 = 0;
- *(volatile unsigned int *)SCU_GLOBAL_TIMER_COUNT_U32 = 0;
-}
-
-/* Compute mask for given delay in miliseconds*/
-int get_number_of_cycles_for_delay(unsigned int delay)
-{
- /* GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x) */
- return APU_FREQ * delay / (2 * 1000);
-}
-
-/* stop timer */
-void perf_disable_clock(void)
-{
- *(volatile unsigned int *)SCU_GLOBAL_TIMER_CONTROL = 0;
-}
-
-void perf_reset_and_start_timer(void)
-{
- perf_reset_clock();
- perf_start_clock();
-}
+++ /dev/null
-/*
- * Copyright (c) Xilinx, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*typedef unsigned int u32; */
-
-/** do we need to make this name more unique ? **/
-/*extern u32 ps7_init_data[]; */
-extern unsigned long *ps7_ddr_init_data;
-extern unsigned long *ps7_mio_init_data;
-extern unsigned long *ps7_pll_init_data;
-extern unsigned long *ps7_clock_init_data;
-extern unsigned long *ps7_peripherals_init_data;
-
-#define OPCODE_EXIT 0U
-#define OPCODE_CLEAR 1U
-#define OPCODE_WRITE 2U
-#define OPCODE_MASKWRITE 3U
-#define OPCODE_MASKPOLL 4U
-#define OPCODE_MASKDELAY 5U
-#define NEW_PS7_ERR_CODE 1
-
-/* Encode number of arguments in last nibble */
-#define EMIT_EXIT() ((OPCODE_EXIT << 4) | 0)
-#define EMIT_CLEAR(addr) ((OPCODE_CLEAR << 4) | 1) , addr
-#define EMIT_WRITE(addr, val) ((OPCODE_WRITE << 4) | 2) , addr, val
-#define EMIT_MASKWRITE(addr, mask, val) ((OPCODE_MASKWRITE << 4) | 3) , addr, mask, val
-#define EMIT_MASKPOLL(addr, mask) ((OPCODE_MASKPOLL << 4) | 2) , addr, mask
-#define EMIT_MASKDELAY(addr, mask) ((OPCODE_MASKDELAY << 4) | 2) , addr, mask
-
-/* Returns codes of PS7_Init */
-#define PS7_INIT_SUCCESS (0) /* 0 is success in good old C */
-#define PS7_INIT_CORRUPT (1) /* 1 the data is corrupted, and slcr reg are in corrupted state now */
-#define PS7_INIT_TIMEOUT (2) /* 2 when a poll operation timed out */
-#define PS7_POLL_FAILED_DDR_INIT (3) /* 3 when a poll operation timed out for ddr init */
-#define PS7_POLL_FAILED_DMA (4) /* 4 when a poll operation timed out for dma done bit */
-#define PS7_POLL_FAILED_PLL (5) /* 5 when a poll operation timed out for pll sequence init */
-
-/* Silicon Versions */
-#define PCW_SILICON_VERSION_1 0
-#define PCW_SILICON_VERSION_2 1
-#define PCW_SILICON_VERSION_3 2
-
-/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
-#define PS7_POST_CONFIG
-
-/* Freq of all peripherals */
-
-#define APU_FREQ 650000000
-#define DDR_FREQ 525000000
-#define DCI_FREQ 10096154
-#define QSPI_FREQ 200000000
-#define SMC_FREQ 10000000
-#define ENET0_FREQ 125000000
-#define ENET1_FREQ 10000000
-#define USB0_FREQ 60000000
-#define USB1_FREQ 60000000
-#define SDIO_FREQ 50000000
-#define UART_FREQ 100000000
-#define SPI_FREQ 10000000
-#define I2C_FREQ 108333336
-#define WDT_FREQ 108333336
-#define TTC_FREQ 50000000
-#define CAN_FREQ 10000000
-#define PCAP_FREQ 200000000
-#define TPIU_FREQ 200000000
-#define FPGA0_FREQ 100000000
-#define FPGA1_FREQ 142857132
-#define FPGA2_FREQ 200000000
-#define FPGA3_FREQ 50000000
-
-
-/* For delay calculation using global registers*/
-#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
-#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204
-#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208
-#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218
-
-int ps7_config(unsigned long *);
-int ps7_init(void);
-int ps7_post_config(void);
-int ps7_debug(void);
-char *getPS7MessageInfo(unsigned key);
-
-void perf_start_clock(void);
-void perf_disable_clock(void);
-void perf_reset_clock(void);
-void perf_reset_and_start_timer(void);
-int get_number_of_cycles_for_delay(unsigned int delay);
-#ifdef __cplusplus
-}
-#endif
--- /dev/null
+/******************************************************************************
+* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
+*
+* SPDX-License-Identifier: GPL-2.0+
+*
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file ps7_init_gpl.c
+*
+* This file is automatically generated
+*
+*****************************************************************************/
+
+#include "ps7_init_gpl.h"
+
+unsigned long ps7_pll_init_data_3_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: PLL SLCR REGISTERS
+ // .. .. START: ARM PLL INIT
+ // .. .. PLL_RES = 0x2
+ // .. .. ==> 0XF8000110[7:4] = 0x00000002U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
+ // .. .. PLL_CP = 0x2
+ // .. .. ==> 0XF8000110[11:8] = 0x00000002U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
+ // .. .. LOCK_CNT = 0xfa
+ // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
+ // .. .. .. START: UPDATE FB_DIV
+ // .. .. .. PLL_FDIV = 0x28
+ // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
+ // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
+ // .. .. .. FINISH: UPDATE FB_DIV
+ // .. .. .. START: BY PASS PLL
+ // .. .. .. PLL_BYPASS_FORCE = 1
+ // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
+ // .. .. .. FINISH: BY PASS PLL
+ // .. .. .. START: ASSERT RESET
+ // .. .. .. PLL_RESET = 1
+ // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
+ // .. .. .. FINISH: ASSERT RESET
+ // .. .. .. START: DEASSERT RESET
+ // .. .. .. PLL_RESET = 0
+ // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
+ // .. .. .. FINISH: DEASSERT RESET
+ // .. .. .. START: CHECK PLL STATUS
+ // .. .. .. ARM_PLL_LOCK = 1
+ // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ..
+ EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+ // .. .. .. FINISH: CHECK PLL STATUS
+ // .. .. .. START: REMOVE PLL BY PASS
+ // .. .. .. PLL_BYPASS_FORCE = 0
+ // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
+ // .. .. .. FINISH: REMOVE PLL BY PASS
+ // .. .. .. SRCSEL = 0x0
+ // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. .. .. DIVISOR = 0x2
+ // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
+ // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U
+ // .. .. .. CPU_6OR4XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
+ // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U
+ // .. .. .. CPU_3OR2XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
+ // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U
+ // .. .. .. CPU_2XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
+ // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U
+ // .. .. .. CPU_1XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
+ // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U
+ // .. .. .. CPU_PERI_CLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
+ // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
+ // .. .. FINISH: ARM PLL INIT
+ // .. .. START: DDR PLL INIT
+ // .. .. PLL_RES = 0x2
+ // .. .. ==> 0XF8000114[7:4] = 0x00000002U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
+ // .. .. PLL_CP = 0x2
+ // .. .. ==> 0XF8000114[11:8] = 0x00000002U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
+ // .. .. LOCK_CNT = 0x12c
+ // .. .. ==> 0XF8000114[21:12] = 0x0000012CU
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
+ // .. .. .. START: UPDATE FB_DIV
+ // .. .. .. PLL_FDIV = 0x20
+ // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
+ // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
+ // .. .. .. FINISH: UPDATE FB_DIV
+ // .. .. .. START: BY PASS PLL
+ // .. .. .. PLL_BYPASS_FORCE = 1
+ // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
+ // .. .. .. FINISH: BY PASS PLL
+ // .. .. .. START: ASSERT RESET
+ // .. .. .. PLL_RESET = 1
+ // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
+ // .. .. .. FINISH: ASSERT RESET
+ // .. .. .. START: DEASSERT RESET
+ // .. .. .. PLL_RESET = 0
+ // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
+ // .. .. .. FINISH: DEASSERT RESET
+ // .. .. .. START: CHECK PLL STATUS
+ // .. .. .. DDR_PLL_LOCK = 1
+ // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. .. ..
+ EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+ // .. .. .. FINISH: CHECK PLL STATUS
+ // .. .. .. START: REMOVE PLL BY PASS
+ // .. .. .. PLL_BYPASS_FORCE = 0
+ // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
+ // .. .. .. FINISH: REMOVE PLL BY PASS
+ // .. .. .. DDR_3XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. .. DDR_2XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. .. .. DDR_3XCLK_DIVISOR = 0x2
+ // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
+ // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U
+ // .. .. .. DDR_2XCLK_DIVISOR = 0x3
+ // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
+ // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
+ // .. .. FINISH: DDR PLL INIT
+ // .. .. START: IO PLL INIT
+ // .. .. PLL_RES = 0xc
+ // .. .. ==> 0XF8000118[7:4] = 0x0000000CU
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U
+ // .. .. PLL_CP = 0x2
+ // .. .. ==> 0XF8000118[11:8] = 0x00000002U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
+ // .. .. LOCK_CNT = 0x145
+ // .. .. ==> 0XF8000118[21:12] = 0x00000145U
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U),
+ // .. .. .. START: UPDATE FB_DIV
+ // .. .. .. PLL_FDIV = 0x1e
+ // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU
+ // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U),
+ // .. .. .. FINISH: UPDATE FB_DIV
+ // .. .. .. START: BY PASS PLL
+ // .. .. .. PLL_BYPASS_FORCE = 1
+ // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
+ // .. .. .. FINISH: BY PASS PLL
+ // .. .. .. START: ASSERT RESET
+ // .. .. .. PLL_RESET = 1
+ // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
+ // .. .. .. FINISH: ASSERT RESET
+ // .. .. .. START: DEASSERT RESET
+ // .. .. .. PLL_RESET = 0
+ // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
+ // .. .. .. FINISH: DEASSERT RESET
+ // .. .. .. START: CHECK PLL STATUS
+ // .. .. .. IO_PLL_LOCK = 1
+ // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. .. ..
+ EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+ // .. .. .. FINISH: CHECK PLL STATUS
+ // .. .. .. START: REMOVE PLL BY PASS
+ // .. .. .. PLL_BYPASS_FORCE = 0
+ // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
+ // .. .. .. FINISH: REMOVE PLL BY PASS
+ // .. .. FINISH: IO PLL INIT
+ // .. FINISH: PLL SLCR REGISTERS
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_clock_init_data_3_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: CLOCK CONTROL SLCR REGISTERS
+ // .. CLKACT = 0x1
+ // .. ==> 0XF8000128[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. DIVISOR0 = 0x23
+ // .. ==> 0XF8000128[13:8] = 0x00000023U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00002300U
+ // .. DIVISOR1 = 0x3
+ // .. ==> 0XF8000128[25:20] = 0x00000003U
+ // .. ==> MASK : 0x03F00000U VAL : 0x00300000U
+ // ..
+ EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U),
+ // .. CLKACT = 0x1
+ // .. ==> 0XF8000138[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000138[4:4] = 0x00000000U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
+ // .. CLKACT = 0x1
+ // .. ==> 0XF8000140[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000140[6:4] = 0x00000000U
+ // .. ==> MASK : 0x00000070U VAL : 0x00000000U
+ // .. DIVISOR = 0x8
+ // .. ==> 0XF8000140[13:8] = 0x00000008U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00000800U
+ // .. DIVISOR1 = 0x1
+ // .. ==> 0XF8000140[25:20] = 0x00000001U
+ // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
+ // ..
+ EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U),
+ // .. CLKACT = 0x1
+ // .. ==> 0XF800014C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF800014C[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR = 0x5
+ // .. ==> 0XF800014C[13:8] = 0x00000005U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00000500U
+ // ..
+ EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
+ // .. CLKACT0 = 0x1
+ // .. ==> 0XF8000150[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. CLKACT1 = 0x0
+ // .. ==> 0XF8000150[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000150[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR = 0x14
+ // .. ==> 0XF8000150[13:8] = 0x00000014U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
+ // ..
+ EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U),
+ // .. CLKACT0 = 0x0
+ // .. ==> 0XF8000154[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. CLKACT1 = 0x1
+ // .. ==> 0XF8000154[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000154[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR = 0x14
+ // .. ==> 0XF8000154[13:8] = 0x00000014U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
+ // ..
+ EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U),
+ // .. CLKACT = 0x1
+ // .. ==> 0XF8000168[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000168[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR = 0x5
+ // .. ==> 0XF8000168[13:8] = 0x00000005U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00000500U
+ // ..
+ EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000170[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR0 = 0xa
+ // .. ==> 0XF8000170[13:8] = 0x0000000AU
+ // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U
+ // .. DIVISOR1 = 0x1
+ // .. ==> 0XF8000170[25:20] = 0x00000001U
+ // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
+ // ..
+ EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00100A00U),
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000180[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR0 = 0xa
+ // .. ==> 0XF8000180[13:8] = 0x0000000AU
+ // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U
+ // .. DIVISOR1 = 0x1
+ // .. ==> 0XF8000180[25:20] = 0x00000001U
+ // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
+ // ..
+ EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00100A00U),
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000190[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR0 = 0x1e
+ // .. ==> 0XF8000190[13:8] = 0x0000001EU
+ // .. ==> MASK : 0x00003F00U VAL : 0x00001E00U
+ // .. DIVISOR1 = 0x1
+ // .. ==> 0XF8000190[25:20] = 0x00000001U
+ // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
+ // ..
+ EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101E00U),
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF80001A0[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR0 = 0x14
+ // .. ==> 0XF80001A0[13:8] = 0x00000014U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
+ // .. DIVISOR1 = 0x1
+ // .. ==> 0XF80001A0[25:20] = 0x00000001U
+ // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
+ // ..
+ EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U),
+ // .. CLK_621_TRUE = 0x1
+ // .. ==> 0XF80001C4[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // ..
+ EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
+ // .. DMA_CPU_2XCLKACT = 0x1
+ // .. ==> 0XF800012C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. USB0_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. USB1_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[3:3] = 0x00000001U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000008U
+ // .. GEM0_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[6:6] = 0x00000001U
+ // .. ==> MASK : 0x00000040U VAL : 0x00000040U
+ // .. GEM1_CPU_1XCLKACT = 0x0
+ // .. ==> 0XF800012C[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. SDI0_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[10:10] = 0x00000001U
+ // .. ==> MASK : 0x00000400U VAL : 0x00000400U
+ // .. SDI1_CPU_1XCLKACT = 0x0
+ // .. ==> 0XF800012C[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. SPI0_CPU_1XCLKACT = 0x0
+ // .. ==> 0XF800012C[14:14] = 0x00000000U
+ // .. ==> MASK : 0x00004000U VAL : 0x00000000U
+ // .. SPI1_CPU_1XCLKACT = 0x0
+ // .. ==> 0XF800012C[15:15] = 0x00000000U
+ // .. ==> MASK : 0x00008000U VAL : 0x00000000U
+ // .. CAN0_CPU_1XCLKACT = 0x0
+ // .. ==> 0XF800012C[16:16] = 0x00000000U
+ // .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. CAN1_CPU_1XCLKACT = 0x0
+ // .. ==> 0XF800012C[17:17] = 0x00000000U
+ // .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. I2C0_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[18:18] = 0x00000001U
+ // .. ==> MASK : 0x00040000U VAL : 0x00040000U
+ // .. I2C1_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[19:19] = 0x00000001U
+ // .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // .. UART0_CPU_1XCLKACT = 0x0
+ // .. ==> 0XF800012C[20:20] = 0x00000000U
+ // .. ==> MASK : 0x00100000U VAL : 0x00000000U
+ // .. UART1_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[21:21] = 0x00000001U
+ // .. ==> MASK : 0x00200000U VAL : 0x00200000U
+ // .. GPIO_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[22:22] = 0x00000001U
+ // .. ==> MASK : 0x00400000U VAL : 0x00400000U
+ // .. LQSPI_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[23:23] = 0x00000001U
+ // .. ==> MASK : 0x00800000U VAL : 0x00800000U
+ // .. SMC_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[24:24] = 0x00000001U
+ // .. ==> MASK : 0x01000000U VAL : 0x01000000U
+ // ..
+ EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC044DU),
+ // .. FINISH: CLOCK CONTROL SLCR REGISTERS
+ // .. START: THIS SHOULD BE BLANK
+ // .. FINISH: THIS SHOULD BE BLANK
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_ddr_init_data_3_0[] = {
+ // START: top
+ // .. START: DDR INITIALIZATION
+ // .. .. START: LOCK DDR
+ // .. .. reg_ddrc_soft_rstb = 0
+ // .. .. ==> 0XF8006000[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_powerdown_en = 0x0
+ // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_ddrc_data_bus_width = 0x0
+ // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U
+ // .. .. reg_ddrc_burst8_refresh = 0x0
+ // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U
+ // .. .. reg_ddrc_rdwr_idle_gap = 0x1
+ // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+ // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U
+ // .. .. reg_ddrc_dis_rd_bypass = 0x0
+ // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+ // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_act_bypass = 0x0
+ // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_auto_refresh = 0x0
+ // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
+ // .. .. FINISH: LOCK DDR
+ // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81
+ // .. .. ==> 0XF8006004[11:0] = 0x00000081U
+ // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U
+ // .. .. reserved_reg_ddrc_active_ranks = 0x1
+ // .. .. ==> 0XF8006004[13:12] = 0x00000001U
+ // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U
+ // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
+ // .. .. ==> 0XF8006004[18:14] = 0x00000000U
+ // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU ,0x00001081U),
+ // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
+ // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU
+ // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
+ // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
+ // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U
+ // .. .. reg_ddrc_hpr_xact_run_length = 0xf
+ // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
+ // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
+ // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
+ // .. .. ==> 0XF800600C[10:0] = 0x00000001U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U
+ // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
+ // .. .. ==> 0XF800600C[21:11] = 0x00000002U
+ // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U
+ // .. .. reg_ddrc_lpr_xact_run_length = 0x8
+ // .. .. ==> 0XF800600C[25:22] = 0x00000008U
+ // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
+ // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
+ // .. .. ==> 0XF8006010[10:0] = 0x00000001U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U
+ // .. .. reg_ddrc_w_xact_run_length = 0x8
+ // .. .. ==> 0XF8006010[14:11] = 0x00000008U
+ // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U
+ // .. .. reg_ddrc_w_max_starve_x32 = 0x2
+ // .. .. ==> 0XF8006010[25:15] = 0x00000002U
+ // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
+ // .. .. reg_ddrc_t_rc = 0x1a
+ // .. .. ==> 0XF8006014[5:0] = 0x0000001AU
+ // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001AU
+ // .. .. reg_ddrc_t_rfc_min = 0xa0
+ // .. .. ==> 0XF8006014[13:6] = 0x000000A0U
+ // .. .. ==> MASK : 0x00003FC0U VAL : 0x00002800U
+ // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
+ // .. .. ==> 0XF8006014[20:14] = 0x00000010U
+ // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281AU),
+ // .. .. reg_ddrc_wr2pre = 0x12
+ // .. .. ==> 0XF8006018[4:0] = 0x00000012U
+ // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U
+ // .. .. reg_ddrc_powerdown_to_x32 = 0x6
+ // .. .. ==> 0XF8006018[9:5] = 0x00000006U
+ // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U
+ // .. .. reg_ddrc_t_faw = 0x16
+ // .. .. ==> 0XF8006018[15:10] = 0x00000016U
+ // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005800U
+ // .. .. reg_ddrc_t_ras_max = 0x24
+ // .. .. ==> 0XF8006018[21:16] = 0x00000024U
+ // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U
+ // .. .. reg_ddrc_t_ras_min = 0x13
+ // .. .. ==> 0XF8006018[26:22] = 0x00000013U
+ // .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U
+ // .. .. reg_ddrc_t_cke = 0x4
+ // .. .. ==> 0XF8006018[31:28] = 0x00000004U
+ // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D2U),
+ // .. .. reg_ddrc_write_latency = 0x5
+ // .. .. ==> 0XF800601C[4:0] = 0x00000005U
+ // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U
+ // .. .. reg_ddrc_rd2wr = 0x7
+ // .. .. ==> 0XF800601C[9:5] = 0x00000007U
+ // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U
+ // .. .. reg_ddrc_wr2rd = 0xe
+ // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
+ // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U
+ // .. .. reg_ddrc_t_xp = 0x4
+ // .. .. ==> 0XF800601C[19:15] = 0x00000004U
+ // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U
+ // .. .. reg_ddrc_pad_pd = 0x0
+ // .. .. ==> 0XF800601C[22:20] = 0x00000000U
+ // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U
+ // .. .. reg_ddrc_rd2pre = 0x4
+ // .. .. ==> 0XF800601C[27:23] = 0x00000004U
+ // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U
+ // .. .. reg_ddrc_t_rcd = 0x7
+ // .. .. ==> 0XF800601C[31:28] = 0x00000007U
+ // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
+ // .. .. reg_ddrc_t_ccd = 0x4
+ // .. .. ==> 0XF8006020[4:2] = 0x00000004U
+ // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U
+ // .. .. reg_ddrc_t_rrd = 0x6
+ // .. .. ==> 0XF8006020[7:5] = 0x00000006U
+ // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U
+ // .. .. reg_ddrc_refresh_margin = 0x2
+ // .. .. ==> 0XF8006020[11:8] = 0x00000002U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
+ // .. .. reg_ddrc_t_rp = 0x7
+ // .. .. ==> 0XF8006020[15:12] = 0x00000007U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U
+ // .. .. reg_ddrc_refresh_to_x32 = 0x8
+ // .. .. ==> 0XF8006020[20:16] = 0x00000008U
+ // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U
+ // .. .. reg_ddrc_mobile = 0x0
+ // .. .. ==> 0XF8006020[22:22] = 0x00000000U
+ // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U
+ // .. .. reg_ddrc_en_dfi_dram_clk_disable = 0x0
+ // .. .. ==> 0XF8006020[23:23] = 0x00000000U
+ // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U
+ // .. .. reg_ddrc_read_latency = 0x7
+ // .. .. ==> 0XF8006020[28:24] = 0x00000007U
+ // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U
+ // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
+ // .. .. ==> 0XF8006020[29:29] = 0x00000001U
+ // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U
+ // .. .. reg_ddrc_dis_pad_pd = 0x0
+ // .. .. ==> 0XF8006020[30:30] = 0x00000000U
+ // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU ,0x270872D0U),
+ // .. .. reg_ddrc_en_2t_timing_mode = 0x0
+ // .. .. ==> 0XF8006024[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_prefer_write = 0x0
+ // .. .. ==> 0XF8006024[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr_wr = 0x0
+ // .. .. ==> 0XF8006024[6:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr_addr = 0x0
+ // .. .. ==> 0XF8006024[8:7] = 0x00000000U
+ // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr_data = 0x0
+ // .. .. ==> 0XF8006024[24:9] = 0x00000000U
+ // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U
+ // .. .. ddrc_reg_mr_wr_busy = 0x0
+ // .. .. ==> 0XF8006024[25:25] = 0x00000000U
+ // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr_type = 0x0
+ // .. .. ==> 0XF8006024[26:26] = 0x00000000U
+ // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr_rdata_valid = 0x0
+ // .. .. ==> 0XF8006024[27:27] = 0x00000000U
+ // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U ,0x00000000U),
+ // .. .. reg_ddrc_final_wait_x32 = 0x7
+ // .. .. ==> 0XF8006028[6:0] = 0x00000007U
+ // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U
+ // .. .. reg_ddrc_pre_ocd_x32 = 0x0
+ // .. .. ==> 0XF8006028[10:7] = 0x00000000U
+ // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U
+ // .. .. reg_ddrc_t_mrd = 0x4
+ // .. .. ==> 0XF8006028[13:11] = 0x00000004U
+ // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
+ // .. .. reg_ddrc_emr2 = 0x8
+ // .. .. ==> 0XF800602C[15:0] = 0x00000008U
+ // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U
+ // .. .. reg_ddrc_emr3 = 0x0
+ // .. .. ==> 0XF800602C[31:16] = 0x00000000U
+ // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
+ // .. .. reg_ddrc_mr = 0x930
+ // .. .. ==> 0XF8006030[15:0] = 0x00000930U
+ // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U
+ // .. .. reg_ddrc_emr = 0x4
+ // .. .. ==> 0XF8006030[31:16] = 0x00000004U
+ // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
+ // .. .. reg_ddrc_burst_rdwr = 0x4
+ // .. .. ==> 0XF8006034[3:0] = 0x00000004U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U
+ // .. .. reg_ddrc_pre_cke_x1024 = 0x105
+ // .. .. ==> 0XF8006034[13:4] = 0x00000105U
+ // .. .. ==> MASK : 0x00003FF0U VAL : 0x00001050U
+ // .. .. reg_ddrc_post_cke_x1024 = 0x1
+ // .. .. ==> 0XF8006034[25:16] = 0x00000001U
+ // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U
+ // .. .. reg_ddrc_burstchop = 0x0
+ // .. .. ==> 0XF8006034[28:28] = 0x00000000U
+ // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U),
+ // .. .. reg_ddrc_force_low_pri_n = 0x0
+ // .. .. ==> 0XF8006038[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_dq = 0x0
+ // .. .. ==> 0XF8006038[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006038, 0x00000003U ,0x00000000U),
+ // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
+ // .. .. ==> 0XF800603C[3:0] = 0x00000007U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U
+ // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
+ // .. .. ==> 0XF800603C[7:4] = 0x00000007U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U
+ // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
+ // .. .. ==> 0XF800603C[11:8] = 0x00000007U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U
+ // .. .. reg_ddrc_addrmap_col_b5 = 0x0
+ // .. .. ==> 0XF800603C[15:12] = 0x00000000U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b6 = 0x0
+ // .. .. ==> 0XF800603C[19:16] = 0x00000000U
+ // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
+ // .. .. reg_ddrc_addrmap_col_b2 = 0x0
+ // .. .. ==> 0XF8006040[3:0] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b3 = 0x0
+ // .. .. ==> 0XF8006040[7:4] = 0x00000000U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b4 = 0x0
+ // .. .. ==> 0XF8006040[11:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b7 = 0x0
+ // .. .. ==> 0XF8006040[15:12] = 0x00000000U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b8 = 0x0
+ // .. .. ==> 0XF8006040[19:16] = 0x00000000U
+ // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b9 = 0xf
+ // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
+ // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U
+ // .. .. reg_ddrc_addrmap_col_b10 = 0xf
+ // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
+ // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U
+ // .. .. reg_ddrc_addrmap_col_b11 = 0xf
+ // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
+ // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
+ // .. .. reg_ddrc_addrmap_row_b0 = 0x6
+ // .. .. ==> 0XF8006044[3:0] = 0x00000006U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U
+ // .. .. reg_ddrc_addrmap_row_b1 = 0x6
+ // .. .. ==> 0XF8006044[7:4] = 0x00000006U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U
+ // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
+ // .. .. ==> 0XF8006044[11:8] = 0x00000006U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U
+ // .. .. reg_ddrc_addrmap_row_b12 = 0x6
+ // .. .. ==> 0XF8006044[15:12] = 0x00000006U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U
+ // .. .. reg_ddrc_addrmap_row_b13 = 0x6
+ // .. .. ==> 0XF8006044[19:16] = 0x00000006U
+ // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U
+ // .. .. reg_ddrc_addrmap_row_b14 = 0x6
+ // .. .. ==> 0XF8006044[23:20] = 0x00000006U
+ // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U
+ // .. .. reg_ddrc_addrmap_row_b15 = 0xf
+ // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
+ // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U),
+ // .. .. reg_phy_rd_local_odt = 0x0
+ // .. .. ==> 0XF8006048[13:12] = 0x00000000U
+ // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U
+ // .. .. reg_phy_wr_local_odt = 0x3
+ // .. .. ==> 0XF8006048[15:14] = 0x00000003U
+ // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U
+ // .. .. reg_phy_idle_local_odt = 0x3
+ // .. .. ==> 0XF8006048[17:16] = 0x00000003U
+ // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006048, 0x0003F000U ,0x0003C000U),
+ // .. .. reg_phy_rd_cmd_to_data = 0x0
+ // .. .. ==> 0XF8006050[3:0] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
+ // .. .. reg_phy_wr_cmd_to_data = 0x0
+ // .. .. ==> 0XF8006050[7:4] = 0x00000000U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. .. reg_phy_rdc_we_to_re_delay = 0x8
+ // .. .. ==> 0XF8006050[11:8] = 0x00000008U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U
+ // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
+ // .. .. ==> 0XF8006050[15:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
+ // .. .. reg_phy_use_fixed_re = 0x1
+ // .. .. ==> 0XF8006050[16:16] = 0x00000001U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U
+ // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
+ // .. .. ==> 0XF8006050[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
+ // .. .. ==> 0XF8006050[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_phy_clk_stall_level = 0x0
+ // .. .. ==> 0XF8006050[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
+ // .. .. ==> 0XF8006050[27:24] = 0x00000007U
+ // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U
+ // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
+ // .. .. ==> 0XF8006050[31:28] = 0x00000007U
+ // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
+ // .. .. reg_ddrc_dis_dll_calib = 0x0
+ // .. .. ==> 0XF8006058[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006058, 0x00010000U ,0x00000000U),
+ // .. .. reg_ddrc_rd_odt_delay = 0x3
+ // .. .. ==> 0XF800605C[3:0] = 0x00000003U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U
+ // .. .. reg_ddrc_wr_odt_delay = 0x0
+ // .. .. ==> 0XF800605C[7:4] = 0x00000000U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. .. reg_ddrc_rd_odt_hold = 0x0
+ // .. .. ==> 0XF800605C[11:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U
+ // .. .. reg_ddrc_wr_odt_hold = 0x5
+ // .. .. ==> 0XF800605C[15:12] = 0x00000005U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
+ // .. .. reg_ddrc_pageclose = 0x0
+ // .. .. ==> 0XF8006060[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_lpr_num_entries = 0x1f
+ // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
+ // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU
+ // .. .. reg_ddrc_auto_pre_en = 0x0
+ // .. .. ==> 0XF8006060[7:7] = 0x00000000U
+ // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. .. reg_ddrc_refresh_update_level = 0x0
+ // .. .. ==> 0XF8006060[8:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_wc = 0x0
+ // .. .. ==> 0XF8006060[9:9] = 0x00000000U
+ // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_collision_page_opt = 0x0
+ // .. .. ==> 0XF8006060[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_ddrc_selfref_en = 0x0
+ // .. .. ==> 0XF8006060[12:12] = 0x00000000U
+ // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
+ // .. .. reg_ddrc_go2critical_hysteresis = 0x0
+ // .. .. ==> 0XF8006064[12:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U
+ // .. .. reg_arb_go2critical_en = 0x1
+ // .. .. ==> 0XF8006064[17:17] = 0x00000001U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
+ // .. .. reg_ddrc_wrlvl_ww = 0x41
+ // .. .. ==> 0XF8006068[7:0] = 0x00000041U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U
+ // .. .. reg_ddrc_rdlvl_rr = 0x41
+ // .. .. ==> 0XF8006068[15:8] = 0x00000041U
+ // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U
+ // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
+ // .. .. ==> 0XF8006068[25:16] = 0x00000028U
+ // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
+ // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
+ // .. .. ==> 0XF800606C[7:0] = 0x00000010U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U
+ // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
+ // .. .. ==> 0XF800606C[15:8] = 0x00000016U
+ // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U
+ // .. ..
+ EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
+ // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1
+ // .. .. ==> 0XF8006078[3:0] = 0x00000001U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U
+ // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1
+ // .. .. ==> 0XF8006078[7:4] = 0x00000001U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U
+ // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1
+ // .. .. ==> 0XF8006078[11:8] = 0x00000001U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U
+ // .. .. reg_ddrc_t_cksre = 0x6
+ // .. .. ==> 0XF8006078[15:12] = 0x00000006U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U
+ // .. .. reg_ddrc_t_cksrx = 0x6
+ // .. .. ==> 0XF8006078[19:16] = 0x00000006U
+ // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U
+ // .. .. reg_ddrc_t_ckesr = 0x4
+ // .. .. ==> 0XF8006078[25:20] = 0x00000004U
+ // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U),
+ // .. .. reg_ddrc_t_ckpde = 0x2
+ // .. .. ==> 0XF800607C[3:0] = 0x00000002U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U
+ // .. .. reg_ddrc_t_ckpdx = 0x2
+ // .. .. ==> 0XF800607C[7:4] = 0x00000002U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
+ // .. .. reg_ddrc_t_ckdpde = 0x2
+ // .. .. ==> 0XF800607C[11:8] = 0x00000002U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
+ // .. .. reg_ddrc_t_ckdpdx = 0x2
+ // .. .. ==> 0XF800607C[15:12] = 0x00000002U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U
+ // .. .. reg_ddrc_t_ckcsx = 0x3
+ // .. .. ==> 0XF800607C[19:16] = 0x00000003U
+ // .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U),
+ // .. .. reg_ddrc_dis_auto_zq = 0x0
+ // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_ddr3 = 0x1
+ // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. .. reg_ddrc_t_mod = 0x200
+ // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
+ // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U
+ // .. .. reg_ddrc_t_zq_long_nop = 0x200
+ // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U
+ // .. .. reg_ddrc_t_zq_short_nop = 0x40
+ // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
+ // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
+ // .. .. t_zq_short_interval_x1024 = 0xcb73
+ // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U
+ // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U
+ // .. .. dram_rstn_x1024 = 0x69
+ // .. .. ==> 0XF80060A8[27:20] = 0x00000069U
+ // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
+ // .. .. deeppowerdown_en = 0x0
+ // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. deeppowerdown_to_x1024 = 0xff
+ // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
+ // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU
+ // .. ..
+ EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
+ // .. .. dfi_wrlvl_max_x1024 = 0xfff
+ // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
+ // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU
+ // .. .. dfi_rdlvl_max_x1024 = 0xfff
+ // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
+ // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U
+ // .. .. ddrc_reg_twrlvl_max_error = 0x0
+ // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
+ // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U
+ // .. .. ddrc_reg_trdlvl_max_error = 0x0
+ // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
+ // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dfi_wr_level_en = 0x1
+ // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
+ // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U
+ // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
+ // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
+ // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U
+ // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
+ // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
+ // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
+ // .. .. reg_ddrc_skip_ocd = 0x1
+ // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
+ // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060B4, 0x00000200U ,0x00000200U),
+ // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
+ // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
+ // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U
+ // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
+ // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
+ // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U
+ // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
+ // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
+ // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
+ // .. .. START: RESET ECC ERROR
+ // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1
+ // .. .. ==> 0XF80060C4[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. Clear_Correctable_DRAM_ECC_error = 1
+ // .. .. ==> 0XF80060C4[1:1] = 0x00000001U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U),
+ // .. .. FINISH: RESET ECC ERROR
+ // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
+ // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
+ // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
+ // .. .. CORR_ECC_LOG_VALID = 0x0
+ // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. ECC_CORRECTED_BIT_NUM = 0x0
+ // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
+ // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
+ // .. .. UNCORR_ECC_LOG_VALID = 0x0
+ // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
+ // .. .. STAT_NUM_CORR_ERR = 0x0
+ // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
+ // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U
+ // .. .. STAT_NUM_UNCORR_ERR = 0x0
+ // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
+ // .. .. reg_ddrc_ecc_mode = 0x0
+ // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_scrub = 0x1
+ // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
+ // .. .. reg_phy_dif_on = 0x0
+ // .. .. ==> 0XF8006114[3:0] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
+ // .. .. reg_phy_dif_off = 0x0
+ // .. .. ==> 0XF8006114[7:4] = 0x00000000U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
+ // .. .. reg_phy_data_slice_in_use = 0x1
+ // .. .. ==> 0XF8006118[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_phy_rdlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006118[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006118[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_wrlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006118[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_bist_shift_dq = 0x0
+ // .. .. ==> 0XF8006118[14:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
+ // .. .. reg_phy_bist_err_clr = 0x0
+ // .. .. ==> 0XF8006118[23:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
+ // .. .. reg_phy_dq_offset = 0x40
+ // .. .. ==> 0XF8006118[30:24] = 0x00000040U
+ // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU ,0x40000001U),
+ // .. .. reg_phy_data_slice_in_use = 0x1
+ // .. .. ==> 0XF800611C[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_phy_rdlvl_inc_mode = 0x0
+ // .. .. ==> 0XF800611C[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_inc_mode = 0x0
+ // .. .. ==> 0XF800611C[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_wrlvl_inc_mode = 0x0
+ // .. .. ==> 0XF800611C[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_bist_shift_dq = 0x0
+ // .. .. ==> 0XF800611C[14:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
+ // .. .. reg_phy_bist_err_clr = 0x0
+ // .. .. ==> 0XF800611C[23:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
+ // .. .. reg_phy_dq_offset = 0x40
+ // .. .. ==> 0XF800611C[30:24] = 0x00000040U
+ // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU ,0x40000001U),
+ // .. .. reg_phy_data_slice_in_use = 0x1
+ // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_phy_rdlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_wrlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_bist_shift_dq = 0x0
+ // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
+ // .. .. reg_phy_bist_err_clr = 0x0
+ // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
+ // .. .. reg_phy_dq_offset = 0x40
+ // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+ // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU ,0x40000001U),
+ // .. .. reg_phy_data_slice_in_use = 0x1
+ // .. .. ==> 0XF8006124[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_phy_rdlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006124[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006124[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_wrlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006124[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_bist_shift_dq = 0x0
+ // .. .. ==> 0XF8006124[14:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
+ // .. .. reg_phy_bist_err_clr = 0x0
+ // .. .. ==> 0XF8006124[23:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
+ // .. .. reg_phy_dq_offset = 0x40
+ // .. .. ==> 0XF8006124[30:24] = 0x00000040U
+ // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU ,0x40000001U),
+ // .. .. reg_phy_wrlvl_init_ratio = 0x0
+ // .. .. ==> 0XF800612C[9:0] = 0x00000000U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_init_ratio = 0xb0
+ // .. .. ==> 0XF800612C[19:10] = 0x000000B0U
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002C000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0002C000U),
+ // .. .. reg_phy_wrlvl_init_ratio = 0x0
+ // .. .. ==> 0XF8006130[9:0] = 0x00000000U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_init_ratio = 0xb1
+ // .. .. ==> 0XF8006130[19:10] = 0x000000B1U
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002C400U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x0002C400U),
+ // .. .. reg_phy_wrlvl_init_ratio = 0x3
+ // .. .. ==> 0XF8006134[9:0] = 0x00000003U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000003U
+ // .. .. reg_phy_gatelvl_init_ratio = 0xbc
+ // .. .. ==> 0XF8006134[19:10] = 0x000000BCU
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002F000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0002F003U),
+ // .. .. reg_phy_wrlvl_init_ratio = 0x3
+ // .. .. ==> 0XF8006138[9:0] = 0x00000003U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000003U
+ // .. .. reg_phy_gatelvl_init_ratio = 0xbb
+ // .. .. ==> 0XF8006138[19:10] = 0x000000BBU
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002EC00U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0002EC03U),
+ // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+ // .. .. ==> 0XF8006140[9:0] = 0x00000035U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
+ // .. .. reg_phy_rd_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006140[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006140[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
+ // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+ // .. .. ==> 0XF8006144[9:0] = 0x00000035U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
+ // .. .. reg_phy_rd_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006144[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006144[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
+ // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+ // .. .. ==> 0XF8006148[9:0] = 0x00000035U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
+ // .. .. reg_phy_rd_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006148[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006148[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
+ // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+ // .. .. ==> 0XF800614C[9:0] = 0x00000035U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
+ // .. .. reg_phy_rd_dqs_slave_force = 0x0
+ // .. .. ==> 0XF800614C[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF800614C[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
+ // .. .. reg_phy_wr_dqs_slave_ratio = 0x77
+ // .. .. ==> 0XF8006154[9:0] = 0x00000077U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000077U
+ // .. .. reg_phy_wr_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006154[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006154[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000077U),
+ // .. .. reg_phy_wr_dqs_slave_ratio = 0x77
+ // .. .. ==> 0XF8006158[9:0] = 0x00000077U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000077U
+ // .. .. reg_phy_wr_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006158[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006158[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000077U),
+ // .. .. reg_phy_wr_dqs_slave_ratio = 0x83
+ // .. .. ==> 0XF800615C[9:0] = 0x00000083U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000083U
+ // .. .. reg_phy_wr_dqs_slave_force = 0x0
+ // .. .. ==> 0XF800615C[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF800615C[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000083U),
+ // .. .. reg_phy_wr_dqs_slave_ratio = 0x83
+ // .. .. ==> 0XF8006160[9:0] = 0x00000083U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000083U
+ // .. .. reg_phy_wr_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006160[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006160[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000083U),
+ // .. .. reg_phy_fifo_we_slave_ratio = 0x105
+ // .. .. ==> 0XF8006168[10:0] = 0x00000105U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000105U
+ // .. .. reg_phy_fifo_we_in_force = 0x0
+ // .. .. ==> 0XF8006168[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. reg_phy_fifo_we_in_delay = 0x0
+ // .. .. ==> 0XF8006168[20:12] = 0x00000000U
+ // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000105U),
+ // .. .. reg_phy_fifo_we_slave_ratio = 0x106
+ // .. .. ==> 0XF800616C[10:0] = 0x00000106U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000106U
+ // .. .. reg_phy_fifo_we_in_force = 0x0
+ // .. .. ==> 0XF800616C[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. reg_phy_fifo_we_in_delay = 0x0
+ // .. .. ==> 0XF800616C[20:12] = 0x00000000U
+ // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x00000106U),
+ // .. .. reg_phy_fifo_we_slave_ratio = 0x111
+ // .. .. ==> 0XF8006170[10:0] = 0x00000111U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000111U
+ // .. .. reg_phy_fifo_we_in_force = 0x0
+ // .. .. ==> 0XF8006170[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. reg_phy_fifo_we_in_delay = 0x0
+ // .. .. ==> 0XF8006170[20:12] = 0x00000000U
+ // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000111U),
+ // .. .. reg_phy_fifo_we_slave_ratio = 0x110
+ // .. .. ==> 0XF8006174[10:0] = 0x00000110U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000110U
+ // .. .. reg_phy_fifo_we_in_force = 0x0
+ // .. .. ==> 0XF8006174[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. reg_phy_fifo_we_in_delay = 0x0
+ // .. .. ==> 0XF8006174[20:12] = 0x00000000U
+ // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000110U),
+ // .. .. reg_phy_wr_data_slave_ratio = 0xb7
+ // .. .. ==> 0XF800617C[9:0] = 0x000000B7U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000B7U
+ // .. .. reg_phy_wr_data_slave_force = 0x0
+ // .. .. ==> 0XF800617C[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_data_slave_delay = 0x0
+ // .. .. ==> 0XF800617C[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000B7U),
+ // .. .. reg_phy_wr_data_slave_ratio = 0xb7
+ // .. .. ==> 0XF8006180[9:0] = 0x000000B7U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000B7U
+ // .. .. reg_phy_wr_data_slave_force = 0x0
+ // .. .. ==> 0XF8006180[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_data_slave_delay = 0x0
+ // .. .. ==> 0XF8006180[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000B7U),
+ // .. .. reg_phy_wr_data_slave_ratio = 0xc3
+ // .. .. ==> 0XF8006184[9:0] = 0x000000C3U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C3U
+ // .. .. reg_phy_wr_data_slave_force = 0x0
+ // .. .. ==> 0XF8006184[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_data_slave_delay = 0x0
+ // .. .. ==> 0XF8006184[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C3U),
+ // .. .. reg_phy_wr_data_slave_ratio = 0xc3
+ // .. .. ==> 0XF8006188[9:0] = 0x000000C3U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C3U
+ // .. .. reg_phy_wr_data_slave_force = 0x0
+ // .. .. ==> 0XF8006188[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_data_slave_delay = 0x0
+ // .. .. ==> 0XF8006188[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C3U),
+ // .. .. reg_phy_bl2 = 0x0
+ // .. .. ==> 0XF8006190[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_at_spd_atpg = 0x0
+ // .. .. ==> 0XF8006190[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_bist_enable = 0x0
+ // .. .. ==> 0XF8006190[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_bist_force_err = 0x0
+ // .. .. ==> 0XF8006190[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reg_phy_bist_mode = 0x0
+ // .. .. ==> 0XF8006190[6:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U
+ // .. .. reg_phy_invert_clkout = 0x1
+ // .. .. ==> 0XF8006190[7:7] = 0x00000001U
+ // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. .. reg_phy_sel_logic = 0x0
+ // .. .. ==> 0XF8006190[9:9] = 0x00000000U
+ // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U
+ // .. .. reg_phy_ctrl_slave_ratio = 0x100
+ // .. .. ==> 0XF8006190[19:10] = 0x00000100U
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U
+ // .. .. reg_phy_ctrl_slave_force = 0x0
+ // .. .. ==> 0XF8006190[20:20] = 0x00000000U
+ // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U
+ // .. .. reg_phy_ctrl_slave_delay = 0x0
+ // .. .. ==> 0XF8006190[27:21] = 0x00000000U
+ // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U
+ // .. .. reg_phy_lpddr = 0x0
+ // .. .. ==> 0XF8006190[29:29] = 0x00000000U
+ // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U
+ // .. .. reg_phy_cmd_latency = 0x0
+ // .. .. ==> 0XF8006190[30:30] = 0x00000000U
+ // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU ,0x00040080U),
+ // .. .. reg_phy_wr_rl_delay = 0x2
+ // .. .. ==> 0XF8006194[4:0] = 0x00000002U
+ // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U
+ // .. .. reg_phy_rd_rl_delay = 0x4
+ // .. .. ==> 0XF8006194[9:5] = 0x00000004U
+ // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U
+ // .. .. reg_phy_dll_lock_diff = 0xf
+ // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
+ // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U
+ // .. .. reg_phy_use_wr_level = 0x1
+ // .. .. ==> 0XF8006194[14:14] = 0x00000001U
+ // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U
+ // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
+ // .. .. ==> 0XF8006194[15:15] = 0x00000001U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U
+ // .. .. reg_phy_use_rd_data_eye_level = 0x1
+ // .. .. ==> 0XF8006194[16:16] = 0x00000001U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U
+ // .. .. reg_phy_dis_calib_rst = 0x0
+ // .. .. ==> 0XF8006194[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_phy_ctrl_slave_delay = 0x0
+ // .. .. ==> 0XF8006194[19:18] = 0x00000000U
+ // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
+ // .. .. reg_arb_page_addr_mask = 0x0
+ // .. .. ==> 0XF8006204[31:0] = 0x00000000U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
+ // .. .. reg_arb_pri_wr_portn = 0x3ff
+ // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_wr_portn = 0x0
+ // .. .. ==> 0XF8006208[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+ // .. .. ==> 0XF8006208[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+ // .. .. ==> 0XF8006208[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006208, 0x000703FFU ,0x000003FFU),
+ // .. .. reg_arb_pri_wr_portn = 0x3ff
+ // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_wr_portn = 0x0
+ // .. .. ==> 0XF800620C[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+ // .. .. ==> 0XF800620C[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+ // .. .. ==> 0XF800620C[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800620C, 0x000703FFU ,0x000003FFU),
+ // .. .. reg_arb_pri_wr_portn = 0x3ff
+ // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_wr_portn = 0x0
+ // .. .. ==> 0XF8006210[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+ // .. .. ==> 0XF8006210[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+ // .. .. ==> 0XF8006210[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006210, 0x000703FFU ,0x000003FFU),
+ // .. .. reg_arb_pri_wr_portn = 0x3ff
+ // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_wr_portn = 0x0
+ // .. .. ==> 0XF8006214[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+ // .. .. ==> 0XF8006214[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+ // .. .. ==> 0XF8006214[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006214, 0x000703FFU ,0x000003FFU),
+ // .. .. reg_arb_pri_rd_portn = 0x3ff
+ // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_rd_portn = 0x0
+ // .. .. ==> 0XF8006218[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+ // .. .. ==> 0XF8006218[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+ // .. .. ==> 0XF8006218[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_set_hpr_rd_portn = 0x0
+ // .. .. ==> 0XF8006218[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
+ // .. .. reg_arb_pri_rd_portn = 0x3ff
+ // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_rd_portn = 0x0
+ // .. .. ==> 0XF800621C[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+ // .. .. ==> 0XF800621C[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+ // .. .. ==> 0XF800621C[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_set_hpr_rd_portn = 0x0
+ // .. .. ==> 0XF800621C[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
+ // .. .. reg_arb_pri_rd_portn = 0x3ff
+ // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_rd_portn = 0x0
+ // .. .. ==> 0XF8006220[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+ // .. .. ==> 0XF8006220[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+ // .. .. ==> 0XF8006220[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_set_hpr_rd_portn = 0x0
+ // .. .. ==> 0XF8006220[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
+ // .. .. reg_arb_pri_rd_portn = 0x3ff
+ // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_rd_portn = 0x0
+ // .. .. ==> 0XF8006224[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+ // .. .. ==> 0XF8006224[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+ // .. .. ==> 0XF8006224[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_set_hpr_rd_portn = 0x0
+ // .. .. ==> 0XF8006224[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
+ // .. .. reg_ddrc_lpddr2 = 0x0
+ // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_derate_enable = 0x0
+ // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr4_margin = 0x0
+ // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U ,0x00000000U),
+ // .. .. reg_ddrc_mr4_read_interval = 0x0
+ // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
+ // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
+ // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U
+ // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
+ // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
+ // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U
+ // .. .. reg_ddrc_t_mrw = 0x5
+ // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
+ // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8
+ // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U
+ // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
+ // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
+ // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U
+ // .. ..
+ EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
+ // .. .. START: POLL ON DCI STATUS
+ // .. .. DONE = 1
+ // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
+ // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U
+ // .. ..
+ EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+ // .. .. FINISH: POLL ON DCI STATUS
+ // .. .. START: UNLOCK DDR
+ // .. .. reg_ddrc_soft_rstb = 0x1
+ // .. .. ==> 0XF8006000[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_ddrc_powerdown_en = 0x0
+ // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_ddrc_data_bus_width = 0x0
+ // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U
+ // .. .. reg_ddrc_burst8_refresh = 0x0
+ // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U
+ // .. .. reg_ddrc_rdwr_idle_gap = 1
+ // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+ // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U
+ // .. .. reg_ddrc_dis_rd_bypass = 0x0
+ // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+ // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_act_bypass = 0x0
+ // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_auto_refresh = 0x0
+ // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
+ // .. .. FINISH: UNLOCK DDR
+ // .. .. START: CHECK DDR STATUS
+ // .. .. ddrc_reg_operating_mode = 1
+ // .. .. ==> 0XF8006054[2:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U
+ // .. ..
+ EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+ // .. .. FINISH: CHECK DDR STATUS
+ // .. FINISH: DDR INITIALIZATION
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_mio_init_data_3_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: OCM REMAPPING
+ // .. FINISH: OCM REMAPPING
+ // .. START: DDRIOB SETTINGS
+ // .. reserved_INP_POWER = 0x0
+ // .. ==> 0XF8000B40[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x0
+ // .. ==> 0XF8000B40[2:1] = 0x00000000U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000000U
+ // .. DCI_UPDATE_B = 0x0
+ // .. ==> 0XF8000B40[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x0
+ // .. ==> 0XF8000B40[4:4] = 0x00000000U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. DCI_TYPE = 0x0
+ // .. ==> 0XF8000B40[6:5] = 0x00000000U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000000U
+ // .. IBUF_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B40[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B40[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B40[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B40[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
+ // .. reserved_INP_POWER = 0x0
+ // .. ==> 0XF8000B44[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x0
+ // .. ==> 0XF8000B44[2:1] = 0x00000000U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000000U
+ // .. DCI_UPDATE_B = 0x0
+ // .. ==> 0XF8000B44[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x0
+ // .. ==> 0XF8000B44[4:4] = 0x00000000U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. DCI_TYPE = 0x0
+ // .. ==> 0XF8000B44[6:5] = 0x00000000U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000000U
+ // .. IBUF_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B44[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B44[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B44[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B44[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
+ // .. reserved_INP_POWER = 0x0
+ // .. ==> 0XF8000B48[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x1
+ // .. ==> 0XF8000B48[2:1] = 0x00000001U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000002U
+ // .. DCI_UPDATE_B = 0x0
+ // .. ==> 0XF8000B48[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x1
+ // .. ==> 0XF8000B48[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. DCI_TYPE = 0x3
+ // .. ==> 0XF8000B48[6:5] = 0x00000003U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000060U
+ // .. IBUF_DISABLE_MODE = 0
+ // .. ==> 0XF8000B48[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0
+ // .. ==> 0XF8000B48[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B48[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B48[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
+ // .. reserved_INP_POWER = 0x0
+ // .. ==> 0XF8000B4C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x1
+ // .. ==> 0XF8000B4C[2:1] = 0x00000001U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000002U
+ // .. DCI_UPDATE_B = 0x0
+ // .. ==> 0XF8000B4C[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x1
+ // .. ==> 0XF8000B4C[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. DCI_TYPE = 0x3
+ // .. ==> 0XF8000B4C[6:5] = 0x00000003U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000060U
+ // .. IBUF_DISABLE_MODE = 0
+ // .. ==> 0XF8000B4C[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0
+ // .. ==> 0XF8000B4C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B4C[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B4C[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
+ // .. reserved_INP_POWER = 0x0
+ // .. ==> 0XF8000B50[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x2
+ // .. ==> 0XF8000B50[2:1] = 0x00000002U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000004U
+ // .. DCI_UPDATE_B = 0x0
+ // .. ==> 0XF8000B50[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x1
+ // .. ==> 0XF8000B50[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. DCI_TYPE = 0x3
+ // .. ==> 0XF8000B50[6:5] = 0x00000003U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000060U
+ // .. IBUF_DISABLE_MODE = 0
+ // .. ==> 0XF8000B50[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0
+ // .. ==> 0XF8000B50[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B50[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B50[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
+ // .. reserved_INP_POWER = 0x0
+ // .. ==> 0XF8000B54[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x2
+ // .. ==> 0XF8000B54[2:1] = 0x00000002U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000004U
+ // .. DCI_UPDATE_B = 0x0
+ // .. ==> 0XF8000B54[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x1
+ // .. ==> 0XF8000B54[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. DCI_TYPE = 0x3
+ // .. ==> 0XF8000B54[6:5] = 0x00000003U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000060U
+ // .. IBUF_DISABLE_MODE = 0
+ // .. ==> 0XF8000B54[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0
+ // .. ==> 0XF8000B54[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B54[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B54[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
+ // .. reserved_INP_POWER = 0x0
+ // .. ==> 0XF8000B58[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x0
+ // .. ==> 0XF8000B58[2:1] = 0x00000000U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000000U
+ // .. DCI_UPDATE_B = 0x0
+ // .. ==> 0XF8000B58[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x0
+ // .. ==> 0XF8000B58[4:4] = 0x00000000U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. DCI_TYPE = 0x0
+ // .. ==> 0XF8000B58[6:5] = 0x00000000U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000000U
+ // .. IBUF_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B58[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B58[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B58[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B58[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
+ // .. reserved_DRIVE_P = 0x1c
+ // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
+ // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
+ // .. reserved_DRIVE_N = 0xc
+ // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
+ // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
+ // .. reserved_SLEW_P = 0x3
+ // .. ==> 0XF8000B5C[18:14] = 0x00000003U
+ // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U
+ // .. reserved_SLEW_N = 0x3
+ // .. ==> 0XF8000B5C[23:19] = 0x00000003U
+ // .. ==> MASK : 0x00F80000U VAL : 0x00180000U
+ // .. reserved_GTL = 0x0
+ // .. ==> 0XF8000B5C[26:24] = 0x00000000U
+ // .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. reserved_RTERM = 0x0
+ // .. ==> 0XF8000B5C[31:27] = 0x00000000U
+ // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
+ // .. reserved_DRIVE_P = 0x1c
+ // .. ==> 0XF8000B60[6:0] = 0x0000001CU
+ // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
+ // .. reserved_DRIVE_N = 0xc
+ // .. ==> 0XF8000B60[13:7] = 0x0000000CU
+ // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
+ // .. reserved_SLEW_P = 0x6
+ // .. ==> 0XF8000B60[18:14] = 0x00000006U
+ // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
+ // .. reserved_SLEW_N = 0x1f
+ // .. ==> 0XF8000B60[23:19] = 0x0000001FU
+ // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
+ // .. reserved_GTL = 0x0
+ // .. ==> 0XF8000B60[26:24] = 0x00000000U
+ // .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. reserved_RTERM = 0x0
+ // .. ==> 0XF8000B60[31:27] = 0x00000000U
+ // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
+ // .. reserved_DRIVE_P = 0x1c
+ // .. ==> 0XF8000B64[6:0] = 0x0000001CU
+ // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
+ // .. reserved_DRIVE_N = 0xc
+ // .. ==> 0XF8000B64[13:7] = 0x0000000CU
+ // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
+ // .. reserved_SLEW_P = 0x6
+ // .. ==> 0XF8000B64[18:14] = 0x00000006U
+ // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
+ // .. reserved_SLEW_N = 0x1f
+ // .. ==> 0XF8000B64[23:19] = 0x0000001FU
+ // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
+ // .. reserved_GTL = 0x0
+ // .. ==> 0XF8000B64[26:24] = 0x00000000U
+ // .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. reserved_RTERM = 0x0
+ // .. ==> 0XF8000B64[31:27] = 0x00000000U
+ // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
+ // .. reserved_DRIVE_P = 0x1c
+ // .. ==> 0XF8000B68[6:0] = 0x0000001CU
+ // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
+ // .. reserved_DRIVE_N = 0xc
+ // .. ==> 0XF8000B68[13:7] = 0x0000000CU
+ // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
+ // .. reserved_SLEW_P = 0x6
+ // .. ==> 0XF8000B68[18:14] = 0x00000006U
+ // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
+ // .. reserved_SLEW_N = 0x1f
+ // .. ==> 0XF8000B68[23:19] = 0x0000001FU
+ // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
+ // .. reserved_GTL = 0x0
+ // .. ==> 0XF8000B68[26:24] = 0x00000000U
+ // .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. reserved_RTERM = 0x0
+ // .. ==> 0XF8000B68[31:27] = 0x00000000U
+ // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
+ // .. VREF_INT_EN = 0x1
+ // .. ==> 0XF8000B6C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. VREF_SEL = 0x4
+ // .. ==> 0XF8000B6C[4:1] = 0x00000004U
+ // .. ==> MASK : 0x0000001EU VAL : 0x00000008U
+ // .. VREF_EXT_EN = 0x0
+ // .. ==> 0XF8000B6C[6:5] = 0x00000000U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000000U
+ // .. reserved_VREF_PULLUP_EN = 0x0
+ // .. ==> 0XF8000B6C[8:7] = 0x00000000U
+ // .. ==> MASK : 0x00000180U VAL : 0x00000000U
+ // .. REFIO_EN = 0x1
+ // .. ==> 0XF8000B6C[9:9] = 0x00000001U
+ // .. ==> MASK : 0x00000200U VAL : 0x00000200U
+ // .. reserved_REFIO_TEST = 0x3
+ // .. ==> 0XF8000B6C[11:10] = 0x00000003U
+ // .. ==> MASK : 0x00000C00U VAL : 0x00000C00U
+ // .. reserved_REFIO_PULLUP_EN = 0x0
+ // .. ==> 0XF8000B6C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. reserved_DRST_B_PULLUP_EN = 0x0
+ // .. ==> 0XF8000B6C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // .. reserved_CKE_PULLUP_EN = 0x0
+ // .. ==> 0XF8000B6C[14:14] = 0x00000000U
+ // .. ==> MASK : 0x00004000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000E09U),
+ // .. .. START: ASSERT RESET
+ // .. .. RESET = 1
+ // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000B70, 0x00000001U ,0x00000001U),
+ // .. .. FINISH: ASSERT RESET
+ // .. .. START: DEASSERT RESET
+ // .. .. RESET = 0
+ // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reserved_VRN_OUT = 0x1
+ // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
+ // .. .. FINISH: DEASSERT RESET
+ // .. .. RESET = 0x1
+ // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ENABLE = 0x1
+ // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. .. reserved_VRP_TRI = 0x0
+ // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reserved_VRN_TRI = 0x0
+ // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reserved_VRP_OUT = 0x0
+ // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reserved_VRN_OUT = 0x1
+ // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
+ // .. .. NREF_OPT1 = 0x0
+ // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
+ // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U
+ // .. .. NREF_OPT2 = 0x0
+ // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U
+ // .. .. NREF_OPT4 = 0x1
+ // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
+ // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U
+ // .. .. PREF_OPT1 = 0x0
+ // .. .. ==> 0XF8000B70[15:14] = 0x00000000U
+ // .. .. ==> MASK : 0x0000C000U VAL : 0x00000000U
+ // .. .. PREF_OPT2 = 0x0
+ // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
+ // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U
+ // .. .. UPDATE_CONTROL = 0x0
+ // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
+ // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U
+ // .. .. reserved_INIT_COMPLETE = 0x0
+ // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
+ // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U
+ // .. .. reserved_TST_CLK = 0x0
+ // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
+ // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U
+ // .. .. reserved_TST_HLN = 0x0
+ // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
+ // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U
+ // .. .. reserved_TST_HLP = 0x0
+ // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
+ // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U
+ // .. .. reserved_TST_RST = 0x0
+ // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
+ // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
+ // .. .. reserved_INT_DCI_EN = 0x0
+ // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
+ // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU ,0x00000823U),
+ // .. FINISH: DDRIOB SETTINGS
+ // .. START: MIO PROGRAMMING
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000700[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000700[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000700[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000700[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000700[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000700[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000700[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000700[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000700[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000704[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000704[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000704[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000704[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000704[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000704[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000704[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000704[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000704[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00000602U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000708[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000708[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000708[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000708[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000708[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000708[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000708[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000708[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000708[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000602U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800070C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF800070C[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800070C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800070C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800070C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800070C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF800070C[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF800070C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800070C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000602U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000710[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000710[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000710[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000710[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000710[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000710[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000710[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000710[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000710[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000602U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000714[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000714[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000714[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000714[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000714[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000714[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000714[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000714[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000714[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000602U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000718[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000718[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000718[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000718[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000718[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000718[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000718[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000718[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000718[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000602U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800071C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800071C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800071C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800071C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800071C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800071C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF800071C[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF800071C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800071C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000720[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000720[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000720[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000720[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000720[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000720[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000720[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000720[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000720[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000602U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000724[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000724[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000724[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000724[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000724[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000724[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000724[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000724[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000724[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000728[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000728[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000728[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000728[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000728[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000728[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000728[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000728[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000728[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800072C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800072C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800072C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800072C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800072C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800072C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF800072C[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF800072C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800072C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000730[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000730[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000730[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000730[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000730[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000730[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000730[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000730[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000730[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000734[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000734[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000734[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000734[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000734[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000734[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000734[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000734[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000734[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000738[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000738[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000738[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000738[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000738[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000738[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000738[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000738[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000738[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800073C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800073C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800073C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800073C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800073C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800073C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF800073C[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF800073C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800073C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000740[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000740[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000740[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000740[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000740[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000740[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000740[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000740[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000740[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000744[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000744[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000744[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000744[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000744[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000744[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000744[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000744[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000744[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000748[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000748[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000748[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000748[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000748[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000748[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000748[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000748[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000748[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800074C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF800074C[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800074C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800074C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800074C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800074C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800074C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800074C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800074C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000750[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000750[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000750[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000750[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000750[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000750[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000750[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000750[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000750[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000754[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000754[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000754[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000754[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000754[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000754[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000754[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000754[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000754[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000202U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000758[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000758[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000758[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000758[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000758[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000758[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000758[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000758[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000758[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000203U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF800075C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF800075C[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800075C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800075C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800075C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800075C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800075C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800075C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800075C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000203U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000760[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000760[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000760[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000760[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000760[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000760[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000760[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000760[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000760[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000203U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000764[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000764[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000764[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000764[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000764[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000764[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000764[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000764[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000764[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000203U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000768[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000768[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000768[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000768[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000768[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000768[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000768[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000768[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000768[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000203U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF800076C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF800076C[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800076C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800076C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800076C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800076C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800076C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800076C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800076C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000203U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000770[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000770[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000770[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000770[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000770[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000770[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000770[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000770[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000770[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000774[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000774[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000774[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000774[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000774[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000774[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000774[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000774[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000774[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000778[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000778[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000778[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000778[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000778[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000778[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000778[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000778[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000778[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF800077C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800077C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF800077C[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800077C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800077C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800077C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800077C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800077C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800077C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000780[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000780[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000780[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000780[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000780[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000780[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000780[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000780[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000780[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000784[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000784[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000784[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000784[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000784[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000784[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000784[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000784[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000784[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000788[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000788[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000788[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000788[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000788[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000788[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000788[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000788[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000788[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800078C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800078C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF800078C[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800078C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800078C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800078C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800078C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800078C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800078C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000790[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000790[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000790[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000790[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000790[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000790[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000790[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000790[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000790[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000794[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000794[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000794[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000794[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000794[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000794[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000794[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000794[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000794[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000798[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000798[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000798[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000798[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000798[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000798[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000798[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000798[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000798[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800079C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800079C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF800079C[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800079C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800079C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800079C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800079C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800079C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800079C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007A0[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007A0[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007A0[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007A0[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007A0[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007A0[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007A0[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007A0[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007A0[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007A4[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007A4[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007A4[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007A4[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007A4[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007A4[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007A4[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007A4[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007A4[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007A8[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007A8[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007A8[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007A8[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007A8[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007A8[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007A8[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007A8[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007A8[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007AC[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007AC[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007AC[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007AC[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007AC[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007AC[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007AC[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007AC[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007AC[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007B0[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007B0[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007B0[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007B0[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007B0[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007B0[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007B0[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007B0[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007B0[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007B4[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007B4[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007B4[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007B4[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007B4[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007B4[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007B4[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007B4[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007B4[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000280U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF80007B8[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. Speed = 0
+ // .. ==> 0XF80007B8[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007B8[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007B8[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007B8[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007B8, 0x00003F01U ,0x00000201U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007BC[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007BC[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007BC[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007BC[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF80007BC[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF80007BC[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007BC[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007BC[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007BC[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00000200U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007C0[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007C0[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007C0[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007C0[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 7
+ // .. ==> 0XF80007C0[7:5] = 0x00000007U
+ // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U
+ // .. Speed = 0
+ // .. ==> 0XF80007C0[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007C0[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007C0[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007C0[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF80007C4[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007C4[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007C4[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007C4[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 7
+ // .. ==> 0XF80007C4[7:5] = 0x00000007U
+ // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U
+ // .. Speed = 0
+ // .. ==> 0XF80007C4[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007C4[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007C4[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007C4[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF80007C8[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. Speed = 0
+ // .. ==> 0XF80007C8[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007C8[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007C8[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007C8[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007C8, 0x00003F01U ,0x00000201U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007CC[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007CC[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007CC[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007CC[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF80007CC[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF80007CC[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007CC[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007CC[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007CC[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00000200U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007D0[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007D0[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007D0[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007D0[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007D0[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007D0[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007D0[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007D0[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007D0[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007D4[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007D4[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007D4[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007D4[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007D4[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007D4[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007D4[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007D4[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007D4[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U),
+ // .. SDIO0_WP_SEL = 50
+ // .. ==> 0XF8000830[5:0] = 0x00000032U
+ // .. ==> MASK : 0x0000003FU VAL : 0x00000032U
+ // .. SDIO0_CD_SEL = 46
+ // .. ==> 0XF8000830[21:16] = 0x0000002EU
+ // .. ==> MASK : 0x003F0000U VAL : 0x002E0000U
+ // ..
+ EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x002E0032U),
+ // .. FINISH: MIO PROGRAMMING
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_peripherals_init_data_3_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+ // .. IBUF_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B48[7:7] = 0x00000001U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. TERM_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B48[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // ..
+ EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
+ // .. IBUF_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B4C[7:7] = 0x00000001U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. TERM_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B4C[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // ..
+ EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
+ // .. IBUF_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B50[7:7] = 0x00000001U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. TERM_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B50[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // ..
+ EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
+ // .. IBUF_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B54[7:7] = 0x00000001U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. TERM_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B54[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // ..
+ EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
+ // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // .. START: SRAM/NOR SET OPMODE
+ // .. FINISH: SRAM/NOR SET OPMODE
+ // .. START: UART REGISTERS
+ // .. BDIV = 0x6
+ // .. ==> 0XE0001034[7:0] = 0x00000006U
+ // .. ==> MASK : 0x000000FFU VAL : 0x00000006U
+ // ..
+ EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
+ // .. CD = 0x3e
+ // .. ==> 0XE0001018[15:0] = 0x0000003EU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU
+ // ..
+ EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
+ // .. STPBRK = 0x0
+ // .. ==> 0XE0001000[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. STTBRK = 0x0
+ // .. ==> 0XE0001000[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. RSTTO = 0x0
+ // .. ==> 0XE0001000[6:6] = 0x00000000U
+ // .. ==> MASK : 0x00000040U VAL : 0x00000000U
+ // .. TXDIS = 0x0
+ // .. ==> 0XE0001000[5:5] = 0x00000000U
+ // .. ==> MASK : 0x00000020U VAL : 0x00000000U
+ // .. TXEN = 0x1
+ // .. ==> 0XE0001000[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. RXDIS = 0x0
+ // .. ==> 0XE0001000[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. RXEN = 0x1
+ // .. ==> 0XE0001000[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. TXRES = 0x1
+ // .. ==> 0XE0001000[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. RXRES = 0x1
+ // .. ==> 0XE0001000[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // ..
+ EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
+ // .. CHMODE = 0x0
+ // .. ==> 0XE0001004[9:8] = 0x00000000U
+ // .. ==> MASK : 0x00000300U VAL : 0x00000000U
+ // .. NBSTOP = 0x0
+ // .. ==> 0XE0001004[7:6] = 0x00000000U
+ // .. ==> MASK : 0x000000C0U VAL : 0x00000000U
+ // .. PAR = 0x4
+ // .. ==> 0XE0001004[5:3] = 0x00000004U
+ // .. ==> MASK : 0x00000038U VAL : 0x00000020U
+ // .. CHRL = 0x0
+ // .. ==> 0XE0001004[2:1] = 0x00000000U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000000U
+ // .. CLKS = 0x0
+ // .. ==> 0XE0001004[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XE0001004, 0x000003FFU ,0x00000020U),
+ // .. FINISH: UART REGISTERS
+ // .. START: QSPI REGISTERS
+ // .. Holdb_dr = 1
+ // .. ==> 0XE000D000[19:19] = 0x00000001U
+ // .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // ..
+ EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
+ // .. FINISH: QSPI REGISTERS
+ // .. START: PL POWER ON RESET REGISTERS
+ // .. PCFG_POR_CNT_4K = 0
+ // .. ==> 0XF8007000[29:29] = 0x00000000U
+ // .. ==> MASK : 0x20000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
+ // .. FINISH: PL POWER ON RESET REGISTERS
+ // .. START: SMC TIMING CALCULATION REGISTER UPDATE
+ // .. .. START: NAND SET CYCLE
+ // .. .. FINISH: NAND SET CYCLE
+ // .. .. START: OPMODE
+ // .. .. FINISH: OPMODE
+ // .. .. START: DIRECT COMMAND
+ // .. .. FINISH: DIRECT COMMAND
+ // .. .. START: SRAM/NOR CS0 SET CYCLE
+ // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
+ // .. .. START: DIRECT COMMAND
+ // .. .. FINISH: DIRECT COMMAND
+ // .. .. START: NOR CS0 BASE ADDRESS
+ // .. .. FINISH: NOR CS0 BASE ADDRESS
+ // .. .. START: SRAM/NOR CS1 SET CYCLE
+ // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
+ // .. .. START: DIRECT COMMAND
+ // .. .. FINISH: DIRECT COMMAND
+ // .. .. START: NOR CS1 BASE ADDRESS
+ // .. .. FINISH: NOR CS1 BASE ADDRESS
+ // .. .. START: USB RESET
+ // .. .. .. START: USB0 RESET
+ // .. .. .. .. START: DIR MODE BANK 0
+ // .. .. .. .. DIRECTION_0 = 0x80
+ // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U
+ // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U),
+ // .. .. .. .. FINISH: DIR MODE BANK 0
+ // .. .. .. .. START: DIR MODE BANK 1
+ // .. .. .. .. FINISH: DIR MODE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. MASK_0_LSW = 0xff7f
+ // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+ // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U
+ // .. .. .. .. DATA_0_LSW = 0x80
+ // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+ // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. START: OUTPUT ENABLE BANK 0
+ // .. .. .. .. OP_ENABLE_0 = 0x80
+ // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U
+ // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U),
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+ // .. .. .. .. START: OUTPUT ENABLE BANK 1
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. MASK_0_LSW = 0xff7f
+ // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+ // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U
+ // .. .. .. .. DATA_0_LSW = 0x0
+ // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+ // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U),
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. START: ADD 1 MS DELAY
+ // .. .. .. ..
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ // .. .. .. .. FINISH: ADD 1 MS DELAY
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. MASK_0_LSW = 0xff7f
+ // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+ // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U
+ // .. .. .. .. DATA_0_LSW = 0x80
+ // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+ // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. FINISH: USB0 RESET
+ // .. .. .. START: USB1 RESET
+ // .. .. .. .. START: DIR MODE BANK 0
+ // .. .. .. .. FINISH: DIR MODE BANK 0
+ // .. .. .. .. START: DIR MODE BANK 1
+ // .. .. .. .. FINISH: DIR MODE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. START: OUTPUT ENABLE BANK 0
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+ // .. .. .. .. START: OUTPUT ENABLE BANK 1
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. START: ADD 1 MS DELAY
+ // .. .. .. ..
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ // .. .. .. .. FINISH: ADD 1 MS DELAY
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. FINISH: USB1 RESET
+ // .. .. FINISH: USB RESET
+ // .. .. START: ENET RESET
+ // .. .. .. START: ENET0 RESET
+ // .. .. .. .. START: DIR MODE BANK 0
+ // .. .. .. .. FINISH: DIR MODE BANK 0
+ // .. .. .. .. START: DIR MODE BANK 1
+ // .. .. .. .. FINISH: DIR MODE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. START: OUTPUT ENABLE BANK 0
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+ // .. .. .. .. START: OUTPUT ENABLE BANK 1
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. START: ADD 1 MS DELAY
+ // .. .. .. ..
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ // .. .. .. .. FINISH: ADD 1 MS DELAY
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. FINISH: ENET0 RESET
+ // .. .. .. START: ENET1 RESET
+ // .. .. .. .. START: DIR MODE BANK 0
+ // .. .. .. .. FINISH: DIR MODE BANK 0
+ // .. .. .. .. START: DIR MODE BANK 1
+ // .. .. .. .. FINISH: DIR MODE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. START: OUTPUT ENABLE BANK 0
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+ // .. .. .. .. START: OUTPUT ENABLE BANK 1
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. START: ADD 1 MS DELAY
+ // .. .. .. ..
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ // .. .. .. .. FINISH: ADD 1 MS DELAY
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. FINISH: ENET1 RESET
+ // .. .. FINISH: ENET RESET
+ // .. .. START: I2C RESET
+ // .. .. .. START: I2C0 RESET
+ // .. .. .. .. START: DIR MODE GPIO BANK0
+ // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+ // .. .. .. .. START: DIR MODE GPIO BANK1
+ // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. START: OUTPUT ENABLE
+ // .. .. .. .. FINISH: OUTPUT ENABLE
+ // .. .. .. .. START: OUTPUT ENABLE
+ // .. .. .. .. FINISH: OUTPUT ENABLE
+ // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. START: ADD 1 MS DELAY
+ // .. .. .. ..
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ // .. .. .. .. FINISH: ADD 1 MS DELAY
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. FINISH: I2C0 RESET
+ // .. .. .. START: I2C1 RESET
+ // .. .. .. .. START: DIR MODE GPIO BANK0
+ // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+ // .. .. .. .. START: DIR MODE GPIO BANK1
+ // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. START: OUTPUT ENABLE
+ // .. .. .. .. FINISH: OUTPUT ENABLE
+ // .. .. .. .. START: OUTPUT ENABLE
+ // .. .. .. .. FINISH: OUTPUT ENABLE
+ // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. START: ADD 1 MS DELAY
+ // .. .. .. ..
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ // .. .. .. .. FINISH: ADD 1 MS DELAY
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. FINISH: I2C1 RESET
+ // .. .. FINISH: I2C RESET
+ // .. .. START: NOR CHIP SELECT
+ // .. .. .. START: DIR MODE BANK 0
+ // .. .. .. FINISH: DIR MODE BANK 0
+ // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. START: OUTPUT ENABLE BANK 0
+ // .. .. .. FINISH: OUTPUT ENABLE BANK 0
+ // .. .. FINISH: NOR CHIP SELECT
+ // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_post_config_3_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: ENABLING LEVEL SHIFTER
+ // .. USER_LVL_INP_EN_0 = 1
+ // .. ==> 0XF8000900[3:3] = 0x00000001U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000008U
+ // .. USER_LVL_OUT_EN_0 = 1
+ // .. ==> 0XF8000900[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. USER_LVL_INP_EN_1 = 1
+ // .. ==> 0XF8000900[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. USER_LVL_OUT_EN_1 = 1
+ // .. ==> 0XF8000900[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // ..
+ EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
+ // .. FINISH: ENABLING LEVEL SHIFTER
+ // .. START: FPGA RESETS TO 0
+ // .. reserved_3 = 0
+ // .. ==> 0XF8000240[31:25] = 0x00000000U
+ // .. ==> MASK : 0xFE000000U VAL : 0x00000000U
+ // .. reserved_FPGA_ACP_RST = 0
+ // .. ==> 0XF8000240[24:24] = 0x00000000U
+ // .. ==> MASK : 0x01000000U VAL : 0x00000000U
+ // .. reserved_FPGA_AXDS3_RST = 0
+ // .. ==> 0XF8000240[23:23] = 0x00000000U
+ // .. ==> MASK : 0x00800000U VAL : 0x00000000U
+ // .. reserved_FPGA_AXDS2_RST = 0
+ // .. ==> 0XF8000240[22:22] = 0x00000000U
+ // .. ==> MASK : 0x00400000U VAL : 0x00000000U
+ // .. reserved_FPGA_AXDS1_RST = 0
+ // .. ==> 0XF8000240[21:21] = 0x00000000U
+ // .. ==> MASK : 0x00200000U VAL : 0x00000000U
+ // .. reserved_FPGA_AXDS0_RST = 0
+ // .. ==> 0XF8000240[20:20] = 0x00000000U
+ // .. ==> MASK : 0x00100000U VAL : 0x00000000U
+ // .. reserved_2 = 0
+ // .. ==> 0XF8000240[19:18] = 0x00000000U
+ // .. ==> MASK : 0x000C0000U VAL : 0x00000000U
+ // .. reserved_FSSW1_FPGA_RST = 0
+ // .. ==> 0XF8000240[17:17] = 0x00000000U
+ // .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. reserved_FSSW0_FPGA_RST = 0
+ // .. ==> 0XF8000240[16:16] = 0x00000000U
+ // .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. reserved_1 = 0
+ // .. ==> 0XF8000240[15:14] = 0x00000000U
+ // .. ==> MASK : 0x0000C000U VAL : 0x00000000U
+ // .. reserved_FPGA_FMSW1_RST = 0
+ // .. ==> 0XF8000240[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // .. reserved_FPGA_FMSW0_RST = 0
+ // .. ==> 0XF8000240[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. reserved_FPGA_DMA3_RST = 0
+ // .. ==> 0XF8000240[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. reserved_FPGA_DMA2_RST = 0
+ // .. ==> 0XF8000240[10:10] = 0x00000000U
+ // .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. reserved_FPGA_DMA1_RST = 0
+ // .. ==> 0XF8000240[9:9] = 0x00000000U
+ // .. ==> MASK : 0x00000200U VAL : 0x00000000U
+ // .. reserved_FPGA_DMA0_RST = 0
+ // .. ==> 0XF8000240[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. reserved = 0
+ // .. ==> 0XF8000240[7:4] = 0x00000000U
+ // .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. FPGA3_OUT_RST = 0
+ // .. ==> 0XF8000240[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. FPGA2_OUT_RST = 0
+ // .. ==> 0XF8000240[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. FPGA1_OUT_RST = 0
+ // .. ==> 0XF8000240[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. FPGA0_OUT_RST = 0
+ // .. ==> 0XF8000240[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
+ // .. FINISH: FPGA RESETS TO 0
+ // .. START: AFI REGISTERS
+ // .. .. START: AFI0 REGISTERS
+ // .. .. FINISH: AFI0 REGISTERS
+ // .. .. START: AFI1 REGISTERS
+ // .. .. FINISH: AFI1 REGISTERS
+ // .. .. START: AFI2 REGISTERS
+ // .. .. FINISH: AFI2 REGISTERS
+ // .. .. START: AFI3 REGISTERS
+ // .. .. FINISH: AFI3 REGISTERS
+ // .. FINISH: AFI REGISTERS
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_debug_3_0[] = {
+ // START: top
+ // .. START: CROSS TRIGGER CONFIGURATIONS
+ // .. .. START: UNLOCKING CTI REGISTERS
+ // .. .. KEY = 0XC5ACCE55
+ // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
+ // .. ..
+ EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
+ // .. .. KEY = 0XC5ACCE55
+ // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
+ // .. ..
+ EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
+ // .. .. KEY = 0XC5ACCE55
+ // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
+ // .. ..
+ EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
+ // .. .. FINISH: UNLOCKING CTI REGISTERS
+ // .. .. START: ENABLING CTI MODULES AND CHANNELS
+ // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
+ // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+ // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+ // .. FINISH: CROSS TRIGGER CONFIGURATIONS
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_pll_init_data_2_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: PLL SLCR REGISTERS
+ // .. .. START: ARM PLL INIT
+ // .. .. PLL_RES = 0x2
+ // .. .. ==> 0XF8000110[7:4] = 0x00000002U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
+ // .. .. PLL_CP = 0x2
+ // .. .. ==> 0XF8000110[11:8] = 0x00000002U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
+ // .. .. LOCK_CNT = 0xfa
+ // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
+ // .. .. .. START: UPDATE FB_DIV
+ // .. .. .. PLL_FDIV = 0x28
+ // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
+ // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
+ // .. .. .. FINISH: UPDATE FB_DIV
+ // .. .. .. START: BY PASS PLL
+ // .. .. .. PLL_BYPASS_FORCE = 1
+ // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
+ // .. .. .. FINISH: BY PASS PLL
+ // .. .. .. START: ASSERT RESET
+ // .. .. .. PLL_RESET = 1
+ // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
+ // .. .. .. FINISH: ASSERT RESET
+ // .. .. .. START: DEASSERT RESET
+ // .. .. .. PLL_RESET = 0
+ // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
+ // .. .. .. FINISH: DEASSERT RESET
+ // .. .. .. START: CHECK PLL STATUS
+ // .. .. .. ARM_PLL_LOCK = 1
+ // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ..
+ EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+ // .. .. .. FINISH: CHECK PLL STATUS
+ // .. .. .. START: REMOVE PLL BY PASS
+ // .. .. .. PLL_BYPASS_FORCE = 0
+ // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
+ // .. .. .. FINISH: REMOVE PLL BY PASS
+ // .. .. .. SRCSEL = 0x0
+ // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. .. .. DIVISOR = 0x2
+ // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
+ // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U
+ // .. .. .. CPU_6OR4XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
+ // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U
+ // .. .. .. CPU_3OR2XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
+ // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U
+ // .. .. .. CPU_2XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
+ // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U
+ // .. .. .. CPU_1XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
+ // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U
+ // .. .. .. CPU_PERI_CLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
+ // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
+ // .. .. FINISH: ARM PLL INIT
+ // .. .. START: DDR PLL INIT
+ // .. .. PLL_RES = 0x2
+ // .. .. ==> 0XF8000114[7:4] = 0x00000002U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
+ // .. .. PLL_CP = 0x2
+ // .. .. ==> 0XF8000114[11:8] = 0x00000002U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
+ // .. .. LOCK_CNT = 0x12c
+ // .. .. ==> 0XF8000114[21:12] = 0x0000012CU
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
+ // .. .. .. START: UPDATE FB_DIV
+ // .. .. .. PLL_FDIV = 0x20
+ // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
+ // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
+ // .. .. .. FINISH: UPDATE FB_DIV
+ // .. .. .. START: BY PASS PLL
+ // .. .. .. PLL_BYPASS_FORCE = 1
+ // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
+ // .. .. .. FINISH: BY PASS PLL
+ // .. .. .. START: ASSERT RESET
+ // .. .. .. PLL_RESET = 1
+ // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
+ // .. .. .. FINISH: ASSERT RESET
+ // .. .. .. START: DEASSERT RESET
+ // .. .. .. PLL_RESET = 0
+ // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
+ // .. .. .. FINISH: DEASSERT RESET
+ // .. .. .. START: CHECK PLL STATUS
+ // .. .. .. DDR_PLL_LOCK = 1
+ // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. .. ..
+ EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+ // .. .. .. FINISH: CHECK PLL STATUS
+ // .. .. .. START: REMOVE PLL BY PASS
+ // .. .. .. PLL_BYPASS_FORCE = 0
+ // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
+ // .. .. .. FINISH: REMOVE PLL BY PASS
+ // .. .. .. DDR_3XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. .. DDR_2XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. .. .. DDR_3XCLK_DIVISOR = 0x2
+ // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
+ // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U
+ // .. .. .. DDR_2XCLK_DIVISOR = 0x3
+ // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
+ // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
+ // .. .. FINISH: DDR PLL INIT
+ // .. .. START: IO PLL INIT
+ // .. .. PLL_RES = 0xc
+ // .. .. ==> 0XF8000118[7:4] = 0x0000000CU
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U
+ // .. .. PLL_CP = 0x2
+ // .. .. ==> 0XF8000118[11:8] = 0x00000002U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
+ // .. .. LOCK_CNT = 0x145
+ // .. .. ==> 0XF8000118[21:12] = 0x00000145U
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U),
+ // .. .. .. START: UPDATE FB_DIV
+ // .. .. .. PLL_FDIV = 0x1e
+ // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU
+ // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U),
+ // .. .. .. FINISH: UPDATE FB_DIV
+ // .. .. .. START: BY PASS PLL
+ // .. .. .. PLL_BYPASS_FORCE = 1
+ // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
+ // .. .. .. FINISH: BY PASS PLL
+ // .. .. .. START: ASSERT RESET
+ // .. .. .. PLL_RESET = 1
+ // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
+ // .. .. .. FINISH: ASSERT RESET
+ // .. .. .. START: DEASSERT RESET
+ // .. .. .. PLL_RESET = 0
+ // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
+ // .. .. .. FINISH: DEASSERT RESET
+ // .. .. .. START: CHECK PLL STATUS
+ // .. .. .. IO_PLL_LOCK = 1
+ // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. .. ..
+ EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+ // .. .. .. FINISH: CHECK PLL STATUS
+ // .. .. .. START: REMOVE PLL BY PASS
+ // .. .. .. PLL_BYPASS_FORCE = 0
+ // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
+ // .. .. .. FINISH: REMOVE PLL BY PASS
+ // .. .. FINISH: IO PLL INIT
+ // .. FINISH: PLL SLCR REGISTERS
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_clock_init_data_2_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: CLOCK CONTROL SLCR REGISTERS
+ // .. CLKACT = 0x1
+ // .. ==> 0XF8000128[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. DIVISOR0 = 0x23
+ // .. ==> 0XF8000128[13:8] = 0x00000023U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00002300U
+ // .. DIVISOR1 = 0x3
+ // .. ==> 0XF8000128[25:20] = 0x00000003U
+ // .. ==> MASK : 0x03F00000U VAL : 0x00300000U
+ // ..
+ EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U),
+ // .. CLKACT = 0x1
+ // .. ==> 0XF8000138[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000138[4:4] = 0x00000000U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
+ // .. CLKACT = 0x1
+ // .. ==> 0XF8000140[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000140[6:4] = 0x00000000U
+ // .. ==> MASK : 0x00000070U VAL : 0x00000000U
+ // .. DIVISOR = 0x8
+ // .. ==> 0XF8000140[13:8] = 0x00000008U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00000800U
+ // .. DIVISOR1 = 0x1
+ // .. ==> 0XF8000140[25:20] = 0x00000001U
+ // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
+ // ..
+ EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U),
+ // .. CLKACT = 0x1
+ // .. ==> 0XF800014C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF800014C[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR = 0x5
+ // .. ==> 0XF800014C[13:8] = 0x00000005U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00000500U
+ // ..
+ EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
+ // .. CLKACT0 = 0x1
+ // .. ==> 0XF8000150[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. CLKACT1 = 0x0
+ // .. ==> 0XF8000150[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000150[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR = 0x14
+ // .. ==> 0XF8000150[13:8] = 0x00000014U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
+ // ..
+ EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U),
+ // .. CLKACT0 = 0x0
+ // .. ==> 0XF8000154[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. CLKACT1 = 0x1
+ // .. ==> 0XF8000154[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000154[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR = 0x14
+ // .. ==> 0XF8000154[13:8] = 0x00000014U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
+ // ..
+ EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U),
+ // .. CLKACT = 0x1
+ // .. ==> 0XF8000168[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000168[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR = 0x5
+ // .. ==> 0XF8000168[13:8] = 0x00000005U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00000500U
+ // ..
+ EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000170[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR0 = 0xa
+ // .. ==> 0XF8000170[13:8] = 0x0000000AU
+ // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U
+ // .. DIVISOR1 = 0x1
+ // .. ==> 0XF8000170[25:20] = 0x00000001U
+ // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
+ // ..
+ EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00100A00U),
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000180[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR0 = 0xa
+ // .. ==> 0XF8000180[13:8] = 0x0000000AU
+ // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U
+ // .. DIVISOR1 = 0x1
+ // .. ==> 0XF8000180[25:20] = 0x00000001U
+ // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
+ // ..
+ EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00100A00U),
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000190[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR0 = 0x1e
+ // .. ==> 0XF8000190[13:8] = 0x0000001EU
+ // .. ==> MASK : 0x00003F00U VAL : 0x00001E00U
+ // .. DIVISOR1 = 0x1
+ // .. ==> 0XF8000190[25:20] = 0x00000001U
+ // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
+ // ..
+ EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101E00U),
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF80001A0[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR0 = 0x14
+ // .. ==> 0XF80001A0[13:8] = 0x00000014U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
+ // .. DIVISOR1 = 0x1
+ // .. ==> 0XF80001A0[25:20] = 0x00000001U
+ // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
+ // ..
+ EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U),
+ // .. CLK_621_TRUE = 0x1
+ // .. ==> 0XF80001C4[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // ..
+ EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
+ // .. DMA_CPU_2XCLKACT = 0x1
+ // .. ==> 0XF800012C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. USB0_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. USB1_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[3:3] = 0x00000001U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000008U
+ // .. GEM0_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[6:6] = 0x00000001U
+ // .. ==> MASK : 0x00000040U VAL : 0x00000040U
+ // .. GEM1_CPU_1XCLKACT = 0x0
+ // .. ==> 0XF800012C[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. SDI0_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[10:10] = 0x00000001U
+ // .. ==> MASK : 0x00000400U VAL : 0x00000400U
+ // .. SDI1_CPU_1XCLKACT = 0x0
+ // .. ==> 0XF800012C[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. SPI0_CPU_1XCLKACT = 0x0
+ // .. ==> 0XF800012C[14:14] = 0x00000000U
+ // .. ==> MASK : 0x00004000U VAL : 0x00000000U
+ // .. SPI1_CPU_1XCLKACT = 0x0
+ // .. ==> 0XF800012C[15:15] = 0x00000000U
+ // .. ==> MASK : 0x00008000U VAL : 0x00000000U
+ // .. CAN0_CPU_1XCLKACT = 0x0
+ // .. ==> 0XF800012C[16:16] = 0x00000000U
+ // .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. CAN1_CPU_1XCLKACT = 0x0
+ // .. ==> 0XF800012C[17:17] = 0x00000000U
+ // .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. I2C0_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[18:18] = 0x00000001U
+ // .. ==> MASK : 0x00040000U VAL : 0x00040000U
+ // .. I2C1_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[19:19] = 0x00000001U
+ // .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // .. UART0_CPU_1XCLKACT = 0x0
+ // .. ==> 0XF800012C[20:20] = 0x00000000U
+ // .. ==> MASK : 0x00100000U VAL : 0x00000000U
+ // .. UART1_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[21:21] = 0x00000001U
+ // .. ==> MASK : 0x00200000U VAL : 0x00200000U
+ // .. GPIO_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[22:22] = 0x00000001U
+ // .. ==> MASK : 0x00400000U VAL : 0x00400000U
+ // .. LQSPI_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[23:23] = 0x00000001U
+ // .. ==> MASK : 0x00800000U VAL : 0x00800000U
+ // .. SMC_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[24:24] = 0x00000001U
+ // .. ==> MASK : 0x01000000U VAL : 0x01000000U
+ // ..
+ EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC044DU),
+ // .. FINISH: CLOCK CONTROL SLCR REGISTERS
+ // .. START: THIS SHOULD BE BLANK
+ // .. FINISH: THIS SHOULD BE BLANK
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_ddr_init_data_2_0[] = {
+ // START: top
+ // .. START: DDR INITIALIZATION
+ // .. .. START: LOCK DDR
+ // .. .. reg_ddrc_soft_rstb = 0
+ // .. .. ==> 0XF8006000[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_powerdown_en = 0x0
+ // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_ddrc_data_bus_width = 0x0
+ // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U
+ // .. .. reg_ddrc_burst8_refresh = 0x0
+ // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U
+ // .. .. reg_ddrc_rdwr_idle_gap = 0x1
+ // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+ // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U
+ // .. .. reg_ddrc_dis_rd_bypass = 0x0
+ // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+ // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_act_bypass = 0x0
+ // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_auto_refresh = 0x0
+ // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
+ // .. .. FINISH: LOCK DDR
+ // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81
+ // .. .. ==> 0XF8006004[11:0] = 0x00000081U
+ // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U
+ // .. .. reg_ddrc_active_ranks = 0x1
+ // .. .. ==> 0XF8006004[13:12] = 0x00000001U
+ // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U
+ // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
+ // .. .. ==> 0XF8006004[18:14] = 0x00000000U
+ // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U
+ // .. .. reg_ddrc_wr_odt_block = 0x1
+ // .. .. ==> 0XF8006004[20:19] = 0x00000001U
+ // .. .. ==> MASK : 0x00180000U VAL : 0x00080000U
+ // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0
+ // .. .. ==> 0XF8006004[21:21] = 0x00000000U
+ // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0
+ // .. .. ==> 0XF8006004[26:22] = 0x00000000U
+ // .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_open_bank = 0x0
+ // .. .. ==> 0XF8006004[27:27] = 0x00000000U
+ // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_4bank_ram = 0x0
+ // .. .. ==> 0XF8006004[28:28] = 0x00000000U
+ // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U),
+ // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
+ // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU
+ // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
+ // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
+ // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U
+ // .. .. reg_ddrc_hpr_xact_run_length = 0xf
+ // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
+ // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
+ // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
+ // .. .. ==> 0XF800600C[10:0] = 0x00000001U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U
+ // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
+ // .. .. ==> 0XF800600C[21:11] = 0x00000002U
+ // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U
+ // .. .. reg_ddrc_lpr_xact_run_length = 0x8
+ // .. .. ==> 0XF800600C[25:22] = 0x00000008U
+ // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
+ // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
+ // .. .. ==> 0XF8006010[10:0] = 0x00000001U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U
+ // .. .. reg_ddrc_w_xact_run_length = 0x8
+ // .. .. ==> 0XF8006010[14:11] = 0x00000008U
+ // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U
+ // .. .. reg_ddrc_w_max_starve_x32 = 0x2
+ // .. .. ==> 0XF8006010[25:15] = 0x00000002U
+ // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
+ // .. .. reg_ddrc_t_rc = 0x1a
+ // .. .. ==> 0XF8006014[5:0] = 0x0000001AU
+ // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001AU
+ // .. .. reg_ddrc_t_rfc_min = 0xa0
+ // .. .. ==> 0XF8006014[13:6] = 0x000000A0U
+ // .. .. ==> MASK : 0x00003FC0U VAL : 0x00002800U
+ // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
+ // .. .. ==> 0XF8006014[20:14] = 0x00000010U
+ // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281AU),
+ // .. .. reg_ddrc_wr2pre = 0x12
+ // .. .. ==> 0XF8006018[4:0] = 0x00000012U
+ // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U
+ // .. .. reg_ddrc_powerdown_to_x32 = 0x6
+ // .. .. ==> 0XF8006018[9:5] = 0x00000006U
+ // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U
+ // .. .. reg_ddrc_t_faw = 0x16
+ // .. .. ==> 0XF8006018[15:10] = 0x00000016U
+ // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005800U
+ // .. .. reg_ddrc_t_ras_max = 0x24
+ // .. .. ==> 0XF8006018[21:16] = 0x00000024U
+ // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U
+ // .. .. reg_ddrc_t_ras_min = 0x13
+ // .. .. ==> 0XF8006018[26:22] = 0x00000013U
+ // .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U
+ // .. .. reg_ddrc_t_cke = 0x4
+ // .. .. ==> 0XF8006018[31:28] = 0x00000004U
+ // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D2U),
+ // .. .. reg_ddrc_write_latency = 0x5
+ // .. .. ==> 0XF800601C[4:0] = 0x00000005U
+ // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U
+ // .. .. reg_ddrc_rd2wr = 0x7
+ // .. .. ==> 0XF800601C[9:5] = 0x00000007U
+ // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U
+ // .. .. reg_ddrc_wr2rd = 0xe
+ // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
+ // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U
+ // .. .. reg_ddrc_t_xp = 0x4
+ // .. .. ==> 0XF800601C[19:15] = 0x00000004U
+ // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U
+ // .. .. reg_ddrc_pad_pd = 0x0
+ // .. .. ==> 0XF800601C[22:20] = 0x00000000U
+ // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U
+ // .. .. reg_ddrc_rd2pre = 0x4
+ // .. .. ==> 0XF800601C[27:23] = 0x00000004U
+ // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U
+ // .. .. reg_ddrc_t_rcd = 0x7
+ // .. .. ==> 0XF800601C[31:28] = 0x00000007U
+ // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
+ // .. .. reg_ddrc_t_ccd = 0x4
+ // .. .. ==> 0XF8006020[4:2] = 0x00000004U
+ // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U
+ // .. .. reg_ddrc_t_rrd = 0x6
+ // .. .. ==> 0XF8006020[7:5] = 0x00000006U
+ // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U
+ // .. .. reg_ddrc_refresh_margin = 0x2
+ // .. .. ==> 0XF8006020[11:8] = 0x00000002U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
+ // .. .. reg_ddrc_t_rp = 0x7
+ // .. .. ==> 0XF8006020[15:12] = 0x00000007U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U
+ // .. .. reg_ddrc_refresh_to_x32 = 0x8
+ // .. .. ==> 0XF8006020[20:16] = 0x00000008U
+ // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U
+ // .. .. reg_ddrc_sdram = 0x1
+ // .. .. ==> 0XF8006020[21:21] = 0x00000001U
+ // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U
+ // .. .. reg_ddrc_mobile = 0x0
+ // .. .. ==> 0XF8006020[22:22] = 0x00000000U
+ // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U
+ // .. .. reg_ddrc_clock_stop_en = 0x0
+ // .. .. ==> 0XF8006020[23:23] = 0x00000000U
+ // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U
+ // .. .. reg_ddrc_read_latency = 0x7
+ // .. .. ==> 0XF8006020[28:24] = 0x00000007U
+ // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U
+ // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
+ // .. .. ==> 0XF8006020[29:29] = 0x00000001U
+ // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U
+ // .. .. reg_ddrc_dis_pad_pd = 0x0
+ // .. .. ==> 0XF8006020[30:30] = 0x00000000U
+ // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_loopback = 0x0
+ // .. .. ==> 0XF8006020[31:31] = 0x00000000U
+ // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U),
+ // .. .. reg_ddrc_en_2t_timing_mode = 0x0
+ // .. .. ==> 0XF8006024[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_prefer_write = 0x0
+ // .. .. ==> 0XF8006024[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_ddrc_max_rank_rd = 0xf
+ // .. .. ==> 0XF8006024[5:2] = 0x0000000FU
+ // .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU
+ // .. .. reg_ddrc_mr_wr = 0x0
+ // .. .. ==> 0XF8006024[6:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr_addr = 0x0
+ // .. .. ==> 0XF8006024[8:7] = 0x00000000U
+ // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr_data = 0x0
+ // .. .. ==> 0XF8006024[24:9] = 0x00000000U
+ // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U
+ // .. .. ddrc_reg_mr_wr_busy = 0x0
+ // .. .. ==> 0XF8006024[25:25] = 0x00000000U
+ // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr_type = 0x0
+ // .. .. ==> 0XF8006024[26:26] = 0x00000000U
+ // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr_rdata_valid = 0x0
+ // .. .. ==> 0XF8006024[27:27] = 0x00000000U
+ // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU),
+ // .. .. reg_ddrc_final_wait_x32 = 0x7
+ // .. .. ==> 0XF8006028[6:0] = 0x00000007U
+ // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U
+ // .. .. reg_ddrc_pre_ocd_x32 = 0x0
+ // .. .. ==> 0XF8006028[10:7] = 0x00000000U
+ // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U
+ // .. .. reg_ddrc_t_mrd = 0x4
+ // .. .. ==> 0XF8006028[13:11] = 0x00000004U
+ // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
+ // .. .. reg_ddrc_emr2 = 0x8
+ // .. .. ==> 0XF800602C[15:0] = 0x00000008U
+ // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U
+ // .. .. reg_ddrc_emr3 = 0x0
+ // .. .. ==> 0XF800602C[31:16] = 0x00000000U
+ // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
+ // .. .. reg_ddrc_mr = 0x930
+ // .. .. ==> 0XF8006030[15:0] = 0x00000930U
+ // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U
+ // .. .. reg_ddrc_emr = 0x4
+ // .. .. ==> 0XF8006030[31:16] = 0x00000004U
+ // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
+ // .. .. reg_ddrc_burst_rdwr = 0x4
+ // .. .. ==> 0XF8006034[3:0] = 0x00000004U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U
+ // .. .. reg_ddrc_pre_cke_x1024 = 0x105
+ // .. .. ==> 0XF8006034[13:4] = 0x00000105U
+ // .. .. ==> MASK : 0x00003FF0U VAL : 0x00001050U
+ // .. .. reg_ddrc_post_cke_x1024 = 0x1
+ // .. .. ==> 0XF8006034[25:16] = 0x00000001U
+ // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U
+ // .. .. reg_ddrc_burstchop = 0x0
+ // .. .. ==> 0XF8006034[28:28] = 0x00000000U
+ // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U),
+ // .. .. reg_ddrc_force_low_pri_n = 0x0
+ // .. .. ==> 0XF8006038[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_dq = 0x0
+ // .. .. ==> 0XF8006038[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_debug_mode = 0x0
+ // .. .. ==> 0XF8006038[6:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U
+ // .. .. reg_phy_wr_level_start = 0x0
+ // .. .. ==> 0XF8006038[7:7] = 0x00000000U
+ // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. .. reg_phy_rd_level_start = 0x0
+ // .. .. ==> 0XF8006038[8:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. .. reg_phy_dq0_wait_t = 0x0
+ // .. .. ==> 0XF8006038[12:9] = 0x00000000U
+ // .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U),
+ // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
+ // .. .. ==> 0XF800603C[3:0] = 0x00000007U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U
+ // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
+ // .. .. ==> 0XF800603C[7:4] = 0x00000007U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U
+ // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
+ // .. .. ==> 0XF800603C[11:8] = 0x00000007U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U
+ // .. .. reg_ddrc_addrmap_col_b5 = 0x0
+ // .. .. ==> 0XF800603C[15:12] = 0x00000000U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b6 = 0x0
+ // .. .. ==> 0XF800603C[19:16] = 0x00000000U
+ // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
+ // .. .. reg_ddrc_addrmap_col_b2 = 0x0
+ // .. .. ==> 0XF8006040[3:0] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b3 = 0x0
+ // .. .. ==> 0XF8006040[7:4] = 0x00000000U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b4 = 0x0
+ // .. .. ==> 0XF8006040[11:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b7 = 0x0
+ // .. .. ==> 0XF8006040[15:12] = 0x00000000U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b8 = 0x0
+ // .. .. ==> 0XF8006040[19:16] = 0x00000000U
+ // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b9 = 0xf
+ // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
+ // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U
+ // .. .. reg_ddrc_addrmap_col_b10 = 0xf
+ // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
+ // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U
+ // .. .. reg_ddrc_addrmap_col_b11 = 0xf
+ // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
+ // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
+ // .. .. reg_ddrc_addrmap_row_b0 = 0x6
+ // .. .. ==> 0XF8006044[3:0] = 0x00000006U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U
+ // .. .. reg_ddrc_addrmap_row_b1 = 0x6
+ // .. .. ==> 0XF8006044[7:4] = 0x00000006U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U
+ // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
+ // .. .. ==> 0XF8006044[11:8] = 0x00000006U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U
+ // .. .. reg_ddrc_addrmap_row_b12 = 0x6
+ // .. .. ==> 0XF8006044[15:12] = 0x00000006U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U
+ // .. .. reg_ddrc_addrmap_row_b13 = 0x6
+ // .. .. ==> 0XF8006044[19:16] = 0x00000006U
+ // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U
+ // .. .. reg_ddrc_addrmap_row_b14 = 0x6
+ // .. .. ==> 0XF8006044[23:20] = 0x00000006U
+ // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U
+ // .. .. reg_ddrc_addrmap_row_b15 = 0xf
+ // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
+ // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U),
+ // .. .. reg_ddrc_rank0_rd_odt = 0x0
+ // .. .. ==> 0XF8006048[2:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U
+ // .. .. reg_ddrc_rank0_wr_odt = 0x1
+ // .. .. ==> 0XF8006048[5:3] = 0x00000001U
+ // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U
+ // .. .. reg_ddrc_rank1_rd_odt = 0x1
+ // .. .. ==> 0XF8006048[8:6] = 0x00000001U
+ // .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U
+ // .. .. reg_ddrc_rank1_wr_odt = 0x1
+ // .. .. ==> 0XF8006048[11:9] = 0x00000001U
+ // .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. .. reg_phy_rd_local_odt = 0x0
+ // .. .. ==> 0XF8006048[13:12] = 0x00000000U
+ // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U
+ // .. .. reg_phy_wr_local_odt = 0x3
+ // .. .. ==> 0XF8006048[15:14] = 0x00000003U
+ // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U
+ // .. .. reg_phy_idle_local_odt = 0x3
+ // .. .. ==> 0XF8006048[17:16] = 0x00000003U
+ // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U
+ // .. .. reg_ddrc_rank2_rd_odt = 0x0
+ // .. .. ==> 0XF8006048[20:18] = 0x00000000U
+ // .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U
+ // .. .. reg_ddrc_rank2_wr_odt = 0x0
+ // .. .. ==> 0XF8006048[23:21] = 0x00000000U
+ // .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U
+ // .. .. reg_ddrc_rank3_rd_odt = 0x0
+ // .. .. ==> 0XF8006048[26:24] = 0x00000000U
+ // .. .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_rank3_wr_odt = 0x0
+ // .. .. ==> 0XF8006048[29:27] = 0x00000000U
+ // .. .. ==> MASK : 0x38000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U),
+ // .. .. reg_phy_rd_cmd_to_data = 0x0
+ // .. .. ==> 0XF8006050[3:0] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
+ // .. .. reg_phy_wr_cmd_to_data = 0x0
+ // .. .. ==> 0XF8006050[7:4] = 0x00000000U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. .. reg_phy_rdc_we_to_re_delay = 0x8
+ // .. .. ==> 0XF8006050[11:8] = 0x00000008U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U
+ // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
+ // .. .. ==> 0XF8006050[15:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
+ // .. .. reg_phy_use_fixed_re = 0x1
+ // .. .. ==> 0XF8006050[16:16] = 0x00000001U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U
+ // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
+ // .. .. ==> 0XF8006050[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
+ // .. .. ==> 0XF8006050[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_phy_clk_stall_level = 0x0
+ // .. .. ==> 0XF8006050[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
+ // .. .. ==> 0XF8006050[27:24] = 0x00000007U
+ // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U
+ // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
+ // .. .. ==> 0XF8006050[31:28] = 0x00000007U
+ // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
+ // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1
+ // .. .. ==> 0XF8006058[7:0] = 0x00000001U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U
+ // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1
+ // .. .. ==> 0XF8006058[15:8] = 0x00000001U
+ // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U
+ // .. .. reg_ddrc_dis_dll_calib = 0x0
+ // .. .. ==> 0XF8006058[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U),
+ // .. .. reg_ddrc_rd_odt_delay = 0x3
+ // .. .. ==> 0XF800605C[3:0] = 0x00000003U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U
+ // .. .. reg_ddrc_wr_odt_delay = 0x0
+ // .. .. ==> 0XF800605C[7:4] = 0x00000000U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. .. reg_ddrc_rd_odt_hold = 0x0
+ // .. .. ==> 0XF800605C[11:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U
+ // .. .. reg_ddrc_wr_odt_hold = 0x5
+ // .. .. ==> 0XF800605C[15:12] = 0x00000005U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
+ // .. .. reg_ddrc_pageclose = 0x0
+ // .. .. ==> 0XF8006060[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_lpr_num_entries = 0x1f
+ // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
+ // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU
+ // .. .. reg_ddrc_auto_pre_en = 0x0
+ // .. .. ==> 0XF8006060[7:7] = 0x00000000U
+ // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. .. reg_ddrc_refresh_update_level = 0x0
+ // .. .. ==> 0XF8006060[8:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_wc = 0x0
+ // .. .. ==> 0XF8006060[9:9] = 0x00000000U
+ // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_collision_page_opt = 0x0
+ // .. .. ==> 0XF8006060[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_ddrc_selfref_en = 0x0
+ // .. .. ==> 0XF8006060[12:12] = 0x00000000U
+ // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
+ // .. .. reg_ddrc_go2critical_hysteresis = 0x0
+ // .. .. ==> 0XF8006064[12:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U
+ // .. .. reg_arb_go2critical_en = 0x1
+ // .. .. ==> 0XF8006064[17:17] = 0x00000001U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
+ // .. .. reg_ddrc_wrlvl_ww = 0x41
+ // .. .. ==> 0XF8006068[7:0] = 0x00000041U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U
+ // .. .. reg_ddrc_rdlvl_rr = 0x41
+ // .. .. ==> 0XF8006068[15:8] = 0x00000041U
+ // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U
+ // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
+ // .. .. ==> 0XF8006068[25:16] = 0x00000028U
+ // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
+ // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
+ // .. .. ==> 0XF800606C[7:0] = 0x00000010U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U
+ // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
+ // .. .. ==> 0XF800606C[15:8] = 0x00000016U
+ // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U
+ // .. ..
+ EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
+ // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1
+ // .. .. ==> 0XF8006078[3:0] = 0x00000001U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U
+ // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1
+ // .. .. ==> 0XF8006078[7:4] = 0x00000001U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U
+ // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1
+ // .. .. ==> 0XF8006078[11:8] = 0x00000001U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U
+ // .. .. reg_ddrc_t_cksre = 0x6
+ // .. .. ==> 0XF8006078[15:12] = 0x00000006U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U
+ // .. .. reg_ddrc_t_cksrx = 0x6
+ // .. .. ==> 0XF8006078[19:16] = 0x00000006U
+ // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U
+ // .. .. reg_ddrc_t_ckesr = 0x4
+ // .. .. ==> 0XF8006078[25:20] = 0x00000004U
+ // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U),
+ // .. .. reg_ddrc_t_ckpde = 0x2
+ // .. .. ==> 0XF800607C[3:0] = 0x00000002U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U
+ // .. .. reg_ddrc_t_ckpdx = 0x2
+ // .. .. ==> 0XF800607C[7:4] = 0x00000002U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
+ // .. .. reg_ddrc_t_ckdpde = 0x2
+ // .. .. ==> 0XF800607C[11:8] = 0x00000002U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
+ // .. .. reg_ddrc_t_ckdpdx = 0x2
+ // .. .. ==> 0XF800607C[15:12] = 0x00000002U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U
+ // .. .. reg_ddrc_t_ckcsx = 0x3
+ // .. .. ==> 0XF800607C[19:16] = 0x00000003U
+ // .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U),
+ // .. .. refresh_timer0_start_value_x32 = 0x0
+ // .. .. ==> 0XF80060A0[11:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U
+ // .. .. refresh_timer1_start_value_x32 = 0x8
+ // .. .. ==> 0XF80060A0[23:12] = 0x00000008U
+ // .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U),
+ // .. .. reg_ddrc_dis_auto_zq = 0x0
+ // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_ddr3 = 0x1
+ // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. .. reg_ddrc_t_mod = 0x200
+ // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
+ // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U
+ // .. .. reg_ddrc_t_zq_long_nop = 0x200
+ // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U
+ // .. .. reg_ddrc_t_zq_short_nop = 0x40
+ // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
+ // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
+ // .. .. t_zq_short_interval_x1024 = 0xcb73
+ // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U
+ // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U
+ // .. .. dram_rstn_x1024 = 0x69
+ // .. .. ==> 0XF80060A8[27:20] = 0x00000069U
+ // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
+ // .. .. deeppowerdown_en = 0x0
+ // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. deeppowerdown_to_x1024 = 0xff
+ // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
+ // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU
+ // .. ..
+ EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
+ // .. .. dfi_wrlvl_max_x1024 = 0xfff
+ // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
+ // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU
+ // .. .. dfi_rdlvl_max_x1024 = 0xfff
+ // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
+ // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U
+ // .. .. ddrc_reg_twrlvl_max_error = 0x0
+ // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
+ // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U
+ // .. .. ddrc_reg_trdlvl_max_error = 0x0
+ // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
+ // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dfi_wr_level_en = 0x1
+ // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
+ // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U
+ // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
+ // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
+ // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U
+ // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
+ // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
+ // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
+ // .. .. reg_ddrc_2t_delay = 0x0
+ // .. .. ==> 0XF80060B4[8:0] = 0x00000000U
+ // .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U
+ // .. .. reg_ddrc_skip_ocd = 0x1
+ // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
+ // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U
+ // .. .. reg_ddrc_dis_pre_bypass = 0x0
+ // .. .. ==> 0XF80060B4[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U),
+ // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
+ // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
+ // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U
+ // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
+ // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
+ // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U
+ // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
+ // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
+ // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
+ // .. .. START: RESET ECC ERROR
+ // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1
+ // .. .. ==> 0XF80060C4[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. Clear_Correctable_DRAM_ECC_error = 1
+ // .. .. ==> 0XF80060C4[1:1] = 0x00000001U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U),
+ // .. .. FINISH: RESET ECC ERROR
+ // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
+ // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
+ // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
+ // .. .. CORR_ECC_LOG_VALID = 0x0
+ // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. ECC_CORRECTED_BIT_NUM = 0x0
+ // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
+ // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
+ // .. .. UNCORR_ECC_LOG_VALID = 0x0
+ // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
+ // .. .. STAT_NUM_CORR_ERR = 0x0
+ // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
+ // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U
+ // .. .. STAT_NUM_UNCORR_ERR = 0x0
+ // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
+ // .. .. reg_ddrc_ecc_mode = 0x0
+ // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_scrub = 0x1
+ // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
+ // .. .. reg_phy_dif_on = 0x0
+ // .. .. ==> 0XF8006114[3:0] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
+ // .. .. reg_phy_dif_off = 0x0
+ // .. .. ==> 0XF8006114[7:4] = 0x00000000U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
+ // .. .. reg_phy_data_slice_in_use = 0x1
+ // .. .. ==> 0XF8006118[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_phy_rdlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006118[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006118[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_wrlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006118[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_tx = 0x0
+ // .. .. ==> 0XF8006118[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_rx = 0x0
+ // .. .. ==> 0XF8006118[5:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
+ // .. .. reg_phy_bist_shift_dq = 0x0
+ // .. .. ==> 0XF8006118[14:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
+ // .. .. reg_phy_bist_err_clr = 0x0
+ // .. .. ==> 0XF8006118[23:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
+ // .. .. reg_phy_dq_offset = 0x40
+ // .. .. ==> 0XF8006118[30:24] = 0x00000040U
+ // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U),
+ // .. .. reg_phy_data_slice_in_use = 0x1
+ // .. .. ==> 0XF800611C[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_phy_rdlvl_inc_mode = 0x0
+ // .. .. ==> 0XF800611C[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_inc_mode = 0x0
+ // .. .. ==> 0XF800611C[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_wrlvl_inc_mode = 0x0
+ // .. .. ==> 0XF800611C[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_tx = 0x0
+ // .. .. ==> 0XF800611C[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_rx = 0x0
+ // .. .. ==> 0XF800611C[5:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
+ // .. .. reg_phy_bist_shift_dq = 0x0
+ // .. .. ==> 0XF800611C[14:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
+ // .. .. reg_phy_bist_err_clr = 0x0
+ // .. .. ==> 0XF800611C[23:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
+ // .. .. reg_phy_dq_offset = 0x40
+ // .. .. ==> 0XF800611C[30:24] = 0x00000040U
+ // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U),
+ // .. .. reg_phy_data_slice_in_use = 0x1
+ // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_phy_rdlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_wrlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_tx = 0x0
+ // .. .. ==> 0XF8006120[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_rx = 0x0
+ // .. .. ==> 0XF8006120[5:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
+ // .. .. reg_phy_bist_shift_dq = 0x0
+ // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
+ // .. .. reg_phy_bist_err_clr = 0x0
+ // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
+ // .. .. reg_phy_dq_offset = 0x40
+ // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+ // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
+ // .. .. reg_phy_data_slice_in_use = 0x1
+ // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_phy_rdlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_wrlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_tx = 0x0
+ // .. .. ==> 0XF8006120[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_rx = 0x0
+ // .. .. ==> 0XF8006120[5:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
+ // .. .. reg_phy_bist_shift_dq = 0x0
+ // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
+ // .. .. reg_phy_bist_err_clr = 0x0
+ // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
+ // .. .. reg_phy_dq_offset = 0x40
+ // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+ // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U),
+ // .. .. reg_phy_data_slice_in_use = 0x1
+ // .. .. ==> 0XF8006124[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_phy_rdlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006124[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006124[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_wrlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006124[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_tx = 0x0
+ // .. .. ==> 0XF8006124[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_rx = 0x0
+ // .. .. ==> 0XF8006124[5:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
+ // .. .. reg_phy_bist_shift_dq = 0x0
+ // .. .. ==> 0XF8006124[14:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
+ // .. .. reg_phy_bist_err_clr = 0x0
+ // .. .. ==> 0XF8006124[23:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
+ // .. .. reg_phy_dq_offset = 0x40
+ // .. .. ==> 0XF8006124[30:24] = 0x00000040U
+ // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U),
+ // .. .. reg_phy_wrlvl_init_ratio = 0x0
+ // .. .. ==> 0XF800612C[9:0] = 0x00000000U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_init_ratio = 0xb0
+ // .. .. ==> 0XF800612C[19:10] = 0x000000B0U
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002C000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0002C000U),
+ // .. .. reg_phy_wrlvl_init_ratio = 0x0
+ // .. .. ==> 0XF8006130[9:0] = 0x00000000U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_init_ratio = 0xb1
+ // .. .. ==> 0XF8006130[19:10] = 0x000000B1U
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002C400U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x0002C400U),
+ // .. .. reg_phy_wrlvl_init_ratio = 0x3
+ // .. .. ==> 0XF8006134[9:0] = 0x00000003U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000003U
+ // .. .. reg_phy_gatelvl_init_ratio = 0xbc
+ // .. .. ==> 0XF8006134[19:10] = 0x000000BCU
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002F000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0002F003U),
+ // .. .. reg_phy_wrlvl_init_ratio = 0x3
+ // .. .. ==> 0XF8006138[9:0] = 0x00000003U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000003U
+ // .. .. reg_phy_gatelvl_init_ratio = 0xbb
+ // .. .. ==> 0XF8006138[19:10] = 0x000000BBU
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002EC00U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0002EC03U),
+ // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+ // .. .. ==> 0XF8006140[9:0] = 0x00000035U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
+ // .. .. reg_phy_rd_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006140[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006140[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
+ // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+ // .. .. ==> 0XF8006144[9:0] = 0x00000035U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
+ // .. .. reg_phy_rd_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006144[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006144[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
+ // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+ // .. .. ==> 0XF8006148[9:0] = 0x00000035U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
+ // .. .. reg_phy_rd_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006148[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006148[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
+ // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+ // .. .. ==> 0XF800614C[9:0] = 0x00000035U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
+ // .. .. reg_phy_rd_dqs_slave_force = 0x0
+ // .. .. ==> 0XF800614C[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF800614C[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
+ // .. .. reg_phy_wr_dqs_slave_ratio = 0x77
+ // .. .. ==> 0XF8006154[9:0] = 0x00000077U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000077U
+ // .. .. reg_phy_wr_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006154[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006154[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000077U),
+ // .. .. reg_phy_wr_dqs_slave_ratio = 0x77
+ // .. .. ==> 0XF8006158[9:0] = 0x00000077U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000077U
+ // .. .. reg_phy_wr_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006158[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006158[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000077U),
+ // .. .. reg_phy_wr_dqs_slave_ratio = 0x83
+ // .. .. ==> 0XF800615C[9:0] = 0x00000083U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000083U
+ // .. .. reg_phy_wr_dqs_slave_force = 0x0
+ // .. .. ==> 0XF800615C[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF800615C[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000083U),
+ // .. .. reg_phy_wr_dqs_slave_ratio = 0x83
+ // .. .. ==> 0XF8006160[9:0] = 0x00000083U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000083U
+ // .. .. reg_phy_wr_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006160[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006160[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000083U),
+ // .. .. reg_phy_fifo_we_slave_ratio = 0x105
+ // .. .. ==> 0XF8006168[10:0] = 0x00000105U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000105U
+ // .. .. reg_phy_fifo_we_in_force = 0x0
+ // .. .. ==> 0XF8006168[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. reg_phy_fifo_we_in_delay = 0x0
+ // .. .. ==> 0XF8006168[20:12] = 0x00000000U
+ // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000105U),
+ // .. .. reg_phy_fifo_we_slave_ratio = 0x106
+ // .. .. ==> 0XF800616C[10:0] = 0x00000106U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000106U
+ // .. .. reg_phy_fifo_we_in_force = 0x0
+ // .. .. ==> 0XF800616C[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. reg_phy_fifo_we_in_delay = 0x0
+ // .. .. ==> 0XF800616C[20:12] = 0x00000000U
+ // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x00000106U),
+ // .. .. reg_phy_fifo_we_slave_ratio = 0x111
+ // .. .. ==> 0XF8006170[10:0] = 0x00000111U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000111U
+ // .. .. reg_phy_fifo_we_in_force = 0x0
+ // .. .. ==> 0XF8006170[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. reg_phy_fifo_we_in_delay = 0x0
+ // .. .. ==> 0XF8006170[20:12] = 0x00000000U
+ // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000111U),
+ // .. .. reg_phy_fifo_we_slave_ratio = 0x110
+ // .. .. ==> 0XF8006174[10:0] = 0x00000110U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000110U
+ // .. .. reg_phy_fifo_we_in_force = 0x0
+ // .. .. ==> 0XF8006174[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. reg_phy_fifo_we_in_delay = 0x0
+ // .. .. ==> 0XF8006174[20:12] = 0x00000000U
+ // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000110U),
+ // .. .. reg_phy_wr_data_slave_ratio = 0xb7
+ // .. .. ==> 0XF800617C[9:0] = 0x000000B7U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000B7U
+ // .. .. reg_phy_wr_data_slave_force = 0x0
+ // .. .. ==> 0XF800617C[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_data_slave_delay = 0x0
+ // .. .. ==> 0XF800617C[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000B7U),
+ // .. .. reg_phy_wr_data_slave_ratio = 0xb7
+ // .. .. ==> 0XF8006180[9:0] = 0x000000B7U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000B7U
+ // .. .. reg_phy_wr_data_slave_force = 0x0
+ // .. .. ==> 0XF8006180[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_data_slave_delay = 0x0
+ // .. .. ==> 0XF8006180[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000B7U),
+ // .. .. reg_phy_wr_data_slave_ratio = 0xc3
+ // .. .. ==> 0XF8006184[9:0] = 0x000000C3U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C3U
+ // .. .. reg_phy_wr_data_slave_force = 0x0
+ // .. .. ==> 0XF8006184[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_data_slave_delay = 0x0
+ // .. .. ==> 0XF8006184[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C3U),
+ // .. .. reg_phy_wr_data_slave_ratio = 0xc3
+ // .. .. ==> 0XF8006188[9:0] = 0x000000C3U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C3U
+ // .. .. reg_phy_wr_data_slave_force = 0x0
+ // .. .. ==> 0XF8006188[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_data_slave_delay = 0x0
+ // .. .. ==> 0XF8006188[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C3U),
+ // .. .. reg_phy_loopback = 0x0
+ // .. .. ==> 0XF8006190[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_phy_bl2 = 0x0
+ // .. .. ==> 0XF8006190[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_at_spd_atpg = 0x0
+ // .. .. ==> 0XF8006190[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_bist_enable = 0x0
+ // .. .. ==> 0XF8006190[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_bist_force_err = 0x0
+ // .. .. ==> 0XF8006190[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reg_phy_bist_mode = 0x0
+ // .. .. ==> 0XF8006190[6:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U
+ // .. .. reg_phy_invert_clkout = 0x1
+ // .. .. ==> 0XF8006190[7:7] = 0x00000001U
+ // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0
+ // .. .. ==> 0XF8006190[8:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. .. reg_phy_sel_logic = 0x0
+ // .. .. ==> 0XF8006190[9:9] = 0x00000000U
+ // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U
+ // .. .. reg_phy_ctrl_slave_ratio = 0x100
+ // .. .. ==> 0XF8006190[19:10] = 0x00000100U
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U
+ // .. .. reg_phy_ctrl_slave_force = 0x0
+ // .. .. ==> 0XF8006190[20:20] = 0x00000000U
+ // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U
+ // .. .. reg_phy_ctrl_slave_delay = 0x0
+ // .. .. ==> 0XF8006190[27:21] = 0x00000000U
+ // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U
+ // .. .. reg_phy_use_rank0_delays = 0x1
+ // .. .. ==> 0XF8006190[28:28] = 0x00000001U
+ // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
+ // .. .. reg_phy_lpddr = 0x0
+ // .. .. ==> 0XF8006190[29:29] = 0x00000000U
+ // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U
+ // .. .. reg_phy_cmd_latency = 0x0
+ // .. .. ==> 0XF8006190[30:30] = 0x00000000U
+ // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U
+ // .. .. reg_phy_int_lpbk = 0x0
+ // .. .. ==> 0XF8006190[31:31] = 0x00000000U
+ // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U),
+ // .. .. reg_phy_wr_rl_delay = 0x2
+ // .. .. ==> 0XF8006194[4:0] = 0x00000002U
+ // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U
+ // .. .. reg_phy_rd_rl_delay = 0x4
+ // .. .. ==> 0XF8006194[9:5] = 0x00000004U
+ // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U
+ // .. .. reg_phy_dll_lock_diff = 0xf
+ // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
+ // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U
+ // .. .. reg_phy_use_wr_level = 0x1
+ // .. .. ==> 0XF8006194[14:14] = 0x00000001U
+ // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U
+ // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
+ // .. .. ==> 0XF8006194[15:15] = 0x00000001U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U
+ // .. .. reg_phy_use_rd_data_eye_level = 0x1
+ // .. .. ==> 0XF8006194[16:16] = 0x00000001U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U
+ // .. .. reg_phy_dis_calib_rst = 0x0
+ // .. .. ==> 0XF8006194[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_phy_ctrl_slave_delay = 0x0
+ // .. .. ==> 0XF8006194[19:18] = 0x00000000U
+ // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
+ // .. .. reg_arb_page_addr_mask = 0x0
+ // .. .. ==> 0XF8006204[31:0] = 0x00000000U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
+ // .. .. reg_arb_pri_wr_portn = 0x3ff
+ // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_wr_portn = 0x0
+ // .. .. ==> 0XF8006208[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+ // .. .. ==> 0XF8006208[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+ // .. .. ==> 0XF8006208[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_rmw_portn = 0x1
+ // .. .. ==> 0XF8006208[19:19] = 0x00000001U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU),
+ // .. .. reg_arb_pri_wr_portn = 0x3ff
+ // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_wr_portn = 0x0
+ // .. .. ==> 0XF800620C[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+ // .. .. ==> 0XF800620C[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+ // .. .. ==> 0XF800620C[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_rmw_portn = 0x1
+ // .. .. ==> 0XF800620C[19:19] = 0x00000001U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU),
+ // .. .. reg_arb_pri_wr_portn = 0x3ff
+ // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_wr_portn = 0x0
+ // .. .. ==> 0XF8006210[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+ // .. .. ==> 0XF8006210[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+ // .. .. ==> 0XF8006210[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_rmw_portn = 0x1
+ // .. .. ==> 0XF8006210[19:19] = 0x00000001U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU),
+ // .. .. reg_arb_pri_wr_portn = 0x3ff
+ // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_wr_portn = 0x0
+ // .. .. ==> 0XF8006214[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+ // .. .. ==> 0XF8006214[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+ // .. .. ==> 0XF8006214[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_rmw_portn = 0x1
+ // .. .. ==> 0XF8006214[19:19] = 0x00000001U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU),
+ // .. .. reg_arb_pri_rd_portn = 0x3ff
+ // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_rd_portn = 0x0
+ // .. .. ==> 0XF8006218[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+ // .. .. ==> 0XF8006218[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+ // .. .. ==> 0XF8006218[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_set_hpr_rd_portn = 0x0
+ // .. .. ==> 0XF8006218[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
+ // .. .. reg_arb_pri_rd_portn = 0x3ff
+ // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_rd_portn = 0x0
+ // .. .. ==> 0XF800621C[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+ // .. .. ==> 0XF800621C[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+ // .. .. ==> 0XF800621C[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_set_hpr_rd_portn = 0x0
+ // .. .. ==> 0XF800621C[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
+ // .. .. reg_arb_pri_rd_portn = 0x3ff
+ // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_rd_portn = 0x0
+ // .. .. ==> 0XF8006220[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+ // .. .. ==> 0XF8006220[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+ // .. .. ==> 0XF8006220[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_set_hpr_rd_portn = 0x0
+ // .. .. ==> 0XF8006220[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
+ // .. .. reg_arb_pri_rd_portn = 0x3ff
+ // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_rd_portn = 0x0
+ // .. .. ==> 0XF8006224[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+ // .. .. ==> 0XF8006224[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+ // .. .. ==> 0XF8006224[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_set_hpr_rd_portn = 0x0
+ // .. .. ==> 0XF8006224[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
+ // .. .. reg_ddrc_lpddr2 = 0x0
+ // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_per_bank_refresh = 0x0
+ // .. .. ==> 0XF80062A8[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_ddrc_derate_enable = 0x0
+ // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr4_margin = 0x0
+ // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U),
+ // .. .. reg_ddrc_mr4_read_interval = 0x0
+ // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
+ // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
+ // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U
+ // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
+ // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
+ // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U
+ // .. .. reg_ddrc_t_mrw = 0x5
+ // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
+ // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8
+ // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U
+ // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
+ // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
+ // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U
+ // .. ..
+ EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
+ // .. .. START: POLL ON DCI STATUS
+ // .. .. DONE = 1
+ // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
+ // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U
+ // .. ..
+ EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+ // .. .. FINISH: POLL ON DCI STATUS
+ // .. .. START: UNLOCK DDR
+ // .. .. reg_ddrc_soft_rstb = 0x1
+ // .. .. ==> 0XF8006000[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_ddrc_powerdown_en = 0x0
+ // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_ddrc_data_bus_width = 0x0
+ // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U
+ // .. .. reg_ddrc_burst8_refresh = 0x0
+ // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U
+ // .. .. reg_ddrc_rdwr_idle_gap = 1
+ // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+ // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U
+ // .. .. reg_ddrc_dis_rd_bypass = 0x0
+ // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+ // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_act_bypass = 0x0
+ // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_auto_refresh = 0x0
+ // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
+ // .. .. FINISH: UNLOCK DDR
+ // .. .. START: CHECK DDR STATUS
+ // .. .. ddrc_reg_operating_mode = 1
+ // .. .. ==> 0XF8006054[2:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U
+ // .. ..
+ EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+ // .. .. FINISH: CHECK DDR STATUS
+ // .. FINISH: DDR INITIALIZATION
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_mio_init_data_2_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: OCM REMAPPING
+ // .. FINISH: OCM REMAPPING
+ // .. START: DDRIOB SETTINGS
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B40[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x0
+ // .. ==> 0XF8000B40[2:1] = 0x00000000U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000000U
+ // .. DCI_UPDATE = 0x0
+ // .. ==> 0XF8000B40[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x0
+ // .. ==> 0XF8000B40[4:4] = 0x00000000U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. DCR_TYPE = 0x0
+ // .. ==> 0XF8000B40[6:5] = 0x00000000U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000000U
+ // .. IBUF_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B40[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B40[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B40[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B40[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B44[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x0
+ // .. ==> 0XF8000B44[2:1] = 0x00000000U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000000U
+ // .. DCI_UPDATE = 0x0
+ // .. ==> 0XF8000B44[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x0
+ // .. ==> 0XF8000B44[4:4] = 0x00000000U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. DCR_TYPE = 0x0
+ // .. ==> 0XF8000B44[6:5] = 0x00000000U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000000U
+ // .. IBUF_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B44[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B44[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B44[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B44[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B48[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x1
+ // .. ==> 0XF8000B48[2:1] = 0x00000001U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000002U
+ // .. DCI_UPDATE = 0x0
+ // .. ==> 0XF8000B48[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x1
+ // .. ==> 0XF8000B48[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. DCR_TYPE = 0x3
+ // .. ==> 0XF8000B48[6:5] = 0x00000003U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000060U
+ // .. IBUF_DISABLE_MODE = 0
+ // .. ==> 0XF8000B48[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0
+ // .. ==> 0XF8000B48[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B48[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B48[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B4C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x1
+ // .. ==> 0XF8000B4C[2:1] = 0x00000001U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000002U
+ // .. DCI_UPDATE = 0x0
+ // .. ==> 0XF8000B4C[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x1
+ // .. ==> 0XF8000B4C[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. DCR_TYPE = 0x3
+ // .. ==> 0XF8000B4C[6:5] = 0x00000003U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000060U
+ // .. IBUF_DISABLE_MODE = 0
+ // .. ==> 0XF8000B4C[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0
+ // .. ==> 0XF8000B4C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B4C[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B4C[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B50[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x2
+ // .. ==> 0XF8000B50[2:1] = 0x00000002U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000004U
+ // .. DCI_UPDATE = 0x0
+ // .. ==> 0XF8000B50[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x1
+ // .. ==> 0XF8000B50[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. DCR_TYPE = 0x3
+ // .. ==> 0XF8000B50[6:5] = 0x00000003U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000060U
+ // .. IBUF_DISABLE_MODE = 0
+ // .. ==> 0XF8000B50[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0
+ // .. ==> 0XF8000B50[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B50[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B50[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B54[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x2
+ // .. ==> 0XF8000B54[2:1] = 0x00000002U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000004U
+ // .. DCI_UPDATE = 0x0
+ // .. ==> 0XF8000B54[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x1
+ // .. ==> 0XF8000B54[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. DCR_TYPE = 0x3
+ // .. ==> 0XF8000B54[6:5] = 0x00000003U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000060U
+ // .. IBUF_DISABLE_MODE = 0
+ // .. ==> 0XF8000B54[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0
+ // .. ==> 0XF8000B54[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B54[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B54[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B58[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x0
+ // .. ==> 0XF8000B58[2:1] = 0x00000000U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000000U
+ // .. DCI_UPDATE = 0x0
+ // .. ==> 0XF8000B58[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x0
+ // .. ==> 0XF8000B58[4:4] = 0x00000000U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. DCR_TYPE = 0x0
+ // .. ==> 0XF8000B58[6:5] = 0x00000000U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000000U
+ // .. IBUF_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B58[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B58[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B58[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B58[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
+ // .. DRIVE_P = 0x1c
+ // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
+ // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
+ // .. DRIVE_N = 0xc
+ // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
+ // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
+ // .. SLEW_P = 0x3
+ // .. ==> 0XF8000B5C[18:14] = 0x00000003U
+ // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U
+ // .. SLEW_N = 0x3
+ // .. ==> 0XF8000B5C[23:19] = 0x00000003U
+ // .. ==> MASK : 0x00F80000U VAL : 0x00180000U
+ // .. GTL = 0x0
+ // .. ==> 0XF8000B5C[26:24] = 0x00000000U
+ // .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. RTERM = 0x0
+ // .. ==> 0XF8000B5C[31:27] = 0x00000000U
+ // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
+ // .. DRIVE_P = 0x1c
+ // .. ==> 0XF8000B60[6:0] = 0x0000001CU
+ // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
+ // .. DRIVE_N = 0xc
+ // .. ==> 0XF8000B60[13:7] = 0x0000000CU
+ // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
+ // .. SLEW_P = 0x6
+ // .. ==> 0XF8000B60[18:14] = 0x00000006U
+ // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
+ // .. SLEW_N = 0x1f
+ // .. ==> 0XF8000B60[23:19] = 0x0000001FU
+ // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
+ // .. GTL = 0x0
+ // .. ==> 0XF8000B60[26:24] = 0x00000000U
+ // .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. RTERM = 0x0
+ // .. ==> 0XF8000B60[31:27] = 0x00000000U
+ // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
+ // .. DRIVE_P = 0x1c
+ // .. ==> 0XF8000B64[6:0] = 0x0000001CU
+ // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
+ // .. DRIVE_N = 0xc
+ // .. ==> 0XF8000B64[13:7] = 0x0000000CU
+ // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
+ // .. SLEW_P = 0x6
+ // .. ==> 0XF8000B64[18:14] = 0x00000006U
+ // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
+ // .. SLEW_N = 0x1f
+ // .. ==> 0XF8000B64[23:19] = 0x0000001FU
+ // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
+ // .. GTL = 0x0
+ // .. ==> 0XF8000B64[26:24] = 0x00000000U
+ // .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. RTERM = 0x0
+ // .. ==> 0XF8000B64[31:27] = 0x00000000U
+ // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
+ // .. DRIVE_P = 0x1c
+ // .. ==> 0XF8000B68[6:0] = 0x0000001CU
+ // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
+ // .. DRIVE_N = 0xc
+ // .. ==> 0XF8000B68[13:7] = 0x0000000CU
+ // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
+ // .. SLEW_P = 0x6
+ // .. ==> 0XF8000B68[18:14] = 0x00000006U
+ // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
+ // .. SLEW_N = 0x1f
+ // .. ==> 0XF8000B68[23:19] = 0x0000001FU
+ // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
+ // .. GTL = 0x0
+ // .. ==> 0XF8000B68[26:24] = 0x00000000U
+ // .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. RTERM = 0x0
+ // .. ==> 0XF8000B68[31:27] = 0x00000000U
+ // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
+ // .. VREF_INT_EN = 0x1
+ // .. ==> 0XF8000B6C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. VREF_SEL = 0x4
+ // .. ==> 0XF8000B6C[4:1] = 0x00000004U
+ // .. ==> MASK : 0x0000001EU VAL : 0x00000008U
+ // .. VREF_EXT_EN = 0x0
+ // .. ==> 0XF8000B6C[6:5] = 0x00000000U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000000U
+ // .. VREF_PULLUP_EN = 0x0
+ // .. ==> 0XF8000B6C[8:7] = 0x00000000U
+ // .. ==> MASK : 0x00000180U VAL : 0x00000000U
+ // .. REFIO_EN = 0x1
+ // .. ==> 0XF8000B6C[9:9] = 0x00000001U
+ // .. ==> MASK : 0x00000200U VAL : 0x00000200U
+ // .. REFIO_TEST = 0x3
+ // .. ==> 0XF8000B6C[11:10] = 0x00000003U
+ // .. ==> MASK : 0x00000C00U VAL : 0x00000C00U
+ // .. REFIO_PULLUP_EN = 0x0
+ // .. ==> 0XF8000B6C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DRST_B_PULLUP_EN = 0x0
+ // .. ==> 0XF8000B6C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // .. CKE_PULLUP_EN = 0x0
+ // .. ==> 0XF8000B6C[14:14] = 0x00000000U
+ // .. ==> MASK : 0x00004000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000E09U),
+ // .. .. START: ASSERT RESET
+ // .. .. RESET = 1
+ // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. VRN_OUT = 0x1
+ // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U),
+ // .. .. FINISH: ASSERT RESET
+ // .. .. START: DEASSERT RESET
+ // .. .. RESET = 0
+ // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. VRN_OUT = 0x1
+ // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
+ // .. .. FINISH: DEASSERT RESET
+ // .. .. RESET = 0x1
+ // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ENABLE = 0x1
+ // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. .. VRP_TRI = 0x0
+ // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. VRN_TRI = 0x0
+ // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. VRP_OUT = 0x0
+ // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. VRN_OUT = 0x1
+ // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
+ // .. .. NREF_OPT1 = 0x0
+ // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
+ // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U
+ // .. .. NREF_OPT2 = 0x0
+ // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U
+ // .. .. NREF_OPT4 = 0x1
+ // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
+ // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U
+ // .. .. PREF_OPT1 = 0x0
+ // .. .. ==> 0XF8000B70[16:14] = 0x00000000U
+ // .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U
+ // .. .. PREF_OPT2 = 0x0
+ // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
+ // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U
+ // .. .. UPDATE_CONTROL = 0x0
+ // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
+ // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U
+ // .. .. INIT_COMPLETE = 0x0
+ // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
+ // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U
+ // .. .. TST_CLK = 0x0
+ // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
+ // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U
+ // .. .. TST_HLN = 0x0
+ // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
+ // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U
+ // .. .. TST_HLP = 0x0
+ // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
+ // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U
+ // .. .. TST_RST = 0x0
+ // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
+ // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
+ // .. .. INT_DCI_EN = 0x0
+ // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
+ // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U),
+ // .. FINISH: DDRIOB SETTINGS
+ // .. START: MIO PROGRAMMING
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000700[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000700[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000700[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000700[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000700[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000700[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000700[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000700[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000700[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000704[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000704[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000704[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000704[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000704[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000704[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000704[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000704[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000704[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00000602U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000708[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000708[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000708[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000708[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000708[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000708[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000708[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000708[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000708[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000602U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800070C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF800070C[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800070C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800070C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800070C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800070C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF800070C[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF800070C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800070C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000602U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000710[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000710[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000710[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000710[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000710[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000710[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000710[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000710[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000710[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000602U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000714[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000714[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000714[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000714[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000714[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000714[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000714[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000714[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000714[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000602U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000718[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000718[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000718[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000718[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000718[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000718[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000718[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000718[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000718[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000602U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800071C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800071C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800071C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800071C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800071C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800071C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF800071C[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF800071C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800071C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000720[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000720[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000720[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000720[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000720[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000720[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000720[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000720[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000720[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000602U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000724[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000724[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000724[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000724[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000724[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000724[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000724[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000724[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000724[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000728[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000728[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000728[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000728[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000728[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000728[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000728[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000728[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000728[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800072C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800072C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800072C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800072C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800072C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800072C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF800072C[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF800072C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800072C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000730[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000730[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000730[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000730[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000730[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000730[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000730[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000730[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000730[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000734[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000734[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000734[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000734[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000734[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000734[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000734[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000734[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000734[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000738[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000738[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000738[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000738[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000738[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000738[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000738[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000738[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000738[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800073C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800073C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800073C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800073C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800073C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800073C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF800073C[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF800073C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800073C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000740[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000740[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000740[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000740[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000740[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000740[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000740[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000740[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000740[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000744[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000744[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000744[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000744[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000744[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000744[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000744[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000744[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000744[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000748[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000748[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000748[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000748[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000748[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000748[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000748[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000748[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000748[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800074C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF800074C[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800074C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800074C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800074C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800074C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800074C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800074C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800074C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000750[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000750[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000750[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000750[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000750[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000750[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000750[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000750[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000750[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000754[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000754[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000754[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000754[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000754[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000754[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000754[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000754[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000754[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000202U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000758[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000758[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000758[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000758[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000758[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000758[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000758[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000758[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000758[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000203U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF800075C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF800075C[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800075C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800075C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800075C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800075C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800075C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800075C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800075C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000203U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000760[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000760[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000760[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000760[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000760[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000760[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000760[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000760[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000760[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000203U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000764[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000764[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000764[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000764[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000764[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000764[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000764[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000764[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000764[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000203U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000768[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000768[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000768[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000768[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000768[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000768[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000768[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000768[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000768[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000203U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF800076C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF800076C[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800076C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800076C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800076C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800076C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800076C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800076C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800076C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000203U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000770[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000770[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000770[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000770[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000770[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000770[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000770[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000770[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000770[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000774[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000774[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000774[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000774[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000774[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000774[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000774[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000774[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000774[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000778[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000778[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000778[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000778[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000778[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000778[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000778[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000778[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000778[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF800077C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800077C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF800077C[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800077C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800077C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800077C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800077C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800077C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800077C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000780[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000780[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000780[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000780[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000780[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000780[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000780[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000780[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000780[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000784[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000784[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000784[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000784[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000784[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000784[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000784[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000784[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000784[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000788[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000788[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000788[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000788[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000788[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000788[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000788[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000788[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000788[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800078C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800078C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF800078C[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800078C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800078C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800078C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800078C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800078C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800078C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000790[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000790[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000790[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000790[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000790[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000790[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000790[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000790[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000790[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000794[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000794[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000794[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000794[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000794[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000794[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000794[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000794[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000794[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000798[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000798[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000798[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000798[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000798[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000798[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000798[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000798[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000798[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800079C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800079C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF800079C[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800079C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800079C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800079C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800079C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800079C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800079C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007A0[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007A0[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007A0[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007A0[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007A0[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007A0[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007A0[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007A0[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007A0[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007A4[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007A4[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007A4[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007A4[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007A4[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007A4[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007A4[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007A4[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007A4[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007A8[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007A8[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007A8[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007A8[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007A8[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007A8[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007A8[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007A8[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007A8[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007AC[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007AC[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007AC[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007AC[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007AC[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007AC[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007AC[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007AC[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007AC[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007B0[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007B0[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007B0[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007B0[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007B0[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007B0[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007B0[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007B0[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007B0[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007B4[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007B4[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007B4[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007B4[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007B4[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007B4[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007B4[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007B4[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007B4[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000280U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF80007B8[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. Speed = 0
+ // .. ==> 0XF80007B8[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007B8[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007B8[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007B8[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007B8, 0x00003F01U ,0x00000201U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007BC[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007BC[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007BC[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007BC[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF80007BC[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF80007BC[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007BC[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007BC[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007BC[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00000200U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007C0[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007C0[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007C0[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007C0[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 7
+ // .. ==> 0XF80007C0[7:5] = 0x00000007U
+ // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U
+ // .. Speed = 0
+ // .. ==> 0XF80007C0[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007C0[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007C0[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007C0[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF80007C4[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007C4[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007C4[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007C4[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 7
+ // .. ==> 0XF80007C4[7:5] = 0x00000007U
+ // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U
+ // .. Speed = 0
+ // .. ==> 0XF80007C4[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007C4[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007C4[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007C4[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF80007C8[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. Speed = 0
+ // .. ==> 0XF80007C8[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007C8[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007C8[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007C8[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007C8, 0x00003F01U ,0x00000201U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007CC[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007CC[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007CC[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007CC[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF80007CC[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF80007CC[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007CC[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007CC[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007CC[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00000200U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007D0[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007D0[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007D0[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007D0[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007D0[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007D0[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007D0[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007D0[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007D0[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007D4[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007D4[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007D4[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007D4[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007D4[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007D4[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007D4[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007D4[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007D4[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U),
+ // .. SDIO0_WP_SEL = 50
+ // .. ==> 0XF8000830[5:0] = 0x00000032U
+ // .. ==> MASK : 0x0000003FU VAL : 0x00000032U
+ // .. SDIO0_CD_SEL = 46
+ // .. ==> 0XF8000830[21:16] = 0x0000002EU
+ // .. ==> MASK : 0x003F0000U VAL : 0x002E0000U
+ // ..
+ EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x002E0032U),
+ // .. FINISH: MIO PROGRAMMING
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_peripherals_init_data_2_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+ // .. IBUF_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B48[7:7] = 0x00000001U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. TERM_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B48[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // ..
+ EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
+ // .. IBUF_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B4C[7:7] = 0x00000001U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. TERM_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B4C[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // ..
+ EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
+ // .. IBUF_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B50[7:7] = 0x00000001U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. TERM_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B50[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // ..
+ EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
+ // .. IBUF_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B54[7:7] = 0x00000001U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. TERM_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B54[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // ..
+ EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
+ // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // .. START: SRAM/NOR SET OPMODE
+ // .. FINISH: SRAM/NOR SET OPMODE
+ // .. START: UART REGISTERS
+ // .. BDIV = 0x6
+ // .. ==> 0XE0001034[7:0] = 0x00000006U
+ // .. ==> MASK : 0x000000FFU VAL : 0x00000006U
+ // ..
+ EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
+ // .. CD = 0x3e
+ // .. ==> 0XE0001018[15:0] = 0x0000003EU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU
+ // ..
+ EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
+ // .. STPBRK = 0x0
+ // .. ==> 0XE0001000[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. STTBRK = 0x0
+ // .. ==> 0XE0001000[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. RSTTO = 0x0
+ // .. ==> 0XE0001000[6:6] = 0x00000000U
+ // .. ==> MASK : 0x00000040U VAL : 0x00000000U
+ // .. TXDIS = 0x0
+ // .. ==> 0XE0001000[5:5] = 0x00000000U
+ // .. ==> MASK : 0x00000020U VAL : 0x00000000U
+ // .. TXEN = 0x1
+ // .. ==> 0XE0001000[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. RXDIS = 0x0
+ // .. ==> 0XE0001000[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. RXEN = 0x1
+ // .. ==> 0XE0001000[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. TXRES = 0x1
+ // .. ==> 0XE0001000[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. RXRES = 0x1
+ // .. ==> 0XE0001000[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // ..
+ EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
+ // .. IRMODE = 0x0
+ // .. ==> 0XE0001004[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. UCLKEN = 0x0
+ // .. ==> 0XE0001004[10:10] = 0x00000000U
+ // .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. CHMODE = 0x0
+ // .. ==> 0XE0001004[9:8] = 0x00000000U
+ // .. ==> MASK : 0x00000300U VAL : 0x00000000U
+ // .. NBSTOP = 0x0
+ // .. ==> 0XE0001004[7:6] = 0x00000000U
+ // .. ==> MASK : 0x000000C0U VAL : 0x00000000U
+ // .. PAR = 0x4
+ // .. ==> 0XE0001004[5:3] = 0x00000004U
+ // .. ==> MASK : 0x00000038U VAL : 0x00000020U
+ // .. CHRL = 0x0
+ // .. ==> 0XE0001004[2:1] = 0x00000000U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000000U
+ // .. CLKS = 0x0
+ // .. ==> 0XE0001004[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U),
+ // .. FINISH: UART REGISTERS
+ // .. START: QSPI REGISTERS
+ // .. Holdb_dr = 1
+ // .. ==> 0XE000D000[19:19] = 0x00000001U
+ // .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // ..
+ EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
+ // .. FINISH: QSPI REGISTERS
+ // .. START: PL POWER ON RESET REGISTERS
+ // .. PCFG_POR_CNT_4K = 0
+ // .. ==> 0XF8007000[29:29] = 0x00000000U
+ // .. ==> MASK : 0x20000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
+ // .. FINISH: PL POWER ON RESET REGISTERS
+ // .. START: SMC TIMING CALCULATION REGISTER UPDATE
+ // .. .. START: NAND SET CYCLE
+ // .. .. FINISH: NAND SET CYCLE
+ // .. .. START: OPMODE
+ // .. .. FINISH: OPMODE
+ // .. .. START: DIRECT COMMAND
+ // .. .. FINISH: DIRECT COMMAND
+ // .. .. START: SRAM/NOR CS0 SET CYCLE
+ // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
+ // .. .. START: DIRECT COMMAND
+ // .. .. FINISH: DIRECT COMMAND
+ // .. .. START: NOR CS0 BASE ADDRESS
+ // .. .. FINISH: NOR CS0 BASE ADDRESS
+ // .. .. START: SRAM/NOR CS1 SET CYCLE
+ // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
+ // .. .. START: DIRECT COMMAND
+ // .. .. FINISH: DIRECT COMMAND
+ // .. .. START: NOR CS1 BASE ADDRESS
+ // .. .. FINISH: NOR CS1 BASE ADDRESS
+ // .. .. START: USB RESET
+ // .. .. .. START: USB0 RESET
+ // .. .. .. .. START: DIR MODE BANK 0
+ // .. .. .. .. DIRECTION_0 = 0x80
+ // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U
+ // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U),
+ // .. .. .. .. FINISH: DIR MODE BANK 0
+ // .. .. .. .. START: DIR MODE BANK 1
+ // .. .. .. .. FINISH: DIR MODE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. MASK_0_LSW = 0xff7f
+ // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+ // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U
+ // .. .. .. .. DATA_0_LSW = 0x80
+ // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+ // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. START: OUTPUT ENABLE BANK 0
+ // .. .. .. .. OP_ENABLE_0 = 0x80
+ // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U
+ // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U),
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+ // .. .. .. .. START: OUTPUT ENABLE BANK 1
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. MASK_0_LSW = 0xff7f
+ // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+ // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U
+ // .. .. .. .. DATA_0_LSW = 0x0
+ // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+ // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U),
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. START: ADD 1 MS DELAY
+ // .. .. .. ..
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ // .. .. .. .. FINISH: ADD 1 MS DELAY
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. MASK_0_LSW = 0xff7f
+ // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+ // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U
+ // .. .. .. .. DATA_0_LSW = 0x80
+ // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+ // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. FINISH: USB0 RESET
+ // .. .. .. START: USB1 RESET
+ // .. .. .. .. START: DIR MODE BANK 0
+ // .. .. .. .. FINISH: DIR MODE BANK 0
+ // .. .. .. .. START: DIR MODE BANK 1
+ // .. .. .. .. FINISH: DIR MODE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. START: OUTPUT ENABLE BANK 0
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+ // .. .. .. .. START: OUTPUT ENABLE BANK 1
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. START: ADD 1 MS DELAY
+ // .. .. .. ..
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ // .. .. .. .. FINISH: ADD 1 MS DELAY
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. FINISH: USB1 RESET
+ // .. .. FINISH: USB RESET
+ // .. .. START: ENET RESET
+ // .. .. .. START: ENET0 RESET
+ // .. .. .. .. START: DIR MODE BANK 0
+ // .. .. .. .. FINISH: DIR MODE BANK 0
+ // .. .. .. .. START: DIR MODE BANK 1
+ // .. .. .. .. FINISH: DIR MODE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. START: OUTPUT ENABLE BANK 0
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+ // .. .. .. .. START: OUTPUT ENABLE BANK 1
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. START: ADD 1 MS DELAY
+ // .. .. .. ..
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ // .. .. .. .. FINISH: ADD 1 MS DELAY
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. FINISH: ENET0 RESET
+ // .. .. .. START: ENET1 RESET
+ // .. .. .. .. START: DIR MODE BANK 0
+ // .. .. .. .. FINISH: DIR MODE BANK 0
+ // .. .. .. .. START: DIR MODE BANK 1
+ // .. .. .. .. FINISH: DIR MODE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. START: OUTPUT ENABLE BANK 0
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+ // .. .. .. .. START: OUTPUT ENABLE BANK 1
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. START: ADD 1 MS DELAY
+ // .. .. .. ..
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ // .. .. .. .. FINISH: ADD 1 MS DELAY
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. FINISH: ENET1 RESET
+ // .. .. FINISH: ENET RESET
+ // .. .. START: I2C RESET
+ // .. .. .. START: I2C0 RESET
+ // .. .. .. .. START: DIR MODE GPIO BANK0
+ // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+ // .. .. .. .. START: DIR MODE GPIO BANK1
+ // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. START: OUTPUT ENABLE
+ // .. .. .. .. FINISH: OUTPUT ENABLE
+ // .. .. .. .. START: OUTPUT ENABLE
+ // .. .. .. .. FINISH: OUTPUT ENABLE
+ // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. START: ADD 1 MS DELAY
+ // .. .. .. ..
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ // .. .. .. .. FINISH: ADD 1 MS DELAY
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. FINISH: I2C0 RESET
+ // .. .. .. START: I2C1 RESET
+ // .. .. .. .. START: DIR MODE GPIO BANK0
+ // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+ // .. .. .. .. START: DIR MODE GPIO BANK1
+ // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. START: OUTPUT ENABLE
+ // .. .. .. .. FINISH: OUTPUT ENABLE
+ // .. .. .. .. START: OUTPUT ENABLE
+ // .. .. .. .. FINISH: OUTPUT ENABLE
+ // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. START: ADD 1 MS DELAY
+ // .. .. .. ..
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ // .. .. .. .. FINISH: ADD 1 MS DELAY
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. FINISH: I2C1 RESET
+ // .. .. FINISH: I2C RESET
+ // .. .. START: NOR CHIP SELECT
+ // .. .. .. START: DIR MODE BANK 0
+ // .. .. .. FINISH: DIR MODE BANK 0
+ // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. START: OUTPUT ENABLE BANK 0
+ // .. .. .. FINISH: OUTPUT ENABLE BANK 0
+ // .. .. FINISH: NOR CHIP SELECT
+ // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_post_config_2_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: ENABLING LEVEL SHIFTER
+ // .. USER_INP_ICT_EN_0 = 3
+ // .. ==> 0XF8000900[1:0] = 0x00000003U
+ // .. ==> MASK : 0x00000003U VAL : 0x00000003U
+ // .. USER_INP_ICT_EN_1 = 3
+ // .. ==> 0XF8000900[3:2] = 0x00000003U
+ // .. ==> MASK : 0x0000000CU VAL : 0x0000000CU
+ // ..
+ EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
+ // .. FINISH: ENABLING LEVEL SHIFTER
+ // .. START: FPGA RESETS TO 0
+ // .. reserved_3 = 0
+ // .. ==> 0XF8000240[31:25] = 0x00000000U
+ // .. ==> MASK : 0xFE000000U VAL : 0x00000000U
+ // .. FPGA_ACP_RST = 0
+ // .. ==> 0XF8000240[24:24] = 0x00000000U
+ // .. ==> MASK : 0x01000000U VAL : 0x00000000U
+ // .. FPGA_AXDS3_RST = 0
+ // .. ==> 0XF8000240[23:23] = 0x00000000U
+ // .. ==> MASK : 0x00800000U VAL : 0x00000000U
+ // .. FPGA_AXDS2_RST = 0
+ // .. ==> 0XF8000240[22:22] = 0x00000000U
+ // .. ==> MASK : 0x00400000U VAL : 0x00000000U
+ // .. FPGA_AXDS1_RST = 0
+ // .. ==> 0XF8000240[21:21] = 0x00000000U
+ // .. ==> MASK : 0x00200000U VAL : 0x00000000U
+ // .. FPGA_AXDS0_RST = 0
+ // .. ==> 0XF8000240[20:20] = 0x00000000U
+ // .. ==> MASK : 0x00100000U VAL : 0x00000000U
+ // .. reserved_2 = 0
+ // .. ==> 0XF8000240[19:18] = 0x00000000U
+ // .. ==> MASK : 0x000C0000U VAL : 0x00000000U
+ // .. FSSW1_FPGA_RST = 0
+ // .. ==> 0XF8000240[17:17] = 0x00000000U
+ // .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. FSSW0_FPGA_RST = 0
+ // .. ==> 0XF8000240[16:16] = 0x00000000U
+ // .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. reserved_1 = 0
+ // .. ==> 0XF8000240[15:14] = 0x00000000U
+ // .. ==> MASK : 0x0000C000U VAL : 0x00000000U
+ // .. FPGA_FMSW1_RST = 0
+ // .. ==> 0XF8000240[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // .. FPGA_FMSW0_RST = 0
+ // .. ==> 0XF8000240[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. FPGA_DMA3_RST = 0
+ // .. ==> 0XF8000240[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. FPGA_DMA2_RST = 0
+ // .. ==> 0XF8000240[10:10] = 0x00000000U
+ // .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. FPGA_DMA1_RST = 0
+ // .. ==> 0XF8000240[9:9] = 0x00000000U
+ // .. ==> MASK : 0x00000200U VAL : 0x00000000U
+ // .. FPGA_DMA0_RST = 0
+ // .. ==> 0XF8000240[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. reserved = 0
+ // .. ==> 0XF8000240[7:4] = 0x00000000U
+ // .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. FPGA3_OUT_RST = 0
+ // .. ==> 0XF8000240[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. FPGA2_OUT_RST = 0
+ // .. ==> 0XF8000240[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. FPGA1_OUT_RST = 0
+ // .. ==> 0XF8000240[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. FPGA0_OUT_RST = 0
+ // .. ==> 0XF8000240[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
+ // .. FINISH: FPGA RESETS TO 0
+ // .. START: AFI REGISTERS
+ // .. .. START: AFI0 REGISTERS
+ // .. .. FINISH: AFI0 REGISTERS
+ // .. .. START: AFI1 REGISTERS
+ // .. .. FINISH: AFI1 REGISTERS
+ // .. .. START: AFI2 REGISTERS
+ // .. .. FINISH: AFI2 REGISTERS
+ // .. .. START: AFI3 REGISTERS
+ // .. .. FINISH: AFI3 REGISTERS
+ // .. FINISH: AFI REGISTERS
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_debug_2_0[] = {
+ // START: top
+ // .. START: CROSS TRIGGER CONFIGURATIONS
+ // .. .. START: UNLOCKING CTI REGISTERS
+ // .. .. KEY = 0XC5ACCE55
+ // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
+ // .. ..
+ EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
+ // .. .. KEY = 0XC5ACCE55
+ // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
+ // .. ..
+ EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
+ // .. .. KEY = 0XC5ACCE55
+ // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
+ // .. ..
+ EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
+ // .. .. FINISH: UNLOCKING CTI REGISTERS
+ // .. .. START: ENABLING CTI MODULES AND CHANNELS
+ // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
+ // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+ // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+ // .. FINISH: CROSS TRIGGER CONFIGURATIONS
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_pll_init_data_1_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: PLL SLCR REGISTERS
+ // .. .. START: ARM PLL INIT
+ // .. .. PLL_RES = 0x2
+ // .. .. ==> 0XF8000110[7:4] = 0x00000002U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
+ // .. .. PLL_CP = 0x2
+ // .. .. ==> 0XF8000110[11:8] = 0x00000002U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
+ // .. .. LOCK_CNT = 0xfa
+ // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
+ // .. .. .. START: UPDATE FB_DIV
+ // .. .. .. PLL_FDIV = 0x28
+ // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
+ // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
+ // .. .. .. FINISH: UPDATE FB_DIV
+ // .. .. .. START: BY PASS PLL
+ // .. .. .. PLL_BYPASS_FORCE = 1
+ // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
+ // .. .. .. FINISH: BY PASS PLL
+ // .. .. .. START: ASSERT RESET
+ // .. .. .. PLL_RESET = 1
+ // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
+ // .. .. .. FINISH: ASSERT RESET
+ // .. .. .. START: DEASSERT RESET
+ // .. .. .. PLL_RESET = 0
+ // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
+ // .. .. .. FINISH: DEASSERT RESET
+ // .. .. .. START: CHECK PLL STATUS
+ // .. .. .. ARM_PLL_LOCK = 1
+ // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ..
+ EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+ // .. .. .. FINISH: CHECK PLL STATUS
+ // .. .. .. START: REMOVE PLL BY PASS
+ // .. .. .. PLL_BYPASS_FORCE = 0
+ // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
+ // .. .. .. FINISH: REMOVE PLL BY PASS
+ // .. .. .. SRCSEL = 0x0
+ // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. .. .. DIVISOR = 0x2
+ // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
+ // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U
+ // .. .. .. CPU_6OR4XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
+ // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U
+ // .. .. .. CPU_3OR2XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
+ // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U
+ // .. .. .. CPU_2XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
+ // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U
+ // .. .. .. CPU_1XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
+ // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U
+ // .. .. .. CPU_PERI_CLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
+ // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
+ // .. .. FINISH: ARM PLL INIT
+ // .. .. START: DDR PLL INIT
+ // .. .. PLL_RES = 0x2
+ // .. .. ==> 0XF8000114[7:4] = 0x00000002U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
+ // .. .. PLL_CP = 0x2
+ // .. .. ==> 0XF8000114[11:8] = 0x00000002U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
+ // .. .. LOCK_CNT = 0x12c
+ // .. .. ==> 0XF8000114[21:12] = 0x0000012CU
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
+ // .. .. .. START: UPDATE FB_DIV
+ // .. .. .. PLL_FDIV = 0x20
+ // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
+ // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
+ // .. .. .. FINISH: UPDATE FB_DIV
+ // .. .. .. START: BY PASS PLL
+ // .. .. .. PLL_BYPASS_FORCE = 1
+ // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
+ // .. .. .. FINISH: BY PASS PLL
+ // .. .. .. START: ASSERT RESET
+ // .. .. .. PLL_RESET = 1
+ // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
+ // .. .. .. FINISH: ASSERT RESET
+ // .. .. .. START: DEASSERT RESET
+ // .. .. .. PLL_RESET = 0
+ // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
+ // .. .. .. FINISH: DEASSERT RESET
+ // .. .. .. START: CHECK PLL STATUS
+ // .. .. .. DDR_PLL_LOCK = 1
+ // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. .. ..
+ EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+ // .. .. .. FINISH: CHECK PLL STATUS
+ // .. .. .. START: REMOVE PLL BY PASS
+ // .. .. .. PLL_BYPASS_FORCE = 0
+ // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
+ // .. .. .. FINISH: REMOVE PLL BY PASS
+ // .. .. .. DDR_3XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. .. DDR_2XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. .. .. DDR_3XCLK_DIVISOR = 0x2
+ // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
+ // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U
+ // .. .. .. DDR_2XCLK_DIVISOR = 0x3
+ // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
+ // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
+ // .. .. FINISH: DDR PLL INIT
+ // .. .. START: IO PLL INIT
+ // .. .. PLL_RES = 0xc
+ // .. .. ==> 0XF8000118[7:4] = 0x0000000CU
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U
+ // .. .. PLL_CP = 0x2
+ // .. .. ==> 0XF8000118[11:8] = 0x00000002U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
+ // .. .. LOCK_CNT = 0x145
+ // .. .. ==> 0XF8000118[21:12] = 0x00000145U
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U),
+ // .. .. .. START: UPDATE FB_DIV
+ // .. .. .. PLL_FDIV = 0x1e
+ // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU
+ // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U),
+ // .. .. .. FINISH: UPDATE FB_DIV
+ // .. .. .. START: BY PASS PLL
+ // .. .. .. PLL_BYPASS_FORCE = 1
+ // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
+ // .. .. .. FINISH: BY PASS PLL
+ // .. .. .. START: ASSERT RESET
+ // .. .. .. PLL_RESET = 1
+ // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
+ // .. .. .. FINISH: ASSERT RESET
+ // .. .. .. START: DEASSERT RESET
+ // .. .. .. PLL_RESET = 0
+ // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
+ // .. .. .. FINISH: DEASSERT RESET
+ // .. .. .. START: CHECK PLL STATUS
+ // .. .. .. IO_PLL_LOCK = 1
+ // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. .. ..
+ EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+ // .. .. .. FINISH: CHECK PLL STATUS
+ // .. .. .. START: REMOVE PLL BY PASS
+ // .. .. .. PLL_BYPASS_FORCE = 0
+ // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
+ // .. .. .. FINISH: REMOVE PLL BY PASS
+ // .. .. FINISH: IO PLL INIT
+ // .. FINISH: PLL SLCR REGISTERS
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_clock_init_data_1_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: CLOCK CONTROL SLCR REGISTERS
+ // .. CLKACT = 0x1
+ // .. ==> 0XF8000128[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. DIVISOR0 = 0x23
+ // .. ==> 0XF8000128[13:8] = 0x00000023U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00002300U
+ // .. DIVISOR1 = 0x3
+ // .. ==> 0XF8000128[25:20] = 0x00000003U
+ // .. ==> MASK : 0x03F00000U VAL : 0x00300000U
+ // ..
+ EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U),
+ // .. CLKACT = 0x1
+ // .. ==> 0XF8000138[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000138[4:4] = 0x00000000U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
+ // .. CLKACT = 0x1
+ // .. ==> 0XF8000140[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000140[6:4] = 0x00000000U
+ // .. ==> MASK : 0x00000070U VAL : 0x00000000U
+ // .. DIVISOR = 0x8
+ // .. ==> 0XF8000140[13:8] = 0x00000008U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00000800U
+ // .. DIVISOR1 = 0x1
+ // .. ==> 0XF8000140[25:20] = 0x00000001U
+ // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
+ // ..
+ EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U),
+ // .. CLKACT = 0x1
+ // .. ==> 0XF800014C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF800014C[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR = 0x5
+ // .. ==> 0XF800014C[13:8] = 0x00000005U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00000500U
+ // ..
+ EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
+ // .. CLKACT0 = 0x1
+ // .. ==> 0XF8000150[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. CLKACT1 = 0x0
+ // .. ==> 0XF8000150[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000150[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR = 0x14
+ // .. ==> 0XF8000150[13:8] = 0x00000014U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
+ // ..
+ EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U),
+ // .. CLKACT0 = 0x0
+ // .. ==> 0XF8000154[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. CLKACT1 = 0x1
+ // .. ==> 0XF8000154[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000154[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR = 0x14
+ // .. ==> 0XF8000154[13:8] = 0x00000014U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
+ // ..
+ EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U),
+ // .. CLKACT = 0x1
+ // .. ==> 0XF8000168[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000168[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR = 0x5
+ // .. ==> 0XF8000168[13:8] = 0x00000005U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00000500U
+ // ..
+ EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000170[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR0 = 0xa
+ // .. ==> 0XF8000170[13:8] = 0x0000000AU
+ // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U
+ // .. DIVISOR1 = 0x1
+ // .. ==> 0XF8000170[25:20] = 0x00000001U
+ // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
+ // ..
+ EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00100A00U),
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000180[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR0 = 0xa
+ // .. ==> 0XF8000180[13:8] = 0x0000000AU
+ // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U
+ // .. DIVISOR1 = 0x1
+ // .. ==> 0XF8000180[25:20] = 0x00000001U
+ // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
+ // ..
+ EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00100A00U),
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000190[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR0 = 0x1e
+ // .. ==> 0XF8000190[13:8] = 0x0000001EU
+ // .. ==> MASK : 0x00003F00U VAL : 0x00001E00U
+ // .. DIVISOR1 = 0x1
+ // .. ==> 0XF8000190[25:20] = 0x00000001U
+ // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
+ // ..
+ EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101E00U),
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF80001A0[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR0 = 0x14
+ // .. ==> 0XF80001A0[13:8] = 0x00000014U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
+ // .. DIVISOR1 = 0x1
+ // .. ==> 0XF80001A0[25:20] = 0x00000001U
+ // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
+ // ..
+ EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U),
+ // .. CLK_621_TRUE = 0x1
+ // .. ==> 0XF80001C4[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // ..
+ EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
+ // .. DMA_CPU_2XCLKACT = 0x1
+ // .. ==> 0XF800012C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. USB0_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. USB1_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[3:3] = 0x00000001U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000008U
+ // .. GEM0_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[6:6] = 0x00000001U
+ // .. ==> MASK : 0x00000040U VAL : 0x00000040U
+ // .. GEM1_CPU_1XCLKACT = 0x0
+ // .. ==> 0XF800012C[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. SDI0_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[10:10] = 0x00000001U
+ // .. ==> MASK : 0x00000400U VAL : 0x00000400U
+ // .. SDI1_CPU_1XCLKACT = 0x0
+ // .. ==> 0XF800012C[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. SPI0_CPU_1XCLKACT = 0x0
+ // .. ==> 0XF800012C[14:14] = 0x00000000U
+ // .. ==> MASK : 0x00004000U VAL : 0x00000000U
+ // .. SPI1_CPU_1XCLKACT = 0x0
+ // .. ==> 0XF800012C[15:15] = 0x00000000U
+ // .. ==> MASK : 0x00008000U VAL : 0x00000000U
+ // .. CAN0_CPU_1XCLKACT = 0x0
+ // .. ==> 0XF800012C[16:16] = 0x00000000U
+ // .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. CAN1_CPU_1XCLKACT = 0x0
+ // .. ==> 0XF800012C[17:17] = 0x00000000U
+ // .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. I2C0_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[18:18] = 0x00000001U
+ // .. ==> MASK : 0x00040000U VAL : 0x00040000U
+ // .. I2C1_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[19:19] = 0x00000001U
+ // .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // .. UART0_CPU_1XCLKACT = 0x0
+ // .. ==> 0XF800012C[20:20] = 0x00000000U
+ // .. ==> MASK : 0x00100000U VAL : 0x00000000U
+ // .. UART1_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[21:21] = 0x00000001U
+ // .. ==> MASK : 0x00200000U VAL : 0x00200000U
+ // .. GPIO_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[22:22] = 0x00000001U
+ // .. ==> MASK : 0x00400000U VAL : 0x00400000U
+ // .. LQSPI_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[23:23] = 0x00000001U
+ // .. ==> MASK : 0x00800000U VAL : 0x00800000U
+ // .. SMC_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[24:24] = 0x00000001U
+ // .. ==> MASK : 0x01000000U VAL : 0x01000000U
+ // ..
+ EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC044DU),
+ // .. FINISH: CLOCK CONTROL SLCR REGISTERS
+ // .. START: THIS SHOULD BE BLANK
+ // .. FINISH: THIS SHOULD BE BLANK
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_ddr_init_data_1_0[] = {
+ // START: top
+ // .. START: DDR INITIALIZATION
+ // .. .. START: LOCK DDR
+ // .. .. reg_ddrc_soft_rstb = 0
+ // .. .. ==> 0XF8006000[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_powerdown_en = 0x0
+ // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_ddrc_data_bus_width = 0x0
+ // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U
+ // .. .. reg_ddrc_burst8_refresh = 0x0
+ // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U
+ // .. .. reg_ddrc_rdwr_idle_gap = 0x1
+ // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+ // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U
+ // .. .. reg_ddrc_dis_rd_bypass = 0x0
+ // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+ // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_act_bypass = 0x0
+ // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_auto_refresh = 0x0
+ // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
+ // .. .. FINISH: LOCK DDR
+ // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81
+ // .. .. ==> 0XF8006004[11:0] = 0x00000081U
+ // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U
+ // .. .. reg_ddrc_active_ranks = 0x1
+ // .. .. ==> 0XF8006004[13:12] = 0x00000001U
+ // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U
+ // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
+ // .. .. ==> 0XF8006004[18:14] = 0x00000000U
+ // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U
+ // .. .. reg_ddrc_wr_odt_block = 0x1
+ // .. .. ==> 0XF8006004[20:19] = 0x00000001U
+ // .. .. ==> MASK : 0x00180000U VAL : 0x00080000U
+ // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0
+ // .. .. ==> 0XF8006004[21:21] = 0x00000000U
+ // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0
+ // .. .. ==> 0XF8006004[26:22] = 0x00000000U
+ // .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_open_bank = 0x0
+ // .. .. ==> 0XF8006004[27:27] = 0x00000000U
+ // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_4bank_ram = 0x0
+ // .. .. ==> 0XF8006004[28:28] = 0x00000000U
+ // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U),
+ // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
+ // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU
+ // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
+ // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
+ // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U
+ // .. .. reg_ddrc_hpr_xact_run_length = 0xf
+ // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
+ // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
+ // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
+ // .. .. ==> 0XF800600C[10:0] = 0x00000001U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U
+ // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
+ // .. .. ==> 0XF800600C[21:11] = 0x00000002U
+ // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U
+ // .. .. reg_ddrc_lpr_xact_run_length = 0x8
+ // .. .. ==> 0XF800600C[25:22] = 0x00000008U
+ // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
+ // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
+ // .. .. ==> 0XF8006010[10:0] = 0x00000001U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U
+ // .. .. reg_ddrc_w_xact_run_length = 0x8
+ // .. .. ==> 0XF8006010[14:11] = 0x00000008U
+ // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U
+ // .. .. reg_ddrc_w_max_starve_x32 = 0x2
+ // .. .. ==> 0XF8006010[25:15] = 0x00000002U
+ // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
+ // .. .. reg_ddrc_t_rc = 0x1a
+ // .. .. ==> 0XF8006014[5:0] = 0x0000001AU
+ // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001AU
+ // .. .. reg_ddrc_t_rfc_min = 0xa0
+ // .. .. ==> 0XF8006014[13:6] = 0x000000A0U
+ // .. .. ==> MASK : 0x00003FC0U VAL : 0x00002800U
+ // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
+ // .. .. ==> 0XF8006014[20:14] = 0x00000010U
+ // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281AU),
+ // .. .. reg_ddrc_wr2pre = 0x12
+ // .. .. ==> 0XF8006018[4:0] = 0x00000012U
+ // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U
+ // .. .. reg_ddrc_powerdown_to_x32 = 0x6
+ // .. .. ==> 0XF8006018[9:5] = 0x00000006U
+ // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U
+ // .. .. reg_ddrc_t_faw = 0x16
+ // .. .. ==> 0XF8006018[15:10] = 0x00000016U
+ // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005800U
+ // .. .. reg_ddrc_t_ras_max = 0x24
+ // .. .. ==> 0XF8006018[21:16] = 0x00000024U
+ // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U
+ // .. .. reg_ddrc_t_ras_min = 0x13
+ // .. .. ==> 0XF8006018[26:22] = 0x00000013U
+ // .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U
+ // .. .. reg_ddrc_t_cke = 0x4
+ // .. .. ==> 0XF8006018[31:28] = 0x00000004U
+ // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D2U),
+ // .. .. reg_ddrc_write_latency = 0x5
+ // .. .. ==> 0XF800601C[4:0] = 0x00000005U
+ // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U
+ // .. .. reg_ddrc_rd2wr = 0x7
+ // .. .. ==> 0XF800601C[9:5] = 0x00000007U
+ // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U
+ // .. .. reg_ddrc_wr2rd = 0xe
+ // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
+ // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U
+ // .. .. reg_ddrc_t_xp = 0x4
+ // .. .. ==> 0XF800601C[19:15] = 0x00000004U
+ // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U
+ // .. .. reg_ddrc_pad_pd = 0x0
+ // .. .. ==> 0XF800601C[22:20] = 0x00000000U
+ // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U
+ // .. .. reg_ddrc_rd2pre = 0x4
+ // .. .. ==> 0XF800601C[27:23] = 0x00000004U
+ // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U
+ // .. .. reg_ddrc_t_rcd = 0x7
+ // .. .. ==> 0XF800601C[31:28] = 0x00000007U
+ // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
+ // .. .. reg_ddrc_t_ccd = 0x4
+ // .. .. ==> 0XF8006020[4:2] = 0x00000004U
+ // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U
+ // .. .. reg_ddrc_t_rrd = 0x6
+ // .. .. ==> 0XF8006020[7:5] = 0x00000006U
+ // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U
+ // .. .. reg_ddrc_refresh_margin = 0x2
+ // .. .. ==> 0XF8006020[11:8] = 0x00000002U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
+ // .. .. reg_ddrc_t_rp = 0x7
+ // .. .. ==> 0XF8006020[15:12] = 0x00000007U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U
+ // .. .. reg_ddrc_refresh_to_x32 = 0x8
+ // .. .. ==> 0XF8006020[20:16] = 0x00000008U
+ // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U
+ // .. .. reg_ddrc_sdram = 0x1
+ // .. .. ==> 0XF8006020[21:21] = 0x00000001U
+ // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U
+ // .. .. reg_ddrc_mobile = 0x0
+ // .. .. ==> 0XF8006020[22:22] = 0x00000000U
+ // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U
+ // .. .. reg_ddrc_clock_stop_en = 0x0
+ // .. .. ==> 0XF8006020[23:23] = 0x00000000U
+ // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U
+ // .. .. reg_ddrc_read_latency = 0x7
+ // .. .. ==> 0XF8006020[28:24] = 0x00000007U
+ // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U
+ // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
+ // .. .. ==> 0XF8006020[29:29] = 0x00000001U
+ // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U
+ // .. .. reg_ddrc_dis_pad_pd = 0x0
+ // .. .. ==> 0XF8006020[30:30] = 0x00000000U
+ // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_loopback = 0x0
+ // .. .. ==> 0XF8006020[31:31] = 0x00000000U
+ // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U),
+ // .. .. reg_ddrc_en_2t_timing_mode = 0x0
+ // .. .. ==> 0XF8006024[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_prefer_write = 0x0
+ // .. .. ==> 0XF8006024[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_ddrc_max_rank_rd = 0xf
+ // .. .. ==> 0XF8006024[5:2] = 0x0000000FU
+ // .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU
+ // .. .. reg_ddrc_mr_wr = 0x0
+ // .. .. ==> 0XF8006024[6:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr_addr = 0x0
+ // .. .. ==> 0XF8006024[8:7] = 0x00000000U
+ // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr_data = 0x0
+ // .. .. ==> 0XF8006024[24:9] = 0x00000000U
+ // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U
+ // .. .. ddrc_reg_mr_wr_busy = 0x0
+ // .. .. ==> 0XF8006024[25:25] = 0x00000000U
+ // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr_type = 0x0
+ // .. .. ==> 0XF8006024[26:26] = 0x00000000U
+ // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr_rdata_valid = 0x0
+ // .. .. ==> 0XF8006024[27:27] = 0x00000000U
+ // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU),
+ // .. .. reg_ddrc_final_wait_x32 = 0x7
+ // .. .. ==> 0XF8006028[6:0] = 0x00000007U
+ // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U
+ // .. .. reg_ddrc_pre_ocd_x32 = 0x0
+ // .. .. ==> 0XF8006028[10:7] = 0x00000000U
+ // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U
+ // .. .. reg_ddrc_t_mrd = 0x4
+ // .. .. ==> 0XF8006028[13:11] = 0x00000004U
+ // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
+ // .. .. reg_ddrc_emr2 = 0x8
+ // .. .. ==> 0XF800602C[15:0] = 0x00000008U
+ // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U
+ // .. .. reg_ddrc_emr3 = 0x0
+ // .. .. ==> 0XF800602C[31:16] = 0x00000000U
+ // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
+ // .. .. reg_ddrc_mr = 0x930
+ // .. .. ==> 0XF8006030[15:0] = 0x00000930U
+ // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U
+ // .. .. reg_ddrc_emr = 0x4
+ // .. .. ==> 0XF8006030[31:16] = 0x00000004U
+ // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
+ // .. .. reg_ddrc_burst_rdwr = 0x4
+ // .. .. ==> 0XF8006034[3:0] = 0x00000004U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U
+ // .. .. reg_ddrc_pre_cke_x1024 = 0x105
+ // .. .. ==> 0XF8006034[13:4] = 0x00000105U
+ // .. .. ==> MASK : 0x00003FF0U VAL : 0x00001050U
+ // .. .. reg_ddrc_post_cke_x1024 = 0x1
+ // .. .. ==> 0XF8006034[25:16] = 0x00000001U
+ // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U
+ // .. .. reg_ddrc_burstchop = 0x0
+ // .. .. ==> 0XF8006034[28:28] = 0x00000000U
+ // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U),
+ // .. .. reg_ddrc_force_low_pri_n = 0x0
+ // .. .. ==> 0XF8006038[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_dq = 0x0
+ // .. .. ==> 0XF8006038[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_debug_mode = 0x0
+ // .. .. ==> 0XF8006038[6:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U
+ // .. .. reg_phy_wr_level_start = 0x0
+ // .. .. ==> 0XF8006038[7:7] = 0x00000000U
+ // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. .. reg_phy_rd_level_start = 0x0
+ // .. .. ==> 0XF8006038[8:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. .. reg_phy_dq0_wait_t = 0x0
+ // .. .. ==> 0XF8006038[12:9] = 0x00000000U
+ // .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U),
+ // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
+ // .. .. ==> 0XF800603C[3:0] = 0x00000007U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U
+ // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
+ // .. .. ==> 0XF800603C[7:4] = 0x00000007U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U
+ // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
+ // .. .. ==> 0XF800603C[11:8] = 0x00000007U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U
+ // .. .. reg_ddrc_addrmap_col_b5 = 0x0
+ // .. .. ==> 0XF800603C[15:12] = 0x00000000U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b6 = 0x0
+ // .. .. ==> 0XF800603C[19:16] = 0x00000000U
+ // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
+ // .. .. reg_ddrc_addrmap_col_b2 = 0x0
+ // .. .. ==> 0XF8006040[3:0] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b3 = 0x0
+ // .. .. ==> 0XF8006040[7:4] = 0x00000000U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b4 = 0x0
+ // .. .. ==> 0XF8006040[11:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b7 = 0x0
+ // .. .. ==> 0XF8006040[15:12] = 0x00000000U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b8 = 0x0
+ // .. .. ==> 0XF8006040[19:16] = 0x00000000U
+ // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b9 = 0xf
+ // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
+ // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U
+ // .. .. reg_ddrc_addrmap_col_b10 = 0xf
+ // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
+ // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U
+ // .. .. reg_ddrc_addrmap_col_b11 = 0xf
+ // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
+ // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
+ // .. .. reg_ddrc_addrmap_row_b0 = 0x6
+ // .. .. ==> 0XF8006044[3:0] = 0x00000006U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U
+ // .. .. reg_ddrc_addrmap_row_b1 = 0x6
+ // .. .. ==> 0XF8006044[7:4] = 0x00000006U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U
+ // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
+ // .. .. ==> 0XF8006044[11:8] = 0x00000006U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U
+ // .. .. reg_ddrc_addrmap_row_b12 = 0x6
+ // .. .. ==> 0XF8006044[15:12] = 0x00000006U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U
+ // .. .. reg_ddrc_addrmap_row_b13 = 0x6
+ // .. .. ==> 0XF8006044[19:16] = 0x00000006U
+ // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U
+ // .. .. reg_ddrc_addrmap_row_b14 = 0x6
+ // .. .. ==> 0XF8006044[23:20] = 0x00000006U
+ // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U
+ // .. .. reg_ddrc_addrmap_row_b15 = 0xf
+ // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
+ // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U),
+ // .. .. reg_ddrc_rank0_rd_odt = 0x0
+ // .. .. ==> 0XF8006048[2:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U
+ // .. .. reg_ddrc_rank0_wr_odt = 0x1
+ // .. .. ==> 0XF8006048[5:3] = 0x00000001U
+ // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U
+ // .. .. reg_ddrc_rank1_rd_odt = 0x1
+ // .. .. ==> 0XF8006048[8:6] = 0x00000001U
+ // .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U
+ // .. .. reg_ddrc_rank1_wr_odt = 0x1
+ // .. .. ==> 0XF8006048[11:9] = 0x00000001U
+ // .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. .. reg_phy_rd_local_odt = 0x0
+ // .. .. ==> 0XF8006048[13:12] = 0x00000000U
+ // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U
+ // .. .. reg_phy_wr_local_odt = 0x3
+ // .. .. ==> 0XF8006048[15:14] = 0x00000003U
+ // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U
+ // .. .. reg_phy_idle_local_odt = 0x3
+ // .. .. ==> 0XF8006048[17:16] = 0x00000003U
+ // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U
+ // .. .. reg_ddrc_rank2_rd_odt = 0x0
+ // .. .. ==> 0XF8006048[20:18] = 0x00000000U
+ // .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U
+ // .. .. reg_ddrc_rank2_wr_odt = 0x0
+ // .. .. ==> 0XF8006048[23:21] = 0x00000000U
+ // .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U
+ // .. .. reg_ddrc_rank3_rd_odt = 0x0
+ // .. .. ==> 0XF8006048[26:24] = 0x00000000U
+ // .. .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_rank3_wr_odt = 0x0
+ // .. .. ==> 0XF8006048[29:27] = 0x00000000U
+ // .. .. ==> MASK : 0x38000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U),
+ // .. .. reg_phy_rd_cmd_to_data = 0x0
+ // .. .. ==> 0XF8006050[3:0] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
+ // .. .. reg_phy_wr_cmd_to_data = 0x0
+ // .. .. ==> 0XF8006050[7:4] = 0x00000000U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. .. reg_phy_rdc_we_to_re_delay = 0x8
+ // .. .. ==> 0XF8006050[11:8] = 0x00000008U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U
+ // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
+ // .. .. ==> 0XF8006050[15:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
+ // .. .. reg_phy_use_fixed_re = 0x1
+ // .. .. ==> 0XF8006050[16:16] = 0x00000001U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U
+ // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
+ // .. .. ==> 0XF8006050[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
+ // .. .. ==> 0XF8006050[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_phy_clk_stall_level = 0x0
+ // .. .. ==> 0XF8006050[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
+ // .. .. ==> 0XF8006050[27:24] = 0x00000007U
+ // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U
+ // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
+ // .. .. ==> 0XF8006050[31:28] = 0x00000007U
+ // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
+ // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1
+ // .. .. ==> 0XF8006058[7:0] = 0x00000001U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U
+ // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1
+ // .. .. ==> 0XF8006058[15:8] = 0x00000001U
+ // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U
+ // .. .. reg_ddrc_dis_dll_calib = 0x0
+ // .. .. ==> 0XF8006058[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U),
+ // .. .. reg_ddrc_rd_odt_delay = 0x3
+ // .. .. ==> 0XF800605C[3:0] = 0x00000003U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U
+ // .. .. reg_ddrc_wr_odt_delay = 0x0
+ // .. .. ==> 0XF800605C[7:4] = 0x00000000U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. .. reg_ddrc_rd_odt_hold = 0x0
+ // .. .. ==> 0XF800605C[11:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U
+ // .. .. reg_ddrc_wr_odt_hold = 0x5
+ // .. .. ==> 0XF800605C[15:12] = 0x00000005U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
+ // .. .. reg_ddrc_pageclose = 0x0
+ // .. .. ==> 0XF8006060[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_lpr_num_entries = 0x1f
+ // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
+ // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU
+ // .. .. reg_ddrc_auto_pre_en = 0x0
+ // .. .. ==> 0XF8006060[7:7] = 0x00000000U
+ // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. .. reg_ddrc_refresh_update_level = 0x0
+ // .. .. ==> 0XF8006060[8:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_wc = 0x0
+ // .. .. ==> 0XF8006060[9:9] = 0x00000000U
+ // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_collision_page_opt = 0x0
+ // .. .. ==> 0XF8006060[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_ddrc_selfref_en = 0x0
+ // .. .. ==> 0XF8006060[12:12] = 0x00000000U
+ // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
+ // .. .. reg_ddrc_go2critical_hysteresis = 0x0
+ // .. .. ==> 0XF8006064[12:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U
+ // .. .. reg_arb_go2critical_en = 0x1
+ // .. .. ==> 0XF8006064[17:17] = 0x00000001U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
+ // .. .. reg_ddrc_wrlvl_ww = 0x41
+ // .. .. ==> 0XF8006068[7:0] = 0x00000041U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U
+ // .. .. reg_ddrc_rdlvl_rr = 0x41
+ // .. .. ==> 0XF8006068[15:8] = 0x00000041U
+ // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U
+ // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
+ // .. .. ==> 0XF8006068[25:16] = 0x00000028U
+ // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
+ // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
+ // .. .. ==> 0XF800606C[7:0] = 0x00000010U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U
+ // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
+ // .. .. ==> 0XF800606C[15:8] = 0x00000016U
+ // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U
+ // .. ..
+ EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
+ // .. .. refresh_timer0_start_value_x32 = 0x0
+ // .. .. ==> 0XF80060A0[11:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U
+ // .. .. refresh_timer1_start_value_x32 = 0x8
+ // .. .. ==> 0XF80060A0[23:12] = 0x00000008U
+ // .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U),
+ // .. .. reg_ddrc_dis_auto_zq = 0x0
+ // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_ddr3 = 0x1
+ // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. .. reg_ddrc_t_mod = 0x200
+ // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
+ // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U
+ // .. .. reg_ddrc_t_zq_long_nop = 0x200
+ // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U
+ // .. .. reg_ddrc_t_zq_short_nop = 0x40
+ // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
+ // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
+ // .. .. t_zq_short_interval_x1024 = 0xcb73
+ // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U
+ // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U
+ // .. .. dram_rstn_x1024 = 0x69
+ // .. .. ==> 0XF80060A8[27:20] = 0x00000069U
+ // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
+ // .. .. deeppowerdown_en = 0x0
+ // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. deeppowerdown_to_x1024 = 0xff
+ // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
+ // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU
+ // .. ..
+ EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
+ // .. .. dfi_wrlvl_max_x1024 = 0xfff
+ // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
+ // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU
+ // .. .. dfi_rdlvl_max_x1024 = 0xfff
+ // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
+ // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U
+ // .. .. ddrc_reg_twrlvl_max_error = 0x0
+ // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
+ // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U
+ // .. .. ddrc_reg_trdlvl_max_error = 0x0
+ // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
+ // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dfi_wr_level_en = 0x1
+ // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
+ // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U
+ // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
+ // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
+ // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U
+ // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
+ // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
+ // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
+ // .. .. reg_ddrc_2t_delay = 0x0
+ // .. .. ==> 0XF80060B4[8:0] = 0x00000000U
+ // .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U
+ // .. .. reg_ddrc_skip_ocd = 0x1
+ // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
+ // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U
+ // .. .. reg_ddrc_dis_pre_bypass = 0x0
+ // .. .. ==> 0XF80060B4[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U),
+ // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
+ // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
+ // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U
+ // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
+ // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
+ // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U
+ // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
+ // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
+ // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
+ // .. .. START: RESET ECC ERROR
+ // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1
+ // .. .. ==> 0XF80060C4[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. Clear_Correctable_DRAM_ECC_error = 1
+ // .. .. ==> 0XF80060C4[1:1] = 0x00000001U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U),
+ // .. .. FINISH: RESET ECC ERROR
+ // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
+ // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
+ // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
+ // .. .. CORR_ECC_LOG_VALID = 0x0
+ // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. ECC_CORRECTED_BIT_NUM = 0x0
+ // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
+ // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
+ // .. .. UNCORR_ECC_LOG_VALID = 0x0
+ // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
+ // .. .. STAT_NUM_CORR_ERR = 0x0
+ // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
+ // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U
+ // .. .. STAT_NUM_UNCORR_ERR = 0x0
+ // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
+ // .. .. reg_ddrc_ecc_mode = 0x0
+ // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_scrub = 0x1
+ // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
+ // .. .. reg_phy_dif_on = 0x0
+ // .. .. ==> 0XF8006114[3:0] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
+ // .. .. reg_phy_dif_off = 0x0
+ // .. .. ==> 0XF8006114[7:4] = 0x00000000U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
+ // .. .. reg_phy_data_slice_in_use = 0x1
+ // .. .. ==> 0XF8006118[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_phy_rdlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006118[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006118[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_wrlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006118[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_tx = 0x0
+ // .. .. ==> 0XF8006118[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_rx = 0x0
+ // .. .. ==> 0XF8006118[5:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
+ // .. .. reg_phy_bist_shift_dq = 0x0
+ // .. .. ==> 0XF8006118[14:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
+ // .. .. reg_phy_bist_err_clr = 0x0
+ // .. .. ==> 0XF8006118[23:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
+ // .. .. reg_phy_dq_offset = 0x40
+ // .. .. ==> 0XF8006118[30:24] = 0x00000040U
+ // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U),
+ // .. .. reg_phy_data_slice_in_use = 0x1
+ // .. .. ==> 0XF800611C[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_phy_rdlvl_inc_mode = 0x0
+ // .. .. ==> 0XF800611C[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_inc_mode = 0x0
+ // .. .. ==> 0XF800611C[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_wrlvl_inc_mode = 0x0
+ // .. .. ==> 0XF800611C[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_tx = 0x0
+ // .. .. ==> 0XF800611C[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_rx = 0x0
+ // .. .. ==> 0XF800611C[5:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
+ // .. .. reg_phy_bist_shift_dq = 0x0
+ // .. .. ==> 0XF800611C[14:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
+ // .. .. reg_phy_bist_err_clr = 0x0
+ // .. .. ==> 0XF800611C[23:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
+ // .. .. reg_phy_dq_offset = 0x40
+ // .. .. ==> 0XF800611C[30:24] = 0x00000040U
+ // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U),
+ // .. .. reg_phy_data_slice_in_use = 0x1
+ // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_phy_rdlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_wrlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_tx = 0x0
+ // .. .. ==> 0XF8006120[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_rx = 0x0
+ // .. .. ==> 0XF8006120[5:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
+ // .. .. reg_phy_bist_shift_dq = 0x0
+ // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
+ // .. .. reg_phy_bist_err_clr = 0x0
+ // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
+ // .. .. reg_phy_dq_offset = 0x40
+ // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+ // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U),
+ // .. .. reg_phy_data_slice_in_use = 0x1
+ // .. .. ==> 0XF8006124[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_phy_rdlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006124[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006124[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_wrlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006124[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_tx = 0x0
+ // .. .. ==> 0XF8006124[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_rx = 0x0
+ // .. .. ==> 0XF8006124[5:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
+ // .. .. reg_phy_bist_shift_dq = 0x0
+ // .. .. ==> 0XF8006124[14:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
+ // .. .. reg_phy_bist_err_clr = 0x0
+ // .. .. ==> 0XF8006124[23:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
+ // .. .. reg_phy_dq_offset = 0x40
+ // .. .. ==> 0XF8006124[30:24] = 0x00000040U
+ // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U),
+ // .. .. reg_phy_wrlvl_init_ratio = 0x0
+ // .. .. ==> 0XF800612C[9:0] = 0x00000000U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_init_ratio = 0xb0
+ // .. .. ==> 0XF800612C[19:10] = 0x000000B0U
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002C000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0002C000U),
+ // .. .. reg_phy_wrlvl_init_ratio = 0x0
+ // .. .. ==> 0XF8006130[9:0] = 0x00000000U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_init_ratio = 0xb1
+ // .. .. ==> 0XF8006130[19:10] = 0x000000B1U
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002C400U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x0002C400U),
+ // .. .. reg_phy_wrlvl_init_ratio = 0x3
+ // .. .. ==> 0XF8006134[9:0] = 0x00000003U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000003U
+ // .. .. reg_phy_gatelvl_init_ratio = 0xbc
+ // .. .. ==> 0XF8006134[19:10] = 0x000000BCU
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002F000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0002F003U),
+ // .. .. reg_phy_wrlvl_init_ratio = 0x3
+ // .. .. ==> 0XF8006138[9:0] = 0x00000003U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000003U
+ // .. .. reg_phy_gatelvl_init_ratio = 0xbb
+ // .. .. ==> 0XF8006138[19:10] = 0x000000BBU
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002EC00U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0002EC03U),
+ // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+ // .. .. ==> 0XF8006140[9:0] = 0x00000035U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
+ // .. .. reg_phy_rd_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006140[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006140[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
+ // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+ // .. .. ==> 0XF8006144[9:0] = 0x00000035U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
+ // .. .. reg_phy_rd_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006144[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006144[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
+ // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+ // .. .. ==> 0XF8006148[9:0] = 0x00000035U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
+ // .. .. reg_phy_rd_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006148[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006148[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
+ // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+ // .. .. ==> 0XF800614C[9:0] = 0x00000035U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
+ // .. .. reg_phy_rd_dqs_slave_force = 0x0
+ // .. .. ==> 0XF800614C[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF800614C[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
+ // .. .. reg_phy_wr_dqs_slave_ratio = 0x77
+ // .. .. ==> 0XF8006154[9:0] = 0x00000077U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000077U
+ // .. .. reg_phy_wr_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006154[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006154[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000077U),
+ // .. .. reg_phy_wr_dqs_slave_ratio = 0x77
+ // .. .. ==> 0XF8006158[9:0] = 0x00000077U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000077U
+ // .. .. reg_phy_wr_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006158[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006158[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000077U),
+ // .. .. reg_phy_wr_dqs_slave_ratio = 0x83
+ // .. .. ==> 0XF800615C[9:0] = 0x00000083U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000083U
+ // .. .. reg_phy_wr_dqs_slave_force = 0x0
+ // .. .. ==> 0XF800615C[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF800615C[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000083U),
+ // .. .. reg_phy_wr_dqs_slave_ratio = 0x83
+ // .. .. ==> 0XF8006160[9:0] = 0x00000083U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000083U
+ // .. .. reg_phy_wr_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006160[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006160[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000083U),
+ // .. .. reg_phy_fifo_we_slave_ratio = 0x105
+ // .. .. ==> 0XF8006168[10:0] = 0x00000105U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000105U
+ // .. .. reg_phy_fifo_we_in_force = 0x0
+ // .. .. ==> 0XF8006168[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. reg_phy_fifo_we_in_delay = 0x0
+ // .. .. ==> 0XF8006168[20:12] = 0x00000000U
+ // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000105U),
+ // .. .. reg_phy_fifo_we_slave_ratio = 0x106
+ // .. .. ==> 0XF800616C[10:0] = 0x00000106U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000106U
+ // .. .. reg_phy_fifo_we_in_force = 0x0
+ // .. .. ==> 0XF800616C[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. reg_phy_fifo_we_in_delay = 0x0
+ // .. .. ==> 0XF800616C[20:12] = 0x00000000U
+ // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x00000106U),
+ // .. .. reg_phy_fifo_we_slave_ratio = 0x111
+ // .. .. ==> 0XF8006170[10:0] = 0x00000111U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000111U
+ // .. .. reg_phy_fifo_we_in_force = 0x0
+ // .. .. ==> 0XF8006170[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. reg_phy_fifo_we_in_delay = 0x0
+ // .. .. ==> 0XF8006170[20:12] = 0x00000000U
+ // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000111U),
+ // .. .. reg_phy_fifo_we_slave_ratio = 0x110
+ // .. .. ==> 0XF8006174[10:0] = 0x00000110U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000110U
+ // .. .. reg_phy_fifo_we_in_force = 0x0
+ // .. .. ==> 0XF8006174[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. reg_phy_fifo_we_in_delay = 0x0
+ // .. .. ==> 0XF8006174[20:12] = 0x00000000U
+ // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000110U),
+ // .. .. reg_phy_wr_data_slave_ratio = 0xb7
+ // .. .. ==> 0XF800617C[9:0] = 0x000000B7U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000B7U
+ // .. .. reg_phy_wr_data_slave_force = 0x0
+ // .. .. ==> 0XF800617C[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_data_slave_delay = 0x0
+ // .. .. ==> 0XF800617C[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000B7U),
+ // .. .. reg_phy_wr_data_slave_ratio = 0xb7
+ // .. .. ==> 0XF8006180[9:0] = 0x000000B7U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000B7U
+ // .. .. reg_phy_wr_data_slave_force = 0x0
+ // .. .. ==> 0XF8006180[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_data_slave_delay = 0x0
+ // .. .. ==> 0XF8006180[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000B7U),
+ // .. .. reg_phy_wr_data_slave_ratio = 0xc3
+ // .. .. ==> 0XF8006184[9:0] = 0x000000C3U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C3U
+ // .. .. reg_phy_wr_data_slave_force = 0x0
+ // .. .. ==> 0XF8006184[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_data_slave_delay = 0x0
+ // .. .. ==> 0XF8006184[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C3U),
+ // .. .. reg_phy_wr_data_slave_ratio = 0xc3
+ // .. .. ==> 0XF8006188[9:0] = 0x000000C3U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C3U
+ // .. .. reg_phy_wr_data_slave_force = 0x0
+ // .. .. ==> 0XF8006188[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_data_slave_delay = 0x0
+ // .. .. ==> 0XF8006188[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C3U),
+ // .. .. reg_phy_loopback = 0x0
+ // .. .. ==> 0XF8006190[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_phy_bl2 = 0x0
+ // .. .. ==> 0XF8006190[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_at_spd_atpg = 0x0
+ // .. .. ==> 0XF8006190[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_bist_enable = 0x0
+ // .. .. ==> 0XF8006190[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_bist_force_err = 0x0
+ // .. .. ==> 0XF8006190[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reg_phy_bist_mode = 0x0
+ // .. .. ==> 0XF8006190[6:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U
+ // .. .. reg_phy_invert_clkout = 0x1
+ // .. .. ==> 0XF8006190[7:7] = 0x00000001U
+ // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0
+ // .. .. ==> 0XF8006190[8:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. .. reg_phy_sel_logic = 0x0
+ // .. .. ==> 0XF8006190[9:9] = 0x00000000U
+ // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U
+ // .. .. reg_phy_ctrl_slave_ratio = 0x100
+ // .. .. ==> 0XF8006190[19:10] = 0x00000100U
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U
+ // .. .. reg_phy_ctrl_slave_force = 0x0
+ // .. .. ==> 0XF8006190[20:20] = 0x00000000U
+ // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U
+ // .. .. reg_phy_ctrl_slave_delay = 0x0
+ // .. .. ==> 0XF8006190[27:21] = 0x00000000U
+ // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U
+ // .. .. reg_phy_use_rank0_delays = 0x1
+ // .. .. ==> 0XF8006190[28:28] = 0x00000001U
+ // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
+ // .. .. reg_phy_lpddr = 0x0
+ // .. .. ==> 0XF8006190[29:29] = 0x00000000U
+ // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U
+ // .. .. reg_phy_cmd_latency = 0x0
+ // .. .. ==> 0XF8006190[30:30] = 0x00000000U
+ // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U
+ // .. .. reg_phy_int_lpbk = 0x0
+ // .. .. ==> 0XF8006190[31:31] = 0x00000000U
+ // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U),
+ // .. .. reg_phy_wr_rl_delay = 0x2
+ // .. .. ==> 0XF8006194[4:0] = 0x00000002U
+ // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U
+ // .. .. reg_phy_rd_rl_delay = 0x4
+ // .. .. ==> 0XF8006194[9:5] = 0x00000004U
+ // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U
+ // .. .. reg_phy_dll_lock_diff = 0xf
+ // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
+ // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U
+ // .. .. reg_phy_use_wr_level = 0x1
+ // .. .. ==> 0XF8006194[14:14] = 0x00000001U
+ // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U
+ // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
+ // .. .. ==> 0XF8006194[15:15] = 0x00000001U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U
+ // .. .. reg_phy_use_rd_data_eye_level = 0x1
+ // .. .. ==> 0XF8006194[16:16] = 0x00000001U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U
+ // .. .. reg_phy_dis_calib_rst = 0x0
+ // .. .. ==> 0XF8006194[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_phy_ctrl_slave_delay = 0x0
+ // .. .. ==> 0XF8006194[19:18] = 0x00000000U
+ // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
+ // .. .. reg_arb_page_addr_mask = 0x0
+ // .. .. ==> 0XF8006204[31:0] = 0x00000000U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
+ // .. .. reg_arb_pri_wr_portn = 0x3ff
+ // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_wr_portn = 0x0
+ // .. .. ==> 0XF8006208[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+ // .. .. ==> 0XF8006208[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+ // .. .. ==> 0XF8006208[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_rmw_portn = 0x1
+ // .. .. ==> 0XF8006208[19:19] = 0x00000001U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU),
+ // .. .. reg_arb_pri_wr_portn = 0x3ff
+ // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_wr_portn = 0x0
+ // .. .. ==> 0XF800620C[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+ // .. .. ==> 0XF800620C[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+ // .. .. ==> 0XF800620C[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_rmw_portn = 0x1
+ // .. .. ==> 0XF800620C[19:19] = 0x00000001U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU),
+ // .. .. reg_arb_pri_wr_portn = 0x3ff
+ // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_wr_portn = 0x0
+ // .. .. ==> 0XF8006210[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+ // .. .. ==> 0XF8006210[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+ // .. .. ==> 0XF8006210[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_rmw_portn = 0x1
+ // .. .. ==> 0XF8006210[19:19] = 0x00000001U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU),
+ // .. .. reg_arb_pri_wr_portn = 0x3ff
+ // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_wr_portn = 0x0
+ // .. .. ==> 0XF8006214[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+ // .. .. ==> 0XF8006214[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+ // .. .. ==> 0XF8006214[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_rmw_portn = 0x1
+ // .. .. ==> 0XF8006214[19:19] = 0x00000001U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU),
+ // .. .. reg_arb_pri_rd_portn = 0x3ff
+ // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_rd_portn = 0x0
+ // .. .. ==> 0XF8006218[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+ // .. .. ==> 0XF8006218[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+ // .. .. ==> 0XF8006218[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_set_hpr_rd_portn = 0x0
+ // .. .. ==> 0XF8006218[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
+ // .. .. reg_arb_pri_rd_portn = 0x3ff
+ // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_rd_portn = 0x0
+ // .. .. ==> 0XF800621C[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+ // .. .. ==> 0XF800621C[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+ // .. .. ==> 0XF800621C[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_set_hpr_rd_portn = 0x0
+ // .. .. ==> 0XF800621C[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
+ // .. .. reg_arb_pri_rd_portn = 0x3ff
+ // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_rd_portn = 0x0
+ // .. .. ==> 0XF8006220[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+ // .. .. ==> 0XF8006220[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+ // .. .. ==> 0XF8006220[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_set_hpr_rd_portn = 0x0
+ // .. .. ==> 0XF8006220[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
+ // .. .. reg_arb_pri_rd_portn = 0x3ff
+ // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_rd_portn = 0x0
+ // .. .. ==> 0XF8006224[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+ // .. .. ==> 0XF8006224[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+ // .. .. ==> 0XF8006224[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_set_hpr_rd_portn = 0x0
+ // .. .. ==> 0XF8006224[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
+ // .. .. reg_ddrc_lpddr2 = 0x0
+ // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_per_bank_refresh = 0x0
+ // .. .. ==> 0XF80062A8[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_ddrc_derate_enable = 0x0
+ // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr4_margin = 0x0
+ // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U),
+ // .. .. reg_ddrc_mr4_read_interval = 0x0
+ // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
+ // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
+ // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U
+ // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
+ // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
+ // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U
+ // .. .. reg_ddrc_t_mrw = 0x5
+ // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
+ // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8
+ // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U
+ // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
+ // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
+ // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U
+ // .. ..
+ EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
+ // .. .. START: POLL ON DCI STATUS
+ // .. .. DONE = 1
+ // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
+ // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U
+ // .. ..
+ EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+ // .. .. FINISH: POLL ON DCI STATUS
+ // .. .. START: UNLOCK DDR
+ // .. .. reg_ddrc_soft_rstb = 0x1
+ // .. .. ==> 0XF8006000[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_ddrc_powerdown_en = 0x0
+ // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_ddrc_data_bus_width = 0x0
+ // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U
+ // .. .. reg_ddrc_burst8_refresh = 0x0
+ // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U
+ // .. .. reg_ddrc_rdwr_idle_gap = 1
+ // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+ // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U
+ // .. .. reg_ddrc_dis_rd_bypass = 0x0
+ // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+ // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_act_bypass = 0x0
+ // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_auto_refresh = 0x0
+ // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
+ // .. .. FINISH: UNLOCK DDR
+ // .. .. START: CHECK DDR STATUS
+ // .. .. ddrc_reg_operating_mode = 1
+ // .. .. ==> 0XF8006054[2:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U
+ // .. ..
+ EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+ // .. .. FINISH: CHECK DDR STATUS
+ // .. FINISH: DDR INITIALIZATION
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_mio_init_data_1_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: OCM REMAPPING
+ // .. FINISH: OCM REMAPPING
+ // .. START: DDRIOB SETTINGS
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B40[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x0
+ // .. ==> 0XF8000B40[2:1] = 0x00000000U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000000U
+ // .. DCI_UPDATE = 0x0
+ // .. ==> 0XF8000B40[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x0
+ // .. ==> 0XF8000B40[4:4] = 0x00000000U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. DCR_TYPE = 0x0
+ // .. ==> 0XF8000B40[6:5] = 0x00000000U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000000U
+ // .. IBUF_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B40[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B40[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B40[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B40[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B44[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x0
+ // .. ==> 0XF8000B44[2:1] = 0x00000000U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000000U
+ // .. DCI_UPDATE = 0x0
+ // .. ==> 0XF8000B44[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x0
+ // .. ==> 0XF8000B44[4:4] = 0x00000000U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. DCR_TYPE = 0x0
+ // .. ==> 0XF8000B44[6:5] = 0x00000000U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000000U
+ // .. IBUF_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B44[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B44[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B44[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B44[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B48[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x1
+ // .. ==> 0XF8000B48[2:1] = 0x00000001U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000002U
+ // .. DCI_UPDATE = 0x0
+ // .. ==> 0XF8000B48[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x1
+ // .. ==> 0XF8000B48[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. DCR_TYPE = 0x3
+ // .. ==> 0XF8000B48[6:5] = 0x00000003U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000060U
+ // .. IBUF_DISABLE_MODE = 0
+ // .. ==> 0XF8000B48[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0
+ // .. ==> 0XF8000B48[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B48[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B48[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B4C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x1
+ // .. ==> 0XF8000B4C[2:1] = 0x00000001U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000002U
+ // .. DCI_UPDATE = 0x0
+ // .. ==> 0XF8000B4C[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x1
+ // .. ==> 0XF8000B4C[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. DCR_TYPE = 0x3
+ // .. ==> 0XF8000B4C[6:5] = 0x00000003U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000060U
+ // .. IBUF_DISABLE_MODE = 0
+ // .. ==> 0XF8000B4C[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0
+ // .. ==> 0XF8000B4C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B4C[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B4C[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B50[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x2
+ // .. ==> 0XF8000B50[2:1] = 0x00000002U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000004U
+ // .. DCI_UPDATE = 0x0
+ // .. ==> 0XF8000B50[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x1
+ // .. ==> 0XF8000B50[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. DCR_TYPE = 0x3
+ // .. ==> 0XF8000B50[6:5] = 0x00000003U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000060U
+ // .. IBUF_DISABLE_MODE = 0
+ // .. ==> 0XF8000B50[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0
+ // .. ==> 0XF8000B50[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B50[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B50[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B54[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x2
+ // .. ==> 0XF8000B54[2:1] = 0x00000002U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000004U
+ // .. DCI_UPDATE = 0x0
+ // .. ==> 0XF8000B54[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x1
+ // .. ==> 0XF8000B54[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. DCR_TYPE = 0x3
+ // .. ==> 0XF8000B54[6:5] = 0x00000003U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000060U
+ // .. IBUF_DISABLE_MODE = 0
+ // .. ==> 0XF8000B54[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0
+ // .. ==> 0XF8000B54[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B54[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B54[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B58[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x0
+ // .. ==> 0XF8000B58[2:1] = 0x00000000U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000000U
+ // .. DCI_UPDATE = 0x0
+ // .. ==> 0XF8000B58[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x0
+ // .. ==> 0XF8000B58[4:4] = 0x00000000U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. DCR_TYPE = 0x0
+ // .. ==> 0XF8000B58[6:5] = 0x00000000U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000000U
+ // .. IBUF_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B58[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B58[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B58[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B58[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
+ // .. DRIVE_P = 0x1c
+ // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
+ // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
+ // .. DRIVE_N = 0xc
+ // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
+ // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
+ // .. SLEW_P = 0x3
+ // .. ==> 0XF8000B5C[18:14] = 0x00000003U
+ // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U
+ // .. SLEW_N = 0x3
+ // .. ==> 0XF8000B5C[23:19] = 0x00000003U
+ // .. ==> MASK : 0x00F80000U VAL : 0x00180000U
+ // .. GTL = 0x0
+ // .. ==> 0XF8000B5C[26:24] = 0x00000000U
+ // .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. RTERM = 0x0
+ // .. ==> 0XF8000B5C[31:27] = 0x00000000U
+ // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
+ // .. DRIVE_P = 0x1c
+ // .. ==> 0XF8000B60[6:0] = 0x0000001CU
+ // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
+ // .. DRIVE_N = 0xc
+ // .. ==> 0XF8000B60[13:7] = 0x0000000CU
+ // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
+ // .. SLEW_P = 0x6
+ // .. ==> 0XF8000B60[18:14] = 0x00000006U
+ // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
+ // .. SLEW_N = 0x1f
+ // .. ==> 0XF8000B60[23:19] = 0x0000001FU
+ // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
+ // .. GTL = 0x0
+ // .. ==> 0XF8000B60[26:24] = 0x00000000U
+ // .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. RTERM = 0x0
+ // .. ==> 0XF8000B60[31:27] = 0x00000000U
+ // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
+ // .. DRIVE_P = 0x1c
+ // .. ==> 0XF8000B64[6:0] = 0x0000001CU
+ // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
+ // .. DRIVE_N = 0xc
+ // .. ==> 0XF8000B64[13:7] = 0x0000000CU
+ // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
+ // .. SLEW_P = 0x6
+ // .. ==> 0XF8000B64[18:14] = 0x00000006U
+ // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
+ // .. SLEW_N = 0x1f
+ // .. ==> 0XF8000B64[23:19] = 0x0000001FU
+ // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
+ // .. GTL = 0x0
+ // .. ==> 0XF8000B64[26:24] = 0x00000000U
+ // .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. RTERM = 0x0
+ // .. ==> 0XF8000B64[31:27] = 0x00000000U
+ // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
+ // .. DRIVE_P = 0x1c
+ // .. ==> 0XF8000B68[6:0] = 0x0000001CU
+ // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
+ // .. DRIVE_N = 0xc
+ // .. ==> 0XF8000B68[13:7] = 0x0000000CU
+ // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
+ // .. SLEW_P = 0x6
+ // .. ==> 0XF8000B68[18:14] = 0x00000006U
+ // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
+ // .. SLEW_N = 0x1f
+ // .. ==> 0XF8000B68[23:19] = 0x0000001FU
+ // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
+ // .. GTL = 0x0
+ // .. ==> 0XF8000B68[26:24] = 0x00000000U
+ // .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. RTERM = 0x0
+ // .. ==> 0XF8000B68[31:27] = 0x00000000U
+ // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
+ // .. VREF_INT_EN = 0x1
+ // .. ==> 0XF8000B6C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. VREF_SEL = 0x4
+ // .. ==> 0XF8000B6C[4:1] = 0x00000004U
+ // .. ==> MASK : 0x0000001EU VAL : 0x00000008U
+ // .. VREF_EXT_EN = 0x0
+ // .. ==> 0XF8000B6C[6:5] = 0x00000000U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000000U
+ // .. VREF_PULLUP_EN = 0x0
+ // .. ==> 0XF8000B6C[8:7] = 0x00000000U
+ // .. ==> MASK : 0x00000180U VAL : 0x00000000U
+ // .. REFIO_EN = 0x1
+ // .. ==> 0XF8000B6C[9:9] = 0x00000001U
+ // .. ==> MASK : 0x00000200U VAL : 0x00000200U
+ // .. REFIO_PULLUP_EN = 0x0
+ // .. ==> 0XF8000B6C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DRST_B_PULLUP_EN = 0x0
+ // .. ==> 0XF8000B6C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // .. CKE_PULLUP_EN = 0x0
+ // .. ==> 0XF8000B6C[14:14] = 0x00000000U
+ // .. ==> MASK : 0x00004000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B6C, 0x000073FFU ,0x00000209U),
+ // .. .. START: ASSERT RESET
+ // .. .. RESET = 1
+ // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. VRN_OUT = 0x1
+ // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U),
+ // .. .. FINISH: ASSERT RESET
+ // .. .. START: DEASSERT RESET
+ // .. .. RESET = 0
+ // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. VRN_OUT = 0x1
+ // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
+ // .. .. FINISH: DEASSERT RESET
+ // .. .. RESET = 0x1
+ // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ENABLE = 0x1
+ // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. .. VRP_TRI = 0x0
+ // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. VRN_TRI = 0x0
+ // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. VRP_OUT = 0x0
+ // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. VRN_OUT = 0x1
+ // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
+ // .. .. NREF_OPT1 = 0x0
+ // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
+ // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U
+ // .. .. NREF_OPT2 = 0x0
+ // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U
+ // .. .. NREF_OPT4 = 0x1
+ // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
+ // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U
+ // .. .. PREF_OPT1 = 0x0
+ // .. .. ==> 0XF8000B70[16:14] = 0x00000000U
+ // .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U
+ // .. .. PREF_OPT2 = 0x0
+ // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
+ // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U
+ // .. .. UPDATE_CONTROL = 0x0
+ // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
+ // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U
+ // .. .. INIT_COMPLETE = 0x0
+ // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
+ // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U
+ // .. .. TST_CLK = 0x0
+ // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
+ // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U
+ // .. .. TST_HLN = 0x0
+ // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
+ // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U
+ // .. .. TST_HLP = 0x0
+ // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
+ // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U
+ // .. .. TST_RST = 0x0
+ // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
+ // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
+ // .. .. INT_DCI_EN = 0x0
+ // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
+ // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U),
+ // .. FINISH: DDRIOB SETTINGS
+ // .. START: MIO PROGRAMMING
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000700[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000700[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000700[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000700[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000700[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000700[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000700[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000700[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000700[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000704[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000704[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000704[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000704[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000704[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000704[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000704[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000704[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000704[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00000602U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000708[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000708[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000708[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000708[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000708[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000708[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000708[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000708[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000708[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000602U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800070C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF800070C[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800070C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800070C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800070C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800070C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF800070C[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF800070C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800070C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000602U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000710[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000710[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000710[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000710[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000710[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000710[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000710[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000710[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000710[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000602U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000714[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000714[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000714[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000714[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000714[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000714[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000714[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000714[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000714[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000602U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000718[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000718[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000718[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000718[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000718[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000718[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000718[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000718[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000718[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000602U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800071C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800071C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800071C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800071C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800071C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800071C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF800071C[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF800071C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800071C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000720[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000720[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000720[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000720[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000720[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000720[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000720[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000720[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000720[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000602U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000724[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000724[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000724[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000724[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000724[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000724[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000724[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000724[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000724[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000728[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000728[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000728[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000728[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000728[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000728[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000728[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000728[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000728[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800072C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800072C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800072C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800072C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800072C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800072C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF800072C[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF800072C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800072C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000730[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000730[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000730[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000730[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000730[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000730[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000730[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000730[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000730[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000734[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000734[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000734[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000734[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000734[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000734[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000734[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000734[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000734[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000738[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000738[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000738[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000738[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000738[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000738[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000738[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000738[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000738[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800073C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800073C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800073C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800073C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800073C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800073C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF800073C[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF800073C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800073C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000740[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000740[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000740[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000740[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000740[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000740[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000740[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000740[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000740[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000744[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000744[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000744[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000744[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000744[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000744[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000744[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000744[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000744[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000748[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000748[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000748[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000748[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000748[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000748[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000748[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000748[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000748[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800074C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF800074C[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800074C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800074C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800074C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800074C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800074C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800074C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800074C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000750[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000750[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000750[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000750[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000750[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000750[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000750[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000750[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000750[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000754[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000754[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000754[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000754[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000754[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000754[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000754[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000754[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000754[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000202U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000758[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000758[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000758[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000758[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000758[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000758[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000758[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000758[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000758[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000203U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF800075C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF800075C[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800075C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800075C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800075C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800075C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800075C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800075C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800075C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000203U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000760[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000760[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000760[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000760[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000760[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000760[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000760[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000760[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000760[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000203U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000764[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000764[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000764[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000764[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000764[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000764[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000764[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000764[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000764[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000203U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000768[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000768[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000768[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000768[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000768[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000768[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000768[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000768[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000768[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000203U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF800076C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF800076C[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800076C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800076C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800076C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800076C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800076C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800076C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800076C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000203U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000770[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000770[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000770[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000770[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000770[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000770[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000770[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000770[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000770[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000774[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000774[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000774[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000774[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000774[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000774[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000774[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000774[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000774[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000778[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000778[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000778[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000778[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000778[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000778[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000778[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000778[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000778[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF800077C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800077C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF800077C[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800077C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800077C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800077C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800077C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800077C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800077C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000780[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000780[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000780[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000780[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000780[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000780[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000780[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000780[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000780[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000784[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000784[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000784[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000784[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000784[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000784[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000784[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000784[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000784[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000788[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000788[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000788[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000788[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000788[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000788[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000788[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000788[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000788[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800078C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800078C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF800078C[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800078C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800078C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800078C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800078C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800078C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800078C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000790[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000790[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000790[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000790[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000790[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000790[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000790[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000790[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000790[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000794[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000794[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000794[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000794[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000794[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000794[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000794[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000794[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000794[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000798[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000798[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000798[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000798[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000798[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000798[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000798[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000798[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000798[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800079C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800079C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF800079C[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800079C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800079C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800079C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800079C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800079C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800079C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007A0[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007A0[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007A0[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007A0[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007A0[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007A0[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007A0[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007A0[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007A0[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007A4[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007A4[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007A4[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007A4[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007A4[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007A4[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007A4[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007A4[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007A4[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007A8[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007A8[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007A8[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007A8[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007A8[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007A8[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007A8[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007A8[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007A8[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007AC[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007AC[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007AC[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007AC[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007AC[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007AC[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007AC[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007AC[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007AC[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007B0[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007B0[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007B0[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007B0[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007B0[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007B0[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007B0[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007B0[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007B0[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007B4[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007B4[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007B4[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007B4[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007B4[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007B4[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007B4[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007B4[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007B4[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000280U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF80007B8[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. Speed = 0
+ // .. ==> 0XF80007B8[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007B8[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007B8[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007B8[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007B8, 0x00003F01U ,0x00000201U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007BC[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007BC[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007BC[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007BC[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF80007BC[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF80007BC[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007BC[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007BC[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007BC[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00000200U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007C0[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007C0[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007C0[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007C0[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 7
+ // .. ==> 0XF80007C0[7:5] = 0x00000007U
+ // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U
+ // .. Speed = 0
+ // .. ==> 0XF80007C0[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007C0[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007C0[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007C0[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF80007C4[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007C4[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007C4[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007C4[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 7
+ // .. ==> 0XF80007C4[7:5] = 0x00000007U
+ // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U
+ // .. Speed = 0
+ // .. ==> 0XF80007C4[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007C4[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007C4[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007C4[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF80007C8[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. Speed = 0
+ // .. ==> 0XF80007C8[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007C8[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007C8[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007C8[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007C8, 0x00003F01U ,0x00000201U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007CC[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007CC[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007CC[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007CC[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF80007CC[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF80007CC[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007CC[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007CC[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007CC[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00000200U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007D0[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007D0[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007D0[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007D0[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007D0[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007D0[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007D0[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007D0[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007D0[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007D4[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007D4[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007D4[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007D4[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007D4[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007D4[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007D4[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007D4[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007D4[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U),
+ // .. SDIO0_WP_SEL = 50
+ // .. ==> 0XF8000830[5:0] = 0x00000032U
+ // .. ==> MASK : 0x0000003FU VAL : 0x00000032U
+ // .. SDIO0_CD_SEL = 46
+ // .. ==> 0XF8000830[21:16] = 0x0000002EU
+ // .. ==> MASK : 0x003F0000U VAL : 0x002E0000U
+ // ..
+ EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x002E0032U),
+ // .. FINISH: MIO PROGRAMMING
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_peripherals_init_data_1_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+ // .. IBUF_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B48[7:7] = 0x00000001U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. TERM_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B48[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // ..
+ EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
+ // .. IBUF_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B4C[7:7] = 0x00000001U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. TERM_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B4C[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // ..
+ EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
+ // .. IBUF_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B50[7:7] = 0x00000001U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. TERM_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B50[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // ..
+ EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
+ // .. IBUF_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B54[7:7] = 0x00000001U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. TERM_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B54[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // ..
+ EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
+ // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // .. START: SRAM/NOR SET OPMODE
+ // .. FINISH: SRAM/NOR SET OPMODE
+ // .. START: UART REGISTERS
+ // .. BDIV = 0x6
+ // .. ==> 0XE0001034[7:0] = 0x00000006U
+ // .. ==> MASK : 0x000000FFU VAL : 0x00000006U
+ // ..
+ EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
+ // .. CD = 0x3e
+ // .. ==> 0XE0001018[15:0] = 0x0000003EU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU
+ // ..
+ EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
+ // .. STPBRK = 0x0
+ // .. ==> 0XE0001000[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. STTBRK = 0x0
+ // .. ==> 0XE0001000[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. RSTTO = 0x0
+ // .. ==> 0XE0001000[6:6] = 0x00000000U
+ // .. ==> MASK : 0x00000040U VAL : 0x00000000U
+ // .. TXDIS = 0x0
+ // .. ==> 0XE0001000[5:5] = 0x00000000U
+ // .. ==> MASK : 0x00000020U VAL : 0x00000000U
+ // .. TXEN = 0x1
+ // .. ==> 0XE0001000[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. RXDIS = 0x0
+ // .. ==> 0XE0001000[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. RXEN = 0x1
+ // .. ==> 0XE0001000[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. TXRES = 0x1
+ // .. ==> 0XE0001000[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. RXRES = 0x1
+ // .. ==> 0XE0001000[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // ..
+ EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
+ // .. IRMODE = 0x0
+ // .. ==> 0XE0001004[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. UCLKEN = 0x0
+ // .. ==> 0XE0001004[10:10] = 0x00000000U
+ // .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. CHMODE = 0x0
+ // .. ==> 0XE0001004[9:8] = 0x00000000U
+ // .. ==> MASK : 0x00000300U VAL : 0x00000000U
+ // .. NBSTOP = 0x0
+ // .. ==> 0XE0001004[7:6] = 0x00000000U
+ // .. ==> MASK : 0x000000C0U VAL : 0x00000000U
+ // .. PAR = 0x4
+ // .. ==> 0XE0001004[5:3] = 0x00000004U
+ // .. ==> MASK : 0x00000038U VAL : 0x00000020U
+ // .. CHRL = 0x0
+ // .. ==> 0XE0001004[2:1] = 0x00000000U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000000U
+ // .. CLKS = 0x0
+ // .. ==> 0XE0001004[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U),
+ // .. FINISH: UART REGISTERS
+ // .. START: QSPI REGISTERS
+ // .. Holdb_dr = 1
+ // .. ==> 0XE000D000[19:19] = 0x00000001U
+ // .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // ..
+ EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
+ // .. FINISH: QSPI REGISTERS
+ // .. START: PL POWER ON RESET REGISTERS
+ // .. PCFG_POR_CNT_4K = 0
+ // .. ==> 0XF8007000[29:29] = 0x00000000U
+ // .. ==> MASK : 0x20000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
+ // .. FINISH: PL POWER ON RESET REGISTERS
+ // .. START: SMC TIMING CALCULATION REGISTER UPDATE
+ // .. .. START: NAND SET CYCLE
+ // .. .. FINISH: NAND SET CYCLE
+ // .. .. START: OPMODE
+ // .. .. FINISH: OPMODE
+ // .. .. START: DIRECT COMMAND
+ // .. .. FINISH: DIRECT COMMAND
+ // .. .. START: SRAM/NOR CS0 SET CYCLE
+ // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
+ // .. .. START: DIRECT COMMAND
+ // .. .. FINISH: DIRECT COMMAND
+ // .. .. START: NOR CS0 BASE ADDRESS
+ // .. .. FINISH: NOR CS0 BASE ADDRESS
+ // .. .. START: SRAM/NOR CS1 SET CYCLE
+ // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
+ // .. .. START: DIRECT COMMAND
+ // .. .. FINISH: DIRECT COMMAND
+ // .. .. START: NOR CS1 BASE ADDRESS
+ // .. .. FINISH: NOR CS1 BASE ADDRESS
+ // .. .. START: USB RESET
+ // .. .. .. START: USB0 RESET
+ // .. .. .. .. START: DIR MODE BANK 0
+ // .. .. .. .. DIRECTION_0 = 0x80
+ // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U
+ // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U),
+ // .. .. .. .. FINISH: DIR MODE BANK 0
+ // .. .. .. .. START: DIR MODE BANK 1
+ // .. .. .. .. FINISH: DIR MODE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. MASK_0_LSW = 0xff7f
+ // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+ // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U
+ // .. .. .. .. DATA_0_LSW = 0x80
+ // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+ // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. START: OUTPUT ENABLE BANK 0
+ // .. .. .. .. OP_ENABLE_0 = 0x80
+ // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U
+ // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U),
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+ // .. .. .. .. START: OUTPUT ENABLE BANK 1
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. MASK_0_LSW = 0xff7f
+ // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+ // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U
+ // .. .. .. .. DATA_0_LSW = 0x0
+ // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+ // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U),
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. START: ADD 1 MS DELAY
+ // .. .. .. ..
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ // .. .. .. .. FINISH: ADD 1 MS DELAY
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. MASK_0_LSW = 0xff7f
+ // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+ // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U
+ // .. .. .. .. DATA_0_LSW = 0x80
+ // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+ // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. FINISH: USB0 RESET
+ // .. .. .. START: USB1 RESET
+ // .. .. .. .. START: DIR MODE BANK 0
+ // .. .. .. .. FINISH: DIR MODE BANK 0
+ // .. .. .. .. START: DIR MODE BANK 1
+ // .. .. .. .. FINISH: DIR MODE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. START: OUTPUT ENABLE BANK 0
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+ // .. .. .. .. START: OUTPUT ENABLE BANK 1
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. START: ADD 1 MS DELAY
+ // .. .. .. ..
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ // .. .. .. .. FINISH: ADD 1 MS DELAY
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. FINISH: USB1 RESET
+ // .. .. FINISH: USB RESET
+ // .. .. START: ENET RESET
+ // .. .. .. START: ENET0 RESET
+ // .. .. .. .. START: DIR MODE BANK 0
+ // .. .. .. .. FINISH: DIR MODE BANK 0
+ // .. .. .. .. START: DIR MODE BANK 1
+ // .. .. .. .. FINISH: DIR MODE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. START: OUTPUT ENABLE BANK 0
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+ // .. .. .. .. START: OUTPUT ENABLE BANK 1
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. START: ADD 1 MS DELAY
+ // .. .. .. ..
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ // .. .. .. .. FINISH: ADD 1 MS DELAY
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. FINISH: ENET0 RESET
+ // .. .. .. START: ENET1 RESET
+ // .. .. .. .. START: DIR MODE BANK 0
+ // .. .. .. .. FINISH: DIR MODE BANK 0
+ // .. .. .. .. START: DIR MODE BANK 1
+ // .. .. .. .. FINISH: DIR MODE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. START: OUTPUT ENABLE BANK 0
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+ // .. .. .. .. START: OUTPUT ENABLE BANK 1
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. START: ADD 1 MS DELAY
+ // .. .. .. ..
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ // .. .. .. .. FINISH: ADD 1 MS DELAY
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. FINISH: ENET1 RESET
+ // .. .. FINISH: ENET RESET
+ // .. .. START: I2C RESET
+ // .. .. .. START: I2C0 RESET
+ // .. .. .. .. START: DIR MODE GPIO BANK0
+ // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+ // .. .. .. .. START: DIR MODE GPIO BANK1
+ // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. START: OUTPUT ENABLE
+ // .. .. .. .. FINISH: OUTPUT ENABLE
+ // .. .. .. .. START: OUTPUT ENABLE
+ // .. .. .. .. FINISH: OUTPUT ENABLE
+ // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. START: ADD 1 MS DELAY
+ // .. .. .. ..
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ // .. .. .. .. FINISH: ADD 1 MS DELAY
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. FINISH: I2C0 RESET
+ // .. .. .. START: I2C1 RESET
+ // .. .. .. .. START: DIR MODE GPIO BANK0
+ // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+ // .. .. .. .. START: DIR MODE GPIO BANK1
+ // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. START: OUTPUT ENABLE
+ // .. .. .. .. FINISH: OUTPUT ENABLE
+ // .. .. .. .. START: OUTPUT ENABLE
+ // .. .. .. .. FINISH: OUTPUT ENABLE
+ // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. START: ADD 1 MS DELAY
+ // .. .. .. ..
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ // .. .. .. .. FINISH: ADD 1 MS DELAY
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. FINISH: I2C1 RESET
+ // .. .. FINISH: I2C RESET
+ // .. .. START: NOR CHIP SELECT
+ // .. .. .. START: DIR MODE BANK 0
+ // .. .. .. FINISH: DIR MODE BANK 0
+ // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. START: OUTPUT ENABLE BANK 0
+ // .. .. .. FINISH: OUTPUT ENABLE BANK 0
+ // .. .. FINISH: NOR CHIP SELECT
+ // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_post_config_1_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: ENABLING LEVEL SHIFTER
+ // .. USER_INP_ICT_EN_0 = 3
+ // .. ==> 0XF8000900[1:0] = 0x00000003U
+ // .. ==> MASK : 0x00000003U VAL : 0x00000003U
+ // .. USER_INP_ICT_EN_1 = 3
+ // .. ==> 0XF8000900[3:2] = 0x00000003U
+ // .. ==> MASK : 0x0000000CU VAL : 0x0000000CU
+ // ..
+ EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
+ // .. FINISH: ENABLING LEVEL SHIFTER
+ // .. START: FPGA RESETS TO 0
+ // .. reserved_3 = 0
+ // .. ==> 0XF8000240[31:25] = 0x00000000U
+ // .. ==> MASK : 0xFE000000U VAL : 0x00000000U
+ // .. FPGA_ACP_RST = 0
+ // .. ==> 0XF8000240[24:24] = 0x00000000U
+ // .. ==> MASK : 0x01000000U VAL : 0x00000000U
+ // .. FPGA_AXDS3_RST = 0
+ // .. ==> 0XF8000240[23:23] = 0x00000000U
+ // .. ==> MASK : 0x00800000U VAL : 0x00000000U
+ // .. FPGA_AXDS2_RST = 0
+ // .. ==> 0XF8000240[22:22] = 0x00000000U
+ // .. ==> MASK : 0x00400000U VAL : 0x00000000U
+ // .. FPGA_AXDS1_RST = 0
+ // .. ==> 0XF8000240[21:21] = 0x00000000U
+ // .. ==> MASK : 0x00200000U VAL : 0x00000000U
+ // .. FPGA_AXDS0_RST = 0
+ // .. ==> 0XF8000240[20:20] = 0x00000000U
+ // .. ==> MASK : 0x00100000U VAL : 0x00000000U
+ // .. reserved_2 = 0
+ // .. ==> 0XF8000240[19:18] = 0x00000000U
+ // .. ==> MASK : 0x000C0000U VAL : 0x00000000U
+ // .. FSSW1_FPGA_RST = 0
+ // .. ==> 0XF8000240[17:17] = 0x00000000U
+ // .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. FSSW0_FPGA_RST = 0
+ // .. ==> 0XF8000240[16:16] = 0x00000000U
+ // .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. reserved_1 = 0
+ // .. ==> 0XF8000240[15:14] = 0x00000000U
+ // .. ==> MASK : 0x0000C000U VAL : 0x00000000U
+ // .. FPGA_FMSW1_RST = 0
+ // .. ==> 0XF8000240[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // .. FPGA_FMSW0_RST = 0
+ // .. ==> 0XF8000240[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. FPGA_DMA3_RST = 0
+ // .. ==> 0XF8000240[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. FPGA_DMA2_RST = 0
+ // .. ==> 0XF8000240[10:10] = 0x00000000U
+ // .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. FPGA_DMA1_RST = 0
+ // .. ==> 0XF8000240[9:9] = 0x00000000U
+ // .. ==> MASK : 0x00000200U VAL : 0x00000000U
+ // .. FPGA_DMA0_RST = 0
+ // .. ==> 0XF8000240[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. reserved = 0
+ // .. ==> 0XF8000240[7:4] = 0x00000000U
+ // .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. FPGA3_OUT_RST = 0
+ // .. ==> 0XF8000240[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. FPGA2_OUT_RST = 0
+ // .. ==> 0XF8000240[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. FPGA1_OUT_RST = 0
+ // .. ==> 0XF8000240[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. FPGA0_OUT_RST = 0
+ // .. ==> 0XF8000240[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
+ // .. FINISH: FPGA RESETS TO 0
+ // .. START: AFI REGISTERS
+ // .. .. START: AFI0 REGISTERS
+ // .. .. FINISH: AFI0 REGISTERS
+ // .. .. START: AFI1 REGISTERS
+ // .. .. FINISH: AFI1 REGISTERS
+ // .. .. START: AFI2 REGISTERS
+ // .. .. FINISH: AFI2 REGISTERS
+ // .. .. START: AFI3 REGISTERS
+ // .. .. FINISH: AFI3 REGISTERS
+ // .. FINISH: AFI REGISTERS
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_debug_1_0[] = {
+ // START: top
+ // .. START: CROSS TRIGGER CONFIGURATIONS
+ // .. .. START: UNLOCKING CTI REGISTERS
+ // .. .. KEY = 0XC5ACCE55
+ // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
+ // .. ..
+ EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
+ // .. .. KEY = 0XC5ACCE55
+ // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
+ // .. ..
+ EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
+ // .. .. KEY = 0XC5ACCE55
+ // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
+ // .. ..
+ EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
+ // .. .. FINISH: UNLOCKING CTI REGISTERS
+ // .. .. START: ENABLING CTI MODULES AND CHANNELS
+ // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
+ // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+ // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+ // .. FINISH: CROSS TRIGGER CONFIGURATIONS
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+
+#include "xil_io.h"
+#define PS7_MASK_POLL_TIME 100000000
+
+char*
+getPS7MessageInfo(unsigned key) {
+
+ char* err_msg = "";
+ switch (key) {
+ case PS7_INIT_SUCCESS: err_msg = "PS7 initialization successful"; break;
+ case PS7_INIT_CORRUPT: err_msg = "PS7 init Data Corrupted"; break;
+ case PS7_INIT_TIMEOUT: err_msg = "PS7 init mask poll timeout"; break;
+ case PS7_POLL_FAILED_DDR_INIT: err_msg = "Mask Poll failed for DDR Init"; break;
+ case PS7_POLL_FAILED_DMA: err_msg = "Mask Poll failed for PLL Init"; break;
+ case PS7_POLL_FAILED_PLL: err_msg = "Mask Poll failed for DMA done bit"; break;
+ default: err_msg = "Undefined error status"; break;
+ }
+
+ return err_msg;
+}
+
+unsigned long
+ps7GetSiliconVersion () {
+ // Read PS version from MCTRL register [31:28]
+ unsigned long mask = 0xF0000000;
+ unsigned long *addr = (unsigned long*) 0XF8007080;
+ unsigned long ps_version = (*addr & mask) >> 28;
+ return ps_version;
+}
+
+void mask_write (unsigned long add , unsigned long mask, unsigned long val ) {
+ unsigned long *addr = (unsigned long*) add;
+ *addr = ( val & mask ) | ( *addr & ~mask);
+ //xil_printf("MaskWrite : 0x%x--> 0x%x \n \r" ,add, *addr);
+}
+
+
+int mask_poll(unsigned long add , unsigned long mask ) {
+ volatile unsigned long *addr = (volatile unsigned long*) add;
+ int i = 0;
+ while (!(*addr & mask)) {
+ if (i == PS7_MASK_POLL_TIME) {
+ return -1;
+ }
+ i++;
+ }
+ return 1;
+ //xil_printf("MaskPoll : 0x%x --> 0x%x \n \r" , add, *addr);
+}
+
+unsigned long mask_read(unsigned long add , unsigned long mask ) {
+ unsigned long *addr = (unsigned long*) add;
+ unsigned long val = (*addr & mask);
+ //xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val);
+ return val;
+}
+
+
+
+int
+ps7_config(unsigned long * ps7_config_init)
+{
+ unsigned long *ptr = ps7_config_init;
+
+ unsigned long opcode; // current instruction ..
+ unsigned long args[16]; // no opcode has so many args ...
+ int numargs; // number of arguments of this instruction
+ int j; // general purpose index
+
+ volatile unsigned long *addr; // some variable to make code readable
+ unsigned long val,mask; // some variable to make code readable
+
+ int finish = -1 ; // loop while this is negative !
+ int i = 0; // Timeout variable
+
+ while( finish < 0 ) {
+ numargs = ptr[0] & 0xF;
+ opcode = ptr[0] >> 4;
+
+ for( j = 0 ; j < numargs ; j ++ )
+ args[j] = ptr[j+1];
+ ptr += numargs + 1;
+
+
+ switch ( opcode ) {
+
+ case OPCODE_EXIT:
+ finish = PS7_INIT_SUCCESS;
+ break;
+
+ case OPCODE_CLEAR:
+ addr = (unsigned long*) args[0];
+ *addr = 0;
+ break;
+
+ case OPCODE_WRITE:
+ addr = (unsigned long*) args[0];
+ val = args[1];
+ *addr = val;
+ break;
+
+ case OPCODE_MASKWRITE:
+ addr = (unsigned long*) args[0];
+ mask = args[1];
+ val = args[2];
+ *addr = ( val & mask ) | ( *addr & ~mask);
+ break;
+
+ case OPCODE_MASKPOLL:
+ addr = (unsigned long*) args[0];
+ mask = args[1];
+ i = 0;
+ while (!(*addr & mask)) {
+ if (i == PS7_MASK_POLL_TIME) {
+ finish = PS7_INIT_TIMEOUT;
+ break;
+ }
+ i++;
+ }
+ break;
+ case OPCODE_MASKDELAY:
+ addr = (unsigned long*) args[0];
+ mask = args[1];
+ int delay = get_number_of_cycles_for_delay(mask);
+ perf_reset_and_start_timer();
+ while ((*addr < delay)) {
+ }
+ break;
+ default:
+ finish = PS7_INIT_CORRUPT;
+ break;
+ }
+ }
+ return finish;
+}
+
+unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0;
+unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0;
+unsigned long *ps7_clock_init_data = ps7_clock_init_data_3_0;
+unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0;
+unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
+
+int
+ps7_post_config()
+{
+ // Get the PS_VERSION on run time
+ unsigned long si_ver = ps7GetSiliconVersion ();
+ int ret = -1;
+ if (si_ver == PCW_SILICON_VERSION_1) {
+ ret = ps7_config (ps7_post_config_1_0);
+ if (ret != PS7_INIT_SUCCESS) return ret;
+ } else if (si_ver == PCW_SILICON_VERSION_2) {
+ ret = ps7_config (ps7_post_config_2_0);
+ if (ret != PS7_INIT_SUCCESS) return ret;
+ } else {
+ ret = ps7_config (ps7_post_config_3_0);
+ if (ret != PS7_INIT_SUCCESS) return ret;
+ }
+ return PS7_INIT_SUCCESS;
+}
+
+int
+ps7_debug()
+{
+ // Get the PS_VERSION on run time
+ unsigned long si_ver = ps7GetSiliconVersion ();
+ int ret = -1;
+ if (si_ver == PCW_SILICON_VERSION_1) {
+ ret = ps7_config (ps7_debug_1_0);
+ if (ret != PS7_INIT_SUCCESS) return ret;
+ } else if (si_ver == PCW_SILICON_VERSION_2) {
+ ret = ps7_config (ps7_debug_2_0);
+ if (ret != PS7_INIT_SUCCESS) return ret;
+ } else {
+ ret = ps7_config (ps7_debug_3_0);
+ if (ret != PS7_INIT_SUCCESS) return ret;
+ }
+ return PS7_INIT_SUCCESS;
+}
+
+int
+ps7_init()
+{
+ // Get the PS_VERSION on run time
+ unsigned long si_ver = ps7GetSiliconVersion ();
+ int ret;
+ //int pcw_ver = 0;
+
+ if (si_ver == PCW_SILICON_VERSION_1) {
+ ps7_mio_init_data = ps7_mio_init_data_1_0;
+ ps7_pll_init_data = ps7_pll_init_data_1_0;
+ ps7_clock_init_data = ps7_clock_init_data_1_0;
+ ps7_ddr_init_data = ps7_ddr_init_data_1_0;
+ ps7_peripherals_init_data = ps7_peripherals_init_data_1_0;
+ //pcw_ver = 1;
+
+ } else if (si_ver == PCW_SILICON_VERSION_2) {
+ ps7_mio_init_data = ps7_mio_init_data_2_0;
+ ps7_pll_init_data = ps7_pll_init_data_2_0;
+ ps7_clock_init_data = ps7_clock_init_data_2_0;
+ ps7_ddr_init_data = ps7_ddr_init_data_2_0;
+ ps7_peripherals_init_data = ps7_peripherals_init_data_2_0;
+ //pcw_ver = 2;
+
+ } else {
+ ps7_mio_init_data = ps7_mio_init_data_3_0;
+ ps7_pll_init_data = ps7_pll_init_data_3_0;
+ ps7_clock_init_data = ps7_clock_init_data_3_0;
+ ps7_ddr_init_data = ps7_ddr_init_data_3_0;
+ ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
+ //pcw_ver = 3;
+ }
+
+ // MIO init
+ ret = ps7_config (ps7_mio_init_data);
+ if (ret != PS7_INIT_SUCCESS) return ret;
+
+ // PLL init
+ ret = ps7_config (ps7_pll_init_data);
+ if (ret != PS7_INIT_SUCCESS) return ret;
+
+ // Clock init
+ ret = ps7_config (ps7_clock_init_data);
+ if (ret != PS7_INIT_SUCCESS) return ret;
+
+ // DDR init
+ ret = ps7_config (ps7_ddr_init_data);
+ if (ret != PS7_INIT_SUCCESS) return ret;
+
+
+
+ // Peripherals init
+ ret = ps7_config (ps7_peripherals_init_data);
+ if (ret != PS7_INIT_SUCCESS) return ret;
+ //xil_printf ("\n PCW Silicon Version : %d.0", pcw_ver);
+ return PS7_INIT_SUCCESS;
+}
+
+
+
+
+/* For delay calculation using global timer */
+
+/* start timer */
+ void perf_start_clock(void)
+{
+ *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) | // Timer Enable
+ (1 << 3) | // Auto-increment
+ (0 << 8) // Pre-scale
+ );
+}
+
+/* stop timer and reset timer count regs */
+ void perf_reset_clock(void)
+{
+ perf_disable_clock();
+ *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_L32 = 0;
+ *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_U32 = 0;
+}
+
+/* Compute mask for given delay in miliseconds*/
+int get_number_of_cycles_for_delay(unsigned int delay)
+{
+ // GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x)
+ return (APU_FREQ*delay/(2*1000));
+
+}
+
+/* stop timer */
+ void perf_disable_clock(void)
+{
+ *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = 0;
+}
+
+void perf_reset_and_start_timer()
+{
+ perf_reset_clock();
+ perf_start_clock();
+}
--- /dev/null
+
+/******************************************************************************
+*
+* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
+*
+* SPDX-License-Identifier: GPL-2.0+
+*
+*
+*******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file ps7_init.h
+*
+* This file can be included in FSBL code
+* to get prototype of ps7_init() function
+* and error codes
+*
+*****************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+//typedef unsigned int u32;
+
+
+/** do we need to make this name more unique ? **/
+//extern u32 ps7_init_data[];
+extern unsigned long * ps7_ddr_init_data;
+extern unsigned long * ps7_mio_init_data;
+extern unsigned long * ps7_pll_init_data;
+extern unsigned long * ps7_clock_init_data;
+extern unsigned long * ps7_peripherals_init_data;
+
+
+
+#define OPCODE_EXIT 0U
+#define OPCODE_CLEAR 1U
+#define OPCODE_WRITE 2U
+#define OPCODE_MASKWRITE 3U
+#define OPCODE_MASKPOLL 4U
+#define OPCODE_MASKDELAY 5U
+#define NEW_PS7_ERR_CODE 1
+
+/* Encode number of arguments in last nibble */
+#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 )
+#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr
+#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val
+#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
+#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask
+#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
+
+/* Returns codes of PS7_Init */
+#define PS7_INIT_SUCCESS (0) // 0 is success in good old C
+#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now
+#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out
+#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init
+#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit
+#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init
+
+
+/* Silicon Versions */
+#define PCW_SILICON_VERSION_1 0
+#define PCW_SILICON_VERSION_2 1
+#define PCW_SILICON_VERSION_3 2
+
+/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
+#define PS7_POST_CONFIG
+
+/* Freq of all peripherals */
+
+#define APU_FREQ 666666687
+#define DDR_FREQ 533333374
+#define DCI_FREQ 10158731
+#define QSPI_FREQ 200000000
+#define SMC_FREQ 10000000
+#define ENET0_FREQ 125000000
+#define ENET1_FREQ 10000000
+#define USB0_FREQ 60000000
+#define USB1_FREQ 60000000
+#define SDIO_FREQ 50000000
+#define UART_FREQ 50000000
+#define SPI_FREQ 10000000
+#define I2C_FREQ 111111115
+#define WDT_FREQ 111111115
+#define TTC_FREQ 50000000
+#define CAN_FREQ 10000000
+#define PCAP_FREQ 200000000
+#define TPIU_FREQ 200000000
+#define FPGA0_FREQ 100000000
+#define FPGA1_FREQ 100000000
+#define FPGA2_FREQ 33333336
+#define FPGA3_FREQ 50000000
+
+
+/* For delay calculation using global registers*/
+#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
+#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204
+#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208
+#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218
+
+int ps7_config( unsigned long*);
+int ps7_init();
+int ps7_post_config();
+int ps7_debug();
+char* getPS7MessageInfo(unsigned key);
+
+void perf_start_clock(void);
+void perf_disable_clock(void);
+void perf_reset_clock(void);
+void perf_reset_and_start_timer();
+int get_number_of_cycles_for_delay(unsigned int delay);
+#ifdef __cplusplus
+}
+#endif
--- /dev/null
+/******************************************************************************
+* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
+*
+* SPDX-License-Identifier: GPL-2.0+
+*
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file ps7_init_gpl.c
+*
+* This file is automatically generated
+*
+*****************************************************************************/
+
+#include "ps7_init_gpl.h"
+
+unsigned long ps7_pll_init_data_3_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: PLL SLCR REGISTERS
+ // .. .. START: ARM PLL INIT
+ // .. .. PLL_RES = 0x2
+ // .. .. ==> 0XF8000110[7:4] = 0x00000002U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
+ // .. .. PLL_CP = 0x2
+ // .. .. ==> 0XF8000110[11:8] = 0x00000002U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
+ // .. .. LOCK_CNT = 0xfa
+ // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
+ // .. .. .. START: UPDATE FB_DIV
+ // .. .. .. PLL_FDIV = 0x28
+ // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
+ // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
+ // .. .. .. FINISH: UPDATE FB_DIV
+ // .. .. .. START: BY PASS PLL
+ // .. .. .. PLL_BYPASS_FORCE = 1
+ // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
+ // .. .. .. FINISH: BY PASS PLL
+ // .. .. .. START: ASSERT RESET
+ // .. .. .. PLL_RESET = 1
+ // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
+ // .. .. .. FINISH: ASSERT RESET
+ // .. .. .. START: DEASSERT RESET
+ // .. .. .. PLL_RESET = 0
+ // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
+ // .. .. .. FINISH: DEASSERT RESET
+ // .. .. .. START: CHECK PLL STATUS
+ // .. .. .. ARM_PLL_LOCK = 1
+ // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ..
+ EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+ // .. .. .. FINISH: CHECK PLL STATUS
+ // .. .. .. START: REMOVE PLL BY PASS
+ // .. .. .. PLL_BYPASS_FORCE = 0
+ // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
+ // .. .. .. FINISH: REMOVE PLL BY PASS
+ // .. .. .. SRCSEL = 0x0
+ // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. .. .. DIVISOR = 0x2
+ // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
+ // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U
+ // .. .. .. CPU_6OR4XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
+ // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U
+ // .. .. .. CPU_3OR2XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
+ // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U
+ // .. .. .. CPU_2XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
+ // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U
+ // .. .. .. CPU_1XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
+ // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U
+ // .. .. .. CPU_PERI_CLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
+ // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
+ // .. .. FINISH: ARM PLL INIT
+ // .. .. START: DDR PLL INIT
+ // .. .. PLL_RES = 0x2
+ // .. .. ==> 0XF8000114[7:4] = 0x00000002U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
+ // .. .. PLL_CP = 0x2
+ // .. .. ==> 0XF8000114[11:8] = 0x00000002U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
+ // .. .. LOCK_CNT = 0x12c
+ // .. .. ==> 0XF8000114[21:12] = 0x0000012CU
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
+ // .. .. .. START: UPDATE FB_DIV
+ // .. .. .. PLL_FDIV = 0x20
+ // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
+ // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
+ // .. .. .. FINISH: UPDATE FB_DIV
+ // .. .. .. START: BY PASS PLL
+ // .. .. .. PLL_BYPASS_FORCE = 1
+ // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
+ // .. .. .. FINISH: BY PASS PLL
+ // .. .. .. START: ASSERT RESET
+ // .. .. .. PLL_RESET = 1
+ // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
+ // .. .. .. FINISH: ASSERT RESET
+ // .. .. .. START: DEASSERT RESET
+ // .. .. .. PLL_RESET = 0
+ // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
+ // .. .. .. FINISH: DEASSERT RESET
+ // .. .. .. START: CHECK PLL STATUS
+ // .. .. .. DDR_PLL_LOCK = 1
+ // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. .. ..
+ EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+ // .. .. .. FINISH: CHECK PLL STATUS
+ // .. .. .. START: REMOVE PLL BY PASS
+ // .. .. .. PLL_BYPASS_FORCE = 0
+ // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
+ // .. .. .. FINISH: REMOVE PLL BY PASS
+ // .. .. .. DDR_3XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. .. DDR_2XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. .. .. DDR_3XCLK_DIVISOR = 0x2
+ // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
+ // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U
+ // .. .. .. DDR_2XCLK_DIVISOR = 0x3
+ // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
+ // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
+ // .. .. FINISH: DDR PLL INIT
+ // .. .. START: IO PLL INIT
+ // .. .. PLL_RES = 0xc
+ // .. .. ==> 0XF8000118[7:4] = 0x0000000CU
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U
+ // .. .. PLL_CP = 0x2
+ // .. .. ==> 0XF8000118[11:8] = 0x00000002U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
+ // .. .. LOCK_CNT = 0x145
+ // .. .. ==> 0XF8000118[21:12] = 0x00000145U
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U),
+ // .. .. .. START: UPDATE FB_DIV
+ // .. .. .. PLL_FDIV = 0x1e
+ // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU
+ // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U),
+ // .. .. .. FINISH: UPDATE FB_DIV
+ // .. .. .. START: BY PASS PLL
+ // .. .. .. PLL_BYPASS_FORCE = 1
+ // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
+ // .. .. .. FINISH: BY PASS PLL
+ // .. .. .. START: ASSERT RESET
+ // .. .. .. PLL_RESET = 1
+ // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
+ // .. .. .. FINISH: ASSERT RESET
+ // .. .. .. START: DEASSERT RESET
+ // .. .. .. PLL_RESET = 0
+ // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
+ // .. .. .. FINISH: DEASSERT RESET
+ // .. .. .. START: CHECK PLL STATUS
+ // .. .. .. IO_PLL_LOCK = 1
+ // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. .. ..
+ EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+ // .. .. .. FINISH: CHECK PLL STATUS
+ // .. .. .. START: REMOVE PLL BY PASS
+ // .. .. .. PLL_BYPASS_FORCE = 0
+ // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
+ // .. .. .. FINISH: REMOVE PLL BY PASS
+ // .. .. FINISH: IO PLL INIT
+ // .. FINISH: PLL SLCR REGISTERS
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_clock_init_data_3_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: CLOCK CONTROL SLCR REGISTERS
+ // .. CLKACT = 0x1
+ // .. ==> 0XF8000128[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. DIVISOR0 = 0x23
+ // .. ==> 0XF8000128[13:8] = 0x00000023U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00002300U
+ // .. DIVISOR1 = 0x3
+ // .. ==> 0XF8000128[25:20] = 0x00000003U
+ // .. ==> MASK : 0x03F00000U VAL : 0x00300000U
+ // ..
+ EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U),
+ // .. CLKACT = 0x1
+ // .. ==> 0XF8000138[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000138[4:4] = 0x00000000U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
+ // .. CLKACT = 0x1
+ // .. ==> 0XF8000140[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000140[6:4] = 0x00000000U
+ // .. ==> MASK : 0x00000070U VAL : 0x00000000U
+ // .. DIVISOR = 0x8
+ // .. ==> 0XF8000140[13:8] = 0x00000008U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00000800U
+ // .. DIVISOR1 = 0x5
+ // .. ==> 0XF8000140[25:20] = 0x00000005U
+ // .. ==> MASK : 0x03F00000U VAL : 0x00500000U
+ // ..
+ EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00500801U),
+ // .. CLKACT = 0x1
+ // .. ==> 0XF800014C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF800014C[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR = 0x5
+ // .. ==> 0XF800014C[13:8] = 0x00000005U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00000500U
+ // ..
+ EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
+ // .. CLKACT0 = 0x1
+ // .. ==> 0XF8000150[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. CLKACT1 = 0x0
+ // .. ==> 0XF8000150[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000150[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR = 0x14
+ // .. ==> 0XF8000150[13:8] = 0x00000014U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
+ // ..
+ EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U),
+ // .. CLKACT0 = 0x0
+ // .. ==> 0XF8000154[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. CLKACT1 = 0x1
+ // .. ==> 0XF8000154[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000154[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR = 0x14
+ // .. ==> 0XF8000154[13:8] = 0x00000014U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
+ // ..
+ EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U),
+ // .. CLKACT0 = 0x1
+ // .. ==> 0XF800015C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. CLKACT1 = 0x0
+ // .. ==> 0XF800015C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF800015C[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR0 = 0xe
+ // .. ==> 0XF800015C[13:8] = 0x0000000EU
+ // .. ==> MASK : 0x00003F00U VAL : 0x00000E00U
+ // .. DIVISOR1 = 0x3
+ // .. ==> 0XF800015C[25:20] = 0x00000003U
+ // .. ==> MASK : 0x03F00000U VAL : 0x00300000U
+ // ..
+ EMIT_MASKWRITE(0XF800015C, 0x03F03F33U ,0x00300E01U),
+ // .. CAN0_MUX = 0x0
+ // .. ==> 0XF8000160[5:0] = 0x00000000U
+ // .. ==> MASK : 0x0000003FU VAL : 0x00000000U
+ // .. CAN0_REF_SEL = 0x0
+ // .. ==> 0XF8000160[6:6] = 0x00000000U
+ // .. ==> MASK : 0x00000040U VAL : 0x00000000U
+ // .. CAN1_MUX = 0x0
+ // .. ==> 0XF8000160[21:16] = 0x00000000U
+ // .. ==> MASK : 0x003F0000U VAL : 0x00000000U
+ // .. CAN1_REF_SEL = 0x0
+ // .. ==> 0XF8000160[22:22] = 0x00000000U
+ // .. ==> MASK : 0x00400000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000160, 0x007F007FU ,0x00000000U),
+ // .. CLKACT = 0x1
+ // .. ==> 0XF8000168[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000168[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR = 0x5
+ // .. ==> 0XF8000168[13:8] = 0x00000005U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00000500U
+ // ..
+ EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000170[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR0 = 0x14
+ // .. ==> 0XF8000170[13:8] = 0x00000014U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
+ // .. DIVISOR1 = 0x1
+ // .. ==> 0XF8000170[25:20] = 0x00000001U
+ // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
+ // ..
+ EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00101400U),
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000180[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR0 = 0x14
+ // .. ==> 0XF8000180[13:8] = 0x00000014U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
+ // .. DIVISOR1 = 0x1
+ // .. ==> 0XF8000180[25:20] = 0x00000001U
+ // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
+ // ..
+ EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00101400U),
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000190[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR0 = 0x14
+ // .. ==> 0XF8000190[13:8] = 0x00000014U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
+ // .. DIVISOR1 = 0x1
+ // .. ==> 0XF8000190[25:20] = 0x00000001U
+ // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
+ // ..
+ EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101400U),
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF80001A0[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR0 = 0x14
+ // .. ==> 0XF80001A0[13:8] = 0x00000014U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
+ // .. DIVISOR1 = 0x1
+ // .. ==> 0XF80001A0[25:20] = 0x00000001U
+ // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
+ // ..
+ EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U),
+ // .. CLK_621_TRUE = 0x1
+ // .. ==> 0XF80001C4[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // ..
+ EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
+ // .. DMA_CPU_2XCLKACT = 0x1
+ // .. ==> 0XF800012C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. USB0_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. USB1_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[3:3] = 0x00000001U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000008U
+ // .. GEM0_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[6:6] = 0x00000001U
+ // .. ==> MASK : 0x00000040U VAL : 0x00000040U
+ // .. GEM1_CPU_1XCLKACT = 0x0
+ // .. ==> 0XF800012C[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. SDI0_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[10:10] = 0x00000001U
+ // .. ==> MASK : 0x00000400U VAL : 0x00000400U
+ // .. SDI1_CPU_1XCLKACT = 0x0
+ // .. ==> 0XF800012C[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. SPI0_CPU_1XCLKACT = 0x0
+ // .. ==> 0XF800012C[14:14] = 0x00000000U
+ // .. ==> MASK : 0x00004000U VAL : 0x00000000U
+ // .. SPI1_CPU_1XCLKACT = 0x0
+ // .. ==> 0XF800012C[15:15] = 0x00000000U
+ // .. ==> MASK : 0x00008000U VAL : 0x00000000U
+ // .. CAN0_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[16:16] = 0x00000001U
+ // .. ==> MASK : 0x00010000U VAL : 0x00010000U
+ // .. CAN1_CPU_1XCLKACT = 0x0
+ // .. ==> 0XF800012C[17:17] = 0x00000000U
+ // .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. I2C0_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[18:18] = 0x00000001U
+ // .. ==> MASK : 0x00040000U VAL : 0x00040000U
+ // .. I2C1_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[19:19] = 0x00000001U
+ // .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // .. UART0_CPU_1XCLKACT = 0x0
+ // .. ==> 0XF800012C[20:20] = 0x00000000U
+ // .. ==> MASK : 0x00100000U VAL : 0x00000000U
+ // .. UART1_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[21:21] = 0x00000001U
+ // .. ==> MASK : 0x00200000U VAL : 0x00200000U
+ // .. GPIO_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[22:22] = 0x00000001U
+ // .. ==> MASK : 0x00400000U VAL : 0x00400000U
+ // .. LQSPI_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[23:23] = 0x00000001U
+ // .. ==> MASK : 0x00800000U VAL : 0x00800000U
+ // .. SMC_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[24:24] = 0x00000001U
+ // .. ==> MASK : 0x01000000U VAL : 0x01000000U
+ // ..
+ EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01ED044DU),
+ // .. FINISH: CLOCK CONTROL SLCR REGISTERS
+ // .. START: THIS SHOULD BE BLANK
+ // .. FINISH: THIS SHOULD BE BLANK
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_ddr_init_data_3_0[] = {
+ // START: top
+ // .. START: DDR INITIALIZATION
+ // .. .. START: LOCK DDR
+ // .. .. reg_ddrc_soft_rstb = 0
+ // .. .. ==> 0XF8006000[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_powerdown_en = 0x0
+ // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_ddrc_data_bus_width = 0x0
+ // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U
+ // .. .. reg_ddrc_burst8_refresh = 0x0
+ // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U
+ // .. .. reg_ddrc_rdwr_idle_gap = 0x1
+ // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+ // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U
+ // .. .. reg_ddrc_dis_rd_bypass = 0x0
+ // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+ // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_act_bypass = 0x0
+ // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_auto_refresh = 0x0
+ // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
+ // .. .. FINISH: LOCK DDR
+ // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81
+ // .. .. ==> 0XF8006004[11:0] = 0x00000081U
+ // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U
+ // .. .. reserved_reg_ddrc_active_ranks = 0x1
+ // .. .. ==> 0XF8006004[13:12] = 0x00000001U
+ // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U
+ // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
+ // .. .. ==> 0XF8006004[18:14] = 0x00000000U
+ // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU ,0x00001081U),
+ // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
+ // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU
+ // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
+ // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
+ // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U
+ // .. .. reg_ddrc_hpr_xact_run_length = 0xf
+ // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
+ // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
+ // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
+ // .. .. ==> 0XF800600C[10:0] = 0x00000001U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U
+ // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
+ // .. .. ==> 0XF800600C[21:11] = 0x00000002U
+ // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U
+ // .. .. reg_ddrc_lpr_xact_run_length = 0x8
+ // .. .. ==> 0XF800600C[25:22] = 0x00000008U
+ // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
+ // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
+ // .. .. ==> 0XF8006010[10:0] = 0x00000001U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U
+ // .. .. reg_ddrc_w_xact_run_length = 0x8
+ // .. .. ==> 0XF8006010[14:11] = 0x00000008U
+ // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U
+ // .. .. reg_ddrc_w_max_starve_x32 = 0x2
+ // .. .. ==> 0XF8006010[25:15] = 0x00000002U
+ // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
+ // .. .. reg_ddrc_t_rc = 0x1b
+ // .. .. ==> 0XF8006014[5:0] = 0x0000001BU
+ // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001BU
+ // .. .. reg_ddrc_t_rfc_min = 0x56
+ // .. .. ==> 0XF8006014[13:6] = 0x00000056U
+ // .. .. ==> MASK : 0x00003FC0U VAL : 0x00001580U
+ // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
+ // .. .. ==> 0XF8006014[20:14] = 0x00000010U
+ // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004159BU),
+ // .. .. reg_ddrc_wr2pre = 0x12
+ // .. .. ==> 0XF8006018[4:0] = 0x00000012U
+ // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U
+ // .. .. reg_ddrc_powerdown_to_x32 = 0x6
+ // .. .. ==> 0XF8006018[9:5] = 0x00000006U
+ // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U
+ // .. .. reg_ddrc_t_faw = 0x10
+ // .. .. ==> 0XF8006018[15:10] = 0x00000010U
+ // .. .. ==> MASK : 0x0000FC00U VAL : 0x00004000U
+ // .. .. reg_ddrc_t_ras_max = 0x24
+ // .. .. ==> 0XF8006018[21:16] = 0x00000024U
+ // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U
+ // .. .. reg_ddrc_t_ras_min = 0x14
+ // .. .. ==> 0XF8006018[26:22] = 0x00000014U
+ // .. .. ==> MASK : 0x07C00000U VAL : 0x05000000U
+ // .. .. reg_ddrc_t_cke = 0x4
+ // .. .. ==> 0XF8006018[31:28] = 0x00000004U
+ // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x452440D2U),
+ // .. .. reg_ddrc_write_latency = 0x5
+ // .. .. ==> 0XF800601C[4:0] = 0x00000005U
+ // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U
+ // .. .. reg_ddrc_rd2wr = 0x7
+ // .. .. ==> 0XF800601C[9:5] = 0x00000007U
+ // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U
+ // .. .. reg_ddrc_wr2rd = 0xe
+ // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
+ // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U
+ // .. .. reg_ddrc_t_xp = 0x4
+ // .. .. ==> 0XF800601C[19:15] = 0x00000004U
+ // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U
+ // .. .. reg_ddrc_pad_pd = 0x0
+ // .. .. ==> 0XF800601C[22:20] = 0x00000000U
+ // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U
+ // .. .. reg_ddrc_rd2pre = 0x4
+ // .. .. ==> 0XF800601C[27:23] = 0x00000004U
+ // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U
+ // .. .. reg_ddrc_t_rcd = 0x7
+ // .. .. ==> 0XF800601C[31:28] = 0x00000007U
+ // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
+ // .. .. reg_ddrc_t_ccd = 0x4
+ // .. .. ==> 0XF8006020[4:2] = 0x00000004U
+ // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U
+ // .. .. reg_ddrc_t_rrd = 0x4
+ // .. .. ==> 0XF8006020[7:5] = 0x00000004U
+ // .. .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. .. reg_ddrc_refresh_margin = 0x2
+ // .. .. ==> 0XF8006020[11:8] = 0x00000002U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
+ // .. .. reg_ddrc_t_rp = 0x7
+ // .. .. ==> 0XF8006020[15:12] = 0x00000007U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U
+ // .. .. reg_ddrc_refresh_to_x32 = 0x8
+ // .. .. ==> 0XF8006020[20:16] = 0x00000008U
+ // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U
+ // .. .. reg_ddrc_mobile = 0x0
+ // .. .. ==> 0XF8006020[22:22] = 0x00000000U
+ // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U
+ // .. .. reg_ddrc_en_dfi_dram_clk_disable = 0x0
+ // .. .. ==> 0XF8006020[23:23] = 0x00000000U
+ // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U
+ // .. .. reg_ddrc_read_latency = 0x7
+ // .. .. ==> 0XF8006020[28:24] = 0x00000007U
+ // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U
+ // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
+ // .. .. ==> 0XF8006020[29:29] = 0x00000001U
+ // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U
+ // .. .. reg_ddrc_dis_pad_pd = 0x0
+ // .. .. ==> 0XF8006020[30:30] = 0x00000000U
+ // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU ,0x27087290U),
+ // .. .. reg_ddrc_en_2t_timing_mode = 0x0
+ // .. .. ==> 0XF8006024[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_prefer_write = 0x0
+ // .. .. ==> 0XF8006024[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr_wr = 0x0
+ // .. .. ==> 0XF8006024[6:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr_addr = 0x0
+ // .. .. ==> 0XF8006024[8:7] = 0x00000000U
+ // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr_data = 0x0
+ // .. .. ==> 0XF8006024[24:9] = 0x00000000U
+ // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U
+ // .. .. ddrc_reg_mr_wr_busy = 0x0
+ // .. .. ==> 0XF8006024[25:25] = 0x00000000U
+ // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr_type = 0x0
+ // .. .. ==> 0XF8006024[26:26] = 0x00000000U
+ // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr_rdata_valid = 0x0
+ // .. .. ==> 0XF8006024[27:27] = 0x00000000U
+ // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U ,0x00000000U),
+ // .. .. reg_ddrc_final_wait_x32 = 0x7
+ // .. .. ==> 0XF8006028[6:0] = 0x00000007U
+ // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U
+ // .. .. reg_ddrc_pre_ocd_x32 = 0x0
+ // .. .. ==> 0XF8006028[10:7] = 0x00000000U
+ // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U
+ // .. .. reg_ddrc_t_mrd = 0x4
+ // .. .. ==> 0XF8006028[13:11] = 0x00000004U
+ // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
+ // .. .. reg_ddrc_emr2 = 0x8
+ // .. .. ==> 0XF800602C[15:0] = 0x00000008U
+ // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U
+ // .. .. reg_ddrc_emr3 = 0x0
+ // .. .. ==> 0XF800602C[31:16] = 0x00000000U
+ // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
+ // .. .. reg_ddrc_mr = 0x930
+ // .. .. ==> 0XF8006030[15:0] = 0x00000930U
+ // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U
+ // .. .. reg_ddrc_emr = 0x4
+ // .. .. ==> 0XF8006030[31:16] = 0x00000004U
+ // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
+ // .. .. reg_ddrc_burst_rdwr = 0x4
+ // .. .. ==> 0XF8006034[3:0] = 0x00000004U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U
+ // .. .. reg_ddrc_pre_cke_x1024 = 0x105
+ // .. .. ==> 0XF8006034[13:4] = 0x00000105U
+ // .. .. ==> MASK : 0x00003FF0U VAL : 0x00001050U
+ // .. .. reg_ddrc_post_cke_x1024 = 0x1
+ // .. .. ==> 0XF8006034[25:16] = 0x00000001U
+ // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U
+ // .. .. reg_ddrc_burstchop = 0x0
+ // .. .. ==> 0XF8006034[28:28] = 0x00000000U
+ // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U),
+ // .. .. reg_ddrc_force_low_pri_n = 0x0
+ // .. .. ==> 0XF8006038[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_dq = 0x0
+ // .. .. ==> 0XF8006038[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006038, 0x00000003U ,0x00000000U),
+ // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
+ // .. .. ==> 0XF800603C[3:0] = 0x00000007U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U
+ // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
+ // .. .. ==> 0XF800603C[7:4] = 0x00000007U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U
+ // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
+ // .. .. ==> 0XF800603C[11:8] = 0x00000007U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U
+ // .. .. reg_ddrc_addrmap_col_b5 = 0x0
+ // .. .. ==> 0XF800603C[15:12] = 0x00000000U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b6 = 0x0
+ // .. .. ==> 0XF800603C[19:16] = 0x00000000U
+ // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
+ // .. .. reg_ddrc_addrmap_col_b2 = 0x0
+ // .. .. ==> 0XF8006040[3:0] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b3 = 0x0
+ // .. .. ==> 0XF8006040[7:4] = 0x00000000U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b4 = 0x0
+ // .. .. ==> 0XF8006040[11:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b7 = 0x0
+ // .. .. ==> 0XF8006040[15:12] = 0x00000000U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b8 = 0x0
+ // .. .. ==> 0XF8006040[19:16] = 0x00000000U
+ // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b9 = 0xf
+ // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
+ // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U
+ // .. .. reg_ddrc_addrmap_col_b10 = 0xf
+ // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
+ // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U
+ // .. .. reg_ddrc_addrmap_col_b11 = 0xf
+ // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
+ // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
+ // .. .. reg_ddrc_addrmap_row_b0 = 0x6
+ // .. .. ==> 0XF8006044[3:0] = 0x00000006U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U
+ // .. .. reg_ddrc_addrmap_row_b1 = 0x6
+ // .. .. ==> 0XF8006044[7:4] = 0x00000006U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U
+ // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
+ // .. .. ==> 0XF8006044[11:8] = 0x00000006U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U
+ // .. .. reg_ddrc_addrmap_row_b12 = 0x6
+ // .. .. ==> 0XF8006044[15:12] = 0x00000006U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U
+ // .. .. reg_ddrc_addrmap_row_b13 = 0x6
+ // .. .. ==> 0XF8006044[19:16] = 0x00000006U
+ // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U
+ // .. .. reg_ddrc_addrmap_row_b14 = 0x6
+ // .. .. ==> 0XF8006044[23:20] = 0x00000006U
+ // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U
+ // .. .. reg_ddrc_addrmap_row_b15 = 0xf
+ // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
+ // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U),
+ // .. .. reg_phy_rd_local_odt = 0x0
+ // .. .. ==> 0XF8006048[13:12] = 0x00000000U
+ // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U
+ // .. .. reg_phy_wr_local_odt = 0x3
+ // .. .. ==> 0XF8006048[15:14] = 0x00000003U
+ // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U
+ // .. .. reg_phy_idle_local_odt = 0x3
+ // .. .. ==> 0XF8006048[17:16] = 0x00000003U
+ // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006048, 0x0003F000U ,0x0003C000U),
+ // .. .. reg_phy_rd_cmd_to_data = 0x0
+ // .. .. ==> 0XF8006050[3:0] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
+ // .. .. reg_phy_wr_cmd_to_data = 0x0
+ // .. .. ==> 0XF8006050[7:4] = 0x00000000U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. .. reg_phy_rdc_we_to_re_delay = 0x8
+ // .. .. ==> 0XF8006050[11:8] = 0x00000008U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U
+ // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
+ // .. .. ==> 0XF8006050[15:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
+ // .. .. reg_phy_use_fixed_re = 0x1
+ // .. .. ==> 0XF8006050[16:16] = 0x00000001U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U
+ // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
+ // .. .. ==> 0XF8006050[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
+ // .. .. ==> 0XF8006050[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_phy_clk_stall_level = 0x0
+ // .. .. ==> 0XF8006050[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
+ // .. .. ==> 0XF8006050[27:24] = 0x00000007U
+ // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U
+ // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
+ // .. .. ==> 0XF8006050[31:28] = 0x00000007U
+ // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
+ // .. .. reg_ddrc_dis_dll_calib = 0x0
+ // .. .. ==> 0XF8006058[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006058, 0x00010000U ,0x00000000U),
+ // .. .. reg_ddrc_rd_odt_delay = 0x3
+ // .. .. ==> 0XF800605C[3:0] = 0x00000003U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U
+ // .. .. reg_ddrc_wr_odt_delay = 0x0
+ // .. .. ==> 0XF800605C[7:4] = 0x00000000U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. .. reg_ddrc_rd_odt_hold = 0x0
+ // .. .. ==> 0XF800605C[11:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U
+ // .. .. reg_ddrc_wr_odt_hold = 0x5
+ // .. .. ==> 0XF800605C[15:12] = 0x00000005U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
+ // .. .. reg_ddrc_pageclose = 0x0
+ // .. .. ==> 0XF8006060[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_lpr_num_entries = 0x1f
+ // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
+ // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU
+ // .. .. reg_ddrc_auto_pre_en = 0x0
+ // .. .. ==> 0XF8006060[7:7] = 0x00000000U
+ // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. .. reg_ddrc_refresh_update_level = 0x0
+ // .. .. ==> 0XF8006060[8:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_wc = 0x0
+ // .. .. ==> 0XF8006060[9:9] = 0x00000000U
+ // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_collision_page_opt = 0x0
+ // .. .. ==> 0XF8006060[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_ddrc_selfref_en = 0x0
+ // .. .. ==> 0XF8006060[12:12] = 0x00000000U
+ // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
+ // .. .. reg_ddrc_go2critical_hysteresis = 0x0
+ // .. .. ==> 0XF8006064[12:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U
+ // .. .. reg_arb_go2critical_en = 0x1
+ // .. .. ==> 0XF8006064[17:17] = 0x00000001U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
+ // .. .. reg_ddrc_wrlvl_ww = 0x41
+ // .. .. ==> 0XF8006068[7:0] = 0x00000041U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U
+ // .. .. reg_ddrc_rdlvl_rr = 0x41
+ // .. .. ==> 0XF8006068[15:8] = 0x00000041U
+ // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U
+ // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
+ // .. .. ==> 0XF8006068[25:16] = 0x00000028U
+ // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
+ // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
+ // .. .. ==> 0XF800606C[7:0] = 0x00000010U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U
+ // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
+ // .. .. ==> 0XF800606C[15:8] = 0x00000016U
+ // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U
+ // .. ..
+ EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
+ // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1
+ // .. .. ==> 0XF8006078[3:0] = 0x00000001U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U
+ // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1
+ // .. .. ==> 0XF8006078[7:4] = 0x00000001U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U
+ // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1
+ // .. .. ==> 0XF8006078[11:8] = 0x00000001U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U
+ // .. .. reg_ddrc_t_cksre = 0x6
+ // .. .. ==> 0XF8006078[15:12] = 0x00000006U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U
+ // .. .. reg_ddrc_t_cksrx = 0x6
+ // .. .. ==> 0XF8006078[19:16] = 0x00000006U
+ // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U
+ // .. .. reg_ddrc_t_ckesr = 0x4
+ // .. .. ==> 0XF8006078[25:20] = 0x00000004U
+ // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U),
+ // .. .. reg_ddrc_t_ckpde = 0x2
+ // .. .. ==> 0XF800607C[3:0] = 0x00000002U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U
+ // .. .. reg_ddrc_t_ckpdx = 0x2
+ // .. .. ==> 0XF800607C[7:4] = 0x00000002U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
+ // .. .. reg_ddrc_t_ckdpde = 0x2
+ // .. .. ==> 0XF800607C[11:8] = 0x00000002U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
+ // .. .. reg_ddrc_t_ckdpdx = 0x2
+ // .. .. ==> 0XF800607C[15:12] = 0x00000002U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U
+ // .. .. reg_ddrc_t_ckcsx = 0x3
+ // .. .. ==> 0XF800607C[19:16] = 0x00000003U
+ // .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U),
+ // .. .. reg_ddrc_dis_auto_zq = 0x0
+ // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_ddr3 = 0x1
+ // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. .. reg_ddrc_t_mod = 0x200
+ // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
+ // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U
+ // .. .. reg_ddrc_t_zq_long_nop = 0x200
+ // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U
+ // .. .. reg_ddrc_t_zq_short_nop = 0x40
+ // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
+ // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
+ // .. .. t_zq_short_interval_x1024 = 0xcb73
+ // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U
+ // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U
+ // .. .. dram_rstn_x1024 = 0x69
+ // .. .. ==> 0XF80060A8[27:20] = 0x00000069U
+ // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
+ // .. .. deeppowerdown_en = 0x0
+ // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. deeppowerdown_to_x1024 = 0xff
+ // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
+ // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU
+ // .. ..
+ EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
+ // .. .. dfi_wrlvl_max_x1024 = 0xfff
+ // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
+ // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU
+ // .. .. dfi_rdlvl_max_x1024 = 0xfff
+ // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
+ // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U
+ // .. .. ddrc_reg_twrlvl_max_error = 0x0
+ // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
+ // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U
+ // .. .. ddrc_reg_trdlvl_max_error = 0x0
+ // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
+ // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dfi_wr_level_en = 0x1
+ // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
+ // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U
+ // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
+ // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
+ // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U
+ // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
+ // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
+ // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
+ // .. .. reg_ddrc_skip_ocd = 0x1
+ // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
+ // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060B4, 0x00000200U ,0x00000200U),
+ // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
+ // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
+ // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U
+ // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
+ // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
+ // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U
+ // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
+ // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
+ // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
+ // .. .. START: RESET ECC ERROR
+ // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1
+ // .. .. ==> 0XF80060C4[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. Clear_Correctable_DRAM_ECC_error = 1
+ // .. .. ==> 0XF80060C4[1:1] = 0x00000001U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U),
+ // .. .. FINISH: RESET ECC ERROR
+ // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
+ // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
+ // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
+ // .. .. CORR_ECC_LOG_VALID = 0x0
+ // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. ECC_CORRECTED_BIT_NUM = 0x0
+ // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
+ // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
+ // .. .. UNCORR_ECC_LOG_VALID = 0x0
+ // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
+ // .. .. STAT_NUM_CORR_ERR = 0x0
+ // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
+ // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U
+ // .. .. STAT_NUM_UNCORR_ERR = 0x0
+ // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
+ // .. .. reg_ddrc_ecc_mode = 0x0
+ // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_scrub = 0x1
+ // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
+ // .. .. reg_phy_dif_on = 0x0
+ // .. .. ==> 0XF8006114[3:0] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
+ // .. .. reg_phy_dif_off = 0x0
+ // .. .. ==> 0XF8006114[7:4] = 0x00000000U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
+ // .. .. reg_phy_data_slice_in_use = 0x1
+ // .. .. ==> 0XF8006118[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_phy_rdlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006118[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006118[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_wrlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006118[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_bist_shift_dq = 0x0
+ // .. .. ==> 0XF8006118[14:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
+ // .. .. reg_phy_bist_err_clr = 0x0
+ // .. .. ==> 0XF8006118[23:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
+ // .. .. reg_phy_dq_offset = 0x40
+ // .. .. ==> 0XF8006118[30:24] = 0x00000040U
+ // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU ,0x40000001U),
+ // .. .. reg_phy_data_slice_in_use = 0x1
+ // .. .. ==> 0XF800611C[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_phy_rdlvl_inc_mode = 0x0
+ // .. .. ==> 0XF800611C[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_inc_mode = 0x0
+ // .. .. ==> 0XF800611C[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_wrlvl_inc_mode = 0x0
+ // .. .. ==> 0XF800611C[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_bist_shift_dq = 0x0
+ // .. .. ==> 0XF800611C[14:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
+ // .. .. reg_phy_bist_err_clr = 0x0
+ // .. .. ==> 0XF800611C[23:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
+ // .. .. reg_phy_dq_offset = 0x40
+ // .. .. ==> 0XF800611C[30:24] = 0x00000040U
+ // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU ,0x40000001U),
+ // .. .. reg_phy_data_slice_in_use = 0x1
+ // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_phy_rdlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_wrlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_bist_shift_dq = 0x0
+ // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
+ // .. .. reg_phy_bist_err_clr = 0x0
+ // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
+ // .. .. reg_phy_dq_offset = 0x40
+ // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+ // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU ,0x40000001U),
+ // .. .. reg_phy_data_slice_in_use = 0x1
+ // .. .. ==> 0XF8006124[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_phy_rdlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006124[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006124[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_wrlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006124[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_bist_shift_dq = 0x0
+ // .. .. ==> 0XF8006124[14:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
+ // .. .. reg_phy_bist_err_clr = 0x0
+ // .. .. ==> 0XF8006124[23:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
+ // .. .. reg_phy_dq_offset = 0x40
+ // .. .. ==> 0XF8006124[30:24] = 0x00000040U
+ // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU ,0x40000001U),
+ // .. .. reg_phy_wrlvl_init_ratio = 0x1d
+ // .. .. ==> 0XF800612C[9:0] = 0x0000001DU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x0000001DU
+ // .. .. reg_phy_gatelvl_init_ratio = 0xf2
+ // .. .. ==> 0XF800612C[19:10] = 0x000000F2U
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x0003C800U
+ // .. ..
+ EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0003C81DU),
+ // .. .. reg_phy_wrlvl_init_ratio = 0x12
+ // .. .. ==> 0XF8006130[9:0] = 0x00000012U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000012U
+ // .. .. reg_phy_gatelvl_init_ratio = 0xd8
+ // .. .. ==> 0XF8006130[19:10] = 0x000000D8U
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x00036000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00036012U),
+ // .. .. reg_phy_wrlvl_init_ratio = 0xc
+ // .. .. ==> 0XF8006134[9:0] = 0x0000000CU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x0000000CU
+ // .. .. reg_phy_gatelvl_init_ratio = 0xde
+ // .. .. ==> 0XF8006134[19:10] = 0x000000DEU
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x00037800U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0003780CU),
+ // .. .. reg_phy_wrlvl_init_ratio = 0x21
+ // .. .. ==> 0XF8006138[9:0] = 0x00000021U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000021U
+ // .. .. reg_phy_gatelvl_init_ratio = 0xee
+ // .. .. ==> 0XF8006138[19:10] = 0x000000EEU
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x0003B800U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0003B821U),
+ // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+ // .. .. ==> 0XF8006140[9:0] = 0x00000035U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
+ // .. .. reg_phy_rd_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006140[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006140[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
+ // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+ // .. .. ==> 0XF8006144[9:0] = 0x00000035U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
+ // .. .. reg_phy_rd_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006144[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006144[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
+ // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+ // .. .. ==> 0XF8006148[9:0] = 0x00000035U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
+ // .. .. reg_phy_rd_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006148[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006148[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
+ // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+ // .. .. ==> 0XF800614C[9:0] = 0x00000035U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
+ // .. .. reg_phy_rd_dqs_slave_force = 0x0
+ // .. .. ==> 0XF800614C[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF800614C[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
+ // .. .. reg_phy_wr_dqs_slave_ratio = 0x9d
+ // .. .. ==> 0XF8006154[9:0] = 0x0000009DU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x0000009DU
+ // .. .. reg_phy_wr_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006154[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006154[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x0000009DU),
+ // .. .. reg_phy_wr_dqs_slave_ratio = 0x92
+ // .. .. ==> 0XF8006158[9:0] = 0x00000092U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000092U
+ // .. .. reg_phy_wr_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006158[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006158[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000092U),
+ // .. .. reg_phy_wr_dqs_slave_ratio = 0x8c
+ // .. .. ==> 0XF800615C[9:0] = 0x0000008CU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x0000008CU
+ // .. .. reg_phy_wr_dqs_slave_force = 0x0
+ // .. .. ==> 0XF800615C[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF800615C[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x0000008CU),
+ // .. .. reg_phy_wr_dqs_slave_ratio = 0xa1
+ // .. .. ==> 0XF8006160[9:0] = 0x000000A1U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000A1U
+ // .. .. reg_phy_wr_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006160[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006160[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x000000A1U),
+ // .. .. reg_phy_fifo_we_slave_ratio = 0x147
+ // .. .. ==> 0XF8006168[10:0] = 0x00000147U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000147U
+ // .. .. reg_phy_fifo_we_in_force = 0x0
+ // .. .. ==> 0XF8006168[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. reg_phy_fifo_we_in_delay = 0x0
+ // .. .. ==> 0XF8006168[20:12] = 0x00000000U
+ // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000147U),
+ // .. .. reg_phy_fifo_we_slave_ratio = 0x12d
+ // .. .. ==> 0XF800616C[10:0] = 0x0000012DU
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x0000012DU
+ // .. .. reg_phy_fifo_we_in_force = 0x0
+ // .. .. ==> 0XF800616C[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. reg_phy_fifo_we_in_delay = 0x0
+ // .. .. ==> 0XF800616C[20:12] = 0x00000000U
+ // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x0000012DU),
+ // .. .. reg_phy_fifo_we_slave_ratio = 0x133
+ // .. .. ==> 0XF8006170[10:0] = 0x00000133U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000133U
+ // .. .. reg_phy_fifo_we_in_force = 0x0
+ // .. .. ==> 0XF8006170[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. reg_phy_fifo_we_in_delay = 0x0
+ // .. .. ==> 0XF8006170[20:12] = 0x00000000U
+ // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000133U),
+ // .. .. reg_phy_fifo_we_slave_ratio = 0x143
+ // .. .. ==> 0XF8006174[10:0] = 0x00000143U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000143U
+ // .. .. reg_phy_fifo_we_in_force = 0x0
+ // .. .. ==> 0XF8006174[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. reg_phy_fifo_we_in_delay = 0x0
+ // .. .. ==> 0XF8006174[20:12] = 0x00000000U
+ // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000143U),
+ // .. .. reg_phy_wr_data_slave_ratio = 0xdd
+ // .. .. ==> 0XF800617C[9:0] = 0x000000DDU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000DDU
+ // .. .. reg_phy_wr_data_slave_force = 0x0
+ // .. .. ==> 0XF800617C[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_data_slave_delay = 0x0
+ // .. .. ==> 0XF800617C[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000DDU),
+ // .. .. reg_phy_wr_data_slave_ratio = 0xd2
+ // .. .. ==> 0XF8006180[9:0] = 0x000000D2U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000D2U
+ // .. .. reg_phy_wr_data_slave_force = 0x0
+ // .. .. ==> 0XF8006180[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_data_slave_delay = 0x0
+ // .. .. ==> 0XF8006180[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000D2U),
+ // .. .. reg_phy_wr_data_slave_ratio = 0xcc
+ // .. .. ==> 0XF8006184[9:0] = 0x000000CCU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000CCU
+ // .. .. reg_phy_wr_data_slave_force = 0x0
+ // .. .. ==> 0XF8006184[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_data_slave_delay = 0x0
+ // .. .. ==> 0XF8006184[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000CCU),
+ // .. .. reg_phy_wr_data_slave_ratio = 0xe1
+ // .. .. ==> 0XF8006188[9:0] = 0x000000E1U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000E1U
+ // .. .. reg_phy_wr_data_slave_force = 0x0
+ // .. .. ==> 0XF8006188[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_data_slave_delay = 0x0
+ // .. .. ==> 0XF8006188[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000E1U),
+ // .. .. reg_phy_bl2 = 0x0
+ // .. .. ==> 0XF8006190[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_at_spd_atpg = 0x0
+ // .. .. ==> 0XF8006190[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_bist_enable = 0x0
+ // .. .. ==> 0XF8006190[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_bist_force_err = 0x0
+ // .. .. ==> 0XF8006190[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reg_phy_bist_mode = 0x0
+ // .. .. ==> 0XF8006190[6:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U
+ // .. .. reg_phy_invert_clkout = 0x1
+ // .. .. ==> 0XF8006190[7:7] = 0x00000001U
+ // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. .. reg_phy_sel_logic = 0x0
+ // .. .. ==> 0XF8006190[9:9] = 0x00000000U
+ // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U
+ // .. .. reg_phy_ctrl_slave_ratio = 0x100
+ // .. .. ==> 0XF8006190[19:10] = 0x00000100U
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U
+ // .. .. reg_phy_ctrl_slave_force = 0x0
+ // .. .. ==> 0XF8006190[20:20] = 0x00000000U
+ // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U
+ // .. .. reg_phy_ctrl_slave_delay = 0x0
+ // .. .. ==> 0XF8006190[27:21] = 0x00000000U
+ // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U
+ // .. .. reg_phy_lpddr = 0x0
+ // .. .. ==> 0XF8006190[29:29] = 0x00000000U
+ // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U
+ // .. .. reg_phy_cmd_latency = 0x0
+ // .. .. ==> 0XF8006190[30:30] = 0x00000000U
+ // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU ,0x00040080U),
+ // .. .. reg_phy_wr_rl_delay = 0x2
+ // .. .. ==> 0XF8006194[4:0] = 0x00000002U
+ // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U
+ // .. .. reg_phy_rd_rl_delay = 0x4
+ // .. .. ==> 0XF8006194[9:5] = 0x00000004U
+ // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U
+ // .. .. reg_phy_dll_lock_diff = 0xf
+ // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
+ // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U
+ // .. .. reg_phy_use_wr_level = 0x1
+ // .. .. ==> 0XF8006194[14:14] = 0x00000001U
+ // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U
+ // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
+ // .. .. ==> 0XF8006194[15:15] = 0x00000001U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U
+ // .. .. reg_phy_use_rd_data_eye_level = 0x1
+ // .. .. ==> 0XF8006194[16:16] = 0x00000001U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U
+ // .. .. reg_phy_dis_calib_rst = 0x0
+ // .. .. ==> 0XF8006194[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_phy_ctrl_slave_delay = 0x0
+ // .. .. ==> 0XF8006194[19:18] = 0x00000000U
+ // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
+ // .. .. reg_arb_page_addr_mask = 0x0
+ // .. .. ==> 0XF8006204[31:0] = 0x00000000U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
+ // .. .. reg_arb_pri_wr_portn = 0x3ff
+ // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_wr_portn = 0x0
+ // .. .. ==> 0XF8006208[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+ // .. .. ==> 0XF8006208[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+ // .. .. ==> 0XF8006208[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006208, 0x000703FFU ,0x000003FFU),
+ // .. .. reg_arb_pri_wr_portn = 0x3ff
+ // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_wr_portn = 0x0
+ // .. .. ==> 0XF800620C[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+ // .. .. ==> 0XF800620C[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+ // .. .. ==> 0XF800620C[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800620C, 0x000703FFU ,0x000003FFU),
+ // .. .. reg_arb_pri_wr_portn = 0x3ff
+ // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_wr_portn = 0x0
+ // .. .. ==> 0XF8006210[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+ // .. .. ==> 0XF8006210[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+ // .. .. ==> 0XF8006210[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006210, 0x000703FFU ,0x000003FFU),
+ // .. .. reg_arb_pri_wr_portn = 0x3ff
+ // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_wr_portn = 0x0
+ // .. .. ==> 0XF8006214[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+ // .. .. ==> 0XF8006214[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+ // .. .. ==> 0XF8006214[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006214, 0x000703FFU ,0x000003FFU),
+ // .. .. reg_arb_pri_rd_portn = 0x3ff
+ // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_rd_portn = 0x0
+ // .. .. ==> 0XF8006218[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+ // .. .. ==> 0XF8006218[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+ // .. .. ==> 0XF8006218[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_set_hpr_rd_portn = 0x0
+ // .. .. ==> 0XF8006218[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
+ // .. .. reg_arb_pri_rd_portn = 0x3ff
+ // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_rd_portn = 0x0
+ // .. .. ==> 0XF800621C[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+ // .. .. ==> 0XF800621C[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+ // .. .. ==> 0XF800621C[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_set_hpr_rd_portn = 0x0
+ // .. .. ==> 0XF800621C[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
+ // .. .. reg_arb_pri_rd_portn = 0x3ff
+ // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_rd_portn = 0x0
+ // .. .. ==> 0XF8006220[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+ // .. .. ==> 0XF8006220[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+ // .. .. ==> 0XF8006220[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_set_hpr_rd_portn = 0x0
+ // .. .. ==> 0XF8006220[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
+ // .. .. reg_arb_pri_rd_portn = 0x3ff
+ // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_rd_portn = 0x0
+ // .. .. ==> 0XF8006224[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+ // .. .. ==> 0XF8006224[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+ // .. .. ==> 0XF8006224[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_set_hpr_rd_portn = 0x0
+ // .. .. ==> 0XF8006224[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
+ // .. .. reg_ddrc_lpddr2 = 0x0
+ // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_derate_enable = 0x0
+ // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr4_margin = 0x0
+ // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U ,0x00000000U),
+ // .. .. reg_ddrc_mr4_read_interval = 0x0
+ // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
+ // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
+ // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U
+ // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
+ // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
+ // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U
+ // .. .. reg_ddrc_t_mrw = 0x5
+ // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
+ // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8
+ // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U
+ // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
+ // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
+ // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U
+ // .. ..
+ EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
+ // .. .. START: POLL ON DCI STATUS
+ // .. .. DONE = 1
+ // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
+ // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U
+ // .. ..
+ EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+ // .. .. FINISH: POLL ON DCI STATUS
+ // .. .. START: UNLOCK DDR
+ // .. .. reg_ddrc_soft_rstb = 0x1
+ // .. .. ==> 0XF8006000[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_ddrc_powerdown_en = 0x0
+ // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_ddrc_data_bus_width = 0x0
+ // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U
+ // .. .. reg_ddrc_burst8_refresh = 0x0
+ // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U
+ // .. .. reg_ddrc_rdwr_idle_gap = 1
+ // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+ // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U
+ // .. .. reg_ddrc_dis_rd_bypass = 0x0
+ // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+ // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_act_bypass = 0x0
+ // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_auto_refresh = 0x0
+ // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
+ // .. .. FINISH: UNLOCK DDR
+ // .. .. START: CHECK DDR STATUS
+ // .. .. ddrc_reg_operating_mode = 1
+ // .. .. ==> 0XF8006054[2:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U
+ // .. ..
+ EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+ // .. .. FINISH: CHECK DDR STATUS
+ // .. FINISH: DDR INITIALIZATION
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_mio_init_data_3_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: OCM REMAPPING
+ // .. VREF_EN = 0x1
+ // .. ==> 0XF8000B00[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. VREF_SEL = 0x0
+ // .. ==> 0XF8000B00[6:4] = 0x00000000U
+ // .. ==> MASK : 0x00000070U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B00, 0x00000071U ,0x00000001U),
+ // .. FINISH: OCM REMAPPING
+ // .. START: DDRIOB SETTINGS
+ // .. reserved_INP_POWER = 0x0
+ // .. ==> 0XF8000B40[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x0
+ // .. ==> 0XF8000B40[2:1] = 0x00000000U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000000U
+ // .. DCI_UPDATE_B = 0x0
+ // .. ==> 0XF8000B40[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x0
+ // .. ==> 0XF8000B40[4:4] = 0x00000000U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. DCI_TYPE = 0x0
+ // .. ==> 0XF8000B40[6:5] = 0x00000000U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000000U
+ // .. IBUF_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B40[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B40[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B40[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B40[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
+ // .. reserved_INP_POWER = 0x0
+ // .. ==> 0XF8000B44[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x0
+ // .. ==> 0XF8000B44[2:1] = 0x00000000U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000000U
+ // .. DCI_UPDATE_B = 0x0
+ // .. ==> 0XF8000B44[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x0
+ // .. ==> 0XF8000B44[4:4] = 0x00000000U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. DCI_TYPE = 0x0
+ // .. ==> 0XF8000B44[6:5] = 0x00000000U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000000U
+ // .. IBUF_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B44[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B44[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B44[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B44[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
+ // .. reserved_INP_POWER = 0x0
+ // .. ==> 0XF8000B48[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x1
+ // .. ==> 0XF8000B48[2:1] = 0x00000001U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000002U
+ // .. DCI_UPDATE_B = 0x0
+ // .. ==> 0XF8000B48[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x1
+ // .. ==> 0XF8000B48[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. DCI_TYPE = 0x3
+ // .. ==> 0XF8000B48[6:5] = 0x00000003U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000060U
+ // .. IBUF_DISABLE_MODE = 0
+ // .. ==> 0XF8000B48[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0
+ // .. ==> 0XF8000B48[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B48[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B48[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
+ // .. reserved_INP_POWER = 0x0
+ // .. ==> 0XF8000B4C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x1
+ // .. ==> 0XF8000B4C[2:1] = 0x00000001U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000002U
+ // .. DCI_UPDATE_B = 0x0
+ // .. ==> 0XF8000B4C[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x1
+ // .. ==> 0XF8000B4C[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. DCI_TYPE = 0x3
+ // .. ==> 0XF8000B4C[6:5] = 0x00000003U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000060U
+ // .. IBUF_DISABLE_MODE = 0
+ // .. ==> 0XF8000B4C[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0
+ // .. ==> 0XF8000B4C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B4C[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B4C[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
+ // .. reserved_INP_POWER = 0x0
+ // .. ==> 0XF8000B50[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x2
+ // .. ==> 0XF8000B50[2:1] = 0x00000002U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000004U
+ // .. DCI_UPDATE_B = 0x0
+ // .. ==> 0XF8000B50[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x1
+ // .. ==> 0XF8000B50[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. DCI_TYPE = 0x3
+ // .. ==> 0XF8000B50[6:5] = 0x00000003U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000060U
+ // .. IBUF_DISABLE_MODE = 0
+ // .. ==> 0XF8000B50[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0
+ // .. ==> 0XF8000B50[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B50[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B50[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
+ // .. reserved_INP_POWER = 0x0
+ // .. ==> 0XF8000B54[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x2
+ // .. ==> 0XF8000B54[2:1] = 0x00000002U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000004U
+ // .. DCI_UPDATE_B = 0x0
+ // .. ==> 0XF8000B54[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x1
+ // .. ==> 0XF8000B54[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. DCI_TYPE = 0x3
+ // .. ==> 0XF8000B54[6:5] = 0x00000003U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000060U
+ // .. IBUF_DISABLE_MODE = 0
+ // .. ==> 0XF8000B54[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0
+ // .. ==> 0XF8000B54[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B54[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B54[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
+ // .. reserved_INP_POWER = 0x0
+ // .. ==> 0XF8000B58[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x0
+ // .. ==> 0XF8000B58[2:1] = 0x00000000U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000000U
+ // .. DCI_UPDATE_B = 0x0
+ // .. ==> 0XF8000B58[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x0
+ // .. ==> 0XF8000B58[4:4] = 0x00000000U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. DCI_TYPE = 0x0
+ // .. ==> 0XF8000B58[6:5] = 0x00000000U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000000U
+ // .. IBUF_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B58[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B58[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B58[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B58[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
+ // .. reserved_DRIVE_P = 0x1c
+ // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
+ // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
+ // .. reserved_DRIVE_N = 0xc
+ // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
+ // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
+ // .. reserved_SLEW_P = 0x3
+ // .. ==> 0XF8000B5C[18:14] = 0x00000003U
+ // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U
+ // .. reserved_SLEW_N = 0x3
+ // .. ==> 0XF8000B5C[23:19] = 0x00000003U
+ // .. ==> MASK : 0x00F80000U VAL : 0x00180000U
+ // .. reserved_GTL = 0x0
+ // .. ==> 0XF8000B5C[26:24] = 0x00000000U
+ // .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. reserved_RTERM = 0x0
+ // .. ==> 0XF8000B5C[31:27] = 0x00000000U
+ // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
+ // .. reserved_DRIVE_P = 0x1c
+ // .. ==> 0XF8000B60[6:0] = 0x0000001CU
+ // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
+ // .. reserved_DRIVE_N = 0xc
+ // .. ==> 0XF8000B60[13:7] = 0x0000000CU
+ // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
+ // .. reserved_SLEW_P = 0x6
+ // .. ==> 0XF8000B60[18:14] = 0x00000006U
+ // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
+ // .. reserved_SLEW_N = 0x1f
+ // .. ==> 0XF8000B60[23:19] = 0x0000001FU
+ // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
+ // .. reserved_GTL = 0x0
+ // .. ==> 0XF8000B60[26:24] = 0x00000000U
+ // .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. reserved_RTERM = 0x0
+ // .. ==> 0XF8000B60[31:27] = 0x00000000U
+ // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
+ // .. reserved_DRIVE_P = 0x1c
+ // .. ==> 0XF8000B64[6:0] = 0x0000001CU
+ // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
+ // .. reserved_DRIVE_N = 0xc
+ // .. ==> 0XF8000B64[13:7] = 0x0000000CU
+ // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
+ // .. reserved_SLEW_P = 0x6
+ // .. ==> 0XF8000B64[18:14] = 0x00000006U
+ // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
+ // .. reserved_SLEW_N = 0x1f
+ // .. ==> 0XF8000B64[23:19] = 0x0000001FU
+ // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
+ // .. reserved_GTL = 0x0
+ // .. ==> 0XF8000B64[26:24] = 0x00000000U
+ // .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. reserved_RTERM = 0x0
+ // .. ==> 0XF8000B64[31:27] = 0x00000000U
+ // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
+ // .. reserved_DRIVE_P = 0x1c
+ // .. ==> 0XF8000B68[6:0] = 0x0000001CU
+ // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
+ // .. reserved_DRIVE_N = 0xc
+ // .. ==> 0XF8000B68[13:7] = 0x0000000CU
+ // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
+ // .. reserved_SLEW_P = 0x6
+ // .. ==> 0XF8000B68[18:14] = 0x00000006U
+ // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
+ // .. reserved_SLEW_N = 0x1f
+ // .. ==> 0XF8000B68[23:19] = 0x0000001FU
+ // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
+ // .. reserved_GTL = 0x0
+ // .. ==> 0XF8000B68[26:24] = 0x00000000U
+ // .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. reserved_RTERM = 0x0
+ // .. ==> 0XF8000B68[31:27] = 0x00000000U
+ // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
+ // .. VREF_INT_EN = 0x1
+ // .. ==> 0XF8000B6C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. VREF_SEL = 0x4
+ // .. ==> 0XF8000B6C[4:1] = 0x00000004U
+ // .. ==> MASK : 0x0000001EU VAL : 0x00000008U
+ // .. VREF_EXT_EN = 0x0
+ // .. ==> 0XF8000B6C[6:5] = 0x00000000U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000000U
+ // .. reserved_VREF_PULLUP_EN = 0x0
+ // .. ==> 0XF8000B6C[8:7] = 0x00000000U
+ // .. ==> MASK : 0x00000180U VAL : 0x00000000U
+ // .. REFIO_EN = 0x1
+ // .. ==> 0XF8000B6C[9:9] = 0x00000001U
+ // .. ==> MASK : 0x00000200U VAL : 0x00000200U
+ // .. reserved_REFIO_TEST = 0x3
+ // .. ==> 0XF8000B6C[11:10] = 0x00000003U
+ // .. ==> MASK : 0x00000C00U VAL : 0x00000C00U
+ // .. reserved_REFIO_PULLUP_EN = 0x0
+ // .. ==> 0XF8000B6C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. reserved_DRST_B_PULLUP_EN = 0x0
+ // .. ==> 0XF8000B6C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // .. reserved_CKE_PULLUP_EN = 0x0
+ // .. ==> 0XF8000B6C[14:14] = 0x00000000U
+ // .. ==> MASK : 0x00004000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000E09U),
+ // .. .. START: ASSERT RESET
+ // .. .. RESET = 1
+ // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000B70, 0x00000001U ,0x00000001U),
+ // .. .. FINISH: ASSERT RESET
+ // .. .. START: DEASSERT RESET
+ // .. .. RESET = 0
+ // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reserved_VRN_OUT = 0x1
+ // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
+ // .. .. FINISH: DEASSERT RESET
+ // .. .. RESET = 0x1
+ // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ENABLE = 0x1
+ // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. .. reserved_VRP_TRI = 0x0
+ // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reserved_VRN_TRI = 0x0
+ // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reserved_VRP_OUT = 0x0
+ // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reserved_VRN_OUT = 0x1
+ // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
+ // .. .. NREF_OPT1 = 0x0
+ // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
+ // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U
+ // .. .. NREF_OPT2 = 0x0
+ // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U
+ // .. .. NREF_OPT4 = 0x1
+ // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
+ // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U
+ // .. .. PREF_OPT1 = 0x0
+ // .. .. ==> 0XF8000B70[15:14] = 0x00000000U
+ // .. .. ==> MASK : 0x0000C000U VAL : 0x00000000U
+ // .. .. PREF_OPT2 = 0x0
+ // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
+ // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U
+ // .. .. UPDATE_CONTROL = 0x0
+ // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
+ // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U
+ // .. .. reserved_INIT_COMPLETE = 0x0
+ // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
+ // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U
+ // .. .. reserved_TST_CLK = 0x0
+ // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
+ // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U
+ // .. .. reserved_TST_HLN = 0x0
+ // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
+ // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U
+ // .. .. reserved_TST_HLP = 0x0
+ // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
+ // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U
+ // .. .. reserved_TST_RST = 0x0
+ // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
+ // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
+ // .. .. reserved_INT_DCI_EN = 0x0
+ // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
+ // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU ,0x00000823U),
+ // .. FINISH: DDRIOB SETTINGS
+ // .. START: MIO PROGRAMMING
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000700[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. Speed = 0
+ // .. ==> 0XF8000700[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000700[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000700[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000700[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000700, 0x00003F01U ,0x00001201U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000704[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000704[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000704[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000704[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000704[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000704[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000704[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000704[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000704[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000708[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000708[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000708[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000708[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000708[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000708[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000708[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000708[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000708[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800070C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF800070C[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800070C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800070C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800070C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800070C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800070C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800070C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800070C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000710[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000710[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000710[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000710[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000710[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000710[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000710[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000710[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000710[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000714[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000714[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000714[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000714[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000714[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000714[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000714[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000714[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000714[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000718[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000718[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000718[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000718[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000718[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000718[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000718[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000718[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000718[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800071C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800071C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800071C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800071C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800071C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800071C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800071C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800071C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800071C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000200U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000720[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000720[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000720[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000720[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000720[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000720[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000720[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000720[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000720[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000724[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000724[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000724[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000724[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000724[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000724[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000724[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000724[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000724[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001200U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000728[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000728[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000728[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000728[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000728[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000728[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000728[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000728[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000728[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001200U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800072C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800072C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800072C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800072C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800072C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800072C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800072C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF800072C[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800072C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001200U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000730[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000730[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000730[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000730[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000730[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000730[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000730[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000730[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000730[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001200U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000734[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000734[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000734[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000734[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000734[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000734[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000734[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000734[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000734[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001200U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000738[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000738[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000738[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000738[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000738[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000738[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000738[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000738[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000738[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00001200U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF800073C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. Speed = 0
+ // .. ==> 0XF800073C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800073C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF800073C[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800073C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800073C, 0x00003F01U ,0x00001201U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000740[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000740[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000740[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000740[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000740[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000740[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 4
+ // .. ==> 0XF8000740[11:9] = 0x00000004U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000740[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 1
+ // .. ==> 0XF8000740[13:13] = 0x00000001U
+ // .. ==> MASK : 0x00002000U VAL : 0x00002000U
+ // ..
+ EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00002802U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000744[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000744[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000744[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000744[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000744[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000744[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 4
+ // .. ==> 0XF8000744[11:9] = 0x00000004U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000744[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 1
+ // .. ==> 0XF8000744[13:13] = 0x00000001U
+ // .. ==> MASK : 0x00002000U VAL : 0x00002000U
+ // ..
+ EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00002802U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000748[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000748[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000748[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000748[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000748[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000748[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 4
+ // .. ==> 0XF8000748[11:9] = 0x00000004U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000748[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 1
+ // .. ==> 0XF8000748[13:13] = 0x00000001U
+ // .. ==> MASK : 0x00002000U VAL : 0x00002000U
+ // ..
+ EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00002802U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800074C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF800074C[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800074C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800074C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800074C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800074C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 4
+ // .. ==> 0XF800074C[11:9] = 0x00000004U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
+ // .. PULLUP = 0
+ // .. ==> 0XF800074C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 1
+ // .. ==> 0XF800074C[13:13] = 0x00000001U
+ // .. ==> MASK : 0x00002000U VAL : 0x00002000U
+ // ..
+ EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00002802U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000750[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000750[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000750[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000750[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000750[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000750[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 4
+ // .. ==> 0XF8000750[11:9] = 0x00000004U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000750[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 1
+ // .. ==> 0XF8000750[13:13] = 0x00000001U
+ // .. ==> MASK : 0x00002000U VAL : 0x00002000U
+ // ..
+ EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00002802U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000754[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000754[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000754[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000754[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000754[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000754[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 4
+ // .. ==> 0XF8000754[11:9] = 0x00000004U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000754[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 1
+ // .. ==> 0XF8000754[13:13] = 0x00000001U
+ // .. ==> MASK : 0x00002000U VAL : 0x00002000U
+ // ..
+ EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00002802U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000758[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000758[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000758[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000758[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000758[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000758[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 4
+ // .. ==> 0XF8000758[11:9] = 0x00000004U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000758[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000758[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000803U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF800075C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF800075C[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800075C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800075C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800075C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800075C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 4
+ // .. ==> 0XF800075C[11:9] = 0x00000004U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
+ // .. PULLUP = 0
+ // .. ==> 0XF800075C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800075C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000803U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000760[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000760[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000760[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000760[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000760[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000760[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 4
+ // .. ==> 0XF8000760[11:9] = 0x00000004U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000760[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000760[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000803U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000764[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000764[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000764[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000764[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000764[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000764[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 4
+ // .. ==> 0XF8000764[11:9] = 0x00000004U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000764[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000764[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000803U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000768[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000768[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000768[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000768[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000768[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000768[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 4
+ // .. ==> 0XF8000768[11:9] = 0x00000004U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000768[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000768[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000803U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF800076C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF800076C[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800076C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800076C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800076C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800076C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 4
+ // .. ==> 0XF800076C[11:9] = 0x00000004U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
+ // .. PULLUP = 0
+ // .. ==> 0XF800076C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800076C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000803U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000770[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000770[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000770[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000770[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000770[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000770[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000770[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000770[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000770[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000774[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000774[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000774[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000774[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000774[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000774[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000774[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000774[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000774[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000778[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000778[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000778[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000778[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000778[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000778[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000778[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000778[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000778[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF800077C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800077C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF800077C[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800077C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800077C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800077C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800077C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800077C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800077C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000780[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000780[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000780[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000780[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000780[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000780[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000780[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000780[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000780[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000784[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000784[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000784[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000784[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000784[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000784[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000784[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000784[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000784[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000788[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000788[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000788[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000788[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000788[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000788[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000788[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000788[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000788[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800078C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800078C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF800078C[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800078C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800078C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800078C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800078C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800078C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800078C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000790[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000790[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000790[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000790[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000790[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000790[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000790[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000790[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000790[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000794[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000794[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000794[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000794[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000794[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000794[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000794[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000794[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000794[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000798[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000798[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000798[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000798[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000798[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000798[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000798[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000798[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000798[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800079C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800079C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF800079C[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800079C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800079C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800079C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800079C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800079C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800079C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007A0[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007A0[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007A0[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007A0[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007A0[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007A0[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007A0[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007A0[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007A0[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007A4[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007A4[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007A4[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007A4[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007A4[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007A4[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007A4[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007A4[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007A4[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007A8[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007A8[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007A8[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007A8[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007A8[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007A8[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007A8[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007A8[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007A8[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007AC[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007AC[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007AC[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007AC[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007AC[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007AC[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007AC[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007AC[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007AC[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007B0[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007B0[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007B0[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007B0[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007B0[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007B0[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007B0[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007B0[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007B0[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007B4[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007B4[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007B4[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007B4[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007B4[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007B4[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007B4[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007B4[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007B4[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000280U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF80007B8[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007B8[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007B8[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007B8[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 1
+ // .. ==> 0XF80007B8[7:5] = 0x00000001U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000020U
+ // .. Speed = 0
+ // .. ==> 0XF80007B8[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007B8[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF80007B8[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007B8[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001221U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007BC[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007BC[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007BC[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007BC[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 1
+ // .. ==> 0XF80007BC[7:5] = 0x00000001U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000020U
+ // .. Speed = 0
+ // .. ==> 0XF80007BC[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007BC[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF80007BC[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007BC[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00001220U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007C0[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007C0[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007C0[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007C0[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 7
+ // .. ==> 0XF80007C0[7:5] = 0x00000007U
+ // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U
+ // .. Speed = 0
+ // .. ==> 0XF80007C0[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007C0[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007C0[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007C0[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF80007C4[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007C4[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007C4[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007C4[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 7
+ // .. ==> 0XF80007C4[7:5] = 0x00000007U
+ // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U
+ // .. Speed = 0
+ // .. ==> 0XF80007C4[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007C4[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007C4[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007C4[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007C8[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007C8[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007C8[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007C8[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 2
+ // .. ==> 0XF80007C8[7:5] = 0x00000002U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000040U
+ // .. Speed = 0
+ // .. ==> 0XF80007C8[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007C8[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF80007C8[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007C8[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001240U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007CC[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007CC[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007CC[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007CC[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 2
+ // .. ==> 0XF80007CC[7:5] = 0x00000002U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000040U
+ // .. Speed = 0
+ // .. ==> 0XF80007CC[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007CC[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF80007CC[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007CC[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001240U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007D0[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007D0[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007D0[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007D0[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007D0[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007D0[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007D0[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007D0[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007D0[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007D4[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007D4[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007D4[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007D4[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007D4[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007D4[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007D4[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007D4[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007D4[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U),
+ // .. SDIO0_WP_SEL = 15
+ // .. ==> 0XF8000830[5:0] = 0x0000000FU
+ // .. ==> MASK : 0x0000003FU VAL : 0x0000000FU
+ // .. SDIO0_CD_SEL = 0
+ // .. ==> 0XF8000830[21:16] = 0x00000000U
+ // .. ==> MASK : 0x003F0000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x0000000FU),
+ // .. FINISH: MIO PROGRAMMING
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_peripherals_init_data_3_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+ // .. IBUF_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B48[7:7] = 0x00000001U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. TERM_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B48[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // ..
+ EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
+ // .. IBUF_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B4C[7:7] = 0x00000001U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. TERM_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B4C[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // ..
+ EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
+ // .. IBUF_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B50[7:7] = 0x00000001U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. TERM_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B50[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // ..
+ EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
+ // .. IBUF_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B54[7:7] = 0x00000001U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. TERM_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B54[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // ..
+ EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
+ // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // .. START: SRAM/NOR SET OPMODE
+ // .. FINISH: SRAM/NOR SET OPMODE
+ // .. START: UART REGISTERS
+ // .. BDIV = 0x6
+ // .. ==> 0XE0001034[7:0] = 0x00000006U
+ // .. ==> MASK : 0x000000FFU VAL : 0x00000006U
+ // ..
+ EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
+ // .. CD = 0x3e
+ // .. ==> 0XE0001018[15:0] = 0x0000003EU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU
+ // ..
+ EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
+ // .. STPBRK = 0x0
+ // .. ==> 0XE0001000[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. STTBRK = 0x0
+ // .. ==> 0XE0001000[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. RSTTO = 0x0
+ // .. ==> 0XE0001000[6:6] = 0x00000000U
+ // .. ==> MASK : 0x00000040U VAL : 0x00000000U
+ // .. TXDIS = 0x0
+ // .. ==> 0XE0001000[5:5] = 0x00000000U
+ // .. ==> MASK : 0x00000020U VAL : 0x00000000U
+ // .. TXEN = 0x1
+ // .. ==> 0XE0001000[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. RXDIS = 0x0
+ // .. ==> 0XE0001000[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. RXEN = 0x1
+ // .. ==> 0XE0001000[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. TXRES = 0x1
+ // .. ==> 0XE0001000[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. RXRES = 0x1
+ // .. ==> 0XE0001000[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // ..
+ EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
+ // .. CHMODE = 0x0
+ // .. ==> 0XE0001004[9:8] = 0x00000000U
+ // .. ==> MASK : 0x00000300U VAL : 0x00000000U
+ // .. NBSTOP = 0x0
+ // .. ==> 0XE0001004[7:6] = 0x00000000U
+ // .. ==> MASK : 0x000000C0U VAL : 0x00000000U
+ // .. PAR = 0x4
+ // .. ==> 0XE0001004[5:3] = 0x00000004U
+ // .. ==> MASK : 0x00000038U VAL : 0x00000020U
+ // .. CHRL = 0x0
+ // .. ==> 0XE0001004[2:1] = 0x00000000U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000000U
+ // .. CLKS = 0x0
+ // .. ==> 0XE0001004[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XE0001004, 0x000003FFU ,0x00000020U),
+ // .. FINISH: UART REGISTERS
+ // .. START: QSPI REGISTERS
+ // .. Holdb_dr = 1
+ // .. ==> 0XE000D000[19:19] = 0x00000001U
+ // .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // ..
+ EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
+ // .. FINISH: QSPI REGISTERS
+ // .. START: PL POWER ON RESET REGISTERS
+ // .. PCFG_POR_CNT_4K = 0
+ // .. ==> 0XF8007000[29:29] = 0x00000000U
+ // .. ==> MASK : 0x20000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
+ // .. FINISH: PL POWER ON RESET REGISTERS
+ // .. START: SMC TIMING CALCULATION REGISTER UPDATE
+ // .. .. START: NAND SET CYCLE
+ // .. .. FINISH: NAND SET CYCLE
+ // .. .. START: OPMODE
+ // .. .. FINISH: OPMODE
+ // .. .. START: DIRECT COMMAND
+ // .. .. FINISH: DIRECT COMMAND
+ // .. .. START: SRAM/NOR CS0 SET CYCLE
+ // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
+ // .. .. START: DIRECT COMMAND
+ // .. .. FINISH: DIRECT COMMAND
+ // .. .. START: NOR CS0 BASE ADDRESS
+ // .. .. FINISH: NOR CS0 BASE ADDRESS
+ // .. .. START: SRAM/NOR CS1 SET CYCLE
+ // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
+ // .. .. START: DIRECT COMMAND
+ // .. .. FINISH: DIRECT COMMAND
+ // .. .. START: NOR CS1 BASE ADDRESS
+ // .. .. FINISH: NOR CS1 BASE ADDRESS
+ // .. .. START: USB RESET
+ // .. .. .. START: USB0 RESET
+ // .. .. .. .. START: DIR MODE BANK 0
+ // .. .. .. .. DIRECTION_0 = 0x80
+ // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U
+ // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U),
+ // .. .. .. .. FINISH: DIR MODE BANK 0
+ // .. .. .. .. START: DIR MODE BANK 1
+ // .. .. .. .. FINISH: DIR MODE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. MASK_0_LSW = 0xff7f
+ // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+ // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U
+ // .. .. .. .. DATA_0_LSW = 0x80
+ // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+ // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. START: OUTPUT ENABLE BANK 0
+ // .. .. .. .. OP_ENABLE_0 = 0x80
+ // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U
+ // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U),
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+ // .. .. .. .. START: OUTPUT ENABLE BANK 1
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. MASK_0_LSW = 0xff7f
+ // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+ // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U
+ // .. .. .. .. DATA_0_LSW = 0x0
+ // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+ // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U),
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. START: ADD 1 MS DELAY
+ // .. .. .. ..
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ // .. .. .. .. FINISH: ADD 1 MS DELAY
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. MASK_0_LSW = 0xff7f
+ // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+ // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U
+ // .. .. .. .. DATA_0_LSW = 0x80
+ // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+ // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. FINISH: USB0 RESET
+ // .. .. .. START: USB1 RESET
+ // .. .. .. .. START: DIR MODE BANK 0
+ // .. .. .. .. FINISH: DIR MODE BANK 0
+ // .. .. .. .. START: DIR MODE BANK 1
+ // .. .. .. .. FINISH: DIR MODE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. START: OUTPUT ENABLE BANK 0
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+ // .. .. .. .. START: OUTPUT ENABLE BANK 1
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. START: ADD 1 MS DELAY
+ // .. .. .. ..
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ // .. .. .. .. FINISH: ADD 1 MS DELAY
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. FINISH: USB1 RESET
+ // .. .. FINISH: USB RESET
+ // .. .. START: ENET RESET
+ // .. .. .. START: ENET0 RESET
+ // .. .. .. .. START: DIR MODE BANK 0
+ // .. .. .. .. DIRECTION_0 = 0x800
+ // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000800U
+ // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000800U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000800U),
+ // .. .. .. .. FINISH: DIR MODE BANK 0
+ // .. .. .. .. START: DIR MODE BANK 1
+ // .. .. .. .. FINISH: DIR MODE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. MASK_0_LSW = 0xf7ff
+ // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU
+ // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xF7FF0000U
+ // .. .. .. .. DATA_0_LSW = 0x800
+ // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000800U
+ // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000800U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0800U),
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. START: OUTPUT ENABLE BANK 0
+ // .. .. .. .. OP_ENABLE_0 = 0x800
+ // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000800U
+ // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000800U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000800U),
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+ // .. .. .. .. START: OUTPUT ENABLE BANK 1
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. MASK_0_LSW = 0xf7ff
+ // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU
+ // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xF7FF0000U
+ // .. .. .. .. DATA_0_LSW = 0x0
+ // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+ // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0000U),
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. START: ADD 1 MS DELAY
+ // .. .. .. ..
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ // .. .. .. .. FINISH: ADD 1 MS DELAY
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. MASK_0_LSW = 0xf7ff
+ // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU
+ // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xF7FF0000U
+ // .. .. .. .. DATA_0_LSW = 0x800
+ // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000800U
+ // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000800U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0800U),
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. FINISH: ENET0 RESET
+ // .. .. .. START: ENET1 RESET
+ // .. .. .. .. START: DIR MODE BANK 0
+ // .. .. .. .. FINISH: DIR MODE BANK 0
+ // .. .. .. .. START: DIR MODE BANK 1
+ // .. .. .. .. FINISH: DIR MODE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. START: OUTPUT ENABLE BANK 0
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+ // .. .. .. .. START: OUTPUT ENABLE BANK 1
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. START: ADD 1 MS DELAY
+ // .. .. .. ..
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ // .. .. .. .. FINISH: ADD 1 MS DELAY
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. FINISH: ENET1 RESET
+ // .. .. FINISH: ENET RESET
+ // .. .. START: I2C RESET
+ // .. .. .. START: I2C0 RESET
+ // .. .. .. .. START: DIR MODE GPIO BANK0
+ // .. .. .. .. DIRECTION_0 = 0x2000
+ // .. .. .. .. ==> 0XE000A204[31:0] = 0x00002000U
+ // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002000U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002000U),
+ // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+ // .. .. .. .. START: DIR MODE GPIO BANK1
+ // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. MASK_0_LSW = 0xdfff
+ // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU
+ // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xDFFF0000U
+ // .. .. .. .. DATA_0_LSW = 0x2000
+ // .. .. .. .. ==> 0XE000A000[15:0] = 0x00002000U
+ // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00002000U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF2000U),
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. START: OUTPUT ENABLE
+ // .. .. .. .. OP_ENABLE_0 = 0x2000
+ // .. .. .. .. ==> 0XE000A208[31:0] = 0x00002000U
+ // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002000U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002000U),
+ // .. .. .. .. FINISH: OUTPUT ENABLE
+ // .. .. .. .. START: OUTPUT ENABLE
+ // .. .. .. .. FINISH: OUTPUT ENABLE
+ // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. MASK_0_LSW = 0xdfff
+ // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU
+ // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xDFFF0000U
+ // .. .. .. .. DATA_0_LSW = 0x0
+ // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+ // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF0000U),
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. START: ADD 1 MS DELAY
+ // .. .. .. ..
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ // .. .. .. .. FINISH: ADD 1 MS DELAY
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. MASK_0_LSW = 0xdfff
+ // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU
+ // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xDFFF0000U
+ // .. .. .. .. DATA_0_LSW = 0x2000
+ // .. .. .. .. ==> 0XE000A000[15:0] = 0x00002000U
+ // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00002000U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF2000U),
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. FINISH: I2C0 RESET
+ // .. .. .. START: I2C1 RESET
+ // .. .. .. .. START: DIR MODE GPIO BANK0
+ // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+ // .. .. .. .. START: DIR MODE GPIO BANK1
+ // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. START: OUTPUT ENABLE
+ // .. .. .. .. FINISH: OUTPUT ENABLE
+ // .. .. .. .. START: OUTPUT ENABLE
+ // .. .. .. .. FINISH: OUTPUT ENABLE
+ // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. START: ADD 1 MS DELAY
+ // .. .. .. ..
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ // .. .. .. .. FINISH: ADD 1 MS DELAY
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. FINISH: I2C1 RESET
+ // .. .. FINISH: I2C RESET
+ // .. .. START: NOR CHIP SELECT
+ // .. .. .. START: DIR MODE BANK 0
+ // .. .. .. FINISH: DIR MODE BANK 0
+ // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. START: OUTPUT ENABLE BANK 0
+ // .. .. .. FINISH: OUTPUT ENABLE BANK 0
+ // .. .. FINISH: NOR CHIP SELECT
+ // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_post_config_3_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: ENABLING LEVEL SHIFTER
+ // .. USER_LVL_INP_EN_0 = 1
+ // .. ==> 0XF8000900[3:3] = 0x00000001U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000008U
+ // .. USER_LVL_OUT_EN_0 = 1
+ // .. ==> 0XF8000900[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. USER_LVL_INP_EN_1 = 1
+ // .. ==> 0XF8000900[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. USER_LVL_OUT_EN_1 = 1
+ // .. ==> 0XF8000900[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // ..
+ EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
+ // .. FINISH: ENABLING LEVEL SHIFTER
+ // .. START: FPGA RESETS TO 0
+ // .. reserved_3 = 0
+ // .. ==> 0XF8000240[31:25] = 0x00000000U
+ // .. ==> MASK : 0xFE000000U VAL : 0x00000000U
+ // .. reserved_FPGA_ACP_RST = 0
+ // .. ==> 0XF8000240[24:24] = 0x00000000U
+ // .. ==> MASK : 0x01000000U VAL : 0x00000000U
+ // .. reserved_FPGA_AXDS3_RST = 0
+ // .. ==> 0XF8000240[23:23] = 0x00000000U
+ // .. ==> MASK : 0x00800000U VAL : 0x00000000U
+ // .. reserved_FPGA_AXDS2_RST = 0
+ // .. ==> 0XF8000240[22:22] = 0x00000000U
+ // .. ==> MASK : 0x00400000U VAL : 0x00000000U
+ // .. reserved_FPGA_AXDS1_RST = 0
+ // .. ==> 0XF8000240[21:21] = 0x00000000U
+ // .. ==> MASK : 0x00200000U VAL : 0x00000000U
+ // .. reserved_FPGA_AXDS0_RST = 0
+ // .. ==> 0XF8000240[20:20] = 0x00000000U
+ // .. ==> MASK : 0x00100000U VAL : 0x00000000U
+ // .. reserved_2 = 0
+ // .. ==> 0XF8000240[19:18] = 0x00000000U
+ // .. ==> MASK : 0x000C0000U VAL : 0x00000000U
+ // .. reserved_FSSW1_FPGA_RST = 0
+ // .. ==> 0XF8000240[17:17] = 0x00000000U
+ // .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. reserved_FSSW0_FPGA_RST = 0
+ // .. ==> 0XF8000240[16:16] = 0x00000000U
+ // .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. reserved_1 = 0
+ // .. ==> 0XF8000240[15:14] = 0x00000000U
+ // .. ==> MASK : 0x0000C000U VAL : 0x00000000U
+ // .. reserved_FPGA_FMSW1_RST = 0
+ // .. ==> 0XF8000240[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // .. reserved_FPGA_FMSW0_RST = 0
+ // .. ==> 0XF8000240[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. reserved_FPGA_DMA3_RST = 0
+ // .. ==> 0XF8000240[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. reserved_FPGA_DMA2_RST = 0
+ // .. ==> 0XF8000240[10:10] = 0x00000000U
+ // .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. reserved_FPGA_DMA1_RST = 0
+ // .. ==> 0XF8000240[9:9] = 0x00000000U
+ // .. ==> MASK : 0x00000200U VAL : 0x00000000U
+ // .. reserved_FPGA_DMA0_RST = 0
+ // .. ==> 0XF8000240[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. reserved = 0
+ // .. ==> 0XF8000240[7:4] = 0x00000000U
+ // .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. FPGA3_OUT_RST = 0
+ // .. ==> 0XF8000240[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. FPGA2_OUT_RST = 0
+ // .. ==> 0XF8000240[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. FPGA1_OUT_RST = 0
+ // .. ==> 0XF8000240[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. FPGA0_OUT_RST = 0
+ // .. ==> 0XF8000240[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
+ // .. FINISH: FPGA RESETS TO 0
+ // .. START: AFI REGISTERS
+ // .. .. START: AFI0 REGISTERS
+ // .. .. FINISH: AFI0 REGISTERS
+ // .. .. START: AFI1 REGISTERS
+ // .. .. FINISH: AFI1 REGISTERS
+ // .. .. START: AFI2 REGISTERS
+ // .. .. FINISH: AFI2 REGISTERS
+ // .. .. START: AFI3 REGISTERS
+ // .. .. FINISH: AFI3 REGISTERS
+ // .. FINISH: AFI REGISTERS
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_debug_3_0[] = {
+ // START: top
+ // .. START: CROSS TRIGGER CONFIGURATIONS
+ // .. .. START: UNLOCKING CTI REGISTERS
+ // .. .. KEY = 0XC5ACCE55
+ // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
+ // .. ..
+ EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
+ // .. .. KEY = 0XC5ACCE55
+ // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
+ // .. ..
+ EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
+ // .. .. KEY = 0XC5ACCE55
+ // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
+ // .. ..
+ EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
+ // .. .. FINISH: UNLOCKING CTI REGISTERS
+ // .. .. START: ENABLING CTI MODULES AND CHANNELS
+ // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
+ // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+ // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+ // .. FINISH: CROSS TRIGGER CONFIGURATIONS
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_pll_init_data_2_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: PLL SLCR REGISTERS
+ // .. .. START: ARM PLL INIT
+ // .. .. PLL_RES = 0x2
+ // .. .. ==> 0XF8000110[7:4] = 0x00000002U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
+ // .. .. PLL_CP = 0x2
+ // .. .. ==> 0XF8000110[11:8] = 0x00000002U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
+ // .. .. LOCK_CNT = 0xfa
+ // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
+ // .. .. .. START: UPDATE FB_DIV
+ // .. .. .. PLL_FDIV = 0x28
+ // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
+ // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
+ // .. .. .. FINISH: UPDATE FB_DIV
+ // .. .. .. START: BY PASS PLL
+ // .. .. .. PLL_BYPASS_FORCE = 1
+ // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
+ // .. .. .. FINISH: BY PASS PLL
+ // .. .. .. START: ASSERT RESET
+ // .. .. .. PLL_RESET = 1
+ // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
+ // .. .. .. FINISH: ASSERT RESET
+ // .. .. .. START: DEASSERT RESET
+ // .. .. .. PLL_RESET = 0
+ // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
+ // .. .. .. FINISH: DEASSERT RESET
+ // .. .. .. START: CHECK PLL STATUS
+ // .. .. .. ARM_PLL_LOCK = 1
+ // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ..
+ EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+ // .. .. .. FINISH: CHECK PLL STATUS
+ // .. .. .. START: REMOVE PLL BY PASS
+ // .. .. .. PLL_BYPASS_FORCE = 0
+ // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
+ // .. .. .. FINISH: REMOVE PLL BY PASS
+ // .. .. .. SRCSEL = 0x0
+ // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. .. .. DIVISOR = 0x2
+ // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
+ // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U
+ // .. .. .. CPU_6OR4XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
+ // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U
+ // .. .. .. CPU_3OR2XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
+ // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U
+ // .. .. .. CPU_2XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
+ // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U
+ // .. .. .. CPU_1XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
+ // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U
+ // .. .. .. CPU_PERI_CLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
+ // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
+ // .. .. FINISH: ARM PLL INIT
+ // .. .. START: DDR PLL INIT
+ // .. .. PLL_RES = 0x2
+ // .. .. ==> 0XF8000114[7:4] = 0x00000002U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
+ // .. .. PLL_CP = 0x2
+ // .. .. ==> 0XF8000114[11:8] = 0x00000002U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
+ // .. .. LOCK_CNT = 0x12c
+ // .. .. ==> 0XF8000114[21:12] = 0x0000012CU
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
+ // .. .. .. START: UPDATE FB_DIV
+ // .. .. .. PLL_FDIV = 0x20
+ // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
+ // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
+ // .. .. .. FINISH: UPDATE FB_DIV
+ // .. .. .. START: BY PASS PLL
+ // .. .. .. PLL_BYPASS_FORCE = 1
+ // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
+ // .. .. .. FINISH: BY PASS PLL
+ // .. .. .. START: ASSERT RESET
+ // .. .. .. PLL_RESET = 1
+ // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
+ // .. .. .. FINISH: ASSERT RESET
+ // .. .. .. START: DEASSERT RESET
+ // .. .. .. PLL_RESET = 0
+ // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
+ // .. .. .. FINISH: DEASSERT RESET
+ // .. .. .. START: CHECK PLL STATUS
+ // .. .. .. DDR_PLL_LOCK = 1
+ // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. .. ..
+ EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+ // .. .. .. FINISH: CHECK PLL STATUS
+ // .. .. .. START: REMOVE PLL BY PASS
+ // .. .. .. PLL_BYPASS_FORCE = 0
+ // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
+ // .. .. .. FINISH: REMOVE PLL BY PASS
+ // .. .. .. DDR_3XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. .. DDR_2XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. .. .. DDR_3XCLK_DIVISOR = 0x2
+ // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
+ // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U
+ // .. .. .. DDR_2XCLK_DIVISOR = 0x3
+ // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
+ // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
+ // .. .. FINISH: DDR PLL INIT
+ // .. .. START: IO PLL INIT
+ // .. .. PLL_RES = 0xc
+ // .. .. ==> 0XF8000118[7:4] = 0x0000000CU
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U
+ // .. .. PLL_CP = 0x2
+ // .. .. ==> 0XF8000118[11:8] = 0x00000002U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
+ // .. .. LOCK_CNT = 0x145
+ // .. .. ==> 0XF8000118[21:12] = 0x00000145U
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U),
+ // .. .. .. START: UPDATE FB_DIV
+ // .. .. .. PLL_FDIV = 0x1e
+ // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU
+ // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U),
+ // .. .. .. FINISH: UPDATE FB_DIV
+ // .. .. .. START: BY PASS PLL
+ // .. .. .. PLL_BYPASS_FORCE = 1
+ // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
+ // .. .. .. FINISH: BY PASS PLL
+ // .. .. .. START: ASSERT RESET
+ // .. .. .. PLL_RESET = 1
+ // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
+ // .. .. .. FINISH: ASSERT RESET
+ // .. .. .. START: DEASSERT RESET
+ // .. .. .. PLL_RESET = 0
+ // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
+ // .. .. .. FINISH: DEASSERT RESET
+ // .. .. .. START: CHECK PLL STATUS
+ // .. .. .. IO_PLL_LOCK = 1
+ // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. .. ..
+ EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+ // .. .. .. FINISH: CHECK PLL STATUS
+ // .. .. .. START: REMOVE PLL BY PASS
+ // .. .. .. PLL_BYPASS_FORCE = 0
+ // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
+ // .. .. .. FINISH: REMOVE PLL BY PASS
+ // .. .. FINISH: IO PLL INIT
+ // .. FINISH: PLL SLCR REGISTERS
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_clock_init_data_2_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: CLOCK CONTROL SLCR REGISTERS
+ // .. CLKACT = 0x1
+ // .. ==> 0XF8000128[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. DIVISOR0 = 0x23
+ // .. ==> 0XF8000128[13:8] = 0x00000023U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00002300U
+ // .. DIVISOR1 = 0x3
+ // .. ==> 0XF8000128[25:20] = 0x00000003U
+ // .. ==> MASK : 0x03F00000U VAL : 0x00300000U
+ // ..
+ EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U),
+ // .. CLKACT = 0x1
+ // .. ==> 0XF8000138[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000138[4:4] = 0x00000000U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
+ // .. CLKACT = 0x1
+ // .. ==> 0XF8000140[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000140[6:4] = 0x00000000U
+ // .. ==> MASK : 0x00000070U VAL : 0x00000000U
+ // .. DIVISOR = 0x8
+ // .. ==> 0XF8000140[13:8] = 0x00000008U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00000800U
+ // .. DIVISOR1 = 0x5
+ // .. ==> 0XF8000140[25:20] = 0x00000005U
+ // .. ==> MASK : 0x03F00000U VAL : 0x00500000U
+ // ..
+ EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00500801U),
+ // .. CLKACT = 0x1
+ // .. ==> 0XF800014C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF800014C[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR = 0x5
+ // .. ==> 0XF800014C[13:8] = 0x00000005U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00000500U
+ // ..
+ EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
+ // .. CLKACT0 = 0x1
+ // .. ==> 0XF8000150[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. CLKACT1 = 0x0
+ // .. ==> 0XF8000150[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000150[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR = 0x14
+ // .. ==> 0XF8000150[13:8] = 0x00000014U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
+ // ..
+ EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U),
+ // .. CLKACT0 = 0x0
+ // .. ==> 0XF8000154[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. CLKACT1 = 0x1
+ // .. ==> 0XF8000154[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000154[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR = 0x14
+ // .. ==> 0XF8000154[13:8] = 0x00000014U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
+ // ..
+ EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U),
+ // .. CLKACT0 = 0x1
+ // .. ==> 0XF800015C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. CLKACT1 = 0x0
+ // .. ==> 0XF800015C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF800015C[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR0 = 0xe
+ // .. ==> 0XF800015C[13:8] = 0x0000000EU
+ // .. ==> MASK : 0x00003F00U VAL : 0x00000E00U
+ // .. DIVISOR1 = 0x3
+ // .. ==> 0XF800015C[25:20] = 0x00000003U
+ // .. ==> MASK : 0x03F00000U VAL : 0x00300000U
+ // ..
+ EMIT_MASKWRITE(0XF800015C, 0x03F03F33U ,0x00300E01U),
+ // .. CAN0_MUX = 0x0
+ // .. ==> 0XF8000160[5:0] = 0x00000000U
+ // .. ==> MASK : 0x0000003FU VAL : 0x00000000U
+ // .. CAN0_REF_SEL = 0x0
+ // .. ==> 0XF8000160[6:6] = 0x00000000U
+ // .. ==> MASK : 0x00000040U VAL : 0x00000000U
+ // .. CAN1_MUX = 0x0
+ // .. ==> 0XF8000160[21:16] = 0x00000000U
+ // .. ==> MASK : 0x003F0000U VAL : 0x00000000U
+ // .. CAN1_REF_SEL = 0x0
+ // .. ==> 0XF8000160[22:22] = 0x00000000U
+ // .. ==> MASK : 0x00400000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000160, 0x007F007FU ,0x00000000U),
+ // .. CLKACT = 0x1
+ // .. ==> 0XF8000168[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000168[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR = 0x5
+ // .. ==> 0XF8000168[13:8] = 0x00000005U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00000500U
+ // ..
+ EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000170[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR0 = 0x14
+ // .. ==> 0XF8000170[13:8] = 0x00000014U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
+ // .. DIVISOR1 = 0x1
+ // .. ==> 0XF8000170[25:20] = 0x00000001U
+ // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
+ // ..
+ EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00101400U),
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000180[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR0 = 0x14
+ // .. ==> 0XF8000180[13:8] = 0x00000014U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
+ // .. DIVISOR1 = 0x1
+ // .. ==> 0XF8000180[25:20] = 0x00000001U
+ // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
+ // ..
+ EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00101400U),
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000190[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR0 = 0x14
+ // .. ==> 0XF8000190[13:8] = 0x00000014U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
+ // .. DIVISOR1 = 0x1
+ // .. ==> 0XF8000190[25:20] = 0x00000001U
+ // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
+ // ..
+ EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101400U),
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF80001A0[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR0 = 0x14
+ // .. ==> 0XF80001A0[13:8] = 0x00000014U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
+ // .. DIVISOR1 = 0x1
+ // .. ==> 0XF80001A0[25:20] = 0x00000001U
+ // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
+ // ..
+ EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U),
+ // .. CLK_621_TRUE = 0x1
+ // .. ==> 0XF80001C4[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // ..
+ EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
+ // .. DMA_CPU_2XCLKACT = 0x1
+ // .. ==> 0XF800012C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. USB0_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. USB1_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[3:3] = 0x00000001U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000008U
+ // .. GEM0_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[6:6] = 0x00000001U
+ // .. ==> MASK : 0x00000040U VAL : 0x00000040U
+ // .. GEM1_CPU_1XCLKACT = 0x0
+ // .. ==> 0XF800012C[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. SDI0_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[10:10] = 0x00000001U
+ // .. ==> MASK : 0x00000400U VAL : 0x00000400U
+ // .. SDI1_CPU_1XCLKACT = 0x0
+ // .. ==> 0XF800012C[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. SPI0_CPU_1XCLKACT = 0x0
+ // .. ==> 0XF800012C[14:14] = 0x00000000U
+ // .. ==> MASK : 0x00004000U VAL : 0x00000000U
+ // .. SPI1_CPU_1XCLKACT = 0x0
+ // .. ==> 0XF800012C[15:15] = 0x00000000U
+ // .. ==> MASK : 0x00008000U VAL : 0x00000000U
+ // .. CAN0_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[16:16] = 0x00000001U
+ // .. ==> MASK : 0x00010000U VAL : 0x00010000U
+ // .. CAN1_CPU_1XCLKACT = 0x0
+ // .. ==> 0XF800012C[17:17] = 0x00000000U
+ // .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. I2C0_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[18:18] = 0x00000001U
+ // .. ==> MASK : 0x00040000U VAL : 0x00040000U
+ // .. I2C1_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[19:19] = 0x00000001U
+ // .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // .. UART0_CPU_1XCLKACT = 0x0
+ // .. ==> 0XF800012C[20:20] = 0x00000000U
+ // .. ==> MASK : 0x00100000U VAL : 0x00000000U
+ // .. UART1_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[21:21] = 0x00000001U
+ // .. ==> MASK : 0x00200000U VAL : 0x00200000U
+ // .. GPIO_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[22:22] = 0x00000001U
+ // .. ==> MASK : 0x00400000U VAL : 0x00400000U
+ // .. LQSPI_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[23:23] = 0x00000001U
+ // .. ==> MASK : 0x00800000U VAL : 0x00800000U
+ // .. SMC_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[24:24] = 0x00000001U
+ // .. ==> MASK : 0x01000000U VAL : 0x01000000U
+ // ..
+ EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01ED044DU),
+ // .. FINISH: CLOCK CONTROL SLCR REGISTERS
+ // .. START: THIS SHOULD BE BLANK
+ // .. FINISH: THIS SHOULD BE BLANK
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_ddr_init_data_2_0[] = {
+ // START: top
+ // .. START: DDR INITIALIZATION
+ // .. .. START: LOCK DDR
+ // .. .. reg_ddrc_soft_rstb = 0
+ // .. .. ==> 0XF8006000[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_powerdown_en = 0x0
+ // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_ddrc_data_bus_width = 0x0
+ // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U
+ // .. .. reg_ddrc_burst8_refresh = 0x0
+ // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U
+ // .. .. reg_ddrc_rdwr_idle_gap = 0x1
+ // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+ // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U
+ // .. .. reg_ddrc_dis_rd_bypass = 0x0
+ // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+ // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_act_bypass = 0x0
+ // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_auto_refresh = 0x0
+ // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
+ // .. .. FINISH: LOCK DDR
+ // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81
+ // .. .. ==> 0XF8006004[11:0] = 0x00000081U
+ // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U
+ // .. .. reg_ddrc_active_ranks = 0x1
+ // .. .. ==> 0XF8006004[13:12] = 0x00000001U
+ // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U
+ // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
+ // .. .. ==> 0XF8006004[18:14] = 0x00000000U
+ // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U
+ // .. .. reg_ddrc_wr_odt_block = 0x1
+ // .. .. ==> 0XF8006004[20:19] = 0x00000001U
+ // .. .. ==> MASK : 0x00180000U VAL : 0x00080000U
+ // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0
+ // .. .. ==> 0XF8006004[21:21] = 0x00000000U
+ // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0
+ // .. .. ==> 0XF8006004[26:22] = 0x00000000U
+ // .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_open_bank = 0x0
+ // .. .. ==> 0XF8006004[27:27] = 0x00000000U
+ // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_4bank_ram = 0x0
+ // .. .. ==> 0XF8006004[28:28] = 0x00000000U
+ // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U),
+ // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
+ // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU
+ // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
+ // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
+ // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U
+ // .. .. reg_ddrc_hpr_xact_run_length = 0xf
+ // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
+ // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
+ // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
+ // .. .. ==> 0XF800600C[10:0] = 0x00000001U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U
+ // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
+ // .. .. ==> 0XF800600C[21:11] = 0x00000002U
+ // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U
+ // .. .. reg_ddrc_lpr_xact_run_length = 0x8
+ // .. .. ==> 0XF800600C[25:22] = 0x00000008U
+ // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
+ // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
+ // .. .. ==> 0XF8006010[10:0] = 0x00000001U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U
+ // .. .. reg_ddrc_w_xact_run_length = 0x8
+ // .. .. ==> 0XF8006010[14:11] = 0x00000008U
+ // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U
+ // .. .. reg_ddrc_w_max_starve_x32 = 0x2
+ // .. .. ==> 0XF8006010[25:15] = 0x00000002U
+ // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
+ // .. .. reg_ddrc_t_rc = 0x1b
+ // .. .. ==> 0XF8006014[5:0] = 0x0000001BU
+ // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001BU
+ // .. .. reg_ddrc_t_rfc_min = 0x56
+ // .. .. ==> 0XF8006014[13:6] = 0x00000056U
+ // .. .. ==> MASK : 0x00003FC0U VAL : 0x00001580U
+ // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
+ // .. .. ==> 0XF8006014[20:14] = 0x00000010U
+ // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004159BU),
+ // .. .. reg_ddrc_wr2pre = 0x12
+ // .. .. ==> 0XF8006018[4:0] = 0x00000012U
+ // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U
+ // .. .. reg_ddrc_powerdown_to_x32 = 0x6
+ // .. .. ==> 0XF8006018[9:5] = 0x00000006U
+ // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U
+ // .. .. reg_ddrc_t_faw = 0x10
+ // .. .. ==> 0XF8006018[15:10] = 0x00000010U
+ // .. .. ==> MASK : 0x0000FC00U VAL : 0x00004000U
+ // .. .. reg_ddrc_t_ras_max = 0x24
+ // .. .. ==> 0XF8006018[21:16] = 0x00000024U
+ // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U
+ // .. .. reg_ddrc_t_ras_min = 0x14
+ // .. .. ==> 0XF8006018[26:22] = 0x00000014U
+ // .. .. ==> MASK : 0x07C00000U VAL : 0x05000000U
+ // .. .. reg_ddrc_t_cke = 0x4
+ // .. .. ==> 0XF8006018[31:28] = 0x00000004U
+ // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x452440D2U),
+ // .. .. reg_ddrc_write_latency = 0x5
+ // .. .. ==> 0XF800601C[4:0] = 0x00000005U
+ // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U
+ // .. .. reg_ddrc_rd2wr = 0x7
+ // .. .. ==> 0XF800601C[9:5] = 0x00000007U
+ // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U
+ // .. .. reg_ddrc_wr2rd = 0xe
+ // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
+ // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U
+ // .. .. reg_ddrc_t_xp = 0x4
+ // .. .. ==> 0XF800601C[19:15] = 0x00000004U
+ // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U
+ // .. .. reg_ddrc_pad_pd = 0x0
+ // .. .. ==> 0XF800601C[22:20] = 0x00000000U
+ // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U
+ // .. .. reg_ddrc_rd2pre = 0x4
+ // .. .. ==> 0XF800601C[27:23] = 0x00000004U
+ // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U
+ // .. .. reg_ddrc_t_rcd = 0x7
+ // .. .. ==> 0XF800601C[31:28] = 0x00000007U
+ // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
+ // .. .. reg_ddrc_t_ccd = 0x4
+ // .. .. ==> 0XF8006020[4:2] = 0x00000004U
+ // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U
+ // .. .. reg_ddrc_t_rrd = 0x4
+ // .. .. ==> 0XF8006020[7:5] = 0x00000004U
+ // .. .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. .. reg_ddrc_refresh_margin = 0x2
+ // .. .. ==> 0XF8006020[11:8] = 0x00000002U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
+ // .. .. reg_ddrc_t_rp = 0x7
+ // .. .. ==> 0XF8006020[15:12] = 0x00000007U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U
+ // .. .. reg_ddrc_refresh_to_x32 = 0x8
+ // .. .. ==> 0XF8006020[20:16] = 0x00000008U
+ // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U
+ // .. .. reg_ddrc_sdram = 0x1
+ // .. .. ==> 0XF8006020[21:21] = 0x00000001U
+ // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U
+ // .. .. reg_ddrc_mobile = 0x0
+ // .. .. ==> 0XF8006020[22:22] = 0x00000000U
+ // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U
+ // .. .. reg_ddrc_clock_stop_en = 0x0
+ // .. .. ==> 0XF8006020[23:23] = 0x00000000U
+ // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U
+ // .. .. reg_ddrc_read_latency = 0x7
+ // .. .. ==> 0XF8006020[28:24] = 0x00000007U
+ // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U
+ // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
+ // .. .. ==> 0XF8006020[29:29] = 0x00000001U
+ // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U
+ // .. .. reg_ddrc_dis_pad_pd = 0x0
+ // .. .. ==> 0XF8006020[30:30] = 0x00000000U
+ // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_loopback = 0x0
+ // .. .. ==> 0XF8006020[31:31] = 0x00000000U
+ // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x27287290U),
+ // .. .. reg_ddrc_en_2t_timing_mode = 0x0
+ // .. .. ==> 0XF8006024[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_prefer_write = 0x0
+ // .. .. ==> 0XF8006024[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_ddrc_max_rank_rd = 0xf
+ // .. .. ==> 0XF8006024[5:2] = 0x0000000FU
+ // .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU
+ // .. .. reg_ddrc_mr_wr = 0x0
+ // .. .. ==> 0XF8006024[6:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr_addr = 0x0
+ // .. .. ==> 0XF8006024[8:7] = 0x00000000U
+ // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr_data = 0x0
+ // .. .. ==> 0XF8006024[24:9] = 0x00000000U
+ // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U
+ // .. .. ddrc_reg_mr_wr_busy = 0x0
+ // .. .. ==> 0XF8006024[25:25] = 0x00000000U
+ // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr_type = 0x0
+ // .. .. ==> 0XF8006024[26:26] = 0x00000000U
+ // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr_rdata_valid = 0x0
+ // .. .. ==> 0XF8006024[27:27] = 0x00000000U
+ // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU),
+ // .. .. reg_ddrc_final_wait_x32 = 0x7
+ // .. .. ==> 0XF8006028[6:0] = 0x00000007U
+ // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U
+ // .. .. reg_ddrc_pre_ocd_x32 = 0x0
+ // .. .. ==> 0XF8006028[10:7] = 0x00000000U
+ // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U
+ // .. .. reg_ddrc_t_mrd = 0x4
+ // .. .. ==> 0XF8006028[13:11] = 0x00000004U
+ // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
+ // .. .. reg_ddrc_emr2 = 0x8
+ // .. .. ==> 0XF800602C[15:0] = 0x00000008U
+ // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U
+ // .. .. reg_ddrc_emr3 = 0x0
+ // .. .. ==> 0XF800602C[31:16] = 0x00000000U
+ // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
+ // .. .. reg_ddrc_mr = 0x930
+ // .. .. ==> 0XF8006030[15:0] = 0x00000930U
+ // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U
+ // .. .. reg_ddrc_emr = 0x4
+ // .. .. ==> 0XF8006030[31:16] = 0x00000004U
+ // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
+ // .. .. reg_ddrc_burst_rdwr = 0x4
+ // .. .. ==> 0XF8006034[3:0] = 0x00000004U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U
+ // .. .. reg_ddrc_pre_cke_x1024 = 0x105
+ // .. .. ==> 0XF8006034[13:4] = 0x00000105U
+ // .. .. ==> MASK : 0x00003FF0U VAL : 0x00001050U
+ // .. .. reg_ddrc_post_cke_x1024 = 0x1
+ // .. .. ==> 0XF8006034[25:16] = 0x00000001U
+ // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U
+ // .. .. reg_ddrc_burstchop = 0x0
+ // .. .. ==> 0XF8006034[28:28] = 0x00000000U
+ // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U),
+ // .. .. reg_ddrc_force_low_pri_n = 0x0
+ // .. .. ==> 0XF8006038[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_dq = 0x0
+ // .. .. ==> 0XF8006038[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_debug_mode = 0x0
+ // .. .. ==> 0XF8006038[6:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U
+ // .. .. reg_phy_wr_level_start = 0x0
+ // .. .. ==> 0XF8006038[7:7] = 0x00000000U
+ // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. .. reg_phy_rd_level_start = 0x0
+ // .. .. ==> 0XF8006038[8:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. .. reg_phy_dq0_wait_t = 0x0
+ // .. .. ==> 0XF8006038[12:9] = 0x00000000U
+ // .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U),
+ // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
+ // .. .. ==> 0XF800603C[3:0] = 0x00000007U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U
+ // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
+ // .. .. ==> 0XF800603C[7:4] = 0x00000007U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U
+ // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
+ // .. .. ==> 0XF800603C[11:8] = 0x00000007U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U
+ // .. .. reg_ddrc_addrmap_col_b5 = 0x0
+ // .. .. ==> 0XF800603C[15:12] = 0x00000000U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b6 = 0x0
+ // .. .. ==> 0XF800603C[19:16] = 0x00000000U
+ // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
+ // .. .. reg_ddrc_addrmap_col_b2 = 0x0
+ // .. .. ==> 0XF8006040[3:0] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b3 = 0x0
+ // .. .. ==> 0XF8006040[7:4] = 0x00000000U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b4 = 0x0
+ // .. .. ==> 0XF8006040[11:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b7 = 0x0
+ // .. .. ==> 0XF8006040[15:12] = 0x00000000U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b8 = 0x0
+ // .. .. ==> 0XF8006040[19:16] = 0x00000000U
+ // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b9 = 0xf
+ // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
+ // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U
+ // .. .. reg_ddrc_addrmap_col_b10 = 0xf
+ // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
+ // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U
+ // .. .. reg_ddrc_addrmap_col_b11 = 0xf
+ // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
+ // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
+ // .. .. reg_ddrc_addrmap_row_b0 = 0x6
+ // .. .. ==> 0XF8006044[3:0] = 0x00000006U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U
+ // .. .. reg_ddrc_addrmap_row_b1 = 0x6
+ // .. .. ==> 0XF8006044[7:4] = 0x00000006U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U
+ // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
+ // .. .. ==> 0XF8006044[11:8] = 0x00000006U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U
+ // .. .. reg_ddrc_addrmap_row_b12 = 0x6
+ // .. .. ==> 0XF8006044[15:12] = 0x00000006U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U
+ // .. .. reg_ddrc_addrmap_row_b13 = 0x6
+ // .. .. ==> 0XF8006044[19:16] = 0x00000006U
+ // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U
+ // .. .. reg_ddrc_addrmap_row_b14 = 0x6
+ // .. .. ==> 0XF8006044[23:20] = 0x00000006U
+ // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U
+ // .. .. reg_ddrc_addrmap_row_b15 = 0xf
+ // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
+ // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U),
+ // .. .. reg_ddrc_rank0_rd_odt = 0x0
+ // .. .. ==> 0XF8006048[2:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U
+ // .. .. reg_ddrc_rank0_wr_odt = 0x1
+ // .. .. ==> 0XF8006048[5:3] = 0x00000001U
+ // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U
+ // .. .. reg_ddrc_rank1_rd_odt = 0x1
+ // .. .. ==> 0XF8006048[8:6] = 0x00000001U
+ // .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U
+ // .. .. reg_ddrc_rank1_wr_odt = 0x1
+ // .. .. ==> 0XF8006048[11:9] = 0x00000001U
+ // .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. .. reg_phy_rd_local_odt = 0x0
+ // .. .. ==> 0XF8006048[13:12] = 0x00000000U
+ // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U
+ // .. .. reg_phy_wr_local_odt = 0x3
+ // .. .. ==> 0XF8006048[15:14] = 0x00000003U
+ // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U
+ // .. .. reg_phy_idle_local_odt = 0x3
+ // .. .. ==> 0XF8006048[17:16] = 0x00000003U
+ // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U
+ // .. .. reg_ddrc_rank2_rd_odt = 0x0
+ // .. .. ==> 0XF8006048[20:18] = 0x00000000U
+ // .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U
+ // .. .. reg_ddrc_rank2_wr_odt = 0x0
+ // .. .. ==> 0XF8006048[23:21] = 0x00000000U
+ // .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U
+ // .. .. reg_ddrc_rank3_rd_odt = 0x0
+ // .. .. ==> 0XF8006048[26:24] = 0x00000000U
+ // .. .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_rank3_wr_odt = 0x0
+ // .. .. ==> 0XF8006048[29:27] = 0x00000000U
+ // .. .. ==> MASK : 0x38000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U),
+ // .. .. reg_phy_rd_cmd_to_data = 0x0
+ // .. .. ==> 0XF8006050[3:0] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
+ // .. .. reg_phy_wr_cmd_to_data = 0x0
+ // .. .. ==> 0XF8006050[7:4] = 0x00000000U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. .. reg_phy_rdc_we_to_re_delay = 0x8
+ // .. .. ==> 0XF8006050[11:8] = 0x00000008U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U
+ // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
+ // .. .. ==> 0XF8006050[15:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
+ // .. .. reg_phy_use_fixed_re = 0x1
+ // .. .. ==> 0XF8006050[16:16] = 0x00000001U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U
+ // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
+ // .. .. ==> 0XF8006050[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
+ // .. .. ==> 0XF8006050[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_phy_clk_stall_level = 0x0
+ // .. .. ==> 0XF8006050[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
+ // .. .. ==> 0XF8006050[27:24] = 0x00000007U
+ // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U
+ // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
+ // .. .. ==> 0XF8006050[31:28] = 0x00000007U
+ // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
+ // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1
+ // .. .. ==> 0XF8006058[7:0] = 0x00000001U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U
+ // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1
+ // .. .. ==> 0XF8006058[15:8] = 0x00000001U
+ // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U
+ // .. .. reg_ddrc_dis_dll_calib = 0x0
+ // .. .. ==> 0XF8006058[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U),
+ // .. .. reg_ddrc_rd_odt_delay = 0x3
+ // .. .. ==> 0XF800605C[3:0] = 0x00000003U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U
+ // .. .. reg_ddrc_wr_odt_delay = 0x0
+ // .. .. ==> 0XF800605C[7:4] = 0x00000000U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. .. reg_ddrc_rd_odt_hold = 0x0
+ // .. .. ==> 0XF800605C[11:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U
+ // .. .. reg_ddrc_wr_odt_hold = 0x5
+ // .. .. ==> 0XF800605C[15:12] = 0x00000005U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
+ // .. .. reg_ddrc_pageclose = 0x0
+ // .. .. ==> 0XF8006060[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_lpr_num_entries = 0x1f
+ // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
+ // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU
+ // .. .. reg_ddrc_auto_pre_en = 0x0
+ // .. .. ==> 0XF8006060[7:7] = 0x00000000U
+ // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. .. reg_ddrc_refresh_update_level = 0x0
+ // .. .. ==> 0XF8006060[8:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_wc = 0x0
+ // .. .. ==> 0XF8006060[9:9] = 0x00000000U
+ // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_collision_page_opt = 0x0
+ // .. .. ==> 0XF8006060[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_ddrc_selfref_en = 0x0
+ // .. .. ==> 0XF8006060[12:12] = 0x00000000U
+ // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
+ // .. .. reg_ddrc_go2critical_hysteresis = 0x0
+ // .. .. ==> 0XF8006064[12:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U
+ // .. .. reg_arb_go2critical_en = 0x1
+ // .. .. ==> 0XF8006064[17:17] = 0x00000001U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
+ // .. .. reg_ddrc_wrlvl_ww = 0x41
+ // .. .. ==> 0XF8006068[7:0] = 0x00000041U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U
+ // .. .. reg_ddrc_rdlvl_rr = 0x41
+ // .. .. ==> 0XF8006068[15:8] = 0x00000041U
+ // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U
+ // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
+ // .. .. ==> 0XF8006068[25:16] = 0x00000028U
+ // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
+ // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
+ // .. .. ==> 0XF800606C[7:0] = 0x00000010U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U
+ // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
+ // .. .. ==> 0XF800606C[15:8] = 0x00000016U
+ // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U
+ // .. ..
+ EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
+ // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1
+ // .. .. ==> 0XF8006078[3:0] = 0x00000001U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U
+ // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1
+ // .. .. ==> 0XF8006078[7:4] = 0x00000001U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U
+ // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1
+ // .. .. ==> 0XF8006078[11:8] = 0x00000001U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U
+ // .. .. reg_ddrc_t_cksre = 0x6
+ // .. .. ==> 0XF8006078[15:12] = 0x00000006U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U
+ // .. .. reg_ddrc_t_cksrx = 0x6
+ // .. .. ==> 0XF8006078[19:16] = 0x00000006U
+ // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U
+ // .. .. reg_ddrc_t_ckesr = 0x4
+ // .. .. ==> 0XF8006078[25:20] = 0x00000004U
+ // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U),
+ // .. .. reg_ddrc_t_ckpde = 0x2
+ // .. .. ==> 0XF800607C[3:0] = 0x00000002U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U
+ // .. .. reg_ddrc_t_ckpdx = 0x2
+ // .. .. ==> 0XF800607C[7:4] = 0x00000002U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
+ // .. .. reg_ddrc_t_ckdpde = 0x2
+ // .. .. ==> 0XF800607C[11:8] = 0x00000002U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
+ // .. .. reg_ddrc_t_ckdpdx = 0x2
+ // .. .. ==> 0XF800607C[15:12] = 0x00000002U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U
+ // .. .. reg_ddrc_t_ckcsx = 0x3
+ // .. .. ==> 0XF800607C[19:16] = 0x00000003U
+ // .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U),
+ // .. .. refresh_timer0_start_value_x32 = 0x0
+ // .. .. ==> 0XF80060A0[11:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U
+ // .. .. refresh_timer1_start_value_x32 = 0x8
+ // .. .. ==> 0XF80060A0[23:12] = 0x00000008U
+ // .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U),
+ // .. .. reg_ddrc_dis_auto_zq = 0x0
+ // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_ddr3 = 0x1
+ // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. .. reg_ddrc_t_mod = 0x200
+ // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
+ // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U
+ // .. .. reg_ddrc_t_zq_long_nop = 0x200
+ // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U
+ // .. .. reg_ddrc_t_zq_short_nop = 0x40
+ // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
+ // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
+ // .. .. t_zq_short_interval_x1024 = 0xcb73
+ // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U
+ // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U
+ // .. .. dram_rstn_x1024 = 0x69
+ // .. .. ==> 0XF80060A8[27:20] = 0x00000069U
+ // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
+ // .. .. deeppowerdown_en = 0x0
+ // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. deeppowerdown_to_x1024 = 0xff
+ // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
+ // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU
+ // .. ..
+ EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
+ // .. .. dfi_wrlvl_max_x1024 = 0xfff
+ // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
+ // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU
+ // .. .. dfi_rdlvl_max_x1024 = 0xfff
+ // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
+ // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U
+ // .. .. ddrc_reg_twrlvl_max_error = 0x0
+ // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
+ // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U
+ // .. .. ddrc_reg_trdlvl_max_error = 0x0
+ // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
+ // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dfi_wr_level_en = 0x1
+ // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
+ // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U
+ // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
+ // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
+ // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U
+ // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
+ // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
+ // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
+ // .. .. reg_ddrc_2t_delay = 0x0
+ // .. .. ==> 0XF80060B4[8:0] = 0x00000000U
+ // .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U
+ // .. .. reg_ddrc_skip_ocd = 0x1
+ // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
+ // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U
+ // .. .. reg_ddrc_dis_pre_bypass = 0x0
+ // .. .. ==> 0XF80060B4[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U),
+ // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
+ // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
+ // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U
+ // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
+ // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
+ // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U
+ // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
+ // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
+ // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
+ // .. .. START: RESET ECC ERROR
+ // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1
+ // .. .. ==> 0XF80060C4[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. Clear_Correctable_DRAM_ECC_error = 1
+ // .. .. ==> 0XF80060C4[1:1] = 0x00000001U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U),
+ // .. .. FINISH: RESET ECC ERROR
+ // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
+ // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
+ // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
+ // .. .. CORR_ECC_LOG_VALID = 0x0
+ // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. ECC_CORRECTED_BIT_NUM = 0x0
+ // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
+ // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
+ // .. .. UNCORR_ECC_LOG_VALID = 0x0
+ // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
+ // .. .. STAT_NUM_CORR_ERR = 0x0
+ // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
+ // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U
+ // .. .. STAT_NUM_UNCORR_ERR = 0x0
+ // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
+ // .. .. reg_ddrc_ecc_mode = 0x0
+ // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_scrub = 0x1
+ // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
+ // .. .. reg_phy_dif_on = 0x0
+ // .. .. ==> 0XF8006114[3:0] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
+ // .. .. reg_phy_dif_off = 0x0
+ // .. .. ==> 0XF8006114[7:4] = 0x00000000U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
+ // .. .. reg_phy_data_slice_in_use = 0x1
+ // .. .. ==> 0XF8006118[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_phy_rdlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006118[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006118[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_wrlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006118[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_tx = 0x0
+ // .. .. ==> 0XF8006118[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_rx = 0x0
+ // .. .. ==> 0XF8006118[5:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
+ // .. .. reg_phy_bist_shift_dq = 0x0
+ // .. .. ==> 0XF8006118[14:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
+ // .. .. reg_phy_bist_err_clr = 0x0
+ // .. .. ==> 0XF8006118[23:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
+ // .. .. reg_phy_dq_offset = 0x40
+ // .. .. ==> 0XF8006118[30:24] = 0x00000040U
+ // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U),
+ // .. .. reg_phy_data_slice_in_use = 0x1
+ // .. .. ==> 0XF800611C[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_phy_rdlvl_inc_mode = 0x0
+ // .. .. ==> 0XF800611C[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_inc_mode = 0x0
+ // .. .. ==> 0XF800611C[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_wrlvl_inc_mode = 0x0
+ // .. .. ==> 0XF800611C[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_tx = 0x0
+ // .. .. ==> 0XF800611C[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_rx = 0x0
+ // .. .. ==> 0XF800611C[5:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
+ // .. .. reg_phy_bist_shift_dq = 0x0
+ // .. .. ==> 0XF800611C[14:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
+ // .. .. reg_phy_bist_err_clr = 0x0
+ // .. .. ==> 0XF800611C[23:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
+ // .. .. reg_phy_dq_offset = 0x40
+ // .. .. ==> 0XF800611C[30:24] = 0x00000040U
+ // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U),
+ // .. .. reg_phy_data_slice_in_use = 0x1
+ // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_phy_rdlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_wrlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_tx = 0x0
+ // .. .. ==> 0XF8006120[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_rx = 0x0
+ // .. .. ==> 0XF8006120[5:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
+ // .. .. reg_phy_bist_shift_dq = 0x0
+ // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
+ // .. .. reg_phy_bist_err_clr = 0x0
+ // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
+ // .. .. reg_phy_dq_offset = 0x40
+ // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+ // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
+ // .. .. reg_phy_data_slice_in_use = 0x1
+ // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_phy_rdlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_wrlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_tx = 0x0
+ // .. .. ==> 0XF8006120[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_rx = 0x0
+ // .. .. ==> 0XF8006120[5:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
+ // .. .. reg_phy_bist_shift_dq = 0x0
+ // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
+ // .. .. reg_phy_bist_err_clr = 0x0
+ // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
+ // .. .. reg_phy_dq_offset = 0x40
+ // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+ // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U),
+ // .. .. reg_phy_data_slice_in_use = 0x1
+ // .. .. ==> 0XF8006124[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_phy_rdlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006124[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006124[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_wrlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006124[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_tx = 0x0
+ // .. .. ==> 0XF8006124[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_rx = 0x0
+ // .. .. ==> 0XF8006124[5:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
+ // .. .. reg_phy_bist_shift_dq = 0x0
+ // .. .. ==> 0XF8006124[14:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
+ // .. .. reg_phy_bist_err_clr = 0x0
+ // .. .. ==> 0XF8006124[23:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
+ // .. .. reg_phy_dq_offset = 0x40
+ // .. .. ==> 0XF8006124[30:24] = 0x00000040U
+ // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U),
+ // .. .. reg_phy_wrlvl_init_ratio = 0x1d
+ // .. .. ==> 0XF800612C[9:0] = 0x0000001DU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x0000001DU
+ // .. .. reg_phy_gatelvl_init_ratio = 0xf2
+ // .. .. ==> 0XF800612C[19:10] = 0x000000F2U
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x0003C800U
+ // .. ..
+ EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0003C81DU),
+ // .. .. reg_phy_wrlvl_init_ratio = 0x12
+ // .. .. ==> 0XF8006130[9:0] = 0x00000012U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000012U
+ // .. .. reg_phy_gatelvl_init_ratio = 0xd8
+ // .. .. ==> 0XF8006130[19:10] = 0x000000D8U
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x00036000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00036012U),
+ // .. .. reg_phy_wrlvl_init_ratio = 0xc
+ // .. .. ==> 0XF8006134[9:0] = 0x0000000CU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x0000000CU
+ // .. .. reg_phy_gatelvl_init_ratio = 0xde
+ // .. .. ==> 0XF8006134[19:10] = 0x000000DEU
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x00037800U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0003780CU),
+ // .. .. reg_phy_wrlvl_init_ratio = 0x21
+ // .. .. ==> 0XF8006138[9:0] = 0x00000021U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000021U
+ // .. .. reg_phy_gatelvl_init_ratio = 0xee
+ // .. .. ==> 0XF8006138[19:10] = 0x000000EEU
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x0003B800U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0003B821U),
+ // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+ // .. .. ==> 0XF8006140[9:0] = 0x00000035U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
+ // .. .. reg_phy_rd_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006140[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006140[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
+ // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+ // .. .. ==> 0XF8006144[9:0] = 0x00000035U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
+ // .. .. reg_phy_rd_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006144[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006144[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
+ // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+ // .. .. ==> 0XF8006148[9:0] = 0x00000035U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
+ // .. .. reg_phy_rd_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006148[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006148[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
+ // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+ // .. .. ==> 0XF800614C[9:0] = 0x00000035U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
+ // .. .. reg_phy_rd_dqs_slave_force = 0x0
+ // .. .. ==> 0XF800614C[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF800614C[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
+ // .. .. reg_phy_wr_dqs_slave_ratio = 0x9d
+ // .. .. ==> 0XF8006154[9:0] = 0x0000009DU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x0000009DU
+ // .. .. reg_phy_wr_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006154[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006154[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x0000009DU),
+ // .. .. reg_phy_wr_dqs_slave_ratio = 0x92
+ // .. .. ==> 0XF8006158[9:0] = 0x00000092U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000092U
+ // .. .. reg_phy_wr_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006158[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006158[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000092U),
+ // .. .. reg_phy_wr_dqs_slave_ratio = 0x8c
+ // .. .. ==> 0XF800615C[9:0] = 0x0000008CU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x0000008CU
+ // .. .. reg_phy_wr_dqs_slave_force = 0x0
+ // .. .. ==> 0XF800615C[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF800615C[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x0000008CU),
+ // .. .. reg_phy_wr_dqs_slave_ratio = 0xa1
+ // .. .. ==> 0XF8006160[9:0] = 0x000000A1U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000A1U
+ // .. .. reg_phy_wr_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006160[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006160[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x000000A1U),
+ // .. .. reg_phy_fifo_we_slave_ratio = 0x147
+ // .. .. ==> 0XF8006168[10:0] = 0x00000147U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000147U
+ // .. .. reg_phy_fifo_we_in_force = 0x0
+ // .. .. ==> 0XF8006168[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. reg_phy_fifo_we_in_delay = 0x0
+ // .. .. ==> 0XF8006168[20:12] = 0x00000000U
+ // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000147U),
+ // .. .. reg_phy_fifo_we_slave_ratio = 0x12d
+ // .. .. ==> 0XF800616C[10:0] = 0x0000012DU
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x0000012DU
+ // .. .. reg_phy_fifo_we_in_force = 0x0
+ // .. .. ==> 0XF800616C[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. reg_phy_fifo_we_in_delay = 0x0
+ // .. .. ==> 0XF800616C[20:12] = 0x00000000U
+ // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x0000012DU),
+ // .. .. reg_phy_fifo_we_slave_ratio = 0x133
+ // .. .. ==> 0XF8006170[10:0] = 0x00000133U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000133U
+ // .. .. reg_phy_fifo_we_in_force = 0x0
+ // .. .. ==> 0XF8006170[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. reg_phy_fifo_we_in_delay = 0x0
+ // .. .. ==> 0XF8006170[20:12] = 0x00000000U
+ // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000133U),
+ // .. .. reg_phy_fifo_we_slave_ratio = 0x143
+ // .. .. ==> 0XF8006174[10:0] = 0x00000143U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000143U
+ // .. .. reg_phy_fifo_we_in_force = 0x0
+ // .. .. ==> 0XF8006174[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. reg_phy_fifo_we_in_delay = 0x0
+ // .. .. ==> 0XF8006174[20:12] = 0x00000000U
+ // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000143U),
+ // .. .. reg_phy_wr_data_slave_ratio = 0xdd
+ // .. .. ==> 0XF800617C[9:0] = 0x000000DDU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000DDU
+ // .. .. reg_phy_wr_data_slave_force = 0x0
+ // .. .. ==> 0XF800617C[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_data_slave_delay = 0x0
+ // .. .. ==> 0XF800617C[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000DDU),
+ // .. .. reg_phy_wr_data_slave_ratio = 0xd2
+ // .. .. ==> 0XF8006180[9:0] = 0x000000D2U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000D2U
+ // .. .. reg_phy_wr_data_slave_force = 0x0
+ // .. .. ==> 0XF8006180[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_data_slave_delay = 0x0
+ // .. .. ==> 0XF8006180[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000D2U),
+ // .. .. reg_phy_wr_data_slave_ratio = 0xcc
+ // .. .. ==> 0XF8006184[9:0] = 0x000000CCU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000CCU
+ // .. .. reg_phy_wr_data_slave_force = 0x0
+ // .. .. ==> 0XF8006184[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_data_slave_delay = 0x0
+ // .. .. ==> 0XF8006184[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000CCU),
+ // .. .. reg_phy_wr_data_slave_ratio = 0xe1
+ // .. .. ==> 0XF8006188[9:0] = 0x000000E1U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000E1U
+ // .. .. reg_phy_wr_data_slave_force = 0x0
+ // .. .. ==> 0XF8006188[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_data_slave_delay = 0x0
+ // .. .. ==> 0XF8006188[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000E1U),
+ // .. .. reg_phy_loopback = 0x0
+ // .. .. ==> 0XF8006190[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_phy_bl2 = 0x0
+ // .. .. ==> 0XF8006190[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_at_spd_atpg = 0x0
+ // .. .. ==> 0XF8006190[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_bist_enable = 0x0
+ // .. .. ==> 0XF8006190[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_bist_force_err = 0x0
+ // .. .. ==> 0XF8006190[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reg_phy_bist_mode = 0x0
+ // .. .. ==> 0XF8006190[6:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U
+ // .. .. reg_phy_invert_clkout = 0x1
+ // .. .. ==> 0XF8006190[7:7] = 0x00000001U
+ // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0
+ // .. .. ==> 0XF8006190[8:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. .. reg_phy_sel_logic = 0x0
+ // .. .. ==> 0XF8006190[9:9] = 0x00000000U
+ // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U
+ // .. .. reg_phy_ctrl_slave_ratio = 0x100
+ // .. .. ==> 0XF8006190[19:10] = 0x00000100U
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U
+ // .. .. reg_phy_ctrl_slave_force = 0x0
+ // .. .. ==> 0XF8006190[20:20] = 0x00000000U
+ // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U
+ // .. .. reg_phy_ctrl_slave_delay = 0x0
+ // .. .. ==> 0XF8006190[27:21] = 0x00000000U
+ // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U
+ // .. .. reg_phy_use_rank0_delays = 0x1
+ // .. .. ==> 0XF8006190[28:28] = 0x00000001U
+ // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
+ // .. .. reg_phy_lpddr = 0x0
+ // .. .. ==> 0XF8006190[29:29] = 0x00000000U
+ // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U
+ // .. .. reg_phy_cmd_latency = 0x0
+ // .. .. ==> 0XF8006190[30:30] = 0x00000000U
+ // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U
+ // .. .. reg_phy_int_lpbk = 0x0
+ // .. .. ==> 0XF8006190[31:31] = 0x00000000U
+ // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U),
+ // .. .. reg_phy_wr_rl_delay = 0x2
+ // .. .. ==> 0XF8006194[4:0] = 0x00000002U
+ // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U
+ // .. .. reg_phy_rd_rl_delay = 0x4
+ // .. .. ==> 0XF8006194[9:5] = 0x00000004U
+ // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U
+ // .. .. reg_phy_dll_lock_diff = 0xf
+ // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
+ // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U
+ // .. .. reg_phy_use_wr_level = 0x1
+ // .. .. ==> 0XF8006194[14:14] = 0x00000001U
+ // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U
+ // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
+ // .. .. ==> 0XF8006194[15:15] = 0x00000001U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U
+ // .. .. reg_phy_use_rd_data_eye_level = 0x1
+ // .. .. ==> 0XF8006194[16:16] = 0x00000001U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U
+ // .. .. reg_phy_dis_calib_rst = 0x0
+ // .. .. ==> 0XF8006194[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_phy_ctrl_slave_delay = 0x0
+ // .. .. ==> 0XF8006194[19:18] = 0x00000000U
+ // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
+ // .. .. reg_arb_page_addr_mask = 0x0
+ // .. .. ==> 0XF8006204[31:0] = 0x00000000U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
+ // .. .. reg_arb_pri_wr_portn = 0x3ff
+ // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_wr_portn = 0x0
+ // .. .. ==> 0XF8006208[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+ // .. .. ==> 0XF8006208[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+ // .. .. ==> 0XF8006208[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_rmw_portn = 0x1
+ // .. .. ==> 0XF8006208[19:19] = 0x00000001U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU),
+ // .. .. reg_arb_pri_wr_portn = 0x3ff
+ // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_wr_portn = 0x0
+ // .. .. ==> 0XF800620C[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+ // .. .. ==> 0XF800620C[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+ // .. .. ==> 0XF800620C[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_rmw_portn = 0x1
+ // .. .. ==> 0XF800620C[19:19] = 0x00000001U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU),
+ // .. .. reg_arb_pri_wr_portn = 0x3ff
+ // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_wr_portn = 0x0
+ // .. .. ==> 0XF8006210[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+ // .. .. ==> 0XF8006210[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+ // .. .. ==> 0XF8006210[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_rmw_portn = 0x1
+ // .. .. ==> 0XF8006210[19:19] = 0x00000001U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU),
+ // .. .. reg_arb_pri_wr_portn = 0x3ff
+ // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_wr_portn = 0x0
+ // .. .. ==> 0XF8006214[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+ // .. .. ==> 0XF8006214[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+ // .. .. ==> 0XF8006214[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_rmw_portn = 0x1
+ // .. .. ==> 0XF8006214[19:19] = 0x00000001U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU),
+ // .. .. reg_arb_pri_rd_portn = 0x3ff
+ // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_rd_portn = 0x0
+ // .. .. ==> 0XF8006218[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+ // .. .. ==> 0XF8006218[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+ // .. .. ==> 0XF8006218[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_set_hpr_rd_portn = 0x0
+ // .. .. ==> 0XF8006218[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
+ // .. .. reg_arb_pri_rd_portn = 0x3ff
+ // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_rd_portn = 0x0
+ // .. .. ==> 0XF800621C[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+ // .. .. ==> 0XF800621C[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+ // .. .. ==> 0XF800621C[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_set_hpr_rd_portn = 0x0
+ // .. .. ==> 0XF800621C[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
+ // .. .. reg_arb_pri_rd_portn = 0x3ff
+ // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_rd_portn = 0x0
+ // .. .. ==> 0XF8006220[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+ // .. .. ==> 0XF8006220[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+ // .. .. ==> 0XF8006220[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_set_hpr_rd_portn = 0x0
+ // .. .. ==> 0XF8006220[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
+ // .. .. reg_arb_pri_rd_portn = 0x3ff
+ // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_rd_portn = 0x0
+ // .. .. ==> 0XF8006224[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+ // .. .. ==> 0XF8006224[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+ // .. .. ==> 0XF8006224[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_set_hpr_rd_portn = 0x0
+ // .. .. ==> 0XF8006224[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
+ // .. .. reg_ddrc_lpddr2 = 0x0
+ // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_per_bank_refresh = 0x0
+ // .. .. ==> 0XF80062A8[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_ddrc_derate_enable = 0x0
+ // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr4_margin = 0x0
+ // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U),
+ // .. .. reg_ddrc_mr4_read_interval = 0x0
+ // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
+ // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
+ // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U
+ // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
+ // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
+ // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U
+ // .. .. reg_ddrc_t_mrw = 0x5
+ // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
+ // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8
+ // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U
+ // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
+ // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
+ // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U
+ // .. ..
+ EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
+ // .. .. START: POLL ON DCI STATUS
+ // .. .. DONE = 1
+ // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
+ // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U
+ // .. ..
+ EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+ // .. .. FINISH: POLL ON DCI STATUS
+ // .. .. START: UNLOCK DDR
+ // .. .. reg_ddrc_soft_rstb = 0x1
+ // .. .. ==> 0XF8006000[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_ddrc_powerdown_en = 0x0
+ // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_ddrc_data_bus_width = 0x0
+ // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U
+ // .. .. reg_ddrc_burst8_refresh = 0x0
+ // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U
+ // .. .. reg_ddrc_rdwr_idle_gap = 1
+ // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+ // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U
+ // .. .. reg_ddrc_dis_rd_bypass = 0x0
+ // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+ // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_act_bypass = 0x0
+ // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_auto_refresh = 0x0
+ // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
+ // .. .. FINISH: UNLOCK DDR
+ // .. .. START: CHECK DDR STATUS
+ // .. .. ddrc_reg_operating_mode = 1
+ // .. .. ==> 0XF8006054[2:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U
+ // .. ..
+ EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+ // .. .. FINISH: CHECK DDR STATUS
+ // .. FINISH: DDR INITIALIZATION
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_mio_init_data_2_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: OCM REMAPPING
+ // .. VREF_EN = 0x1
+ // .. ==> 0XF8000B00[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. VREF_PULLUP_EN = 0x0
+ // .. ==> 0XF8000B00[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. CLK_PULLUP_EN = 0x0
+ // .. ==> 0XF8000B00[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. SRSTN_PULLUP_EN = 0x0
+ // .. ==> 0XF8000B00[9:9] = 0x00000000U
+ // .. ==> MASK : 0x00000200U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B00, 0x00000303U ,0x00000001U),
+ // .. FINISH: OCM REMAPPING
+ // .. START: DDRIOB SETTINGS
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B40[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x0
+ // .. ==> 0XF8000B40[2:1] = 0x00000000U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000000U
+ // .. DCI_UPDATE = 0x0
+ // .. ==> 0XF8000B40[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x0
+ // .. ==> 0XF8000B40[4:4] = 0x00000000U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. DCR_TYPE = 0x0
+ // .. ==> 0XF8000B40[6:5] = 0x00000000U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000000U
+ // .. IBUF_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B40[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B40[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B40[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B40[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B44[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x0
+ // .. ==> 0XF8000B44[2:1] = 0x00000000U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000000U
+ // .. DCI_UPDATE = 0x0
+ // .. ==> 0XF8000B44[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x0
+ // .. ==> 0XF8000B44[4:4] = 0x00000000U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. DCR_TYPE = 0x0
+ // .. ==> 0XF8000B44[6:5] = 0x00000000U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000000U
+ // .. IBUF_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B44[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B44[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B44[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B44[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B48[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x1
+ // .. ==> 0XF8000B48[2:1] = 0x00000001U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000002U
+ // .. DCI_UPDATE = 0x0
+ // .. ==> 0XF8000B48[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x1
+ // .. ==> 0XF8000B48[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. DCR_TYPE = 0x3
+ // .. ==> 0XF8000B48[6:5] = 0x00000003U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000060U
+ // .. IBUF_DISABLE_MODE = 0
+ // .. ==> 0XF8000B48[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0
+ // .. ==> 0XF8000B48[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B48[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B48[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B4C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x1
+ // .. ==> 0XF8000B4C[2:1] = 0x00000001U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000002U
+ // .. DCI_UPDATE = 0x0
+ // .. ==> 0XF8000B4C[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x1
+ // .. ==> 0XF8000B4C[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. DCR_TYPE = 0x3
+ // .. ==> 0XF8000B4C[6:5] = 0x00000003U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000060U
+ // .. IBUF_DISABLE_MODE = 0
+ // .. ==> 0XF8000B4C[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0
+ // .. ==> 0XF8000B4C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B4C[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B4C[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B50[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x2
+ // .. ==> 0XF8000B50[2:1] = 0x00000002U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000004U
+ // .. DCI_UPDATE = 0x0
+ // .. ==> 0XF8000B50[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x1
+ // .. ==> 0XF8000B50[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. DCR_TYPE = 0x3
+ // .. ==> 0XF8000B50[6:5] = 0x00000003U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000060U
+ // .. IBUF_DISABLE_MODE = 0
+ // .. ==> 0XF8000B50[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0
+ // .. ==> 0XF8000B50[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B50[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B50[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B54[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x2
+ // .. ==> 0XF8000B54[2:1] = 0x00000002U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000004U
+ // .. DCI_UPDATE = 0x0
+ // .. ==> 0XF8000B54[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x1
+ // .. ==> 0XF8000B54[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. DCR_TYPE = 0x3
+ // .. ==> 0XF8000B54[6:5] = 0x00000003U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000060U
+ // .. IBUF_DISABLE_MODE = 0
+ // .. ==> 0XF8000B54[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0
+ // .. ==> 0XF8000B54[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B54[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B54[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B58[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x0
+ // .. ==> 0XF8000B58[2:1] = 0x00000000U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000000U
+ // .. DCI_UPDATE = 0x0
+ // .. ==> 0XF8000B58[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x0
+ // .. ==> 0XF8000B58[4:4] = 0x00000000U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. DCR_TYPE = 0x0
+ // .. ==> 0XF8000B58[6:5] = 0x00000000U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000000U
+ // .. IBUF_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B58[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B58[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B58[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B58[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
+ // .. DRIVE_P = 0x1c
+ // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
+ // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
+ // .. DRIVE_N = 0xc
+ // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
+ // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
+ // .. SLEW_P = 0x3
+ // .. ==> 0XF8000B5C[18:14] = 0x00000003U
+ // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U
+ // .. SLEW_N = 0x3
+ // .. ==> 0XF8000B5C[23:19] = 0x00000003U
+ // .. ==> MASK : 0x00F80000U VAL : 0x00180000U
+ // .. GTL = 0x0
+ // .. ==> 0XF8000B5C[26:24] = 0x00000000U
+ // .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. RTERM = 0x0
+ // .. ==> 0XF8000B5C[31:27] = 0x00000000U
+ // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
+ // .. DRIVE_P = 0x1c
+ // .. ==> 0XF8000B60[6:0] = 0x0000001CU
+ // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
+ // .. DRIVE_N = 0xc
+ // .. ==> 0XF8000B60[13:7] = 0x0000000CU
+ // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
+ // .. SLEW_P = 0x6
+ // .. ==> 0XF8000B60[18:14] = 0x00000006U
+ // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
+ // .. SLEW_N = 0x1f
+ // .. ==> 0XF8000B60[23:19] = 0x0000001FU
+ // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
+ // .. GTL = 0x0
+ // .. ==> 0XF8000B60[26:24] = 0x00000000U
+ // .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. RTERM = 0x0
+ // .. ==> 0XF8000B60[31:27] = 0x00000000U
+ // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
+ // .. DRIVE_P = 0x1c
+ // .. ==> 0XF8000B64[6:0] = 0x0000001CU
+ // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
+ // .. DRIVE_N = 0xc
+ // .. ==> 0XF8000B64[13:7] = 0x0000000CU
+ // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
+ // .. SLEW_P = 0x6
+ // .. ==> 0XF8000B64[18:14] = 0x00000006U
+ // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
+ // .. SLEW_N = 0x1f
+ // .. ==> 0XF8000B64[23:19] = 0x0000001FU
+ // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
+ // .. GTL = 0x0
+ // .. ==> 0XF8000B64[26:24] = 0x00000000U
+ // .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. RTERM = 0x0
+ // .. ==> 0XF8000B64[31:27] = 0x00000000U
+ // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
+ // .. DRIVE_P = 0x1c
+ // .. ==> 0XF8000B68[6:0] = 0x0000001CU
+ // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
+ // .. DRIVE_N = 0xc
+ // .. ==> 0XF8000B68[13:7] = 0x0000000CU
+ // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
+ // .. SLEW_P = 0x6
+ // .. ==> 0XF8000B68[18:14] = 0x00000006U
+ // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
+ // .. SLEW_N = 0x1f
+ // .. ==> 0XF8000B68[23:19] = 0x0000001FU
+ // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
+ // .. GTL = 0x0
+ // .. ==> 0XF8000B68[26:24] = 0x00000000U
+ // .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. RTERM = 0x0
+ // .. ==> 0XF8000B68[31:27] = 0x00000000U
+ // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
+ // .. VREF_INT_EN = 0x1
+ // .. ==> 0XF8000B6C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. VREF_SEL = 0x4
+ // .. ==> 0XF8000B6C[4:1] = 0x00000004U
+ // .. ==> MASK : 0x0000001EU VAL : 0x00000008U
+ // .. VREF_EXT_EN = 0x0
+ // .. ==> 0XF8000B6C[6:5] = 0x00000000U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000000U
+ // .. VREF_PULLUP_EN = 0x0
+ // .. ==> 0XF8000B6C[8:7] = 0x00000000U
+ // .. ==> MASK : 0x00000180U VAL : 0x00000000U
+ // .. REFIO_EN = 0x1
+ // .. ==> 0XF8000B6C[9:9] = 0x00000001U
+ // .. ==> MASK : 0x00000200U VAL : 0x00000200U
+ // .. REFIO_TEST = 0x3
+ // .. ==> 0XF8000B6C[11:10] = 0x00000003U
+ // .. ==> MASK : 0x00000C00U VAL : 0x00000C00U
+ // .. REFIO_PULLUP_EN = 0x0
+ // .. ==> 0XF8000B6C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DRST_B_PULLUP_EN = 0x0
+ // .. ==> 0XF8000B6C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // .. CKE_PULLUP_EN = 0x0
+ // .. ==> 0XF8000B6C[14:14] = 0x00000000U
+ // .. ==> MASK : 0x00004000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000E09U),
+ // .. .. START: ASSERT RESET
+ // .. .. RESET = 1
+ // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. VRN_OUT = 0x1
+ // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U),
+ // .. .. FINISH: ASSERT RESET
+ // .. .. START: DEASSERT RESET
+ // .. .. RESET = 0
+ // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. VRN_OUT = 0x1
+ // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
+ // .. .. FINISH: DEASSERT RESET
+ // .. .. RESET = 0x1
+ // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ENABLE = 0x1
+ // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. .. VRP_TRI = 0x0
+ // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. VRN_TRI = 0x0
+ // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. VRP_OUT = 0x0
+ // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. VRN_OUT = 0x1
+ // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
+ // .. .. NREF_OPT1 = 0x0
+ // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
+ // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U
+ // .. .. NREF_OPT2 = 0x0
+ // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U
+ // .. .. NREF_OPT4 = 0x1
+ // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
+ // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U
+ // .. .. PREF_OPT1 = 0x0
+ // .. .. ==> 0XF8000B70[16:14] = 0x00000000U
+ // .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U
+ // .. .. PREF_OPT2 = 0x0
+ // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
+ // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U
+ // .. .. UPDATE_CONTROL = 0x0
+ // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
+ // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U
+ // .. .. INIT_COMPLETE = 0x0
+ // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
+ // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U
+ // .. .. TST_CLK = 0x0
+ // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
+ // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U
+ // .. .. TST_HLN = 0x0
+ // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
+ // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U
+ // .. .. TST_HLP = 0x0
+ // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
+ // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U
+ // .. .. TST_RST = 0x0
+ // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
+ // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
+ // .. .. INT_DCI_EN = 0x0
+ // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
+ // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U),
+ // .. FINISH: DDRIOB SETTINGS
+ // .. START: MIO PROGRAMMING
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000700[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. Speed = 0
+ // .. ==> 0XF8000700[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000700[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000700[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000700[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000700, 0x00003F01U ,0x00001201U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000704[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000704[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000704[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000704[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000704[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000704[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000704[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000704[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000704[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000708[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000708[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000708[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000708[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000708[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000708[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000708[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000708[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000708[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800070C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF800070C[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800070C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800070C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800070C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800070C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800070C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800070C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800070C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000710[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000710[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000710[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000710[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000710[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000710[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000710[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000710[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000710[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000714[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000714[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000714[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000714[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000714[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000714[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000714[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000714[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000714[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000718[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000718[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000718[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000718[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000718[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000718[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000718[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000718[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000718[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800071C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800071C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800071C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800071C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800071C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800071C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800071C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800071C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800071C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000200U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000720[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000720[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000720[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000720[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000720[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000720[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000720[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000720[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000720[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000724[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000724[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000724[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000724[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000724[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000724[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000724[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000724[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000724[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001200U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000728[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000728[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000728[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000728[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000728[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000728[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000728[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000728[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000728[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001200U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800072C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800072C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800072C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800072C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800072C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800072C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800072C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF800072C[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800072C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001200U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000730[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000730[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000730[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000730[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000730[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000730[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000730[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000730[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000730[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001200U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000734[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000734[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000734[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000734[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000734[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000734[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000734[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000734[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000734[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001200U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000738[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000738[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000738[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000738[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000738[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000738[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000738[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000738[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000738[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00001200U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF800073C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. Speed = 0
+ // .. ==> 0XF800073C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800073C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF800073C[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800073C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800073C, 0x00003F01U ,0x00001201U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000740[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000740[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000740[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000740[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000740[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000740[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 4
+ // .. ==> 0XF8000740[11:9] = 0x00000004U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000740[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 1
+ // .. ==> 0XF8000740[13:13] = 0x00000001U
+ // .. ==> MASK : 0x00002000U VAL : 0x00002000U
+ // ..
+ EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00002802U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000744[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000744[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000744[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000744[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000744[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000744[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 4
+ // .. ==> 0XF8000744[11:9] = 0x00000004U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000744[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 1
+ // .. ==> 0XF8000744[13:13] = 0x00000001U
+ // .. ==> MASK : 0x00002000U VAL : 0x00002000U
+ // ..
+ EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00002802U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000748[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000748[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000748[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000748[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000748[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000748[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 4
+ // .. ==> 0XF8000748[11:9] = 0x00000004U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000748[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 1
+ // .. ==> 0XF8000748[13:13] = 0x00000001U
+ // .. ==> MASK : 0x00002000U VAL : 0x00002000U
+ // ..
+ EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00002802U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800074C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF800074C[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800074C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800074C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800074C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800074C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 4
+ // .. ==> 0XF800074C[11:9] = 0x00000004U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
+ // .. PULLUP = 0
+ // .. ==> 0XF800074C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 1
+ // .. ==> 0XF800074C[13:13] = 0x00000001U
+ // .. ==> MASK : 0x00002000U VAL : 0x00002000U
+ // ..
+ EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00002802U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000750[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000750[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000750[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000750[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000750[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000750[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 4
+ // .. ==> 0XF8000750[11:9] = 0x00000004U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000750[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 1
+ // .. ==> 0XF8000750[13:13] = 0x00000001U
+ // .. ==> MASK : 0x00002000U VAL : 0x00002000U
+ // ..
+ EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00002802U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000754[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000754[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000754[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000754[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000754[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000754[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 4
+ // .. ==> 0XF8000754[11:9] = 0x00000004U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000754[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 1
+ // .. ==> 0XF8000754[13:13] = 0x00000001U
+ // .. ==> MASK : 0x00002000U VAL : 0x00002000U
+ // ..
+ EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00002802U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000758[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000758[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000758[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000758[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000758[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000758[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 4
+ // .. ==> 0XF8000758[11:9] = 0x00000004U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000758[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000758[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000803U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF800075C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF800075C[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800075C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800075C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800075C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800075C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 4
+ // .. ==> 0XF800075C[11:9] = 0x00000004U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
+ // .. PULLUP = 0
+ // .. ==> 0XF800075C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800075C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000803U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000760[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000760[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000760[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000760[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000760[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000760[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 4
+ // .. ==> 0XF8000760[11:9] = 0x00000004U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000760[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000760[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000803U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000764[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000764[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000764[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000764[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000764[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000764[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 4
+ // .. ==> 0XF8000764[11:9] = 0x00000004U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000764[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000764[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000803U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000768[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000768[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000768[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000768[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000768[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000768[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 4
+ // .. ==> 0XF8000768[11:9] = 0x00000004U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000768[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000768[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000803U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF800076C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF800076C[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800076C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800076C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800076C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800076C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 4
+ // .. ==> 0XF800076C[11:9] = 0x00000004U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
+ // .. PULLUP = 0
+ // .. ==> 0XF800076C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800076C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000803U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000770[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000770[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000770[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000770[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000770[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000770[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000770[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000770[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000770[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000774[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000774[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000774[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000774[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000774[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000774[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000774[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000774[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000774[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000778[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000778[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000778[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000778[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000778[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000778[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000778[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000778[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000778[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF800077C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800077C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF800077C[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800077C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800077C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800077C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800077C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800077C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800077C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000780[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000780[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000780[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000780[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000780[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000780[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000780[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000780[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000780[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000784[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000784[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000784[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000784[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000784[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000784[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000784[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000784[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000784[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000788[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000788[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000788[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000788[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000788[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000788[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000788[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000788[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000788[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800078C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800078C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF800078C[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800078C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800078C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800078C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800078C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800078C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800078C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000790[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000790[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000790[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000790[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000790[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000790[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000790[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000790[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000790[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000794[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000794[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000794[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000794[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000794[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000794[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000794[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000794[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000794[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000798[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000798[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000798[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000798[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000798[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000798[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000798[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000798[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000798[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800079C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800079C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF800079C[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800079C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800079C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800079C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800079C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800079C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800079C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007A0[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007A0[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007A0[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007A0[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007A0[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007A0[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007A0[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007A0[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007A0[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007A4[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007A4[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007A4[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007A4[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007A4[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007A4[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007A4[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007A4[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007A4[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007A8[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007A8[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007A8[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007A8[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007A8[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007A8[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007A8[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007A8[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007A8[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007AC[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007AC[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007AC[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007AC[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007AC[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007AC[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007AC[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007AC[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007AC[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007B0[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007B0[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007B0[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007B0[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007B0[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007B0[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007B0[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007B0[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007B0[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007B4[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007B4[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007B4[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007B4[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007B4[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007B4[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007B4[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007B4[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007B4[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000280U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF80007B8[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007B8[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007B8[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007B8[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 1
+ // .. ==> 0XF80007B8[7:5] = 0x00000001U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000020U
+ // .. Speed = 0
+ // .. ==> 0XF80007B8[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007B8[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF80007B8[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007B8[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001221U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007BC[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007BC[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007BC[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007BC[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 1
+ // .. ==> 0XF80007BC[7:5] = 0x00000001U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000020U
+ // .. Speed = 0
+ // .. ==> 0XF80007BC[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007BC[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF80007BC[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007BC[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00001220U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007C0[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007C0[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007C0[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007C0[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 7
+ // .. ==> 0XF80007C0[7:5] = 0x00000007U
+ // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U
+ // .. Speed = 0
+ // .. ==> 0XF80007C0[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007C0[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007C0[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007C0[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF80007C4[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007C4[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007C4[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007C4[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 7
+ // .. ==> 0XF80007C4[7:5] = 0x00000007U
+ // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U
+ // .. Speed = 0
+ // .. ==> 0XF80007C4[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007C4[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007C4[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007C4[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007C8[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007C8[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007C8[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007C8[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 2
+ // .. ==> 0XF80007C8[7:5] = 0x00000002U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000040U
+ // .. Speed = 0
+ // .. ==> 0XF80007C8[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007C8[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF80007C8[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007C8[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001240U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007CC[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007CC[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007CC[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007CC[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 2
+ // .. ==> 0XF80007CC[7:5] = 0x00000002U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000040U
+ // .. Speed = 0
+ // .. ==> 0XF80007CC[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007CC[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF80007CC[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007CC[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001240U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007D0[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007D0[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007D0[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007D0[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007D0[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007D0[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007D0[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007D0[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007D0[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007D4[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007D4[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007D4[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007D4[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007D4[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007D4[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007D4[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007D4[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007D4[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U),
+ // .. SDIO0_WP_SEL = 15
+ // .. ==> 0XF8000830[5:0] = 0x0000000FU
+ // .. ==> MASK : 0x0000003FU VAL : 0x0000000FU
+ // .. SDIO0_CD_SEL = 0
+ // .. ==> 0XF8000830[21:16] = 0x00000000U
+ // .. ==> MASK : 0x003F0000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x0000000FU),
+ // .. FINISH: MIO PROGRAMMING
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_peripherals_init_data_2_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+ // .. IBUF_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B48[7:7] = 0x00000001U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. TERM_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B48[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // ..
+ EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
+ // .. IBUF_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B4C[7:7] = 0x00000001U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. TERM_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B4C[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // ..
+ EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
+ // .. IBUF_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B50[7:7] = 0x00000001U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. TERM_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B50[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // ..
+ EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
+ // .. IBUF_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B54[7:7] = 0x00000001U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. TERM_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B54[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // ..
+ EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
+ // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // .. START: SRAM/NOR SET OPMODE
+ // .. FINISH: SRAM/NOR SET OPMODE
+ // .. START: UART REGISTERS
+ // .. BDIV = 0x6
+ // .. ==> 0XE0001034[7:0] = 0x00000006U
+ // .. ==> MASK : 0x000000FFU VAL : 0x00000006U
+ // ..
+ EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
+ // .. CD = 0x3e
+ // .. ==> 0XE0001018[15:0] = 0x0000003EU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU
+ // ..
+ EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
+ // .. STPBRK = 0x0
+ // .. ==> 0XE0001000[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. STTBRK = 0x0
+ // .. ==> 0XE0001000[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. RSTTO = 0x0
+ // .. ==> 0XE0001000[6:6] = 0x00000000U
+ // .. ==> MASK : 0x00000040U VAL : 0x00000000U
+ // .. TXDIS = 0x0
+ // .. ==> 0XE0001000[5:5] = 0x00000000U
+ // .. ==> MASK : 0x00000020U VAL : 0x00000000U
+ // .. TXEN = 0x1
+ // .. ==> 0XE0001000[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. RXDIS = 0x0
+ // .. ==> 0XE0001000[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. RXEN = 0x1
+ // .. ==> 0XE0001000[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. TXRES = 0x1
+ // .. ==> 0XE0001000[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. RXRES = 0x1
+ // .. ==> 0XE0001000[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // ..
+ EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
+ // .. IRMODE = 0x0
+ // .. ==> 0XE0001004[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. UCLKEN = 0x0
+ // .. ==> 0XE0001004[10:10] = 0x00000000U
+ // .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. CHMODE = 0x0
+ // .. ==> 0XE0001004[9:8] = 0x00000000U
+ // .. ==> MASK : 0x00000300U VAL : 0x00000000U
+ // .. NBSTOP = 0x0
+ // .. ==> 0XE0001004[7:6] = 0x00000000U
+ // .. ==> MASK : 0x000000C0U VAL : 0x00000000U
+ // .. PAR = 0x4
+ // .. ==> 0XE0001004[5:3] = 0x00000004U
+ // .. ==> MASK : 0x00000038U VAL : 0x00000020U
+ // .. CHRL = 0x0
+ // .. ==> 0XE0001004[2:1] = 0x00000000U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000000U
+ // .. CLKS = 0x0
+ // .. ==> 0XE0001004[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U),
+ // .. FINISH: UART REGISTERS
+ // .. START: QSPI REGISTERS
+ // .. Holdb_dr = 1
+ // .. ==> 0XE000D000[19:19] = 0x00000001U
+ // .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // ..
+ EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
+ // .. FINISH: QSPI REGISTERS
+ // .. START: PL POWER ON RESET REGISTERS
+ // .. PCFG_POR_CNT_4K = 0
+ // .. ==> 0XF8007000[29:29] = 0x00000000U
+ // .. ==> MASK : 0x20000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
+ // .. FINISH: PL POWER ON RESET REGISTERS
+ // .. START: SMC TIMING CALCULATION REGISTER UPDATE
+ // .. .. START: NAND SET CYCLE
+ // .. .. FINISH: NAND SET CYCLE
+ // .. .. START: OPMODE
+ // .. .. FINISH: OPMODE
+ // .. .. START: DIRECT COMMAND
+ // .. .. FINISH: DIRECT COMMAND
+ // .. .. START: SRAM/NOR CS0 SET CYCLE
+ // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
+ // .. .. START: DIRECT COMMAND
+ // .. .. FINISH: DIRECT COMMAND
+ // .. .. START: NOR CS0 BASE ADDRESS
+ // .. .. FINISH: NOR CS0 BASE ADDRESS
+ // .. .. START: SRAM/NOR CS1 SET CYCLE
+ // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
+ // .. .. START: DIRECT COMMAND
+ // .. .. FINISH: DIRECT COMMAND
+ // .. .. START: NOR CS1 BASE ADDRESS
+ // .. .. FINISH: NOR CS1 BASE ADDRESS
+ // .. .. START: USB RESET
+ // .. .. .. START: USB0 RESET
+ // .. .. .. .. START: DIR MODE BANK 0
+ // .. .. .. .. DIRECTION_0 = 0x80
+ // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U
+ // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U),
+ // .. .. .. .. FINISH: DIR MODE BANK 0
+ // .. .. .. .. START: DIR MODE BANK 1
+ // .. .. .. .. FINISH: DIR MODE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. MASK_0_LSW = 0xff7f
+ // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+ // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U
+ // .. .. .. .. DATA_0_LSW = 0x80
+ // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+ // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. START: OUTPUT ENABLE BANK 0
+ // .. .. .. .. OP_ENABLE_0 = 0x80
+ // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U
+ // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U),
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+ // .. .. .. .. START: OUTPUT ENABLE BANK 1
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. MASK_0_LSW = 0xff7f
+ // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+ // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U
+ // .. .. .. .. DATA_0_LSW = 0x0
+ // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+ // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U),
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. START: ADD 1 MS DELAY
+ // .. .. .. ..
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ // .. .. .. .. FINISH: ADD 1 MS DELAY
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. MASK_0_LSW = 0xff7f
+ // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+ // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U
+ // .. .. .. .. DATA_0_LSW = 0x80
+ // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+ // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. FINISH: USB0 RESET
+ // .. .. .. START: USB1 RESET
+ // .. .. .. .. START: DIR MODE BANK 0
+ // .. .. .. .. FINISH: DIR MODE BANK 0
+ // .. .. .. .. START: DIR MODE BANK 1
+ // .. .. .. .. FINISH: DIR MODE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. START: OUTPUT ENABLE BANK 0
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+ // .. .. .. .. START: OUTPUT ENABLE BANK 1
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. START: ADD 1 MS DELAY
+ // .. .. .. ..
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ // .. .. .. .. FINISH: ADD 1 MS DELAY
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. FINISH: USB1 RESET
+ // .. .. FINISH: USB RESET
+ // .. .. START: ENET RESET
+ // .. .. .. START: ENET0 RESET
+ // .. .. .. .. START: DIR MODE BANK 0
+ // .. .. .. .. DIRECTION_0 = 0x800
+ // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000800U
+ // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000800U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000800U),
+ // .. .. .. .. FINISH: DIR MODE BANK 0
+ // .. .. .. .. START: DIR MODE BANK 1
+ // .. .. .. .. FINISH: DIR MODE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. MASK_0_LSW = 0xf7ff
+ // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU
+ // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xF7FF0000U
+ // .. .. .. .. DATA_0_LSW = 0x800
+ // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000800U
+ // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000800U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0800U),
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. START: OUTPUT ENABLE BANK 0
+ // .. .. .. .. OP_ENABLE_0 = 0x800
+ // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000800U
+ // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000800U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000800U),
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+ // .. .. .. .. START: OUTPUT ENABLE BANK 1
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. MASK_0_LSW = 0xf7ff
+ // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU
+ // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xF7FF0000U
+ // .. .. .. .. DATA_0_LSW = 0x0
+ // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+ // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0000U),
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. START: ADD 1 MS DELAY
+ // .. .. .. ..
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ // .. .. .. .. FINISH: ADD 1 MS DELAY
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. MASK_0_LSW = 0xf7ff
+ // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU
+ // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xF7FF0000U
+ // .. .. .. .. DATA_0_LSW = 0x800
+ // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000800U
+ // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000800U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0800U),
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. FINISH: ENET0 RESET
+ // .. .. .. START: ENET1 RESET
+ // .. .. .. .. START: DIR MODE BANK 0
+ // .. .. .. .. FINISH: DIR MODE BANK 0
+ // .. .. .. .. START: DIR MODE BANK 1
+ // .. .. .. .. FINISH: DIR MODE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. START: OUTPUT ENABLE BANK 0
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+ // .. .. .. .. START: OUTPUT ENABLE BANK 1
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. START: ADD 1 MS DELAY
+ // .. .. .. ..
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ // .. .. .. .. FINISH: ADD 1 MS DELAY
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. FINISH: ENET1 RESET
+ // .. .. FINISH: ENET RESET
+ // .. .. START: I2C RESET
+ // .. .. .. START: I2C0 RESET
+ // .. .. .. .. START: DIR MODE GPIO BANK0
+ // .. .. .. .. DIRECTION_0 = 0x2000
+ // .. .. .. .. ==> 0XE000A204[31:0] = 0x00002000U
+ // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002000U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002000U),
+ // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+ // .. .. .. .. START: DIR MODE GPIO BANK1
+ // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. MASK_0_LSW = 0xdfff
+ // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU
+ // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xDFFF0000U
+ // .. .. .. .. DATA_0_LSW = 0x2000
+ // .. .. .. .. ==> 0XE000A000[15:0] = 0x00002000U
+ // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00002000U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF2000U),
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. START: OUTPUT ENABLE
+ // .. .. .. .. OP_ENABLE_0 = 0x2000
+ // .. .. .. .. ==> 0XE000A208[31:0] = 0x00002000U
+ // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002000U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002000U),
+ // .. .. .. .. FINISH: OUTPUT ENABLE
+ // .. .. .. .. START: OUTPUT ENABLE
+ // .. .. .. .. FINISH: OUTPUT ENABLE
+ // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. MASK_0_LSW = 0xdfff
+ // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU
+ // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xDFFF0000U
+ // .. .. .. .. DATA_0_LSW = 0x0
+ // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+ // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF0000U),
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. START: ADD 1 MS DELAY
+ // .. .. .. ..
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ // .. .. .. .. FINISH: ADD 1 MS DELAY
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. MASK_0_LSW = 0xdfff
+ // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU
+ // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xDFFF0000U
+ // .. .. .. .. DATA_0_LSW = 0x2000
+ // .. .. .. .. ==> 0XE000A000[15:0] = 0x00002000U
+ // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00002000U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF2000U),
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. FINISH: I2C0 RESET
+ // .. .. .. START: I2C1 RESET
+ // .. .. .. .. START: DIR MODE GPIO BANK0
+ // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+ // .. .. .. .. START: DIR MODE GPIO BANK1
+ // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. START: OUTPUT ENABLE
+ // .. .. .. .. FINISH: OUTPUT ENABLE
+ // .. .. .. .. START: OUTPUT ENABLE
+ // .. .. .. .. FINISH: OUTPUT ENABLE
+ // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. START: ADD 1 MS DELAY
+ // .. .. .. ..
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ // .. .. .. .. FINISH: ADD 1 MS DELAY
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. FINISH: I2C1 RESET
+ // .. .. FINISH: I2C RESET
+ // .. .. START: NOR CHIP SELECT
+ // .. .. .. START: DIR MODE BANK 0
+ // .. .. .. FINISH: DIR MODE BANK 0
+ // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. START: OUTPUT ENABLE BANK 0
+ // .. .. .. FINISH: OUTPUT ENABLE BANK 0
+ // .. .. FINISH: NOR CHIP SELECT
+ // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_post_config_2_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: ENABLING LEVEL SHIFTER
+ // .. USER_INP_ICT_EN_0 = 3
+ // .. ==> 0XF8000900[1:0] = 0x00000003U
+ // .. ==> MASK : 0x00000003U VAL : 0x00000003U
+ // .. USER_INP_ICT_EN_1 = 3
+ // .. ==> 0XF8000900[3:2] = 0x00000003U
+ // .. ==> MASK : 0x0000000CU VAL : 0x0000000CU
+ // ..
+ EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
+ // .. FINISH: ENABLING LEVEL SHIFTER
+ // .. START: FPGA RESETS TO 0
+ // .. reserved_3 = 0
+ // .. ==> 0XF8000240[31:25] = 0x00000000U
+ // .. ==> MASK : 0xFE000000U VAL : 0x00000000U
+ // .. FPGA_ACP_RST = 0
+ // .. ==> 0XF8000240[24:24] = 0x00000000U
+ // .. ==> MASK : 0x01000000U VAL : 0x00000000U
+ // .. FPGA_AXDS3_RST = 0
+ // .. ==> 0XF8000240[23:23] = 0x00000000U
+ // .. ==> MASK : 0x00800000U VAL : 0x00000000U
+ // .. FPGA_AXDS2_RST = 0
+ // .. ==> 0XF8000240[22:22] = 0x00000000U
+ // .. ==> MASK : 0x00400000U VAL : 0x00000000U
+ // .. FPGA_AXDS1_RST = 0
+ // .. ==> 0XF8000240[21:21] = 0x00000000U
+ // .. ==> MASK : 0x00200000U VAL : 0x00000000U
+ // .. FPGA_AXDS0_RST = 0
+ // .. ==> 0XF8000240[20:20] = 0x00000000U
+ // .. ==> MASK : 0x00100000U VAL : 0x00000000U
+ // .. reserved_2 = 0
+ // .. ==> 0XF8000240[19:18] = 0x00000000U
+ // .. ==> MASK : 0x000C0000U VAL : 0x00000000U
+ // .. FSSW1_FPGA_RST = 0
+ // .. ==> 0XF8000240[17:17] = 0x00000000U
+ // .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. FSSW0_FPGA_RST = 0
+ // .. ==> 0XF8000240[16:16] = 0x00000000U
+ // .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. reserved_1 = 0
+ // .. ==> 0XF8000240[15:14] = 0x00000000U
+ // .. ==> MASK : 0x0000C000U VAL : 0x00000000U
+ // .. FPGA_FMSW1_RST = 0
+ // .. ==> 0XF8000240[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // .. FPGA_FMSW0_RST = 0
+ // .. ==> 0XF8000240[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. FPGA_DMA3_RST = 0
+ // .. ==> 0XF8000240[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. FPGA_DMA2_RST = 0
+ // .. ==> 0XF8000240[10:10] = 0x00000000U
+ // .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. FPGA_DMA1_RST = 0
+ // .. ==> 0XF8000240[9:9] = 0x00000000U
+ // .. ==> MASK : 0x00000200U VAL : 0x00000000U
+ // .. FPGA_DMA0_RST = 0
+ // .. ==> 0XF8000240[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. reserved = 0
+ // .. ==> 0XF8000240[7:4] = 0x00000000U
+ // .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. FPGA3_OUT_RST = 0
+ // .. ==> 0XF8000240[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. FPGA2_OUT_RST = 0
+ // .. ==> 0XF8000240[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. FPGA1_OUT_RST = 0
+ // .. ==> 0XF8000240[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. FPGA0_OUT_RST = 0
+ // .. ==> 0XF8000240[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
+ // .. FINISH: FPGA RESETS TO 0
+ // .. START: AFI REGISTERS
+ // .. .. START: AFI0 REGISTERS
+ // .. .. FINISH: AFI0 REGISTERS
+ // .. .. START: AFI1 REGISTERS
+ // .. .. FINISH: AFI1 REGISTERS
+ // .. .. START: AFI2 REGISTERS
+ // .. .. FINISH: AFI2 REGISTERS
+ // .. .. START: AFI3 REGISTERS
+ // .. .. FINISH: AFI3 REGISTERS
+ // .. FINISH: AFI REGISTERS
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_debug_2_0[] = {
+ // START: top
+ // .. START: CROSS TRIGGER CONFIGURATIONS
+ // .. .. START: UNLOCKING CTI REGISTERS
+ // .. .. KEY = 0XC5ACCE55
+ // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
+ // .. ..
+ EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
+ // .. .. KEY = 0XC5ACCE55
+ // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
+ // .. ..
+ EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
+ // .. .. KEY = 0XC5ACCE55
+ // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
+ // .. ..
+ EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
+ // .. .. FINISH: UNLOCKING CTI REGISTERS
+ // .. .. START: ENABLING CTI MODULES AND CHANNELS
+ // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
+ // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+ // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+ // .. FINISH: CROSS TRIGGER CONFIGURATIONS
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_pll_init_data_1_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: PLL SLCR REGISTERS
+ // .. .. START: ARM PLL INIT
+ // .. .. PLL_RES = 0x2
+ // .. .. ==> 0XF8000110[7:4] = 0x00000002U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
+ // .. .. PLL_CP = 0x2
+ // .. .. ==> 0XF8000110[11:8] = 0x00000002U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
+ // .. .. LOCK_CNT = 0xfa
+ // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
+ // .. .. .. START: UPDATE FB_DIV
+ // .. .. .. PLL_FDIV = 0x28
+ // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
+ // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
+ // .. .. .. FINISH: UPDATE FB_DIV
+ // .. .. .. START: BY PASS PLL
+ // .. .. .. PLL_BYPASS_FORCE = 1
+ // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
+ // .. .. .. FINISH: BY PASS PLL
+ // .. .. .. START: ASSERT RESET
+ // .. .. .. PLL_RESET = 1
+ // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
+ // .. .. .. FINISH: ASSERT RESET
+ // .. .. .. START: DEASSERT RESET
+ // .. .. .. PLL_RESET = 0
+ // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
+ // .. .. .. FINISH: DEASSERT RESET
+ // .. .. .. START: CHECK PLL STATUS
+ // .. .. .. ARM_PLL_LOCK = 1
+ // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ..
+ EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+ // .. .. .. FINISH: CHECK PLL STATUS
+ // .. .. .. START: REMOVE PLL BY PASS
+ // .. .. .. PLL_BYPASS_FORCE = 0
+ // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
+ // .. .. .. FINISH: REMOVE PLL BY PASS
+ // .. .. .. SRCSEL = 0x0
+ // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. .. .. DIVISOR = 0x2
+ // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
+ // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U
+ // .. .. .. CPU_6OR4XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
+ // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U
+ // .. .. .. CPU_3OR2XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
+ // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U
+ // .. .. .. CPU_2XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
+ // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U
+ // .. .. .. CPU_1XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
+ // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U
+ // .. .. .. CPU_PERI_CLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
+ // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
+ // .. .. FINISH: ARM PLL INIT
+ // .. .. START: DDR PLL INIT
+ // .. .. PLL_RES = 0x2
+ // .. .. ==> 0XF8000114[7:4] = 0x00000002U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
+ // .. .. PLL_CP = 0x2
+ // .. .. ==> 0XF8000114[11:8] = 0x00000002U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
+ // .. .. LOCK_CNT = 0x12c
+ // .. .. ==> 0XF8000114[21:12] = 0x0000012CU
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
+ // .. .. .. START: UPDATE FB_DIV
+ // .. .. .. PLL_FDIV = 0x20
+ // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
+ // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
+ // .. .. .. FINISH: UPDATE FB_DIV
+ // .. .. .. START: BY PASS PLL
+ // .. .. .. PLL_BYPASS_FORCE = 1
+ // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
+ // .. .. .. FINISH: BY PASS PLL
+ // .. .. .. START: ASSERT RESET
+ // .. .. .. PLL_RESET = 1
+ // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
+ // .. .. .. FINISH: ASSERT RESET
+ // .. .. .. START: DEASSERT RESET
+ // .. .. .. PLL_RESET = 0
+ // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
+ // .. .. .. FINISH: DEASSERT RESET
+ // .. .. .. START: CHECK PLL STATUS
+ // .. .. .. DDR_PLL_LOCK = 1
+ // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. .. ..
+ EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+ // .. .. .. FINISH: CHECK PLL STATUS
+ // .. .. .. START: REMOVE PLL BY PASS
+ // .. .. .. PLL_BYPASS_FORCE = 0
+ // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
+ // .. .. .. FINISH: REMOVE PLL BY PASS
+ // .. .. .. DDR_3XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. .. DDR_2XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. .. .. DDR_3XCLK_DIVISOR = 0x2
+ // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
+ // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U
+ // .. .. .. DDR_2XCLK_DIVISOR = 0x3
+ // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
+ // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
+ // .. .. FINISH: DDR PLL INIT
+ // .. .. START: IO PLL INIT
+ // .. .. PLL_RES = 0xc
+ // .. .. ==> 0XF8000118[7:4] = 0x0000000CU
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U
+ // .. .. PLL_CP = 0x2
+ // .. .. ==> 0XF8000118[11:8] = 0x00000002U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
+ // .. .. LOCK_CNT = 0x145
+ // .. .. ==> 0XF8000118[21:12] = 0x00000145U
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U),
+ // .. .. .. START: UPDATE FB_DIV
+ // .. .. .. PLL_FDIV = 0x1e
+ // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU
+ // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U),
+ // .. .. .. FINISH: UPDATE FB_DIV
+ // .. .. .. START: BY PASS PLL
+ // .. .. .. PLL_BYPASS_FORCE = 1
+ // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
+ // .. .. .. FINISH: BY PASS PLL
+ // .. .. .. START: ASSERT RESET
+ // .. .. .. PLL_RESET = 1
+ // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
+ // .. .. .. FINISH: ASSERT RESET
+ // .. .. .. START: DEASSERT RESET
+ // .. .. .. PLL_RESET = 0
+ // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
+ // .. .. .. FINISH: DEASSERT RESET
+ // .. .. .. START: CHECK PLL STATUS
+ // .. .. .. IO_PLL_LOCK = 1
+ // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. .. ..
+ EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+ // .. .. .. FINISH: CHECK PLL STATUS
+ // .. .. .. START: REMOVE PLL BY PASS
+ // .. .. .. PLL_BYPASS_FORCE = 0
+ // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
+ // .. .. .. FINISH: REMOVE PLL BY PASS
+ // .. .. FINISH: IO PLL INIT
+ // .. FINISH: PLL SLCR REGISTERS
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_clock_init_data_1_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: CLOCK CONTROL SLCR REGISTERS
+ // .. CLKACT = 0x1
+ // .. ==> 0XF8000128[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. DIVISOR0 = 0x23
+ // .. ==> 0XF8000128[13:8] = 0x00000023U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00002300U
+ // .. DIVISOR1 = 0x3
+ // .. ==> 0XF8000128[25:20] = 0x00000003U
+ // .. ==> MASK : 0x03F00000U VAL : 0x00300000U
+ // ..
+ EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U),
+ // .. CLKACT = 0x1
+ // .. ==> 0XF8000138[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000138[4:4] = 0x00000000U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
+ // .. CLKACT = 0x1
+ // .. ==> 0XF8000140[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000140[6:4] = 0x00000000U
+ // .. ==> MASK : 0x00000070U VAL : 0x00000000U
+ // .. DIVISOR = 0x8
+ // .. ==> 0XF8000140[13:8] = 0x00000008U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00000800U
+ // .. DIVISOR1 = 0x5
+ // .. ==> 0XF8000140[25:20] = 0x00000005U
+ // .. ==> MASK : 0x03F00000U VAL : 0x00500000U
+ // ..
+ EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00500801U),
+ // .. CLKACT = 0x1
+ // .. ==> 0XF800014C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF800014C[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR = 0x5
+ // .. ==> 0XF800014C[13:8] = 0x00000005U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00000500U
+ // ..
+ EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
+ // .. CLKACT0 = 0x1
+ // .. ==> 0XF8000150[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. CLKACT1 = 0x0
+ // .. ==> 0XF8000150[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000150[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR = 0x14
+ // .. ==> 0XF8000150[13:8] = 0x00000014U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
+ // ..
+ EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U),
+ // .. CLKACT0 = 0x0
+ // .. ==> 0XF8000154[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. CLKACT1 = 0x1
+ // .. ==> 0XF8000154[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000154[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR = 0x14
+ // .. ==> 0XF8000154[13:8] = 0x00000014U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
+ // ..
+ EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U),
+ // .. CLKACT0 = 0x1
+ // .. ==> 0XF800015C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. CLKACT1 = 0x0
+ // .. ==> 0XF800015C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF800015C[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR0 = 0xe
+ // .. ==> 0XF800015C[13:8] = 0x0000000EU
+ // .. ==> MASK : 0x00003F00U VAL : 0x00000E00U
+ // .. DIVISOR1 = 0x3
+ // .. ==> 0XF800015C[25:20] = 0x00000003U
+ // .. ==> MASK : 0x03F00000U VAL : 0x00300000U
+ // ..
+ EMIT_MASKWRITE(0XF800015C, 0x03F03F33U ,0x00300E01U),
+ // .. CAN0_MUX = 0x0
+ // .. ==> 0XF8000160[5:0] = 0x00000000U
+ // .. ==> MASK : 0x0000003FU VAL : 0x00000000U
+ // .. CAN0_REF_SEL = 0x0
+ // .. ==> 0XF8000160[6:6] = 0x00000000U
+ // .. ==> MASK : 0x00000040U VAL : 0x00000000U
+ // .. CAN1_MUX = 0x0
+ // .. ==> 0XF8000160[21:16] = 0x00000000U
+ // .. ==> MASK : 0x003F0000U VAL : 0x00000000U
+ // .. CAN1_REF_SEL = 0x0
+ // .. ==> 0XF8000160[22:22] = 0x00000000U
+ // .. ==> MASK : 0x00400000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000160, 0x007F007FU ,0x00000000U),
+ // .. CLKACT = 0x1
+ // .. ==> 0XF8000168[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000168[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR = 0x5
+ // .. ==> 0XF8000168[13:8] = 0x00000005U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00000500U
+ // ..
+ EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000170[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR0 = 0x14
+ // .. ==> 0XF8000170[13:8] = 0x00000014U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
+ // .. DIVISOR1 = 0x1
+ // .. ==> 0XF8000170[25:20] = 0x00000001U
+ // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
+ // ..
+ EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00101400U),
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000180[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR0 = 0x14
+ // .. ==> 0XF8000180[13:8] = 0x00000014U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
+ // .. DIVISOR1 = 0x1
+ // .. ==> 0XF8000180[25:20] = 0x00000001U
+ // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
+ // ..
+ EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00101400U),
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000190[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR0 = 0x14
+ // .. ==> 0XF8000190[13:8] = 0x00000014U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
+ // .. DIVISOR1 = 0x1
+ // .. ==> 0XF8000190[25:20] = 0x00000001U
+ // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
+ // ..
+ EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101400U),
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF80001A0[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR0 = 0x14
+ // .. ==> 0XF80001A0[13:8] = 0x00000014U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
+ // .. DIVISOR1 = 0x1
+ // .. ==> 0XF80001A0[25:20] = 0x00000001U
+ // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
+ // ..
+ EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U),
+ // .. CLK_621_TRUE = 0x1
+ // .. ==> 0XF80001C4[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // ..
+ EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
+ // .. DMA_CPU_2XCLKACT = 0x1
+ // .. ==> 0XF800012C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. USB0_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. USB1_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[3:3] = 0x00000001U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000008U
+ // .. GEM0_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[6:6] = 0x00000001U
+ // .. ==> MASK : 0x00000040U VAL : 0x00000040U
+ // .. GEM1_CPU_1XCLKACT = 0x0
+ // .. ==> 0XF800012C[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. SDI0_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[10:10] = 0x00000001U
+ // .. ==> MASK : 0x00000400U VAL : 0x00000400U
+ // .. SDI1_CPU_1XCLKACT = 0x0
+ // .. ==> 0XF800012C[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. SPI0_CPU_1XCLKACT = 0x0
+ // .. ==> 0XF800012C[14:14] = 0x00000000U
+ // .. ==> MASK : 0x00004000U VAL : 0x00000000U
+ // .. SPI1_CPU_1XCLKACT = 0x0
+ // .. ==> 0XF800012C[15:15] = 0x00000000U
+ // .. ==> MASK : 0x00008000U VAL : 0x00000000U
+ // .. CAN0_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[16:16] = 0x00000001U
+ // .. ==> MASK : 0x00010000U VAL : 0x00010000U
+ // .. CAN1_CPU_1XCLKACT = 0x0
+ // .. ==> 0XF800012C[17:17] = 0x00000000U
+ // .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. I2C0_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[18:18] = 0x00000001U
+ // .. ==> MASK : 0x00040000U VAL : 0x00040000U
+ // .. I2C1_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[19:19] = 0x00000001U
+ // .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // .. UART0_CPU_1XCLKACT = 0x0
+ // .. ==> 0XF800012C[20:20] = 0x00000000U
+ // .. ==> MASK : 0x00100000U VAL : 0x00000000U
+ // .. UART1_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[21:21] = 0x00000001U
+ // .. ==> MASK : 0x00200000U VAL : 0x00200000U
+ // .. GPIO_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[22:22] = 0x00000001U
+ // .. ==> MASK : 0x00400000U VAL : 0x00400000U
+ // .. LQSPI_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[23:23] = 0x00000001U
+ // .. ==> MASK : 0x00800000U VAL : 0x00800000U
+ // .. SMC_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[24:24] = 0x00000001U
+ // .. ==> MASK : 0x01000000U VAL : 0x01000000U
+ // ..
+ EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01ED044DU),
+ // .. FINISH: CLOCK CONTROL SLCR REGISTERS
+ // .. START: THIS SHOULD BE BLANK
+ // .. FINISH: THIS SHOULD BE BLANK
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_ddr_init_data_1_0[] = {
+ // START: top
+ // .. START: DDR INITIALIZATION
+ // .. .. START: LOCK DDR
+ // .. .. reg_ddrc_soft_rstb = 0
+ // .. .. ==> 0XF8006000[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_powerdown_en = 0x0
+ // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_ddrc_data_bus_width = 0x0
+ // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U
+ // .. .. reg_ddrc_burst8_refresh = 0x0
+ // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U
+ // .. .. reg_ddrc_rdwr_idle_gap = 0x1
+ // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+ // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U
+ // .. .. reg_ddrc_dis_rd_bypass = 0x0
+ // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+ // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_act_bypass = 0x0
+ // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_auto_refresh = 0x0
+ // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
+ // .. .. FINISH: LOCK DDR
+ // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81
+ // .. .. ==> 0XF8006004[11:0] = 0x00000081U
+ // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U
+ // .. .. reg_ddrc_active_ranks = 0x1
+ // .. .. ==> 0XF8006004[13:12] = 0x00000001U
+ // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U
+ // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
+ // .. .. ==> 0XF8006004[18:14] = 0x00000000U
+ // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U
+ // .. .. reg_ddrc_wr_odt_block = 0x1
+ // .. .. ==> 0XF8006004[20:19] = 0x00000001U
+ // .. .. ==> MASK : 0x00180000U VAL : 0x00080000U
+ // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0
+ // .. .. ==> 0XF8006004[21:21] = 0x00000000U
+ // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0
+ // .. .. ==> 0XF8006004[26:22] = 0x00000000U
+ // .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_open_bank = 0x0
+ // .. .. ==> 0XF8006004[27:27] = 0x00000000U
+ // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_4bank_ram = 0x0
+ // .. .. ==> 0XF8006004[28:28] = 0x00000000U
+ // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U),
+ // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
+ // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU
+ // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
+ // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
+ // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U
+ // .. .. reg_ddrc_hpr_xact_run_length = 0xf
+ // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
+ // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
+ // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
+ // .. .. ==> 0XF800600C[10:0] = 0x00000001U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U
+ // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
+ // .. .. ==> 0XF800600C[21:11] = 0x00000002U
+ // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U
+ // .. .. reg_ddrc_lpr_xact_run_length = 0x8
+ // .. .. ==> 0XF800600C[25:22] = 0x00000008U
+ // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
+ // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
+ // .. .. ==> 0XF8006010[10:0] = 0x00000001U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U
+ // .. .. reg_ddrc_w_xact_run_length = 0x8
+ // .. .. ==> 0XF8006010[14:11] = 0x00000008U
+ // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U
+ // .. .. reg_ddrc_w_max_starve_x32 = 0x2
+ // .. .. ==> 0XF8006010[25:15] = 0x00000002U
+ // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
+ // .. .. reg_ddrc_t_rc = 0x1b
+ // .. .. ==> 0XF8006014[5:0] = 0x0000001BU
+ // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001BU
+ // .. .. reg_ddrc_t_rfc_min = 0x56
+ // .. .. ==> 0XF8006014[13:6] = 0x00000056U
+ // .. .. ==> MASK : 0x00003FC0U VAL : 0x00001580U
+ // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
+ // .. .. ==> 0XF8006014[20:14] = 0x00000010U
+ // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004159BU),
+ // .. .. reg_ddrc_wr2pre = 0x12
+ // .. .. ==> 0XF8006018[4:0] = 0x00000012U
+ // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U
+ // .. .. reg_ddrc_powerdown_to_x32 = 0x6
+ // .. .. ==> 0XF8006018[9:5] = 0x00000006U
+ // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U
+ // .. .. reg_ddrc_t_faw = 0x10
+ // .. .. ==> 0XF8006018[15:10] = 0x00000010U
+ // .. .. ==> MASK : 0x0000FC00U VAL : 0x00004000U
+ // .. .. reg_ddrc_t_ras_max = 0x24
+ // .. .. ==> 0XF8006018[21:16] = 0x00000024U
+ // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U
+ // .. .. reg_ddrc_t_ras_min = 0x14
+ // .. .. ==> 0XF8006018[26:22] = 0x00000014U
+ // .. .. ==> MASK : 0x07C00000U VAL : 0x05000000U
+ // .. .. reg_ddrc_t_cke = 0x4
+ // .. .. ==> 0XF8006018[31:28] = 0x00000004U
+ // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x452440D2U),
+ // .. .. reg_ddrc_write_latency = 0x5
+ // .. .. ==> 0XF800601C[4:0] = 0x00000005U
+ // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U
+ // .. .. reg_ddrc_rd2wr = 0x7
+ // .. .. ==> 0XF800601C[9:5] = 0x00000007U
+ // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U
+ // .. .. reg_ddrc_wr2rd = 0xe
+ // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
+ // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U
+ // .. .. reg_ddrc_t_xp = 0x4
+ // .. .. ==> 0XF800601C[19:15] = 0x00000004U
+ // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U
+ // .. .. reg_ddrc_pad_pd = 0x0
+ // .. .. ==> 0XF800601C[22:20] = 0x00000000U
+ // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U
+ // .. .. reg_ddrc_rd2pre = 0x4
+ // .. .. ==> 0XF800601C[27:23] = 0x00000004U
+ // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U
+ // .. .. reg_ddrc_t_rcd = 0x7
+ // .. .. ==> 0XF800601C[31:28] = 0x00000007U
+ // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
+ // .. .. reg_ddrc_t_ccd = 0x4
+ // .. .. ==> 0XF8006020[4:2] = 0x00000004U
+ // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U
+ // .. .. reg_ddrc_t_rrd = 0x4
+ // .. .. ==> 0XF8006020[7:5] = 0x00000004U
+ // .. .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. .. reg_ddrc_refresh_margin = 0x2
+ // .. .. ==> 0XF8006020[11:8] = 0x00000002U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
+ // .. .. reg_ddrc_t_rp = 0x7
+ // .. .. ==> 0XF8006020[15:12] = 0x00000007U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U
+ // .. .. reg_ddrc_refresh_to_x32 = 0x8
+ // .. .. ==> 0XF8006020[20:16] = 0x00000008U
+ // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U
+ // .. .. reg_ddrc_sdram = 0x1
+ // .. .. ==> 0XF8006020[21:21] = 0x00000001U
+ // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U
+ // .. .. reg_ddrc_mobile = 0x0
+ // .. .. ==> 0XF8006020[22:22] = 0x00000000U
+ // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U
+ // .. .. reg_ddrc_clock_stop_en = 0x0
+ // .. .. ==> 0XF8006020[23:23] = 0x00000000U
+ // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U
+ // .. .. reg_ddrc_read_latency = 0x7
+ // .. .. ==> 0XF8006020[28:24] = 0x00000007U
+ // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U
+ // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
+ // .. .. ==> 0XF8006020[29:29] = 0x00000001U
+ // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U
+ // .. .. reg_ddrc_dis_pad_pd = 0x0
+ // .. .. ==> 0XF8006020[30:30] = 0x00000000U
+ // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_loopback = 0x0
+ // .. .. ==> 0XF8006020[31:31] = 0x00000000U
+ // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x27287290U),
+ // .. .. reg_ddrc_en_2t_timing_mode = 0x0
+ // .. .. ==> 0XF8006024[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_prefer_write = 0x0
+ // .. .. ==> 0XF8006024[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_ddrc_max_rank_rd = 0xf
+ // .. .. ==> 0XF8006024[5:2] = 0x0000000FU
+ // .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU
+ // .. .. reg_ddrc_mr_wr = 0x0
+ // .. .. ==> 0XF8006024[6:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr_addr = 0x0
+ // .. .. ==> 0XF8006024[8:7] = 0x00000000U
+ // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr_data = 0x0
+ // .. .. ==> 0XF8006024[24:9] = 0x00000000U
+ // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U
+ // .. .. ddrc_reg_mr_wr_busy = 0x0
+ // .. .. ==> 0XF8006024[25:25] = 0x00000000U
+ // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr_type = 0x0
+ // .. .. ==> 0XF8006024[26:26] = 0x00000000U
+ // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr_rdata_valid = 0x0
+ // .. .. ==> 0XF8006024[27:27] = 0x00000000U
+ // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU),
+ // .. .. reg_ddrc_final_wait_x32 = 0x7
+ // .. .. ==> 0XF8006028[6:0] = 0x00000007U
+ // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U
+ // .. .. reg_ddrc_pre_ocd_x32 = 0x0
+ // .. .. ==> 0XF8006028[10:7] = 0x00000000U
+ // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U
+ // .. .. reg_ddrc_t_mrd = 0x4
+ // .. .. ==> 0XF8006028[13:11] = 0x00000004U
+ // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
+ // .. .. reg_ddrc_emr2 = 0x8
+ // .. .. ==> 0XF800602C[15:0] = 0x00000008U
+ // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U
+ // .. .. reg_ddrc_emr3 = 0x0
+ // .. .. ==> 0XF800602C[31:16] = 0x00000000U
+ // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
+ // .. .. reg_ddrc_mr = 0x930
+ // .. .. ==> 0XF8006030[15:0] = 0x00000930U
+ // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U
+ // .. .. reg_ddrc_emr = 0x4
+ // .. .. ==> 0XF8006030[31:16] = 0x00000004U
+ // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
+ // .. .. reg_ddrc_burst_rdwr = 0x4
+ // .. .. ==> 0XF8006034[3:0] = 0x00000004U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U
+ // .. .. reg_ddrc_pre_cke_x1024 = 0x105
+ // .. .. ==> 0XF8006034[13:4] = 0x00000105U
+ // .. .. ==> MASK : 0x00003FF0U VAL : 0x00001050U
+ // .. .. reg_ddrc_post_cke_x1024 = 0x1
+ // .. .. ==> 0XF8006034[25:16] = 0x00000001U
+ // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U
+ // .. .. reg_ddrc_burstchop = 0x0
+ // .. .. ==> 0XF8006034[28:28] = 0x00000000U
+ // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U),
+ // .. .. reg_ddrc_force_low_pri_n = 0x0
+ // .. .. ==> 0XF8006038[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_dq = 0x0
+ // .. .. ==> 0XF8006038[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_debug_mode = 0x0
+ // .. .. ==> 0XF8006038[6:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U
+ // .. .. reg_phy_wr_level_start = 0x0
+ // .. .. ==> 0XF8006038[7:7] = 0x00000000U
+ // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. .. reg_phy_rd_level_start = 0x0
+ // .. .. ==> 0XF8006038[8:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. .. reg_phy_dq0_wait_t = 0x0
+ // .. .. ==> 0XF8006038[12:9] = 0x00000000U
+ // .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U),
+ // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
+ // .. .. ==> 0XF800603C[3:0] = 0x00000007U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U
+ // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
+ // .. .. ==> 0XF800603C[7:4] = 0x00000007U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U
+ // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
+ // .. .. ==> 0XF800603C[11:8] = 0x00000007U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U
+ // .. .. reg_ddrc_addrmap_col_b5 = 0x0
+ // .. .. ==> 0XF800603C[15:12] = 0x00000000U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b6 = 0x0
+ // .. .. ==> 0XF800603C[19:16] = 0x00000000U
+ // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
+ // .. .. reg_ddrc_addrmap_col_b2 = 0x0
+ // .. .. ==> 0XF8006040[3:0] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b3 = 0x0
+ // .. .. ==> 0XF8006040[7:4] = 0x00000000U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b4 = 0x0
+ // .. .. ==> 0XF8006040[11:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b7 = 0x0
+ // .. .. ==> 0XF8006040[15:12] = 0x00000000U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b8 = 0x0
+ // .. .. ==> 0XF8006040[19:16] = 0x00000000U
+ // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b9 = 0xf
+ // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
+ // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U
+ // .. .. reg_ddrc_addrmap_col_b10 = 0xf
+ // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
+ // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U
+ // .. .. reg_ddrc_addrmap_col_b11 = 0xf
+ // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
+ // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
+ // .. .. reg_ddrc_addrmap_row_b0 = 0x6
+ // .. .. ==> 0XF8006044[3:0] = 0x00000006U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U
+ // .. .. reg_ddrc_addrmap_row_b1 = 0x6
+ // .. .. ==> 0XF8006044[7:4] = 0x00000006U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U
+ // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
+ // .. .. ==> 0XF8006044[11:8] = 0x00000006U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U
+ // .. .. reg_ddrc_addrmap_row_b12 = 0x6
+ // .. .. ==> 0XF8006044[15:12] = 0x00000006U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U
+ // .. .. reg_ddrc_addrmap_row_b13 = 0x6
+ // .. .. ==> 0XF8006044[19:16] = 0x00000006U
+ // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U
+ // .. .. reg_ddrc_addrmap_row_b14 = 0x6
+ // .. .. ==> 0XF8006044[23:20] = 0x00000006U
+ // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U
+ // .. .. reg_ddrc_addrmap_row_b15 = 0xf
+ // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
+ // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U),
+ // .. .. reg_ddrc_rank0_rd_odt = 0x0
+ // .. .. ==> 0XF8006048[2:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U
+ // .. .. reg_ddrc_rank0_wr_odt = 0x1
+ // .. .. ==> 0XF8006048[5:3] = 0x00000001U
+ // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U
+ // .. .. reg_ddrc_rank1_rd_odt = 0x1
+ // .. .. ==> 0XF8006048[8:6] = 0x00000001U
+ // .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U
+ // .. .. reg_ddrc_rank1_wr_odt = 0x1
+ // .. .. ==> 0XF8006048[11:9] = 0x00000001U
+ // .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. .. reg_phy_rd_local_odt = 0x0
+ // .. .. ==> 0XF8006048[13:12] = 0x00000000U
+ // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U
+ // .. .. reg_phy_wr_local_odt = 0x3
+ // .. .. ==> 0XF8006048[15:14] = 0x00000003U
+ // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U
+ // .. .. reg_phy_idle_local_odt = 0x3
+ // .. .. ==> 0XF8006048[17:16] = 0x00000003U
+ // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U
+ // .. .. reg_ddrc_rank2_rd_odt = 0x0
+ // .. .. ==> 0XF8006048[20:18] = 0x00000000U
+ // .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U
+ // .. .. reg_ddrc_rank2_wr_odt = 0x0
+ // .. .. ==> 0XF8006048[23:21] = 0x00000000U
+ // .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U
+ // .. .. reg_ddrc_rank3_rd_odt = 0x0
+ // .. .. ==> 0XF8006048[26:24] = 0x00000000U
+ // .. .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_rank3_wr_odt = 0x0
+ // .. .. ==> 0XF8006048[29:27] = 0x00000000U
+ // .. .. ==> MASK : 0x38000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U),
+ // .. .. reg_phy_rd_cmd_to_data = 0x0
+ // .. .. ==> 0XF8006050[3:0] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
+ // .. .. reg_phy_wr_cmd_to_data = 0x0
+ // .. .. ==> 0XF8006050[7:4] = 0x00000000U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. .. reg_phy_rdc_we_to_re_delay = 0x8
+ // .. .. ==> 0XF8006050[11:8] = 0x00000008U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U
+ // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
+ // .. .. ==> 0XF8006050[15:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
+ // .. .. reg_phy_use_fixed_re = 0x1
+ // .. .. ==> 0XF8006050[16:16] = 0x00000001U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U
+ // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
+ // .. .. ==> 0XF8006050[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
+ // .. .. ==> 0XF8006050[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_phy_clk_stall_level = 0x0
+ // .. .. ==> 0XF8006050[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
+ // .. .. ==> 0XF8006050[27:24] = 0x00000007U
+ // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U
+ // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
+ // .. .. ==> 0XF8006050[31:28] = 0x00000007U
+ // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
+ // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1
+ // .. .. ==> 0XF8006058[7:0] = 0x00000001U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U
+ // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1
+ // .. .. ==> 0XF8006058[15:8] = 0x00000001U
+ // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U
+ // .. .. reg_ddrc_dis_dll_calib = 0x0
+ // .. .. ==> 0XF8006058[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U),
+ // .. .. reg_ddrc_rd_odt_delay = 0x3
+ // .. .. ==> 0XF800605C[3:0] = 0x00000003U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U
+ // .. .. reg_ddrc_wr_odt_delay = 0x0
+ // .. .. ==> 0XF800605C[7:4] = 0x00000000U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. .. reg_ddrc_rd_odt_hold = 0x0
+ // .. .. ==> 0XF800605C[11:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U
+ // .. .. reg_ddrc_wr_odt_hold = 0x5
+ // .. .. ==> 0XF800605C[15:12] = 0x00000005U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
+ // .. .. reg_ddrc_pageclose = 0x0
+ // .. .. ==> 0XF8006060[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_lpr_num_entries = 0x1f
+ // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
+ // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU
+ // .. .. reg_ddrc_auto_pre_en = 0x0
+ // .. .. ==> 0XF8006060[7:7] = 0x00000000U
+ // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. .. reg_ddrc_refresh_update_level = 0x0
+ // .. .. ==> 0XF8006060[8:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_wc = 0x0
+ // .. .. ==> 0XF8006060[9:9] = 0x00000000U
+ // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_collision_page_opt = 0x0
+ // .. .. ==> 0XF8006060[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_ddrc_selfref_en = 0x0
+ // .. .. ==> 0XF8006060[12:12] = 0x00000000U
+ // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
+ // .. .. reg_ddrc_go2critical_hysteresis = 0x0
+ // .. .. ==> 0XF8006064[12:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U
+ // .. .. reg_arb_go2critical_en = 0x1
+ // .. .. ==> 0XF8006064[17:17] = 0x00000001U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
+ // .. .. reg_ddrc_wrlvl_ww = 0x41
+ // .. .. ==> 0XF8006068[7:0] = 0x00000041U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U
+ // .. .. reg_ddrc_rdlvl_rr = 0x41
+ // .. .. ==> 0XF8006068[15:8] = 0x00000041U
+ // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U
+ // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
+ // .. .. ==> 0XF8006068[25:16] = 0x00000028U
+ // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
+ // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
+ // .. .. ==> 0XF800606C[7:0] = 0x00000010U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U
+ // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
+ // .. .. ==> 0XF800606C[15:8] = 0x00000016U
+ // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U
+ // .. ..
+ EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
+ // .. .. refresh_timer0_start_value_x32 = 0x0
+ // .. .. ==> 0XF80060A0[11:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U
+ // .. .. refresh_timer1_start_value_x32 = 0x8
+ // .. .. ==> 0XF80060A0[23:12] = 0x00000008U
+ // .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U),
+ // .. .. reg_ddrc_dis_auto_zq = 0x0
+ // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_ddr3 = 0x1
+ // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. .. reg_ddrc_t_mod = 0x200
+ // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
+ // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U
+ // .. .. reg_ddrc_t_zq_long_nop = 0x200
+ // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U
+ // .. .. reg_ddrc_t_zq_short_nop = 0x40
+ // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
+ // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
+ // .. .. t_zq_short_interval_x1024 = 0xcb73
+ // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U
+ // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U
+ // .. .. dram_rstn_x1024 = 0x69
+ // .. .. ==> 0XF80060A8[27:20] = 0x00000069U
+ // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
+ // .. .. deeppowerdown_en = 0x0
+ // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. deeppowerdown_to_x1024 = 0xff
+ // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
+ // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU
+ // .. ..
+ EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
+ // .. .. dfi_wrlvl_max_x1024 = 0xfff
+ // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
+ // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU
+ // .. .. dfi_rdlvl_max_x1024 = 0xfff
+ // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
+ // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U
+ // .. .. ddrc_reg_twrlvl_max_error = 0x0
+ // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
+ // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U
+ // .. .. ddrc_reg_trdlvl_max_error = 0x0
+ // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
+ // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dfi_wr_level_en = 0x1
+ // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
+ // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U
+ // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
+ // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
+ // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U
+ // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
+ // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
+ // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
+ // .. .. reg_ddrc_2t_delay = 0x0
+ // .. .. ==> 0XF80060B4[8:0] = 0x00000000U
+ // .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U
+ // .. .. reg_ddrc_skip_ocd = 0x1
+ // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
+ // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U
+ // .. .. reg_ddrc_dis_pre_bypass = 0x0
+ // .. .. ==> 0XF80060B4[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U),
+ // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
+ // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
+ // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U
+ // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
+ // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
+ // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U
+ // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
+ // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
+ // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
+ // .. .. START: RESET ECC ERROR
+ // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1
+ // .. .. ==> 0XF80060C4[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. Clear_Correctable_DRAM_ECC_error = 1
+ // .. .. ==> 0XF80060C4[1:1] = 0x00000001U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U),
+ // .. .. FINISH: RESET ECC ERROR
+ // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
+ // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
+ // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
+ // .. .. CORR_ECC_LOG_VALID = 0x0
+ // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. ECC_CORRECTED_BIT_NUM = 0x0
+ // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
+ // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
+ // .. .. UNCORR_ECC_LOG_VALID = 0x0
+ // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
+ // .. .. STAT_NUM_CORR_ERR = 0x0
+ // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
+ // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U
+ // .. .. STAT_NUM_UNCORR_ERR = 0x0
+ // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
+ // .. .. reg_ddrc_ecc_mode = 0x0
+ // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_scrub = 0x1
+ // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
+ // .. .. reg_phy_dif_on = 0x0
+ // .. .. ==> 0XF8006114[3:0] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
+ // .. .. reg_phy_dif_off = 0x0
+ // .. .. ==> 0XF8006114[7:4] = 0x00000000U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
+ // .. .. reg_phy_data_slice_in_use = 0x1
+ // .. .. ==> 0XF8006118[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_phy_rdlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006118[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006118[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_wrlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006118[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_tx = 0x0
+ // .. .. ==> 0XF8006118[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_rx = 0x0
+ // .. .. ==> 0XF8006118[5:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
+ // .. .. reg_phy_bist_shift_dq = 0x0
+ // .. .. ==> 0XF8006118[14:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
+ // .. .. reg_phy_bist_err_clr = 0x0
+ // .. .. ==> 0XF8006118[23:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
+ // .. .. reg_phy_dq_offset = 0x40
+ // .. .. ==> 0XF8006118[30:24] = 0x00000040U
+ // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U),
+ // .. .. reg_phy_data_slice_in_use = 0x1
+ // .. .. ==> 0XF800611C[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_phy_rdlvl_inc_mode = 0x0
+ // .. .. ==> 0XF800611C[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_inc_mode = 0x0
+ // .. .. ==> 0XF800611C[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_wrlvl_inc_mode = 0x0
+ // .. .. ==> 0XF800611C[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_tx = 0x0
+ // .. .. ==> 0XF800611C[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_rx = 0x0
+ // .. .. ==> 0XF800611C[5:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
+ // .. .. reg_phy_bist_shift_dq = 0x0
+ // .. .. ==> 0XF800611C[14:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
+ // .. .. reg_phy_bist_err_clr = 0x0
+ // .. .. ==> 0XF800611C[23:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
+ // .. .. reg_phy_dq_offset = 0x40
+ // .. .. ==> 0XF800611C[30:24] = 0x00000040U
+ // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U),
+ // .. .. reg_phy_data_slice_in_use = 0x1
+ // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_phy_rdlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_wrlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_tx = 0x0
+ // .. .. ==> 0XF8006120[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_rx = 0x0
+ // .. .. ==> 0XF8006120[5:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
+ // .. .. reg_phy_bist_shift_dq = 0x0
+ // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
+ // .. .. reg_phy_bist_err_clr = 0x0
+ // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
+ // .. .. reg_phy_dq_offset = 0x40
+ // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+ // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U),
+ // .. .. reg_phy_data_slice_in_use = 0x1
+ // .. .. ==> 0XF8006124[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_phy_rdlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006124[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006124[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_wrlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006124[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_tx = 0x0
+ // .. .. ==> 0XF8006124[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_rx = 0x0
+ // .. .. ==> 0XF8006124[5:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
+ // .. .. reg_phy_bist_shift_dq = 0x0
+ // .. .. ==> 0XF8006124[14:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
+ // .. .. reg_phy_bist_err_clr = 0x0
+ // .. .. ==> 0XF8006124[23:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
+ // .. .. reg_phy_dq_offset = 0x40
+ // .. .. ==> 0XF8006124[30:24] = 0x00000040U
+ // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U),
+ // .. .. reg_phy_wrlvl_init_ratio = 0x1d
+ // .. .. ==> 0XF800612C[9:0] = 0x0000001DU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x0000001DU
+ // .. .. reg_phy_gatelvl_init_ratio = 0xf2
+ // .. .. ==> 0XF800612C[19:10] = 0x000000F2U
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x0003C800U
+ // .. ..
+ EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0003C81DU),
+ // .. .. reg_phy_wrlvl_init_ratio = 0x12
+ // .. .. ==> 0XF8006130[9:0] = 0x00000012U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000012U
+ // .. .. reg_phy_gatelvl_init_ratio = 0xd8
+ // .. .. ==> 0XF8006130[19:10] = 0x000000D8U
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x00036000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00036012U),
+ // .. .. reg_phy_wrlvl_init_ratio = 0xc
+ // .. .. ==> 0XF8006134[9:0] = 0x0000000CU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x0000000CU
+ // .. .. reg_phy_gatelvl_init_ratio = 0xde
+ // .. .. ==> 0XF8006134[19:10] = 0x000000DEU
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x00037800U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0003780CU),
+ // .. .. reg_phy_wrlvl_init_ratio = 0x21
+ // .. .. ==> 0XF8006138[9:0] = 0x00000021U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000021U
+ // .. .. reg_phy_gatelvl_init_ratio = 0xee
+ // .. .. ==> 0XF8006138[19:10] = 0x000000EEU
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x0003B800U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0003B821U),
+ // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+ // .. .. ==> 0XF8006140[9:0] = 0x00000035U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
+ // .. .. reg_phy_rd_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006140[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006140[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
+ // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+ // .. .. ==> 0XF8006144[9:0] = 0x00000035U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
+ // .. .. reg_phy_rd_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006144[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006144[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
+ // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+ // .. .. ==> 0XF8006148[9:0] = 0x00000035U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
+ // .. .. reg_phy_rd_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006148[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006148[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
+ // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+ // .. .. ==> 0XF800614C[9:0] = 0x00000035U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
+ // .. .. reg_phy_rd_dqs_slave_force = 0x0
+ // .. .. ==> 0XF800614C[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF800614C[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
+ // .. .. reg_phy_wr_dqs_slave_ratio = 0x9d
+ // .. .. ==> 0XF8006154[9:0] = 0x0000009DU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x0000009DU
+ // .. .. reg_phy_wr_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006154[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006154[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x0000009DU),
+ // .. .. reg_phy_wr_dqs_slave_ratio = 0x92
+ // .. .. ==> 0XF8006158[9:0] = 0x00000092U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000092U
+ // .. .. reg_phy_wr_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006158[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006158[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000092U),
+ // .. .. reg_phy_wr_dqs_slave_ratio = 0x8c
+ // .. .. ==> 0XF800615C[9:0] = 0x0000008CU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x0000008CU
+ // .. .. reg_phy_wr_dqs_slave_force = 0x0
+ // .. .. ==> 0XF800615C[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF800615C[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x0000008CU),
+ // .. .. reg_phy_wr_dqs_slave_ratio = 0xa1
+ // .. .. ==> 0XF8006160[9:0] = 0x000000A1U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000A1U
+ // .. .. reg_phy_wr_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006160[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006160[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x000000A1U),
+ // .. .. reg_phy_fifo_we_slave_ratio = 0x147
+ // .. .. ==> 0XF8006168[10:0] = 0x00000147U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000147U
+ // .. .. reg_phy_fifo_we_in_force = 0x0
+ // .. .. ==> 0XF8006168[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. reg_phy_fifo_we_in_delay = 0x0
+ // .. .. ==> 0XF8006168[20:12] = 0x00000000U
+ // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000147U),
+ // .. .. reg_phy_fifo_we_slave_ratio = 0x12d
+ // .. .. ==> 0XF800616C[10:0] = 0x0000012DU
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x0000012DU
+ // .. .. reg_phy_fifo_we_in_force = 0x0
+ // .. .. ==> 0XF800616C[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. reg_phy_fifo_we_in_delay = 0x0
+ // .. .. ==> 0XF800616C[20:12] = 0x00000000U
+ // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x0000012DU),
+ // .. .. reg_phy_fifo_we_slave_ratio = 0x133
+ // .. .. ==> 0XF8006170[10:0] = 0x00000133U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000133U
+ // .. .. reg_phy_fifo_we_in_force = 0x0
+ // .. .. ==> 0XF8006170[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. reg_phy_fifo_we_in_delay = 0x0
+ // .. .. ==> 0XF8006170[20:12] = 0x00000000U
+ // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000133U),
+ // .. .. reg_phy_fifo_we_slave_ratio = 0x143
+ // .. .. ==> 0XF8006174[10:0] = 0x00000143U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000143U
+ // .. .. reg_phy_fifo_we_in_force = 0x0
+ // .. .. ==> 0XF8006174[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. reg_phy_fifo_we_in_delay = 0x0
+ // .. .. ==> 0XF8006174[20:12] = 0x00000000U
+ // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000143U),
+ // .. .. reg_phy_wr_data_slave_ratio = 0xdd
+ // .. .. ==> 0XF800617C[9:0] = 0x000000DDU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000DDU
+ // .. .. reg_phy_wr_data_slave_force = 0x0
+ // .. .. ==> 0XF800617C[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_data_slave_delay = 0x0
+ // .. .. ==> 0XF800617C[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000DDU),
+ // .. .. reg_phy_wr_data_slave_ratio = 0xd2
+ // .. .. ==> 0XF8006180[9:0] = 0x000000D2U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000D2U
+ // .. .. reg_phy_wr_data_slave_force = 0x0
+ // .. .. ==> 0XF8006180[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_data_slave_delay = 0x0
+ // .. .. ==> 0XF8006180[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000D2U),
+ // .. .. reg_phy_wr_data_slave_ratio = 0xcc
+ // .. .. ==> 0XF8006184[9:0] = 0x000000CCU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000CCU
+ // .. .. reg_phy_wr_data_slave_force = 0x0
+ // .. .. ==> 0XF8006184[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_data_slave_delay = 0x0
+ // .. .. ==> 0XF8006184[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000CCU),
+ // .. .. reg_phy_wr_data_slave_ratio = 0xe1
+ // .. .. ==> 0XF8006188[9:0] = 0x000000E1U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000E1U
+ // .. .. reg_phy_wr_data_slave_force = 0x0
+ // .. .. ==> 0XF8006188[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_data_slave_delay = 0x0
+ // .. .. ==> 0XF8006188[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000E1U),
+ // .. .. reg_phy_loopback = 0x0
+ // .. .. ==> 0XF8006190[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_phy_bl2 = 0x0
+ // .. .. ==> 0XF8006190[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_at_spd_atpg = 0x0
+ // .. .. ==> 0XF8006190[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_bist_enable = 0x0
+ // .. .. ==> 0XF8006190[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_bist_force_err = 0x0
+ // .. .. ==> 0XF8006190[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reg_phy_bist_mode = 0x0
+ // .. .. ==> 0XF8006190[6:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U
+ // .. .. reg_phy_invert_clkout = 0x1
+ // .. .. ==> 0XF8006190[7:7] = 0x00000001U
+ // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0
+ // .. .. ==> 0XF8006190[8:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. .. reg_phy_sel_logic = 0x0
+ // .. .. ==> 0XF8006190[9:9] = 0x00000000U
+ // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U
+ // .. .. reg_phy_ctrl_slave_ratio = 0x100
+ // .. .. ==> 0XF8006190[19:10] = 0x00000100U
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U
+ // .. .. reg_phy_ctrl_slave_force = 0x0
+ // .. .. ==> 0XF8006190[20:20] = 0x00000000U
+ // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U
+ // .. .. reg_phy_ctrl_slave_delay = 0x0
+ // .. .. ==> 0XF8006190[27:21] = 0x00000000U
+ // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U
+ // .. .. reg_phy_use_rank0_delays = 0x1
+ // .. .. ==> 0XF8006190[28:28] = 0x00000001U
+ // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
+ // .. .. reg_phy_lpddr = 0x0
+ // .. .. ==> 0XF8006190[29:29] = 0x00000000U
+ // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U
+ // .. .. reg_phy_cmd_latency = 0x0
+ // .. .. ==> 0XF8006190[30:30] = 0x00000000U
+ // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U
+ // .. .. reg_phy_int_lpbk = 0x0
+ // .. .. ==> 0XF8006190[31:31] = 0x00000000U
+ // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U),
+ // .. .. reg_phy_wr_rl_delay = 0x2
+ // .. .. ==> 0XF8006194[4:0] = 0x00000002U
+ // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U
+ // .. .. reg_phy_rd_rl_delay = 0x4
+ // .. .. ==> 0XF8006194[9:5] = 0x00000004U
+ // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U
+ // .. .. reg_phy_dll_lock_diff = 0xf
+ // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
+ // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U
+ // .. .. reg_phy_use_wr_level = 0x1
+ // .. .. ==> 0XF8006194[14:14] = 0x00000001U
+ // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U
+ // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
+ // .. .. ==> 0XF8006194[15:15] = 0x00000001U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U
+ // .. .. reg_phy_use_rd_data_eye_level = 0x1
+ // .. .. ==> 0XF8006194[16:16] = 0x00000001U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U
+ // .. .. reg_phy_dis_calib_rst = 0x0
+ // .. .. ==> 0XF8006194[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_phy_ctrl_slave_delay = 0x0
+ // .. .. ==> 0XF8006194[19:18] = 0x00000000U
+ // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
+ // .. .. reg_arb_page_addr_mask = 0x0
+ // .. .. ==> 0XF8006204[31:0] = 0x00000000U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
+ // .. .. reg_arb_pri_wr_portn = 0x3ff
+ // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_wr_portn = 0x0
+ // .. .. ==> 0XF8006208[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+ // .. .. ==> 0XF8006208[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+ // .. .. ==> 0XF8006208[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_rmw_portn = 0x1
+ // .. .. ==> 0XF8006208[19:19] = 0x00000001U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU),
+ // .. .. reg_arb_pri_wr_portn = 0x3ff
+ // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_wr_portn = 0x0
+ // .. .. ==> 0XF800620C[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+ // .. .. ==> 0XF800620C[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+ // .. .. ==> 0XF800620C[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_rmw_portn = 0x1
+ // .. .. ==> 0XF800620C[19:19] = 0x00000001U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU),
+ // .. .. reg_arb_pri_wr_portn = 0x3ff
+ // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_wr_portn = 0x0
+ // .. .. ==> 0XF8006210[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+ // .. .. ==> 0XF8006210[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+ // .. .. ==> 0XF8006210[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_rmw_portn = 0x1
+ // .. .. ==> 0XF8006210[19:19] = 0x00000001U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU),
+ // .. .. reg_arb_pri_wr_portn = 0x3ff
+ // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_wr_portn = 0x0
+ // .. .. ==> 0XF8006214[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+ // .. .. ==> 0XF8006214[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+ // .. .. ==> 0XF8006214[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_rmw_portn = 0x1
+ // .. .. ==> 0XF8006214[19:19] = 0x00000001U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU),
+ // .. .. reg_arb_pri_rd_portn = 0x3ff
+ // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_rd_portn = 0x0
+ // .. .. ==> 0XF8006218[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+ // .. .. ==> 0XF8006218[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+ // .. .. ==> 0XF8006218[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_set_hpr_rd_portn = 0x0
+ // .. .. ==> 0XF8006218[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
+ // .. .. reg_arb_pri_rd_portn = 0x3ff
+ // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_rd_portn = 0x0
+ // .. .. ==> 0XF800621C[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+ // .. .. ==> 0XF800621C[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+ // .. .. ==> 0XF800621C[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_set_hpr_rd_portn = 0x0
+ // .. .. ==> 0XF800621C[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
+ // .. .. reg_arb_pri_rd_portn = 0x3ff
+ // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_rd_portn = 0x0
+ // .. .. ==> 0XF8006220[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+ // .. .. ==> 0XF8006220[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+ // .. .. ==> 0XF8006220[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_set_hpr_rd_portn = 0x0
+ // .. .. ==> 0XF8006220[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
+ // .. .. reg_arb_pri_rd_portn = 0x3ff
+ // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_rd_portn = 0x0
+ // .. .. ==> 0XF8006224[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+ // .. .. ==> 0XF8006224[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+ // .. .. ==> 0XF8006224[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_set_hpr_rd_portn = 0x0
+ // .. .. ==> 0XF8006224[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
+ // .. .. reg_ddrc_lpddr2 = 0x0
+ // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_per_bank_refresh = 0x0
+ // .. .. ==> 0XF80062A8[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_ddrc_derate_enable = 0x0
+ // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr4_margin = 0x0
+ // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U),
+ // .. .. reg_ddrc_mr4_read_interval = 0x0
+ // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
+ // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
+ // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U
+ // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
+ // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
+ // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U
+ // .. .. reg_ddrc_t_mrw = 0x5
+ // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
+ // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8
+ // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U
+ // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
+ // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
+ // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U
+ // .. ..
+ EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
+ // .. .. START: POLL ON DCI STATUS
+ // .. .. DONE = 1
+ // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
+ // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U
+ // .. ..
+ EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+ // .. .. FINISH: POLL ON DCI STATUS
+ // .. .. START: UNLOCK DDR
+ // .. .. reg_ddrc_soft_rstb = 0x1
+ // .. .. ==> 0XF8006000[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_ddrc_powerdown_en = 0x0
+ // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_ddrc_data_bus_width = 0x0
+ // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U
+ // .. .. reg_ddrc_burst8_refresh = 0x0
+ // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U
+ // .. .. reg_ddrc_rdwr_idle_gap = 1
+ // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+ // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U
+ // .. .. reg_ddrc_dis_rd_bypass = 0x0
+ // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+ // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_act_bypass = 0x0
+ // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_auto_refresh = 0x0
+ // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
+ // .. .. FINISH: UNLOCK DDR
+ // .. .. START: CHECK DDR STATUS
+ // .. .. ddrc_reg_operating_mode = 1
+ // .. .. ==> 0XF8006054[2:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U
+ // .. ..
+ EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+ // .. .. FINISH: CHECK DDR STATUS
+ // .. FINISH: DDR INITIALIZATION
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_mio_init_data_1_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: OCM REMAPPING
+ // .. VREF_EN = 0x1
+ // .. ==> 0XF8000B00[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. VREF_PULLUP_EN = 0x0
+ // .. ==> 0XF8000B00[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. CLK_PULLUP_EN = 0x0
+ // .. ==> 0XF8000B00[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. SRSTN_PULLUP_EN = 0x0
+ // .. ==> 0XF8000B00[9:9] = 0x00000000U
+ // .. ==> MASK : 0x00000200U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B00, 0x00000303U ,0x00000001U),
+ // .. FINISH: OCM REMAPPING
+ // .. START: DDRIOB SETTINGS
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B40[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x0
+ // .. ==> 0XF8000B40[2:1] = 0x00000000U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000000U
+ // .. DCI_UPDATE = 0x0
+ // .. ==> 0XF8000B40[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x0
+ // .. ==> 0XF8000B40[4:4] = 0x00000000U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. DCR_TYPE = 0x0
+ // .. ==> 0XF8000B40[6:5] = 0x00000000U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000000U
+ // .. IBUF_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B40[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B40[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B40[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B40[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B44[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x0
+ // .. ==> 0XF8000B44[2:1] = 0x00000000U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000000U
+ // .. DCI_UPDATE = 0x0
+ // .. ==> 0XF8000B44[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x0
+ // .. ==> 0XF8000B44[4:4] = 0x00000000U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. DCR_TYPE = 0x0
+ // .. ==> 0XF8000B44[6:5] = 0x00000000U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000000U
+ // .. IBUF_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B44[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B44[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B44[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B44[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B48[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x1
+ // .. ==> 0XF8000B48[2:1] = 0x00000001U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000002U
+ // .. DCI_UPDATE = 0x0
+ // .. ==> 0XF8000B48[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x1
+ // .. ==> 0XF8000B48[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. DCR_TYPE = 0x3
+ // .. ==> 0XF8000B48[6:5] = 0x00000003U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000060U
+ // .. IBUF_DISABLE_MODE = 0
+ // .. ==> 0XF8000B48[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0
+ // .. ==> 0XF8000B48[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B48[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B48[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B4C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x1
+ // .. ==> 0XF8000B4C[2:1] = 0x00000001U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000002U
+ // .. DCI_UPDATE = 0x0
+ // .. ==> 0XF8000B4C[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x1
+ // .. ==> 0XF8000B4C[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. DCR_TYPE = 0x3
+ // .. ==> 0XF8000B4C[6:5] = 0x00000003U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000060U
+ // .. IBUF_DISABLE_MODE = 0
+ // .. ==> 0XF8000B4C[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0
+ // .. ==> 0XF8000B4C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B4C[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B4C[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B50[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x2
+ // .. ==> 0XF8000B50[2:1] = 0x00000002U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000004U
+ // .. DCI_UPDATE = 0x0
+ // .. ==> 0XF8000B50[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x1
+ // .. ==> 0XF8000B50[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. DCR_TYPE = 0x3
+ // .. ==> 0XF8000B50[6:5] = 0x00000003U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000060U
+ // .. IBUF_DISABLE_MODE = 0
+ // .. ==> 0XF8000B50[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0
+ // .. ==> 0XF8000B50[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B50[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B50[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B54[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x2
+ // .. ==> 0XF8000B54[2:1] = 0x00000002U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000004U
+ // .. DCI_UPDATE = 0x0
+ // .. ==> 0XF8000B54[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x1
+ // .. ==> 0XF8000B54[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. DCR_TYPE = 0x3
+ // .. ==> 0XF8000B54[6:5] = 0x00000003U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000060U
+ // .. IBUF_DISABLE_MODE = 0
+ // .. ==> 0XF8000B54[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0
+ // .. ==> 0XF8000B54[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B54[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B54[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B58[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x0
+ // .. ==> 0XF8000B58[2:1] = 0x00000000U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000000U
+ // .. DCI_UPDATE = 0x0
+ // .. ==> 0XF8000B58[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x0
+ // .. ==> 0XF8000B58[4:4] = 0x00000000U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. DCR_TYPE = 0x0
+ // .. ==> 0XF8000B58[6:5] = 0x00000000U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000000U
+ // .. IBUF_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B58[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B58[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B58[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B58[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
+ // .. DRIVE_P = 0x1c
+ // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
+ // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
+ // .. DRIVE_N = 0xc
+ // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
+ // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
+ // .. SLEW_P = 0x3
+ // .. ==> 0XF8000B5C[18:14] = 0x00000003U
+ // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U
+ // .. SLEW_N = 0x3
+ // .. ==> 0XF8000B5C[23:19] = 0x00000003U
+ // .. ==> MASK : 0x00F80000U VAL : 0x00180000U
+ // .. GTL = 0x0
+ // .. ==> 0XF8000B5C[26:24] = 0x00000000U
+ // .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. RTERM = 0x0
+ // .. ==> 0XF8000B5C[31:27] = 0x00000000U
+ // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
+ // .. DRIVE_P = 0x1c
+ // .. ==> 0XF8000B60[6:0] = 0x0000001CU
+ // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
+ // .. DRIVE_N = 0xc
+ // .. ==> 0XF8000B60[13:7] = 0x0000000CU
+ // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
+ // .. SLEW_P = 0x6
+ // .. ==> 0XF8000B60[18:14] = 0x00000006U
+ // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
+ // .. SLEW_N = 0x1f
+ // .. ==> 0XF8000B60[23:19] = 0x0000001FU
+ // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
+ // .. GTL = 0x0
+ // .. ==> 0XF8000B60[26:24] = 0x00000000U
+ // .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. RTERM = 0x0
+ // .. ==> 0XF8000B60[31:27] = 0x00000000U
+ // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
+ // .. DRIVE_P = 0x1c
+ // .. ==> 0XF8000B64[6:0] = 0x0000001CU
+ // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
+ // .. DRIVE_N = 0xc
+ // .. ==> 0XF8000B64[13:7] = 0x0000000CU
+ // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
+ // .. SLEW_P = 0x6
+ // .. ==> 0XF8000B64[18:14] = 0x00000006U
+ // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
+ // .. SLEW_N = 0x1f
+ // .. ==> 0XF8000B64[23:19] = 0x0000001FU
+ // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
+ // .. GTL = 0x0
+ // .. ==> 0XF8000B64[26:24] = 0x00000000U
+ // .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. RTERM = 0x0
+ // .. ==> 0XF8000B64[31:27] = 0x00000000U
+ // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
+ // .. DRIVE_P = 0x1c
+ // .. ==> 0XF8000B68[6:0] = 0x0000001CU
+ // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
+ // .. DRIVE_N = 0xc
+ // .. ==> 0XF8000B68[13:7] = 0x0000000CU
+ // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
+ // .. SLEW_P = 0x6
+ // .. ==> 0XF8000B68[18:14] = 0x00000006U
+ // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
+ // .. SLEW_N = 0x1f
+ // .. ==> 0XF8000B68[23:19] = 0x0000001FU
+ // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
+ // .. GTL = 0x0
+ // .. ==> 0XF8000B68[26:24] = 0x00000000U
+ // .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. RTERM = 0x0
+ // .. ==> 0XF8000B68[31:27] = 0x00000000U
+ // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
+ // .. VREF_INT_EN = 0x1
+ // .. ==> 0XF8000B6C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. VREF_SEL = 0x4
+ // .. ==> 0XF8000B6C[4:1] = 0x00000004U
+ // .. ==> MASK : 0x0000001EU VAL : 0x00000008U
+ // .. VREF_EXT_EN = 0x0
+ // .. ==> 0XF8000B6C[6:5] = 0x00000000U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000000U
+ // .. VREF_PULLUP_EN = 0x0
+ // .. ==> 0XF8000B6C[8:7] = 0x00000000U
+ // .. ==> MASK : 0x00000180U VAL : 0x00000000U
+ // .. REFIO_EN = 0x1
+ // .. ==> 0XF8000B6C[9:9] = 0x00000001U
+ // .. ==> MASK : 0x00000200U VAL : 0x00000200U
+ // .. REFIO_PULLUP_EN = 0x0
+ // .. ==> 0XF8000B6C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DRST_B_PULLUP_EN = 0x0
+ // .. ==> 0XF8000B6C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // .. CKE_PULLUP_EN = 0x0
+ // .. ==> 0XF8000B6C[14:14] = 0x00000000U
+ // .. ==> MASK : 0x00004000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B6C, 0x000073FFU ,0x00000209U),
+ // .. .. START: ASSERT RESET
+ // .. .. RESET = 1
+ // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. VRN_OUT = 0x1
+ // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U),
+ // .. .. FINISH: ASSERT RESET
+ // .. .. START: DEASSERT RESET
+ // .. .. RESET = 0
+ // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. VRN_OUT = 0x1
+ // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
+ // .. .. FINISH: DEASSERT RESET
+ // .. .. RESET = 0x1
+ // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ENABLE = 0x1
+ // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. .. VRP_TRI = 0x0
+ // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. VRN_TRI = 0x0
+ // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. VRP_OUT = 0x0
+ // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. VRN_OUT = 0x1
+ // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
+ // .. .. NREF_OPT1 = 0x0
+ // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
+ // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U
+ // .. .. NREF_OPT2 = 0x0
+ // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U
+ // .. .. NREF_OPT4 = 0x1
+ // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
+ // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U
+ // .. .. PREF_OPT1 = 0x0
+ // .. .. ==> 0XF8000B70[16:14] = 0x00000000U
+ // .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U
+ // .. .. PREF_OPT2 = 0x0
+ // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
+ // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U
+ // .. .. UPDATE_CONTROL = 0x0
+ // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
+ // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U
+ // .. .. INIT_COMPLETE = 0x0
+ // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
+ // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U
+ // .. .. TST_CLK = 0x0
+ // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
+ // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U
+ // .. .. TST_HLN = 0x0
+ // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
+ // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U
+ // .. .. TST_HLP = 0x0
+ // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
+ // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U
+ // .. .. TST_RST = 0x0
+ // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
+ // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
+ // .. .. INT_DCI_EN = 0x0
+ // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
+ // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U),
+ // .. FINISH: DDRIOB SETTINGS
+ // .. START: MIO PROGRAMMING
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000700[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. Speed = 0
+ // .. ==> 0XF8000700[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000700[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000700[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000700[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000700, 0x00003F01U ,0x00001201U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000704[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000704[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000704[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000704[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000704[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000704[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000704[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000704[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000704[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000708[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000708[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000708[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000708[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000708[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000708[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000708[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000708[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000708[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800070C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF800070C[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800070C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800070C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800070C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800070C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800070C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800070C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800070C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000710[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000710[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000710[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000710[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000710[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000710[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000710[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000710[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000710[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000714[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000714[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000714[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000714[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000714[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000714[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000714[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000714[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000714[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000718[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000718[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000718[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000718[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000718[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000718[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000718[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000718[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000718[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800071C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800071C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800071C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800071C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800071C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800071C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800071C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800071C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800071C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000200U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000720[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000720[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000720[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000720[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000720[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000720[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000720[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000720[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000720[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000724[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000724[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000724[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000724[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000724[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000724[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000724[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000724[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000724[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001200U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000728[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000728[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000728[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000728[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000728[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000728[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000728[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000728[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000728[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001200U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800072C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800072C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800072C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800072C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800072C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800072C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800072C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF800072C[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800072C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001200U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000730[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000730[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000730[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000730[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000730[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000730[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000730[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000730[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000730[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001200U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000734[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000734[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000734[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000734[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000734[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000734[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000734[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000734[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000734[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001200U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000738[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000738[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000738[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000738[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000738[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000738[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000738[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000738[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000738[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00001200U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF800073C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. Speed = 0
+ // .. ==> 0XF800073C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800073C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF800073C[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800073C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800073C, 0x00003F01U ,0x00001201U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000740[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000740[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000740[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000740[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000740[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000740[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 4
+ // .. ==> 0XF8000740[11:9] = 0x00000004U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000740[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 1
+ // .. ==> 0XF8000740[13:13] = 0x00000001U
+ // .. ==> MASK : 0x00002000U VAL : 0x00002000U
+ // ..
+ EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00002802U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000744[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000744[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000744[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000744[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000744[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000744[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 4
+ // .. ==> 0XF8000744[11:9] = 0x00000004U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000744[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 1
+ // .. ==> 0XF8000744[13:13] = 0x00000001U
+ // .. ==> MASK : 0x00002000U VAL : 0x00002000U
+ // ..
+ EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00002802U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000748[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000748[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000748[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000748[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000748[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000748[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 4
+ // .. ==> 0XF8000748[11:9] = 0x00000004U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000748[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 1
+ // .. ==> 0XF8000748[13:13] = 0x00000001U
+ // .. ==> MASK : 0x00002000U VAL : 0x00002000U
+ // ..
+ EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00002802U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800074C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF800074C[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800074C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800074C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800074C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800074C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 4
+ // .. ==> 0XF800074C[11:9] = 0x00000004U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
+ // .. PULLUP = 0
+ // .. ==> 0XF800074C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 1
+ // .. ==> 0XF800074C[13:13] = 0x00000001U
+ // .. ==> MASK : 0x00002000U VAL : 0x00002000U
+ // ..
+ EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00002802U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000750[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000750[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000750[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000750[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000750[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000750[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 4
+ // .. ==> 0XF8000750[11:9] = 0x00000004U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000750[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 1
+ // .. ==> 0XF8000750[13:13] = 0x00000001U
+ // .. ==> MASK : 0x00002000U VAL : 0x00002000U
+ // ..
+ EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00002802U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000754[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000754[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000754[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000754[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000754[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000754[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 4
+ // .. ==> 0XF8000754[11:9] = 0x00000004U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000754[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 1
+ // .. ==> 0XF8000754[13:13] = 0x00000001U
+ // .. ==> MASK : 0x00002000U VAL : 0x00002000U
+ // ..
+ EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00002802U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000758[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000758[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000758[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000758[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000758[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000758[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 4
+ // .. ==> 0XF8000758[11:9] = 0x00000004U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000758[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000758[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000803U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF800075C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF800075C[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800075C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800075C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800075C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800075C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 4
+ // .. ==> 0XF800075C[11:9] = 0x00000004U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
+ // .. PULLUP = 0
+ // .. ==> 0XF800075C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800075C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000803U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000760[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000760[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000760[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000760[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000760[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000760[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 4
+ // .. ==> 0XF8000760[11:9] = 0x00000004U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000760[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000760[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000803U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000764[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000764[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000764[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000764[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000764[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000764[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 4
+ // .. ==> 0XF8000764[11:9] = 0x00000004U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000764[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000764[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000803U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000768[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000768[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000768[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000768[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000768[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000768[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 4
+ // .. ==> 0XF8000768[11:9] = 0x00000004U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000768[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000768[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000803U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF800076C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF800076C[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800076C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800076C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800076C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800076C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 4
+ // .. ==> 0XF800076C[11:9] = 0x00000004U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
+ // .. PULLUP = 0
+ // .. ==> 0XF800076C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800076C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000803U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000770[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000770[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000770[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000770[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000770[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000770[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000770[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000770[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000770[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000774[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000774[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000774[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000774[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000774[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000774[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000774[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000774[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000774[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000778[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000778[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000778[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000778[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000778[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000778[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000778[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000778[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000778[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF800077C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800077C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF800077C[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800077C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800077C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800077C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800077C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800077C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800077C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000780[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000780[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000780[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000780[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000780[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000780[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000780[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000780[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000780[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000784[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000784[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000784[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000784[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000784[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000784[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000784[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000784[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000784[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000788[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000788[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000788[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000788[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000788[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000788[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000788[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000788[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000788[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800078C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800078C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF800078C[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800078C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800078C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800078C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800078C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800078C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800078C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000790[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000790[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000790[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000790[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000790[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000790[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000790[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000790[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000790[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000794[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000794[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000794[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000794[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000794[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000794[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000794[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000794[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000794[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000798[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000798[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000798[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000798[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000798[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000798[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000798[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000798[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000798[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800079C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800079C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF800079C[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800079C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800079C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800079C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800079C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800079C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800079C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007A0[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007A0[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007A0[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007A0[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007A0[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007A0[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007A0[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007A0[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007A0[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007A4[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007A4[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007A4[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007A4[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007A4[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007A4[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007A4[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007A4[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007A4[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007A8[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007A8[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007A8[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007A8[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007A8[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007A8[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007A8[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007A8[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007A8[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007AC[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007AC[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007AC[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007AC[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007AC[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007AC[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007AC[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007AC[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007AC[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007B0[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007B0[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007B0[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007B0[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007B0[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007B0[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007B0[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007B0[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007B0[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007B4[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007B4[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007B4[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007B4[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007B4[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007B4[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007B4[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007B4[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007B4[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000280U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF80007B8[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007B8[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007B8[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007B8[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 1
+ // .. ==> 0XF80007B8[7:5] = 0x00000001U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000020U
+ // .. Speed = 0
+ // .. ==> 0XF80007B8[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007B8[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF80007B8[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007B8[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001221U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007BC[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007BC[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007BC[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007BC[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 1
+ // .. ==> 0XF80007BC[7:5] = 0x00000001U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000020U
+ // .. Speed = 0
+ // .. ==> 0XF80007BC[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007BC[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF80007BC[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007BC[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00001220U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007C0[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007C0[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007C0[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007C0[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 7
+ // .. ==> 0XF80007C0[7:5] = 0x00000007U
+ // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U
+ // .. Speed = 0
+ // .. ==> 0XF80007C0[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007C0[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007C0[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007C0[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF80007C4[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007C4[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007C4[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007C4[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 7
+ // .. ==> 0XF80007C4[7:5] = 0x00000007U
+ // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U
+ // .. Speed = 0
+ // .. ==> 0XF80007C4[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007C4[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007C4[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007C4[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007C8[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007C8[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007C8[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007C8[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 2
+ // .. ==> 0XF80007C8[7:5] = 0x00000002U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000040U
+ // .. Speed = 0
+ // .. ==> 0XF80007C8[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007C8[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF80007C8[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007C8[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001240U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007CC[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007CC[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007CC[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007CC[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 2
+ // .. ==> 0XF80007CC[7:5] = 0x00000002U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000040U
+ // .. Speed = 0
+ // .. ==> 0XF80007CC[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007CC[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF80007CC[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007CC[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001240U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007D0[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007D0[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007D0[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007D0[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007D0[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007D0[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007D0[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007D0[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007D0[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007D4[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007D4[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007D4[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007D4[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007D4[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007D4[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007D4[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007D4[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007D4[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U),
+ // .. SDIO0_WP_SEL = 15
+ // .. ==> 0XF8000830[5:0] = 0x0000000FU
+ // .. ==> MASK : 0x0000003FU VAL : 0x0000000FU
+ // .. SDIO0_CD_SEL = 0
+ // .. ==> 0XF8000830[21:16] = 0x00000000U
+ // .. ==> MASK : 0x003F0000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x0000000FU),
+ // .. FINISH: MIO PROGRAMMING
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_peripherals_init_data_1_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+ // .. IBUF_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B48[7:7] = 0x00000001U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. TERM_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B48[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // ..
+ EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
+ // .. IBUF_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B4C[7:7] = 0x00000001U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. TERM_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B4C[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // ..
+ EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
+ // .. IBUF_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B50[7:7] = 0x00000001U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. TERM_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B50[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // ..
+ EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
+ // .. IBUF_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B54[7:7] = 0x00000001U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. TERM_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B54[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // ..
+ EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
+ // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // .. START: SRAM/NOR SET OPMODE
+ // .. FINISH: SRAM/NOR SET OPMODE
+ // .. START: UART REGISTERS
+ // .. BDIV = 0x6
+ // .. ==> 0XE0001034[7:0] = 0x00000006U
+ // .. ==> MASK : 0x000000FFU VAL : 0x00000006U
+ // ..
+ EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
+ // .. CD = 0x3e
+ // .. ==> 0XE0001018[15:0] = 0x0000003EU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU
+ // ..
+ EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
+ // .. STPBRK = 0x0
+ // .. ==> 0XE0001000[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. STTBRK = 0x0
+ // .. ==> 0XE0001000[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. RSTTO = 0x0
+ // .. ==> 0XE0001000[6:6] = 0x00000000U
+ // .. ==> MASK : 0x00000040U VAL : 0x00000000U
+ // .. TXDIS = 0x0
+ // .. ==> 0XE0001000[5:5] = 0x00000000U
+ // .. ==> MASK : 0x00000020U VAL : 0x00000000U
+ // .. TXEN = 0x1
+ // .. ==> 0XE0001000[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. RXDIS = 0x0
+ // .. ==> 0XE0001000[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. RXEN = 0x1
+ // .. ==> 0XE0001000[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. TXRES = 0x1
+ // .. ==> 0XE0001000[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. RXRES = 0x1
+ // .. ==> 0XE0001000[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // ..
+ EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
+ // .. IRMODE = 0x0
+ // .. ==> 0XE0001004[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. UCLKEN = 0x0
+ // .. ==> 0XE0001004[10:10] = 0x00000000U
+ // .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. CHMODE = 0x0
+ // .. ==> 0XE0001004[9:8] = 0x00000000U
+ // .. ==> MASK : 0x00000300U VAL : 0x00000000U
+ // .. NBSTOP = 0x0
+ // .. ==> 0XE0001004[7:6] = 0x00000000U
+ // .. ==> MASK : 0x000000C0U VAL : 0x00000000U
+ // .. PAR = 0x4
+ // .. ==> 0XE0001004[5:3] = 0x00000004U
+ // .. ==> MASK : 0x00000038U VAL : 0x00000020U
+ // .. CHRL = 0x0
+ // .. ==> 0XE0001004[2:1] = 0x00000000U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000000U
+ // .. CLKS = 0x0
+ // .. ==> 0XE0001004[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U),
+ // .. FINISH: UART REGISTERS
+ // .. START: QSPI REGISTERS
+ // .. Holdb_dr = 1
+ // .. ==> 0XE000D000[19:19] = 0x00000001U
+ // .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // ..
+ EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
+ // .. FINISH: QSPI REGISTERS
+ // .. START: PL POWER ON RESET REGISTERS
+ // .. PCFG_POR_CNT_4K = 0
+ // .. ==> 0XF8007000[29:29] = 0x00000000U
+ // .. ==> MASK : 0x20000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
+ // .. FINISH: PL POWER ON RESET REGISTERS
+ // .. START: SMC TIMING CALCULATION REGISTER UPDATE
+ // .. .. START: NAND SET CYCLE
+ // .. .. FINISH: NAND SET CYCLE
+ // .. .. START: OPMODE
+ // .. .. FINISH: OPMODE
+ // .. .. START: DIRECT COMMAND
+ // .. .. FINISH: DIRECT COMMAND
+ // .. .. START: SRAM/NOR CS0 SET CYCLE
+ // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
+ // .. .. START: DIRECT COMMAND
+ // .. .. FINISH: DIRECT COMMAND
+ // .. .. START: NOR CS0 BASE ADDRESS
+ // .. .. FINISH: NOR CS0 BASE ADDRESS
+ // .. .. START: SRAM/NOR CS1 SET CYCLE
+ // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
+ // .. .. START: DIRECT COMMAND
+ // .. .. FINISH: DIRECT COMMAND
+ // .. .. START: NOR CS1 BASE ADDRESS
+ // .. .. FINISH: NOR CS1 BASE ADDRESS
+ // .. .. START: USB RESET
+ // .. .. .. START: USB0 RESET
+ // .. .. .. .. START: DIR MODE BANK 0
+ // .. .. .. .. DIRECTION_0 = 0x80
+ // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U
+ // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U),
+ // .. .. .. .. FINISH: DIR MODE BANK 0
+ // .. .. .. .. START: DIR MODE BANK 1
+ // .. .. .. .. FINISH: DIR MODE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. MASK_0_LSW = 0xff7f
+ // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+ // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U
+ // .. .. .. .. DATA_0_LSW = 0x80
+ // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+ // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. START: OUTPUT ENABLE BANK 0
+ // .. .. .. .. OP_ENABLE_0 = 0x80
+ // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U
+ // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U),
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+ // .. .. .. .. START: OUTPUT ENABLE BANK 1
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. MASK_0_LSW = 0xff7f
+ // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+ // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U
+ // .. .. .. .. DATA_0_LSW = 0x0
+ // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+ // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U),
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. START: ADD 1 MS DELAY
+ // .. .. .. ..
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ // .. .. .. .. FINISH: ADD 1 MS DELAY
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. MASK_0_LSW = 0xff7f
+ // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+ // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U
+ // .. .. .. .. DATA_0_LSW = 0x80
+ // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+ // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. FINISH: USB0 RESET
+ // .. .. .. START: USB1 RESET
+ // .. .. .. .. START: DIR MODE BANK 0
+ // .. .. .. .. FINISH: DIR MODE BANK 0
+ // .. .. .. .. START: DIR MODE BANK 1
+ // .. .. .. .. FINISH: DIR MODE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. START: OUTPUT ENABLE BANK 0
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+ // .. .. .. .. START: OUTPUT ENABLE BANK 1
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. START: ADD 1 MS DELAY
+ // .. .. .. ..
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ // .. .. .. .. FINISH: ADD 1 MS DELAY
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. FINISH: USB1 RESET
+ // .. .. FINISH: USB RESET
+ // .. .. START: ENET RESET
+ // .. .. .. START: ENET0 RESET
+ // .. .. .. .. START: DIR MODE BANK 0
+ // .. .. .. .. DIRECTION_0 = 0x800
+ // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000800U
+ // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000800U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000800U),
+ // .. .. .. .. FINISH: DIR MODE BANK 0
+ // .. .. .. .. START: DIR MODE BANK 1
+ // .. .. .. .. FINISH: DIR MODE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. MASK_0_LSW = 0xf7ff
+ // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU
+ // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xF7FF0000U
+ // .. .. .. .. DATA_0_LSW = 0x800
+ // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000800U
+ // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000800U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0800U),
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. START: OUTPUT ENABLE BANK 0
+ // .. .. .. .. OP_ENABLE_0 = 0x800
+ // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000800U
+ // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000800U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000800U),
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+ // .. .. .. .. START: OUTPUT ENABLE BANK 1
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. MASK_0_LSW = 0xf7ff
+ // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU
+ // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xF7FF0000U
+ // .. .. .. .. DATA_0_LSW = 0x0
+ // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+ // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0000U),
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. START: ADD 1 MS DELAY
+ // .. .. .. ..
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ // .. .. .. .. FINISH: ADD 1 MS DELAY
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. MASK_0_LSW = 0xf7ff
+ // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU
+ // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xF7FF0000U
+ // .. .. .. .. DATA_0_LSW = 0x800
+ // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000800U
+ // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000800U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0800U),
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. FINISH: ENET0 RESET
+ // .. .. .. START: ENET1 RESET
+ // .. .. .. .. START: DIR MODE BANK 0
+ // .. .. .. .. FINISH: DIR MODE BANK 0
+ // .. .. .. .. START: DIR MODE BANK 1
+ // .. .. .. .. FINISH: DIR MODE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. START: OUTPUT ENABLE BANK 0
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+ // .. .. .. .. START: OUTPUT ENABLE BANK 1
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. START: ADD 1 MS DELAY
+ // .. .. .. ..
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ // .. .. .. .. FINISH: ADD 1 MS DELAY
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. FINISH: ENET1 RESET
+ // .. .. FINISH: ENET RESET
+ // .. .. START: I2C RESET
+ // .. .. .. START: I2C0 RESET
+ // .. .. .. .. START: DIR MODE GPIO BANK0
+ // .. .. .. .. DIRECTION_0 = 0x2000
+ // .. .. .. .. ==> 0XE000A204[31:0] = 0x00002000U
+ // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002000U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002000U),
+ // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+ // .. .. .. .. START: DIR MODE GPIO BANK1
+ // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. MASK_0_LSW = 0xdfff
+ // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU
+ // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xDFFF0000U
+ // .. .. .. .. DATA_0_LSW = 0x2000
+ // .. .. .. .. ==> 0XE000A000[15:0] = 0x00002000U
+ // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00002000U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF2000U),
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. START: OUTPUT ENABLE
+ // .. .. .. .. OP_ENABLE_0 = 0x2000
+ // .. .. .. .. ==> 0XE000A208[31:0] = 0x00002000U
+ // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002000U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002000U),
+ // .. .. .. .. FINISH: OUTPUT ENABLE
+ // .. .. .. .. START: OUTPUT ENABLE
+ // .. .. .. .. FINISH: OUTPUT ENABLE
+ // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. MASK_0_LSW = 0xdfff
+ // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU
+ // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xDFFF0000U
+ // .. .. .. .. DATA_0_LSW = 0x0
+ // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+ // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF0000U),
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. START: ADD 1 MS DELAY
+ // .. .. .. ..
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ // .. .. .. .. FINISH: ADD 1 MS DELAY
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. MASK_0_LSW = 0xdfff
+ // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU
+ // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xDFFF0000U
+ // .. .. .. .. DATA_0_LSW = 0x2000
+ // .. .. .. .. ==> 0XE000A000[15:0] = 0x00002000U
+ // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00002000U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF2000U),
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. FINISH: I2C0 RESET
+ // .. .. .. START: I2C1 RESET
+ // .. .. .. .. START: DIR MODE GPIO BANK0
+ // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+ // .. .. .. .. START: DIR MODE GPIO BANK1
+ // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. START: OUTPUT ENABLE
+ // .. .. .. .. FINISH: OUTPUT ENABLE
+ // .. .. .. .. START: OUTPUT ENABLE
+ // .. .. .. .. FINISH: OUTPUT ENABLE
+ // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. START: ADD 1 MS DELAY
+ // .. .. .. ..
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ // .. .. .. .. FINISH: ADD 1 MS DELAY
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. FINISH: I2C1 RESET
+ // .. .. FINISH: I2C RESET
+ // .. .. START: NOR CHIP SELECT
+ // .. .. .. START: DIR MODE BANK 0
+ // .. .. .. FINISH: DIR MODE BANK 0
+ // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. START: OUTPUT ENABLE BANK 0
+ // .. .. .. FINISH: OUTPUT ENABLE BANK 0
+ // .. .. FINISH: NOR CHIP SELECT
+ // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_post_config_1_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: ENABLING LEVEL SHIFTER
+ // .. USER_INP_ICT_EN_0 = 3
+ // .. ==> 0XF8000900[1:0] = 0x00000003U
+ // .. ==> MASK : 0x00000003U VAL : 0x00000003U
+ // .. USER_INP_ICT_EN_1 = 3
+ // .. ==> 0XF8000900[3:2] = 0x00000003U
+ // .. ==> MASK : 0x0000000CU VAL : 0x0000000CU
+ // ..
+ EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
+ // .. FINISH: ENABLING LEVEL SHIFTER
+ // .. START: FPGA RESETS TO 0
+ // .. reserved_3 = 0
+ // .. ==> 0XF8000240[31:25] = 0x00000000U
+ // .. ==> MASK : 0xFE000000U VAL : 0x00000000U
+ // .. FPGA_ACP_RST = 0
+ // .. ==> 0XF8000240[24:24] = 0x00000000U
+ // .. ==> MASK : 0x01000000U VAL : 0x00000000U
+ // .. FPGA_AXDS3_RST = 0
+ // .. ==> 0XF8000240[23:23] = 0x00000000U
+ // .. ==> MASK : 0x00800000U VAL : 0x00000000U
+ // .. FPGA_AXDS2_RST = 0
+ // .. ==> 0XF8000240[22:22] = 0x00000000U
+ // .. ==> MASK : 0x00400000U VAL : 0x00000000U
+ // .. FPGA_AXDS1_RST = 0
+ // .. ==> 0XF8000240[21:21] = 0x00000000U
+ // .. ==> MASK : 0x00200000U VAL : 0x00000000U
+ // .. FPGA_AXDS0_RST = 0
+ // .. ==> 0XF8000240[20:20] = 0x00000000U
+ // .. ==> MASK : 0x00100000U VAL : 0x00000000U
+ // .. reserved_2 = 0
+ // .. ==> 0XF8000240[19:18] = 0x00000000U
+ // .. ==> MASK : 0x000C0000U VAL : 0x00000000U
+ // .. FSSW1_FPGA_RST = 0
+ // .. ==> 0XF8000240[17:17] = 0x00000000U
+ // .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. FSSW0_FPGA_RST = 0
+ // .. ==> 0XF8000240[16:16] = 0x00000000U
+ // .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. reserved_1 = 0
+ // .. ==> 0XF8000240[15:14] = 0x00000000U
+ // .. ==> MASK : 0x0000C000U VAL : 0x00000000U
+ // .. FPGA_FMSW1_RST = 0
+ // .. ==> 0XF8000240[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // .. FPGA_FMSW0_RST = 0
+ // .. ==> 0XF8000240[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. FPGA_DMA3_RST = 0
+ // .. ==> 0XF8000240[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. FPGA_DMA2_RST = 0
+ // .. ==> 0XF8000240[10:10] = 0x00000000U
+ // .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. FPGA_DMA1_RST = 0
+ // .. ==> 0XF8000240[9:9] = 0x00000000U
+ // .. ==> MASK : 0x00000200U VAL : 0x00000000U
+ // .. FPGA_DMA0_RST = 0
+ // .. ==> 0XF8000240[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. reserved = 0
+ // .. ==> 0XF8000240[7:4] = 0x00000000U
+ // .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. FPGA3_OUT_RST = 0
+ // .. ==> 0XF8000240[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. FPGA2_OUT_RST = 0
+ // .. ==> 0XF8000240[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. FPGA1_OUT_RST = 0
+ // .. ==> 0XF8000240[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. FPGA0_OUT_RST = 0
+ // .. ==> 0XF8000240[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
+ // .. FINISH: FPGA RESETS TO 0
+ // .. START: AFI REGISTERS
+ // .. .. START: AFI0 REGISTERS
+ // .. .. FINISH: AFI0 REGISTERS
+ // .. .. START: AFI1 REGISTERS
+ // .. .. FINISH: AFI1 REGISTERS
+ // .. .. START: AFI2 REGISTERS
+ // .. .. FINISH: AFI2 REGISTERS
+ // .. .. START: AFI3 REGISTERS
+ // .. .. FINISH: AFI3 REGISTERS
+ // .. FINISH: AFI REGISTERS
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_debug_1_0[] = {
+ // START: top
+ // .. START: CROSS TRIGGER CONFIGURATIONS
+ // .. .. START: UNLOCKING CTI REGISTERS
+ // .. .. KEY = 0XC5ACCE55
+ // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
+ // .. ..
+ EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
+ // .. .. KEY = 0XC5ACCE55
+ // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
+ // .. ..
+ EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
+ // .. .. KEY = 0XC5ACCE55
+ // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
+ // .. ..
+ EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
+ // .. .. FINISH: UNLOCKING CTI REGISTERS
+ // .. .. START: ENABLING CTI MODULES AND CHANNELS
+ // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
+ // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+ // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+ // .. FINISH: CROSS TRIGGER CONFIGURATIONS
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+
+#include "xil_io.h"
+#define PS7_MASK_POLL_TIME 100000000
+
+char*
+getPS7MessageInfo(unsigned key) {
+
+ char* err_msg = "";
+ switch (key) {
+ case PS7_INIT_SUCCESS: err_msg = "PS7 initialization successful"; break;
+ case PS7_INIT_CORRUPT: err_msg = "PS7 init Data Corrupted"; break;
+ case PS7_INIT_TIMEOUT: err_msg = "PS7 init mask poll timeout"; break;
+ case PS7_POLL_FAILED_DDR_INIT: err_msg = "Mask Poll failed for DDR Init"; break;
+ case PS7_POLL_FAILED_DMA: err_msg = "Mask Poll failed for PLL Init"; break;
+ case PS7_POLL_FAILED_PLL: err_msg = "Mask Poll failed for DMA done bit"; break;
+ default: err_msg = "Undefined error status"; break;
+ }
+
+ return err_msg;
+}
+
+unsigned long
+ps7GetSiliconVersion () {
+ // Read PS version from MCTRL register [31:28]
+ unsigned long mask = 0xF0000000;
+ unsigned long *addr = (unsigned long*) 0XF8007080;
+ unsigned long ps_version = (*addr & mask) >> 28;
+ return ps_version;
+}
+
+void mask_write (unsigned long add , unsigned long mask, unsigned long val ) {
+ unsigned long *addr = (unsigned long*) add;
+ *addr = ( val & mask ) | ( *addr & ~mask);
+ //xil_printf("MaskWrite : 0x%x--> 0x%x \n \r" ,add, *addr);
+}
+
+
+int mask_poll(unsigned long add , unsigned long mask ) {
+ volatile unsigned long *addr = (volatile unsigned long*) add;
+ int i = 0;
+ while (!(*addr & mask)) {
+ if (i == PS7_MASK_POLL_TIME) {
+ return -1;
+ }
+ i++;
+ }
+ return 1;
+ //xil_printf("MaskPoll : 0x%x --> 0x%x \n \r" , add, *addr);
+}
+
+unsigned long mask_read(unsigned long add , unsigned long mask ) {
+ unsigned long *addr = (unsigned long*) add;
+ unsigned long val = (*addr & mask);
+ //xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val);
+ return val;
+}
+
+
+
+int
+ps7_config(unsigned long * ps7_config_init)
+{
+ unsigned long *ptr = ps7_config_init;
+
+ unsigned long opcode; // current instruction ..
+ unsigned long args[16]; // no opcode has so many args ...
+ int numargs; // number of arguments of this instruction
+ int j; // general purpose index
+
+ volatile unsigned long *addr; // some variable to make code readable
+ unsigned long val,mask; // some variable to make code readable
+
+ int finish = -1 ; // loop while this is negative !
+ int i = 0; // Timeout variable
+
+ while( finish < 0 ) {
+ numargs = ptr[0] & 0xF;
+ opcode = ptr[0] >> 4;
+
+ for( j = 0 ; j < numargs ; j ++ )
+ args[j] = ptr[j+1];
+ ptr += numargs + 1;
+
+
+ switch ( opcode ) {
+
+ case OPCODE_EXIT:
+ finish = PS7_INIT_SUCCESS;
+ break;
+
+ case OPCODE_CLEAR:
+ addr = (unsigned long*) args[0];
+ *addr = 0;
+ break;
+
+ case OPCODE_WRITE:
+ addr = (unsigned long*) args[0];
+ val = args[1];
+ *addr = val;
+ break;
+
+ case OPCODE_MASKWRITE:
+ addr = (unsigned long*) args[0];
+ mask = args[1];
+ val = args[2];
+ *addr = ( val & mask ) | ( *addr & ~mask);
+ break;
+
+ case OPCODE_MASKPOLL:
+ addr = (unsigned long*) args[0];
+ mask = args[1];
+ i = 0;
+ while (!(*addr & mask)) {
+ if (i == PS7_MASK_POLL_TIME) {
+ finish = PS7_INIT_TIMEOUT;
+ break;
+ }
+ i++;
+ }
+ break;
+ case OPCODE_MASKDELAY:
+ addr = (unsigned long*) args[0];
+ mask = args[1];
+ int delay = get_number_of_cycles_for_delay(mask);
+ perf_reset_and_start_timer();
+ while ((*addr < delay)) {
+ }
+ break;
+ default:
+ finish = PS7_INIT_CORRUPT;
+ break;
+ }
+ }
+ return finish;
+}
+
+unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0;
+unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0;
+unsigned long *ps7_clock_init_data = ps7_clock_init_data_3_0;
+unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0;
+unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
+
+int
+ps7_post_config()
+{
+ // Get the PS_VERSION on run time
+ unsigned long si_ver = ps7GetSiliconVersion ();
+ int ret = -1;
+ if (si_ver == PCW_SILICON_VERSION_1) {
+ ret = ps7_config (ps7_post_config_1_0);
+ if (ret != PS7_INIT_SUCCESS) return ret;
+ } else if (si_ver == PCW_SILICON_VERSION_2) {
+ ret = ps7_config (ps7_post_config_2_0);
+ if (ret != PS7_INIT_SUCCESS) return ret;
+ } else {
+ ret = ps7_config (ps7_post_config_3_0);
+ if (ret != PS7_INIT_SUCCESS) return ret;
+ }
+ return PS7_INIT_SUCCESS;
+}
+
+int
+ps7_debug()
+{
+ // Get the PS_VERSION on run time
+ unsigned long si_ver = ps7GetSiliconVersion ();
+ int ret = -1;
+ if (si_ver == PCW_SILICON_VERSION_1) {
+ ret = ps7_config (ps7_debug_1_0);
+ if (ret != PS7_INIT_SUCCESS) return ret;
+ } else if (si_ver == PCW_SILICON_VERSION_2) {
+ ret = ps7_config (ps7_debug_2_0);
+ if (ret != PS7_INIT_SUCCESS) return ret;
+ } else {
+ ret = ps7_config (ps7_debug_3_0);
+ if (ret != PS7_INIT_SUCCESS) return ret;
+ }
+ return PS7_INIT_SUCCESS;
+}
+
+int
+ps7_init()
+{
+ // Get the PS_VERSION on run time
+ unsigned long si_ver = ps7GetSiliconVersion ();
+ int ret;
+ //int pcw_ver = 0;
+
+ if (si_ver == PCW_SILICON_VERSION_1) {
+ ps7_mio_init_data = ps7_mio_init_data_1_0;
+ ps7_pll_init_data = ps7_pll_init_data_1_0;
+ ps7_clock_init_data = ps7_clock_init_data_1_0;
+ ps7_ddr_init_data = ps7_ddr_init_data_1_0;
+ ps7_peripherals_init_data = ps7_peripherals_init_data_1_0;
+ //pcw_ver = 1;
+
+ } else if (si_ver == PCW_SILICON_VERSION_2) {
+ ps7_mio_init_data = ps7_mio_init_data_2_0;
+ ps7_pll_init_data = ps7_pll_init_data_2_0;
+ ps7_clock_init_data = ps7_clock_init_data_2_0;
+ ps7_ddr_init_data = ps7_ddr_init_data_2_0;
+ ps7_peripherals_init_data = ps7_peripherals_init_data_2_0;
+ //pcw_ver = 2;
+
+ } else {
+ ps7_mio_init_data = ps7_mio_init_data_3_0;
+ ps7_pll_init_data = ps7_pll_init_data_3_0;
+ ps7_clock_init_data = ps7_clock_init_data_3_0;
+ ps7_ddr_init_data = ps7_ddr_init_data_3_0;
+ ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
+ //pcw_ver = 3;
+ }
+
+ // MIO init
+ ret = ps7_config (ps7_mio_init_data);
+ if (ret != PS7_INIT_SUCCESS) return ret;
+
+ // PLL init
+ ret = ps7_config (ps7_pll_init_data);
+ if (ret != PS7_INIT_SUCCESS) return ret;
+
+ // Clock init
+ ret = ps7_config (ps7_clock_init_data);
+ if (ret != PS7_INIT_SUCCESS) return ret;
+
+ // DDR init
+ ret = ps7_config (ps7_ddr_init_data);
+ if (ret != PS7_INIT_SUCCESS) return ret;
+
+
+
+ // Peripherals init
+ ret = ps7_config (ps7_peripherals_init_data);
+ if (ret != PS7_INIT_SUCCESS) return ret;
+ //xil_printf ("\n PCW Silicon Version : %d.0", pcw_ver);
+ return PS7_INIT_SUCCESS;
+}
+
+
+
+
+/* For delay calculation using global timer */
+
+/* start timer */
+ void perf_start_clock(void)
+{
+ *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) | // Timer Enable
+ (1 << 3) | // Auto-increment
+ (0 << 8) // Pre-scale
+ );
+}
+
+/* stop timer and reset timer count regs */
+ void perf_reset_clock(void)
+{
+ perf_disable_clock();
+ *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_L32 = 0;
+ *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_U32 = 0;
+}
+
+/* Compute mask for given delay in miliseconds*/
+int get_number_of_cycles_for_delay(unsigned int delay)
+{
+ // GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x)
+ return (APU_FREQ*delay/(2*1000));
+
+}
+
+/* stop timer */
+ void perf_disable_clock(void)
+{
+ *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = 0;
+}
+
+void perf_reset_and_start_timer()
+{
+ perf_reset_clock();
+ perf_start_clock();
+}
--- /dev/null
+
+/******************************************************************************
+*
+* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
+*
+* SPDX-License-Identifier: GPL-2.0+
+*
+*
+*******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file ps7_init.h
+*
+* This file can be included in FSBL code
+* to get prototype of ps7_init() function
+* and error codes
+*
+*****************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+//typedef unsigned int u32;
+
+
+/** do we need to make this name more unique ? **/
+//extern u32 ps7_init_data[];
+extern unsigned long * ps7_ddr_init_data;
+extern unsigned long * ps7_mio_init_data;
+extern unsigned long * ps7_pll_init_data;
+extern unsigned long * ps7_clock_init_data;
+extern unsigned long * ps7_peripherals_init_data;
+
+
+
+#define OPCODE_EXIT 0U
+#define OPCODE_CLEAR 1U
+#define OPCODE_WRITE 2U
+#define OPCODE_MASKWRITE 3U
+#define OPCODE_MASKPOLL 4U
+#define OPCODE_MASKDELAY 5U
+#define NEW_PS7_ERR_CODE 1
+
+/* Encode number of arguments in last nibble */
+#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 )
+#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr
+#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val
+#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
+#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask
+#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
+
+/* Returns codes of PS7_Init */
+#define PS7_INIT_SUCCESS (0) // 0 is success in good old C
+#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now
+#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out
+#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init
+#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit
+#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init
+
+
+/* Silicon Versions */
+#define PCW_SILICON_VERSION_1 0
+#define PCW_SILICON_VERSION_2 1
+#define PCW_SILICON_VERSION_3 2
+
+/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
+#define PS7_POST_CONFIG
+
+/* Freq of all peripherals */
+
+#define APU_FREQ 666666687
+#define DDR_FREQ 533333374
+#define DCI_FREQ 10158731
+#define QSPI_FREQ 200000000
+#define SMC_FREQ 10000000
+#define ENET0_FREQ 25000000
+#define ENET1_FREQ 10000000
+#define USB0_FREQ 60000000
+#define USB1_FREQ 60000000
+#define SDIO_FREQ 50000000
+#define UART_FREQ 50000000
+#define SPI_FREQ 10000000
+#define I2C_FREQ 111111115
+#define WDT_FREQ 111111115
+#define TTC_FREQ 50000000
+#define CAN_FREQ 23809523
+#define PCAP_FREQ 200000000
+#define TPIU_FREQ 200000000
+#define FPGA0_FREQ 50000000
+#define FPGA1_FREQ 50000000
+#define FPGA2_FREQ 50000000
+#define FPGA3_FREQ 50000000
+
+
+/* For delay calculation using global registers*/
+#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
+#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204
+#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208
+#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218
+
+int ps7_config( unsigned long*);
+int ps7_init();
+int ps7_post_config();
+int ps7_debug();
+char* getPS7MessageInfo(unsigned key);
+
+void perf_start_clock(void);
+void perf_disable_clock(void);
+void perf_reset_clock(void);
+void perf_reset_and_start_timer();
+int get_number_of_cycles_for_delay(unsigned int delay);
+#ifdef __cplusplus
+}
+#endif
--- /dev/null
+/******************************************************************************
+* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
+*
+* SPDX-License-Identifier: GPL-2.0+
+*
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file ps7_init_gpl.c
+*
+* This file is automatically generated
+*
+*****************************************************************************/
+
+#include "ps7_init_gpl.h"
+
+unsigned long ps7_pll_init_data_3_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: PLL SLCR REGISTERS
+ // .. .. START: ARM PLL INIT
+ // .. .. PLL_RES = 0x2
+ // .. .. ==> 0XF8000110[7:4] = 0x00000002U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
+ // .. .. PLL_CP = 0x2
+ // .. .. ==> 0XF8000110[11:8] = 0x00000002U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
+ // .. .. LOCK_CNT = 0xfa
+ // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
+ // .. .. .. START: UPDATE FB_DIV
+ // .. .. .. PLL_FDIV = 0x28
+ // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
+ // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
+ // .. .. .. FINISH: UPDATE FB_DIV
+ // .. .. .. START: BY PASS PLL
+ // .. .. .. PLL_BYPASS_FORCE = 1
+ // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
+ // .. .. .. FINISH: BY PASS PLL
+ // .. .. .. START: ASSERT RESET
+ // .. .. .. PLL_RESET = 1
+ // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
+ // .. .. .. FINISH: ASSERT RESET
+ // .. .. .. START: DEASSERT RESET
+ // .. .. .. PLL_RESET = 0
+ // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
+ // .. .. .. FINISH: DEASSERT RESET
+ // .. .. .. START: CHECK PLL STATUS
+ // .. .. .. ARM_PLL_LOCK = 1
+ // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ..
+ EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+ // .. .. .. FINISH: CHECK PLL STATUS
+ // .. .. .. START: REMOVE PLL BY PASS
+ // .. .. .. PLL_BYPASS_FORCE = 0
+ // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
+ // .. .. .. FINISH: REMOVE PLL BY PASS
+ // .. .. .. SRCSEL = 0x0
+ // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. .. .. DIVISOR = 0x2
+ // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
+ // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U
+ // .. .. .. CPU_6OR4XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
+ // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U
+ // .. .. .. CPU_3OR2XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
+ // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U
+ // .. .. .. CPU_2XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
+ // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U
+ // .. .. .. CPU_1XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
+ // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U
+ // .. .. .. CPU_PERI_CLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
+ // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
+ // .. .. FINISH: ARM PLL INIT
+ // .. .. START: DDR PLL INIT
+ // .. .. PLL_RES = 0x2
+ // .. .. ==> 0XF8000114[7:4] = 0x00000002U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
+ // .. .. PLL_CP = 0x2
+ // .. .. ==> 0XF8000114[11:8] = 0x00000002U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
+ // .. .. LOCK_CNT = 0x12c
+ // .. .. ==> 0XF8000114[21:12] = 0x0000012CU
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
+ // .. .. .. START: UPDATE FB_DIV
+ // .. .. .. PLL_FDIV = 0x20
+ // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
+ // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
+ // .. .. .. FINISH: UPDATE FB_DIV
+ // .. .. .. START: BY PASS PLL
+ // .. .. .. PLL_BYPASS_FORCE = 1
+ // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
+ // .. .. .. FINISH: BY PASS PLL
+ // .. .. .. START: ASSERT RESET
+ // .. .. .. PLL_RESET = 1
+ // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
+ // .. .. .. FINISH: ASSERT RESET
+ // .. .. .. START: DEASSERT RESET
+ // .. .. .. PLL_RESET = 0
+ // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
+ // .. .. .. FINISH: DEASSERT RESET
+ // .. .. .. START: CHECK PLL STATUS
+ // .. .. .. DDR_PLL_LOCK = 1
+ // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. .. ..
+ EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+ // .. .. .. FINISH: CHECK PLL STATUS
+ // .. .. .. START: REMOVE PLL BY PASS
+ // .. .. .. PLL_BYPASS_FORCE = 0
+ // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
+ // .. .. .. FINISH: REMOVE PLL BY PASS
+ // .. .. .. DDR_3XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. .. DDR_2XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. .. .. DDR_3XCLK_DIVISOR = 0x2
+ // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
+ // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U
+ // .. .. .. DDR_2XCLK_DIVISOR = 0x3
+ // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
+ // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
+ // .. .. FINISH: DDR PLL INIT
+ // .. .. START: IO PLL INIT
+ // .. .. PLL_RES = 0xc
+ // .. .. ==> 0XF8000118[7:4] = 0x0000000CU
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U
+ // .. .. PLL_CP = 0x2
+ // .. .. ==> 0XF8000118[11:8] = 0x00000002U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
+ // .. .. LOCK_CNT = 0x145
+ // .. .. ==> 0XF8000118[21:12] = 0x00000145U
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U),
+ // .. .. .. START: UPDATE FB_DIV
+ // .. .. .. PLL_FDIV = 0x1e
+ // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU
+ // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U),
+ // .. .. .. FINISH: UPDATE FB_DIV
+ // .. .. .. START: BY PASS PLL
+ // .. .. .. PLL_BYPASS_FORCE = 1
+ // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
+ // .. .. .. FINISH: BY PASS PLL
+ // .. .. .. START: ASSERT RESET
+ // .. .. .. PLL_RESET = 1
+ // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
+ // .. .. .. FINISH: ASSERT RESET
+ // .. .. .. START: DEASSERT RESET
+ // .. .. .. PLL_RESET = 0
+ // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
+ // .. .. .. FINISH: DEASSERT RESET
+ // .. .. .. START: CHECK PLL STATUS
+ // .. .. .. IO_PLL_LOCK = 1
+ // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. .. ..
+ EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+ // .. .. .. FINISH: CHECK PLL STATUS
+ // .. .. .. START: REMOVE PLL BY PASS
+ // .. .. .. PLL_BYPASS_FORCE = 0
+ // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
+ // .. .. .. FINISH: REMOVE PLL BY PASS
+ // .. .. FINISH: IO PLL INIT
+ // .. FINISH: PLL SLCR REGISTERS
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_clock_init_data_3_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: CLOCK CONTROL SLCR REGISTERS
+ // .. CLKACT = 0x1
+ // .. ==> 0XF8000128[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. DIVISOR0 = 0x23
+ // .. ==> 0XF8000128[13:8] = 0x00000023U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00002300U
+ // .. DIVISOR1 = 0x3
+ // .. ==> 0XF8000128[25:20] = 0x00000003U
+ // .. ==> MASK : 0x03F00000U VAL : 0x00300000U
+ // ..
+ EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U),
+ // .. CLKACT = 0x1
+ // .. ==> 0XF8000138[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000138[4:4] = 0x00000000U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
+ // .. CLKACT = 0x1
+ // .. ==> 0XF8000140[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000140[6:4] = 0x00000000U
+ // .. ==> MASK : 0x00000070U VAL : 0x00000000U
+ // .. DIVISOR = 0x8
+ // .. ==> 0XF8000140[13:8] = 0x00000008U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00000800U
+ // .. DIVISOR1 = 0x5
+ // .. ==> 0XF8000140[25:20] = 0x00000005U
+ // .. ==> MASK : 0x03F00000U VAL : 0x00500000U
+ // ..
+ EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00500801U),
+ // .. CLKACT = 0x1
+ // .. ==> 0XF800014C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF800014C[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR = 0x5
+ // .. ==> 0XF800014C[13:8] = 0x00000005U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00000500U
+ // ..
+ EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
+ // .. CLKACT0 = 0x1
+ // .. ==> 0XF8000150[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. CLKACT1 = 0x0
+ // .. ==> 0XF8000150[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000150[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR = 0x14
+ // .. ==> 0XF8000150[13:8] = 0x00000014U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
+ // ..
+ EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U),
+ // .. CLKACT0 = 0x0
+ // .. ==> 0XF8000154[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. CLKACT1 = 0x1
+ // .. ==> 0XF8000154[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000154[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR = 0x14
+ // .. ==> 0XF8000154[13:8] = 0x00000014U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
+ // ..
+ EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U),
+ // .. CLKACT = 0x1
+ // .. ==> 0XF8000168[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000168[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR = 0x5
+ // .. ==> 0XF8000168[13:8] = 0x00000005U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00000500U
+ // ..
+ EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000170[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR0 = 0x14
+ // .. ==> 0XF8000170[13:8] = 0x00000014U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
+ // .. DIVISOR1 = 0x1
+ // .. ==> 0XF8000170[25:20] = 0x00000001U
+ // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
+ // ..
+ EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00101400U),
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000180[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR0 = 0x14
+ // .. ==> 0XF8000180[13:8] = 0x00000014U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
+ // .. DIVISOR1 = 0x1
+ // .. ==> 0XF8000180[25:20] = 0x00000001U
+ // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
+ // ..
+ EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00101400U),
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000190[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR0 = 0x14
+ // .. ==> 0XF8000190[13:8] = 0x00000014U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
+ // .. DIVISOR1 = 0x1
+ // .. ==> 0XF8000190[25:20] = 0x00000001U
+ // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
+ // ..
+ EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101400U),
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF80001A0[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR0 = 0x14
+ // .. ==> 0XF80001A0[13:8] = 0x00000014U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
+ // .. DIVISOR1 = 0x1
+ // .. ==> 0XF80001A0[25:20] = 0x00000001U
+ // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
+ // ..
+ EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U),
+ // .. CLK_621_TRUE = 0x1
+ // .. ==> 0XF80001C4[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // ..
+ EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
+ // .. DMA_CPU_2XCLKACT = 0x1
+ // .. ==> 0XF800012C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. USB0_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. USB1_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[3:3] = 0x00000001U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000008U
+ // .. GEM0_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[6:6] = 0x00000001U
+ // .. ==> MASK : 0x00000040U VAL : 0x00000040U
+ // .. GEM1_CPU_1XCLKACT = 0x0
+ // .. ==> 0XF800012C[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. SDI0_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[10:10] = 0x00000001U
+ // .. ==> MASK : 0x00000400U VAL : 0x00000400U
+ // .. SDI1_CPU_1XCLKACT = 0x0
+ // .. ==> 0XF800012C[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. SPI0_CPU_1XCLKACT = 0x0
+ // .. ==> 0XF800012C[14:14] = 0x00000000U
+ // .. ==> MASK : 0x00004000U VAL : 0x00000000U
+ // .. SPI1_CPU_1XCLKACT = 0x0
+ // .. ==> 0XF800012C[15:15] = 0x00000000U
+ // .. ==> MASK : 0x00008000U VAL : 0x00000000U
+ // .. CAN0_CPU_1XCLKACT = 0x0
+ // .. ==> 0XF800012C[16:16] = 0x00000000U
+ // .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. CAN1_CPU_1XCLKACT = 0x0
+ // .. ==> 0XF800012C[17:17] = 0x00000000U
+ // .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. I2C0_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[18:18] = 0x00000001U
+ // .. ==> MASK : 0x00040000U VAL : 0x00040000U
+ // .. I2C1_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[19:19] = 0x00000001U
+ // .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // .. UART0_CPU_1XCLKACT = 0x0
+ // .. ==> 0XF800012C[20:20] = 0x00000000U
+ // .. ==> MASK : 0x00100000U VAL : 0x00000000U
+ // .. UART1_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[21:21] = 0x00000001U
+ // .. ==> MASK : 0x00200000U VAL : 0x00200000U
+ // .. GPIO_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[22:22] = 0x00000001U
+ // .. ==> MASK : 0x00400000U VAL : 0x00400000U
+ // .. LQSPI_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[23:23] = 0x00000001U
+ // .. ==> MASK : 0x00800000U VAL : 0x00800000U
+ // .. SMC_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[24:24] = 0x00000001U
+ // .. ==> MASK : 0x01000000U VAL : 0x01000000U
+ // ..
+ EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC044DU),
+ // .. FINISH: CLOCK CONTROL SLCR REGISTERS
+ // .. START: THIS SHOULD BE BLANK
+ // .. FINISH: THIS SHOULD BE BLANK
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_ddr_init_data_3_0[] = {
+ // START: top
+ // .. START: DDR INITIALIZATION
+ // .. .. START: LOCK DDR
+ // .. .. reg_ddrc_soft_rstb = 0
+ // .. .. ==> 0XF8006000[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_powerdown_en = 0x0
+ // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_ddrc_data_bus_width = 0x0
+ // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U
+ // .. .. reg_ddrc_burst8_refresh = 0x0
+ // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U
+ // .. .. reg_ddrc_rdwr_idle_gap = 0x1
+ // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+ // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U
+ // .. .. reg_ddrc_dis_rd_bypass = 0x0
+ // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+ // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_act_bypass = 0x0
+ // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_auto_refresh = 0x0
+ // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
+ // .. .. FINISH: LOCK DDR
+ // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81
+ // .. .. ==> 0XF8006004[11:0] = 0x00000081U
+ // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U
+ // .. .. reserved_reg_ddrc_active_ranks = 0x1
+ // .. .. ==> 0XF8006004[13:12] = 0x00000001U
+ // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U
+ // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
+ // .. .. ==> 0XF8006004[18:14] = 0x00000000U
+ // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU ,0x00001081U),
+ // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
+ // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU
+ // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
+ // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
+ // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U
+ // .. .. reg_ddrc_hpr_xact_run_length = 0xf
+ // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
+ // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
+ // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
+ // .. .. ==> 0XF800600C[10:0] = 0x00000001U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U
+ // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
+ // .. .. ==> 0XF800600C[21:11] = 0x00000002U
+ // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U
+ // .. .. reg_ddrc_lpr_xact_run_length = 0x8
+ // .. .. ==> 0XF800600C[25:22] = 0x00000008U
+ // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
+ // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
+ // .. .. ==> 0XF8006010[10:0] = 0x00000001U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U
+ // .. .. reg_ddrc_w_xact_run_length = 0x8
+ // .. .. ==> 0XF8006010[14:11] = 0x00000008U
+ // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U
+ // .. .. reg_ddrc_w_max_starve_x32 = 0x2
+ // .. .. ==> 0XF8006010[25:15] = 0x00000002U
+ // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
+ // .. .. reg_ddrc_t_rc = 0x1b
+ // .. .. ==> 0XF8006014[5:0] = 0x0000001BU
+ // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001BU
+ // .. .. reg_ddrc_t_rfc_min = 0x56
+ // .. .. ==> 0XF8006014[13:6] = 0x00000056U
+ // .. .. ==> MASK : 0x00003FC0U VAL : 0x00001580U
+ // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
+ // .. .. ==> 0XF8006014[20:14] = 0x00000010U
+ // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004159BU),
+ // .. .. reg_ddrc_wr2pre = 0x12
+ // .. .. ==> 0XF8006018[4:0] = 0x00000012U
+ // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U
+ // .. .. reg_ddrc_powerdown_to_x32 = 0x6
+ // .. .. ==> 0XF8006018[9:5] = 0x00000006U
+ // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U
+ // .. .. reg_ddrc_t_faw = 0x10
+ // .. .. ==> 0XF8006018[15:10] = 0x00000010U
+ // .. .. ==> MASK : 0x0000FC00U VAL : 0x00004000U
+ // .. .. reg_ddrc_t_ras_max = 0x24
+ // .. .. ==> 0XF8006018[21:16] = 0x00000024U
+ // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U
+ // .. .. reg_ddrc_t_ras_min = 0x14
+ // .. .. ==> 0XF8006018[26:22] = 0x00000014U
+ // .. .. ==> MASK : 0x07C00000U VAL : 0x05000000U
+ // .. .. reg_ddrc_t_cke = 0x4
+ // .. .. ==> 0XF8006018[31:28] = 0x00000004U
+ // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x452440D2U),
+ // .. .. reg_ddrc_write_latency = 0x5
+ // .. .. ==> 0XF800601C[4:0] = 0x00000005U
+ // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U
+ // .. .. reg_ddrc_rd2wr = 0x7
+ // .. .. ==> 0XF800601C[9:5] = 0x00000007U
+ // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U
+ // .. .. reg_ddrc_wr2rd = 0xe
+ // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
+ // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U
+ // .. .. reg_ddrc_t_xp = 0x4
+ // .. .. ==> 0XF800601C[19:15] = 0x00000004U
+ // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U
+ // .. .. reg_ddrc_pad_pd = 0x0
+ // .. .. ==> 0XF800601C[22:20] = 0x00000000U
+ // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U
+ // .. .. reg_ddrc_rd2pre = 0x4
+ // .. .. ==> 0XF800601C[27:23] = 0x00000004U
+ // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U
+ // .. .. reg_ddrc_t_rcd = 0x7
+ // .. .. ==> 0XF800601C[31:28] = 0x00000007U
+ // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
+ // .. .. reg_ddrc_t_ccd = 0x4
+ // .. .. ==> 0XF8006020[4:2] = 0x00000004U
+ // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U
+ // .. .. reg_ddrc_t_rrd = 0x4
+ // .. .. ==> 0XF8006020[7:5] = 0x00000004U
+ // .. .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. .. reg_ddrc_refresh_margin = 0x2
+ // .. .. ==> 0XF8006020[11:8] = 0x00000002U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
+ // .. .. reg_ddrc_t_rp = 0x7
+ // .. .. ==> 0XF8006020[15:12] = 0x00000007U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U
+ // .. .. reg_ddrc_refresh_to_x32 = 0x8
+ // .. .. ==> 0XF8006020[20:16] = 0x00000008U
+ // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U
+ // .. .. reg_ddrc_mobile = 0x0
+ // .. .. ==> 0XF8006020[22:22] = 0x00000000U
+ // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U
+ // .. .. reg_ddrc_en_dfi_dram_clk_disable = 0x0
+ // .. .. ==> 0XF8006020[23:23] = 0x00000000U
+ // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U
+ // .. .. reg_ddrc_read_latency = 0x7
+ // .. .. ==> 0XF8006020[28:24] = 0x00000007U
+ // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U
+ // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
+ // .. .. ==> 0XF8006020[29:29] = 0x00000001U
+ // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U
+ // .. .. reg_ddrc_dis_pad_pd = 0x0
+ // .. .. ==> 0XF8006020[30:30] = 0x00000000U
+ // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU ,0x27087290U),
+ // .. .. reg_ddrc_en_2t_timing_mode = 0x0
+ // .. .. ==> 0XF8006024[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_prefer_write = 0x0
+ // .. .. ==> 0XF8006024[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr_wr = 0x0
+ // .. .. ==> 0XF8006024[6:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr_addr = 0x0
+ // .. .. ==> 0XF8006024[8:7] = 0x00000000U
+ // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr_data = 0x0
+ // .. .. ==> 0XF8006024[24:9] = 0x00000000U
+ // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U
+ // .. .. ddrc_reg_mr_wr_busy = 0x0
+ // .. .. ==> 0XF8006024[25:25] = 0x00000000U
+ // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr_type = 0x0
+ // .. .. ==> 0XF8006024[26:26] = 0x00000000U
+ // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr_rdata_valid = 0x0
+ // .. .. ==> 0XF8006024[27:27] = 0x00000000U
+ // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U ,0x00000000U),
+ // .. .. reg_ddrc_final_wait_x32 = 0x7
+ // .. .. ==> 0XF8006028[6:0] = 0x00000007U
+ // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U
+ // .. .. reg_ddrc_pre_ocd_x32 = 0x0
+ // .. .. ==> 0XF8006028[10:7] = 0x00000000U
+ // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U
+ // .. .. reg_ddrc_t_mrd = 0x4
+ // .. .. ==> 0XF8006028[13:11] = 0x00000004U
+ // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
+ // .. .. reg_ddrc_emr2 = 0x8
+ // .. .. ==> 0XF800602C[15:0] = 0x00000008U
+ // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U
+ // .. .. reg_ddrc_emr3 = 0x0
+ // .. .. ==> 0XF800602C[31:16] = 0x00000000U
+ // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
+ // .. .. reg_ddrc_mr = 0x930
+ // .. .. ==> 0XF8006030[15:0] = 0x00000930U
+ // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U
+ // .. .. reg_ddrc_emr = 0x4
+ // .. .. ==> 0XF8006030[31:16] = 0x00000004U
+ // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
+ // .. .. reg_ddrc_burst_rdwr = 0x4
+ // .. .. ==> 0XF8006034[3:0] = 0x00000004U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U
+ // .. .. reg_ddrc_pre_cke_x1024 = 0x105
+ // .. .. ==> 0XF8006034[13:4] = 0x00000105U
+ // .. .. ==> MASK : 0x00003FF0U VAL : 0x00001050U
+ // .. .. reg_ddrc_post_cke_x1024 = 0x1
+ // .. .. ==> 0XF8006034[25:16] = 0x00000001U
+ // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U
+ // .. .. reg_ddrc_burstchop = 0x0
+ // .. .. ==> 0XF8006034[28:28] = 0x00000000U
+ // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U),
+ // .. .. reg_ddrc_force_low_pri_n = 0x0
+ // .. .. ==> 0XF8006038[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_dq = 0x0
+ // .. .. ==> 0XF8006038[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006038, 0x00000003U ,0x00000000U),
+ // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
+ // .. .. ==> 0XF800603C[3:0] = 0x00000007U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U
+ // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
+ // .. .. ==> 0XF800603C[7:4] = 0x00000007U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U
+ // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
+ // .. .. ==> 0XF800603C[11:8] = 0x00000007U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U
+ // .. .. reg_ddrc_addrmap_col_b5 = 0x0
+ // .. .. ==> 0XF800603C[15:12] = 0x00000000U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b6 = 0x0
+ // .. .. ==> 0XF800603C[19:16] = 0x00000000U
+ // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
+ // .. .. reg_ddrc_addrmap_col_b2 = 0x0
+ // .. .. ==> 0XF8006040[3:0] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b3 = 0x0
+ // .. .. ==> 0XF8006040[7:4] = 0x00000000U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b4 = 0x0
+ // .. .. ==> 0XF8006040[11:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b7 = 0x0
+ // .. .. ==> 0XF8006040[15:12] = 0x00000000U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b8 = 0x0
+ // .. .. ==> 0XF8006040[19:16] = 0x00000000U
+ // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b9 = 0xf
+ // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
+ // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U
+ // .. .. reg_ddrc_addrmap_col_b10 = 0xf
+ // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
+ // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U
+ // .. .. reg_ddrc_addrmap_col_b11 = 0xf
+ // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
+ // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
+ // .. .. reg_ddrc_addrmap_row_b0 = 0x6
+ // .. .. ==> 0XF8006044[3:0] = 0x00000006U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U
+ // .. .. reg_ddrc_addrmap_row_b1 = 0x6
+ // .. .. ==> 0XF8006044[7:4] = 0x00000006U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U
+ // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
+ // .. .. ==> 0XF8006044[11:8] = 0x00000006U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U
+ // .. .. reg_ddrc_addrmap_row_b12 = 0x6
+ // .. .. ==> 0XF8006044[15:12] = 0x00000006U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U
+ // .. .. reg_ddrc_addrmap_row_b13 = 0x6
+ // .. .. ==> 0XF8006044[19:16] = 0x00000006U
+ // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U
+ // .. .. reg_ddrc_addrmap_row_b14 = 0x6
+ // .. .. ==> 0XF8006044[23:20] = 0x00000006U
+ // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U
+ // .. .. reg_ddrc_addrmap_row_b15 = 0xf
+ // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
+ // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U),
+ // .. .. reg_phy_rd_local_odt = 0x0
+ // .. .. ==> 0XF8006048[13:12] = 0x00000000U
+ // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U
+ // .. .. reg_phy_wr_local_odt = 0x3
+ // .. .. ==> 0XF8006048[15:14] = 0x00000003U
+ // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U
+ // .. .. reg_phy_idle_local_odt = 0x3
+ // .. .. ==> 0XF8006048[17:16] = 0x00000003U
+ // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006048, 0x0003F000U ,0x0003C000U),
+ // .. .. reg_phy_rd_cmd_to_data = 0x0
+ // .. .. ==> 0XF8006050[3:0] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
+ // .. .. reg_phy_wr_cmd_to_data = 0x0
+ // .. .. ==> 0XF8006050[7:4] = 0x00000000U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. .. reg_phy_rdc_we_to_re_delay = 0x8
+ // .. .. ==> 0XF8006050[11:8] = 0x00000008U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U
+ // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
+ // .. .. ==> 0XF8006050[15:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
+ // .. .. reg_phy_use_fixed_re = 0x1
+ // .. .. ==> 0XF8006050[16:16] = 0x00000001U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U
+ // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
+ // .. .. ==> 0XF8006050[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
+ // .. .. ==> 0XF8006050[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_phy_clk_stall_level = 0x0
+ // .. .. ==> 0XF8006050[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
+ // .. .. ==> 0XF8006050[27:24] = 0x00000007U
+ // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U
+ // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
+ // .. .. ==> 0XF8006050[31:28] = 0x00000007U
+ // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
+ // .. .. reg_ddrc_dis_dll_calib = 0x0
+ // .. .. ==> 0XF8006058[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006058, 0x00010000U ,0x00000000U),
+ // .. .. reg_ddrc_rd_odt_delay = 0x3
+ // .. .. ==> 0XF800605C[3:0] = 0x00000003U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U
+ // .. .. reg_ddrc_wr_odt_delay = 0x0
+ // .. .. ==> 0XF800605C[7:4] = 0x00000000U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. .. reg_ddrc_rd_odt_hold = 0x0
+ // .. .. ==> 0XF800605C[11:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U
+ // .. .. reg_ddrc_wr_odt_hold = 0x5
+ // .. .. ==> 0XF800605C[15:12] = 0x00000005U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
+ // .. .. reg_ddrc_pageclose = 0x0
+ // .. .. ==> 0XF8006060[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_lpr_num_entries = 0x1f
+ // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
+ // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU
+ // .. .. reg_ddrc_auto_pre_en = 0x0
+ // .. .. ==> 0XF8006060[7:7] = 0x00000000U
+ // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. .. reg_ddrc_refresh_update_level = 0x0
+ // .. .. ==> 0XF8006060[8:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_wc = 0x0
+ // .. .. ==> 0XF8006060[9:9] = 0x00000000U
+ // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_collision_page_opt = 0x0
+ // .. .. ==> 0XF8006060[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_ddrc_selfref_en = 0x0
+ // .. .. ==> 0XF8006060[12:12] = 0x00000000U
+ // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
+ // .. .. reg_ddrc_go2critical_hysteresis = 0x0
+ // .. .. ==> 0XF8006064[12:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U
+ // .. .. reg_arb_go2critical_en = 0x1
+ // .. .. ==> 0XF8006064[17:17] = 0x00000001U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
+ // .. .. reg_ddrc_wrlvl_ww = 0x41
+ // .. .. ==> 0XF8006068[7:0] = 0x00000041U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U
+ // .. .. reg_ddrc_rdlvl_rr = 0x41
+ // .. .. ==> 0XF8006068[15:8] = 0x00000041U
+ // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U
+ // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
+ // .. .. ==> 0XF8006068[25:16] = 0x00000028U
+ // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
+ // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
+ // .. .. ==> 0XF800606C[7:0] = 0x00000010U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U
+ // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
+ // .. .. ==> 0XF800606C[15:8] = 0x00000016U
+ // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U
+ // .. ..
+ EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
+ // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1
+ // .. .. ==> 0XF8006078[3:0] = 0x00000001U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U
+ // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1
+ // .. .. ==> 0XF8006078[7:4] = 0x00000001U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U
+ // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1
+ // .. .. ==> 0XF8006078[11:8] = 0x00000001U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U
+ // .. .. reg_ddrc_t_cksre = 0x6
+ // .. .. ==> 0XF8006078[15:12] = 0x00000006U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U
+ // .. .. reg_ddrc_t_cksrx = 0x6
+ // .. .. ==> 0XF8006078[19:16] = 0x00000006U
+ // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U
+ // .. .. reg_ddrc_t_ckesr = 0x4
+ // .. .. ==> 0XF8006078[25:20] = 0x00000004U
+ // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U),
+ // .. .. reg_ddrc_t_ckpde = 0x2
+ // .. .. ==> 0XF800607C[3:0] = 0x00000002U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U
+ // .. .. reg_ddrc_t_ckpdx = 0x2
+ // .. .. ==> 0XF800607C[7:4] = 0x00000002U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
+ // .. .. reg_ddrc_t_ckdpde = 0x2
+ // .. .. ==> 0XF800607C[11:8] = 0x00000002U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
+ // .. .. reg_ddrc_t_ckdpdx = 0x2
+ // .. .. ==> 0XF800607C[15:12] = 0x00000002U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U
+ // .. .. reg_ddrc_t_ckcsx = 0x3
+ // .. .. ==> 0XF800607C[19:16] = 0x00000003U
+ // .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U),
+ // .. .. reg_ddrc_dis_auto_zq = 0x0
+ // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_ddr3 = 0x1
+ // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. .. reg_ddrc_t_mod = 0x200
+ // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
+ // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U
+ // .. .. reg_ddrc_t_zq_long_nop = 0x200
+ // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U
+ // .. .. reg_ddrc_t_zq_short_nop = 0x40
+ // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
+ // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
+ // .. .. t_zq_short_interval_x1024 = 0xcb73
+ // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U
+ // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U
+ // .. .. dram_rstn_x1024 = 0x69
+ // .. .. ==> 0XF80060A8[27:20] = 0x00000069U
+ // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
+ // .. .. deeppowerdown_en = 0x0
+ // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. deeppowerdown_to_x1024 = 0xff
+ // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
+ // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU
+ // .. ..
+ EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
+ // .. .. dfi_wrlvl_max_x1024 = 0xfff
+ // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
+ // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU
+ // .. .. dfi_rdlvl_max_x1024 = 0xfff
+ // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
+ // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U
+ // .. .. ddrc_reg_twrlvl_max_error = 0x0
+ // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
+ // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U
+ // .. .. ddrc_reg_trdlvl_max_error = 0x0
+ // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
+ // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dfi_wr_level_en = 0x1
+ // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
+ // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U
+ // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
+ // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
+ // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U
+ // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
+ // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
+ // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
+ // .. .. reg_ddrc_skip_ocd = 0x1
+ // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
+ // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060B4, 0x00000200U ,0x00000200U),
+ // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
+ // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
+ // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U
+ // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
+ // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
+ // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U
+ // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
+ // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
+ // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
+ // .. .. START: RESET ECC ERROR
+ // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1
+ // .. .. ==> 0XF80060C4[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. Clear_Correctable_DRAM_ECC_error = 1
+ // .. .. ==> 0XF80060C4[1:1] = 0x00000001U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U),
+ // .. .. FINISH: RESET ECC ERROR
+ // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
+ // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
+ // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
+ // .. .. CORR_ECC_LOG_VALID = 0x0
+ // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. ECC_CORRECTED_BIT_NUM = 0x0
+ // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
+ // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
+ // .. .. UNCORR_ECC_LOG_VALID = 0x0
+ // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
+ // .. .. STAT_NUM_CORR_ERR = 0x0
+ // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
+ // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U
+ // .. .. STAT_NUM_UNCORR_ERR = 0x0
+ // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
+ // .. .. reg_ddrc_ecc_mode = 0x0
+ // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_scrub = 0x1
+ // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
+ // .. .. reg_phy_dif_on = 0x0
+ // .. .. ==> 0XF8006114[3:0] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
+ // .. .. reg_phy_dif_off = 0x0
+ // .. .. ==> 0XF8006114[7:4] = 0x00000000U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
+ // .. .. reg_phy_data_slice_in_use = 0x1
+ // .. .. ==> 0XF8006118[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_phy_rdlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006118[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006118[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_wrlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006118[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_bist_shift_dq = 0x0
+ // .. .. ==> 0XF8006118[14:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
+ // .. .. reg_phy_bist_err_clr = 0x0
+ // .. .. ==> 0XF8006118[23:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
+ // .. .. reg_phy_dq_offset = 0x40
+ // .. .. ==> 0XF8006118[30:24] = 0x00000040U
+ // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU ,0x40000001U),
+ // .. .. reg_phy_data_slice_in_use = 0x1
+ // .. .. ==> 0XF800611C[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_phy_rdlvl_inc_mode = 0x0
+ // .. .. ==> 0XF800611C[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_inc_mode = 0x0
+ // .. .. ==> 0XF800611C[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_wrlvl_inc_mode = 0x0
+ // .. .. ==> 0XF800611C[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_bist_shift_dq = 0x0
+ // .. .. ==> 0XF800611C[14:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
+ // .. .. reg_phy_bist_err_clr = 0x0
+ // .. .. ==> 0XF800611C[23:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
+ // .. .. reg_phy_dq_offset = 0x40
+ // .. .. ==> 0XF800611C[30:24] = 0x00000040U
+ // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU ,0x40000001U),
+ // .. .. reg_phy_data_slice_in_use = 0x1
+ // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_phy_rdlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_wrlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_bist_shift_dq = 0x0
+ // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
+ // .. .. reg_phy_bist_err_clr = 0x0
+ // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
+ // .. .. reg_phy_dq_offset = 0x40
+ // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+ // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU ,0x40000001U),
+ // .. .. reg_phy_data_slice_in_use = 0x1
+ // .. .. ==> 0XF8006124[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_phy_rdlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006124[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006124[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_wrlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006124[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_bist_shift_dq = 0x0
+ // .. .. ==> 0XF8006124[14:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
+ // .. .. reg_phy_bist_err_clr = 0x0
+ // .. .. ==> 0XF8006124[23:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
+ // .. .. reg_phy_dq_offset = 0x40
+ // .. .. ==> 0XF8006124[30:24] = 0x00000040U
+ // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU ,0x40000001U),
+ // .. .. reg_phy_wrlvl_init_ratio = 0x1e
+ // .. .. ==> 0XF800612C[9:0] = 0x0000001EU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x0000001EU
+ // .. .. reg_phy_gatelvl_init_ratio = 0xee
+ // .. .. ==> 0XF800612C[19:10] = 0x000000EEU
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x0003B800U
+ // .. ..
+ EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0003B81EU),
+ // .. .. reg_phy_wrlvl_init_ratio = 0x25
+ // .. .. ==> 0XF8006130[9:0] = 0x00000025U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000025U
+ // .. .. reg_phy_gatelvl_init_ratio = 0x10d
+ // .. .. ==> 0XF8006130[19:10] = 0x0000010DU
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x00043400U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00043425U),
+ // .. .. reg_phy_wrlvl_init_ratio = 0x19
+ // .. .. ==> 0XF8006134[9:0] = 0x00000019U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000019U
+ // .. .. reg_phy_gatelvl_init_ratio = 0xf3
+ // .. .. ==> 0XF8006134[19:10] = 0x000000F3U
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x0003CC00U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0003CC19U),
+ // .. .. reg_phy_wrlvl_init_ratio = 0x2a
+ // .. .. ==> 0XF8006138[9:0] = 0x0000002AU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x0000002AU
+ // .. .. reg_phy_gatelvl_init_ratio = 0x109
+ // .. .. ==> 0XF8006138[19:10] = 0x00000109U
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x00042400U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0004242AU),
+ // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+ // .. .. ==> 0XF8006140[9:0] = 0x00000035U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
+ // .. .. reg_phy_rd_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006140[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006140[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
+ // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+ // .. .. ==> 0XF8006144[9:0] = 0x00000035U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
+ // .. .. reg_phy_rd_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006144[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006144[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
+ // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+ // .. .. ==> 0XF8006148[9:0] = 0x00000035U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
+ // .. .. reg_phy_rd_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006148[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006148[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
+ // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+ // .. .. ==> 0XF800614C[9:0] = 0x00000035U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
+ // .. .. reg_phy_rd_dqs_slave_force = 0x0
+ // .. .. ==> 0XF800614C[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF800614C[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
+ // .. .. reg_phy_wr_dqs_slave_ratio = 0x9e
+ // .. .. ==> 0XF8006154[9:0] = 0x0000009EU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x0000009EU
+ // .. .. reg_phy_wr_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006154[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006154[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x0000009EU),
+ // .. .. reg_phy_wr_dqs_slave_ratio = 0xa5
+ // .. .. ==> 0XF8006158[9:0] = 0x000000A5U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000A5U
+ // .. .. reg_phy_wr_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006158[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006158[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x000000A5U),
+ // .. .. reg_phy_wr_dqs_slave_ratio = 0x99
+ // .. .. ==> 0XF800615C[9:0] = 0x00000099U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000099U
+ // .. .. reg_phy_wr_dqs_slave_force = 0x0
+ // .. .. ==> 0XF800615C[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF800615C[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000099U),
+ // .. .. reg_phy_wr_dqs_slave_ratio = 0xaa
+ // .. .. ==> 0XF8006160[9:0] = 0x000000AAU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000AAU
+ // .. .. reg_phy_wr_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006160[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006160[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x000000AAU),
+ // .. .. reg_phy_fifo_we_slave_ratio = 0x143
+ // .. .. ==> 0XF8006168[10:0] = 0x00000143U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000143U
+ // .. .. reg_phy_fifo_we_in_force = 0x0
+ // .. .. ==> 0XF8006168[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. reg_phy_fifo_we_in_delay = 0x0
+ // .. .. ==> 0XF8006168[20:12] = 0x00000000U
+ // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000143U),
+ // .. .. reg_phy_fifo_we_slave_ratio = 0x162
+ // .. .. ==> 0XF800616C[10:0] = 0x00000162U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000162U
+ // .. .. reg_phy_fifo_we_in_force = 0x0
+ // .. .. ==> 0XF800616C[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. reg_phy_fifo_we_in_delay = 0x0
+ // .. .. ==> 0XF800616C[20:12] = 0x00000000U
+ // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x00000162U),
+ // .. .. reg_phy_fifo_we_slave_ratio = 0x148
+ // .. .. ==> 0XF8006170[10:0] = 0x00000148U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000148U
+ // .. .. reg_phy_fifo_we_in_force = 0x0
+ // .. .. ==> 0XF8006170[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. reg_phy_fifo_we_in_delay = 0x0
+ // .. .. ==> 0XF8006170[20:12] = 0x00000000U
+ // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000148U),
+ // .. .. reg_phy_fifo_we_slave_ratio = 0x15e
+ // .. .. ==> 0XF8006174[10:0] = 0x0000015EU
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x0000015EU
+ // .. .. reg_phy_fifo_we_in_force = 0x0
+ // .. .. ==> 0XF8006174[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. reg_phy_fifo_we_in_delay = 0x0
+ // .. .. ==> 0XF8006174[20:12] = 0x00000000U
+ // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x0000015EU),
+ // .. .. reg_phy_wr_data_slave_ratio = 0xde
+ // .. .. ==> 0XF800617C[9:0] = 0x000000DEU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000DEU
+ // .. .. reg_phy_wr_data_slave_force = 0x0
+ // .. .. ==> 0XF800617C[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_data_slave_delay = 0x0
+ // .. .. ==> 0XF800617C[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000DEU),
+ // .. .. reg_phy_wr_data_slave_ratio = 0xe5
+ // .. .. ==> 0XF8006180[9:0] = 0x000000E5U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000E5U
+ // .. .. reg_phy_wr_data_slave_force = 0x0
+ // .. .. ==> 0XF8006180[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_data_slave_delay = 0x0
+ // .. .. ==> 0XF8006180[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000E5U),
+ // .. .. reg_phy_wr_data_slave_ratio = 0xd9
+ // .. .. ==> 0XF8006184[9:0] = 0x000000D9U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000D9U
+ // .. .. reg_phy_wr_data_slave_force = 0x0
+ // .. .. ==> 0XF8006184[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_data_slave_delay = 0x0
+ // .. .. ==> 0XF8006184[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000D9U),
+ // .. .. reg_phy_wr_data_slave_ratio = 0xea
+ // .. .. ==> 0XF8006188[9:0] = 0x000000EAU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000EAU
+ // .. .. reg_phy_wr_data_slave_force = 0x0
+ // .. .. ==> 0XF8006188[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_data_slave_delay = 0x0
+ // .. .. ==> 0XF8006188[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000EAU),
+ // .. .. reg_phy_bl2 = 0x0
+ // .. .. ==> 0XF8006190[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_at_spd_atpg = 0x0
+ // .. .. ==> 0XF8006190[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_bist_enable = 0x0
+ // .. .. ==> 0XF8006190[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_bist_force_err = 0x0
+ // .. .. ==> 0XF8006190[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reg_phy_bist_mode = 0x0
+ // .. .. ==> 0XF8006190[6:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U
+ // .. .. reg_phy_invert_clkout = 0x1
+ // .. .. ==> 0XF8006190[7:7] = 0x00000001U
+ // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. .. reg_phy_sel_logic = 0x0
+ // .. .. ==> 0XF8006190[9:9] = 0x00000000U
+ // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U
+ // .. .. reg_phy_ctrl_slave_ratio = 0x100
+ // .. .. ==> 0XF8006190[19:10] = 0x00000100U
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U
+ // .. .. reg_phy_ctrl_slave_force = 0x0
+ // .. .. ==> 0XF8006190[20:20] = 0x00000000U
+ // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U
+ // .. .. reg_phy_ctrl_slave_delay = 0x0
+ // .. .. ==> 0XF8006190[27:21] = 0x00000000U
+ // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U
+ // .. .. reg_phy_lpddr = 0x0
+ // .. .. ==> 0XF8006190[29:29] = 0x00000000U
+ // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U
+ // .. .. reg_phy_cmd_latency = 0x0
+ // .. .. ==> 0XF8006190[30:30] = 0x00000000U
+ // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU ,0x00040080U),
+ // .. .. reg_phy_wr_rl_delay = 0x2
+ // .. .. ==> 0XF8006194[4:0] = 0x00000002U
+ // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U
+ // .. .. reg_phy_rd_rl_delay = 0x4
+ // .. .. ==> 0XF8006194[9:5] = 0x00000004U
+ // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U
+ // .. .. reg_phy_dll_lock_diff = 0xf
+ // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
+ // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U
+ // .. .. reg_phy_use_wr_level = 0x1
+ // .. .. ==> 0XF8006194[14:14] = 0x00000001U
+ // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U
+ // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
+ // .. .. ==> 0XF8006194[15:15] = 0x00000001U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U
+ // .. .. reg_phy_use_rd_data_eye_level = 0x1
+ // .. .. ==> 0XF8006194[16:16] = 0x00000001U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U
+ // .. .. reg_phy_dis_calib_rst = 0x0
+ // .. .. ==> 0XF8006194[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_phy_ctrl_slave_delay = 0x0
+ // .. .. ==> 0XF8006194[19:18] = 0x00000000U
+ // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
+ // .. .. reg_arb_page_addr_mask = 0x0
+ // .. .. ==> 0XF8006204[31:0] = 0x00000000U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
+ // .. .. reg_arb_pri_wr_portn = 0x3ff
+ // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_wr_portn = 0x0
+ // .. .. ==> 0XF8006208[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+ // .. .. ==> 0XF8006208[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+ // .. .. ==> 0XF8006208[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006208, 0x000703FFU ,0x000003FFU),
+ // .. .. reg_arb_pri_wr_portn = 0x3ff
+ // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_wr_portn = 0x0
+ // .. .. ==> 0XF800620C[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+ // .. .. ==> 0XF800620C[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+ // .. .. ==> 0XF800620C[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800620C, 0x000703FFU ,0x000003FFU),
+ // .. .. reg_arb_pri_wr_portn = 0x3ff
+ // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_wr_portn = 0x0
+ // .. .. ==> 0XF8006210[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+ // .. .. ==> 0XF8006210[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+ // .. .. ==> 0XF8006210[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006210, 0x000703FFU ,0x000003FFU),
+ // .. .. reg_arb_pri_wr_portn = 0x3ff
+ // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_wr_portn = 0x0
+ // .. .. ==> 0XF8006214[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+ // .. .. ==> 0XF8006214[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+ // .. .. ==> 0XF8006214[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006214, 0x000703FFU ,0x000003FFU),
+ // .. .. reg_arb_pri_rd_portn = 0x3ff
+ // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_rd_portn = 0x0
+ // .. .. ==> 0XF8006218[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+ // .. .. ==> 0XF8006218[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+ // .. .. ==> 0XF8006218[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_set_hpr_rd_portn = 0x0
+ // .. .. ==> 0XF8006218[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
+ // .. .. reg_arb_pri_rd_portn = 0x3ff
+ // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_rd_portn = 0x0
+ // .. .. ==> 0XF800621C[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+ // .. .. ==> 0XF800621C[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+ // .. .. ==> 0XF800621C[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_set_hpr_rd_portn = 0x0
+ // .. .. ==> 0XF800621C[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
+ // .. .. reg_arb_pri_rd_portn = 0x3ff
+ // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_rd_portn = 0x0
+ // .. .. ==> 0XF8006220[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+ // .. .. ==> 0XF8006220[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+ // .. .. ==> 0XF8006220[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_set_hpr_rd_portn = 0x0
+ // .. .. ==> 0XF8006220[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
+ // .. .. reg_arb_pri_rd_portn = 0x3ff
+ // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_rd_portn = 0x0
+ // .. .. ==> 0XF8006224[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+ // .. .. ==> 0XF8006224[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+ // .. .. ==> 0XF8006224[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_set_hpr_rd_portn = 0x0
+ // .. .. ==> 0XF8006224[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
+ // .. .. reg_ddrc_lpddr2 = 0x0
+ // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_derate_enable = 0x0
+ // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr4_margin = 0x0
+ // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U ,0x00000000U),
+ // .. .. reg_ddrc_mr4_read_interval = 0x0
+ // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
+ // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
+ // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U
+ // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
+ // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
+ // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U
+ // .. .. reg_ddrc_t_mrw = 0x5
+ // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
+ // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8
+ // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U
+ // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
+ // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
+ // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U
+ // .. ..
+ EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
+ // .. .. START: POLL ON DCI STATUS
+ // .. .. DONE = 1
+ // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
+ // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U
+ // .. ..
+ EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+ // .. .. FINISH: POLL ON DCI STATUS
+ // .. .. START: UNLOCK DDR
+ // .. .. reg_ddrc_soft_rstb = 0x1
+ // .. .. ==> 0XF8006000[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_ddrc_powerdown_en = 0x0
+ // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_ddrc_data_bus_width = 0x0
+ // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U
+ // .. .. reg_ddrc_burst8_refresh = 0x0
+ // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U
+ // .. .. reg_ddrc_rdwr_idle_gap = 1
+ // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+ // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U
+ // .. .. reg_ddrc_dis_rd_bypass = 0x0
+ // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+ // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_act_bypass = 0x0
+ // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_auto_refresh = 0x0
+ // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
+ // .. .. FINISH: UNLOCK DDR
+ // .. .. START: CHECK DDR STATUS
+ // .. .. ddrc_reg_operating_mode = 1
+ // .. .. ==> 0XF8006054[2:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U
+ // .. ..
+ EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+ // .. .. FINISH: CHECK DDR STATUS
+ // .. FINISH: DDR INITIALIZATION
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_mio_init_data_3_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: OCM REMAPPING
+ // .. VREF_EN = 0x1
+ // .. ==> 0XF8000B00[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. VREF_SEL = 0x0
+ // .. ==> 0XF8000B00[6:4] = 0x00000000U
+ // .. ==> MASK : 0x00000070U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B00, 0x00000071U ,0x00000001U),
+ // .. FINISH: OCM REMAPPING
+ // .. START: DDRIOB SETTINGS
+ // .. reserved_INP_POWER = 0x0
+ // .. ==> 0XF8000B40[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x0
+ // .. ==> 0XF8000B40[2:1] = 0x00000000U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000000U
+ // .. DCI_UPDATE_B = 0x0
+ // .. ==> 0XF8000B40[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x0
+ // .. ==> 0XF8000B40[4:4] = 0x00000000U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. DCI_TYPE = 0x0
+ // .. ==> 0XF8000B40[6:5] = 0x00000000U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000000U
+ // .. IBUF_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B40[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B40[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B40[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B40[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
+ // .. reserved_INP_POWER = 0x0
+ // .. ==> 0XF8000B44[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x0
+ // .. ==> 0XF8000B44[2:1] = 0x00000000U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000000U
+ // .. DCI_UPDATE_B = 0x0
+ // .. ==> 0XF8000B44[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x0
+ // .. ==> 0XF8000B44[4:4] = 0x00000000U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. DCI_TYPE = 0x0
+ // .. ==> 0XF8000B44[6:5] = 0x00000000U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000000U
+ // .. IBUF_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B44[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B44[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B44[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B44[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
+ // .. reserved_INP_POWER = 0x0
+ // .. ==> 0XF8000B48[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x1
+ // .. ==> 0XF8000B48[2:1] = 0x00000001U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000002U
+ // .. DCI_UPDATE_B = 0x0
+ // .. ==> 0XF8000B48[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x1
+ // .. ==> 0XF8000B48[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. DCI_TYPE = 0x3
+ // .. ==> 0XF8000B48[6:5] = 0x00000003U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000060U
+ // .. IBUF_DISABLE_MODE = 0
+ // .. ==> 0XF8000B48[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0
+ // .. ==> 0XF8000B48[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B48[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B48[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
+ // .. reserved_INP_POWER = 0x0
+ // .. ==> 0XF8000B4C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x1
+ // .. ==> 0XF8000B4C[2:1] = 0x00000001U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000002U
+ // .. DCI_UPDATE_B = 0x0
+ // .. ==> 0XF8000B4C[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x1
+ // .. ==> 0XF8000B4C[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. DCI_TYPE = 0x3
+ // .. ==> 0XF8000B4C[6:5] = 0x00000003U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000060U
+ // .. IBUF_DISABLE_MODE = 0
+ // .. ==> 0XF8000B4C[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0
+ // .. ==> 0XF8000B4C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B4C[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B4C[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
+ // .. reserved_INP_POWER = 0x0
+ // .. ==> 0XF8000B50[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x2
+ // .. ==> 0XF8000B50[2:1] = 0x00000002U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000004U
+ // .. DCI_UPDATE_B = 0x0
+ // .. ==> 0XF8000B50[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x1
+ // .. ==> 0XF8000B50[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. DCI_TYPE = 0x3
+ // .. ==> 0XF8000B50[6:5] = 0x00000003U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000060U
+ // .. IBUF_DISABLE_MODE = 0
+ // .. ==> 0XF8000B50[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0
+ // .. ==> 0XF8000B50[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B50[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B50[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
+ // .. reserved_INP_POWER = 0x0
+ // .. ==> 0XF8000B54[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x2
+ // .. ==> 0XF8000B54[2:1] = 0x00000002U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000004U
+ // .. DCI_UPDATE_B = 0x0
+ // .. ==> 0XF8000B54[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x1
+ // .. ==> 0XF8000B54[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. DCI_TYPE = 0x3
+ // .. ==> 0XF8000B54[6:5] = 0x00000003U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000060U
+ // .. IBUF_DISABLE_MODE = 0
+ // .. ==> 0XF8000B54[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0
+ // .. ==> 0XF8000B54[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B54[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B54[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
+ // .. reserved_INP_POWER = 0x0
+ // .. ==> 0XF8000B58[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x0
+ // .. ==> 0XF8000B58[2:1] = 0x00000000U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000000U
+ // .. DCI_UPDATE_B = 0x0
+ // .. ==> 0XF8000B58[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x0
+ // .. ==> 0XF8000B58[4:4] = 0x00000000U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. DCI_TYPE = 0x0
+ // .. ==> 0XF8000B58[6:5] = 0x00000000U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000000U
+ // .. IBUF_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B58[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B58[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B58[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B58[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
+ // .. reserved_DRIVE_P = 0x1c
+ // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
+ // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
+ // .. reserved_DRIVE_N = 0xc
+ // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
+ // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
+ // .. reserved_SLEW_P = 0x3
+ // .. ==> 0XF8000B5C[18:14] = 0x00000003U
+ // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U
+ // .. reserved_SLEW_N = 0x3
+ // .. ==> 0XF8000B5C[23:19] = 0x00000003U
+ // .. ==> MASK : 0x00F80000U VAL : 0x00180000U
+ // .. reserved_GTL = 0x0
+ // .. ==> 0XF8000B5C[26:24] = 0x00000000U
+ // .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. reserved_RTERM = 0x0
+ // .. ==> 0XF8000B5C[31:27] = 0x00000000U
+ // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
+ // .. reserved_DRIVE_P = 0x1c
+ // .. ==> 0XF8000B60[6:0] = 0x0000001CU
+ // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
+ // .. reserved_DRIVE_N = 0xc
+ // .. ==> 0XF8000B60[13:7] = 0x0000000CU
+ // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
+ // .. reserved_SLEW_P = 0x6
+ // .. ==> 0XF8000B60[18:14] = 0x00000006U
+ // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
+ // .. reserved_SLEW_N = 0x1f
+ // .. ==> 0XF8000B60[23:19] = 0x0000001FU
+ // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
+ // .. reserved_GTL = 0x0
+ // .. ==> 0XF8000B60[26:24] = 0x00000000U
+ // .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. reserved_RTERM = 0x0
+ // .. ==> 0XF8000B60[31:27] = 0x00000000U
+ // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
+ // .. reserved_DRIVE_P = 0x1c
+ // .. ==> 0XF8000B64[6:0] = 0x0000001CU
+ // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
+ // .. reserved_DRIVE_N = 0xc
+ // .. ==> 0XF8000B64[13:7] = 0x0000000CU
+ // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
+ // .. reserved_SLEW_P = 0x6
+ // .. ==> 0XF8000B64[18:14] = 0x00000006U
+ // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
+ // .. reserved_SLEW_N = 0x1f
+ // .. ==> 0XF8000B64[23:19] = 0x0000001FU
+ // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
+ // .. reserved_GTL = 0x0
+ // .. ==> 0XF8000B64[26:24] = 0x00000000U
+ // .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. reserved_RTERM = 0x0
+ // .. ==> 0XF8000B64[31:27] = 0x00000000U
+ // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
+ // .. reserved_DRIVE_P = 0x1c
+ // .. ==> 0XF8000B68[6:0] = 0x0000001CU
+ // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
+ // .. reserved_DRIVE_N = 0xc
+ // .. ==> 0XF8000B68[13:7] = 0x0000000CU
+ // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
+ // .. reserved_SLEW_P = 0x6
+ // .. ==> 0XF8000B68[18:14] = 0x00000006U
+ // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
+ // .. reserved_SLEW_N = 0x1f
+ // .. ==> 0XF8000B68[23:19] = 0x0000001FU
+ // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
+ // .. reserved_GTL = 0x0
+ // .. ==> 0XF8000B68[26:24] = 0x00000000U
+ // .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. reserved_RTERM = 0x0
+ // .. ==> 0XF8000B68[31:27] = 0x00000000U
+ // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
+ // .. VREF_INT_EN = 0x1
+ // .. ==> 0XF8000B6C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. VREF_SEL = 0x4
+ // .. ==> 0XF8000B6C[4:1] = 0x00000004U
+ // .. ==> MASK : 0x0000001EU VAL : 0x00000008U
+ // .. VREF_EXT_EN = 0x0
+ // .. ==> 0XF8000B6C[6:5] = 0x00000000U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000000U
+ // .. reserved_VREF_PULLUP_EN = 0x0
+ // .. ==> 0XF8000B6C[8:7] = 0x00000000U
+ // .. ==> MASK : 0x00000180U VAL : 0x00000000U
+ // .. REFIO_EN = 0x1
+ // .. ==> 0XF8000B6C[9:9] = 0x00000001U
+ // .. ==> MASK : 0x00000200U VAL : 0x00000200U
+ // .. reserved_REFIO_TEST = 0x3
+ // .. ==> 0XF8000B6C[11:10] = 0x00000003U
+ // .. ==> MASK : 0x00000C00U VAL : 0x00000C00U
+ // .. reserved_REFIO_PULLUP_EN = 0x0
+ // .. ==> 0XF8000B6C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. reserved_DRST_B_PULLUP_EN = 0x0
+ // .. ==> 0XF8000B6C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // .. reserved_CKE_PULLUP_EN = 0x0
+ // .. ==> 0XF8000B6C[14:14] = 0x00000000U
+ // .. ==> MASK : 0x00004000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000E09U),
+ // .. .. START: ASSERT RESET
+ // .. .. RESET = 1
+ // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000B70, 0x00000001U ,0x00000001U),
+ // .. .. FINISH: ASSERT RESET
+ // .. .. START: DEASSERT RESET
+ // .. .. RESET = 0
+ // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reserved_VRN_OUT = 0x1
+ // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
+ // .. .. FINISH: DEASSERT RESET
+ // .. .. RESET = 0x1
+ // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ENABLE = 0x1
+ // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. .. reserved_VRP_TRI = 0x0
+ // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reserved_VRN_TRI = 0x0
+ // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reserved_VRP_OUT = 0x0
+ // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reserved_VRN_OUT = 0x1
+ // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
+ // .. .. NREF_OPT1 = 0x0
+ // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
+ // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U
+ // .. .. NREF_OPT2 = 0x0
+ // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U
+ // .. .. NREF_OPT4 = 0x1
+ // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
+ // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U
+ // .. .. PREF_OPT1 = 0x0
+ // .. .. ==> 0XF8000B70[15:14] = 0x00000000U
+ // .. .. ==> MASK : 0x0000C000U VAL : 0x00000000U
+ // .. .. PREF_OPT2 = 0x0
+ // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
+ // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U
+ // .. .. UPDATE_CONTROL = 0x0
+ // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
+ // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U
+ // .. .. reserved_INIT_COMPLETE = 0x0
+ // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
+ // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U
+ // .. .. reserved_TST_CLK = 0x0
+ // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
+ // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U
+ // .. .. reserved_TST_HLN = 0x0
+ // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
+ // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U
+ // .. .. reserved_TST_HLP = 0x0
+ // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
+ // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U
+ // .. .. reserved_TST_RST = 0x0
+ // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
+ // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
+ // .. .. reserved_INT_DCI_EN = 0x0
+ // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
+ // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU ,0x00000823U),
+ // .. FINISH: DDRIOB SETTINGS
+ // .. START: MIO PROGRAMMING
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000700[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000700[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000700[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000700[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000700[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000700[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000700[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000700[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000700[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000704[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000704[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000704[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000704[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000704[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000704[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000704[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000704[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000704[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000708[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000708[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000708[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000708[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000708[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000708[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000708[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000708[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000708[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800070C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF800070C[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800070C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800070C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800070C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800070C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800070C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800070C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800070C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000710[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000710[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000710[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000710[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000710[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000710[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000710[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000710[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000710[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000714[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000714[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000714[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000714[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000714[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000714[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000714[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000714[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000714[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000718[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000718[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000718[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000718[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000718[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000718[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000718[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000718[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000718[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800071C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800071C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800071C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800071C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800071C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800071C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800071C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800071C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800071C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000200U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000720[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000720[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000720[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000720[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000720[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000720[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000720[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000720[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000720[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000724[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000724[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000724[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000724[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000724[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000724[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000724[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000724[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000724[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000728[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000728[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000728[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000728[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000728[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000728[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000728[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000728[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000728[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800072C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF800072C[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800072C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800072C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800072C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800072C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800072C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF800072C[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800072C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000730[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000730[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000730[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000730[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000730[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000730[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000730[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000730[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000730[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000734[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000734[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000734[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000734[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000734[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000734[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000734[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000734[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000734[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001202U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000738[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. Speed = 0
+ // .. ==> 0XF8000738[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000738[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000738[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000738[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000738, 0x00003F01U ,0x00001201U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF800073C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. Speed = 0
+ // .. ==> 0XF800073C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800073C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF800073C[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800073C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800073C, 0x00003F01U ,0x00001201U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000740[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000740[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000740[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000740[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000740[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000740[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 4
+ // .. ==> 0XF8000740[11:9] = 0x00000004U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000740[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 1
+ // .. ==> 0XF8000740[13:13] = 0x00000001U
+ // .. ==> MASK : 0x00002000U VAL : 0x00002000U
+ // ..
+ EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00002802U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000744[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000744[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000744[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000744[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000744[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000744[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 4
+ // .. ==> 0XF8000744[11:9] = 0x00000004U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000744[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 1
+ // .. ==> 0XF8000744[13:13] = 0x00000001U
+ // .. ==> MASK : 0x00002000U VAL : 0x00002000U
+ // ..
+ EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00002802U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000748[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000748[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000748[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000748[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000748[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000748[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 4
+ // .. ==> 0XF8000748[11:9] = 0x00000004U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000748[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 1
+ // .. ==> 0XF8000748[13:13] = 0x00000001U
+ // .. ==> MASK : 0x00002000U VAL : 0x00002000U
+ // ..
+ EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00002802U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800074C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF800074C[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800074C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800074C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800074C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800074C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 4
+ // .. ==> 0XF800074C[11:9] = 0x00000004U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
+ // .. PULLUP = 0
+ // .. ==> 0XF800074C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 1
+ // .. ==> 0XF800074C[13:13] = 0x00000001U
+ // .. ==> MASK : 0x00002000U VAL : 0x00002000U
+ // ..
+ EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00002802U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000750[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000750[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000750[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000750[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000750[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000750[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 4
+ // .. ==> 0XF8000750[11:9] = 0x00000004U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000750[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 1
+ // .. ==> 0XF8000750[13:13] = 0x00000001U
+ // .. ==> MASK : 0x00002000U VAL : 0x00002000U
+ // ..
+ EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00002802U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000754[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000754[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000754[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000754[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000754[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000754[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 4
+ // .. ==> 0XF8000754[11:9] = 0x00000004U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000754[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 1
+ // .. ==> 0XF8000754[13:13] = 0x00000001U
+ // .. ==> MASK : 0x00002000U VAL : 0x00002000U
+ // ..
+ EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00002802U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000758[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000758[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000758[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000758[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000758[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000758[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 4
+ // .. ==> 0XF8000758[11:9] = 0x00000004U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000758[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000758[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000803U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF800075C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF800075C[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800075C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800075C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800075C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800075C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 4
+ // .. ==> 0XF800075C[11:9] = 0x00000004U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
+ // .. PULLUP = 0
+ // .. ==> 0XF800075C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800075C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000803U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000760[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000760[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000760[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000760[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000760[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000760[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 4
+ // .. ==> 0XF8000760[11:9] = 0x00000004U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000760[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000760[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000803U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000764[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000764[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000764[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000764[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000764[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000764[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 4
+ // .. ==> 0XF8000764[11:9] = 0x00000004U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000764[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000764[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000803U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000768[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000768[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000768[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000768[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000768[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000768[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 4
+ // .. ==> 0XF8000768[11:9] = 0x00000004U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000768[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000768[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000803U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF800076C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF800076C[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800076C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800076C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800076C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800076C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 4
+ // .. ==> 0XF800076C[11:9] = 0x00000004U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
+ // .. PULLUP = 0
+ // .. ==> 0XF800076C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800076C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000803U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000770[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000770[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000770[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000770[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000770[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000770[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000770[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000770[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000770[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000774[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000774[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000774[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000774[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000774[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000774[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000774[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000774[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000774[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000778[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000778[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000778[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000778[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000778[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000778[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000778[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000778[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000778[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF800077C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800077C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF800077C[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800077C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800077C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800077C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800077C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800077C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800077C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000780[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000780[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000780[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000780[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000780[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000780[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000780[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000780[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000780[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000784[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000784[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000784[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000784[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000784[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000784[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000784[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000784[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000784[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000788[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000788[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000788[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000788[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000788[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000788[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000788[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000788[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000788[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800078C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800078C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF800078C[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800078C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800078C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800078C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800078C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800078C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800078C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000790[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000790[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000790[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000790[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000790[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000790[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000790[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000790[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000790[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000794[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000794[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000794[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000794[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000794[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000794[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000794[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000794[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000794[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000798[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000798[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000798[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000798[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000798[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000798[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000798[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000798[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000798[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800079C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800079C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF800079C[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800079C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800079C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800079C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800079C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800079C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800079C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007A0[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007A0[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007A0[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007A0[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007A0[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007A0[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007A0[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007A0[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007A0[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007A4[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007A4[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007A4[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007A4[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007A4[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007A4[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007A4[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007A4[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007A4[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007A8[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007A8[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007A8[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007A8[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007A8[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007A8[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007A8[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007A8[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007A8[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007AC[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007AC[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007AC[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007AC[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007AC[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007AC[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007AC[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007AC[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007AC[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007B0[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007B0[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007B0[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007B0[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007B0[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007B0[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007B0[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007B0[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007B0[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007B4[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007B4[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007B4[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007B4[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007B4[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007B4[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007B4[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007B4[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007B4[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007B8[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007B8[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007B8[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007B8[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF80007B8[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF80007B8[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007B8[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF80007B8[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007B8[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001200U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007BC[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007BC[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007BC[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007BC[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF80007BC[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF80007BC[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007BC[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF80007BC[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007BC[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00001200U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007C0[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007C0[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007C0[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007C0[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 7
+ // .. ==> 0XF80007C0[7:5] = 0x00000007U
+ // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U
+ // .. Speed = 0
+ // .. ==> 0XF80007C0[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007C0[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007C0[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007C0[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF80007C4[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007C4[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007C4[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007C4[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 7
+ // .. ==> 0XF80007C4[7:5] = 0x00000007U
+ // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U
+ // .. Speed = 0
+ // .. ==> 0XF80007C4[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007C4[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007C4[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007C4[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007C8[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007C8[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007C8[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007C8[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 2
+ // .. ==> 0XF80007C8[7:5] = 0x00000002U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000040U
+ // .. Speed = 0
+ // .. ==> 0XF80007C8[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007C8[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF80007C8[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007C8[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001240U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007CC[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007CC[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007CC[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007CC[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 2
+ // .. ==> 0XF80007CC[7:5] = 0x00000002U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000040U
+ // .. Speed = 0
+ // .. ==> 0XF80007CC[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007CC[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF80007CC[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007CC[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001240U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007D0[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007D0[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007D0[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007D0[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007D0[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007D0[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007D0[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007D0[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007D0[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007D4[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007D4[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007D4[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007D4[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007D4[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007D4[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007D4[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007D4[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007D4[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U),
+ // .. SDIO0_WP_SEL = 15
+ // .. ==> 0XF8000830[5:0] = 0x0000000FU
+ // .. ==> MASK : 0x0000003FU VAL : 0x0000000FU
+ // .. SDIO0_CD_SEL = 14
+ // .. ==> 0XF8000830[21:16] = 0x0000000EU
+ // .. ==> MASK : 0x003F0000U VAL : 0x000E0000U
+ // ..
+ EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x000E000FU),
+ // .. FINISH: MIO PROGRAMMING
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_peripherals_init_data_3_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+ // .. IBUF_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B48[7:7] = 0x00000001U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. TERM_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B48[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // ..
+ EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
+ // .. IBUF_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B4C[7:7] = 0x00000001U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. TERM_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B4C[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // ..
+ EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
+ // .. IBUF_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B50[7:7] = 0x00000001U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. TERM_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B50[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // ..
+ EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
+ // .. IBUF_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B54[7:7] = 0x00000001U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. TERM_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B54[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // ..
+ EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
+ // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // .. START: SRAM/NOR SET OPMODE
+ // .. FINISH: SRAM/NOR SET OPMODE
+ // .. START: UART REGISTERS
+ // .. BDIV = 0x6
+ // .. ==> 0XE0001034[7:0] = 0x00000006U
+ // .. ==> MASK : 0x000000FFU VAL : 0x00000006U
+ // ..
+ EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
+ // .. CD = 0x3e
+ // .. ==> 0XE0001018[15:0] = 0x0000003EU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU
+ // ..
+ EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
+ // .. STPBRK = 0x0
+ // .. ==> 0XE0001000[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. STTBRK = 0x0
+ // .. ==> 0XE0001000[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. RSTTO = 0x0
+ // .. ==> 0XE0001000[6:6] = 0x00000000U
+ // .. ==> MASK : 0x00000040U VAL : 0x00000000U
+ // .. TXDIS = 0x0
+ // .. ==> 0XE0001000[5:5] = 0x00000000U
+ // .. ==> MASK : 0x00000020U VAL : 0x00000000U
+ // .. TXEN = 0x1
+ // .. ==> 0XE0001000[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. RXDIS = 0x0
+ // .. ==> 0XE0001000[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. RXEN = 0x1
+ // .. ==> 0XE0001000[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. TXRES = 0x1
+ // .. ==> 0XE0001000[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. RXRES = 0x1
+ // .. ==> 0XE0001000[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // ..
+ EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
+ // .. CHMODE = 0x0
+ // .. ==> 0XE0001004[9:8] = 0x00000000U
+ // .. ==> MASK : 0x00000300U VAL : 0x00000000U
+ // .. NBSTOP = 0x0
+ // .. ==> 0XE0001004[7:6] = 0x00000000U
+ // .. ==> MASK : 0x000000C0U VAL : 0x00000000U
+ // .. PAR = 0x4
+ // .. ==> 0XE0001004[5:3] = 0x00000004U
+ // .. ==> MASK : 0x00000038U VAL : 0x00000020U
+ // .. CHRL = 0x0
+ // .. ==> 0XE0001004[2:1] = 0x00000000U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000000U
+ // .. CLKS = 0x0
+ // .. ==> 0XE0001004[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XE0001004, 0x000003FFU ,0x00000020U),
+ // .. FINISH: UART REGISTERS
+ // .. START: QSPI REGISTERS
+ // .. Holdb_dr = 1
+ // .. ==> 0XE000D000[19:19] = 0x00000001U
+ // .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // ..
+ EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
+ // .. FINISH: QSPI REGISTERS
+ // .. START: PL POWER ON RESET REGISTERS
+ // .. PCFG_POR_CNT_4K = 0
+ // .. ==> 0XF8007000[29:29] = 0x00000000U
+ // .. ==> MASK : 0x20000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
+ // .. FINISH: PL POWER ON RESET REGISTERS
+ // .. START: SMC TIMING CALCULATION REGISTER UPDATE
+ // .. .. START: NAND SET CYCLE
+ // .. .. FINISH: NAND SET CYCLE
+ // .. .. START: OPMODE
+ // .. .. FINISH: OPMODE
+ // .. .. START: DIRECT COMMAND
+ // .. .. FINISH: DIRECT COMMAND
+ // .. .. START: SRAM/NOR CS0 SET CYCLE
+ // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
+ // .. .. START: DIRECT COMMAND
+ // .. .. FINISH: DIRECT COMMAND
+ // .. .. START: NOR CS0 BASE ADDRESS
+ // .. .. FINISH: NOR CS0 BASE ADDRESS
+ // .. .. START: SRAM/NOR CS1 SET CYCLE
+ // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
+ // .. .. START: DIRECT COMMAND
+ // .. .. FINISH: DIRECT COMMAND
+ // .. .. START: NOR CS1 BASE ADDRESS
+ // .. .. FINISH: NOR CS1 BASE ADDRESS
+ // .. .. START: USB RESET
+ // .. .. .. START: USB0 RESET
+ // .. .. .. .. START: DIR MODE BANK 0
+ // .. .. .. .. DIRECTION_0 = 0x80
+ // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U
+ // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U),
+ // .. .. .. .. FINISH: DIR MODE BANK 0
+ // .. .. .. .. START: DIR MODE BANK 1
+ // .. .. .. .. FINISH: DIR MODE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. MASK_0_LSW = 0xff7f
+ // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+ // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U
+ // .. .. .. .. DATA_0_LSW = 0x80
+ // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+ // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. START: OUTPUT ENABLE BANK 0
+ // .. .. .. .. OP_ENABLE_0 = 0x80
+ // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U
+ // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U),
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+ // .. .. .. .. START: OUTPUT ENABLE BANK 1
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. MASK_0_LSW = 0xff7f
+ // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+ // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U
+ // .. .. .. .. DATA_0_LSW = 0x0
+ // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+ // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U),
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. START: ADD 1 MS DELAY
+ // .. .. .. ..
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ // .. .. .. .. FINISH: ADD 1 MS DELAY
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. MASK_0_LSW = 0xff7f
+ // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+ // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U
+ // .. .. .. .. DATA_0_LSW = 0x80
+ // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+ // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. FINISH: USB0 RESET
+ // .. .. .. START: USB1 RESET
+ // .. .. .. .. START: DIR MODE BANK 0
+ // .. .. .. .. FINISH: DIR MODE BANK 0
+ // .. .. .. .. START: DIR MODE BANK 1
+ // .. .. .. .. FINISH: DIR MODE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. START: OUTPUT ENABLE BANK 0
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+ // .. .. .. .. START: OUTPUT ENABLE BANK 1
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. START: ADD 1 MS DELAY
+ // .. .. .. ..
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ // .. .. .. .. FINISH: ADD 1 MS DELAY
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. FINISH: USB1 RESET
+ // .. .. FINISH: USB RESET
+ // .. .. START: ENET RESET
+ // .. .. .. START: ENET0 RESET
+ // .. .. .. .. START: DIR MODE BANK 0
+ // .. .. .. .. FINISH: DIR MODE BANK 0
+ // .. .. .. .. START: DIR MODE BANK 1
+ // .. .. .. .. DIRECTION_1 = 0x8000
+ // .. .. .. .. ==> 0XE000A244[21:0] = 0x00008000U
+ // .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00008000U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x00008000U),
+ // .. .. .. .. FINISH: DIR MODE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. MASK_1_LSW = 0x7fff
+ // .. .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU
+ // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0x7FFF0000U
+ // .. .. .. .. DATA_1_LSW = 0x8000
+ // .. .. .. .. ==> 0XE000A008[15:0] = 0x00008000U
+ // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00008000U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF8000U),
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. START: OUTPUT ENABLE BANK 0
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+ // .. .. .. .. START: OUTPUT ENABLE BANK 1
+ // .. .. .. .. OP_ENABLE_1 = 0x8000
+ // .. .. .. .. ==> 0XE000A248[21:0] = 0x00008000U
+ // .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00008000U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x00008000U),
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. MASK_1_LSW = 0x7fff
+ // .. .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU
+ // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0x7FFF0000U
+ // .. .. .. .. DATA_1_LSW = 0x0
+ // .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U
+ // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF0000U),
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. START: ADD 1 MS DELAY
+ // .. .. .. ..
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ // .. .. .. .. FINISH: ADD 1 MS DELAY
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. MASK_1_LSW = 0x7fff
+ // .. .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU
+ // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0x7FFF0000U
+ // .. .. .. .. DATA_1_LSW = 0x8000
+ // .. .. .. .. ==> 0XE000A008[15:0] = 0x00008000U
+ // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00008000U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF8000U),
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. FINISH: ENET0 RESET
+ // .. .. .. START: ENET1 RESET
+ // .. .. .. .. START: DIR MODE BANK 0
+ // .. .. .. .. FINISH: DIR MODE BANK 0
+ // .. .. .. .. START: DIR MODE BANK 1
+ // .. .. .. .. FINISH: DIR MODE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. START: OUTPUT ENABLE BANK 0
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+ // .. .. .. .. START: OUTPUT ENABLE BANK 1
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. START: ADD 1 MS DELAY
+ // .. .. .. ..
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ // .. .. .. .. FINISH: ADD 1 MS DELAY
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. FINISH: ENET1 RESET
+ // .. .. FINISH: ENET RESET
+ // .. .. START: I2C RESET
+ // .. .. .. START: I2C0 RESET
+ // .. .. .. .. START: DIR MODE GPIO BANK0
+ // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+ // .. .. .. .. START: DIR MODE GPIO BANK1
+ // .. .. .. .. DIRECTION_1 = 0x4000
+ // .. .. .. .. ==> 0XE000A244[21:0] = 0x00004000U
+ // .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x00004000U),
+ // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. MASK_1_LSW = 0xbfff
+ // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
+ // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U
+ // .. .. .. .. DATA_1_LSW = 0x4000
+ // .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U
+ // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U),
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. START: OUTPUT ENABLE
+ // .. .. .. .. FINISH: OUTPUT ENABLE
+ // .. .. .. .. START: OUTPUT ENABLE
+ // .. .. .. .. OP_ENABLE_1 = 0x4000
+ // .. .. .. .. ==> 0XE000A248[21:0] = 0x00004000U
+ // .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x00004000U),
+ // .. .. .. .. FINISH: OUTPUT ENABLE
+ // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. MASK_1_LSW = 0xbfff
+ // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
+ // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U
+ // .. .. .. .. DATA_1_LSW = 0x0
+ // .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U
+ // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF0000U),
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. START: ADD 1 MS DELAY
+ // .. .. .. ..
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ // .. .. .. .. FINISH: ADD 1 MS DELAY
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. MASK_1_LSW = 0xbfff
+ // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
+ // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U
+ // .. .. .. .. DATA_1_LSW = 0x4000
+ // .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U
+ // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U),
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. FINISH: I2C0 RESET
+ // .. .. .. START: I2C1 RESET
+ // .. .. .. .. START: DIR MODE GPIO BANK0
+ // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+ // .. .. .. .. START: DIR MODE GPIO BANK1
+ // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. START: OUTPUT ENABLE
+ // .. .. .. .. FINISH: OUTPUT ENABLE
+ // .. .. .. .. START: OUTPUT ENABLE
+ // .. .. .. .. FINISH: OUTPUT ENABLE
+ // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. START: ADD 1 MS DELAY
+ // .. .. .. ..
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ // .. .. .. .. FINISH: ADD 1 MS DELAY
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. FINISH: I2C1 RESET
+ // .. .. FINISH: I2C RESET
+ // .. .. START: NOR CHIP SELECT
+ // .. .. .. START: DIR MODE BANK 0
+ // .. .. .. FINISH: DIR MODE BANK 0
+ // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. START: OUTPUT ENABLE BANK 0
+ // .. .. .. FINISH: OUTPUT ENABLE BANK 0
+ // .. .. FINISH: NOR CHIP SELECT
+ // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_post_config_3_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: ENABLING LEVEL SHIFTER
+ // .. USER_LVL_INP_EN_0 = 1
+ // .. ==> 0XF8000900[3:3] = 0x00000001U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000008U
+ // .. USER_LVL_OUT_EN_0 = 1
+ // .. ==> 0XF8000900[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. USER_LVL_INP_EN_1 = 1
+ // .. ==> 0XF8000900[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. USER_LVL_OUT_EN_1 = 1
+ // .. ==> 0XF8000900[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // ..
+ EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
+ // .. FINISH: ENABLING LEVEL SHIFTER
+ // .. START: FPGA RESETS TO 0
+ // .. reserved_3 = 0
+ // .. ==> 0XF8000240[31:25] = 0x00000000U
+ // .. ==> MASK : 0xFE000000U VAL : 0x00000000U
+ // .. reserved_FPGA_ACP_RST = 0
+ // .. ==> 0XF8000240[24:24] = 0x00000000U
+ // .. ==> MASK : 0x01000000U VAL : 0x00000000U
+ // .. reserved_FPGA_AXDS3_RST = 0
+ // .. ==> 0XF8000240[23:23] = 0x00000000U
+ // .. ==> MASK : 0x00800000U VAL : 0x00000000U
+ // .. reserved_FPGA_AXDS2_RST = 0
+ // .. ==> 0XF8000240[22:22] = 0x00000000U
+ // .. ==> MASK : 0x00400000U VAL : 0x00000000U
+ // .. reserved_FPGA_AXDS1_RST = 0
+ // .. ==> 0XF8000240[21:21] = 0x00000000U
+ // .. ==> MASK : 0x00200000U VAL : 0x00000000U
+ // .. reserved_FPGA_AXDS0_RST = 0
+ // .. ==> 0XF8000240[20:20] = 0x00000000U
+ // .. ==> MASK : 0x00100000U VAL : 0x00000000U
+ // .. reserved_2 = 0
+ // .. ==> 0XF8000240[19:18] = 0x00000000U
+ // .. ==> MASK : 0x000C0000U VAL : 0x00000000U
+ // .. reserved_FSSW1_FPGA_RST = 0
+ // .. ==> 0XF8000240[17:17] = 0x00000000U
+ // .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. reserved_FSSW0_FPGA_RST = 0
+ // .. ==> 0XF8000240[16:16] = 0x00000000U
+ // .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. reserved_1 = 0
+ // .. ==> 0XF8000240[15:14] = 0x00000000U
+ // .. ==> MASK : 0x0000C000U VAL : 0x00000000U
+ // .. reserved_FPGA_FMSW1_RST = 0
+ // .. ==> 0XF8000240[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // .. reserved_FPGA_FMSW0_RST = 0
+ // .. ==> 0XF8000240[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. reserved_FPGA_DMA3_RST = 0
+ // .. ==> 0XF8000240[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. reserved_FPGA_DMA2_RST = 0
+ // .. ==> 0XF8000240[10:10] = 0x00000000U
+ // .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. reserved_FPGA_DMA1_RST = 0
+ // .. ==> 0XF8000240[9:9] = 0x00000000U
+ // .. ==> MASK : 0x00000200U VAL : 0x00000000U
+ // .. reserved_FPGA_DMA0_RST = 0
+ // .. ==> 0XF8000240[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. reserved = 0
+ // .. ==> 0XF8000240[7:4] = 0x00000000U
+ // .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. FPGA3_OUT_RST = 0
+ // .. ==> 0XF8000240[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. FPGA2_OUT_RST = 0
+ // .. ==> 0XF8000240[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. FPGA1_OUT_RST = 0
+ // .. ==> 0XF8000240[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. FPGA0_OUT_RST = 0
+ // .. ==> 0XF8000240[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
+ // .. FINISH: FPGA RESETS TO 0
+ // .. START: AFI REGISTERS
+ // .. .. START: AFI0 REGISTERS
+ // .. .. FINISH: AFI0 REGISTERS
+ // .. .. START: AFI1 REGISTERS
+ // .. .. FINISH: AFI1 REGISTERS
+ // .. .. START: AFI2 REGISTERS
+ // .. .. FINISH: AFI2 REGISTERS
+ // .. .. START: AFI3 REGISTERS
+ // .. .. FINISH: AFI3 REGISTERS
+ // .. FINISH: AFI REGISTERS
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_debug_3_0[] = {
+ // START: top
+ // .. START: CROSS TRIGGER CONFIGURATIONS
+ // .. .. START: UNLOCKING CTI REGISTERS
+ // .. .. KEY = 0XC5ACCE55
+ // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
+ // .. ..
+ EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
+ // .. .. KEY = 0XC5ACCE55
+ // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
+ // .. ..
+ EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
+ // .. .. KEY = 0XC5ACCE55
+ // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
+ // .. ..
+ EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
+ // .. .. FINISH: UNLOCKING CTI REGISTERS
+ // .. .. START: ENABLING CTI MODULES AND CHANNELS
+ // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
+ // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+ // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+ // .. FINISH: CROSS TRIGGER CONFIGURATIONS
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_pll_init_data_2_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: PLL SLCR REGISTERS
+ // .. .. START: ARM PLL INIT
+ // .. .. PLL_RES = 0x2
+ // .. .. ==> 0XF8000110[7:4] = 0x00000002U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
+ // .. .. PLL_CP = 0x2
+ // .. .. ==> 0XF8000110[11:8] = 0x00000002U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
+ // .. .. LOCK_CNT = 0xfa
+ // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
+ // .. .. .. START: UPDATE FB_DIV
+ // .. .. .. PLL_FDIV = 0x28
+ // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
+ // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
+ // .. .. .. FINISH: UPDATE FB_DIV
+ // .. .. .. START: BY PASS PLL
+ // .. .. .. PLL_BYPASS_FORCE = 1
+ // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
+ // .. .. .. FINISH: BY PASS PLL
+ // .. .. .. START: ASSERT RESET
+ // .. .. .. PLL_RESET = 1
+ // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
+ // .. .. .. FINISH: ASSERT RESET
+ // .. .. .. START: DEASSERT RESET
+ // .. .. .. PLL_RESET = 0
+ // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
+ // .. .. .. FINISH: DEASSERT RESET
+ // .. .. .. START: CHECK PLL STATUS
+ // .. .. .. ARM_PLL_LOCK = 1
+ // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ..
+ EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+ // .. .. .. FINISH: CHECK PLL STATUS
+ // .. .. .. START: REMOVE PLL BY PASS
+ // .. .. .. PLL_BYPASS_FORCE = 0
+ // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
+ // .. .. .. FINISH: REMOVE PLL BY PASS
+ // .. .. .. SRCSEL = 0x0
+ // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. .. .. DIVISOR = 0x2
+ // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
+ // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U
+ // .. .. .. CPU_6OR4XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
+ // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U
+ // .. .. .. CPU_3OR2XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
+ // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U
+ // .. .. .. CPU_2XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
+ // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U
+ // .. .. .. CPU_1XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
+ // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U
+ // .. .. .. CPU_PERI_CLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
+ // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
+ // .. .. FINISH: ARM PLL INIT
+ // .. .. START: DDR PLL INIT
+ // .. .. PLL_RES = 0x2
+ // .. .. ==> 0XF8000114[7:4] = 0x00000002U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
+ // .. .. PLL_CP = 0x2
+ // .. .. ==> 0XF8000114[11:8] = 0x00000002U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
+ // .. .. LOCK_CNT = 0x12c
+ // .. .. ==> 0XF8000114[21:12] = 0x0000012CU
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
+ // .. .. .. START: UPDATE FB_DIV
+ // .. .. .. PLL_FDIV = 0x20
+ // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
+ // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
+ // .. .. .. FINISH: UPDATE FB_DIV
+ // .. .. .. START: BY PASS PLL
+ // .. .. .. PLL_BYPASS_FORCE = 1
+ // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
+ // .. .. .. FINISH: BY PASS PLL
+ // .. .. .. START: ASSERT RESET
+ // .. .. .. PLL_RESET = 1
+ // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
+ // .. .. .. FINISH: ASSERT RESET
+ // .. .. .. START: DEASSERT RESET
+ // .. .. .. PLL_RESET = 0
+ // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
+ // .. .. .. FINISH: DEASSERT RESET
+ // .. .. .. START: CHECK PLL STATUS
+ // .. .. .. DDR_PLL_LOCK = 1
+ // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. .. ..
+ EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+ // .. .. .. FINISH: CHECK PLL STATUS
+ // .. .. .. START: REMOVE PLL BY PASS
+ // .. .. .. PLL_BYPASS_FORCE = 0
+ // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
+ // .. .. .. FINISH: REMOVE PLL BY PASS
+ // .. .. .. DDR_3XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. .. DDR_2XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. .. .. DDR_3XCLK_DIVISOR = 0x2
+ // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
+ // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U
+ // .. .. .. DDR_2XCLK_DIVISOR = 0x3
+ // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
+ // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
+ // .. .. FINISH: DDR PLL INIT
+ // .. .. START: IO PLL INIT
+ // .. .. PLL_RES = 0xc
+ // .. .. ==> 0XF8000118[7:4] = 0x0000000CU
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U
+ // .. .. PLL_CP = 0x2
+ // .. .. ==> 0XF8000118[11:8] = 0x00000002U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
+ // .. .. LOCK_CNT = 0x145
+ // .. .. ==> 0XF8000118[21:12] = 0x00000145U
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U),
+ // .. .. .. START: UPDATE FB_DIV
+ // .. .. .. PLL_FDIV = 0x1e
+ // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU
+ // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U),
+ // .. .. .. FINISH: UPDATE FB_DIV
+ // .. .. .. START: BY PASS PLL
+ // .. .. .. PLL_BYPASS_FORCE = 1
+ // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
+ // .. .. .. FINISH: BY PASS PLL
+ // .. .. .. START: ASSERT RESET
+ // .. .. .. PLL_RESET = 1
+ // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
+ // .. .. .. FINISH: ASSERT RESET
+ // .. .. .. START: DEASSERT RESET
+ // .. .. .. PLL_RESET = 0
+ // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
+ // .. .. .. FINISH: DEASSERT RESET
+ // .. .. .. START: CHECK PLL STATUS
+ // .. .. .. IO_PLL_LOCK = 1
+ // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. .. ..
+ EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+ // .. .. .. FINISH: CHECK PLL STATUS
+ // .. .. .. START: REMOVE PLL BY PASS
+ // .. .. .. PLL_BYPASS_FORCE = 0
+ // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
+ // .. .. .. FINISH: REMOVE PLL BY PASS
+ // .. .. FINISH: IO PLL INIT
+ // .. FINISH: PLL SLCR REGISTERS
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_clock_init_data_2_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: CLOCK CONTROL SLCR REGISTERS
+ // .. CLKACT = 0x1
+ // .. ==> 0XF8000128[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. DIVISOR0 = 0x23
+ // .. ==> 0XF8000128[13:8] = 0x00000023U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00002300U
+ // .. DIVISOR1 = 0x3
+ // .. ==> 0XF8000128[25:20] = 0x00000003U
+ // .. ==> MASK : 0x03F00000U VAL : 0x00300000U
+ // ..
+ EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U),
+ // .. CLKACT = 0x1
+ // .. ==> 0XF8000138[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000138[4:4] = 0x00000000U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
+ // .. CLKACT = 0x1
+ // .. ==> 0XF8000140[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000140[6:4] = 0x00000000U
+ // .. ==> MASK : 0x00000070U VAL : 0x00000000U
+ // .. DIVISOR = 0x8
+ // .. ==> 0XF8000140[13:8] = 0x00000008U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00000800U
+ // .. DIVISOR1 = 0x5
+ // .. ==> 0XF8000140[25:20] = 0x00000005U
+ // .. ==> MASK : 0x03F00000U VAL : 0x00500000U
+ // ..
+ EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00500801U),
+ // .. CLKACT = 0x1
+ // .. ==> 0XF800014C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF800014C[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR = 0x5
+ // .. ==> 0XF800014C[13:8] = 0x00000005U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00000500U
+ // ..
+ EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
+ // .. CLKACT0 = 0x1
+ // .. ==> 0XF8000150[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. CLKACT1 = 0x0
+ // .. ==> 0XF8000150[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000150[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR = 0x14
+ // .. ==> 0XF8000150[13:8] = 0x00000014U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
+ // ..
+ EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U),
+ // .. CLKACT0 = 0x0
+ // .. ==> 0XF8000154[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. CLKACT1 = 0x1
+ // .. ==> 0XF8000154[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000154[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR = 0x14
+ // .. ==> 0XF8000154[13:8] = 0x00000014U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
+ // ..
+ EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U),
+ // .. CLKACT = 0x1
+ // .. ==> 0XF8000168[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000168[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR = 0x5
+ // .. ==> 0XF8000168[13:8] = 0x00000005U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00000500U
+ // ..
+ EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000170[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR0 = 0x14
+ // .. ==> 0XF8000170[13:8] = 0x00000014U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
+ // .. DIVISOR1 = 0x1
+ // .. ==> 0XF8000170[25:20] = 0x00000001U
+ // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
+ // ..
+ EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00101400U),
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000180[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR0 = 0x14
+ // .. ==> 0XF8000180[13:8] = 0x00000014U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
+ // .. DIVISOR1 = 0x1
+ // .. ==> 0XF8000180[25:20] = 0x00000001U
+ // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
+ // ..
+ EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00101400U),
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000190[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR0 = 0x14
+ // .. ==> 0XF8000190[13:8] = 0x00000014U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
+ // .. DIVISOR1 = 0x1
+ // .. ==> 0XF8000190[25:20] = 0x00000001U
+ // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
+ // ..
+ EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101400U),
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF80001A0[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR0 = 0x14
+ // .. ==> 0XF80001A0[13:8] = 0x00000014U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
+ // .. DIVISOR1 = 0x1
+ // .. ==> 0XF80001A0[25:20] = 0x00000001U
+ // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
+ // ..
+ EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U),
+ // .. CLK_621_TRUE = 0x1
+ // .. ==> 0XF80001C4[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // ..
+ EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
+ // .. DMA_CPU_2XCLKACT = 0x1
+ // .. ==> 0XF800012C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. USB0_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. USB1_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[3:3] = 0x00000001U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000008U
+ // .. GEM0_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[6:6] = 0x00000001U
+ // .. ==> MASK : 0x00000040U VAL : 0x00000040U
+ // .. GEM1_CPU_1XCLKACT = 0x0
+ // .. ==> 0XF800012C[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. SDI0_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[10:10] = 0x00000001U
+ // .. ==> MASK : 0x00000400U VAL : 0x00000400U
+ // .. SDI1_CPU_1XCLKACT = 0x0
+ // .. ==> 0XF800012C[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. SPI0_CPU_1XCLKACT = 0x0
+ // .. ==> 0XF800012C[14:14] = 0x00000000U
+ // .. ==> MASK : 0x00004000U VAL : 0x00000000U
+ // .. SPI1_CPU_1XCLKACT = 0x0
+ // .. ==> 0XF800012C[15:15] = 0x00000000U
+ // .. ==> MASK : 0x00008000U VAL : 0x00000000U
+ // .. CAN0_CPU_1XCLKACT = 0x0
+ // .. ==> 0XF800012C[16:16] = 0x00000000U
+ // .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. CAN1_CPU_1XCLKACT = 0x0
+ // .. ==> 0XF800012C[17:17] = 0x00000000U
+ // .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. I2C0_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[18:18] = 0x00000001U
+ // .. ==> MASK : 0x00040000U VAL : 0x00040000U
+ // .. I2C1_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[19:19] = 0x00000001U
+ // .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // .. UART0_CPU_1XCLKACT = 0x0
+ // .. ==> 0XF800012C[20:20] = 0x00000000U
+ // .. ==> MASK : 0x00100000U VAL : 0x00000000U
+ // .. UART1_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[21:21] = 0x00000001U
+ // .. ==> MASK : 0x00200000U VAL : 0x00200000U
+ // .. GPIO_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[22:22] = 0x00000001U
+ // .. ==> MASK : 0x00400000U VAL : 0x00400000U
+ // .. LQSPI_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[23:23] = 0x00000001U
+ // .. ==> MASK : 0x00800000U VAL : 0x00800000U
+ // .. SMC_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[24:24] = 0x00000001U
+ // .. ==> MASK : 0x01000000U VAL : 0x01000000U
+ // ..
+ EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC044DU),
+ // .. FINISH: CLOCK CONTROL SLCR REGISTERS
+ // .. START: THIS SHOULD BE BLANK
+ // .. FINISH: THIS SHOULD BE BLANK
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_ddr_init_data_2_0[] = {
+ // START: top
+ // .. START: DDR INITIALIZATION
+ // .. .. START: LOCK DDR
+ // .. .. reg_ddrc_soft_rstb = 0
+ // .. .. ==> 0XF8006000[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_powerdown_en = 0x0
+ // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_ddrc_data_bus_width = 0x0
+ // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U
+ // .. .. reg_ddrc_burst8_refresh = 0x0
+ // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U
+ // .. .. reg_ddrc_rdwr_idle_gap = 0x1
+ // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+ // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U
+ // .. .. reg_ddrc_dis_rd_bypass = 0x0
+ // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+ // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_act_bypass = 0x0
+ // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_auto_refresh = 0x0
+ // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
+ // .. .. FINISH: LOCK DDR
+ // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81
+ // .. .. ==> 0XF8006004[11:0] = 0x00000081U
+ // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U
+ // .. .. reg_ddrc_active_ranks = 0x1
+ // .. .. ==> 0XF8006004[13:12] = 0x00000001U
+ // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U
+ // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
+ // .. .. ==> 0XF8006004[18:14] = 0x00000000U
+ // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U
+ // .. .. reg_ddrc_wr_odt_block = 0x1
+ // .. .. ==> 0XF8006004[20:19] = 0x00000001U
+ // .. .. ==> MASK : 0x00180000U VAL : 0x00080000U
+ // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0
+ // .. .. ==> 0XF8006004[21:21] = 0x00000000U
+ // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0
+ // .. .. ==> 0XF8006004[26:22] = 0x00000000U
+ // .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_open_bank = 0x0
+ // .. .. ==> 0XF8006004[27:27] = 0x00000000U
+ // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_4bank_ram = 0x0
+ // .. .. ==> 0XF8006004[28:28] = 0x00000000U
+ // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U),
+ // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
+ // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU
+ // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
+ // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
+ // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U
+ // .. .. reg_ddrc_hpr_xact_run_length = 0xf
+ // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
+ // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
+ // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
+ // .. .. ==> 0XF800600C[10:0] = 0x00000001U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U
+ // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
+ // .. .. ==> 0XF800600C[21:11] = 0x00000002U
+ // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U
+ // .. .. reg_ddrc_lpr_xact_run_length = 0x8
+ // .. .. ==> 0XF800600C[25:22] = 0x00000008U
+ // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
+ // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
+ // .. .. ==> 0XF8006010[10:0] = 0x00000001U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U
+ // .. .. reg_ddrc_w_xact_run_length = 0x8
+ // .. .. ==> 0XF8006010[14:11] = 0x00000008U
+ // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U
+ // .. .. reg_ddrc_w_max_starve_x32 = 0x2
+ // .. .. ==> 0XF8006010[25:15] = 0x00000002U
+ // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
+ // .. .. reg_ddrc_t_rc = 0x1b
+ // .. .. ==> 0XF8006014[5:0] = 0x0000001BU
+ // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001BU
+ // .. .. reg_ddrc_t_rfc_min = 0x56
+ // .. .. ==> 0XF8006014[13:6] = 0x00000056U
+ // .. .. ==> MASK : 0x00003FC0U VAL : 0x00001580U
+ // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
+ // .. .. ==> 0XF8006014[20:14] = 0x00000010U
+ // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004159BU),
+ // .. .. reg_ddrc_wr2pre = 0x12
+ // .. .. ==> 0XF8006018[4:0] = 0x00000012U
+ // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U
+ // .. .. reg_ddrc_powerdown_to_x32 = 0x6
+ // .. .. ==> 0XF8006018[9:5] = 0x00000006U
+ // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U
+ // .. .. reg_ddrc_t_faw = 0x10
+ // .. .. ==> 0XF8006018[15:10] = 0x00000010U
+ // .. .. ==> MASK : 0x0000FC00U VAL : 0x00004000U
+ // .. .. reg_ddrc_t_ras_max = 0x24
+ // .. .. ==> 0XF8006018[21:16] = 0x00000024U
+ // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U
+ // .. .. reg_ddrc_t_ras_min = 0x14
+ // .. .. ==> 0XF8006018[26:22] = 0x00000014U
+ // .. .. ==> MASK : 0x07C00000U VAL : 0x05000000U
+ // .. .. reg_ddrc_t_cke = 0x4
+ // .. .. ==> 0XF8006018[31:28] = 0x00000004U
+ // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x452440D2U),
+ // .. .. reg_ddrc_write_latency = 0x5
+ // .. .. ==> 0XF800601C[4:0] = 0x00000005U
+ // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U
+ // .. .. reg_ddrc_rd2wr = 0x7
+ // .. .. ==> 0XF800601C[9:5] = 0x00000007U
+ // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U
+ // .. .. reg_ddrc_wr2rd = 0xe
+ // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
+ // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U
+ // .. .. reg_ddrc_t_xp = 0x4
+ // .. .. ==> 0XF800601C[19:15] = 0x00000004U
+ // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U
+ // .. .. reg_ddrc_pad_pd = 0x0
+ // .. .. ==> 0XF800601C[22:20] = 0x00000000U
+ // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U
+ // .. .. reg_ddrc_rd2pre = 0x4
+ // .. .. ==> 0XF800601C[27:23] = 0x00000004U
+ // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U
+ // .. .. reg_ddrc_t_rcd = 0x7
+ // .. .. ==> 0XF800601C[31:28] = 0x00000007U
+ // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
+ // .. .. reg_ddrc_t_ccd = 0x4
+ // .. .. ==> 0XF8006020[4:2] = 0x00000004U
+ // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U
+ // .. .. reg_ddrc_t_rrd = 0x4
+ // .. .. ==> 0XF8006020[7:5] = 0x00000004U
+ // .. .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. .. reg_ddrc_refresh_margin = 0x2
+ // .. .. ==> 0XF8006020[11:8] = 0x00000002U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
+ // .. .. reg_ddrc_t_rp = 0x7
+ // .. .. ==> 0XF8006020[15:12] = 0x00000007U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U
+ // .. .. reg_ddrc_refresh_to_x32 = 0x8
+ // .. .. ==> 0XF8006020[20:16] = 0x00000008U
+ // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U
+ // .. .. reg_ddrc_sdram = 0x1
+ // .. .. ==> 0XF8006020[21:21] = 0x00000001U
+ // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U
+ // .. .. reg_ddrc_mobile = 0x0
+ // .. .. ==> 0XF8006020[22:22] = 0x00000000U
+ // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U
+ // .. .. reg_ddrc_clock_stop_en = 0x0
+ // .. .. ==> 0XF8006020[23:23] = 0x00000000U
+ // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U
+ // .. .. reg_ddrc_read_latency = 0x7
+ // .. .. ==> 0XF8006020[28:24] = 0x00000007U
+ // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U
+ // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
+ // .. .. ==> 0XF8006020[29:29] = 0x00000001U
+ // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U
+ // .. .. reg_ddrc_dis_pad_pd = 0x0
+ // .. .. ==> 0XF8006020[30:30] = 0x00000000U
+ // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_loopback = 0x0
+ // .. .. ==> 0XF8006020[31:31] = 0x00000000U
+ // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x27287290U),
+ // .. .. reg_ddrc_en_2t_timing_mode = 0x0
+ // .. .. ==> 0XF8006024[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_prefer_write = 0x0
+ // .. .. ==> 0XF8006024[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_ddrc_max_rank_rd = 0xf
+ // .. .. ==> 0XF8006024[5:2] = 0x0000000FU
+ // .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU
+ // .. .. reg_ddrc_mr_wr = 0x0
+ // .. .. ==> 0XF8006024[6:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr_addr = 0x0
+ // .. .. ==> 0XF8006024[8:7] = 0x00000000U
+ // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr_data = 0x0
+ // .. .. ==> 0XF8006024[24:9] = 0x00000000U
+ // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U
+ // .. .. ddrc_reg_mr_wr_busy = 0x0
+ // .. .. ==> 0XF8006024[25:25] = 0x00000000U
+ // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr_type = 0x0
+ // .. .. ==> 0XF8006024[26:26] = 0x00000000U
+ // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr_rdata_valid = 0x0
+ // .. .. ==> 0XF8006024[27:27] = 0x00000000U
+ // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU),
+ // .. .. reg_ddrc_final_wait_x32 = 0x7
+ // .. .. ==> 0XF8006028[6:0] = 0x00000007U
+ // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U
+ // .. .. reg_ddrc_pre_ocd_x32 = 0x0
+ // .. .. ==> 0XF8006028[10:7] = 0x00000000U
+ // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U
+ // .. .. reg_ddrc_t_mrd = 0x4
+ // .. .. ==> 0XF8006028[13:11] = 0x00000004U
+ // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
+ // .. .. reg_ddrc_emr2 = 0x8
+ // .. .. ==> 0XF800602C[15:0] = 0x00000008U
+ // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U
+ // .. .. reg_ddrc_emr3 = 0x0
+ // .. .. ==> 0XF800602C[31:16] = 0x00000000U
+ // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
+ // .. .. reg_ddrc_mr = 0x930
+ // .. .. ==> 0XF8006030[15:0] = 0x00000930U
+ // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U
+ // .. .. reg_ddrc_emr = 0x4
+ // .. .. ==> 0XF8006030[31:16] = 0x00000004U
+ // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
+ // .. .. reg_ddrc_burst_rdwr = 0x4
+ // .. .. ==> 0XF8006034[3:0] = 0x00000004U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U
+ // .. .. reg_ddrc_pre_cke_x1024 = 0x105
+ // .. .. ==> 0XF8006034[13:4] = 0x00000105U
+ // .. .. ==> MASK : 0x00003FF0U VAL : 0x00001050U
+ // .. .. reg_ddrc_post_cke_x1024 = 0x1
+ // .. .. ==> 0XF8006034[25:16] = 0x00000001U
+ // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U
+ // .. .. reg_ddrc_burstchop = 0x0
+ // .. .. ==> 0XF8006034[28:28] = 0x00000000U
+ // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U),
+ // .. .. reg_ddrc_force_low_pri_n = 0x0
+ // .. .. ==> 0XF8006038[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_dq = 0x0
+ // .. .. ==> 0XF8006038[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_debug_mode = 0x0
+ // .. .. ==> 0XF8006038[6:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U
+ // .. .. reg_phy_wr_level_start = 0x0
+ // .. .. ==> 0XF8006038[7:7] = 0x00000000U
+ // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. .. reg_phy_rd_level_start = 0x0
+ // .. .. ==> 0XF8006038[8:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. .. reg_phy_dq0_wait_t = 0x0
+ // .. .. ==> 0XF8006038[12:9] = 0x00000000U
+ // .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U),
+ // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
+ // .. .. ==> 0XF800603C[3:0] = 0x00000007U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U
+ // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
+ // .. .. ==> 0XF800603C[7:4] = 0x00000007U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U
+ // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
+ // .. .. ==> 0XF800603C[11:8] = 0x00000007U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U
+ // .. .. reg_ddrc_addrmap_col_b5 = 0x0
+ // .. .. ==> 0XF800603C[15:12] = 0x00000000U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b6 = 0x0
+ // .. .. ==> 0XF800603C[19:16] = 0x00000000U
+ // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
+ // .. .. reg_ddrc_addrmap_col_b2 = 0x0
+ // .. .. ==> 0XF8006040[3:0] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b3 = 0x0
+ // .. .. ==> 0XF8006040[7:4] = 0x00000000U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b4 = 0x0
+ // .. .. ==> 0XF8006040[11:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b7 = 0x0
+ // .. .. ==> 0XF8006040[15:12] = 0x00000000U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b8 = 0x0
+ // .. .. ==> 0XF8006040[19:16] = 0x00000000U
+ // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b9 = 0xf
+ // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
+ // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U
+ // .. .. reg_ddrc_addrmap_col_b10 = 0xf
+ // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
+ // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U
+ // .. .. reg_ddrc_addrmap_col_b11 = 0xf
+ // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
+ // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
+ // .. .. reg_ddrc_addrmap_row_b0 = 0x6
+ // .. .. ==> 0XF8006044[3:0] = 0x00000006U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U
+ // .. .. reg_ddrc_addrmap_row_b1 = 0x6
+ // .. .. ==> 0XF8006044[7:4] = 0x00000006U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U
+ // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
+ // .. .. ==> 0XF8006044[11:8] = 0x00000006U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U
+ // .. .. reg_ddrc_addrmap_row_b12 = 0x6
+ // .. .. ==> 0XF8006044[15:12] = 0x00000006U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U
+ // .. .. reg_ddrc_addrmap_row_b13 = 0x6
+ // .. .. ==> 0XF8006044[19:16] = 0x00000006U
+ // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U
+ // .. .. reg_ddrc_addrmap_row_b14 = 0x6
+ // .. .. ==> 0XF8006044[23:20] = 0x00000006U
+ // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U
+ // .. .. reg_ddrc_addrmap_row_b15 = 0xf
+ // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
+ // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U),
+ // .. .. reg_ddrc_rank0_rd_odt = 0x0
+ // .. .. ==> 0XF8006048[2:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U
+ // .. .. reg_ddrc_rank0_wr_odt = 0x1
+ // .. .. ==> 0XF8006048[5:3] = 0x00000001U
+ // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U
+ // .. .. reg_ddrc_rank1_rd_odt = 0x1
+ // .. .. ==> 0XF8006048[8:6] = 0x00000001U
+ // .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U
+ // .. .. reg_ddrc_rank1_wr_odt = 0x1
+ // .. .. ==> 0XF8006048[11:9] = 0x00000001U
+ // .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. .. reg_phy_rd_local_odt = 0x0
+ // .. .. ==> 0XF8006048[13:12] = 0x00000000U
+ // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U
+ // .. .. reg_phy_wr_local_odt = 0x3
+ // .. .. ==> 0XF8006048[15:14] = 0x00000003U
+ // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U
+ // .. .. reg_phy_idle_local_odt = 0x3
+ // .. .. ==> 0XF8006048[17:16] = 0x00000003U
+ // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U
+ // .. .. reg_ddrc_rank2_rd_odt = 0x0
+ // .. .. ==> 0XF8006048[20:18] = 0x00000000U
+ // .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U
+ // .. .. reg_ddrc_rank2_wr_odt = 0x0
+ // .. .. ==> 0XF8006048[23:21] = 0x00000000U
+ // .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U
+ // .. .. reg_ddrc_rank3_rd_odt = 0x0
+ // .. .. ==> 0XF8006048[26:24] = 0x00000000U
+ // .. .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_rank3_wr_odt = 0x0
+ // .. .. ==> 0XF8006048[29:27] = 0x00000000U
+ // .. .. ==> MASK : 0x38000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U),
+ // .. .. reg_phy_rd_cmd_to_data = 0x0
+ // .. .. ==> 0XF8006050[3:0] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
+ // .. .. reg_phy_wr_cmd_to_data = 0x0
+ // .. .. ==> 0XF8006050[7:4] = 0x00000000U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. .. reg_phy_rdc_we_to_re_delay = 0x8
+ // .. .. ==> 0XF8006050[11:8] = 0x00000008U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U
+ // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
+ // .. .. ==> 0XF8006050[15:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
+ // .. .. reg_phy_use_fixed_re = 0x1
+ // .. .. ==> 0XF8006050[16:16] = 0x00000001U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U
+ // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
+ // .. .. ==> 0XF8006050[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
+ // .. .. ==> 0XF8006050[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_phy_clk_stall_level = 0x0
+ // .. .. ==> 0XF8006050[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
+ // .. .. ==> 0XF8006050[27:24] = 0x00000007U
+ // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U
+ // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
+ // .. .. ==> 0XF8006050[31:28] = 0x00000007U
+ // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
+ // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1
+ // .. .. ==> 0XF8006058[7:0] = 0x00000001U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U
+ // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1
+ // .. .. ==> 0XF8006058[15:8] = 0x00000001U
+ // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U
+ // .. .. reg_ddrc_dis_dll_calib = 0x0
+ // .. .. ==> 0XF8006058[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U),
+ // .. .. reg_ddrc_rd_odt_delay = 0x3
+ // .. .. ==> 0XF800605C[3:0] = 0x00000003U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U
+ // .. .. reg_ddrc_wr_odt_delay = 0x0
+ // .. .. ==> 0XF800605C[7:4] = 0x00000000U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. .. reg_ddrc_rd_odt_hold = 0x0
+ // .. .. ==> 0XF800605C[11:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U
+ // .. .. reg_ddrc_wr_odt_hold = 0x5
+ // .. .. ==> 0XF800605C[15:12] = 0x00000005U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
+ // .. .. reg_ddrc_pageclose = 0x0
+ // .. .. ==> 0XF8006060[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_lpr_num_entries = 0x1f
+ // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
+ // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU
+ // .. .. reg_ddrc_auto_pre_en = 0x0
+ // .. .. ==> 0XF8006060[7:7] = 0x00000000U
+ // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. .. reg_ddrc_refresh_update_level = 0x0
+ // .. .. ==> 0XF8006060[8:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_wc = 0x0
+ // .. .. ==> 0XF8006060[9:9] = 0x00000000U
+ // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_collision_page_opt = 0x0
+ // .. .. ==> 0XF8006060[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_ddrc_selfref_en = 0x0
+ // .. .. ==> 0XF8006060[12:12] = 0x00000000U
+ // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
+ // .. .. reg_ddrc_go2critical_hysteresis = 0x0
+ // .. .. ==> 0XF8006064[12:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U
+ // .. .. reg_arb_go2critical_en = 0x1
+ // .. .. ==> 0XF8006064[17:17] = 0x00000001U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
+ // .. .. reg_ddrc_wrlvl_ww = 0x41
+ // .. .. ==> 0XF8006068[7:0] = 0x00000041U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U
+ // .. .. reg_ddrc_rdlvl_rr = 0x41
+ // .. .. ==> 0XF8006068[15:8] = 0x00000041U
+ // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U
+ // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
+ // .. .. ==> 0XF8006068[25:16] = 0x00000028U
+ // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
+ // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
+ // .. .. ==> 0XF800606C[7:0] = 0x00000010U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U
+ // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
+ // .. .. ==> 0XF800606C[15:8] = 0x00000016U
+ // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U
+ // .. ..
+ EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
+ // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1
+ // .. .. ==> 0XF8006078[3:0] = 0x00000001U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U
+ // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1
+ // .. .. ==> 0XF8006078[7:4] = 0x00000001U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U
+ // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1
+ // .. .. ==> 0XF8006078[11:8] = 0x00000001U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U
+ // .. .. reg_ddrc_t_cksre = 0x6
+ // .. .. ==> 0XF8006078[15:12] = 0x00000006U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U
+ // .. .. reg_ddrc_t_cksrx = 0x6
+ // .. .. ==> 0XF8006078[19:16] = 0x00000006U
+ // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U
+ // .. .. reg_ddrc_t_ckesr = 0x4
+ // .. .. ==> 0XF8006078[25:20] = 0x00000004U
+ // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U),
+ // .. .. reg_ddrc_t_ckpde = 0x2
+ // .. .. ==> 0XF800607C[3:0] = 0x00000002U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U
+ // .. .. reg_ddrc_t_ckpdx = 0x2
+ // .. .. ==> 0XF800607C[7:4] = 0x00000002U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
+ // .. .. reg_ddrc_t_ckdpde = 0x2
+ // .. .. ==> 0XF800607C[11:8] = 0x00000002U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
+ // .. .. reg_ddrc_t_ckdpdx = 0x2
+ // .. .. ==> 0XF800607C[15:12] = 0x00000002U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U
+ // .. .. reg_ddrc_t_ckcsx = 0x3
+ // .. .. ==> 0XF800607C[19:16] = 0x00000003U
+ // .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U),
+ // .. .. refresh_timer0_start_value_x32 = 0x0
+ // .. .. ==> 0XF80060A0[11:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U
+ // .. .. refresh_timer1_start_value_x32 = 0x8
+ // .. .. ==> 0XF80060A0[23:12] = 0x00000008U
+ // .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U),
+ // .. .. reg_ddrc_dis_auto_zq = 0x0
+ // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_ddr3 = 0x1
+ // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. .. reg_ddrc_t_mod = 0x200
+ // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
+ // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U
+ // .. .. reg_ddrc_t_zq_long_nop = 0x200
+ // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U
+ // .. .. reg_ddrc_t_zq_short_nop = 0x40
+ // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
+ // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
+ // .. .. t_zq_short_interval_x1024 = 0xcb73
+ // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U
+ // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U
+ // .. .. dram_rstn_x1024 = 0x69
+ // .. .. ==> 0XF80060A8[27:20] = 0x00000069U
+ // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
+ // .. .. deeppowerdown_en = 0x0
+ // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. deeppowerdown_to_x1024 = 0xff
+ // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
+ // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU
+ // .. ..
+ EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
+ // .. .. dfi_wrlvl_max_x1024 = 0xfff
+ // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
+ // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU
+ // .. .. dfi_rdlvl_max_x1024 = 0xfff
+ // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
+ // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U
+ // .. .. ddrc_reg_twrlvl_max_error = 0x0
+ // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
+ // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U
+ // .. .. ddrc_reg_trdlvl_max_error = 0x0
+ // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
+ // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dfi_wr_level_en = 0x1
+ // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
+ // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U
+ // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
+ // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
+ // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U
+ // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
+ // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
+ // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
+ // .. .. reg_ddrc_2t_delay = 0x0
+ // .. .. ==> 0XF80060B4[8:0] = 0x00000000U
+ // .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U
+ // .. .. reg_ddrc_skip_ocd = 0x1
+ // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
+ // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U
+ // .. .. reg_ddrc_dis_pre_bypass = 0x0
+ // .. .. ==> 0XF80060B4[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U),
+ // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
+ // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
+ // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U
+ // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
+ // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
+ // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U
+ // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
+ // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
+ // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
+ // .. .. START: RESET ECC ERROR
+ // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1
+ // .. .. ==> 0XF80060C4[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. Clear_Correctable_DRAM_ECC_error = 1
+ // .. .. ==> 0XF80060C4[1:1] = 0x00000001U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U),
+ // .. .. FINISH: RESET ECC ERROR
+ // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
+ // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
+ // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
+ // .. .. CORR_ECC_LOG_VALID = 0x0
+ // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. ECC_CORRECTED_BIT_NUM = 0x0
+ // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
+ // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
+ // .. .. UNCORR_ECC_LOG_VALID = 0x0
+ // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
+ // .. .. STAT_NUM_CORR_ERR = 0x0
+ // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
+ // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U
+ // .. .. STAT_NUM_UNCORR_ERR = 0x0
+ // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
+ // .. .. reg_ddrc_ecc_mode = 0x0
+ // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_scrub = 0x1
+ // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
+ // .. .. reg_phy_dif_on = 0x0
+ // .. .. ==> 0XF8006114[3:0] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
+ // .. .. reg_phy_dif_off = 0x0
+ // .. .. ==> 0XF8006114[7:4] = 0x00000000U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
+ // .. .. reg_phy_data_slice_in_use = 0x1
+ // .. .. ==> 0XF8006118[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_phy_rdlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006118[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006118[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_wrlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006118[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_tx = 0x0
+ // .. .. ==> 0XF8006118[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_rx = 0x0
+ // .. .. ==> 0XF8006118[5:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
+ // .. .. reg_phy_bist_shift_dq = 0x0
+ // .. .. ==> 0XF8006118[14:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
+ // .. .. reg_phy_bist_err_clr = 0x0
+ // .. .. ==> 0XF8006118[23:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
+ // .. .. reg_phy_dq_offset = 0x40
+ // .. .. ==> 0XF8006118[30:24] = 0x00000040U
+ // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U),
+ // .. .. reg_phy_data_slice_in_use = 0x1
+ // .. .. ==> 0XF800611C[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_phy_rdlvl_inc_mode = 0x0
+ // .. .. ==> 0XF800611C[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_inc_mode = 0x0
+ // .. .. ==> 0XF800611C[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_wrlvl_inc_mode = 0x0
+ // .. .. ==> 0XF800611C[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_tx = 0x0
+ // .. .. ==> 0XF800611C[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_rx = 0x0
+ // .. .. ==> 0XF800611C[5:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
+ // .. .. reg_phy_bist_shift_dq = 0x0
+ // .. .. ==> 0XF800611C[14:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
+ // .. .. reg_phy_bist_err_clr = 0x0
+ // .. .. ==> 0XF800611C[23:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
+ // .. .. reg_phy_dq_offset = 0x40
+ // .. .. ==> 0XF800611C[30:24] = 0x00000040U
+ // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U),
+ // .. .. reg_phy_data_slice_in_use = 0x1
+ // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_phy_rdlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_wrlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_tx = 0x0
+ // .. .. ==> 0XF8006120[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_rx = 0x0
+ // .. .. ==> 0XF8006120[5:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
+ // .. .. reg_phy_bist_shift_dq = 0x0
+ // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
+ // .. .. reg_phy_bist_err_clr = 0x0
+ // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
+ // .. .. reg_phy_dq_offset = 0x40
+ // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+ // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
+ // .. .. reg_phy_data_slice_in_use = 0x1
+ // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_phy_rdlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_wrlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_tx = 0x0
+ // .. .. ==> 0XF8006120[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_rx = 0x0
+ // .. .. ==> 0XF8006120[5:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
+ // .. .. reg_phy_bist_shift_dq = 0x0
+ // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
+ // .. .. reg_phy_bist_err_clr = 0x0
+ // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
+ // .. .. reg_phy_dq_offset = 0x40
+ // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+ // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U),
+ // .. .. reg_phy_data_slice_in_use = 0x1
+ // .. .. ==> 0XF8006124[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_phy_rdlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006124[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006124[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_wrlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006124[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_tx = 0x0
+ // .. .. ==> 0XF8006124[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_rx = 0x0
+ // .. .. ==> 0XF8006124[5:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
+ // .. .. reg_phy_bist_shift_dq = 0x0
+ // .. .. ==> 0XF8006124[14:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
+ // .. .. reg_phy_bist_err_clr = 0x0
+ // .. .. ==> 0XF8006124[23:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
+ // .. .. reg_phy_dq_offset = 0x40
+ // .. .. ==> 0XF8006124[30:24] = 0x00000040U
+ // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U),
+ // .. .. reg_phy_wrlvl_init_ratio = 0x1e
+ // .. .. ==> 0XF800612C[9:0] = 0x0000001EU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x0000001EU
+ // .. .. reg_phy_gatelvl_init_ratio = 0xee
+ // .. .. ==> 0XF800612C[19:10] = 0x000000EEU
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x0003B800U
+ // .. ..
+ EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0003B81EU),
+ // .. .. reg_phy_wrlvl_init_ratio = 0x25
+ // .. .. ==> 0XF8006130[9:0] = 0x00000025U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000025U
+ // .. .. reg_phy_gatelvl_init_ratio = 0x10d
+ // .. .. ==> 0XF8006130[19:10] = 0x0000010DU
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x00043400U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00043425U),
+ // .. .. reg_phy_wrlvl_init_ratio = 0x19
+ // .. .. ==> 0XF8006134[9:0] = 0x00000019U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000019U
+ // .. .. reg_phy_gatelvl_init_ratio = 0xf3
+ // .. .. ==> 0XF8006134[19:10] = 0x000000F3U
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x0003CC00U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0003CC19U),
+ // .. .. reg_phy_wrlvl_init_ratio = 0x2a
+ // .. .. ==> 0XF8006138[9:0] = 0x0000002AU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x0000002AU
+ // .. .. reg_phy_gatelvl_init_ratio = 0x109
+ // .. .. ==> 0XF8006138[19:10] = 0x00000109U
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x00042400U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0004242AU),
+ // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+ // .. .. ==> 0XF8006140[9:0] = 0x00000035U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
+ // .. .. reg_phy_rd_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006140[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006140[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
+ // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+ // .. .. ==> 0XF8006144[9:0] = 0x00000035U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
+ // .. .. reg_phy_rd_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006144[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006144[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
+ // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+ // .. .. ==> 0XF8006148[9:0] = 0x00000035U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
+ // .. .. reg_phy_rd_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006148[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006148[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
+ // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+ // .. .. ==> 0XF800614C[9:0] = 0x00000035U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
+ // .. .. reg_phy_rd_dqs_slave_force = 0x0
+ // .. .. ==> 0XF800614C[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF800614C[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
+ // .. .. reg_phy_wr_dqs_slave_ratio = 0x9e
+ // .. .. ==> 0XF8006154[9:0] = 0x0000009EU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x0000009EU
+ // .. .. reg_phy_wr_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006154[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006154[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x0000009EU),
+ // .. .. reg_phy_wr_dqs_slave_ratio = 0xa5
+ // .. .. ==> 0XF8006158[9:0] = 0x000000A5U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000A5U
+ // .. .. reg_phy_wr_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006158[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006158[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x000000A5U),
+ // .. .. reg_phy_wr_dqs_slave_ratio = 0x99
+ // .. .. ==> 0XF800615C[9:0] = 0x00000099U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000099U
+ // .. .. reg_phy_wr_dqs_slave_force = 0x0
+ // .. .. ==> 0XF800615C[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF800615C[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000099U),
+ // .. .. reg_phy_wr_dqs_slave_ratio = 0xaa
+ // .. .. ==> 0XF8006160[9:0] = 0x000000AAU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000AAU
+ // .. .. reg_phy_wr_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006160[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006160[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x000000AAU),
+ // .. .. reg_phy_fifo_we_slave_ratio = 0x143
+ // .. .. ==> 0XF8006168[10:0] = 0x00000143U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000143U
+ // .. .. reg_phy_fifo_we_in_force = 0x0
+ // .. .. ==> 0XF8006168[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. reg_phy_fifo_we_in_delay = 0x0
+ // .. .. ==> 0XF8006168[20:12] = 0x00000000U
+ // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000143U),
+ // .. .. reg_phy_fifo_we_slave_ratio = 0x162
+ // .. .. ==> 0XF800616C[10:0] = 0x00000162U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000162U
+ // .. .. reg_phy_fifo_we_in_force = 0x0
+ // .. .. ==> 0XF800616C[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. reg_phy_fifo_we_in_delay = 0x0
+ // .. .. ==> 0XF800616C[20:12] = 0x00000000U
+ // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x00000162U),
+ // .. .. reg_phy_fifo_we_slave_ratio = 0x148
+ // .. .. ==> 0XF8006170[10:0] = 0x00000148U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000148U
+ // .. .. reg_phy_fifo_we_in_force = 0x0
+ // .. .. ==> 0XF8006170[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. reg_phy_fifo_we_in_delay = 0x0
+ // .. .. ==> 0XF8006170[20:12] = 0x00000000U
+ // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000148U),
+ // .. .. reg_phy_fifo_we_slave_ratio = 0x15e
+ // .. .. ==> 0XF8006174[10:0] = 0x0000015EU
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x0000015EU
+ // .. .. reg_phy_fifo_we_in_force = 0x0
+ // .. .. ==> 0XF8006174[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. reg_phy_fifo_we_in_delay = 0x0
+ // .. .. ==> 0XF8006174[20:12] = 0x00000000U
+ // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x0000015EU),
+ // .. .. reg_phy_wr_data_slave_ratio = 0xde
+ // .. .. ==> 0XF800617C[9:0] = 0x000000DEU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000DEU
+ // .. .. reg_phy_wr_data_slave_force = 0x0
+ // .. .. ==> 0XF800617C[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_data_slave_delay = 0x0
+ // .. .. ==> 0XF800617C[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000DEU),
+ // .. .. reg_phy_wr_data_slave_ratio = 0xe5
+ // .. .. ==> 0XF8006180[9:0] = 0x000000E5U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000E5U
+ // .. .. reg_phy_wr_data_slave_force = 0x0
+ // .. .. ==> 0XF8006180[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_data_slave_delay = 0x0
+ // .. .. ==> 0XF8006180[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000E5U),
+ // .. .. reg_phy_wr_data_slave_ratio = 0xd9
+ // .. .. ==> 0XF8006184[9:0] = 0x000000D9U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000D9U
+ // .. .. reg_phy_wr_data_slave_force = 0x0
+ // .. .. ==> 0XF8006184[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_data_slave_delay = 0x0
+ // .. .. ==> 0XF8006184[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000D9U),
+ // .. .. reg_phy_wr_data_slave_ratio = 0xea
+ // .. .. ==> 0XF8006188[9:0] = 0x000000EAU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000EAU
+ // .. .. reg_phy_wr_data_slave_force = 0x0
+ // .. .. ==> 0XF8006188[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_data_slave_delay = 0x0
+ // .. .. ==> 0XF8006188[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000EAU),
+ // .. .. reg_phy_loopback = 0x0
+ // .. .. ==> 0XF8006190[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_phy_bl2 = 0x0
+ // .. .. ==> 0XF8006190[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_at_spd_atpg = 0x0
+ // .. .. ==> 0XF8006190[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_bist_enable = 0x0
+ // .. .. ==> 0XF8006190[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_bist_force_err = 0x0
+ // .. .. ==> 0XF8006190[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reg_phy_bist_mode = 0x0
+ // .. .. ==> 0XF8006190[6:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U
+ // .. .. reg_phy_invert_clkout = 0x1
+ // .. .. ==> 0XF8006190[7:7] = 0x00000001U
+ // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0
+ // .. .. ==> 0XF8006190[8:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. .. reg_phy_sel_logic = 0x0
+ // .. .. ==> 0XF8006190[9:9] = 0x00000000U
+ // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U
+ // .. .. reg_phy_ctrl_slave_ratio = 0x100
+ // .. .. ==> 0XF8006190[19:10] = 0x00000100U
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U
+ // .. .. reg_phy_ctrl_slave_force = 0x0
+ // .. .. ==> 0XF8006190[20:20] = 0x00000000U
+ // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U
+ // .. .. reg_phy_ctrl_slave_delay = 0x0
+ // .. .. ==> 0XF8006190[27:21] = 0x00000000U
+ // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U
+ // .. .. reg_phy_use_rank0_delays = 0x1
+ // .. .. ==> 0XF8006190[28:28] = 0x00000001U
+ // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
+ // .. .. reg_phy_lpddr = 0x0
+ // .. .. ==> 0XF8006190[29:29] = 0x00000000U
+ // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U
+ // .. .. reg_phy_cmd_latency = 0x0
+ // .. .. ==> 0XF8006190[30:30] = 0x00000000U
+ // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U
+ // .. .. reg_phy_int_lpbk = 0x0
+ // .. .. ==> 0XF8006190[31:31] = 0x00000000U
+ // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U),
+ // .. .. reg_phy_wr_rl_delay = 0x2
+ // .. .. ==> 0XF8006194[4:0] = 0x00000002U
+ // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U
+ // .. .. reg_phy_rd_rl_delay = 0x4
+ // .. .. ==> 0XF8006194[9:5] = 0x00000004U
+ // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U
+ // .. .. reg_phy_dll_lock_diff = 0xf
+ // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
+ // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U
+ // .. .. reg_phy_use_wr_level = 0x1
+ // .. .. ==> 0XF8006194[14:14] = 0x00000001U
+ // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U
+ // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
+ // .. .. ==> 0XF8006194[15:15] = 0x00000001U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U
+ // .. .. reg_phy_use_rd_data_eye_level = 0x1
+ // .. .. ==> 0XF8006194[16:16] = 0x00000001U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U
+ // .. .. reg_phy_dis_calib_rst = 0x0
+ // .. .. ==> 0XF8006194[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_phy_ctrl_slave_delay = 0x0
+ // .. .. ==> 0XF8006194[19:18] = 0x00000000U
+ // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
+ // .. .. reg_arb_page_addr_mask = 0x0
+ // .. .. ==> 0XF8006204[31:0] = 0x00000000U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
+ // .. .. reg_arb_pri_wr_portn = 0x3ff
+ // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_wr_portn = 0x0
+ // .. .. ==> 0XF8006208[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+ // .. .. ==> 0XF8006208[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+ // .. .. ==> 0XF8006208[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_rmw_portn = 0x1
+ // .. .. ==> 0XF8006208[19:19] = 0x00000001U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU),
+ // .. .. reg_arb_pri_wr_portn = 0x3ff
+ // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_wr_portn = 0x0
+ // .. .. ==> 0XF800620C[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+ // .. .. ==> 0XF800620C[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+ // .. .. ==> 0XF800620C[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_rmw_portn = 0x1
+ // .. .. ==> 0XF800620C[19:19] = 0x00000001U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU),
+ // .. .. reg_arb_pri_wr_portn = 0x3ff
+ // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_wr_portn = 0x0
+ // .. .. ==> 0XF8006210[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+ // .. .. ==> 0XF8006210[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+ // .. .. ==> 0XF8006210[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_rmw_portn = 0x1
+ // .. .. ==> 0XF8006210[19:19] = 0x00000001U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU),
+ // .. .. reg_arb_pri_wr_portn = 0x3ff
+ // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_wr_portn = 0x0
+ // .. .. ==> 0XF8006214[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+ // .. .. ==> 0XF8006214[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+ // .. .. ==> 0XF8006214[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_rmw_portn = 0x1
+ // .. .. ==> 0XF8006214[19:19] = 0x00000001U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU),
+ // .. .. reg_arb_pri_rd_portn = 0x3ff
+ // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_rd_portn = 0x0
+ // .. .. ==> 0XF8006218[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+ // .. .. ==> 0XF8006218[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+ // .. .. ==> 0XF8006218[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_set_hpr_rd_portn = 0x0
+ // .. .. ==> 0XF8006218[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
+ // .. .. reg_arb_pri_rd_portn = 0x3ff
+ // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_rd_portn = 0x0
+ // .. .. ==> 0XF800621C[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+ // .. .. ==> 0XF800621C[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+ // .. .. ==> 0XF800621C[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_set_hpr_rd_portn = 0x0
+ // .. .. ==> 0XF800621C[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
+ // .. .. reg_arb_pri_rd_portn = 0x3ff
+ // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_rd_portn = 0x0
+ // .. .. ==> 0XF8006220[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+ // .. .. ==> 0XF8006220[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+ // .. .. ==> 0XF8006220[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_set_hpr_rd_portn = 0x0
+ // .. .. ==> 0XF8006220[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
+ // .. .. reg_arb_pri_rd_portn = 0x3ff
+ // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_rd_portn = 0x0
+ // .. .. ==> 0XF8006224[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+ // .. .. ==> 0XF8006224[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+ // .. .. ==> 0XF8006224[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_set_hpr_rd_portn = 0x0
+ // .. .. ==> 0XF8006224[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
+ // .. .. reg_ddrc_lpddr2 = 0x0
+ // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_per_bank_refresh = 0x0
+ // .. .. ==> 0XF80062A8[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_ddrc_derate_enable = 0x0
+ // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr4_margin = 0x0
+ // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U),
+ // .. .. reg_ddrc_mr4_read_interval = 0x0
+ // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
+ // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
+ // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U
+ // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
+ // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
+ // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U
+ // .. .. reg_ddrc_t_mrw = 0x5
+ // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
+ // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8
+ // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U
+ // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
+ // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
+ // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U
+ // .. ..
+ EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
+ // .. .. START: POLL ON DCI STATUS
+ // .. .. DONE = 1
+ // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
+ // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U
+ // .. ..
+ EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+ // .. .. FINISH: POLL ON DCI STATUS
+ // .. .. START: UNLOCK DDR
+ // .. .. reg_ddrc_soft_rstb = 0x1
+ // .. .. ==> 0XF8006000[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_ddrc_powerdown_en = 0x0
+ // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_ddrc_data_bus_width = 0x0
+ // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U
+ // .. .. reg_ddrc_burst8_refresh = 0x0
+ // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U
+ // .. .. reg_ddrc_rdwr_idle_gap = 1
+ // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+ // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U
+ // .. .. reg_ddrc_dis_rd_bypass = 0x0
+ // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+ // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_act_bypass = 0x0
+ // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_auto_refresh = 0x0
+ // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
+ // .. .. FINISH: UNLOCK DDR
+ // .. .. START: CHECK DDR STATUS
+ // .. .. ddrc_reg_operating_mode = 1
+ // .. .. ==> 0XF8006054[2:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U
+ // .. ..
+ EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+ // .. .. FINISH: CHECK DDR STATUS
+ // .. FINISH: DDR INITIALIZATION
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_mio_init_data_2_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: OCM REMAPPING
+ // .. VREF_EN = 0x1
+ // .. ==> 0XF8000B00[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. VREF_PULLUP_EN = 0x0
+ // .. ==> 0XF8000B00[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. CLK_PULLUP_EN = 0x0
+ // .. ==> 0XF8000B00[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. SRSTN_PULLUP_EN = 0x0
+ // .. ==> 0XF8000B00[9:9] = 0x00000000U
+ // .. ==> MASK : 0x00000200U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B00, 0x00000303U ,0x00000001U),
+ // .. FINISH: OCM REMAPPING
+ // .. START: DDRIOB SETTINGS
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B40[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x0
+ // .. ==> 0XF8000B40[2:1] = 0x00000000U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000000U
+ // .. DCI_UPDATE = 0x0
+ // .. ==> 0XF8000B40[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x0
+ // .. ==> 0XF8000B40[4:4] = 0x00000000U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. DCR_TYPE = 0x0
+ // .. ==> 0XF8000B40[6:5] = 0x00000000U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000000U
+ // .. IBUF_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B40[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B40[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B40[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B40[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B44[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x0
+ // .. ==> 0XF8000B44[2:1] = 0x00000000U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000000U
+ // .. DCI_UPDATE = 0x0
+ // .. ==> 0XF8000B44[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x0
+ // .. ==> 0XF8000B44[4:4] = 0x00000000U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. DCR_TYPE = 0x0
+ // .. ==> 0XF8000B44[6:5] = 0x00000000U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000000U
+ // .. IBUF_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B44[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B44[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B44[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B44[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B48[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x1
+ // .. ==> 0XF8000B48[2:1] = 0x00000001U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000002U
+ // .. DCI_UPDATE = 0x0
+ // .. ==> 0XF8000B48[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x1
+ // .. ==> 0XF8000B48[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. DCR_TYPE = 0x3
+ // .. ==> 0XF8000B48[6:5] = 0x00000003U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000060U
+ // .. IBUF_DISABLE_MODE = 0
+ // .. ==> 0XF8000B48[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0
+ // .. ==> 0XF8000B48[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B48[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B48[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B4C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x1
+ // .. ==> 0XF8000B4C[2:1] = 0x00000001U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000002U
+ // .. DCI_UPDATE = 0x0
+ // .. ==> 0XF8000B4C[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x1
+ // .. ==> 0XF8000B4C[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. DCR_TYPE = 0x3
+ // .. ==> 0XF8000B4C[6:5] = 0x00000003U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000060U
+ // .. IBUF_DISABLE_MODE = 0
+ // .. ==> 0XF8000B4C[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0
+ // .. ==> 0XF8000B4C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B4C[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B4C[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B50[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x2
+ // .. ==> 0XF8000B50[2:1] = 0x00000002U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000004U
+ // .. DCI_UPDATE = 0x0
+ // .. ==> 0XF8000B50[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x1
+ // .. ==> 0XF8000B50[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. DCR_TYPE = 0x3
+ // .. ==> 0XF8000B50[6:5] = 0x00000003U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000060U
+ // .. IBUF_DISABLE_MODE = 0
+ // .. ==> 0XF8000B50[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0
+ // .. ==> 0XF8000B50[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B50[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B50[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B54[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x2
+ // .. ==> 0XF8000B54[2:1] = 0x00000002U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000004U
+ // .. DCI_UPDATE = 0x0
+ // .. ==> 0XF8000B54[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x1
+ // .. ==> 0XF8000B54[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. DCR_TYPE = 0x3
+ // .. ==> 0XF8000B54[6:5] = 0x00000003U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000060U
+ // .. IBUF_DISABLE_MODE = 0
+ // .. ==> 0XF8000B54[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0
+ // .. ==> 0XF8000B54[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B54[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B54[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B58[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x0
+ // .. ==> 0XF8000B58[2:1] = 0x00000000U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000000U
+ // .. DCI_UPDATE = 0x0
+ // .. ==> 0XF8000B58[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x0
+ // .. ==> 0XF8000B58[4:4] = 0x00000000U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. DCR_TYPE = 0x0
+ // .. ==> 0XF8000B58[6:5] = 0x00000000U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000000U
+ // .. IBUF_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B58[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B58[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B58[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B58[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
+ // .. DRIVE_P = 0x1c
+ // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
+ // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
+ // .. DRIVE_N = 0xc
+ // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
+ // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
+ // .. SLEW_P = 0x3
+ // .. ==> 0XF8000B5C[18:14] = 0x00000003U
+ // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U
+ // .. SLEW_N = 0x3
+ // .. ==> 0XF8000B5C[23:19] = 0x00000003U
+ // .. ==> MASK : 0x00F80000U VAL : 0x00180000U
+ // .. GTL = 0x0
+ // .. ==> 0XF8000B5C[26:24] = 0x00000000U
+ // .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. RTERM = 0x0
+ // .. ==> 0XF8000B5C[31:27] = 0x00000000U
+ // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
+ // .. DRIVE_P = 0x1c
+ // .. ==> 0XF8000B60[6:0] = 0x0000001CU
+ // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
+ // .. DRIVE_N = 0xc
+ // .. ==> 0XF8000B60[13:7] = 0x0000000CU
+ // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
+ // .. SLEW_P = 0x6
+ // .. ==> 0XF8000B60[18:14] = 0x00000006U
+ // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
+ // .. SLEW_N = 0x1f
+ // .. ==> 0XF8000B60[23:19] = 0x0000001FU
+ // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
+ // .. GTL = 0x0
+ // .. ==> 0XF8000B60[26:24] = 0x00000000U
+ // .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. RTERM = 0x0
+ // .. ==> 0XF8000B60[31:27] = 0x00000000U
+ // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
+ // .. DRIVE_P = 0x1c
+ // .. ==> 0XF8000B64[6:0] = 0x0000001CU
+ // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
+ // .. DRIVE_N = 0xc
+ // .. ==> 0XF8000B64[13:7] = 0x0000000CU
+ // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
+ // .. SLEW_P = 0x6
+ // .. ==> 0XF8000B64[18:14] = 0x00000006U
+ // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
+ // .. SLEW_N = 0x1f
+ // .. ==> 0XF8000B64[23:19] = 0x0000001FU
+ // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
+ // .. GTL = 0x0
+ // .. ==> 0XF8000B64[26:24] = 0x00000000U
+ // .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. RTERM = 0x0
+ // .. ==> 0XF8000B64[31:27] = 0x00000000U
+ // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
+ // .. DRIVE_P = 0x1c
+ // .. ==> 0XF8000B68[6:0] = 0x0000001CU
+ // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
+ // .. DRIVE_N = 0xc
+ // .. ==> 0XF8000B68[13:7] = 0x0000000CU
+ // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
+ // .. SLEW_P = 0x6
+ // .. ==> 0XF8000B68[18:14] = 0x00000006U
+ // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
+ // .. SLEW_N = 0x1f
+ // .. ==> 0XF8000B68[23:19] = 0x0000001FU
+ // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
+ // .. GTL = 0x0
+ // .. ==> 0XF8000B68[26:24] = 0x00000000U
+ // .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. RTERM = 0x0
+ // .. ==> 0XF8000B68[31:27] = 0x00000000U
+ // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
+ // .. VREF_INT_EN = 0x1
+ // .. ==> 0XF8000B6C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. VREF_SEL = 0x4
+ // .. ==> 0XF8000B6C[4:1] = 0x00000004U
+ // .. ==> MASK : 0x0000001EU VAL : 0x00000008U
+ // .. VREF_EXT_EN = 0x0
+ // .. ==> 0XF8000B6C[6:5] = 0x00000000U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000000U
+ // .. VREF_PULLUP_EN = 0x0
+ // .. ==> 0XF8000B6C[8:7] = 0x00000000U
+ // .. ==> MASK : 0x00000180U VAL : 0x00000000U
+ // .. REFIO_EN = 0x1
+ // .. ==> 0XF8000B6C[9:9] = 0x00000001U
+ // .. ==> MASK : 0x00000200U VAL : 0x00000200U
+ // .. REFIO_TEST = 0x3
+ // .. ==> 0XF8000B6C[11:10] = 0x00000003U
+ // .. ==> MASK : 0x00000C00U VAL : 0x00000C00U
+ // .. REFIO_PULLUP_EN = 0x0
+ // .. ==> 0XF8000B6C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DRST_B_PULLUP_EN = 0x0
+ // .. ==> 0XF8000B6C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // .. CKE_PULLUP_EN = 0x0
+ // .. ==> 0XF8000B6C[14:14] = 0x00000000U
+ // .. ==> MASK : 0x00004000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000E09U),
+ // .. .. START: ASSERT RESET
+ // .. .. RESET = 1
+ // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. VRN_OUT = 0x1
+ // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U),
+ // .. .. FINISH: ASSERT RESET
+ // .. .. START: DEASSERT RESET
+ // .. .. RESET = 0
+ // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. VRN_OUT = 0x1
+ // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
+ // .. .. FINISH: DEASSERT RESET
+ // .. .. RESET = 0x1
+ // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ENABLE = 0x1
+ // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. .. VRP_TRI = 0x0
+ // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. VRN_TRI = 0x0
+ // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. VRP_OUT = 0x0
+ // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. VRN_OUT = 0x1
+ // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
+ // .. .. NREF_OPT1 = 0x0
+ // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
+ // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U
+ // .. .. NREF_OPT2 = 0x0
+ // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U
+ // .. .. NREF_OPT4 = 0x1
+ // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
+ // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U
+ // .. .. PREF_OPT1 = 0x0
+ // .. .. ==> 0XF8000B70[16:14] = 0x00000000U
+ // .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U
+ // .. .. PREF_OPT2 = 0x0
+ // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
+ // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U
+ // .. .. UPDATE_CONTROL = 0x0
+ // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
+ // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U
+ // .. .. INIT_COMPLETE = 0x0
+ // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
+ // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U
+ // .. .. TST_CLK = 0x0
+ // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
+ // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U
+ // .. .. TST_HLN = 0x0
+ // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
+ // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U
+ // .. .. TST_HLP = 0x0
+ // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
+ // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U
+ // .. .. TST_RST = 0x0
+ // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
+ // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
+ // .. .. INT_DCI_EN = 0x0
+ // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
+ // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U),
+ // .. FINISH: DDRIOB SETTINGS
+ // .. START: MIO PROGRAMMING
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000700[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000700[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000700[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000700[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000700[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000700[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000700[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000700[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000700[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000704[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000704[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000704[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000704[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000704[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000704[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000704[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000704[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000704[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000708[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000708[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000708[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000708[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000708[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000708[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000708[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000708[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000708[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800070C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF800070C[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800070C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800070C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800070C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800070C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800070C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800070C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800070C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000710[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000710[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000710[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000710[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000710[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000710[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000710[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000710[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000710[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000714[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000714[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000714[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000714[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000714[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000714[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000714[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000714[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000714[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000718[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000718[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000718[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000718[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000718[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000718[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000718[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000718[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000718[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800071C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800071C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800071C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800071C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800071C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800071C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800071C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800071C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800071C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000200U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000720[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000720[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000720[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000720[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000720[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000720[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000720[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000720[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000720[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000724[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000724[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000724[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000724[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000724[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000724[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000724[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000724[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000724[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000728[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000728[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000728[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000728[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000728[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000728[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000728[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000728[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000728[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800072C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF800072C[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800072C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800072C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800072C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800072C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800072C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF800072C[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800072C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000730[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000730[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000730[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000730[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000730[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000730[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000730[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000730[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000730[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000734[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000734[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000734[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000734[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000734[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000734[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000734[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000734[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000734[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001202U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000738[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. Speed = 0
+ // .. ==> 0XF8000738[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000738[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000738[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000738[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000738, 0x00003F01U ,0x00001201U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF800073C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. Speed = 0
+ // .. ==> 0XF800073C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800073C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF800073C[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800073C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800073C, 0x00003F01U ,0x00001201U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000740[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000740[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000740[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000740[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000740[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000740[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 4
+ // .. ==> 0XF8000740[11:9] = 0x00000004U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000740[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 1
+ // .. ==> 0XF8000740[13:13] = 0x00000001U
+ // .. ==> MASK : 0x00002000U VAL : 0x00002000U
+ // ..
+ EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00002802U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000744[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000744[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000744[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000744[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000744[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000744[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 4
+ // .. ==> 0XF8000744[11:9] = 0x00000004U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000744[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 1
+ // .. ==> 0XF8000744[13:13] = 0x00000001U
+ // .. ==> MASK : 0x00002000U VAL : 0x00002000U
+ // ..
+ EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00002802U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000748[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000748[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000748[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000748[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000748[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000748[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 4
+ // .. ==> 0XF8000748[11:9] = 0x00000004U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000748[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 1
+ // .. ==> 0XF8000748[13:13] = 0x00000001U
+ // .. ==> MASK : 0x00002000U VAL : 0x00002000U
+ // ..
+ EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00002802U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800074C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF800074C[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800074C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800074C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800074C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800074C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 4
+ // .. ==> 0XF800074C[11:9] = 0x00000004U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
+ // .. PULLUP = 0
+ // .. ==> 0XF800074C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 1
+ // .. ==> 0XF800074C[13:13] = 0x00000001U
+ // .. ==> MASK : 0x00002000U VAL : 0x00002000U
+ // ..
+ EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00002802U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000750[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000750[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000750[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000750[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000750[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000750[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 4
+ // .. ==> 0XF8000750[11:9] = 0x00000004U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000750[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 1
+ // .. ==> 0XF8000750[13:13] = 0x00000001U
+ // .. ==> MASK : 0x00002000U VAL : 0x00002000U
+ // ..
+ EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00002802U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000754[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000754[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000754[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000754[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000754[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000754[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 4
+ // .. ==> 0XF8000754[11:9] = 0x00000004U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000754[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 1
+ // .. ==> 0XF8000754[13:13] = 0x00000001U
+ // .. ==> MASK : 0x00002000U VAL : 0x00002000U
+ // ..
+ EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00002802U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000758[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000758[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000758[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000758[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000758[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000758[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 4
+ // .. ==> 0XF8000758[11:9] = 0x00000004U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000758[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000758[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000803U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF800075C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF800075C[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800075C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800075C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800075C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800075C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 4
+ // .. ==> 0XF800075C[11:9] = 0x00000004U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
+ // .. PULLUP = 0
+ // .. ==> 0XF800075C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800075C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000803U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000760[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000760[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000760[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000760[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000760[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000760[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 4
+ // .. ==> 0XF8000760[11:9] = 0x00000004U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000760[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000760[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000803U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000764[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000764[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000764[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000764[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000764[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000764[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 4
+ // .. ==> 0XF8000764[11:9] = 0x00000004U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000764[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000764[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000803U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000768[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000768[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000768[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000768[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000768[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000768[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 4
+ // .. ==> 0XF8000768[11:9] = 0x00000004U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000768[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000768[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000803U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF800076C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF800076C[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800076C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800076C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800076C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800076C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 4
+ // .. ==> 0XF800076C[11:9] = 0x00000004U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
+ // .. PULLUP = 0
+ // .. ==> 0XF800076C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800076C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000803U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000770[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000770[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000770[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000770[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000770[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000770[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000770[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000770[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000770[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000774[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000774[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000774[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000774[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000774[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000774[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000774[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000774[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000774[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000778[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000778[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000778[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000778[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000778[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000778[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000778[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000778[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000778[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF800077C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800077C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF800077C[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800077C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800077C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800077C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800077C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800077C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800077C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000780[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000780[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000780[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000780[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000780[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000780[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000780[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000780[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000780[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000784[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000784[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000784[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000784[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000784[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000784[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000784[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000784[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000784[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000788[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000788[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000788[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000788[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000788[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000788[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000788[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000788[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000788[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800078C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800078C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF800078C[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800078C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800078C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800078C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800078C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800078C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800078C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000790[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000790[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000790[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000790[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000790[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000790[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000790[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000790[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000790[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000794[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000794[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000794[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000794[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000794[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000794[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000794[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000794[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000794[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000798[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000798[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000798[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000798[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000798[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000798[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000798[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000798[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000798[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800079C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800079C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF800079C[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800079C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800079C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800079C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800079C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800079C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800079C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007A0[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007A0[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007A0[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007A0[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007A0[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007A0[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007A0[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007A0[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007A0[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007A4[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007A4[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007A4[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007A4[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007A4[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007A4[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007A4[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007A4[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007A4[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007A8[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007A8[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007A8[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007A8[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007A8[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007A8[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007A8[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007A8[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007A8[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007AC[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007AC[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007AC[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007AC[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007AC[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007AC[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007AC[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007AC[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007AC[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007B0[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007B0[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007B0[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007B0[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007B0[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007B0[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007B0[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007B0[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007B0[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007B4[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007B4[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007B4[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007B4[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007B4[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007B4[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007B4[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007B4[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007B4[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007B8[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007B8[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007B8[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007B8[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF80007B8[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF80007B8[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007B8[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF80007B8[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007B8[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001200U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007BC[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007BC[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007BC[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007BC[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF80007BC[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF80007BC[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007BC[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF80007BC[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007BC[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00001200U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007C0[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007C0[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007C0[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007C0[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 7
+ // .. ==> 0XF80007C0[7:5] = 0x00000007U
+ // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U
+ // .. Speed = 0
+ // .. ==> 0XF80007C0[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007C0[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007C0[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007C0[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF80007C4[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007C4[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007C4[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007C4[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 7
+ // .. ==> 0XF80007C4[7:5] = 0x00000007U
+ // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U
+ // .. Speed = 0
+ // .. ==> 0XF80007C4[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007C4[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007C4[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007C4[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007C8[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007C8[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007C8[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007C8[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 2
+ // .. ==> 0XF80007C8[7:5] = 0x00000002U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000040U
+ // .. Speed = 0
+ // .. ==> 0XF80007C8[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007C8[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF80007C8[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007C8[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001240U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007CC[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007CC[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007CC[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007CC[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 2
+ // .. ==> 0XF80007CC[7:5] = 0x00000002U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000040U
+ // .. Speed = 0
+ // .. ==> 0XF80007CC[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007CC[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF80007CC[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007CC[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001240U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007D0[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007D0[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007D0[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007D0[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007D0[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007D0[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007D0[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007D0[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007D0[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007D4[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007D4[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007D4[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007D4[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007D4[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007D4[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007D4[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007D4[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007D4[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U),
+ // .. SDIO0_WP_SEL = 15
+ // .. ==> 0XF8000830[5:0] = 0x0000000FU
+ // .. ==> MASK : 0x0000003FU VAL : 0x0000000FU
+ // .. SDIO0_CD_SEL = 14
+ // .. ==> 0XF8000830[21:16] = 0x0000000EU
+ // .. ==> MASK : 0x003F0000U VAL : 0x000E0000U
+ // ..
+ EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x000E000FU),
+ // .. FINISH: MIO PROGRAMMING
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_peripherals_init_data_2_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+ // .. IBUF_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B48[7:7] = 0x00000001U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. TERM_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B48[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // ..
+ EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
+ // .. IBUF_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B4C[7:7] = 0x00000001U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. TERM_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B4C[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // ..
+ EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
+ // .. IBUF_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B50[7:7] = 0x00000001U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. TERM_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B50[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // ..
+ EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
+ // .. IBUF_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B54[7:7] = 0x00000001U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. TERM_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B54[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // ..
+ EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
+ // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // .. START: SRAM/NOR SET OPMODE
+ // .. FINISH: SRAM/NOR SET OPMODE
+ // .. START: UART REGISTERS
+ // .. BDIV = 0x6
+ // .. ==> 0XE0001034[7:0] = 0x00000006U
+ // .. ==> MASK : 0x000000FFU VAL : 0x00000006U
+ // ..
+ EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
+ // .. CD = 0x3e
+ // .. ==> 0XE0001018[15:0] = 0x0000003EU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU
+ // ..
+ EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
+ // .. STPBRK = 0x0
+ // .. ==> 0XE0001000[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. STTBRK = 0x0
+ // .. ==> 0XE0001000[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. RSTTO = 0x0
+ // .. ==> 0XE0001000[6:6] = 0x00000000U
+ // .. ==> MASK : 0x00000040U VAL : 0x00000000U
+ // .. TXDIS = 0x0
+ // .. ==> 0XE0001000[5:5] = 0x00000000U
+ // .. ==> MASK : 0x00000020U VAL : 0x00000000U
+ // .. TXEN = 0x1
+ // .. ==> 0XE0001000[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. RXDIS = 0x0
+ // .. ==> 0XE0001000[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. RXEN = 0x1
+ // .. ==> 0XE0001000[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. TXRES = 0x1
+ // .. ==> 0XE0001000[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. RXRES = 0x1
+ // .. ==> 0XE0001000[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // ..
+ EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
+ // .. IRMODE = 0x0
+ // .. ==> 0XE0001004[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. UCLKEN = 0x0
+ // .. ==> 0XE0001004[10:10] = 0x00000000U
+ // .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. CHMODE = 0x0
+ // .. ==> 0XE0001004[9:8] = 0x00000000U
+ // .. ==> MASK : 0x00000300U VAL : 0x00000000U
+ // .. NBSTOP = 0x0
+ // .. ==> 0XE0001004[7:6] = 0x00000000U
+ // .. ==> MASK : 0x000000C0U VAL : 0x00000000U
+ // .. PAR = 0x4
+ // .. ==> 0XE0001004[5:3] = 0x00000004U
+ // .. ==> MASK : 0x00000038U VAL : 0x00000020U
+ // .. CHRL = 0x0
+ // .. ==> 0XE0001004[2:1] = 0x00000000U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000000U
+ // .. CLKS = 0x0
+ // .. ==> 0XE0001004[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U),
+ // .. FINISH: UART REGISTERS
+ // .. START: QSPI REGISTERS
+ // .. Holdb_dr = 1
+ // .. ==> 0XE000D000[19:19] = 0x00000001U
+ // .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // ..
+ EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
+ // .. FINISH: QSPI REGISTERS
+ // .. START: PL POWER ON RESET REGISTERS
+ // .. PCFG_POR_CNT_4K = 0
+ // .. ==> 0XF8007000[29:29] = 0x00000000U
+ // .. ==> MASK : 0x20000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
+ // .. FINISH: PL POWER ON RESET REGISTERS
+ // .. START: SMC TIMING CALCULATION REGISTER UPDATE
+ // .. .. START: NAND SET CYCLE
+ // .. .. FINISH: NAND SET CYCLE
+ // .. .. START: OPMODE
+ // .. .. FINISH: OPMODE
+ // .. .. START: DIRECT COMMAND
+ // .. .. FINISH: DIRECT COMMAND
+ // .. .. START: SRAM/NOR CS0 SET CYCLE
+ // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
+ // .. .. START: DIRECT COMMAND
+ // .. .. FINISH: DIRECT COMMAND
+ // .. .. START: NOR CS0 BASE ADDRESS
+ // .. .. FINISH: NOR CS0 BASE ADDRESS
+ // .. .. START: SRAM/NOR CS1 SET CYCLE
+ // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
+ // .. .. START: DIRECT COMMAND
+ // .. .. FINISH: DIRECT COMMAND
+ // .. .. START: NOR CS1 BASE ADDRESS
+ // .. .. FINISH: NOR CS1 BASE ADDRESS
+ // .. .. START: USB RESET
+ // .. .. .. START: USB0 RESET
+ // .. .. .. .. START: DIR MODE BANK 0
+ // .. .. .. .. DIRECTION_0 = 0x80
+ // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U
+ // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U),
+ // .. .. .. .. FINISH: DIR MODE BANK 0
+ // .. .. .. .. START: DIR MODE BANK 1
+ // .. .. .. .. FINISH: DIR MODE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. MASK_0_LSW = 0xff7f
+ // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+ // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U
+ // .. .. .. .. DATA_0_LSW = 0x80
+ // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+ // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. START: OUTPUT ENABLE BANK 0
+ // .. .. .. .. OP_ENABLE_0 = 0x80
+ // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U
+ // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U),
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+ // .. .. .. .. START: OUTPUT ENABLE BANK 1
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. MASK_0_LSW = 0xff7f
+ // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+ // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U
+ // .. .. .. .. DATA_0_LSW = 0x0
+ // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+ // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U),
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. START: ADD 1 MS DELAY
+ // .. .. .. ..
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ // .. .. .. .. FINISH: ADD 1 MS DELAY
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. MASK_0_LSW = 0xff7f
+ // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+ // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U
+ // .. .. .. .. DATA_0_LSW = 0x80
+ // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+ // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. FINISH: USB0 RESET
+ // .. .. .. START: USB1 RESET
+ // .. .. .. .. START: DIR MODE BANK 0
+ // .. .. .. .. FINISH: DIR MODE BANK 0
+ // .. .. .. .. START: DIR MODE BANK 1
+ // .. .. .. .. FINISH: DIR MODE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. START: OUTPUT ENABLE BANK 0
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+ // .. .. .. .. START: OUTPUT ENABLE BANK 1
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. START: ADD 1 MS DELAY
+ // .. .. .. ..
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ // .. .. .. .. FINISH: ADD 1 MS DELAY
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. FINISH: USB1 RESET
+ // .. .. FINISH: USB RESET
+ // .. .. START: ENET RESET
+ // .. .. .. START: ENET0 RESET
+ // .. .. .. .. START: DIR MODE BANK 0
+ // .. .. .. .. FINISH: DIR MODE BANK 0
+ // .. .. .. .. START: DIR MODE BANK 1
+ // .. .. .. .. DIRECTION_1 = 0x8000
+ // .. .. .. .. ==> 0XE000A244[21:0] = 0x00008000U
+ // .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00008000U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x00008000U),
+ // .. .. .. .. FINISH: DIR MODE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. MASK_1_LSW = 0x7fff
+ // .. .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU
+ // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0x7FFF0000U
+ // .. .. .. .. DATA_1_LSW = 0x8000
+ // .. .. .. .. ==> 0XE000A008[15:0] = 0x00008000U
+ // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00008000U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF8000U),
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. START: OUTPUT ENABLE BANK 0
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+ // .. .. .. .. START: OUTPUT ENABLE BANK 1
+ // .. .. .. .. OP_ENABLE_1 = 0x8000
+ // .. .. .. .. ==> 0XE000A248[21:0] = 0x00008000U
+ // .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00008000U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x00008000U),
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. MASK_1_LSW = 0x7fff
+ // .. .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU
+ // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0x7FFF0000U
+ // .. .. .. .. DATA_1_LSW = 0x0
+ // .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U
+ // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF0000U),
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. START: ADD 1 MS DELAY
+ // .. .. .. ..
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ // .. .. .. .. FINISH: ADD 1 MS DELAY
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. MASK_1_LSW = 0x7fff
+ // .. .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU
+ // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0x7FFF0000U
+ // .. .. .. .. DATA_1_LSW = 0x8000
+ // .. .. .. .. ==> 0XE000A008[15:0] = 0x00008000U
+ // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00008000U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF8000U),
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. FINISH: ENET0 RESET
+ // .. .. .. START: ENET1 RESET
+ // .. .. .. .. START: DIR MODE BANK 0
+ // .. .. .. .. FINISH: DIR MODE BANK 0
+ // .. .. .. .. START: DIR MODE BANK 1
+ // .. .. .. .. FINISH: DIR MODE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. START: OUTPUT ENABLE BANK 0
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+ // .. .. .. .. START: OUTPUT ENABLE BANK 1
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. START: ADD 1 MS DELAY
+ // .. .. .. ..
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ // .. .. .. .. FINISH: ADD 1 MS DELAY
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. FINISH: ENET1 RESET
+ // .. .. FINISH: ENET RESET
+ // .. .. START: I2C RESET
+ // .. .. .. START: I2C0 RESET
+ // .. .. .. .. START: DIR MODE GPIO BANK0
+ // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+ // .. .. .. .. START: DIR MODE GPIO BANK1
+ // .. .. .. .. DIRECTION_1 = 0x4000
+ // .. .. .. .. ==> 0XE000A244[21:0] = 0x00004000U
+ // .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x00004000U),
+ // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. MASK_1_LSW = 0xbfff
+ // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
+ // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U
+ // .. .. .. .. DATA_1_LSW = 0x4000
+ // .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U
+ // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U),
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. START: OUTPUT ENABLE
+ // .. .. .. .. FINISH: OUTPUT ENABLE
+ // .. .. .. .. START: OUTPUT ENABLE
+ // .. .. .. .. OP_ENABLE_1 = 0x4000
+ // .. .. .. .. ==> 0XE000A248[21:0] = 0x00004000U
+ // .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x00004000U),
+ // .. .. .. .. FINISH: OUTPUT ENABLE
+ // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. MASK_1_LSW = 0xbfff
+ // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
+ // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U
+ // .. .. .. .. DATA_1_LSW = 0x0
+ // .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U
+ // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF0000U),
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. START: ADD 1 MS DELAY
+ // .. .. .. ..
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ // .. .. .. .. FINISH: ADD 1 MS DELAY
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. MASK_1_LSW = 0xbfff
+ // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
+ // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U
+ // .. .. .. .. DATA_1_LSW = 0x4000
+ // .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U
+ // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U),
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. FINISH: I2C0 RESET
+ // .. .. .. START: I2C1 RESET
+ // .. .. .. .. START: DIR MODE GPIO BANK0
+ // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+ // .. .. .. .. START: DIR MODE GPIO BANK1
+ // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. START: OUTPUT ENABLE
+ // .. .. .. .. FINISH: OUTPUT ENABLE
+ // .. .. .. .. START: OUTPUT ENABLE
+ // .. .. .. .. FINISH: OUTPUT ENABLE
+ // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. START: ADD 1 MS DELAY
+ // .. .. .. ..
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ // .. .. .. .. FINISH: ADD 1 MS DELAY
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. FINISH: I2C1 RESET
+ // .. .. FINISH: I2C RESET
+ // .. .. START: NOR CHIP SELECT
+ // .. .. .. START: DIR MODE BANK 0
+ // .. .. .. FINISH: DIR MODE BANK 0
+ // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. START: OUTPUT ENABLE BANK 0
+ // .. .. .. FINISH: OUTPUT ENABLE BANK 0
+ // .. .. FINISH: NOR CHIP SELECT
+ // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_post_config_2_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: ENABLING LEVEL SHIFTER
+ // .. USER_INP_ICT_EN_0 = 3
+ // .. ==> 0XF8000900[1:0] = 0x00000003U
+ // .. ==> MASK : 0x00000003U VAL : 0x00000003U
+ // .. USER_INP_ICT_EN_1 = 3
+ // .. ==> 0XF8000900[3:2] = 0x00000003U
+ // .. ==> MASK : 0x0000000CU VAL : 0x0000000CU
+ // ..
+ EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
+ // .. FINISH: ENABLING LEVEL SHIFTER
+ // .. START: FPGA RESETS TO 0
+ // .. reserved_3 = 0
+ // .. ==> 0XF8000240[31:25] = 0x00000000U
+ // .. ==> MASK : 0xFE000000U VAL : 0x00000000U
+ // .. FPGA_ACP_RST = 0
+ // .. ==> 0XF8000240[24:24] = 0x00000000U
+ // .. ==> MASK : 0x01000000U VAL : 0x00000000U
+ // .. FPGA_AXDS3_RST = 0
+ // .. ==> 0XF8000240[23:23] = 0x00000000U
+ // .. ==> MASK : 0x00800000U VAL : 0x00000000U
+ // .. FPGA_AXDS2_RST = 0
+ // .. ==> 0XF8000240[22:22] = 0x00000000U
+ // .. ==> MASK : 0x00400000U VAL : 0x00000000U
+ // .. FPGA_AXDS1_RST = 0
+ // .. ==> 0XF8000240[21:21] = 0x00000000U
+ // .. ==> MASK : 0x00200000U VAL : 0x00000000U
+ // .. FPGA_AXDS0_RST = 0
+ // .. ==> 0XF8000240[20:20] = 0x00000000U
+ // .. ==> MASK : 0x00100000U VAL : 0x00000000U
+ // .. reserved_2 = 0
+ // .. ==> 0XF8000240[19:18] = 0x00000000U
+ // .. ==> MASK : 0x000C0000U VAL : 0x00000000U
+ // .. FSSW1_FPGA_RST = 0
+ // .. ==> 0XF8000240[17:17] = 0x00000000U
+ // .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. FSSW0_FPGA_RST = 0
+ // .. ==> 0XF8000240[16:16] = 0x00000000U
+ // .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. reserved_1 = 0
+ // .. ==> 0XF8000240[15:14] = 0x00000000U
+ // .. ==> MASK : 0x0000C000U VAL : 0x00000000U
+ // .. FPGA_FMSW1_RST = 0
+ // .. ==> 0XF8000240[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // .. FPGA_FMSW0_RST = 0
+ // .. ==> 0XF8000240[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. FPGA_DMA3_RST = 0
+ // .. ==> 0XF8000240[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. FPGA_DMA2_RST = 0
+ // .. ==> 0XF8000240[10:10] = 0x00000000U
+ // .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. FPGA_DMA1_RST = 0
+ // .. ==> 0XF8000240[9:9] = 0x00000000U
+ // .. ==> MASK : 0x00000200U VAL : 0x00000000U
+ // .. FPGA_DMA0_RST = 0
+ // .. ==> 0XF8000240[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. reserved = 0
+ // .. ==> 0XF8000240[7:4] = 0x00000000U
+ // .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. FPGA3_OUT_RST = 0
+ // .. ==> 0XF8000240[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. FPGA2_OUT_RST = 0
+ // .. ==> 0XF8000240[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. FPGA1_OUT_RST = 0
+ // .. ==> 0XF8000240[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. FPGA0_OUT_RST = 0
+ // .. ==> 0XF8000240[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
+ // .. FINISH: FPGA RESETS TO 0
+ // .. START: AFI REGISTERS
+ // .. .. START: AFI0 REGISTERS
+ // .. .. FINISH: AFI0 REGISTERS
+ // .. .. START: AFI1 REGISTERS
+ // .. .. FINISH: AFI1 REGISTERS
+ // .. .. START: AFI2 REGISTERS
+ // .. .. FINISH: AFI2 REGISTERS
+ // .. .. START: AFI3 REGISTERS
+ // .. .. FINISH: AFI3 REGISTERS
+ // .. FINISH: AFI REGISTERS
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_debug_2_0[] = {
+ // START: top
+ // .. START: CROSS TRIGGER CONFIGURATIONS
+ // .. .. START: UNLOCKING CTI REGISTERS
+ // .. .. KEY = 0XC5ACCE55
+ // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
+ // .. ..
+ EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
+ // .. .. KEY = 0XC5ACCE55
+ // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
+ // .. ..
+ EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
+ // .. .. KEY = 0XC5ACCE55
+ // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
+ // .. ..
+ EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
+ // .. .. FINISH: UNLOCKING CTI REGISTERS
+ // .. .. START: ENABLING CTI MODULES AND CHANNELS
+ // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
+ // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+ // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+ // .. FINISH: CROSS TRIGGER CONFIGURATIONS
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_pll_init_data_1_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: PLL SLCR REGISTERS
+ // .. .. START: ARM PLL INIT
+ // .. .. PLL_RES = 0x2
+ // .. .. ==> 0XF8000110[7:4] = 0x00000002U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
+ // .. .. PLL_CP = 0x2
+ // .. .. ==> 0XF8000110[11:8] = 0x00000002U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
+ // .. .. LOCK_CNT = 0xfa
+ // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
+ // .. .. .. START: UPDATE FB_DIV
+ // .. .. .. PLL_FDIV = 0x28
+ // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
+ // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
+ // .. .. .. FINISH: UPDATE FB_DIV
+ // .. .. .. START: BY PASS PLL
+ // .. .. .. PLL_BYPASS_FORCE = 1
+ // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
+ // .. .. .. FINISH: BY PASS PLL
+ // .. .. .. START: ASSERT RESET
+ // .. .. .. PLL_RESET = 1
+ // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
+ // .. .. .. FINISH: ASSERT RESET
+ // .. .. .. START: DEASSERT RESET
+ // .. .. .. PLL_RESET = 0
+ // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
+ // .. .. .. FINISH: DEASSERT RESET
+ // .. .. .. START: CHECK PLL STATUS
+ // .. .. .. ARM_PLL_LOCK = 1
+ // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ..
+ EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+ // .. .. .. FINISH: CHECK PLL STATUS
+ // .. .. .. START: REMOVE PLL BY PASS
+ // .. .. .. PLL_BYPASS_FORCE = 0
+ // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
+ // .. .. .. FINISH: REMOVE PLL BY PASS
+ // .. .. .. SRCSEL = 0x0
+ // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. .. .. DIVISOR = 0x2
+ // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
+ // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U
+ // .. .. .. CPU_6OR4XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
+ // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U
+ // .. .. .. CPU_3OR2XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
+ // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U
+ // .. .. .. CPU_2XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
+ // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U
+ // .. .. .. CPU_1XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
+ // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U
+ // .. .. .. CPU_PERI_CLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
+ // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
+ // .. .. FINISH: ARM PLL INIT
+ // .. .. START: DDR PLL INIT
+ // .. .. PLL_RES = 0x2
+ // .. .. ==> 0XF8000114[7:4] = 0x00000002U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
+ // .. .. PLL_CP = 0x2
+ // .. .. ==> 0XF8000114[11:8] = 0x00000002U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
+ // .. .. LOCK_CNT = 0x12c
+ // .. .. ==> 0XF8000114[21:12] = 0x0000012CU
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
+ // .. .. .. START: UPDATE FB_DIV
+ // .. .. .. PLL_FDIV = 0x20
+ // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
+ // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
+ // .. .. .. FINISH: UPDATE FB_DIV
+ // .. .. .. START: BY PASS PLL
+ // .. .. .. PLL_BYPASS_FORCE = 1
+ // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
+ // .. .. .. FINISH: BY PASS PLL
+ // .. .. .. START: ASSERT RESET
+ // .. .. .. PLL_RESET = 1
+ // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
+ // .. .. .. FINISH: ASSERT RESET
+ // .. .. .. START: DEASSERT RESET
+ // .. .. .. PLL_RESET = 0
+ // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
+ // .. .. .. FINISH: DEASSERT RESET
+ // .. .. .. START: CHECK PLL STATUS
+ // .. .. .. DDR_PLL_LOCK = 1
+ // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. .. ..
+ EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+ // .. .. .. FINISH: CHECK PLL STATUS
+ // .. .. .. START: REMOVE PLL BY PASS
+ // .. .. .. PLL_BYPASS_FORCE = 0
+ // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
+ // .. .. .. FINISH: REMOVE PLL BY PASS
+ // .. .. .. DDR_3XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. .. DDR_2XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. .. .. DDR_3XCLK_DIVISOR = 0x2
+ // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
+ // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U
+ // .. .. .. DDR_2XCLK_DIVISOR = 0x3
+ // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
+ // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
+ // .. .. FINISH: DDR PLL INIT
+ // .. .. START: IO PLL INIT
+ // .. .. PLL_RES = 0xc
+ // .. .. ==> 0XF8000118[7:4] = 0x0000000CU
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U
+ // .. .. PLL_CP = 0x2
+ // .. .. ==> 0XF8000118[11:8] = 0x00000002U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
+ // .. .. LOCK_CNT = 0x145
+ // .. .. ==> 0XF8000118[21:12] = 0x00000145U
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U),
+ // .. .. .. START: UPDATE FB_DIV
+ // .. .. .. PLL_FDIV = 0x1e
+ // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU
+ // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U),
+ // .. .. .. FINISH: UPDATE FB_DIV
+ // .. .. .. START: BY PASS PLL
+ // .. .. .. PLL_BYPASS_FORCE = 1
+ // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
+ // .. .. .. FINISH: BY PASS PLL
+ // .. .. .. START: ASSERT RESET
+ // .. .. .. PLL_RESET = 1
+ // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
+ // .. .. .. FINISH: ASSERT RESET
+ // .. .. .. START: DEASSERT RESET
+ // .. .. .. PLL_RESET = 0
+ // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
+ // .. .. .. FINISH: DEASSERT RESET
+ // .. .. .. START: CHECK PLL STATUS
+ // .. .. .. IO_PLL_LOCK = 1
+ // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. .. ..
+ EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+ // .. .. .. FINISH: CHECK PLL STATUS
+ // .. .. .. START: REMOVE PLL BY PASS
+ // .. .. .. PLL_BYPASS_FORCE = 0
+ // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
+ // .. .. .. FINISH: REMOVE PLL BY PASS
+ // .. .. FINISH: IO PLL INIT
+ // .. FINISH: PLL SLCR REGISTERS
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_clock_init_data_1_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: CLOCK CONTROL SLCR REGISTERS
+ // .. CLKACT = 0x1
+ // .. ==> 0XF8000128[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. DIVISOR0 = 0x23
+ // .. ==> 0XF8000128[13:8] = 0x00000023U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00002300U
+ // .. DIVISOR1 = 0x3
+ // .. ==> 0XF8000128[25:20] = 0x00000003U
+ // .. ==> MASK : 0x03F00000U VAL : 0x00300000U
+ // ..
+ EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U),
+ // .. CLKACT = 0x1
+ // .. ==> 0XF8000138[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000138[4:4] = 0x00000000U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
+ // .. CLKACT = 0x1
+ // .. ==> 0XF8000140[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000140[6:4] = 0x00000000U
+ // .. ==> MASK : 0x00000070U VAL : 0x00000000U
+ // .. DIVISOR = 0x8
+ // .. ==> 0XF8000140[13:8] = 0x00000008U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00000800U
+ // .. DIVISOR1 = 0x5
+ // .. ==> 0XF8000140[25:20] = 0x00000005U
+ // .. ==> MASK : 0x03F00000U VAL : 0x00500000U
+ // ..
+ EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00500801U),
+ // .. CLKACT = 0x1
+ // .. ==> 0XF800014C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF800014C[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR = 0x5
+ // .. ==> 0XF800014C[13:8] = 0x00000005U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00000500U
+ // ..
+ EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
+ // .. CLKACT0 = 0x1
+ // .. ==> 0XF8000150[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. CLKACT1 = 0x0
+ // .. ==> 0XF8000150[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000150[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR = 0x14
+ // .. ==> 0XF8000150[13:8] = 0x00000014U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
+ // ..
+ EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U),
+ // .. CLKACT0 = 0x0
+ // .. ==> 0XF8000154[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. CLKACT1 = 0x1
+ // .. ==> 0XF8000154[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000154[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR = 0x14
+ // .. ==> 0XF8000154[13:8] = 0x00000014U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
+ // ..
+ EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U),
+ // .. CLKACT = 0x1
+ // .. ==> 0XF8000168[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000168[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR = 0x5
+ // .. ==> 0XF8000168[13:8] = 0x00000005U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00000500U
+ // ..
+ EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000170[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR0 = 0x14
+ // .. ==> 0XF8000170[13:8] = 0x00000014U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
+ // .. DIVISOR1 = 0x1
+ // .. ==> 0XF8000170[25:20] = 0x00000001U
+ // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
+ // ..
+ EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00101400U),
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000180[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR0 = 0x14
+ // .. ==> 0XF8000180[13:8] = 0x00000014U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
+ // .. DIVISOR1 = 0x1
+ // .. ==> 0XF8000180[25:20] = 0x00000001U
+ // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
+ // ..
+ EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00101400U),
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000190[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR0 = 0x14
+ // .. ==> 0XF8000190[13:8] = 0x00000014U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
+ // .. DIVISOR1 = 0x1
+ // .. ==> 0XF8000190[25:20] = 0x00000001U
+ // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
+ // ..
+ EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101400U),
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF80001A0[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR0 = 0x14
+ // .. ==> 0XF80001A0[13:8] = 0x00000014U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
+ // .. DIVISOR1 = 0x1
+ // .. ==> 0XF80001A0[25:20] = 0x00000001U
+ // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
+ // ..
+ EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U),
+ // .. CLK_621_TRUE = 0x1
+ // .. ==> 0XF80001C4[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // ..
+ EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
+ // .. DMA_CPU_2XCLKACT = 0x1
+ // .. ==> 0XF800012C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. USB0_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. USB1_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[3:3] = 0x00000001U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000008U
+ // .. GEM0_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[6:6] = 0x00000001U
+ // .. ==> MASK : 0x00000040U VAL : 0x00000040U
+ // .. GEM1_CPU_1XCLKACT = 0x0
+ // .. ==> 0XF800012C[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. SDI0_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[10:10] = 0x00000001U
+ // .. ==> MASK : 0x00000400U VAL : 0x00000400U
+ // .. SDI1_CPU_1XCLKACT = 0x0
+ // .. ==> 0XF800012C[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. SPI0_CPU_1XCLKACT = 0x0
+ // .. ==> 0XF800012C[14:14] = 0x00000000U
+ // .. ==> MASK : 0x00004000U VAL : 0x00000000U
+ // .. SPI1_CPU_1XCLKACT = 0x0
+ // .. ==> 0XF800012C[15:15] = 0x00000000U
+ // .. ==> MASK : 0x00008000U VAL : 0x00000000U
+ // .. CAN0_CPU_1XCLKACT = 0x0
+ // .. ==> 0XF800012C[16:16] = 0x00000000U
+ // .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. CAN1_CPU_1XCLKACT = 0x0
+ // .. ==> 0XF800012C[17:17] = 0x00000000U
+ // .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. I2C0_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[18:18] = 0x00000001U
+ // .. ==> MASK : 0x00040000U VAL : 0x00040000U
+ // .. I2C1_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[19:19] = 0x00000001U
+ // .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // .. UART0_CPU_1XCLKACT = 0x0
+ // .. ==> 0XF800012C[20:20] = 0x00000000U
+ // .. ==> MASK : 0x00100000U VAL : 0x00000000U
+ // .. UART1_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[21:21] = 0x00000001U
+ // .. ==> MASK : 0x00200000U VAL : 0x00200000U
+ // .. GPIO_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[22:22] = 0x00000001U
+ // .. ==> MASK : 0x00400000U VAL : 0x00400000U
+ // .. LQSPI_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[23:23] = 0x00000001U
+ // .. ==> MASK : 0x00800000U VAL : 0x00800000U
+ // .. SMC_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[24:24] = 0x00000001U
+ // .. ==> MASK : 0x01000000U VAL : 0x01000000U
+ // ..
+ EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC044DU),
+ // .. FINISH: CLOCK CONTROL SLCR REGISTERS
+ // .. START: THIS SHOULD BE BLANK
+ // .. FINISH: THIS SHOULD BE BLANK
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_ddr_init_data_1_0[] = {
+ // START: top
+ // .. START: DDR INITIALIZATION
+ // .. .. START: LOCK DDR
+ // .. .. reg_ddrc_soft_rstb = 0
+ // .. .. ==> 0XF8006000[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_powerdown_en = 0x0
+ // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_ddrc_data_bus_width = 0x0
+ // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U
+ // .. .. reg_ddrc_burst8_refresh = 0x0
+ // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U
+ // .. .. reg_ddrc_rdwr_idle_gap = 0x1
+ // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+ // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U
+ // .. .. reg_ddrc_dis_rd_bypass = 0x0
+ // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+ // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_act_bypass = 0x0
+ // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_auto_refresh = 0x0
+ // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
+ // .. .. FINISH: LOCK DDR
+ // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81
+ // .. .. ==> 0XF8006004[11:0] = 0x00000081U
+ // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U
+ // .. .. reg_ddrc_active_ranks = 0x1
+ // .. .. ==> 0XF8006004[13:12] = 0x00000001U
+ // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U
+ // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
+ // .. .. ==> 0XF8006004[18:14] = 0x00000000U
+ // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U
+ // .. .. reg_ddrc_wr_odt_block = 0x1
+ // .. .. ==> 0XF8006004[20:19] = 0x00000001U
+ // .. .. ==> MASK : 0x00180000U VAL : 0x00080000U
+ // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0
+ // .. .. ==> 0XF8006004[21:21] = 0x00000000U
+ // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0
+ // .. .. ==> 0XF8006004[26:22] = 0x00000000U
+ // .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_open_bank = 0x0
+ // .. .. ==> 0XF8006004[27:27] = 0x00000000U
+ // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_4bank_ram = 0x0
+ // .. .. ==> 0XF8006004[28:28] = 0x00000000U
+ // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U),
+ // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
+ // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU
+ // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
+ // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
+ // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U
+ // .. .. reg_ddrc_hpr_xact_run_length = 0xf
+ // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
+ // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
+ // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
+ // .. .. ==> 0XF800600C[10:0] = 0x00000001U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U
+ // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
+ // .. .. ==> 0XF800600C[21:11] = 0x00000002U
+ // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U
+ // .. .. reg_ddrc_lpr_xact_run_length = 0x8
+ // .. .. ==> 0XF800600C[25:22] = 0x00000008U
+ // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
+ // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
+ // .. .. ==> 0XF8006010[10:0] = 0x00000001U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U
+ // .. .. reg_ddrc_w_xact_run_length = 0x8
+ // .. .. ==> 0XF8006010[14:11] = 0x00000008U
+ // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U
+ // .. .. reg_ddrc_w_max_starve_x32 = 0x2
+ // .. .. ==> 0XF8006010[25:15] = 0x00000002U
+ // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
+ // .. .. reg_ddrc_t_rc = 0x1b
+ // .. .. ==> 0XF8006014[5:0] = 0x0000001BU
+ // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001BU
+ // .. .. reg_ddrc_t_rfc_min = 0x56
+ // .. .. ==> 0XF8006014[13:6] = 0x00000056U
+ // .. .. ==> MASK : 0x00003FC0U VAL : 0x00001580U
+ // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
+ // .. .. ==> 0XF8006014[20:14] = 0x00000010U
+ // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004159BU),
+ // .. .. reg_ddrc_wr2pre = 0x12
+ // .. .. ==> 0XF8006018[4:0] = 0x00000012U
+ // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U
+ // .. .. reg_ddrc_powerdown_to_x32 = 0x6
+ // .. .. ==> 0XF8006018[9:5] = 0x00000006U
+ // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U
+ // .. .. reg_ddrc_t_faw = 0x10
+ // .. .. ==> 0XF8006018[15:10] = 0x00000010U
+ // .. .. ==> MASK : 0x0000FC00U VAL : 0x00004000U
+ // .. .. reg_ddrc_t_ras_max = 0x24
+ // .. .. ==> 0XF8006018[21:16] = 0x00000024U
+ // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U
+ // .. .. reg_ddrc_t_ras_min = 0x14
+ // .. .. ==> 0XF8006018[26:22] = 0x00000014U
+ // .. .. ==> MASK : 0x07C00000U VAL : 0x05000000U
+ // .. .. reg_ddrc_t_cke = 0x4
+ // .. .. ==> 0XF8006018[31:28] = 0x00000004U
+ // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x452440D2U),
+ // .. .. reg_ddrc_write_latency = 0x5
+ // .. .. ==> 0XF800601C[4:0] = 0x00000005U
+ // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U
+ // .. .. reg_ddrc_rd2wr = 0x7
+ // .. .. ==> 0XF800601C[9:5] = 0x00000007U
+ // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U
+ // .. .. reg_ddrc_wr2rd = 0xe
+ // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
+ // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U
+ // .. .. reg_ddrc_t_xp = 0x4
+ // .. .. ==> 0XF800601C[19:15] = 0x00000004U
+ // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U
+ // .. .. reg_ddrc_pad_pd = 0x0
+ // .. .. ==> 0XF800601C[22:20] = 0x00000000U
+ // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U
+ // .. .. reg_ddrc_rd2pre = 0x4
+ // .. .. ==> 0XF800601C[27:23] = 0x00000004U
+ // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U
+ // .. .. reg_ddrc_t_rcd = 0x7
+ // .. .. ==> 0XF800601C[31:28] = 0x00000007U
+ // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
+ // .. .. reg_ddrc_t_ccd = 0x4
+ // .. .. ==> 0XF8006020[4:2] = 0x00000004U
+ // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U
+ // .. .. reg_ddrc_t_rrd = 0x4
+ // .. .. ==> 0XF8006020[7:5] = 0x00000004U
+ // .. .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. .. reg_ddrc_refresh_margin = 0x2
+ // .. .. ==> 0XF8006020[11:8] = 0x00000002U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
+ // .. .. reg_ddrc_t_rp = 0x7
+ // .. .. ==> 0XF8006020[15:12] = 0x00000007U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U
+ // .. .. reg_ddrc_refresh_to_x32 = 0x8
+ // .. .. ==> 0XF8006020[20:16] = 0x00000008U
+ // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U
+ // .. .. reg_ddrc_sdram = 0x1
+ // .. .. ==> 0XF8006020[21:21] = 0x00000001U
+ // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U
+ // .. .. reg_ddrc_mobile = 0x0
+ // .. .. ==> 0XF8006020[22:22] = 0x00000000U
+ // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U
+ // .. .. reg_ddrc_clock_stop_en = 0x0
+ // .. .. ==> 0XF8006020[23:23] = 0x00000000U
+ // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U
+ // .. .. reg_ddrc_read_latency = 0x7
+ // .. .. ==> 0XF8006020[28:24] = 0x00000007U
+ // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U
+ // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
+ // .. .. ==> 0XF8006020[29:29] = 0x00000001U
+ // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U
+ // .. .. reg_ddrc_dis_pad_pd = 0x0
+ // .. .. ==> 0XF8006020[30:30] = 0x00000000U
+ // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_loopback = 0x0
+ // .. .. ==> 0XF8006020[31:31] = 0x00000000U
+ // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x27287290U),
+ // .. .. reg_ddrc_en_2t_timing_mode = 0x0
+ // .. .. ==> 0XF8006024[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_prefer_write = 0x0
+ // .. .. ==> 0XF8006024[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_ddrc_max_rank_rd = 0xf
+ // .. .. ==> 0XF8006024[5:2] = 0x0000000FU
+ // .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU
+ // .. .. reg_ddrc_mr_wr = 0x0
+ // .. .. ==> 0XF8006024[6:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr_addr = 0x0
+ // .. .. ==> 0XF8006024[8:7] = 0x00000000U
+ // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr_data = 0x0
+ // .. .. ==> 0XF8006024[24:9] = 0x00000000U
+ // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U
+ // .. .. ddrc_reg_mr_wr_busy = 0x0
+ // .. .. ==> 0XF8006024[25:25] = 0x00000000U
+ // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr_type = 0x0
+ // .. .. ==> 0XF8006024[26:26] = 0x00000000U
+ // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr_rdata_valid = 0x0
+ // .. .. ==> 0XF8006024[27:27] = 0x00000000U
+ // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU),
+ // .. .. reg_ddrc_final_wait_x32 = 0x7
+ // .. .. ==> 0XF8006028[6:0] = 0x00000007U
+ // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U
+ // .. .. reg_ddrc_pre_ocd_x32 = 0x0
+ // .. .. ==> 0XF8006028[10:7] = 0x00000000U
+ // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U
+ // .. .. reg_ddrc_t_mrd = 0x4
+ // .. .. ==> 0XF8006028[13:11] = 0x00000004U
+ // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
+ // .. .. reg_ddrc_emr2 = 0x8
+ // .. .. ==> 0XF800602C[15:0] = 0x00000008U
+ // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U
+ // .. .. reg_ddrc_emr3 = 0x0
+ // .. .. ==> 0XF800602C[31:16] = 0x00000000U
+ // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
+ // .. .. reg_ddrc_mr = 0x930
+ // .. .. ==> 0XF8006030[15:0] = 0x00000930U
+ // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U
+ // .. .. reg_ddrc_emr = 0x4
+ // .. .. ==> 0XF8006030[31:16] = 0x00000004U
+ // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
+ // .. .. reg_ddrc_burst_rdwr = 0x4
+ // .. .. ==> 0XF8006034[3:0] = 0x00000004U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U
+ // .. .. reg_ddrc_pre_cke_x1024 = 0x105
+ // .. .. ==> 0XF8006034[13:4] = 0x00000105U
+ // .. .. ==> MASK : 0x00003FF0U VAL : 0x00001050U
+ // .. .. reg_ddrc_post_cke_x1024 = 0x1
+ // .. .. ==> 0XF8006034[25:16] = 0x00000001U
+ // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U
+ // .. .. reg_ddrc_burstchop = 0x0
+ // .. .. ==> 0XF8006034[28:28] = 0x00000000U
+ // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U),
+ // .. .. reg_ddrc_force_low_pri_n = 0x0
+ // .. .. ==> 0XF8006038[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_dq = 0x0
+ // .. .. ==> 0XF8006038[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_debug_mode = 0x0
+ // .. .. ==> 0XF8006038[6:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U
+ // .. .. reg_phy_wr_level_start = 0x0
+ // .. .. ==> 0XF8006038[7:7] = 0x00000000U
+ // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. .. reg_phy_rd_level_start = 0x0
+ // .. .. ==> 0XF8006038[8:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. .. reg_phy_dq0_wait_t = 0x0
+ // .. .. ==> 0XF8006038[12:9] = 0x00000000U
+ // .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U),
+ // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
+ // .. .. ==> 0XF800603C[3:0] = 0x00000007U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U
+ // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
+ // .. .. ==> 0XF800603C[7:4] = 0x00000007U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U
+ // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
+ // .. .. ==> 0XF800603C[11:8] = 0x00000007U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U
+ // .. .. reg_ddrc_addrmap_col_b5 = 0x0
+ // .. .. ==> 0XF800603C[15:12] = 0x00000000U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b6 = 0x0
+ // .. .. ==> 0XF800603C[19:16] = 0x00000000U
+ // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
+ // .. .. reg_ddrc_addrmap_col_b2 = 0x0
+ // .. .. ==> 0XF8006040[3:0] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b3 = 0x0
+ // .. .. ==> 0XF8006040[7:4] = 0x00000000U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b4 = 0x0
+ // .. .. ==> 0XF8006040[11:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b7 = 0x0
+ // .. .. ==> 0XF8006040[15:12] = 0x00000000U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b8 = 0x0
+ // .. .. ==> 0XF8006040[19:16] = 0x00000000U
+ // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b9 = 0xf
+ // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
+ // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U
+ // .. .. reg_ddrc_addrmap_col_b10 = 0xf
+ // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
+ // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U
+ // .. .. reg_ddrc_addrmap_col_b11 = 0xf
+ // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
+ // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
+ // .. .. reg_ddrc_addrmap_row_b0 = 0x6
+ // .. .. ==> 0XF8006044[3:0] = 0x00000006U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U
+ // .. .. reg_ddrc_addrmap_row_b1 = 0x6
+ // .. .. ==> 0XF8006044[7:4] = 0x00000006U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U
+ // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
+ // .. .. ==> 0XF8006044[11:8] = 0x00000006U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U
+ // .. .. reg_ddrc_addrmap_row_b12 = 0x6
+ // .. .. ==> 0XF8006044[15:12] = 0x00000006U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U
+ // .. .. reg_ddrc_addrmap_row_b13 = 0x6
+ // .. .. ==> 0XF8006044[19:16] = 0x00000006U
+ // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U
+ // .. .. reg_ddrc_addrmap_row_b14 = 0x6
+ // .. .. ==> 0XF8006044[23:20] = 0x00000006U
+ // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U
+ // .. .. reg_ddrc_addrmap_row_b15 = 0xf
+ // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
+ // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U),
+ // .. .. reg_ddrc_rank0_rd_odt = 0x0
+ // .. .. ==> 0XF8006048[2:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U
+ // .. .. reg_ddrc_rank0_wr_odt = 0x1
+ // .. .. ==> 0XF8006048[5:3] = 0x00000001U
+ // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U
+ // .. .. reg_ddrc_rank1_rd_odt = 0x1
+ // .. .. ==> 0XF8006048[8:6] = 0x00000001U
+ // .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U
+ // .. .. reg_ddrc_rank1_wr_odt = 0x1
+ // .. .. ==> 0XF8006048[11:9] = 0x00000001U
+ // .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. .. reg_phy_rd_local_odt = 0x0
+ // .. .. ==> 0XF8006048[13:12] = 0x00000000U
+ // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U
+ // .. .. reg_phy_wr_local_odt = 0x3
+ // .. .. ==> 0XF8006048[15:14] = 0x00000003U
+ // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U
+ // .. .. reg_phy_idle_local_odt = 0x3
+ // .. .. ==> 0XF8006048[17:16] = 0x00000003U
+ // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U
+ // .. .. reg_ddrc_rank2_rd_odt = 0x0
+ // .. .. ==> 0XF8006048[20:18] = 0x00000000U
+ // .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U
+ // .. .. reg_ddrc_rank2_wr_odt = 0x0
+ // .. .. ==> 0XF8006048[23:21] = 0x00000000U
+ // .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U
+ // .. .. reg_ddrc_rank3_rd_odt = 0x0
+ // .. .. ==> 0XF8006048[26:24] = 0x00000000U
+ // .. .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_rank3_wr_odt = 0x0
+ // .. .. ==> 0XF8006048[29:27] = 0x00000000U
+ // .. .. ==> MASK : 0x38000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U),
+ // .. .. reg_phy_rd_cmd_to_data = 0x0
+ // .. .. ==> 0XF8006050[3:0] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
+ // .. .. reg_phy_wr_cmd_to_data = 0x0
+ // .. .. ==> 0XF8006050[7:4] = 0x00000000U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. .. reg_phy_rdc_we_to_re_delay = 0x8
+ // .. .. ==> 0XF8006050[11:8] = 0x00000008U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U
+ // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
+ // .. .. ==> 0XF8006050[15:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
+ // .. .. reg_phy_use_fixed_re = 0x1
+ // .. .. ==> 0XF8006050[16:16] = 0x00000001U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U
+ // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
+ // .. .. ==> 0XF8006050[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
+ // .. .. ==> 0XF8006050[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_phy_clk_stall_level = 0x0
+ // .. .. ==> 0XF8006050[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
+ // .. .. ==> 0XF8006050[27:24] = 0x00000007U
+ // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U
+ // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
+ // .. .. ==> 0XF8006050[31:28] = 0x00000007U
+ // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
+ // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1
+ // .. .. ==> 0XF8006058[7:0] = 0x00000001U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U
+ // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1
+ // .. .. ==> 0XF8006058[15:8] = 0x00000001U
+ // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U
+ // .. .. reg_ddrc_dis_dll_calib = 0x0
+ // .. .. ==> 0XF8006058[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U),
+ // .. .. reg_ddrc_rd_odt_delay = 0x3
+ // .. .. ==> 0XF800605C[3:0] = 0x00000003U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U
+ // .. .. reg_ddrc_wr_odt_delay = 0x0
+ // .. .. ==> 0XF800605C[7:4] = 0x00000000U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. .. reg_ddrc_rd_odt_hold = 0x0
+ // .. .. ==> 0XF800605C[11:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U
+ // .. .. reg_ddrc_wr_odt_hold = 0x5
+ // .. .. ==> 0XF800605C[15:12] = 0x00000005U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
+ // .. .. reg_ddrc_pageclose = 0x0
+ // .. .. ==> 0XF8006060[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_lpr_num_entries = 0x1f
+ // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
+ // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU
+ // .. .. reg_ddrc_auto_pre_en = 0x0
+ // .. .. ==> 0XF8006060[7:7] = 0x00000000U
+ // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. .. reg_ddrc_refresh_update_level = 0x0
+ // .. .. ==> 0XF8006060[8:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_wc = 0x0
+ // .. .. ==> 0XF8006060[9:9] = 0x00000000U
+ // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_collision_page_opt = 0x0
+ // .. .. ==> 0XF8006060[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_ddrc_selfref_en = 0x0
+ // .. .. ==> 0XF8006060[12:12] = 0x00000000U
+ // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
+ // .. .. reg_ddrc_go2critical_hysteresis = 0x0
+ // .. .. ==> 0XF8006064[12:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U
+ // .. .. reg_arb_go2critical_en = 0x1
+ // .. .. ==> 0XF8006064[17:17] = 0x00000001U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
+ // .. .. reg_ddrc_wrlvl_ww = 0x41
+ // .. .. ==> 0XF8006068[7:0] = 0x00000041U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U
+ // .. .. reg_ddrc_rdlvl_rr = 0x41
+ // .. .. ==> 0XF8006068[15:8] = 0x00000041U
+ // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U
+ // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
+ // .. .. ==> 0XF8006068[25:16] = 0x00000028U
+ // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
+ // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
+ // .. .. ==> 0XF800606C[7:0] = 0x00000010U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U
+ // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
+ // .. .. ==> 0XF800606C[15:8] = 0x00000016U
+ // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U
+ // .. ..
+ EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
+ // .. .. refresh_timer0_start_value_x32 = 0x0
+ // .. .. ==> 0XF80060A0[11:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U
+ // .. .. refresh_timer1_start_value_x32 = 0x8
+ // .. .. ==> 0XF80060A0[23:12] = 0x00000008U
+ // .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U),
+ // .. .. reg_ddrc_dis_auto_zq = 0x0
+ // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_ddr3 = 0x1
+ // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. .. reg_ddrc_t_mod = 0x200
+ // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
+ // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U
+ // .. .. reg_ddrc_t_zq_long_nop = 0x200
+ // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U
+ // .. .. reg_ddrc_t_zq_short_nop = 0x40
+ // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
+ // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
+ // .. .. t_zq_short_interval_x1024 = 0xcb73
+ // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U
+ // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U
+ // .. .. dram_rstn_x1024 = 0x69
+ // .. .. ==> 0XF80060A8[27:20] = 0x00000069U
+ // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
+ // .. .. deeppowerdown_en = 0x0
+ // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. deeppowerdown_to_x1024 = 0xff
+ // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
+ // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU
+ // .. ..
+ EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
+ // .. .. dfi_wrlvl_max_x1024 = 0xfff
+ // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
+ // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU
+ // .. .. dfi_rdlvl_max_x1024 = 0xfff
+ // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
+ // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U
+ // .. .. ddrc_reg_twrlvl_max_error = 0x0
+ // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
+ // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U
+ // .. .. ddrc_reg_trdlvl_max_error = 0x0
+ // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
+ // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dfi_wr_level_en = 0x1
+ // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
+ // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U
+ // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
+ // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
+ // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U
+ // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
+ // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
+ // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
+ // .. .. reg_ddrc_2t_delay = 0x0
+ // .. .. ==> 0XF80060B4[8:0] = 0x00000000U
+ // .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U
+ // .. .. reg_ddrc_skip_ocd = 0x1
+ // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
+ // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U
+ // .. .. reg_ddrc_dis_pre_bypass = 0x0
+ // .. .. ==> 0XF80060B4[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U),
+ // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
+ // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
+ // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U
+ // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
+ // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
+ // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U
+ // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
+ // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
+ // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
+ // .. .. START: RESET ECC ERROR
+ // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1
+ // .. .. ==> 0XF80060C4[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. Clear_Correctable_DRAM_ECC_error = 1
+ // .. .. ==> 0XF80060C4[1:1] = 0x00000001U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U),
+ // .. .. FINISH: RESET ECC ERROR
+ // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
+ // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
+ // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
+ // .. .. CORR_ECC_LOG_VALID = 0x0
+ // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. ECC_CORRECTED_BIT_NUM = 0x0
+ // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
+ // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
+ // .. .. UNCORR_ECC_LOG_VALID = 0x0
+ // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
+ // .. .. STAT_NUM_CORR_ERR = 0x0
+ // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
+ // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U
+ // .. .. STAT_NUM_UNCORR_ERR = 0x0
+ // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
+ // .. .. reg_ddrc_ecc_mode = 0x0
+ // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_scrub = 0x1
+ // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
+ // .. .. reg_phy_dif_on = 0x0
+ // .. .. ==> 0XF8006114[3:0] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
+ // .. .. reg_phy_dif_off = 0x0
+ // .. .. ==> 0XF8006114[7:4] = 0x00000000U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
+ // .. .. reg_phy_data_slice_in_use = 0x1
+ // .. .. ==> 0XF8006118[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_phy_rdlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006118[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006118[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_wrlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006118[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_tx = 0x0
+ // .. .. ==> 0XF8006118[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_rx = 0x0
+ // .. .. ==> 0XF8006118[5:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
+ // .. .. reg_phy_bist_shift_dq = 0x0
+ // .. .. ==> 0XF8006118[14:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
+ // .. .. reg_phy_bist_err_clr = 0x0
+ // .. .. ==> 0XF8006118[23:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
+ // .. .. reg_phy_dq_offset = 0x40
+ // .. .. ==> 0XF8006118[30:24] = 0x00000040U
+ // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U),
+ // .. .. reg_phy_data_slice_in_use = 0x1
+ // .. .. ==> 0XF800611C[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_phy_rdlvl_inc_mode = 0x0
+ // .. .. ==> 0XF800611C[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_inc_mode = 0x0
+ // .. .. ==> 0XF800611C[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_wrlvl_inc_mode = 0x0
+ // .. .. ==> 0XF800611C[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_tx = 0x0
+ // .. .. ==> 0XF800611C[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_rx = 0x0
+ // .. .. ==> 0XF800611C[5:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
+ // .. .. reg_phy_bist_shift_dq = 0x0
+ // .. .. ==> 0XF800611C[14:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
+ // .. .. reg_phy_bist_err_clr = 0x0
+ // .. .. ==> 0XF800611C[23:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
+ // .. .. reg_phy_dq_offset = 0x40
+ // .. .. ==> 0XF800611C[30:24] = 0x00000040U
+ // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U),
+ // .. .. reg_phy_data_slice_in_use = 0x1
+ // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_phy_rdlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_wrlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_tx = 0x0
+ // .. .. ==> 0XF8006120[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_rx = 0x0
+ // .. .. ==> 0XF8006120[5:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
+ // .. .. reg_phy_bist_shift_dq = 0x0
+ // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
+ // .. .. reg_phy_bist_err_clr = 0x0
+ // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
+ // .. .. reg_phy_dq_offset = 0x40
+ // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+ // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U),
+ // .. .. reg_phy_data_slice_in_use = 0x1
+ // .. .. ==> 0XF8006124[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_phy_rdlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006124[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006124[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_wrlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006124[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_tx = 0x0
+ // .. .. ==> 0XF8006124[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_rx = 0x0
+ // .. .. ==> 0XF8006124[5:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
+ // .. .. reg_phy_bist_shift_dq = 0x0
+ // .. .. ==> 0XF8006124[14:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
+ // .. .. reg_phy_bist_err_clr = 0x0
+ // .. .. ==> 0XF8006124[23:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
+ // .. .. reg_phy_dq_offset = 0x40
+ // .. .. ==> 0XF8006124[30:24] = 0x00000040U
+ // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U),
+ // .. .. reg_phy_wrlvl_init_ratio = 0x1e
+ // .. .. ==> 0XF800612C[9:0] = 0x0000001EU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x0000001EU
+ // .. .. reg_phy_gatelvl_init_ratio = 0xee
+ // .. .. ==> 0XF800612C[19:10] = 0x000000EEU
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x0003B800U
+ // .. ..
+ EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0003B81EU),
+ // .. .. reg_phy_wrlvl_init_ratio = 0x25
+ // .. .. ==> 0XF8006130[9:0] = 0x00000025U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000025U
+ // .. .. reg_phy_gatelvl_init_ratio = 0x10d
+ // .. .. ==> 0XF8006130[19:10] = 0x0000010DU
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x00043400U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00043425U),
+ // .. .. reg_phy_wrlvl_init_ratio = 0x19
+ // .. .. ==> 0XF8006134[9:0] = 0x00000019U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000019U
+ // .. .. reg_phy_gatelvl_init_ratio = 0xf3
+ // .. .. ==> 0XF8006134[19:10] = 0x000000F3U
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x0003CC00U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0003CC19U),
+ // .. .. reg_phy_wrlvl_init_ratio = 0x2a
+ // .. .. ==> 0XF8006138[9:0] = 0x0000002AU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x0000002AU
+ // .. .. reg_phy_gatelvl_init_ratio = 0x109
+ // .. .. ==> 0XF8006138[19:10] = 0x00000109U
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x00042400U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0004242AU),
+ // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+ // .. .. ==> 0XF8006140[9:0] = 0x00000035U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
+ // .. .. reg_phy_rd_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006140[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006140[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
+ // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+ // .. .. ==> 0XF8006144[9:0] = 0x00000035U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
+ // .. .. reg_phy_rd_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006144[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006144[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
+ // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+ // .. .. ==> 0XF8006148[9:0] = 0x00000035U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
+ // .. .. reg_phy_rd_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006148[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006148[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
+ // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+ // .. .. ==> 0XF800614C[9:0] = 0x00000035U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
+ // .. .. reg_phy_rd_dqs_slave_force = 0x0
+ // .. .. ==> 0XF800614C[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF800614C[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
+ // .. .. reg_phy_wr_dqs_slave_ratio = 0x9e
+ // .. .. ==> 0XF8006154[9:0] = 0x0000009EU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x0000009EU
+ // .. .. reg_phy_wr_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006154[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006154[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x0000009EU),
+ // .. .. reg_phy_wr_dqs_slave_ratio = 0xa5
+ // .. .. ==> 0XF8006158[9:0] = 0x000000A5U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000A5U
+ // .. .. reg_phy_wr_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006158[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006158[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x000000A5U),
+ // .. .. reg_phy_wr_dqs_slave_ratio = 0x99
+ // .. .. ==> 0XF800615C[9:0] = 0x00000099U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000099U
+ // .. .. reg_phy_wr_dqs_slave_force = 0x0
+ // .. .. ==> 0XF800615C[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF800615C[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000099U),
+ // .. .. reg_phy_wr_dqs_slave_ratio = 0xaa
+ // .. .. ==> 0XF8006160[9:0] = 0x000000AAU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000AAU
+ // .. .. reg_phy_wr_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006160[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006160[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x000000AAU),
+ // .. .. reg_phy_fifo_we_slave_ratio = 0x143
+ // .. .. ==> 0XF8006168[10:0] = 0x00000143U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000143U
+ // .. .. reg_phy_fifo_we_in_force = 0x0
+ // .. .. ==> 0XF8006168[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. reg_phy_fifo_we_in_delay = 0x0
+ // .. .. ==> 0XF8006168[20:12] = 0x00000000U
+ // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000143U),
+ // .. .. reg_phy_fifo_we_slave_ratio = 0x162
+ // .. .. ==> 0XF800616C[10:0] = 0x00000162U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000162U
+ // .. .. reg_phy_fifo_we_in_force = 0x0
+ // .. .. ==> 0XF800616C[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. reg_phy_fifo_we_in_delay = 0x0
+ // .. .. ==> 0XF800616C[20:12] = 0x00000000U
+ // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x00000162U),
+ // .. .. reg_phy_fifo_we_slave_ratio = 0x148
+ // .. .. ==> 0XF8006170[10:0] = 0x00000148U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000148U
+ // .. .. reg_phy_fifo_we_in_force = 0x0
+ // .. .. ==> 0XF8006170[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. reg_phy_fifo_we_in_delay = 0x0
+ // .. .. ==> 0XF8006170[20:12] = 0x00000000U
+ // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000148U),
+ // .. .. reg_phy_fifo_we_slave_ratio = 0x15e
+ // .. .. ==> 0XF8006174[10:0] = 0x0000015EU
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x0000015EU
+ // .. .. reg_phy_fifo_we_in_force = 0x0
+ // .. .. ==> 0XF8006174[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. reg_phy_fifo_we_in_delay = 0x0
+ // .. .. ==> 0XF8006174[20:12] = 0x00000000U
+ // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x0000015EU),
+ // .. .. reg_phy_wr_data_slave_ratio = 0xde
+ // .. .. ==> 0XF800617C[9:0] = 0x000000DEU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000DEU
+ // .. .. reg_phy_wr_data_slave_force = 0x0
+ // .. .. ==> 0XF800617C[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_data_slave_delay = 0x0
+ // .. .. ==> 0XF800617C[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000DEU),
+ // .. .. reg_phy_wr_data_slave_ratio = 0xe5
+ // .. .. ==> 0XF8006180[9:0] = 0x000000E5U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000E5U
+ // .. .. reg_phy_wr_data_slave_force = 0x0
+ // .. .. ==> 0XF8006180[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_data_slave_delay = 0x0
+ // .. .. ==> 0XF8006180[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000E5U),
+ // .. .. reg_phy_wr_data_slave_ratio = 0xd9
+ // .. .. ==> 0XF8006184[9:0] = 0x000000D9U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000D9U
+ // .. .. reg_phy_wr_data_slave_force = 0x0
+ // .. .. ==> 0XF8006184[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_data_slave_delay = 0x0
+ // .. .. ==> 0XF8006184[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000D9U),
+ // .. .. reg_phy_wr_data_slave_ratio = 0xea
+ // .. .. ==> 0XF8006188[9:0] = 0x000000EAU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000EAU
+ // .. .. reg_phy_wr_data_slave_force = 0x0
+ // .. .. ==> 0XF8006188[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_data_slave_delay = 0x0
+ // .. .. ==> 0XF8006188[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000EAU),
+ // .. .. reg_phy_loopback = 0x0
+ // .. .. ==> 0XF8006190[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_phy_bl2 = 0x0
+ // .. .. ==> 0XF8006190[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_at_spd_atpg = 0x0
+ // .. .. ==> 0XF8006190[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_bist_enable = 0x0
+ // .. .. ==> 0XF8006190[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_bist_force_err = 0x0
+ // .. .. ==> 0XF8006190[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reg_phy_bist_mode = 0x0
+ // .. .. ==> 0XF8006190[6:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U
+ // .. .. reg_phy_invert_clkout = 0x1
+ // .. .. ==> 0XF8006190[7:7] = 0x00000001U
+ // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0
+ // .. .. ==> 0XF8006190[8:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. .. reg_phy_sel_logic = 0x0
+ // .. .. ==> 0XF8006190[9:9] = 0x00000000U
+ // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U
+ // .. .. reg_phy_ctrl_slave_ratio = 0x100
+ // .. .. ==> 0XF8006190[19:10] = 0x00000100U
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U
+ // .. .. reg_phy_ctrl_slave_force = 0x0
+ // .. .. ==> 0XF8006190[20:20] = 0x00000000U
+ // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U
+ // .. .. reg_phy_ctrl_slave_delay = 0x0
+ // .. .. ==> 0XF8006190[27:21] = 0x00000000U
+ // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U
+ // .. .. reg_phy_use_rank0_delays = 0x1
+ // .. .. ==> 0XF8006190[28:28] = 0x00000001U
+ // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
+ // .. .. reg_phy_lpddr = 0x0
+ // .. .. ==> 0XF8006190[29:29] = 0x00000000U
+ // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U
+ // .. .. reg_phy_cmd_latency = 0x0
+ // .. .. ==> 0XF8006190[30:30] = 0x00000000U
+ // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U
+ // .. .. reg_phy_int_lpbk = 0x0
+ // .. .. ==> 0XF8006190[31:31] = 0x00000000U
+ // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U),
+ // .. .. reg_phy_wr_rl_delay = 0x2
+ // .. .. ==> 0XF8006194[4:0] = 0x00000002U
+ // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U
+ // .. .. reg_phy_rd_rl_delay = 0x4
+ // .. .. ==> 0XF8006194[9:5] = 0x00000004U
+ // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U
+ // .. .. reg_phy_dll_lock_diff = 0xf
+ // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
+ // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U
+ // .. .. reg_phy_use_wr_level = 0x1
+ // .. .. ==> 0XF8006194[14:14] = 0x00000001U
+ // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U
+ // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
+ // .. .. ==> 0XF8006194[15:15] = 0x00000001U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U
+ // .. .. reg_phy_use_rd_data_eye_level = 0x1
+ // .. .. ==> 0XF8006194[16:16] = 0x00000001U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U
+ // .. .. reg_phy_dis_calib_rst = 0x0
+ // .. .. ==> 0XF8006194[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_phy_ctrl_slave_delay = 0x0
+ // .. .. ==> 0XF8006194[19:18] = 0x00000000U
+ // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
+ // .. .. reg_arb_page_addr_mask = 0x0
+ // .. .. ==> 0XF8006204[31:0] = 0x00000000U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
+ // .. .. reg_arb_pri_wr_portn = 0x3ff
+ // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_wr_portn = 0x0
+ // .. .. ==> 0XF8006208[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+ // .. .. ==> 0XF8006208[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+ // .. .. ==> 0XF8006208[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_rmw_portn = 0x1
+ // .. .. ==> 0XF8006208[19:19] = 0x00000001U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU),
+ // .. .. reg_arb_pri_wr_portn = 0x3ff
+ // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_wr_portn = 0x0
+ // .. .. ==> 0XF800620C[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+ // .. .. ==> 0XF800620C[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+ // .. .. ==> 0XF800620C[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_rmw_portn = 0x1
+ // .. .. ==> 0XF800620C[19:19] = 0x00000001U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU),
+ // .. .. reg_arb_pri_wr_portn = 0x3ff
+ // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_wr_portn = 0x0
+ // .. .. ==> 0XF8006210[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+ // .. .. ==> 0XF8006210[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+ // .. .. ==> 0XF8006210[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_rmw_portn = 0x1
+ // .. .. ==> 0XF8006210[19:19] = 0x00000001U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU),
+ // .. .. reg_arb_pri_wr_portn = 0x3ff
+ // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_wr_portn = 0x0
+ // .. .. ==> 0XF8006214[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+ // .. .. ==> 0XF8006214[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+ // .. .. ==> 0XF8006214[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_rmw_portn = 0x1
+ // .. .. ==> 0XF8006214[19:19] = 0x00000001U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU),
+ // .. .. reg_arb_pri_rd_portn = 0x3ff
+ // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_rd_portn = 0x0
+ // .. .. ==> 0XF8006218[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+ // .. .. ==> 0XF8006218[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+ // .. .. ==> 0XF8006218[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_set_hpr_rd_portn = 0x0
+ // .. .. ==> 0XF8006218[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
+ // .. .. reg_arb_pri_rd_portn = 0x3ff
+ // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_rd_portn = 0x0
+ // .. .. ==> 0XF800621C[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+ // .. .. ==> 0XF800621C[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+ // .. .. ==> 0XF800621C[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_set_hpr_rd_portn = 0x0
+ // .. .. ==> 0XF800621C[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
+ // .. .. reg_arb_pri_rd_portn = 0x3ff
+ // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_rd_portn = 0x0
+ // .. .. ==> 0XF8006220[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+ // .. .. ==> 0XF8006220[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+ // .. .. ==> 0XF8006220[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_set_hpr_rd_portn = 0x0
+ // .. .. ==> 0XF8006220[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
+ // .. .. reg_arb_pri_rd_portn = 0x3ff
+ // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_rd_portn = 0x0
+ // .. .. ==> 0XF8006224[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+ // .. .. ==> 0XF8006224[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+ // .. .. ==> 0XF8006224[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_set_hpr_rd_portn = 0x0
+ // .. .. ==> 0XF8006224[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
+ // .. .. reg_ddrc_lpddr2 = 0x0
+ // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_per_bank_refresh = 0x0
+ // .. .. ==> 0XF80062A8[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_ddrc_derate_enable = 0x0
+ // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr4_margin = 0x0
+ // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U),
+ // .. .. reg_ddrc_mr4_read_interval = 0x0
+ // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
+ // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
+ // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U
+ // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
+ // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
+ // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U
+ // .. .. reg_ddrc_t_mrw = 0x5
+ // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
+ // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8
+ // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U
+ // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
+ // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
+ // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U
+ // .. ..
+ EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
+ // .. .. START: POLL ON DCI STATUS
+ // .. .. DONE = 1
+ // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
+ // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U
+ // .. ..
+ EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+ // .. .. FINISH: POLL ON DCI STATUS
+ // .. .. START: UNLOCK DDR
+ // .. .. reg_ddrc_soft_rstb = 0x1
+ // .. .. ==> 0XF8006000[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_ddrc_powerdown_en = 0x0
+ // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_ddrc_data_bus_width = 0x0
+ // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U
+ // .. .. reg_ddrc_burst8_refresh = 0x0
+ // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U
+ // .. .. reg_ddrc_rdwr_idle_gap = 1
+ // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+ // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U
+ // .. .. reg_ddrc_dis_rd_bypass = 0x0
+ // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+ // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_act_bypass = 0x0
+ // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_auto_refresh = 0x0
+ // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
+ // .. .. FINISH: UNLOCK DDR
+ // .. .. START: CHECK DDR STATUS
+ // .. .. ddrc_reg_operating_mode = 1
+ // .. .. ==> 0XF8006054[2:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U
+ // .. ..
+ EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+ // .. .. FINISH: CHECK DDR STATUS
+ // .. FINISH: DDR INITIALIZATION
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_mio_init_data_1_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: OCM REMAPPING
+ // .. VREF_EN = 0x1
+ // .. ==> 0XF8000B00[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. VREF_PULLUP_EN = 0x0
+ // .. ==> 0XF8000B00[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. CLK_PULLUP_EN = 0x0
+ // .. ==> 0XF8000B00[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. SRSTN_PULLUP_EN = 0x0
+ // .. ==> 0XF8000B00[9:9] = 0x00000000U
+ // .. ==> MASK : 0x00000200U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B00, 0x00000303U ,0x00000001U),
+ // .. FINISH: OCM REMAPPING
+ // .. START: DDRIOB SETTINGS
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B40[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x0
+ // .. ==> 0XF8000B40[2:1] = 0x00000000U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000000U
+ // .. DCI_UPDATE = 0x0
+ // .. ==> 0XF8000B40[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x0
+ // .. ==> 0XF8000B40[4:4] = 0x00000000U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. DCR_TYPE = 0x0
+ // .. ==> 0XF8000B40[6:5] = 0x00000000U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000000U
+ // .. IBUF_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B40[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B40[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B40[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B40[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B44[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x0
+ // .. ==> 0XF8000B44[2:1] = 0x00000000U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000000U
+ // .. DCI_UPDATE = 0x0
+ // .. ==> 0XF8000B44[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x0
+ // .. ==> 0XF8000B44[4:4] = 0x00000000U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. DCR_TYPE = 0x0
+ // .. ==> 0XF8000B44[6:5] = 0x00000000U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000000U
+ // .. IBUF_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B44[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B44[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B44[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B44[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B48[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x1
+ // .. ==> 0XF8000B48[2:1] = 0x00000001U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000002U
+ // .. DCI_UPDATE = 0x0
+ // .. ==> 0XF8000B48[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x1
+ // .. ==> 0XF8000B48[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. DCR_TYPE = 0x3
+ // .. ==> 0XF8000B48[6:5] = 0x00000003U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000060U
+ // .. IBUF_DISABLE_MODE = 0
+ // .. ==> 0XF8000B48[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0
+ // .. ==> 0XF8000B48[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B48[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B48[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B4C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x1
+ // .. ==> 0XF8000B4C[2:1] = 0x00000001U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000002U
+ // .. DCI_UPDATE = 0x0
+ // .. ==> 0XF8000B4C[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x1
+ // .. ==> 0XF8000B4C[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. DCR_TYPE = 0x3
+ // .. ==> 0XF8000B4C[6:5] = 0x00000003U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000060U
+ // .. IBUF_DISABLE_MODE = 0
+ // .. ==> 0XF8000B4C[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0
+ // .. ==> 0XF8000B4C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B4C[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B4C[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B50[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x2
+ // .. ==> 0XF8000B50[2:1] = 0x00000002U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000004U
+ // .. DCI_UPDATE = 0x0
+ // .. ==> 0XF8000B50[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x1
+ // .. ==> 0XF8000B50[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. DCR_TYPE = 0x3
+ // .. ==> 0XF8000B50[6:5] = 0x00000003U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000060U
+ // .. IBUF_DISABLE_MODE = 0
+ // .. ==> 0XF8000B50[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0
+ // .. ==> 0XF8000B50[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B50[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B50[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B54[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x2
+ // .. ==> 0XF8000B54[2:1] = 0x00000002U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000004U
+ // .. DCI_UPDATE = 0x0
+ // .. ==> 0XF8000B54[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x1
+ // .. ==> 0XF8000B54[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. DCR_TYPE = 0x3
+ // .. ==> 0XF8000B54[6:5] = 0x00000003U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000060U
+ // .. IBUF_DISABLE_MODE = 0
+ // .. ==> 0XF8000B54[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0
+ // .. ==> 0XF8000B54[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B54[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B54[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B58[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x0
+ // .. ==> 0XF8000B58[2:1] = 0x00000000U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000000U
+ // .. DCI_UPDATE = 0x0
+ // .. ==> 0XF8000B58[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x0
+ // .. ==> 0XF8000B58[4:4] = 0x00000000U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. DCR_TYPE = 0x0
+ // .. ==> 0XF8000B58[6:5] = 0x00000000U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000000U
+ // .. IBUF_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B58[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B58[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B58[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B58[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
+ // .. DRIVE_P = 0x1c
+ // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
+ // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
+ // .. DRIVE_N = 0xc
+ // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
+ // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
+ // .. SLEW_P = 0x3
+ // .. ==> 0XF8000B5C[18:14] = 0x00000003U
+ // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U
+ // .. SLEW_N = 0x3
+ // .. ==> 0XF8000B5C[23:19] = 0x00000003U
+ // .. ==> MASK : 0x00F80000U VAL : 0x00180000U
+ // .. GTL = 0x0
+ // .. ==> 0XF8000B5C[26:24] = 0x00000000U
+ // .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. RTERM = 0x0
+ // .. ==> 0XF8000B5C[31:27] = 0x00000000U
+ // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
+ // .. DRIVE_P = 0x1c
+ // .. ==> 0XF8000B60[6:0] = 0x0000001CU
+ // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
+ // .. DRIVE_N = 0xc
+ // .. ==> 0XF8000B60[13:7] = 0x0000000CU
+ // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
+ // .. SLEW_P = 0x6
+ // .. ==> 0XF8000B60[18:14] = 0x00000006U
+ // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
+ // .. SLEW_N = 0x1f
+ // .. ==> 0XF8000B60[23:19] = 0x0000001FU
+ // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
+ // .. GTL = 0x0
+ // .. ==> 0XF8000B60[26:24] = 0x00000000U
+ // .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. RTERM = 0x0
+ // .. ==> 0XF8000B60[31:27] = 0x00000000U
+ // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
+ // .. DRIVE_P = 0x1c
+ // .. ==> 0XF8000B64[6:0] = 0x0000001CU
+ // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
+ // .. DRIVE_N = 0xc
+ // .. ==> 0XF8000B64[13:7] = 0x0000000CU
+ // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
+ // .. SLEW_P = 0x6
+ // .. ==> 0XF8000B64[18:14] = 0x00000006U
+ // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
+ // .. SLEW_N = 0x1f
+ // .. ==> 0XF8000B64[23:19] = 0x0000001FU
+ // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
+ // .. GTL = 0x0
+ // .. ==> 0XF8000B64[26:24] = 0x00000000U
+ // .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. RTERM = 0x0
+ // .. ==> 0XF8000B64[31:27] = 0x00000000U
+ // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
+ // .. DRIVE_P = 0x1c
+ // .. ==> 0XF8000B68[6:0] = 0x0000001CU
+ // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
+ // .. DRIVE_N = 0xc
+ // .. ==> 0XF8000B68[13:7] = 0x0000000CU
+ // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
+ // .. SLEW_P = 0x6
+ // .. ==> 0XF8000B68[18:14] = 0x00000006U
+ // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
+ // .. SLEW_N = 0x1f
+ // .. ==> 0XF8000B68[23:19] = 0x0000001FU
+ // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
+ // .. GTL = 0x0
+ // .. ==> 0XF8000B68[26:24] = 0x00000000U
+ // .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. RTERM = 0x0
+ // .. ==> 0XF8000B68[31:27] = 0x00000000U
+ // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
+ // .. VREF_INT_EN = 0x1
+ // .. ==> 0XF8000B6C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. VREF_SEL = 0x4
+ // .. ==> 0XF8000B6C[4:1] = 0x00000004U
+ // .. ==> MASK : 0x0000001EU VAL : 0x00000008U
+ // .. VREF_EXT_EN = 0x0
+ // .. ==> 0XF8000B6C[6:5] = 0x00000000U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000000U
+ // .. VREF_PULLUP_EN = 0x0
+ // .. ==> 0XF8000B6C[8:7] = 0x00000000U
+ // .. ==> MASK : 0x00000180U VAL : 0x00000000U
+ // .. REFIO_EN = 0x1
+ // .. ==> 0XF8000B6C[9:9] = 0x00000001U
+ // .. ==> MASK : 0x00000200U VAL : 0x00000200U
+ // .. REFIO_PULLUP_EN = 0x0
+ // .. ==> 0XF8000B6C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DRST_B_PULLUP_EN = 0x0
+ // .. ==> 0XF8000B6C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // .. CKE_PULLUP_EN = 0x0
+ // .. ==> 0XF8000B6C[14:14] = 0x00000000U
+ // .. ==> MASK : 0x00004000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B6C, 0x000073FFU ,0x00000209U),
+ // .. .. START: ASSERT RESET
+ // .. .. RESET = 1
+ // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. VRN_OUT = 0x1
+ // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U),
+ // .. .. FINISH: ASSERT RESET
+ // .. .. START: DEASSERT RESET
+ // .. .. RESET = 0
+ // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. VRN_OUT = 0x1
+ // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
+ // .. .. FINISH: DEASSERT RESET
+ // .. .. RESET = 0x1
+ // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ENABLE = 0x1
+ // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. .. VRP_TRI = 0x0
+ // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. VRN_TRI = 0x0
+ // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. VRP_OUT = 0x0
+ // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. VRN_OUT = 0x1
+ // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
+ // .. .. NREF_OPT1 = 0x0
+ // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
+ // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U
+ // .. .. NREF_OPT2 = 0x0
+ // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U
+ // .. .. NREF_OPT4 = 0x1
+ // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
+ // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U
+ // .. .. PREF_OPT1 = 0x0
+ // .. .. ==> 0XF8000B70[16:14] = 0x00000000U
+ // .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U
+ // .. .. PREF_OPT2 = 0x0
+ // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
+ // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U
+ // .. .. UPDATE_CONTROL = 0x0
+ // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
+ // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U
+ // .. .. INIT_COMPLETE = 0x0
+ // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
+ // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U
+ // .. .. TST_CLK = 0x0
+ // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
+ // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U
+ // .. .. TST_HLN = 0x0
+ // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
+ // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U
+ // .. .. TST_HLP = 0x0
+ // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
+ // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U
+ // .. .. TST_RST = 0x0
+ // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
+ // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
+ // .. .. INT_DCI_EN = 0x0
+ // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
+ // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U),
+ // .. FINISH: DDRIOB SETTINGS
+ // .. START: MIO PROGRAMMING
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000700[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000700[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000700[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000700[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000700[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000700[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000700[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000700[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000700[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000704[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000704[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000704[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000704[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000704[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000704[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000704[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000704[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000704[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000708[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000708[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000708[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000708[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000708[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000708[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000708[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000708[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000708[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800070C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF800070C[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800070C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800070C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800070C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800070C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800070C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800070C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800070C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000710[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000710[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000710[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000710[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000710[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000710[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000710[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000710[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000710[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000714[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000714[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000714[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000714[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000714[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000714[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000714[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000714[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000714[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000718[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000718[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000718[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000718[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000718[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000718[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000718[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000718[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000718[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800071C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800071C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800071C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800071C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800071C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800071C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800071C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800071C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800071C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000200U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000720[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000720[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000720[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000720[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000720[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000720[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000720[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000720[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000720[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000724[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000724[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000724[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000724[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000724[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000724[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000724[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000724[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000724[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000728[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000728[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000728[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000728[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000728[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000728[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000728[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000728[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000728[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800072C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF800072C[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800072C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800072C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800072C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800072C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800072C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF800072C[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800072C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000730[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000730[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000730[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000730[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000730[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000730[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000730[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000730[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000730[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001202U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000734[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000734[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000734[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000734[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000734[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000734[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000734[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000734[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000734[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001202U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000738[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. Speed = 0
+ // .. ==> 0XF8000738[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000738[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF8000738[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000738[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000738, 0x00003F01U ,0x00001201U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF800073C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. Speed = 0
+ // .. ==> 0XF800073C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800073C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF800073C[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800073C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800073C, 0x00003F01U ,0x00001201U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000740[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000740[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000740[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000740[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000740[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000740[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 4
+ // .. ==> 0XF8000740[11:9] = 0x00000004U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000740[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 1
+ // .. ==> 0XF8000740[13:13] = 0x00000001U
+ // .. ==> MASK : 0x00002000U VAL : 0x00002000U
+ // ..
+ EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00002802U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000744[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000744[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000744[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000744[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000744[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000744[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 4
+ // .. ==> 0XF8000744[11:9] = 0x00000004U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000744[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 1
+ // .. ==> 0XF8000744[13:13] = 0x00000001U
+ // .. ==> MASK : 0x00002000U VAL : 0x00002000U
+ // ..
+ EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00002802U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000748[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000748[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000748[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000748[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000748[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000748[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 4
+ // .. ==> 0XF8000748[11:9] = 0x00000004U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000748[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 1
+ // .. ==> 0XF8000748[13:13] = 0x00000001U
+ // .. ==> MASK : 0x00002000U VAL : 0x00002000U
+ // ..
+ EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00002802U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800074C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF800074C[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800074C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800074C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800074C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800074C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 4
+ // .. ==> 0XF800074C[11:9] = 0x00000004U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
+ // .. PULLUP = 0
+ // .. ==> 0XF800074C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 1
+ // .. ==> 0XF800074C[13:13] = 0x00000001U
+ // .. ==> MASK : 0x00002000U VAL : 0x00002000U
+ // ..
+ EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00002802U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000750[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000750[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000750[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000750[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000750[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000750[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 4
+ // .. ==> 0XF8000750[11:9] = 0x00000004U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000750[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 1
+ // .. ==> 0XF8000750[13:13] = 0x00000001U
+ // .. ==> MASK : 0x00002000U VAL : 0x00002000U
+ // ..
+ EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00002802U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000754[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000754[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000754[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000754[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000754[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000754[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 4
+ // .. ==> 0XF8000754[11:9] = 0x00000004U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000754[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 1
+ // .. ==> 0XF8000754[13:13] = 0x00000001U
+ // .. ==> MASK : 0x00002000U VAL : 0x00002000U
+ // ..
+ EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00002802U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000758[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000758[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000758[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000758[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000758[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000758[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 4
+ // .. ==> 0XF8000758[11:9] = 0x00000004U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000758[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000758[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000803U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF800075C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF800075C[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800075C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800075C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800075C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800075C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 4
+ // .. ==> 0XF800075C[11:9] = 0x00000004U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
+ // .. PULLUP = 0
+ // .. ==> 0XF800075C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800075C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000803U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000760[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000760[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000760[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000760[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000760[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000760[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 4
+ // .. ==> 0XF8000760[11:9] = 0x00000004U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000760[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000760[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000803U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000764[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000764[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000764[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000764[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000764[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000764[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 4
+ // .. ==> 0XF8000764[11:9] = 0x00000004U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000764[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000764[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000803U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000768[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000768[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000768[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000768[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000768[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000768[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 4
+ // .. ==> 0XF8000768[11:9] = 0x00000004U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000768[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000768[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000803U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF800076C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF800076C[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800076C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800076C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800076C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800076C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 4
+ // .. ==> 0XF800076C[11:9] = 0x00000004U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000800U
+ // .. PULLUP = 0
+ // .. ==> 0XF800076C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800076C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000803U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000770[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000770[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000770[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000770[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000770[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000770[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000770[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000770[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000770[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000774[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000774[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000774[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000774[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000774[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000774[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000774[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000774[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000774[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000778[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000778[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000778[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000778[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000778[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000778[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000778[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000778[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000778[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF800077C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800077C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF800077C[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800077C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800077C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800077C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800077C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800077C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800077C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000780[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000780[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000780[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000780[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000780[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000780[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000780[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000780[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000780[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000784[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000784[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000784[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000784[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000784[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000784[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000784[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000784[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000784[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000788[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000788[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000788[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000788[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000788[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000788[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000788[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000788[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000788[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800078C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800078C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF800078C[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800078C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800078C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800078C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800078C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800078C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800078C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000790[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000790[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000790[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000790[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000790[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000790[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000790[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000790[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000790[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000794[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000794[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000794[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000794[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000794[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000794[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000794[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000794[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000794[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000798[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000798[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000798[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000798[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000798[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000798[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000798[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000798[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000798[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800079C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800079C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF800079C[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800079C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800079C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800079C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF800079C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800079C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800079C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007A0[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007A0[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007A0[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007A0[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007A0[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007A0[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007A0[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007A0[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007A0[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007A4[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007A4[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007A4[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007A4[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007A4[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007A4[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007A4[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007A4[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007A4[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007A8[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007A8[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007A8[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007A8[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007A8[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007A8[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007A8[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007A8[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007A8[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007AC[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007AC[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007AC[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007AC[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007AC[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007AC[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007AC[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007AC[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007AC[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007B0[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007B0[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007B0[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007B0[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007B0[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007B0[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007B0[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007B0[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007B0[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007B4[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007B4[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007B4[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007B4[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007B4[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007B4[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007B4[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007B4[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007B4[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007B8[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007B8[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007B8[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007B8[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF80007B8[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF80007B8[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007B8[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF80007B8[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007B8[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001200U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007BC[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007BC[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007BC[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007BC[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF80007BC[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF80007BC[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007BC[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF80007BC[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007BC[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00001200U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007C0[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007C0[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007C0[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007C0[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 7
+ // .. ==> 0XF80007C0[7:5] = 0x00000007U
+ // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U
+ // .. Speed = 0
+ // .. ==> 0XF80007C0[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007C0[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007C0[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007C0[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF80007C4[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007C4[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007C4[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007C4[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 7
+ // .. ==> 0XF80007C4[7:5] = 0x00000007U
+ // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U
+ // .. Speed = 0
+ // .. ==> 0XF80007C4[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007C4[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007C4[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007C4[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007C8[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007C8[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007C8[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007C8[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 2
+ // .. ==> 0XF80007C8[7:5] = 0x00000002U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000040U
+ // .. Speed = 0
+ // .. ==> 0XF80007C8[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007C8[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF80007C8[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007C8[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001240U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007CC[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007CC[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007CC[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007CC[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 2
+ // .. ==> 0XF80007CC[7:5] = 0x00000002U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000040U
+ // .. Speed = 0
+ // .. ==> 0XF80007CC[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007CC[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 1
+ // .. ==> 0XF80007CC[12:12] = 0x00000001U
+ // .. ==> MASK : 0x00001000U VAL : 0x00001000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007CC[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001240U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007D0[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007D0[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007D0[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007D0[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007D0[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007D0[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007D0[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007D0[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007D0[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007D4[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007D4[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007D4[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007D4[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007D4[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007D4[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007D4[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007D4[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007D4[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U),
+ // .. SDIO0_WP_SEL = 15
+ // .. ==> 0XF8000830[5:0] = 0x0000000FU
+ // .. ==> MASK : 0x0000003FU VAL : 0x0000000FU
+ // .. SDIO0_CD_SEL = 14
+ // .. ==> 0XF8000830[21:16] = 0x0000000EU
+ // .. ==> MASK : 0x003F0000U VAL : 0x000E0000U
+ // ..
+ EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x000E000FU),
+ // .. FINISH: MIO PROGRAMMING
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_peripherals_init_data_1_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+ // .. IBUF_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B48[7:7] = 0x00000001U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. TERM_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B48[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // ..
+ EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
+ // .. IBUF_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B4C[7:7] = 0x00000001U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. TERM_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B4C[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // ..
+ EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
+ // .. IBUF_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B50[7:7] = 0x00000001U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. TERM_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B50[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // ..
+ EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
+ // .. IBUF_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B54[7:7] = 0x00000001U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. TERM_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B54[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // ..
+ EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
+ // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // .. START: SRAM/NOR SET OPMODE
+ // .. FINISH: SRAM/NOR SET OPMODE
+ // .. START: UART REGISTERS
+ // .. BDIV = 0x6
+ // .. ==> 0XE0001034[7:0] = 0x00000006U
+ // .. ==> MASK : 0x000000FFU VAL : 0x00000006U
+ // ..
+ EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
+ // .. CD = 0x3e
+ // .. ==> 0XE0001018[15:0] = 0x0000003EU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU
+ // ..
+ EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
+ // .. STPBRK = 0x0
+ // .. ==> 0XE0001000[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. STTBRK = 0x0
+ // .. ==> 0XE0001000[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. RSTTO = 0x0
+ // .. ==> 0XE0001000[6:6] = 0x00000000U
+ // .. ==> MASK : 0x00000040U VAL : 0x00000000U
+ // .. TXDIS = 0x0
+ // .. ==> 0XE0001000[5:5] = 0x00000000U
+ // .. ==> MASK : 0x00000020U VAL : 0x00000000U
+ // .. TXEN = 0x1
+ // .. ==> 0XE0001000[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. RXDIS = 0x0
+ // .. ==> 0XE0001000[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. RXEN = 0x1
+ // .. ==> 0XE0001000[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. TXRES = 0x1
+ // .. ==> 0XE0001000[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. RXRES = 0x1
+ // .. ==> 0XE0001000[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // ..
+ EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
+ // .. IRMODE = 0x0
+ // .. ==> 0XE0001004[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. UCLKEN = 0x0
+ // .. ==> 0XE0001004[10:10] = 0x00000000U
+ // .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. CHMODE = 0x0
+ // .. ==> 0XE0001004[9:8] = 0x00000000U
+ // .. ==> MASK : 0x00000300U VAL : 0x00000000U
+ // .. NBSTOP = 0x0
+ // .. ==> 0XE0001004[7:6] = 0x00000000U
+ // .. ==> MASK : 0x000000C0U VAL : 0x00000000U
+ // .. PAR = 0x4
+ // .. ==> 0XE0001004[5:3] = 0x00000004U
+ // .. ==> MASK : 0x00000038U VAL : 0x00000020U
+ // .. CHRL = 0x0
+ // .. ==> 0XE0001004[2:1] = 0x00000000U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000000U
+ // .. CLKS = 0x0
+ // .. ==> 0XE0001004[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U),
+ // .. FINISH: UART REGISTERS
+ // .. START: QSPI REGISTERS
+ // .. Holdb_dr = 1
+ // .. ==> 0XE000D000[19:19] = 0x00000001U
+ // .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // ..
+ EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
+ // .. FINISH: QSPI REGISTERS
+ // .. START: PL POWER ON RESET REGISTERS
+ // .. PCFG_POR_CNT_4K = 0
+ // .. ==> 0XF8007000[29:29] = 0x00000000U
+ // .. ==> MASK : 0x20000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
+ // .. FINISH: PL POWER ON RESET REGISTERS
+ // .. START: SMC TIMING CALCULATION REGISTER UPDATE
+ // .. .. START: NAND SET CYCLE
+ // .. .. FINISH: NAND SET CYCLE
+ // .. .. START: OPMODE
+ // .. .. FINISH: OPMODE
+ // .. .. START: DIRECT COMMAND
+ // .. .. FINISH: DIRECT COMMAND
+ // .. .. START: SRAM/NOR CS0 SET CYCLE
+ // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
+ // .. .. START: DIRECT COMMAND
+ // .. .. FINISH: DIRECT COMMAND
+ // .. .. START: NOR CS0 BASE ADDRESS
+ // .. .. FINISH: NOR CS0 BASE ADDRESS
+ // .. .. START: SRAM/NOR CS1 SET CYCLE
+ // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
+ // .. .. START: DIRECT COMMAND
+ // .. .. FINISH: DIRECT COMMAND
+ // .. .. START: NOR CS1 BASE ADDRESS
+ // .. .. FINISH: NOR CS1 BASE ADDRESS
+ // .. .. START: USB RESET
+ // .. .. .. START: USB0 RESET
+ // .. .. .. .. START: DIR MODE BANK 0
+ // .. .. .. .. DIRECTION_0 = 0x80
+ // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U
+ // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U),
+ // .. .. .. .. FINISH: DIR MODE BANK 0
+ // .. .. .. .. START: DIR MODE BANK 1
+ // .. .. .. .. FINISH: DIR MODE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. MASK_0_LSW = 0xff7f
+ // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+ // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U
+ // .. .. .. .. DATA_0_LSW = 0x80
+ // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+ // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. START: OUTPUT ENABLE BANK 0
+ // .. .. .. .. OP_ENABLE_0 = 0x80
+ // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U
+ // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U),
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+ // .. .. .. .. START: OUTPUT ENABLE BANK 1
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. MASK_0_LSW = 0xff7f
+ // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+ // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U
+ // .. .. .. .. DATA_0_LSW = 0x0
+ // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+ // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U),
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. START: ADD 1 MS DELAY
+ // .. .. .. ..
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ // .. .. .. .. FINISH: ADD 1 MS DELAY
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. MASK_0_LSW = 0xff7f
+ // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+ // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U
+ // .. .. .. .. DATA_0_LSW = 0x80
+ // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+ // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. FINISH: USB0 RESET
+ // .. .. .. START: USB1 RESET
+ // .. .. .. .. START: DIR MODE BANK 0
+ // .. .. .. .. FINISH: DIR MODE BANK 0
+ // .. .. .. .. START: DIR MODE BANK 1
+ // .. .. .. .. FINISH: DIR MODE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. START: OUTPUT ENABLE BANK 0
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+ // .. .. .. .. START: OUTPUT ENABLE BANK 1
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. START: ADD 1 MS DELAY
+ // .. .. .. ..
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ // .. .. .. .. FINISH: ADD 1 MS DELAY
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. FINISH: USB1 RESET
+ // .. .. FINISH: USB RESET
+ // .. .. START: ENET RESET
+ // .. .. .. START: ENET0 RESET
+ // .. .. .. .. START: DIR MODE BANK 0
+ // .. .. .. .. FINISH: DIR MODE BANK 0
+ // .. .. .. .. START: DIR MODE BANK 1
+ // .. .. .. .. DIRECTION_1 = 0x8000
+ // .. .. .. .. ==> 0XE000A244[21:0] = 0x00008000U
+ // .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00008000U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x00008000U),
+ // .. .. .. .. FINISH: DIR MODE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. MASK_1_LSW = 0x7fff
+ // .. .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU
+ // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0x7FFF0000U
+ // .. .. .. .. DATA_1_LSW = 0x8000
+ // .. .. .. .. ==> 0XE000A008[15:0] = 0x00008000U
+ // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00008000U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF8000U),
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. START: OUTPUT ENABLE BANK 0
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+ // .. .. .. .. START: OUTPUT ENABLE BANK 1
+ // .. .. .. .. OP_ENABLE_1 = 0x8000
+ // .. .. .. .. ==> 0XE000A248[21:0] = 0x00008000U
+ // .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00008000U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x00008000U),
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. MASK_1_LSW = 0x7fff
+ // .. .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU
+ // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0x7FFF0000U
+ // .. .. .. .. DATA_1_LSW = 0x0
+ // .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U
+ // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF0000U),
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. START: ADD 1 MS DELAY
+ // .. .. .. ..
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ // .. .. .. .. FINISH: ADD 1 MS DELAY
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. MASK_1_LSW = 0x7fff
+ // .. .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU
+ // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0x7FFF0000U
+ // .. .. .. .. DATA_1_LSW = 0x8000
+ // .. .. .. .. ==> 0XE000A008[15:0] = 0x00008000U
+ // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00008000U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF8000U),
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. FINISH: ENET0 RESET
+ // .. .. .. START: ENET1 RESET
+ // .. .. .. .. START: DIR MODE BANK 0
+ // .. .. .. .. FINISH: DIR MODE BANK 0
+ // .. .. .. .. START: DIR MODE BANK 1
+ // .. .. .. .. FINISH: DIR MODE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. START: OUTPUT ENABLE BANK 0
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+ // .. .. .. .. START: OUTPUT ENABLE BANK 1
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. START: ADD 1 MS DELAY
+ // .. .. .. ..
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ // .. .. .. .. FINISH: ADD 1 MS DELAY
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. FINISH: ENET1 RESET
+ // .. .. FINISH: ENET RESET
+ // .. .. START: I2C RESET
+ // .. .. .. START: I2C0 RESET
+ // .. .. .. .. START: DIR MODE GPIO BANK0
+ // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+ // .. .. .. .. START: DIR MODE GPIO BANK1
+ // .. .. .. .. DIRECTION_1 = 0x4000
+ // .. .. .. .. ==> 0XE000A244[21:0] = 0x00004000U
+ // .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x00004000U),
+ // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. MASK_1_LSW = 0xbfff
+ // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
+ // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U
+ // .. .. .. .. DATA_1_LSW = 0x4000
+ // .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U
+ // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U),
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. START: OUTPUT ENABLE
+ // .. .. .. .. FINISH: OUTPUT ENABLE
+ // .. .. .. .. START: OUTPUT ENABLE
+ // .. .. .. .. OP_ENABLE_1 = 0x4000
+ // .. .. .. .. ==> 0XE000A248[21:0] = 0x00004000U
+ // .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x00004000U),
+ // .. .. .. .. FINISH: OUTPUT ENABLE
+ // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. MASK_1_LSW = 0xbfff
+ // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
+ // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U
+ // .. .. .. .. DATA_1_LSW = 0x0
+ // .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U
+ // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF0000U),
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. START: ADD 1 MS DELAY
+ // .. .. .. ..
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ // .. .. .. .. FINISH: ADD 1 MS DELAY
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. MASK_1_LSW = 0xbfff
+ // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
+ // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U
+ // .. .. .. .. DATA_1_LSW = 0x4000
+ // .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U
+ // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U
+ // .. .. .. ..
+ EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U),
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. FINISH: I2C0 RESET
+ // .. .. .. START: I2C1 RESET
+ // .. .. .. .. START: DIR MODE GPIO BANK0
+ // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+ // .. .. .. .. START: DIR MODE GPIO BANK1
+ // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. START: OUTPUT ENABLE
+ // .. .. .. .. FINISH: OUTPUT ENABLE
+ // .. .. .. .. START: OUTPUT ENABLE
+ // .. .. .. .. FINISH: OUTPUT ENABLE
+ // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. START: ADD 1 MS DELAY
+ // .. .. .. ..
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ // .. .. .. .. FINISH: ADD 1 MS DELAY
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. FINISH: I2C1 RESET
+ // .. .. FINISH: I2C RESET
+ // .. .. START: NOR CHIP SELECT
+ // .. .. .. START: DIR MODE BANK 0
+ // .. .. .. FINISH: DIR MODE BANK 0
+ // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. START: OUTPUT ENABLE BANK 0
+ // .. .. .. FINISH: OUTPUT ENABLE BANK 0
+ // .. .. FINISH: NOR CHIP SELECT
+ // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_post_config_1_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: ENABLING LEVEL SHIFTER
+ // .. USER_INP_ICT_EN_0 = 3
+ // .. ==> 0XF8000900[1:0] = 0x00000003U
+ // .. ==> MASK : 0x00000003U VAL : 0x00000003U
+ // .. USER_INP_ICT_EN_1 = 3
+ // .. ==> 0XF8000900[3:2] = 0x00000003U
+ // .. ==> MASK : 0x0000000CU VAL : 0x0000000CU
+ // ..
+ EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
+ // .. FINISH: ENABLING LEVEL SHIFTER
+ // .. START: FPGA RESETS TO 0
+ // .. reserved_3 = 0
+ // .. ==> 0XF8000240[31:25] = 0x00000000U
+ // .. ==> MASK : 0xFE000000U VAL : 0x00000000U
+ // .. FPGA_ACP_RST = 0
+ // .. ==> 0XF8000240[24:24] = 0x00000000U
+ // .. ==> MASK : 0x01000000U VAL : 0x00000000U
+ // .. FPGA_AXDS3_RST = 0
+ // .. ==> 0XF8000240[23:23] = 0x00000000U
+ // .. ==> MASK : 0x00800000U VAL : 0x00000000U
+ // .. FPGA_AXDS2_RST = 0
+ // .. ==> 0XF8000240[22:22] = 0x00000000U
+ // .. ==> MASK : 0x00400000U VAL : 0x00000000U
+ // .. FPGA_AXDS1_RST = 0
+ // .. ==> 0XF8000240[21:21] = 0x00000000U
+ // .. ==> MASK : 0x00200000U VAL : 0x00000000U
+ // .. FPGA_AXDS0_RST = 0
+ // .. ==> 0XF8000240[20:20] = 0x00000000U
+ // .. ==> MASK : 0x00100000U VAL : 0x00000000U
+ // .. reserved_2 = 0
+ // .. ==> 0XF8000240[19:18] = 0x00000000U
+ // .. ==> MASK : 0x000C0000U VAL : 0x00000000U
+ // .. FSSW1_FPGA_RST = 0
+ // .. ==> 0XF8000240[17:17] = 0x00000000U
+ // .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. FSSW0_FPGA_RST = 0
+ // .. ==> 0XF8000240[16:16] = 0x00000000U
+ // .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. reserved_1 = 0
+ // .. ==> 0XF8000240[15:14] = 0x00000000U
+ // .. ==> MASK : 0x0000C000U VAL : 0x00000000U
+ // .. FPGA_FMSW1_RST = 0
+ // .. ==> 0XF8000240[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // .. FPGA_FMSW0_RST = 0
+ // .. ==> 0XF8000240[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. FPGA_DMA3_RST = 0
+ // .. ==> 0XF8000240[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. FPGA_DMA2_RST = 0
+ // .. ==> 0XF8000240[10:10] = 0x00000000U
+ // .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. FPGA_DMA1_RST = 0
+ // .. ==> 0XF8000240[9:9] = 0x00000000U
+ // .. ==> MASK : 0x00000200U VAL : 0x00000000U
+ // .. FPGA_DMA0_RST = 0
+ // .. ==> 0XF8000240[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. reserved = 0
+ // .. ==> 0XF8000240[7:4] = 0x00000000U
+ // .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. FPGA3_OUT_RST = 0
+ // .. ==> 0XF8000240[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. FPGA2_OUT_RST = 0
+ // .. ==> 0XF8000240[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. FPGA1_OUT_RST = 0
+ // .. ==> 0XF8000240[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. FPGA0_OUT_RST = 0
+ // .. ==> 0XF8000240[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
+ // .. FINISH: FPGA RESETS TO 0
+ // .. START: AFI REGISTERS
+ // .. .. START: AFI0 REGISTERS
+ // .. .. FINISH: AFI0 REGISTERS
+ // .. .. START: AFI1 REGISTERS
+ // .. .. FINISH: AFI1 REGISTERS
+ // .. .. START: AFI2 REGISTERS
+ // .. .. FINISH: AFI2 REGISTERS
+ // .. .. START: AFI3 REGISTERS
+ // .. .. FINISH: AFI3 REGISTERS
+ // .. FINISH: AFI REGISTERS
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_debug_1_0[] = {
+ // START: top
+ // .. START: CROSS TRIGGER CONFIGURATIONS
+ // .. .. START: UNLOCKING CTI REGISTERS
+ // .. .. KEY = 0XC5ACCE55
+ // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
+ // .. ..
+ EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
+ // .. .. KEY = 0XC5ACCE55
+ // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
+ // .. ..
+ EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
+ // .. .. KEY = 0XC5ACCE55
+ // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
+ // .. ..
+ EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
+ // .. .. FINISH: UNLOCKING CTI REGISTERS
+ // .. .. START: ENABLING CTI MODULES AND CHANNELS
+ // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
+ // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+ // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+ // .. FINISH: CROSS TRIGGER CONFIGURATIONS
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+
+#include "xil_io.h"
+#define PS7_MASK_POLL_TIME 100000000
+
+char*
+getPS7MessageInfo(unsigned key) {
+
+ char* err_msg = "";
+ switch (key) {
+ case PS7_INIT_SUCCESS: err_msg = "PS7 initialization successful"; break;
+ case PS7_INIT_CORRUPT: err_msg = "PS7 init Data Corrupted"; break;
+ case PS7_INIT_TIMEOUT: err_msg = "PS7 init mask poll timeout"; break;
+ case PS7_POLL_FAILED_DDR_INIT: err_msg = "Mask Poll failed for DDR Init"; break;
+ case PS7_POLL_FAILED_DMA: err_msg = "Mask Poll failed for PLL Init"; break;
+ case PS7_POLL_FAILED_PLL: err_msg = "Mask Poll failed for DMA done bit"; break;
+ default: err_msg = "Undefined error status"; break;
+ }
+
+ return err_msg;
+}
+
+unsigned long
+ps7GetSiliconVersion () {
+ // Read PS version from MCTRL register [31:28]
+ unsigned long mask = 0xF0000000;
+ unsigned long *addr = (unsigned long*) 0XF8007080;
+ unsigned long ps_version = (*addr & mask) >> 28;
+ return ps_version;
+}
+
+void mask_write (unsigned long add , unsigned long mask, unsigned long val ) {
+ unsigned long *addr = (unsigned long*) add;
+ *addr = ( val & mask ) | ( *addr & ~mask);
+ //xil_printf("MaskWrite : 0x%x--> 0x%x \n \r" ,add, *addr);
+}
+
+
+int mask_poll(unsigned long add , unsigned long mask ) {
+ volatile unsigned long *addr = (volatile unsigned long*) add;
+ int i = 0;
+ while (!(*addr & mask)) {
+ if (i == PS7_MASK_POLL_TIME) {
+ return -1;
+ }
+ i++;
+ }
+ return 1;
+ //xil_printf("MaskPoll : 0x%x --> 0x%x \n \r" , add, *addr);
+}
+
+unsigned long mask_read(unsigned long add , unsigned long mask ) {
+ unsigned long *addr = (unsigned long*) add;
+ unsigned long val = (*addr & mask);
+ //xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val);
+ return val;
+}
+
+
+
+int
+ps7_config(unsigned long * ps7_config_init)
+{
+ unsigned long *ptr = ps7_config_init;
+
+ unsigned long opcode; // current instruction ..
+ unsigned long args[16]; // no opcode has so many args ...
+ int numargs; // number of arguments of this instruction
+ int j; // general purpose index
+
+ volatile unsigned long *addr; // some variable to make code readable
+ unsigned long val,mask; // some variable to make code readable
+
+ int finish = -1 ; // loop while this is negative !
+ int i = 0; // Timeout variable
+
+ while( finish < 0 ) {
+ numargs = ptr[0] & 0xF;
+ opcode = ptr[0] >> 4;
+
+ for( j = 0 ; j < numargs ; j ++ )
+ args[j] = ptr[j+1];
+ ptr += numargs + 1;
+
+
+ switch ( opcode ) {
+
+ case OPCODE_EXIT:
+ finish = PS7_INIT_SUCCESS;
+ break;
+
+ case OPCODE_CLEAR:
+ addr = (unsigned long*) args[0];
+ *addr = 0;
+ break;
+
+ case OPCODE_WRITE:
+ addr = (unsigned long*) args[0];
+ val = args[1];
+ *addr = val;
+ break;
+
+ case OPCODE_MASKWRITE:
+ addr = (unsigned long*) args[0];
+ mask = args[1];
+ val = args[2];
+ *addr = ( val & mask ) | ( *addr & ~mask);
+ break;
+
+ case OPCODE_MASKPOLL:
+ addr = (unsigned long*) args[0];
+ mask = args[1];
+ i = 0;
+ while (!(*addr & mask)) {
+ if (i == PS7_MASK_POLL_TIME) {
+ finish = PS7_INIT_TIMEOUT;
+ break;
+ }
+ i++;
+ }
+ break;
+ case OPCODE_MASKDELAY:
+ addr = (unsigned long*) args[0];
+ mask = args[1];
+ int delay = get_number_of_cycles_for_delay(mask);
+ perf_reset_and_start_timer();
+ while ((*addr < delay)) {
+ }
+ break;
+ default:
+ finish = PS7_INIT_CORRUPT;
+ break;
+ }
+ }
+ return finish;
+}
+
+unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0;
+unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0;
+unsigned long *ps7_clock_init_data = ps7_clock_init_data_3_0;
+unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0;
+unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
+
+int
+ps7_post_config()
+{
+ // Get the PS_VERSION on run time
+ unsigned long si_ver = ps7GetSiliconVersion ();
+ int ret = -1;
+ if (si_ver == PCW_SILICON_VERSION_1) {
+ ret = ps7_config (ps7_post_config_1_0);
+ if (ret != PS7_INIT_SUCCESS) return ret;
+ } else if (si_ver == PCW_SILICON_VERSION_2) {
+ ret = ps7_config (ps7_post_config_2_0);
+ if (ret != PS7_INIT_SUCCESS) return ret;
+ } else {
+ ret = ps7_config (ps7_post_config_3_0);
+ if (ret != PS7_INIT_SUCCESS) return ret;
+ }
+ return PS7_INIT_SUCCESS;
+}
+
+int
+ps7_debug()
+{
+ // Get the PS_VERSION on run time
+ unsigned long si_ver = ps7GetSiliconVersion ();
+ int ret = -1;
+ if (si_ver == PCW_SILICON_VERSION_1) {
+ ret = ps7_config (ps7_debug_1_0);
+ if (ret != PS7_INIT_SUCCESS) return ret;
+ } else if (si_ver == PCW_SILICON_VERSION_2) {
+ ret = ps7_config (ps7_debug_2_0);
+ if (ret != PS7_INIT_SUCCESS) return ret;
+ } else {
+ ret = ps7_config (ps7_debug_3_0);
+ if (ret != PS7_INIT_SUCCESS) return ret;
+ }
+ return PS7_INIT_SUCCESS;
+}
+
+int
+ps7_init()
+{
+ // Get the PS_VERSION on run time
+ unsigned long si_ver = ps7GetSiliconVersion ();
+ int ret;
+ //int pcw_ver = 0;
+
+ if (si_ver == PCW_SILICON_VERSION_1) {
+ ps7_mio_init_data = ps7_mio_init_data_1_0;
+ ps7_pll_init_data = ps7_pll_init_data_1_0;
+ ps7_clock_init_data = ps7_clock_init_data_1_0;
+ ps7_ddr_init_data = ps7_ddr_init_data_1_0;
+ ps7_peripherals_init_data = ps7_peripherals_init_data_1_0;
+ //pcw_ver = 1;
+
+ } else if (si_ver == PCW_SILICON_VERSION_2) {
+ ps7_mio_init_data = ps7_mio_init_data_2_0;
+ ps7_pll_init_data = ps7_pll_init_data_2_0;
+ ps7_clock_init_data = ps7_clock_init_data_2_0;
+ ps7_ddr_init_data = ps7_ddr_init_data_2_0;
+ ps7_peripherals_init_data = ps7_peripherals_init_data_2_0;
+ //pcw_ver = 2;
+
+ } else {
+ ps7_mio_init_data = ps7_mio_init_data_3_0;
+ ps7_pll_init_data = ps7_pll_init_data_3_0;
+ ps7_clock_init_data = ps7_clock_init_data_3_0;
+ ps7_ddr_init_data = ps7_ddr_init_data_3_0;
+ ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
+ //pcw_ver = 3;
+ }
+
+ // MIO init
+ ret = ps7_config (ps7_mio_init_data);
+ if (ret != PS7_INIT_SUCCESS) return ret;
+
+ // PLL init
+ ret = ps7_config (ps7_pll_init_data);
+ if (ret != PS7_INIT_SUCCESS) return ret;
+
+ // Clock init
+ ret = ps7_config (ps7_clock_init_data);
+ if (ret != PS7_INIT_SUCCESS) return ret;
+
+ // DDR init
+ ret = ps7_config (ps7_ddr_init_data);
+ if (ret != PS7_INIT_SUCCESS) return ret;
+
+
+
+ // Peripherals init
+ ret = ps7_config (ps7_peripherals_init_data);
+ if (ret != PS7_INIT_SUCCESS) return ret;
+ //xil_printf ("\n PCW Silicon Version : %d.0", pcw_ver);
+ return PS7_INIT_SUCCESS;
+}
+
+
+
+
+/* For delay calculation using global timer */
+
+/* start timer */
+ void perf_start_clock(void)
+{
+ *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) | // Timer Enable
+ (1 << 3) | // Auto-increment
+ (0 << 8) // Pre-scale
+ );
+}
+
+/* stop timer and reset timer count regs */
+ void perf_reset_clock(void)
+{
+ perf_disable_clock();
+ *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_L32 = 0;
+ *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_U32 = 0;
+}
+
+/* Compute mask for given delay in miliseconds*/
+int get_number_of_cycles_for_delay(unsigned int delay)
+{
+ // GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x)
+ return (APU_FREQ*delay/(2*1000));
+
+}
+
+/* stop timer */
+ void perf_disable_clock(void)
+{
+ *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = 0;
+}
+
+void perf_reset_and_start_timer()
+{
+ perf_reset_clock();
+ perf_start_clock();
+}
--- /dev/null
+
+/******************************************************************************
+*
+* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
+*
+* SPDX-License-Identifier: GPL-2.0+
+*
+*
+*******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file ps7_init.h
+*
+* This file can be included in FSBL code
+* to get prototype of ps7_init() function
+* and error codes
+*
+*****************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+//typedef unsigned int u32;
+
+
+/** do we need to make this name more unique ? **/
+//extern u32 ps7_init_data[];
+extern unsigned long * ps7_ddr_init_data;
+extern unsigned long * ps7_mio_init_data;
+extern unsigned long * ps7_pll_init_data;
+extern unsigned long * ps7_clock_init_data;
+extern unsigned long * ps7_peripherals_init_data;
+
+
+
+#define OPCODE_EXIT 0U
+#define OPCODE_CLEAR 1U
+#define OPCODE_WRITE 2U
+#define OPCODE_MASKWRITE 3U
+#define OPCODE_MASKPOLL 4U
+#define OPCODE_MASKDELAY 5U
+#define NEW_PS7_ERR_CODE 1
+
+/* Encode number of arguments in last nibble */
+#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 )
+#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr
+#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val
+#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
+#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask
+#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
+
+/* Returns codes of PS7_Init */
+#define PS7_INIT_SUCCESS (0) // 0 is success in good old C
+#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now
+#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out
+#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init
+#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit
+#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init
+
+
+/* Silicon Versions */
+#define PCW_SILICON_VERSION_1 0
+#define PCW_SILICON_VERSION_2 1
+#define PCW_SILICON_VERSION_3 2
+
+/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
+#define PS7_POST_CONFIG
+
+/* Freq of all peripherals */
+
+#define APU_FREQ 666666687
+#define DDR_FREQ 533333374
+#define DCI_FREQ 10158731
+#define QSPI_FREQ 200000000
+#define SMC_FREQ 10000000
+#define ENET0_FREQ 25000000
+#define ENET1_FREQ 10000000
+#define USB0_FREQ 60000000
+#define USB1_FREQ 60000000
+#define SDIO_FREQ 50000000
+#define UART_FREQ 50000000
+#define SPI_FREQ 10000000
+#define I2C_FREQ 111111115
+#define WDT_FREQ 111111115
+#define TTC_FREQ 50000000
+#define CAN_FREQ 10000000
+#define PCAP_FREQ 200000000
+#define TPIU_FREQ 200000000
+#define FPGA0_FREQ 50000000
+#define FPGA1_FREQ 50000000
+#define FPGA2_FREQ 50000000
+#define FPGA3_FREQ 50000000
+
+
+/* For delay calculation using global registers*/
+#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
+#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204
+#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208
+#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218
+
+int ps7_config( unsigned long*);
+int ps7_init();
+int ps7_post_config();
+int ps7_debug();
+char* getPS7MessageInfo(unsigned key);
+
+void perf_start_clock(void);
+void perf_disable_clock(void);
+void perf_reset_clock(void);
+void perf_reset_and_start_timer();
+int get_number_of_cycles_for_delay(unsigned int delay);
+#ifdef __cplusplus
+}
+#endif
--- /dev/null
+/******************************************************************************
+* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
+*
+* SPDX-License-Identifier: GPL-2.0+
+*
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file ps7_init_gpl.c
+*
+* This file is automatically generated
+*
+*****************************************************************************/
+
+#include "ps7_init_gpl.h"
+
+unsigned long ps7_pll_init_data_3_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: PLL SLCR REGISTERS
+ // .. .. START: ARM PLL INIT
+ // .. .. PLL_RES = 0x2
+ // .. .. ==> 0XF8000110[7:4] = 0x00000002U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
+ // .. .. PLL_CP = 0x2
+ // .. .. ==> 0XF8000110[11:8] = 0x00000002U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
+ // .. .. LOCK_CNT = 0xfa
+ // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
+ // .. .. .. START: UPDATE FB_DIV
+ // .. .. .. PLL_FDIV = 0x28
+ // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
+ // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
+ // .. .. .. FINISH: UPDATE FB_DIV
+ // .. .. .. START: BY PASS PLL
+ // .. .. .. PLL_BYPASS_FORCE = 1
+ // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
+ // .. .. .. FINISH: BY PASS PLL
+ // .. .. .. START: ASSERT RESET
+ // .. .. .. PLL_RESET = 1
+ // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
+ // .. .. .. FINISH: ASSERT RESET
+ // .. .. .. START: DEASSERT RESET
+ // .. .. .. PLL_RESET = 0
+ // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
+ // .. .. .. FINISH: DEASSERT RESET
+ // .. .. .. START: CHECK PLL STATUS
+ // .. .. .. ARM_PLL_LOCK = 1
+ // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ..
+ EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+ // .. .. .. FINISH: CHECK PLL STATUS
+ // .. .. .. START: REMOVE PLL BY PASS
+ // .. .. .. PLL_BYPASS_FORCE = 0
+ // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
+ // .. .. .. FINISH: REMOVE PLL BY PASS
+ // .. .. .. SRCSEL = 0x0
+ // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. .. .. DIVISOR = 0x2
+ // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
+ // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U
+ // .. .. .. CPU_6OR4XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
+ // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U
+ // .. .. .. CPU_3OR2XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
+ // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U
+ // .. .. .. CPU_2XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
+ // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U
+ // .. .. .. CPU_1XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
+ // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U
+ // .. .. .. CPU_PERI_CLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
+ // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
+ // .. .. FINISH: ARM PLL INIT
+ // .. .. START: DDR PLL INIT
+ // .. .. PLL_RES = 0x2
+ // .. .. ==> 0XF8000114[7:4] = 0x00000002U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
+ // .. .. PLL_CP = 0x2
+ // .. .. ==> 0XF8000114[11:8] = 0x00000002U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
+ // .. .. LOCK_CNT = 0x12c
+ // .. .. ==> 0XF8000114[21:12] = 0x0000012CU
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
+ // .. .. .. START: UPDATE FB_DIV
+ // .. .. .. PLL_FDIV = 0x20
+ // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
+ // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
+ // .. .. .. FINISH: UPDATE FB_DIV
+ // .. .. .. START: BY PASS PLL
+ // .. .. .. PLL_BYPASS_FORCE = 1
+ // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
+ // .. .. .. FINISH: BY PASS PLL
+ // .. .. .. START: ASSERT RESET
+ // .. .. .. PLL_RESET = 1
+ // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
+ // .. .. .. FINISH: ASSERT RESET
+ // .. .. .. START: DEASSERT RESET
+ // .. .. .. PLL_RESET = 0
+ // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
+ // .. .. .. FINISH: DEASSERT RESET
+ // .. .. .. START: CHECK PLL STATUS
+ // .. .. .. DDR_PLL_LOCK = 1
+ // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. .. ..
+ EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+ // .. .. .. FINISH: CHECK PLL STATUS
+ // .. .. .. START: REMOVE PLL BY PASS
+ // .. .. .. PLL_BYPASS_FORCE = 0
+ // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
+ // .. .. .. FINISH: REMOVE PLL BY PASS
+ // .. .. .. DDR_3XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. .. DDR_2XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. .. .. DDR_3XCLK_DIVISOR = 0x2
+ // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
+ // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U
+ // .. .. .. DDR_2XCLK_DIVISOR = 0x3
+ // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
+ // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
+ // .. .. FINISH: DDR PLL INIT
+ // .. .. START: IO PLL INIT
+ // .. .. PLL_RES = 0xc
+ // .. .. ==> 0XF8000118[7:4] = 0x0000000CU
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U
+ // .. .. PLL_CP = 0x2
+ // .. .. ==> 0XF8000118[11:8] = 0x00000002U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
+ // .. .. LOCK_CNT = 0x145
+ // .. .. ==> 0XF8000118[21:12] = 0x00000145U
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U),
+ // .. .. .. START: UPDATE FB_DIV
+ // .. .. .. PLL_FDIV = 0x1e
+ // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU
+ // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U),
+ // .. .. .. FINISH: UPDATE FB_DIV
+ // .. .. .. START: BY PASS PLL
+ // .. .. .. PLL_BYPASS_FORCE = 1
+ // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
+ // .. .. .. FINISH: BY PASS PLL
+ // .. .. .. START: ASSERT RESET
+ // .. .. .. PLL_RESET = 1
+ // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
+ // .. .. .. FINISH: ASSERT RESET
+ // .. .. .. START: DEASSERT RESET
+ // .. .. .. PLL_RESET = 0
+ // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
+ // .. .. .. FINISH: DEASSERT RESET
+ // .. .. .. START: CHECK PLL STATUS
+ // .. .. .. IO_PLL_LOCK = 1
+ // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. .. ..
+ EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+ // .. .. .. FINISH: CHECK PLL STATUS
+ // .. .. .. START: REMOVE PLL BY PASS
+ // .. .. .. PLL_BYPASS_FORCE = 0
+ // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
+ // .. .. .. FINISH: REMOVE PLL BY PASS
+ // .. .. FINISH: IO PLL INIT
+ // .. FINISH: PLL SLCR REGISTERS
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_clock_init_data_3_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: CLOCK CONTROL SLCR REGISTERS
+ // .. CLKACT = 0x1
+ // .. ==> 0XF8000128[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. DIVISOR0 = 0x23
+ // .. ==> 0XF8000128[13:8] = 0x00000023U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00002300U
+ // .. DIVISOR1 = 0x3
+ // .. ==> 0XF8000128[25:20] = 0x00000003U
+ // .. ==> MASK : 0x03F00000U VAL : 0x00300000U
+ // ..
+ EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U),
+ // .. CLKACT = 0x1
+ // .. ==> 0XF8000138[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000138[4:4] = 0x00000000U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
+ // .. CLKACT = 0x1
+ // .. ==> 0XF8000140[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000140[6:4] = 0x00000000U
+ // .. ==> MASK : 0x00000070U VAL : 0x00000000U
+ // .. DIVISOR = 0x8
+ // .. ==> 0XF8000140[13:8] = 0x00000008U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00000800U
+ // .. DIVISOR1 = 0x1
+ // .. ==> 0XF8000140[25:20] = 0x00000001U
+ // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
+ // ..
+ EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U),
+ // .. CLKACT = 0x1
+ // .. ==> 0XF800014C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF800014C[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR = 0x5
+ // .. ==> 0XF800014C[13:8] = 0x00000005U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00000500U
+ // ..
+ EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
+ // .. CLKACT0 = 0x1
+ // .. ==> 0XF8000150[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. CLKACT1 = 0x0
+ // .. ==> 0XF8000150[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000150[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR = 0x14
+ // .. ==> 0XF8000150[13:8] = 0x00000014U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
+ // ..
+ EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U),
+ // .. CLKACT0 = 0x0
+ // .. ==> 0XF8000154[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. CLKACT1 = 0x1
+ // .. ==> 0XF8000154[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000154[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR = 0x14
+ // .. ==> 0XF8000154[13:8] = 0x00000014U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
+ // ..
+ EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U),
+ // .. CLKACT = 0x1
+ // .. ==> 0XF8000168[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000168[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR = 0x5
+ // .. ==> 0XF8000168[13:8] = 0x00000005U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00000500U
+ // ..
+ EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000170[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR0 = 0xa
+ // .. ==> 0XF8000170[13:8] = 0x0000000AU
+ // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U
+ // .. DIVISOR1 = 0x1
+ // .. ==> 0XF8000170[25:20] = 0x00000001U
+ // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
+ // ..
+ EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00100A00U),
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000180[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR0 = 0x7
+ // .. ==> 0XF8000180[13:8] = 0x00000007U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00000700U
+ // .. DIVISOR1 = 0x1
+ // .. ==> 0XF8000180[25:20] = 0x00000001U
+ // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
+ // ..
+ EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00100700U),
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000190[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR0 = 0x14
+ // .. ==> 0XF8000190[13:8] = 0x00000014U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
+ // .. DIVISOR1 = 0x1
+ // .. ==> 0XF8000190[25:20] = 0x00000001U
+ // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
+ // ..
+ EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101400U),
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF80001A0[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR0 = 0x14
+ // .. ==> 0XF80001A0[13:8] = 0x00000014U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
+ // .. DIVISOR1 = 0x1
+ // .. ==> 0XF80001A0[25:20] = 0x00000001U
+ // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
+ // ..
+ EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U),
+ // .. CLK_621_TRUE = 0x1
+ // .. ==> 0XF80001C4[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // ..
+ EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
+ // .. DMA_CPU_2XCLKACT = 0x1
+ // .. ==> 0XF800012C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. USB0_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. USB1_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[3:3] = 0x00000001U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000008U
+ // .. GEM0_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[6:6] = 0x00000001U
+ // .. ==> MASK : 0x00000040U VAL : 0x00000040U
+ // .. GEM1_CPU_1XCLKACT = 0x0
+ // .. ==> 0XF800012C[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. SDI0_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[10:10] = 0x00000001U
+ // .. ==> MASK : 0x00000400U VAL : 0x00000400U
+ // .. SDI1_CPU_1XCLKACT = 0x0
+ // .. ==> 0XF800012C[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. SPI0_CPU_1XCLKACT = 0x0
+ // .. ==> 0XF800012C[14:14] = 0x00000000U
+ // .. ==> MASK : 0x00004000U VAL : 0x00000000U
+ // .. SPI1_CPU_1XCLKACT = 0x0
+ // .. ==> 0XF800012C[15:15] = 0x00000000U
+ // .. ==> MASK : 0x00008000U VAL : 0x00000000U
+ // .. CAN0_CPU_1XCLKACT = 0x0
+ // .. ==> 0XF800012C[16:16] = 0x00000000U
+ // .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. CAN1_CPU_1XCLKACT = 0x0
+ // .. ==> 0XF800012C[17:17] = 0x00000000U
+ // .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. I2C0_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[18:18] = 0x00000001U
+ // .. ==> MASK : 0x00040000U VAL : 0x00040000U
+ // .. I2C1_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[19:19] = 0x00000001U
+ // .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // .. UART0_CPU_1XCLKACT = 0x0
+ // .. ==> 0XF800012C[20:20] = 0x00000000U
+ // .. ==> MASK : 0x00100000U VAL : 0x00000000U
+ // .. UART1_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[21:21] = 0x00000001U
+ // .. ==> MASK : 0x00200000U VAL : 0x00200000U
+ // .. GPIO_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[22:22] = 0x00000001U
+ // .. ==> MASK : 0x00400000U VAL : 0x00400000U
+ // .. LQSPI_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[23:23] = 0x00000001U
+ // .. ==> MASK : 0x00800000U VAL : 0x00800000U
+ // .. SMC_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[24:24] = 0x00000001U
+ // .. ==> MASK : 0x01000000U VAL : 0x01000000U
+ // ..
+ EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC044DU),
+ // .. FINISH: CLOCK CONTROL SLCR REGISTERS
+ // .. START: THIS SHOULD BE BLANK
+ // .. FINISH: THIS SHOULD BE BLANK
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_ddr_init_data_3_0[] = {
+ // START: top
+ // .. START: DDR INITIALIZATION
+ // .. .. START: LOCK DDR
+ // .. .. reg_ddrc_soft_rstb = 0
+ // .. .. ==> 0XF8006000[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_powerdown_en = 0x0
+ // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_ddrc_data_bus_width = 0x0
+ // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U
+ // .. .. reg_ddrc_burst8_refresh = 0x0
+ // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U
+ // .. .. reg_ddrc_rdwr_idle_gap = 0x1
+ // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+ // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U
+ // .. .. reg_ddrc_dis_rd_bypass = 0x0
+ // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+ // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_act_bypass = 0x0
+ // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_auto_refresh = 0x0
+ // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
+ // .. .. FINISH: LOCK DDR
+ // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81
+ // .. .. ==> 0XF8006004[11:0] = 0x00000081U
+ // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U
+ // .. .. reserved_reg_ddrc_active_ranks = 0x1
+ // .. .. ==> 0XF8006004[13:12] = 0x00000001U
+ // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U
+ // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
+ // .. .. ==> 0XF8006004[18:14] = 0x00000000U
+ // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU ,0x00001081U),
+ // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
+ // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU
+ // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
+ // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
+ // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U
+ // .. .. reg_ddrc_hpr_xact_run_length = 0xf
+ // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
+ // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
+ // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
+ // .. .. ==> 0XF800600C[10:0] = 0x00000001U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U
+ // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
+ // .. .. ==> 0XF800600C[21:11] = 0x00000002U
+ // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U
+ // .. .. reg_ddrc_lpr_xact_run_length = 0x8
+ // .. .. ==> 0XF800600C[25:22] = 0x00000008U
+ // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
+ // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
+ // .. .. ==> 0XF8006010[10:0] = 0x00000001U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U
+ // .. .. reg_ddrc_w_xact_run_length = 0x8
+ // .. .. ==> 0XF8006010[14:11] = 0x00000008U
+ // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U
+ // .. .. reg_ddrc_w_max_starve_x32 = 0x2
+ // .. .. ==> 0XF8006010[25:15] = 0x00000002U
+ // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
+ // .. .. reg_ddrc_t_rc = 0x1b
+ // .. .. ==> 0XF8006014[5:0] = 0x0000001BU
+ // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001BU
+ // .. .. reg_ddrc_t_rfc_min = 0x56
+ // .. .. ==> 0XF8006014[13:6] = 0x00000056U
+ // .. .. ==> MASK : 0x00003FC0U VAL : 0x00001580U
+ // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
+ // .. .. ==> 0XF8006014[20:14] = 0x00000010U
+ // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004159BU),
+ // .. .. reg_ddrc_wr2pre = 0x12
+ // .. .. ==> 0XF8006018[4:0] = 0x00000012U
+ // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U
+ // .. .. reg_ddrc_powerdown_to_x32 = 0x6
+ // .. .. ==> 0XF8006018[9:5] = 0x00000006U
+ // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U
+ // .. .. reg_ddrc_t_faw = 0x18
+ // .. .. ==> 0XF8006018[15:10] = 0x00000018U
+ // .. .. ==> MASK : 0x0000FC00U VAL : 0x00006000U
+ // .. .. reg_ddrc_t_ras_max = 0x24
+ // .. .. ==> 0XF8006018[21:16] = 0x00000024U
+ // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U
+ // .. .. reg_ddrc_t_ras_min = 0x14
+ // .. .. ==> 0XF8006018[26:22] = 0x00000014U
+ // .. .. ==> MASK : 0x07C00000U VAL : 0x05000000U
+ // .. .. reg_ddrc_t_cke = 0x4
+ // .. .. ==> 0XF8006018[31:28] = 0x00000004U
+ // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x452460D2U),
+ // .. .. reg_ddrc_write_latency = 0x5
+ // .. .. ==> 0XF800601C[4:0] = 0x00000005U
+ // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U
+ // .. .. reg_ddrc_rd2wr = 0x7
+ // .. .. ==> 0XF800601C[9:5] = 0x00000007U
+ // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U
+ // .. .. reg_ddrc_wr2rd = 0xe
+ // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
+ // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U
+ // .. .. reg_ddrc_t_xp = 0x4
+ // .. .. ==> 0XF800601C[19:15] = 0x00000004U
+ // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U
+ // .. .. reg_ddrc_pad_pd = 0x0
+ // .. .. ==> 0XF800601C[22:20] = 0x00000000U
+ // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U
+ // .. .. reg_ddrc_rd2pre = 0x4
+ // .. .. ==> 0XF800601C[27:23] = 0x00000004U
+ // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U
+ // .. .. reg_ddrc_t_rcd = 0x7
+ // .. .. ==> 0XF800601C[31:28] = 0x00000007U
+ // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
+ // .. .. reg_ddrc_t_ccd = 0x4
+ // .. .. ==> 0XF8006020[4:2] = 0x00000004U
+ // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U
+ // .. .. reg_ddrc_t_rrd = 0x6
+ // .. .. ==> 0XF8006020[7:5] = 0x00000006U
+ // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U
+ // .. .. reg_ddrc_refresh_margin = 0x2
+ // .. .. ==> 0XF8006020[11:8] = 0x00000002U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
+ // .. .. reg_ddrc_t_rp = 0x7
+ // .. .. ==> 0XF8006020[15:12] = 0x00000007U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U
+ // .. .. reg_ddrc_refresh_to_x32 = 0x8
+ // .. .. ==> 0XF8006020[20:16] = 0x00000008U
+ // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U
+ // .. .. reg_ddrc_mobile = 0x0
+ // .. .. ==> 0XF8006020[22:22] = 0x00000000U
+ // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U
+ // .. .. reg_ddrc_en_dfi_dram_clk_disable = 0x0
+ // .. .. ==> 0XF8006020[23:23] = 0x00000000U
+ // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U
+ // .. .. reg_ddrc_read_latency = 0x7
+ // .. .. ==> 0XF8006020[28:24] = 0x00000007U
+ // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U
+ // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
+ // .. .. ==> 0XF8006020[29:29] = 0x00000001U
+ // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U
+ // .. .. reg_ddrc_dis_pad_pd = 0x0
+ // .. .. ==> 0XF8006020[30:30] = 0x00000000U
+ // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU ,0x270872D0U),
+ // .. .. reg_ddrc_en_2t_timing_mode = 0x0
+ // .. .. ==> 0XF8006024[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_prefer_write = 0x0
+ // .. .. ==> 0XF8006024[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr_wr = 0x0
+ // .. .. ==> 0XF8006024[6:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr_addr = 0x0
+ // .. .. ==> 0XF8006024[8:7] = 0x00000000U
+ // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr_data = 0x0
+ // .. .. ==> 0XF8006024[24:9] = 0x00000000U
+ // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U
+ // .. .. ddrc_reg_mr_wr_busy = 0x0
+ // .. .. ==> 0XF8006024[25:25] = 0x00000000U
+ // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr_type = 0x0
+ // .. .. ==> 0XF8006024[26:26] = 0x00000000U
+ // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr_rdata_valid = 0x0
+ // .. .. ==> 0XF8006024[27:27] = 0x00000000U
+ // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U ,0x00000000U),
+ // .. .. reg_ddrc_final_wait_x32 = 0x7
+ // .. .. ==> 0XF8006028[6:0] = 0x00000007U
+ // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U
+ // .. .. reg_ddrc_pre_ocd_x32 = 0x0
+ // .. .. ==> 0XF8006028[10:7] = 0x00000000U
+ // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U
+ // .. .. reg_ddrc_t_mrd = 0x4
+ // .. .. ==> 0XF8006028[13:11] = 0x00000004U
+ // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
+ // .. .. reg_ddrc_emr2 = 0x8
+ // .. .. ==> 0XF800602C[15:0] = 0x00000008U
+ // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U
+ // .. .. reg_ddrc_emr3 = 0x0
+ // .. .. ==> 0XF800602C[31:16] = 0x00000000U
+ // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
+ // .. .. reg_ddrc_mr = 0x930
+ // .. .. ==> 0XF8006030[15:0] = 0x00000930U
+ // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U
+ // .. .. reg_ddrc_emr = 0x4
+ // .. .. ==> 0XF8006030[31:16] = 0x00000004U
+ // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
+ // .. .. reg_ddrc_burst_rdwr = 0x4
+ // .. .. ==> 0XF8006034[3:0] = 0x00000004U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U
+ // .. .. reg_ddrc_pre_cke_x1024 = 0x105
+ // .. .. ==> 0XF8006034[13:4] = 0x00000105U
+ // .. .. ==> MASK : 0x00003FF0U VAL : 0x00001050U
+ // .. .. reg_ddrc_post_cke_x1024 = 0x1
+ // .. .. ==> 0XF8006034[25:16] = 0x00000001U
+ // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U
+ // .. .. reg_ddrc_burstchop = 0x0
+ // .. .. ==> 0XF8006034[28:28] = 0x00000000U
+ // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U),
+ // .. .. reg_ddrc_force_low_pri_n = 0x0
+ // .. .. ==> 0XF8006038[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_dq = 0x0
+ // .. .. ==> 0XF8006038[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006038, 0x00000003U ,0x00000000U),
+ // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
+ // .. .. ==> 0XF800603C[3:0] = 0x00000007U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U
+ // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
+ // .. .. ==> 0XF800603C[7:4] = 0x00000007U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U
+ // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
+ // .. .. ==> 0XF800603C[11:8] = 0x00000007U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U
+ // .. .. reg_ddrc_addrmap_col_b5 = 0x0
+ // .. .. ==> 0XF800603C[15:12] = 0x00000000U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b6 = 0x0
+ // .. .. ==> 0XF800603C[19:16] = 0x00000000U
+ // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
+ // .. .. reg_ddrc_addrmap_col_b2 = 0x0
+ // .. .. ==> 0XF8006040[3:0] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b3 = 0x0
+ // .. .. ==> 0XF8006040[7:4] = 0x00000000U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b4 = 0x0
+ // .. .. ==> 0XF8006040[11:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b7 = 0x0
+ // .. .. ==> 0XF8006040[15:12] = 0x00000000U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b8 = 0x0
+ // .. .. ==> 0XF8006040[19:16] = 0x00000000U
+ // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b9 = 0xf
+ // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
+ // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U
+ // .. .. reg_ddrc_addrmap_col_b10 = 0xf
+ // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
+ // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U
+ // .. .. reg_ddrc_addrmap_col_b11 = 0xf
+ // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
+ // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
+ // .. .. reg_ddrc_addrmap_row_b0 = 0x6
+ // .. .. ==> 0XF8006044[3:0] = 0x00000006U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U
+ // .. .. reg_ddrc_addrmap_row_b1 = 0x6
+ // .. .. ==> 0XF8006044[7:4] = 0x00000006U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U
+ // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
+ // .. .. ==> 0XF8006044[11:8] = 0x00000006U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U
+ // .. .. reg_ddrc_addrmap_row_b12 = 0x6
+ // .. .. ==> 0XF8006044[15:12] = 0x00000006U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U
+ // .. .. reg_ddrc_addrmap_row_b13 = 0x6
+ // .. .. ==> 0XF8006044[19:16] = 0x00000006U
+ // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U
+ // .. .. reg_ddrc_addrmap_row_b14 = 0xf
+ // .. .. ==> 0XF8006044[23:20] = 0x0000000FU
+ // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U
+ // .. .. reg_ddrc_addrmap_row_b15 = 0xf
+ // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
+ // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0FF66666U),
+ // .. .. reg_phy_rd_local_odt = 0x0
+ // .. .. ==> 0XF8006048[13:12] = 0x00000000U
+ // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U
+ // .. .. reg_phy_wr_local_odt = 0x3
+ // .. .. ==> 0XF8006048[15:14] = 0x00000003U
+ // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U
+ // .. .. reg_phy_idle_local_odt = 0x3
+ // .. .. ==> 0XF8006048[17:16] = 0x00000003U
+ // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006048, 0x0003F000U ,0x0003C000U),
+ // .. .. reg_phy_rd_cmd_to_data = 0x0
+ // .. .. ==> 0XF8006050[3:0] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
+ // .. .. reg_phy_wr_cmd_to_data = 0x0
+ // .. .. ==> 0XF8006050[7:4] = 0x00000000U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. .. reg_phy_rdc_we_to_re_delay = 0x8
+ // .. .. ==> 0XF8006050[11:8] = 0x00000008U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U
+ // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
+ // .. .. ==> 0XF8006050[15:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
+ // .. .. reg_phy_use_fixed_re = 0x1
+ // .. .. ==> 0XF8006050[16:16] = 0x00000001U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U
+ // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
+ // .. .. ==> 0XF8006050[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
+ // .. .. ==> 0XF8006050[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_phy_clk_stall_level = 0x0
+ // .. .. ==> 0XF8006050[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
+ // .. .. ==> 0XF8006050[27:24] = 0x00000007U
+ // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U
+ // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
+ // .. .. ==> 0XF8006050[31:28] = 0x00000007U
+ // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
+ // .. .. reg_ddrc_dis_dll_calib = 0x0
+ // .. .. ==> 0XF8006058[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006058, 0x00010000U ,0x00000000U),
+ // .. .. reg_ddrc_rd_odt_delay = 0x3
+ // .. .. ==> 0XF800605C[3:0] = 0x00000003U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U
+ // .. .. reg_ddrc_wr_odt_delay = 0x0
+ // .. .. ==> 0XF800605C[7:4] = 0x00000000U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. .. reg_ddrc_rd_odt_hold = 0x0
+ // .. .. ==> 0XF800605C[11:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U
+ // .. .. reg_ddrc_wr_odt_hold = 0x5
+ // .. .. ==> 0XF800605C[15:12] = 0x00000005U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
+ // .. .. reg_ddrc_pageclose = 0x0
+ // .. .. ==> 0XF8006060[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_lpr_num_entries = 0x1f
+ // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
+ // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU
+ // .. .. reg_ddrc_auto_pre_en = 0x0
+ // .. .. ==> 0XF8006060[7:7] = 0x00000000U
+ // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. .. reg_ddrc_refresh_update_level = 0x0
+ // .. .. ==> 0XF8006060[8:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_wc = 0x0
+ // .. .. ==> 0XF8006060[9:9] = 0x00000000U
+ // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_collision_page_opt = 0x0
+ // .. .. ==> 0XF8006060[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_ddrc_selfref_en = 0x0
+ // .. .. ==> 0XF8006060[12:12] = 0x00000000U
+ // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
+ // .. .. reg_ddrc_go2critical_hysteresis = 0x0
+ // .. .. ==> 0XF8006064[12:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U
+ // .. .. reg_arb_go2critical_en = 0x1
+ // .. .. ==> 0XF8006064[17:17] = 0x00000001U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
+ // .. .. reg_ddrc_wrlvl_ww = 0x41
+ // .. .. ==> 0XF8006068[7:0] = 0x00000041U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U
+ // .. .. reg_ddrc_rdlvl_rr = 0x41
+ // .. .. ==> 0XF8006068[15:8] = 0x00000041U
+ // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U
+ // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
+ // .. .. ==> 0XF8006068[25:16] = 0x00000028U
+ // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
+ // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
+ // .. .. ==> 0XF800606C[7:0] = 0x00000010U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U
+ // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
+ // .. .. ==> 0XF800606C[15:8] = 0x00000016U
+ // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U
+ // .. ..
+ EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
+ // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1
+ // .. .. ==> 0XF8006078[3:0] = 0x00000001U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U
+ // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1
+ // .. .. ==> 0XF8006078[7:4] = 0x00000001U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U
+ // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1
+ // .. .. ==> 0XF8006078[11:8] = 0x00000001U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U
+ // .. .. reg_ddrc_t_cksre = 0x6
+ // .. .. ==> 0XF8006078[15:12] = 0x00000006U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U
+ // .. .. reg_ddrc_t_cksrx = 0x6
+ // .. .. ==> 0XF8006078[19:16] = 0x00000006U
+ // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U
+ // .. .. reg_ddrc_t_ckesr = 0x4
+ // .. .. ==> 0XF8006078[25:20] = 0x00000004U
+ // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U),
+ // .. .. reg_ddrc_t_ckpde = 0x2
+ // .. .. ==> 0XF800607C[3:0] = 0x00000002U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U
+ // .. .. reg_ddrc_t_ckpdx = 0x2
+ // .. .. ==> 0XF800607C[7:4] = 0x00000002U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
+ // .. .. reg_ddrc_t_ckdpde = 0x2
+ // .. .. ==> 0XF800607C[11:8] = 0x00000002U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
+ // .. .. reg_ddrc_t_ckdpdx = 0x2
+ // .. .. ==> 0XF800607C[15:12] = 0x00000002U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U
+ // .. .. reg_ddrc_t_ckcsx = 0x3
+ // .. .. ==> 0XF800607C[19:16] = 0x00000003U
+ // .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U),
+ // .. .. reg_ddrc_dis_auto_zq = 0x0
+ // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_ddr3 = 0x1
+ // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. .. reg_ddrc_t_mod = 0x200
+ // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
+ // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U
+ // .. .. reg_ddrc_t_zq_long_nop = 0x200
+ // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U
+ // .. .. reg_ddrc_t_zq_short_nop = 0x40
+ // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
+ // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
+ // .. .. t_zq_short_interval_x1024 = 0xcb73
+ // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U
+ // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U
+ // .. .. dram_rstn_x1024 = 0x69
+ // .. .. ==> 0XF80060A8[27:20] = 0x00000069U
+ // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
+ // .. .. deeppowerdown_en = 0x0
+ // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. deeppowerdown_to_x1024 = 0xff
+ // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
+ // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU
+ // .. ..
+ EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
+ // .. .. dfi_wrlvl_max_x1024 = 0xfff
+ // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
+ // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU
+ // .. .. dfi_rdlvl_max_x1024 = 0xfff
+ // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
+ // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U
+ // .. .. ddrc_reg_twrlvl_max_error = 0x0
+ // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
+ // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U
+ // .. .. ddrc_reg_trdlvl_max_error = 0x0
+ // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
+ // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dfi_wr_level_en = 0x1
+ // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
+ // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U
+ // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
+ // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
+ // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U
+ // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
+ // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
+ // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
+ // .. .. reg_ddrc_skip_ocd = 0x1
+ // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
+ // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060B4, 0x00000200U ,0x00000200U),
+ // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
+ // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
+ // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U
+ // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
+ // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
+ // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U
+ // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
+ // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
+ // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
+ // .. .. START: RESET ECC ERROR
+ // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1
+ // .. .. ==> 0XF80060C4[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. Clear_Correctable_DRAM_ECC_error = 1
+ // .. .. ==> 0XF80060C4[1:1] = 0x00000001U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U),
+ // .. .. FINISH: RESET ECC ERROR
+ // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
+ // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
+ // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
+ // .. .. CORR_ECC_LOG_VALID = 0x0
+ // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. ECC_CORRECTED_BIT_NUM = 0x0
+ // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
+ // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
+ // .. .. UNCORR_ECC_LOG_VALID = 0x0
+ // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
+ // .. .. STAT_NUM_CORR_ERR = 0x0
+ // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
+ // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U
+ // .. .. STAT_NUM_UNCORR_ERR = 0x0
+ // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
+ // .. .. reg_ddrc_ecc_mode = 0x0
+ // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_scrub = 0x1
+ // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
+ // .. .. reg_phy_dif_on = 0x0
+ // .. .. ==> 0XF8006114[3:0] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
+ // .. .. reg_phy_dif_off = 0x0
+ // .. .. ==> 0XF8006114[7:4] = 0x00000000U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
+ // .. .. reg_phy_data_slice_in_use = 0x1
+ // .. .. ==> 0XF8006118[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_phy_rdlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006118[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006118[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_wrlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006118[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_bist_shift_dq = 0x0
+ // .. .. ==> 0XF8006118[14:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
+ // .. .. reg_phy_bist_err_clr = 0x0
+ // .. .. ==> 0XF8006118[23:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
+ // .. .. reg_phy_dq_offset = 0x40
+ // .. .. ==> 0XF8006118[30:24] = 0x00000040U
+ // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU ,0x40000001U),
+ // .. .. reg_phy_data_slice_in_use = 0x1
+ // .. .. ==> 0XF800611C[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_phy_rdlvl_inc_mode = 0x0
+ // .. .. ==> 0XF800611C[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_inc_mode = 0x0
+ // .. .. ==> 0XF800611C[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_wrlvl_inc_mode = 0x0
+ // .. .. ==> 0XF800611C[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_bist_shift_dq = 0x0
+ // .. .. ==> 0XF800611C[14:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
+ // .. .. reg_phy_bist_err_clr = 0x0
+ // .. .. ==> 0XF800611C[23:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
+ // .. .. reg_phy_dq_offset = 0x40
+ // .. .. ==> 0XF800611C[30:24] = 0x00000040U
+ // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU ,0x40000001U),
+ // .. .. reg_phy_data_slice_in_use = 0x1
+ // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_phy_rdlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_wrlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_bist_shift_dq = 0x0
+ // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
+ // .. .. reg_phy_bist_err_clr = 0x0
+ // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
+ // .. .. reg_phy_dq_offset = 0x40
+ // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+ // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU ,0x40000001U),
+ // .. .. reg_phy_data_slice_in_use = 0x1
+ // .. .. ==> 0XF8006124[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_phy_rdlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006124[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006124[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_wrlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006124[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_bist_shift_dq = 0x0
+ // .. .. ==> 0XF8006124[14:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
+ // .. .. reg_phy_bist_err_clr = 0x0
+ // .. .. ==> 0XF8006124[23:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
+ // .. .. reg_phy_dq_offset = 0x40
+ // .. .. ==> 0XF8006124[30:24] = 0x00000040U
+ // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU ,0x40000001U),
+ // .. .. reg_phy_wrlvl_init_ratio = 0x3
+ // .. .. ==> 0XF800612C[9:0] = 0x00000003U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000003U
+ // .. .. reg_phy_gatelvl_init_ratio = 0xcf
+ // .. .. ==> 0XF800612C[19:10] = 0x000000CFU
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x00033C00U
+ // .. ..
+ EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00033C03U),
+ // .. .. reg_phy_wrlvl_init_ratio = 0x3
+ // .. .. ==> 0XF8006130[9:0] = 0x00000003U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000003U
+ // .. .. reg_phy_gatelvl_init_ratio = 0xd0
+ // .. .. ==> 0XF8006130[19:10] = 0x000000D0U
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x00034000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00034003U),
+ // .. .. reg_phy_wrlvl_init_ratio = 0x0
+ // .. .. ==> 0XF8006134[9:0] = 0x00000000U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_init_ratio = 0xbd
+ // .. .. ==> 0XF8006134[19:10] = 0x000000BDU
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002F400U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0002F400U),
+ // .. .. reg_phy_wrlvl_init_ratio = 0x0
+ // .. .. ==> 0XF8006138[9:0] = 0x00000000U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_init_ratio = 0xc1
+ // .. .. ==> 0XF8006138[19:10] = 0x000000C1U
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x00030400U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x00030400U),
+ // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+ // .. .. ==> 0XF8006140[9:0] = 0x00000035U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
+ // .. .. reg_phy_rd_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006140[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006140[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
+ // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+ // .. .. ==> 0XF8006144[9:0] = 0x00000035U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
+ // .. .. reg_phy_rd_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006144[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006144[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
+ // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+ // .. .. ==> 0XF8006148[9:0] = 0x00000035U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
+ // .. .. reg_phy_rd_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006148[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006148[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
+ // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+ // .. .. ==> 0XF800614C[9:0] = 0x00000035U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
+ // .. .. reg_phy_rd_dqs_slave_force = 0x0
+ // .. .. ==> 0XF800614C[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF800614C[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
+ // .. .. reg_phy_wr_dqs_slave_ratio = 0x83
+ // .. .. ==> 0XF8006154[9:0] = 0x00000083U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000083U
+ // .. .. reg_phy_wr_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006154[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006154[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000083U),
+ // .. .. reg_phy_wr_dqs_slave_ratio = 0x83
+ // .. .. ==> 0XF8006158[9:0] = 0x00000083U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000083U
+ // .. .. reg_phy_wr_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006158[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006158[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000083U),
+ // .. .. reg_phy_wr_dqs_slave_ratio = 0x7f
+ // .. .. ==> 0XF800615C[9:0] = 0x0000007FU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x0000007FU
+ // .. .. reg_phy_wr_dqs_slave_force = 0x0
+ // .. .. ==> 0XF800615C[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF800615C[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x0000007FU),
+ // .. .. reg_phy_wr_dqs_slave_ratio = 0x78
+ // .. .. ==> 0XF8006160[9:0] = 0x00000078U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000078U
+ // .. .. reg_phy_wr_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006160[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006160[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000078U),
+ // .. .. reg_phy_fifo_we_slave_ratio = 0x124
+ // .. .. ==> 0XF8006168[10:0] = 0x00000124U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000124U
+ // .. .. reg_phy_fifo_we_in_force = 0x0
+ // .. .. ==> 0XF8006168[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. reg_phy_fifo_we_in_delay = 0x0
+ // .. .. ==> 0XF8006168[20:12] = 0x00000000U
+ // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000124U),
+ // .. .. reg_phy_fifo_we_slave_ratio = 0x125
+ // .. .. ==> 0XF800616C[10:0] = 0x00000125U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000125U
+ // .. .. reg_phy_fifo_we_in_force = 0x0
+ // .. .. ==> 0XF800616C[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. reg_phy_fifo_we_in_delay = 0x0
+ // .. .. ==> 0XF800616C[20:12] = 0x00000000U
+ // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x00000125U),
+ // .. .. reg_phy_fifo_we_slave_ratio = 0x112
+ // .. .. ==> 0XF8006170[10:0] = 0x00000112U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000112U
+ // .. .. reg_phy_fifo_we_in_force = 0x0
+ // .. .. ==> 0XF8006170[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. reg_phy_fifo_we_in_delay = 0x0
+ // .. .. ==> 0XF8006170[20:12] = 0x00000000U
+ // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000112U),
+ // .. .. reg_phy_fifo_we_slave_ratio = 0x116
+ // .. .. ==> 0XF8006174[10:0] = 0x00000116U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000116U
+ // .. .. reg_phy_fifo_we_in_force = 0x0
+ // .. .. ==> 0XF8006174[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. reg_phy_fifo_we_in_delay = 0x0
+ // .. .. ==> 0XF8006174[20:12] = 0x00000000U
+ // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000116U),
+ // .. .. reg_phy_wr_data_slave_ratio = 0xc3
+ // .. .. ==> 0XF800617C[9:0] = 0x000000C3U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C3U
+ // .. .. reg_phy_wr_data_slave_force = 0x0
+ // .. .. ==> 0XF800617C[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_data_slave_delay = 0x0
+ // .. .. ==> 0XF800617C[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000C3U),
+ // .. .. reg_phy_wr_data_slave_ratio = 0xc3
+ // .. .. ==> 0XF8006180[9:0] = 0x000000C3U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C3U
+ // .. .. reg_phy_wr_data_slave_force = 0x0
+ // .. .. ==> 0XF8006180[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_data_slave_delay = 0x0
+ // .. .. ==> 0XF8006180[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000C3U),
+ // .. .. reg_phy_wr_data_slave_ratio = 0xbf
+ // .. .. ==> 0XF8006184[9:0] = 0x000000BFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000BFU
+ // .. .. reg_phy_wr_data_slave_force = 0x0
+ // .. .. ==> 0XF8006184[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_data_slave_delay = 0x0
+ // .. .. ==> 0XF8006184[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000BFU),
+ // .. .. reg_phy_wr_data_slave_ratio = 0xb8
+ // .. .. ==> 0XF8006188[9:0] = 0x000000B8U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000B8U
+ // .. .. reg_phy_wr_data_slave_force = 0x0
+ // .. .. ==> 0XF8006188[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_data_slave_delay = 0x0
+ // .. .. ==> 0XF8006188[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000B8U),
+ // .. .. reg_phy_bl2 = 0x0
+ // .. .. ==> 0XF8006190[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_at_spd_atpg = 0x0
+ // .. .. ==> 0XF8006190[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_bist_enable = 0x0
+ // .. .. ==> 0XF8006190[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_bist_force_err = 0x0
+ // .. .. ==> 0XF8006190[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reg_phy_bist_mode = 0x0
+ // .. .. ==> 0XF8006190[6:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U
+ // .. .. reg_phy_invert_clkout = 0x1
+ // .. .. ==> 0XF8006190[7:7] = 0x00000001U
+ // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. .. reg_phy_sel_logic = 0x0
+ // .. .. ==> 0XF8006190[9:9] = 0x00000000U
+ // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U
+ // .. .. reg_phy_ctrl_slave_ratio = 0x100
+ // .. .. ==> 0XF8006190[19:10] = 0x00000100U
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U
+ // .. .. reg_phy_ctrl_slave_force = 0x0
+ // .. .. ==> 0XF8006190[20:20] = 0x00000000U
+ // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U
+ // .. .. reg_phy_ctrl_slave_delay = 0x0
+ // .. .. ==> 0XF8006190[27:21] = 0x00000000U
+ // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U
+ // .. .. reg_phy_lpddr = 0x0
+ // .. .. ==> 0XF8006190[29:29] = 0x00000000U
+ // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U
+ // .. .. reg_phy_cmd_latency = 0x0
+ // .. .. ==> 0XF8006190[30:30] = 0x00000000U
+ // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU ,0x00040080U),
+ // .. .. reg_phy_wr_rl_delay = 0x2
+ // .. .. ==> 0XF8006194[4:0] = 0x00000002U
+ // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U
+ // .. .. reg_phy_rd_rl_delay = 0x4
+ // .. .. ==> 0XF8006194[9:5] = 0x00000004U
+ // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U
+ // .. .. reg_phy_dll_lock_diff = 0xf
+ // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
+ // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U
+ // .. .. reg_phy_use_wr_level = 0x1
+ // .. .. ==> 0XF8006194[14:14] = 0x00000001U
+ // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U
+ // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
+ // .. .. ==> 0XF8006194[15:15] = 0x00000001U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U
+ // .. .. reg_phy_use_rd_data_eye_level = 0x1
+ // .. .. ==> 0XF8006194[16:16] = 0x00000001U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U
+ // .. .. reg_phy_dis_calib_rst = 0x0
+ // .. .. ==> 0XF8006194[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_phy_ctrl_slave_delay = 0x0
+ // .. .. ==> 0XF8006194[19:18] = 0x00000000U
+ // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
+ // .. .. reg_arb_page_addr_mask = 0x0
+ // .. .. ==> 0XF8006204[31:0] = 0x00000000U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
+ // .. .. reg_arb_pri_wr_portn = 0x3ff
+ // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_wr_portn = 0x0
+ // .. .. ==> 0XF8006208[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+ // .. .. ==> 0XF8006208[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+ // .. .. ==> 0XF8006208[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006208, 0x000703FFU ,0x000003FFU),
+ // .. .. reg_arb_pri_wr_portn = 0x3ff
+ // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_wr_portn = 0x0
+ // .. .. ==> 0XF800620C[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+ // .. .. ==> 0XF800620C[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+ // .. .. ==> 0XF800620C[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800620C, 0x000703FFU ,0x000003FFU),
+ // .. .. reg_arb_pri_wr_portn = 0x3ff
+ // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_wr_portn = 0x0
+ // .. .. ==> 0XF8006210[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+ // .. .. ==> 0XF8006210[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+ // .. .. ==> 0XF8006210[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006210, 0x000703FFU ,0x000003FFU),
+ // .. .. reg_arb_pri_wr_portn = 0x3ff
+ // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_wr_portn = 0x0
+ // .. .. ==> 0XF8006214[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+ // .. .. ==> 0XF8006214[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+ // .. .. ==> 0XF8006214[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006214, 0x000703FFU ,0x000003FFU),
+ // .. .. reg_arb_pri_rd_portn = 0x3ff
+ // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_rd_portn = 0x0
+ // .. .. ==> 0XF8006218[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+ // .. .. ==> 0XF8006218[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+ // .. .. ==> 0XF8006218[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_set_hpr_rd_portn = 0x0
+ // .. .. ==> 0XF8006218[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
+ // .. .. reg_arb_pri_rd_portn = 0x3ff
+ // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_rd_portn = 0x0
+ // .. .. ==> 0XF800621C[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+ // .. .. ==> 0XF800621C[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+ // .. .. ==> 0XF800621C[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_set_hpr_rd_portn = 0x0
+ // .. .. ==> 0XF800621C[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
+ // .. .. reg_arb_pri_rd_portn = 0x3ff
+ // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_rd_portn = 0x0
+ // .. .. ==> 0XF8006220[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+ // .. .. ==> 0XF8006220[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+ // .. .. ==> 0XF8006220[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_set_hpr_rd_portn = 0x0
+ // .. .. ==> 0XF8006220[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
+ // .. .. reg_arb_pri_rd_portn = 0x3ff
+ // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_rd_portn = 0x0
+ // .. .. ==> 0XF8006224[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+ // .. .. ==> 0XF8006224[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+ // .. .. ==> 0XF8006224[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_set_hpr_rd_portn = 0x0
+ // .. .. ==> 0XF8006224[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
+ // .. .. reg_ddrc_lpddr2 = 0x0
+ // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_derate_enable = 0x0
+ // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr4_margin = 0x0
+ // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U ,0x00000000U),
+ // .. .. reg_ddrc_mr4_read_interval = 0x0
+ // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
+ // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
+ // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U
+ // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
+ // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
+ // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U
+ // .. .. reg_ddrc_t_mrw = 0x5
+ // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
+ // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8
+ // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U
+ // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
+ // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
+ // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U
+ // .. ..
+ EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
+ // .. .. START: POLL ON DCI STATUS
+ // .. .. DONE = 1
+ // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
+ // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U
+ // .. ..
+ EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+ // .. .. FINISH: POLL ON DCI STATUS
+ // .. .. START: UNLOCK DDR
+ // .. .. reg_ddrc_soft_rstb = 0x1
+ // .. .. ==> 0XF8006000[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_ddrc_powerdown_en = 0x0
+ // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_ddrc_data_bus_width = 0x0
+ // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U
+ // .. .. reg_ddrc_burst8_refresh = 0x0
+ // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U
+ // .. .. reg_ddrc_rdwr_idle_gap = 1
+ // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+ // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U
+ // .. .. reg_ddrc_dis_rd_bypass = 0x0
+ // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+ // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_act_bypass = 0x0
+ // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_auto_refresh = 0x0
+ // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
+ // .. .. FINISH: UNLOCK DDR
+ // .. .. START: CHECK DDR STATUS
+ // .. .. ddrc_reg_operating_mode = 1
+ // .. .. ==> 0XF8006054[2:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U
+ // .. ..
+ EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+ // .. .. FINISH: CHECK DDR STATUS
+ // .. FINISH: DDR INITIALIZATION
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_mio_init_data_3_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: OCM REMAPPING
+ // .. FINISH: OCM REMAPPING
+ // .. START: DDRIOB SETTINGS
+ // .. reserved_INP_POWER = 0x0
+ // .. ==> 0XF8000B40[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x0
+ // .. ==> 0XF8000B40[2:1] = 0x00000000U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000000U
+ // .. DCI_UPDATE_B = 0x0
+ // .. ==> 0XF8000B40[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x0
+ // .. ==> 0XF8000B40[4:4] = 0x00000000U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. DCI_TYPE = 0x0
+ // .. ==> 0XF8000B40[6:5] = 0x00000000U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000000U
+ // .. IBUF_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B40[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B40[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B40[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B40[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
+ // .. reserved_INP_POWER = 0x0
+ // .. ==> 0XF8000B44[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x0
+ // .. ==> 0XF8000B44[2:1] = 0x00000000U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000000U
+ // .. DCI_UPDATE_B = 0x0
+ // .. ==> 0XF8000B44[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x0
+ // .. ==> 0XF8000B44[4:4] = 0x00000000U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. DCI_TYPE = 0x0
+ // .. ==> 0XF8000B44[6:5] = 0x00000000U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000000U
+ // .. IBUF_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B44[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B44[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B44[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B44[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
+ // .. reserved_INP_POWER = 0x0
+ // .. ==> 0XF8000B48[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x1
+ // .. ==> 0XF8000B48[2:1] = 0x00000001U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000002U
+ // .. DCI_UPDATE_B = 0x0
+ // .. ==> 0XF8000B48[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x1
+ // .. ==> 0XF8000B48[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. DCI_TYPE = 0x3
+ // .. ==> 0XF8000B48[6:5] = 0x00000003U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000060U
+ // .. IBUF_DISABLE_MODE = 0
+ // .. ==> 0XF8000B48[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0
+ // .. ==> 0XF8000B48[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B48[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B48[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
+ // .. reserved_INP_POWER = 0x0
+ // .. ==> 0XF8000B4C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x1
+ // .. ==> 0XF8000B4C[2:1] = 0x00000001U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000002U
+ // .. DCI_UPDATE_B = 0x0
+ // .. ==> 0XF8000B4C[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x1
+ // .. ==> 0XF8000B4C[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. DCI_TYPE = 0x3
+ // .. ==> 0XF8000B4C[6:5] = 0x00000003U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000060U
+ // .. IBUF_DISABLE_MODE = 0
+ // .. ==> 0XF8000B4C[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0
+ // .. ==> 0XF8000B4C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B4C[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B4C[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
+ // .. reserved_INP_POWER = 0x0
+ // .. ==> 0XF8000B50[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x2
+ // .. ==> 0XF8000B50[2:1] = 0x00000002U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000004U
+ // .. DCI_UPDATE_B = 0x0
+ // .. ==> 0XF8000B50[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x1
+ // .. ==> 0XF8000B50[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. DCI_TYPE = 0x3
+ // .. ==> 0XF8000B50[6:5] = 0x00000003U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000060U
+ // .. IBUF_DISABLE_MODE = 0
+ // .. ==> 0XF8000B50[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0
+ // .. ==> 0XF8000B50[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B50[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B50[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
+ // .. reserved_INP_POWER = 0x0
+ // .. ==> 0XF8000B54[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x2
+ // .. ==> 0XF8000B54[2:1] = 0x00000002U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000004U
+ // .. DCI_UPDATE_B = 0x0
+ // .. ==> 0XF8000B54[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x1
+ // .. ==> 0XF8000B54[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. DCI_TYPE = 0x3
+ // .. ==> 0XF8000B54[6:5] = 0x00000003U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000060U
+ // .. IBUF_DISABLE_MODE = 0
+ // .. ==> 0XF8000B54[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0
+ // .. ==> 0XF8000B54[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B54[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B54[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
+ // .. reserved_INP_POWER = 0x0
+ // .. ==> 0XF8000B58[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x0
+ // .. ==> 0XF8000B58[2:1] = 0x00000000U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000000U
+ // .. DCI_UPDATE_B = 0x0
+ // .. ==> 0XF8000B58[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x0
+ // .. ==> 0XF8000B58[4:4] = 0x00000000U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. DCI_TYPE = 0x0
+ // .. ==> 0XF8000B58[6:5] = 0x00000000U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000000U
+ // .. IBUF_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B58[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B58[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B58[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B58[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
+ // .. reserved_DRIVE_P = 0x1c
+ // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
+ // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
+ // .. reserved_DRIVE_N = 0xc
+ // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
+ // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
+ // .. reserved_SLEW_P = 0x3
+ // .. ==> 0XF8000B5C[18:14] = 0x00000003U
+ // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U
+ // .. reserved_SLEW_N = 0x3
+ // .. ==> 0XF8000B5C[23:19] = 0x00000003U
+ // .. ==> MASK : 0x00F80000U VAL : 0x00180000U
+ // .. reserved_GTL = 0x0
+ // .. ==> 0XF8000B5C[26:24] = 0x00000000U
+ // .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. reserved_RTERM = 0x0
+ // .. ==> 0XF8000B5C[31:27] = 0x00000000U
+ // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
+ // .. reserved_DRIVE_P = 0x1c
+ // .. ==> 0XF8000B60[6:0] = 0x0000001CU
+ // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
+ // .. reserved_DRIVE_N = 0xc
+ // .. ==> 0XF8000B60[13:7] = 0x0000000CU
+ // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
+ // .. reserved_SLEW_P = 0x6
+ // .. ==> 0XF8000B60[18:14] = 0x00000006U
+ // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
+ // .. reserved_SLEW_N = 0x1f
+ // .. ==> 0XF8000B60[23:19] = 0x0000001FU
+ // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
+ // .. reserved_GTL = 0x0
+ // .. ==> 0XF8000B60[26:24] = 0x00000000U
+ // .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. reserved_RTERM = 0x0
+ // .. ==> 0XF8000B60[31:27] = 0x00000000U
+ // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
+ // .. reserved_DRIVE_P = 0x1c
+ // .. ==> 0XF8000B64[6:0] = 0x0000001CU
+ // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
+ // .. reserved_DRIVE_N = 0xc
+ // .. ==> 0XF8000B64[13:7] = 0x0000000CU
+ // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
+ // .. reserved_SLEW_P = 0x6
+ // .. ==> 0XF8000B64[18:14] = 0x00000006U
+ // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
+ // .. reserved_SLEW_N = 0x1f
+ // .. ==> 0XF8000B64[23:19] = 0x0000001FU
+ // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
+ // .. reserved_GTL = 0x0
+ // .. ==> 0XF8000B64[26:24] = 0x00000000U
+ // .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. reserved_RTERM = 0x0
+ // .. ==> 0XF8000B64[31:27] = 0x00000000U
+ // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
+ // .. reserved_DRIVE_P = 0x1c
+ // .. ==> 0XF8000B68[6:0] = 0x0000001CU
+ // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
+ // .. reserved_DRIVE_N = 0xc
+ // .. ==> 0XF8000B68[13:7] = 0x0000000CU
+ // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
+ // .. reserved_SLEW_P = 0x6
+ // .. ==> 0XF8000B68[18:14] = 0x00000006U
+ // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
+ // .. reserved_SLEW_N = 0x1f
+ // .. ==> 0XF8000B68[23:19] = 0x0000001FU
+ // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
+ // .. reserved_GTL = 0x0
+ // .. ==> 0XF8000B68[26:24] = 0x00000000U
+ // .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. reserved_RTERM = 0x0
+ // .. ==> 0XF8000B68[31:27] = 0x00000000U
+ // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
+ // .. VREF_INT_EN = 0x1
+ // .. ==> 0XF8000B6C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. VREF_SEL = 0x4
+ // .. ==> 0XF8000B6C[4:1] = 0x00000004U
+ // .. ==> MASK : 0x0000001EU VAL : 0x00000008U
+ // .. VREF_EXT_EN = 0x0
+ // .. ==> 0XF8000B6C[6:5] = 0x00000000U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000000U
+ // .. reserved_VREF_PULLUP_EN = 0x0
+ // .. ==> 0XF8000B6C[8:7] = 0x00000000U
+ // .. ==> MASK : 0x00000180U VAL : 0x00000000U
+ // .. REFIO_EN = 0x1
+ // .. ==> 0XF8000B6C[9:9] = 0x00000001U
+ // .. ==> MASK : 0x00000200U VAL : 0x00000200U
+ // .. reserved_REFIO_TEST = 0x3
+ // .. ==> 0XF8000B6C[11:10] = 0x00000003U
+ // .. ==> MASK : 0x00000C00U VAL : 0x00000C00U
+ // .. reserved_REFIO_PULLUP_EN = 0x0
+ // .. ==> 0XF8000B6C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. reserved_DRST_B_PULLUP_EN = 0x0
+ // .. ==> 0XF8000B6C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // .. reserved_CKE_PULLUP_EN = 0x0
+ // .. ==> 0XF8000B6C[14:14] = 0x00000000U
+ // .. ==> MASK : 0x00004000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000E09U),
+ // .. .. START: ASSERT RESET
+ // .. .. RESET = 1
+ // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000B70, 0x00000001U ,0x00000001U),
+ // .. .. FINISH: ASSERT RESET
+ // .. .. START: DEASSERT RESET
+ // .. .. RESET = 0
+ // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reserved_VRN_OUT = 0x1
+ // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
+ // .. .. FINISH: DEASSERT RESET
+ // .. .. RESET = 0x1
+ // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ENABLE = 0x1
+ // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. .. reserved_VRP_TRI = 0x0
+ // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reserved_VRN_TRI = 0x0
+ // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reserved_VRP_OUT = 0x0
+ // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reserved_VRN_OUT = 0x1
+ // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
+ // .. .. NREF_OPT1 = 0x0
+ // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
+ // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U
+ // .. .. NREF_OPT2 = 0x0
+ // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U
+ // .. .. NREF_OPT4 = 0x1
+ // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
+ // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U
+ // .. .. PREF_OPT1 = 0x0
+ // .. .. ==> 0XF8000B70[15:14] = 0x00000000U
+ // .. .. ==> MASK : 0x0000C000U VAL : 0x00000000U
+ // .. .. PREF_OPT2 = 0x0
+ // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
+ // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U
+ // .. .. UPDATE_CONTROL = 0x0
+ // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
+ // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U
+ // .. .. reserved_INIT_COMPLETE = 0x0
+ // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
+ // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U
+ // .. .. reserved_TST_CLK = 0x0
+ // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
+ // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U
+ // .. .. reserved_TST_HLN = 0x0
+ // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
+ // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U
+ // .. .. reserved_TST_HLP = 0x0
+ // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
+ // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U
+ // .. .. reserved_TST_RST = 0x0
+ // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
+ // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
+ // .. .. reserved_INT_DCI_EN = 0x0
+ // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
+ // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU ,0x00000823U),
+ // .. FINISH: DDRIOB SETTINGS
+ // .. START: MIO PROGRAMMING
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000700[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000700[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000700[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000700[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000700[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000700[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000700[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000700[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000700[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000704[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000704[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000704[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000704[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000704[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000704[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000704[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000704[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000704[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00000702U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000708[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000708[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000708[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000708[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000708[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000708[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000708[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000708[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000708[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000702U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800070C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF800070C[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800070C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800070C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800070C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF800070C[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 3
+ // .. ==> 0XF800070C[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF800070C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800070C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000702U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000710[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000710[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000710[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000710[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000710[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000710[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000710[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000710[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000710[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000702U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000714[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000714[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000714[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000714[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000714[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000714[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000714[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000714[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000714[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000702U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000718[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000718[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000718[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000718[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000718[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000718[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000718[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000718[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000718[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000702U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800071C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800071C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800071C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800071C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800071C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800071C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF800071C[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF800071C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800071C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000720[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000720[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000720[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000720[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000720[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000720[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000720[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000720[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000720[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000700U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000724[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000724[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000724[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000724[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000724[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000724[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000724[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000724[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000724[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000728[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000728[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000728[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000728[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000728[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000728[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000728[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000728[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000728[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800072C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800072C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800072C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800072C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800072C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800072C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF800072C[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF800072C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800072C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000730[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000730[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000730[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000730[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000730[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000730[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000730[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000730[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000730[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000734[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000734[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000734[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000734[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000734[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000734[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000734[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000734[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000734[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000738[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000738[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000738[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000738[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000738[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000738[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000738[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000738[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000738[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800073C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800073C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800073C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800073C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800073C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800073C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF800073C[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF800073C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800073C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000740[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000740[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000740[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000740[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000740[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000740[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000740[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000740[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000740[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000302U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000744[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000744[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000744[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000744[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000744[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000744[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000744[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000744[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000744[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000302U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000748[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000748[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000748[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000748[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000748[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000748[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000748[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000748[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000748[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000302U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800074C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF800074C[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800074C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800074C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800074C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF800074C[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF800074C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800074C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800074C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000302U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000750[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000750[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000750[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000750[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000750[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000750[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000750[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000750[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000750[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000302U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000754[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000754[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000754[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000754[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000754[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000754[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000754[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000754[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000754[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000302U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000758[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000758[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000758[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000758[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000758[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000758[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000758[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000758[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000758[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000303U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF800075C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF800075C[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800075C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800075C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800075C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF800075C[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF800075C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800075C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800075C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000303U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000760[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000760[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000760[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000760[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000760[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000760[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000760[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000760[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000760[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000303U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000764[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000764[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000764[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000764[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000764[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000764[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000764[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000764[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000764[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000303U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000768[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000768[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000768[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000768[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000768[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000768[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000768[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000768[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000768[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000303U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF800076C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF800076C[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800076C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800076C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800076C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF800076C[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF800076C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800076C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800076C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000303U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000770[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000770[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000770[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000770[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000770[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000770[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000770[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000770[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000770[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000304U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000774[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000774[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000774[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000774[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000774[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000774[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000774[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000774[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000774[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000305U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000778[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000778[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000778[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000778[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000778[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000778[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000778[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000778[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000778[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000304U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF800077C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800077C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF800077C[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800077C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800077C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF800077C[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF800077C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800077C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800077C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000305U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000780[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000780[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000780[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000780[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000780[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000780[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000780[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000780[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000780[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000304U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000784[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000784[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000784[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000784[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000784[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000784[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000784[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000784[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000784[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000304U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000788[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000788[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000788[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000788[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000788[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000788[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000788[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000788[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000788[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000304U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800078C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800078C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF800078C[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800078C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800078C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF800078C[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF800078C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800078C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800078C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000304U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000790[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000790[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000790[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000790[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000790[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000790[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000790[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000790[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000790[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000305U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000794[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000794[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000794[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000794[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000794[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000794[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000794[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000794[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000794[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000304U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000798[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000798[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000798[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000798[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000798[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000798[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000798[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000798[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000798[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000304U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800079C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800079C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF800079C[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800079C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800079C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF800079C[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF800079C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800079C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800079C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000304U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007A0[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007A0[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007A0[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007A0[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007A0[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 1
+ // .. ==> 0XF80007A0[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007A0[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007A0[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007A0[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000380U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007A4[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007A4[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007A4[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007A4[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007A4[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 1
+ // .. ==> 0XF80007A4[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007A4[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007A4[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007A4[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000380U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007A8[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007A8[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007A8[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007A8[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007A8[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 1
+ // .. ==> 0XF80007A8[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007A8[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007A8[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007A8[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000380U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007AC[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007AC[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007AC[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007AC[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007AC[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 1
+ // .. ==> 0XF80007AC[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007AC[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007AC[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007AC[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000380U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007B0[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007B0[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007B0[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007B0[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007B0[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 1
+ // .. ==> 0XF80007B0[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007B0[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007B0[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007B0[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000380U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007B4[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007B4[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007B4[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007B4[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007B4[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 1
+ // .. ==> 0XF80007B4[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007B4[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007B4[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007B4[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000380U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF80007B8[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. Speed = 0
+ // .. ==> 0XF80007B8[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007B8[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007B8[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007B8[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007B8, 0x00003F01U ,0x00000201U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF80007BC[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. Speed = 0
+ // .. ==> 0XF80007BC[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007BC[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007BC[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007BC[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007BC, 0x00003F01U ,0x00000201U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007C0[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007C0[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007C0[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007C0[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 7
+ // .. ==> 0XF80007C0[7:5] = 0x00000007U
+ // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U
+ // .. Speed = 0
+ // .. ==> 0XF80007C0[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007C0[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007C0[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007C0[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF80007C4[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007C4[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007C4[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007C4[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 7
+ // .. ==> 0XF80007C4[7:5] = 0x00000007U
+ // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U
+ // .. Speed = 0
+ // .. ==> 0XF80007C4[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007C4[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007C4[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007C4[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF80007C8[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007C8[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007C8[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007C8[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF80007C8[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF80007C8[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007C8[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007C8[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007C8[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00000201U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF80007CC[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007CC[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007CC[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007CC[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF80007CC[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF80007CC[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007CC[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007CC[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007CC[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00000201U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007D0[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007D0[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007D0[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007D0[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007D0[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007D0[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007D0[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007D0[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007D0[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007D4[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007D4[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007D4[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007D4[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007D4[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007D4[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007D4[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007D4[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007D4[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U),
+ // .. SDIO0_WP_SEL = 46
+ // .. ==> 0XF8000830[5:0] = 0x0000002EU
+ // .. ==> MASK : 0x0000003FU VAL : 0x0000002EU
+ // .. SDIO0_CD_SEL = 47
+ // .. ==> 0XF8000830[21:16] = 0x0000002FU
+ // .. ==> MASK : 0x003F0000U VAL : 0x002F0000U
+ // ..
+ EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x002F002EU),
+ // .. FINISH: MIO PROGRAMMING
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_peripherals_init_data_3_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+ // .. IBUF_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B48[7:7] = 0x00000001U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. TERM_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B48[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // ..
+ EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
+ // .. IBUF_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B4C[7:7] = 0x00000001U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. TERM_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B4C[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // ..
+ EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
+ // .. IBUF_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B50[7:7] = 0x00000001U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. TERM_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B50[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // ..
+ EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
+ // .. IBUF_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B54[7:7] = 0x00000001U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. TERM_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B54[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // ..
+ EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
+ // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // .. START: SRAM/NOR SET OPMODE
+ // .. FINISH: SRAM/NOR SET OPMODE
+ // .. START: UART REGISTERS
+ // .. BDIV = 0x6
+ // .. ==> 0XE0001034[7:0] = 0x00000006U
+ // .. ==> MASK : 0x000000FFU VAL : 0x00000006U
+ // ..
+ EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
+ // .. CD = 0x3e
+ // .. ==> 0XE0001018[15:0] = 0x0000003EU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU
+ // ..
+ EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
+ // .. STPBRK = 0x0
+ // .. ==> 0XE0001000[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. STTBRK = 0x0
+ // .. ==> 0XE0001000[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. RSTTO = 0x0
+ // .. ==> 0XE0001000[6:6] = 0x00000000U
+ // .. ==> MASK : 0x00000040U VAL : 0x00000000U
+ // .. TXDIS = 0x0
+ // .. ==> 0XE0001000[5:5] = 0x00000000U
+ // .. ==> MASK : 0x00000020U VAL : 0x00000000U
+ // .. TXEN = 0x1
+ // .. ==> 0XE0001000[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. RXDIS = 0x0
+ // .. ==> 0XE0001000[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. RXEN = 0x1
+ // .. ==> 0XE0001000[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. TXRES = 0x1
+ // .. ==> 0XE0001000[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. RXRES = 0x1
+ // .. ==> 0XE0001000[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // ..
+ EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
+ // .. CHMODE = 0x0
+ // .. ==> 0XE0001004[9:8] = 0x00000000U
+ // .. ==> MASK : 0x00000300U VAL : 0x00000000U
+ // .. NBSTOP = 0x0
+ // .. ==> 0XE0001004[7:6] = 0x00000000U
+ // .. ==> MASK : 0x000000C0U VAL : 0x00000000U
+ // .. PAR = 0x4
+ // .. ==> 0XE0001004[5:3] = 0x00000004U
+ // .. ==> MASK : 0x00000038U VAL : 0x00000020U
+ // .. CHRL = 0x0
+ // .. ==> 0XE0001004[2:1] = 0x00000000U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000000U
+ // .. CLKS = 0x0
+ // .. ==> 0XE0001004[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XE0001004, 0x000003FFU ,0x00000020U),
+ // .. FINISH: UART REGISTERS
+ // .. START: QSPI REGISTERS
+ // .. Holdb_dr = 1
+ // .. ==> 0XE000D000[19:19] = 0x00000001U
+ // .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // ..
+ EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
+ // .. FINISH: QSPI REGISTERS
+ // .. START: PL POWER ON RESET REGISTERS
+ // .. PCFG_POR_CNT_4K = 0
+ // .. ==> 0XF8007000[29:29] = 0x00000000U
+ // .. ==> MASK : 0x20000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
+ // .. FINISH: PL POWER ON RESET REGISTERS
+ // .. START: SMC TIMING CALCULATION REGISTER UPDATE
+ // .. .. START: NAND SET CYCLE
+ // .. .. FINISH: NAND SET CYCLE
+ // .. .. START: OPMODE
+ // .. .. FINISH: OPMODE
+ // .. .. START: DIRECT COMMAND
+ // .. .. FINISH: DIRECT COMMAND
+ // .. .. START: SRAM/NOR CS0 SET CYCLE
+ // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
+ // .. .. START: DIRECT COMMAND
+ // .. .. FINISH: DIRECT COMMAND
+ // .. .. START: NOR CS0 BASE ADDRESS
+ // .. .. FINISH: NOR CS0 BASE ADDRESS
+ // .. .. START: SRAM/NOR CS1 SET CYCLE
+ // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
+ // .. .. START: DIRECT COMMAND
+ // .. .. FINISH: DIRECT COMMAND
+ // .. .. START: NOR CS1 BASE ADDRESS
+ // .. .. FINISH: NOR CS1 BASE ADDRESS
+ // .. .. START: USB RESET
+ // .. .. .. START: USB0 RESET
+ // .. .. .. .. START: DIR MODE BANK 0
+ // .. .. .. .. FINISH: DIR MODE BANK 0
+ // .. .. .. .. START: DIR MODE BANK 1
+ // .. .. .. .. FINISH: DIR MODE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. START: OUTPUT ENABLE BANK 0
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+ // .. .. .. .. START: OUTPUT ENABLE BANK 1
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. START: ADD 1 MS DELAY
+ // .. .. .. ..
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ // .. .. .. .. FINISH: ADD 1 MS DELAY
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. FINISH: USB0 RESET
+ // .. .. .. START: USB1 RESET
+ // .. .. .. .. START: DIR MODE BANK 0
+ // .. .. .. .. FINISH: DIR MODE BANK 0
+ // .. .. .. .. START: DIR MODE BANK 1
+ // .. .. .. .. FINISH: DIR MODE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. START: OUTPUT ENABLE BANK 0
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+ // .. .. .. .. START: OUTPUT ENABLE BANK 1
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. START: ADD 1 MS DELAY
+ // .. .. .. ..
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ // .. .. .. .. FINISH: ADD 1 MS DELAY
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. FINISH: USB1 RESET
+ // .. .. FINISH: USB RESET
+ // .. .. START: ENET RESET
+ // .. .. .. START: ENET0 RESET
+ // .. .. .. .. START: DIR MODE BANK 0
+ // .. .. .. .. FINISH: DIR MODE BANK 0
+ // .. .. .. .. START: DIR MODE BANK 1
+ // .. .. .. .. FINISH: DIR MODE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. START: OUTPUT ENABLE BANK 0
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+ // .. .. .. .. START: OUTPUT ENABLE BANK 1
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. START: ADD 1 MS DELAY
+ // .. .. .. ..
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ // .. .. .. .. FINISH: ADD 1 MS DELAY
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. FINISH: ENET0 RESET
+ // .. .. .. START: ENET1 RESET
+ // .. .. .. .. START: DIR MODE BANK 0
+ // .. .. .. .. FINISH: DIR MODE BANK 0
+ // .. .. .. .. START: DIR MODE BANK 1
+ // .. .. .. .. FINISH: DIR MODE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. START: OUTPUT ENABLE BANK 0
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+ // .. .. .. .. START: OUTPUT ENABLE BANK 1
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. START: ADD 1 MS DELAY
+ // .. .. .. ..
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ // .. .. .. .. FINISH: ADD 1 MS DELAY
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. FINISH: ENET1 RESET
+ // .. .. FINISH: ENET RESET
+ // .. .. START: I2C RESET
+ // .. .. .. START: I2C0 RESET
+ // .. .. .. .. START: DIR MODE GPIO BANK0
+ // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+ // .. .. .. .. START: DIR MODE GPIO BANK1
+ // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. START: OUTPUT ENABLE
+ // .. .. .. .. FINISH: OUTPUT ENABLE
+ // .. .. .. .. START: OUTPUT ENABLE
+ // .. .. .. .. FINISH: OUTPUT ENABLE
+ // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. START: ADD 1 MS DELAY
+ // .. .. .. ..
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ // .. .. .. .. FINISH: ADD 1 MS DELAY
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. FINISH: I2C0 RESET
+ // .. .. .. START: I2C1 RESET
+ // .. .. .. .. START: DIR MODE GPIO BANK0
+ // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+ // .. .. .. .. START: DIR MODE GPIO BANK1
+ // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. START: OUTPUT ENABLE
+ // .. .. .. .. FINISH: OUTPUT ENABLE
+ // .. .. .. .. START: OUTPUT ENABLE
+ // .. .. .. .. FINISH: OUTPUT ENABLE
+ // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. START: ADD 1 MS DELAY
+ // .. .. .. ..
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ // .. .. .. .. FINISH: ADD 1 MS DELAY
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. FINISH: I2C1 RESET
+ // .. .. FINISH: I2C RESET
+ // .. .. START: NOR CHIP SELECT
+ // .. .. .. START: DIR MODE BANK 0
+ // .. .. .. FINISH: DIR MODE BANK 0
+ // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. START: OUTPUT ENABLE BANK 0
+ // .. .. .. FINISH: OUTPUT ENABLE BANK 0
+ // .. .. FINISH: NOR CHIP SELECT
+ // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_post_config_3_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: ENABLING LEVEL SHIFTER
+ // .. USER_LVL_INP_EN_0 = 1
+ // .. ==> 0XF8000900[3:3] = 0x00000001U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000008U
+ // .. USER_LVL_OUT_EN_0 = 1
+ // .. ==> 0XF8000900[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. USER_LVL_INP_EN_1 = 1
+ // .. ==> 0XF8000900[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. USER_LVL_OUT_EN_1 = 1
+ // .. ==> 0XF8000900[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // ..
+ EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
+ // .. FINISH: ENABLING LEVEL SHIFTER
+ // .. START: FPGA RESETS TO 0
+ // .. reserved_3 = 0
+ // .. ==> 0XF8000240[31:25] = 0x00000000U
+ // .. ==> MASK : 0xFE000000U VAL : 0x00000000U
+ // .. reserved_FPGA_ACP_RST = 0
+ // .. ==> 0XF8000240[24:24] = 0x00000000U
+ // .. ==> MASK : 0x01000000U VAL : 0x00000000U
+ // .. reserved_FPGA_AXDS3_RST = 0
+ // .. ==> 0XF8000240[23:23] = 0x00000000U
+ // .. ==> MASK : 0x00800000U VAL : 0x00000000U
+ // .. reserved_FPGA_AXDS2_RST = 0
+ // .. ==> 0XF8000240[22:22] = 0x00000000U
+ // .. ==> MASK : 0x00400000U VAL : 0x00000000U
+ // .. reserved_FPGA_AXDS1_RST = 0
+ // .. ==> 0XF8000240[21:21] = 0x00000000U
+ // .. ==> MASK : 0x00200000U VAL : 0x00000000U
+ // .. reserved_FPGA_AXDS0_RST = 0
+ // .. ==> 0XF8000240[20:20] = 0x00000000U
+ // .. ==> MASK : 0x00100000U VAL : 0x00000000U
+ // .. reserved_2 = 0
+ // .. ==> 0XF8000240[19:18] = 0x00000000U
+ // .. ==> MASK : 0x000C0000U VAL : 0x00000000U
+ // .. reserved_FSSW1_FPGA_RST = 0
+ // .. ==> 0XF8000240[17:17] = 0x00000000U
+ // .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. reserved_FSSW0_FPGA_RST = 0
+ // .. ==> 0XF8000240[16:16] = 0x00000000U
+ // .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. reserved_1 = 0
+ // .. ==> 0XF8000240[15:14] = 0x00000000U
+ // .. ==> MASK : 0x0000C000U VAL : 0x00000000U
+ // .. reserved_FPGA_FMSW1_RST = 0
+ // .. ==> 0XF8000240[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // .. reserved_FPGA_FMSW0_RST = 0
+ // .. ==> 0XF8000240[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. reserved_FPGA_DMA3_RST = 0
+ // .. ==> 0XF8000240[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. reserved_FPGA_DMA2_RST = 0
+ // .. ==> 0XF8000240[10:10] = 0x00000000U
+ // .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. reserved_FPGA_DMA1_RST = 0
+ // .. ==> 0XF8000240[9:9] = 0x00000000U
+ // .. ==> MASK : 0x00000200U VAL : 0x00000000U
+ // .. reserved_FPGA_DMA0_RST = 0
+ // .. ==> 0XF8000240[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. reserved = 0
+ // .. ==> 0XF8000240[7:4] = 0x00000000U
+ // .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. FPGA3_OUT_RST = 0
+ // .. ==> 0XF8000240[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. FPGA2_OUT_RST = 0
+ // .. ==> 0XF8000240[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. FPGA1_OUT_RST = 0
+ // .. ==> 0XF8000240[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. FPGA0_OUT_RST = 0
+ // .. ==> 0XF8000240[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
+ // .. FINISH: FPGA RESETS TO 0
+ // .. START: AFI REGISTERS
+ // .. .. START: AFI0 REGISTERS
+ // .. .. FINISH: AFI0 REGISTERS
+ // .. .. START: AFI1 REGISTERS
+ // .. .. FINISH: AFI1 REGISTERS
+ // .. .. START: AFI2 REGISTERS
+ // .. .. FINISH: AFI2 REGISTERS
+ // .. .. START: AFI3 REGISTERS
+ // .. .. FINISH: AFI3 REGISTERS
+ // .. FINISH: AFI REGISTERS
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_debug_3_0[] = {
+ // START: top
+ // .. START: CROSS TRIGGER CONFIGURATIONS
+ // .. .. START: UNLOCKING CTI REGISTERS
+ // .. .. KEY = 0XC5ACCE55
+ // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
+ // .. ..
+ EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
+ // .. .. KEY = 0XC5ACCE55
+ // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
+ // .. ..
+ EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
+ // .. .. KEY = 0XC5ACCE55
+ // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
+ // .. ..
+ EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
+ // .. .. FINISH: UNLOCKING CTI REGISTERS
+ // .. .. START: ENABLING CTI MODULES AND CHANNELS
+ // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
+ // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+ // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+ // .. FINISH: CROSS TRIGGER CONFIGURATIONS
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_pll_init_data_2_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: PLL SLCR REGISTERS
+ // .. .. START: ARM PLL INIT
+ // .. .. PLL_RES = 0x2
+ // .. .. ==> 0XF8000110[7:4] = 0x00000002U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
+ // .. .. PLL_CP = 0x2
+ // .. .. ==> 0XF8000110[11:8] = 0x00000002U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
+ // .. .. LOCK_CNT = 0xfa
+ // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
+ // .. .. .. START: UPDATE FB_DIV
+ // .. .. .. PLL_FDIV = 0x28
+ // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
+ // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
+ // .. .. .. FINISH: UPDATE FB_DIV
+ // .. .. .. START: BY PASS PLL
+ // .. .. .. PLL_BYPASS_FORCE = 1
+ // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
+ // .. .. .. FINISH: BY PASS PLL
+ // .. .. .. START: ASSERT RESET
+ // .. .. .. PLL_RESET = 1
+ // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
+ // .. .. .. FINISH: ASSERT RESET
+ // .. .. .. START: DEASSERT RESET
+ // .. .. .. PLL_RESET = 0
+ // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
+ // .. .. .. FINISH: DEASSERT RESET
+ // .. .. .. START: CHECK PLL STATUS
+ // .. .. .. ARM_PLL_LOCK = 1
+ // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ..
+ EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+ // .. .. .. FINISH: CHECK PLL STATUS
+ // .. .. .. START: REMOVE PLL BY PASS
+ // .. .. .. PLL_BYPASS_FORCE = 0
+ // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
+ // .. .. .. FINISH: REMOVE PLL BY PASS
+ // .. .. .. SRCSEL = 0x0
+ // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. .. .. DIVISOR = 0x2
+ // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
+ // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U
+ // .. .. .. CPU_6OR4XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
+ // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U
+ // .. .. .. CPU_3OR2XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
+ // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U
+ // .. .. .. CPU_2XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
+ // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U
+ // .. .. .. CPU_1XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
+ // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U
+ // .. .. .. CPU_PERI_CLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
+ // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
+ // .. .. FINISH: ARM PLL INIT
+ // .. .. START: DDR PLL INIT
+ // .. .. PLL_RES = 0x2
+ // .. .. ==> 0XF8000114[7:4] = 0x00000002U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
+ // .. .. PLL_CP = 0x2
+ // .. .. ==> 0XF8000114[11:8] = 0x00000002U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
+ // .. .. LOCK_CNT = 0x12c
+ // .. .. ==> 0XF8000114[21:12] = 0x0000012CU
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
+ // .. .. .. START: UPDATE FB_DIV
+ // .. .. .. PLL_FDIV = 0x20
+ // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
+ // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
+ // .. .. .. FINISH: UPDATE FB_DIV
+ // .. .. .. START: BY PASS PLL
+ // .. .. .. PLL_BYPASS_FORCE = 1
+ // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
+ // .. .. .. FINISH: BY PASS PLL
+ // .. .. .. START: ASSERT RESET
+ // .. .. .. PLL_RESET = 1
+ // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
+ // .. .. .. FINISH: ASSERT RESET
+ // .. .. .. START: DEASSERT RESET
+ // .. .. .. PLL_RESET = 0
+ // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
+ // .. .. .. FINISH: DEASSERT RESET
+ // .. .. .. START: CHECK PLL STATUS
+ // .. .. .. DDR_PLL_LOCK = 1
+ // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. .. ..
+ EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+ // .. .. .. FINISH: CHECK PLL STATUS
+ // .. .. .. START: REMOVE PLL BY PASS
+ // .. .. .. PLL_BYPASS_FORCE = 0
+ // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
+ // .. .. .. FINISH: REMOVE PLL BY PASS
+ // .. .. .. DDR_3XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. .. DDR_2XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. .. .. DDR_3XCLK_DIVISOR = 0x2
+ // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
+ // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U
+ // .. .. .. DDR_2XCLK_DIVISOR = 0x3
+ // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
+ // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
+ // .. .. FINISH: DDR PLL INIT
+ // .. .. START: IO PLL INIT
+ // .. .. PLL_RES = 0xc
+ // .. .. ==> 0XF8000118[7:4] = 0x0000000CU
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U
+ // .. .. PLL_CP = 0x2
+ // .. .. ==> 0XF8000118[11:8] = 0x00000002U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
+ // .. .. LOCK_CNT = 0x145
+ // .. .. ==> 0XF8000118[21:12] = 0x00000145U
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U),
+ // .. .. .. START: UPDATE FB_DIV
+ // .. .. .. PLL_FDIV = 0x1e
+ // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU
+ // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U),
+ // .. .. .. FINISH: UPDATE FB_DIV
+ // .. .. .. START: BY PASS PLL
+ // .. .. .. PLL_BYPASS_FORCE = 1
+ // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
+ // .. .. .. FINISH: BY PASS PLL
+ // .. .. .. START: ASSERT RESET
+ // .. .. .. PLL_RESET = 1
+ // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
+ // .. .. .. FINISH: ASSERT RESET
+ // .. .. .. START: DEASSERT RESET
+ // .. .. .. PLL_RESET = 0
+ // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
+ // .. .. .. FINISH: DEASSERT RESET
+ // .. .. .. START: CHECK PLL STATUS
+ // .. .. .. IO_PLL_LOCK = 1
+ // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. .. ..
+ EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+ // .. .. .. FINISH: CHECK PLL STATUS
+ // .. .. .. START: REMOVE PLL BY PASS
+ // .. .. .. PLL_BYPASS_FORCE = 0
+ // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
+ // .. .. .. FINISH: REMOVE PLL BY PASS
+ // .. .. FINISH: IO PLL INIT
+ // .. FINISH: PLL SLCR REGISTERS
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_clock_init_data_2_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: CLOCK CONTROL SLCR REGISTERS
+ // .. CLKACT = 0x1
+ // .. ==> 0XF8000128[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. DIVISOR0 = 0x23
+ // .. ==> 0XF8000128[13:8] = 0x00000023U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00002300U
+ // .. DIVISOR1 = 0x3
+ // .. ==> 0XF8000128[25:20] = 0x00000003U
+ // .. ==> MASK : 0x03F00000U VAL : 0x00300000U
+ // ..
+ EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U),
+ // .. CLKACT = 0x1
+ // .. ==> 0XF8000138[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000138[4:4] = 0x00000000U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
+ // .. CLKACT = 0x1
+ // .. ==> 0XF8000140[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000140[6:4] = 0x00000000U
+ // .. ==> MASK : 0x00000070U VAL : 0x00000000U
+ // .. DIVISOR = 0x8
+ // .. ==> 0XF8000140[13:8] = 0x00000008U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00000800U
+ // .. DIVISOR1 = 0x1
+ // .. ==> 0XF8000140[25:20] = 0x00000001U
+ // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
+ // ..
+ EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U),
+ // .. CLKACT = 0x1
+ // .. ==> 0XF800014C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF800014C[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR = 0x5
+ // .. ==> 0XF800014C[13:8] = 0x00000005U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00000500U
+ // ..
+ EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
+ // .. CLKACT0 = 0x1
+ // .. ==> 0XF8000150[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. CLKACT1 = 0x0
+ // .. ==> 0XF8000150[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000150[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR = 0x14
+ // .. ==> 0XF8000150[13:8] = 0x00000014U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
+ // ..
+ EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U),
+ // .. CLKACT0 = 0x0
+ // .. ==> 0XF8000154[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. CLKACT1 = 0x1
+ // .. ==> 0XF8000154[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000154[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR = 0x14
+ // .. ==> 0XF8000154[13:8] = 0x00000014U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
+ // ..
+ EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U),
+ // .. CLKACT = 0x1
+ // .. ==> 0XF8000168[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000168[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR = 0x5
+ // .. ==> 0XF8000168[13:8] = 0x00000005U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00000500U
+ // ..
+ EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000170[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR0 = 0xa
+ // .. ==> 0XF8000170[13:8] = 0x0000000AU
+ // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U
+ // .. DIVISOR1 = 0x1
+ // .. ==> 0XF8000170[25:20] = 0x00000001U
+ // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
+ // ..
+ EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00100A00U),
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000180[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR0 = 0x7
+ // .. ==> 0XF8000180[13:8] = 0x00000007U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00000700U
+ // .. DIVISOR1 = 0x1
+ // .. ==> 0XF8000180[25:20] = 0x00000001U
+ // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
+ // ..
+ EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00100700U),
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000190[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR0 = 0x14
+ // .. ==> 0XF8000190[13:8] = 0x00000014U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
+ // .. DIVISOR1 = 0x1
+ // .. ==> 0XF8000190[25:20] = 0x00000001U
+ // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
+ // ..
+ EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101400U),
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF80001A0[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR0 = 0x14
+ // .. ==> 0XF80001A0[13:8] = 0x00000014U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
+ // .. DIVISOR1 = 0x1
+ // .. ==> 0XF80001A0[25:20] = 0x00000001U
+ // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
+ // ..
+ EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U),
+ // .. CLK_621_TRUE = 0x1
+ // .. ==> 0XF80001C4[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // ..
+ EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
+ // .. DMA_CPU_2XCLKACT = 0x1
+ // .. ==> 0XF800012C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. USB0_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. USB1_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[3:3] = 0x00000001U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000008U
+ // .. GEM0_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[6:6] = 0x00000001U
+ // .. ==> MASK : 0x00000040U VAL : 0x00000040U
+ // .. GEM1_CPU_1XCLKACT = 0x0
+ // .. ==> 0XF800012C[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. SDI0_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[10:10] = 0x00000001U
+ // .. ==> MASK : 0x00000400U VAL : 0x00000400U
+ // .. SDI1_CPU_1XCLKACT = 0x0
+ // .. ==> 0XF800012C[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. SPI0_CPU_1XCLKACT = 0x0
+ // .. ==> 0XF800012C[14:14] = 0x00000000U
+ // .. ==> MASK : 0x00004000U VAL : 0x00000000U
+ // .. SPI1_CPU_1XCLKACT = 0x0
+ // .. ==> 0XF800012C[15:15] = 0x00000000U
+ // .. ==> MASK : 0x00008000U VAL : 0x00000000U
+ // .. CAN0_CPU_1XCLKACT = 0x0
+ // .. ==> 0XF800012C[16:16] = 0x00000000U
+ // .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. CAN1_CPU_1XCLKACT = 0x0
+ // .. ==> 0XF800012C[17:17] = 0x00000000U
+ // .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. I2C0_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[18:18] = 0x00000001U
+ // .. ==> MASK : 0x00040000U VAL : 0x00040000U
+ // .. I2C1_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[19:19] = 0x00000001U
+ // .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // .. UART0_CPU_1XCLKACT = 0x0
+ // .. ==> 0XF800012C[20:20] = 0x00000000U
+ // .. ==> MASK : 0x00100000U VAL : 0x00000000U
+ // .. UART1_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[21:21] = 0x00000001U
+ // .. ==> MASK : 0x00200000U VAL : 0x00200000U
+ // .. GPIO_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[22:22] = 0x00000001U
+ // .. ==> MASK : 0x00400000U VAL : 0x00400000U
+ // .. LQSPI_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[23:23] = 0x00000001U
+ // .. ==> MASK : 0x00800000U VAL : 0x00800000U
+ // .. SMC_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[24:24] = 0x00000001U
+ // .. ==> MASK : 0x01000000U VAL : 0x01000000U
+ // ..
+ EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC044DU),
+ // .. FINISH: CLOCK CONTROL SLCR REGISTERS
+ // .. START: THIS SHOULD BE BLANK
+ // .. FINISH: THIS SHOULD BE BLANK
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_ddr_init_data_2_0[] = {
+ // START: top
+ // .. START: DDR INITIALIZATION
+ // .. .. START: LOCK DDR
+ // .. .. reg_ddrc_soft_rstb = 0
+ // .. .. ==> 0XF8006000[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_powerdown_en = 0x0
+ // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_ddrc_data_bus_width = 0x0
+ // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U
+ // .. .. reg_ddrc_burst8_refresh = 0x0
+ // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U
+ // .. .. reg_ddrc_rdwr_idle_gap = 0x1
+ // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+ // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U
+ // .. .. reg_ddrc_dis_rd_bypass = 0x0
+ // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+ // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_act_bypass = 0x0
+ // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_auto_refresh = 0x0
+ // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
+ // .. .. FINISH: LOCK DDR
+ // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81
+ // .. .. ==> 0XF8006004[11:0] = 0x00000081U
+ // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U
+ // .. .. reg_ddrc_active_ranks = 0x1
+ // .. .. ==> 0XF8006004[13:12] = 0x00000001U
+ // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U
+ // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
+ // .. .. ==> 0XF8006004[18:14] = 0x00000000U
+ // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U
+ // .. .. reg_ddrc_wr_odt_block = 0x1
+ // .. .. ==> 0XF8006004[20:19] = 0x00000001U
+ // .. .. ==> MASK : 0x00180000U VAL : 0x00080000U
+ // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0
+ // .. .. ==> 0XF8006004[21:21] = 0x00000000U
+ // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0
+ // .. .. ==> 0XF8006004[26:22] = 0x00000000U
+ // .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_open_bank = 0x0
+ // .. .. ==> 0XF8006004[27:27] = 0x00000000U
+ // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_4bank_ram = 0x0
+ // .. .. ==> 0XF8006004[28:28] = 0x00000000U
+ // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U),
+ // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
+ // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU
+ // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
+ // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
+ // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U
+ // .. .. reg_ddrc_hpr_xact_run_length = 0xf
+ // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
+ // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
+ // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
+ // .. .. ==> 0XF800600C[10:0] = 0x00000001U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U
+ // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
+ // .. .. ==> 0XF800600C[21:11] = 0x00000002U
+ // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U
+ // .. .. reg_ddrc_lpr_xact_run_length = 0x8
+ // .. .. ==> 0XF800600C[25:22] = 0x00000008U
+ // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
+ // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
+ // .. .. ==> 0XF8006010[10:0] = 0x00000001U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U
+ // .. .. reg_ddrc_w_xact_run_length = 0x8
+ // .. .. ==> 0XF8006010[14:11] = 0x00000008U
+ // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U
+ // .. .. reg_ddrc_w_max_starve_x32 = 0x2
+ // .. .. ==> 0XF8006010[25:15] = 0x00000002U
+ // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
+ // .. .. reg_ddrc_t_rc = 0x1b
+ // .. .. ==> 0XF8006014[5:0] = 0x0000001BU
+ // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001BU
+ // .. .. reg_ddrc_t_rfc_min = 0x56
+ // .. .. ==> 0XF8006014[13:6] = 0x00000056U
+ // .. .. ==> MASK : 0x00003FC0U VAL : 0x00001580U
+ // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
+ // .. .. ==> 0XF8006014[20:14] = 0x00000010U
+ // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004159BU),
+ // .. .. reg_ddrc_wr2pre = 0x12
+ // .. .. ==> 0XF8006018[4:0] = 0x00000012U
+ // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U
+ // .. .. reg_ddrc_powerdown_to_x32 = 0x6
+ // .. .. ==> 0XF8006018[9:5] = 0x00000006U
+ // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U
+ // .. .. reg_ddrc_t_faw = 0x18
+ // .. .. ==> 0XF8006018[15:10] = 0x00000018U
+ // .. .. ==> MASK : 0x0000FC00U VAL : 0x00006000U
+ // .. .. reg_ddrc_t_ras_max = 0x24
+ // .. .. ==> 0XF8006018[21:16] = 0x00000024U
+ // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U
+ // .. .. reg_ddrc_t_ras_min = 0x14
+ // .. .. ==> 0XF8006018[26:22] = 0x00000014U
+ // .. .. ==> MASK : 0x07C00000U VAL : 0x05000000U
+ // .. .. reg_ddrc_t_cke = 0x4
+ // .. .. ==> 0XF8006018[31:28] = 0x00000004U
+ // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x452460D2U),
+ // .. .. reg_ddrc_write_latency = 0x5
+ // .. .. ==> 0XF800601C[4:0] = 0x00000005U
+ // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U
+ // .. .. reg_ddrc_rd2wr = 0x7
+ // .. .. ==> 0XF800601C[9:5] = 0x00000007U
+ // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U
+ // .. .. reg_ddrc_wr2rd = 0xe
+ // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
+ // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U
+ // .. .. reg_ddrc_t_xp = 0x4
+ // .. .. ==> 0XF800601C[19:15] = 0x00000004U
+ // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U
+ // .. .. reg_ddrc_pad_pd = 0x0
+ // .. .. ==> 0XF800601C[22:20] = 0x00000000U
+ // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U
+ // .. .. reg_ddrc_rd2pre = 0x4
+ // .. .. ==> 0XF800601C[27:23] = 0x00000004U
+ // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U
+ // .. .. reg_ddrc_t_rcd = 0x7
+ // .. .. ==> 0XF800601C[31:28] = 0x00000007U
+ // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
+ // .. .. reg_ddrc_t_ccd = 0x4
+ // .. .. ==> 0XF8006020[4:2] = 0x00000004U
+ // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U
+ // .. .. reg_ddrc_t_rrd = 0x6
+ // .. .. ==> 0XF8006020[7:5] = 0x00000006U
+ // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U
+ // .. .. reg_ddrc_refresh_margin = 0x2
+ // .. .. ==> 0XF8006020[11:8] = 0x00000002U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
+ // .. .. reg_ddrc_t_rp = 0x7
+ // .. .. ==> 0XF8006020[15:12] = 0x00000007U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U
+ // .. .. reg_ddrc_refresh_to_x32 = 0x8
+ // .. .. ==> 0XF8006020[20:16] = 0x00000008U
+ // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U
+ // .. .. reg_ddrc_sdram = 0x1
+ // .. .. ==> 0XF8006020[21:21] = 0x00000001U
+ // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U
+ // .. .. reg_ddrc_mobile = 0x0
+ // .. .. ==> 0XF8006020[22:22] = 0x00000000U
+ // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U
+ // .. .. reg_ddrc_clock_stop_en = 0x0
+ // .. .. ==> 0XF8006020[23:23] = 0x00000000U
+ // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U
+ // .. .. reg_ddrc_read_latency = 0x7
+ // .. .. ==> 0XF8006020[28:24] = 0x00000007U
+ // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U
+ // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
+ // .. .. ==> 0XF8006020[29:29] = 0x00000001U
+ // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U
+ // .. .. reg_ddrc_dis_pad_pd = 0x0
+ // .. .. ==> 0XF8006020[30:30] = 0x00000000U
+ // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_loopback = 0x0
+ // .. .. ==> 0XF8006020[31:31] = 0x00000000U
+ // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U),
+ // .. .. reg_ddrc_en_2t_timing_mode = 0x0
+ // .. .. ==> 0XF8006024[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_prefer_write = 0x0
+ // .. .. ==> 0XF8006024[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_ddrc_max_rank_rd = 0xf
+ // .. .. ==> 0XF8006024[5:2] = 0x0000000FU
+ // .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU
+ // .. .. reg_ddrc_mr_wr = 0x0
+ // .. .. ==> 0XF8006024[6:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr_addr = 0x0
+ // .. .. ==> 0XF8006024[8:7] = 0x00000000U
+ // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr_data = 0x0
+ // .. .. ==> 0XF8006024[24:9] = 0x00000000U
+ // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U
+ // .. .. ddrc_reg_mr_wr_busy = 0x0
+ // .. .. ==> 0XF8006024[25:25] = 0x00000000U
+ // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr_type = 0x0
+ // .. .. ==> 0XF8006024[26:26] = 0x00000000U
+ // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr_rdata_valid = 0x0
+ // .. .. ==> 0XF8006024[27:27] = 0x00000000U
+ // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU),
+ // .. .. reg_ddrc_final_wait_x32 = 0x7
+ // .. .. ==> 0XF8006028[6:0] = 0x00000007U
+ // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U
+ // .. .. reg_ddrc_pre_ocd_x32 = 0x0
+ // .. .. ==> 0XF8006028[10:7] = 0x00000000U
+ // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U
+ // .. .. reg_ddrc_t_mrd = 0x4
+ // .. .. ==> 0XF8006028[13:11] = 0x00000004U
+ // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
+ // .. .. reg_ddrc_emr2 = 0x8
+ // .. .. ==> 0XF800602C[15:0] = 0x00000008U
+ // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U
+ // .. .. reg_ddrc_emr3 = 0x0
+ // .. .. ==> 0XF800602C[31:16] = 0x00000000U
+ // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
+ // .. .. reg_ddrc_mr = 0x930
+ // .. .. ==> 0XF8006030[15:0] = 0x00000930U
+ // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U
+ // .. .. reg_ddrc_emr = 0x4
+ // .. .. ==> 0XF8006030[31:16] = 0x00000004U
+ // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
+ // .. .. reg_ddrc_burst_rdwr = 0x4
+ // .. .. ==> 0XF8006034[3:0] = 0x00000004U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U
+ // .. .. reg_ddrc_pre_cke_x1024 = 0x105
+ // .. .. ==> 0XF8006034[13:4] = 0x00000105U
+ // .. .. ==> MASK : 0x00003FF0U VAL : 0x00001050U
+ // .. .. reg_ddrc_post_cke_x1024 = 0x1
+ // .. .. ==> 0XF8006034[25:16] = 0x00000001U
+ // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U
+ // .. .. reg_ddrc_burstchop = 0x0
+ // .. .. ==> 0XF8006034[28:28] = 0x00000000U
+ // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U),
+ // .. .. reg_ddrc_force_low_pri_n = 0x0
+ // .. .. ==> 0XF8006038[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_dq = 0x0
+ // .. .. ==> 0XF8006038[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_debug_mode = 0x0
+ // .. .. ==> 0XF8006038[6:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U
+ // .. .. reg_phy_wr_level_start = 0x0
+ // .. .. ==> 0XF8006038[7:7] = 0x00000000U
+ // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. .. reg_phy_rd_level_start = 0x0
+ // .. .. ==> 0XF8006038[8:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. .. reg_phy_dq0_wait_t = 0x0
+ // .. .. ==> 0XF8006038[12:9] = 0x00000000U
+ // .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U),
+ // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
+ // .. .. ==> 0XF800603C[3:0] = 0x00000007U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U
+ // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
+ // .. .. ==> 0XF800603C[7:4] = 0x00000007U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U
+ // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
+ // .. .. ==> 0XF800603C[11:8] = 0x00000007U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U
+ // .. .. reg_ddrc_addrmap_col_b5 = 0x0
+ // .. .. ==> 0XF800603C[15:12] = 0x00000000U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b6 = 0x0
+ // .. .. ==> 0XF800603C[19:16] = 0x00000000U
+ // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
+ // .. .. reg_ddrc_addrmap_col_b2 = 0x0
+ // .. .. ==> 0XF8006040[3:0] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b3 = 0x0
+ // .. .. ==> 0XF8006040[7:4] = 0x00000000U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b4 = 0x0
+ // .. .. ==> 0XF8006040[11:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b7 = 0x0
+ // .. .. ==> 0XF8006040[15:12] = 0x00000000U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b8 = 0x0
+ // .. .. ==> 0XF8006040[19:16] = 0x00000000U
+ // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b9 = 0xf
+ // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
+ // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U
+ // .. .. reg_ddrc_addrmap_col_b10 = 0xf
+ // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
+ // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U
+ // .. .. reg_ddrc_addrmap_col_b11 = 0xf
+ // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
+ // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
+ // .. .. reg_ddrc_addrmap_row_b0 = 0x6
+ // .. .. ==> 0XF8006044[3:0] = 0x00000006U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U
+ // .. .. reg_ddrc_addrmap_row_b1 = 0x6
+ // .. .. ==> 0XF8006044[7:4] = 0x00000006U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U
+ // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
+ // .. .. ==> 0XF8006044[11:8] = 0x00000006U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U
+ // .. .. reg_ddrc_addrmap_row_b12 = 0x6
+ // .. .. ==> 0XF8006044[15:12] = 0x00000006U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U
+ // .. .. reg_ddrc_addrmap_row_b13 = 0x6
+ // .. .. ==> 0XF8006044[19:16] = 0x00000006U
+ // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U
+ // .. .. reg_ddrc_addrmap_row_b14 = 0xf
+ // .. .. ==> 0XF8006044[23:20] = 0x0000000FU
+ // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U
+ // .. .. reg_ddrc_addrmap_row_b15 = 0xf
+ // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
+ // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0FF66666U),
+ // .. .. reg_ddrc_rank0_rd_odt = 0x0
+ // .. .. ==> 0XF8006048[2:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U
+ // .. .. reg_ddrc_rank0_wr_odt = 0x1
+ // .. .. ==> 0XF8006048[5:3] = 0x00000001U
+ // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U
+ // .. .. reg_ddrc_rank1_rd_odt = 0x1
+ // .. .. ==> 0XF8006048[8:6] = 0x00000001U
+ // .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U
+ // .. .. reg_ddrc_rank1_wr_odt = 0x1
+ // .. .. ==> 0XF8006048[11:9] = 0x00000001U
+ // .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. .. reg_phy_rd_local_odt = 0x0
+ // .. .. ==> 0XF8006048[13:12] = 0x00000000U
+ // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U
+ // .. .. reg_phy_wr_local_odt = 0x3
+ // .. .. ==> 0XF8006048[15:14] = 0x00000003U
+ // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U
+ // .. .. reg_phy_idle_local_odt = 0x3
+ // .. .. ==> 0XF8006048[17:16] = 0x00000003U
+ // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U
+ // .. .. reg_ddrc_rank2_rd_odt = 0x0
+ // .. .. ==> 0XF8006048[20:18] = 0x00000000U
+ // .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U
+ // .. .. reg_ddrc_rank2_wr_odt = 0x0
+ // .. .. ==> 0XF8006048[23:21] = 0x00000000U
+ // .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U
+ // .. .. reg_ddrc_rank3_rd_odt = 0x0
+ // .. .. ==> 0XF8006048[26:24] = 0x00000000U
+ // .. .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_rank3_wr_odt = 0x0
+ // .. .. ==> 0XF8006048[29:27] = 0x00000000U
+ // .. .. ==> MASK : 0x38000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U),
+ // .. .. reg_phy_rd_cmd_to_data = 0x0
+ // .. .. ==> 0XF8006050[3:0] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
+ // .. .. reg_phy_wr_cmd_to_data = 0x0
+ // .. .. ==> 0XF8006050[7:4] = 0x00000000U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. .. reg_phy_rdc_we_to_re_delay = 0x8
+ // .. .. ==> 0XF8006050[11:8] = 0x00000008U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U
+ // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
+ // .. .. ==> 0XF8006050[15:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
+ // .. .. reg_phy_use_fixed_re = 0x1
+ // .. .. ==> 0XF8006050[16:16] = 0x00000001U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U
+ // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
+ // .. .. ==> 0XF8006050[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
+ // .. .. ==> 0XF8006050[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_phy_clk_stall_level = 0x0
+ // .. .. ==> 0XF8006050[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
+ // .. .. ==> 0XF8006050[27:24] = 0x00000007U
+ // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U
+ // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
+ // .. .. ==> 0XF8006050[31:28] = 0x00000007U
+ // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
+ // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1
+ // .. .. ==> 0XF8006058[7:0] = 0x00000001U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U
+ // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1
+ // .. .. ==> 0XF8006058[15:8] = 0x00000001U
+ // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U
+ // .. .. reg_ddrc_dis_dll_calib = 0x0
+ // .. .. ==> 0XF8006058[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U),
+ // .. .. reg_ddrc_rd_odt_delay = 0x3
+ // .. .. ==> 0XF800605C[3:0] = 0x00000003U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U
+ // .. .. reg_ddrc_wr_odt_delay = 0x0
+ // .. .. ==> 0XF800605C[7:4] = 0x00000000U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. .. reg_ddrc_rd_odt_hold = 0x0
+ // .. .. ==> 0XF800605C[11:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U
+ // .. .. reg_ddrc_wr_odt_hold = 0x5
+ // .. .. ==> 0XF800605C[15:12] = 0x00000005U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
+ // .. .. reg_ddrc_pageclose = 0x0
+ // .. .. ==> 0XF8006060[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_lpr_num_entries = 0x1f
+ // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
+ // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU
+ // .. .. reg_ddrc_auto_pre_en = 0x0
+ // .. .. ==> 0XF8006060[7:7] = 0x00000000U
+ // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. .. reg_ddrc_refresh_update_level = 0x0
+ // .. .. ==> 0XF8006060[8:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_wc = 0x0
+ // .. .. ==> 0XF8006060[9:9] = 0x00000000U
+ // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_collision_page_opt = 0x0
+ // .. .. ==> 0XF8006060[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_ddrc_selfref_en = 0x0
+ // .. .. ==> 0XF8006060[12:12] = 0x00000000U
+ // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
+ // .. .. reg_ddrc_go2critical_hysteresis = 0x0
+ // .. .. ==> 0XF8006064[12:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U
+ // .. .. reg_arb_go2critical_en = 0x1
+ // .. .. ==> 0XF8006064[17:17] = 0x00000001U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
+ // .. .. reg_ddrc_wrlvl_ww = 0x41
+ // .. .. ==> 0XF8006068[7:0] = 0x00000041U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U
+ // .. .. reg_ddrc_rdlvl_rr = 0x41
+ // .. .. ==> 0XF8006068[15:8] = 0x00000041U
+ // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U
+ // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
+ // .. .. ==> 0XF8006068[25:16] = 0x00000028U
+ // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
+ // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
+ // .. .. ==> 0XF800606C[7:0] = 0x00000010U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U
+ // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
+ // .. .. ==> 0XF800606C[15:8] = 0x00000016U
+ // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U
+ // .. ..
+ EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
+ // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1
+ // .. .. ==> 0XF8006078[3:0] = 0x00000001U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U
+ // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1
+ // .. .. ==> 0XF8006078[7:4] = 0x00000001U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U
+ // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1
+ // .. .. ==> 0XF8006078[11:8] = 0x00000001U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U
+ // .. .. reg_ddrc_t_cksre = 0x6
+ // .. .. ==> 0XF8006078[15:12] = 0x00000006U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U
+ // .. .. reg_ddrc_t_cksrx = 0x6
+ // .. .. ==> 0XF8006078[19:16] = 0x00000006U
+ // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U
+ // .. .. reg_ddrc_t_ckesr = 0x4
+ // .. .. ==> 0XF8006078[25:20] = 0x00000004U
+ // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U),
+ // .. .. reg_ddrc_t_ckpde = 0x2
+ // .. .. ==> 0XF800607C[3:0] = 0x00000002U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U
+ // .. .. reg_ddrc_t_ckpdx = 0x2
+ // .. .. ==> 0XF800607C[7:4] = 0x00000002U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
+ // .. .. reg_ddrc_t_ckdpde = 0x2
+ // .. .. ==> 0XF800607C[11:8] = 0x00000002U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
+ // .. .. reg_ddrc_t_ckdpdx = 0x2
+ // .. .. ==> 0XF800607C[15:12] = 0x00000002U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U
+ // .. .. reg_ddrc_t_ckcsx = 0x3
+ // .. .. ==> 0XF800607C[19:16] = 0x00000003U
+ // .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U),
+ // .. .. refresh_timer0_start_value_x32 = 0x0
+ // .. .. ==> 0XF80060A0[11:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U
+ // .. .. refresh_timer1_start_value_x32 = 0x8
+ // .. .. ==> 0XF80060A0[23:12] = 0x00000008U
+ // .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U),
+ // .. .. reg_ddrc_dis_auto_zq = 0x0
+ // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_ddr3 = 0x1
+ // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. .. reg_ddrc_t_mod = 0x200
+ // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
+ // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U
+ // .. .. reg_ddrc_t_zq_long_nop = 0x200
+ // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U
+ // .. .. reg_ddrc_t_zq_short_nop = 0x40
+ // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
+ // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
+ // .. .. t_zq_short_interval_x1024 = 0xcb73
+ // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U
+ // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U
+ // .. .. dram_rstn_x1024 = 0x69
+ // .. .. ==> 0XF80060A8[27:20] = 0x00000069U
+ // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
+ // .. .. deeppowerdown_en = 0x0
+ // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. deeppowerdown_to_x1024 = 0xff
+ // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
+ // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU
+ // .. ..
+ EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
+ // .. .. dfi_wrlvl_max_x1024 = 0xfff
+ // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
+ // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU
+ // .. .. dfi_rdlvl_max_x1024 = 0xfff
+ // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
+ // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U
+ // .. .. ddrc_reg_twrlvl_max_error = 0x0
+ // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
+ // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U
+ // .. .. ddrc_reg_trdlvl_max_error = 0x0
+ // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
+ // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dfi_wr_level_en = 0x1
+ // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
+ // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U
+ // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
+ // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
+ // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U
+ // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
+ // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
+ // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
+ // .. .. reg_ddrc_2t_delay = 0x0
+ // .. .. ==> 0XF80060B4[8:0] = 0x00000000U
+ // .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U
+ // .. .. reg_ddrc_skip_ocd = 0x1
+ // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
+ // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U
+ // .. .. reg_ddrc_dis_pre_bypass = 0x0
+ // .. .. ==> 0XF80060B4[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U),
+ // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
+ // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
+ // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U
+ // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
+ // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
+ // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U
+ // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
+ // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
+ // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
+ // .. .. START: RESET ECC ERROR
+ // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1
+ // .. .. ==> 0XF80060C4[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. Clear_Correctable_DRAM_ECC_error = 1
+ // .. .. ==> 0XF80060C4[1:1] = 0x00000001U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U),
+ // .. .. FINISH: RESET ECC ERROR
+ // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
+ // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
+ // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
+ // .. .. CORR_ECC_LOG_VALID = 0x0
+ // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. ECC_CORRECTED_BIT_NUM = 0x0
+ // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
+ // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
+ // .. .. UNCORR_ECC_LOG_VALID = 0x0
+ // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
+ // .. .. STAT_NUM_CORR_ERR = 0x0
+ // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
+ // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U
+ // .. .. STAT_NUM_UNCORR_ERR = 0x0
+ // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
+ // .. .. reg_ddrc_ecc_mode = 0x0
+ // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_scrub = 0x1
+ // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
+ // .. .. reg_phy_dif_on = 0x0
+ // .. .. ==> 0XF8006114[3:0] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
+ // .. .. reg_phy_dif_off = 0x0
+ // .. .. ==> 0XF8006114[7:4] = 0x00000000U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
+ // .. .. reg_phy_data_slice_in_use = 0x1
+ // .. .. ==> 0XF8006118[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_phy_rdlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006118[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006118[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_wrlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006118[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_tx = 0x0
+ // .. .. ==> 0XF8006118[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_rx = 0x0
+ // .. .. ==> 0XF8006118[5:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
+ // .. .. reg_phy_bist_shift_dq = 0x0
+ // .. .. ==> 0XF8006118[14:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
+ // .. .. reg_phy_bist_err_clr = 0x0
+ // .. .. ==> 0XF8006118[23:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
+ // .. .. reg_phy_dq_offset = 0x40
+ // .. .. ==> 0XF8006118[30:24] = 0x00000040U
+ // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U),
+ // .. .. reg_phy_data_slice_in_use = 0x1
+ // .. .. ==> 0XF800611C[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_phy_rdlvl_inc_mode = 0x0
+ // .. .. ==> 0XF800611C[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_inc_mode = 0x0
+ // .. .. ==> 0XF800611C[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_wrlvl_inc_mode = 0x0
+ // .. .. ==> 0XF800611C[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_tx = 0x0
+ // .. .. ==> 0XF800611C[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_rx = 0x0
+ // .. .. ==> 0XF800611C[5:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
+ // .. .. reg_phy_bist_shift_dq = 0x0
+ // .. .. ==> 0XF800611C[14:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
+ // .. .. reg_phy_bist_err_clr = 0x0
+ // .. .. ==> 0XF800611C[23:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
+ // .. .. reg_phy_dq_offset = 0x40
+ // .. .. ==> 0XF800611C[30:24] = 0x00000040U
+ // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U),
+ // .. .. reg_phy_data_slice_in_use = 0x1
+ // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_phy_rdlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_wrlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_tx = 0x0
+ // .. .. ==> 0XF8006120[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_rx = 0x0
+ // .. .. ==> 0XF8006120[5:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
+ // .. .. reg_phy_bist_shift_dq = 0x0
+ // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
+ // .. .. reg_phy_bist_err_clr = 0x0
+ // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
+ // .. .. reg_phy_dq_offset = 0x40
+ // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+ // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
+ // .. .. reg_phy_data_slice_in_use = 0x1
+ // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_phy_rdlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_wrlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_tx = 0x0
+ // .. .. ==> 0XF8006120[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_rx = 0x0
+ // .. .. ==> 0XF8006120[5:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
+ // .. .. reg_phy_bist_shift_dq = 0x0
+ // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
+ // .. .. reg_phy_bist_err_clr = 0x0
+ // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
+ // .. .. reg_phy_dq_offset = 0x40
+ // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+ // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U),
+ // .. .. reg_phy_data_slice_in_use = 0x1
+ // .. .. ==> 0XF8006124[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_phy_rdlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006124[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006124[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_wrlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006124[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_tx = 0x0
+ // .. .. ==> 0XF8006124[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_rx = 0x0
+ // .. .. ==> 0XF8006124[5:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
+ // .. .. reg_phy_bist_shift_dq = 0x0
+ // .. .. ==> 0XF8006124[14:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
+ // .. .. reg_phy_bist_err_clr = 0x0
+ // .. .. ==> 0XF8006124[23:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
+ // .. .. reg_phy_dq_offset = 0x40
+ // .. .. ==> 0XF8006124[30:24] = 0x00000040U
+ // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U),
+ // .. .. reg_phy_wrlvl_init_ratio = 0x3
+ // .. .. ==> 0XF800612C[9:0] = 0x00000003U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000003U
+ // .. .. reg_phy_gatelvl_init_ratio = 0xcf
+ // .. .. ==> 0XF800612C[19:10] = 0x000000CFU
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x00033C00U
+ // .. ..
+ EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00033C03U),
+ // .. .. reg_phy_wrlvl_init_ratio = 0x3
+ // .. .. ==> 0XF8006130[9:0] = 0x00000003U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000003U
+ // .. .. reg_phy_gatelvl_init_ratio = 0xd0
+ // .. .. ==> 0XF8006130[19:10] = 0x000000D0U
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x00034000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00034003U),
+ // .. .. reg_phy_wrlvl_init_ratio = 0x0
+ // .. .. ==> 0XF8006134[9:0] = 0x00000000U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_init_ratio = 0xbd
+ // .. .. ==> 0XF8006134[19:10] = 0x000000BDU
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002F400U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0002F400U),
+ // .. .. reg_phy_wrlvl_init_ratio = 0x0
+ // .. .. ==> 0XF8006138[9:0] = 0x00000000U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_init_ratio = 0xc1
+ // .. .. ==> 0XF8006138[19:10] = 0x000000C1U
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x00030400U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x00030400U),
+ // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+ // .. .. ==> 0XF8006140[9:0] = 0x00000035U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
+ // .. .. reg_phy_rd_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006140[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006140[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
+ // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+ // .. .. ==> 0XF8006144[9:0] = 0x00000035U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
+ // .. .. reg_phy_rd_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006144[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006144[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
+ // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+ // .. .. ==> 0XF8006148[9:0] = 0x00000035U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
+ // .. .. reg_phy_rd_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006148[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006148[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
+ // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+ // .. .. ==> 0XF800614C[9:0] = 0x00000035U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
+ // .. .. reg_phy_rd_dqs_slave_force = 0x0
+ // .. .. ==> 0XF800614C[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF800614C[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
+ // .. .. reg_phy_wr_dqs_slave_ratio = 0x83
+ // .. .. ==> 0XF8006154[9:0] = 0x00000083U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000083U
+ // .. .. reg_phy_wr_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006154[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006154[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000083U),
+ // .. .. reg_phy_wr_dqs_slave_ratio = 0x83
+ // .. .. ==> 0XF8006158[9:0] = 0x00000083U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000083U
+ // .. .. reg_phy_wr_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006158[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006158[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000083U),
+ // .. .. reg_phy_wr_dqs_slave_ratio = 0x7f
+ // .. .. ==> 0XF800615C[9:0] = 0x0000007FU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x0000007FU
+ // .. .. reg_phy_wr_dqs_slave_force = 0x0
+ // .. .. ==> 0XF800615C[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF800615C[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x0000007FU),
+ // .. .. reg_phy_wr_dqs_slave_ratio = 0x78
+ // .. .. ==> 0XF8006160[9:0] = 0x00000078U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000078U
+ // .. .. reg_phy_wr_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006160[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006160[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000078U),
+ // .. .. reg_phy_fifo_we_slave_ratio = 0x124
+ // .. .. ==> 0XF8006168[10:0] = 0x00000124U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000124U
+ // .. .. reg_phy_fifo_we_in_force = 0x0
+ // .. .. ==> 0XF8006168[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. reg_phy_fifo_we_in_delay = 0x0
+ // .. .. ==> 0XF8006168[20:12] = 0x00000000U
+ // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000124U),
+ // .. .. reg_phy_fifo_we_slave_ratio = 0x125
+ // .. .. ==> 0XF800616C[10:0] = 0x00000125U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000125U
+ // .. .. reg_phy_fifo_we_in_force = 0x0
+ // .. .. ==> 0XF800616C[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. reg_phy_fifo_we_in_delay = 0x0
+ // .. .. ==> 0XF800616C[20:12] = 0x00000000U
+ // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x00000125U),
+ // .. .. reg_phy_fifo_we_slave_ratio = 0x112
+ // .. .. ==> 0XF8006170[10:0] = 0x00000112U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000112U
+ // .. .. reg_phy_fifo_we_in_force = 0x0
+ // .. .. ==> 0XF8006170[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. reg_phy_fifo_we_in_delay = 0x0
+ // .. .. ==> 0XF8006170[20:12] = 0x00000000U
+ // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000112U),
+ // .. .. reg_phy_fifo_we_slave_ratio = 0x116
+ // .. .. ==> 0XF8006174[10:0] = 0x00000116U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000116U
+ // .. .. reg_phy_fifo_we_in_force = 0x0
+ // .. .. ==> 0XF8006174[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. reg_phy_fifo_we_in_delay = 0x0
+ // .. .. ==> 0XF8006174[20:12] = 0x00000000U
+ // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000116U),
+ // .. .. reg_phy_wr_data_slave_ratio = 0xc3
+ // .. .. ==> 0XF800617C[9:0] = 0x000000C3U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C3U
+ // .. .. reg_phy_wr_data_slave_force = 0x0
+ // .. .. ==> 0XF800617C[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_data_slave_delay = 0x0
+ // .. .. ==> 0XF800617C[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000C3U),
+ // .. .. reg_phy_wr_data_slave_ratio = 0xc3
+ // .. .. ==> 0XF8006180[9:0] = 0x000000C3U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C3U
+ // .. .. reg_phy_wr_data_slave_force = 0x0
+ // .. .. ==> 0XF8006180[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_data_slave_delay = 0x0
+ // .. .. ==> 0XF8006180[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000C3U),
+ // .. .. reg_phy_wr_data_slave_ratio = 0xbf
+ // .. .. ==> 0XF8006184[9:0] = 0x000000BFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000BFU
+ // .. .. reg_phy_wr_data_slave_force = 0x0
+ // .. .. ==> 0XF8006184[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_data_slave_delay = 0x0
+ // .. .. ==> 0XF8006184[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000BFU),
+ // .. .. reg_phy_wr_data_slave_ratio = 0xb8
+ // .. .. ==> 0XF8006188[9:0] = 0x000000B8U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000B8U
+ // .. .. reg_phy_wr_data_slave_force = 0x0
+ // .. .. ==> 0XF8006188[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_data_slave_delay = 0x0
+ // .. .. ==> 0XF8006188[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000B8U),
+ // .. .. reg_phy_loopback = 0x0
+ // .. .. ==> 0XF8006190[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_phy_bl2 = 0x0
+ // .. .. ==> 0XF8006190[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_at_spd_atpg = 0x0
+ // .. .. ==> 0XF8006190[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_bist_enable = 0x0
+ // .. .. ==> 0XF8006190[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_bist_force_err = 0x0
+ // .. .. ==> 0XF8006190[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reg_phy_bist_mode = 0x0
+ // .. .. ==> 0XF8006190[6:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U
+ // .. .. reg_phy_invert_clkout = 0x1
+ // .. .. ==> 0XF8006190[7:7] = 0x00000001U
+ // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0
+ // .. .. ==> 0XF8006190[8:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. .. reg_phy_sel_logic = 0x0
+ // .. .. ==> 0XF8006190[9:9] = 0x00000000U
+ // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U
+ // .. .. reg_phy_ctrl_slave_ratio = 0x100
+ // .. .. ==> 0XF8006190[19:10] = 0x00000100U
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U
+ // .. .. reg_phy_ctrl_slave_force = 0x0
+ // .. .. ==> 0XF8006190[20:20] = 0x00000000U
+ // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U
+ // .. .. reg_phy_ctrl_slave_delay = 0x0
+ // .. .. ==> 0XF8006190[27:21] = 0x00000000U
+ // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U
+ // .. .. reg_phy_use_rank0_delays = 0x1
+ // .. .. ==> 0XF8006190[28:28] = 0x00000001U
+ // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
+ // .. .. reg_phy_lpddr = 0x0
+ // .. .. ==> 0XF8006190[29:29] = 0x00000000U
+ // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U
+ // .. .. reg_phy_cmd_latency = 0x0
+ // .. .. ==> 0XF8006190[30:30] = 0x00000000U
+ // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U
+ // .. .. reg_phy_int_lpbk = 0x0
+ // .. .. ==> 0XF8006190[31:31] = 0x00000000U
+ // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U),
+ // .. .. reg_phy_wr_rl_delay = 0x2
+ // .. .. ==> 0XF8006194[4:0] = 0x00000002U
+ // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U
+ // .. .. reg_phy_rd_rl_delay = 0x4
+ // .. .. ==> 0XF8006194[9:5] = 0x00000004U
+ // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U
+ // .. .. reg_phy_dll_lock_diff = 0xf
+ // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
+ // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U
+ // .. .. reg_phy_use_wr_level = 0x1
+ // .. .. ==> 0XF8006194[14:14] = 0x00000001U
+ // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U
+ // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
+ // .. .. ==> 0XF8006194[15:15] = 0x00000001U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U
+ // .. .. reg_phy_use_rd_data_eye_level = 0x1
+ // .. .. ==> 0XF8006194[16:16] = 0x00000001U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U
+ // .. .. reg_phy_dis_calib_rst = 0x0
+ // .. .. ==> 0XF8006194[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_phy_ctrl_slave_delay = 0x0
+ // .. .. ==> 0XF8006194[19:18] = 0x00000000U
+ // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
+ // .. .. reg_arb_page_addr_mask = 0x0
+ // .. .. ==> 0XF8006204[31:0] = 0x00000000U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
+ // .. .. reg_arb_pri_wr_portn = 0x3ff
+ // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_wr_portn = 0x0
+ // .. .. ==> 0XF8006208[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+ // .. .. ==> 0XF8006208[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+ // .. .. ==> 0XF8006208[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_rmw_portn = 0x1
+ // .. .. ==> 0XF8006208[19:19] = 0x00000001U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU),
+ // .. .. reg_arb_pri_wr_portn = 0x3ff
+ // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_wr_portn = 0x0
+ // .. .. ==> 0XF800620C[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+ // .. .. ==> 0XF800620C[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+ // .. .. ==> 0XF800620C[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_rmw_portn = 0x1
+ // .. .. ==> 0XF800620C[19:19] = 0x00000001U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU),
+ // .. .. reg_arb_pri_wr_portn = 0x3ff
+ // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_wr_portn = 0x0
+ // .. .. ==> 0XF8006210[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+ // .. .. ==> 0XF8006210[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+ // .. .. ==> 0XF8006210[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_rmw_portn = 0x1
+ // .. .. ==> 0XF8006210[19:19] = 0x00000001U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU),
+ // .. .. reg_arb_pri_wr_portn = 0x3ff
+ // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_wr_portn = 0x0
+ // .. .. ==> 0XF8006214[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+ // .. .. ==> 0XF8006214[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+ // .. .. ==> 0XF8006214[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_rmw_portn = 0x1
+ // .. .. ==> 0XF8006214[19:19] = 0x00000001U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU),
+ // .. .. reg_arb_pri_rd_portn = 0x3ff
+ // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_rd_portn = 0x0
+ // .. .. ==> 0XF8006218[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+ // .. .. ==> 0XF8006218[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+ // .. .. ==> 0XF8006218[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_set_hpr_rd_portn = 0x0
+ // .. .. ==> 0XF8006218[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
+ // .. .. reg_arb_pri_rd_portn = 0x3ff
+ // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_rd_portn = 0x0
+ // .. .. ==> 0XF800621C[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+ // .. .. ==> 0XF800621C[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+ // .. .. ==> 0XF800621C[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_set_hpr_rd_portn = 0x0
+ // .. .. ==> 0XF800621C[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
+ // .. .. reg_arb_pri_rd_portn = 0x3ff
+ // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_rd_portn = 0x0
+ // .. .. ==> 0XF8006220[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+ // .. .. ==> 0XF8006220[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+ // .. .. ==> 0XF8006220[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_set_hpr_rd_portn = 0x0
+ // .. .. ==> 0XF8006220[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
+ // .. .. reg_arb_pri_rd_portn = 0x3ff
+ // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_rd_portn = 0x0
+ // .. .. ==> 0XF8006224[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+ // .. .. ==> 0XF8006224[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+ // .. .. ==> 0XF8006224[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_set_hpr_rd_portn = 0x0
+ // .. .. ==> 0XF8006224[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
+ // .. .. reg_ddrc_lpddr2 = 0x0
+ // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_per_bank_refresh = 0x0
+ // .. .. ==> 0XF80062A8[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_ddrc_derate_enable = 0x0
+ // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr4_margin = 0x0
+ // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U),
+ // .. .. reg_ddrc_mr4_read_interval = 0x0
+ // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
+ // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
+ // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U
+ // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
+ // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
+ // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U
+ // .. .. reg_ddrc_t_mrw = 0x5
+ // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
+ // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8
+ // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U
+ // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
+ // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
+ // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U
+ // .. ..
+ EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
+ // .. .. START: POLL ON DCI STATUS
+ // .. .. DONE = 1
+ // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
+ // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U
+ // .. ..
+ EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+ // .. .. FINISH: POLL ON DCI STATUS
+ // .. .. START: UNLOCK DDR
+ // .. .. reg_ddrc_soft_rstb = 0x1
+ // .. .. ==> 0XF8006000[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_ddrc_powerdown_en = 0x0
+ // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_ddrc_data_bus_width = 0x0
+ // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U
+ // .. .. reg_ddrc_burst8_refresh = 0x0
+ // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U
+ // .. .. reg_ddrc_rdwr_idle_gap = 1
+ // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+ // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U
+ // .. .. reg_ddrc_dis_rd_bypass = 0x0
+ // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+ // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_act_bypass = 0x0
+ // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_auto_refresh = 0x0
+ // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
+ // .. .. FINISH: UNLOCK DDR
+ // .. .. START: CHECK DDR STATUS
+ // .. .. ddrc_reg_operating_mode = 1
+ // .. .. ==> 0XF8006054[2:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U
+ // .. ..
+ EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+ // .. .. FINISH: CHECK DDR STATUS
+ // .. FINISH: DDR INITIALIZATION
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_mio_init_data_2_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: OCM REMAPPING
+ // .. FINISH: OCM REMAPPING
+ // .. START: DDRIOB SETTINGS
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B40[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x0
+ // .. ==> 0XF8000B40[2:1] = 0x00000000U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000000U
+ // .. DCI_UPDATE = 0x0
+ // .. ==> 0XF8000B40[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x0
+ // .. ==> 0XF8000B40[4:4] = 0x00000000U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. DCR_TYPE = 0x0
+ // .. ==> 0XF8000B40[6:5] = 0x00000000U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000000U
+ // .. IBUF_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B40[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B40[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B40[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B40[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B44[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x0
+ // .. ==> 0XF8000B44[2:1] = 0x00000000U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000000U
+ // .. DCI_UPDATE = 0x0
+ // .. ==> 0XF8000B44[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x0
+ // .. ==> 0XF8000B44[4:4] = 0x00000000U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. DCR_TYPE = 0x0
+ // .. ==> 0XF8000B44[6:5] = 0x00000000U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000000U
+ // .. IBUF_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B44[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B44[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B44[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B44[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B48[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x1
+ // .. ==> 0XF8000B48[2:1] = 0x00000001U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000002U
+ // .. DCI_UPDATE = 0x0
+ // .. ==> 0XF8000B48[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x1
+ // .. ==> 0XF8000B48[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. DCR_TYPE = 0x3
+ // .. ==> 0XF8000B48[6:5] = 0x00000003U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000060U
+ // .. IBUF_DISABLE_MODE = 0
+ // .. ==> 0XF8000B48[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0
+ // .. ==> 0XF8000B48[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B48[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B48[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B4C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x1
+ // .. ==> 0XF8000B4C[2:1] = 0x00000001U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000002U
+ // .. DCI_UPDATE = 0x0
+ // .. ==> 0XF8000B4C[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x1
+ // .. ==> 0XF8000B4C[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. DCR_TYPE = 0x3
+ // .. ==> 0XF8000B4C[6:5] = 0x00000003U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000060U
+ // .. IBUF_DISABLE_MODE = 0
+ // .. ==> 0XF8000B4C[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0
+ // .. ==> 0XF8000B4C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B4C[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B4C[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B50[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x2
+ // .. ==> 0XF8000B50[2:1] = 0x00000002U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000004U
+ // .. DCI_UPDATE = 0x0
+ // .. ==> 0XF8000B50[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x1
+ // .. ==> 0XF8000B50[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. DCR_TYPE = 0x3
+ // .. ==> 0XF8000B50[6:5] = 0x00000003U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000060U
+ // .. IBUF_DISABLE_MODE = 0
+ // .. ==> 0XF8000B50[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0
+ // .. ==> 0XF8000B50[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B50[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B50[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B54[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x2
+ // .. ==> 0XF8000B54[2:1] = 0x00000002U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000004U
+ // .. DCI_UPDATE = 0x0
+ // .. ==> 0XF8000B54[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x1
+ // .. ==> 0XF8000B54[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. DCR_TYPE = 0x3
+ // .. ==> 0XF8000B54[6:5] = 0x00000003U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000060U
+ // .. IBUF_DISABLE_MODE = 0
+ // .. ==> 0XF8000B54[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0
+ // .. ==> 0XF8000B54[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B54[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B54[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B58[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x0
+ // .. ==> 0XF8000B58[2:1] = 0x00000000U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000000U
+ // .. DCI_UPDATE = 0x0
+ // .. ==> 0XF8000B58[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x0
+ // .. ==> 0XF8000B58[4:4] = 0x00000000U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. DCR_TYPE = 0x0
+ // .. ==> 0XF8000B58[6:5] = 0x00000000U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000000U
+ // .. IBUF_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B58[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B58[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B58[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B58[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
+ // .. DRIVE_P = 0x1c
+ // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
+ // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
+ // .. DRIVE_N = 0xc
+ // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
+ // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
+ // .. SLEW_P = 0x3
+ // .. ==> 0XF8000B5C[18:14] = 0x00000003U
+ // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U
+ // .. SLEW_N = 0x3
+ // .. ==> 0XF8000B5C[23:19] = 0x00000003U
+ // .. ==> MASK : 0x00F80000U VAL : 0x00180000U
+ // .. GTL = 0x0
+ // .. ==> 0XF8000B5C[26:24] = 0x00000000U
+ // .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. RTERM = 0x0
+ // .. ==> 0XF8000B5C[31:27] = 0x00000000U
+ // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
+ // .. DRIVE_P = 0x1c
+ // .. ==> 0XF8000B60[6:0] = 0x0000001CU
+ // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
+ // .. DRIVE_N = 0xc
+ // .. ==> 0XF8000B60[13:7] = 0x0000000CU
+ // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
+ // .. SLEW_P = 0x6
+ // .. ==> 0XF8000B60[18:14] = 0x00000006U
+ // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
+ // .. SLEW_N = 0x1f
+ // .. ==> 0XF8000B60[23:19] = 0x0000001FU
+ // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
+ // .. GTL = 0x0
+ // .. ==> 0XF8000B60[26:24] = 0x00000000U
+ // .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. RTERM = 0x0
+ // .. ==> 0XF8000B60[31:27] = 0x00000000U
+ // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
+ // .. DRIVE_P = 0x1c
+ // .. ==> 0XF8000B64[6:0] = 0x0000001CU
+ // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
+ // .. DRIVE_N = 0xc
+ // .. ==> 0XF8000B64[13:7] = 0x0000000CU
+ // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
+ // .. SLEW_P = 0x6
+ // .. ==> 0XF8000B64[18:14] = 0x00000006U
+ // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
+ // .. SLEW_N = 0x1f
+ // .. ==> 0XF8000B64[23:19] = 0x0000001FU
+ // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
+ // .. GTL = 0x0
+ // .. ==> 0XF8000B64[26:24] = 0x00000000U
+ // .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. RTERM = 0x0
+ // .. ==> 0XF8000B64[31:27] = 0x00000000U
+ // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
+ // .. DRIVE_P = 0x1c
+ // .. ==> 0XF8000B68[6:0] = 0x0000001CU
+ // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
+ // .. DRIVE_N = 0xc
+ // .. ==> 0XF8000B68[13:7] = 0x0000000CU
+ // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
+ // .. SLEW_P = 0x6
+ // .. ==> 0XF8000B68[18:14] = 0x00000006U
+ // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
+ // .. SLEW_N = 0x1f
+ // .. ==> 0XF8000B68[23:19] = 0x0000001FU
+ // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
+ // .. GTL = 0x0
+ // .. ==> 0XF8000B68[26:24] = 0x00000000U
+ // .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. RTERM = 0x0
+ // .. ==> 0XF8000B68[31:27] = 0x00000000U
+ // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
+ // .. VREF_INT_EN = 0x1
+ // .. ==> 0XF8000B6C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. VREF_SEL = 0x4
+ // .. ==> 0XF8000B6C[4:1] = 0x00000004U
+ // .. ==> MASK : 0x0000001EU VAL : 0x00000008U
+ // .. VREF_EXT_EN = 0x0
+ // .. ==> 0XF8000B6C[6:5] = 0x00000000U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000000U
+ // .. VREF_PULLUP_EN = 0x0
+ // .. ==> 0XF8000B6C[8:7] = 0x00000000U
+ // .. ==> MASK : 0x00000180U VAL : 0x00000000U
+ // .. REFIO_EN = 0x1
+ // .. ==> 0XF8000B6C[9:9] = 0x00000001U
+ // .. ==> MASK : 0x00000200U VAL : 0x00000200U
+ // .. REFIO_TEST = 0x3
+ // .. ==> 0XF8000B6C[11:10] = 0x00000003U
+ // .. ==> MASK : 0x00000C00U VAL : 0x00000C00U
+ // .. REFIO_PULLUP_EN = 0x0
+ // .. ==> 0XF8000B6C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DRST_B_PULLUP_EN = 0x0
+ // .. ==> 0XF8000B6C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // .. CKE_PULLUP_EN = 0x0
+ // .. ==> 0XF8000B6C[14:14] = 0x00000000U
+ // .. ==> MASK : 0x00004000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000E09U),
+ // .. .. START: ASSERT RESET
+ // .. .. RESET = 1
+ // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. VRN_OUT = 0x1
+ // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U),
+ // .. .. FINISH: ASSERT RESET
+ // .. .. START: DEASSERT RESET
+ // .. .. RESET = 0
+ // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. VRN_OUT = 0x1
+ // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
+ // .. .. FINISH: DEASSERT RESET
+ // .. .. RESET = 0x1
+ // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ENABLE = 0x1
+ // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. .. VRP_TRI = 0x0
+ // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. VRN_TRI = 0x0
+ // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. VRP_OUT = 0x0
+ // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. VRN_OUT = 0x1
+ // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
+ // .. .. NREF_OPT1 = 0x0
+ // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
+ // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U
+ // .. .. NREF_OPT2 = 0x0
+ // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U
+ // .. .. NREF_OPT4 = 0x1
+ // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
+ // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U
+ // .. .. PREF_OPT1 = 0x0
+ // .. .. ==> 0XF8000B70[16:14] = 0x00000000U
+ // .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U
+ // .. .. PREF_OPT2 = 0x0
+ // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
+ // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U
+ // .. .. UPDATE_CONTROL = 0x0
+ // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
+ // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U
+ // .. .. INIT_COMPLETE = 0x0
+ // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
+ // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U
+ // .. .. TST_CLK = 0x0
+ // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
+ // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U
+ // .. .. TST_HLN = 0x0
+ // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
+ // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U
+ // .. .. TST_HLP = 0x0
+ // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
+ // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U
+ // .. .. TST_RST = 0x0
+ // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
+ // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
+ // .. .. INT_DCI_EN = 0x0
+ // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
+ // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U),
+ // .. FINISH: DDRIOB SETTINGS
+ // .. START: MIO PROGRAMMING
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000700[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000700[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000700[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000700[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000700[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000700[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000700[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000700[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000700[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000704[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000704[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000704[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000704[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000704[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000704[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000704[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000704[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000704[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00000702U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000708[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000708[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000708[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000708[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000708[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000708[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000708[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000708[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000708[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000702U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800070C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF800070C[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800070C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800070C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800070C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF800070C[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 3
+ // .. ==> 0XF800070C[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF800070C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800070C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000702U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000710[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000710[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000710[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000710[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000710[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000710[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000710[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000710[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000710[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000702U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000714[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000714[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000714[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000714[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000714[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000714[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000714[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000714[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000714[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000702U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000718[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000718[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000718[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000718[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000718[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000718[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000718[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000718[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000718[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000702U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800071C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800071C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800071C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800071C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800071C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800071C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF800071C[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF800071C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800071C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000720[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000720[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000720[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000720[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000720[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000720[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000720[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000720[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000720[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000700U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000724[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000724[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000724[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000724[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000724[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000724[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000724[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000724[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000724[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000728[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000728[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000728[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000728[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000728[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000728[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000728[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000728[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000728[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800072C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800072C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800072C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800072C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800072C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800072C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF800072C[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF800072C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800072C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000730[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000730[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000730[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000730[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000730[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000730[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000730[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000730[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000730[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000734[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000734[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000734[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000734[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000734[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000734[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000734[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000734[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000734[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000738[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000738[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000738[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000738[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000738[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000738[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000738[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000738[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000738[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800073C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800073C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800073C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800073C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800073C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800073C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF800073C[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF800073C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800073C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000740[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000740[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000740[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000740[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000740[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000740[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000740[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000740[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000740[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000302U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000744[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000744[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000744[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000744[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000744[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000744[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000744[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000744[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000744[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000302U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000748[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000748[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000748[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000748[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000748[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000748[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000748[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000748[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000748[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000302U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800074C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF800074C[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800074C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800074C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800074C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF800074C[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF800074C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800074C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800074C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000302U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000750[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000750[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000750[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000750[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000750[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000750[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000750[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000750[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000750[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000302U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000754[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000754[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000754[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000754[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000754[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000754[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000754[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000754[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000754[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000302U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000758[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000758[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000758[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000758[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000758[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000758[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000758[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000758[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000758[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000303U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF800075C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF800075C[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800075C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800075C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800075C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF800075C[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF800075C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800075C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800075C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000303U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000760[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000760[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000760[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000760[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000760[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000760[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000760[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000760[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000760[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000303U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000764[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000764[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000764[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000764[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000764[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000764[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000764[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000764[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000764[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000303U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000768[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000768[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000768[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000768[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000768[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000768[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000768[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000768[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000768[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000303U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF800076C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF800076C[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800076C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800076C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800076C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF800076C[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF800076C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800076C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800076C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000303U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000770[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000770[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000770[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000770[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000770[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000770[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000770[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000770[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000770[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000304U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000774[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000774[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000774[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000774[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000774[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000774[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000774[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000774[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000774[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000305U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000778[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000778[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000778[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000778[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000778[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000778[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000778[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000778[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000778[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000304U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF800077C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800077C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF800077C[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800077C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800077C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF800077C[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF800077C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800077C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800077C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000305U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000780[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000780[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000780[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000780[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000780[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000780[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000780[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000780[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000780[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000304U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000784[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000784[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000784[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000784[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000784[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000784[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000784[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000784[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000784[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000304U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000788[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000788[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000788[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000788[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000788[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000788[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000788[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000788[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000788[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000304U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800078C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800078C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF800078C[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800078C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800078C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF800078C[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF800078C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800078C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800078C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000304U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000790[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000790[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000790[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000790[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000790[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000790[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000790[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000790[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000790[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000305U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000794[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000794[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000794[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000794[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000794[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000794[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000794[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000794[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000794[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000304U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000798[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000798[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000798[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000798[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000798[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000798[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000798[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000798[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000798[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000304U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800079C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800079C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF800079C[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800079C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800079C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF800079C[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF800079C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800079C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800079C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000304U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007A0[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007A0[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007A0[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007A0[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007A0[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 1
+ // .. ==> 0XF80007A0[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007A0[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007A0[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007A0[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000380U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007A4[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007A4[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007A4[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007A4[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007A4[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 1
+ // .. ==> 0XF80007A4[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007A4[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007A4[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007A4[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000380U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007A8[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007A8[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007A8[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007A8[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007A8[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 1
+ // .. ==> 0XF80007A8[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007A8[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007A8[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007A8[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000380U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007AC[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007AC[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007AC[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007AC[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007AC[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 1
+ // .. ==> 0XF80007AC[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007AC[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007AC[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007AC[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000380U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007B0[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007B0[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007B0[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007B0[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007B0[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 1
+ // .. ==> 0XF80007B0[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007B0[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007B0[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007B0[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000380U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007B4[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007B4[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007B4[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007B4[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007B4[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 1
+ // .. ==> 0XF80007B4[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007B4[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007B4[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007B4[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000380U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF80007B8[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. Speed = 0
+ // .. ==> 0XF80007B8[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007B8[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007B8[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007B8[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007B8, 0x00003F01U ,0x00000201U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF80007BC[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. Speed = 0
+ // .. ==> 0XF80007BC[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007BC[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007BC[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007BC[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007BC, 0x00003F01U ,0x00000201U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007C0[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007C0[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007C0[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007C0[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 7
+ // .. ==> 0XF80007C0[7:5] = 0x00000007U
+ // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U
+ // .. Speed = 0
+ // .. ==> 0XF80007C0[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007C0[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007C0[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007C0[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF80007C4[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007C4[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007C4[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007C4[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 7
+ // .. ==> 0XF80007C4[7:5] = 0x00000007U
+ // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U
+ // .. Speed = 0
+ // .. ==> 0XF80007C4[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007C4[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007C4[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007C4[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF80007C8[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007C8[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007C8[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007C8[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF80007C8[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF80007C8[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007C8[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007C8[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007C8[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00000201U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF80007CC[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007CC[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007CC[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007CC[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF80007CC[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF80007CC[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007CC[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007CC[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007CC[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00000201U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007D0[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007D0[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007D0[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007D0[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007D0[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007D0[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007D0[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007D0[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007D0[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007D4[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007D4[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007D4[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007D4[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007D4[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007D4[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007D4[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007D4[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007D4[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U),
+ // .. SDIO0_WP_SEL = 46
+ // .. ==> 0XF8000830[5:0] = 0x0000002EU
+ // .. ==> MASK : 0x0000003FU VAL : 0x0000002EU
+ // .. SDIO0_CD_SEL = 47
+ // .. ==> 0XF8000830[21:16] = 0x0000002FU
+ // .. ==> MASK : 0x003F0000U VAL : 0x002F0000U
+ // ..
+ EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x002F002EU),
+ // .. FINISH: MIO PROGRAMMING
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_peripherals_init_data_2_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+ // .. IBUF_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B48[7:7] = 0x00000001U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. TERM_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B48[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // ..
+ EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
+ // .. IBUF_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B4C[7:7] = 0x00000001U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. TERM_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B4C[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // ..
+ EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
+ // .. IBUF_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B50[7:7] = 0x00000001U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. TERM_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B50[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // ..
+ EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
+ // .. IBUF_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B54[7:7] = 0x00000001U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. TERM_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B54[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // ..
+ EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
+ // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // .. START: SRAM/NOR SET OPMODE
+ // .. FINISH: SRAM/NOR SET OPMODE
+ // .. START: UART REGISTERS
+ // .. BDIV = 0x6
+ // .. ==> 0XE0001034[7:0] = 0x00000006U
+ // .. ==> MASK : 0x000000FFU VAL : 0x00000006U
+ // ..
+ EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
+ // .. CD = 0x3e
+ // .. ==> 0XE0001018[15:0] = 0x0000003EU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU
+ // ..
+ EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
+ // .. STPBRK = 0x0
+ // .. ==> 0XE0001000[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. STTBRK = 0x0
+ // .. ==> 0XE0001000[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. RSTTO = 0x0
+ // .. ==> 0XE0001000[6:6] = 0x00000000U
+ // .. ==> MASK : 0x00000040U VAL : 0x00000000U
+ // .. TXDIS = 0x0
+ // .. ==> 0XE0001000[5:5] = 0x00000000U
+ // .. ==> MASK : 0x00000020U VAL : 0x00000000U
+ // .. TXEN = 0x1
+ // .. ==> 0XE0001000[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. RXDIS = 0x0
+ // .. ==> 0XE0001000[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. RXEN = 0x1
+ // .. ==> 0XE0001000[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. TXRES = 0x1
+ // .. ==> 0XE0001000[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. RXRES = 0x1
+ // .. ==> 0XE0001000[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // ..
+ EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
+ // .. IRMODE = 0x0
+ // .. ==> 0XE0001004[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. UCLKEN = 0x0
+ // .. ==> 0XE0001004[10:10] = 0x00000000U
+ // .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. CHMODE = 0x0
+ // .. ==> 0XE0001004[9:8] = 0x00000000U
+ // .. ==> MASK : 0x00000300U VAL : 0x00000000U
+ // .. NBSTOP = 0x0
+ // .. ==> 0XE0001004[7:6] = 0x00000000U
+ // .. ==> MASK : 0x000000C0U VAL : 0x00000000U
+ // .. PAR = 0x4
+ // .. ==> 0XE0001004[5:3] = 0x00000004U
+ // .. ==> MASK : 0x00000038U VAL : 0x00000020U
+ // .. CHRL = 0x0
+ // .. ==> 0XE0001004[2:1] = 0x00000000U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000000U
+ // .. CLKS = 0x0
+ // .. ==> 0XE0001004[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U),
+ // .. FINISH: UART REGISTERS
+ // .. START: QSPI REGISTERS
+ // .. Holdb_dr = 1
+ // .. ==> 0XE000D000[19:19] = 0x00000001U
+ // .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // ..
+ EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
+ // .. FINISH: QSPI REGISTERS
+ // .. START: PL POWER ON RESET REGISTERS
+ // .. PCFG_POR_CNT_4K = 0
+ // .. ==> 0XF8007000[29:29] = 0x00000000U
+ // .. ==> MASK : 0x20000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
+ // .. FINISH: PL POWER ON RESET REGISTERS
+ // .. START: SMC TIMING CALCULATION REGISTER UPDATE
+ // .. .. START: NAND SET CYCLE
+ // .. .. FINISH: NAND SET CYCLE
+ // .. .. START: OPMODE
+ // .. .. FINISH: OPMODE
+ // .. .. START: DIRECT COMMAND
+ // .. .. FINISH: DIRECT COMMAND
+ // .. .. START: SRAM/NOR CS0 SET CYCLE
+ // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
+ // .. .. START: DIRECT COMMAND
+ // .. .. FINISH: DIRECT COMMAND
+ // .. .. START: NOR CS0 BASE ADDRESS
+ // .. .. FINISH: NOR CS0 BASE ADDRESS
+ // .. .. START: SRAM/NOR CS1 SET CYCLE
+ // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
+ // .. .. START: DIRECT COMMAND
+ // .. .. FINISH: DIRECT COMMAND
+ // .. .. START: NOR CS1 BASE ADDRESS
+ // .. .. FINISH: NOR CS1 BASE ADDRESS
+ // .. .. START: USB RESET
+ // .. .. .. START: USB0 RESET
+ // .. .. .. .. START: DIR MODE BANK 0
+ // .. .. .. .. FINISH: DIR MODE BANK 0
+ // .. .. .. .. START: DIR MODE BANK 1
+ // .. .. .. .. FINISH: DIR MODE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. START: OUTPUT ENABLE BANK 0
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+ // .. .. .. .. START: OUTPUT ENABLE BANK 1
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. START: ADD 1 MS DELAY
+ // .. .. .. ..
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ // .. .. .. .. FINISH: ADD 1 MS DELAY
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. FINISH: USB0 RESET
+ // .. .. .. START: USB1 RESET
+ // .. .. .. .. START: DIR MODE BANK 0
+ // .. .. .. .. FINISH: DIR MODE BANK 0
+ // .. .. .. .. START: DIR MODE BANK 1
+ // .. .. .. .. FINISH: DIR MODE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. START: OUTPUT ENABLE BANK 0
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+ // .. .. .. .. START: OUTPUT ENABLE BANK 1
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. START: ADD 1 MS DELAY
+ // .. .. .. ..
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ // .. .. .. .. FINISH: ADD 1 MS DELAY
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. FINISH: USB1 RESET
+ // .. .. FINISH: USB RESET
+ // .. .. START: ENET RESET
+ // .. .. .. START: ENET0 RESET
+ // .. .. .. .. START: DIR MODE BANK 0
+ // .. .. .. .. FINISH: DIR MODE BANK 0
+ // .. .. .. .. START: DIR MODE BANK 1
+ // .. .. .. .. FINISH: DIR MODE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. START: OUTPUT ENABLE BANK 0
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+ // .. .. .. .. START: OUTPUT ENABLE BANK 1
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. START: ADD 1 MS DELAY
+ // .. .. .. ..
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ // .. .. .. .. FINISH: ADD 1 MS DELAY
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. FINISH: ENET0 RESET
+ // .. .. .. START: ENET1 RESET
+ // .. .. .. .. START: DIR MODE BANK 0
+ // .. .. .. .. FINISH: DIR MODE BANK 0
+ // .. .. .. .. START: DIR MODE BANK 1
+ // .. .. .. .. FINISH: DIR MODE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. START: OUTPUT ENABLE BANK 0
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+ // .. .. .. .. START: OUTPUT ENABLE BANK 1
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. START: ADD 1 MS DELAY
+ // .. .. .. ..
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ // .. .. .. .. FINISH: ADD 1 MS DELAY
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. FINISH: ENET1 RESET
+ // .. .. FINISH: ENET RESET
+ // .. .. START: I2C RESET
+ // .. .. .. START: I2C0 RESET
+ // .. .. .. .. START: DIR MODE GPIO BANK0
+ // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+ // .. .. .. .. START: DIR MODE GPIO BANK1
+ // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. START: OUTPUT ENABLE
+ // .. .. .. .. FINISH: OUTPUT ENABLE
+ // .. .. .. .. START: OUTPUT ENABLE
+ // .. .. .. .. FINISH: OUTPUT ENABLE
+ // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. START: ADD 1 MS DELAY
+ // .. .. .. ..
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ // .. .. .. .. FINISH: ADD 1 MS DELAY
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. FINISH: I2C0 RESET
+ // .. .. .. START: I2C1 RESET
+ // .. .. .. .. START: DIR MODE GPIO BANK0
+ // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+ // .. .. .. .. START: DIR MODE GPIO BANK1
+ // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. START: OUTPUT ENABLE
+ // .. .. .. .. FINISH: OUTPUT ENABLE
+ // .. .. .. .. START: OUTPUT ENABLE
+ // .. .. .. .. FINISH: OUTPUT ENABLE
+ // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. START: ADD 1 MS DELAY
+ // .. .. .. ..
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ // .. .. .. .. FINISH: ADD 1 MS DELAY
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. FINISH: I2C1 RESET
+ // .. .. FINISH: I2C RESET
+ // .. .. START: NOR CHIP SELECT
+ // .. .. .. START: DIR MODE BANK 0
+ // .. .. .. FINISH: DIR MODE BANK 0
+ // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. START: OUTPUT ENABLE BANK 0
+ // .. .. .. FINISH: OUTPUT ENABLE BANK 0
+ // .. .. FINISH: NOR CHIP SELECT
+ // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_post_config_2_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: ENABLING LEVEL SHIFTER
+ // .. USER_INP_ICT_EN_0 = 3
+ // .. ==> 0XF8000900[1:0] = 0x00000003U
+ // .. ==> MASK : 0x00000003U VAL : 0x00000003U
+ // .. USER_INP_ICT_EN_1 = 3
+ // .. ==> 0XF8000900[3:2] = 0x00000003U
+ // .. ==> MASK : 0x0000000CU VAL : 0x0000000CU
+ // ..
+ EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
+ // .. FINISH: ENABLING LEVEL SHIFTER
+ // .. START: FPGA RESETS TO 0
+ // .. reserved_3 = 0
+ // .. ==> 0XF8000240[31:25] = 0x00000000U
+ // .. ==> MASK : 0xFE000000U VAL : 0x00000000U
+ // .. FPGA_ACP_RST = 0
+ // .. ==> 0XF8000240[24:24] = 0x00000000U
+ // .. ==> MASK : 0x01000000U VAL : 0x00000000U
+ // .. FPGA_AXDS3_RST = 0
+ // .. ==> 0XF8000240[23:23] = 0x00000000U
+ // .. ==> MASK : 0x00800000U VAL : 0x00000000U
+ // .. FPGA_AXDS2_RST = 0
+ // .. ==> 0XF8000240[22:22] = 0x00000000U
+ // .. ==> MASK : 0x00400000U VAL : 0x00000000U
+ // .. FPGA_AXDS1_RST = 0
+ // .. ==> 0XF8000240[21:21] = 0x00000000U
+ // .. ==> MASK : 0x00200000U VAL : 0x00000000U
+ // .. FPGA_AXDS0_RST = 0
+ // .. ==> 0XF8000240[20:20] = 0x00000000U
+ // .. ==> MASK : 0x00100000U VAL : 0x00000000U
+ // .. reserved_2 = 0
+ // .. ==> 0XF8000240[19:18] = 0x00000000U
+ // .. ==> MASK : 0x000C0000U VAL : 0x00000000U
+ // .. FSSW1_FPGA_RST = 0
+ // .. ==> 0XF8000240[17:17] = 0x00000000U
+ // .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. FSSW0_FPGA_RST = 0
+ // .. ==> 0XF8000240[16:16] = 0x00000000U
+ // .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. reserved_1 = 0
+ // .. ==> 0XF8000240[15:14] = 0x00000000U
+ // .. ==> MASK : 0x0000C000U VAL : 0x00000000U
+ // .. FPGA_FMSW1_RST = 0
+ // .. ==> 0XF8000240[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // .. FPGA_FMSW0_RST = 0
+ // .. ==> 0XF8000240[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. FPGA_DMA3_RST = 0
+ // .. ==> 0XF8000240[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. FPGA_DMA2_RST = 0
+ // .. ==> 0XF8000240[10:10] = 0x00000000U
+ // .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. FPGA_DMA1_RST = 0
+ // .. ==> 0XF8000240[9:9] = 0x00000000U
+ // .. ==> MASK : 0x00000200U VAL : 0x00000000U
+ // .. FPGA_DMA0_RST = 0
+ // .. ==> 0XF8000240[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. reserved = 0
+ // .. ==> 0XF8000240[7:4] = 0x00000000U
+ // .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. FPGA3_OUT_RST = 0
+ // .. ==> 0XF8000240[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. FPGA2_OUT_RST = 0
+ // .. ==> 0XF8000240[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. FPGA1_OUT_RST = 0
+ // .. ==> 0XF8000240[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. FPGA0_OUT_RST = 0
+ // .. ==> 0XF8000240[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
+ // .. FINISH: FPGA RESETS TO 0
+ // .. START: AFI REGISTERS
+ // .. .. START: AFI0 REGISTERS
+ // .. .. FINISH: AFI0 REGISTERS
+ // .. .. START: AFI1 REGISTERS
+ // .. .. FINISH: AFI1 REGISTERS
+ // .. .. START: AFI2 REGISTERS
+ // .. .. FINISH: AFI2 REGISTERS
+ // .. .. START: AFI3 REGISTERS
+ // .. .. FINISH: AFI3 REGISTERS
+ // .. FINISH: AFI REGISTERS
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_debug_2_0[] = {
+ // START: top
+ // .. START: CROSS TRIGGER CONFIGURATIONS
+ // .. .. START: UNLOCKING CTI REGISTERS
+ // .. .. KEY = 0XC5ACCE55
+ // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
+ // .. ..
+ EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
+ // .. .. KEY = 0XC5ACCE55
+ // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
+ // .. ..
+ EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
+ // .. .. KEY = 0XC5ACCE55
+ // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
+ // .. ..
+ EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
+ // .. .. FINISH: UNLOCKING CTI REGISTERS
+ // .. .. START: ENABLING CTI MODULES AND CHANNELS
+ // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
+ // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+ // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+ // .. FINISH: CROSS TRIGGER CONFIGURATIONS
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_pll_init_data_1_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: PLL SLCR REGISTERS
+ // .. .. START: ARM PLL INIT
+ // .. .. PLL_RES = 0x2
+ // .. .. ==> 0XF8000110[7:4] = 0x00000002U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
+ // .. .. PLL_CP = 0x2
+ // .. .. ==> 0XF8000110[11:8] = 0x00000002U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
+ // .. .. LOCK_CNT = 0xfa
+ // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
+ // .. .. .. START: UPDATE FB_DIV
+ // .. .. .. PLL_FDIV = 0x28
+ // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
+ // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
+ // .. .. .. FINISH: UPDATE FB_DIV
+ // .. .. .. START: BY PASS PLL
+ // .. .. .. PLL_BYPASS_FORCE = 1
+ // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
+ // .. .. .. FINISH: BY PASS PLL
+ // .. .. .. START: ASSERT RESET
+ // .. .. .. PLL_RESET = 1
+ // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
+ // .. .. .. FINISH: ASSERT RESET
+ // .. .. .. START: DEASSERT RESET
+ // .. .. .. PLL_RESET = 0
+ // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
+ // .. .. .. FINISH: DEASSERT RESET
+ // .. .. .. START: CHECK PLL STATUS
+ // .. .. .. ARM_PLL_LOCK = 1
+ // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ..
+ EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+ // .. .. .. FINISH: CHECK PLL STATUS
+ // .. .. .. START: REMOVE PLL BY PASS
+ // .. .. .. PLL_BYPASS_FORCE = 0
+ // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
+ // .. .. .. FINISH: REMOVE PLL BY PASS
+ // .. .. .. SRCSEL = 0x0
+ // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. .. .. DIVISOR = 0x2
+ // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
+ // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U
+ // .. .. .. CPU_6OR4XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
+ // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U
+ // .. .. .. CPU_3OR2XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
+ // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U
+ // .. .. .. CPU_2XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
+ // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U
+ // .. .. .. CPU_1XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
+ // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U
+ // .. .. .. CPU_PERI_CLKACT = 0x1
+ // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
+ // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
+ // .. .. FINISH: ARM PLL INIT
+ // .. .. START: DDR PLL INIT
+ // .. .. PLL_RES = 0x2
+ // .. .. ==> 0XF8000114[7:4] = 0x00000002U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
+ // .. .. PLL_CP = 0x2
+ // .. .. ==> 0XF8000114[11:8] = 0x00000002U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
+ // .. .. LOCK_CNT = 0x12c
+ // .. .. ==> 0XF8000114[21:12] = 0x0000012CU
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
+ // .. .. .. START: UPDATE FB_DIV
+ // .. .. .. PLL_FDIV = 0x20
+ // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
+ // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
+ // .. .. .. FINISH: UPDATE FB_DIV
+ // .. .. .. START: BY PASS PLL
+ // .. .. .. PLL_BYPASS_FORCE = 1
+ // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
+ // .. .. .. FINISH: BY PASS PLL
+ // .. .. .. START: ASSERT RESET
+ // .. .. .. PLL_RESET = 1
+ // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
+ // .. .. .. FINISH: ASSERT RESET
+ // .. .. .. START: DEASSERT RESET
+ // .. .. .. PLL_RESET = 0
+ // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
+ // .. .. .. FINISH: DEASSERT RESET
+ // .. .. .. START: CHECK PLL STATUS
+ // .. .. .. DDR_PLL_LOCK = 1
+ // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. .. ..
+ EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+ // .. .. .. FINISH: CHECK PLL STATUS
+ // .. .. .. START: REMOVE PLL BY PASS
+ // .. .. .. PLL_BYPASS_FORCE = 0
+ // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
+ // .. .. .. FINISH: REMOVE PLL BY PASS
+ // .. .. .. DDR_3XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. .. DDR_2XCLKACT = 0x1
+ // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. .. .. DDR_3XCLK_DIVISOR = 0x2
+ // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
+ // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U
+ // .. .. .. DDR_2XCLK_DIVISOR = 0x3
+ // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
+ // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
+ // .. .. FINISH: DDR PLL INIT
+ // .. .. START: IO PLL INIT
+ // .. .. PLL_RES = 0xc
+ // .. .. ==> 0XF8000118[7:4] = 0x0000000CU
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U
+ // .. .. PLL_CP = 0x2
+ // .. .. ==> 0XF8000118[11:8] = 0x00000002U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
+ // .. .. LOCK_CNT = 0x145
+ // .. .. ==> 0XF8000118[21:12] = 0x00000145U
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U),
+ // .. .. .. START: UPDATE FB_DIV
+ // .. .. .. PLL_FDIV = 0x1e
+ // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU
+ // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U),
+ // .. .. .. FINISH: UPDATE FB_DIV
+ // .. .. .. START: BY PASS PLL
+ // .. .. .. PLL_BYPASS_FORCE = 1
+ // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
+ // .. .. .. FINISH: BY PASS PLL
+ // .. .. .. START: ASSERT RESET
+ // .. .. .. PLL_RESET = 1
+ // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
+ // .. .. .. FINISH: ASSERT RESET
+ // .. .. .. START: DEASSERT RESET
+ // .. .. .. PLL_RESET = 0
+ // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
+ // .. .. .. FINISH: DEASSERT RESET
+ // .. .. .. START: CHECK PLL STATUS
+ // .. .. .. IO_PLL_LOCK = 1
+ // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
+ // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. .. ..
+ EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+ // .. .. .. FINISH: CHECK PLL STATUS
+ // .. .. .. START: REMOVE PLL BY PASS
+ // .. .. .. PLL_BYPASS_FORCE = 0
+ // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
+ // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. ..
+ EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
+ // .. .. .. FINISH: REMOVE PLL BY PASS
+ // .. .. FINISH: IO PLL INIT
+ // .. FINISH: PLL SLCR REGISTERS
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_clock_init_data_1_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: CLOCK CONTROL SLCR REGISTERS
+ // .. CLKACT = 0x1
+ // .. ==> 0XF8000128[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. DIVISOR0 = 0x23
+ // .. ==> 0XF8000128[13:8] = 0x00000023U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00002300U
+ // .. DIVISOR1 = 0x3
+ // .. ==> 0XF8000128[25:20] = 0x00000003U
+ // .. ==> MASK : 0x03F00000U VAL : 0x00300000U
+ // ..
+ EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U),
+ // .. CLKACT = 0x1
+ // .. ==> 0XF8000138[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000138[4:4] = 0x00000000U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
+ // .. CLKACT = 0x1
+ // .. ==> 0XF8000140[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000140[6:4] = 0x00000000U
+ // .. ==> MASK : 0x00000070U VAL : 0x00000000U
+ // .. DIVISOR = 0x8
+ // .. ==> 0XF8000140[13:8] = 0x00000008U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00000800U
+ // .. DIVISOR1 = 0x1
+ // .. ==> 0XF8000140[25:20] = 0x00000001U
+ // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
+ // ..
+ EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U),
+ // .. CLKACT = 0x1
+ // .. ==> 0XF800014C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF800014C[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR = 0x5
+ // .. ==> 0XF800014C[13:8] = 0x00000005U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00000500U
+ // ..
+ EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
+ // .. CLKACT0 = 0x1
+ // .. ==> 0XF8000150[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. CLKACT1 = 0x0
+ // .. ==> 0XF8000150[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000150[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR = 0x14
+ // .. ==> 0XF8000150[13:8] = 0x00000014U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
+ // ..
+ EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U),
+ // .. CLKACT0 = 0x0
+ // .. ==> 0XF8000154[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. CLKACT1 = 0x1
+ // .. ==> 0XF8000154[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000154[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR = 0x14
+ // .. ==> 0XF8000154[13:8] = 0x00000014U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
+ // ..
+ EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U),
+ // .. CLKACT = 0x1
+ // .. ==> 0XF8000168[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000168[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR = 0x5
+ // .. ==> 0XF8000168[13:8] = 0x00000005U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00000500U
+ // ..
+ EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000170[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR0 = 0xa
+ // .. ==> 0XF8000170[13:8] = 0x0000000AU
+ // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U
+ // .. DIVISOR1 = 0x1
+ // .. ==> 0XF8000170[25:20] = 0x00000001U
+ // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
+ // ..
+ EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00100A00U),
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000180[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR0 = 0x7
+ // .. ==> 0XF8000180[13:8] = 0x00000007U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00000700U
+ // .. DIVISOR1 = 0x1
+ // .. ==> 0XF8000180[25:20] = 0x00000001U
+ // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
+ // ..
+ EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00100700U),
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF8000190[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR0 = 0x14
+ // .. ==> 0XF8000190[13:8] = 0x00000014U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
+ // .. DIVISOR1 = 0x1
+ // .. ==> 0XF8000190[25:20] = 0x00000001U
+ // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
+ // ..
+ EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101400U),
+ // .. SRCSEL = 0x0
+ // .. ==> 0XF80001A0[5:4] = 0x00000000U
+ // .. ==> MASK : 0x00000030U VAL : 0x00000000U
+ // .. DIVISOR0 = 0x14
+ // .. ==> 0XF80001A0[13:8] = 0x00000014U
+ // .. ==> MASK : 0x00003F00U VAL : 0x00001400U
+ // .. DIVISOR1 = 0x1
+ // .. ==> 0XF80001A0[25:20] = 0x00000001U
+ // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
+ // ..
+ EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U),
+ // .. CLK_621_TRUE = 0x1
+ // .. ==> 0XF80001C4[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // ..
+ EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
+ // .. DMA_CPU_2XCLKACT = 0x1
+ // .. ==> 0XF800012C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. USB0_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. USB1_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[3:3] = 0x00000001U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000008U
+ // .. GEM0_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[6:6] = 0x00000001U
+ // .. ==> MASK : 0x00000040U VAL : 0x00000040U
+ // .. GEM1_CPU_1XCLKACT = 0x0
+ // .. ==> 0XF800012C[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. SDI0_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[10:10] = 0x00000001U
+ // .. ==> MASK : 0x00000400U VAL : 0x00000400U
+ // .. SDI1_CPU_1XCLKACT = 0x0
+ // .. ==> 0XF800012C[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. SPI0_CPU_1XCLKACT = 0x0
+ // .. ==> 0XF800012C[14:14] = 0x00000000U
+ // .. ==> MASK : 0x00004000U VAL : 0x00000000U
+ // .. SPI1_CPU_1XCLKACT = 0x0
+ // .. ==> 0XF800012C[15:15] = 0x00000000U
+ // .. ==> MASK : 0x00008000U VAL : 0x00000000U
+ // .. CAN0_CPU_1XCLKACT = 0x0
+ // .. ==> 0XF800012C[16:16] = 0x00000000U
+ // .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. CAN1_CPU_1XCLKACT = 0x0
+ // .. ==> 0XF800012C[17:17] = 0x00000000U
+ // .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. I2C0_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[18:18] = 0x00000001U
+ // .. ==> MASK : 0x00040000U VAL : 0x00040000U
+ // .. I2C1_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[19:19] = 0x00000001U
+ // .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // .. UART0_CPU_1XCLKACT = 0x0
+ // .. ==> 0XF800012C[20:20] = 0x00000000U
+ // .. ==> MASK : 0x00100000U VAL : 0x00000000U
+ // .. UART1_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[21:21] = 0x00000001U
+ // .. ==> MASK : 0x00200000U VAL : 0x00200000U
+ // .. GPIO_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[22:22] = 0x00000001U
+ // .. ==> MASK : 0x00400000U VAL : 0x00400000U
+ // .. LQSPI_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[23:23] = 0x00000001U
+ // .. ==> MASK : 0x00800000U VAL : 0x00800000U
+ // .. SMC_CPU_1XCLKACT = 0x1
+ // .. ==> 0XF800012C[24:24] = 0x00000001U
+ // .. ==> MASK : 0x01000000U VAL : 0x01000000U
+ // ..
+ EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC044DU),
+ // .. FINISH: CLOCK CONTROL SLCR REGISTERS
+ // .. START: THIS SHOULD BE BLANK
+ // .. FINISH: THIS SHOULD BE BLANK
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_ddr_init_data_1_0[] = {
+ // START: top
+ // .. START: DDR INITIALIZATION
+ // .. .. START: LOCK DDR
+ // .. .. reg_ddrc_soft_rstb = 0
+ // .. .. ==> 0XF8006000[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_powerdown_en = 0x0
+ // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_ddrc_data_bus_width = 0x0
+ // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U
+ // .. .. reg_ddrc_burst8_refresh = 0x0
+ // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U
+ // .. .. reg_ddrc_rdwr_idle_gap = 0x1
+ // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+ // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U
+ // .. .. reg_ddrc_dis_rd_bypass = 0x0
+ // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+ // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_act_bypass = 0x0
+ // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_auto_refresh = 0x0
+ // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
+ // .. .. FINISH: LOCK DDR
+ // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81
+ // .. .. ==> 0XF8006004[11:0] = 0x00000081U
+ // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U
+ // .. .. reg_ddrc_active_ranks = 0x1
+ // .. .. ==> 0XF8006004[13:12] = 0x00000001U
+ // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U
+ // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
+ // .. .. ==> 0XF8006004[18:14] = 0x00000000U
+ // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U
+ // .. .. reg_ddrc_wr_odt_block = 0x1
+ // .. .. ==> 0XF8006004[20:19] = 0x00000001U
+ // .. .. ==> MASK : 0x00180000U VAL : 0x00080000U
+ // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0
+ // .. .. ==> 0XF8006004[21:21] = 0x00000000U
+ // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0
+ // .. .. ==> 0XF8006004[26:22] = 0x00000000U
+ // .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_open_bank = 0x0
+ // .. .. ==> 0XF8006004[27:27] = 0x00000000U
+ // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_4bank_ram = 0x0
+ // .. .. ==> 0XF8006004[28:28] = 0x00000000U
+ // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U),
+ // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
+ // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU
+ // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
+ // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
+ // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U
+ // .. .. reg_ddrc_hpr_xact_run_length = 0xf
+ // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
+ // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
+ // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
+ // .. .. ==> 0XF800600C[10:0] = 0x00000001U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U
+ // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
+ // .. .. ==> 0XF800600C[21:11] = 0x00000002U
+ // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U
+ // .. .. reg_ddrc_lpr_xact_run_length = 0x8
+ // .. .. ==> 0XF800600C[25:22] = 0x00000008U
+ // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
+ // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
+ // .. .. ==> 0XF8006010[10:0] = 0x00000001U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U
+ // .. .. reg_ddrc_w_xact_run_length = 0x8
+ // .. .. ==> 0XF8006010[14:11] = 0x00000008U
+ // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U
+ // .. .. reg_ddrc_w_max_starve_x32 = 0x2
+ // .. .. ==> 0XF8006010[25:15] = 0x00000002U
+ // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
+ // .. .. reg_ddrc_t_rc = 0x1b
+ // .. .. ==> 0XF8006014[5:0] = 0x0000001BU
+ // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001BU
+ // .. .. reg_ddrc_t_rfc_min = 0x56
+ // .. .. ==> 0XF8006014[13:6] = 0x00000056U
+ // .. .. ==> MASK : 0x00003FC0U VAL : 0x00001580U
+ // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
+ // .. .. ==> 0XF8006014[20:14] = 0x00000010U
+ // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004159BU),
+ // .. .. reg_ddrc_wr2pre = 0x12
+ // .. .. ==> 0XF8006018[4:0] = 0x00000012U
+ // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U
+ // .. .. reg_ddrc_powerdown_to_x32 = 0x6
+ // .. .. ==> 0XF8006018[9:5] = 0x00000006U
+ // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U
+ // .. .. reg_ddrc_t_faw = 0x18
+ // .. .. ==> 0XF8006018[15:10] = 0x00000018U
+ // .. .. ==> MASK : 0x0000FC00U VAL : 0x00006000U
+ // .. .. reg_ddrc_t_ras_max = 0x24
+ // .. .. ==> 0XF8006018[21:16] = 0x00000024U
+ // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U
+ // .. .. reg_ddrc_t_ras_min = 0x14
+ // .. .. ==> 0XF8006018[26:22] = 0x00000014U
+ // .. .. ==> MASK : 0x07C00000U VAL : 0x05000000U
+ // .. .. reg_ddrc_t_cke = 0x4
+ // .. .. ==> 0XF8006018[31:28] = 0x00000004U
+ // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x452460D2U),
+ // .. .. reg_ddrc_write_latency = 0x5
+ // .. .. ==> 0XF800601C[4:0] = 0x00000005U
+ // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U
+ // .. .. reg_ddrc_rd2wr = 0x7
+ // .. .. ==> 0XF800601C[9:5] = 0x00000007U
+ // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U
+ // .. .. reg_ddrc_wr2rd = 0xe
+ // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
+ // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U
+ // .. .. reg_ddrc_t_xp = 0x4
+ // .. .. ==> 0XF800601C[19:15] = 0x00000004U
+ // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U
+ // .. .. reg_ddrc_pad_pd = 0x0
+ // .. .. ==> 0XF800601C[22:20] = 0x00000000U
+ // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U
+ // .. .. reg_ddrc_rd2pre = 0x4
+ // .. .. ==> 0XF800601C[27:23] = 0x00000004U
+ // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U
+ // .. .. reg_ddrc_t_rcd = 0x7
+ // .. .. ==> 0XF800601C[31:28] = 0x00000007U
+ // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
+ // .. .. reg_ddrc_t_ccd = 0x4
+ // .. .. ==> 0XF8006020[4:2] = 0x00000004U
+ // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U
+ // .. .. reg_ddrc_t_rrd = 0x6
+ // .. .. ==> 0XF8006020[7:5] = 0x00000006U
+ // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U
+ // .. .. reg_ddrc_refresh_margin = 0x2
+ // .. .. ==> 0XF8006020[11:8] = 0x00000002U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
+ // .. .. reg_ddrc_t_rp = 0x7
+ // .. .. ==> 0XF8006020[15:12] = 0x00000007U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U
+ // .. .. reg_ddrc_refresh_to_x32 = 0x8
+ // .. .. ==> 0XF8006020[20:16] = 0x00000008U
+ // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U
+ // .. .. reg_ddrc_sdram = 0x1
+ // .. .. ==> 0XF8006020[21:21] = 0x00000001U
+ // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U
+ // .. .. reg_ddrc_mobile = 0x0
+ // .. .. ==> 0XF8006020[22:22] = 0x00000000U
+ // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U
+ // .. .. reg_ddrc_clock_stop_en = 0x0
+ // .. .. ==> 0XF8006020[23:23] = 0x00000000U
+ // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U
+ // .. .. reg_ddrc_read_latency = 0x7
+ // .. .. ==> 0XF8006020[28:24] = 0x00000007U
+ // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U
+ // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
+ // .. .. ==> 0XF8006020[29:29] = 0x00000001U
+ // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U
+ // .. .. reg_ddrc_dis_pad_pd = 0x0
+ // .. .. ==> 0XF8006020[30:30] = 0x00000000U
+ // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_loopback = 0x0
+ // .. .. ==> 0XF8006020[31:31] = 0x00000000U
+ // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U),
+ // .. .. reg_ddrc_en_2t_timing_mode = 0x0
+ // .. .. ==> 0XF8006024[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_prefer_write = 0x0
+ // .. .. ==> 0XF8006024[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_ddrc_max_rank_rd = 0xf
+ // .. .. ==> 0XF8006024[5:2] = 0x0000000FU
+ // .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU
+ // .. .. reg_ddrc_mr_wr = 0x0
+ // .. .. ==> 0XF8006024[6:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr_addr = 0x0
+ // .. .. ==> 0XF8006024[8:7] = 0x00000000U
+ // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr_data = 0x0
+ // .. .. ==> 0XF8006024[24:9] = 0x00000000U
+ // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U
+ // .. .. ddrc_reg_mr_wr_busy = 0x0
+ // .. .. ==> 0XF8006024[25:25] = 0x00000000U
+ // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr_type = 0x0
+ // .. .. ==> 0XF8006024[26:26] = 0x00000000U
+ // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr_rdata_valid = 0x0
+ // .. .. ==> 0XF8006024[27:27] = 0x00000000U
+ // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU),
+ // .. .. reg_ddrc_final_wait_x32 = 0x7
+ // .. .. ==> 0XF8006028[6:0] = 0x00000007U
+ // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U
+ // .. .. reg_ddrc_pre_ocd_x32 = 0x0
+ // .. .. ==> 0XF8006028[10:7] = 0x00000000U
+ // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U
+ // .. .. reg_ddrc_t_mrd = 0x4
+ // .. .. ==> 0XF8006028[13:11] = 0x00000004U
+ // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
+ // .. .. reg_ddrc_emr2 = 0x8
+ // .. .. ==> 0XF800602C[15:0] = 0x00000008U
+ // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U
+ // .. .. reg_ddrc_emr3 = 0x0
+ // .. .. ==> 0XF800602C[31:16] = 0x00000000U
+ // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
+ // .. .. reg_ddrc_mr = 0x930
+ // .. .. ==> 0XF8006030[15:0] = 0x00000930U
+ // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U
+ // .. .. reg_ddrc_emr = 0x4
+ // .. .. ==> 0XF8006030[31:16] = 0x00000004U
+ // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
+ // .. .. reg_ddrc_burst_rdwr = 0x4
+ // .. .. ==> 0XF8006034[3:0] = 0x00000004U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U
+ // .. .. reg_ddrc_pre_cke_x1024 = 0x105
+ // .. .. ==> 0XF8006034[13:4] = 0x00000105U
+ // .. .. ==> MASK : 0x00003FF0U VAL : 0x00001050U
+ // .. .. reg_ddrc_post_cke_x1024 = 0x1
+ // .. .. ==> 0XF8006034[25:16] = 0x00000001U
+ // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U
+ // .. .. reg_ddrc_burstchop = 0x0
+ // .. .. ==> 0XF8006034[28:28] = 0x00000000U
+ // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U),
+ // .. .. reg_ddrc_force_low_pri_n = 0x0
+ // .. .. ==> 0XF8006038[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_dq = 0x0
+ // .. .. ==> 0XF8006038[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_debug_mode = 0x0
+ // .. .. ==> 0XF8006038[6:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U
+ // .. .. reg_phy_wr_level_start = 0x0
+ // .. .. ==> 0XF8006038[7:7] = 0x00000000U
+ // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. .. reg_phy_rd_level_start = 0x0
+ // .. .. ==> 0XF8006038[8:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. .. reg_phy_dq0_wait_t = 0x0
+ // .. .. ==> 0XF8006038[12:9] = 0x00000000U
+ // .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U),
+ // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
+ // .. .. ==> 0XF800603C[3:0] = 0x00000007U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U
+ // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
+ // .. .. ==> 0XF800603C[7:4] = 0x00000007U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U
+ // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
+ // .. .. ==> 0XF800603C[11:8] = 0x00000007U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U
+ // .. .. reg_ddrc_addrmap_col_b5 = 0x0
+ // .. .. ==> 0XF800603C[15:12] = 0x00000000U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b6 = 0x0
+ // .. .. ==> 0XF800603C[19:16] = 0x00000000U
+ // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
+ // .. .. reg_ddrc_addrmap_col_b2 = 0x0
+ // .. .. ==> 0XF8006040[3:0] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b3 = 0x0
+ // .. .. ==> 0XF8006040[7:4] = 0x00000000U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b4 = 0x0
+ // .. .. ==> 0XF8006040[11:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b7 = 0x0
+ // .. .. ==> 0XF8006040[15:12] = 0x00000000U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b8 = 0x0
+ // .. .. ==> 0XF8006040[19:16] = 0x00000000U
+ // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U
+ // .. .. reg_ddrc_addrmap_col_b9 = 0xf
+ // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
+ // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U
+ // .. .. reg_ddrc_addrmap_col_b10 = 0xf
+ // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
+ // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U
+ // .. .. reg_ddrc_addrmap_col_b11 = 0xf
+ // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
+ // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
+ // .. .. reg_ddrc_addrmap_row_b0 = 0x6
+ // .. .. ==> 0XF8006044[3:0] = 0x00000006U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U
+ // .. .. reg_ddrc_addrmap_row_b1 = 0x6
+ // .. .. ==> 0XF8006044[7:4] = 0x00000006U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U
+ // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
+ // .. .. ==> 0XF8006044[11:8] = 0x00000006U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U
+ // .. .. reg_ddrc_addrmap_row_b12 = 0x6
+ // .. .. ==> 0XF8006044[15:12] = 0x00000006U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U
+ // .. .. reg_ddrc_addrmap_row_b13 = 0x6
+ // .. .. ==> 0XF8006044[19:16] = 0x00000006U
+ // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U
+ // .. .. reg_ddrc_addrmap_row_b14 = 0xf
+ // .. .. ==> 0XF8006044[23:20] = 0x0000000FU
+ // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U
+ // .. .. reg_ddrc_addrmap_row_b15 = 0xf
+ // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
+ // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0FF66666U),
+ // .. .. reg_ddrc_rank0_rd_odt = 0x0
+ // .. .. ==> 0XF8006048[2:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U
+ // .. .. reg_ddrc_rank0_wr_odt = 0x1
+ // .. .. ==> 0XF8006048[5:3] = 0x00000001U
+ // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U
+ // .. .. reg_ddrc_rank1_rd_odt = 0x1
+ // .. .. ==> 0XF8006048[8:6] = 0x00000001U
+ // .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U
+ // .. .. reg_ddrc_rank1_wr_odt = 0x1
+ // .. .. ==> 0XF8006048[11:9] = 0x00000001U
+ // .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. .. reg_phy_rd_local_odt = 0x0
+ // .. .. ==> 0XF8006048[13:12] = 0x00000000U
+ // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U
+ // .. .. reg_phy_wr_local_odt = 0x3
+ // .. .. ==> 0XF8006048[15:14] = 0x00000003U
+ // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U
+ // .. .. reg_phy_idle_local_odt = 0x3
+ // .. .. ==> 0XF8006048[17:16] = 0x00000003U
+ // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U
+ // .. .. reg_ddrc_rank2_rd_odt = 0x0
+ // .. .. ==> 0XF8006048[20:18] = 0x00000000U
+ // .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U
+ // .. .. reg_ddrc_rank2_wr_odt = 0x0
+ // .. .. ==> 0XF8006048[23:21] = 0x00000000U
+ // .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U
+ // .. .. reg_ddrc_rank3_rd_odt = 0x0
+ // .. .. ==> 0XF8006048[26:24] = 0x00000000U
+ // .. .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_rank3_wr_odt = 0x0
+ // .. .. ==> 0XF8006048[29:27] = 0x00000000U
+ // .. .. ==> MASK : 0x38000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U),
+ // .. .. reg_phy_rd_cmd_to_data = 0x0
+ // .. .. ==> 0XF8006050[3:0] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
+ // .. .. reg_phy_wr_cmd_to_data = 0x0
+ // .. .. ==> 0XF8006050[7:4] = 0x00000000U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. .. reg_phy_rdc_we_to_re_delay = 0x8
+ // .. .. ==> 0XF8006050[11:8] = 0x00000008U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U
+ // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
+ // .. .. ==> 0XF8006050[15:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
+ // .. .. reg_phy_use_fixed_re = 0x1
+ // .. .. ==> 0XF8006050[16:16] = 0x00000001U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U
+ // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
+ // .. .. ==> 0XF8006050[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
+ // .. .. ==> 0XF8006050[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_phy_clk_stall_level = 0x0
+ // .. .. ==> 0XF8006050[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
+ // .. .. ==> 0XF8006050[27:24] = 0x00000007U
+ // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U
+ // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
+ // .. .. ==> 0XF8006050[31:28] = 0x00000007U
+ // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
+ // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1
+ // .. .. ==> 0XF8006058[7:0] = 0x00000001U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U
+ // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1
+ // .. .. ==> 0XF8006058[15:8] = 0x00000001U
+ // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U
+ // .. .. reg_ddrc_dis_dll_calib = 0x0
+ // .. .. ==> 0XF8006058[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U),
+ // .. .. reg_ddrc_rd_odt_delay = 0x3
+ // .. .. ==> 0XF800605C[3:0] = 0x00000003U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U
+ // .. .. reg_ddrc_wr_odt_delay = 0x0
+ // .. .. ==> 0XF800605C[7:4] = 0x00000000U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. .. reg_ddrc_rd_odt_hold = 0x0
+ // .. .. ==> 0XF800605C[11:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U
+ // .. .. reg_ddrc_wr_odt_hold = 0x5
+ // .. .. ==> 0XF800605C[15:12] = 0x00000005U
+ // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
+ // .. .. reg_ddrc_pageclose = 0x0
+ // .. .. ==> 0XF8006060[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_lpr_num_entries = 0x1f
+ // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
+ // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU
+ // .. .. reg_ddrc_auto_pre_en = 0x0
+ // .. .. ==> 0XF8006060[7:7] = 0x00000000U
+ // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. .. reg_ddrc_refresh_update_level = 0x0
+ // .. .. ==> 0XF8006060[8:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_wc = 0x0
+ // .. .. ==> 0XF8006060[9:9] = 0x00000000U
+ // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_collision_page_opt = 0x0
+ // .. .. ==> 0XF8006060[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_ddrc_selfref_en = 0x0
+ // .. .. ==> 0XF8006060[12:12] = 0x00000000U
+ // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
+ // .. .. reg_ddrc_go2critical_hysteresis = 0x0
+ // .. .. ==> 0XF8006064[12:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U
+ // .. .. reg_arb_go2critical_en = 0x1
+ // .. .. ==> 0XF8006064[17:17] = 0x00000001U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
+ // .. .. reg_ddrc_wrlvl_ww = 0x41
+ // .. .. ==> 0XF8006068[7:0] = 0x00000041U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U
+ // .. .. reg_ddrc_rdlvl_rr = 0x41
+ // .. .. ==> 0XF8006068[15:8] = 0x00000041U
+ // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U
+ // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
+ // .. .. ==> 0XF8006068[25:16] = 0x00000028U
+ // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
+ // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
+ // .. .. ==> 0XF800606C[7:0] = 0x00000010U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U
+ // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
+ // .. .. ==> 0XF800606C[15:8] = 0x00000016U
+ // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U
+ // .. ..
+ EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
+ // .. .. refresh_timer0_start_value_x32 = 0x0
+ // .. .. ==> 0XF80060A0[11:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U
+ // .. .. refresh_timer1_start_value_x32 = 0x8
+ // .. .. ==> 0XF80060A0[23:12] = 0x00000008U
+ // .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U),
+ // .. .. reg_ddrc_dis_auto_zq = 0x0
+ // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_ddr3 = 0x1
+ // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. .. reg_ddrc_t_mod = 0x200
+ // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
+ // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U
+ // .. .. reg_ddrc_t_zq_long_nop = 0x200
+ // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U
+ // .. .. reg_ddrc_t_zq_short_nop = 0x40
+ // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
+ // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
+ // .. .. t_zq_short_interval_x1024 = 0xcb73
+ // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U
+ // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U
+ // .. .. dram_rstn_x1024 = 0x69
+ // .. .. ==> 0XF80060A8[27:20] = 0x00000069U
+ // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
+ // .. .. deeppowerdown_en = 0x0
+ // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. deeppowerdown_to_x1024 = 0xff
+ // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
+ // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU
+ // .. ..
+ EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
+ // .. .. dfi_wrlvl_max_x1024 = 0xfff
+ // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
+ // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU
+ // .. .. dfi_rdlvl_max_x1024 = 0xfff
+ // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
+ // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U
+ // .. .. ddrc_reg_twrlvl_max_error = 0x0
+ // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
+ // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U
+ // .. .. ddrc_reg_trdlvl_max_error = 0x0
+ // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
+ // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dfi_wr_level_en = 0x1
+ // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
+ // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U
+ // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
+ // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
+ // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U
+ // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
+ // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
+ // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
+ // .. .. reg_ddrc_2t_delay = 0x0
+ // .. .. ==> 0XF80060B4[8:0] = 0x00000000U
+ // .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U
+ // .. .. reg_ddrc_skip_ocd = 0x1
+ // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
+ // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U
+ // .. .. reg_ddrc_dis_pre_bypass = 0x0
+ // .. .. ==> 0XF80060B4[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U),
+ // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
+ // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
+ // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U
+ // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
+ // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
+ // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U
+ // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
+ // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
+ // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
+ // .. .. START: RESET ECC ERROR
+ // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1
+ // .. .. ==> 0XF80060C4[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. Clear_Correctable_DRAM_ECC_error = 1
+ // .. .. ==> 0XF80060C4[1:1] = 0x00000001U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U),
+ // .. .. FINISH: RESET ECC ERROR
+ // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
+ // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
+ // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
+ // .. .. CORR_ECC_LOG_VALID = 0x0
+ // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. ECC_CORRECTED_BIT_NUM = 0x0
+ // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
+ // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
+ // .. .. UNCORR_ECC_LOG_VALID = 0x0
+ // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
+ // .. .. STAT_NUM_CORR_ERR = 0x0
+ // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
+ // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U
+ // .. .. STAT_NUM_UNCORR_ERR = 0x0
+ // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
+ // .. .. reg_ddrc_ecc_mode = 0x0
+ // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_scrub = 0x1
+ // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U
+ // .. ..
+ EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
+ // .. .. reg_phy_dif_on = 0x0
+ // .. .. ==> 0XF8006114[3:0] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
+ // .. .. reg_phy_dif_off = 0x0
+ // .. .. ==> 0XF8006114[7:4] = 0x00000000U
+ // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
+ // .. .. reg_phy_data_slice_in_use = 0x1
+ // .. .. ==> 0XF8006118[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_phy_rdlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006118[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006118[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_wrlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006118[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_tx = 0x0
+ // .. .. ==> 0XF8006118[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_rx = 0x0
+ // .. .. ==> 0XF8006118[5:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
+ // .. .. reg_phy_bist_shift_dq = 0x0
+ // .. .. ==> 0XF8006118[14:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
+ // .. .. reg_phy_bist_err_clr = 0x0
+ // .. .. ==> 0XF8006118[23:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
+ // .. .. reg_phy_dq_offset = 0x40
+ // .. .. ==> 0XF8006118[30:24] = 0x00000040U
+ // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U),
+ // .. .. reg_phy_data_slice_in_use = 0x1
+ // .. .. ==> 0XF800611C[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_phy_rdlvl_inc_mode = 0x0
+ // .. .. ==> 0XF800611C[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_inc_mode = 0x0
+ // .. .. ==> 0XF800611C[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_wrlvl_inc_mode = 0x0
+ // .. .. ==> 0XF800611C[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_tx = 0x0
+ // .. .. ==> 0XF800611C[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_rx = 0x0
+ // .. .. ==> 0XF800611C[5:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
+ // .. .. reg_phy_bist_shift_dq = 0x0
+ // .. .. ==> 0XF800611C[14:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
+ // .. .. reg_phy_bist_err_clr = 0x0
+ // .. .. ==> 0XF800611C[23:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
+ // .. .. reg_phy_dq_offset = 0x40
+ // .. .. ==> 0XF800611C[30:24] = 0x00000040U
+ // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U),
+ // .. .. reg_phy_data_slice_in_use = 0x1
+ // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_phy_rdlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_wrlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_tx = 0x0
+ // .. .. ==> 0XF8006120[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_rx = 0x0
+ // .. .. ==> 0XF8006120[5:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
+ // .. .. reg_phy_bist_shift_dq = 0x0
+ // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
+ // .. .. reg_phy_bist_err_clr = 0x0
+ // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
+ // .. .. reg_phy_dq_offset = 0x40
+ // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+ // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U),
+ // .. .. reg_phy_data_slice_in_use = 0x1
+ // .. .. ==> 0XF8006124[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_phy_rdlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006124[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006124[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_wrlvl_inc_mode = 0x0
+ // .. .. ==> 0XF8006124[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_tx = 0x0
+ // .. .. ==> 0XF8006124[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reg_phy_board_lpbk_rx = 0x0
+ // .. .. ==> 0XF8006124[5:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
+ // .. .. reg_phy_bist_shift_dq = 0x0
+ // .. .. ==> 0XF8006124[14:6] = 0x00000000U
+ // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
+ // .. .. reg_phy_bist_err_clr = 0x0
+ // .. .. ==> 0XF8006124[23:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
+ // .. .. reg_phy_dq_offset = 0x40
+ // .. .. ==> 0XF8006124[30:24] = 0x00000040U
+ // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U),
+ // .. .. reg_phy_wrlvl_init_ratio = 0x3
+ // .. .. ==> 0XF800612C[9:0] = 0x00000003U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000003U
+ // .. .. reg_phy_gatelvl_init_ratio = 0xcf
+ // .. .. ==> 0XF800612C[19:10] = 0x000000CFU
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x00033C00U
+ // .. ..
+ EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00033C03U),
+ // .. .. reg_phy_wrlvl_init_ratio = 0x3
+ // .. .. ==> 0XF8006130[9:0] = 0x00000003U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000003U
+ // .. .. reg_phy_gatelvl_init_ratio = 0xd0
+ // .. .. ==> 0XF8006130[19:10] = 0x000000D0U
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x00034000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00034003U),
+ // .. .. reg_phy_wrlvl_init_ratio = 0x0
+ // .. .. ==> 0XF8006134[9:0] = 0x00000000U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_init_ratio = 0xbd
+ // .. .. ==> 0XF8006134[19:10] = 0x000000BDU
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002F400U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0002F400U),
+ // .. .. reg_phy_wrlvl_init_ratio = 0x0
+ // .. .. ==> 0XF8006138[9:0] = 0x00000000U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
+ // .. .. reg_phy_gatelvl_init_ratio = 0xc1
+ // .. .. ==> 0XF8006138[19:10] = 0x000000C1U
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x00030400U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x00030400U),
+ // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+ // .. .. ==> 0XF8006140[9:0] = 0x00000035U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
+ // .. .. reg_phy_rd_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006140[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006140[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
+ // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+ // .. .. ==> 0XF8006144[9:0] = 0x00000035U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
+ // .. .. reg_phy_rd_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006144[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006144[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
+ // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+ // .. .. ==> 0XF8006148[9:0] = 0x00000035U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
+ // .. .. reg_phy_rd_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006148[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006148[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
+ // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+ // .. .. ==> 0XF800614C[9:0] = 0x00000035U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
+ // .. .. reg_phy_rd_dqs_slave_force = 0x0
+ // .. .. ==> 0XF800614C[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF800614C[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
+ // .. .. reg_phy_wr_dqs_slave_ratio = 0x83
+ // .. .. ==> 0XF8006154[9:0] = 0x00000083U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000083U
+ // .. .. reg_phy_wr_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006154[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006154[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000083U),
+ // .. .. reg_phy_wr_dqs_slave_ratio = 0x83
+ // .. .. ==> 0XF8006158[9:0] = 0x00000083U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000083U
+ // .. .. reg_phy_wr_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006158[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006158[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000083U),
+ // .. .. reg_phy_wr_dqs_slave_ratio = 0x7f
+ // .. .. ==> 0XF800615C[9:0] = 0x0000007FU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x0000007FU
+ // .. .. reg_phy_wr_dqs_slave_force = 0x0
+ // .. .. ==> 0XF800615C[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF800615C[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x0000007FU),
+ // .. .. reg_phy_wr_dqs_slave_ratio = 0x78
+ // .. .. ==> 0XF8006160[9:0] = 0x00000078U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x00000078U
+ // .. .. reg_phy_wr_dqs_slave_force = 0x0
+ // .. .. ==> 0XF8006160[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+ // .. .. ==> 0XF8006160[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000078U),
+ // .. .. reg_phy_fifo_we_slave_ratio = 0x124
+ // .. .. ==> 0XF8006168[10:0] = 0x00000124U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000124U
+ // .. .. reg_phy_fifo_we_in_force = 0x0
+ // .. .. ==> 0XF8006168[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. reg_phy_fifo_we_in_delay = 0x0
+ // .. .. ==> 0XF8006168[20:12] = 0x00000000U
+ // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000124U),
+ // .. .. reg_phy_fifo_we_slave_ratio = 0x125
+ // .. .. ==> 0XF800616C[10:0] = 0x00000125U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000125U
+ // .. .. reg_phy_fifo_we_in_force = 0x0
+ // .. .. ==> 0XF800616C[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. reg_phy_fifo_we_in_delay = 0x0
+ // .. .. ==> 0XF800616C[20:12] = 0x00000000U
+ // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x00000125U),
+ // .. .. reg_phy_fifo_we_slave_ratio = 0x112
+ // .. .. ==> 0XF8006170[10:0] = 0x00000112U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000112U
+ // .. .. reg_phy_fifo_we_in_force = 0x0
+ // .. .. ==> 0XF8006170[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. reg_phy_fifo_we_in_delay = 0x0
+ // .. .. ==> 0XF8006170[20:12] = 0x00000000U
+ // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000112U),
+ // .. .. reg_phy_fifo_we_slave_ratio = 0x116
+ // .. .. ==> 0XF8006174[10:0] = 0x00000116U
+ // .. .. ==> MASK : 0x000007FFU VAL : 0x00000116U
+ // .. .. reg_phy_fifo_we_in_force = 0x0
+ // .. .. ==> 0XF8006174[11:11] = 0x00000000U
+ // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. .. reg_phy_fifo_we_in_delay = 0x0
+ // .. .. ==> 0XF8006174[20:12] = 0x00000000U
+ // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000116U),
+ // .. .. reg_phy_wr_data_slave_ratio = 0xc3
+ // .. .. ==> 0XF800617C[9:0] = 0x000000C3U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C3U
+ // .. .. reg_phy_wr_data_slave_force = 0x0
+ // .. .. ==> 0XF800617C[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_data_slave_delay = 0x0
+ // .. .. ==> 0XF800617C[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000C3U),
+ // .. .. reg_phy_wr_data_slave_ratio = 0xc3
+ // .. .. ==> 0XF8006180[9:0] = 0x000000C3U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C3U
+ // .. .. reg_phy_wr_data_slave_force = 0x0
+ // .. .. ==> 0XF8006180[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_data_slave_delay = 0x0
+ // .. .. ==> 0XF8006180[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000C3U),
+ // .. .. reg_phy_wr_data_slave_ratio = 0xbf
+ // .. .. ==> 0XF8006184[9:0] = 0x000000BFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000BFU
+ // .. .. reg_phy_wr_data_slave_force = 0x0
+ // .. .. ==> 0XF8006184[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_data_slave_delay = 0x0
+ // .. .. ==> 0XF8006184[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000BFU),
+ // .. .. reg_phy_wr_data_slave_ratio = 0xb8
+ // .. .. ==> 0XF8006188[9:0] = 0x000000B8U
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000000B8U
+ // .. .. reg_phy_wr_data_slave_force = 0x0
+ // .. .. ==> 0XF8006188[10:10] = 0x00000000U
+ // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. .. reg_phy_wr_data_slave_delay = 0x0
+ // .. .. ==> 0XF8006188[19:11] = 0x00000000U
+ // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000B8U),
+ // .. .. reg_phy_loopback = 0x0
+ // .. .. ==> 0XF8006190[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_phy_bl2 = 0x0
+ // .. .. ==> 0XF8006190[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_phy_at_spd_atpg = 0x0
+ // .. .. ==> 0XF8006190[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_phy_bist_enable = 0x0
+ // .. .. ==> 0XF8006190[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. reg_phy_bist_force_err = 0x0
+ // .. .. ==> 0XF8006190[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. reg_phy_bist_mode = 0x0
+ // .. .. ==> 0XF8006190[6:5] = 0x00000000U
+ // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U
+ // .. .. reg_phy_invert_clkout = 0x1
+ // .. .. ==> 0XF8006190[7:7] = 0x00000001U
+ // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0
+ // .. .. ==> 0XF8006190[8:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. .. reg_phy_sel_logic = 0x0
+ // .. .. ==> 0XF8006190[9:9] = 0x00000000U
+ // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U
+ // .. .. reg_phy_ctrl_slave_ratio = 0x100
+ // .. .. ==> 0XF8006190[19:10] = 0x00000100U
+ // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U
+ // .. .. reg_phy_ctrl_slave_force = 0x0
+ // .. .. ==> 0XF8006190[20:20] = 0x00000000U
+ // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U
+ // .. .. reg_phy_ctrl_slave_delay = 0x0
+ // .. .. ==> 0XF8006190[27:21] = 0x00000000U
+ // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U
+ // .. .. reg_phy_use_rank0_delays = 0x1
+ // .. .. ==> 0XF8006190[28:28] = 0x00000001U
+ // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
+ // .. .. reg_phy_lpddr = 0x0
+ // .. .. ==> 0XF8006190[29:29] = 0x00000000U
+ // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U
+ // .. .. reg_phy_cmd_latency = 0x0
+ // .. .. ==> 0XF8006190[30:30] = 0x00000000U
+ // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U
+ // .. .. reg_phy_int_lpbk = 0x0
+ // .. .. ==> 0XF8006190[31:31] = 0x00000000U
+ // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U),
+ // .. .. reg_phy_wr_rl_delay = 0x2
+ // .. .. ==> 0XF8006194[4:0] = 0x00000002U
+ // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U
+ // .. .. reg_phy_rd_rl_delay = 0x4
+ // .. .. ==> 0XF8006194[9:5] = 0x00000004U
+ // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U
+ // .. .. reg_phy_dll_lock_diff = 0xf
+ // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
+ // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U
+ // .. .. reg_phy_use_wr_level = 0x1
+ // .. .. ==> 0XF8006194[14:14] = 0x00000001U
+ // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U
+ // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
+ // .. .. ==> 0XF8006194[15:15] = 0x00000001U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U
+ // .. .. reg_phy_use_rd_data_eye_level = 0x1
+ // .. .. ==> 0XF8006194[16:16] = 0x00000001U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U
+ // .. .. reg_phy_dis_calib_rst = 0x0
+ // .. .. ==> 0XF8006194[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_phy_ctrl_slave_delay = 0x0
+ // .. .. ==> 0XF8006194[19:18] = 0x00000000U
+ // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
+ // .. .. reg_arb_page_addr_mask = 0x0
+ // .. .. ==> 0XF8006204[31:0] = 0x00000000U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
+ // .. .. reg_arb_pri_wr_portn = 0x3ff
+ // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_wr_portn = 0x0
+ // .. .. ==> 0XF8006208[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+ // .. .. ==> 0XF8006208[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+ // .. .. ==> 0XF8006208[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_rmw_portn = 0x1
+ // .. .. ==> 0XF8006208[19:19] = 0x00000001U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU),
+ // .. .. reg_arb_pri_wr_portn = 0x3ff
+ // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_wr_portn = 0x0
+ // .. .. ==> 0XF800620C[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+ // .. .. ==> 0XF800620C[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+ // .. .. ==> 0XF800620C[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_rmw_portn = 0x1
+ // .. .. ==> 0XF800620C[19:19] = 0x00000001U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU),
+ // .. .. reg_arb_pri_wr_portn = 0x3ff
+ // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_wr_portn = 0x0
+ // .. .. ==> 0XF8006210[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+ // .. .. ==> 0XF8006210[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+ // .. .. ==> 0XF8006210[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_rmw_portn = 0x1
+ // .. .. ==> 0XF8006210[19:19] = 0x00000001U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU),
+ // .. .. reg_arb_pri_wr_portn = 0x3ff
+ // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_wr_portn = 0x0
+ // .. .. ==> 0XF8006214[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+ // .. .. ==> 0XF8006214[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+ // .. .. ==> 0XF8006214[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_rmw_portn = 0x1
+ // .. .. ==> 0XF8006214[19:19] = 0x00000001U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU),
+ // .. .. reg_arb_pri_rd_portn = 0x3ff
+ // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_rd_portn = 0x0
+ // .. .. ==> 0XF8006218[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+ // .. .. ==> 0XF8006218[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+ // .. .. ==> 0XF8006218[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_set_hpr_rd_portn = 0x0
+ // .. .. ==> 0XF8006218[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
+ // .. .. reg_arb_pri_rd_portn = 0x3ff
+ // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_rd_portn = 0x0
+ // .. .. ==> 0XF800621C[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+ // .. .. ==> 0XF800621C[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+ // .. .. ==> 0XF800621C[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_set_hpr_rd_portn = 0x0
+ // .. .. ==> 0XF800621C[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
+ // .. .. reg_arb_pri_rd_portn = 0x3ff
+ // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_rd_portn = 0x0
+ // .. .. ==> 0XF8006220[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+ // .. .. ==> 0XF8006220[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+ // .. .. ==> 0XF8006220[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_set_hpr_rd_portn = 0x0
+ // .. .. ==> 0XF8006220[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
+ // .. .. reg_arb_pri_rd_portn = 0x3ff
+ // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
+ // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
+ // .. .. reg_arb_disable_aging_rd_portn = 0x0
+ // .. .. ==> 0XF8006224[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+ // .. .. ==> 0XF8006224[17:17] = 0x00000000U
+ // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+ // .. .. ==> 0XF8006224[18:18] = 0x00000000U
+ // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
+ // .. .. reg_arb_set_hpr_rd_portn = 0x0
+ // .. .. ==> 0XF8006224[19:19] = 0x00000000U
+ // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
+ // .. .. reg_ddrc_lpddr2 = 0x0
+ // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. reg_ddrc_per_bank_refresh = 0x0
+ // .. .. ==> 0XF80062A8[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_ddrc_derate_enable = 0x0
+ // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. reg_ddrc_mr4_margin = 0x0
+ // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U),
+ // .. .. reg_ddrc_mr4_read_interval = 0x0
+ // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
+ // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
+ // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
+ // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U
+ // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
+ // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
+ // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U
+ // .. .. reg_ddrc_t_mrw = 0x5
+ // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
+ // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U
+ // .. ..
+ EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
+ // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8
+ // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U
+ // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U
+ // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
+ // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
+ // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U
+ // .. ..
+ EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
+ // .. .. START: POLL ON DCI STATUS
+ // .. .. DONE = 1
+ // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
+ // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U
+ // .. ..
+ EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+ // .. .. FINISH: POLL ON DCI STATUS
+ // .. .. START: UNLOCK DDR
+ // .. .. reg_ddrc_soft_rstb = 0x1
+ // .. .. ==> 0XF8006000[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. reg_ddrc_powerdown_en = 0x0
+ // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. .. reg_ddrc_data_bus_width = 0x0
+ // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+ // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U
+ // .. .. reg_ddrc_burst8_refresh = 0x0
+ // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U
+ // .. .. reg_ddrc_rdwr_idle_gap = 1
+ // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+ // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U
+ // .. .. reg_ddrc_dis_rd_bypass = 0x0
+ // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+ // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_act_bypass = 0x0
+ // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+ // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
+ // .. .. reg_ddrc_dis_auto_refresh = 0x0
+ // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+ // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
+ // .. .. FINISH: UNLOCK DDR
+ // .. .. START: CHECK DDR STATUS
+ // .. .. ddrc_reg_operating_mode = 1
+ // .. .. ==> 0XF8006054[2:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U
+ // .. ..
+ EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+ // .. .. FINISH: CHECK DDR STATUS
+ // .. FINISH: DDR INITIALIZATION
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_mio_init_data_1_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: OCM REMAPPING
+ // .. FINISH: OCM REMAPPING
+ // .. START: DDRIOB SETTINGS
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B40[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x0
+ // .. ==> 0XF8000B40[2:1] = 0x00000000U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000000U
+ // .. DCI_UPDATE = 0x0
+ // .. ==> 0XF8000B40[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x0
+ // .. ==> 0XF8000B40[4:4] = 0x00000000U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. DCR_TYPE = 0x0
+ // .. ==> 0XF8000B40[6:5] = 0x00000000U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000000U
+ // .. IBUF_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B40[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B40[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B40[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B40[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B44[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x0
+ // .. ==> 0XF8000B44[2:1] = 0x00000000U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000000U
+ // .. DCI_UPDATE = 0x0
+ // .. ==> 0XF8000B44[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x0
+ // .. ==> 0XF8000B44[4:4] = 0x00000000U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. DCR_TYPE = 0x0
+ // .. ==> 0XF8000B44[6:5] = 0x00000000U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000000U
+ // .. IBUF_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B44[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B44[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B44[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B44[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B48[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x1
+ // .. ==> 0XF8000B48[2:1] = 0x00000001U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000002U
+ // .. DCI_UPDATE = 0x0
+ // .. ==> 0XF8000B48[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x1
+ // .. ==> 0XF8000B48[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. DCR_TYPE = 0x3
+ // .. ==> 0XF8000B48[6:5] = 0x00000003U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000060U
+ // .. IBUF_DISABLE_MODE = 0
+ // .. ==> 0XF8000B48[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0
+ // .. ==> 0XF8000B48[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B48[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B48[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B4C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x1
+ // .. ==> 0XF8000B4C[2:1] = 0x00000001U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000002U
+ // .. DCI_UPDATE = 0x0
+ // .. ==> 0XF8000B4C[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x1
+ // .. ==> 0XF8000B4C[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. DCR_TYPE = 0x3
+ // .. ==> 0XF8000B4C[6:5] = 0x00000003U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000060U
+ // .. IBUF_DISABLE_MODE = 0
+ // .. ==> 0XF8000B4C[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0
+ // .. ==> 0XF8000B4C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B4C[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B4C[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B50[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x2
+ // .. ==> 0XF8000B50[2:1] = 0x00000002U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000004U
+ // .. DCI_UPDATE = 0x0
+ // .. ==> 0XF8000B50[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x1
+ // .. ==> 0XF8000B50[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. DCR_TYPE = 0x3
+ // .. ==> 0XF8000B50[6:5] = 0x00000003U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000060U
+ // .. IBUF_DISABLE_MODE = 0
+ // .. ==> 0XF8000B50[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0
+ // .. ==> 0XF8000B50[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B50[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B50[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B54[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x2
+ // .. ==> 0XF8000B54[2:1] = 0x00000002U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000004U
+ // .. DCI_UPDATE = 0x0
+ // .. ==> 0XF8000B54[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x1
+ // .. ==> 0XF8000B54[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. DCR_TYPE = 0x3
+ // .. ==> 0XF8000B54[6:5] = 0x00000003U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000060U
+ // .. IBUF_DISABLE_MODE = 0
+ // .. ==> 0XF8000B54[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0
+ // .. ==> 0XF8000B54[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B54[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B54[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
+ // .. INP_POWER = 0x0
+ // .. ==> 0XF8000B58[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. INP_TYPE = 0x0
+ // .. ==> 0XF8000B58[2:1] = 0x00000000U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000000U
+ // .. DCI_UPDATE = 0x0
+ // .. ==> 0XF8000B58[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. TERM_EN = 0x0
+ // .. ==> 0XF8000B58[4:4] = 0x00000000U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. DCR_TYPE = 0x0
+ // .. ==> 0XF8000B58[6:5] = 0x00000000U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000000U
+ // .. IBUF_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B58[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. TERM_DISABLE_MODE = 0x0
+ // .. ==> 0XF8000B58[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. OUTPUT_EN = 0x3
+ // .. ==> 0XF8000B58[10:9] = 0x00000003U
+ // .. ==> MASK : 0x00000600U VAL : 0x00000600U
+ // .. PULLUP_EN = 0x0
+ // .. ==> 0XF8000B58[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
+ // .. DRIVE_P = 0x1c
+ // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
+ // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
+ // .. DRIVE_N = 0xc
+ // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
+ // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
+ // .. SLEW_P = 0x3
+ // .. ==> 0XF8000B5C[18:14] = 0x00000003U
+ // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U
+ // .. SLEW_N = 0x3
+ // .. ==> 0XF8000B5C[23:19] = 0x00000003U
+ // .. ==> MASK : 0x00F80000U VAL : 0x00180000U
+ // .. GTL = 0x0
+ // .. ==> 0XF8000B5C[26:24] = 0x00000000U
+ // .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. RTERM = 0x0
+ // .. ==> 0XF8000B5C[31:27] = 0x00000000U
+ // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
+ // .. DRIVE_P = 0x1c
+ // .. ==> 0XF8000B60[6:0] = 0x0000001CU
+ // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
+ // .. DRIVE_N = 0xc
+ // .. ==> 0XF8000B60[13:7] = 0x0000000CU
+ // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
+ // .. SLEW_P = 0x6
+ // .. ==> 0XF8000B60[18:14] = 0x00000006U
+ // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
+ // .. SLEW_N = 0x1f
+ // .. ==> 0XF8000B60[23:19] = 0x0000001FU
+ // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
+ // .. GTL = 0x0
+ // .. ==> 0XF8000B60[26:24] = 0x00000000U
+ // .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. RTERM = 0x0
+ // .. ==> 0XF8000B60[31:27] = 0x00000000U
+ // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
+ // .. DRIVE_P = 0x1c
+ // .. ==> 0XF8000B64[6:0] = 0x0000001CU
+ // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
+ // .. DRIVE_N = 0xc
+ // .. ==> 0XF8000B64[13:7] = 0x0000000CU
+ // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
+ // .. SLEW_P = 0x6
+ // .. ==> 0XF8000B64[18:14] = 0x00000006U
+ // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
+ // .. SLEW_N = 0x1f
+ // .. ==> 0XF8000B64[23:19] = 0x0000001FU
+ // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
+ // .. GTL = 0x0
+ // .. ==> 0XF8000B64[26:24] = 0x00000000U
+ // .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. RTERM = 0x0
+ // .. ==> 0XF8000B64[31:27] = 0x00000000U
+ // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
+ // .. DRIVE_P = 0x1c
+ // .. ==> 0XF8000B68[6:0] = 0x0000001CU
+ // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU
+ // .. DRIVE_N = 0xc
+ // .. ==> 0XF8000B68[13:7] = 0x0000000CU
+ // .. ==> MASK : 0x00003F80U VAL : 0x00000600U
+ // .. SLEW_P = 0x6
+ // .. ==> 0XF8000B68[18:14] = 0x00000006U
+ // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
+ // .. SLEW_N = 0x1f
+ // .. ==> 0XF8000B68[23:19] = 0x0000001FU
+ // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
+ // .. GTL = 0x0
+ // .. ==> 0XF8000B68[26:24] = 0x00000000U
+ // .. ==> MASK : 0x07000000U VAL : 0x00000000U
+ // .. RTERM = 0x0
+ // .. ==> 0XF8000B68[31:27] = 0x00000000U
+ // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
+ // .. VREF_INT_EN = 0x1
+ // .. ==> 0XF8000B6C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. VREF_SEL = 0x4
+ // .. ==> 0XF8000B6C[4:1] = 0x00000004U
+ // .. ==> MASK : 0x0000001EU VAL : 0x00000008U
+ // .. VREF_EXT_EN = 0x0
+ // .. ==> 0XF8000B6C[6:5] = 0x00000000U
+ // .. ==> MASK : 0x00000060U VAL : 0x00000000U
+ // .. VREF_PULLUP_EN = 0x0
+ // .. ==> 0XF8000B6C[8:7] = 0x00000000U
+ // .. ==> MASK : 0x00000180U VAL : 0x00000000U
+ // .. REFIO_EN = 0x1
+ // .. ==> 0XF8000B6C[9:9] = 0x00000001U
+ // .. ==> MASK : 0x00000200U VAL : 0x00000200U
+ // .. REFIO_PULLUP_EN = 0x0
+ // .. ==> 0XF8000B6C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DRST_B_PULLUP_EN = 0x0
+ // .. ==> 0XF8000B6C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // .. CKE_PULLUP_EN = 0x0
+ // .. ==> 0XF8000B6C[14:14] = 0x00000000U
+ // .. ==> MASK : 0x00004000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000B6C, 0x000073FFU ,0x00000209U),
+ // .. .. START: ASSERT RESET
+ // .. .. RESET = 1
+ // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. VRN_OUT = 0x1
+ // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U),
+ // .. .. FINISH: ASSERT RESET
+ // .. .. START: DEASSERT RESET
+ // .. .. RESET = 0
+ // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. .. VRN_OUT = 0x1
+ // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
+ // .. .. FINISH: DEASSERT RESET
+ // .. .. RESET = 0x1
+ // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+ // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. .. ENABLE = 0x1
+ // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
+ // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. .. VRP_TRI = 0x0
+ // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
+ // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. .. VRN_TRI = 0x0
+ // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
+ // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. .. VRP_OUT = 0x0
+ // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
+ // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
+ // .. .. VRN_OUT = 0x1
+ // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+ // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
+ // .. .. NREF_OPT1 = 0x0
+ // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
+ // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U
+ // .. .. NREF_OPT2 = 0x0
+ // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
+ // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U
+ // .. .. NREF_OPT4 = 0x1
+ // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
+ // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U
+ // .. .. PREF_OPT1 = 0x0
+ // .. .. ==> 0XF8000B70[16:14] = 0x00000000U
+ // .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U
+ // .. .. PREF_OPT2 = 0x0
+ // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
+ // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U
+ // .. .. UPDATE_CONTROL = 0x0
+ // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
+ // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U
+ // .. .. INIT_COMPLETE = 0x0
+ // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
+ // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U
+ // .. .. TST_CLK = 0x0
+ // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
+ // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U
+ // .. .. TST_HLN = 0x0
+ // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
+ // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U
+ // .. .. TST_HLP = 0x0
+ // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
+ // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U
+ // .. .. TST_RST = 0x0
+ // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
+ // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
+ // .. .. INT_DCI_EN = 0x0
+ // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
+ // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U
+ // .. ..
+ EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U),
+ // .. FINISH: DDRIOB SETTINGS
+ // .. START: MIO PROGRAMMING
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000700[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000700[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000700[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000700[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000700[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000700[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000700[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000700[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000700[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000704[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000704[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000704[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000704[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000704[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000704[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000704[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000704[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000704[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00000702U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000708[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000708[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000708[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000708[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000708[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000708[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000708[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000708[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000708[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000702U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800070C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF800070C[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800070C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800070C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800070C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF800070C[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 3
+ // .. ==> 0XF800070C[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF800070C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800070C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000702U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000710[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000710[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000710[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000710[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000710[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000710[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000710[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000710[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000710[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000702U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000714[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000714[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000714[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000714[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000714[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000714[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000714[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000714[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000714[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000702U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000718[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000718[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000718[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000718[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000718[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000718[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000718[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000718[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000718[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000702U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800071C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800071C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800071C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800071C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800071C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800071C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF800071C[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF800071C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800071C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000720[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000720[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000720[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000720[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000720[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000720[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000720[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000720[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000720[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000700U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000724[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000724[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000724[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000724[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000724[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000724[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000724[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000724[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000724[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000728[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000728[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000728[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000728[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000728[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000728[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000728[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000728[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000728[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800072C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800072C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800072C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800072C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800072C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800072C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF800072C[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF800072C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800072C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000730[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000730[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000730[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000730[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000730[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000730[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000730[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000730[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000730[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000734[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000734[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000734[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000734[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000734[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000734[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000734[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000734[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000734[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000738[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000738[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000738[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000738[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000738[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF8000738[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF8000738[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000738[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000738[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800073C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800073C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800073C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800073C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800073C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF800073C[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 3
+ // .. ==> 0XF800073C[11:9] = 0x00000003U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
+ // .. PULLUP = 0
+ // .. ==> 0XF800073C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800073C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00000600U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000740[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000740[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000740[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000740[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000740[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000740[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000740[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000740[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000740[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000302U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000744[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000744[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000744[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000744[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000744[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000744[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000744[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000744[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000744[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000302U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000748[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000748[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000748[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000748[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000748[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000748[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000748[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000748[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000748[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000302U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800074C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF800074C[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800074C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800074C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800074C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF800074C[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF800074C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800074C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800074C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000302U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000750[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000750[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000750[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000750[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000750[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000750[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000750[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000750[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000750[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000302U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000754[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000754[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000754[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000754[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000754[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000754[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000754[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000754[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000754[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000302U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000758[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000758[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000758[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000758[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000758[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000758[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000758[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000758[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000758[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000303U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF800075C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF800075C[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800075C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800075C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800075C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF800075C[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF800075C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800075C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800075C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000303U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000760[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000760[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000760[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000760[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000760[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000760[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000760[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000760[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000760[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000303U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000764[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000764[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000764[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000764[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000764[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000764[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000764[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000764[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000764[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000303U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000768[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF8000768[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF8000768[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000768[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000768[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000768[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000768[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000768[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000768[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000303U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF800076C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 1
+ // .. ==> 0XF800076C[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. L1_SEL = 0
+ // .. ==> 0XF800076C[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800076C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800076C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF800076C[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF800076C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800076C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800076C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000303U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000770[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000770[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000770[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000770[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000770[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000770[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000770[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000770[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000770[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000304U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000774[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000774[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000774[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000774[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000774[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000774[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000774[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000774[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000774[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000305U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000778[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000778[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000778[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000778[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000778[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000778[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000778[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000778[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000778[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000304U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF800077C[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800077C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF800077C[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800077C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800077C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF800077C[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF800077C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800077C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800077C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000305U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000780[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000780[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000780[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000780[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000780[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000780[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000780[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000780[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000780[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000304U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000784[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000784[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000784[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000784[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000784[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000784[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000784[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000784[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000784[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000304U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000788[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000788[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000788[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000788[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000788[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000788[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000788[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000788[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000788[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000304U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800078C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800078C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF800078C[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800078C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800078C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF800078C[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF800078C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800078C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800078C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000304U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF8000790[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000790[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000790[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000790[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000790[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000790[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000790[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000790[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000790[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000305U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000794[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000794[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000794[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000794[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000794[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000794[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000794[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000794[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000794[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000304U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF8000798[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF8000798[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF8000798[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF8000798[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF8000798[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF8000798[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF8000798[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF8000798[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF8000798[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000304U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF800079C[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF800079C[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 1
+ // .. ==> 0XF800079C[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. L2_SEL = 0
+ // .. ==> 0XF800079C[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF800079C[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 1
+ // .. ==> 0XF800079C[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF800079C[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF800079C[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF800079C[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000304U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007A0[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007A0[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007A0[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007A0[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007A0[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 1
+ // .. ==> 0XF80007A0[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007A0[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007A0[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007A0[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000380U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007A4[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007A4[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007A4[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007A4[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007A4[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 1
+ // .. ==> 0XF80007A4[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007A4[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007A4[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007A4[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000380U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007A8[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007A8[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007A8[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007A8[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007A8[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 1
+ // .. ==> 0XF80007A8[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007A8[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007A8[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007A8[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000380U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007AC[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007AC[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007AC[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007AC[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007AC[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 1
+ // .. ==> 0XF80007AC[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007AC[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007AC[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007AC[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000380U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007B0[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007B0[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007B0[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007B0[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007B0[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 1
+ // .. ==> 0XF80007B0[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007B0[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007B0[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007B0[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000380U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007B4[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007B4[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007B4[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007B4[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007B4[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 1
+ // .. ==> 0XF80007B4[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007B4[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007B4[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007B4[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000380U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF80007B8[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. Speed = 0
+ // .. ==> 0XF80007B8[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007B8[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007B8[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007B8[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007B8, 0x00003F01U ,0x00000201U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF80007BC[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. Speed = 0
+ // .. ==> 0XF80007BC[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007BC[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007BC[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007BC[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007BC, 0x00003F01U ,0x00000201U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007C0[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007C0[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007C0[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007C0[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 7
+ // .. ==> 0XF80007C0[7:5] = 0x00000007U
+ // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U
+ // .. Speed = 0
+ // .. ==> 0XF80007C0[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007C0[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007C0[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007C0[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF80007C4[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007C4[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007C4[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007C4[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 7
+ // .. ==> 0XF80007C4[7:5] = 0x00000007U
+ // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U
+ // .. Speed = 0
+ // .. ==> 0XF80007C4[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007C4[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007C4[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007C4[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF80007C8[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007C8[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007C8[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007C8[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF80007C8[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF80007C8[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007C8[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007C8[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007C8[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00000201U),
+ // .. TRI_ENABLE = 1
+ // .. ==> 0XF80007CC[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007CC[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007CC[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007CC[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 0
+ // .. ==> 0XF80007CC[7:5] = 0x00000000U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
+ // .. Speed = 0
+ // .. ==> 0XF80007CC[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007CC[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007CC[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007CC[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00000201U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007D0[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007D0[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007D0[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007D0[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007D0[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007D0[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007D0[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007D0[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007D0[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U),
+ // .. TRI_ENABLE = 0
+ // .. ==> 0XF80007D4[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // .. L0_SEL = 0
+ // .. ==> 0XF80007D4[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. L1_SEL = 0
+ // .. ==> 0XF80007D4[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. L2_SEL = 0
+ // .. ==> 0XF80007D4[4:3] = 0x00000000U
+ // .. ==> MASK : 0x00000018U VAL : 0x00000000U
+ // .. L3_SEL = 4
+ // .. ==> 0XF80007D4[7:5] = 0x00000004U
+ // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
+ // .. Speed = 0
+ // .. ==> 0XF80007D4[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. IO_Type = 1
+ // .. ==> 0XF80007D4[11:9] = 0x00000001U
+ // .. ==> MASK : 0x00000E00U VAL : 0x00000200U
+ // .. PULLUP = 0
+ // .. ==> 0XF80007D4[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. DisableRcvr = 0
+ // .. ==> 0XF80007D4[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U),
+ // .. SDIO0_WP_SEL = 46
+ // .. ==> 0XF8000830[5:0] = 0x0000002EU
+ // .. ==> MASK : 0x0000003FU VAL : 0x0000002EU
+ // .. SDIO0_CD_SEL = 47
+ // .. ==> 0XF8000830[21:16] = 0x0000002FU
+ // .. ==> MASK : 0x003F0000U VAL : 0x002F0000U
+ // ..
+ EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x002F002EU),
+ // .. FINISH: MIO PROGRAMMING
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_peripherals_init_data_1_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+ // .. IBUF_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B48[7:7] = 0x00000001U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. TERM_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B48[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // ..
+ EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
+ // .. IBUF_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B4C[7:7] = 0x00000001U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. TERM_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B4C[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // ..
+ EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
+ // .. IBUF_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B50[7:7] = 0x00000001U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. TERM_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B50[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // ..
+ EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
+ // .. IBUF_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B54[7:7] = 0x00000001U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000080U
+ // .. TERM_DISABLE_MODE = 0x1
+ // .. ==> 0XF8000B54[8:8] = 0x00000001U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000100U
+ // ..
+ EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
+ // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // .. START: SRAM/NOR SET OPMODE
+ // .. FINISH: SRAM/NOR SET OPMODE
+ // .. START: UART REGISTERS
+ // .. BDIV = 0x6
+ // .. ==> 0XE0001034[7:0] = 0x00000006U
+ // .. ==> MASK : 0x000000FFU VAL : 0x00000006U
+ // ..
+ EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
+ // .. CD = 0x3e
+ // .. ==> 0XE0001018[15:0] = 0x0000003EU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU
+ // ..
+ EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
+ // .. STPBRK = 0x0
+ // .. ==> 0XE0001000[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. STTBRK = 0x0
+ // .. ==> 0XE0001000[7:7] = 0x00000000U
+ // .. ==> MASK : 0x00000080U VAL : 0x00000000U
+ // .. RSTTO = 0x0
+ // .. ==> 0XE0001000[6:6] = 0x00000000U
+ // .. ==> MASK : 0x00000040U VAL : 0x00000000U
+ // .. TXDIS = 0x0
+ // .. ==> 0XE0001000[5:5] = 0x00000000U
+ // .. ==> MASK : 0x00000020U VAL : 0x00000000U
+ // .. TXEN = 0x1
+ // .. ==> 0XE0001000[4:4] = 0x00000001U
+ // .. ==> MASK : 0x00000010U VAL : 0x00000010U
+ // .. RXDIS = 0x0
+ // .. ==> 0XE0001000[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. RXEN = 0x1
+ // .. ==> 0XE0001000[2:2] = 0x00000001U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000004U
+ // .. TXRES = 0x1
+ // .. ==> 0XE0001000[1:1] = 0x00000001U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000002U
+ // .. RXRES = 0x1
+ // .. ==> 0XE0001000[0:0] = 0x00000001U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000001U
+ // ..
+ EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
+ // .. IRMODE = 0x0
+ // .. ==> 0XE0001004[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. UCLKEN = 0x0
+ // .. ==> 0XE0001004[10:10] = 0x00000000U
+ // .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. CHMODE = 0x0
+ // .. ==> 0XE0001004[9:8] = 0x00000000U
+ // .. ==> MASK : 0x00000300U VAL : 0x00000000U
+ // .. NBSTOP = 0x0
+ // .. ==> 0XE0001004[7:6] = 0x00000000U
+ // .. ==> MASK : 0x000000C0U VAL : 0x00000000U
+ // .. PAR = 0x4
+ // .. ==> 0XE0001004[5:3] = 0x00000004U
+ // .. ==> MASK : 0x00000038U VAL : 0x00000020U
+ // .. CHRL = 0x0
+ // .. ==> 0XE0001004[2:1] = 0x00000000U
+ // .. ==> MASK : 0x00000006U VAL : 0x00000000U
+ // .. CLKS = 0x0
+ // .. ==> 0XE0001004[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U),
+ // .. FINISH: UART REGISTERS
+ // .. START: QSPI REGISTERS
+ // .. Holdb_dr = 1
+ // .. ==> 0XE000D000[19:19] = 0x00000001U
+ // .. ==> MASK : 0x00080000U VAL : 0x00080000U
+ // ..
+ EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
+ // .. FINISH: QSPI REGISTERS
+ // .. START: PL POWER ON RESET REGISTERS
+ // .. PCFG_POR_CNT_4K = 0
+ // .. ==> 0XF8007000[29:29] = 0x00000000U
+ // .. ==> MASK : 0x20000000U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
+ // .. FINISH: PL POWER ON RESET REGISTERS
+ // .. START: SMC TIMING CALCULATION REGISTER UPDATE
+ // .. .. START: NAND SET CYCLE
+ // .. .. FINISH: NAND SET CYCLE
+ // .. .. START: OPMODE
+ // .. .. FINISH: OPMODE
+ // .. .. START: DIRECT COMMAND
+ // .. .. FINISH: DIRECT COMMAND
+ // .. .. START: SRAM/NOR CS0 SET CYCLE
+ // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
+ // .. .. START: DIRECT COMMAND
+ // .. .. FINISH: DIRECT COMMAND
+ // .. .. START: NOR CS0 BASE ADDRESS
+ // .. .. FINISH: NOR CS0 BASE ADDRESS
+ // .. .. START: SRAM/NOR CS1 SET CYCLE
+ // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
+ // .. .. START: DIRECT COMMAND
+ // .. .. FINISH: DIRECT COMMAND
+ // .. .. START: NOR CS1 BASE ADDRESS
+ // .. .. FINISH: NOR CS1 BASE ADDRESS
+ // .. .. START: USB RESET
+ // .. .. .. START: USB0 RESET
+ // .. .. .. .. START: DIR MODE BANK 0
+ // .. .. .. .. FINISH: DIR MODE BANK 0
+ // .. .. .. .. START: DIR MODE BANK 1
+ // .. .. .. .. FINISH: DIR MODE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. START: OUTPUT ENABLE BANK 0
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+ // .. .. .. .. START: OUTPUT ENABLE BANK 1
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. START: ADD 1 MS DELAY
+ // .. .. .. ..
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ // .. .. .. .. FINISH: ADD 1 MS DELAY
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. FINISH: USB0 RESET
+ // .. .. .. START: USB1 RESET
+ // .. .. .. .. START: DIR MODE BANK 0
+ // .. .. .. .. FINISH: DIR MODE BANK 0
+ // .. .. .. .. START: DIR MODE BANK 1
+ // .. .. .. .. FINISH: DIR MODE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. START: OUTPUT ENABLE BANK 0
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+ // .. .. .. .. START: OUTPUT ENABLE BANK 1
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. START: ADD 1 MS DELAY
+ // .. .. .. ..
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ // .. .. .. .. FINISH: ADD 1 MS DELAY
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. FINISH: USB1 RESET
+ // .. .. FINISH: USB RESET
+ // .. .. START: ENET RESET
+ // .. .. .. START: ENET0 RESET
+ // .. .. .. .. START: DIR MODE BANK 0
+ // .. .. .. .. FINISH: DIR MODE BANK 0
+ // .. .. .. .. START: DIR MODE BANK 1
+ // .. .. .. .. FINISH: DIR MODE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. START: OUTPUT ENABLE BANK 0
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+ // .. .. .. .. START: OUTPUT ENABLE BANK 1
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. START: ADD 1 MS DELAY
+ // .. .. .. ..
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ // .. .. .. .. FINISH: ADD 1 MS DELAY
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. FINISH: ENET0 RESET
+ // .. .. .. START: ENET1 RESET
+ // .. .. .. .. START: DIR MODE BANK 0
+ // .. .. .. .. FINISH: DIR MODE BANK 0
+ // .. .. .. .. START: DIR MODE BANK 1
+ // .. .. .. .. FINISH: DIR MODE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. START: OUTPUT ENABLE BANK 0
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+ // .. .. .. .. START: OUTPUT ENABLE BANK 1
+ // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+ // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. START: ADD 1 MS DELAY
+ // .. .. .. ..
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ // .. .. .. .. FINISH: ADD 1 MS DELAY
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. FINISH: ENET1 RESET
+ // .. .. FINISH: ENET RESET
+ // .. .. START: I2C RESET
+ // .. .. .. START: I2C0 RESET
+ // .. .. .. .. START: DIR MODE GPIO BANK0
+ // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+ // .. .. .. .. START: DIR MODE GPIO BANK1
+ // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. START: OUTPUT ENABLE
+ // .. .. .. .. FINISH: OUTPUT ENABLE
+ // .. .. .. .. START: OUTPUT ENABLE
+ // .. .. .. .. FINISH: OUTPUT ENABLE
+ // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. START: ADD 1 MS DELAY
+ // .. .. .. ..
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ // .. .. .. .. FINISH: ADD 1 MS DELAY
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. FINISH: I2C0 RESET
+ // .. .. .. START: I2C1 RESET
+ // .. .. .. .. START: DIR MODE GPIO BANK0
+ // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+ // .. .. .. .. START: DIR MODE GPIO BANK1
+ // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. START: OUTPUT ENABLE
+ // .. .. .. .. FINISH: OUTPUT ENABLE
+ // .. .. .. .. START: OUTPUT ENABLE
+ // .. .. .. .. FINISH: OUTPUT ENABLE
+ // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+ // .. .. .. .. START: ADD 1 MS DELAY
+ // .. .. .. ..
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ // .. .. .. .. FINISH: ADD 1 MS DELAY
+ // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+ // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+ // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+ // .. .. .. FINISH: I2C1 RESET
+ // .. .. FINISH: I2C RESET
+ // .. .. START: NOR CHIP SELECT
+ // .. .. .. START: DIR MODE BANK 0
+ // .. .. .. FINISH: DIR MODE BANK 0
+ // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+ // .. .. .. START: OUTPUT ENABLE BANK 0
+ // .. .. .. FINISH: OUTPUT ENABLE BANK 0
+ // .. .. FINISH: NOR CHIP SELECT
+ // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_post_config_1_0[] = {
+ // START: top
+ // .. START: SLCR SETTINGS
+ // .. UNLOCK_KEY = 0XDF0D
+ // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
+ // ..
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+ // .. FINISH: SLCR SETTINGS
+ // .. START: ENABLING LEVEL SHIFTER
+ // .. USER_INP_ICT_EN_0 = 3
+ // .. ==> 0XF8000900[1:0] = 0x00000003U
+ // .. ==> MASK : 0x00000003U VAL : 0x00000003U
+ // .. USER_INP_ICT_EN_1 = 3
+ // .. ==> 0XF8000900[3:2] = 0x00000003U
+ // .. ==> MASK : 0x0000000CU VAL : 0x0000000CU
+ // ..
+ EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
+ // .. FINISH: ENABLING LEVEL SHIFTER
+ // .. START: FPGA RESETS TO 0
+ // .. reserved_3 = 0
+ // .. ==> 0XF8000240[31:25] = 0x00000000U
+ // .. ==> MASK : 0xFE000000U VAL : 0x00000000U
+ // .. FPGA_ACP_RST = 0
+ // .. ==> 0XF8000240[24:24] = 0x00000000U
+ // .. ==> MASK : 0x01000000U VAL : 0x00000000U
+ // .. FPGA_AXDS3_RST = 0
+ // .. ==> 0XF8000240[23:23] = 0x00000000U
+ // .. ==> MASK : 0x00800000U VAL : 0x00000000U
+ // .. FPGA_AXDS2_RST = 0
+ // .. ==> 0XF8000240[22:22] = 0x00000000U
+ // .. ==> MASK : 0x00400000U VAL : 0x00000000U
+ // .. FPGA_AXDS1_RST = 0
+ // .. ==> 0XF8000240[21:21] = 0x00000000U
+ // .. ==> MASK : 0x00200000U VAL : 0x00000000U
+ // .. FPGA_AXDS0_RST = 0
+ // .. ==> 0XF8000240[20:20] = 0x00000000U
+ // .. ==> MASK : 0x00100000U VAL : 0x00000000U
+ // .. reserved_2 = 0
+ // .. ==> 0XF8000240[19:18] = 0x00000000U
+ // .. ==> MASK : 0x000C0000U VAL : 0x00000000U
+ // .. FSSW1_FPGA_RST = 0
+ // .. ==> 0XF8000240[17:17] = 0x00000000U
+ // .. ==> MASK : 0x00020000U VAL : 0x00000000U
+ // .. FSSW0_FPGA_RST = 0
+ // .. ==> 0XF8000240[16:16] = 0x00000000U
+ // .. ==> MASK : 0x00010000U VAL : 0x00000000U
+ // .. reserved_1 = 0
+ // .. ==> 0XF8000240[15:14] = 0x00000000U
+ // .. ==> MASK : 0x0000C000U VAL : 0x00000000U
+ // .. FPGA_FMSW1_RST = 0
+ // .. ==> 0XF8000240[13:13] = 0x00000000U
+ // .. ==> MASK : 0x00002000U VAL : 0x00000000U
+ // .. FPGA_FMSW0_RST = 0
+ // .. ==> 0XF8000240[12:12] = 0x00000000U
+ // .. ==> MASK : 0x00001000U VAL : 0x00000000U
+ // .. FPGA_DMA3_RST = 0
+ // .. ==> 0XF8000240[11:11] = 0x00000000U
+ // .. ==> MASK : 0x00000800U VAL : 0x00000000U
+ // .. FPGA_DMA2_RST = 0
+ // .. ==> 0XF8000240[10:10] = 0x00000000U
+ // .. ==> MASK : 0x00000400U VAL : 0x00000000U
+ // .. FPGA_DMA1_RST = 0
+ // .. ==> 0XF8000240[9:9] = 0x00000000U
+ // .. ==> MASK : 0x00000200U VAL : 0x00000000U
+ // .. FPGA_DMA0_RST = 0
+ // .. ==> 0XF8000240[8:8] = 0x00000000U
+ // .. ==> MASK : 0x00000100U VAL : 0x00000000U
+ // .. reserved = 0
+ // .. ==> 0XF8000240[7:4] = 0x00000000U
+ // .. ==> MASK : 0x000000F0U VAL : 0x00000000U
+ // .. FPGA3_OUT_RST = 0
+ // .. ==> 0XF8000240[3:3] = 0x00000000U
+ // .. ==> MASK : 0x00000008U VAL : 0x00000000U
+ // .. FPGA2_OUT_RST = 0
+ // .. ==> 0XF8000240[2:2] = 0x00000000U
+ // .. ==> MASK : 0x00000004U VAL : 0x00000000U
+ // .. FPGA1_OUT_RST = 0
+ // .. ==> 0XF8000240[1:1] = 0x00000000U
+ // .. ==> MASK : 0x00000002U VAL : 0x00000000U
+ // .. FPGA0_OUT_RST = 0
+ // .. ==> 0XF8000240[0:0] = 0x00000000U
+ // .. ==> MASK : 0x00000001U VAL : 0x00000000U
+ // ..
+ EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
+ // .. FINISH: FPGA RESETS TO 0
+ // .. START: AFI REGISTERS
+ // .. .. START: AFI0 REGISTERS
+ // .. .. FINISH: AFI0 REGISTERS
+ // .. .. START: AFI1 REGISTERS
+ // .. .. FINISH: AFI1 REGISTERS
+ // .. .. START: AFI2 REGISTERS
+ // .. .. FINISH: AFI2 REGISTERS
+ // .. .. START: AFI3 REGISTERS
+ // .. .. FINISH: AFI3 REGISTERS
+ // .. FINISH: AFI REGISTERS
+ // .. START: LOCK IT BACK
+ // .. LOCK_KEY = 0X767B
+ // .. ==> 0XF8000004[15:0] = 0x0000767BU
+ // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
+ // ..
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+ // .. FINISH: LOCK IT BACK
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+unsigned long ps7_debug_1_0[] = {
+ // START: top
+ // .. START: CROSS TRIGGER CONFIGURATIONS
+ // .. .. START: UNLOCKING CTI REGISTERS
+ // .. .. KEY = 0XC5ACCE55
+ // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
+ // .. ..
+ EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
+ // .. .. KEY = 0XC5ACCE55
+ // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
+ // .. ..
+ EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
+ // .. .. KEY = 0XC5ACCE55
+ // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
+ // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
+ // .. ..
+ EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
+ // .. .. FINISH: UNLOCKING CTI REGISTERS
+ // .. .. START: ENABLING CTI MODULES AND CHANNELS
+ // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
+ // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+ // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+ // .. FINISH: CROSS TRIGGER CONFIGURATIONS
+ // FINISH: top
+ //
+ EMIT_EXIT(),
+
+ //
+};
+
+
+#include "xil_io.h"
+#define PS7_MASK_POLL_TIME 100000000
+
+char*
+getPS7MessageInfo(unsigned key) {
+
+ char* err_msg = "";
+ switch (key) {
+ case PS7_INIT_SUCCESS: err_msg = "PS7 initialization successful"; break;
+ case PS7_INIT_CORRUPT: err_msg = "PS7 init Data Corrupted"; break;
+ case PS7_INIT_TIMEOUT: err_msg = "PS7 init mask poll timeout"; break;
+ case PS7_POLL_FAILED_DDR_INIT: err_msg = "Mask Poll failed for DDR Init"; break;
+ case PS7_POLL_FAILED_DMA: err_msg = "Mask Poll failed for PLL Init"; break;
+ case PS7_POLL_FAILED_PLL: err_msg = "Mask Poll failed for DMA done bit"; break;
+ default: err_msg = "Undefined error status"; break;
+ }
+
+ return err_msg;
+}
+
+unsigned long
+ps7GetSiliconVersion () {
+ // Read PS version from MCTRL register [31:28]
+ unsigned long mask = 0xF0000000;
+ unsigned long *addr = (unsigned long*) 0XF8007080;
+ unsigned long ps_version = (*addr & mask) >> 28;
+ return ps_version;
+}
+
+void mask_write (unsigned long add , unsigned long mask, unsigned long val ) {
+ unsigned long *addr = (unsigned long*) add;
+ *addr = ( val & mask ) | ( *addr & ~mask);
+ //xil_printf("MaskWrite : 0x%x--> 0x%x \n \r" ,add, *addr);
+}
+
+
+int mask_poll(unsigned long add , unsigned long mask ) {
+ volatile unsigned long *addr = (volatile unsigned long*) add;
+ int i = 0;
+ while (!(*addr & mask)) {
+ if (i == PS7_MASK_POLL_TIME) {
+ return -1;
+ }
+ i++;
+ }
+ return 1;
+ //xil_printf("MaskPoll : 0x%x --> 0x%x \n \r" , add, *addr);
+}
+
+unsigned long mask_read(unsigned long add , unsigned long mask ) {
+ unsigned long *addr = (unsigned long*) add;
+ unsigned long val = (*addr & mask);
+ //xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val);
+ return val;
+}
+
+
+
+int
+ps7_config(unsigned long * ps7_config_init)
+{
+ unsigned long *ptr = ps7_config_init;
+
+ unsigned long opcode; // current instruction ..
+ unsigned long args[16]; // no opcode has so many args ...
+ int numargs; // number of arguments of this instruction
+ int j; // general purpose index
+
+ volatile unsigned long *addr; // some variable to make code readable
+ unsigned long val,mask; // some variable to make code readable
+
+ int finish = -1 ; // loop while this is negative !
+ int i = 0; // Timeout variable
+
+ while( finish < 0 ) {
+ numargs = ptr[0] & 0xF;
+ opcode = ptr[0] >> 4;
+
+ for( j = 0 ; j < numargs ; j ++ )
+ args[j] = ptr[j+1];
+ ptr += numargs + 1;
+
+
+ switch ( opcode ) {
+
+ case OPCODE_EXIT:
+ finish = PS7_INIT_SUCCESS;
+ break;
+
+ case OPCODE_CLEAR:
+ addr = (unsigned long*) args[0];
+ *addr = 0;
+ break;
+
+ case OPCODE_WRITE:
+ addr = (unsigned long*) args[0];
+ val = args[1];
+ *addr = val;
+ break;
+
+ case OPCODE_MASKWRITE:
+ addr = (unsigned long*) args[0];
+ mask = args[1];
+ val = args[2];
+ *addr = ( val & mask ) | ( *addr & ~mask);
+ break;
+
+ case OPCODE_MASKPOLL:
+ addr = (unsigned long*) args[0];
+ mask = args[1];
+ i = 0;
+ while (!(*addr & mask)) {
+ if (i == PS7_MASK_POLL_TIME) {
+ finish = PS7_INIT_TIMEOUT;
+ break;
+ }
+ i++;
+ }
+ break;
+ case OPCODE_MASKDELAY:
+ addr = (unsigned long*) args[0];
+ mask = args[1];
+ int delay = get_number_of_cycles_for_delay(mask);
+ perf_reset_and_start_timer();
+ while ((*addr < delay)) {
+ }
+ break;
+ default:
+ finish = PS7_INIT_CORRUPT;
+ break;
+ }
+ }
+ return finish;
+}
+
+unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0;
+unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0;
+unsigned long *ps7_clock_init_data = ps7_clock_init_data_3_0;
+unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0;
+unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
+
+int
+ps7_post_config()
+{
+ // Get the PS_VERSION on run time
+ unsigned long si_ver = ps7GetSiliconVersion ();
+ int ret = -1;
+ if (si_ver == PCW_SILICON_VERSION_1) {
+ ret = ps7_config (ps7_post_config_1_0);
+ if (ret != PS7_INIT_SUCCESS) return ret;
+ } else if (si_ver == PCW_SILICON_VERSION_2) {
+ ret = ps7_config (ps7_post_config_2_0);
+ if (ret != PS7_INIT_SUCCESS) return ret;
+ } else {
+ ret = ps7_config (ps7_post_config_3_0);
+ if (ret != PS7_INIT_SUCCESS) return ret;
+ }
+ return PS7_INIT_SUCCESS;
+}
+
+int
+ps7_debug()
+{
+ // Get the PS_VERSION on run time
+ unsigned long si_ver = ps7GetSiliconVersion ();
+ int ret = -1;
+ if (si_ver == PCW_SILICON_VERSION_1) {
+ ret = ps7_config (ps7_debug_1_0);
+ if (ret != PS7_INIT_SUCCESS) return ret;
+ } else if (si_ver == PCW_SILICON_VERSION_2) {
+ ret = ps7_config (ps7_debug_2_0);
+ if (ret != PS7_INIT_SUCCESS) return ret;
+ } else {
+ ret = ps7_config (ps7_debug_3_0);
+ if (ret != PS7_INIT_SUCCESS) return ret;
+ }
+ return PS7_INIT_SUCCESS;
+}
+
+int
+ps7_init()
+{
+ // Get the PS_VERSION on run time
+ unsigned long si_ver = ps7GetSiliconVersion ();
+ int ret;
+ //int pcw_ver = 0;
+
+ if (si_ver == PCW_SILICON_VERSION_1) {
+ ps7_mio_init_data = ps7_mio_init_data_1_0;
+ ps7_pll_init_data = ps7_pll_init_data_1_0;
+ ps7_clock_init_data = ps7_clock_init_data_1_0;
+ ps7_ddr_init_data = ps7_ddr_init_data_1_0;
+ ps7_peripherals_init_data = ps7_peripherals_init_data_1_0;
+ //pcw_ver = 1;
+
+ } else if (si_ver == PCW_SILICON_VERSION_2) {
+ ps7_mio_init_data = ps7_mio_init_data_2_0;
+ ps7_pll_init_data = ps7_pll_init_data_2_0;
+ ps7_clock_init_data = ps7_clock_init_data_2_0;
+ ps7_ddr_init_data = ps7_ddr_init_data_2_0;
+ ps7_peripherals_init_data = ps7_peripherals_init_data_2_0;
+ //pcw_ver = 2;
+
+ } else {
+ ps7_mio_init_data = ps7_mio_init_data_3_0;
+ ps7_pll_init_data = ps7_pll_init_data_3_0;
+ ps7_clock_init_data = ps7_clock_init_data_3_0;
+ ps7_ddr_init_data = ps7_ddr_init_data_3_0;
+ ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
+ //pcw_ver = 3;
+ }
+
+ // MIO init
+ ret = ps7_config (ps7_mio_init_data);
+ if (ret != PS7_INIT_SUCCESS) return ret;
+
+ // PLL init
+ ret = ps7_config (ps7_pll_init_data);
+ if (ret != PS7_INIT_SUCCESS) return ret;
+
+ // Clock init
+ ret = ps7_config (ps7_clock_init_data);
+ if (ret != PS7_INIT_SUCCESS) return ret;
+
+ // DDR init
+ ret = ps7_config (ps7_ddr_init_data);
+ if (ret != PS7_INIT_SUCCESS) return ret;
+
+
+
+ // Peripherals init
+ ret = ps7_config (ps7_peripherals_init_data);
+ if (ret != PS7_INIT_SUCCESS) return ret;
+ //xil_printf ("\n PCW Silicon Version : %d.0", pcw_ver);
+ return PS7_INIT_SUCCESS;
+}
+
+
+
+
+/* For delay calculation using global timer */
+
+/* start timer */
+ void perf_start_clock(void)
+{
+ *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) | // Timer Enable
+ (1 << 3) | // Auto-increment
+ (0 << 8) // Pre-scale
+ );
+}
+
+/* stop timer and reset timer count regs */
+ void perf_reset_clock(void)
+{
+ perf_disable_clock();
+ *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_L32 = 0;
+ *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_U32 = 0;
+}
+
+/* Compute mask for given delay in miliseconds*/
+int get_number_of_cycles_for_delay(unsigned int delay)
+{
+ // GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x)
+ return (APU_FREQ*delay/(2*1000));
+
+}
+
+/* stop timer */
+ void perf_disable_clock(void)
+{
+ *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = 0;
+}
+
+void perf_reset_and_start_timer()
+{
+ perf_reset_clock();
+ perf_start_clock();
+}
--- /dev/null
+
+/******************************************************************************
+*
+* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
+*
+* SPDX-License-Identifier: GPL-2.0+
+*
+*
+*******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file ps7_init.h
+*
+* This file can be included in FSBL code
+* to get prototype of ps7_init() function
+* and error codes
+*
+*****************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+//typedef unsigned int u32;
+
+
+/** do we need to make this name more unique ? **/
+//extern u32 ps7_init_data[];
+extern unsigned long * ps7_ddr_init_data;
+extern unsigned long * ps7_mio_init_data;
+extern unsigned long * ps7_pll_init_data;
+extern unsigned long * ps7_clock_init_data;
+extern unsigned long * ps7_peripherals_init_data;
+
+
+
+#define OPCODE_EXIT 0U
+#define OPCODE_CLEAR 1U
+#define OPCODE_WRITE 2U
+#define OPCODE_MASKWRITE 3U
+#define OPCODE_MASKPOLL 4U
+#define OPCODE_MASKDELAY 5U
+#define NEW_PS7_ERR_CODE 1
+
+/* Encode number of arguments in last nibble */
+#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 )
+#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr
+#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val
+#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
+#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask
+#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
+
+/* Returns codes of PS7_Init */
+#define PS7_INIT_SUCCESS (0) // 0 is success in good old C
+#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now
+#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out
+#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init
+#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit
+#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init
+
+
+/* Silicon Versions */
+#define PCW_SILICON_VERSION_1 0
+#define PCW_SILICON_VERSION_2 1
+#define PCW_SILICON_VERSION_3 2
+
+/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
+#define PS7_POST_CONFIG
+
+/* Freq of all peripherals */
+
+#define APU_FREQ 666666687
+#define DDR_FREQ 533333374
+#define DCI_FREQ 10158731
+#define QSPI_FREQ 200000000
+#define SMC_FREQ 10000000
+#define ENET0_FREQ 125000000
+#define ENET1_FREQ 10000000
+#define USB0_FREQ 60000000
+#define USB1_FREQ 60000000
+#define SDIO_FREQ 50000000
+#define UART_FREQ 50000000
+#define SPI_FREQ 10000000
+#define I2C_FREQ 111111115
+#define WDT_FREQ 111111115
+#define TTC_FREQ 50000000
+#define CAN_FREQ 10000000
+#define PCAP_FREQ 200000000
+#define TPIU_FREQ 200000000
+#define FPGA0_FREQ 100000000
+#define FPGA1_FREQ 142857132
+#define FPGA2_FREQ 50000000
+#define FPGA3_FREQ 50000000
+
+
+/* For delay calculation using global registers*/
+#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
+#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204
+#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208
+#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218
+
+int ps7_config( unsigned long*);
+int ps7_init();
+int ps7_post_config();
+int ps7_debug();
+char* getPS7MessageInfo(unsigned key);
+
+void perf_start_clock(void);
+void perf_disable_clock(void);
+void perf_reset_clock(void);
+void perf_reset_and_start_timer();
+int get_number_of_cycles_for_delay(unsigned int delay);
+#ifdef __cplusplus
+}
+#endif
--- /dev/null
+/*
+ * Copyright (c) Xilinx, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include "ps7_init_gpl.h"
+
+unsigned long ps7_pll_init_data_3_0[] = {
+ /* START: top */
+ /* .. START: SLCR SETTINGS */
+ /* .. UNLOCK_KEY = 0XDF0D */
+ /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
+ /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ /* .. FINISH: SLCR SETTINGS */
+ /* .. START: PLL SLCR REGISTERS */
+ /* .. .. START: ARM PLL INIT */
+ /* .. .. PLL_RES = 0xc */
+ /* .. .. ==> 0XF8000110[7:4] = 0x0000000CU */
+ /* .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U */
+ /* .. .. PLL_CP = 0x2 */
+ /* .. .. ==> 0XF8000110[11:8] = 0x00000002U */
+ /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */
+ /* .. .. LOCK_CNT = 0x177 */
+ /* .. .. ==> 0XF8000110[21:12] = 0x00000177U */
+ /* .. .. ==> MASK : 0x003FF000U VAL : 0x00177000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x001772C0U),
+ /* .. .. .. START: UPDATE FB_DIV */
+ /* .. .. .. PLL_FDIV = 0x1a */
+ /* .. .. .. ==> 0XF8000100[18:12] = 0x0000001AU */
+ /* .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001A000U */
+ /* .. .. .. */
+ EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x0001A000U),
+ /* .. .. .. FINISH: UPDATE FB_DIV */
+ /* .. .. .. START: BY PASS PLL */
+ /* .. .. .. PLL_BYPASS_FORCE = 1 */
+ /* .. .. .. ==> 0XF8000100[4:4] = 0x00000001U */
+ /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U */
+ /* .. .. .. */
+ EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U),
+ /* .. .. .. FINISH: BY PASS PLL */
+ /* .. .. .. START: ASSERT RESET */
+ /* .. .. .. PLL_RESET = 1 */
+ /* .. .. .. ==> 0XF8000100[0:0] = 0x00000001U */
+ /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. .. .. */
+ EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U),
+ /* .. .. .. FINISH: ASSERT RESET */
+ /* .. .. .. START: DEASSERT RESET */
+ /* .. .. .. PLL_RESET = 0 */
+ /* .. .. .. ==> 0XF8000100[0:0] = 0x00000000U */
+ /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. .. .. */
+ EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U),
+ /* .. .. .. FINISH: DEASSERT RESET */
+ /* .. .. .. START: CHECK PLL STATUS */
+ /* .. .. .. ARM_PLL_LOCK = 1 */
+ /* .. .. .. ==> 0XF800010C[0:0] = 0x00000001U */
+ /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. .. .. */
+ EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+ /* .. .. .. FINISH: CHECK PLL STATUS */
+ /* .. .. .. START: REMOVE PLL BY PASS */
+ /* .. .. .. PLL_BYPASS_FORCE = 0 */
+ /* .. .. .. ==> 0XF8000100[4:4] = 0x00000000U */
+ /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
+ /* .. .. .. */
+ EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U),
+ /* .. .. .. FINISH: REMOVE PLL BY PASS */
+ /* .. .. .. SRCSEL = 0x0 */
+ /* .. .. .. ==> 0XF8000120[5:4] = 0x00000000U */
+ /* .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
+ /* .. .. .. DIVISOR = 0x2 */
+ /* .. .. .. ==> 0XF8000120[13:8] = 0x00000002U */
+ /* .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U */
+ /* .. .. .. CPU_6OR4XCLKACT = 0x1 */
+ /* .. .. .. ==> 0XF8000120[24:24] = 0x00000001U */
+ /* .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U */
+ /* .. .. .. CPU_3OR2XCLKACT = 0x1 */
+ /* .. .. .. ==> 0XF8000120[25:25] = 0x00000001U */
+ /* .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U */
+ /* .. .. .. CPU_2XCLKACT = 0x1 */
+ /* .. .. .. ==> 0XF8000120[26:26] = 0x00000001U */
+ /* .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U */
+ /* .. .. .. CPU_1XCLKACT = 0x1 */
+ /* .. .. .. ==> 0XF8000120[27:27] = 0x00000001U */
+ /* .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U */
+ /* .. .. .. CPU_PERI_CLKACT = 0x1 */
+ /* .. .. .. ==> 0XF8000120[28:28] = 0x00000001U */
+ /* .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U */
+ /* .. .. .. */
+ EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000200U),
+ /* .. .. FINISH: ARM PLL INIT */
+ /* .. .. START: DDR PLL INIT */
+ /* .. .. PLL_RES = 0xc */
+ /* .. .. ==> 0XF8000114[7:4] = 0x0000000CU */
+ /* .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U */
+ /* .. .. PLL_CP = 0x2 */
+ /* .. .. ==> 0XF8000114[11:8] = 0x00000002U */
+ /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */
+ /* .. .. LOCK_CNT = 0x1db */
+ /* .. .. ==> 0XF8000114[21:12] = 0x000001DBU */
+ /* .. .. ==> MASK : 0x003FF000U VAL : 0x001DB000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x001DB2C0U),
+ /* .. .. .. START: UPDATE FB_DIV */
+ /* .. .. .. PLL_FDIV = 0x15 */
+ /* .. .. .. ==> 0XF8000104[18:12] = 0x00000015U */
+ /* .. .. .. ==> MASK : 0x0007F000U VAL : 0x00015000U */
+ /* .. .. .. */
+ EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x00015000U),
+ /* .. .. .. FINISH: UPDATE FB_DIV */
+ /* .. .. .. START: BY PASS PLL */
+ /* .. .. .. PLL_BYPASS_FORCE = 1 */
+ /* .. .. .. ==> 0XF8000104[4:4] = 0x00000001U */
+ /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U */
+ /* .. .. .. */
+ EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000010U),
+ /* .. .. .. FINISH: BY PASS PLL */
+ /* .. .. .. START: ASSERT RESET */
+ /* .. .. .. PLL_RESET = 1 */
+ /* .. .. .. ==> 0XF8000104[0:0] = 0x00000001U */
+ /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. .. .. */
+ EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000001U),
+ /* .. .. .. FINISH: ASSERT RESET */
+ /* .. .. .. START: DEASSERT RESET */
+ /* .. .. .. PLL_RESET = 0 */
+ /* .. .. .. ==> 0XF8000104[0:0] = 0x00000000U */
+ /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. .. .. */
+ EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000000U),
+ /* .. .. .. FINISH: DEASSERT RESET */
+ /* .. .. .. START: CHECK PLL STATUS */
+ /* .. .. .. DDR_PLL_LOCK = 1 */
+ /* .. .. .. ==> 0XF800010C[1:1] = 0x00000001U */
+ /* .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. .. .. */
+ EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+ /* .. .. .. FINISH: CHECK PLL STATUS */
+ /* .. .. .. START: REMOVE PLL BY PASS */
+ /* .. .. .. PLL_BYPASS_FORCE = 0 */
+ /* .. .. .. ==> 0XF8000104[4:4] = 0x00000000U */
+ /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
+ /* .. .. .. */
+ EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U),
+ /* .. .. .. FINISH: REMOVE PLL BY PASS */
+ /* .. .. .. DDR_3XCLKACT = 0x1 */
+ /* .. .. .. ==> 0XF8000124[0:0] = 0x00000001U */
+ /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. .. .. DDR_2XCLKACT = 0x1 */
+ /* .. .. .. ==> 0XF8000124[1:1] = 0x00000001U */
+ /* .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. .. .. DDR_3XCLK_DIVISOR = 0x2 */
+ /* .. .. .. ==> 0XF8000124[25:20] = 0x00000002U */
+ /* .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U */
+ /* .. .. .. DDR_2XCLK_DIVISOR = 0x3 */
+ /* .. .. .. ==> 0XF8000124[31:26] = 0x00000003U */
+ /* .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U */
+ /* .. .. .. */
+ EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U),
+ /* .. .. FINISH: DDR PLL INIT */
+ /* .. .. START: IO PLL INIT */
+ /* .. .. PLL_RES = 0xc */
+ /* .. .. ==> 0XF8000118[7:4] = 0x0000000CU */
+ /* .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U */
+ /* .. .. PLL_CP = 0x2 */
+ /* .. .. ==> 0XF8000118[11:8] = 0x00000002U */
+ /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */
+ /* .. .. LOCK_CNT = 0x1f4 */
+ /* .. .. ==> 0XF8000118[21:12] = 0x000001F4U */
+ /* .. .. ==> MASK : 0x003FF000U VAL : 0x001F4000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x001F42C0U),
+ /* .. .. .. START: UPDATE FB_DIV */
+ /* .. .. .. PLL_FDIV = 0x14 */
+ /* .. .. .. ==> 0XF8000108[18:12] = 0x00000014U */
+ /* .. .. .. ==> MASK : 0x0007F000U VAL : 0x00014000U */
+ /* .. .. .. */
+ EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x00014000U),
+ /* .. .. .. FINISH: UPDATE FB_DIV */
+ /* .. .. .. START: BY PASS PLL */
+ /* .. .. .. PLL_BYPASS_FORCE = 1 */
+ /* .. .. .. ==> 0XF8000108[4:4] = 0x00000001U */
+ /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U */
+ /* .. .. .. */
+ EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U),
+ /* .. .. .. FINISH: BY PASS PLL */
+ /* .. .. .. START: ASSERT RESET */
+ /* .. .. .. PLL_RESET = 1 */
+ /* .. .. .. ==> 0XF8000108[0:0] = 0x00000001U */
+ /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. .. .. */
+ EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U),
+ /* .. .. .. FINISH: ASSERT RESET */
+ /* .. .. .. START: DEASSERT RESET */
+ /* .. .. .. PLL_RESET = 0 */
+ /* .. .. .. ==> 0XF8000108[0:0] = 0x00000000U */
+ /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. .. .. */
+ EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U),
+ /* .. .. .. FINISH: DEASSERT RESET */
+ /* .. .. .. START: CHECK PLL STATUS */
+ /* .. .. .. IO_PLL_LOCK = 1 */
+ /* .. .. .. ==> 0XF800010C[2:2] = 0x00000001U */
+ /* .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U */
+ /* .. .. .. */
+ EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+ /* .. .. .. FINISH: CHECK PLL STATUS */
+ /* .. .. .. START: REMOVE PLL BY PASS */
+ /* .. .. .. PLL_BYPASS_FORCE = 0 */
+ /* .. .. .. ==> 0XF8000108[4:4] = 0x00000000U */
+ /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
+ /* .. .. .. */
+ EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000000U),
+ /* .. .. .. FINISH: REMOVE PLL BY PASS */
+ /* .. .. FINISH: IO PLL INIT */
+ /* .. FINISH: PLL SLCR REGISTERS */
+ /* .. START: LOCK IT BACK */
+ /* .. LOCK_KEY = 0X767B */
+ /* .. ==> 0XF8000004[15:0] = 0x0000767BU */
+ /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+ /* .. FINISH: LOCK IT BACK */
+ /* FINISH: top */
+ /* */
+ EMIT_EXIT(),
+
+ /* */
+};
+
+unsigned long ps7_clock_init_data_3_0[] = {
+ /* START: top */
+ /* .. START: SLCR SETTINGS */
+ /* .. UNLOCK_KEY = 0XDF0D */
+ /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
+ /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ /* .. FINISH: SLCR SETTINGS */
+ /* .. START: CLOCK CONTROL SLCR REGISTERS */
+ /* .. CLKACT = 0x1 */
+ /* .. ==> 0XF8000128[0:0] = 0x00000001U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. DIVISOR0 = 0x34 */
+ /* .. ==> 0XF8000128[13:8] = 0x00000034U */
+ /* .. ==> MASK : 0x00003F00U VAL : 0x00003400U */
+ /* .. DIVISOR1 = 0x2 */
+ /* .. ==> 0XF8000128[25:20] = 0x00000002U */
+ /* .. ==> MASK : 0x03F00000U VAL : 0x00200000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00203401U),
+ /* .. CLKACT = 0x1 */
+ /* .. ==> 0XF8000138[0:0] = 0x00000001U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. SRCSEL = 0x0 */
+ /* .. ==> 0XF8000138[4:4] = 0x00000000U */
+ /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000001U),
+ /* .. CLKACT = 0x1 */
+ /* .. ==> 0XF8000140[0:0] = 0x00000001U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. SRCSEL = 0x0 */
+ /* .. ==> 0XF8000140[6:4] = 0x00000000U */
+ /* .. ==> MASK : 0x00000070U VAL : 0x00000000U */
+ /* .. DIVISOR = 0x8 */
+ /* .. ==> 0XF8000140[13:8] = 0x00000008U */
+ /* .. ==> MASK : 0x00003F00U VAL : 0x00000800U */
+ /* .. DIVISOR1 = 0x1 */
+ /* .. ==> 0XF8000140[25:20] = 0x00000001U */
+ /* .. ==> MASK : 0x03F00000U VAL : 0x00100000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00100801U),
+ /* .. CLKACT = 0x1 */
+ /* .. ==> 0XF800014C[0:0] = 0x00000001U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. SRCSEL = 0x0 */
+ /* .. ==> 0XF800014C[5:4] = 0x00000000U */
+ /* .. ==> MASK : 0x00000030U VAL : 0x00000000U */
+ /* .. DIVISOR = 0x5 */
+ /* .. ==> 0XF800014C[13:8] = 0x00000005U */
+ /* .. ==> MASK : 0x00003F00U VAL : 0x00000500U */
+ /* .. */
+ EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000501U),
+ /* .. CLKACT0 = 0x1 */
+ /* .. ==> 0XF8000150[0:0] = 0x00000001U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. CLKACT1 = 0x0 */
+ /* .. ==> 0XF8000150[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. SRCSEL = 0x0 */
+ /* .. ==> 0XF8000150[5:4] = 0x00000000U */
+ /* .. ==> MASK : 0x00000030U VAL : 0x00000000U */
+ /* .. DIVISOR = 0x14 */
+ /* .. ==> 0XF8000150[13:8] = 0x00000014U */
+ /* .. ==> MASK : 0x00003F00U VAL : 0x00001400U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00001401U),
+ /* .. CLKACT0 = 0x0 */
+ /* .. ==> 0XF8000154[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. CLKACT1 = 0x1 */
+ /* .. ==> 0XF8000154[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. SRCSEL = 0x0 */
+ /* .. ==> 0XF8000154[5:4] = 0x00000000U */
+ /* .. ==> MASK : 0x00000030U VAL : 0x00000000U */
+ /* .. DIVISOR = 0xa */
+ /* .. ==> 0XF8000154[13:8] = 0x0000000AU */
+ /* .. ==> MASK : 0x00003F00U VAL : 0x00000A00U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00000A02U),
+ /* .. .. START: TRACE CLOCK */
+ /* .. .. FINISH: TRACE CLOCK */
+ /* .. .. CLKACT = 0x1 */
+ /* .. .. ==> 0XF8000168[0:0] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. .. SRCSEL = 0x0 */
+ /* .. .. ==> 0XF8000168[5:4] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
+ /* .. .. DIVISOR = 0x5 */
+ /* .. .. ==> 0XF8000168[13:8] = 0x00000005U */
+ /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000501U),
+ /* .. .. SRCSEL = 0x0 */
+ /* .. .. ==> 0XF8000170[5:4] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
+ /* .. .. DIVISOR0 = 0xa */
+ /* .. .. ==> 0XF8000170[13:8] = 0x0000000AU */
+ /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U */
+ /* .. .. DIVISOR1 = 0x1 */
+ /* .. .. ==> 0XF8000170[25:20] = 0x00000001U */
+ /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00100A00U),
+ /* .. .. SRCSEL = 0x0 */
+ /* .. .. ==> 0XF8000180[5:4] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
+ /* .. .. DIVISOR0 = 0x7 */
+ /* .. .. ==> 0XF8000180[13:8] = 0x00000007U */
+ /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000700U */
+ /* .. .. DIVISOR1 = 0x1 */
+ /* .. .. ==> 0XF8000180[25:20] = 0x00000001U */
+ /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00100700U),
+ /* .. .. SRCSEL = 0x0 */
+ /* .. .. ==> 0XF8000190[5:4] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
+ /* .. .. DIVISOR0 = 0x5 */
+ /* .. .. ==> 0XF8000190[13:8] = 0x00000005U */
+ /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U */
+ /* .. .. DIVISOR1 = 0x1 */
+ /* .. .. ==> 0XF8000190[25:20] = 0x00000001U */
+ /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00100500U),
+ /* .. .. SRCSEL = 0x0 */
+ /* .. .. ==> 0XF80001A0[5:4] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
+ /* .. .. DIVISOR0 = 0x14 */
+ /* .. .. ==> 0XF80001A0[13:8] = 0x00000014U */
+ /* .. .. ==> MASK : 0x00003F00U VAL : 0x00001400U */
+ /* .. .. DIVISOR1 = 0x1 */
+ /* .. .. ==> 0XF80001A0[25:20] = 0x00000001U */
+ /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00101400U),
+ /* .. .. CLK_621_TRUE = 0x1 */
+ /* .. .. ==> 0XF80001C4[0:0] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U),
+ /* .. .. DMA_CPU_2XCLKACT = 0x1 */
+ /* .. .. ==> 0XF800012C[0:0] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. .. USB0_CPU_1XCLKACT = 0x1 */
+ /* .. .. ==> 0XF800012C[2:2] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000004U VAL : 0x00000004U */
+ /* .. .. USB1_CPU_1XCLKACT = 0x1 */
+ /* .. .. ==> 0XF800012C[3:3] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000008U VAL : 0x00000008U */
+ /* .. .. GEM0_CPU_1XCLKACT = 0x1 */
+ /* .. .. ==> 0XF800012C[6:6] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000040U VAL : 0x00000040U */
+ /* .. .. GEM1_CPU_1XCLKACT = 0x0 */
+ /* .. .. ==> 0XF800012C[7:7] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000080U VAL : 0x00000000U */
+ /* .. .. SDI0_CPU_1XCLKACT = 0x1 */
+ /* .. .. ==> 0XF800012C[10:10] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000400U VAL : 0x00000400U */
+ /* .. .. SDI1_CPU_1XCLKACT = 0x0 */
+ /* .. .. ==> 0XF800012C[11:11] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */
+ /* .. .. SPI0_CPU_1XCLKACT = 0x0 */
+ /* .. .. ==> 0XF800012C[14:14] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00004000U VAL : 0x00000000U */
+ /* .. .. SPI1_CPU_1XCLKACT = 0x0 */
+ /* .. .. ==> 0XF800012C[15:15] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */
+ /* .. .. CAN0_CPU_1XCLKACT = 0x0 */
+ /* .. .. ==> 0XF800012C[16:16] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
+ /* .. .. CAN1_CPU_1XCLKACT = 0x0 */
+ /* .. .. ==> 0XF800012C[17:17] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
+ /* .. .. I2C0_CPU_1XCLKACT = 0x1 */
+ /* .. .. ==> 0XF800012C[18:18] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00040000U VAL : 0x00040000U */
+ /* .. .. I2C1_CPU_1XCLKACT = 0x1 */
+ /* .. .. ==> 0XF800012C[19:19] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00080000U VAL : 0x00080000U */
+ /* .. .. UART0_CPU_1XCLKACT = 0x0 */
+ /* .. .. ==> 0XF800012C[20:20] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00100000U VAL : 0x00000000U */
+ /* .. .. UART1_CPU_1XCLKACT = 0x1 */
+ /* .. .. ==> 0XF800012C[21:21] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00200000U VAL : 0x00200000U */
+ /* .. .. GPIO_CPU_1XCLKACT = 0x1 */
+ /* .. .. ==> 0XF800012C[22:22] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00400000U VAL : 0x00400000U */
+ /* .. .. LQSPI_CPU_1XCLKACT = 0x1 */
+ /* .. .. ==> 0XF800012C[23:23] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00800000U VAL : 0x00800000U */
+ /* .. .. SMC_CPU_1XCLKACT = 0x1 */
+ /* .. .. ==> 0XF800012C[24:24] = 0x00000001U */
+ /* .. .. ==> MASK : 0x01000000U VAL : 0x01000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01EC044DU),
+ /* .. FINISH: CLOCK CONTROL SLCR REGISTERS */
+ /* .. START: THIS SHOULD BE BLANK */
+ /* .. FINISH: THIS SHOULD BE BLANK */
+ /* .. START: LOCK IT BACK */
+ /* .. LOCK_KEY = 0X767B */
+ /* .. ==> 0XF8000004[15:0] = 0x0000767BU */
+ /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+ /* .. FINISH: LOCK IT BACK */
+ /* FINISH: top */
+ /* */
+ EMIT_EXIT(),
+
+ /* */
+};
+
+unsigned long ps7_ddr_init_data_3_0[] = {
+ /* START: top */
+ /* .. START: DDR INITIALIZATION */
+ /* .. .. START: LOCK DDR */
+ /* .. .. reg_ddrc_soft_rstb = 0 */
+ /* .. .. ==> 0XF8006000[0:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_powerdown_en = 0x0 */
+ /* .. .. ==> 0XF8006000[1:1] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_data_bus_width = 0x0 */
+ /* .. .. ==> 0XF8006000[3:2] = 0x00000000U */
+ /* .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U */
+ /* .. .. reg_ddrc_burst8_refresh = 0x0 */
+ /* .. .. ==> 0XF8006000[6:4] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000070U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_rdwr_idle_gap = 0x1 */
+ /* .. .. ==> 0XF8006000[13:7] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U */
+ /* .. .. reg_ddrc_dis_rd_bypass = 0x0 */
+ /* .. .. ==> 0XF8006000[14:14] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00004000U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_dis_act_bypass = 0x0 */
+ /* .. .. ==> 0XF8006000[15:15] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_dis_auto_refresh = 0x0 */
+ /* .. .. ==> 0XF8006000[16:16] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000080U),
+ /* .. .. FINISH: LOCK DDR */
+ /* .. .. reg_ddrc_t_rfc_nom_x32 = 0x7f */
+ /* .. .. ==> 0XF8006004[11:0] = 0x0000007FU */
+ /* .. .. ==> MASK : 0x00000FFFU VAL : 0x0000007FU */
+ /* .. .. reserved_reg_ddrc_active_ranks = 0x1 */
+ /* .. .. ==> 0XF8006004[13:12] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00003000U VAL : 0x00001000U */
+ /* .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 */
+ /* .. .. ==> 0XF8006004[18:14] = 0x00000000U */
+ /* .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU, 0x0000107FU),
+ /* .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf */
+ /* .. .. ==> 0XF8006008[10:0] = 0x0000000FU */
+ /* .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU */
+ /* .. .. reg_ddrc_hpr_max_starve_x32 = 0xf */
+ /* .. .. ==> 0XF8006008[21:11] = 0x0000000FU */
+ /* .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U */
+ /* .. .. reg_ddrc_hpr_xact_run_length = 0xf */
+ /* .. .. ==> 0XF8006008[25:22] = 0x0000000FU */
+ /* .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU, 0x03C0780FU),
+ /* .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 */
+ /* .. .. ==> 0XF800600C[10:0] = 0x00000001U */
+ /* .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U */
+ /* .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 */
+ /* .. .. ==> 0XF800600C[21:11] = 0x00000002U */
+ /* .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U */
+ /* .. .. reg_ddrc_lpr_xact_run_length = 0x8 */
+ /* .. .. ==> 0XF800600C[25:22] = 0x00000008U */
+ /* .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU, 0x02001001U),
+ /* .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 */
+ /* .. .. ==> 0XF8006010[10:0] = 0x00000001U */
+ /* .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U */
+ /* .. .. reg_ddrc_w_xact_run_length = 0x8 */
+ /* .. .. ==> 0XF8006010[14:11] = 0x00000008U */
+ /* .. .. ==> MASK : 0x00007800U VAL : 0x00004000U */
+ /* .. .. reg_ddrc_w_max_starve_x32 = 0x2 */
+ /* .. .. ==> 0XF8006010[25:15] = 0x00000002U */
+ /* .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU, 0x00014001U),
+ /* .. .. reg_ddrc_t_rc = 0x1a */
+ /* .. .. ==> 0XF8006014[5:0] = 0x0000001AU */
+ /* .. .. ==> MASK : 0x0000003FU VAL : 0x0000001AU */
+ /* .. .. reg_ddrc_t_rfc_min = 0x54 */
+ /* .. .. ==> 0XF8006014[13:6] = 0x00000054U */
+ /* .. .. ==> MASK : 0x00003FC0U VAL : 0x00001500U */
+ /* .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 */
+ /* .. .. ==> 0XF8006014[20:14] = 0x00000010U */
+ /* .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU, 0x0004151AU),
+ /* .. .. reg_ddrc_wr2pre = 0x12 */
+ /* .. .. ==> 0XF8006018[4:0] = 0x00000012U */
+ /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U */
+ /* .. .. reg_ddrc_powerdown_to_x32 = 0x6 */
+ /* .. .. ==> 0XF8006018[9:5] = 0x00000006U */
+ /* .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U */
+ /* .. .. reg_ddrc_t_faw = 0x15 */
+ /* .. .. ==> 0XF8006018[15:10] = 0x00000015U */
+ /* .. .. ==> MASK : 0x0000FC00U VAL : 0x00005400U */
+ /* .. .. reg_ddrc_t_ras_max = 0x23 */
+ /* .. .. ==> 0XF8006018[21:16] = 0x00000023U */
+ /* .. .. ==> MASK : 0x003F0000U VAL : 0x00230000U */
+ /* .. .. reg_ddrc_t_ras_min = 0x13 */
+ /* .. .. ==> 0XF8006018[26:22] = 0x00000013U */
+ /* .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U */
+ /* .. .. reg_ddrc_t_cke = 0x4 */
+ /* .. .. ==> 0XF8006018[31:28] = 0x00000004U */
+ /* .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU, 0x44E354D2U),
+ /* .. .. reg_ddrc_write_latency = 0x5 */
+ /* .. .. ==> 0XF800601C[4:0] = 0x00000005U */
+ /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U */
+ /* .. .. reg_ddrc_rd2wr = 0x7 */
+ /* .. .. ==> 0XF800601C[9:5] = 0x00000007U */
+ /* .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U */
+ /* .. .. reg_ddrc_wr2rd = 0xe */
+ /* .. .. ==> 0XF800601C[14:10] = 0x0000000EU */
+ /* .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U */
+ /* .. .. reg_ddrc_t_xp = 0x4 */
+ /* .. .. ==> 0XF800601C[19:15] = 0x00000004U */
+ /* .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U */
+ /* .. .. reg_ddrc_pad_pd = 0x0 */
+ /* .. .. ==> 0XF800601C[22:20] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00700000U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_rd2pre = 0x4 */
+ /* .. .. ==> 0XF800601C[27:23] = 0x00000004U */
+ /* .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U */
+ /* .. .. reg_ddrc_t_rcd = 0x7 */
+ /* .. .. ==> 0XF800601C[31:28] = 0x00000007U */
+ /* .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU, 0x720238E5U),
+ /* .. .. reg_ddrc_t_ccd = 0x4 */
+ /* .. .. ==> 0XF8006020[4:2] = 0x00000004U */
+ /* .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U */
+ /* .. .. reg_ddrc_t_rrd = 0x6 */
+ /* .. .. ==> 0XF8006020[7:5] = 0x00000006U */
+ /* .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U */
+ /* .. .. reg_ddrc_refresh_margin = 0x2 */
+ /* .. .. ==> 0XF8006020[11:8] = 0x00000002U */
+ /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */
+ /* .. .. reg_ddrc_t_rp = 0x7 */
+ /* .. .. ==> 0XF8006020[15:12] = 0x00000007U */
+ /* .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U */
+ /* .. .. reg_ddrc_refresh_to_x32 = 0x8 */
+ /* .. .. ==> 0XF8006020[20:16] = 0x00000008U */
+ /* .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U */
+ /* .. .. reg_ddrc_mobile = 0x0 */
+ /* .. .. ==> 0XF8006020[22:22] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00400000U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_en_dfi_dram_clk_disable = 0x0 */
+ /* .. .. ==> 0XF8006020[23:23] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00800000U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_read_latency = 0x7 */
+ /* .. .. ==> 0XF8006020[28:24] = 0x00000007U */
+ /* .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U */
+ /* .. .. reg_phy_mode_ddr1_ddr2 = 0x1 */
+ /* .. .. ==> 0XF8006020[29:29] = 0x00000001U */
+ /* .. .. ==> MASK : 0x20000000U VAL : 0x20000000U */
+ /* .. .. reg_ddrc_dis_pad_pd = 0x0 */
+ /* .. .. ==> 0XF8006020[30:30] = 0x00000000U */
+ /* .. .. ==> MASK : 0x40000000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU, 0x270872D0U),
+ /* .. .. reg_ddrc_en_2t_timing_mode = 0x0 */
+ /* .. .. ==> 0XF8006024[0:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_prefer_write = 0x0 */
+ /* .. .. ==> 0XF8006024[1:1] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_mr_wr = 0x0 */
+ /* .. .. ==> 0XF8006024[6:6] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000040U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_mr_addr = 0x0 */
+ /* .. .. ==> 0XF8006024[8:7] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000180U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_mr_data = 0x0 */
+ /* .. .. ==> 0XF8006024[24:9] = 0x00000000U */
+ /* .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U */
+ /* .. .. ddrc_reg_mr_wr_busy = 0x0 */
+ /* .. .. ==> 0XF8006024[25:25] = 0x00000000U */
+ /* .. .. ==> MASK : 0x02000000U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_mr_type = 0x0 */
+ /* .. .. ==> 0XF8006024[26:26] = 0x00000000U */
+ /* .. .. ==> MASK : 0x04000000U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_mr_rdata_valid = 0x0 */
+ /* .. .. ==> 0XF8006024[27:27] = 0x00000000U */
+ /* .. .. ==> MASK : 0x08000000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U, 0x00000000U),
+ /* .. .. reg_ddrc_final_wait_x32 = 0x7 */
+ /* .. .. ==> 0XF8006028[6:0] = 0x00000007U */
+ /* .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U */
+ /* .. .. reg_ddrc_pre_ocd_x32 = 0x0 */
+ /* .. .. ==> 0XF8006028[10:7] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000780U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_t_mrd = 0x4 */
+ /* .. .. ==> 0XF8006028[13:11] = 0x00000004U */
+ /* .. .. ==> MASK : 0x00003800U VAL : 0x00002000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006028, 0x00003FFFU, 0x00002007U),
+ /* .. .. reg_ddrc_emr2 = 0x8 */
+ /* .. .. ==> 0XF800602C[15:0] = 0x00000008U */
+ /* .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U */
+ /* .. .. reg_ddrc_emr3 = 0x0 */
+ /* .. .. ==> 0XF800602C[31:16] = 0x00000000U */
+ /* .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU, 0x00000008U),
+ /* .. .. reg_ddrc_mr = 0x930 */
+ /* .. .. ==> 0XF8006030[15:0] = 0x00000930U */
+ /* .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U */
+ /* .. .. reg_ddrc_emr = 0x4 */
+ /* .. .. ==> 0XF8006030[31:16] = 0x00000004U */
+ /* .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU, 0x00040930U),
+ /* .. .. reg_ddrc_burst_rdwr = 0x4 */
+ /* .. .. ==> 0XF8006034[3:0] = 0x00000004U */
+ /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U */
+ /* .. .. reg_ddrc_pre_cke_x1024 = 0x167 */
+ /* .. .. ==> 0XF8006034[13:4] = 0x00000167U */
+ /* .. .. ==> MASK : 0x00003FF0U VAL : 0x00001670U */
+ /* .. .. reg_ddrc_post_cke_x1024 = 0x1 */
+ /* .. .. ==> 0XF8006034[25:16] = 0x00000001U */
+ /* .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U */
+ /* .. .. reg_ddrc_burstchop = 0x0 */
+ /* .. .. ==> 0XF8006034[28:28] = 0x00000000U */
+ /* .. .. ==> MASK : 0x10000000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x00011674U),
+ /* .. .. reg_ddrc_force_low_pri_n = 0x0 */
+ /* .. .. ==> 0XF8006038[0:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_dis_dq = 0x0 */
+ /* .. .. ==> 0XF8006038[1:1] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006038, 0x00000003U, 0x00000000U),
+ /* .. .. reg_ddrc_addrmap_bank_b0 = 0x7 */
+ /* .. .. ==> 0XF800603C[3:0] = 0x00000007U */
+ /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U */
+ /* .. .. reg_ddrc_addrmap_bank_b1 = 0x7 */
+ /* .. .. ==> 0XF800603C[7:4] = 0x00000007U */
+ /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U */
+ /* .. .. reg_ddrc_addrmap_bank_b2 = 0x7 */
+ /* .. .. ==> 0XF800603C[11:8] = 0x00000007U */
+ /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U */
+ /* .. .. reg_ddrc_addrmap_col_b5 = 0x0 */
+ /* .. .. ==> 0XF800603C[15:12] = 0x00000000U */
+ /* .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_addrmap_col_b6 = 0x0 */
+ /* .. .. ==> 0XF800603C[19:16] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU, 0x00000777U),
+ /* .. .. reg_ddrc_addrmap_col_b2 = 0x0 */
+ /* .. .. ==> 0XF8006040[3:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U */
+ /* .. .. reg_ddrc_addrmap_col_b3 = 0x0 */
+ /* .. .. ==> 0XF8006040[7:4] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_addrmap_col_b4 = 0x0 */
+ /* .. .. ==> 0XF8006040[11:8] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_addrmap_col_b7 = 0x0 */
+ /* .. .. ==> 0XF8006040[15:12] = 0x00000000U */
+ /* .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_addrmap_col_b8 = 0x0 */
+ /* .. .. ==> 0XF8006040[19:16] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_addrmap_col_b9 = 0xf */
+ /* .. .. ==> 0XF8006040[23:20] = 0x0000000FU */
+ /* .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U */
+ /* .. .. reg_ddrc_addrmap_col_b10 = 0xf */
+ /* .. .. ==> 0XF8006040[27:24] = 0x0000000FU */
+ /* .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U */
+ /* .. .. reg_ddrc_addrmap_col_b11 = 0xf */
+ /* .. .. ==> 0XF8006040[31:28] = 0x0000000FU */
+ /* .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU, 0xFFF00000U),
+ /* .. .. reg_ddrc_addrmap_row_b0 = 0x6 */
+ /* .. .. ==> 0XF8006044[3:0] = 0x00000006U */
+ /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U */
+ /* .. .. reg_ddrc_addrmap_row_b1 = 0x6 */
+ /* .. .. ==> 0XF8006044[7:4] = 0x00000006U */
+ /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U */
+ /* .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 */
+ /* .. .. ==> 0XF8006044[11:8] = 0x00000006U */
+ /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U */
+ /* .. .. reg_ddrc_addrmap_row_b12 = 0x6 */
+ /* .. .. ==> 0XF8006044[15:12] = 0x00000006U */
+ /* .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U */
+ /* .. .. reg_ddrc_addrmap_row_b13 = 0x6 */
+ /* .. .. ==> 0XF8006044[19:16] = 0x00000006U */
+ /* .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U */
+ /* .. .. reg_ddrc_addrmap_row_b14 = 0xf */
+ /* .. .. ==> 0XF8006044[23:20] = 0x0000000FU */
+ /* .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U */
+ /* .. .. reg_ddrc_addrmap_row_b15 = 0xf */
+ /* .. .. ==> 0XF8006044[27:24] = 0x0000000FU */
+ /* .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU, 0x0FF66666U),
+ /* .. .. reg_phy_rd_local_odt = 0x0 */
+ /* .. .. ==> 0XF8006048[13:12] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00003000U VAL : 0x00000000U */
+ /* .. .. reg_phy_wr_local_odt = 0x3 */
+ /* .. .. ==> 0XF8006048[15:14] = 0x00000003U */
+ /* .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U */
+ /* .. .. reg_phy_idle_local_odt = 0x3 */
+ /* .. .. ==> 0XF8006048[17:16] = 0x00000003U */
+ /* .. .. ==> MASK : 0x00030000U VAL : 0x00030000U */
+ /* .. .. reserved_reg_ddrc_rank0_wr_odt = 0x1 */
+ /* .. .. ==> 0XF8006048[5:3] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000038U VAL : 0x00000008U */
+ /* .. .. reserved_reg_ddrc_rank0_rd_odt = 0x0 */
+ /* .. .. ==> 0XF8006048[2:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000007U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006048, 0x0003F03FU, 0x0003C008U),
+ /* .. .. reg_phy_rd_cmd_to_data = 0x0 */
+ /* .. .. ==> 0XF8006050[3:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U */
+ /* .. .. reg_phy_wr_cmd_to_data = 0x0 */
+ /* .. .. ==> 0XF8006050[7:4] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */
+ /* .. .. reg_phy_rdc_we_to_re_delay = 0x8 */
+ /* .. .. ==> 0XF8006050[11:8] = 0x00000008U */
+ /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U */
+ /* .. .. reg_phy_rdc_fifo_rst_disable = 0x0 */
+ /* .. .. ==> 0XF8006050[15:15] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */
+ /* .. .. reg_phy_use_fixed_re = 0x1 */
+ /* .. .. ==> 0XF8006050[16:16] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00010000U VAL : 0x00010000U */
+ /* .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 */
+ /* .. .. ==> 0XF8006050[17:17] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
+ /* .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 */
+ /* .. .. ==> 0XF8006050[18:18] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
+ /* .. .. reg_phy_clk_stall_level = 0x0 */
+ /* .. .. ==> 0XF8006050[19:19] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */
+ /* .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 */
+ /* .. .. ==> 0XF8006050[27:24] = 0x00000007U */
+ /* .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U */
+ /* .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 */
+ /* .. .. ==> 0XF8006050[31:28] = 0x00000007U */
+ /* .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU, 0x77010800U),
+ /* .. .. reg_ddrc_dis_dll_calib = 0x0 */
+ /* .. .. ==> 0XF8006058[16:16] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006058, 0x00010000U, 0x00000000U),
+ /* .. .. reg_ddrc_rd_odt_delay = 0x3 */
+ /* .. .. ==> 0XF800605C[3:0] = 0x00000003U */
+ /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U */
+ /* .. .. reg_ddrc_wr_odt_delay = 0x0 */
+ /* .. .. ==> 0XF800605C[7:4] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_rd_odt_hold = 0x0 */
+ /* .. .. ==> 0XF800605C[11:8] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_wr_odt_hold = 0x5 */
+ /* .. .. ==> 0XF800605C[15:12] = 0x00000005U */
+ /* .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU, 0x00005003U),
+ /* .. .. reg_ddrc_pageclose = 0x0 */
+ /* .. .. ==> 0XF8006060[0:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_lpr_num_entries = 0x1f */
+ /* .. .. ==> 0XF8006060[6:1] = 0x0000001FU */
+ /* .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU */
+ /* .. .. reg_ddrc_auto_pre_en = 0x0 */
+ /* .. .. ==> 0XF8006060[7:7] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000080U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_refresh_update_level = 0x0 */
+ /* .. .. ==> 0XF8006060[8:8] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_dis_wc = 0x0 */
+ /* .. .. ==> 0XF8006060[9:9] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000200U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_dis_collision_page_opt = 0x0 */
+ /* .. .. ==> 0XF8006060[10:10] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_selfref_en = 0x0 */
+ /* .. .. ==> 0XF8006060[12:12] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006060, 0x000017FFU, 0x0000003EU),
+ /* .. .. reg_ddrc_go2critical_hysteresis = 0x0 */
+ /* .. .. ==> 0XF8006064[12:5] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U */
+ /* .. .. reg_arb_go2critical_en = 0x1 */
+ /* .. .. ==> 0XF8006064[17:17] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00020000U VAL : 0x00020000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006064, 0x00021FE0U, 0x00020000U),
+ /* .. .. reg_ddrc_wrlvl_ww = 0x41 */
+ /* .. .. ==> 0XF8006068[7:0] = 0x00000041U */
+ /* .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U */
+ /* .. .. reg_ddrc_rdlvl_rr = 0x41 */
+ /* .. .. ==> 0XF8006068[15:8] = 0x00000041U */
+ /* .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U */
+ /* .. .. reg_ddrc_dfi_t_wlmrd = 0x28 */
+ /* .. .. ==> 0XF8006068[25:16] = 0x00000028U */
+ /* .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU, 0x00284141U),
+ /* .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 */
+ /* .. .. ==> 0XF800606C[7:0] = 0x00000010U */
+ /* .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U */
+ /* .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 */
+ /* .. .. ==> 0XF800606C[15:8] = 0x00000016U */
+ /* .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU, 0x00001610U),
+ /* .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1 */
+ /* .. .. ==> 0XF8006078[3:0] = 0x00000001U */
+ /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U */
+ /* .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1 */
+ /* .. .. ==> 0XF8006078[7:4] = 0x00000001U */
+ /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U */
+ /* .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1 */
+ /* .. .. ==> 0XF8006078[11:8] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U */
+ /* .. .. reg_ddrc_t_cksre = 0x6 */
+ /* .. .. ==> 0XF8006078[15:12] = 0x00000006U */
+ /* .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U */
+ /* .. .. reg_ddrc_t_cksrx = 0x6 */
+ /* .. .. ==> 0XF8006078[19:16] = 0x00000006U */
+ /* .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U */
+ /* .. .. reg_ddrc_t_ckesr = 0x4 */
+ /* .. .. ==> 0XF8006078[25:20] = 0x00000004U */
+ /* .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU, 0x00466111U),
+ /* .. .. reg_ddrc_t_ckpde = 0x2 */
+ /* .. .. ==> 0XF800607C[3:0] = 0x00000002U */
+ /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U */
+ /* .. .. reg_ddrc_t_ckpdx = 0x2 */
+ /* .. .. ==> 0XF800607C[7:4] = 0x00000002U */
+ /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U */
+ /* .. .. reg_ddrc_t_ckdpde = 0x2 */
+ /* .. .. ==> 0XF800607C[11:8] = 0x00000002U */
+ /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */
+ /* .. .. reg_ddrc_t_ckdpdx = 0x2 */
+ /* .. .. ==> 0XF800607C[15:12] = 0x00000002U */
+ /* .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U */
+ /* .. .. reg_ddrc_t_ckcsx = 0x3 */
+ /* .. .. ==> 0XF800607C[19:16] = 0x00000003U */
+ /* .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU, 0x00032222U),
+ /* .. .. reg_ddrc_dis_auto_zq = 0x0 */
+ /* .. .. ==> 0XF80060A4[0:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_ddr3 = 0x1 */
+ /* .. .. ==> 0XF80060A4[1:1] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. .. reg_ddrc_t_mod = 0x200 */
+ /* .. .. ==> 0XF80060A4[11:2] = 0x00000200U */
+ /* .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U */
+ /* .. .. reg_ddrc_t_zq_long_nop = 0x200 */
+ /* .. .. ==> 0XF80060A4[21:12] = 0x00000200U */
+ /* .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U */
+ /* .. .. reg_ddrc_t_zq_short_nop = 0x40 */
+ /* .. .. ==> 0XF80060A4[31:22] = 0x00000040U */
+ /* .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U),
+ /* .. .. t_zq_short_interval_x1024 = 0xc845 */
+ /* .. .. ==> 0XF80060A8[19:0] = 0x0000C845U */
+ /* .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000C845U */
+ /* .. .. dram_rstn_x1024 = 0x67 */
+ /* .. .. ==> 0XF80060A8[27:20] = 0x00000067U */
+ /* .. .. ==> MASK : 0x0FF00000U VAL : 0x06700000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0670C845U),
+ /* .. .. deeppowerdown_en = 0x0 */
+ /* .. .. ==> 0XF80060AC[0:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. .. deeppowerdown_to_x1024 = 0xff */
+ /* .. .. ==> 0XF80060AC[8:1] = 0x000000FFU */
+ /* .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU),
+ /* .. .. dfi_wrlvl_max_x1024 = 0xfff */
+ /* .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU */
+ /* .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU */
+ /* .. .. dfi_rdlvl_max_x1024 = 0xfff */
+ /* .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU */
+ /* .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U */
+ /* .. .. ddrc_reg_twrlvl_max_error = 0x0 */
+ /* .. .. ==> 0XF80060B0[24:24] = 0x00000000U */
+ /* .. .. ==> MASK : 0x01000000U VAL : 0x00000000U */
+ /* .. .. ddrc_reg_trdlvl_max_error = 0x0 */
+ /* .. .. ==> 0XF80060B0[25:25] = 0x00000000U */
+ /* .. .. ==> MASK : 0x02000000U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_dfi_wr_level_en = 0x1 */
+ /* .. .. ==> 0XF80060B0[26:26] = 0x00000001U */
+ /* .. .. ==> MASK : 0x04000000U VAL : 0x04000000U */
+ /* .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 */
+ /* .. .. ==> 0XF80060B0[27:27] = 0x00000001U */
+ /* .. .. ==> MASK : 0x08000000U VAL : 0x08000000U */
+ /* .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 */
+ /* .. .. ==> 0XF80060B0[28:28] = 0x00000001U */
+ /* .. .. ==> MASK : 0x10000000U VAL : 0x10000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+ /* .. .. reg_ddrc_skip_ocd = 0x1 */
+ /* .. .. ==> 0XF80060B4[9:9] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000200U VAL : 0x00000200U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF80060B4, 0x00000200U, 0x00000200U),
+ /* .. .. reg_ddrc_dfi_t_rddata_en = 0x6 */
+ /* .. .. ==> 0XF80060B8[4:0] = 0x00000006U */
+ /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U */
+ /* .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 */
+ /* .. .. ==> 0XF80060B8[14:5] = 0x00000003U */
+ /* .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U */
+ /* .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 */
+ /* .. .. ==> 0XF80060B8[24:15] = 0x00000040U */
+ /* .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU, 0x00200066U),
+ /* .. .. START: RESET ECC ERROR */
+ /* .. .. Clear_Uncorrectable_DRAM_ECC_error = 1 */
+ /* .. .. ==> 0XF80060C4[0:0] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. .. Clear_Correctable_DRAM_ECC_error = 1 */
+ /* .. .. ==> 0XF80060C4[1:1] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000003U),
+ /* .. .. FINISH: RESET ECC ERROR */
+ /* .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 */
+ /* .. .. ==> 0XF80060C4[0:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. .. Clear_Correctable_DRAM_ECC_error = 0x0 */
+ /* .. .. ==> 0XF80060C4[1:1] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000000U),
+ /* .. .. CORR_ECC_LOG_VALID = 0x0 */
+ /* .. .. ==> 0XF80060C8[0:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. .. ECC_CORRECTED_BIT_NUM = 0x0 */
+ /* .. .. ==> 0XF80060C8[7:1] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF80060C8, 0x000000FFU, 0x00000000U),
+ /* .. .. UNCORR_ECC_LOG_VALID = 0x0 */
+ /* .. .. ==> 0XF80060DC[0:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF80060DC, 0x00000001U, 0x00000000U),
+ /* .. .. STAT_NUM_CORR_ERR = 0x0 */
+ /* .. .. ==> 0XF80060F0[15:8] = 0x00000000U */
+ /* .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U */
+ /* .. .. STAT_NUM_UNCORR_ERR = 0x0 */
+ /* .. .. ==> 0XF80060F0[7:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU, 0x00000000U),
+ /* .. .. reg_ddrc_ecc_mode = 0x0 */
+ /* .. .. ==> 0XF80060F4[2:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000007U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_dis_scrub = 0x1 */
+ /* .. .. ==> 0XF80060F4[3:3] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000008U VAL : 0x00000008U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF80060F4, 0x0000000FU, 0x00000008U),
+ /* .. .. reg_phy_dif_on = 0x0 */
+ /* .. .. ==> 0XF8006114[3:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U */
+ /* .. .. reg_phy_dif_off = 0x0 */
+ /* .. .. ==> 0XF8006114[7:4] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006114, 0x000000FFU, 0x00000000U),
+ /* .. .. reg_phy_data_slice_in_use = 0x1 */
+ /* .. .. ==> 0XF8006118[0:0] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
+ /* .. .. ==> 0XF8006118[1:1] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
+ /* .. .. ==> 0XF8006118[2:2] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
+ /* .. .. ==> 0XF8006118[3:3] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */
+ /* .. .. reg_phy_bist_shift_dq = 0x0 */
+ /* .. .. ==> 0XF8006118[14:6] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */
+ /* .. .. reg_phy_bist_err_clr = 0x0 */
+ /* .. .. ==> 0XF8006118[23:15] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */
+ /* .. .. reg_phy_dq_offset = 0x40 */
+ /* .. .. ==> 0XF8006118[30:24] = 0x00000040U */
+ /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU, 0x40000001U),
+ /* .. .. reg_phy_data_slice_in_use = 0x1 */
+ /* .. .. ==> 0XF800611C[0:0] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
+ /* .. .. ==> 0XF800611C[1:1] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
+ /* .. .. ==> 0XF800611C[2:2] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
+ /* .. .. ==> 0XF800611C[3:3] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */
+ /* .. .. reg_phy_bist_shift_dq = 0x0 */
+ /* .. .. ==> 0XF800611C[14:6] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */
+ /* .. .. reg_phy_bist_err_clr = 0x0 */
+ /* .. .. ==> 0XF800611C[23:15] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */
+ /* .. .. reg_phy_dq_offset = 0x40 */
+ /* .. .. ==> 0XF800611C[30:24] = 0x00000040U */
+ /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU, 0x40000001U),
+ /* .. .. reg_phy_data_slice_in_use = 0x1 */
+ /* .. .. ==> 0XF8006120[0:0] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
+ /* .. .. ==> 0XF8006120[1:1] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
+ /* .. .. ==> 0XF8006120[2:2] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
+ /* .. .. ==> 0XF8006120[3:3] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */
+ /* .. .. reg_phy_bist_shift_dq = 0x0 */
+ /* .. .. ==> 0XF8006120[14:6] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */
+ /* .. .. reg_phy_bist_err_clr = 0x0 */
+ /* .. .. ==> 0XF8006120[23:15] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */
+ /* .. .. reg_phy_dq_offset = 0x40 */
+ /* .. .. ==> 0XF8006120[30:24] = 0x00000040U */
+ /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU, 0x40000001U),
+ /* .. .. reg_phy_data_slice_in_use = 0x1 */
+ /* .. .. ==> 0XF8006124[0:0] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
+ /* .. .. ==> 0XF8006124[1:1] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
+ /* .. .. ==> 0XF8006124[2:2] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
+ /* .. .. ==> 0XF8006124[3:3] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */
+ /* .. .. reg_phy_bist_shift_dq = 0x0 */
+ /* .. .. ==> 0XF8006124[14:6] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */
+ /* .. .. reg_phy_bist_err_clr = 0x0 */
+ /* .. .. ==> 0XF8006124[23:15] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */
+ /* .. .. reg_phy_dq_offset = 0x40 */
+ /* .. .. ==> 0XF8006124[30:24] = 0x00000040U */
+ /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU, 0x40000001U),
+ /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
+ /* .. .. ==> 0XF800612C[9:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */
+ /* .. .. reg_phy_gatelvl_init_ratio = 0x8f */
+ /* .. .. ==> 0XF800612C[19:10] = 0x0000008FU */
+ /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00023C00U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU, 0x00023C00U),
+ /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
+ /* .. .. ==> 0XF8006130[9:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */
+ /* .. .. reg_phy_gatelvl_init_ratio = 0x8a */
+ /* .. .. ==> 0XF8006130[19:10] = 0x0000008AU */
+ /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00022800U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU, 0x00022800U),
+ /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
+ /* .. .. ==> 0XF8006134[9:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */
+ /* .. .. reg_phy_gatelvl_init_ratio = 0x8b */
+ /* .. .. ==> 0XF8006134[19:10] = 0x0000008BU */
+ /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00022C00U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU, 0x00022C00U),
+ /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
+ /* .. .. ==> 0XF8006138[9:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */
+ /* .. .. reg_phy_gatelvl_init_ratio = 0x92 */
+ /* .. .. ==> 0XF8006138[19:10] = 0x00000092U */
+ /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00024800U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU, 0x00024800U),
+ /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
+ /* .. .. ==> 0XF8006140[9:0] = 0x00000035U */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */
+ /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
+ /* .. .. ==> 0XF8006140[10:10] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
+ /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
+ /* .. .. ==> 0XF8006140[19:11] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU, 0x00000035U),
+ /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
+ /* .. .. ==> 0XF8006144[9:0] = 0x00000035U */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */
+ /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
+ /* .. .. ==> 0XF8006144[10:10] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
+ /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
+ /* .. .. ==> 0XF8006144[19:11] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU, 0x00000035U),
+ /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
+ /* .. .. ==> 0XF8006148[9:0] = 0x00000035U */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */
+ /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
+ /* .. .. ==> 0XF8006148[10:10] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
+ /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
+ /* .. .. ==> 0XF8006148[19:11] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU, 0x00000035U),
+ /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
+ /* .. .. ==> 0XF800614C[9:0] = 0x00000035U */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */
+ /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
+ /* .. .. ==> 0XF800614C[10:10] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
+ /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
+ /* .. .. ==> 0XF800614C[19:11] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU, 0x00000035U),
+ /* .. .. reg_phy_wr_dqs_slave_ratio = 0x77 */
+ /* .. .. ==> 0XF8006154[9:0] = 0x00000077U */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000077U */
+ /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
+ /* .. .. ==> 0XF8006154[10:10] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
+ /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
+ /* .. .. ==> 0XF8006154[19:11] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU, 0x00000077U),
+ /* .. .. reg_phy_wr_dqs_slave_ratio = 0x7c */
+ /* .. .. ==> 0XF8006158[9:0] = 0x0000007CU */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU */
+ /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
+ /* .. .. ==> 0XF8006158[10:10] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
+ /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
+ /* .. .. ==> 0XF8006158[19:11] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU, 0x0000007CU),
+ /* .. .. reg_phy_wr_dqs_slave_ratio = 0x7c */
+ /* .. .. ==> 0XF800615C[9:0] = 0x0000007CU */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU */
+ /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
+ /* .. .. ==> 0XF800615C[10:10] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
+ /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
+ /* .. .. ==> 0XF800615C[19:11] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU, 0x0000007CU),
+ /* .. .. reg_phy_wr_dqs_slave_ratio = 0x75 */
+ /* .. .. ==> 0XF8006160[9:0] = 0x00000075U */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000075U */
+ /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
+ /* .. .. ==> 0XF8006160[10:10] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
+ /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
+ /* .. .. ==> 0XF8006160[19:11] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU, 0x00000075U),
+ /* .. .. reg_phy_fifo_we_slave_ratio = 0xe4 */
+ /* .. .. ==> 0XF8006168[10:0] = 0x000000E4U */
+ /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000E4U */
+ /* .. .. reg_phy_fifo_we_in_force = 0x0 */
+ /* .. .. ==> 0XF8006168[11:11] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */
+ /* .. .. reg_phy_fifo_we_in_delay = 0x0 */
+ /* .. .. ==> 0XF8006168[20:12] = 0x00000000U */
+ /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU, 0x000000E4U),
+ /* .. .. reg_phy_fifo_we_slave_ratio = 0xdf */
+ /* .. .. ==> 0XF800616C[10:0] = 0x000000DFU */
+ /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000DFU */
+ /* .. .. reg_phy_fifo_we_in_force = 0x0 */
+ /* .. .. ==> 0XF800616C[11:11] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */
+ /* .. .. reg_phy_fifo_we_in_delay = 0x0 */
+ /* .. .. ==> 0XF800616C[20:12] = 0x00000000U */
+ /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU, 0x000000DFU),
+ /* .. .. reg_phy_fifo_we_slave_ratio = 0xe0 */
+ /* .. .. ==> 0XF8006170[10:0] = 0x000000E0U */
+ /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000E0U */
+ /* .. .. reg_phy_fifo_we_in_force = 0x0 */
+ /* .. .. ==> 0XF8006170[11:11] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */
+ /* .. .. reg_phy_fifo_we_in_delay = 0x0 */
+ /* .. .. ==> 0XF8006170[20:12] = 0x00000000U */
+ /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU, 0x000000E0U),
+ /* .. .. reg_phy_fifo_we_slave_ratio = 0xe7 */
+ /* .. .. ==> 0XF8006174[10:0] = 0x000000E7U */
+ /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000E7U */
+ /* .. .. reg_phy_fifo_we_in_force = 0x0 */
+ /* .. .. ==> 0XF8006174[11:11] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */
+ /* .. .. reg_phy_fifo_we_in_delay = 0x0 */
+ /* .. .. ==> 0XF8006174[20:12] = 0x00000000U */
+ /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU, 0x000000E7U),
+ /* .. .. reg_phy_wr_data_slave_ratio = 0xb7 */
+ /* .. .. ==> 0XF800617C[9:0] = 0x000000B7U */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000B7U */
+ /* .. .. reg_phy_wr_data_slave_force = 0x0 */
+ /* .. .. ==> 0XF800617C[10:10] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
+ /* .. .. reg_phy_wr_data_slave_delay = 0x0 */
+ /* .. .. ==> 0XF800617C[19:11] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU, 0x000000B7U),
+ /* .. .. reg_phy_wr_data_slave_ratio = 0xbc */
+ /* .. .. ==> 0XF8006180[9:0] = 0x000000BCU */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU */
+ /* .. .. reg_phy_wr_data_slave_force = 0x0 */
+ /* .. .. ==> 0XF8006180[10:10] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
+ /* .. .. reg_phy_wr_data_slave_delay = 0x0 */
+ /* .. .. ==> 0XF8006180[19:11] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU, 0x000000BCU),
+ /* .. .. reg_phy_wr_data_slave_ratio = 0xbc */
+ /* .. .. ==> 0XF8006184[9:0] = 0x000000BCU */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU */
+ /* .. .. reg_phy_wr_data_slave_force = 0x0 */
+ /* .. .. ==> 0XF8006184[10:10] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
+ /* .. .. reg_phy_wr_data_slave_delay = 0x0 */
+ /* .. .. ==> 0XF8006184[19:11] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU, 0x000000BCU),
+ /* .. .. reg_phy_wr_data_slave_ratio = 0xb5 */
+ /* .. .. ==> 0XF8006188[9:0] = 0x000000B5U */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000B5U */
+ /* .. .. reg_phy_wr_data_slave_force = 0x0 */
+ /* .. .. ==> 0XF8006188[10:10] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
+ /* .. .. reg_phy_wr_data_slave_delay = 0x0 */
+ /* .. .. ==> 0XF8006188[19:11] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU, 0x000000B5U),
+ /* .. .. reg_phy_bl2 = 0x0 */
+ /* .. .. ==> 0XF8006190[1:1] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. .. reg_phy_at_spd_atpg = 0x0 */
+ /* .. .. ==> 0XF8006190[2:2] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. .. reg_phy_bist_enable = 0x0 */
+ /* .. .. ==> 0XF8006190[3:3] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */
+ /* .. .. reg_phy_bist_force_err = 0x0 */
+ /* .. .. ==> 0XF8006190[4:4] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
+ /* .. .. reg_phy_bist_mode = 0x0 */
+ /* .. .. ==> 0XF8006190[6:5] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000060U VAL : 0x00000000U */
+ /* .. .. reg_phy_invert_clkout = 0x1 */
+ /* .. .. ==> 0XF8006190[7:7] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000080U VAL : 0x00000080U */
+ /* .. .. reg_phy_sel_logic = 0x0 */
+ /* .. .. ==> 0XF8006190[9:9] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000200U VAL : 0x00000000U */
+ /* .. .. reg_phy_ctrl_slave_ratio = 0x100 */
+ /* .. .. ==> 0XF8006190[19:10] = 0x00000100U */
+ /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U */
+ /* .. .. reg_phy_ctrl_slave_force = 0x0 */
+ /* .. .. ==> 0XF8006190[20:20] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00100000U VAL : 0x00000000U */
+ /* .. .. reg_phy_ctrl_slave_delay = 0x0 */
+ /* .. .. ==> 0XF8006190[27:21] = 0x00000000U */
+ /* .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U */
+ /* .. .. reg_phy_lpddr = 0x0 */
+ /* .. .. ==> 0XF8006190[29:29] = 0x00000000U */
+ /* .. .. ==> MASK : 0x20000000U VAL : 0x00000000U */
+ /* .. .. reg_phy_cmd_latency = 0x0 */
+ /* .. .. ==> 0XF8006190[30:30] = 0x00000000U */
+ /* .. .. ==> MASK : 0x40000000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU, 0x00040080U),
+ /* .. .. reg_phy_wr_rl_delay = 0x2 */
+ /* .. .. ==> 0XF8006194[4:0] = 0x00000002U */
+ /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U */
+ /* .. .. reg_phy_rd_rl_delay = 0x4 */
+ /* .. .. ==> 0XF8006194[9:5] = 0x00000004U */
+ /* .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U */
+ /* .. .. reg_phy_dll_lock_diff = 0xf */
+ /* .. .. ==> 0XF8006194[13:10] = 0x0000000FU */
+ /* .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U */
+ /* .. .. reg_phy_use_wr_level = 0x1 */
+ /* .. .. ==> 0XF8006194[14:14] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00004000U VAL : 0x00004000U */
+ /* .. .. reg_phy_use_rd_dqs_gate_level = 0x1 */
+ /* .. .. ==> 0XF8006194[15:15] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00008000U VAL : 0x00008000U */
+ /* .. .. reg_phy_use_rd_data_eye_level = 0x1 */
+ /* .. .. ==> 0XF8006194[16:16] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00010000U VAL : 0x00010000U */
+ /* .. .. reg_phy_dis_calib_rst = 0x0 */
+ /* .. .. ==> 0XF8006194[17:17] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
+ /* .. .. reg_phy_ctrl_slave_delay = 0x0 */
+ /* .. .. ==> 0XF8006194[19:18] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU, 0x0001FC82U),
+ /* .. .. reg_arb_page_addr_mask = 0x0 */
+ /* .. .. ==> 0XF8006204[31:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU, 0x00000000U),
+ /* .. .. reg_arb_pri_wr_portn = 0x3ff */
+ /* .. .. ==> 0XF8006208[9:0] = 0x000003FFU */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
+ /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
+ /* .. .. ==> 0XF8006208[16:16] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
+ /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
+ /* .. .. ==> 0XF8006208[17:17] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
+ /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
+ /* .. .. ==> 0XF8006208[18:18] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006208, 0x000703FFU, 0x000003FFU),
+ /* .. .. reg_arb_pri_wr_portn = 0x3ff */
+ /* .. .. ==> 0XF800620C[9:0] = 0x000003FFU */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
+ /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
+ /* .. .. ==> 0XF800620C[16:16] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
+ /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
+ /* .. .. ==> 0XF800620C[17:17] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
+ /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
+ /* .. .. ==> 0XF800620C[18:18] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF800620C, 0x000703FFU, 0x000003FFU),
+ /* .. .. reg_arb_pri_wr_portn = 0x3ff */
+ /* .. .. ==> 0XF8006210[9:0] = 0x000003FFU */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
+ /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
+ /* .. .. ==> 0XF8006210[16:16] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
+ /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
+ /* .. .. ==> 0XF8006210[17:17] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
+ /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
+ /* .. .. ==> 0XF8006210[18:18] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006210, 0x000703FFU, 0x000003FFU),
+ /* .. .. reg_arb_pri_wr_portn = 0x3ff */
+ /* .. .. ==> 0XF8006214[9:0] = 0x000003FFU */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
+ /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
+ /* .. .. ==> 0XF8006214[16:16] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
+ /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
+ /* .. .. ==> 0XF8006214[17:17] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
+ /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
+ /* .. .. ==> 0XF8006214[18:18] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006214, 0x000703FFU, 0x000003FFU),
+ /* .. .. reg_arb_pri_rd_portn = 0x3ff */
+ /* .. .. ==> 0XF8006218[9:0] = 0x000003FFU */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
+ /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
+ /* .. .. ==> 0XF8006218[16:16] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
+ /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
+ /* .. .. ==> 0XF8006218[17:17] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
+ /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
+ /* .. .. ==> 0XF8006218[18:18] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
+ /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
+ /* .. .. ==> 0XF8006218[19:19] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006218, 0x000F03FFU, 0x000003FFU),
+ /* .. .. reg_arb_pri_rd_portn = 0x3ff */
+ /* .. .. ==> 0XF800621C[9:0] = 0x000003FFU */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
+ /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
+ /* .. .. ==> 0XF800621C[16:16] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
+ /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
+ /* .. .. ==> 0XF800621C[17:17] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
+ /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
+ /* .. .. ==> 0XF800621C[18:18] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
+ /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
+ /* .. .. ==> 0XF800621C[19:19] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF800621C, 0x000F03FFU, 0x000003FFU),
+ /* .. .. reg_arb_pri_rd_portn = 0x3ff */
+ /* .. .. ==> 0XF8006220[9:0] = 0x000003FFU */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
+ /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
+ /* .. .. ==> 0XF8006220[16:16] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
+ /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
+ /* .. .. ==> 0XF8006220[17:17] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
+ /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
+ /* .. .. ==> 0XF8006220[18:18] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
+ /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
+ /* .. .. ==> 0XF8006220[19:19] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006220, 0x000F03FFU, 0x000003FFU),
+ /* .. .. reg_arb_pri_rd_portn = 0x3ff */
+ /* .. .. ==> 0XF8006224[9:0] = 0x000003FFU */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
+ /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
+ /* .. .. ==> 0XF8006224[16:16] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
+ /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
+ /* .. .. ==> 0XF8006224[17:17] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
+ /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
+ /* .. .. ==> 0XF8006224[18:18] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
+ /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
+ /* .. .. ==> 0XF8006224[19:19] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006224, 0x000F03FFU, 0x000003FFU),
+ /* .. .. reg_ddrc_lpddr2 = 0x0 */
+ /* .. .. ==> 0XF80062A8[0:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_derate_enable = 0x0 */
+ /* .. .. ==> 0XF80062A8[2:2] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_mr4_margin = 0x0 */
+ /* .. .. ==> 0XF80062A8[11:4] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U, 0x00000000U),
+ /* .. .. reg_ddrc_mr4_read_interval = 0x0 */
+ /* .. .. ==> 0XF80062AC[31:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU, 0x00000000U),
+ /* .. .. reg_ddrc_min_stable_clock_x1 = 0x5 */
+ /* .. .. ==> 0XF80062B0[3:0] = 0x00000005U */
+ /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U */
+ /* .. .. reg_ddrc_idle_after_reset_x32 = 0x12 */
+ /* .. .. ==> 0XF80062B0[11:4] = 0x00000012U */
+ /* .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U */
+ /* .. .. reg_ddrc_t_mrw = 0x5 */
+ /* .. .. ==> 0XF80062B0[21:12] = 0x00000005U */
+ /* .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU, 0x00005125U),
+ /* .. .. reg_ddrc_max_auto_init_x1024 = 0xa6 */
+ /* .. .. ==> 0XF80062B4[7:0] = 0x000000A6U */
+ /* .. .. ==> MASK : 0x000000FFU VAL : 0x000000A6U */
+ /* .. .. reg_ddrc_dev_zqinit_x32 = 0x12 */
+ /* .. .. ==> 0XF80062B4[17:8] = 0x00000012U */
+ /* .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU, 0x000012A6U),
+ /* .. .. START: POLL ON DCI STATUS */
+ /* .. .. DONE = 1 */
+ /* .. .. ==> 0XF8000B74[13:13] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00002000U VAL : 0x00002000U */
+ /* .. .. */
+ EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+ /* .. .. FINISH: POLL ON DCI STATUS */
+ /* .. .. START: UNLOCK DDR */
+ /* .. .. reg_ddrc_soft_rstb = 0x1 */
+ /* .. .. ==> 0XF8006000[0:0] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. .. reg_ddrc_powerdown_en = 0x0 */
+ /* .. .. ==> 0XF8006000[1:1] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_data_bus_width = 0x0 */
+ /* .. .. ==> 0XF8006000[3:2] = 0x00000000U */
+ /* .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U */
+ /* .. .. reg_ddrc_burst8_refresh = 0x0 */
+ /* .. .. ==> 0XF8006000[6:4] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000070U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_rdwr_idle_gap = 1 */
+ /* .. .. ==> 0XF8006000[13:7] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U */
+ /* .. .. reg_ddrc_dis_rd_bypass = 0x0 */
+ /* .. .. ==> 0XF8006000[14:14] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00004000U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_dis_act_bypass = 0x0 */
+ /* .. .. ==> 0XF8006000[15:15] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_dis_auto_refresh = 0x0 */
+ /* .. .. ==> 0XF8006000[16:16] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000081U),
+ /* .. .. FINISH: UNLOCK DDR */
+ /* .. .. START: CHECK DDR STATUS */
+ /* .. .. ddrc_reg_operating_mode = 1 */
+ /* .. .. ==> 0XF8006054[2:0] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000007U VAL : 0x00000001U */
+ /* .. .. */
+ EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+ /* .. .. FINISH: CHECK DDR STATUS */
+ /* .. FINISH: DDR INITIALIZATION */
+ /* FINISH: top */
+ /* */
+ EMIT_EXIT(),
+
+ /* */
+};
+
+unsigned long ps7_mio_init_data_3_0[] = {
+ /* START: top */
+ /* .. START: SLCR SETTINGS */
+ /* .. UNLOCK_KEY = 0XDF0D */
+ /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
+ /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ /* .. FINISH: SLCR SETTINGS */
+ /* .. START: OCM REMAPPING */
+ /* .. VREF_EN = 0x1 */
+ /* .. ==> 0XF8000B00[0:0] = 0x00000001U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. VREF_SEL = 0x0 */
+ /* .. ==> 0XF8000B00[6:4] = 0x00000000U */
+ /* .. ==> MASK : 0x00000070U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000B00, 0x00000071U, 0x00000001U),
+ /* .. FINISH: OCM REMAPPING */
+ /* .. START: DDRIOB SETTINGS */
+ /* .. reserved_INP_POWER = 0x0 */
+ /* .. ==> 0XF8000B40[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. INP_TYPE = 0x0 */
+ /* .. ==> 0XF8000B40[2:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */
+ /* .. DCI_UPDATE_B = 0x0 */
+ /* .. ==> 0XF8000B40[3:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
+ /* .. TERM_EN = 0x0 */
+ /* .. ==> 0XF8000B40[4:4] = 0x00000000U */
+ /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */
+ /* .. DCI_TYPE = 0x0 */
+ /* .. ==> 0XF8000B40[6:5] = 0x00000000U */
+ /* .. ==> MASK : 0x00000060U VAL : 0x00000000U */
+ /* .. IBUF_DISABLE_MODE = 0x0 */
+ /* .. ==> 0XF8000B40[7:7] = 0x00000000U */
+ /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
+ /* .. TERM_DISABLE_MODE = 0x0 */
+ /* .. ==> 0XF8000B40[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. OUTPUT_EN = 0x3 */
+ /* .. ==> 0XF8000B40[10:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
+ /* .. PULLUP_EN = 0x0 */
+ /* .. ==> 0XF8000B40[11:11] = 0x00000000U */
+ /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU, 0x00000600U),
+ /* .. reserved_INP_POWER = 0x0 */
+ /* .. ==> 0XF8000B44[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. INP_TYPE = 0x0 */
+ /* .. ==> 0XF8000B44[2:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */
+ /* .. DCI_UPDATE_B = 0x0 */
+ /* .. ==> 0XF8000B44[3:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
+ /* .. TERM_EN = 0x0 */
+ /* .. ==> 0XF8000B44[4:4] = 0x00000000U */
+ /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */
+ /* .. DCI_TYPE = 0x0 */
+ /* .. ==> 0XF8000B44[6:5] = 0x00000000U */
+ /* .. ==> MASK : 0x00000060U VAL : 0x00000000U */
+ /* .. IBUF_DISABLE_MODE = 0x0 */
+ /* .. ==> 0XF8000B44[7:7] = 0x00000000U */
+ /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
+ /* .. TERM_DISABLE_MODE = 0x0 */
+ /* .. ==> 0XF8000B44[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. OUTPUT_EN = 0x3 */
+ /* .. ==> 0XF8000B44[10:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
+ /* .. PULLUP_EN = 0x0 */
+ /* .. ==> 0XF8000B44[11:11] = 0x00000000U */
+ /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU, 0x00000600U),
+ /* .. reserved_INP_POWER = 0x0 */
+ /* .. ==> 0XF8000B48[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. INP_TYPE = 0x1 */
+ /* .. ==> 0XF8000B48[2:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000006U VAL : 0x00000002U */
+ /* .. DCI_UPDATE_B = 0x0 */
+ /* .. ==> 0XF8000B48[3:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
+ /* .. TERM_EN = 0x1 */
+ /* .. ==> 0XF8000B48[4:4] = 0x00000001U */
+ /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */
+ /* .. DCI_TYPE = 0x3 */
+ /* .. ==> 0XF8000B48[6:5] = 0x00000003U */
+ /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */
+ /* .. IBUF_DISABLE_MODE = 0 */
+ /* .. ==> 0XF8000B48[7:7] = 0x00000000U */
+ /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
+ /* .. TERM_DISABLE_MODE = 0 */
+ /* .. ==> 0XF8000B48[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. OUTPUT_EN = 0x3 */
+ /* .. ==> 0XF8000B48[10:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
+ /* .. PULLUP_EN = 0x0 */
+ /* .. ==> 0XF8000B48[11:11] = 0x00000000U */
+ /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU, 0x00000672U),
+ /* .. reserved_INP_POWER = 0x0 */
+ /* .. ==> 0XF8000B4C[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. INP_TYPE = 0x1 */
+ /* .. ==> 0XF8000B4C[2:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000006U VAL : 0x00000002U */
+ /* .. DCI_UPDATE_B = 0x0 */
+ /* .. ==> 0XF8000B4C[3:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
+ /* .. TERM_EN = 0x1 */
+ /* .. ==> 0XF8000B4C[4:4] = 0x00000001U */
+ /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */
+ /* .. DCI_TYPE = 0x3 */
+ /* .. ==> 0XF8000B4C[6:5] = 0x00000003U */
+ /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */
+ /* .. IBUF_DISABLE_MODE = 0 */
+ /* .. ==> 0XF8000B4C[7:7] = 0x00000000U */
+ /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
+ /* .. TERM_DISABLE_MODE = 0 */
+ /* .. ==> 0XF8000B4C[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. OUTPUT_EN = 0x3 */
+ /* .. ==> 0XF8000B4C[10:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
+ /* .. PULLUP_EN = 0x0 */
+ /* .. ==> 0XF8000B4C[11:11] = 0x00000000U */
+ /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU, 0x00000672U),
+ /* .. reserved_INP_POWER = 0x0 */
+ /* .. ==> 0XF8000B50[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. INP_TYPE = 0x2 */
+ /* .. ==> 0XF8000B50[2:1] = 0x00000002U */
+ /* .. ==> MASK : 0x00000006U VAL : 0x00000004U */
+ /* .. DCI_UPDATE_B = 0x0 */
+ /* .. ==> 0XF8000B50[3:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
+ /* .. TERM_EN = 0x1 */
+ /* .. ==> 0XF8000B50[4:4] = 0x00000001U */
+ /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */
+ /* .. DCI_TYPE = 0x3 */
+ /* .. ==> 0XF8000B50[6:5] = 0x00000003U */
+ /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */
+ /* .. IBUF_DISABLE_MODE = 0 */
+ /* .. ==> 0XF8000B50[7:7] = 0x00000000U */
+ /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
+ /* .. TERM_DISABLE_MODE = 0 */
+ /* .. ==> 0XF8000B50[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. OUTPUT_EN = 0x3 */
+ /* .. ==> 0XF8000B50[10:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
+ /* .. PULLUP_EN = 0x0 */
+ /* .. ==> 0XF8000B50[11:11] = 0x00000000U */
+ /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU, 0x00000674U),
+ /* .. reserved_INP_POWER = 0x0 */
+ /* .. ==> 0XF8000B54[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. INP_TYPE = 0x2 */
+ /* .. ==> 0XF8000B54[2:1] = 0x00000002U */
+ /* .. ==> MASK : 0x00000006U VAL : 0x00000004U */
+ /* .. DCI_UPDATE_B = 0x0 */
+ /* .. ==> 0XF8000B54[3:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
+ /* .. TERM_EN = 0x1 */
+ /* .. ==> 0XF8000B54[4:4] = 0x00000001U */
+ /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */
+ /* .. DCI_TYPE = 0x3 */
+ /* .. ==> 0XF8000B54[6:5] = 0x00000003U */
+ /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */
+ /* .. IBUF_DISABLE_MODE = 0 */
+ /* .. ==> 0XF8000B54[7:7] = 0x00000000U */
+ /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
+ /* .. TERM_DISABLE_MODE = 0 */
+ /* .. ==> 0XF8000B54[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. OUTPUT_EN = 0x3 */
+ /* .. ==> 0XF8000B54[10:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
+ /* .. PULLUP_EN = 0x0 */
+ /* .. ==> 0XF8000B54[11:11] = 0x00000000U */
+ /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU, 0x00000674U),
+ /* .. reserved_INP_POWER = 0x0 */
+ /* .. ==> 0XF8000B58[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. INP_TYPE = 0x0 */
+ /* .. ==> 0XF8000B58[2:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */
+ /* .. DCI_UPDATE_B = 0x0 */
+ /* .. ==> 0XF8000B58[3:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
+ /* .. TERM_EN = 0x0 */
+ /* .. ==> 0XF8000B58[4:4] = 0x00000000U */
+ /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */
+ /* .. DCI_TYPE = 0x0 */
+ /* .. ==> 0XF8000B58[6:5] = 0x00000000U */
+ /* .. ==> MASK : 0x00000060U VAL : 0x00000000U */
+ /* .. IBUF_DISABLE_MODE = 0x0 */
+ /* .. ==> 0XF8000B58[7:7] = 0x00000000U */
+ /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
+ /* .. TERM_DISABLE_MODE = 0x0 */
+ /* .. ==> 0XF8000B58[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. OUTPUT_EN = 0x3 */
+ /* .. ==> 0XF8000B58[10:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
+ /* .. PULLUP_EN = 0x0 */
+ /* .. ==> 0XF8000B58[11:11] = 0x00000000U */
+ /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU, 0x00000600U),
+ /* .. reserved_DRIVE_P = 0x1c */
+ /* .. ==> 0XF8000B5C[6:0] = 0x0000001CU */
+ /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */
+ /* .. reserved_DRIVE_N = 0xc */
+ /* .. ==> 0XF8000B5C[13:7] = 0x0000000CU */
+ /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */
+ /* .. reserved_SLEW_P = 0x3 */
+ /* .. ==> 0XF8000B5C[18:14] = 0x00000003U */
+ /* .. ==> MASK : 0x0007C000U VAL : 0x0000C000U */
+ /* .. reserved_SLEW_N = 0x3 */
+ /* .. ==> 0XF8000B5C[23:19] = 0x00000003U */
+ /* .. ==> MASK : 0x00F80000U VAL : 0x00180000U */
+ /* .. reserved_GTL = 0x0 */
+ /* .. ==> 0XF8000B5C[26:24] = 0x00000000U */
+ /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */
+ /* .. reserved_RTERM = 0x0 */
+ /* .. ==> 0XF8000B5C[31:27] = 0x00000000U */
+ /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU, 0x0018C61CU),
+ /* .. reserved_DRIVE_P = 0x1c */
+ /* .. ==> 0XF8000B60[6:0] = 0x0000001CU */
+ /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */
+ /* .. reserved_DRIVE_N = 0xc */
+ /* .. ==> 0XF8000B60[13:7] = 0x0000000CU */
+ /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */
+ /* .. reserved_SLEW_P = 0x6 */
+ /* .. ==> 0XF8000B60[18:14] = 0x00000006U */
+ /* .. ==> MASK : 0x0007C000U VAL : 0x00018000U */
+ /* .. reserved_SLEW_N = 0x1f */
+ /* .. ==> 0XF8000B60[23:19] = 0x0000001FU */
+ /* .. ==> MASK : 0x00F80000U VAL : 0x00F80000U */
+ /* .. reserved_GTL = 0x0 */
+ /* .. ==> 0XF8000B60[26:24] = 0x00000000U */
+ /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */
+ /* .. reserved_RTERM = 0x0 */
+ /* .. ==> 0XF8000B60[31:27] = 0x00000000U */
+ /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU, 0x00F9861CU),
+ /* .. reserved_DRIVE_P = 0x1c */
+ /* .. ==> 0XF8000B64[6:0] = 0x0000001CU */
+ /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */
+ /* .. reserved_DRIVE_N = 0xc */
+ /* .. ==> 0XF8000B64[13:7] = 0x0000000CU */
+ /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */
+ /* .. reserved_SLEW_P = 0x6 */
+ /* .. ==> 0XF8000B64[18:14] = 0x00000006U */
+ /* .. ==> MASK : 0x0007C000U VAL : 0x00018000U */
+ /* .. reserved_SLEW_N = 0x1f */
+ /* .. ==> 0XF8000B64[23:19] = 0x0000001FU */
+ /* .. ==> MASK : 0x00F80000U VAL : 0x00F80000U */
+ /* .. reserved_GTL = 0x0 */
+ /* .. ==> 0XF8000B64[26:24] = 0x00000000U */
+ /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */
+ /* .. reserved_RTERM = 0x0 */
+ /* .. ==> 0XF8000B64[31:27] = 0x00000000U */
+ /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU, 0x00F9861CU),
+ /* .. reserved_DRIVE_P = 0x1c */
+ /* .. ==> 0XF8000B68[6:0] = 0x0000001CU */
+ /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */
+ /* .. reserved_DRIVE_N = 0xc */
+ /* .. ==> 0XF8000B68[13:7] = 0x0000000CU */
+ /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */
+ /* .. reserved_SLEW_P = 0x6 */
+ /* .. ==> 0XF8000B68[18:14] = 0x00000006U */
+ /* .. ==> MASK : 0x0007C000U VAL : 0x00018000U */
+ /* .. reserved_SLEW_N = 0x1f */
+ /* .. ==> 0XF8000B68[23:19] = 0x0000001FU */
+ /* .. ==> MASK : 0x00F80000U VAL : 0x00F80000U */
+ /* .. reserved_GTL = 0x0 */
+ /* .. ==> 0XF8000B68[26:24] = 0x00000000U */
+ /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */
+ /* .. reserved_RTERM = 0x0 */
+ /* .. ==> 0XF8000B68[31:27] = 0x00000000U */
+ /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU, 0x00F9861CU),
+ /* .. VREF_INT_EN = 0x0 */
+ /* .. ==> 0XF8000B6C[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. VREF_SEL = 0x0 */
+ /* .. ==> 0XF8000B6C[4:1] = 0x00000000U */
+ /* .. ==> MASK : 0x0000001EU VAL : 0x00000000U */
+ /* .. VREF_EXT_EN = 0x3 */
+ /* .. ==> 0XF8000B6C[6:5] = 0x00000003U */
+ /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */
+ /* .. reserved_VREF_PULLUP_EN = 0x0 */
+ /* .. ==> 0XF8000B6C[8:7] = 0x00000000U */
+ /* .. ==> MASK : 0x00000180U VAL : 0x00000000U */
+ /* .. REFIO_EN = 0x1 */
+ /* .. ==> 0XF8000B6C[9:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000200U VAL : 0x00000200U */
+ /* .. reserved_REFIO_TEST = 0x0 */
+ /* .. ==> 0XF8000B6C[11:10] = 0x00000000U */
+ /* .. ==> MASK : 0x00000C00U VAL : 0x00000000U */
+ /* .. reserved_REFIO_PULLUP_EN = 0x0 */
+ /* .. ==> 0XF8000B6C[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. reserved_DRST_B_PULLUP_EN = 0x0 */
+ /* .. ==> 0XF8000B6C[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. reserved_CKE_PULLUP_EN = 0x0 */
+ /* .. ==> 0XF8000B6C[14:14] = 0x00000000U */
+ /* .. ==> MASK : 0x00004000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU, 0x00000260U),
+ /* .. .. START: ASSERT RESET */
+ /* .. .. RESET = 1 */
+ /* .. .. ==> 0XF8000B70[0:0] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8000B70, 0x00000001U, 0x00000001U),
+ /* .. .. FINISH: ASSERT RESET */
+ /* .. .. START: DEASSERT RESET */
+ /* .. .. RESET = 0 */
+ /* .. .. ==> 0XF8000B70[0:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. .. reserved_VRN_OUT = 0x1 */
+ /* .. .. ==> 0XF8000B70[5:5] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000020U VAL : 0x00000020U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000020U),
+ /* .. .. FINISH: DEASSERT RESET */
+ /* .. .. RESET = 0x1 */
+ /* .. .. ==> 0XF8000B70[0:0] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. .. ENABLE = 0x1 */
+ /* .. .. ==> 0XF8000B70[1:1] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. .. reserved_VRP_TRI = 0x0 */
+ /* .. .. ==> 0XF8000B70[2:2] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. .. reserved_VRN_TRI = 0x0 */
+ /* .. .. ==> 0XF8000B70[3:3] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */
+ /* .. .. reserved_VRP_OUT = 0x0 */
+ /* .. .. ==> 0XF8000B70[4:4] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
+ /* .. .. reserved_VRN_OUT = 0x1 */
+ /* .. .. ==> 0XF8000B70[5:5] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000020U VAL : 0x00000020U */
+ /* .. .. NREF_OPT1 = 0x0 */
+ /* .. .. ==> 0XF8000B70[7:6] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U */
+ /* .. .. NREF_OPT2 = 0x0 */
+ /* .. .. ==> 0XF8000B70[10:8] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000700U VAL : 0x00000000U */
+ /* .. .. NREF_OPT4 = 0x1 */
+ /* .. .. ==> 0XF8000B70[13:11] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00003800U VAL : 0x00000800U */
+ /* .. .. PREF_OPT1 = 0x0 */
+ /* .. .. ==> 0XF8000B70[15:14] = 0x00000000U */
+ /* .. .. ==> MASK : 0x0000C000U VAL : 0x00000000U */
+ /* .. .. PREF_OPT2 = 0x0 */
+ /* .. .. ==> 0XF8000B70[19:17] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U */
+ /* .. .. UPDATE_CONTROL = 0x0 */
+ /* .. .. ==> 0XF8000B70[20:20] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00100000U VAL : 0x00000000U */
+ /* .. .. reserved_INIT_COMPLETE = 0x0 */
+ /* .. .. ==> 0XF8000B70[21:21] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00200000U VAL : 0x00000000U */
+ /* .. .. reserved_TST_CLK = 0x0 */
+ /* .. .. ==> 0XF8000B70[22:22] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00400000U VAL : 0x00000000U */
+ /* .. .. reserved_TST_HLN = 0x0 */
+ /* .. .. ==> 0XF8000B70[23:23] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00800000U VAL : 0x00000000U */
+ /* .. .. reserved_TST_HLP = 0x0 */
+ /* .. .. ==> 0XF8000B70[24:24] = 0x00000000U */
+ /* .. .. ==> MASK : 0x01000000U VAL : 0x00000000U */
+ /* .. .. reserved_TST_RST = 0x0 */
+ /* .. .. ==> 0XF8000B70[25:25] = 0x00000000U */
+ /* .. .. ==> MASK : 0x02000000U VAL : 0x00000000U */
+ /* .. .. reserved_INT_DCI_EN = 0x0 */
+ /* .. .. ==> 0XF8000B70[26:26] = 0x00000000U */
+ /* .. .. ==> MASK : 0x04000000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU, 0x00000823U),
+ /* .. FINISH: DDRIOB SETTINGS */
+ /* .. START: MIO PROGRAMMING */
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000700[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF8000700[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000700[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000700[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000700[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF8000700[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF8000700[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 1 */
+ /* .. ==> 0XF8000700[12:12] = 0x00000001U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000700[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000700, 0x00003FFFU, 0x00001600U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000704[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF8000704[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000704[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000704[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000704[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000704[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF8000704[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000704[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000704[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000704, 0x00003FFFU, 0x00000702U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000708[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF8000708[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000708[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000708[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000708[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000708[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF8000708[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000708[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000708[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000708, 0x00003FFFU, 0x00000702U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF800070C[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF800070C[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF800070C[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF800070C[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF800070C[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF800070C[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF800070C[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF800070C[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF800070C[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF800070C, 0x00003FFFU, 0x00000702U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000710[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF8000710[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000710[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000710[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000710[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000710[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF8000710[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000710[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000710[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000710, 0x00003FFFU, 0x00000702U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000714[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF8000714[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000714[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000714[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000714[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000714[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF8000714[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000714[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000714[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000714, 0x00003FFFU, 0x00000702U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000718[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF8000718[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000718[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000718[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000718[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000718[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF8000718[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000718[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000718[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000702U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF800071C[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF800071C[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF800071C[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF800071C[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF800071C[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF800071C[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF800071C[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF800071C[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF800071C[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF800071C, 0x00003FFFU, 0x00000600U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000720[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF8000720[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000720[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000720[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000720[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000720[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF8000720[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000720[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000720[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000720, 0x00003FFFU, 0x00000702U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000724[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF8000724[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000724[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000724[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000724[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF8000724[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF8000724[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 1 */
+ /* .. ==> 0XF8000724[12:12] = 0x00000001U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000724[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000724, 0x00003FFFU, 0x00001600U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000728[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF8000728[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000728[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000728[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000728[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF8000728[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF8000728[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 1 */
+ /* .. ==> 0XF8000728[12:12] = 0x00000001U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000728[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000728, 0x00003FFFU, 0x00001600U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF800072C[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF800072C[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF800072C[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF800072C[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF800072C[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF800072C[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF800072C[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 1 */
+ /* .. ==> 0XF800072C[12:12] = 0x00000001U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF800072C[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF800072C, 0x00003FFFU, 0x00001600U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000730[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF8000730[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000730[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000730[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000730[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF8000730[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF8000730[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 1 */
+ /* .. ==> 0XF8000730[12:12] = 0x00000001U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000730[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000730, 0x00003FFFU, 0x00001600U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000734[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF8000734[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000734[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000734[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000734[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF8000734[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF8000734[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 1 */
+ /* .. ==> 0XF8000734[12:12] = 0x00000001U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000734[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000734, 0x00003FFFU, 0x00001600U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000738[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF8000738[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000738[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000738[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000738[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF8000738[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF8000738[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 1 */
+ /* .. ==> 0XF8000738[12:12] = 0x00000001U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000738[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000738, 0x00003FFFU, 0x00001600U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF800073C[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF800073C[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF800073C[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF800073C[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF800073C[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF800073C[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF800073C[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 1 */
+ /* .. ==> 0XF800073C[12:12] = 0x00000001U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF800073C[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF800073C, 0x00003FFFU, 0x00001600U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000740[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF8000740[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000740[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000740[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000740[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000740[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 4 */
+ /* .. ==> 0XF8000740[11:9] = 0x00000004U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000740[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 1 */
+ /* .. ==> 0XF8000740[13:13] = 0x00000001U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000740, 0x00003FFFU, 0x00002902U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000744[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF8000744[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000744[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000744[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000744[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000744[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 4 */
+ /* .. ==> 0XF8000744[11:9] = 0x00000004U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000744[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 1 */
+ /* .. ==> 0XF8000744[13:13] = 0x00000001U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000744, 0x00003FFFU, 0x00002902U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000748[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF8000748[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000748[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000748[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000748[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000748[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 4 */
+ /* .. ==> 0XF8000748[11:9] = 0x00000004U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000748[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 1 */
+ /* .. ==> 0XF8000748[13:13] = 0x00000001U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000748, 0x00003FFFU, 0x00002902U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF800074C[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF800074C[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF800074C[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF800074C[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF800074C[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF800074C[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 4 */
+ /* .. ==> 0XF800074C[11:9] = 0x00000004U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF800074C[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 1 */
+ /* .. ==> 0XF800074C[13:13] = 0x00000001U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF800074C, 0x00003FFFU, 0x00002902U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000750[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF8000750[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000750[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000750[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000750[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000750[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 4 */
+ /* .. ==> 0XF8000750[11:9] = 0x00000004U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000750[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 1 */
+ /* .. ==> 0XF8000750[13:13] = 0x00000001U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000750, 0x00003FFFU, 0x00002902U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000754[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF8000754[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000754[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000754[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000754[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000754[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 4 */
+ /* .. ==> 0XF8000754[11:9] = 0x00000004U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000754[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 1 */
+ /* .. ==> 0XF8000754[13:13] = 0x00000001U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000754, 0x00003FFFU, 0x00002902U),
+ /* .. TRI_ENABLE = 1 */
+ /* .. ==> 0XF8000758[0:0] = 0x00000001U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF8000758[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000758[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000758[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000758[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000758[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 4 */
+ /* .. ==> 0XF8000758[11:9] = 0x00000004U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000758[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000758[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000758, 0x00003FFFU, 0x00000903U),
+ /* .. TRI_ENABLE = 1 */
+ /* .. ==> 0XF800075C[0:0] = 0x00000001U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF800075C[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF800075C[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF800075C[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF800075C[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF800075C[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 4 */
+ /* .. ==> 0XF800075C[11:9] = 0x00000004U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF800075C[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF800075C[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF800075C, 0x00003FFFU, 0x00000903U),
+ /* .. TRI_ENABLE = 1 */
+ /* .. ==> 0XF8000760[0:0] = 0x00000001U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF8000760[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000760[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000760[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000760[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000760[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 4 */
+ /* .. ==> 0XF8000760[11:9] = 0x00000004U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000760[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000760[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000760, 0x00003FFFU, 0x00000903U),
+ /* .. TRI_ENABLE = 1 */
+ /* .. ==> 0XF8000764[0:0] = 0x00000001U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF8000764[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000764[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000764[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000764[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000764[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 4 */
+ /* .. ==> 0XF8000764[11:9] = 0x00000004U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000764[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000764[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000764, 0x00003FFFU, 0x00000903U),
+ /* .. TRI_ENABLE = 1 */
+ /* .. ==> 0XF8000768[0:0] = 0x00000001U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF8000768[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000768[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000768[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000768[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000768[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 4 */
+ /* .. ==> 0XF8000768[11:9] = 0x00000004U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000768[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000768[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000768, 0x00003FFFU, 0x00000903U),
+ /* .. TRI_ENABLE = 1 */
+ /* .. ==> 0XF800076C[0:0] = 0x00000001U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF800076C[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF800076C[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF800076C[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF800076C[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF800076C[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 4 */
+ /* .. ==> 0XF800076C[11:9] = 0x00000004U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF800076C[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF800076C[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF800076C, 0x00003FFFU, 0x00000903U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000770[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF8000770[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 1 */
+ /* .. ==> 0XF8000770[2:2] = 0x00000001U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000770[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000770[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000770[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF8000770[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000770[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000770[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000770, 0x00003FFFU, 0x00000304U),
+ /* .. TRI_ENABLE = 1 */
+ /* .. ==> 0XF8000774[0:0] = 0x00000001U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF8000774[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 1 */
+ /* .. ==> 0XF8000774[2:2] = 0x00000001U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000774[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000774[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000774[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF8000774[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000774[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000774[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000774, 0x00003FFFU, 0x00000305U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000778[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF8000778[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 1 */
+ /* .. ==> 0XF8000778[2:2] = 0x00000001U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000778[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000778[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000778[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF8000778[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000778[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000778[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000778, 0x00003FFFU, 0x00000304U),
+ /* .. TRI_ENABLE = 1 */
+ /* .. ==> 0XF800077C[0:0] = 0x00000001U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF800077C[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 1 */
+ /* .. ==> 0XF800077C[2:2] = 0x00000001U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF800077C[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF800077C[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF800077C[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF800077C[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF800077C[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF800077C[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF800077C, 0x00003FFFU, 0x00000305U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000780[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF8000780[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 1 */
+ /* .. ==> 0XF8000780[2:2] = 0x00000001U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000780[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000780[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000780[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF8000780[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000780[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000780[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000780, 0x00003FFFU, 0x00000304U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000784[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF8000784[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 1 */
+ /* .. ==> 0XF8000784[2:2] = 0x00000001U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000784[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000784[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000784[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF8000784[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000784[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000784[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000784, 0x00003FFFU, 0x00000304U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000788[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF8000788[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 1 */
+ /* .. ==> 0XF8000788[2:2] = 0x00000001U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000788[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000788[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000788[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF8000788[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000788[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000788[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000788, 0x00003FFFU, 0x00000304U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF800078C[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF800078C[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 1 */
+ /* .. ==> 0XF800078C[2:2] = 0x00000001U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF800078C[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF800078C[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF800078C[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF800078C[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF800078C[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF800078C[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF800078C, 0x00003FFFU, 0x00000304U),
+ /* .. TRI_ENABLE = 1 */
+ /* .. ==> 0XF8000790[0:0] = 0x00000001U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF8000790[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 1 */
+ /* .. ==> 0XF8000790[2:2] = 0x00000001U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000790[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000790[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000790[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF8000790[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000790[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000790[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000790, 0x00003FFFU, 0x00000305U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000794[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF8000794[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 1 */
+ /* .. ==> 0XF8000794[2:2] = 0x00000001U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000794[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000794[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000794[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF8000794[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000794[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000794[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000794, 0x00003FFFU, 0x00000304U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000798[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF8000798[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 1 */
+ /* .. ==> 0XF8000798[2:2] = 0x00000001U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000798[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000798[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000798[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF8000798[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000798[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000798[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000798, 0x00003FFFU, 0x00000304U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF800079C[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF800079C[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 1 */
+ /* .. ==> 0XF800079C[2:2] = 0x00000001U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF800079C[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF800079C[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF800079C[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF800079C[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF800079C[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF800079C[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF800079C, 0x00003FFFU, 0x00000304U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF80007A0[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF80007A0[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF80007A0[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF80007A0[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 4 */
+ /* .. ==> 0XF80007A0[7:5] = 0x00000004U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF80007A0[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF80007A0[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF80007A0[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF80007A0[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU, 0x00000380U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF80007A4[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF80007A4[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF80007A4[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF80007A4[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 4 */
+ /* .. ==> 0XF80007A4[7:5] = 0x00000004U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF80007A4[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF80007A4[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF80007A4[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF80007A4[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU, 0x00000380U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF80007A8[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF80007A8[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF80007A8[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF80007A8[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 4 */
+ /* .. ==> 0XF80007A8[7:5] = 0x00000004U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF80007A8[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF80007A8[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF80007A8[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF80007A8[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU, 0x00000380U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF80007AC[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF80007AC[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF80007AC[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF80007AC[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 4 */
+ /* .. ==> 0XF80007AC[7:5] = 0x00000004U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF80007AC[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF80007AC[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF80007AC[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF80007AC[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU, 0x00000380U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF80007B0[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF80007B0[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF80007B0[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF80007B0[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 4 */
+ /* .. ==> 0XF80007B0[7:5] = 0x00000004U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF80007B0[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF80007B0[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF80007B0[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF80007B0[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU, 0x00000380U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF80007B4[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF80007B4[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF80007B4[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF80007B4[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 4 */
+ /* .. ==> 0XF80007B4[7:5] = 0x00000004U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF80007B4[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF80007B4[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF80007B4[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF80007B4[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00000380U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF80007B8[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF80007B8[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF80007B8[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF80007B8[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF80007B8[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF80007B8[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF80007B8[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 1 */
+ /* .. ==> 0XF80007B8[12:12] = 0x00000001U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF80007B8[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU, 0x00001200U),
+ /* .. TRI_ENABLE = 1 */
+ /* .. ==> 0XF80007BC[0:0] = 0x00000001U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF80007BC[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF80007BC[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF80007BC[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF80007BC[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF80007BC, 0x00003F01U, 0x00000201U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF80007C0[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF80007C0[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF80007C0[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF80007C0[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 7 */
+ /* .. ==> 0XF80007C0[7:5] = 0x00000007U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x000000E0U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF80007C0[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF80007C0[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF80007C0[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF80007C0[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU, 0x000002E0U),
+ /* .. TRI_ENABLE = 1 */
+ /* .. ==> 0XF80007C4[0:0] = 0x00000001U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF80007C4[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF80007C4[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF80007C4[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 7 */
+ /* .. ==> 0XF80007C4[7:5] = 0x00000007U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x000000E0U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF80007C4[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF80007C4[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF80007C4[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF80007C4[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x000002E1U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF80007C8[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF80007C8[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF80007C8[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF80007C8[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF80007C8[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF80007C8[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF80007C8[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF80007C8[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF80007C8[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU, 0x00000200U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF80007CC[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF80007CC[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF80007CC[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF80007CC[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF80007CC[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF80007CC[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF80007CC[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF80007CC[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF80007CC[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU, 0x00000200U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF80007D0[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF80007D0[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF80007D0[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF80007D0[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 4 */
+ /* .. ==> 0XF80007D0[7:5] = 0x00000004U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF80007D0[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF80007D0[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF80007D0[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF80007D0[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU, 0x00000280U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF80007D4[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF80007D4[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF80007D4[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF80007D4[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 4 */
+ /* .. ==> 0XF80007D4[7:5] = 0x00000004U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF80007D4[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF80007D4[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF80007D4[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF80007D4[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU, 0x00000280U),
+ /* .. SDIO0_WP_SEL = 55 */
+ /* .. ==> 0XF8000830[5:0] = 0x00000037U */
+ /* .. ==> MASK : 0x0000003FU VAL : 0x00000037U */
+ /* .. SDIO0_CD_SEL = 47 */
+ /* .. ==> 0XF8000830[21:16] = 0x0000002FU */
+ /* .. ==> MASK : 0x003F0000U VAL : 0x002F0000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000830, 0x003F003FU, 0x002F0037U),
+ /* .. FINISH: MIO PROGRAMMING */
+ /* .. START: LOCK IT BACK */
+ /* .. LOCK_KEY = 0X767B */
+ /* .. ==> 0XF8000004[15:0] = 0x0000767BU */
+ /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+ /* .. FINISH: LOCK IT BACK */
+ /* FINISH: top */
+ /* */
+ EMIT_EXIT(),
+
+ /* */
+};
+
+unsigned long ps7_peripherals_init_data_3_0[] = {
+ /* START: top */
+ /* .. START: SLCR SETTINGS */
+ /* .. UNLOCK_KEY = 0XDF0D */
+ /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
+ /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ /* .. FINISH: SLCR SETTINGS */
+ /* .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS */
+ /* .. IBUF_DISABLE_MODE = 0x1 */
+ /* .. ==> 0XF8000B48[7:7] = 0x00000001U */
+ /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */
+ /* .. TERM_DISABLE_MODE = 0x1 */
+ /* .. ==> 0XF8000B48[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000B48, 0x00000180U, 0x00000180U),
+ /* .. IBUF_DISABLE_MODE = 0x1 */
+ /* .. ==> 0XF8000B4C[7:7] = 0x00000001U */
+ /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */
+ /* .. TERM_DISABLE_MODE = 0x1 */
+ /* .. ==> 0XF8000B4C[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000B4C, 0x00000180U, 0x00000180U),
+ /* .. IBUF_DISABLE_MODE = 0x1 */
+ /* .. ==> 0XF8000B50[7:7] = 0x00000001U */
+ /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */
+ /* .. TERM_DISABLE_MODE = 0x1 */
+ /* .. ==> 0XF8000B50[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U),
+ /* .. IBUF_DISABLE_MODE = 0x1 */
+ /* .. ==> 0XF8000B54[7:7] = 0x00000001U */
+ /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */
+ /* .. TERM_DISABLE_MODE = 0x1 */
+ /* .. ==> 0XF8000B54[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U),
+ /* .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS */
+ /* .. START: LOCK IT BACK */
+ /* .. LOCK_KEY = 0X767B */
+ /* .. ==> 0XF8000004[15:0] = 0x0000767BU */
+ /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+ /* .. FINISH: LOCK IT BACK */
+ /* .. START: SRAM/NOR SET OPMODE */
+ /* .. FINISH: SRAM/NOR SET OPMODE */
+ /* .. START: UART REGISTERS */
+ /* .. BDIV = 0x6 */
+ /* .. ==> 0XE0001034[7:0] = 0x00000006U */
+ /* .. ==> MASK : 0x000000FFU VAL : 0x00000006U */
+ /* .. */
+ EMIT_MASKWRITE(0XE0001034, 0x000000FFU, 0x00000006U),
+ /* .. CD = 0x7c */
+ /* .. ==> 0XE0001018[15:0] = 0x0000007CU */
+ /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU */
+ /* .. */
+ EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU, 0x0000007CU),
+ /* .. STPBRK = 0x0 */
+ /* .. ==> 0XE0001000[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. STTBRK = 0x0 */
+ /* .. ==> 0XE0001000[7:7] = 0x00000000U */
+ /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
+ /* .. RSTTO = 0x0 */
+ /* .. ==> 0XE0001000[6:6] = 0x00000000U */
+ /* .. ==> MASK : 0x00000040U VAL : 0x00000000U */
+ /* .. TXDIS = 0x0 */
+ /* .. ==> 0XE0001000[5:5] = 0x00000000U */
+ /* .. ==> MASK : 0x00000020U VAL : 0x00000000U */
+ /* .. TXEN = 0x1 */
+ /* .. ==> 0XE0001000[4:4] = 0x00000001U */
+ /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */
+ /* .. RXDIS = 0x0 */
+ /* .. ==> 0XE0001000[3:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
+ /* .. RXEN = 0x1 */
+ /* .. ==> 0XE0001000[2:2] = 0x00000001U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
+ /* .. TXRES = 0x1 */
+ /* .. ==> 0XE0001000[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. RXRES = 0x1 */
+ /* .. ==> 0XE0001000[0:0] = 0x00000001U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. */
+ EMIT_MASKWRITE(0XE0001000, 0x000001FFU, 0x00000017U),
+ /* .. CHMODE = 0x0 */
+ /* .. ==> 0XE0001004[9:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000300U VAL : 0x00000000U */
+ /* .. NBSTOP = 0x0 */
+ /* .. ==> 0XE0001004[7:6] = 0x00000000U */
+ /* .. ==> MASK : 0x000000C0U VAL : 0x00000000U */
+ /* .. PAR = 0x4 */
+ /* .. ==> 0XE0001004[5:3] = 0x00000004U */
+ /* .. ==> MASK : 0x00000038U VAL : 0x00000020U */
+ /* .. CHRL = 0x0 */
+ /* .. ==> 0XE0001004[2:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */
+ /* .. CLKS = 0x0 */
+ /* .. ==> 0XE0001004[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XE0001004, 0x000003FFU, 0x00000020U),
+ /* .. FINISH: UART REGISTERS */
+ /* .. START: QSPI REGISTERS */
+ /* .. Holdb_dr = 1 */
+ /* .. ==> 0XE000D000[19:19] = 0x00000001U */
+ /* .. ==> MASK : 0x00080000U VAL : 0x00080000U */
+ /* .. */
+ EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U),
+ /* .. FINISH: QSPI REGISTERS */
+ /* .. START: PL POWER ON RESET REGISTERS */
+ /* .. PCFG_POR_CNT_4K = 0 */
+ /* .. ==> 0XF8007000[29:29] = 0x00000000U */
+ /* .. ==> MASK : 0x20000000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U),
+ /* .. FINISH: PL POWER ON RESET REGISTERS */
+ /* .. START: SMC TIMING CALCULATION REGISTER UPDATE */
+ /* .. .. START: NAND SET CYCLE */
+ /* .. .. FINISH: NAND SET CYCLE */
+ /* .. .. START: OPMODE */
+ /* .. .. FINISH: OPMODE */
+ /* .. .. START: DIRECT COMMAND */
+ /* .. .. FINISH: DIRECT COMMAND */
+ /* .. .. START: SRAM/NOR CS0 SET CYCLE */
+ /* .. .. FINISH: SRAM/NOR CS0 SET CYCLE */
+ /* .. .. START: DIRECT COMMAND */
+ /* .. .. FINISH: DIRECT COMMAND */
+ /* .. .. START: NOR CS0 BASE ADDRESS */
+ /* .. .. FINISH: NOR CS0 BASE ADDRESS */
+ /* .. .. START: SRAM/NOR CS1 SET CYCLE */
+ /* .. .. FINISH: SRAM/NOR CS1 SET CYCLE */
+ /* .. .. START: DIRECT COMMAND */
+ /* .. .. FINISH: DIRECT COMMAND */
+ /* .. .. START: NOR CS1 BASE ADDRESS */
+ /* .. .. FINISH: NOR CS1 BASE ADDRESS */
+ /* .. .. START: USB RESET */
+ /* .. .. .. START: USB0 RESET */
+ /* .. .. .. .. START: DIR MODE BANK 0 */
+ /* .. .. .. .. FINISH: DIR MODE BANK 0 */
+ /* .. .. .. .. START: DIR MODE BANK 1 */
+ /* .. .. .. .. DIRECTION_1 = 0x4000 */
+ /* .. .. .. .. ==> 0XE000A244[21:0] = 0x00004000U */
+ /* .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U */
+ /* .. .. .. .. */
+ EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU, 0x00004000U),
+ /* .. .. .. .. FINISH: DIR MODE BANK 1 */
+ /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. MASK_1_LSW = 0xbfff */
+ /* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */
+ /* .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U */
+ /* .. .. .. .. DATA_1_LSW = 0x4000 */
+ /* .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U */
+ /* .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U */
+ /* .. .. .. .. */
+ EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF4000U),
+ /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
+ /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
+ /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
+ /* .. .. .. .. OP_ENABLE_1 = 0x4000 */
+ /* .. .. .. .. ==> 0XE000A248[21:0] = 0x00004000U */
+ /* .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U */
+ /* .. .. .. .. */
+ EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU, 0x00004000U),
+ /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
+ /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
+ /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
+ /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
+ /* .. .. .. .. MASK_1_LSW = 0xbfff */
+ /* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */
+ /* .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U */
+ /* .. .. .. .. DATA_1_LSW = 0x0 */
+ /* .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U */
+ /* .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U */
+ /* .. .. .. .. */
+ EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF0000U),
+ /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
+ /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
+ /* .. .. .. .. START: ADD 1 MS DELAY */
+ /* .. .. .. .. */
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ /* .. .. .. .. FINISH: ADD 1 MS DELAY */
+ /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. MASK_1_LSW = 0xbfff */
+ /* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */
+ /* .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U */
+ /* .. .. .. .. DATA_1_LSW = 0x4000 */
+ /* .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U */
+ /* .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U */
+ /* .. .. .. .. */
+ EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF4000U),
+ /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. FINISH: USB0 RESET */
+ /* .. .. .. START: USB1 RESET */
+ /* .. .. .. .. START: DIR MODE BANK 0 */
+ /* .. .. .. .. FINISH: DIR MODE BANK 0 */
+ /* .. .. .. .. START: DIR MODE BANK 1 */
+ /* .. .. .. .. FINISH: DIR MODE BANK 1 */
+ /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
+ /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
+ /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
+ /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
+ /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
+ /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
+ /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
+ /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
+ /* .. .. .. .. START: ADD 1 MS DELAY */
+ /* .. .. .. .. */
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ /* .. .. .. .. FINISH: ADD 1 MS DELAY */
+ /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. FINISH: USB1 RESET */
+ /* .. .. FINISH: USB RESET */
+ /* .. .. START: ENET RESET */
+ /* .. .. .. START: ENET0 RESET */
+ /* .. .. .. .. START: DIR MODE BANK 0 */
+ /* .. .. .. .. FINISH: DIR MODE BANK 0 */
+ /* .. .. .. .. START: DIR MODE BANK 1 */
+ /* .. .. .. .. FINISH: DIR MODE BANK 1 */
+ /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
+ /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
+ /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
+ /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
+ /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
+ /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
+ /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
+ /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
+ /* .. .. .. .. START: ADD 1 MS DELAY */
+ /* .. .. .. .. */
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ /* .. .. .. .. FINISH: ADD 1 MS DELAY */
+ /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. FINISH: ENET0 RESET */
+ /* .. .. .. START: ENET1 RESET */
+ /* .. .. .. .. START: DIR MODE BANK 0 */
+ /* .. .. .. .. FINISH: DIR MODE BANK 0 */
+ /* .. .. .. .. START: DIR MODE BANK 1 */
+ /* .. .. .. .. FINISH: DIR MODE BANK 1 */
+ /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
+ /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
+ /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
+ /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
+ /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
+ /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
+ /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
+ /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
+ /* .. .. .. .. START: ADD 1 MS DELAY */
+ /* .. .. .. .. */
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ /* .. .. .. .. FINISH: ADD 1 MS DELAY */
+ /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. FINISH: ENET1 RESET */
+ /* .. .. FINISH: ENET RESET */
+ /* .. .. START: I2C RESET */
+ /* .. .. .. START: I2C0 RESET */
+ /* .. .. .. .. START: DIR MODE GPIO BANK0 */
+ /* .. .. .. .. FINISH: DIR MODE GPIO BANK0 */
+ /* .. .. .. .. START: DIR MODE GPIO BANK1 */
+ /* .. .. .. .. FINISH: DIR MODE GPIO BANK1 */
+ /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. .. START: OUTPUT ENABLE */
+ /* .. .. .. .. FINISH: OUTPUT ENABLE */
+ /* .. .. .. .. START: OUTPUT ENABLE */
+ /* .. .. .. .. FINISH: OUTPUT ENABLE */
+ /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
+ /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
+ /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
+ /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
+ /* .. .. .. .. START: ADD 1 MS DELAY */
+ /* .. .. .. .. */
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ /* .. .. .. .. FINISH: ADD 1 MS DELAY */
+ /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. FINISH: I2C0 RESET */
+ /* .. .. .. START: I2C1 RESET */
+ /* .. .. .. .. START: DIR MODE GPIO BANK0 */
+ /* .. .. .. .. FINISH: DIR MODE GPIO BANK0 */
+ /* .. .. .. .. START: DIR MODE GPIO BANK1 */
+ /* .. .. .. .. FINISH: DIR MODE GPIO BANK1 */
+ /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. .. START: OUTPUT ENABLE */
+ /* .. .. .. .. FINISH: OUTPUT ENABLE */
+ /* .. .. .. .. START: OUTPUT ENABLE */
+ /* .. .. .. .. FINISH: OUTPUT ENABLE */
+ /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
+ /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
+ /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
+ /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
+ /* .. .. .. .. START: ADD 1 MS DELAY */
+ /* .. .. .. .. */
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ /* .. .. .. .. FINISH: ADD 1 MS DELAY */
+ /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. FINISH: I2C1 RESET */
+ /* .. .. FINISH: I2C RESET */
+ /* .. .. START: NOR CHIP SELECT */
+ /* .. .. .. START: DIR MODE BANK 0 */
+ /* .. .. .. FINISH: DIR MODE BANK 0 */
+ /* .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. START: OUTPUT ENABLE BANK 0 */
+ /* .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
+ /* .. .. FINISH: NOR CHIP SELECT */
+ /* .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE */
+ /* FINISH: top */
+ /* */
+ EMIT_EXIT(),
+
+ /* */
+};
+
+unsigned long ps7_post_config_3_0[] = {
+ /* START: top */
+ /* .. START: SLCR SETTINGS */
+ /* .. UNLOCK_KEY = 0XDF0D */
+ /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
+ /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ /* .. FINISH: SLCR SETTINGS */
+ /* .. START: ENABLING LEVEL SHIFTER */
+ /* .. USER_LVL_INP_EN_0 = 1 */
+ /* .. ==> 0XF8000900[3:3] = 0x00000001U */
+ /* .. ==> MASK : 0x00000008U VAL : 0x00000008U */
+ /* .. USER_LVL_OUT_EN_0 = 1 */
+ /* .. ==> 0XF8000900[2:2] = 0x00000001U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
+ /* .. USER_LVL_INP_EN_1 = 1 */
+ /* .. ==> 0XF8000900[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. USER_LVL_OUT_EN_1 = 1 */
+ /* .. ==> 0XF8000900[0:0] = 0x00000001U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU),
+ /* .. FINISH: ENABLING LEVEL SHIFTER */
+ /* .. START: FPGA RESETS TO 0 */
+ /* .. reserved_3 = 0 */
+ /* .. ==> 0XF8000240[31:25] = 0x00000000U */
+ /* .. ==> MASK : 0xFE000000U VAL : 0x00000000U */
+ /* .. reserved_FPGA_ACP_RST = 0 */
+ /* .. ==> 0XF8000240[24:24] = 0x00000000U */
+ /* .. ==> MASK : 0x01000000U VAL : 0x00000000U */
+ /* .. reserved_FPGA_AXDS3_RST = 0 */
+ /* .. ==> 0XF8000240[23:23] = 0x00000000U */
+ /* .. ==> MASK : 0x00800000U VAL : 0x00000000U */
+ /* .. reserved_FPGA_AXDS2_RST = 0 */
+ /* .. ==> 0XF8000240[22:22] = 0x00000000U */
+ /* .. ==> MASK : 0x00400000U VAL : 0x00000000U */
+ /* .. reserved_FPGA_AXDS1_RST = 0 */
+ /* .. ==> 0XF8000240[21:21] = 0x00000000U */
+ /* .. ==> MASK : 0x00200000U VAL : 0x00000000U */
+ /* .. reserved_FPGA_AXDS0_RST = 0 */
+ /* .. ==> 0XF8000240[20:20] = 0x00000000U */
+ /* .. ==> MASK : 0x00100000U VAL : 0x00000000U */
+ /* .. reserved_2 = 0 */
+ /* .. ==> 0XF8000240[19:18] = 0x00000000U */
+ /* .. ==> MASK : 0x000C0000U VAL : 0x00000000U */
+ /* .. reserved_FSSW1_FPGA_RST = 0 */
+ /* .. ==> 0XF8000240[17:17] = 0x00000000U */
+ /* .. ==> MASK : 0x00020000U VAL : 0x00000000U */
+ /* .. reserved_FSSW0_FPGA_RST = 0 */
+ /* .. ==> 0XF8000240[16:16] = 0x00000000U */
+ /* .. ==> MASK : 0x00010000U VAL : 0x00000000U */
+ /* .. reserved_1 = 0 */
+ /* .. ==> 0XF8000240[15:14] = 0x00000000U */
+ /* .. ==> MASK : 0x0000C000U VAL : 0x00000000U */
+ /* .. reserved_FPGA_FMSW1_RST = 0 */
+ /* .. ==> 0XF8000240[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. reserved_FPGA_FMSW0_RST = 0 */
+ /* .. ==> 0XF8000240[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. reserved_FPGA_DMA3_RST = 0 */
+ /* .. ==> 0XF8000240[11:11] = 0x00000000U */
+ /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
+ /* .. reserved_FPGA_DMA2_RST = 0 */
+ /* .. ==> 0XF8000240[10:10] = 0x00000000U */
+ /* .. ==> MASK : 0x00000400U VAL : 0x00000000U */
+ /* .. reserved_FPGA_DMA1_RST = 0 */
+ /* .. ==> 0XF8000240[9:9] = 0x00000000U */
+ /* .. ==> MASK : 0x00000200U VAL : 0x00000000U */
+ /* .. reserved_FPGA_DMA0_RST = 0 */
+ /* .. ==> 0XF8000240[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. reserved = 0 */
+ /* .. ==> 0XF8000240[7:4] = 0x00000000U */
+ /* .. ==> MASK : 0x000000F0U VAL : 0x00000000U */
+ /* .. FPGA3_OUT_RST = 0 */
+ /* .. ==> 0XF8000240[3:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
+ /* .. FPGA2_OUT_RST = 0 */
+ /* .. ==> 0XF8000240[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. FPGA1_OUT_RST = 0 */
+ /* .. ==> 0XF8000240[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. FPGA0_OUT_RST = 0 */
+ /* .. ==> 0XF8000240[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU, 0x00000000U),
+ /* .. FINISH: FPGA RESETS TO 0 */
+ /* .. START: AFI REGISTERS */
+ /* .. .. START: AFI0 REGISTERS */
+ /* .. .. FINISH: AFI0 REGISTERS */
+ /* .. .. START: AFI1 REGISTERS */
+ /* .. .. FINISH: AFI1 REGISTERS */
+ /* .. .. START: AFI2 REGISTERS */
+ /* .. .. FINISH: AFI2 REGISTERS */
+ /* .. .. START: AFI3 REGISTERS */
+ /* .. .. FINISH: AFI3 REGISTERS */
+ /* .. .. START: AFI2 SECURE REGISTER */
+ /* .. .. FINISH: AFI2 SECURE REGISTER */
+ /* .. FINISH: AFI REGISTERS */
+ /* .. START: LOCK IT BACK */
+ /* .. LOCK_KEY = 0X767B */
+ /* .. ==> 0XF8000004[15:0] = 0x0000767BU */
+ /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+ /* .. FINISH: LOCK IT BACK */
+ /* FINISH: top */
+ /* */
+ EMIT_EXIT(),
+
+ /* */
+};
+
+unsigned long ps7_debug_3_0[] = {
+ /* START: top */
+ /* .. START: CROSS TRIGGER CONFIGURATIONS */
+ /* .. .. START: UNLOCKING CTI REGISTERS */
+ /* .. .. KEY = 0XC5ACCE55 */
+ /* .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U */
+ /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU, 0xC5ACCE55U),
+ /* .. .. KEY = 0XC5ACCE55 */
+ /* .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U */
+ /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU, 0xC5ACCE55U),
+ /* .. .. KEY = 0XC5ACCE55 */
+ /* .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U */
+ /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU, 0xC5ACCE55U),
+ /* .. .. FINISH: UNLOCKING CTI REGISTERS */
+ /* .. .. START: ENABLING CTI MODULES AND CHANNELS */
+ /* .. .. FINISH: ENABLING CTI MODULES AND CHANNELS */
+ /* .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS */
+ /* .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS */
+ /* .. FINISH: CROSS TRIGGER CONFIGURATIONS */
+ /* FINISH: top */
+ /* */
+ EMIT_EXIT(),
+
+ /* */
+};
+
+unsigned long ps7_pll_init_data_2_0[] = {
+ /* START: top */
+ /* .. START: SLCR SETTINGS */
+ /* .. UNLOCK_KEY = 0XDF0D */
+ /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
+ /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ /* .. FINISH: SLCR SETTINGS */
+ /* .. START: PLL SLCR REGISTERS */
+ /* .. .. START: ARM PLL INIT */
+ /* .. .. PLL_RES = 0xc */
+ /* .. .. ==> 0XF8000110[7:4] = 0x0000000CU */
+ /* .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U */
+ /* .. .. PLL_CP = 0x2 */
+ /* .. .. ==> 0XF8000110[11:8] = 0x00000002U */
+ /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */
+ /* .. .. LOCK_CNT = 0x177 */
+ /* .. .. ==> 0XF8000110[21:12] = 0x00000177U */
+ /* .. .. ==> MASK : 0x003FF000U VAL : 0x00177000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x001772C0U),
+ /* .. .. .. START: UPDATE FB_DIV */
+ /* .. .. .. PLL_FDIV = 0x1a */
+ /* .. .. .. ==> 0XF8000100[18:12] = 0x0000001AU */
+ /* .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001A000U */
+ /* .. .. .. */
+ EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x0001A000U),
+ /* .. .. .. FINISH: UPDATE FB_DIV */
+ /* .. .. .. START: BY PASS PLL */
+ /* .. .. .. PLL_BYPASS_FORCE = 1 */
+ /* .. .. .. ==> 0XF8000100[4:4] = 0x00000001U */
+ /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U */
+ /* .. .. .. */
+ EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U),
+ /* .. .. .. FINISH: BY PASS PLL */
+ /* .. .. .. START: ASSERT RESET */
+ /* .. .. .. PLL_RESET = 1 */
+ /* .. .. .. ==> 0XF8000100[0:0] = 0x00000001U */
+ /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. .. .. */
+ EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U),
+ /* .. .. .. FINISH: ASSERT RESET */
+ /* .. .. .. START: DEASSERT RESET */
+ /* .. .. .. PLL_RESET = 0 */
+ /* .. .. .. ==> 0XF8000100[0:0] = 0x00000000U */
+ /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. .. .. */
+ EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U),
+ /* .. .. .. FINISH: DEASSERT RESET */
+ /* .. .. .. START: CHECK PLL STATUS */
+ /* .. .. .. ARM_PLL_LOCK = 1 */
+ /* .. .. .. ==> 0XF800010C[0:0] = 0x00000001U */
+ /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. .. .. */
+ EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+ /* .. .. .. FINISH: CHECK PLL STATUS */
+ /* .. .. .. START: REMOVE PLL BY PASS */
+ /* .. .. .. PLL_BYPASS_FORCE = 0 */
+ /* .. .. .. ==> 0XF8000100[4:4] = 0x00000000U */
+ /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
+ /* .. .. .. */
+ EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U),
+ /* .. .. .. FINISH: REMOVE PLL BY PASS */
+ /* .. .. .. SRCSEL = 0x0 */
+ /* .. .. .. ==> 0XF8000120[5:4] = 0x00000000U */
+ /* .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
+ /* .. .. .. DIVISOR = 0x2 */
+ /* .. .. .. ==> 0XF8000120[13:8] = 0x00000002U */
+ /* .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U */
+ /* .. .. .. CPU_6OR4XCLKACT = 0x1 */
+ /* .. .. .. ==> 0XF8000120[24:24] = 0x00000001U */
+ /* .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U */
+ /* .. .. .. CPU_3OR2XCLKACT = 0x1 */
+ /* .. .. .. ==> 0XF8000120[25:25] = 0x00000001U */
+ /* .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U */
+ /* .. .. .. CPU_2XCLKACT = 0x1 */
+ /* .. .. .. ==> 0XF8000120[26:26] = 0x00000001U */
+ /* .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U */
+ /* .. .. .. CPU_1XCLKACT = 0x1 */
+ /* .. .. .. ==> 0XF8000120[27:27] = 0x00000001U */
+ /* .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U */
+ /* .. .. .. CPU_PERI_CLKACT = 0x1 */
+ /* .. .. .. ==> 0XF8000120[28:28] = 0x00000001U */
+ /* .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U */
+ /* .. .. .. */
+ EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000200U),
+ /* .. .. FINISH: ARM PLL INIT */
+ /* .. .. START: DDR PLL INIT */
+ /* .. .. PLL_RES = 0xc */
+ /* .. .. ==> 0XF8000114[7:4] = 0x0000000CU */
+ /* .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U */
+ /* .. .. PLL_CP = 0x2 */
+ /* .. .. ==> 0XF8000114[11:8] = 0x00000002U */
+ /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */
+ /* .. .. LOCK_CNT = 0x1db */
+ /* .. .. ==> 0XF8000114[21:12] = 0x000001DBU */
+ /* .. .. ==> MASK : 0x003FF000U VAL : 0x001DB000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x001DB2C0U),
+ /* .. .. .. START: UPDATE FB_DIV */
+ /* .. .. .. PLL_FDIV = 0x15 */
+ /* .. .. .. ==> 0XF8000104[18:12] = 0x00000015U */
+ /* .. .. .. ==> MASK : 0x0007F000U VAL : 0x00015000U */
+ /* .. .. .. */
+ EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x00015000U),
+ /* .. .. .. FINISH: UPDATE FB_DIV */
+ /* .. .. .. START: BY PASS PLL */
+ /* .. .. .. PLL_BYPASS_FORCE = 1 */
+ /* .. .. .. ==> 0XF8000104[4:4] = 0x00000001U */
+ /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U */
+ /* .. .. .. */
+ EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000010U),
+ /* .. .. .. FINISH: BY PASS PLL */
+ /* .. .. .. START: ASSERT RESET */
+ /* .. .. .. PLL_RESET = 1 */
+ /* .. .. .. ==> 0XF8000104[0:0] = 0x00000001U */
+ /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. .. .. */
+ EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000001U),
+ /* .. .. .. FINISH: ASSERT RESET */
+ /* .. .. .. START: DEASSERT RESET */
+ /* .. .. .. PLL_RESET = 0 */
+ /* .. .. .. ==> 0XF8000104[0:0] = 0x00000000U */
+ /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. .. .. */
+ EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000000U),
+ /* .. .. .. FINISH: DEASSERT RESET */
+ /* .. .. .. START: CHECK PLL STATUS */
+ /* .. .. .. DDR_PLL_LOCK = 1 */
+ /* .. .. .. ==> 0XF800010C[1:1] = 0x00000001U */
+ /* .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. .. .. */
+ EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+ /* .. .. .. FINISH: CHECK PLL STATUS */
+ /* .. .. .. START: REMOVE PLL BY PASS */
+ /* .. .. .. PLL_BYPASS_FORCE = 0 */
+ /* .. .. .. ==> 0XF8000104[4:4] = 0x00000000U */
+ /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
+ /* .. .. .. */
+ EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U),
+ /* .. .. .. FINISH: REMOVE PLL BY PASS */
+ /* .. .. .. DDR_3XCLKACT = 0x1 */
+ /* .. .. .. ==> 0XF8000124[0:0] = 0x00000001U */
+ /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. .. .. DDR_2XCLKACT = 0x1 */
+ /* .. .. .. ==> 0XF8000124[1:1] = 0x00000001U */
+ /* .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. .. .. DDR_3XCLK_DIVISOR = 0x2 */
+ /* .. .. .. ==> 0XF8000124[25:20] = 0x00000002U */
+ /* .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U */
+ /* .. .. .. DDR_2XCLK_DIVISOR = 0x3 */
+ /* .. .. .. ==> 0XF8000124[31:26] = 0x00000003U */
+ /* .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U */
+ /* .. .. .. */
+ EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U),
+ /* .. .. FINISH: DDR PLL INIT */
+ /* .. .. START: IO PLL INIT */
+ /* .. .. PLL_RES = 0xc */
+ /* .. .. ==> 0XF8000118[7:4] = 0x0000000CU */
+ /* .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U */
+ /* .. .. PLL_CP = 0x2 */
+ /* .. .. ==> 0XF8000118[11:8] = 0x00000002U */
+ /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */
+ /* .. .. LOCK_CNT = 0x1f4 */
+ /* .. .. ==> 0XF8000118[21:12] = 0x000001F4U */
+ /* .. .. ==> MASK : 0x003FF000U VAL : 0x001F4000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x001F42C0U),
+ /* .. .. .. START: UPDATE FB_DIV */
+ /* .. .. .. PLL_FDIV = 0x14 */
+ /* .. .. .. ==> 0XF8000108[18:12] = 0x00000014U */
+ /* .. .. .. ==> MASK : 0x0007F000U VAL : 0x00014000U */
+ /* .. .. .. */
+ EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x00014000U),
+ /* .. .. .. FINISH: UPDATE FB_DIV */
+ /* .. .. .. START: BY PASS PLL */
+ /* .. .. .. PLL_BYPASS_FORCE = 1 */
+ /* .. .. .. ==> 0XF8000108[4:4] = 0x00000001U */
+ /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U */
+ /* .. .. .. */
+ EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U),
+ /* .. .. .. FINISH: BY PASS PLL */
+ /* .. .. .. START: ASSERT RESET */
+ /* .. .. .. PLL_RESET = 1 */
+ /* .. .. .. ==> 0XF8000108[0:0] = 0x00000001U */
+ /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. .. .. */
+ EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U),
+ /* .. .. .. FINISH: ASSERT RESET */
+ /* .. .. .. START: DEASSERT RESET */
+ /* .. .. .. PLL_RESET = 0 */
+ /* .. .. .. ==> 0XF8000108[0:0] = 0x00000000U */
+ /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. .. .. */
+ EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U),
+ /* .. .. .. FINISH: DEASSERT RESET */
+ /* .. .. .. START: CHECK PLL STATUS */
+ /* .. .. .. IO_PLL_LOCK = 1 */
+ /* .. .. .. ==> 0XF800010C[2:2] = 0x00000001U */
+ /* .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U */
+ /* .. .. .. */
+ EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+ /* .. .. .. FINISH: CHECK PLL STATUS */
+ /* .. .. .. START: REMOVE PLL BY PASS */
+ /* .. .. .. PLL_BYPASS_FORCE = 0 */
+ /* .. .. .. ==> 0XF8000108[4:4] = 0x00000000U */
+ /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
+ /* .. .. .. */
+ EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000000U),
+ /* .. .. .. FINISH: REMOVE PLL BY PASS */
+ /* .. .. FINISH: IO PLL INIT */
+ /* .. FINISH: PLL SLCR REGISTERS */
+ /* .. START: LOCK IT BACK */
+ /* .. LOCK_KEY = 0X767B */
+ /* .. ==> 0XF8000004[15:0] = 0x0000767BU */
+ /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+ /* .. FINISH: LOCK IT BACK */
+ /* FINISH: top */
+ /* */
+ EMIT_EXIT(),
+
+ /* */
+};
+
+unsigned long ps7_clock_init_data_2_0[] = {
+ /* START: top */
+ /* .. START: SLCR SETTINGS */
+ /* .. UNLOCK_KEY = 0XDF0D */
+ /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
+ /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ /* .. FINISH: SLCR SETTINGS */
+ /* .. START: CLOCK CONTROL SLCR REGISTERS */
+ /* .. CLKACT = 0x1 */
+ /* .. ==> 0XF8000128[0:0] = 0x00000001U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. DIVISOR0 = 0x34 */
+ /* .. ==> 0XF8000128[13:8] = 0x00000034U */
+ /* .. ==> MASK : 0x00003F00U VAL : 0x00003400U */
+ /* .. DIVISOR1 = 0x2 */
+ /* .. ==> 0XF8000128[25:20] = 0x00000002U */
+ /* .. ==> MASK : 0x03F00000U VAL : 0x00200000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00203401U),
+ /* .. CLKACT = 0x1 */
+ /* .. ==> 0XF8000138[0:0] = 0x00000001U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. SRCSEL = 0x0 */
+ /* .. ==> 0XF8000138[4:4] = 0x00000000U */
+ /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000001U),
+ /* .. CLKACT = 0x1 */
+ /* .. ==> 0XF8000140[0:0] = 0x00000001U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. SRCSEL = 0x0 */
+ /* .. ==> 0XF8000140[6:4] = 0x00000000U */
+ /* .. ==> MASK : 0x00000070U VAL : 0x00000000U */
+ /* .. DIVISOR = 0x8 */
+ /* .. ==> 0XF8000140[13:8] = 0x00000008U */
+ /* .. ==> MASK : 0x00003F00U VAL : 0x00000800U */
+ /* .. DIVISOR1 = 0x1 */
+ /* .. ==> 0XF8000140[25:20] = 0x00000001U */
+ /* .. ==> MASK : 0x03F00000U VAL : 0x00100000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00100801U),
+ /* .. CLKACT = 0x1 */
+ /* .. ==> 0XF800014C[0:0] = 0x00000001U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. SRCSEL = 0x0 */
+ /* .. ==> 0XF800014C[5:4] = 0x00000000U */
+ /* .. ==> MASK : 0x00000030U VAL : 0x00000000U */
+ /* .. DIVISOR = 0x5 */
+ /* .. ==> 0XF800014C[13:8] = 0x00000005U */
+ /* .. ==> MASK : 0x00003F00U VAL : 0x00000500U */
+ /* .. */
+ EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000501U),
+ /* .. CLKACT0 = 0x1 */
+ /* .. ==> 0XF8000150[0:0] = 0x00000001U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. CLKACT1 = 0x0 */
+ /* .. ==> 0XF8000150[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. SRCSEL = 0x0 */
+ /* .. ==> 0XF8000150[5:4] = 0x00000000U */
+ /* .. ==> MASK : 0x00000030U VAL : 0x00000000U */
+ /* .. DIVISOR = 0x14 */
+ /* .. ==> 0XF8000150[13:8] = 0x00000014U */
+ /* .. ==> MASK : 0x00003F00U VAL : 0x00001400U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00001401U),
+ /* .. CLKACT0 = 0x0 */
+ /* .. ==> 0XF8000154[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. CLKACT1 = 0x1 */
+ /* .. ==> 0XF8000154[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. SRCSEL = 0x0 */
+ /* .. ==> 0XF8000154[5:4] = 0x00000000U */
+ /* .. ==> MASK : 0x00000030U VAL : 0x00000000U */
+ /* .. DIVISOR = 0xa */
+ /* .. ==> 0XF8000154[13:8] = 0x0000000AU */
+ /* .. ==> MASK : 0x00003F00U VAL : 0x00000A00U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00000A02U),
+ /* .. .. START: TRACE CLOCK */
+ /* .. .. FINISH: TRACE CLOCK */
+ /* .. .. CLKACT = 0x1 */
+ /* .. .. ==> 0XF8000168[0:0] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. .. SRCSEL = 0x0 */
+ /* .. .. ==> 0XF8000168[5:4] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
+ /* .. .. DIVISOR = 0x5 */
+ /* .. .. ==> 0XF8000168[13:8] = 0x00000005U */
+ /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000501U),
+ /* .. .. SRCSEL = 0x0 */
+ /* .. .. ==> 0XF8000170[5:4] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
+ /* .. .. DIVISOR0 = 0xa */
+ /* .. .. ==> 0XF8000170[13:8] = 0x0000000AU */
+ /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U */
+ /* .. .. DIVISOR1 = 0x1 */
+ /* .. .. ==> 0XF8000170[25:20] = 0x00000001U */
+ /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00100A00U),
+ /* .. .. SRCSEL = 0x0 */
+ /* .. .. ==> 0XF8000180[5:4] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
+ /* .. .. DIVISOR0 = 0x7 */
+ /* .. .. ==> 0XF8000180[13:8] = 0x00000007U */
+ /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000700U */
+ /* .. .. DIVISOR1 = 0x1 */
+ /* .. .. ==> 0XF8000180[25:20] = 0x00000001U */
+ /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00100700U),
+ /* .. .. SRCSEL = 0x0 */
+ /* .. .. ==> 0XF8000190[5:4] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
+ /* .. .. DIVISOR0 = 0x5 */
+ /* .. .. ==> 0XF8000190[13:8] = 0x00000005U */
+ /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U */
+ /* .. .. DIVISOR1 = 0x1 */
+ /* .. .. ==> 0XF8000190[25:20] = 0x00000001U */
+ /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00100500U),
+ /* .. .. SRCSEL = 0x0 */
+ /* .. .. ==> 0XF80001A0[5:4] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
+ /* .. .. DIVISOR0 = 0x14 */
+ /* .. .. ==> 0XF80001A0[13:8] = 0x00000014U */
+ /* .. .. ==> MASK : 0x00003F00U VAL : 0x00001400U */
+ /* .. .. DIVISOR1 = 0x1 */
+ /* .. .. ==> 0XF80001A0[25:20] = 0x00000001U */
+ /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00101400U),
+ /* .. .. CLK_621_TRUE = 0x1 */
+ /* .. .. ==> 0XF80001C4[0:0] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U),
+ /* .. .. DMA_CPU_2XCLKACT = 0x1 */
+ /* .. .. ==> 0XF800012C[0:0] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. .. USB0_CPU_1XCLKACT = 0x1 */
+ /* .. .. ==> 0XF800012C[2:2] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000004U VAL : 0x00000004U */
+ /* .. .. USB1_CPU_1XCLKACT = 0x1 */
+ /* .. .. ==> 0XF800012C[3:3] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000008U VAL : 0x00000008U */
+ /* .. .. GEM0_CPU_1XCLKACT = 0x1 */
+ /* .. .. ==> 0XF800012C[6:6] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000040U VAL : 0x00000040U */
+ /* .. .. GEM1_CPU_1XCLKACT = 0x0 */
+ /* .. .. ==> 0XF800012C[7:7] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000080U VAL : 0x00000000U */
+ /* .. .. SDI0_CPU_1XCLKACT = 0x1 */
+ /* .. .. ==> 0XF800012C[10:10] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000400U VAL : 0x00000400U */
+ /* .. .. SDI1_CPU_1XCLKACT = 0x0 */
+ /* .. .. ==> 0XF800012C[11:11] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */
+ /* .. .. SPI0_CPU_1XCLKACT = 0x0 */
+ /* .. .. ==> 0XF800012C[14:14] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00004000U VAL : 0x00000000U */
+ /* .. .. SPI1_CPU_1XCLKACT = 0x0 */
+ /* .. .. ==> 0XF800012C[15:15] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */
+ /* .. .. CAN0_CPU_1XCLKACT = 0x0 */
+ /* .. .. ==> 0XF800012C[16:16] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
+ /* .. .. CAN1_CPU_1XCLKACT = 0x0 */
+ /* .. .. ==> 0XF800012C[17:17] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
+ /* .. .. I2C0_CPU_1XCLKACT = 0x1 */
+ /* .. .. ==> 0XF800012C[18:18] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00040000U VAL : 0x00040000U */
+ /* .. .. I2C1_CPU_1XCLKACT = 0x1 */
+ /* .. .. ==> 0XF800012C[19:19] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00080000U VAL : 0x00080000U */
+ /* .. .. UART0_CPU_1XCLKACT = 0x0 */
+ /* .. .. ==> 0XF800012C[20:20] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00100000U VAL : 0x00000000U */
+ /* .. .. UART1_CPU_1XCLKACT = 0x1 */
+ /* .. .. ==> 0XF800012C[21:21] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00200000U VAL : 0x00200000U */
+ /* .. .. GPIO_CPU_1XCLKACT = 0x1 */
+ /* .. .. ==> 0XF800012C[22:22] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00400000U VAL : 0x00400000U */
+ /* .. .. LQSPI_CPU_1XCLKACT = 0x1 */
+ /* .. .. ==> 0XF800012C[23:23] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00800000U VAL : 0x00800000U */
+ /* .. .. SMC_CPU_1XCLKACT = 0x1 */
+ /* .. .. ==> 0XF800012C[24:24] = 0x00000001U */
+ /* .. .. ==> MASK : 0x01000000U VAL : 0x01000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01EC044DU),
+ /* .. FINISH: CLOCK CONTROL SLCR REGISTERS */
+ /* .. START: THIS SHOULD BE BLANK */
+ /* .. FINISH: THIS SHOULD BE BLANK */
+ /* .. START: LOCK IT BACK */
+ /* .. LOCK_KEY = 0X767B */
+ /* .. ==> 0XF8000004[15:0] = 0x0000767BU */
+ /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+ /* .. FINISH: LOCK IT BACK */
+ /* FINISH: top */
+ /* */
+ EMIT_EXIT(),
+
+ /* */
+};
+
+unsigned long ps7_ddr_init_data_2_0[] = {
+ /* START: top */
+ /* .. START: DDR INITIALIZATION */
+ /* .. .. START: LOCK DDR */
+ /* .. .. reg_ddrc_soft_rstb = 0 */
+ /* .. .. ==> 0XF8006000[0:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_powerdown_en = 0x0 */
+ /* .. .. ==> 0XF8006000[1:1] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_data_bus_width = 0x0 */
+ /* .. .. ==> 0XF8006000[3:2] = 0x00000000U */
+ /* .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U */
+ /* .. .. reg_ddrc_burst8_refresh = 0x0 */
+ /* .. .. ==> 0XF8006000[6:4] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000070U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_rdwr_idle_gap = 0x1 */
+ /* .. .. ==> 0XF8006000[13:7] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U */
+ /* .. .. reg_ddrc_dis_rd_bypass = 0x0 */
+ /* .. .. ==> 0XF8006000[14:14] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00004000U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_dis_act_bypass = 0x0 */
+ /* .. .. ==> 0XF8006000[15:15] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_dis_auto_refresh = 0x0 */
+ /* .. .. ==> 0XF8006000[16:16] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000080U),
+ /* .. .. FINISH: LOCK DDR */
+ /* .. .. reg_ddrc_t_rfc_nom_x32 = 0x7f */
+ /* .. .. ==> 0XF8006004[11:0] = 0x0000007FU */
+ /* .. .. ==> MASK : 0x00000FFFU VAL : 0x0000007FU */
+ /* .. .. reg_ddrc_active_ranks = 0x1 */
+ /* .. .. ==> 0XF8006004[13:12] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00003000U VAL : 0x00001000U */
+ /* .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 */
+ /* .. .. ==> 0XF8006004[18:14] = 0x00000000U */
+ /* .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_wr_odt_block = 0x1 */
+ /* .. .. ==> 0XF8006004[20:19] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00180000U VAL : 0x00080000U */
+ /* .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0 */
+ /* .. .. ==> 0XF8006004[21:21] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00200000U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_addrmap_cs_bit1 = 0x0 */
+ /* .. .. ==> 0XF8006004[26:22] = 0x00000000U */
+ /* .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_addrmap_open_bank = 0x0 */
+ /* .. .. ==> 0XF8006004[27:27] = 0x00000000U */
+ /* .. .. ==> MASK : 0x08000000U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_addrmap_4bank_ram = 0x0 */
+ /* .. .. ==> 0XF8006004[28:28] = 0x00000000U */
+ /* .. .. ==> MASK : 0x10000000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU, 0x0008107FU),
+ /* .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf */
+ /* .. .. ==> 0XF8006008[10:0] = 0x0000000FU */
+ /* .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU */
+ /* .. .. reg_ddrc_hpr_max_starve_x32 = 0xf */
+ /* .. .. ==> 0XF8006008[21:11] = 0x0000000FU */
+ /* .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U */
+ /* .. .. reg_ddrc_hpr_xact_run_length = 0xf */
+ /* .. .. ==> 0XF8006008[25:22] = 0x0000000FU */
+ /* .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU, 0x03C0780FU),
+ /* .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 */
+ /* .. .. ==> 0XF800600C[10:0] = 0x00000001U */
+ /* .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U */
+ /* .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 */
+ /* .. .. ==> 0XF800600C[21:11] = 0x00000002U */
+ /* .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U */
+ /* .. .. reg_ddrc_lpr_xact_run_length = 0x8 */
+ /* .. .. ==> 0XF800600C[25:22] = 0x00000008U */
+ /* .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU, 0x02001001U),
+ /* .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 */
+ /* .. .. ==> 0XF8006010[10:0] = 0x00000001U */
+ /* .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U */
+ /* .. .. reg_ddrc_w_xact_run_length = 0x8 */
+ /* .. .. ==> 0XF8006010[14:11] = 0x00000008U */
+ /* .. .. ==> MASK : 0x00007800U VAL : 0x00004000U */
+ /* .. .. reg_ddrc_w_max_starve_x32 = 0x2 */
+ /* .. .. ==> 0XF8006010[25:15] = 0x00000002U */
+ /* .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU, 0x00014001U),
+ /* .. .. reg_ddrc_t_rc = 0x1a */
+ /* .. .. ==> 0XF8006014[5:0] = 0x0000001AU */
+ /* .. .. ==> MASK : 0x0000003FU VAL : 0x0000001AU */
+ /* .. .. reg_ddrc_t_rfc_min = 0x54 */
+ /* .. .. ==> 0XF8006014[13:6] = 0x00000054U */
+ /* .. .. ==> MASK : 0x00003FC0U VAL : 0x00001500U */
+ /* .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 */
+ /* .. .. ==> 0XF8006014[20:14] = 0x00000010U */
+ /* .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU, 0x0004151AU),
+ /* .. .. reg_ddrc_wr2pre = 0x12 */
+ /* .. .. ==> 0XF8006018[4:0] = 0x00000012U */
+ /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U */
+ /* .. .. reg_ddrc_powerdown_to_x32 = 0x6 */
+ /* .. .. ==> 0XF8006018[9:5] = 0x00000006U */
+ /* .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U */
+ /* .. .. reg_ddrc_t_faw = 0x15 */
+ /* .. .. ==> 0XF8006018[15:10] = 0x00000015U */
+ /* .. .. ==> MASK : 0x0000FC00U VAL : 0x00005400U */
+ /* .. .. reg_ddrc_t_ras_max = 0x23 */
+ /* .. .. ==> 0XF8006018[21:16] = 0x00000023U */
+ /* .. .. ==> MASK : 0x003F0000U VAL : 0x00230000U */
+ /* .. .. reg_ddrc_t_ras_min = 0x13 */
+ /* .. .. ==> 0XF8006018[26:22] = 0x00000013U */
+ /* .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U */
+ /* .. .. reg_ddrc_t_cke = 0x4 */
+ /* .. .. ==> 0XF8006018[31:28] = 0x00000004U */
+ /* .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU, 0x44E354D2U),
+ /* .. .. reg_ddrc_write_latency = 0x5 */
+ /* .. .. ==> 0XF800601C[4:0] = 0x00000005U */
+ /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U */
+ /* .. .. reg_ddrc_rd2wr = 0x7 */
+ /* .. .. ==> 0XF800601C[9:5] = 0x00000007U */
+ /* .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U */
+ /* .. .. reg_ddrc_wr2rd = 0xe */
+ /* .. .. ==> 0XF800601C[14:10] = 0x0000000EU */
+ /* .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U */
+ /* .. .. reg_ddrc_t_xp = 0x4 */
+ /* .. .. ==> 0XF800601C[19:15] = 0x00000004U */
+ /* .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U */
+ /* .. .. reg_ddrc_pad_pd = 0x0 */
+ /* .. .. ==> 0XF800601C[22:20] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00700000U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_rd2pre = 0x4 */
+ /* .. .. ==> 0XF800601C[27:23] = 0x00000004U */
+ /* .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U */
+ /* .. .. reg_ddrc_t_rcd = 0x7 */
+ /* .. .. ==> 0XF800601C[31:28] = 0x00000007U */
+ /* .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU, 0x720238E5U),
+ /* .. .. reg_ddrc_t_ccd = 0x4 */
+ /* .. .. ==> 0XF8006020[4:2] = 0x00000004U */
+ /* .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U */
+ /* .. .. reg_ddrc_t_rrd = 0x6 */
+ /* .. .. ==> 0XF8006020[7:5] = 0x00000006U */
+ /* .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U */
+ /* .. .. reg_ddrc_refresh_margin = 0x2 */
+ /* .. .. ==> 0XF8006020[11:8] = 0x00000002U */
+ /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */
+ /* .. .. reg_ddrc_t_rp = 0x7 */
+ /* .. .. ==> 0XF8006020[15:12] = 0x00000007U */
+ /* .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U */
+ /* .. .. reg_ddrc_refresh_to_x32 = 0x8 */
+ /* .. .. ==> 0XF8006020[20:16] = 0x00000008U */
+ /* .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U */
+ /* .. .. reg_ddrc_sdram = 0x1 */
+ /* .. .. ==> 0XF8006020[21:21] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00200000U VAL : 0x00200000U */
+ /* .. .. reg_ddrc_mobile = 0x0 */
+ /* .. .. ==> 0XF8006020[22:22] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00400000U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_clock_stop_en = 0x0 */
+ /* .. .. ==> 0XF8006020[23:23] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00800000U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_read_latency = 0x7 */
+ /* .. .. ==> 0XF8006020[28:24] = 0x00000007U */
+ /* .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U */
+ /* .. .. reg_phy_mode_ddr1_ddr2 = 0x1 */
+ /* .. .. ==> 0XF8006020[29:29] = 0x00000001U */
+ /* .. .. ==> MASK : 0x20000000U VAL : 0x20000000U */
+ /* .. .. reg_ddrc_dis_pad_pd = 0x0 */
+ /* .. .. ==> 0XF8006020[30:30] = 0x00000000U */
+ /* .. .. ==> MASK : 0x40000000U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_loopback = 0x0 */
+ /* .. .. ==> 0XF8006020[31:31] = 0x00000000U */
+ /* .. .. ==> MASK : 0x80000000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU, 0x272872D0U),
+ /* .. .. reg_ddrc_en_2t_timing_mode = 0x0 */
+ /* .. .. ==> 0XF8006024[0:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_prefer_write = 0x0 */
+ /* .. .. ==> 0XF8006024[1:1] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_max_rank_rd = 0xf */
+ /* .. .. ==> 0XF8006024[5:2] = 0x0000000FU */
+ /* .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU */
+ /* .. .. reg_ddrc_mr_wr = 0x0 */
+ /* .. .. ==> 0XF8006024[6:6] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000040U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_mr_addr = 0x0 */
+ /* .. .. ==> 0XF8006024[8:7] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000180U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_mr_data = 0x0 */
+ /* .. .. ==> 0XF8006024[24:9] = 0x00000000U */
+ /* .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U */
+ /* .. .. ddrc_reg_mr_wr_busy = 0x0 */
+ /* .. .. ==> 0XF8006024[25:25] = 0x00000000U */
+ /* .. .. ==> MASK : 0x02000000U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_mr_type = 0x0 */
+ /* .. .. ==> 0XF8006024[26:26] = 0x00000000U */
+ /* .. .. ==> MASK : 0x04000000U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_mr_rdata_valid = 0x0 */
+ /* .. .. ==> 0XF8006024[27:27] = 0x00000000U */
+ /* .. .. ==> MASK : 0x08000000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU, 0x0000003CU),
+ /* .. .. reg_ddrc_final_wait_x32 = 0x7 */
+ /* .. .. ==> 0XF8006028[6:0] = 0x00000007U */
+ /* .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U */
+ /* .. .. reg_ddrc_pre_ocd_x32 = 0x0 */
+ /* .. .. ==> 0XF8006028[10:7] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000780U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_t_mrd = 0x4 */
+ /* .. .. ==> 0XF8006028[13:11] = 0x00000004U */
+ /* .. .. ==> MASK : 0x00003800U VAL : 0x00002000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006028, 0x00003FFFU, 0x00002007U),
+ /* .. .. reg_ddrc_emr2 = 0x8 */
+ /* .. .. ==> 0XF800602C[15:0] = 0x00000008U */
+ /* .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U */
+ /* .. .. reg_ddrc_emr3 = 0x0 */
+ /* .. .. ==> 0XF800602C[31:16] = 0x00000000U */
+ /* .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU, 0x00000008U),
+ /* .. .. reg_ddrc_mr = 0x930 */
+ /* .. .. ==> 0XF8006030[15:0] = 0x00000930U */
+ /* .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U */
+ /* .. .. reg_ddrc_emr = 0x4 */
+ /* .. .. ==> 0XF8006030[31:16] = 0x00000004U */
+ /* .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU, 0x00040930U),
+ /* .. .. reg_ddrc_burst_rdwr = 0x4 */
+ /* .. .. ==> 0XF8006034[3:0] = 0x00000004U */
+ /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U */
+ /* .. .. reg_ddrc_pre_cke_x1024 = 0x167 */
+ /* .. .. ==> 0XF8006034[13:4] = 0x00000167U */
+ /* .. .. ==> MASK : 0x00003FF0U VAL : 0x00001670U */
+ /* .. .. reg_ddrc_post_cke_x1024 = 0x1 */
+ /* .. .. ==> 0XF8006034[25:16] = 0x00000001U */
+ /* .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U */
+ /* .. .. reg_ddrc_burstchop = 0x0 */
+ /* .. .. ==> 0XF8006034[28:28] = 0x00000000U */
+ /* .. .. ==> MASK : 0x10000000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x00011674U),
+ /* .. .. reg_ddrc_force_low_pri_n = 0x0 */
+ /* .. .. ==> 0XF8006038[0:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_dis_dq = 0x0 */
+ /* .. .. ==> 0XF8006038[1:1] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. .. reg_phy_debug_mode = 0x0 */
+ /* .. .. ==> 0XF8006038[6:6] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000040U VAL : 0x00000000U */
+ /* .. .. reg_phy_wr_level_start = 0x0 */
+ /* .. .. ==> 0XF8006038[7:7] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000080U VAL : 0x00000000U */
+ /* .. .. reg_phy_rd_level_start = 0x0 */
+ /* .. .. ==> 0XF8006038[8:8] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. .. reg_phy_dq0_wait_t = 0x0 */
+ /* .. .. ==> 0XF8006038[12:9] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006038, 0x00001FC3U, 0x00000000U),
+ /* .. .. reg_ddrc_addrmap_bank_b0 = 0x7 */
+ /* .. .. ==> 0XF800603C[3:0] = 0x00000007U */
+ /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U */
+ /* .. .. reg_ddrc_addrmap_bank_b1 = 0x7 */
+ /* .. .. ==> 0XF800603C[7:4] = 0x00000007U */
+ /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U */
+ /* .. .. reg_ddrc_addrmap_bank_b2 = 0x7 */
+ /* .. .. ==> 0XF800603C[11:8] = 0x00000007U */
+ /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U */
+ /* .. .. reg_ddrc_addrmap_col_b5 = 0x0 */
+ /* .. .. ==> 0XF800603C[15:12] = 0x00000000U */
+ /* .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_addrmap_col_b6 = 0x0 */
+ /* .. .. ==> 0XF800603C[19:16] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU, 0x00000777U),
+ /* .. .. reg_ddrc_addrmap_col_b2 = 0x0 */
+ /* .. .. ==> 0XF8006040[3:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U */
+ /* .. .. reg_ddrc_addrmap_col_b3 = 0x0 */
+ /* .. .. ==> 0XF8006040[7:4] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_addrmap_col_b4 = 0x0 */
+ /* .. .. ==> 0XF8006040[11:8] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_addrmap_col_b7 = 0x0 */
+ /* .. .. ==> 0XF8006040[15:12] = 0x00000000U */
+ /* .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_addrmap_col_b8 = 0x0 */
+ /* .. .. ==> 0XF8006040[19:16] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_addrmap_col_b9 = 0xf */
+ /* .. .. ==> 0XF8006040[23:20] = 0x0000000FU */
+ /* .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U */
+ /* .. .. reg_ddrc_addrmap_col_b10 = 0xf */
+ /* .. .. ==> 0XF8006040[27:24] = 0x0000000FU */
+ /* .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U */
+ /* .. .. reg_ddrc_addrmap_col_b11 = 0xf */
+ /* .. .. ==> 0XF8006040[31:28] = 0x0000000FU */
+ /* .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU, 0xFFF00000U),
+ /* .. .. reg_ddrc_addrmap_row_b0 = 0x6 */
+ /* .. .. ==> 0XF8006044[3:0] = 0x00000006U */
+ /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U */
+ /* .. .. reg_ddrc_addrmap_row_b1 = 0x6 */
+ /* .. .. ==> 0XF8006044[7:4] = 0x00000006U */
+ /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U */
+ /* .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 */
+ /* .. .. ==> 0XF8006044[11:8] = 0x00000006U */
+ /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U */
+ /* .. .. reg_ddrc_addrmap_row_b12 = 0x6 */
+ /* .. .. ==> 0XF8006044[15:12] = 0x00000006U */
+ /* .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U */
+ /* .. .. reg_ddrc_addrmap_row_b13 = 0x6 */
+ /* .. .. ==> 0XF8006044[19:16] = 0x00000006U */
+ /* .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U */
+ /* .. .. reg_ddrc_addrmap_row_b14 = 0xf */
+ /* .. .. ==> 0XF8006044[23:20] = 0x0000000FU */
+ /* .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U */
+ /* .. .. reg_ddrc_addrmap_row_b15 = 0xf */
+ /* .. .. ==> 0XF8006044[27:24] = 0x0000000FU */
+ /* .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU, 0x0FF66666U),
+ /* .. .. reg_ddrc_rank0_rd_odt = 0x0 */
+ /* .. .. ==> 0XF8006048[2:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000007U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_rank0_wr_odt = 0x1 */
+ /* .. .. ==> 0XF8006048[5:3] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000038U VAL : 0x00000008U */
+ /* .. .. reg_ddrc_rank1_rd_odt = 0x1 */
+ /* .. .. ==> 0XF8006048[8:6] = 0x00000001U */
+ /* .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U */
+ /* .. .. reg_ddrc_rank1_wr_odt = 0x1 */
+ /* .. .. ==> 0XF8006048[11:9] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. .. reg_phy_rd_local_odt = 0x0 */
+ /* .. .. ==> 0XF8006048[13:12] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00003000U VAL : 0x00000000U */
+ /* .. .. reg_phy_wr_local_odt = 0x3 */
+ /* .. .. ==> 0XF8006048[15:14] = 0x00000003U */
+ /* .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U */
+ /* .. .. reg_phy_idle_local_odt = 0x3 */
+ /* .. .. ==> 0XF8006048[17:16] = 0x00000003U */
+ /* .. .. ==> MASK : 0x00030000U VAL : 0x00030000U */
+ /* .. .. reg_ddrc_rank2_rd_odt = 0x0 */
+ /* .. .. ==> 0XF8006048[20:18] = 0x00000000U */
+ /* .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_rank2_wr_odt = 0x0 */
+ /* .. .. ==> 0XF8006048[23:21] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_rank3_rd_odt = 0x0 */
+ /* .. .. ==> 0XF8006048[26:24] = 0x00000000U */
+ /* .. .. ==> MASK : 0x07000000U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_rank3_wr_odt = 0x0 */
+ /* .. .. ==> 0XF8006048[29:27] = 0x00000000U */
+ /* .. .. ==> MASK : 0x38000000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU, 0x0003C248U),
+ /* .. .. reg_phy_rd_cmd_to_data = 0x0 */
+ /* .. .. ==> 0XF8006050[3:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U */
+ /* .. .. reg_phy_wr_cmd_to_data = 0x0 */
+ /* .. .. ==> 0XF8006050[7:4] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */
+ /* .. .. reg_phy_rdc_we_to_re_delay = 0x8 */
+ /* .. .. ==> 0XF8006050[11:8] = 0x00000008U */
+ /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U */
+ /* .. .. reg_phy_rdc_fifo_rst_disable = 0x0 */
+ /* .. .. ==> 0XF8006050[15:15] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */
+ /* .. .. reg_phy_use_fixed_re = 0x1 */
+ /* .. .. ==> 0XF8006050[16:16] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00010000U VAL : 0x00010000U */
+ /* .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 */
+ /* .. .. ==> 0XF8006050[17:17] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
+ /* .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 */
+ /* .. .. ==> 0XF8006050[18:18] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
+ /* .. .. reg_phy_clk_stall_level = 0x0 */
+ /* .. .. ==> 0XF8006050[19:19] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */
+ /* .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 */
+ /* .. .. ==> 0XF8006050[27:24] = 0x00000007U */
+ /* .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U */
+ /* .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 */
+ /* .. .. ==> 0XF8006050[31:28] = 0x00000007U */
+ /* .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU, 0x77010800U),
+ /* .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1 */
+ /* .. .. ==> 0XF8006058[7:0] = 0x00000001U */
+ /* .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U */
+ /* .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1 */
+ /* .. .. ==> 0XF8006058[15:8] = 0x00000001U */
+ /* .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U */
+ /* .. .. reg_ddrc_dis_dll_calib = 0x0 */
+ /* .. .. ==> 0XF8006058[16:16] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU, 0x00000101U),
+ /* .. .. reg_ddrc_rd_odt_delay = 0x3 */
+ /* .. .. ==> 0XF800605C[3:0] = 0x00000003U */
+ /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U */
+ /* .. .. reg_ddrc_wr_odt_delay = 0x0 */
+ /* .. .. ==> 0XF800605C[7:4] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_rd_odt_hold = 0x0 */
+ /* .. .. ==> 0XF800605C[11:8] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_wr_odt_hold = 0x5 */
+ /* .. .. ==> 0XF800605C[15:12] = 0x00000005U */
+ /* .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU, 0x00005003U),
+ /* .. .. reg_ddrc_pageclose = 0x0 */
+ /* .. .. ==> 0XF8006060[0:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_lpr_num_entries = 0x1f */
+ /* .. .. ==> 0XF8006060[6:1] = 0x0000001FU */
+ /* .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU */
+ /* .. .. reg_ddrc_auto_pre_en = 0x0 */
+ /* .. .. ==> 0XF8006060[7:7] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000080U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_refresh_update_level = 0x0 */
+ /* .. .. ==> 0XF8006060[8:8] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_dis_wc = 0x0 */
+ /* .. .. ==> 0XF8006060[9:9] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000200U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_dis_collision_page_opt = 0x0 */
+ /* .. .. ==> 0XF8006060[10:10] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_selfref_en = 0x0 */
+ /* .. .. ==> 0XF8006060[12:12] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006060, 0x000017FFU, 0x0000003EU),
+ /* .. .. reg_ddrc_go2critical_hysteresis = 0x0 */
+ /* .. .. ==> 0XF8006064[12:5] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U */
+ /* .. .. reg_arb_go2critical_en = 0x1 */
+ /* .. .. ==> 0XF8006064[17:17] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00020000U VAL : 0x00020000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006064, 0x00021FE0U, 0x00020000U),
+ /* .. .. reg_ddrc_wrlvl_ww = 0x41 */
+ /* .. .. ==> 0XF8006068[7:0] = 0x00000041U */
+ /* .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U */
+ /* .. .. reg_ddrc_rdlvl_rr = 0x41 */
+ /* .. .. ==> 0XF8006068[15:8] = 0x00000041U */
+ /* .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U */
+ /* .. .. reg_ddrc_dfi_t_wlmrd = 0x28 */
+ /* .. .. ==> 0XF8006068[25:16] = 0x00000028U */
+ /* .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU, 0x00284141U),
+ /* .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 */
+ /* .. .. ==> 0XF800606C[7:0] = 0x00000010U */
+ /* .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U */
+ /* .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 */
+ /* .. .. ==> 0XF800606C[15:8] = 0x00000016U */
+ /* .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU, 0x00001610U),
+ /* .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1 */
+ /* .. .. ==> 0XF8006078[3:0] = 0x00000001U */
+ /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U */
+ /* .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1 */
+ /* .. .. ==> 0XF8006078[7:4] = 0x00000001U */
+ /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U */
+ /* .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1 */
+ /* .. .. ==> 0XF8006078[11:8] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U */
+ /* .. .. reg_ddrc_t_cksre = 0x6 */
+ /* .. .. ==> 0XF8006078[15:12] = 0x00000006U */
+ /* .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U */
+ /* .. .. reg_ddrc_t_cksrx = 0x6 */
+ /* .. .. ==> 0XF8006078[19:16] = 0x00000006U */
+ /* .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U */
+ /* .. .. reg_ddrc_t_ckesr = 0x4 */
+ /* .. .. ==> 0XF8006078[25:20] = 0x00000004U */
+ /* .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU, 0x00466111U),
+ /* .. .. reg_ddrc_t_ckpde = 0x2 */
+ /* .. .. ==> 0XF800607C[3:0] = 0x00000002U */
+ /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U */
+ /* .. .. reg_ddrc_t_ckpdx = 0x2 */
+ /* .. .. ==> 0XF800607C[7:4] = 0x00000002U */
+ /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U */
+ /* .. .. reg_ddrc_t_ckdpde = 0x2 */
+ /* .. .. ==> 0XF800607C[11:8] = 0x00000002U */
+ /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */
+ /* .. .. reg_ddrc_t_ckdpdx = 0x2 */
+ /* .. .. ==> 0XF800607C[15:12] = 0x00000002U */
+ /* .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U */
+ /* .. .. reg_ddrc_t_ckcsx = 0x3 */
+ /* .. .. ==> 0XF800607C[19:16] = 0x00000003U */
+ /* .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU, 0x00032222U),
+ /* .. .. refresh_timer0_start_value_x32 = 0x0 */
+ /* .. .. ==> 0XF80060A0[11:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U */
+ /* .. .. refresh_timer1_start_value_x32 = 0x8 */
+ /* .. .. ==> 0XF80060A0[23:12] = 0x00000008U */
+ /* .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU, 0x00008000U),
+ /* .. .. reg_ddrc_dis_auto_zq = 0x0 */
+ /* .. .. ==> 0XF80060A4[0:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_ddr3 = 0x1 */
+ /* .. .. ==> 0XF80060A4[1:1] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. .. reg_ddrc_t_mod = 0x200 */
+ /* .. .. ==> 0XF80060A4[11:2] = 0x00000200U */
+ /* .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U */
+ /* .. .. reg_ddrc_t_zq_long_nop = 0x200 */
+ /* .. .. ==> 0XF80060A4[21:12] = 0x00000200U */
+ /* .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U */
+ /* .. .. reg_ddrc_t_zq_short_nop = 0x40 */
+ /* .. .. ==> 0XF80060A4[31:22] = 0x00000040U */
+ /* .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U),
+ /* .. .. t_zq_short_interval_x1024 = 0xc845 */
+ /* .. .. ==> 0XF80060A8[19:0] = 0x0000C845U */
+ /* .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000C845U */
+ /* .. .. dram_rstn_x1024 = 0x67 */
+ /* .. .. ==> 0XF80060A8[27:20] = 0x00000067U */
+ /* .. .. ==> MASK : 0x0FF00000U VAL : 0x06700000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0670C845U),
+ /* .. .. deeppowerdown_en = 0x0 */
+ /* .. .. ==> 0XF80060AC[0:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. .. deeppowerdown_to_x1024 = 0xff */
+ /* .. .. ==> 0XF80060AC[8:1] = 0x000000FFU */
+ /* .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU),
+ /* .. .. dfi_wrlvl_max_x1024 = 0xfff */
+ /* .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU */
+ /* .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU */
+ /* .. .. dfi_rdlvl_max_x1024 = 0xfff */
+ /* .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU */
+ /* .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U */
+ /* .. .. ddrc_reg_twrlvl_max_error = 0x0 */
+ /* .. .. ==> 0XF80060B0[24:24] = 0x00000000U */
+ /* .. .. ==> MASK : 0x01000000U VAL : 0x00000000U */
+ /* .. .. ddrc_reg_trdlvl_max_error = 0x0 */
+ /* .. .. ==> 0XF80060B0[25:25] = 0x00000000U */
+ /* .. .. ==> MASK : 0x02000000U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_dfi_wr_level_en = 0x1 */
+ /* .. .. ==> 0XF80060B0[26:26] = 0x00000001U */
+ /* .. .. ==> MASK : 0x04000000U VAL : 0x04000000U */
+ /* .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 */
+ /* .. .. ==> 0XF80060B0[27:27] = 0x00000001U */
+ /* .. .. ==> MASK : 0x08000000U VAL : 0x08000000U */
+ /* .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 */
+ /* .. .. ==> 0XF80060B0[28:28] = 0x00000001U */
+ /* .. .. ==> MASK : 0x10000000U VAL : 0x10000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+ /* .. .. reg_ddrc_2t_delay = 0x0 */
+ /* .. .. ==> 0XF80060B4[8:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U */
+ /* .. .. reg_ddrc_skip_ocd = 0x1 */
+ /* .. .. ==> 0XF80060B4[9:9] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000200U VAL : 0x00000200U */
+ /* .. .. reg_ddrc_dis_pre_bypass = 0x0 */
+ /* .. .. ==> 0XF80060B4[10:10] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF80060B4, 0x000007FFU, 0x00000200U),
+ /* .. .. reg_ddrc_dfi_t_rddata_en = 0x6 */
+ /* .. .. ==> 0XF80060B8[4:0] = 0x00000006U */
+ /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U */
+ /* .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 */
+ /* .. .. ==> 0XF80060B8[14:5] = 0x00000003U */
+ /* .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U */
+ /* .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 */
+ /* .. .. ==> 0XF80060B8[24:15] = 0x00000040U */
+ /* .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU, 0x00200066U),
+ /* .. .. START: RESET ECC ERROR */
+ /* .. .. Clear_Uncorrectable_DRAM_ECC_error = 1 */
+ /* .. .. ==> 0XF80060C4[0:0] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. .. Clear_Correctable_DRAM_ECC_error = 1 */
+ /* .. .. ==> 0XF80060C4[1:1] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000003U),
+ /* .. .. FINISH: RESET ECC ERROR */
+ /* .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 */
+ /* .. .. ==> 0XF80060C4[0:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. .. Clear_Correctable_DRAM_ECC_error = 0x0 */
+ /* .. .. ==> 0XF80060C4[1:1] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000000U),
+ /* .. .. CORR_ECC_LOG_VALID = 0x0 */
+ /* .. .. ==> 0XF80060C8[0:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. .. ECC_CORRECTED_BIT_NUM = 0x0 */
+ /* .. .. ==> 0XF80060C8[7:1] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF80060C8, 0x000000FFU, 0x00000000U),
+ /* .. .. UNCORR_ECC_LOG_VALID = 0x0 */
+ /* .. .. ==> 0XF80060DC[0:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF80060DC, 0x00000001U, 0x00000000U),
+ /* .. .. STAT_NUM_CORR_ERR = 0x0 */
+ /* .. .. ==> 0XF80060F0[15:8] = 0x00000000U */
+ /* .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U */
+ /* .. .. STAT_NUM_UNCORR_ERR = 0x0 */
+ /* .. .. ==> 0XF80060F0[7:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU, 0x00000000U),
+ /* .. .. reg_ddrc_ecc_mode = 0x0 */
+ /* .. .. ==> 0XF80060F4[2:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000007U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_dis_scrub = 0x1 */
+ /* .. .. ==> 0XF80060F4[3:3] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000008U VAL : 0x00000008U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF80060F4, 0x0000000FU, 0x00000008U),
+ /* .. .. reg_phy_dif_on = 0x0 */
+ /* .. .. ==> 0XF8006114[3:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U */
+ /* .. .. reg_phy_dif_off = 0x0 */
+ /* .. .. ==> 0XF8006114[7:4] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006114, 0x000000FFU, 0x00000000U),
+ /* .. .. reg_phy_data_slice_in_use = 0x1 */
+ /* .. .. ==> 0XF8006118[0:0] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
+ /* .. .. ==> 0XF8006118[1:1] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
+ /* .. .. ==> 0XF8006118[2:2] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
+ /* .. .. ==> 0XF8006118[3:3] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */
+ /* .. .. reg_phy_board_lpbk_tx = 0x0 */
+ /* .. .. ==> 0XF8006118[4:4] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
+ /* .. .. reg_phy_board_lpbk_rx = 0x0 */
+ /* .. .. ==> 0XF8006118[5:5] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000020U VAL : 0x00000000U */
+ /* .. .. reg_phy_bist_shift_dq = 0x0 */
+ /* .. .. ==> 0XF8006118[14:6] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */
+ /* .. .. reg_phy_bist_err_clr = 0x0 */
+ /* .. .. ==> 0XF8006118[23:15] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */
+ /* .. .. reg_phy_dq_offset = 0x40 */
+ /* .. .. ==> 0XF8006118[30:24] = 0x00000040U */
+ /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU, 0x40000001U),
+ /* .. .. reg_phy_data_slice_in_use = 0x1 */
+ /* .. .. ==> 0XF800611C[0:0] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
+ /* .. .. ==> 0XF800611C[1:1] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
+ /* .. .. ==> 0XF800611C[2:2] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
+ /* .. .. ==> 0XF800611C[3:3] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */
+ /* .. .. reg_phy_board_lpbk_tx = 0x0 */
+ /* .. .. ==> 0XF800611C[4:4] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
+ /* .. .. reg_phy_board_lpbk_rx = 0x0 */
+ /* .. .. ==> 0XF800611C[5:5] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000020U VAL : 0x00000000U */
+ /* .. .. reg_phy_bist_shift_dq = 0x0 */
+ /* .. .. ==> 0XF800611C[14:6] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */
+ /* .. .. reg_phy_bist_err_clr = 0x0 */
+ /* .. .. ==> 0XF800611C[23:15] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */
+ /* .. .. reg_phy_dq_offset = 0x40 */
+ /* .. .. ==> 0XF800611C[30:24] = 0x00000040U */
+ /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU, 0x40000001U),
+ /* .. .. reg_phy_data_slice_in_use = 0x1 */
+ /* .. .. ==> 0XF8006120[0:0] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
+ /* .. .. ==> 0XF8006120[1:1] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
+ /* .. .. ==> 0XF8006120[2:2] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
+ /* .. .. ==> 0XF8006120[3:3] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */
+ /* .. .. reg_phy_board_lpbk_tx = 0x0 */
+ /* .. .. ==> 0XF8006120[4:4] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
+ /* .. .. reg_phy_board_lpbk_rx = 0x0 */
+ /* .. .. ==> 0XF8006120[5:5] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000020U VAL : 0x00000000U */
+ /* .. .. reg_phy_bist_shift_dq = 0x0 */
+ /* .. .. ==> 0XF8006120[14:6] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */
+ /* .. .. reg_phy_bist_err_clr = 0x0 */
+ /* .. .. ==> 0XF8006120[23:15] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */
+ /* .. .. reg_phy_dq_offset = 0x40 */
+ /* .. .. ==> 0XF8006120[30:24] = 0x00000040U */
+ /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */
+ /* .. .. reg_phy_data_slice_in_use = 0x1 */
+ /* .. .. ==> 0XF8006120[0:0] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
+ /* .. .. ==> 0XF8006120[1:1] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
+ /* .. .. ==> 0XF8006120[2:2] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
+ /* .. .. ==> 0XF8006120[3:3] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */
+ /* .. .. reg_phy_board_lpbk_tx = 0x0 */
+ /* .. .. ==> 0XF8006120[4:4] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
+ /* .. .. reg_phy_board_lpbk_rx = 0x0 */
+ /* .. .. ==> 0XF8006120[5:5] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000020U VAL : 0x00000000U */
+ /* .. .. reg_phy_bist_shift_dq = 0x0 */
+ /* .. .. ==> 0XF8006120[14:6] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */
+ /* .. .. reg_phy_bist_err_clr = 0x0 */
+ /* .. .. ==> 0XF8006120[23:15] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */
+ /* .. .. reg_phy_dq_offset = 0x40 */
+ /* .. .. ==> 0XF8006120[30:24] = 0x00000040U */
+ /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU, 0x40000001U),
+ /* .. .. reg_phy_data_slice_in_use = 0x1 */
+ /* .. .. ==> 0XF8006124[0:0] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
+ /* .. .. ==> 0XF8006124[1:1] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
+ /* .. .. ==> 0XF8006124[2:2] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
+ /* .. .. ==> 0XF8006124[3:3] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */
+ /* .. .. reg_phy_board_lpbk_tx = 0x0 */
+ /* .. .. ==> 0XF8006124[4:4] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
+ /* .. .. reg_phy_board_lpbk_rx = 0x0 */
+ /* .. .. ==> 0XF8006124[5:5] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000020U VAL : 0x00000000U */
+ /* .. .. reg_phy_bist_shift_dq = 0x0 */
+ /* .. .. ==> 0XF8006124[14:6] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */
+ /* .. .. reg_phy_bist_err_clr = 0x0 */
+ /* .. .. ==> 0XF8006124[23:15] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */
+ /* .. .. reg_phy_dq_offset = 0x40 */
+ /* .. .. ==> 0XF8006124[30:24] = 0x00000040U */
+ /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU, 0x40000001U),
+ /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
+ /* .. .. ==> 0XF800612C[9:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */
+ /* .. .. reg_phy_gatelvl_init_ratio = 0x8f */
+ /* .. .. ==> 0XF800612C[19:10] = 0x0000008FU */
+ /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00023C00U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU, 0x00023C00U),
+ /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
+ /* .. .. ==> 0XF8006130[9:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */
+ /* .. .. reg_phy_gatelvl_init_ratio = 0x8a */
+ /* .. .. ==> 0XF8006130[19:10] = 0x0000008AU */
+ /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00022800U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU, 0x00022800U),
+ /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
+ /* .. .. ==> 0XF8006134[9:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */
+ /* .. .. reg_phy_gatelvl_init_ratio = 0x8b */
+ /* .. .. ==> 0XF8006134[19:10] = 0x0000008BU */
+ /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00022C00U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU, 0x00022C00U),
+ /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
+ /* .. .. ==> 0XF8006138[9:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */
+ /* .. .. reg_phy_gatelvl_init_ratio = 0x92 */
+ /* .. .. ==> 0XF8006138[19:10] = 0x00000092U */
+ /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00024800U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU, 0x00024800U),
+ /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
+ /* .. .. ==> 0XF8006140[9:0] = 0x00000035U */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */
+ /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
+ /* .. .. ==> 0XF8006140[10:10] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
+ /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
+ /* .. .. ==> 0XF8006140[19:11] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU, 0x00000035U),
+ /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
+ /* .. .. ==> 0XF8006144[9:0] = 0x00000035U */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */
+ /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
+ /* .. .. ==> 0XF8006144[10:10] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
+ /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
+ /* .. .. ==> 0XF8006144[19:11] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU, 0x00000035U),
+ /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
+ /* .. .. ==> 0XF8006148[9:0] = 0x00000035U */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */
+ /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
+ /* .. .. ==> 0XF8006148[10:10] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
+ /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
+ /* .. .. ==> 0XF8006148[19:11] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU, 0x00000035U),
+ /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
+ /* .. .. ==> 0XF800614C[9:0] = 0x00000035U */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */
+ /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
+ /* .. .. ==> 0XF800614C[10:10] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
+ /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
+ /* .. .. ==> 0XF800614C[19:11] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU, 0x00000035U),
+ /* .. .. reg_phy_wr_dqs_slave_ratio = 0x77 */
+ /* .. .. ==> 0XF8006154[9:0] = 0x00000077U */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000077U */
+ /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
+ /* .. .. ==> 0XF8006154[10:10] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
+ /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
+ /* .. .. ==> 0XF8006154[19:11] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU, 0x00000077U),
+ /* .. .. reg_phy_wr_dqs_slave_ratio = 0x7c */
+ /* .. .. ==> 0XF8006158[9:0] = 0x0000007CU */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU */
+ /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
+ /* .. .. ==> 0XF8006158[10:10] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
+ /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
+ /* .. .. ==> 0XF8006158[19:11] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU, 0x0000007CU),
+ /* .. .. reg_phy_wr_dqs_slave_ratio = 0x7c */
+ /* .. .. ==> 0XF800615C[9:0] = 0x0000007CU */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU */
+ /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
+ /* .. .. ==> 0XF800615C[10:10] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
+ /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
+ /* .. .. ==> 0XF800615C[19:11] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU, 0x0000007CU),
+ /* .. .. reg_phy_wr_dqs_slave_ratio = 0x75 */
+ /* .. .. ==> 0XF8006160[9:0] = 0x00000075U */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000075U */
+ /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
+ /* .. .. ==> 0XF8006160[10:10] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
+ /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
+ /* .. .. ==> 0XF8006160[19:11] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU, 0x00000075U),
+ /* .. .. reg_phy_fifo_we_slave_ratio = 0xe4 */
+ /* .. .. ==> 0XF8006168[10:0] = 0x000000E4U */
+ /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000E4U */
+ /* .. .. reg_phy_fifo_we_in_force = 0x0 */
+ /* .. .. ==> 0XF8006168[11:11] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */
+ /* .. .. reg_phy_fifo_we_in_delay = 0x0 */
+ /* .. .. ==> 0XF8006168[20:12] = 0x00000000U */
+ /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU, 0x000000E4U),
+ /* .. .. reg_phy_fifo_we_slave_ratio = 0xdf */
+ /* .. .. ==> 0XF800616C[10:0] = 0x000000DFU */
+ /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000DFU */
+ /* .. .. reg_phy_fifo_we_in_force = 0x0 */
+ /* .. .. ==> 0XF800616C[11:11] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */
+ /* .. .. reg_phy_fifo_we_in_delay = 0x0 */
+ /* .. .. ==> 0XF800616C[20:12] = 0x00000000U */
+ /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU, 0x000000DFU),
+ /* .. .. reg_phy_fifo_we_slave_ratio = 0xe0 */
+ /* .. .. ==> 0XF8006170[10:0] = 0x000000E0U */
+ /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000E0U */
+ /* .. .. reg_phy_fifo_we_in_force = 0x0 */
+ /* .. .. ==> 0XF8006170[11:11] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */
+ /* .. .. reg_phy_fifo_we_in_delay = 0x0 */
+ /* .. .. ==> 0XF8006170[20:12] = 0x00000000U */
+ /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU, 0x000000E0U),
+ /* .. .. reg_phy_fifo_we_slave_ratio = 0xe7 */
+ /* .. .. ==> 0XF8006174[10:0] = 0x000000E7U */
+ /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000E7U */
+ /* .. .. reg_phy_fifo_we_in_force = 0x0 */
+ /* .. .. ==> 0XF8006174[11:11] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */
+ /* .. .. reg_phy_fifo_we_in_delay = 0x0 */
+ /* .. .. ==> 0XF8006174[20:12] = 0x00000000U */
+ /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU, 0x000000E7U),
+ /* .. .. reg_phy_wr_data_slave_ratio = 0xb7 */
+ /* .. .. ==> 0XF800617C[9:0] = 0x000000B7U */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000B7U */
+ /* .. .. reg_phy_wr_data_slave_force = 0x0 */
+ /* .. .. ==> 0XF800617C[10:10] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
+ /* .. .. reg_phy_wr_data_slave_delay = 0x0 */
+ /* .. .. ==> 0XF800617C[19:11] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU, 0x000000B7U),
+ /* .. .. reg_phy_wr_data_slave_ratio = 0xbc */
+ /* .. .. ==> 0XF8006180[9:0] = 0x000000BCU */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU */
+ /* .. .. reg_phy_wr_data_slave_force = 0x0 */
+ /* .. .. ==> 0XF8006180[10:10] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
+ /* .. .. reg_phy_wr_data_slave_delay = 0x0 */
+ /* .. .. ==> 0XF8006180[19:11] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU, 0x000000BCU),
+ /* .. .. reg_phy_wr_data_slave_ratio = 0xbc */
+ /* .. .. ==> 0XF8006184[9:0] = 0x000000BCU */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU */
+ /* .. .. reg_phy_wr_data_slave_force = 0x0 */
+ /* .. .. ==> 0XF8006184[10:10] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
+ /* .. .. reg_phy_wr_data_slave_delay = 0x0 */
+ /* .. .. ==> 0XF8006184[19:11] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU, 0x000000BCU),
+ /* .. .. reg_phy_wr_data_slave_ratio = 0xb5 */
+ /* .. .. ==> 0XF8006188[9:0] = 0x000000B5U */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000B5U */
+ /* .. .. reg_phy_wr_data_slave_force = 0x0 */
+ /* .. .. ==> 0XF8006188[10:10] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
+ /* .. .. reg_phy_wr_data_slave_delay = 0x0 */
+ /* .. .. ==> 0XF8006188[19:11] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU, 0x000000B5U),
+ /* .. .. reg_phy_loopback = 0x0 */
+ /* .. .. ==> 0XF8006190[0:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. .. reg_phy_bl2 = 0x0 */
+ /* .. .. ==> 0XF8006190[1:1] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. .. reg_phy_at_spd_atpg = 0x0 */
+ /* .. .. ==> 0XF8006190[2:2] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. .. reg_phy_bist_enable = 0x0 */
+ /* .. .. ==> 0XF8006190[3:3] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */
+ /* .. .. reg_phy_bist_force_err = 0x0 */
+ /* .. .. ==> 0XF8006190[4:4] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
+ /* .. .. reg_phy_bist_mode = 0x0 */
+ /* .. .. ==> 0XF8006190[6:5] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000060U VAL : 0x00000000U */
+ /* .. .. reg_phy_invert_clkout = 0x1 */
+ /* .. .. ==> 0XF8006190[7:7] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000080U VAL : 0x00000080U */
+ /* .. .. reg_phy_all_dq_mpr_rd_resp = 0x0 */
+ /* .. .. ==> 0XF8006190[8:8] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. .. reg_phy_sel_logic = 0x0 */
+ /* .. .. ==> 0XF8006190[9:9] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000200U VAL : 0x00000000U */
+ /* .. .. reg_phy_ctrl_slave_ratio = 0x100 */
+ /* .. .. ==> 0XF8006190[19:10] = 0x00000100U */
+ /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U */
+ /* .. .. reg_phy_ctrl_slave_force = 0x0 */
+ /* .. .. ==> 0XF8006190[20:20] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00100000U VAL : 0x00000000U */
+ /* .. .. reg_phy_ctrl_slave_delay = 0x0 */
+ /* .. .. ==> 0XF8006190[27:21] = 0x00000000U */
+ /* .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U */
+ /* .. .. reg_phy_use_rank0_delays = 0x1 */
+ /* .. .. ==> 0XF8006190[28:28] = 0x00000001U */
+ /* .. .. ==> MASK : 0x10000000U VAL : 0x10000000U */
+ /* .. .. reg_phy_lpddr = 0x0 */
+ /* .. .. ==> 0XF8006190[29:29] = 0x00000000U */
+ /* .. .. ==> MASK : 0x20000000U VAL : 0x00000000U */
+ /* .. .. reg_phy_cmd_latency = 0x0 */
+ /* .. .. ==> 0XF8006190[30:30] = 0x00000000U */
+ /* .. .. ==> MASK : 0x40000000U VAL : 0x00000000U */
+ /* .. .. reg_phy_int_lpbk = 0x0 */
+ /* .. .. ==> 0XF8006190[31:31] = 0x00000000U */
+ /* .. .. ==> MASK : 0x80000000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU, 0x10040080U),
+ /* .. .. reg_phy_wr_rl_delay = 0x2 */
+ /* .. .. ==> 0XF8006194[4:0] = 0x00000002U */
+ /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U */
+ /* .. .. reg_phy_rd_rl_delay = 0x4 */
+ /* .. .. ==> 0XF8006194[9:5] = 0x00000004U */
+ /* .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U */
+ /* .. .. reg_phy_dll_lock_diff = 0xf */
+ /* .. .. ==> 0XF8006194[13:10] = 0x0000000FU */
+ /* .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U */
+ /* .. .. reg_phy_use_wr_level = 0x1 */
+ /* .. .. ==> 0XF8006194[14:14] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00004000U VAL : 0x00004000U */
+ /* .. .. reg_phy_use_rd_dqs_gate_level = 0x1 */
+ /* .. .. ==> 0XF8006194[15:15] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00008000U VAL : 0x00008000U */
+ /* .. .. reg_phy_use_rd_data_eye_level = 0x1 */
+ /* .. .. ==> 0XF8006194[16:16] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00010000U VAL : 0x00010000U */
+ /* .. .. reg_phy_dis_calib_rst = 0x0 */
+ /* .. .. ==> 0XF8006194[17:17] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
+ /* .. .. reg_phy_ctrl_slave_delay = 0x0 */
+ /* .. .. ==> 0XF8006194[19:18] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU, 0x0001FC82U),
+ /* .. .. reg_arb_page_addr_mask = 0x0 */
+ /* .. .. ==> 0XF8006204[31:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU, 0x00000000U),
+ /* .. .. reg_arb_pri_wr_portn = 0x3ff */
+ /* .. .. ==> 0XF8006208[9:0] = 0x000003FFU */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
+ /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
+ /* .. .. ==> 0XF8006208[16:16] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
+ /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
+ /* .. .. ==> 0XF8006208[17:17] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
+ /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
+ /* .. .. ==> 0XF8006208[18:18] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
+ /* .. .. reg_arb_dis_rmw_portn = 0x1 */
+ /* .. .. ==> 0XF8006208[19:19] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00080000U VAL : 0x00080000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006208, 0x000F03FFU, 0x000803FFU),
+ /* .. .. reg_arb_pri_wr_portn = 0x3ff */
+ /* .. .. ==> 0XF800620C[9:0] = 0x000003FFU */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
+ /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
+ /* .. .. ==> 0XF800620C[16:16] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
+ /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
+ /* .. .. ==> 0XF800620C[17:17] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
+ /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
+ /* .. .. ==> 0XF800620C[18:18] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
+ /* .. .. reg_arb_dis_rmw_portn = 0x1 */
+ /* .. .. ==> 0XF800620C[19:19] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00080000U VAL : 0x00080000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF800620C, 0x000F03FFU, 0x000803FFU),
+ /* .. .. reg_arb_pri_wr_portn = 0x3ff */
+ /* .. .. ==> 0XF8006210[9:0] = 0x000003FFU */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
+ /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
+ /* .. .. ==> 0XF8006210[16:16] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
+ /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
+ /* .. .. ==> 0XF8006210[17:17] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
+ /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
+ /* .. .. ==> 0XF8006210[18:18] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
+ /* .. .. reg_arb_dis_rmw_portn = 0x1 */
+ /* .. .. ==> 0XF8006210[19:19] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00080000U VAL : 0x00080000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006210, 0x000F03FFU, 0x000803FFU),
+ /* .. .. reg_arb_pri_wr_portn = 0x3ff */
+ /* .. .. ==> 0XF8006214[9:0] = 0x000003FFU */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
+ /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
+ /* .. .. ==> 0XF8006214[16:16] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
+ /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
+ /* .. .. ==> 0XF8006214[17:17] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
+ /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
+ /* .. .. ==> 0XF8006214[18:18] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
+ /* .. .. reg_arb_dis_rmw_portn = 0x1 */
+ /* .. .. ==> 0XF8006214[19:19] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00080000U VAL : 0x00080000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006214, 0x000F03FFU, 0x000803FFU),
+ /* .. .. reg_arb_pri_rd_portn = 0x3ff */
+ /* .. .. ==> 0XF8006218[9:0] = 0x000003FFU */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
+ /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
+ /* .. .. ==> 0XF8006218[16:16] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
+ /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
+ /* .. .. ==> 0XF8006218[17:17] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
+ /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
+ /* .. .. ==> 0XF8006218[18:18] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
+ /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
+ /* .. .. ==> 0XF8006218[19:19] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006218, 0x000F03FFU, 0x000003FFU),
+ /* .. .. reg_arb_pri_rd_portn = 0x3ff */
+ /* .. .. ==> 0XF800621C[9:0] = 0x000003FFU */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
+ /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
+ /* .. .. ==> 0XF800621C[16:16] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
+ /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
+ /* .. .. ==> 0XF800621C[17:17] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
+ /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
+ /* .. .. ==> 0XF800621C[18:18] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
+ /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
+ /* .. .. ==> 0XF800621C[19:19] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF800621C, 0x000F03FFU, 0x000003FFU),
+ /* .. .. reg_arb_pri_rd_portn = 0x3ff */
+ /* .. .. ==> 0XF8006220[9:0] = 0x000003FFU */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
+ /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
+ /* .. .. ==> 0XF8006220[16:16] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
+ /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
+ /* .. .. ==> 0XF8006220[17:17] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
+ /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
+ /* .. .. ==> 0XF8006220[18:18] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
+ /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
+ /* .. .. ==> 0XF8006220[19:19] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006220, 0x000F03FFU, 0x000003FFU),
+ /* .. .. reg_arb_pri_rd_portn = 0x3ff */
+ /* .. .. ==> 0XF8006224[9:0] = 0x000003FFU */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
+ /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
+ /* .. .. ==> 0XF8006224[16:16] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
+ /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
+ /* .. .. ==> 0XF8006224[17:17] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
+ /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
+ /* .. .. ==> 0XF8006224[18:18] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
+ /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
+ /* .. .. ==> 0XF8006224[19:19] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006224, 0x000F03FFU, 0x000003FFU),
+ /* .. .. reg_ddrc_lpddr2 = 0x0 */
+ /* .. .. ==> 0XF80062A8[0:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_per_bank_refresh = 0x0 */
+ /* .. .. ==> 0XF80062A8[1:1] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_derate_enable = 0x0 */
+ /* .. .. ==> 0XF80062A8[2:2] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_mr4_margin = 0x0 */
+ /* .. .. ==> 0XF80062A8[11:4] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U, 0x00000000U),
+ /* .. .. reg_ddrc_mr4_read_interval = 0x0 */
+ /* .. .. ==> 0XF80062AC[31:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU, 0x00000000U),
+ /* .. .. reg_ddrc_min_stable_clock_x1 = 0x5 */
+ /* .. .. ==> 0XF80062B0[3:0] = 0x00000005U */
+ /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U */
+ /* .. .. reg_ddrc_idle_after_reset_x32 = 0x12 */
+ /* .. .. ==> 0XF80062B0[11:4] = 0x00000012U */
+ /* .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U */
+ /* .. .. reg_ddrc_t_mrw = 0x5 */
+ /* .. .. ==> 0XF80062B0[21:12] = 0x00000005U */
+ /* .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU, 0x00005125U),
+ /* .. .. reg_ddrc_max_auto_init_x1024 = 0xa6 */
+ /* .. .. ==> 0XF80062B4[7:0] = 0x000000A6U */
+ /* .. .. ==> MASK : 0x000000FFU VAL : 0x000000A6U */
+ /* .. .. reg_ddrc_dev_zqinit_x32 = 0x12 */
+ /* .. .. ==> 0XF80062B4[17:8] = 0x00000012U */
+ /* .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU, 0x000012A6U),
+ /* .. .. START: POLL ON DCI STATUS */
+ /* .. .. DONE = 1 */
+ /* .. .. ==> 0XF8000B74[13:13] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00002000U VAL : 0x00002000U */
+ /* .. .. */
+ EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+ /* .. .. FINISH: POLL ON DCI STATUS */
+ /* .. .. START: UNLOCK DDR */
+ /* .. .. reg_ddrc_soft_rstb = 0x1 */
+ /* .. .. ==> 0XF8006000[0:0] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. .. reg_ddrc_powerdown_en = 0x0 */
+ /* .. .. ==> 0XF8006000[1:1] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_data_bus_width = 0x0 */
+ /* .. .. ==> 0XF8006000[3:2] = 0x00000000U */
+ /* .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U */
+ /* .. .. reg_ddrc_burst8_refresh = 0x0 */
+ /* .. .. ==> 0XF8006000[6:4] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000070U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_rdwr_idle_gap = 1 */
+ /* .. .. ==> 0XF8006000[13:7] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U */
+ /* .. .. reg_ddrc_dis_rd_bypass = 0x0 */
+ /* .. .. ==> 0XF8006000[14:14] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00004000U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_dis_act_bypass = 0x0 */
+ /* .. .. ==> 0XF8006000[15:15] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_dis_auto_refresh = 0x0 */
+ /* .. .. ==> 0XF8006000[16:16] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000081U),
+ /* .. .. FINISH: UNLOCK DDR */
+ /* .. .. START: CHECK DDR STATUS */
+ /* .. .. ddrc_reg_operating_mode = 1 */
+ /* .. .. ==> 0XF8006054[2:0] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000007U VAL : 0x00000001U */
+ /* .. .. */
+ EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+ /* .. .. FINISH: CHECK DDR STATUS */
+ /* .. FINISH: DDR INITIALIZATION */
+ /* FINISH: top */
+ /* */
+ EMIT_EXIT(),
+
+ /* */
+};
+
+unsigned long ps7_mio_init_data_2_0[] = {
+ /* START: top */
+ /* .. START: SLCR SETTINGS */
+ /* .. UNLOCK_KEY = 0XDF0D */
+ /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
+ /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ /* .. FINISH: SLCR SETTINGS */
+ /* .. START: OCM REMAPPING */
+ /* .. VREF_EN = 0x1 */
+ /* .. ==> 0XF8000B00[0:0] = 0x00000001U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. VREF_PULLUP_EN = 0x0 */
+ /* .. ==> 0XF8000B00[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. CLK_PULLUP_EN = 0x0 */
+ /* .. ==> 0XF8000B00[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. SRSTN_PULLUP_EN = 0x0 */
+ /* .. ==> 0XF8000B00[9:9] = 0x00000000U */
+ /* .. ==> MASK : 0x00000200U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000B00, 0x00000303U, 0x00000001U),
+ /* .. FINISH: OCM REMAPPING */
+ /* .. START: DDRIOB SETTINGS */
+ /* .. INP_POWER = 0x0 */
+ /* .. ==> 0XF8000B40[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. INP_TYPE = 0x0 */
+ /* .. ==> 0XF8000B40[2:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */
+ /* .. DCI_UPDATE = 0x0 */
+ /* .. ==> 0XF8000B40[3:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
+ /* .. TERM_EN = 0x0 */
+ /* .. ==> 0XF8000B40[4:4] = 0x00000000U */
+ /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */
+ /* .. DCR_TYPE = 0x0 */
+ /* .. ==> 0XF8000B40[6:5] = 0x00000000U */
+ /* .. ==> MASK : 0x00000060U VAL : 0x00000000U */
+ /* .. IBUF_DISABLE_MODE = 0x0 */
+ /* .. ==> 0XF8000B40[7:7] = 0x00000000U */
+ /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
+ /* .. TERM_DISABLE_MODE = 0x0 */
+ /* .. ==> 0XF8000B40[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. OUTPUT_EN = 0x3 */
+ /* .. ==> 0XF8000B40[10:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
+ /* .. PULLUP_EN = 0x0 */
+ /* .. ==> 0XF8000B40[11:11] = 0x00000000U */
+ /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU, 0x00000600U),
+ /* .. INP_POWER = 0x0 */
+ /* .. ==> 0XF8000B44[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. INP_TYPE = 0x0 */
+ /* .. ==> 0XF8000B44[2:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */
+ /* .. DCI_UPDATE = 0x0 */
+ /* .. ==> 0XF8000B44[3:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
+ /* .. TERM_EN = 0x0 */
+ /* .. ==> 0XF8000B44[4:4] = 0x00000000U */
+ /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */
+ /* .. DCR_TYPE = 0x0 */
+ /* .. ==> 0XF8000B44[6:5] = 0x00000000U */
+ /* .. ==> MASK : 0x00000060U VAL : 0x00000000U */
+ /* .. IBUF_DISABLE_MODE = 0x0 */
+ /* .. ==> 0XF8000B44[7:7] = 0x00000000U */
+ /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
+ /* .. TERM_DISABLE_MODE = 0x0 */
+ /* .. ==> 0XF8000B44[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. OUTPUT_EN = 0x3 */
+ /* .. ==> 0XF8000B44[10:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
+ /* .. PULLUP_EN = 0x0 */
+ /* .. ==> 0XF8000B44[11:11] = 0x00000000U */
+ /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU, 0x00000600U),
+ /* .. INP_POWER = 0x0 */
+ /* .. ==> 0XF8000B48[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. INP_TYPE = 0x1 */
+ /* .. ==> 0XF8000B48[2:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000006U VAL : 0x00000002U */
+ /* .. DCI_UPDATE = 0x0 */
+ /* .. ==> 0XF8000B48[3:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
+ /* .. TERM_EN = 0x1 */
+ /* .. ==> 0XF8000B48[4:4] = 0x00000001U */
+ /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */
+ /* .. DCR_TYPE = 0x3 */
+ /* .. ==> 0XF8000B48[6:5] = 0x00000003U */
+ /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */
+ /* .. IBUF_DISABLE_MODE = 0 */
+ /* .. ==> 0XF8000B48[7:7] = 0x00000000U */
+ /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
+ /* .. TERM_DISABLE_MODE = 0 */
+ /* .. ==> 0XF8000B48[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. OUTPUT_EN = 0x3 */
+ /* .. ==> 0XF8000B48[10:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
+ /* .. PULLUP_EN = 0x0 */
+ /* .. ==> 0XF8000B48[11:11] = 0x00000000U */
+ /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU, 0x00000672U),
+ /* .. INP_POWER = 0x0 */
+ /* .. ==> 0XF8000B4C[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. INP_TYPE = 0x1 */
+ /* .. ==> 0XF8000B4C[2:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000006U VAL : 0x00000002U */
+ /* .. DCI_UPDATE = 0x0 */
+ /* .. ==> 0XF8000B4C[3:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
+ /* .. TERM_EN = 0x1 */
+ /* .. ==> 0XF8000B4C[4:4] = 0x00000001U */
+ /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */
+ /* .. DCR_TYPE = 0x3 */
+ /* .. ==> 0XF8000B4C[6:5] = 0x00000003U */
+ /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */
+ /* .. IBUF_DISABLE_MODE = 0 */
+ /* .. ==> 0XF8000B4C[7:7] = 0x00000000U */
+ /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
+ /* .. TERM_DISABLE_MODE = 0 */
+ /* .. ==> 0XF8000B4C[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. OUTPUT_EN = 0x3 */
+ /* .. ==> 0XF8000B4C[10:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
+ /* .. PULLUP_EN = 0x0 */
+ /* .. ==> 0XF8000B4C[11:11] = 0x00000000U */
+ /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU, 0x00000672U),
+ /* .. INP_POWER = 0x0 */
+ /* .. ==> 0XF8000B50[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. INP_TYPE = 0x2 */
+ /* .. ==> 0XF8000B50[2:1] = 0x00000002U */
+ /* .. ==> MASK : 0x00000006U VAL : 0x00000004U */
+ /* .. DCI_UPDATE = 0x0 */
+ /* .. ==> 0XF8000B50[3:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
+ /* .. TERM_EN = 0x1 */
+ /* .. ==> 0XF8000B50[4:4] = 0x00000001U */
+ /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */
+ /* .. DCR_TYPE = 0x3 */
+ /* .. ==> 0XF8000B50[6:5] = 0x00000003U */
+ /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */
+ /* .. IBUF_DISABLE_MODE = 0 */
+ /* .. ==> 0XF8000B50[7:7] = 0x00000000U */
+ /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
+ /* .. TERM_DISABLE_MODE = 0 */
+ /* .. ==> 0XF8000B50[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. OUTPUT_EN = 0x3 */
+ /* .. ==> 0XF8000B50[10:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
+ /* .. PULLUP_EN = 0x0 */
+ /* .. ==> 0XF8000B50[11:11] = 0x00000000U */
+ /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU, 0x00000674U),
+ /* .. INP_POWER = 0x0 */
+ /* .. ==> 0XF8000B54[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. INP_TYPE = 0x2 */
+ /* .. ==> 0XF8000B54[2:1] = 0x00000002U */
+ /* .. ==> MASK : 0x00000006U VAL : 0x00000004U */
+ /* .. DCI_UPDATE = 0x0 */
+ /* .. ==> 0XF8000B54[3:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
+ /* .. TERM_EN = 0x1 */
+ /* .. ==> 0XF8000B54[4:4] = 0x00000001U */
+ /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */
+ /* .. DCR_TYPE = 0x3 */
+ /* .. ==> 0XF8000B54[6:5] = 0x00000003U */
+ /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */
+ /* .. IBUF_DISABLE_MODE = 0 */
+ /* .. ==> 0XF8000B54[7:7] = 0x00000000U */
+ /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
+ /* .. TERM_DISABLE_MODE = 0 */
+ /* .. ==> 0XF8000B54[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. OUTPUT_EN = 0x3 */
+ /* .. ==> 0XF8000B54[10:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
+ /* .. PULLUP_EN = 0x0 */
+ /* .. ==> 0XF8000B54[11:11] = 0x00000000U */
+ /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU, 0x00000674U),
+ /* .. INP_POWER = 0x0 */
+ /* .. ==> 0XF8000B58[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. INP_TYPE = 0x0 */
+ /* .. ==> 0XF8000B58[2:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */
+ /* .. DCI_UPDATE = 0x0 */
+ /* .. ==> 0XF8000B58[3:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
+ /* .. TERM_EN = 0x0 */
+ /* .. ==> 0XF8000B58[4:4] = 0x00000000U */
+ /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */
+ /* .. DCR_TYPE = 0x0 */
+ /* .. ==> 0XF8000B58[6:5] = 0x00000000U */
+ /* .. ==> MASK : 0x00000060U VAL : 0x00000000U */
+ /* .. IBUF_DISABLE_MODE = 0x0 */
+ /* .. ==> 0XF8000B58[7:7] = 0x00000000U */
+ /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
+ /* .. TERM_DISABLE_MODE = 0x0 */
+ /* .. ==> 0XF8000B58[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. OUTPUT_EN = 0x3 */
+ /* .. ==> 0XF8000B58[10:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
+ /* .. PULLUP_EN = 0x0 */
+ /* .. ==> 0XF8000B58[11:11] = 0x00000000U */
+ /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU, 0x00000600U),
+ /* .. DRIVE_P = 0x1c */
+ /* .. ==> 0XF8000B5C[6:0] = 0x0000001CU */
+ /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */
+ /* .. DRIVE_N = 0xc */
+ /* .. ==> 0XF8000B5C[13:7] = 0x0000000CU */
+ /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */
+ /* .. SLEW_P = 0x3 */
+ /* .. ==> 0XF8000B5C[18:14] = 0x00000003U */
+ /* .. ==> MASK : 0x0007C000U VAL : 0x0000C000U */
+ /* .. SLEW_N = 0x3 */
+ /* .. ==> 0XF8000B5C[23:19] = 0x00000003U */
+ /* .. ==> MASK : 0x00F80000U VAL : 0x00180000U */
+ /* .. GTL = 0x0 */
+ /* .. ==> 0XF8000B5C[26:24] = 0x00000000U */
+ /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */
+ /* .. RTERM = 0x0 */
+ /* .. ==> 0XF8000B5C[31:27] = 0x00000000U */
+ /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU, 0x0018C61CU),
+ /* .. DRIVE_P = 0x1c */
+ /* .. ==> 0XF8000B60[6:0] = 0x0000001CU */
+ /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */
+ /* .. DRIVE_N = 0xc */
+ /* .. ==> 0XF8000B60[13:7] = 0x0000000CU */
+ /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */
+ /* .. SLEW_P = 0x6 */
+ /* .. ==> 0XF8000B60[18:14] = 0x00000006U */
+ /* .. ==> MASK : 0x0007C000U VAL : 0x00018000U */
+ /* .. SLEW_N = 0x1f */
+ /* .. ==> 0XF8000B60[23:19] = 0x0000001FU */
+ /* .. ==> MASK : 0x00F80000U VAL : 0x00F80000U */
+ /* .. GTL = 0x0 */
+ /* .. ==> 0XF8000B60[26:24] = 0x00000000U */
+ /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */
+ /* .. RTERM = 0x0 */
+ /* .. ==> 0XF8000B60[31:27] = 0x00000000U */
+ /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU, 0x00F9861CU),
+ /* .. DRIVE_P = 0x1c */
+ /* .. ==> 0XF8000B64[6:0] = 0x0000001CU */
+ /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */
+ /* .. DRIVE_N = 0xc */
+ /* .. ==> 0XF8000B64[13:7] = 0x0000000CU */
+ /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */
+ /* .. SLEW_P = 0x6 */
+ /* .. ==> 0XF8000B64[18:14] = 0x00000006U */
+ /* .. ==> MASK : 0x0007C000U VAL : 0x00018000U */
+ /* .. SLEW_N = 0x1f */
+ /* .. ==> 0XF8000B64[23:19] = 0x0000001FU */
+ /* .. ==> MASK : 0x00F80000U VAL : 0x00F80000U */
+ /* .. GTL = 0x0 */
+ /* .. ==> 0XF8000B64[26:24] = 0x00000000U */
+ /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */
+ /* .. RTERM = 0x0 */
+ /* .. ==> 0XF8000B64[31:27] = 0x00000000U */
+ /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU, 0x00F9861CU),
+ /* .. DRIVE_P = 0x1c */
+ /* .. ==> 0XF8000B68[6:0] = 0x0000001CU */
+ /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */
+ /* .. DRIVE_N = 0xc */
+ /* .. ==> 0XF8000B68[13:7] = 0x0000000CU */
+ /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */
+ /* .. SLEW_P = 0x6 */
+ /* .. ==> 0XF8000B68[18:14] = 0x00000006U */
+ /* .. ==> MASK : 0x0007C000U VAL : 0x00018000U */
+ /* .. SLEW_N = 0x1f */
+ /* .. ==> 0XF8000B68[23:19] = 0x0000001FU */
+ /* .. ==> MASK : 0x00F80000U VAL : 0x00F80000U */
+ /* .. GTL = 0x0 */
+ /* .. ==> 0XF8000B68[26:24] = 0x00000000U */
+ /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */
+ /* .. RTERM = 0x0 */
+ /* .. ==> 0XF8000B68[31:27] = 0x00000000U */
+ /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU, 0x00F9861CU),
+ /* .. VREF_INT_EN = 0x0 */
+ /* .. ==> 0XF8000B6C[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. VREF_SEL = 0x0 */
+ /* .. ==> 0XF8000B6C[4:1] = 0x00000000U */
+ /* .. ==> MASK : 0x0000001EU VAL : 0x00000000U */
+ /* .. VREF_EXT_EN = 0x3 */
+ /* .. ==> 0XF8000B6C[6:5] = 0x00000003U */
+ /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */
+ /* .. VREF_PULLUP_EN = 0x0 */
+ /* .. ==> 0XF8000B6C[8:7] = 0x00000000U */
+ /* .. ==> MASK : 0x00000180U VAL : 0x00000000U */
+ /* .. REFIO_EN = 0x1 */
+ /* .. ==> 0XF8000B6C[9:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000200U VAL : 0x00000200U */
+ /* .. REFIO_TEST = 0x0 */
+ /* .. ==> 0XF8000B6C[11:10] = 0x00000000U */
+ /* .. ==> MASK : 0x00000C00U VAL : 0x00000000U */
+ /* .. REFIO_PULLUP_EN = 0x0 */
+ /* .. ==> 0XF8000B6C[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DRST_B_PULLUP_EN = 0x0 */
+ /* .. ==> 0XF8000B6C[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. CKE_PULLUP_EN = 0x0 */
+ /* .. ==> 0XF8000B6C[14:14] = 0x00000000U */
+ /* .. ==> MASK : 0x00004000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU, 0x00000260U),
+ /* .. .. START: ASSERT RESET */
+ /* .. .. RESET = 1 */
+ /* .. .. ==> 0XF8000B70[0:0] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. .. VRN_OUT = 0x1 */
+ /* .. .. ==> 0XF8000B70[5:5] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000020U VAL : 0x00000020U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000021U),
+ /* .. .. FINISH: ASSERT RESET */
+ /* .. .. START: DEASSERT RESET */
+ /* .. .. RESET = 0 */
+ /* .. .. ==> 0XF8000B70[0:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. .. VRN_OUT = 0x1 */
+ /* .. .. ==> 0XF8000B70[5:5] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000020U VAL : 0x00000020U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000020U),
+ /* .. .. FINISH: DEASSERT RESET */
+ /* .. .. RESET = 0x1 */
+ /* .. .. ==> 0XF8000B70[0:0] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. .. ENABLE = 0x1 */
+ /* .. .. ==> 0XF8000B70[1:1] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. .. VRP_TRI = 0x0 */
+ /* .. .. ==> 0XF8000B70[2:2] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. .. VRN_TRI = 0x0 */
+ /* .. .. ==> 0XF8000B70[3:3] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */
+ /* .. .. VRP_OUT = 0x0 */
+ /* .. .. ==> 0XF8000B70[4:4] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
+ /* .. .. VRN_OUT = 0x1 */
+ /* .. .. ==> 0XF8000B70[5:5] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000020U VAL : 0x00000020U */
+ /* .. .. NREF_OPT1 = 0x0 */
+ /* .. .. ==> 0XF8000B70[7:6] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U */
+ /* .. .. NREF_OPT2 = 0x0 */
+ /* .. .. ==> 0XF8000B70[10:8] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000700U VAL : 0x00000000U */
+ /* .. .. NREF_OPT4 = 0x1 */
+ /* .. .. ==> 0XF8000B70[13:11] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00003800U VAL : 0x00000800U */
+ /* .. .. PREF_OPT1 = 0x0 */
+ /* .. .. ==> 0XF8000B70[16:14] = 0x00000000U */
+ /* .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U */
+ /* .. .. PREF_OPT2 = 0x0 */
+ /* .. .. ==> 0XF8000B70[19:17] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U */
+ /* .. .. UPDATE_CONTROL = 0x0 */
+ /* .. .. ==> 0XF8000B70[20:20] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00100000U VAL : 0x00000000U */
+ /* .. .. INIT_COMPLETE = 0x0 */
+ /* .. .. ==> 0XF8000B70[21:21] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00200000U VAL : 0x00000000U */
+ /* .. .. TST_CLK = 0x0 */
+ /* .. .. ==> 0XF8000B70[22:22] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00400000U VAL : 0x00000000U */
+ /* .. .. TST_HLN = 0x0 */
+ /* .. .. ==> 0XF8000B70[23:23] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00800000U VAL : 0x00000000U */
+ /* .. .. TST_HLP = 0x0 */
+ /* .. .. ==> 0XF8000B70[24:24] = 0x00000000U */
+ /* .. .. ==> MASK : 0x01000000U VAL : 0x00000000U */
+ /* .. .. TST_RST = 0x0 */
+ /* .. .. ==> 0XF8000B70[25:25] = 0x00000000U */
+ /* .. .. ==> MASK : 0x02000000U VAL : 0x00000000U */
+ /* .. .. INT_DCI_EN = 0x0 */
+ /* .. .. ==> 0XF8000B70[26:26] = 0x00000000U */
+ /* .. .. ==> MASK : 0x04000000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU, 0x00000823U),
+ /* .. FINISH: DDRIOB SETTINGS */
+ /* .. START: MIO PROGRAMMING */
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000700[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF8000700[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000700[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000700[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000700[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF8000700[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF8000700[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 1 */
+ /* .. ==> 0XF8000700[12:12] = 0x00000001U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000700[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000700, 0x00003FFFU, 0x00001600U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000704[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF8000704[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000704[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000704[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000704[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000704[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF8000704[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000704[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000704[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000704, 0x00003FFFU, 0x00000702U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000708[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF8000708[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000708[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000708[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000708[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000708[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF8000708[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000708[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000708[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000708, 0x00003FFFU, 0x00000702U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF800070C[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF800070C[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF800070C[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF800070C[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF800070C[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF800070C[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF800070C[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF800070C[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF800070C[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF800070C, 0x00003FFFU, 0x00000702U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000710[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF8000710[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000710[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000710[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000710[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000710[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF8000710[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000710[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000710[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000710, 0x00003FFFU, 0x00000702U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000714[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF8000714[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000714[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000714[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000714[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000714[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF8000714[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000714[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000714[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000714, 0x00003FFFU, 0x00000702U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000718[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF8000718[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000718[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000718[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000718[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000718[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF8000718[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000718[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000718[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000702U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF800071C[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF800071C[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF800071C[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF800071C[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF800071C[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF800071C[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF800071C[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF800071C[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF800071C[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF800071C, 0x00003FFFU, 0x00000600U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000720[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF8000720[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000720[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000720[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000720[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000720[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF8000720[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000720[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000720[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000720, 0x00003FFFU, 0x00000702U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000724[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF8000724[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000724[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000724[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000724[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF8000724[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF8000724[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 1 */
+ /* .. ==> 0XF8000724[12:12] = 0x00000001U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000724[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000724, 0x00003FFFU, 0x00001600U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000728[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF8000728[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000728[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000728[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000728[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF8000728[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF8000728[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 1 */
+ /* .. ==> 0XF8000728[12:12] = 0x00000001U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000728[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000728, 0x00003FFFU, 0x00001600U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF800072C[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF800072C[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF800072C[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF800072C[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF800072C[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF800072C[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF800072C[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 1 */
+ /* .. ==> 0XF800072C[12:12] = 0x00000001U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF800072C[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF800072C, 0x00003FFFU, 0x00001600U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000730[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF8000730[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000730[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000730[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000730[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF8000730[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF8000730[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 1 */
+ /* .. ==> 0XF8000730[12:12] = 0x00000001U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000730[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000730, 0x00003FFFU, 0x00001600U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000734[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF8000734[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000734[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000734[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000734[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF8000734[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF8000734[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 1 */
+ /* .. ==> 0XF8000734[12:12] = 0x00000001U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000734[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000734, 0x00003FFFU, 0x00001600U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000738[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF8000738[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000738[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000738[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000738[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF8000738[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF8000738[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 1 */
+ /* .. ==> 0XF8000738[12:12] = 0x00000001U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000738[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000738, 0x00003FFFU, 0x00001600U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF800073C[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF800073C[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF800073C[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF800073C[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF800073C[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF800073C[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF800073C[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 1 */
+ /* .. ==> 0XF800073C[12:12] = 0x00000001U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF800073C[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF800073C, 0x00003FFFU, 0x00001600U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000740[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF8000740[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000740[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000740[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000740[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000740[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 4 */
+ /* .. ==> 0XF8000740[11:9] = 0x00000004U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000740[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 1 */
+ /* .. ==> 0XF8000740[13:13] = 0x00000001U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000740, 0x00003FFFU, 0x00002902U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000744[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF8000744[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000744[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000744[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000744[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000744[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 4 */
+ /* .. ==> 0XF8000744[11:9] = 0x00000004U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000744[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 1 */
+ /* .. ==> 0XF8000744[13:13] = 0x00000001U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000744, 0x00003FFFU, 0x00002902U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000748[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF8000748[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000748[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000748[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000748[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000748[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 4 */
+ /* .. ==> 0XF8000748[11:9] = 0x00000004U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000748[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 1 */
+ /* .. ==> 0XF8000748[13:13] = 0x00000001U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000748, 0x00003FFFU, 0x00002902U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF800074C[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF800074C[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF800074C[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF800074C[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF800074C[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF800074C[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 4 */
+ /* .. ==> 0XF800074C[11:9] = 0x00000004U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF800074C[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 1 */
+ /* .. ==> 0XF800074C[13:13] = 0x00000001U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF800074C, 0x00003FFFU, 0x00002902U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000750[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF8000750[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000750[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000750[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000750[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000750[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 4 */
+ /* .. ==> 0XF8000750[11:9] = 0x00000004U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000750[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 1 */
+ /* .. ==> 0XF8000750[13:13] = 0x00000001U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000750, 0x00003FFFU, 0x00002902U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000754[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF8000754[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000754[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000754[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000754[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000754[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 4 */
+ /* .. ==> 0XF8000754[11:9] = 0x00000004U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000754[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 1 */
+ /* .. ==> 0XF8000754[13:13] = 0x00000001U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000754, 0x00003FFFU, 0x00002902U),
+ /* .. TRI_ENABLE = 1 */
+ /* .. ==> 0XF8000758[0:0] = 0x00000001U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF8000758[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000758[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000758[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000758[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000758[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 4 */
+ /* .. ==> 0XF8000758[11:9] = 0x00000004U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000758[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000758[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000758, 0x00003FFFU, 0x00000903U),
+ /* .. TRI_ENABLE = 1 */
+ /* .. ==> 0XF800075C[0:0] = 0x00000001U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF800075C[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF800075C[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF800075C[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF800075C[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF800075C[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 4 */
+ /* .. ==> 0XF800075C[11:9] = 0x00000004U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF800075C[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF800075C[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF800075C, 0x00003FFFU, 0x00000903U),
+ /* .. TRI_ENABLE = 1 */
+ /* .. ==> 0XF8000760[0:0] = 0x00000001U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF8000760[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000760[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000760[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000760[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000760[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 4 */
+ /* .. ==> 0XF8000760[11:9] = 0x00000004U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000760[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000760[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000760, 0x00003FFFU, 0x00000903U),
+ /* .. TRI_ENABLE = 1 */
+ /* .. ==> 0XF8000764[0:0] = 0x00000001U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF8000764[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000764[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000764[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000764[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000764[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 4 */
+ /* .. ==> 0XF8000764[11:9] = 0x00000004U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000764[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000764[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000764, 0x00003FFFU, 0x00000903U),
+ /* .. TRI_ENABLE = 1 */
+ /* .. ==> 0XF8000768[0:0] = 0x00000001U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF8000768[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000768[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000768[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000768[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000768[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 4 */
+ /* .. ==> 0XF8000768[11:9] = 0x00000004U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000768[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000768[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000768, 0x00003FFFU, 0x00000903U),
+ /* .. TRI_ENABLE = 1 */
+ /* .. ==> 0XF800076C[0:0] = 0x00000001U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF800076C[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF800076C[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF800076C[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF800076C[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF800076C[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 4 */
+ /* .. ==> 0XF800076C[11:9] = 0x00000004U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF800076C[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF800076C[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF800076C, 0x00003FFFU, 0x00000903U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000770[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF8000770[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 1 */
+ /* .. ==> 0XF8000770[2:2] = 0x00000001U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000770[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000770[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000770[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF8000770[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000770[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000770[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000770, 0x00003FFFU, 0x00000304U),
+ /* .. TRI_ENABLE = 1 */
+ /* .. ==> 0XF8000774[0:0] = 0x00000001U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF8000774[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 1 */
+ /* .. ==> 0XF8000774[2:2] = 0x00000001U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000774[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000774[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000774[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF8000774[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000774[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000774[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000774, 0x00003FFFU, 0x00000305U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000778[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF8000778[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 1 */
+ /* .. ==> 0XF8000778[2:2] = 0x00000001U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000778[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000778[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000778[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF8000778[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000778[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000778[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000778, 0x00003FFFU, 0x00000304U),
+ /* .. TRI_ENABLE = 1 */
+ /* .. ==> 0XF800077C[0:0] = 0x00000001U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF800077C[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 1 */
+ /* .. ==> 0XF800077C[2:2] = 0x00000001U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF800077C[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF800077C[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF800077C[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF800077C[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF800077C[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF800077C[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF800077C, 0x00003FFFU, 0x00000305U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000780[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF8000780[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 1 */
+ /* .. ==> 0XF8000780[2:2] = 0x00000001U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000780[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000780[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000780[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF8000780[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000780[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000780[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000780, 0x00003FFFU, 0x00000304U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000784[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF8000784[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 1 */
+ /* .. ==> 0XF8000784[2:2] = 0x00000001U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000784[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000784[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000784[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF8000784[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000784[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000784[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000784, 0x00003FFFU, 0x00000304U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000788[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF8000788[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 1 */
+ /* .. ==> 0XF8000788[2:2] = 0x00000001U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000788[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000788[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000788[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF8000788[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000788[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000788[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000788, 0x00003FFFU, 0x00000304U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF800078C[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF800078C[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 1 */
+ /* .. ==> 0XF800078C[2:2] = 0x00000001U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF800078C[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF800078C[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF800078C[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF800078C[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF800078C[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF800078C[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF800078C, 0x00003FFFU, 0x00000304U),
+ /* .. TRI_ENABLE = 1 */
+ /* .. ==> 0XF8000790[0:0] = 0x00000001U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF8000790[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 1 */
+ /* .. ==> 0XF8000790[2:2] = 0x00000001U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000790[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000790[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000790[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF8000790[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000790[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000790[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000790, 0x00003FFFU, 0x00000305U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000794[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF8000794[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 1 */
+ /* .. ==> 0XF8000794[2:2] = 0x00000001U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000794[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000794[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000794[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF8000794[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000794[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000794[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000794, 0x00003FFFU, 0x00000304U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000798[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF8000798[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 1 */
+ /* .. ==> 0XF8000798[2:2] = 0x00000001U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000798[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000798[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000798[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF8000798[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000798[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000798[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000798, 0x00003FFFU, 0x00000304U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF800079C[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF800079C[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 1 */
+ /* .. ==> 0XF800079C[2:2] = 0x00000001U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF800079C[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF800079C[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF800079C[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF800079C[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF800079C[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF800079C[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF800079C, 0x00003FFFU, 0x00000304U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF80007A0[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF80007A0[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF80007A0[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF80007A0[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 4 */
+ /* .. ==> 0XF80007A0[7:5] = 0x00000004U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF80007A0[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF80007A0[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF80007A0[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF80007A0[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU, 0x00000380U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF80007A4[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF80007A4[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF80007A4[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF80007A4[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 4 */
+ /* .. ==> 0XF80007A4[7:5] = 0x00000004U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF80007A4[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF80007A4[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF80007A4[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF80007A4[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU, 0x00000380U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF80007A8[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF80007A8[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF80007A8[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF80007A8[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 4 */
+ /* .. ==> 0XF80007A8[7:5] = 0x00000004U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF80007A8[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF80007A8[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF80007A8[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF80007A8[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU, 0x00000380U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF80007AC[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF80007AC[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF80007AC[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF80007AC[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 4 */
+ /* .. ==> 0XF80007AC[7:5] = 0x00000004U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF80007AC[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF80007AC[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF80007AC[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF80007AC[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU, 0x00000380U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF80007B0[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF80007B0[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF80007B0[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF80007B0[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 4 */
+ /* .. ==> 0XF80007B0[7:5] = 0x00000004U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF80007B0[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF80007B0[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF80007B0[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF80007B0[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU, 0x00000380U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF80007B4[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF80007B4[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF80007B4[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF80007B4[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 4 */
+ /* .. ==> 0XF80007B4[7:5] = 0x00000004U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF80007B4[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF80007B4[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF80007B4[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF80007B4[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00000380U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF80007B8[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF80007B8[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF80007B8[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF80007B8[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF80007B8[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF80007B8[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF80007B8[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 1 */
+ /* .. ==> 0XF80007B8[12:12] = 0x00000001U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF80007B8[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU, 0x00001200U),
+ /* .. TRI_ENABLE = 1 */
+ /* .. ==> 0XF80007BC[0:0] = 0x00000001U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF80007BC[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF80007BC[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF80007BC[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF80007BC[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF80007BC, 0x00003F01U, 0x00000201U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF80007C0[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF80007C0[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF80007C0[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF80007C0[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 7 */
+ /* .. ==> 0XF80007C0[7:5] = 0x00000007U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x000000E0U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF80007C0[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF80007C0[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF80007C0[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF80007C0[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU, 0x000002E0U),
+ /* .. TRI_ENABLE = 1 */
+ /* .. ==> 0XF80007C4[0:0] = 0x00000001U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF80007C4[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF80007C4[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF80007C4[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 7 */
+ /* .. ==> 0XF80007C4[7:5] = 0x00000007U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x000000E0U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF80007C4[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF80007C4[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF80007C4[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF80007C4[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x000002E1U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF80007C8[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF80007C8[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF80007C8[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF80007C8[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF80007C8[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF80007C8[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF80007C8[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF80007C8[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF80007C8[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU, 0x00000200U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF80007CC[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF80007CC[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF80007CC[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF80007CC[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF80007CC[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF80007CC[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF80007CC[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF80007CC[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF80007CC[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU, 0x00000200U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF80007D0[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF80007D0[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF80007D0[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF80007D0[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 4 */
+ /* .. ==> 0XF80007D0[7:5] = 0x00000004U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF80007D0[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF80007D0[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF80007D0[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF80007D0[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU, 0x00000280U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF80007D4[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF80007D4[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF80007D4[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF80007D4[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 4 */
+ /* .. ==> 0XF80007D4[7:5] = 0x00000004U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF80007D4[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF80007D4[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF80007D4[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF80007D4[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU, 0x00000280U),
+ /* .. SDIO0_WP_SEL = 55 */
+ /* .. ==> 0XF8000830[5:0] = 0x00000037U */
+ /* .. ==> MASK : 0x0000003FU VAL : 0x00000037U */
+ /* .. SDIO0_CD_SEL = 47 */
+ /* .. ==> 0XF8000830[21:16] = 0x0000002FU */
+ /* .. ==> MASK : 0x003F0000U VAL : 0x002F0000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000830, 0x003F003FU, 0x002F0037U),
+ /* .. FINISH: MIO PROGRAMMING */
+ /* .. START: LOCK IT BACK */
+ /* .. LOCK_KEY = 0X767B */
+ /* .. ==> 0XF8000004[15:0] = 0x0000767BU */
+ /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+ /* .. FINISH: LOCK IT BACK */
+ /* FINISH: top */
+ /* */
+ EMIT_EXIT(),
+
+ /* */
+};
+
+unsigned long ps7_peripherals_init_data_2_0[] = {
+ /* START: top */
+ /* .. START: SLCR SETTINGS */
+ /* .. UNLOCK_KEY = 0XDF0D */
+ /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
+ /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ /* .. FINISH: SLCR SETTINGS */
+ /* .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS */
+ /* .. IBUF_DISABLE_MODE = 0x1 */
+ /* .. ==> 0XF8000B48[7:7] = 0x00000001U */
+ /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */
+ /* .. TERM_DISABLE_MODE = 0x1 */
+ /* .. ==> 0XF8000B48[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000B48, 0x00000180U, 0x00000180U),
+ /* .. IBUF_DISABLE_MODE = 0x1 */
+ /* .. ==> 0XF8000B4C[7:7] = 0x00000001U */
+ /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */
+ /* .. TERM_DISABLE_MODE = 0x1 */
+ /* .. ==> 0XF8000B4C[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000B4C, 0x00000180U, 0x00000180U),
+ /* .. IBUF_DISABLE_MODE = 0x1 */
+ /* .. ==> 0XF8000B50[7:7] = 0x00000001U */
+ /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */
+ /* .. TERM_DISABLE_MODE = 0x1 */
+ /* .. ==> 0XF8000B50[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U),
+ /* .. IBUF_DISABLE_MODE = 0x1 */
+ /* .. ==> 0XF8000B54[7:7] = 0x00000001U */
+ /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */
+ /* .. TERM_DISABLE_MODE = 0x1 */
+ /* .. ==> 0XF8000B54[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U),
+ /* .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS */
+ /* .. START: LOCK IT BACK */
+ /* .. LOCK_KEY = 0X767B */
+ /* .. ==> 0XF8000004[15:0] = 0x0000767BU */
+ /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+ /* .. FINISH: LOCK IT BACK */
+ /* .. START: SRAM/NOR SET OPMODE */
+ /* .. FINISH: SRAM/NOR SET OPMODE */
+ /* .. START: UART REGISTERS */
+ /* .. BDIV = 0x6 */
+ /* .. ==> 0XE0001034[7:0] = 0x00000006U */
+ /* .. ==> MASK : 0x000000FFU VAL : 0x00000006U */
+ /* .. */
+ EMIT_MASKWRITE(0XE0001034, 0x000000FFU, 0x00000006U),
+ /* .. CD = 0x7c */
+ /* .. ==> 0XE0001018[15:0] = 0x0000007CU */
+ /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU */
+ /* .. */
+ EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU, 0x0000007CU),
+ /* .. STPBRK = 0x0 */
+ /* .. ==> 0XE0001000[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. STTBRK = 0x0 */
+ /* .. ==> 0XE0001000[7:7] = 0x00000000U */
+ /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
+ /* .. RSTTO = 0x0 */
+ /* .. ==> 0XE0001000[6:6] = 0x00000000U */
+ /* .. ==> MASK : 0x00000040U VAL : 0x00000000U */
+ /* .. TXDIS = 0x0 */
+ /* .. ==> 0XE0001000[5:5] = 0x00000000U */
+ /* .. ==> MASK : 0x00000020U VAL : 0x00000000U */
+ /* .. TXEN = 0x1 */
+ /* .. ==> 0XE0001000[4:4] = 0x00000001U */
+ /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */
+ /* .. RXDIS = 0x0 */
+ /* .. ==> 0XE0001000[3:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
+ /* .. RXEN = 0x1 */
+ /* .. ==> 0XE0001000[2:2] = 0x00000001U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
+ /* .. TXRES = 0x1 */
+ /* .. ==> 0XE0001000[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. RXRES = 0x1 */
+ /* .. ==> 0XE0001000[0:0] = 0x00000001U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. */
+ EMIT_MASKWRITE(0XE0001000, 0x000001FFU, 0x00000017U),
+ /* .. IRMODE = 0x0 */
+ /* .. ==> 0XE0001004[11:11] = 0x00000000U */
+ /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
+ /* .. UCLKEN = 0x0 */
+ /* .. ==> 0XE0001004[10:10] = 0x00000000U */
+ /* .. ==> MASK : 0x00000400U VAL : 0x00000000U */
+ /* .. CHMODE = 0x0 */
+ /* .. ==> 0XE0001004[9:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000300U VAL : 0x00000000U */
+ /* .. NBSTOP = 0x0 */
+ /* .. ==> 0XE0001004[7:6] = 0x00000000U */
+ /* .. ==> MASK : 0x000000C0U VAL : 0x00000000U */
+ /* .. PAR = 0x4 */
+ /* .. ==> 0XE0001004[5:3] = 0x00000004U */
+ /* .. ==> MASK : 0x00000038U VAL : 0x00000020U */
+ /* .. CHRL = 0x0 */
+ /* .. ==> 0XE0001004[2:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */
+ /* .. CLKS = 0x0 */
+ /* .. ==> 0XE0001004[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XE0001004, 0x00000FFFU, 0x00000020U),
+ /* .. FINISH: UART REGISTERS */
+ /* .. START: QSPI REGISTERS */
+ /* .. Holdb_dr = 1 */
+ /* .. ==> 0XE000D000[19:19] = 0x00000001U */
+ /* .. ==> MASK : 0x00080000U VAL : 0x00080000U */
+ /* .. */
+ EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U),
+ /* .. FINISH: QSPI REGISTERS */
+ /* .. START: PL POWER ON RESET REGISTERS */
+ /* .. PCFG_POR_CNT_4K = 0 */
+ /* .. ==> 0XF8007000[29:29] = 0x00000000U */
+ /* .. ==> MASK : 0x20000000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U),
+ /* .. FINISH: PL POWER ON RESET REGISTERS */
+ /* .. START: SMC TIMING CALCULATION REGISTER UPDATE */
+ /* .. .. START: NAND SET CYCLE */
+ /* .. .. FINISH: NAND SET CYCLE */
+ /* .. .. START: OPMODE */
+ /* .. .. FINISH: OPMODE */
+ /* .. .. START: DIRECT COMMAND */
+ /* .. .. FINISH: DIRECT COMMAND */
+ /* .. .. START: SRAM/NOR CS0 SET CYCLE */
+ /* .. .. FINISH: SRAM/NOR CS0 SET CYCLE */
+ /* .. .. START: DIRECT COMMAND */
+ /* .. .. FINISH: DIRECT COMMAND */
+ /* .. .. START: NOR CS0 BASE ADDRESS */
+ /* .. .. FINISH: NOR CS0 BASE ADDRESS */
+ /* .. .. START: SRAM/NOR CS1 SET CYCLE */
+ /* .. .. FINISH: SRAM/NOR CS1 SET CYCLE */
+ /* .. .. START: DIRECT COMMAND */
+ /* .. .. FINISH: DIRECT COMMAND */
+ /* .. .. START: NOR CS1 BASE ADDRESS */
+ /* .. .. FINISH: NOR CS1 BASE ADDRESS */
+ /* .. .. START: USB RESET */
+ /* .. .. .. START: USB0 RESET */
+ /* .. .. .. .. START: DIR MODE BANK 0 */
+ /* .. .. .. .. FINISH: DIR MODE BANK 0 */
+ /* .. .. .. .. START: DIR MODE BANK 1 */
+ /* .. .. .. .. DIRECTION_1 = 0x4000 */
+ /* .. .. .. .. ==> 0XE000A244[21:0] = 0x00004000U */
+ /* .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U */
+ /* .. .. .. .. */
+ EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU, 0x00004000U),
+ /* .. .. .. .. FINISH: DIR MODE BANK 1 */
+ /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. MASK_1_LSW = 0xbfff */
+ /* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */
+ /* .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U */
+ /* .. .. .. .. DATA_1_LSW = 0x4000 */
+ /* .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U */
+ /* .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U */
+ /* .. .. .. .. */
+ EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF4000U),
+ /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
+ /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
+ /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
+ /* .. .. .. .. OP_ENABLE_1 = 0x4000 */
+ /* .. .. .. .. ==> 0XE000A248[21:0] = 0x00004000U */
+ /* .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U */
+ /* .. .. .. .. */
+ EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU, 0x00004000U),
+ /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
+ /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
+ /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
+ /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
+ /* .. .. .. .. MASK_1_LSW = 0xbfff */
+ /* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */
+ /* .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U */
+ /* .. .. .. .. DATA_1_LSW = 0x0 */
+ /* .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U */
+ /* .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U */
+ /* .. .. .. .. */
+ EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF0000U),
+ /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
+ /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
+ /* .. .. .. .. START: ADD 1 MS DELAY */
+ /* .. .. .. .. */
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ /* .. .. .. .. FINISH: ADD 1 MS DELAY */
+ /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. MASK_1_LSW = 0xbfff */
+ /* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */
+ /* .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U */
+ /* .. .. .. .. DATA_1_LSW = 0x4000 */
+ /* .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U */
+ /* .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U */
+ /* .. .. .. .. */
+ EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF4000U),
+ /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. FINISH: USB0 RESET */
+ /* .. .. .. START: USB1 RESET */
+ /* .. .. .. .. START: DIR MODE BANK 0 */
+ /* .. .. .. .. FINISH: DIR MODE BANK 0 */
+ /* .. .. .. .. START: DIR MODE BANK 1 */
+ /* .. .. .. .. FINISH: DIR MODE BANK 1 */
+ /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
+ /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
+ /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
+ /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
+ /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
+ /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
+ /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
+ /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
+ /* .. .. .. .. START: ADD 1 MS DELAY */
+ /* .. .. .. .. */
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ /* .. .. .. .. FINISH: ADD 1 MS DELAY */
+ /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. FINISH: USB1 RESET */
+ /* .. .. FINISH: USB RESET */
+ /* .. .. START: ENET RESET */
+ /* .. .. .. START: ENET0 RESET */
+ /* .. .. .. .. START: DIR MODE BANK 0 */
+ /* .. .. .. .. FINISH: DIR MODE BANK 0 */
+ /* .. .. .. .. START: DIR MODE BANK 1 */
+ /* .. .. .. .. FINISH: DIR MODE BANK 1 */
+ /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
+ /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
+ /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
+ /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
+ /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
+ /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
+ /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
+ /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
+ /* .. .. .. .. START: ADD 1 MS DELAY */
+ /* .. .. .. .. */
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ /* .. .. .. .. FINISH: ADD 1 MS DELAY */
+ /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. FINISH: ENET0 RESET */
+ /* .. .. .. START: ENET1 RESET */
+ /* .. .. .. .. START: DIR MODE BANK 0 */
+ /* .. .. .. .. FINISH: DIR MODE BANK 0 */
+ /* .. .. .. .. START: DIR MODE BANK 1 */
+ /* .. .. .. .. FINISH: DIR MODE BANK 1 */
+ /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
+ /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
+ /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
+ /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
+ /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
+ /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
+ /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
+ /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
+ /* .. .. .. .. START: ADD 1 MS DELAY */
+ /* .. .. .. .. */
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ /* .. .. .. .. FINISH: ADD 1 MS DELAY */
+ /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. FINISH: ENET1 RESET */
+ /* .. .. FINISH: ENET RESET */
+ /* .. .. START: I2C RESET */
+ /* .. .. .. START: I2C0 RESET */
+ /* .. .. .. .. START: DIR MODE GPIO BANK0 */
+ /* .. .. .. .. FINISH: DIR MODE GPIO BANK0 */
+ /* .. .. .. .. START: DIR MODE GPIO BANK1 */
+ /* .. .. .. .. FINISH: DIR MODE GPIO BANK1 */
+ /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. .. START: OUTPUT ENABLE */
+ /* .. .. .. .. FINISH: OUTPUT ENABLE */
+ /* .. .. .. .. START: OUTPUT ENABLE */
+ /* .. .. .. .. FINISH: OUTPUT ENABLE */
+ /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
+ /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
+ /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
+ /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
+ /* .. .. .. .. START: ADD 1 MS DELAY */
+ /* .. .. .. .. */
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ /* .. .. .. .. FINISH: ADD 1 MS DELAY */
+ /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. FINISH: I2C0 RESET */
+ /* .. .. .. START: I2C1 RESET */
+ /* .. .. .. .. START: DIR MODE GPIO BANK0 */
+ /* .. .. .. .. FINISH: DIR MODE GPIO BANK0 */
+ /* .. .. .. .. START: DIR MODE GPIO BANK1 */
+ /* .. .. .. .. FINISH: DIR MODE GPIO BANK1 */
+ /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. .. START: OUTPUT ENABLE */
+ /* .. .. .. .. FINISH: OUTPUT ENABLE */
+ /* .. .. .. .. START: OUTPUT ENABLE */
+ /* .. .. .. .. FINISH: OUTPUT ENABLE */
+ /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
+ /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
+ /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
+ /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
+ /* .. .. .. .. START: ADD 1 MS DELAY */
+ /* .. .. .. .. */
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ /* .. .. .. .. FINISH: ADD 1 MS DELAY */
+ /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. FINISH: I2C1 RESET */
+ /* .. .. FINISH: I2C RESET */
+ /* .. .. START: NOR CHIP SELECT */
+ /* .. .. .. START: DIR MODE BANK 0 */
+ /* .. .. .. FINISH: DIR MODE BANK 0 */
+ /* .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. START: OUTPUT ENABLE BANK 0 */
+ /* .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
+ /* .. .. FINISH: NOR CHIP SELECT */
+ /* .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE */
+ /* FINISH: top */
+ /* */
+ EMIT_EXIT(),
+
+ /* */
+};
+
+unsigned long ps7_post_config_2_0[] = {
+ /* START: top */
+ /* .. START: SLCR SETTINGS */
+ /* .. UNLOCK_KEY = 0XDF0D */
+ /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
+ /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ /* .. FINISH: SLCR SETTINGS */
+ /* .. START: ENABLING LEVEL SHIFTER */
+ /* .. USER_INP_ICT_EN_0 = 3 */
+ /* .. ==> 0XF8000900[1:0] = 0x00000003U */
+ /* .. ==> MASK : 0x00000003U VAL : 0x00000003U */
+ /* .. USER_INP_ICT_EN_1 = 3 */
+ /* .. ==> 0XF8000900[3:2] = 0x00000003U */
+ /* .. ==> MASK : 0x0000000CU VAL : 0x0000000CU */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU),
+ /* .. FINISH: ENABLING LEVEL SHIFTER */
+ /* .. START: FPGA RESETS TO 0 */
+ /* .. reserved_3 = 0 */
+ /* .. ==> 0XF8000240[31:25] = 0x00000000U */
+ /* .. ==> MASK : 0xFE000000U VAL : 0x00000000U */
+ /* .. FPGA_ACP_RST = 0 */
+ /* .. ==> 0XF8000240[24:24] = 0x00000000U */
+ /* .. ==> MASK : 0x01000000U VAL : 0x00000000U */
+ /* .. FPGA_AXDS3_RST = 0 */
+ /* .. ==> 0XF8000240[23:23] = 0x00000000U */
+ /* .. ==> MASK : 0x00800000U VAL : 0x00000000U */
+ /* .. FPGA_AXDS2_RST = 0 */
+ /* .. ==> 0XF8000240[22:22] = 0x00000000U */
+ /* .. ==> MASK : 0x00400000U VAL : 0x00000000U */
+ /* .. FPGA_AXDS1_RST = 0 */
+ /* .. ==> 0XF8000240[21:21] = 0x00000000U */
+ /* .. ==> MASK : 0x00200000U VAL : 0x00000000U */
+ /* .. FPGA_AXDS0_RST = 0 */
+ /* .. ==> 0XF8000240[20:20] = 0x00000000U */
+ /* .. ==> MASK : 0x00100000U VAL : 0x00000000U */
+ /* .. reserved_2 = 0 */
+ /* .. ==> 0XF8000240[19:18] = 0x00000000U */
+ /* .. ==> MASK : 0x000C0000U VAL : 0x00000000U */
+ /* .. FSSW1_FPGA_RST = 0 */
+ /* .. ==> 0XF8000240[17:17] = 0x00000000U */
+ /* .. ==> MASK : 0x00020000U VAL : 0x00000000U */
+ /* .. FSSW0_FPGA_RST = 0 */
+ /* .. ==> 0XF8000240[16:16] = 0x00000000U */
+ /* .. ==> MASK : 0x00010000U VAL : 0x00000000U */
+ /* .. reserved_1 = 0 */
+ /* .. ==> 0XF8000240[15:14] = 0x00000000U */
+ /* .. ==> MASK : 0x0000C000U VAL : 0x00000000U */
+ /* .. FPGA_FMSW1_RST = 0 */
+ /* .. ==> 0XF8000240[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. FPGA_FMSW0_RST = 0 */
+ /* .. ==> 0XF8000240[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. FPGA_DMA3_RST = 0 */
+ /* .. ==> 0XF8000240[11:11] = 0x00000000U */
+ /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
+ /* .. FPGA_DMA2_RST = 0 */
+ /* .. ==> 0XF8000240[10:10] = 0x00000000U */
+ /* .. ==> MASK : 0x00000400U VAL : 0x00000000U */
+ /* .. FPGA_DMA1_RST = 0 */
+ /* .. ==> 0XF8000240[9:9] = 0x00000000U */
+ /* .. ==> MASK : 0x00000200U VAL : 0x00000000U */
+ /* .. FPGA_DMA0_RST = 0 */
+ /* .. ==> 0XF8000240[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. reserved = 0 */
+ /* .. ==> 0XF8000240[7:4] = 0x00000000U */
+ /* .. ==> MASK : 0x000000F0U VAL : 0x00000000U */
+ /* .. FPGA3_OUT_RST = 0 */
+ /* .. ==> 0XF8000240[3:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
+ /* .. FPGA2_OUT_RST = 0 */
+ /* .. ==> 0XF8000240[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. FPGA1_OUT_RST = 0 */
+ /* .. ==> 0XF8000240[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. FPGA0_OUT_RST = 0 */
+ /* .. ==> 0XF8000240[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU, 0x00000000U),
+ /* .. FINISH: FPGA RESETS TO 0 */
+ /* .. START: AFI REGISTERS */
+ /* .. .. START: AFI0 REGISTERS */
+ /* .. .. FINISH: AFI0 REGISTERS */
+ /* .. .. START: AFI1 REGISTERS */
+ /* .. .. FINISH: AFI1 REGISTERS */
+ /* .. .. START: AFI2 REGISTERS */
+ /* .. .. FINISH: AFI2 REGISTERS */
+ /* .. .. START: AFI3 REGISTERS */
+ /* .. .. FINISH: AFI3 REGISTERS */
+ /* .. FINISH: AFI REGISTERS */
+ /* .. START: LOCK IT BACK */
+ /* .. LOCK_KEY = 0X767B */
+ /* .. ==> 0XF8000004[15:0] = 0x0000767BU */
+ /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+ /* .. FINISH: LOCK IT BACK */
+ /* FINISH: top */
+ /* */
+ EMIT_EXIT(),
+
+ /* */
+};
+
+unsigned long ps7_debug_2_0[] = {
+ /* START: top */
+ /* .. START: CROSS TRIGGER CONFIGURATIONS */
+ /* .. .. START: UNLOCKING CTI REGISTERS */
+ /* .. .. KEY = 0XC5ACCE55 */
+ /* .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U */
+ /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU, 0xC5ACCE55U),
+ /* .. .. KEY = 0XC5ACCE55 */
+ /* .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U */
+ /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU, 0xC5ACCE55U),
+ /* .. .. KEY = 0XC5ACCE55 */
+ /* .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U */
+ /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU, 0xC5ACCE55U),
+ /* .. .. FINISH: UNLOCKING CTI REGISTERS */
+ /* .. .. START: ENABLING CTI MODULES AND CHANNELS */
+ /* .. .. FINISH: ENABLING CTI MODULES AND CHANNELS */
+ /* .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS */
+ /* .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS */
+ /* .. FINISH: CROSS TRIGGER CONFIGURATIONS */
+ /* FINISH: top */
+ /* */
+ EMIT_EXIT(),
+
+ /* */
+};
+
+unsigned long ps7_pll_init_data_1_0[] = {
+ /* START: top */
+ /* .. START: SLCR SETTINGS */
+ /* .. UNLOCK_KEY = 0XDF0D */
+ /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
+ /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ /* .. FINISH: SLCR SETTINGS */
+ /* .. START: PLL SLCR REGISTERS */
+ /* .. .. START: ARM PLL INIT */
+ /* .. .. PLL_RES = 0xc */
+ /* .. .. ==> 0XF8000110[7:4] = 0x0000000CU */
+ /* .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U */
+ /* .. .. PLL_CP = 0x2 */
+ /* .. .. ==> 0XF8000110[11:8] = 0x00000002U */
+ /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */
+ /* .. .. LOCK_CNT = 0x177 */
+ /* .. .. ==> 0XF8000110[21:12] = 0x00000177U */
+ /* .. .. ==> MASK : 0x003FF000U VAL : 0x00177000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x001772C0U),
+ /* .. .. .. START: UPDATE FB_DIV */
+ /* .. .. .. PLL_FDIV = 0x1a */
+ /* .. .. .. ==> 0XF8000100[18:12] = 0x0000001AU */
+ /* .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001A000U */
+ /* .. .. .. */
+ EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x0001A000U),
+ /* .. .. .. FINISH: UPDATE FB_DIV */
+ /* .. .. .. START: BY PASS PLL */
+ /* .. .. .. PLL_BYPASS_FORCE = 1 */
+ /* .. .. .. ==> 0XF8000100[4:4] = 0x00000001U */
+ /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U */
+ /* .. .. .. */
+ EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U),
+ /* .. .. .. FINISH: BY PASS PLL */
+ /* .. .. .. START: ASSERT RESET */
+ /* .. .. .. PLL_RESET = 1 */
+ /* .. .. .. ==> 0XF8000100[0:0] = 0x00000001U */
+ /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. .. .. */
+ EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U),
+ /* .. .. .. FINISH: ASSERT RESET */
+ /* .. .. .. START: DEASSERT RESET */
+ /* .. .. .. PLL_RESET = 0 */
+ /* .. .. .. ==> 0XF8000100[0:0] = 0x00000000U */
+ /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. .. .. */
+ EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U),
+ /* .. .. .. FINISH: DEASSERT RESET */
+ /* .. .. .. START: CHECK PLL STATUS */
+ /* .. .. .. ARM_PLL_LOCK = 1 */
+ /* .. .. .. ==> 0XF800010C[0:0] = 0x00000001U */
+ /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. .. .. */
+ EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+ /* .. .. .. FINISH: CHECK PLL STATUS */
+ /* .. .. .. START: REMOVE PLL BY PASS */
+ /* .. .. .. PLL_BYPASS_FORCE = 0 */
+ /* .. .. .. ==> 0XF8000100[4:4] = 0x00000000U */
+ /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
+ /* .. .. .. */
+ EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U),
+ /* .. .. .. FINISH: REMOVE PLL BY PASS */
+ /* .. .. .. SRCSEL = 0x0 */
+ /* .. .. .. ==> 0XF8000120[5:4] = 0x00000000U */
+ /* .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
+ /* .. .. .. DIVISOR = 0x2 */
+ /* .. .. .. ==> 0XF8000120[13:8] = 0x00000002U */
+ /* .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U */
+ /* .. .. .. CPU_6OR4XCLKACT = 0x1 */
+ /* .. .. .. ==> 0XF8000120[24:24] = 0x00000001U */
+ /* .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U */
+ /* .. .. .. CPU_3OR2XCLKACT = 0x1 */
+ /* .. .. .. ==> 0XF8000120[25:25] = 0x00000001U */
+ /* .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U */
+ /* .. .. .. CPU_2XCLKACT = 0x1 */
+ /* .. .. .. ==> 0XF8000120[26:26] = 0x00000001U */
+ /* .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U */
+ /* .. .. .. CPU_1XCLKACT = 0x1 */
+ /* .. .. .. ==> 0XF8000120[27:27] = 0x00000001U */
+ /* .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U */
+ /* .. .. .. CPU_PERI_CLKACT = 0x1 */
+ /* .. .. .. ==> 0XF8000120[28:28] = 0x00000001U */
+ /* .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U */
+ /* .. .. .. */
+ EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000200U),
+ /* .. .. FINISH: ARM PLL INIT */
+ /* .. .. START: DDR PLL INIT */
+ /* .. .. PLL_RES = 0xc */
+ /* .. .. ==> 0XF8000114[7:4] = 0x0000000CU */
+ /* .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U */
+ /* .. .. PLL_CP = 0x2 */
+ /* .. .. ==> 0XF8000114[11:8] = 0x00000002U */
+ /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */
+ /* .. .. LOCK_CNT = 0x1db */
+ /* .. .. ==> 0XF8000114[21:12] = 0x000001DBU */
+ /* .. .. ==> MASK : 0x003FF000U VAL : 0x001DB000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x001DB2C0U),
+ /* .. .. .. START: UPDATE FB_DIV */
+ /* .. .. .. PLL_FDIV = 0x15 */
+ /* .. .. .. ==> 0XF8000104[18:12] = 0x00000015U */
+ /* .. .. .. ==> MASK : 0x0007F000U VAL : 0x00015000U */
+ /* .. .. .. */
+ EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x00015000U),
+ /* .. .. .. FINISH: UPDATE FB_DIV */
+ /* .. .. .. START: BY PASS PLL */
+ /* .. .. .. PLL_BYPASS_FORCE = 1 */
+ /* .. .. .. ==> 0XF8000104[4:4] = 0x00000001U */
+ /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U */
+ /* .. .. .. */
+ EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000010U),
+ /* .. .. .. FINISH: BY PASS PLL */
+ /* .. .. .. START: ASSERT RESET */
+ /* .. .. .. PLL_RESET = 1 */
+ /* .. .. .. ==> 0XF8000104[0:0] = 0x00000001U */
+ /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. .. .. */
+ EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000001U),
+ /* .. .. .. FINISH: ASSERT RESET */
+ /* .. .. .. START: DEASSERT RESET */
+ /* .. .. .. PLL_RESET = 0 */
+ /* .. .. .. ==> 0XF8000104[0:0] = 0x00000000U */
+ /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. .. .. */
+ EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000000U),
+ /* .. .. .. FINISH: DEASSERT RESET */
+ /* .. .. .. START: CHECK PLL STATUS */
+ /* .. .. .. DDR_PLL_LOCK = 1 */
+ /* .. .. .. ==> 0XF800010C[1:1] = 0x00000001U */
+ /* .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. .. .. */
+ EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+ /* .. .. .. FINISH: CHECK PLL STATUS */
+ /* .. .. .. START: REMOVE PLL BY PASS */
+ /* .. .. .. PLL_BYPASS_FORCE = 0 */
+ /* .. .. .. ==> 0XF8000104[4:4] = 0x00000000U */
+ /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
+ /* .. .. .. */
+ EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U),
+ /* .. .. .. FINISH: REMOVE PLL BY PASS */
+ /* .. .. .. DDR_3XCLKACT = 0x1 */
+ /* .. .. .. ==> 0XF8000124[0:0] = 0x00000001U */
+ /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. .. .. DDR_2XCLKACT = 0x1 */
+ /* .. .. .. ==> 0XF8000124[1:1] = 0x00000001U */
+ /* .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. .. .. DDR_3XCLK_DIVISOR = 0x2 */
+ /* .. .. .. ==> 0XF8000124[25:20] = 0x00000002U */
+ /* .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U */
+ /* .. .. .. DDR_2XCLK_DIVISOR = 0x3 */
+ /* .. .. .. ==> 0XF8000124[31:26] = 0x00000003U */
+ /* .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U */
+ /* .. .. .. */
+ EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U),
+ /* .. .. FINISH: DDR PLL INIT */
+ /* .. .. START: IO PLL INIT */
+ /* .. .. PLL_RES = 0xc */
+ /* .. .. ==> 0XF8000118[7:4] = 0x0000000CU */
+ /* .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U */
+ /* .. .. PLL_CP = 0x2 */
+ /* .. .. ==> 0XF8000118[11:8] = 0x00000002U */
+ /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */
+ /* .. .. LOCK_CNT = 0x1f4 */
+ /* .. .. ==> 0XF8000118[21:12] = 0x000001F4U */
+ /* .. .. ==> MASK : 0x003FF000U VAL : 0x001F4000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x001F42C0U),
+ /* .. .. .. START: UPDATE FB_DIV */
+ /* .. .. .. PLL_FDIV = 0x14 */
+ /* .. .. .. ==> 0XF8000108[18:12] = 0x00000014U */
+ /* .. .. .. ==> MASK : 0x0007F000U VAL : 0x00014000U */
+ /* .. .. .. */
+ EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x00014000U),
+ /* .. .. .. FINISH: UPDATE FB_DIV */
+ /* .. .. .. START: BY PASS PLL */
+ /* .. .. .. PLL_BYPASS_FORCE = 1 */
+ /* .. .. .. ==> 0XF8000108[4:4] = 0x00000001U */
+ /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U */
+ /* .. .. .. */
+ EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U),
+ /* .. .. .. FINISH: BY PASS PLL */
+ /* .. .. .. START: ASSERT RESET */
+ /* .. .. .. PLL_RESET = 1 */
+ /* .. .. .. ==> 0XF8000108[0:0] = 0x00000001U */
+ /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. .. .. */
+ EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U),
+ /* .. .. .. FINISH: ASSERT RESET */
+ /* .. .. .. START: DEASSERT RESET */
+ /* .. .. .. PLL_RESET = 0 */
+ /* .. .. .. ==> 0XF8000108[0:0] = 0x00000000U */
+ /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. .. .. */
+ EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U),
+ /* .. .. .. FINISH: DEASSERT RESET */
+ /* .. .. .. START: CHECK PLL STATUS */
+ /* .. .. .. IO_PLL_LOCK = 1 */
+ /* .. .. .. ==> 0XF800010C[2:2] = 0x00000001U */
+ /* .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U */
+ /* .. .. .. */
+ EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+ /* .. .. .. FINISH: CHECK PLL STATUS */
+ /* .. .. .. START: REMOVE PLL BY PASS */
+ /* .. .. .. PLL_BYPASS_FORCE = 0 */
+ /* .. .. .. ==> 0XF8000108[4:4] = 0x00000000U */
+ /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
+ /* .. .. .. */
+ EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000000U),
+ /* .. .. .. FINISH: REMOVE PLL BY PASS */
+ /* .. .. FINISH: IO PLL INIT */
+ /* .. FINISH: PLL SLCR REGISTERS */
+ /* .. START: LOCK IT BACK */
+ /* .. LOCK_KEY = 0X767B */
+ /* .. ==> 0XF8000004[15:0] = 0x0000767BU */
+ /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+ /* .. FINISH: LOCK IT BACK */
+ /* FINISH: top */
+ /* */
+ EMIT_EXIT(),
+
+ /* */
+};
+
+unsigned long ps7_clock_init_data_1_0[] = {
+ /* START: top */
+ /* .. START: SLCR SETTINGS */
+ /* .. UNLOCK_KEY = 0XDF0D */
+ /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
+ /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ /* .. FINISH: SLCR SETTINGS */
+ /* .. START: CLOCK CONTROL SLCR REGISTERS */
+ /* .. CLKACT = 0x1 */
+ /* .. ==> 0XF8000128[0:0] = 0x00000001U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. DIVISOR0 = 0x34 */
+ /* .. ==> 0XF8000128[13:8] = 0x00000034U */
+ /* .. ==> MASK : 0x00003F00U VAL : 0x00003400U */
+ /* .. DIVISOR1 = 0x2 */
+ /* .. ==> 0XF8000128[25:20] = 0x00000002U */
+ /* .. ==> MASK : 0x03F00000U VAL : 0x00200000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00203401U),
+ /* .. CLKACT = 0x1 */
+ /* .. ==> 0XF8000138[0:0] = 0x00000001U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. SRCSEL = 0x0 */
+ /* .. ==> 0XF8000138[4:4] = 0x00000000U */
+ /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000001U),
+ /* .. CLKACT = 0x1 */
+ /* .. ==> 0XF8000140[0:0] = 0x00000001U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. SRCSEL = 0x0 */
+ /* .. ==> 0XF8000140[6:4] = 0x00000000U */
+ /* .. ==> MASK : 0x00000070U VAL : 0x00000000U */
+ /* .. DIVISOR = 0x8 */
+ /* .. ==> 0XF8000140[13:8] = 0x00000008U */
+ /* .. ==> MASK : 0x00003F00U VAL : 0x00000800U */
+ /* .. DIVISOR1 = 0x1 */
+ /* .. ==> 0XF8000140[25:20] = 0x00000001U */
+ /* .. ==> MASK : 0x03F00000U VAL : 0x00100000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00100801U),
+ /* .. CLKACT = 0x1 */
+ /* .. ==> 0XF800014C[0:0] = 0x00000001U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. SRCSEL = 0x0 */
+ /* .. ==> 0XF800014C[5:4] = 0x00000000U */
+ /* .. ==> MASK : 0x00000030U VAL : 0x00000000U */
+ /* .. DIVISOR = 0x5 */
+ /* .. ==> 0XF800014C[13:8] = 0x00000005U */
+ /* .. ==> MASK : 0x00003F00U VAL : 0x00000500U */
+ /* .. */
+ EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000501U),
+ /* .. CLKACT0 = 0x1 */
+ /* .. ==> 0XF8000150[0:0] = 0x00000001U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. CLKACT1 = 0x0 */
+ /* .. ==> 0XF8000150[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. SRCSEL = 0x0 */
+ /* .. ==> 0XF8000150[5:4] = 0x00000000U */
+ /* .. ==> MASK : 0x00000030U VAL : 0x00000000U */
+ /* .. DIVISOR = 0x14 */
+ /* .. ==> 0XF8000150[13:8] = 0x00000014U */
+ /* .. ==> MASK : 0x00003F00U VAL : 0x00001400U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00001401U),
+ /* .. CLKACT0 = 0x0 */
+ /* .. ==> 0XF8000154[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. CLKACT1 = 0x1 */
+ /* .. ==> 0XF8000154[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. SRCSEL = 0x0 */
+ /* .. ==> 0XF8000154[5:4] = 0x00000000U */
+ /* .. ==> MASK : 0x00000030U VAL : 0x00000000U */
+ /* .. DIVISOR = 0xa */
+ /* .. ==> 0XF8000154[13:8] = 0x0000000AU */
+ /* .. ==> MASK : 0x00003F00U VAL : 0x00000A00U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00000A02U),
+ /* .. .. START: TRACE CLOCK */
+ /* .. .. FINISH: TRACE CLOCK */
+ /* .. .. CLKACT = 0x1 */
+ /* .. .. ==> 0XF8000168[0:0] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. .. SRCSEL = 0x0 */
+ /* .. .. ==> 0XF8000168[5:4] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
+ /* .. .. DIVISOR = 0x5 */
+ /* .. .. ==> 0XF8000168[13:8] = 0x00000005U */
+ /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000501U),
+ /* .. .. SRCSEL = 0x0 */
+ /* .. .. ==> 0XF8000170[5:4] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
+ /* .. .. DIVISOR0 = 0xa */
+ /* .. .. ==> 0XF8000170[13:8] = 0x0000000AU */
+ /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U */
+ /* .. .. DIVISOR1 = 0x1 */
+ /* .. .. ==> 0XF8000170[25:20] = 0x00000001U */
+ /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00100A00U),
+ /* .. .. SRCSEL = 0x0 */
+ /* .. .. ==> 0XF8000180[5:4] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
+ /* .. .. DIVISOR0 = 0x7 */
+ /* .. .. ==> 0XF8000180[13:8] = 0x00000007U */
+ /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000700U */
+ /* .. .. DIVISOR1 = 0x1 */
+ /* .. .. ==> 0XF8000180[25:20] = 0x00000001U */
+ /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00100700U),
+ /* .. .. SRCSEL = 0x0 */
+ /* .. .. ==> 0XF8000190[5:4] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
+ /* .. .. DIVISOR0 = 0x5 */
+ /* .. .. ==> 0XF8000190[13:8] = 0x00000005U */
+ /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U */
+ /* .. .. DIVISOR1 = 0x1 */
+ /* .. .. ==> 0XF8000190[25:20] = 0x00000001U */
+ /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00100500U),
+ /* .. .. SRCSEL = 0x0 */
+ /* .. .. ==> 0XF80001A0[5:4] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
+ /* .. .. DIVISOR0 = 0x14 */
+ /* .. .. ==> 0XF80001A0[13:8] = 0x00000014U */
+ /* .. .. ==> MASK : 0x00003F00U VAL : 0x00001400U */
+ /* .. .. DIVISOR1 = 0x1 */
+ /* .. .. ==> 0XF80001A0[25:20] = 0x00000001U */
+ /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00101400U),
+ /* .. .. CLK_621_TRUE = 0x1 */
+ /* .. .. ==> 0XF80001C4[0:0] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U),
+ /* .. .. DMA_CPU_2XCLKACT = 0x1 */
+ /* .. .. ==> 0XF800012C[0:0] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. .. USB0_CPU_1XCLKACT = 0x1 */
+ /* .. .. ==> 0XF800012C[2:2] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000004U VAL : 0x00000004U */
+ /* .. .. USB1_CPU_1XCLKACT = 0x1 */
+ /* .. .. ==> 0XF800012C[3:3] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000008U VAL : 0x00000008U */
+ /* .. .. GEM0_CPU_1XCLKACT = 0x1 */
+ /* .. .. ==> 0XF800012C[6:6] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000040U VAL : 0x00000040U */
+ /* .. .. GEM1_CPU_1XCLKACT = 0x0 */
+ /* .. .. ==> 0XF800012C[7:7] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000080U VAL : 0x00000000U */
+ /* .. .. SDI0_CPU_1XCLKACT = 0x1 */
+ /* .. .. ==> 0XF800012C[10:10] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000400U VAL : 0x00000400U */
+ /* .. .. SDI1_CPU_1XCLKACT = 0x0 */
+ /* .. .. ==> 0XF800012C[11:11] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */
+ /* .. .. SPI0_CPU_1XCLKACT = 0x0 */
+ /* .. .. ==> 0XF800012C[14:14] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00004000U VAL : 0x00000000U */
+ /* .. .. SPI1_CPU_1XCLKACT = 0x0 */
+ /* .. .. ==> 0XF800012C[15:15] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */
+ /* .. .. CAN0_CPU_1XCLKACT = 0x0 */
+ /* .. .. ==> 0XF800012C[16:16] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
+ /* .. .. CAN1_CPU_1XCLKACT = 0x0 */
+ /* .. .. ==> 0XF800012C[17:17] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
+ /* .. .. I2C0_CPU_1XCLKACT = 0x1 */
+ /* .. .. ==> 0XF800012C[18:18] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00040000U VAL : 0x00040000U */
+ /* .. .. I2C1_CPU_1XCLKACT = 0x1 */
+ /* .. .. ==> 0XF800012C[19:19] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00080000U VAL : 0x00080000U */
+ /* .. .. UART0_CPU_1XCLKACT = 0x0 */
+ /* .. .. ==> 0XF800012C[20:20] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00100000U VAL : 0x00000000U */
+ /* .. .. UART1_CPU_1XCLKACT = 0x1 */
+ /* .. .. ==> 0XF800012C[21:21] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00200000U VAL : 0x00200000U */
+ /* .. .. GPIO_CPU_1XCLKACT = 0x1 */
+ /* .. .. ==> 0XF800012C[22:22] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00400000U VAL : 0x00400000U */
+ /* .. .. LQSPI_CPU_1XCLKACT = 0x1 */
+ /* .. .. ==> 0XF800012C[23:23] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00800000U VAL : 0x00800000U */
+ /* .. .. SMC_CPU_1XCLKACT = 0x1 */
+ /* .. .. ==> 0XF800012C[24:24] = 0x00000001U */
+ /* .. .. ==> MASK : 0x01000000U VAL : 0x01000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01EC044DU),
+ /* .. FINISH: CLOCK CONTROL SLCR REGISTERS */
+ /* .. START: THIS SHOULD BE BLANK */
+ /* .. FINISH: THIS SHOULD BE BLANK */
+ /* .. START: LOCK IT BACK */
+ /* .. LOCK_KEY = 0X767B */
+ /* .. ==> 0XF8000004[15:0] = 0x0000767BU */
+ /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+ /* .. FINISH: LOCK IT BACK */
+ /* FINISH: top */
+ /* */
+ EMIT_EXIT(),
+
+ /* */
+};
+
+unsigned long ps7_ddr_init_data_1_0[] = {
+ /* START: top */
+ /* .. START: DDR INITIALIZATION */
+ /* .. .. START: LOCK DDR */
+ /* .. .. reg_ddrc_soft_rstb = 0 */
+ /* .. .. ==> 0XF8006000[0:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_powerdown_en = 0x0 */
+ /* .. .. ==> 0XF8006000[1:1] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_data_bus_width = 0x0 */
+ /* .. .. ==> 0XF8006000[3:2] = 0x00000000U */
+ /* .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U */
+ /* .. .. reg_ddrc_burst8_refresh = 0x0 */
+ /* .. .. ==> 0XF8006000[6:4] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000070U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_rdwr_idle_gap = 0x1 */
+ /* .. .. ==> 0XF8006000[13:7] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U */
+ /* .. .. reg_ddrc_dis_rd_bypass = 0x0 */
+ /* .. .. ==> 0XF8006000[14:14] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00004000U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_dis_act_bypass = 0x0 */
+ /* .. .. ==> 0XF8006000[15:15] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_dis_auto_refresh = 0x0 */
+ /* .. .. ==> 0XF8006000[16:16] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000080U),
+ /* .. .. FINISH: LOCK DDR */
+ /* .. .. reg_ddrc_t_rfc_nom_x32 = 0x7f */
+ /* .. .. ==> 0XF8006004[11:0] = 0x0000007FU */
+ /* .. .. ==> MASK : 0x00000FFFU VAL : 0x0000007FU */
+ /* .. .. reg_ddrc_active_ranks = 0x1 */
+ /* .. .. ==> 0XF8006004[13:12] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00003000U VAL : 0x00001000U */
+ /* .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 */
+ /* .. .. ==> 0XF8006004[18:14] = 0x00000000U */
+ /* .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_wr_odt_block = 0x1 */
+ /* .. .. ==> 0XF8006004[20:19] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00180000U VAL : 0x00080000U */
+ /* .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0 */
+ /* .. .. ==> 0XF8006004[21:21] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00200000U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_addrmap_cs_bit1 = 0x0 */
+ /* .. .. ==> 0XF8006004[26:22] = 0x00000000U */
+ /* .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_addrmap_open_bank = 0x0 */
+ /* .. .. ==> 0XF8006004[27:27] = 0x00000000U */
+ /* .. .. ==> MASK : 0x08000000U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_addrmap_4bank_ram = 0x0 */
+ /* .. .. ==> 0XF8006004[28:28] = 0x00000000U */
+ /* .. .. ==> MASK : 0x10000000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU, 0x0008107FU),
+ /* .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf */
+ /* .. .. ==> 0XF8006008[10:0] = 0x0000000FU */
+ /* .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU */
+ /* .. .. reg_ddrc_hpr_max_starve_x32 = 0xf */
+ /* .. .. ==> 0XF8006008[21:11] = 0x0000000FU */
+ /* .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U */
+ /* .. .. reg_ddrc_hpr_xact_run_length = 0xf */
+ /* .. .. ==> 0XF8006008[25:22] = 0x0000000FU */
+ /* .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU, 0x03C0780FU),
+ /* .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 */
+ /* .. .. ==> 0XF800600C[10:0] = 0x00000001U */
+ /* .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U */
+ /* .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 */
+ /* .. .. ==> 0XF800600C[21:11] = 0x00000002U */
+ /* .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U */
+ /* .. .. reg_ddrc_lpr_xact_run_length = 0x8 */
+ /* .. .. ==> 0XF800600C[25:22] = 0x00000008U */
+ /* .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU, 0x02001001U),
+ /* .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 */
+ /* .. .. ==> 0XF8006010[10:0] = 0x00000001U */
+ /* .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U */
+ /* .. .. reg_ddrc_w_xact_run_length = 0x8 */
+ /* .. .. ==> 0XF8006010[14:11] = 0x00000008U */
+ /* .. .. ==> MASK : 0x00007800U VAL : 0x00004000U */
+ /* .. .. reg_ddrc_w_max_starve_x32 = 0x2 */
+ /* .. .. ==> 0XF8006010[25:15] = 0x00000002U */
+ /* .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU, 0x00014001U),
+ /* .. .. reg_ddrc_t_rc = 0x1a */
+ /* .. .. ==> 0XF8006014[5:0] = 0x0000001AU */
+ /* .. .. ==> MASK : 0x0000003FU VAL : 0x0000001AU */
+ /* .. .. reg_ddrc_t_rfc_min = 0x54 */
+ /* .. .. ==> 0XF8006014[13:6] = 0x00000054U */
+ /* .. .. ==> MASK : 0x00003FC0U VAL : 0x00001500U */
+ /* .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 */
+ /* .. .. ==> 0XF8006014[20:14] = 0x00000010U */
+ /* .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU, 0x0004151AU),
+ /* .. .. reg_ddrc_wr2pre = 0x12 */
+ /* .. .. ==> 0XF8006018[4:0] = 0x00000012U */
+ /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U */
+ /* .. .. reg_ddrc_powerdown_to_x32 = 0x6 */
+ /* .. .. ==> 0XF8006018[9:5] = 0x00000006U */
+ /* .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U */
+ /* .. .. reg_ddrc_t_faw = 0x15 */
+ /* .. .. ==> 0XF8006018[15:10] = 0x00000015U */
+ /* .. .. ==> MASK : 0x0000FC00U VAL : 0x00005400U */
+ /* .. .. reg_ddrc_t_ras_max = 0x23 */
+ /* .. .. ==> 0XF8006018[21:16] = 0x00000023U */
+ /* .. .. ==> MASK : 0x003F0000U VAL : 0x00230000U */
+ /* .. .. reg_ddrc_t_ras_min = 0x13 */
+ /* .. .. ==> 0XF8006018[26:22] = 0x00000013U */
+ /* .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U */
+ /* .. .. reg_ddrc_t_cke = 0x4 */
+ /* .. .. ==> 0XF8006018[31:28] = 0x00000004U */
+ /* .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU, 0x44E354D2U),
+ /* .. .. reg_ddrc_write_latency = 0x5 */
+ /* .. .. ==> 0XF800601C[4:0] = 0x00000005U */
+ /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U */
+ /* .. .. reg_ddrc_rd2wr = 0x7 */
+ /* .. .. ==> 0XF800601C[9:5] = 0x00000007U */
+ /* .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U */
+ /* .. .. reg_ddrc_wr2rd = 0xe */
+ /* .. .. ==> 0XF800601C[14:10] = 0x0000000EU */
+ /* .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U */
+ /* .. .. reg_ddrc_t_xp = 0x4 */
+ /* .. .. ==> 0XF800601C[19:15] = 0x00000004U */
+ /* .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U */
+ /* .. .. reg_ddrc_pad_pd = 0x0 */
+ /* .. .. ==> 0XF800601C[22:20] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00700000U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_rd2pre = 0x4 */
+ /* .. .. ==> 0XF800601C[27:23] = 0x00000004U */
+ /* .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U */
+ /* .. .. reg_ddrc_t_rcd = 0x7 */
+ /* .. .. ==> 0XF800601C[31:28] = 0x00000007U */
+ /* .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU, 0x720238E5U),
+ /* .. .. reg_ddrc_t_ccd = 0x4 */
+ /* .. .. ==> 0XF8006020[4:2] = 0x00000004U */
+ /* .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U */
+ /* .. .. reg_ddrc_t_rrd = 0x6 */
+ /* .. .. ==> 0XF8006020[7:5] = 0x00000006U */
+ /* .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U */
+ /* .. .. reg_ddrc_refresh_margin = 0x2 */
+ /* .. .. ==> 0XF8006020[11:8] = 0x00000002U */
+ /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */
+ /* .. .. reg_ddrc_t_rp = 0x7 */
+ /* .. .. ==> 0XF8006020[15:12] = 0x00000007U */
+ /* .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U */
+ /* .. .. reg_ddrc_refresh_to_x32 = 0x8 */
+ /* .. .. ==> 0XF8006020[20:16] = 0x00000008U */
+ /* .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U */
+ /* .. .. reg_ddrc_sdram = 0x1 */
+ /* .. .. ==> 0XF8006020[21:21] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00200000U VAL : 0x00200000U */
+ /* .. .. reg_ddrc_mobile = 0x0 */
+ /* .. .. ==> 0XF8006020[22:22] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00400000U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_clock_stop_en = 0x0 */
+ /* .. .. ==> 0XF8006020[23:23] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00800000U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_read_latency = 0x7 */
+ /* .. .. ==> 0XF8006020[28:24] = 0x00000007U */
+ /* .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U */
+ /* .. .. reg_phy_mode_ddr1_ddr2 = 0x1 */
+ /* .. .. ==> 0XF8006020[29:29] = 0x00000001U */
+ /* .. .. ==> MASK : 0x20000000U VAL : 0x20000000U */
+ /* .. .. reg_ddrc_dis_pad_pd = 0x0 */
+ /* .. .. ==> 0XF8006020[30:30] = 0x00000000U */
+ /* .. .. ==> MASK : 0x40000000U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_loopback = 0x0 */
+ /* .. .. ==> 0XF8006020[31:31] = 0x00000000U */
+ /* .. .. ==> MASK : 0x80000000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU, 0x272872D0U),
+ /* .. .. reg_ddrc_en_2t_timing_mode = 0x0 */
+ /* .. .. ==> 0XF8006024[0:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_prefer_write = 0x0 */
+ /* .. .. ==> 0XF8006024[1:1] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_max_rank_rd = 0xf */
+ /* .. .. ==> 0XF8006024[5:2] = 0x0000000FU */
+ /* .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU */
+ /* .. .. reg_ddrc_mr_wr = 0x0 */
+ /* .. .. ==> 0XF8006024[6:6] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000040U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_mr_addr = 0x0 */
+ /* .. .. ==> 0XF8006024[8:7] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000180U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_mr_data = 0x0 */
+ /* .. .. ==> 0XF8006024[24:9] = 0x00000000U */
+ /* .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U */
+ /* .. .. ddrc_reg_mr_wr_busy = 0x0 */
+ /* .. .. ==> 0XF8006024[25:25] = 0x00000000U */
+ /* .. .. ==> MASK : 0x02000000U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_mr_type = 0x0 */
+ /* .. .. ==> 0XF8006024[26:26] = 0x00000000U */
+ /* .. .. ==> MASK : 0x04000000U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_mr_rdata_valid = 0x0 */
+ /* .. .. ==> 0XF8006024[27:27] = 0x00000000U */
+ /* .. .. ==> MASK : 0x08000000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU, 0x0000003CU),
+ /* .. .. reg_ddrc_final_wait_x32 = 0x7 */
+ /* .. .. ==> 0XF8006028[6:0] = 0x00000007U */
+ /* .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U */
+ /* .. .. reg_ddrc_pre_ocd_x32 = 0x0 */
+ /* .. .. ==> 0XF8006028[10:7] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000780U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_t_mrd = 0x4 */
+ /* .. .. ==> 0XF8006028[13:11] = 0x00000004U */
+ /* .. .. ==> MASK : 0x00003800U VAL : 0x00002000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006028, 0x00003FFFU, 0x00002007U),
+ /* .. .. reg_ddrc_emr2 = 0x8 */
+ /* .. .. ==> 0XF800602C[15:0] = 0x00000008U */
+ /* .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U */
+ /* .. .. reg_ddrc_emr3 = 0x0 */
+ /* .. .. ==> 0XF800602C[31:16] = 0x00000000U */
+ /* .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU, 0x00000008U),
+ /* .. .. reg_ddrc_mr = 0x930 */
+ /* .. .. ==> 0XF8006030[15:0] = 0x00000930U */
+ /* .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U */
+ /* .. .. reg_ddrc_emr = 0x4 */
+ /* .. .. ==> 0XF8006030[31:16] = 0x00000004U */
+ /* .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU, 0x00040930U),
+ /* .. .. reg_ddrc_burst_rdwr = 0x4 */
+ /* .. .. ==> 0XF8006034[3:0] = 0x00000004U */
+ /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U */
+ /* .. .. reg_ddrc_pre_cke_x1024 = 0x167 */
+ /* .. .. ==> 0XF8006034[13:4] = 0x00000167U */
+ /* .. .. ==> MASK : 0x00003FF0U VAL : 0x00001670U */
+ /* .. .. reg_ddrc_post_cke_x1024 = 0x1 */
+ /* .. .. ==> 0XF8006034[25:16] = 0x00000001U */
+ /* .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U */
+ /* .. .. reg_ddrc_burstchop = 0x0 */
+ /* .. .. ==> 0XF8006034[28:28] = 0x00000000U */
+ /* .. .. ==> MASK : 0x10000000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x00011674U),
+ /* .. .. reg_ddrc_force_low_pri_n = 0x0 */
+ /* .. .. ==> 0XF8006038[0:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_dis_dq = 0x0 */
+ /* .. .. ==> 0XF8006038[1:1] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. .. reg_phy_debug_mode = 0x0 */
+ /* .. .. ==> 0XF8006038[6:6] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000040U VAL : 0x00000000U */
+ /* .. .. reg_phy_wr_level_start = 0x0 */
+ /* .. .. ==> 0XF8006038[7:7] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000080U VAL : 0x00000000U */
+ /* .. .. reg_phy_rd_level_start = 0x0 */
+ /* .. .. ==> 0XF8006038[8:8] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. .. reg_phy_dq0_wait_t = 0x0 */
+ /* .. .. ==> 0XF8006038[12:9] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006038, 0x00001FC3U, 0x00000000U),
+ /* .. .. reg_ddrc_addrmap_bank_b0 = 0x7 */
+ /* .. .. ==> 0XF800603C[3:0] = 0x00000007U */
+ /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U */
+ /* .. .. reg_ddrc_addrmap_bank_b1 = 0x7 */
+ /* .. .. ==> 0XF800603C[7:4] = 0x00000007U */
+ /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U */
+ /* .. .. reg_ddrc_addrmap_bank_b2 = 0x7 */
+ /* .. .. ==> 0XF800603C[11:8] = 0x00000007U */
+ /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U */
+ /* .. .. reg_ddrc_addrmap_col_b5 = 0x0 */
+ /* .. .. ==> 0XF800603C[15:12] = 0x00000000U */
+ /* .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_addrmap_col_b6 = 0x0 */
+ /* .. .. ==> 0XF800603C[19:16] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU, 0x00000777U),
+ /* .. .. reg_ddrc_addrmap_col_b2 = 0x0 */
+ /* .. .. ==> 0XF8006040[3:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U */
+ /* .. .. reg_ddrc_addrmap_col_b3 = 0x0 */
+ /* .. .. ==> 0XF8006040[7:4] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_addrmap_col_b4 = 0x0 */
+ /* .. .. ==> 0XF8006040[11:8] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_addrmap_col_b7 = 0x0 */
+ /* .. .. ==> 0XF8006040[15:12] = 0x00000000U */
+ /* .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_addrmap_col_b8 = 0x0 */
+ /* .. .. ==> 0XF8006040[19:16] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_addrmap_col_b9 = 0xf */
+ /* .. .. ==> 0XF8006040[23:20] = 0x0000000FU */
+ /* .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U */
+ /* .. .. reg_ddrc_addrmap_col_b10 = 0xf */
+ /* .. .. ==> 0XF8006040[27:24] = 0x0000000FU */
+ /* .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U */
+ /* .. .. reg_ddrc_addrmap_col_b11 = 0xf */
+ /* .. .. ==> 0XF8006040[31:28] = 0x0000000FU */
+ /* .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU, 0xFFF00000U),
+ /* .. .. reg_ddrc_addrmap_row_b0 = 0x6 */
+ /* .. .. ==> 0XF8006044[3:0] = 0x00000006U */
+ /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U */
+ /* .. .. reg_ddrc_addrmap_row_b1 = 0x6 */
+ /* .. .. ==> 0XF8006044[7:4] = 0x00000006U */
+ /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U */
+ /* .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 */
+ /* .. .. ==> 0XF8006044[11:8] = 0x00000006U */
+ /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U */
+ /* .. .. reg_ddrc_addrmap_row_b12 = 0x6 */
+ /* .. .. ==> 0XF8006044[15:12] = 0x00000006U */
+ /* .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U */
+ /* .. .. reg_ddrc_addrmap_row_b13 = 0x6 */
+ /* .. .. ==> 0XF8006044[19:16] = 0x00000006U */
+ /* .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U */
+ /* .. .. reg_ddrc_addrmap_row_b14 = 0xf */
+ /* .. .. ==> 0XF8006044[23:20] = 0x0000000FU */
+ /* .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U */
+ /* .. .. reg_ddrc_addrmap_row_b15 = 0xf */
+ /* .. .. ==> 0XF8006044[27:24] = 0x0000000FU */
+ /* .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU, 0x0FF66666U),
+ /* .. .. reg_ddrc_rank0_rd_odt = 0x0 */
+ /* .. .. ==> 0XF8006048[2:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000007U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_rank0_wr_odt = 0x1 */
+ /* .. .. ==> 0XF8006048[5:3] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000038U VAL : 0x00000008U */
+ /* .. .. reg_ddrc_rank1_rd_odt = 0x1 */
+ /* .. .. ==> 0XF8006048[8:6] = 0x00000001U */
+ /* .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U */
+ /* .. .. reg_ddrc_rank1_wr_odt = 0x1 */
+ /* .. .. ==> 0XF8006048[11:9] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. .. reg_phy_rd_local_odt = 0x0 */
+ /* .. .. ==> 0XF8006048[13:12] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00003000U VAL : 0x00000000U */
+ /* .. .. reg_phy_wr_local_odt = 0x3 */
+ /* .. .. ==> 0XF8006048[15:14] = 0x00000003U */
+ /* .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U */
+ /* .. .. reg_phy_idle_local_odt = 0x3 */
+ /* .. .. ==> 0XF8006048[17:16] = 0x00000003U */
+ /* .. .. ==> MASK : 0x00030000U VAL : 0x00030000U */
+ /* .. .. reg_ddrc_rank2_rd_odt = 0x0 */
+ /* .. .. ==> 0XF8006048[20:18] = 0x00000000U */
+ /* .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_rank2_wr_odt = 0x0 */
+ /* .. .. ==> 0XF8006048[23:21] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_rank3_rd_odt = 0x0 */
+ /* .. .. ==> 0XF8006048[26:24] = 0x00000000U */
+ /* .. .. ==> MASK : 0x07000000U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_rank3_wr_odt = 0x0 */
+ /* .. .. ==> 0XF8006048[29:27] = 0x00000000U */
+ /* .. .. ==> MASK : 0x38000000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU, 0x0003C248U),
+ /* .. .. reg_phy_rd_cmd_to_data = 0x0 */
+ /* .. .. ==> 0XF8006050[3:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U */
+ /* .. .. reg_phy_wr_cmd_to_data = 0x0 */
+ /* .. .. ==> 0XF8006050[7:4] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */
+ /* .. .. reg_phy_rdc_we_to_re_delay = 0x8 */
+ /* .. .. ==> 0XF8006050[11:8] = 0x00000008U */
+ /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U */
+ /* .. .. reg_phy_rdc_fifo_rst_disable = 0x0 */
+ /* .. .. ==> 0XF8006050[15:15] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */
+ /* .. .. reg_phy_use_fixed_re = 0x1 */
+ /* .. .. ==> 0XF8006050[16:16] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00010000U VAL : 0x00010000U */
+ /* .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 */
+ /* .. .. ==> 0XF8006050[17:17] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
+ /* .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 */
+ /* .. .. ==> 0XF8006050[18:18] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
+ /* .. .. reg_phy_clk_stall_level = 0x0 */
+ /* .. .. ==> 0XF8006050[19:19] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */
+ /* .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 */
+ /* .. .. ==> 0XF8006050[27:24] = 0x00000007U */
+ /* .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U */
+ /* .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 */
+ /* .. .. ==> 0XF8006050[31:28] = 0x00000007U */
+ /* .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU, 0x77010800U),
+ /* .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1 */
+ /* .. .. ==> 0XF8006058[7:0] = 0x00000001U */
+ /* .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U */
+ /* .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1 */
+ /* .. .. ==> 0XF8006058[15:8] = 0x00000001U */
+ /* .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U */
+ /* .. .. reg_ddrc_dis_dll_calib = 0x0 */
+ /* .. .. ==> 0XF8006058[16:16] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU, 0x00000101U),
+ /* .. .. reg_ddrc_rd_odt_delay = 0x3 */
+ /* .. .. ==> 0XF800605C[3:0] = 0x00000003U */
+ /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U */
+ /* .. .. reg_ddrc_wr_odt_delay = 0x0 */
+ /* .. .. ==> 0XF800605C[7:4] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_rd_odt_hold = 0x0 */
+ /* .. .. ==> 0XF800605C[11:8] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_wr_odt_hold = 0x5 */
+ /* .. .. ==> 0XF800605C[15:12] = 0x00000005U */
+ /* .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU, 0x00005003U),
+ /* .. .. reg_ddrc_pageclose = 0x0 */
+ /* .. .. ==> 0XF8006060[0:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_lpr_num_entries = 0x1f */
+ /* .. .. ==> 0XF8006060[6:1] = 0x0000001FU */
+ /* .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU */
+ /* .. .. reg_ddrc_auto_pre_en = 0x0 */
+ /* .. .. ==> 0XF8006060[7:7] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000080U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_refresh_update_level = 0x0 */
+ /* .. .. ==> 0XF8006060[8:8] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_dis_wc = 0x0 */
+ /* .. .. ==> 0XF8006060[9:9] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000200U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_dis_collision_page_opt = 0x0 */
+ /* .. .. ==> 0XF8006060[10:10] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_selfref_en = 0x0 */
+ /* .. .. ==> 0XF8006060[12:12] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006060, 0x000017FFU, 0x0000003EU),
+ /* .. .. reg_ddrc_go2critical_hysteresis = 0x0 */
+ /* .. .. ==> 0XF8006064[12:5] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U */
+ /* .. .. reg_arb_go2critical_en = 0x1 */
+ /* .. .. ==> 0XF8006064[17:17] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00020000U VAL : 0x00020000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006064, 0x00021FE0U, 0x00020000U),
+ /* .. .. reg_ddrc_wrlvl_ww = 0x41 */
+ /* .. .. ==> 0XF8006068[7:0] = 0x00000041U */
+ /* .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U */
+ /* .. .. reg_ddrc_rdlvl_rr = 0x41 */
+ /* .. .. ==> 0XF8006068[15:8] = 0x00000041U */
+ /* .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U */
+ /* .. .. reg_ddrc_dfi_t_wlmrd = 0x28 */
+ /* .. .. ==> 0XF8006068[25:16] = 0x00000028U */
+ /* .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU, 0x00284141U),
+ /* .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 */
+ /* .. .. ==> 0XF800606C[7:0] = 0x00000010U */
+ /* .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U */
+ /* .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 */
+ /* .. .. ==> 0XF800606C[15:8] = 0x00000016U */
+ /* .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU, 0x00001610U),
+ /* .. .. refresh_timer0_start_value_x32 = 0x0 */
+ /* .. .. ==> 0XF80060A0[11:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U */
+ /* .. .. refresh_timer1_start_value_x32 = 0x8 */
+ /* .. .. ==> 0XF80060A0[23:12] = 0x00000008U */
+ /* .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU, 0x00008000U),
+ /* .. .. reg_ddrc_dis_auto_zq = 0x0 */
+ /* .. .. ==> 0XF80060A4[0:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_ddr3 = 0x1 */
+ /* .. .. ==> 0XF80060A4[1:1] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. .. reg_ddrc_t_mod = 0x200 */
+ /* .. .. ==> 0XF80060A4[11:2] = 0x00000200U */
+ /* .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U */
+ /* .. .. reg_ddrc_t_zq_long_nop = 0x200 */
+ /* .. .. ==> 0XF80060A4[21:12] = 0x00000200U */
+ /* .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U */
+ /* .. .. reg_ddrc_t_zq_short_nop = 0x40 */
+ /* .. .. ==> 0XF80060A4[31:22] = 0x00000040U */
+ /* .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U),
+ /* .. .. t_zq_short_interval_x1024 = 0xc845 */
+ /* .. .. ==> 0XF80060A8[19:0] = 0x0000C845U */
+ /* .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000C845U */
+ /* .. .. dram_rstn_x1024 = 0x67 */
+ /* .. .. ==> 0XF80060A8[27:20] = 0x00000067U */
+ /* .. .. ==> MASK : 0x0FF00000U VAL : 0x06700000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0670C845U),
+ /* .. .. deeppowerdown_en = 0x0 */
+ /* .. .. ==> 0XF80060AC[0:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. .. deeppowerdown_to_x1024 = 0xff */
+ /* .. .. ==> 0XF80060AC[8:1] = 0x000000FFU */
+ /* .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU),
+ /* .. .. dfi_wrlvl_max_x1024 = 0xfff */
+ /* .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU */
+ /* .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU */
+ /* .. .. dfi_rdlvl_max_x1024 = 0xfff */
+ /* .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU */
+ /* .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U */
+ /* .. .. ddrc_reg_twrlvl_max_error = 0x0 */
+ /* .. .. ==> 0XF80060B0[24:24] = 0x00000000U */
+ /* .. .. ==> MASK : 0x01000000U VAL : 0x00000000U */
+ /* .. .. ddrc_reg_trdlvl_max_error = 0x0 */
+ /* .. .. ==> 0XF80060B0[25:25] = 0x00000000U */
+ /* .. .. ==> MASK : 0x02000000U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_dfi_wr_level_en = 0x1 */
+ /* .. .. ==> 0XF80060B0[26:26] = 0x00000001U */
+ /* .. .. ==> MASK : 0x04000000U VAL : 0x04000000U */
+ /* .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 */
+ /* .. .. ==> 0XF80060B0[27:27] = 0x00000001U */
+ /* .. .. ==> MASK : 0x08000000U VAL : 0x08000000U */
+ /* .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 */
+ /* .. .. ==> 0XF80060B0[28:28] = 0x00000001U */
+ /* .. .. ==> MASK : 0x10000000U VAL : 0x10000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+ /* .. .. reg_ddrc_2t_delay = 0x0 */
+ /* .. .. ==> 0XF80060B4[8:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U */
+ /* .. .. reg_ddrc_skip_ocd = 0x1 */
+ /* .. .. ==> 0XF80060B4[9:9] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000200U VAL : 0x00000200U */
+ /* .. .. reg_ddrc_dis_pre_bypass = 0x0 */
+ /* .. .. ==> 0XF80060B4[10:10] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF80060B4, 0x000007FFU, 0x00000200U),
+ /* .. .. reg_ddrc_dfi_t_rddata_en = 0x6 */
+ /* .. .. ==> 0XF80060B8[4:0] = 0x00000006U */
+ /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U */
+ /* .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 */
+ /* .. .. ==> 0XF80060B8[14:5] = 0x00000003U */
+ /* .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U */
+ /* .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 */
+ /* .. .. ==> 0XF80060B8[24:15] = 0x00000040U */
+ /* .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU, 0x00200066U),
+ /* .. .. START: RESET ECC ERROR */
+ /* .. .. Clear_Uncorrectable_DRAM_ECC_error = 1 */
+ /* .. .. ==> 0XF80060C4[0:0] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. .. Clear_Correctable_DRAM_ECC_error = 1 */
+ /* .. .. ==> 0XF80060C4[1:1] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000003U),
+ /* .. .. FINISH: RESET ECC ERROR */
+ /* .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 */
+ /* .. .. ==> 0XF80060C4[0:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. .. Clear_Correctable_DRAM_ECC_error = 0x0 */
+ /* .. .. ==> 0XF80060C4[1:1] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000000U),
+ /* .. .. CORR_ECC_LOG_VALID = 0x0 */
+ /* .. .. ==> 0XF80060C8[0:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. .. ECC_CORRECTED_BIT_NUM = 0x0 */
+ /* .. .. ==> 0XF80060C8[7:1] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF80060C8, 0x000000FFU, 0x00000000U),
+ /* .. .. UNCORR_ECC_LOG_VALID = 0x0 */
+ /* .. .. ==> 0XF80060DC[0:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF80060DC, 0x00000001U, 0x00000000U),
+ /* .. .. STAT_NUM_CORR_ERR = 0x0 */
+ /* .. .. ==> 0XF80060F0[15:8] = 0x00000000U */
+ /* .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U */
+ /* .. .. STAT_NUM_UNCORR_ERR = 0x0 */
+ /* .. .. ==> 0XF80060F0[7:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU, 0x00000000U),
+ /* .. .. reg_ddrc_ecc_mode = 0x0 */
+ /* .. .. ==> 0XF80060F4[2:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000007U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_dis_scrub = 0x1 */
+ /* .. .. ==> 0XF80060F4[3:3] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000008U VAL : 0x00000008U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF80060F4, 0x0000000FU, 0x00000008U),
+ /* .. .. reg_phy_dif_on = 0x0 */
+ /* .. .. ==> 0XF8006114[3:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U */
+ /* .. .. reg_phy_dif_off = 0x0 */
+ /* .. .. ==> 0XF8006114[7:4] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006114, 0x000000FFU, 0x00000000U),
+ /* .. .. reg_phy_data_slice_in_use = 0x1 */
+ /* .. .. ==> 0XF8006118[0:0] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
+ /* .. .. ==> 0XF8006118[1:1] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
+ /* .. .. ==> 0XF8006118[2:2] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
+ /* .. .. ==> 0XF8006118[3:3] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */
+ /* .. .. reg_phy_board_lpbk_tx = 0x0 */
+ /* .. .. ==> 0XF8006118[4:4] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
+ /* .. .. reg_phy_board_lpbk_rx = 0x0 */
+ /* .. .. ==> 0XF8006118[5:5] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000020U VAL : 0x00000000U */
+ /* .. .. reg_phy_bist_shift_dq = 0x0 */
+ /* .. .. ==> 0XF8006118[14:6] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */
+ /* .. .. reg_phy_bist_err_clr = 0x0 */
+ /* .. .. ==> 0XF8006118[23:15] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */
+ /* .. .. reg_phy_dq_offset = 0x40 */
+ /* .. .. ==> 0XF8006118[30:24] = 0x00000040U */
+ /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU, 0x40000001U),
+ /* .. .. reg_phy_data_slice_in_use = 0x1 */
+ /* .. .. ==> 0XF800611C[0:0] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
+ /* .. .. ==> 0XF800611C[1:1] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
+ /* .. .. ==> 0XF800611C[2:2] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
+ /* .. .. ==> 0XF800611C[3:3] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */
+ /* .. .. reg_phy_board_lpbk_tx = 0x0 */
+ /* .. .. ==> 0XF800611C[4:4] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
+ /* .. .. reg_phy_board_lpbk_rx = 0x0 */
+ /* .. .. ==> 0XF800611C[5:5] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000020U VAL : 0x00000000U */
+ /* .. .. reg_phy_bist_shift_dq = 0x0 */
+ /* .. .. ==> 0XF800611C[14:6] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */
+ /* .. .. reg_phy_bist_err_clr = 0x0 */
+ /* .. .. ==> 0XF800611C[23:15] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */
+ /* .. .. reg_phy_dq_offset = 0x40 */
+ /* .. .. ==> 0XF800611C[30:24] = 0x00000040U */
+ /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU, 0x40000001U),
+ /* .. .. reg_phy_data_slice_in_use = 0x1 */
+ /* .. .. ==> 0XF8006120[0:0] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
+ /* .. .. ==> 0XF8006120[1:1] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
+ /* .. .. ==> 0XF8006120[2:2] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
+ /* .. .. ==> 0XF8006120[3:3] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */
+ /* .. .. reg_phy_board_lpbk_tx = 0x0 */
+ /* .. .. ==> 0XF8006120[4:4] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
+ /* .. .. reg_phy_board_lpbk_rx = 0x0 */
+ /* .. .. ==> 0XF8006120[5:5] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000020U VAL : 0x00000000U */
+ /* .. .. reg_phy_bist_shift_dq = 0x0 */
+ /* .. .. ==> 0XF8006120[14:6] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */
+ /* .. .. reg_phy_bist_err_clr = 0x0 */
+ /* .. .. ==> 0XF8006120[23:15] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */
+ /* .. .. reg_phy_dq_offset = 0x40 */
+ /* .. .. ==> 0XF8006120[30:24] = 0x00000040U */
+ /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU, 0x40000001U),
+ /* .. .. reg_phy_data_slice_in_use = 0x1 */
+ /* .. .. ==> 0XF8006124[0:0] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
+ /* .. .. ==> 0XF8006124[1:1] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
+ /* .. .. ==> 0XF8006124[2:2] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
+ /* .. .. ==> 0XF8006124[3:3] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */
+ /* .. .. reg_phy_board_lpbk_tx = 0x0 */
+ /* .. .. ==> 0XF8006124[4:4] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
+ /* .. .. reg_phy_board_lpbk_rx = 0x0 */
+ /* .. .. ==> 0XF8006124[5:5] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000020U VAL : 0x00000000U */
+ /* .. .. reg_phy_bist_shift_dq = 0x0 */
+ /* .. .. ==> 0XF8006124[14:6] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */
+ /* .. .. reg_phy_bist_err_clr = 0x0 */
+ /* .. .. ==> 0XF8006124[23:15] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */
+ /* .. .. reg_phy_dq_offset = 0x40 */
+ /* .. .. ==> 0XF8006124[30:24] = 0x00000040U */
+ /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU, 0x40000001U),
+ /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
+ /* .. .. ==> 0XF800612C[9:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */
+ /* .. .. reg_phy_gatelvl_init_ratio = 0x8f */
+ /* .. .. ==> 0XF800612C[19:10] = 0x0000008FU */
+ /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00023C00U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU, 0x00023C00U),
+ /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
+ /* .. .. ==> 0XF8006130[9:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */
+ /* .. .. reg_phy_gatelvl_init_ratio = 0x8a */
+ /* .. .. ==> 0XF8006130[19:10] = 0x0000008AU */
+ /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00022800U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU, 0x00022800U),
+ /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
+ /* .. .. ==> 0XF8006134[9:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */
+ /* .. .. reg_phy_gatelvl_init_ratio = 0x8b */
+ /* .. .. ==> 0XF8006134[19:10] = 0x0000008BU */
+ /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00022C00U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU, 0x00022C00U),
+ /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
+ /* .. .. ==> 0XF8006138[9:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */
+ /* .. .. reg_phy_gatelvl_init_ratio = 0x92 */
+ /* .. .. ==> 0XF8006138[19:10] = 0x00000092U */
+ /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00024800U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU, 0x00024800U),
+ /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
+ /* .. .. ==> 0XF8006140[9:0] = 0x00000035U */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */
+ /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
+ /* .. .. ==> 0XF8006140[10:10] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
+ /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
+ /* .. .. ==> 0XF8006140[19:11] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU, 0x00000035U),
+ /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
+ /* .. .. ==> 0XF8006144[9:0] = 0x00000035U */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */
+ /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
+ /* .. .. ==> 0XF8006144[10:10] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
+ /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
+ /* .. .. ==> 0XF8006144[19:11] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU, 0x00000035U),
+ /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
+ /* .. .. ==> 0XF8006148[9:0] = 0x00000035U */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */
+ /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
+ /* .. .. ==> 0XF8006148[10:10] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
+ /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
+ /* .. .. ==> 0XF8006148[19:11] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU, 0x00000035U),
+ /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
+ /* .. .. ==> 0XF800614C[9:0] = 0x00000035U */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */
+ /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
+ /* .. .. ==> 0XF800614C[10:10] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
+ /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
+ /* .. .. ==> 0XF800614C[19:11] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU, 0x00000035U),
+ /* .. .. reg_phy_wr_dqs_slave_ratio = 0x77 */
+ /* .. .. ==> 0XF8006154[9:0] = 0x00000077U */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000077U */
+ /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
+ /* .. .. ==> 0XF8006154[10:10] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
+ /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
+ /* .. .. ==> 0XF8006154[19:11] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU, 0x00000077U),
+ /* .. .. reg_phy_wr_dqs_slave_ratio = 0x7c */
+ /* .. .. ==> 0XF8006158[9:0] = 0x0000007CU */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU */
+ /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
+ /* .. .. ==> 0XF8006158[10:10] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
+ /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
+ /* .. .. ==> 0XF8006158[19:11] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU, 0x0000007CU),
+ /* .. .. reg_phy_wr_dqs_slave_ratio = 0x7c */
+ /* .. .. ==> 0XF800615C[9:0] = 0x0000007CU */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU */
+ /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
+ /* .. .. ==> 0XF800615C[10:10] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
+ /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
+ /* .. .. ==> 0XF800615C[19:11] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU, 0x0000007CU),
+ /* .. .. reg_phy_wr_dqs_slave_ratio = 0x75 */
+ /* .. .. ==> 0XF8006160[9:0] = 0x00000075U */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000075U */
+ /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
+ /* .. .. ==> 0XF8006160[10:10] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
+ /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
+ /* .. .. ==> 0XF8006160[19:11] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU, 0x00000075U),
+ /* .. .. reg_phy_fifo_we_slave_ratio = 0xe4 */
+ /* .. .. ==> 0XF8006168[10:0] = 0x000000E4U */
+ /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000E4U */
+ /* .. .. reg_phy_fifo_we_in_force = 0x0 */
+ /* .. .. ==> 0XF8006168[11:11] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */
+ /* .. .. reg_phy_fifo_we_in_delay = 0x0 */
+ /* .. .. ==> 0XF8006168[20:12] = 0x00000000U */
+ /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU, 0x000000E4U),
+ /* .. .. reg_phy_fifo_we_slave_ratio = 0xdf */
+ /* .. .. ==> 0XF800616C[10:0] = 0x000000DFU */
+ /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000DFU */
+ /* .. .. reg_phy_fifo_we_in_force = 0x0 */
+ /* .. .. ==> 0XF800616C[11:11] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */
+ /* .. .. reg_phy_fifo_we_in_delay = 0x0 */
+ /* .. .. ==> 0XF800616C[20:12] = 0x00000000U */
+ /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU, 0x000000DFU),
+ /* .. .. reg_phy_fifo_we_slave_ratio = 0xe0 */
+ /* .. .. ==> 0XF8006170[10:0] = 0x000000E0U */
+ /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000E0U */
+ /* .. .. reg_phy_fifo_we_in_force = 0x0 */
+ /* .. .. ==> 0XF8006170[11:11] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */
+ /* .. .. reg_phy_fifo_we_in_delay = 0x0 */
+ /* .. .. ==> 0XF8006170[20:12] = 0x00000000U */
+ /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU, 0x000000E0U),
+ /* .. .. reg_phy_fifo_we_slave_ratio = 0xe7 */
+ /* .. .. ==> 0XF8006174[10:0] = 0x000000E7U */
+ /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000E7U */
+ /* .. .. reg_phy_fifo_we_in_force = 0x0 */
+ /* .. .. ==> 0XF8006174[11:11] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */
+ /* .. .. reg_phy_fifo_we_in_delay = 0x0 */
+ /* .. .. ==> 0XF8006174[20:12] = 0x00000000U */
+ /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU, 0x000000E7U),
+ /* .. .. reg_phy_wr_data_slave_ratio = 0xb7 */
+ /* .. .. ==> 0XF800617C[9:0] = 0x000000B7U */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000B7U */
+ /* .. .. reg_phy_wr_data_slave_force = 0x0 */
+ /* .. .. ==> 0XF800617C[10:10] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
+ /* .. .. reg_phy_wr_data_slave_delay = 0x0 */
+ /* .. .. ==> 0XF800617C[19:11] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU, 0x000000B7U),
+ /* .. .. reg_phy_wr_data_slave_ratio = 0xbc */
+ /* .. .. ==> 0XF8006180[9:0] = 0x000000BCU */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU */
+ /* .. .. reg_phy_wr_data_slave_force = 0x0 */
+ /* .. .. ==> 0XF8006180[10:10] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
+ /* .. .. reg_phy_wr_data_slave_delay = 0x0 */
+ /* .. .. ==> 0XF8006180[19:11] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU, 0x000000BCU),
+ /* .. .. reg_phy_wr_data_slave_ratio = 0xbc */
+ /* .. .. ==> 0XF8006184[9:0] = 0x000000BCU */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU */
+ /* .. .. reg_phy_wr_data_slave_force = 0x0 */
+ /* .. .. ==> 0XF8006184[10:10] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
+ /* .. .. reg_phy_wr_data_slave_delay = 0x0 */
+ /* .. .. ==> 0XF8006184[19:11] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU, 0x000000BCU),
+ /* .. .. reg_phy_wr_data_slave_ratio = 0xb5 */
+ /* .. .. ==> 0XF8006188[9:0] = 0x000000B5U */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000B5U */
+ /* .. .. reg_phy_wr_data_slave_force = 0x0 */
+ /* .. .. ==> 0XF8006188[10:10] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
+ /* .. .. reg_phy_wr_data_slave_delay = 0x0 */
+ /* .. .. ==> 0XF8006188[19:11] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU, 0x000000B5U),
+ /* .. .. reg_phy_loopback = 0x0 */
+ /* .. .. ==> 0XF8006190[0:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. .. reg_phy_bl2 = 0x0 */
+ /* .. .. ==> 0XF8006190[1:1] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. .. reg_phy_at_spd_atpg = 0x0 */
+ /* .. .. ==> 0XF8006190[2:2] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. .. reg_phy_bist_enable = 0x0 */
+ /* .. .. ==> 0XF8006190[3:3] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */
+ /* .. .. reg_phy_bist_force_err = 0x0 */
+ /* .. .. ==> 0XF8006190[4:4] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
+ /* .. .. reg_phy_bist_mode = 0x0 */
+ /* .. .. ==> 0XF8006190[6:5] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000060U VAL : 0x00000000U */
+ /* .. .. reg_phy_invert_clkout = 0x1 */
+ /* .. .. ==> 0XF8006190[7:7] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000080U VAL : 0x00000080U */
+ /* .. .. reg_phy_all_dq_mpr_rd_resp = 0x0 */
+ /* .. .. ==> 0XF8006190[8:8] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. .. reg_phy_sel_logic = 0x0 */
+ /* .. .. ==> 0XF8006190[9:9] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000200U VAL : 0x00000000U */
+ /* .. .. reg_phy_ctrl_slave_ratio = 0x100 */
+ /* .. .. ==> 0XF8006190[19:10] = 0x00000100U */
+ /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U */
+ /* .. .. reg_phy_ctrl_slave_force = 0x0 */
+ /* .. .. ==> 0XF8006190[20:20] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00100000U VAL : 0x00000000U */
+ /* .. .. reg_phy_ctrl_slave_delay = 0x0 */
+ /* .. .. ==> 0XF8006190[27:21] = 0x00000000U */
+ /* .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U */
+ /* .. .. reg_phy_use_rank0_delays = 0x1 */
+ /* .. .. ==> 0XF8006190[28:28] = 0x00000001U */
+ /* .. .. ==> MASK : 0x10000000U VAL : 0x10000000U */
+ /* .. .. reg_phy_lpddr = 0x0 */
+ /* .. .. ==> 0XF8006190[29:29] = 0x00000000U */
+ /* .. .. ==> MASK : 0x20000000U VAL : 0x00000000U */
+ /* .. .. reg_phy_cmd_latency = 0x0 */
+ /* .. .. ==> 0XF8006190[30:30] = 0x00000000U */
+ /* .. .. ==> MASK : 0x40000000U VAL : 0x00000000U */
+ /* .. .. reg_phy_int_lpbk = 0x0 */
+ /* .. .. ==> 0XF8006190[31:31] = 0x00000000U */
+ /* .. .. ==> MASK : 0x80000000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU, 0x10040080U),
+ /* .. .. reg_phy_wr_rl_delay = 0x2 */
+ /* .. .. ==> 0XF8006194[4:0] = 0x00000002U */
+ /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U */
+ /* .. .. reg_phy_rd_rl_delay = 0x4 */
+ /* .. .. ==> 0XF8006194[9:5] = 0x00000004U */
+ /* .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U */
+ /* .. .. reg_phy_dll_lock_diff = 0xf */
+ /* .. .. ==> 0XF8006194[13:10] = 0x0000000FU */
+ /* .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U */
+ /* .. .. reg_phy_use_wr_level = 0x1 */
+ /* .. .. ==> 0XF8006194[14:14] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00004000U VAL : 0x00004000U */
+ /* .. .. reg_phy_use_rd_dqs_gate_level = 0x1 */
+ /* .. .. ==> 0XF8006194[15:15] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00008000U VAL : 0x00008000U */
+ /* .. .. reg_phy_use_rd_data_eye_level = 0x1 */
+ /* .. .. ==> 0XF8006194[16:16] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00010000U VAL : 0x00010000U */
+ /* .. .. reg_phy_dis_calib_rst = 0x0 */
+ /* .. .. ==> 0XF8006194[17:17] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
+ /* .. .. reg_phy_ctrl_slave_delay = 0x0 */
+ /* .. .. ==> 0XF8006194[19:18] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU, 0x0001FC82U),
+ /* .. .. reg_arb_page_addr_mask = 0x0 */
+ /* .. .. ==> 0XF8006204[31:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU, 0x00000000U),
+ /* .. .. reg_arb_pri_wr_portn = 0x3ff */
+ /* .. .. ==> 0XF8006208[9:0] = 0x000003FFU */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
+ /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
+ /* .. .. ==> 0XF8006208[16:16] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
+ /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
+ /* .. .. ==> 0XF8006208[17:17] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
+ /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
+ /* .. .. ==> 0XF8006208[18:18] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
+ /* .. .. reg_arb_dis_rmw_portn = 0x1 */
+ /* .. .. ==> 0XF8006208[19:19] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00080000U VAL : 0x00080000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006208, 0x000F03FFU, 0x000803FFU),
+ /* .. .. reg_arb_pri_wr_portn = 0x3ff */
+ /* .. .. ==> 0XF800620C[9:0] = 0x000003FFU */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
+ /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
+ /* .. .. ==> 0XF800620C[16:16] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
+ /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
+ /* .. .. ==> 0XF800620C[17:17] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
+ /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
+ /* .. .. ==> 0XF800620C[18:18] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
+ /* .. .. reg_arb_dis_rmw_portn = 0x1 */
+ /* .. .. ==> 0XF800620C[19:19] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00080000U VAL : 0x00080000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF800620C, 0x000F03FFU, 0x000803FFU),
+ /* .. .. reg_arb_pri_wr_portn = 0x3ff */
+ /* .. .. ==> 0XF8006210[9:0] = 0x000003FFU */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
+ /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
+ /* .. .. ==> 0XF8006210[16:16] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
+ /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
+ /* .. .. ==> 0XF8006210[17:17] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
+ /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
+ /* .. .. ==> 0XF8006210[18:18] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
+ /* .. .. reg_arb_dis_rmw_portn = 0x1 */
+ /* .. .. ==> 0XF8006210[19:19] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00080000U VAL : 0x00080000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006210, 0x000F03FFU, 0x000803FFU),
+ /* .. .. reg_arb_pri_wr_portn = 0x3ff */
+ /* .. .. ==> 0XF8006214[9:0] = 0x000003FFU */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
+ /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
+ /* .. .. ==> 0XF8006214[16:16] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
+ /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
+ /* .. .. ==> 0XF8006214[17:17] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
+ /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
+ /* .. .. ==> 0XF8006214[18:18] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
+ /* .. .. reg_arb_dis_rmw_portn = 0x1 */
+ /* .. .. ==> 0XF8006214[19:19] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00080000U VAL : 0x00080000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006214, 0x000F03FFU, 0x000803FFU),
+ /* .. .. reg_arb_pri_rd_portn = 0x3ff */
+ /* .. .. ==> 0XF8006218[9:0] = 0x000003FFU */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
+ /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
+ /* .. .. ==> 0XF8006218[16:16] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
+ /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
+ /* .. .. ==> 0XF8006218[17:17] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
+ /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
+ /* .. .. ==> 0XF8006218[18:18] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
+ /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
+ /* .. .. ==> 0XF8006218[19:19] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006218, 0x000F03FFU, 0x000003FFU),
+ /* .. .. reg_arb_pri_rd_portn = 0x3ff */
+ /* .. .. ==> 0XF800621C[9:0] = 0x000003FFU */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
+ /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
+ /* .. .. ==> 0XF800621C[16:16] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
+ /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
+ /* .. .. ==> 0XF800621C[17:17] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
+ /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
+ /* .. .. ==> 0XF800621C[18:18] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
+ /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
+ /* .. .. ==> 0XF800621C[19:19] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF800621C, 0x000F03FFU, 0x000003FFU),
+ /* .. .. reg_arb_pri_rd_portn = 0x3ff */
+ /* .. .. ==> 0XF8006220[9:0] = 0x000003FFU */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
+ /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
+ /* .. .. ==> 0XF8006220[16:16] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
+ /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
+ /* .. .. ==> 0XF8006220[17:17] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
+ /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
+ /* .. .. ==> 0XF8006220[18:18] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
+ /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
+ /* .. .. ==> 0XF8006220[19:19] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006220, 0x000F03FFU, 0x000003FFU),
+ /* .. .. reg_arb_pri_rd_portn = 0x3ff */
+ /* .. .. ==> 0XF8006224[9:0] = 0x000003FFU */
+ /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
+ /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
+ /* .. .. ==> 0XF8006224[16:16] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
+ /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
+ /* .. .. ==> 0XF8006224[17:17] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
+ /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
+ /* .. .. ==> 0XF8006224[18:18] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
+ /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
+ /* .. .. ==> 0XF8006224[19:19] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006224, 0x000F03FFU, 0x000003FFU),
+ /* .. .. reg_ddrc_lpddr2 = 0x0 */
+ /* .. .. ==> 0XF80062A8[0:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_per_bank_refresh = 0x0 */
+ /* .. .. ==> 0XF80062A8[1:1] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_derate_enable = 0x0 */
+ /* .. .. ==> 0XF80062A8[2:2] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_mr4_margin = 0x0 */
+ /* .. .. ==> 0XF80062A8[11:4] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U, 0x00000000U),
+ /* .. .. reg_ddrc_mr4_read_interval = 0x0 */
+ /* .. .. ==> 0XF80062AC[31:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU, 0x00000000U),
+ /* .. .. reg_ddrc_min_stable_clock_x1 = 0x5 */
+ /* .. .. ==> 0XF80062B0[3:0] = 0x00000005U */
+ /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U */
+ /* .. .. reg_ddrc_idle_after_reset_x32 = 0x12 */
+ /* .. .. ==> 0XF80062B0[11:4] = 0x00000012U */
+ /* .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U */
+ /* .. .. reg_ddrc_t_mrw = 0x5 */
+ /* .. .. ==> 0XF80062B0[21:12] = 0x00000005U */
+ /* .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU, 0x00005125U),
+ /* .. .. reg_ddrc_max_auto_init_x1024 = 0xa6 */
+ /* .. .. ==> 0XF80062B4[7:0] = 0x000000A6U */
+ /* .. .. ==> MASK : 0x000000FFU VAL : 0x000000A6U */
+ /* .. .. reg_ddrc_dev_zqinit_x32 = 0x12 */
+ /* .. .. ==> 0XF80062B4[17:8] = 0x00000012U */
+ /* .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU, 0x000012A6U),
+ /* .. .. START: POLL ON DCI STATUS */
+ /* .. .. DONE = 1 */
+ /* .. .. ==> 0XF8000B74[13:13] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00002000U VAL : 0x00002000U */
+ /* .. .. */
+ EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+ /* .. .. FINISH: POLL ON DCI STATUS */
+ /* .. .. START: UNLOCK DDR */
+ /* .. .. reg_ddrc_soft_rstb = 0x1 */
+ /* .. .. ==> 0XF8006000[0:0] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. .. reg_ddrc_powerdown_en = 0x0 */
+ /* .. .. ==> 0XF8006000[1:1] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_data_bus_width = 0x0 */
+ /* .. .. ==> 0XF8006000[3:2] = 0x00000000U */
+ /* .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U */
+ /* .. .. reg_ddrc_burst8_refresh = 0x0 */
+ /* .. .. ==> 0XF8006000[6:4] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000070U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_rdwr_idle_gap = 1 */
+ /* .. .. ==> 0XF8006000[13:7] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U */
+ /* .. .. reg_ddrc_dis_rd_bypass = 0x0 */
+ /* .. .. ==> 0XF8006000[14:14] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00004000U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_dis_act_bypass = 0x0 */
+ /* .. .. ==> 0XF8006000[15:15] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */
+ /* .. .. reg_ddrc_dis_auto_refresh = 0x0 */
+ /* .. .. ==> 0XF8006000[16:16] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000081U),
+ /* .. .. FINISH: UNLOCK DDR */
+ /* .. .. START: CHECK DDR STATUS */
+ /* .. .. ddrc_reg_operating_mode = 1 */
+ /* .. .. ==> 0XF8006054[2:0] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000007U VAL : 0x00000001U */
+ /* .. .. */
+ EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+ /* .. .. FINISH: CHECK DDR STATUS */
+ /* .. FINISH: DDR INITIALIZATION */
+ /* FINISH: top */
+ /* */
+ EMIT_EXIT(),
+
+ /* */
+};
+
+unsigned long ps7_mio_init_data_1_0[] = {
+ /* START: top */
+ /* .. START: SLCR SETTINGS */
+ /* .. UNLOCK_KEY = 0XDF0D */
+ /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
+ /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ /* .. FINISH: SLCR SETTINGS */
+ /* .. START: OCM REMAPPING */
+ /* .. VREF_EN = 0x1 */
+ /* .. ==> 0XF8000B00[0:0] = 0x00000001U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. VREF_PULLUP_EN = 0x0 */
+ /* .. ==> 0XF8000B00[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. CLK_PULLUP_EN = 0x0 */
+ /* .. ==> 0XF8000B00[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. SRSTN_PULLUP_EN = 0x0 */
+ /* .. ==> 0XF8000B00[9:9] = 0x00000000U */
+ /* .. ==> MASK : 0x00000200U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000B00, 0x00000303U, 0x00000001U),
+ /* .. FINISH: OCM REMAPPING */
+ /* .. START: DDRIOB SETTINGS */
+ /* .. INP_POWER = 0x0 */
+ /* .. ==> 0XF8000B40[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. INP_TYPE = 0x0 */
+ /* .. ==> 0XF8000B40[2:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */
+ /* .. DCI_UPDATE = 0x0 */
+ /* .. ==> 0XF8000B40[3:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
+ /* .. TERM_EN = 0x0 */
+ /* .. ==> 0XF8000B40[4:4] = 0x00000000U */
+ /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */
+ /* .. DCR_TYPE = 0x0 */
+ /* .. ==> 0XF8000B40[6:5] = 0x00000000U */
+ /* .. ==> MASK : 0x00000060U VAL : 0x00000000U */
+ /* .. IBUF_DISABLE_MODE = 0x0 */
+ /* .. ==> 0XF8000B40[7:7] = 0x00000000U */
+ /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
+ /* .. TERM_DISABLE_MODE = 0x0 */
+ /* .. ==> 0XF8000B40[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. OUTPUT_EN = 0x3 */
+ /* .. ==> 0XF8000B40[10:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
+ /* .. PULLUP_EN = 0x0 */
+ /* .. ==> 0XF8000B40[11:11] = 0x00000000U */
+ /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU, 0x00000600U),
+ /* .. INP_POWER = 0x0 */
+ /* .. ==> 0XF8000B44[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. INP_TYPE = 0x0 */
+ /* .. ==> 0XF8000B44[2:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */
+ /* .. DCI_UPDATE = 0x0 */
+ /* .. ==> 0XF8000B44[3:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
+ /* .. TERM_EN = 0x0 */
+ /* .. ==> 0XF8000B44[4:4] = 0x00000000U */
+ /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */
+ /* .. DCR_TYPE = 0x0 */
+ /* .. ==> 0XF8000B44[6:5] = 0x00000000U */
+ /* .. ==> MASK : 0x00000060U VAL : 0x00000000U */
+ /* .. IBUF_DISABLE_MODE = 0x0 */
+ /* .. ==> 0XF8000B44[7:7] = 0x00000000U */
+ /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
+ /* .. TERM_DISABLE_MODE = 0x0 */
+ /* .. ==> 0XF8000B44[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. OUTPUT_EN = 0x3 */
+ /* .. ==> 0XF8000B44[10:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
+ /* .. PULLUP_EN = 0x0 */
+ /* .. ==> 0XF8000B44[11:11] = 0x00000000U */
+ /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU, 0x00000600U),
+ /* .. INP_POWER = 0x0 */
+ /* .. ==> 0XF8000B48[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. INP_TYPE = 0x1 */
+ /* .. ==> 0XF8000B48[2:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000006U VAL : 0x00000002U */
+ /* .. DCI_UPDATE = 0x0 */
+ /* .. ==> 0XF8000B48[3:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
+ /* .. TERM_EN = 0x1 */
+ /* .. ==> 0XF8000B48[4:4] = 0x00000001U */
+ /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */
+ /* .. DCR_TYPE = 0x3 */
+ /* .. ==> 0XF8000B48[6:5] = 0x00000003U */
+ /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */
+ /* .. IBUF_DISABLE_MODE = 0 */
+ /* .. ==> 0XF8000B48[7:7] = 0x00000000U */
+ /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
+ /* .. TERM_DISABLE_MODE = 0 */
+ /* .. ==> 0XF8000B48[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. OUTPUT_EN = 0x3 */
+ /* .. ==> 0XF8000B48[10:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
+ /* .. PULLUP_EN = 0x0 */
+ /* .. ==> 0XF8000B48[11:11] = 0x00000000U */
+ /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU, 0x00000672U),
+ /* .. INP_POWER = 0x0 */
+ /* .. ==> 0XF8000B4C[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. INP_TYPE = 0x1 */
+ /* .. ==> 0XF8000B4C[2:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000006U VAL : 0x00000002U */
+ /* .. DCI_UPDATE = 0x0 */
+ /* .. ==> 0XF8000B4C[3:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
+ /* .. TERM_EN = 0x1 */
+ /* .. ==> 0XF8000B4C[4:4] = 0x00000001U */
+ /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */
+ /* .. DCR_TYPE = 0x3 */
+ /* .. ==> 0XF8000B4C[6:5] = 0x00000003U */
+ /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */
+ /* .. IBUF_DISABLE_MODE = 0 */
+ /* .. ==> 0XF8000B4C[7:7] = 0x00000000U */
+ /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
+ /* .. TERM_DISABLE_MODE = 0 */
+ /* .. ==> 0XF8000B4C[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. OUTPUT_EN = 0x3 */
+ /* .. ==> 0XF8000B4C[10:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
+ /* .. PULLUP_EN = 0x0 */
+ /* .. ==> 0XF8000B4C[11:11] = 0x00000000U */
+ /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU, 0x00000672U),
+ /* .. INP_POWER = 0x0 */
+ /* .. ==> 0XF8000B50[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. INP_TYPE = 0x2 */
+ /* .. ==> 0XF8000B50[2:1] = 0x00000002U */
+ /* .. ==> MASK : 0x00000006U VAL : 0x00000004U */
+ /* .. DCI_UPDATE = 0x0 */
+ /* .. ==> 0XF8000B50[3:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
+ /* .. TERM_EN = 0x1 */
+ /* .. ==> 0XF8000B50[4:4] = 0x00000001U */
+ /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */
+ /* .. DCR_TYPE = 0x3 */
+ /* .. ==> 0XF8000B50[6:5] = 0x00000003U */
+ /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */
+ /* .. IBUF_DISABLE_MODE = 0 */
+ /* .. ==> 0XF8000B50[7:7] = 0x00000000U */
+ /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
+ /* .. TERM_DISABLE_MODE = 0 */
+ /* .. ==> 0XF8000B50[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. OUTPUT_EN = 0x3 */
+ /* .. ==> 0XF8000B50[10:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
+ /* .. PULLUP_EN = 0x0 */
+ /* .. ==> 0XF8000B50[11:11] = 0x00000000U */
+ /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU, 0x00000674U),
+ /* .. INP_POWER = 0x0 */
+ /* .. ==> 0XF8000B54[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. INP_TYPE = 0x2 */
+ /* .. ==> 0XF8000B54[2:1] = 0x00000002U */
+ /* .. ==> MASK : 0x00000006U VAL : 0x00000004U */
+ /* .. DCI_UPDATE = 0x0 */
+ /* .. ==> 0XF8000B54[3:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
+ /* .. TERM_EN = 0x1 */
+ /* .. ==> 0XF8000B54[4:4] = 0x00000001U */
+ /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */
+ /* .. DCR_TYPE = 0x3 */
+ /* .. ==> 0XF8000B54[6:5] = 0x00000003U */
+ /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */
+ /* .. IBUF_DISABLE_MODE = 0 */
+ /* .. ==> 0XF8000B54[7:7] = 0x00000000U */
+ /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
+ /* .. TERM_DISABLE_MODE = 0 */
+ /* .. ==> 0XF8000B54[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. OUTPUT_EN = 0x3 */
+ /* .. ==> 0XF8000B54[10:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
+ /* .. PULLUP_EN = 0x0 */
+ /* .. ==> 0XF8000B54[11:11] = 0x00000000U */
+ /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU, 0x00000674U),
+ /* .. INP_POWER = 0x0 */
+ /* .. ==> 0XF8000B58[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. INP_TYPE = 0x0 */
+ /* .. ==> 0XF8000B58[2:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */
+ /* .. DCI_UPDATE = 0x0 */
+ /* .. ==> 0XF8000B58[3:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
+ /* .. TERM_EN = 0x0 */
+ /* .. ==> 0XF8000B58[4:4] = 0x00000000U */
+ /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */
+ /* .. DCR_TYPE = 0x0 */
+ /* .. ==> 0XF8000B58[6:5] = 0x00000000U */
+ /* .. ==> MASK : 0x00000060U VAL : 0x00000000U */
+ /* .. IBUF_DISABLE_MODE = 0x0 */
+ /* .. ==> 0XF8000B58[7:7] = 0x00000000U */
+ /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
+ /* .. TERM_DISABLE_MODE = 0x0 */
+ /* .. ==> 0XF8000B58[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. OUTPUT_EN = 0x3 */
+ /* .. ==> 0XF8000B58[10:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
+ /* .. PULLUP_EN = 0x0 */
+ /* .. ==> 0XF8000B58[11:11] = 0x00000000U */
+ /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU, 0x00000600U),
+ /* .. DRIVE_P = 0x1c */
+ /* .. ==> 0XF8000B5C[6:0] = 0x0000001CU */
+ /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */
+ /* .. DRIVE_N = 0xc */
+ /* .. ==> 0XF8000B5C[13:7] = 0x0000000CU */
+ /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */
+ /* .. SLEW_P = 0x3 */
+ /* .. ==> 0XF8000B5C[18:14] = 0x00000003U */
+ /* .. ==> MASK : 0x0007C000U VAL : 0x0000C000U */
+ /* .. SLEW_N = 0x3 */
+ /* .. ==> 0XF8000B5C[23:19] = 0x00000003U */
+ /* .. ==> MASK : 0x00F80000U VAL : 0x00180000U */
+ /* .. GTL = 0x0 */
+ /* .. ==> 0XF8000B5C[26:24] = 0x00000000U */
+ /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */
+ /* .. RTERM = 0x0 */
+ /* .. ==> 0XF8000B5C[31:27] = 0x00000000U */
+ /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU, 0x0018C61CU),
+ /* .. DRIVE_P = 0x1c */
+ /* .. ==> 0XF8000B60[6:0] = 0x0000001CU */
+ /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */
+ /* .. DRIVE_N = 0xc */
+ /* .. ==> 0XF8000B60[13:7] = 0x0000000CU */
+ /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */
+ /* .. SLEW_P = 0x6 */
+ /* .. ==> 0XF8000B60[18:14] = 0x00000006U */
+ /* .. ==> MASK : 0x0007C000U VAL : 0x00018000U */
+ /* .. SLEW_N = 0x1f */
+ /* .. ==> 0XF8000B60[23:19] = 0x0000001FU */
+ /* .. ==> MASK : 0x00F80000U VAL : 0x00F80000U */
+ /* .. GTL = 0x0 */
+ /* .. ==> 0XF8000B60[26:24] = 0x00000000U */
+ /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */
+ /* .. RTERM = 0x0 */
+ /* .. ==> 0XF8000B60[31:27] = 0x00000000U */
+ /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU, 0x00F9861CU),
+ /* .. DRIVE_P = 0x1c */
+ /* .. ==> 0XF8000B64[6:0] = 0x0000001CU */
+ /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */
+ /* .. DRIVE_N = 0xc */
+ /* .. ==> 0XF8000B64[13:7] = 0x0000000CU */
+ /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */
+ /* .. SLEW_P = 0x6 */
+ /* .. ==> 0XF8000B64[18:14] = 0x00000006U */
+ /* .. ==> MASK : 0x0007C000U VAL : 0x00018000U */
+ /* .. SLEW_N = 0x1f */
+ /* .. ==> 0XF8000B64[23:19] = 0x0000001FU */
+ /* .. ==> MASK : 0x00F80000U VAL : 0x00F80000U */
+ /* .. GTL = 0x0 */
+ /* .. ==> 0XF8000B64[26:24] = 0x00000000U */
+ /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */
+ /* .. RTERM = 0x0 */
+ /* .. ==> 0XF8000B64[31:27] = 0x00000000U */
+ /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU, 0x00F9861CU),
+ /* .. DRIVE_P = 0x1c */
+ /* .. ==> 0XF8000B68[6:0] = 0x0000001CU */
+ /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */
+ /* .. DRIVE_N = 0xc */
+ /* .. ==> 0XF8000B68[13:7] = 0x0000000CU */
+ /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */
+ /* .. SLEW_P = 0x6 */
+ /* .. ==> 0XF8000B68[18:14] = 0x00000006U */
+ /* .. ==> MASK : 0x0007C000U VAL : 0x00018000U */
+ /* .. SLEW_N = 0x1f */
+ /* .. ==> 0XF8000B68[23:19] = 0x0000001FU */
+ /* .. ==> MASK : 0x00F80000U VAL : 0x00F80000U */
+ /* .. GTL = 0x0 */
+ /* .. ==> 0XF8000B68[26:24] = 0x00000000U */
+ /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */
+ /* .. RTERM = 0x0 */
+ /* .. ==> 0XF8000B68[31:27] = 0x00000000U */
+ /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU, 0x00F9861CU),
+ /* .. VREF_INT_EN = 0x0 */
+ /* .. ==> 0XF8000B6C[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. VREF_SEL = 0x0 */
+ /* .. ==> 0XF8000B6C[4:1] = 0x00000000U */
+ /* .. ==> MASK : 0x0000001EU VAL : 0x00000000U */
+ /* .. VREF_EXT_EN = 0x3 */
+ /* .. ==> 0XF8000B6C[6:5] = 0x00000003U */
+ /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */
+ /* .. VREF_PULLUP_EN = 0x0 */
+ /* .. ==> 0XF8000B6C[8:7] = 0x00000000U */
+ /* .. ==> MASK : 0x00000180U VAL : 0x00000000U */
+ /* .. REFIO_EN = 0x1 */
+ /* .. ==> 0XF8000B6C[9:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000200U VAL : 0x00000200U */
+ /* .. REFIO_PULLUP_EN = 0x0 */
+ /* .. ==> 0XF8000B6C[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DRST_B_PULLUP_EN = 0x0 */
+ /* .. ==> 0XF8000B6C[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. CKE_PULLUP_EN = 0x0 */
+ /* .. ==> 0XF8000B6C[14:14] = 0x00000000U */
+ /* .. ==> MASK : 0x00004000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000B6C, 0x000073FFU, 0x00000260U),
+ /* .. .. START: ASSERT RESET */
+ /* .. .. RESET = 1 */
+ /* .. .. ==> 0XF8000B70[0:0] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. .. VRN_OUT = 0x1 */
+ /* .. .. ==> 0XF8000B70[5:5] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000020U VAL : 0x00000020U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000021U),
+ /* .. .. FINISH: ASSERT RESET */
+ /* .. .. START: DEASSERT RESET */
+ /* .. .. RESET = 0 */
+ /* .. .. ==> 0XF8000B70[0:0] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. .. VRN_OUT = 0x1 */
+ /* .. .. ==> 0XF8000B70[5:5] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000020U VAL : 0x00000020U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000020U),
+ /* .. .. FINISH: DEASSERT RESET */
+ /* .. .. RESET = 0x1 */
+ /* .. .. ==> 0XF8000B70[0:0] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. .. ENABLE = 0x1 */
+ /* .. .. ==> 0XF8000B70[1:1] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. .. VRP_TRI = 0x0 */
+ /* .. .. ==> 0XF8000B70[2:2] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. .. VRN_TRI = 0x0 */
+ /* .. .. ==> 0XF8000B70[3:3] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */
+ /* .. .. VRP_OUT = 0x0 */
+ /* .. .. ==> 0XF8000B70[4:4] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
+ /* .. .. VRN_OUT = 0x1 */
+ /* .. .. ==> 0XF8000B70[5:5] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00000020U VAL : 0x00000020U */
+ /* .. .. NREF_OPT1 = 0x0 */
+ /* .. .. ==> 0XF8000B70[7:6] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U */
+ /* .. .. NREF_OPT2 = 0x0 */
+ /* .. .. ==> 0XF8000B70[10:8] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00000700U VAL : 0x00000000U */
+ /* .. .. NREF_OPT4 = 0x1 */
+ /* .. .. ==> 0XF8000B70[13:11] = 0x00000001U */
+ /* .. .. ==> MASK : 0x00003800U VAL : 0x00000800U */
+ /* .. .. PREF_OPT1 = 0x0 */
+ /* .. .. ==> 0XF8000B70[16:14] = 0x00000000U */
+ /* .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U */
+ /* .. .. PREF_OPT2 = 0x0 */
+ /* .. .. ==> 0XF8000B70[19:17] = 0x00000000U */
+ /* .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U */
+ /* .. .. UPDATE_CONTROL = 0x0 */
+ /* .. .. ==> 0XF8000B70[20:20] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00100000U VAL : 0x00000000U */
+ /* .. .. INIT_COMPLETE = 0x0 */
+ /* .. .. ==> 0XF8000B70[21:21] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00200000U VAL : 0x00000000U */
+ /* .. .. TST_CLK = 0x0 */
+ /* .. .. ==> 0XF8000B70[22:22] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00400000U VAL : 0x00000000U */
+ /* .. .. TST_HLN = 0x0 */
+ /* .. .. ==> 0XF8000B70[23:23] = 0x00000000U */
+ /* .. .. ==> MASK : 0x00800000U VAL : 0x00000000U */
+ /* .. .. TST_HLP = 0x0 */
+ /* .. .. ==> 0XF8000B70[24:24] = 0x00000000U */
+ /* .. .. ==> MASK : 0x01000000U VAL : 0x00000000U */
+ /* .. .. TST_RST = 0x0 */
+ /* .. .. ==> 0XF8000B70[25:25] = 0x00000000U */
+ /* .. .. ==> MASK : 0x02000000U VAL : 0x00000000U */
+ /* .. .. INT_DCI_EN = 0x0 */
+ /* .. .. ==> 0XF8000B70[26:26] = 0x00000000U */
+ /* .. .. ==> MASK : 0x04000000U VAL : 0x00000000U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU, 0x00000823U),
+ /* .. FINISH: DDRIOB SETTINGS */
+ /* .. START: MIO PROGRAMMING */
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000700[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF8000700[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000700[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000700[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000700[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF8000700[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF8000700[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 1 */
+ /* .. ==> 0XF8000700[12:12] = 0x00000001U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000700[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000700, 0x00003FFFU, 0x00001600U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000704[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF8000704[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000704[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000704[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000704[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000704[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF8000704[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000704[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000704[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000704, 0x00003FFFU, 0x00000702U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000708[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF8000708[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000708[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000708[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000708[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000708[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF8000708[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000708[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000708[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000708, 0x00003FFFU, 0x00000702U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF800070C[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF800070C[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF800070C[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF800070C[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF800070C[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF800070C[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF800070C[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF800070C[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF800070C[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF800070C, 0x00003FFFU, 0x00000702U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000710[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF8000710[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000710[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000710[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000710[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000710[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF8000710[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000710[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000710[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000710, 0x00003FFFU, 0x00000702U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000714[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF8000714[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000714[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000714[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000714[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000714[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF8000714[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000714[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000714[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000714, 0x00003FFFU, 0x00000702U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000718[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF8000718[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000718[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000718[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000718[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000718[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF8000718[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000718[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000718[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000702U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF800071C[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF800071C[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF800071C[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF800071C[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF800071C[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF800071C[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF800071C[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF800071C[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF800071C[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF800071C, 0x00003FFFU, 0x00000600U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000720[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF8000720[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000720[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000720[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000720[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000720[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF8000720[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000720[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000720[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000720, 0x00003FFFU, 0x00000702U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000724[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF8000724[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000724[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000724[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000724[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF8000724[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF8000724[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 1 */
+ /* .. ==> 0XF8000724[12:12] = 0x00000001U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000724[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000724, 0x00003FFFU, 0x00001600U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000728[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF8000728[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000728[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000728[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000728[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF8000728[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF8000728[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 1 */
+ /* .. ==> 0XF8000728[12:12] = 0x00000001U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000728[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000728, 0x00003FFFU, 0x00001600U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF800072C[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF800072C[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF800072C[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF800072C[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF800072C[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF800072C[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF800072C[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 1 */
+ /* .. ==> 0XF800072C[12:12] = 0x00000001U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF800072C[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF800072C, 0x00003FFFU, 0x00001600U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000730[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF8000730[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000730[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000730[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000730[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF8000730[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF8000730[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 1 */
+ /* .. ==> 0XF8000730[12:12] = 0x00000001U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000730[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000730, 0x00003FFFU, 0x00001600U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000734[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF8000734[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000734[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000734[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000734[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF8000734[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF8000734[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 1 */
+ /* .. ==> 0XF8000734[12:12] = 0x00000001U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000734[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000734, 0x00003FFFU, 0x00001600U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000738[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF8000738[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000738[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000738[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000738[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF8000738[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF8000738[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 1 */
+ /* .. ==> 0XF8000738[12:12] = 0x00000001U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000738[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000738, 0x00003FFFU, 0x00001600U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF800073C[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF800073C[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF800073C[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF800073C[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF800073C[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF800073C[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 3 */
+ /* .. ==> 0XF800073C[11:9] = 0x00000003U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
+ /* .. PULLUP = 1 */
+ /* .. ==> 0XF800073C[12:12] = 0x00000001U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF800073C[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF800073C, 0x00003FFFU, 0x00001600U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000740[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF8000740[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000740[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000740[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000740[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000740[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 4 */
+ /* .. ==> 0XF8000740[11:9] = 0x00000004U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000740[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 1 */
+ /* .. ==> 0XF8000740[13:13] = 0x00000001U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000740, 0x00003FFFU, 0x00002902U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000744[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF8000744[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000744[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000744[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000744[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000744[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 4 */
+ /* .. ==> 0XF8000744[11:9] = 0x00000004U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000744[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 1 */
+ /* .. ==> 0XF8000744[13:13] = 0x00000001U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000744, 0x00003FFFU, 0x00002902U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000748[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF8000748[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000748[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000748[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000748[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000748[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 4 */
+ /* .. ==> 0XF8000748[11:9] = 0x00000004U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000748[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 1 */
+ /* .. ==> 0XF8000748[13:13] = 0x00000001U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000748, 0x00003FFFU, 0x00002902U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF800074C[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF800074C[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF800074C[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF800074C[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF800074C[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF800074C[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 4 */
+ /* .. ==> 0XF800074C[11:9] = 0x00000004U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF800074C[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 1 */
+ /* .. ==> 0XF800074C[13:13] = 0x00000001U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF800074C, 0x00003FFFU, 0x00002902U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000750[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF8000750[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000750[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000750[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000750[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000750[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 4 */
+ /* .. ==> 0XF8000750[11:9] = 0x00000004U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000750[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 1 */
+ /* .. ==> 0XF8000750[13:13] = 0x00000001U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000750, 0x00003FFFU, 0x00002902U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000754[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF8000754[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000754[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000754[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000754[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000754[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 4 */
+ /* .. ==> 0XF8000754[11:9] = 0x00000004U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000754[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 1 */
+ /* .. ==> 0XF8000754[13:13] = 0x00000001U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000754, 0x00003FFFU, 0x00002902U),
+ /* .. TRI_ENABLE = 1 */
+ /* .. ==> 0XF8000758[0:0] = 0x00000001U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF8000758[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000758[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000758[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000758[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000758[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 4 */
+ /* .. ==> 0XF8000758[11:9] = 0x00000004U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000758[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000758[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000758, 0x00003FFFU, 0x00000903U),
+ /* .. TRI_ENABLE = 1 */
+ /* .. ==> 0XF800075C[0:0] = 0x00000001U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF800075C[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF800075C[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF800075C[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF800075C[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF800075C[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 4 */
+ /* .. ==> 0XF800075C[11:9] = 0x00000004U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF800075C[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF800075C[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF800075C, 0x00003FFFU, 0x00000903U),
+ /* .. TRI_ENABLE = 1 */
+ /* .. ==> 0XF8000760[0:0] = 0x00000001U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF8000760[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000760[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000760[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000760[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000760[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 4 */
+ /* .. ==> 0XF8000760[11:9] = 0x00000004U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000760[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000760[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000760, 0x00003FFFU, 0x00000903U),
+ /* .. TRI_ENABLE = 1 */
+ /* .. ==> 0XF8000764[0:0] = 0x00000001U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF8000764[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000764[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000764[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000764[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000764[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 4 */
+ /* .. ==> 0XF8000764[11:9] = 0x00000004U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000764[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000764[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000764, 0x00003FFFU, 0x00000903U),
+ /* .. TRI_ENABLE = 1 */
+ /* .. ==> 0XF8000768[0:0] = 0x00000001U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF8000768[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF8000768[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000768[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000768[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000768[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 4 */
+ /* .. ==> 0XF8000768[11:9] = 0x00000004U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000768[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000768[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000768, 0x00003FFFU, 0x00000903U),
+ /* .. TRI_ENABLE = 1 */
+ /* .. ==> 0XF800076C[0:0] = 0x00000001U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. L0_SEL = 1 */
+ /* .. ==> 0XF800076C[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF800076C[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF800076C[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF800076C[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF800076C[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 4 */
+ /* .. ==> 0XF800076C[11:9] = 0x00000004U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF800076C[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF800076C[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF800076C, 0x00003FFFU, 0x00000903U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000770[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF8000770[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 1 */
+ /* .. ==> 0XF8000770[2:2] = 0x00000001U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000770[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000770[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000770[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF8000770[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000770[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000770[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000770, 0x00003FFFU, 0x00000304U),
+ /* .. TRI_ENABLE = 1 */
+ /* .. ==> 0XF8000774[0:0] = 0x00000001U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF8000774[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 1 */
+ /* .. ==> 0XF8000774[2:2] = 0x00000001U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000774[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000774[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000774[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF8000774[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000774[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000774[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000774, 0x00003FFFU, 0x00000305U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000778[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF8000778[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 1 */
+ /* .. ==> 0XF8000778[2:2] = 0x00000001U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000778[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000778[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000778[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF8000778[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000778[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000778[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000778, 0x00003FFFU, 0x00000304U),
+ /* .. TRI_ENABLE = 1 */
+ /* .. ==> 0XF800077C[0:0] = 0x00000001U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF800077C[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 1 */
+ /* .. ==> 0XF800077C[2:2] = 0x00000001U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF800077C[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF800077C[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF800077C[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF800077C[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF800077C[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF800077C[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF800077C, 0x00003FFFU, 0x00000305U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000780[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF8000780[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 1 */
+ /* .. ==> 0XF8000780[2:2] = 0x00000001U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000780[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000780[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000780[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF8000780[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000780[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000780[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000780, 0x00003FFFU, 0x00000304U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000784[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF8000784[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 1 */
+ /* .. ==> 0XF8000784[2:2] = 0x00000001U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000784[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000784[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000784[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF8000784[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000784[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000784[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000784, 0x00003FFFU, 0x00000304U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000788[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF8000788[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 1 */
+ /* .. ==> 0XF8000788[2:2] = 0x00000001U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000788[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000788[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000788[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF8000788[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000788[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000788[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000788, 0x00003FFFU, 0x00000304U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF800078C[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF800078C[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 1 */
+ /* .. ==> 0XF800078C[2:2] = 0x00000001U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF800078C[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF800078C[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF800078C[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF800078C[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF800078C[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF800078C[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF800078C, 0x00003FFFU, 0x00000304U),
+ /* .. TRI_ENABLE = 1 */
+ /* .. ==> 0XF8000790[0:0] = 0x00000001U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF8000790[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 1 */
+ /* .. ==> 0XF8000790[2:2] = 0x00000001U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000790[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000790[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000790[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF8000790[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000790[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000790[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000790, 0x00003FFFU, 0x00000305U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000794[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF8000794[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 1 */
+ /* .. ==> 0XF8000794[2:2] = 0x00000001U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000794[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000794[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000794[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF8000794[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000794[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000794[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000794, 0x00003FFFU, 0x00000304U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF8000798[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF8000798[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 1 */
+ /* .. ==> 0XF8000798[2:2] = 0x00000001U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF8000798[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF8000798[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF8000798[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF8000798[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF8000798[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF8000798[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000798, 0x00003FFFU, 0x00000304U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF800079C[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF800079C[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 1 */
+ /* .. ==> 0XF800079C[2:2] = 0x00000001U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF800079C[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF800079C[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF800079C[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF800079C[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF800079C[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF800079C[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF800079C, 0x00003FFFU, 0x00000304U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF80007A0[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF80007A0[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF80007A0[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF80007A0[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 4 */
+ /* .. ==> 0XF80007A0[7:5] = 0x00000004U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF80007A0[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF80007A0[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF80007A0[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF80007A0[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU, 0x00000380U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF80007A4[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF80007A4[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF80007A4[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF80007A4[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 4 */
+ /* .. ==> 0XF80007A4[7:5] = 0x00000004U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF80007A4[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF80007A4[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF80007A4[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF80007A4[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU, 0x00000380U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF80007A8[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF80007A8[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF80007A8[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF80007A8[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 4 */
+ /* .. ==> 0XF80007A8[7:5] = 0x00000004U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF80007A8[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF80007A8[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF80007A8[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF80007A8[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU, 0x00000380U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF80007AC[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF80007AC[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF80007AC[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF80007AC[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 4 */
+ /* .. ==> 0XF80007AC[7:5] = 0x00000004U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF80007AC[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF80007AC[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF80007AC[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF80007AC[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU, 0x00000380U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF80007B0[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF80007B0[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF80007B0[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF80007B0[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 4 */
+ /* .. ==> 0XF80007B0[7:5] = 0x00000004U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF80007B0[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF80007B0[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF80007B0[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF80007B0[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU, 0x00000380U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF80007B4[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF80007B4[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF80007B4[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF80007B4[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 4 */
+ /* .. ==> 0XF80007B4[7:5] = 0x00000004U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
+ /* .. Speed = 1 */
+ /* .. ==> 0XF80007B4[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF80007B4[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF80007B4[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF80007B4[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00000380U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF80007B8[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF80007B8[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF80007B8[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF80007B8[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF80007B8[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF80007B8[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF80007B8[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 1 */
+ /* .. ==> 0XF80007B8[12:12] = 0x00000001U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF80007B8[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU, 0x00001200U),
+ /* .. TRI_ENABLE = 1 */
+ /* .. ==> 0XF80007BC[0:0] = 0x00000001U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF80007BC[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF80007BC[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF80007BC[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF80007BC[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF80007BC, 0x00003F01U, 0x00000201U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF80007C0[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF80007C0[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF80007C0[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF80007C0[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 7 */
+ /* .. ==> 0XF80007C0[7:5] = 0x00000007U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x000000E0U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF80007C0[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF80007C0[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF80007C0[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF80007C0[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU, 0x000002E0U),
+ /* .. TRI_ENABLE = 1 */
+ /* .. ==> 0XF80007C4[0:0] = 0x00000001U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF80007C4[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF80007C4[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF80007C4[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 7 */
+ /* .. ==> 0XF80007C4[7:5] = 0x00000007U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x000000E0U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF80007C4[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF80007C4[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF80007C4[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF80007C4[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x000002E1U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF80007C8[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF80007C8[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF80007C8[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF80007C8[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF80007C8[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF80007C8[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF80007C8[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF80007C8[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF80007C8[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU, 0x00000200U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF80007CC[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF80007CC[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF80007CC[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF80007CC[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 0 */
+ /* .. ==> 0XF80007CC[7:5] = 0x00000000U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF80007CC[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF80007CC[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF80007CC[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF80007CC[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU, 0x00000200U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF80007D0[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF80007D0[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF80007D0[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF80007D0[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 4 */
+ /* .. ==> 0XF80007D0[7:5] = 0x00000004U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF80007D0[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF80007D0[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF80007D0[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF80007D0[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU, 0x00000280U),
+ /* .. TRI_ENABLE = 0 */
+ /* .. ==> 0XF80007D4[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. L0_SEL = 0 */
+ /* .. ==> 0XF80007D4[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. L1_SEL = 0 */
+ /* .. ==> 0XF80007D4[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. L2_SEL = 0 */
+ /* .. ==> 0XF80007D4[4:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
+ /* .. L3_SEL = 4 */
+ /* .. ==> 0XF80007D4[7:5] = 0x00000004U */
+ /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
+ /* .. Speed = 0 */
+ /* .. ==> 0XF80007D4[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. IO_Type = 1 */
+ /* .. ==> 0XF80007D4[11:9] = 0x00000001U */
+ /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
+ /* .. PULLUP = 0 */
+ /* .. ==> 0XF80007D4[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. DisableRcvr = 0 */
+ /* .. ==> 0XF80007D4[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU, 0x00000280U),
+ /* .. SDIO0_WP_SEL = 55 */
+ /* .. ==> 0XF8000830[5:0] = 0x00000037U */
+ /* .. ==> MASK : 0x0000003FU VAL : 0x00000037U */
+ /* .. SDIO0_CD_SEL = 47 */
+ /* .. ==> 0XF8000830[21:16] = 0x0000002FU */
+ /* .. ==> MASK : 0x003F0000U VAL : 0x002F0000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000830, 0x003F003FU, 0x002F0037U),
+ /* .. FINISH: MIO PROGRAMMING */
+ /* .. START: LOCK IT BACK */
+ /* .. LOCK_KEY = 0X767B */
+ /* .. ==> 0XF8000004[15:0] = 0x0000767BU */
+ /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+ /* .. FINISH: LOCK IT BACK */
+ /* FINISH: top */
+ /* */
+ EMIT_EXIT(),
+
+ /* */
+};
+
+unsigned long ps7_peripherals_init_data_1_0[] = {
+ /* START: top */
+ /* .. START: SLCR SETTINGS */
+ /* .. UNLOCK_KEY = 0XDF0D */
+ /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
+ /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ /* .. FINISH: SLCR SETTINGS */
+ /* .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS */
+ /* .. IBUF_DISABLE_MODE = 0x1 */
+ /* .. ==> 0XF8000B48[7:7] = 0x00000001U */
+ /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */
+ /* .. TERM_DISABLE_MODE = 0x1 */
+ /* .. ==> 0XF8000B48[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000B48, 0x00000180U, 0x00000180U),
+ /* .. IBUF_DISABLE_MODE = 0x1 */
+ /* .. ==> 0XF8000B4C[7:7] = 0x00000001U */
+ /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */
+ /* .. TERM_DISABLE_MODE = 0x1 */
+ /* .. ==> 0XF8000B4C[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000B4C, 0x00000180U, 0x00000180U),
+ /* .. IBUF_DISABLE_MODE = 0x1 */
+ /* .. ==> 0XF8000B50[7:7] = 0x00000001U */
+ /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */
+ /* .. TERM_DISABLE_MODE = 0x1 */
+ /* .. ==> 0XF8000B50[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U),
+ /* .. IBUF_DISABLE_MODE = 0x1 */
+ /* .. ==> 0XF8000B54[7:7] = 0x00000001U */
+ /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */
+ /* .. TERM_DISABLE_MODE = 0x1 */
+ /* .. ==> 0XF8000B54[8:8] = 0x00000001U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U),
+ /* .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS */
+ /* .. START: LOCK IT BACK */
+ /* .. LOCK_KEY = 0X767B */
+ /* .. ==> 0XF8000004[15:0] = 0x0000767BU */
+ /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+ /* .. FINISH: LOCK IT BACK */
+ /* .. START: SRAM/NOR SET OPMODE */
+ /* .. FINISH: SRAM/NOR SET OPMODE */
+ /* .. START: UART REGISTERS */
+ /* .. BDIV = 0x6 */
+ /* .. ==> 0XE0001034[7:0] = 0x00000006U */
+ /* .. ==> MASK : 0x000000FFU VAL : 0x00000006U */
+ /* .. */
+ EMIT_MASKWRITE(0XE0001034, 0x000000FFU, 0x00000006U),
+ /* .. CD = 0x7c */
+ /* .. ==> 0XE0001018[15:0] = 0x0000007CU */
+ /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU */
+ /* .. */
+ EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU, 0x0000007CU),
+ /* .. STPBRK = 0x0 */
+ /* .. ==> 0XE0001000[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. STTBRK = 0x0 */
+ /* .. ==> 0XE0001000[7:7] = 0x00000000U */
+ /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
+ /* .. RSTTO = 0x0 */
+ /* .. ==> 0XE0001000[6:6] = 0x00000000U */
+ /* .. ==> MASK : 0x00000040U VAL : 0x00000000U */
+ /* .. TXDIS = 0x0 */
+ /* .. ==> 0XE0001000[5:5] = 0x00000000U */
+ /* .. ==> MASK : 0x00000020U VAL : 0x00000000U */
+ /* .. TXEN = 0x1 */
+ /* .. ==> 0XE0001000[4:4] = 0x00000001U */
+ /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */
+ /* .. RXDIS = 0x0 */
+ /* .. ==> 0XE0001000[3:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
+ /* .. RXEN = 0x1 */
+ /* .. ==> 0XE0001000[2:2] = 0x00000001U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
+ /* .. TXRES = 0x1 */
+ /* .. ==> 0XE0001000[1:1] = 0x00000001U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
+ /* .. RXRES = 0x1 */
+ /* .. ==> 0XE0001000[0:0] = 0x00000001U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
+ /* .. */
+ EMIT_MASKWRITE(0XE0001000, 0x000001FFU, 0x00000017U),
+ /* .. IRMODE = 0x0 */
+ /* .. ==> 0XE0001004[11:11] = 0x00000000U */
+ /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
+ /* .. UCLKEN = 0x0 */
+ /* .. ==> 0XE0001004[10:10] = 0x00000000U */
+ /* .. ==> MASK : 0x00000400U VAL : 0x00000000U */
+ /* .. CHMODE = 0x0 */
+ /* .. ==> 0XE0001004[9:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000300U VAL : 0x00000000U */
+ /* .. NBSTOP = 0x0 */
+ /* .. ==> 0XE0001004[7:6] = 0x00000000U */
+ /* .. ==> MASK : 0x000000C0U VAL : 0x00000000U */
+ /* .. PAR = 0x4 */
+ /* .. ==> 0XE0001004[5:3] = 0x00000004U */
+ /* .. ==> MASK : 0x00000038U VAL : 0x00000020U */
+ /* .. CHRL = 0x0 */
+ /* .. ==> 0XE0001004[2:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */
+ /* .. CLKS = 0x0 */
+ /* .. ==> 0XE0001004[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XE0001004, 0x00000FFFU, 0x00000020U),
+ /* .. FINISH: UART REGISTERS */
+ /* .. START: QSPI REGISTERS */
+ /* .. Holdb_dr = 1 */
+ /* .. ==> 0XE000D000[19:19] = 0x00000001U */
+ /* .. ==> MASK : 0x00080000U VAL : 0x00080000U */
+ /* .. */
+ EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U),
+ /* .. FINISH: QSPI REGISTERS */
+ /* .. START: PL POWER ON RESET REGISTERS */
+ /* .. PCFG_POR_CNT_4K = 0 */
+ /* .. ==> 0XF8007000[29:29] = 0x00000000U */
+ /* .. ==> MASK : 0x20000000U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U),
+ /* .. FINISH: PL POWER ON RESET REGISTERS */
+ /* .. START: SMC TIMING CALCULATION REGISTER UPDATE */
+ /* .. .. START: NAND SET CYCLE */
+ /* .. .. FINISH: NAND SET CYCLE */
+ /* .. .. START: OPMODE */
+ /* .. .. FINISH: OPMODE */
+ /* .. .. START: DIRECT COMMAND */
+ /* .. .. FINISH: DIRECT COMMAND */
+ /* .. .. START: SRAM/NOR CS0 SET CYCLE */
+ /* .. .. FINISH: SRAM/NOR CS0 SET CYCLE */
+ /* .. .. START: DIRECT COMMAND */
+ /* .. .. FINISH: DIRECT COMMAND */
+ /* .. .. START: NOR CS0 BASE ADDRESS */
+ /* .. .. FINISH: NOR CS0 BASE ADDRESS */
+ /* .. .. START: SRAM/NOR CS1 SET CYCLE */
+ /* .. .. FINISH: SRAM/NOR CS1 SET CYCLE */
+ /* .. .. START: DIRECT COMMAND */
+ /* .. .. FINISH: DIRECT COMMAND */
+ /* .. .. START: NOR CS1 BASE ADDRESS */
+ /* .. .. FINISH: NOR CS1 BASE ADDRESS */
+ /* .. .. START: USB RESET */
+ /* .. .. .. START: USB0 RESET */
+ /* .. .. .. .. START: DIR MODE BANK 0 */
+ /* .. .. .. .. FINISH: DIR MODE BANK 0 */
+ /* .. .. .. .. START: DIR MODE BANK 1 */
+ /* .. .. .. .. DIRECTION_1 = 0x4000 */
+ /* .. .. .. .. ==> 0XE000A244[21:0] = 0x00004000U */
+ /* .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U */
+ /* .. .. .. .. */
+ EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU, 0x00004000U),
+ /* .. .. .. .. FINISH: DIR MODE BANK 1 */
+ /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. MASK_1_LSW = 0xbfff */
+ /* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */
+ /* .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U */
+ /* .. .. .. .. DATA_1_LSW = 0x4000 */
+ /* .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U */
+ /* .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U */
+ /* .. .. .. .. */
+ EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF4000U),
+ /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
+ /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
+ /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
+ /* .. .. .. .. OP_ENABLE_1 = 0x4000 */
+ /* .. .. .. .. ==> 0XE000A248[21:0] = 0x00004000U */
+ /* .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U */
+ /* .. .. .. .. */
+ EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU, 0x00004000U),
+ /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
+ /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
+ /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
+ /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
+ /* .. .. .. .. MASK_1_LSW = 0xbfff */
+ /* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */
+ /* .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U */
+ /* .. .. .. .. DATA_1_LSW = 0x0 */
+ /* .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U */
+ /* .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U */
+ /* .. .. .. .. */
+ EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF0000U),
+ /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
+ /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
+ /* .. .. .. .. START: ADD 1 MS DELAY */
+ /* .. .. .. .. */
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ /* .. .. .. .. FINISH: ADD 1 MS DELAY */
+ /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. MASK_1_LSW = 0xbfff */
+ /* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */
+ /* .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U */
+ /* .. .. .. .. DATA_1_LSW = 0x4000 */
+ /* .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U */
+ /* .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U */
+ /* .. .. .. .. */
+ EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF4000U),
+ /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. FINISH: USB0 RESET */
+ /* .. .. .. START: USB1 RESET */
+ /* .. .. .. .. START: DIR MODE BANK 0 */
+ /* .. .. .. .. FINISH: DIR MODE BANK 0 */
+ /* .. .. .. .. START: DIR MODE BANK 1 */
+ /* .. .. .. .. FINISH: DIR MODE BANK 1 */
+ /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
+ /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
+ /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
+ /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
+ /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
+ /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
+ /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
+ /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
+ /* .. .. .. .. START: ADD 1 MS DELAY */
+ /* .. .. .. .. */
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ /* .. .. .. .. FINISH: ADD 1 MS DELAY */
+ /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. FINISH: USB1 RESET */
+ /* .. .. FINISH: USB RESET */
+ /* .. .. START: ENET RESET */
+ /* .. .. .. START: ENET0 RESET */
+ /* .. .. .. .. START: DIR MODE BANK 0 */
+ /* .. .. .. .. FINISH: DIR MODE BANK 0 */
+ /* .. .. .. .. START: DIR MODE BANK 1 */
+ /* .. .. .. .. FINISH: DIR MODE BANK 1 */
+ /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
+ /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
+ /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
+ /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
+ /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
+ /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
+ /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
+ /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
+ /* .. .. .. .. START: ADD 1 MS DELAY */
+ /* .. .. .. .. */
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ /* .. .. .. .. FINISH: ADD 1 MS DELAY */
+ /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. FINISH: ENET0 RESET */
+ /* .. .. .. START: ENET1 RESET */
+ /* .. .. .. .. START: DIR MODE BANK 0 */
+ /* .. .. .. .. FINISH: DIR MODE BANK 0 */
+ /* .. .. .. .. START: DIR MODE BANK 1 */
+ /* .. .. .. .. FINISH: DIR MODE BANK 1 */
+ /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
+ /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
+ /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
+ /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
+ /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
+ /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
+ /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
+ /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
+ /* .. .. .. .. START: ADD 1 MS DELAY */
+ /* .. .. .. .. */
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ /* .. .. .. .. FINISH: ADD 1 MS DELAY */
+ /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. FINISH: ENET1 RESET */
+ /* .. .. FINISH: ENET RESET */
+ /* .. .. START: I2C RESET */
+ /* .. .. .. START: I2C0 RESET */
+ /* .. .. .. .. START: DIR MODE GPIO BANK0 */
+ /* .. .. .. .. FINISH: DIR MODE GPIO BANK0 */
+ /* .. .. .. .. START: DIR MODE GPIO BANK1 */
+ /* .. .. .. .. FINISH: DIR MODE GPIO BANK1 */
+ /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. .. START: OUTPUT ENABLE */
+ /* .. .. .. .. FINISH: OUTPUT ENABLE */
+ /* .. .. .. .. START: OUTPUT ENABLE */
+ /* .. .. .. .. FINISH: OUTPUT ENABLE */
+ /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
+ /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
+ /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
+ /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
+ /* .. .. .. .. START: ADD 1 MS DELAY */
+ /* .. .. .. .. */
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ /* .. .. .. .. FINISH: ADD 1 MS DELAY */
+ /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. FINISH: I2C0 RESET */
+ /* .. .. .. START: I2C1 RESET */
+ /* .. .. .. .. START: DIR MODE GPIO BANK0 */
+ /* .. .. .. .. FINISH: DIR MODE GPIO BANK0 */
+ /* .. .. .. .. START: DIR MODE GPIO BANK1 */
+ /* .. .. .. .. FINISH: DIR MODE GPIO BANK1 */
+ /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. .. START: OUTPUT ENABLE */
+ /* .. .. .. .. FINISH: OUTPUT ENABLE */
+ /* .. .. .. .. START: OUTPUT ENABLE */
+ /* .. .. .. .. FINISH: OUTPUT ENABLE */
+ /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
+ /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
+ /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
+ /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
+ /* .. .. .. .. START: ADD 1 MS DELAY */
+ /* .. .. .. .. */
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ /* .. .. .. .. FINISH: ADD 1 MS DELAY */
+ /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+ /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+ /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+ /* .. .. .. FINISH: I2C1 RESET */
+ /* .. .. FINISH: I2C RESET */
+ /* .. .. START: NOR CHIP SELECT */
+ /* .. .. .. START: DIR MODE BANK 0 */
+ /* .. .. .. FINISH: DIR MODE BANK 0 */
+ /* .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+ /* .. .. .. START: OUTPUT ENABLE BANK 0 */
+ /* .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
+ /* .. .. FINISH: NOR CHIP SELECT */
+ /* .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE */
+ /* FINISH: top */
+ /* */
+ EMIT_EXIT(),
+
+ /* */
+};
+
+unsigned long ps7_post_config_1_0[] = {
+ /* START: top */
+ /* .. START: SLCR SETTINGS */
+ /* .. UNLOCK_KEY = 0XDF0D */
+ /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
+ /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ /* .. FINISH: SLCR SETTINGS */
+ /* .. START: ENABLING LEVEL SHIFTER */
+ /* .. USER_INP_ICT_EN_0 = 3 */
+ /* .. ==> 0XF8000900[1:0] = 0x00000003U */
+ /* .. ==> MASK : 0x00000003U VAL : 0x00000003U */
+ /* .. USER_INP_ICT_EN_1 = 3 */
+ /* .. ==> 0XF8000900[3:2] = 0x00000003U */
+ /* .. ==> MASK : 0x0000000CU VAL : 0x0000000CU */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU),
+ /* .. FINISH: ENABLING LEVEL SHIFTER */
+ /* .. START: FPGA RESETS TO 0 */
+ /* .. reserved_3 = 0 */
+ /* .. ==> 0XF8000240[31:25] = 0x00000000U */
+ /* .. ==> MASK : 0xFE000000U VAL : 0x00000000U */
+ /* .. FPGA_ACP_RST = 0 */
+ /* .. ==> 0XF8000240[24:24] = 0x00000000U */
+ /* .. ==> MASK : 0x01000000U VAL : 0x00000000U */
+ /* .. FPGA_AXDS3_RST = 0 */
+ /* .. ==> 0XF8000240[23:23] = 0x00000000U */
+ /* .. ==> MASK : 0x00800000U VAL : 0x00000000U */
+ /* .. FPGA_AXDS2_RST = 0 */
+ /* .. ==> 0XF8000240[22:22] = 0x00000000U */
+ /* .. ==> MASK : 0x00400000U VAL : 0x00000000U */
+ /* .. FPGA_AXDS1_RST = 0 */
+ /* .. ==> 0XF8000240[21:21] = 0x00000000U */
+ /* .. ==> MASK : 0x00200000U VAL : 0x00000000U */
+ /* .. FPGA_AXDS0_RST = 0 */
+ /* .. ==> 0XF8000240[20:20] = 0x00000000U */
+ /* .. ==> MASK : 0x00100000U VAL : 0x00000000U */
+ /* .. reserved_2 = 0 */
+ /* .. ==> 0XF8000240[19:18] = 0x00000000U */
+ /* .. ==> MASK : 0x000C0000U VAL : 0x00000000U */
+ /* .. FSSW1_FPGA_RST = 0 */
+ /* .. ==> 0XF8000240[17:17] = 0x00000000U */
+ /* .. ==> MASK : 0x00020000U VAL : 0x00000000U */
+ /* .. FSSW0_FPGA_RST = 0 */
+ /* .. ==> 0XF8000240[16:16] = 0x00000000U */
+ /* .. ==> MASK : 0x00010000U VAL : 0x00000000U */
+ /* .. reserved_1 = 0 */
+ /* .. ==> 0XF8000240[15:14] = 0x00000000U */
+ /* .. ==> MASK : 0x0000C000U VAL : 0x00000000U */
+ /* .. FPGA_FMSW1_RST = 0 */
+ /* .. ==> 0XF8000240[13:13] = 0x00000000U */
+ /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
+ /* .. FPGA_FMSW0_RST = 0 */
+ /* .. ==> 0XF8000240[12:12] = 0x00000000U */
+ /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
+ /* .. FPGA_DMA3_RST = 0 */
+ /* .. ==> 0XF8000240[11:11] = 0x00000000U */
+ /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
+ /* .. FPGA_DMA2_RST = 0 */
+ /* .. ==> 0XF8000240[10:10] = 0x00000000U */
+ /* .. ==> MASK : 0x00000400U VAL : 0x00000000U */
+ /* .. FPGA_DMA1_RST = 0 */
+ /* .. ==> 0XF8000240[9:9] = 0x00000000U */
+ /* .. ==> MASK : 0x00000200U VAL : 0x00000000U */
+ /* .. FPGA_DMA0_RST = 0 */
+ /* .. ==> 0XF8000240[8:8] = 0x00000000U */
+ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
+ /* .. reserved = 0 */
+ /* .. ==> 0XF8000240[7:4] = 0x00000000U */
+ /* .. ==> MASK : 0x000000F0U VAL : 0x00000000U */
+ /* .. FPGA3_OUT_RST = 0 */
+ /* .. ==> 0XF8000240[3:3] = 0x00000000U */
+ /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
+ /* .. FPGA2_OUT_RST = 0 */
+ /* .. ==> 0XF8000240[2:2] = 0x00000000U */
+ /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
+ /* .. FPGA1_OUT_RST = 0 */
+ /* .. ==> 0XF8000240[1:1] = 0x00000000U */
+ /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
+ /* .. FPGA0_OUT_RST = 0 */
+ /* .. ==> 0XF8000240[0:0] = 0x00000000U */
+ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU, 0x00000000U),
+ /* .. FINISH: FPGA RESETS TO 0 */
+ /* .. START: AFI REGISTERS */
+ /* .. .. START: AFI0 REGISTERS */
+ /* .. .. FINISH: AFI0 REGISTERS */
+ /* .. .. START: AFI1 REGISTERS */
+ /* .. .. FINISH: AFI1 REGISTERS */
+ /* .. .. START: AFI2 REGISTERS */
+ /* .. .. FINISH: AFI2 REGISTERS */
+ /* .. .. START: AFI3 REGISTERS */
+ /* .. .. FINISH: AFI3 REGISTERS */
+ /* .. FINISH: AFI REGISTERS */
+ /* .. START: LOCK IT BACK */
+ /* .. LOCK_KEY = 0X767B */
+ /* .. ==> 0XF8000004[15:0] = 0x0000767BU */
+ /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */
+ /* .. */
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+ /* .. FINISH: LOCK IT BACK */
+ /* FINISH: top */
+ /* */
+ EMIT_EXIT(),
+
+ /* */
+};
+
+unsigned long ps7_debug_1_0[] = {
+ /* START: top */
+ /* .. START: CROSS TRIGGER CONFIGURATIONS */
+ /* .. .. START: UNLOCKING CTI REGISTERS */
+ /* .. .. KEY = 0XC5ACCE55 */
+ /* .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U */
+ /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU, 0xC5ACCE55U),
+ /* .. .. KEY = 0XC5ACCE55 */
+ /* .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U */
+ /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU, 0xC5ACCE55U),
+ /* .. .. KEY = 0XC5ACCE55 */
+ /* .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U */
+ /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */
+ /* .. .. */
+ EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU, 0xC5ACCE55U),
+ /* .. .. FINISH: UNLOCKING CTI REGISTERS */
+ /* .. .. START: ENABLING CTI MODULES AND CHANNELS */
+ /* .. .. FINISH: ENABLING CTI MODULES AND CHANNELS */
+ /* .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS */
+ /* .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS */
+ /* .. FINISH: CROSS TRIGGER CONFIGURATIONS */
+ /* FINISH: top */
+ /* */
+ EMIT_EXIT(),
+
+ /* */
+};
+
+#include "xil_io.h"
+#define PS7_MASK_POLL_TIME 100000000
+
+char *getPS7MessageInfo(unsigned key)
+{
+ char *err_msg = "";
+ switch (key) {
+ case PS7_INIT_SUCCESS:
+ err_msg = "PS7 initialization successful";
+ break;
+ case PS7_INIT_CORRUPT:
+ err_msg = "PS7 init Data Corrupted";
+ break;
+ case PS7_INIT_TIMEOUT:
+ err_msg = "PS7 init mask poll timeout";
+ break;
+ case PS7_POLL_FAILED_DDR_INIT:
+ err_msg = "Mask Poll failed for DDR Init";
+ break;
+ case PS7_POLL_FAILED_DMA:
+ err_msg = "Mask Poll failed for PLL Init";
+ break;
+ case PS7_POLL_FAILED_PLL:
+ err_msg = "Mask Poll failed for DMA done bit";
+ break;
+ default:
+ err_msg = "Undefined error status";
+ break;
+ }
+
+ return err_msg;
+}
+
+unsigned long ps7GetSiliconVersion(void)
+{
+ /* Read PS version from MCTRL register [31:28] */
+ unsigned long mask = 0xF0000000;
+ unsigned long *addr = (unsigned long *)0XF8007080;
+ unsigned long ps_version = (*addr & mask) >> 28;
+ return ps_version;
+}
+
+void mask_write(unsigned long add, unsigned long mask, unsigned long val)
+{
+ unsigned long *addr = (unsigned long *)add;
+ *addr = (val & mask) | (*addr & ~mask);
+}
+
+int mask_poll(unsigned long add, unsigned long mask)
+{
+ volatile unsigned long *addr = (volatile unsigned long *)add;
+ int i = 0;
+ while (!(*addr & mask)) {
+ if (i == PS7_MASK_POLL_TIME)
+ return -1;
+ i++;
+ }
+ return 1;
+}
+
+unsigned long mask_read(unsigned long add, unsigned long mask)
+{
+ unsigned long *addr = (unsigned long *)add;
+ unsigned long val = (*addr & mask);
+ return val;
+}
+
+int ps7_config(unsigned long *ps7_config_init)
+{
+ unsigned long *ptr = ps7_config_init;
+
+ unsigned long opcode; /* current instruction .. */
+ unsigned long args[16]; /* no opcode has so many args ... */
+ int numargs; /* number of arguments of this instruction */
+ int j; /* general purpose index */
+
+ volatile unsigned long *addr; /* some variable to make code readable */
+ unsigned long val, mask; /* some variable to make code readable */
+
+ int finish = -1; /* loop while this is negative ! */
+ int i = 0; /* Timeout variable */
+
+ while (finish < 0) {
+ numargs = ptr[0] & 0xF;
+ opcode = ptr[0] >> 4;
+
+ for (j = 0; j < numargs; j++)
+ args[j] = ptr[j + 1];
+ ptr += numargs + 1;
+
+ switch (opcode) {
+ case OPCODE_EXIT:
+ finish = PS7_INIT_SUCCESS;
+ break;
+
+ case OPCODE_CLEAR:
+ addr = (unsigned long *)args[0];
+ *addr = 0;
+ break;
+
+ case OPCODE_WRITE:
+ addr = (unsigned long *)args[0];
+ val = args[1];
+ *addr = val;
+ break;
+
+ case OPCODE_MASKWRITE:
+ addr = (unsigned long *)args[0];
+ mask = args[1];
+ val = args[2];
+ *addr = (val & mask) | (*addr & ~mask);
+ break;
+
+ case OPCODE_MASKPOLL:
+ addr = (unsigned long *)args[0];
+ mask = args[1];
+ i = 0;
+ while (!(*addr & mask)) {
+ if (i == PS7_MASK_POLL_TIME) {
+ finish = PS7_INIT_TIMEOUT;
+ break;
+ }
+ i++;
+ }
+ break;
+ case OPCODE_MASKDELAY:
+ addr = (unsigned long *)args[0];
+ mask = args[1];
+ int delay = get_number_of_cycles_for_delay(mask);
+ perf_reset_and_start_timer();
+ while ((*addr < delay))
+ ;
+ break;
+ default:
+ finish = PS7_INIT_CORRUPT;
+ break;
+ }
+ }
+ return finish;
+}
+
+unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0;
+unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0;
+unsigned long *ps7_clock_init_data = ps7_clock_init_data_3_0;
+unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0;
+unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
+
+int ps7_post_config(void)
+{
+ /* Get the PS_VERSION on run time */
+ unsigned long si_ver = ps7GetSiliconVersion();
+ int ret = -1;
+ if (si_ver == PCW_SILICON_VERSION_1) {
+ ret = ps7_config(ps7_post_config_1_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+ } else if (si_ver == PCW_SILICON_VERSION_2) {
+ ret = ps7_config(ps7_post_config_2_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+ } else {
+ ret = ps7_config(ps7_post_config_3_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+ }
+ return PS7_INIT_SUCCESS;
+}
+
+int ps7_debug(void)
+{
+ /* Get the PS_VERSION on run time */
+ unsigned long si_ver = ps7GetSiliconVersion();
+ int ret = -1;
+ if (si_ver == PCW_SILICON_VERSION_1) {
+ ret = ps7_config(ps7_debug_1_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+ } else if (si_ver == PCW_SILICON_VERSION_2) {
+ ret = ps7_config(ps7_debug_2_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+ } else {
+ ret = ps7_config(ps7_debug_3_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+ }
+ return PS7_INIT_SUCCESS;
+}
+
+int ps7_init(void)
+{
+ /* Get the PS_VERSION on run time */
+ unsigned long si_ver = ps7GetSiliconVersion();
+ int ret;
+ /*int pcw_ver = 0; */
+
+ if (si_ver == PCW_SILICON_VERSION_1) {
+ ps7_mio_init_data = ps7_mio_init_data_1_0;
+ ps7_pll_init_data = ps7_pll_init_data_1_0;
+ ps7_clock_init_data = ps7_clock_init_data_1_0;
+ ps7_ddr_init_data = ps7_ddr_init_data_1_0;
+ ps7_peripherals_init_data = ps7_peripherals_init_data_1_0;
+ /*pcw_ver = 1; */
+
+ } else if (si_ver == PCW_SILICON_VERSION_2) {
+ ps7_mio_init_data = ps7_mio_init_data_2_0;
+ ps7_pll_init_data = ps7_pll_init_data_2_0;
+ ps7_clock_init_data = ps7_clock_init_data_2_0;
+ ps7_ddr_init_data = ps7_ddr_init_data_2_0;
+ ps7_peripherals_init_data = ps7_peripherals_init_data_2_0;
+ /*pcw_ver = 2; */
+
+ } else {
+ ps7_mio_init_data = ps7_mio_init_data_3_0;
+ ps7_pll_init_data = ps7_pll_init_data_3_0;
+ ps7_clock_init_data = ps7_clock_init_data_3_0;
+ ps7_ddr_init_data = ps7_ddr_init_data_3_0;
+ ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
+ /*pcw_ver = 3; */
+ }
+
+ /* MIO init */
+ ret = ps7_config(ps7_mio_init_data);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ /* PLL init */
+ ret = ps7_config(ps7_pll_init_data);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ /* Clock init */
+ ret = ps7_config(ps7_clock_init_data);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ /* DDR init */
+ ret = ps7_config(ps7_ddr_init_data);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ /* Peripherals init */
+ ret = ps7_config(ps7_peripherals_init_data);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+ return PS7_INIT_SUCCESS;
+}
+
+/* For delay calculation using global timer */
+
+/* start timer */
+void perf_start_clock(void)
+{
+ *(volatile unsigned int *)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) | /* Timer Enable */
+ (1 << 3) | /* Auto-increment */
+ (0 << 8) /* Pre-scale */
+ );
+}
+
+/* stop timer and reset timer count regs */
+void perf_reset_clock(void)
+{
+ perf_disable_clock();
+ *(volatile unsigned int *)SCU_GLOBAL_TIMER_COUNT_L32 = 0;
+ *(volatile unsigned int *)SCU_GLOBAL_TIMER_COUNT_U32 = 0;
+}
+
+/* Compute mask for given delay in miliseconds*/
+int get_number_of_cycles_for_delay(unsigned int delay)
+{
+ /* GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x) */
+ return APU_FREQ * delay / (2 * 1000);
+}
+
+/* stop timer */
+void perf_disable_clock(void)
+{
+ *(volatile unsigned int *)SCU_GLOBAL_TIMER_CONTROL = 0;
+}
+
+void perf_reset_and_start_timer(void)
+{
+ perf_reset_clock();
+ perf_start_clock();
+}
--- /dev/null
+/*
+ * Copyright (c) Xilinx, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*typedef unsigned int u32; */
+
+/** do we need to make this name more unique ? **/
+/*extern u32 ps7_init_data[]; */
+extern unsigned long *ps7_ddr_init_data;
+extern unsigned long *ps7_mio_init_data;
+extern unsigned long *ps7_pll_init_data;
+extern unsigned long *ps7_clock_init_data;
+extern unsigned long *ps7_peripherals_init_data;
+
+#define OPCODE_EXIT 0U
+#define OPCODE_CLEAR 1U
+#define OPCODE_WRITE 2U
+#define OPCODE_MASKWRITE 3U
+#define OPCODE_MASKPOLL 4U
+#define OPCODE_MASKDELAY 5U
+#define NEW_PS7_ERR_CODE 1
+
+/* Encode number of arguments in last nibble */
+#define EMIT_EXIT() ((OPCODE_EXIT << 4) | 0)
+#define EMIT_CLEAR(addr) ((OPCODE_CLEAR << 4) | 1) , addr
+#define EMIT_WRITE(addr, val) ((OPCODE_WRITE << 4) | 2) , addr, val
+#define EMIT_MASKWRITE(addr, mask, val) ((OPCODE_MASKWRITE << 4) | 3) , addr, mask, val
+#define EMIT_MASKPOLL(addr, mask) ((OPCODE_MASKPOLL << 4) | 2) , addr, mask
+#define EMIT_MASKDELAY(addr, mask) ((OPCODE_MASKDELAY << 4) | 2) , addr, mask
+
+/* Returns codes of PS7_Init */
+#define PS7_INIT_SUCCESS (0) /* 0 is success in good old C */
+#define PS7_INIT_CORRUPT (1) /* 1 the data is corrupted, and slcr reg are in corrupted state now */
+#define PS7_INIT_TIMEOUT (2) /* 2 when a poll operation timed out */
+#define PS7_POLL_FAILED_DDR_INIT (3) /* 3 when a poll operation timed out for ddr init */
+#define PS7_POLL_FAILED_DMA (4) /* 4 when a poll operation timed out for dma done bit */
+#define PS7_POLL_FAILED_PLL (5) /* 5 when a poll operation timed out for pll sequence init */
+
+/* Silicon Versions */
+#define PCW_SILICON_VERSION_1 0
+#define PCW_SILICON_VERSION_2 1
+#define PCW_SILICON_VERSION_3 2
+
+/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
+#define PS7_POST_CONFIG
+
+/* Freq of all peripherals */
+
+#define APU_FREQ 650000000
+#define DDR_FREQ 525000000
+#define DCI_FREQ 10096154
+#define QSPI_FREQ 200000000
+#define SMC_FREQ 10000000
+#define ENET0_FREQ 125000000
+#define ENET1_FREQ 10000000
+#define USB0_FREQ 60000000
+#define USB1_FREQ 60000000
+#define SDIO_FREQ 50000000
+#define UART_FREQ 100000000
+#define SPI_FREQ 10000000
+#define I2C_FREQ 108333336
+#define WDT_FREQ 108333336
+#define TTC_FREQ 50000000
+#define CAN_FREQ 10000000
+#define PCAP_FREQ 200000000
+#define TPIU_FREQ 200000000
+#define FPGA0_FREQ 100000000
+#define FPGA1_FREQ 142857132
+#define FPGA2_FREQ 200000000
+#define FPGA3_FREQ 50000000
+
+
+/* For delay calculation using global registers*/
+#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
+#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204
+#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208
+#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218
+
+int ps7_config(unsigned long *);
+int ps7_init(void);
+int ps7_post_config(void);
+int ps7_debug(void);
+char *getPS7MessageInfo(unsigned key);
+
+void perf_start_clock(void);
+void perf_disable_clock(void);
+void perf_reset_clock(void);
+void perf_reset_and_start_timer(void);
+int get_number_of_cycles_for_delay(unsigned int delay);
+#ifdef __cplusplus
+}
+#endif
#
-# (C) Copyright 2014 - 2015 Xilinx, Inc.
+# (C) Copyright 2014 - 2016 Xilinx, Inc.
# Michal Simek <michal.simek@xilinx.com>
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y := zynqmp.o
+
+hw-platform-y :=$(shell echo $(CONFIG_SYS_CONFIG_NAME))
+
+init-objs := $(if $(wildcard $(srctree)/$(src)/$(hw-platform-y)/psu_init_gpl.c),\
+ $(hw-platform-y)/psu_init_gpl.o)
+
+ifeq ($(init-objs),)
+ifneq ($(wildcard $(srctree)/$(src)/psu_init_gpl.c),)
+init-objs := psu_init_gpl.o
+$(if $(CONFIG_SPL_BUILD),\
+$(warning Put custom psu_init_gpl.c/h to board/xilinx/zynqmp/custom_hw_platform/))
+endif
+endif
+
+obj-$(CONFIG_SPL_BUILD) += $(init-objs)
+
+# Suppress "warning: function declaration isn't a prototype"
+CFLAGS_REMOVE_psu_init_gpl.o := -Wstrict-prototypes
+
+# To include xil_io.h
+CFLAGS_psu_init_gpl.o := -I$(srctree)/$(src)
--- /dev/null
+/*
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef XIL_IO_H /* prevent circular inclusions */
+#define XIL_IO_H
+
+/* FIXME remove this when vivado is fixed */
+#include <asm/io.h>
+
+#define xil_printf(...)
+
+void Xil_ICacheEnable(void)
+{}
+
+void Xil_DCacheEnable(void)
+{}
+
+void Xil_ICacheDisable(void)
+{}
+
+void Xil_DCacheDisable(void)
+{}
+
+void Xil_Out32(unsigned long addr, unsigned long val)
+{
+ writel(val, addr);
+}
+
+int Xil_In32(unsigned long addr)
+{
+ return readl(addr);
+}
+
+#endif /* XIL_IO_H */
#include <asm/io.h>
#include <usb.h>
#include <dwc3-uboot.h>
+#include <i2c.h>
DECLARE_GLOBAL_DATA_PTR;
return 0;
}
+int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
+{
+#if defined(CONFIG_ZYNQ_GEM_EEPROM_ADDR) && \
+ defined(CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET) && \
+ defined(CONFIG_ZYNQ_EEPROM_BUS)
+ i2c_set_bus_num(CONFIG_ZYNQ_EEPROM_BUS);
+
+ if (eeprom_read(CONFIG_ZYNQ_GEM_EEPROM_ADDR,
+ CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET,
+ ethaddr, 6))
+ printf("I2C EEPROM MAC address read failed\n");
+#endif
+
+ return 0;
+}
+
#if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
/*
* fdt_get_reg - Fill buffer by information from DT
sound init - set up sound system
sound play - play a sound
+config CMD_QFW
+ bool "qfw"
+ select QFW
+ help
+ This provides access to the QEMU firmware interface. The main
+ feature is to allow easy loading of files passed to qemu-system
+ via -kernel / -initrd
endmenu
config CMD_BOOTSTAGE
obj-y += pcmcia.o
obj-$(CONFIG_CMD_PORTIO) += portio.o
obj-$(CONFIG_CMD_PXE) += pxe.o
+obj-$(CONFIG_CMD_QFW) += qfw.o
obj-$(CONFIG_CMD_READ) += read.o
obj-$(CONFIG_CMD_REGINFO) += reginfo.o
obj-$(CONFIG_CMD_REISER) += reiser.o
obj-$(CONFIG_SANDBOX) += host.o
obj-$(CONFIG_CMD_SATA) += sata.o
obj-$(CONFIG_CMD_SF) += sf.o
-obj-$(CONFIG_CMD_SCSI) += scsi.o
+obj-$(CONFIG_SCSI) += scsi.o
obj-$(CONFIG_CMD_SHA1SUM) += sha1sum.o
obj-$(CONFIG_CMD_SETEXPR) += setexpr.o
obj-$(CONFIG_CMD_SOFTSWITCH) += softswitch.o
obj-$(CONFIG_CMD_REGULATOR) += regulator.o
endif # !CONFIG_SPL_BUILD
-ifdef CONFIG_SPL_BUILD
-ifdef CONFIG_SPL_SATA_SUPPORT
-obj-$(CONFIG_CMD_SCSI) += scsi.o
-endif
-endif # CONFIG_SPL_BUILD
-
obj-$(CONFIG_CMD_BLOB) += blob.o
# core command
print_eth(0);
printf("ip_addr = %s\n", getenv("ipaddr"));
printf("baudrate = %u bps\n", gd->baudrate);
+ print_num("relocaddr", gd->relocaddr);
+ print_num("reloc off", gd->reloc_off);
return 0;
}
#include <command.h>
#include <part.h>
-#if defined(CONFIG_CMD_IDE) || defined(CONFIG_CMD_SCSI) || \
+#if defined(CONFIG_CMD_IDE) || defined(CONFIG_SCSI) || \
defined(CONFIG_USB_STORAGE)
int common_diskboot(cmd_tbl_t *cmdtp, const char *intf, int argc,
char *const argv[])
#include <config.h>
#include <command.h>
#include <i2c.h>
+#include <eeprom_layout.h>
#ifndef CONFIG_SYS_I2C_SPEED
#define CONFIG_SYS_I2C_SPEED 50000
#endif
/* I2C EEPROM */
-#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C_SOFT)
+#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C)
#if defined(CONFIG_SYS_I2C)
if (bus >= 0)
i2c_set_bus_num(bus);
return ret;
}
-static int do_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int parse_numeric_param(char *str)
{
- const char *const fmt =
- "\nEEPROM @0x%lX %s: addr %08lx off %04lx count %ld ... ";
- char * const *args = &argv[2];
- int rcode;
- ulong dev_addr, addr, off, cnt;
- int bus_addr;
+ char *endptr;
+ int value = simple_strtol(str, &endptr, 16);
+
+ return (*endptr != '\0') ? -1 : value;
+}
+
+/**
+ * parse_i2c_bus_addr - parse the i2c bus and i2c devaddr parameters
+ *
+ * @i2c_bus: address to store the i2c bus
+ * @i2c_addr: address to store the device i2c address
+ * @argc: count of command line arguments left to parse
+ * @argv: command line arguments left to parse
+ * @argc_no_bus_addr: argc value we expect to see when bus & addr aren't given
+ *
+ * @returns: number of arguments parsed or CMD_RET_USAGE if error
+ */
+static int parse_i2c_bus_addr(int *i2c_bus, ulong *i2c_addr, int argc,
+ char * const argv[], int argc_no_bus_addr)
+{
+ int argc_no_bus = argc_no_bus_addr + 1;
+ int argc_bus_addr = argc_no_bus_addr + 2;
- switch (argc) {
#ifdef CONFIG_SYS_DEF_EEPROM_ADDR
- case 5:
- bus_addr = -1;
- dev_addr = CONFIG_SYS_DEF_EEPROM_ADDR;
- break;
+ if (argc == argc_no_bus_addr) {
+ *i2c_bus = -1;
+ *i2c_addr = CONFIG_SYS_DEF_EEPROM_ADDR;
+
+ return 0;
+ }
#endif
- case 6:
- bus_addr = -1;
- dev_addr = simple_strtoul(*args++, NULL, 16);
- break;
- case 7:
- bus_addr = simple_strtoul(*args++, NULL, 16);
- dev_addr = simple_strtoul(*args++, NULL, 16);
- break;
- default:
- return CMD_RET_USAGE;
+ if (argc == argc_no_bus) {
+ *i2c_bus = -1;
+ *i2c_addr = parse_numeric_param(argv[0]);
+
+ return 1;
}
- addr = simple_strtoul(*args++, NULL, 16);
- off = simple_strtoul(*args++, NULL, 16);
- cnt = simple_strtoul(*args++, NULL, 16);
+ if (argc == argc_bus_addr) {
+ *i2c_bus = parse_numeric_param(argv[0]);
+ *i2c_addr = parse_numeric_param(argv[1]);
+
+ return 2;
+ }
+
+ return CMD_RET_USAGE;
+}
+
+#ifdef CONFIG_CMD_EEPROM_LAYOUT
+
+__weak int eeprom_parse_layout_version(char *str)
+{
+ return LAYOUT_VERSION_UNRECOGNIZED;
+}
- eeprom_init(bus_addr);
+static unsigned char eeprom_buf[CONFIG_SYS_EEPROM_SIZE];
- if (strcmp(argv[1], "read") == 0) {
- printf(fmt, dev_addr, argv[1], addr, off, cnt);
+#ifndef CONFIG_EEPROM_LAYOUT_HELP_STRING
+#define CONFIG_EEPROM_LAYOUT_HELP_STRING "<not defined>"
+#endif
- rcode = eeprom_read(dev_addr, off, (uchar *)addr, cnt);
+#endif
+
+enum eeprom_action {
+ EEPROM_READ,
+ EEPROM_WRITE,
+ EEPROM_PRINT,
+ EEPROM_UPDATE,
+ EEPROM_ACTION_INVALID,
+};
+
+static enum eeprom_action parse_action(char *cmd)
+{
+ if (!strncmp(cmd, "read", 4))
+ return EEPROM_READ;
+ if (!strncmp(cmd, "write", 5))
+ return EEPROM_WRITE;
+#ifdef CONFIG_CMD_EEPROM_LAYOUT
+ if (!strncmp(cmd, "print", 5))
+ return EEPROM_PRINT;
+ if (!strncmp(cmd, "update", 6))
+ return EEPROM_UPDATE;
+#endif
+
+ return EEPROM_ACTION_INVALID;
+}
+
+static int eeprom_execute_command(enum eeprom_action action, int i2c_bus,
+ ulong i2c_addr, int layout_ver, char *key,
+ char *value, ulong addr, ulong off, ulong cnt)
+{
+ int rcode = 0;
+ const char *const fmt =
+ "\nEEPROM @0x%lX %s: addr %08lx off %04lx count %ld ... ";
+#ifdef CONFIG_CMD_EEPROM_LAYOUT
+ struct eeprom_layout layout;
+#endif
+
+ if (action == EEPROM_ACTION_INVALID)
+ return CMD_RET_USAGE;
+
+ eeprom_init(i2c_bus);
+ if (action == EEPROM_READ) {
+ printf(fmt, i2c_addr, "read", addr, off, cnt);
+
+ rcode = eeprom_read(i2c_addr, off, (uchar *)addr, cnt);
puts("done\n");
return rcode;
- } else if (strcmp(argv[1], "write") == 0) {
- printf(fmt, dev_addr, argv[1], addr, off, cnt);
+ } else if (action == EEPROM_WRITE) {
+ printf(fmt, i2c_addr, "write", addr, off, cnt);
- rcode = eeprom_write(dev_addr, off, (uchar *)addr, cnt);
+ rcode = eeprom_write(i2c_addr, off, (uchar *)addr, cnt);
puts("done\n");
return rcode;
}
- return CMD_RET_USAGE;
+#ifdef CONFIG_CMD_EEPROM_LAYOUT
+ rcode = eeprom_read(i2c_addr, 0, eeprom_buf, CONFIG_SYS_EEPROM_SIZE);
+ if (rcode < 0)
+ return rcode;
+
+ eeprom_layout_setup(&layout, eeprom_buf, CONFIG_SYS_EEPROM_SIZE,
+ layout_ver);
+
+ if (action == EEPROM_PRINT) {
+ layout.print(&layout);
+ return 0;
+ }
+
+ layout.update(&layout, key, value);
+
+ rcode = eeprom_write(i2c_addr, 0, layout.data, CONFIG_SYS_EEPROM_SIZE);
+#endif
+
+ return rcode;
+}
+
+#define NEXT_PARAM(argc, index) { (argc)--; (index)++; }
+int do_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ int layout_ver = LAYOUT_VERSION_AUTODETECT;
+ enum eeprom_action action = EEPROM_ACTION_INVALID;
+ int i2c_bus = -1, index = 0;
+ ulong i2c_addr = -1, addr = 0, cnt = 0, off = 0;
+ int ret;
+ char *field_name = "";
+ char *field_value = "";
+
+ if (argc <= 1)
+ return CMD_RET_USAGE;
+
+ NEXT_PARAM(argc, index); /* Skip program name */
+
+ action = parse_action(argv[index]);
+ NEXT_PARAM(argc, index);
+
+ if (action == EEPROM_ACTION_INVALID)
+ return CMD_RET_USAGE;
+
+#ifdef CONFIG_CMD_EEPROM_LAYOUT
+ if (action == EEPROM_PRINT || action == EEPROM_UPDATE) {
+ if (!strcmp(argv[index], "-l")) {
+ NEXT_PARAM(argc, index);
+ layout_ver = eeprom_parse_layout_version(argv[index]);
+ NEXT_PARAM(argc, index);
+ }
+ }
+#endif
+
+ switch (action) {
+ case EEPROM_READ:
+ case EEPROM_WRITE:
+ ret = parse_i2c_bus_addr(&i2c_bus, &i2c_addr, argc,
+ argv + index, 3);
+ break;
+ case EEPROM_PRINT:
+ ret = parse_i2c_bus_addr(&i2c_bus, &i2c_addr, argc,
+ argv + index, 0);
+ break;
+ case EEPROM_UPDATE:
+ ret = parse_i2c_bus_addr(&i2c_bus, &i2c_addr, argc,
+ argv + index, 2);
+ break;
+ default:
+ /* Get compiler to stop whining */
+ return CMD_RET_USAGE;
+ }
+
+ if (ret == CMD_RET_USAGE)
+ return ret;
+
+ while (ret--)
+ NEXT_PARAM(argc, index);
+
+ if (action == EEPROM_READ || action == EEPROM_WRITE) {
+ addr = parse_numeric_param(argv[index]);
+ NEXT_PARAM(argc, index);
+ off = parse_numeric_param(argv[index]);
+ NEXT_PARAM(argc, index);
+ cnt = parse_numeric_param(argv[index]);
+ }
+
+#ifdef CONFIG_CMD_EEPROM_LAYOUT
+ if (action == EEPROM_UPDATE) {
+ field_name = argv[index];
+ NEXT_PARAM(argc, index);
+ field_value = argv[index];
+ NEXT_PARAM(argc, index);
+ }
+#endif
+
+ return eeprom_execute_command(action, i2c_bus, i2c_addr, layout_ver,
+ field_name, field_value, addr, off, cnt);
}
U_BOOT_CMD(
- eeprom, 7, 1, do_eeprom,
+ eeprom, 8, 1, do_eeprom,
"EEPROM sub-system",
"read <bus> <devaddr> addr off cnt\n"
"eeprom write <bus> <devaddr> addr off cnt\n"
" - read/write `cnt' bytes from `devaddr` EEPROM at offset `off'"
+#ifdef CONFIG_CMD_EEPROM_LAYOUT
+ "\n"
+ "eeprom print [-l <layout_version>] <bus> <devaddr>\n"
+ " - Print layout fields and their data in human readable format\n"
+ "eeprom update [-l <layout_version>] <bus> <devaddr> field_name field_value\n"
+ " - Update a specific eeprom field with new data.\n"
+ " The new data must be written in the same human readable format as shown by the print command.\n"
+ "\n"
+ "LAYOUT VERSIONS\n"
+ "The -l option can be used to force the command to interpret the EEPROM data using the chosen layout.\n"
+ "If the -l option is omitted, the command will auto detect the layout based on the data in the EEPROM.\n"
+ "The values which can be provided with the -l option are:\n"
+ CONFIG_EEPROM_LAYOUT_HELP_STRING"\n"
+#endif
)
# include <status_led.h>
#endif
-#ifdef __PPC__
-# define EIEIO __asm__ volatile ("eieio")
-# define SYNC __asm__ volatile ("sync")
-#else
-# define EIEIO /* nothing */
-# define SYNC /* nothing */
-#endif
-
-/* ------------------------------------------------------------------------- */
-
/* Current I/O Device */
static int curr_device = -1;
-/* Current offset for IDE0 / IDE1 bus access */
-ulong ide_bus_offset[CONFIG_SYS_IDE_MAXBUS] = {
-#if defined(CONFIG_SYS_ATA_IDE0_OFFSET)
- CONFIG_SYS_ATA_IDE0_OFFSET,
-#endif
-#if defined(CONFIG_SYS_ATA_IDE1_OFFSET) && (CONFIG_SYS_IDE_MAXBUS > 1)
- CONFIG_SYS_ATA_IDE1_OFFSET,
-#endif
-};
-
-static int ide_bus_ok[CONFIG_SYS_IDE_MAXBUS];
-
-struct blk_desc ide_dev_desc[CONFIG_SYS_IDE_MAXDEVICE];
-/* ------------------------------------------------------------------------- */
-
-#ifdef CONFIG_IDE_RESET
-static void ide_reset (void);
-#else
-#define ide_reset() /* dummy */
-#endif
-
-static void ide_ident(struct blk_desc *dev_desc);
-static uchar ide_wait (int dev, ulong t);
-
-#define IDE_TIME_OUT 2000 /* 2 sec timeout */
-
-#define ATAPI_TIME_OUT 7000 /* 7 sec timeout (5 sec seems to work...) */
-
-#define IDE_SPIN_UP_TIME_OUT 5000 /* 5 sec spin-up timeout */
-
-static void ident_cpy (unsigned char *dest, unsigned char *src, unsigned int len);
-
-#ifndef CONFIG_SYS_ATA_PORT_ADDR
-#define CONFIG_SYS_ATA_PORT_ADDR(port) (port)
-#endif
-
-#ifdef CONFIG_ATAPI
-static void atapi_inquiry(struct blk_desc *dev_desc);
-static ulong atapi_read(struct blk_desc *block_dev, lbaint_t blknr,
- lbaint_t blkcnt, void *buffer);
-#endif
-
-
-/* ------------------------------------------------------------------------- */
-
int do_ide(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
{
int rcode = 0;
ide_init();
return 0;
} else if (strncmp(argv[1], "inf", 3) == 0) {
- int i;
-
- putc('\n');
-
- for (i = 0; i < CONFIG_SYS_IDE_MAXDEVICE; ++i) {
- if (ide_dev_desc[i].type == DEV_TYPE_UNKNOWN)
- continue; /* list only known devices */
- printf("IDE device %d: ", i);
- dev_print(&ide_dev_desc[i]);
- }
+ blk_list_devices(IF_TYPE_IDE);
return 0;
} else if (strncmp(argv[1], "dev", 3) == 0) {
- if ((curr_device < 0)
- || (curr_device >= CONFIG_SYS_IDE_MAXDEVICE)) {
- puts("\nno IDE devices available\n");
- return 1;
+ if (blk_print_device_num(IF_TYPE_IDE, curr_device)) {
+ printf("\nno IDE devices available\n");
+ return CMD_RET_FAILURE;
}
- printf("\nIDE device %d: ", curr_device);
- dev_print(&ide_dev_desc[curr_device]);
+
return 0;
} else if (strncmp(argv[1], "part", 4) == 0) {
- int dev, ok;
-
- for (ok = 0, dev = 0;
- dev < CONFIG_SYS_IDE_MAXDEVICE;
- ++dev) {
- if (ide_dev_desc[dev].part_type !=
- PART_TYPE_UNKNOWN) {
- ++ok;
- if (dev)
- putc('\n');
- part_print(&ide_dev_desc[dev]);
- }
- }
- if (!ok) {
- puts("\nno IDE devices available\n");
- rcode++;
- }
- return rcode;
+ if (blk_list_part(IF_TYPE_IDE))
+ printf("\nno IDE devices available\n");
+ return 1;
}
return CMD_RET_USAGE;
case 3:
if (strncmp(argv[1], "dev", 3) == 0) {
- int dev = (int) simple_strtoul(argv[2], NULL, 10);
+ int dev = (int)simple_strtoul(argv[2], NULL, 10);
- printf("\nIDE device %d: ", dev);
- if (dev >= CONFIG_SYS_IDE_MAXDEVICE) {
- puts("unknown device\n");
- return 1;
+ if (!blk_show_device(IF_TYPE_IDE, dev)) {
+ curr_device = dev;
+ printf("... is now current device\n");
+ } else {
+ return CMD_RET_FAILURE;
}
- dev_print(&ide_dev_desc[dev]);
- /*ide_print (dev); */
-
- if (ide_dev_desc[dev].type == DEV_TYPE_UNKNOWN)
- return 1;
-
- curr_device = dev;
-
- puts("... is now current device\n");
-
return 0;
} else if (strncmp(argv[1], "part", 4) == 0) {
- int dev = (int) simple_strtoul(argv[2], NULL, 10);
+ int dev = (int)simple_strtoul(argv[2], NULL, 10);
- if (ide_dev_desc[dev].part_type != PART_TYPE_UNKNOWN) {
- part_print(&ide_dev_desc[dev]);
- } else {
- printf("\nIDE device %d not available\n",
- dev);
- rcode = 1;
+ if (blk_print_part_devnum(IF_TYPE_IDE, dev)) {
+ printf("\nIDE device %d not available\n", dev);
+ return CMD_RET_FAILURE;
}
- return rcode;
+ return 1;
}
return CMD_RET_USAGE;
if (strcmp(argv[1], "read") == 0) {
ulong addr = simple_strtoul(argv[2], NULL, 16);
ulong cnt = simple_strtoul(argv[4], NULL, 16);
- struct blk_desc *dev_desc;
ulong n;
#ifdef CONFIG_SYS_64BIT_LBA
lbaint_t blk = simple_strtoull(argv[3], NULL, 16);
- printf("\nIDE read: device %d block # %lld, count %ld ... ",
- curr_device, blk, cnt);
+ printf("\nIDE read: device %d block # %lld, count %ld...",
+ curr_device, blk, cnt);
#else
lbaint_t blk = simple_strtoul(argv[3], NULL, 16);
- printf("\nIDE read: device %d block # %ld, count %ld ... ",
- curr_device, blk, cnt);
+ printf("\nIDE read: device %d block # %ld, count %ld...",
+ curr_device, blk, cnt);
#endif
- dev_desc = &ide_dev_desc[curr_device];
- n = blk_dread(dev_desc, blk, cnt, (ulong *)addr);
- /* flush cache after read */
- flush_cache(addr,
- cnt * ide_dev_desc[curr_device].blksz);
+ n = blk_read_devnum(IF_TYPE_IDE, curr_device, blk, cnt,
+ (ulong *)addr);
printf("%ld blocks read: %s\n",
n, (n == cnt) ? "OK" : "ERROR");
#ifdef CONFIG_SYS_64BIT_LBA
lbaint_t blk = simple_strtoull(argv[3], NULL, 16);
- printf("\nIDE write: device %d block # %lld, count %ld ... ",
- curr_device, blk, cnt);
+ printf("\nIDE write: device %d block # %lld, count %ld...",
+ curr_device, blk, cnt);
#else
lbaint_t blk = simple_strtoul(argv[3], NULL, 16);
- printf("\nIDE write: device %d block # %ld, count %ld ... ",
- curr_device, blk, cnt);
+ printf("\nIDE write: device %d block # %ld, count %ld...",
+ curr_device, blk, cnt);
#endif
- n = ide_write(&ide_dev_desc[curr_device], blk, cnt,
- (ulong *)addr);
+ n = blk_write_devnum(IF_TYPE_IDE, curr_device, blk, cnt,
+ (ulong *)addr);
- printf("%ld blocks written: %s\n",
- n, (n == cnt) ? "OK" : "ERROR");
+ printf("%ld blocks written: %s\n", n,
+ n == cnt ? "OK" : "ERROR");
if (n == cnt)
return 0;
else
return common_diskboot(cmdtp, "ide", argc, argv);
}
-/* ------------------------------------------------------------------------- */
-
-__weak void ide_led(uchar led, uchar status)
-{
-#if defined(CONFIG_IDE_LED) && defined(PER8_BASE) /* required by LED_PORT */
- static uchar led_buffer; /* Buffer for current LED status */
-
- uchar *led_port = LED_PORT;
-
- if (status) /* switch LED on */
- led_buffer |= led;
- else /* switch LED off */
- led_buffer &= ~led;
-
- *led_port = led_buffer;
-#endif
-}
-
-#ifndef CONFIG_IDE_LED /* define LED macros, they are not used anyways */
-# define DEVICE_LED(x) 0
-# define LED_IDE1 1
-# define LED_IDE2 2
-#endif
-
-/* ------------------------------------------------------------------------- */
-
-__weak void ide_outb(int dev, int port, unsigned char val)
-{
- debug("ide_outb (dev= %d, port= 0x%x, val= 0x%02x) : @ 0x%08lx\n",
- dev, port, val,
- (ATA_CURR_BASE(dev) + CONFIG_SYS_ATA_PORT_ADDR(port)));
-
-#if defined(CONFIG_IDE_AHB)
- if (port) {
- /* write command */
- ide_write_register(dev, port, val);
- } else {
- /* write data */
- outb(val, (ATA_CURR_BASE(dev)));
- }
-#else
- outb(val, (ATA_CURR_BASE(dev) + CONFIG_SYS_ATA_PORT_ADDR(port)));
-#endif
-}
-
-__weak unsigned char ide_inb(int dev, int port)
-{
- uchar val;
-
-#if defined(CONFIG_IDE_AHB)
- val = ide_read_register(dev, port);
-#else
- val = inb((ATA_CURR_BASE(dev) + CONFIG_SYS_ATA_PORT_ADDR(port)));
-#endif
-
- debug("ide_inb (dev= %d, port= 0x%x) : @ 0x%08lx -> 0x%02x\n",
- dev, port,
- (ATA_CURR_BASE(dev) + CONFIG_SYS_ATA_PORT_ADDR(port)), val);
- return val;
-}
-
-void ide_init(void)
-{
- unsigned char c;
- int i, bus;
-
-#ifdef CONFIG_IDE_8xx_PCCARD
- extern int ide_devices_found; /* Initialized in check_ide_device() */
-#endif /* CONFIG_IDE_8xx_PCCARD */
-
-#ifdef CONFIG_IDE_PREINIT
- WATCHDOG_RESET();
-
- if (ide_preinit()) {
- puts("ide_preinit failed\n");
- return;
- }
-#endif /* CONFIG_IDE_PREINIT */
-
- WATCHDOG_RESET();
-
- /*
- * Reset the IDE just to be sure.
- * Light LED's to show
- */
- ide_led((LED_IDE1 | LED_IDE2), 1); /* LED's on */
-
- /* ATAPI Drives seems to need a proper IDE Reset */
- ide_reset();
-
-#ifdef CONFIG_IDE_INIT_POSTRESET
- WATCHDOG_RESET();
-
- if (ide_init_postreset()) {
- puts("ide_preinit_postreset failed\n");
- return;
- }
-#endif /* CONFIG_IDE_INIT_POSTRESET */
-
- /*
- * Wait for IDE to get ready.
- * According to spec, this can take up to 31 seconds!
- */
- for (bus = 0; bus < CONFIG_SYS_IDE_MAXBUS; ++bus) {
- int dev =
- bus * (CONFIG_SYS_IDE_MAXDEVICE /
- CONFIG_SYS_IDE_MAXBUS);
-
-#ifdef CONFIG_IDE_8xx_PCCARD
- /* Skip non-ide devices from probing */
- if ((ide_devices_found & (1 << bus)) == 0) {
- ide_led((LED_IDE1 | LED_IDE2), 0); /* LED's off */
- continue;
- }
-#endif
- printf("Bus %d: ", bus);
-
- ide_bus_ok[bus] = 0;
-
- /* Select device
- */
- udelay(100000); /* 100 ms */
- ide_outb(dev, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(dev));
- udelay(100000); /* 100 ms */
- i = 0;
- do {
- udelay(10000); /* 10 ms */
-
- c = ide_inb(dev, ATA_STATUS);
- i++;
- if (i > (ATA_RESET_TIME * 100)) {
- puts("** Timeout **\n");
- /* LED's off */
- ide_led((LED_IDE1 | LED_IDE2), 0);
- return;
- }
- if ((i >= 100) && ((i % 100) == 0))
- putc('.');
-
- } while (c & ATA_STAT_BUSY);
-
- if (c & (ATA_STAT_BUSY | ATA_STAT_FAULT)) {
- puts("not available ");
- debug("Status = 0x%02X ", c);
-#ifndef CONFIG_ATAPI /* ATAPI Devices do not set DRDY */
- } else if ((c & ATA_STAT_READY) == 0) {
- puts("not available ");
- debug("Status = 0x%02X ", c);
-#endif
- } else {
- puts("OK ");
- ide_bus_ok[bus] = 1;
- }
- WATCHDOG_RESET();
- }
-
- putc('\n');
-
- ide_led((LED_IDE1 | LED_IDE2), 0); /* LED's off */
-
- curr_device = -1;
- for (i = 0; i < CONFIG_SYS_IDE_MAXDEVICE; ++i) {
- int led = (IDE_BUS(i) == 0) ? LED_IDE1 : LED_IDE2;
- ide_dev_desc[i].type = DEV_TYPE_UNKNOWN;
- ide_dev_desc[i].if_type = IF_TYPE_IDE;
- ide_dev_desc[i].devnum = i;
- ide_dev_desc[i].part_type = PART_TYPE_UNKNOWN;
- ide_dev_desc[i].blksz = 0;
- ide_dev_desc[i].log2blksz =
- LOG2_INVALID(typeof(ide_dev_desc[i].log2blksz));
- ide_dev_desc[i].lba = 0;
- ide_dev_desc[i].block_read = ide_read;
- ide_dev_desc[i].block_write = ide_write;
- if (!ide_bus_ok[IDE_BUS(i)])
- continue;
- ide_led(led, 1); /* LED on */
- ide_ident(&ide_dev_desc[i]);
- ide_led(led, 0); /* LED off */
- dev_print(&ide_dev_desc[i]);
-
- if ((ide_dev_desc[i].lba > 0) && (ide_dev_desc[i].blksz > 0)) {
- /* initialize partition type */
- part_init(&ide_dev_desc[i]);
- if (curr_device < 0)
- curr_device = i;
- }
- }
- WATCHDOG_RESET();
-}
-
-/* ------------------------------------------------------------------------- */
-
-#ifdef CONFIG_PARTITIONS
-struct blk_desc *ide_get_dev(int dev)
-{
- return (dev < CONFIG_SYS_IDE_MAXDEVICE) ? &ide_dev_desc[dev] : NULL;
-}
-#endif
-
-/* ------------------------------------------------------------------------- */
-
-/* We only need to swap data if we are running on a big endian cpu. */
-#if defined(__LITTLE_ENDIAN)
-__weak void ide_input_swap_data(int dev, ulong *sect_buf, int words)
-{
- ide_input_data(dev, sect_buf, words);
-}
-#else
-__weak void ide_input_swap_data(int dev, ulong *sect_buf, int words)
-{
- volatile ushort *pbuf =
- (ushort *) (ATA_CURR_BASE(dev) + ATA_DATA_REG);
- ushort *dbuf = (ushort *) sect_buf;
-
- debug("in input swap data base for read is %lx\n",
- (unsigned long) pbuf);
-
- while (words--) {
-#ifdef __MIPS__
- *dbuf++ = swab16p((u16 *) pbuf);
- *dbuf++ = swab16p((u16 *) pbuf);
-#else
- *dbuf++ = ld_le16(pbuf);
- *dbuf++ = ld_le16(pbuf);
-#endif /* !MIPS */
- }
-}
-#endif /* __LITTLE_ENDIAN */
-
-
-#if defined(CONFIG_IDE_SWAP_IO)
-__weak void ide_output_data(int dev, const ulong *sect_buf, int words)
-{
- ushort *dbuf;
- volatile ushort *pbuf;
-
- pbuf = (ushort *) (ATA_CURR_BASE(dev) + ATA_DATA_REG);
- dbuf = (ushort *) sect_buf;
- while (words--) {
- EIEIO;
- *pbuf = *dbuf++;
- EIEIO;
- *pbuf = *dbuf++;
- }
-}
-#else /* ! CONFIG_IDE_SWAP_IO */
-__weak void ide_output_data(int dev, const ulong *sect_buf, int words)
-{
-#if defined(CONFIG_IDE_AHB)
- ide_write_data(dev, sect_buf, words);
-#else
- outsw(ATA_CURR_BASE(dev) + ATA_DATA_REG, sect_buf, words << 1);
-#endif
-}
-#endif /* CONFIG_IDE_SWAP_IO */
-
-#if defined(CONFIG_IDE_SWAP_IO)
-__weak void ide_input_data(int dev, ulong *sect_buf, int words)
-{
- ushort *dbuf;
- volatile ushort *pbuf;
-
- pbuf = (ushort *) (ATA_CURR_BASE(dev) + ATA_DATA_REG);
- dbuf = (ushort *) sect_buf;
-
- debug("in input data base for read is %lx\n", (unsigned long) pbuf);
-
- while (words--) {
- EIEIO;
- *dbuf++ = *pbuf;
- EIEIO;
- *dbuf++ = *pbuf;
- }
-}
-#else /* ! CONFIG_IDE_SWAP_IO */
-__weak void ide_input_data(int dev, ulong *sect_buf, int words)
-{
-#if defined(CONFIG_IDE_AHB)
- ide_read_data(dev, sect_buf, words);
-#else
- insw(ATA_CURR_BASE(dev) + ATA_DATA_REG, sect_buf, words << 1);
-#endif
-}
-
-#endif /* CONFIG_IDE_SWAP_IO */
-
-/* -------------------------------------------------------------------------
- */
-static void ide_ident(struct blk_desc *dev_desc)
-{
- unsigned char c;
- hd_driveid_t iop;
-
-#ifdef CONFIG_ATAPI
- int retries = 0;
-#endif
- int device;
-
- device = dev_desc->devnum;
- printf(" Device %d: ", device);
-
- ide_led(DEVICE_LED(device), 1); /* LED on */
- /* Select device
- */
- ide_outb(device, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(device));
- dev_desc->if_type = IF_TYPE_IDE;
-#ifdef CONFIG_ATAPI
-
- retries = 0;
-
- /* Warning: This will be tricky to read */
- while (retries <= 1) {
- /* check signature */
- if ((ide_inb(device, ATA_SECT_CNT) == 0x01) &&
- (ide_inb(device, ATA_SECT_NUM) == 0x01) &&
- (ide_inb(device, ATA_CYL_LOW) == 0x14) &&
- (ide_inb(device, ATA_CYL_HIGH) == 0xEB)) {
- /* ATAPI Signature found */
- dev_desc->if_type = IF_TYPE_ATAPI;
- /*
- * Start Ident Command
- */
- ide_outb(device, ATA_COMMAND, ATAPI_CMD_IDENT);
- /*
- * Wait for completion - ATAPI devices need more time
- * to become ready
- */
- c = ide_wait(device, ATAPI_TIME_OUT);
- } else
-#endif
- {
- /*
- * Start Ident Command
- */
- ide_outb(device, ATA_COMMAND, ATA_CMD_IDENT);
-
- /*
- * Wait for completion
- */
- c = ide_wait(device, IDE_TIME_OUT);
- }
- ide_led(DEVICE_LED(device), 0); /* LED off */
-
- if (((c & ATA_STAT_DRQ) == 0) ||
- ((c & (ATA_STAT_FAULT | ATA_STAT_ERR)) != 0)) {
-#ifdef CONFIG_ATAPI
- {
- /*
- * Need to soft reset the device
- * in case it's an ATAPI...
- */
- debug("Retrying...\n");
- ide_outb(device, ATA_DEV_HD,
- ATA_LBA | ATA_DEVICE(device));
- udelay(100000);
- ide_outb(device, ATA_COMMAND, 0x08);
- udelay(500000); /* 500 ms */
- }
- /*
- * Select device
- */
- ide_outb(device, ATA_DEV_HD,
- ATA_LBA | ATA_DEVICE(device));
- retries++;
-#else
- return;
-#endif
- }
-#ifdef CONFIG_ATAPI
- else
- break;
- } /* see above - ugly to read */
-
- if (retries == 2) /* Not found */
- return;
-#endif
-
- ide_input_swap_data(device, (ulong *)&iop, ATA_SECTORWORDS);
-
- ident_cpy((unsigned char *) dev_desc->revision, iop.fw_rev,
- sizeof(dev_desc->revision));
- ident_cpy((unsigned char *) dev_desc->vendor, iop.model,
- sizeof(dev_desc->vendor));
- ident_cpy((unsigned char *) dev_desc->product, iop.serial_no,
- sizeof(dev_desc->product));
-#ifdef __LITTLE_ENDIAN
- /*
- * firmware revision, model, and serial number have Big Endian Byte
- * order in Word. Convert all three to little endian.
- *
- * See CF+ and CompactFlash Specification Revision 2.0:
- * 6.2.1.6: Identify Drive, Table 39 for more details
- */
-
- strswab(dev_desc->revision);
- strswab(dev_desc->vendor);
- strswab(dev_desc->product);
-#endif /* __LITTLE_ENDIAN */
-
- if ((iop.config & 0x0080) == 0x0080)
- dev_desc->removable = 1;
- else
- dev_desc->removable = 0;
-
-#ifdef CONFIG_ATAPI
- if (dev_desc->if_type == IF_TYPE_ATAPI) {
- atapi_inquiry(dev_desc);
- return;
- }
-#endif /* CONFIG_ATAPI */
-
-#ifdef __BIG_ENDIAN
- /* swap shorts */
- dev_desc->lba = (iop.lba_capacity << 16) | (iop.lba_capacity >> 16);
-#else /* ! __BIG_ENDIAN */
- /*
- * do not swap shorts on little endian
- *
- * See CF+ and CompactFlash Specification Revision 2.0:
- * 6.2.1.6: Identfy Drive, Table 39, Word Address 57-58 for details.
- */
- dev_desc->lba = iop.lba_capacity;
-#endif /* __BIG_ENDIAN */
-
-#ifdef CONFIG_LBA48
- if (iop.command_set_2 & 0x0400) { /* LBA 48 support */
- dev_desc->lba48 = 1;
- dev_desc->lba = (unsigned long long) iop.lba48_capacity[0] |
- ((unsigned long long) iop.lba48_capacity[1] << 16) |
- ((unsigned long long) iop.lba48_capacity[2] << 32) |
- ((unsigned long long) iop.lba48_capacity[3] << 48);
- } else {
- dev_desc->lba48 = 0;
- }
-#endif /* CONFIG_LBA48 */
- /* assuming HD */
- dev_desc->type = DEV_TYPE_HARDDISK;
- dev_desc->blksz = ATA_BLOCKSIZE;
- dev_desc->log2blksz = LOG2(dev_desc->blksz);
- dev_desc->lun = 0; /* just to fill something in... */
-
-#if 0 /* only used to test the powersaving mode,
- * if enabled, the drive goes after 5 sec
- * in standby mode */
- ide_outb(device, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(device));
- c = ide_wait(device, IDE_TIME_OUT);
- ide_outb(device, ATA_SECT_CNT, 1);
- ide_outb(device, ATA_LBA_LOW, 0);
- ide_outb(device, ATA_LBA_MID, 0);
- ide_outb(device, ATA_LBA_HIGH, 0);
- ide_outb(device, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(device));
- ide_outb(device, ATA_COMMAND, 0xe3);
- udelay(50);
- c = ide_wait(device, IDE_TIME_OUT); /* can't take over 500 ms */
-#endif
-}
-
-
-/* ------------------------------------------------------------------------- */
-
-ulong ide_read(struct blk_desc *block_dev, lbaint_t blknr, lbaint_t blkcnt,
- void *buffer)
-{
- int device = block_dev->devnum;
- ulong n = 0;
- unsigned char c;
- unsigned char pwrsave = 0; /* power save */
-
-#ifdef CONFIG_LBA48
- unsigned char lba48 = 0;
-
- if (blknr & 0x0000fffff0000000ULL) {
- /* more than 28 bits used, use 48bit mode */
- lba48 = 1;
- }
-#endif
- debug("ide_read dev %d start " LBAF ", blocks " LBAF " buffer at %lX\n",
- device, blknr, blkcnt, (ulong) buffer);
-
- ide_led(DEVICE_LED(device), 1); /* LED on */
-
- /* Select device
- */
- ide_outb(device, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(device));
- c = ide_wait(device, IDE_TIME_OUT);
-
- if (c & ATA_STAT_BUSY) {
- printf("IDE read: device %d not ready\n", device);
- goto IDE_READ_E;
- }
-
- /* first check if the drive is in Powersaving mode, if yes,
- * increase the timeout value */
- ide_outb(device, ATA_COMMAND, ATA_CMD_CHK_PWR);
- udelay(50);
-
- c = ide_wait(device, IDE_TIME_OUT); /* can't take over 500 ms */
-
- if (c & ATA_STAT_BUSY) {
- printf("IDE read: device %d not ready\n", device);
- goto IDE_READ_E;
- }
- if ((c & ATA_STAT_ERR) == ATA_STAT_ERR) {
- printf("No Powersaving mode %X\n", c);
- } else {
- c = ide_inb(device, ATA_SECT_CNT);
- debug("Powersaving %02X\n", c);
- if (c == 0)
- pwrsave = 1;
- }
-
-
- while (blkcnt-- > 0) {
-
- c = ide_wait(device, IDE_TIME_OUT);
-
- if (c & ATA_STAT_BUSY) {
- printf("IDE read: device %d not ready\n", device);
- break;
- }
-#ifdef CONFIG_LBA48
- if (lba48) {
- /* write high bits */
- ide_outb(device, ATA_SECT_CNT, 0);
- ide_outb(device, ATA_LBA_LOW, (blknr >> 24) & 0xFF);
-#ifdef CONFIG_SYS_64BIT_LBA
- ide_outb(device, ATA_LBA_MID, (blknr >> 32) & 0xFF);
- ide_outb(device, ATA_LBA_HIGH, (blknr >> 40) & 0xFF);
-#else
- ide_outb(device, ATA_LBA_MID, 0);
- ide_outb(device, ATA_LBA_HIGH, 0);
-#endif
- }
-#endif
- ide_outb(device, ATA_SECT_CNT, 1);
- ide_outb(device, ATA_LBA_LOW, (blknr >> 0) & 0xFF);
- ide_outb(device, ATA_LBA_MID, (blknr >> 8) & 0xFF);
- ide_outb(device, ATA_LBA_HIGH, (blknr >> 16) & 0xFF);
-
-#ifdef CONFIG_LBA48
- if (lba48) {
- ide_outb(device, ATA_DEV_HD,
- ATA_LBA | ATA_DEVICE(device));
- ide_outb(device, ATA_COMMAND, ATA_CMD_READ_EXT);
-
- } else
-#endif
- {
- ide_outb(device, ATA_DEV_HD, ATA_LBA |
- ATA_DEVICE(device) | ((blknr >> 24) & 0xF));
- ide_outb(device, ATA_COMMAND, ATA_CMD_READ);
- }
-
- udelay(50);
-
- if (pwrsave) {
- /* may take up to 4 sec */
- c = ide_wait(device, IDE_SPIN_UP_TIME_OUT);
- pwrsave = 0;
- } else {
- /* can't take over 500 ms */
- c = ide_wait(device, IDE_TIME_OUT);
- }
-
- if ((c & (ATA_STAT_DRQ | ATA_STAT_BUSY | ATA_STAT_ERR)) !=
- ATA_STAT_DRQ) {
- printf("Error (no IRQ) dev %d blk " LBAF ": status "
- "%#02x\n", device, blknr, c);
- break;
- }
-
- ide_input_data(device, buffer, ATA_SECTORWORDS);
- (void) ide_inb(device, ATA_STATUS); /* clear IRQ */
-
- ++n;
- ++blknr;
- buffer += ATA_BLOCKSIZE;
- }
-IDE_READ_E:
- ide_led(DEVICE_LED(device), 0); /* LED off */
- return (n);
-}
-
-/* ------------------------------------------------------------------------- */
-
-
-ulong ide_write(struct blk_desc *block_dev, lbaint_t blknr, lbaint_t blkcnt,
- const void *buffer)
-{
- int device = block_dev->devnum;
- ulong n = 0;
- unsigned char c;
-
-#ifdef CONFIG_LBA48
- unsigned char lba48 = 0;
-
- if (blknr & 0x0000fffff0000000ULL) {
- /* more than 28 bits used, use 48bit mode */
- lba48 = 1;
- }
-#endif
-
- ide_led(DEVICE_LED(device), 1); /* LED on */
-
- /* Select device
- */
- ide_outb(device, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(device));
-
- while (blkcnt-- > 0) {
-
- c = ide_wait(device, IDE_TIME_OUT);
-
- if (c & ATA_STAT_BUSY) {
- printf("IDE read: device %d not ready\n", device);
- goto WR_OUT;
- }
-#ifdef CONFIG_LBA48
- if (lba48) {
- /* write high bits */
- ide_outb(device, ATA_SECT_CNT, 0);
- ide_outb(device, ATA_LBA_LOW, (blknr >> 24) & 0xFF);
-#ifdef CONFIG_SYS_64BIT_LBA
- ide_outb(device, ATA_LBA_MID, (blknr >> 32) & 0xFF);
- ide_outb(device, ATA_LBA_HIGH, (blknr >> 40) & 0xFF);
-#else
- ide_outb(device, ATA_LBA_MID, 0);
- ide_outb(device, ATA_LBA_HIGH, 0);
-#endif
- }
-#endif
- ide_outb(device, ATA_SECT_CNT, 1);
- ide_outb(device, ATA_LBA_LOW, (blknr >> 0) & 0xFF);
- ide_outb(device, ATA_LBA_MID, (blknr >> 8) & 0xFF);
- ide_outb(device, ATA_LBA_HIGH, (blknr >> 16) & 0xFF);
-
-#ifdef CONFIG_LBA48
- if (lba48) {
- ide_outb(device, ATA_DEV_HD,
- ATA_LBA | ATA_DEVICE(device));
- ide_outb(device, ATA_COMMAND, ATA_CMD_WRITE_EXT);
-
- } else
-#endif
- {
- ide_outb(device, ATA_DEV_HD, ATA_LBA |
- ATA_DEVICE(device) | ((blknr >> 24) & 0xF));
- ide_outb(device, ATA_COMMAND, ATA_CMD_WRITE);
- }
-
- udelay(50);
-
- /* can't take over 500 ms */
- c = ide_wait(device, IDE_TIME_OUT);
-
- if ((c & (ATA_STAT_DRQ | ATA_STAT_BUSY | ATA_STAT_ERR)) !=
- ATA_STAT_DRQ) {
- printf("Error (no IRQ) dev %d blk " LBAF ": status "
- "%#02x\n", device, blknr, c);
- goto WR_OUT;
- }
-
- ide_output_data(device, buffer, ATA_SECTORWORDS);
- c = ide_inb(device, ATA_STATUS); /* clear IRQ */
- ++n;
- ++blknr;
- buffer += ATA_BLOCKSIZE;
- }
-WR_OUT:
- ide_led(DEVICE_LED(device), 0); /* LED off */
- return (n);
-}
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * copy src to dest, skipping leading and trailing blanks and null
- * terminate the string
- * "len" is the size of available memory including the terminating '\0'
- */
-static void ident_cpy(unsigned char *dst, unsigned char *src,
- unsigned int len)
-{
- unsigned char *end, *last;
-
- last = dst;
- end = src + len - 1;
-
- /* reserve space for '\0' */
- if (len < 2)
- goto OUT;
-
- /* skip leading white space */
- while ((*src) && (src < end) && (*src == ' '))
- ++src;
-
- /* copy string, omitting trailing white space */
- while ((*src) && (src < end)) {
- *dst++ = *src;
- if (*src++ != ' ')
- last = dst;
- }
-OUT:
- *last = '\0';
-}
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * Wait until Busy bit is off, or timeout (in ms)
- * Return last status
- */
-static uchar ide_wait(int dev, ulong t)
-{
- ulong delay = 10 * t; /* poll every 100 us */
- uchar c;
-
- while ((c = ide_inb(dev, ATA_STATUS)) & ATA_STAT_BUSY) {
- udelay(100);
- if (delay-- == 0)
- break;
- }
- return (c);
-}
-
-/* ------------------------------------------------------------------------- */
-
-#ifdef CONFIG_IDE_RESET
-extern void ide_set_reset(int idereset);
-
-static void ide_reset(void)
-{
- int i;
-
- curr_device = -1;
- for (i = 0; i < CONFIG_SYS_IDE_MAXBUS; ++i)
- ide_bus_ok[i] = 0;
- for (i = 0; i < CONFIG_SYS_IDE_MAXDEVICE; ++i)
- ide_dev_desc[i].type = DEV_TYPE_UNKNOWN;
-
- ide_set_reset(1); /* assert reset */
-
- /* the reset signal shall be asserted for et least 25 us */
- udelay(25);
-
- WATCHDOG_RESET();
-
- /* de-assert RESET signal */
- ide_set_reset(0);
-
- /* wait 250 ms */
- for (i = 0; i < 250; ++i)
- udelay(1000);
-}
-
-#endif /* CONFIG_IDE_RESET */
-
-/* ------------------------------------------------------------------------- */
-
-#if defined(CONFIG_OF_IDE_FIXUP)
-int ide_device_present(int dev)
-{
- if (dev >= CONFIG_SYS_IDE_MAXBUS)
- return 0;
- return (ide_dev_desc[dev].type == DEV_TYPE_UNKNOWN ? 0 : 1);
-}
-#endif
-/* ------------------------------------------------------------------------- */
-
-#ifdef CONFIG_ATAPI
-/****************************************************************************
- * ATAPI Support
- */
-
-#if defined(CONFIG_IDE_SWAP_IO)
-/* since ATAPI may use commands with not 4 bytes alligned length
- * we have our own transfer functions, 2 bytes alligned */
-__weak void ide_output_data_shorts(int dev, ushort *sect_buf, int shorts)
-{
- ushort *dbuf;
- volatile ushort *pbuf;
-
- pbuf = (ushort *) (ATA_CURR_BASE(dev) + ATA_DATA_REG);
- dbuf = (ushort *) sect_buf;
-
- debug("in output data shorts base for read is %lx\n",
- (unsigned long) pbuf);
-
- while (shorts--) {
- EIEIO;
- *pbuf = *dbuf++;
- }
-}
-
-__weak void ide_input_data_shorts(int dev, ushort *sect_buf, int shorts)
-{
- ushort *dbuf;
- volatile ushort *pbuf;
-
- pbuf = (ushort *) (ATA_CURR_BASE(dev) + ATA_DATA_REG);
- dbuf = (ushort *) sect_buf;
-
- debug("in input data shorts base for read is %lx\n",
- (unsigned long) pbuf);
-
- while (shorts--) {
- EIEIO;
- *dbuf++ = *pbuf;
- }
-}
-
-#else /* ! CONFIG_IDE_SWAP_IO */
-__weak void ide_output_data_shorts(int dev, ushort *sect_buf, int shorts)
-{
- outsw(ATA_CURR_BASE(dev) + ATA_DATA_REG, sect_buf, shorts);
-}
-
-__weak void ide_input_data_shorts(int dev, ushort *sect_buf, int shorts)
-{
- insw(ATA_CURR_BASE(dev) + ATA_DATA_REG, sect_buf, shorts);
-}
-
-#endif /* CONFIG_IDE_SWAP_IO */
-
-/*
- * Wait until (Status & mask) == res, or timeout (in ms)
- * Return last status
- * This is used since some ATAPI CD ROMs clears their Busy Bit first
- * and then they set their DRQ Bit
- */
-static uchar atapi_wait_mask(int dev, ulong t, uchar mask, uchar res)
-{
- ulong delay = 10 * t; /* poll every 100 us */
- uchar c;
-
- /* prevents to read the status before valid */
- c = ide_inb(dev, ATA_DEV_CTL);
-
- while (((c = ide_inb(dev, ATA_STATUS)) & mask) != res) {
- /* break if error occurs (doesn't make sense to wait more) */
- if ((c & ATA_STAT_ERR) == ATA_STAT_ERR)
- break;
- udelay(100);
- if (delay-- == 0)
- break;
- }
- return (c);
-}
-
-/*
- * issue an atapi command
- */
-unsigned char atapi_issue(int device, unsigned char *ccb, int ccblen,
- unsigned char *buffer, int buflen)
-{
- unsigned char c, err, mask, res;
- int n;
-
- ide_led(DEVICE_LED(device), 1); /* LED on */
-
- /* Select device
- */
- mask = ATA_STAT_BUSY | ATA_STAT_DRQ;
- res = 0;
- ide_outb(device, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(device));
- c = atapi_wait_mask(device, ATAPI_TIME_OUT, mask, res);
- if ((c & mask) != res) {
- printf("ATAPI_ISSUE: device %d not ready status %X\n", device,
- c);
- err = 0xFF;
- goto AI_OUT;
- }
- /* write taskfile */
- ide_outb(device, ATA_ERROR_REG, 0); /* no DMA, no overlaped */
- ide_outb(device, ATA_SECT_CNT, 0);
- ide_outb(device, ATA_SECT_NUM, 0);
- ide_outb(device, ATA_CYL_LOW, (unsigned char) (buflen & 0xFF));
- ide_outb(device, ATA_CYL_HIGH,
- (unsigned char) ((buflen >> 8) & 0xFF));
- ide_outb(device, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(device));
-
- ide_outb(device, ATA_COMMAND, ATAPI_CMD_PACKET);
- udelay(50);
-
- mask = ATA_STAT_DRQ | ATA_STAT_BUSY | ATA_STAT_ERR;
- res = ATA_STAT_DRQ;
- c = atapi_wait_mask(device, ATAPI_TIME_OUT, mask, res);
-
- if ((c & mask) != res) { /* DRQ must be 1, BSY 0 */
- printf("ATAPI_ISSUE: Error (no IRQ) before sending ccb dev %d status 0x%02x\n",
- device, c);
- err = 0xFF;
- goto AI_OUT;
- }
-
- /* write command block */
- ide_output_data_shorts(device, (unsigned short *) ccb, ccblen / 2);
-
- /* ATAPI Command written wait for completition */
- udelay(5000); /* device must set bsy */
-
- mask = ATA_STAT_DRQ | ATA_STAT_BUSY | ATA_STAT_ERR;
- /*
- * if no data wait for DRQ = 0 BSY = 0
- * if data wait for DRQ = 1 BSY = 0
- */
- res = 0;
- if (buflen)
- res = ATA_STAT_DRQ;
- c = atapi_wait_mask(device, ATAPI_TIME_OUT, mask, res);
- if ((c & mask) != res) {
- if (c & ATA_STAT_ERR) {
- err = (ide_inb(device, ATA_ERROR_REG)) >> 4;
- debug("atapi_issue 1 returned sense key %X status %02X\n",
- err, c);
- } else {
- printf("ATAPI_ISSUE: (no DRQ) after sending ccb (%x) status 0x%02x\n",
- ccb[0], c);
- err = 0xFF;
- }
- goto AI_OUT;
- }
- n = ide_inb(device, ATA_CYL_HIGH);
- n <<= 8;
- n += ide_inb(device, ATA_CYL_LOW);
- if (n > buflen) {
- printf("ERROR, transfer bytes %d requested only %d\n", n,
- buflen);
- err = 0xff;
- goto AI_OUT;
- }
- if ((n == 0) && (buflen < 0)) {
- printf("ERROR, transfer bytes %d requested %d\n", n, buflen);
- err = 0xff;
- goto AI_OUT;
- }
- if (n != buflen) {
- debug("WARNING, transfer bytes %d not equal with requested %d\n",
- n, buflen);
- }
- if (n != 0) { /* data transfer */
- debug("ATAPI_ISSUE: %d Bytes to transfer\n", n);
- /* we transfer shorts */
- n >>= 1;
- /* ok now decide if it is an in or output */
- if ((ide_inb(device, ATA_SECT_CNT) & 0x02) == 0) {
- debug("Write to device\n");
- ide_output_data_shorts(device,
- (unsigned short *) buffer, n);
- } else {
- debug("Read from device @ %p shorts %d\n", buffer, n);
- ide_input_data_shorts(device,
- (unsigned short *) buffer, n);
- }
- }
- udelay(5000); /* seems that some CD ROMs need this... */
- mask = ATA_STAT_BUSY | ATA_STAT_ERR;
- res = 0;
- c = atapi_wait_mask(device, ATAPI_TIME_OUT, mask, res);
- if ((c & ATA_STAT_ERR) == ATA_STAT_ERR) {
- err = (ide_inb(device, ATA_ERROR_REG) >> 4);
- debug("atapi_issue 2 returned sense key %X status %X\n", err,
- c);
- } else {
- err = 0;
- }
-AI_OUT:
- ide_led(DEVICE_LED(device), 0); /* LED off */
- return (err);
-}
-
-/*
- * sending the command to atapi_issue. If an status other than good
- * returns, an request_sense will be issued
- */
-
-#define ATAPI_DRIVE_NOT_READY 100
-#define ATAPI_UNIT_ATTN 10
-
-unsigned char atapi_issue_autoreq(int device,
- unsigned char *ccb,
- int ccblen,
- unsigned char *buffer, int buflen)
-{
- unsigned char sense_data[18], sense_ccb[12];
- unsigned char res, key, asc, ascq;
- int notready, unitattn;
-
- unitattn = ATAPI_UNIT_ATTN;
- notready = ATAPI_DRIVE_NOT_READY;
-
-retry:
- res = atapi_issue(device, ccb, ccblen, buffer, buflen);
- if (res == 0)
- return 0; /* Ok */
-
- if (res == 0xFF)
- return 0xFF; /* error */
-
- debug("(auto_req)atapi_issue returned sense key %X\n", res);
-
- memset(sense_ccb, 0, sizeof(sense_ccb));
- memset(sense_data, 0, sizeof(sense_data));
- sense_ccb[0] = ATAPI_CMD_REQ_SENSE;
- sense_ccb[4] = 18; /* allocation Length */
-
- res = atapi_issue(device, sense_ccb, 12, sense_data, 18);
- key = (sense_data[2] & 0xF);
- asc = (sense_data[12]);
- ascq = (sense_data[13]);
-
- debug("ATAPI_CMD_REQ_SENSE returned %x\n", res);
- debug(" Sense page: %02X key %02X ASC %02X ASCQ %02X\n",
- sense_data[0], key, asc, ascq);
-
- if ((key == 0))
- return 0; /* ok device ready */
-
- if ((key == 6) || (asc == 0x29) || (asc == 0x28)) { /* Unit Attention */
- if (unitattn-- > 0) {
- udelay(200 * 1000);
- goto retry;
- }
- printf("Unit Attention, tried %d\n", ATAPI_UNIT_ATTN);
- goto error;
- }
- if ((asc == 0x4) && (ascq == 0x1)) {
- /* not ready, but will be ready soon */
- if (notready-- > 0) {
- udelay(200 * 1000);
- goto retry;
- }
- printf("Drive not ready, tried %d times\n",
- ATAPI_DRIVE_NOT_READY);
- goto error;
- }
- if (asc == 0x3a) {
- debug("Media not present\n");
- goto error;
- }
-
- printf("ERROR: Unknown Sense key %02X ASC %02X ASCQ %02X\n", key, asc,
- ascq);
-error:
- debug("ERROR Sense key %02X ASC %02X ASCQ %02X\n", key, asc, ascq);
- return (0xFF);
-}
-
-
-static void atapi_inquiry(struct blk_desc *dev_desc)
-{
- unsigned char ccb[12]; /* Command descriptor block */
- unsigned char iobuf[64]; /* temp buf */
- unsigned char c;
- int device;
-
- device = dev_desc->devnum;
- dev_desc->type = DEV_TYPE_UNKNOWN; /* not yet valid */
- dev_desc->block_read = atapi_read;
-
- memset(ccb, 0, sizeof(ccb));
- memset(iobuf, 0, sizeof(iobuf));
-
- ccb[0] = ATAPI_CMD_INQUIRY;
- ccb[4] = 40; /* allocation Legnth */
- c = atapi_issue_autoreq(device, ccb, 12, (unsigned char *) iobuf, 40);
-
- debug("ATAPI_CMD_INQUIRY returned %x\n", c);
- if (c != 0)
- return;
-
- /* copy device ident strings */
- ident_cpy((unsigned char *) dev_desc->vendor, &iobuf[8], 8);
- ident_cpy((unsigned char *) dev_desc->product, &iobuf[16], 16);
- ident_cpy((unsigned char *) dev_desc->revision, &iobuf[32], 5);
-
- dev_desc->lun = 0;
- dev_desc->lba = 0;
- dev_desc->blksz = 0;
- dev_desc->log2blksz = LOG2_INVALID(typeof(dev_desc->log2blksz));
- dev_desc->type = iobuf[0] & 0x1f;
-
- if ((iobuf[1] & 0x80) == 0x80)
- dev_desc->removable = 1;
- else
- dev_desc->removable = 0;
-
- memset(ccb, 0, sizeof(ccb));
- memset(iobuf, 0, sizeof(iobuf));
- ccb[0] = ATAPI_CMD_START_STOP;
- ccb[4] = 0x03; /* start */
-
- c = atapi_issue_autoreq(device, ccb, 12, (unsigned char *) iobuf, 0);
-
- debug("ATAPI_CMD_START_STOP returned %x\n", c);
- if (c != 0)
- return;
-
- memset(ccb, 0, sizeof(ccb));
- memset(iobuf, 0, sizeof(iobuf));
- c = atapi_issue_autoreq(device, ccb, 12, (unsigned char *) iobuf, 0);
-
- debug("ATAPI_CMD_UNIT_TEST_READY returned %x\n", c);
- if (c != 0)
- return;
-
- memset(ccb, 0, sizeof(ccb));
- memset(iobuf, 0, sizeof(iobuf));
- ccb[0] = ATAPI_CMD_READ_CAP;
- c = atapi_issue_autoreq(device, ccb, 12, (unsigned char *) iobuf, 8);
- debug("ATAPI_CMD_READ_CAP returned %x\n", c);
- if (c != 0)
- return;
-
- debug("Read Cap: LBA %02X%02X%02X%02X blksize %02X%02X%02X%02X\n",
- iobuf[0], iobuf[1], iobuf[2], iobuf[3],
- iobuf[4], iobuf[5], iobuf[6], iobuf[7]);
-
- dev_desc->lba = ((unsigned long) iobuf[0] << 24) +
- ((unsigned long) iobuf[1] << 16) +
- ((unsigned long) iobuf[2] << 8) + ((unsigned long) iobuf[3]);
- dev_desc->blksz = ((unsigned long) iobuf[4] << 24) +
- ((unsigned long) iobuf[5] << 16) +
- ((unsigned long) iobuf[6] << 8) + ((unsigned long) iobuf[7]);
- dev_desc->log2blksz = LOG2(dev_desc->blksz);
-#ifdef CONFIG_LBA48
- /* ATAPI devices cannot use 48bit addressing (ATA/ATAPI v7) */
- dev_desc->lba48 = 0;
-#endif
- return;
-}
-
-
-/*
- * atapi_read:
- * we transfer only one block per command, since the multiple DRQ per
- * command is not yet implemented
- */
-#define ATAPI_READ_MAX_BYTES 2048 /* we read max 2kbytes */
-#define ATAPI_READ_BLOCK_SIZE 2048 /* assuming CD part */
-#define ATAPI_READ_MAX_BLOCK (ATAPI_READ_MAX_BYTES/ATAPI_READ_BLOCK_SIZE)
-
-ulong atapi_read(struct blk_desc *block_dev, lbaint_t blknr, lbaint_t blkcnt,
- void *buffer)
-{
- int device = block_dev->devnum;
- ulong n = 0;
- unsigned char ccb[12]; /* Command descriptor block */
- ulong cnt;
-
- debug("atapi_read dev %d start " LBAF " blocks " LBAF " buffer at %lX\n",
- device, blknr, blkcnt, (ulong) buffer);
-
- do {
- if (blkcnt > ATAPI_READ_MAX_BLOCK)
- cnt = ATAPI_READ_MAX_BLOCK;
- else
- cnt = blkcnt;
-
- ccb[0] = ATAPI_CMD_READ_12;
- ccb[1] = 0; /* reserved */
- ccb[2] = (unsigned char) (blknr >> 24) & 0xFF; /* MSB Block */
- ccb[3] = (unsigned char) (blknr >> 16) & 0xFF; /* */
- ccb[4] = (unsigned char) (blknr >> 8) & 0xFF;
- ccb[5] = (unsigned char) blknr & 0xFF; /* LSB Block */
- ccb[6] = (unsigned char) (cnt >> 24) & 0xFF; /* MSB Block cnt */
- ccb[7] = (unsigned char) (cnt >> 16) & 0xFF;
- ccb[8] = (unsigned char) (cnt >> 8) & 0xFF;
- ccb[9] = (unsigned char) cnt & 0xFF; /* LSB Block */
- ccb[10] = 0; /* reserved */
- ccb[11] = 0; /* reserved */
-
- if (atapi_issue_autoreq(device, ccb, 12,
- (unsigned char *) buffer,
- cnt * ATAPI_READ_BLOCK_SIZE)
- == 0xFF) {
- return (n);
- }
- n += cnt;
- blkcnt -= cnt;
- blknr += cnt;
- buffer += (cnt * ATAPI_READ_BLOCK_SIZE);
- } while (blkcnt > 0);
- return (n);
-}
-
-/* ------------------------------------------------------------------------- */
-
-#endif /* CONFIG_ATAPI */
-
U_BOOT_CMD(ide, 5, 1, do_ide,
"IDE sub-system",
"reset - reset IDE controller\n"
}
/* Switch to the RPMB partition */
original_part = mmc->block_dev.hwpart;
- if (mmc_select_hwpart(curr_device, MMC_PART_RPMB) != 0)
+ if (blk_select_hwpart_devnum(IF_TYPE_MMC, curr_device, MMC_PART_RPMB) !=
+ 0)
return CMD_RET_FAILURE;
ret = cp->cmd(cmdtp, flag, argc, argv);
/* Return to original partition */
- if (mmc_select_hwpart(curr_device, original_part) != 0)
+ if (blk_select_hwpart_devnum(IF_TYPE_MMC, curr_device, original_part) !=
+ 0)
return CMD_RET_FAILURE;
return ret;
}
printf("\nMMC read: dev # %d, block # %d, count %d ... ",
curr_device, blk, cnt);
- n = blk_dread(&mmc->block_dev, blk, cnt, addr);
+ n = blk_dread(mmc_get_blk_desc(mmc), blk, cnt, addr);
/* flush cache after read */
flush_cache((ulong)addr, cnt * 512); /* FIXME */
printf("%d blocks read: %s\n", n, (n == cnt) ? "OK" : "ERROR");
printf("Error: card is write protected!\n");
return CMD_RET_FAILURE;
}
- n = blk_dwrite(&mmc->block_dev, blk, cnt, addr);
+ n = blk_dwrite(mmc_get_blk_desc(mmc), blk, cnt, addr);
printf("%d blocks written: %s\n", n, (n == cnt) ? "OK" : "ERROR");
return (n == cnt) ? CMD_RET_SUCCESS : CMD_RET_FAILURE;
printf("Error: card is write protected!\n");
return CMD_RET_FAILURE;
}
- n = blk_derase(&mmc->block_dev, blk, cnt);
+ n = blk_derase(mmc_get_blk_desc(mmc), blk, cnt);
printf("%d blocks erased: %s\n", n, (n == cnt) ? "OK" : "ERROR");
return (n == cnt) ? CMD_RET_SUCCESS : CMD_RET_FAILURE;
if (!mmc)
return CMD_RET_FAILURE;
- mmc_dev = mmc_get_dev(curr_device);
+ mmc_dev = blk_get_devnum_by_type(IF_TYPE_MMC, curr_device);
if (mmc_dev != NULL && mmc_dev->type != DEV_TYPE_UNKNOWN) {
part_print(mmc_dev);
return CMD_RET_SUCCESS;
if (!mmc)
return CMD_RET_FAILURE;
- ret = mmc_select_hwpart(dev, part);
+ ret = blk_select_hwpart_devnum(IF_TYPE_MMC, dev, part);
printf("switch to partitions #%d, %s\n",
part, (!ret) ? "OK" : "ERROR");
if (ret)
printf("mmc%d is current device\n", curr_device);
else
printf("mmc%d(part %d) is current device\n",
- curr_device, mmc->block_dev.hwpart);
+ curr_device, mmc_get_blk_desc(mmc)->hwpart);
return CMD_RET_SUCCESS;
}
--- /dev/null
+/*
+ * (C) Copyright 2015 Miao Yan <yanmiaobest@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <errno.h>
+#include <qfw.h>
+
+/*
+ * This function prepares kernel for zboot. It loads kernel data
+ * to 'load_addr', initrd to 'initrd_addr' and kernel command
+ * line using qemu fw_cfg interface.
+ */
+static int qemu_fwcfg_setup_kernel(void *load_addr, void *initrd_addr)
+{
+ char *data_addr;
+ uint32_t setup_size, kernel_size, cmdline_size, initrd_size;
+
+ qemu_fwcfg_read_entry(FW_CFG_SETUP_SIZE, 4, &setup_size);
+ qemu_fwcfg_read_entry(FW_CFG_KERNEL_SIZE, 4, &kernel_size);
+
+ if (setup_size == 0 || kernel_size == 0) {
+ printf("warning: no kernel available\n");
+ return -1;
+ }
+
+ data_addr = load_addr;
+ qemu_fwcfg_read_entry(FW_CFG_SETUP_DATA,
+ le32_to_cpu(setup_size), data_addr);
+ data_addr += le32_to_cpu(setup_size);
+
+ qemu_fwcfg_read_entry(FW_CFG_KERNEL_DATA,
+ le32_to_cpu(kernel_size), data_addr);
+ data_addr += le32_to_cpu(kernel_size);
+
+ data_addr = initrd_addr;
+ qemu_fwcfg_read_entry(FW_CFG_INITRD_SIZE, 4, &initrd_size);
+ if (initrd_size == 0) {
+ printf("warning: no initrd available\n");
+ } else {
+ qemu_fwcfg_read_entry(FW_CFG_INITRD_DATA,
+ le32_to_cpu(initrd_size), data_addr);
+ data_addr += le32_to_cpu(initrd_size);
+ }
+
+ qemu_fwcfg_read_entry(FW_CFG_CMDLINE_SIZE, 4, &cmdline_size);
+ if (cmdline_size) {
+ qemu_fwcfg_read_entry(FW_CFG_CMDLINE_DATA,
+ le32_to_cpu(cmdline_size), data_addr);
+ /*
+ * if kernel cmdline only contains '\0', (e.g. no -append
+ * when invoking qemu), do not update bootargs
+ */
+ if (*data_addr != '\0') {
+ if (setenv("bootargs", data_addr) < 0)
+ printf("warning: unable to change bootargs\n");
+ }
+ }
+
+ printf("loading kernel to address %p size %x", load_addr,
+ le32_to_cpu(kernel_size));
+ if (initrd_size)
+ printf(" initrd %p size %x\n",
+ initrd_addr,
+ le32_to_cpu(initrd_size));
+ else
+ printf("\n");
+
+ return 0;
+}
+
+static int qemu_fwcfg_list_firmware(void)
+{
+ int ret;
+ struct fw_cfg_file_iter iter;
+ struct fw_file *file;
+
+ /* make sure fw_list is loaded */
+ ret = qemu_fwcfg_read_firmware_list();
+ if (ret)
+ return ret;
+
+
+ for (file = qemu_fwcfg_file_iter_init(&iter);
+ !qemu_fwcfg_file_iter_end(&iter);
+ file = qemu_fwcfg_file_iter_next(&iter)) {
+ printf("%-56s\n", file->cfg.name);
+ }
+
+ return 0;
+}
+
+static int qemu_fwcfg_do_list(cmd_tbl_t *cmdtp, int flag,
+ int argc, char * const argv[])
+{
+ if (qemu_fwcfg_list_firmware() < 0)
+ return CMD_RET_FAILURE;
+
+ return 0;
+}
+
+static int qemu_fwcfg_do_cpus(cmd_tbl_t *cmdtp, int flag,
+ int argc, char * const argv[])
+{
+ int ret = qemu_fwcfg_online_cpus();
+ if (ret < 0) {
+ printf("QEMU fw_cfg interface not found\n");
+ return CMD_RET_FAILURE;
+ }
+
+ printf("%d cpu(s) online\n", qemu_fwcfg_online_cpus());
+
+ return 0;
+}
+
+static int qemu_fwcfg_do_load(cmd_tbl_t *cmdtp, int flag,
+ int argc, char * const argv[])
+{
+ char *env;
+ void *load_addr;
+ void *initrd_addr;
+
+ env = getenv("loadaddr");
+ load_addr = env ?
+ (void *)simple_strtoul(env, NULL, 16) :
+#ifdef CONFIG_LOADADDR
+ (void *)CONFIG_LOADADDR;
+#else
+ NULL;
+#endif
+
+ env = getenv("ramdiskaddr");
+ initrd_addr = env ?
+ (void *)simple_strtoul(env, NULL, 16) :
+#ifdef CONFIG_RAMDISK_ADDR
+ (void *)CONFIG_RAMDISK_ADDR;
+#else
+ NULL;
+#endif
+
+ if (argc == 2) {
+ load_addr = (void *)simple_strtoul(argv[0], NULL, 16);
+ initrd_addr = (void *)simple_strtoul(argv[1], NULL, 16);
+ } else if (argc == 1) {
+ load_addr = (void *)simple_strtoul(argv[0], NULL, 16);
+ }
+
+ if (!load_addr || !initrd_addr) {
+ printf("missing load or initrd address\n");
+ return CMD_RET_FAILURE;
+ }
+
+ return qemu_fwcfg_setup_kernel(load_addr, initrd_addr);
+}
+
+static cmd_tbl_t fwcfg_commands[] = {
+ U_BOOT_CMD_MKENT(list, 0, 1, qemu_fwcfg_do_list, "", ""),
+ U_BOOT_CMD_MKENT(cpus, 0, 1, qemu_fwcfg_do_cpus, "", ""),
+ U_BOOT_CMD_MKENT(load, 2, 1, qemu_fwcfg_do_load, "", ""),
+};
+
+static int do_qemu_fw(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ int ret;
+ cmd_tbl_t *fwcfg_cmd;
+
+ if (!qemu_fwcfg_present()) {
+ printf("QEMU fw_cfg interface not found\n");
+ return CMD_RET_USAGE;
+ }
+
+ fwcfg_cmd = find_cmd_tbl(argv[1], fwcfg_commands,
+ ARRAY_SIZE(fwcfg_commands));
+ argc -= 2;
+ argv += 2;
+ if (!fwcfg_cmd || argc > fwcfg_cmd->maxargs)
+ return CMD_RET_USAGE;
+
+ ret = fwcfg_cmd->cmd(fwcfg_cmd, flag, argc, argv);
+
+ return cmd_process_error(fwcfg_cmd, ret);
+}
+
+U_BOOT_CMD(
+ qfw, 4, 1, do_qemu_fw,
+ "QEMU firmware interface",
+ "<command>\n"
+ " - list : print firmware(s) currently loaded\n"
+ " - cpus : print online cpu number\n"
+ " - load <kernel addr> <initrd addr> : load kernel and initrd (if any), and setup for zboot\n"
+)
#include <sata.h>
static int sata_curr_device = -1;
-struct blk_desc sata_dev_desc[CONFIG_SYS_SATA_MAX_DEVICE];
-
-static unsigned long sata_bread(struct blk_desc *block_dev, lbaint_t start,
- lbaint_t blkcnt, void *dst)
-{
- return sata_read(block_dev->devnum, start, blkcnt, dst);
-}
-
-static unsigned long sata_bwrite(struct blk_desc *block_dev, lbaint_t start,
- lbaint_t blkcnt, const void *buffer)
-{
- return sata_write(block_dev->devnum, start, blkcnt, buffer);
-}
-
-int __sata_initialize(void)
-{
- int rc;
- int i;
-
- for (i = 0; i < CONFIG_SYS_SATA_MAX_DEVICE; i++) {
- memset(&sata_dev_desc[i], 0, sizeof(struct blk_desc));
- sata_dev_desc[i].if_type = IF_TYPE_SATA;
- sata_dev_desc[i].devnum = i;
- sata_dev_desc[i].part_type = PART_TYPE_UNKNOWN;
- sata_dev_desc[i].type = DEV_TYPE_HARDDISK;
- sata_dev_desc[i].lba = 0;
- sata_dev_desc[i].blksz = 512;
- sata_dev_desc[i].log2blksz = LOG2(sata_dev_desc[i].blksz);
- sata_dev_desc[i].block_read = sata_bread;
- sata_dev_desc[i].block_write = sata_bwrite;
-
- rc = init_sata(i);
- if (!rc) {
- rc = scan_sata(i);
- if (!rc && (sata_dev_desc[i].lba > 0) &&
- (sata_dev_desc[i].blksz > 0))
- part_init(&sata_dev_desc[i]);
- }
- }
- sata_curr_device = 0;
- return rc;
-}
-int sata_initialize(void) __attribute__((weak,alias("__sata_initialize")));
-
-__weak int __sata_stop(void)
-{
- int i, err = 0;
-
- for (i = 0; i < CONFIG_SYS_SATA_MAX_DEVICE; i++)
- err |= reset_sata(i);
-
- if (err)
- printf("Could not reset some SATA devices\n");
-
- return err;
-}
-int sata_stop(void) __attribute__((weak, alias("__sata_stop")));
-
-#ifdef CONFIG_PARTITIONS
-struct blk_desc *sata_get_dev(int dev)
-{
- return (dev < CONFIG_SYS_SATA_MAX_DEVICE) ? &sata_dev_desc[dev] : NULL;
-}
-#endif
static int do_sata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
case 1:
return CMD_RET_USAGE;
case 2:
- if (strncmp(argv[1],"inf", 3) == 0) {
- int i;
- putc('\n');
- for (i = 0; i < CONFIG_SYS_SATA_MAX_DEVICE; ++i) {
- if (sata_dev_desc[i].type == DEV_TYPE_UNKNOWN)
- continue;
- printf ("SATA device %d: ", i);
- dev_print(&sata_dev_desc[i]);
- }
+ if (strncmp(argv[1], "inf", 3) == 0) {
+ blk_list_devices(IF_TYPE_SATA);
return 0;
- } else if (strncmp(argv[1],"dev", 3) == 0) {
- if ((sata_curr_device < 0) || (sata_curr_device >= CONFIG_SYS_SATA_MAX_DEVICE)) {
- puts("\nno SATA devices available\n");
- return 1;
+ } else if (strncmp(argv[1], "dev", 3) == 0) {
+ if (blk_print_device_num(IF_TYPE_SATA,
+ sata_curr_device)) {
+ printf("\nno SATA devices available\n");
+ return CMD_RET_FAILURE;
}
- printf("\nSATA device %d: ", sata_curr_device);
- dev_print(&sata_dev_desc[sata_curr_device]);
return 0;
- } else if (strncmp(argv[1],"part",4) == 0) {
- int dev, ok;
-
- for (ok = 0, dev = 0; dev < CONFIG_SYS_SATA_MAX_DEVICE; ++dev) {
- if (sata_dev_desc[dev].part_type != PART_TYPE_UNKNOWN) {
- ++ok;
- if (dev)
- putc ('\n');
- part_print(&sata_dev_desc[dev]);
- }
- }
- if (!ok) {
+ } else if (strncmp(argv[1], "part", 4) == 0) {
+ if (blk_list_part(IF_TYPE_SATA))
puts("\nno SATA devices available\n");
- rc ++;
- }
- return rc;
+ return 0;
}
return CMD_RET_USAGE;
case 3:
if (strncmp(argv[1], "dev", 3) == 0) {
int dev = (int)simple_strtoul(argv[2], NULL, 10);
- printf("\nSATA device %d: ", dev);
- if (dev >= CONFIG_SYS_SATA_MAX_DEVICE) {
- puts ("unknown device\n");
- return 1;
+ if (!blk_show_device(IF_TYPE_SATA, dev)) {
+ sata_curr_device = dev;
+ printf("... is now current device\n");
+ } else {
+ return CMD_RET_FAILURE;
}
- dev_print(&sata_dev_desc[dev]);
-
- if (sata_dev_desc[dev].type == DEV_TYPE_UNKNOWN)
- return 1;
-
- sata_curr_device = dev;
-
- puts("... is now current device\n");
-
return 0;
} else if (strncmp(argv[1], "part", 4) == 0) {
int dev = (int)simple_strtoul(argv[2], NULL, 10);
- if (sata_dev_desc[dev].part_type != PART_TYPE_UNKNOWN) {
- part_print(&sata_dev_desc[dev]);
- } else {
- printf("\nSATA device %d not available\n", dev);
- rc = 1;
+ if (blk_print_part_devnum(IF_TYPE_SATA, dev)) {
+ printf("\nSATA device %d not available\n",
+ dev);
+ return CMD_RET_FAILURE;
}
return rc;
}
printf("\nSATA read: device %d block # %ld, count %ld ... ",
sata_curr_device, blk, cnt);
- n = blk_dread(&sata_dev_desc[sata_curr_device],
- blk, cnt, (u32 *)addr);
-
- /* flush cache after read */
- flush_cache(addr, cnt * sata_dev_desc[sata_curr_device].blksz);
+ n = blk_read_devnum(IF_TYPE_SATA, sata_curr_device, blk,
+ cnt, (ulong *)addr);
printf("%ld blocks read: %s\n",
n, (n==cnt) ? "OK" : "ERROR");
printf("\nSATA write: device %d block # %ld, count %ld ... ",
sata_curr_device, blk, cnt);
- n = blk_dwrite(&sata_dev_desc[sata_curr_device],
- blk, cnt, (u32 *)addr);
+ n = blk_write_devnum(IF_TYPE_SATA, sata_curr_device,
+ blk, cnt, (ulong *)addr);
printf("%ld blocks written: %s\n",
n, (n == cnt) ? "OK" : "ERROR");
*/
#include <common.h>
#include <command.h>
-#include <inttypes.h>
-#include <asm/processor.h>
#include <scsi.h>
-#include <image.h>
-#include <pci.h>
-
-#ifdef CONFIG_SCSI_DEV_LIST
-#define SCSI_DEV_LIST CONFIG_SCSI_DEV_LIST
-#else
-#ifdef CONFIG_SCSI_SYM53C8XX
-#define SCSI_VEND_ID 0x1000
-#ifndef CONFIG_SCSI_DEV_ID
-#define SCSI_DEV_ID 0x0001
-#else
-#define SCSI_DEV_ID CONFIG_SCSI_DEV_ID
-#endif
-#elif defined CONFIG_SATA_ULI5288
-
-#define SCSI_VEND_ID 0x10b9
-#define SCSI_DEV_ID 0x5288
-
-#elif !defined(CONFIG_SCSI_AHCI_PLAT)
-#error no scsi device defined
-#endif
-#define SCSI_DEV_LIST {SCSI_VEND_ID, SCSI_DEV_ID}
-#endif
-
-#if defined(CONFIG_PCI) && !defined(CONFIG_SCSI_AHCI_PLAT)
-const struct pci_device_id scsi_device_list[] = { SCSI_DEV_LIST };
-#endif
-static ccb tempccb; /* temporary scsi command buffer */
-
-static unsigned char tempbuff[512]; /* temporary data buffer */
-
-static int scsi_max_devs; /* number of highest available scsi device */
static int scsi_curr_dev; /* current device */
-static struct blk_desc scsi_dev_desc[CONFIG_SYS_SCSI_MAX_DEVICE];
-
-/********************************************************************************
- * forward declerations of some Setup Routines
- */
-void scsi_setup_test_unit_ready(ccb * pccb);
-void scsi_setup_read6(ccb * pccb, lbaint_t start, unsigned short blocks);
-void scsi_setup_read_ext(ccb * pccb, lbaint_t start, unsigned short blocks);
-void scsi_setup_read16(ccb * pccb, lbaint_t start, unsigned long blocks);
-
-static void scsi_setup_write_ext(ccb *pccb, lbaint_t start,
- unsigned short blocks);
-void scsi_setup_inquiry(ccb * pccb);
-void scsi_ident_cpy (unsigned char *dest, unsigned char *src, unsigned int len);
-
-
-static int scsi_read_capacity(ccb *pccb, lbaint_t *capacity,
- unsigned long *blksz);
-static ulong scsi_read(struct blk_desc *block_dev, lbaint_t blknr,
- lbaint_t blkcnt, void *buffer);
-static ulong scsi_write(struct blk_desc *block_dev, lbaint_t blknr,
- lbaint_t blkcnt, const void *buffer);
-
-
-/*********************************************************************************
- * (re)-scan the scsi bus and reports scsi device info
- * to the user if mode = 1
- */
-void scsi_scan(int mode)
-{
- unsigned char i,perq,modi,lun;
- lbaint_t capacity;
- unsigned long blksz;
- ccb* pccb=(ccb *)&tempccb;
-
- if(mode==1) {
- printf("scanning bus for devices...\n");
- }
- for(i=0;i<CONFIG_SYS_SCSI_MAX_DEVICE;i++) {
- scsi_dev_desc[i].target=0xff;
- scsi_dev_desc[i].lun=0xff;
- scsi_dev_desc[i].lba=0;
- scsi_dev_desc[i].blksz=0;
- scsi_dev_desc[i].log2blksz =
- LOG2_INVALID(typeof(scsi_dev_desc[i].log2blksz));
- scsi_dev_desc[i].type=DEV_TYPE_UNKNOWN;
- scsi_dev_desc[i].vendor[0]=0;
- scsi_dev_desc[i].product[0]=0;
- scsi_dev_desc[i].revision[0]=0;
- scsi_dev_desc[i].removable = false;
- scsi_dev_desc[i].if_type=IF_TYPE_SCSI;
- scsi_dev_desc[i].devnum = i;
- scsi_dev_desc[i].part_type=PART_TYPE_UNKNOWN;
- scsi_dev_desc[i].block_read=scsi_read;
- scsi_dev_desc[i].block_write = scsi_write;
- }
- scsi_max_devs=0;
- for(i=0;i<CONFIG_SYS_SCSI_MAX_SCSI_ID;i++) {
- pccb->target=i;
- for(lun=0;lun<CONFIG_SYS_SCSI_MAX_LUN;lun++) {
- pccb->lun=lun;
- pccb->pdata=(unsigned char *)&tempbuff;
- pccb->datalen=512;
- scsi_setup_inquiry(pccb);
- if (scsi_exec(pccb) != true) {
- if(pccb->contr_stat==SCSI_SEL_TIME_OUT) {
- debug ("Selection timeout ID %d\n",pccb->target);
- continue; /* selection timeout => assuming no device present */
- }
- scsi_print_error(pccb);
- continue;
- }
- perq=tempbuff[0];
- modi=tempbuff[1];
- if((perq & 0x1f)==0x1f) {
- continue; /* skip unknown devices */
- }
- if((modi&0x80)==0x80) /* drive is removable */
- scsi_dev_desc[scsi_max_devs].removable=true;
- /* get info for this device */
- scsi_ident_cpy((unsigned char *)&scsi_dev_desc[scsi_max_devs].vendor[0],
- &tempbuff[8], 8);
- scsi_ident_cpy((unsigned char *)&scsi_dev_desc[scsi_max_devs].product[0],
- &tempbuff[16], 16);
- scsi_ident_cpy((unsigned char *)&scsi_dev_desc[scsi_max_devs].revision[0],
- &tempbuff[32], 4);
- scsi_dev_desc[scsi_max_devs].target=pccb->target;
- scsi_dev_desc[scsi_max_devs].lun=pccb->lun;
-
- pccb->datalen=0;
- scsi_setup_test_unit_ready(pccb);
- if (scsi_exec(pccb) != true) {
- if (scsi_dev_desc[scsi_max_devs].removable == true) {
- scsi_dev_desc[scsi_max_devs].type=perq;
- goto removable;
- }
- scsi_print_error(pccb);
- continue;
- }
- if (scsi_read_capacity(pccb, &capacity, &blksz)) {
- scsi_print_error(pccb);
- continue;
- }
- scsi_dev_desc[scsi_max_devs].lba=capacity;
- scsi_dev_desc[scsi_max_devs].blksz=blksz;
- scsi_dev_desc[scsi_max_devs].log2blksz =
- LOG2(scsi_dev_desc[scsi_max_devs].blksz);
- scsi_dev_desc[scsi_max_devs].type=perq;
- part_init(&scsi_dev_desc[scsi_max_devs]);
-removable:
- if(mode==1) {
- printf (" Device %d: ", scsi_max_devs);
- dev_print(&scsi_dev_desc[scsi_max_devs]);
- } /* if mode */
- scsi_max_devs++;
- } /* next LUN */
- }
- if(scsi_max_devs>0)
- scsi_curr_dev=0;
- else
- scsi_curr_dev = -1;
-
- printf("Found %d device(s).\n", scsi_max_devs);
-#ifndef CONFIG_SPL_BUILD
- setenv_ulong("scsidevs", scsi_max_devs);
-#endif
-}
-
-int scsi_get_disk_count(void)
-{
- return scsi_max_devs;
-}
-
-#if defined(CONFIG_PCI) && !defined(CONFIG_SCSI_AHCI_PLAT)
-void scsi_init(void)
-{
- int busdevfunc = -1;
- int i;
- /*
- * Find a device from the list, this driver will support a single
- * controller.
- */
- for (i = 0; i < ARRAY_SIZE(scsi_device_list); i++) {
- /* get PCI Device ID */
-#ifdef CONFIG_DM_PCI
- struct udevice *dev;
- int ret;
-
- ret = dm_pci_find_device(scsi_device_list[i].vendor,
- scsi_device_list[i].device, 0, &dev);
- if (!ret) {
- busdevfunc = dm_pci_get_bdf(dev);
- break;
- }
-#else
- busdevfunc = pci_find_device(scsi_device_list[i].vendor,
- scsi_device_list[i].device,
- 0);
-#endif
- if (busdevfunc != -1)
- break;
- }
-
- if (busdevfunc == -1) {
- printf("Error: SCSI Controller(s) ");
- for (i = 0; i < ARRAY_SIZE(scsi_device_list); i++) {
- printf("%04X:%04X ",
- scsi_device_list[i].vendor,
- scsi_device_list[i].device);
- }
- printf("not found\n");
- return;
- }
-#ifdef DEBUG
- else {
- printf("SCSI Controller (%04X,%04X) found (%d:%d:%d)\n",
- scsi_device_list[i].vendor,
- scsi_device_list[i].device,
- (busdevfunc >> 16) & 0xFF,
- (busdevfunc >> 11) & 0x1F,
- (busdevfunc >> 8) & 0x7);
- }
-#endif
- bootstage_start(BOOTSTAGE_ID_ACCUM_SCSI, "ahci");
- scsi_low_level_init(busdevfunc);
- scsi_scan(1);
- bootstage_accum(BOOTSTAGE_ID_ACCUM_SCSI);
-}
-#endif
-
-#ifdef CONFIG_PARTITIONS
-struct blk_desc *scsi_get_dev(int dev)
-{
- return (dev < CONFIG_SYS_SCSI_MAX_DEVICE) ? &scsi_dev_desc[dev] : NULL;
-}
-#endif
-
-#ifndef CONFIG_SPL_BUILD
-/******************************************************************************
+/*
* scsi boot command intepreter. Derived from diskboot
*/
-int do_scsiboot (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+int do_scsiboot(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
{
return common_diskboot(cmdtp, "scsi", argc, argv);
}
-/*********************************************************************************
+/*
* scsi command intepreter
*/
-int do_scsi (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+int do_scsi(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
{
switch (argc) {
case 0:
case 1:
return CMD_RET_USAGE;
-
case 2:
- if (strncmp(argv[1],"res",3) == 0) {
- printf("\nReset SCSI\n");
- scsi_bus_reset();
- scsi_scan(1);
- return 0;
- }
- if (strncmp(argv[1],"inf",3) == 0) {
- int i;
- for (i=0; i<CONFIG_SYS_SCSI_MAX_DEVICE; ++i) {
- if(scsi_dev_desc[i].type==DEV_TYPE_UNKNOWN)
- continue; /* list only known devices */
- printf ("SCSI dev. %d: ", i);
- dev_print(&scsi_dev_desc[i]);
- }
- return 0;
- }
- if (strncmp(argv[1],"dev",3) == 0) {
- if ((scsi_curr_dev < 0) || (scsi_curr_dev >= CONFIG_SYS_SCSI_MAX_DEVICE)) {
- printf("\nno SCSI devices available\n");
- return 1;
- }
- printf ("\n Device %d: ", scsi_curr_dev);
- dev_print(&scsi_dev_desc[scsi_curr_dev]);
- return 0;
- }
- if (strncmp(argv[1],"scan",4) == 0) {
- scsi_scan(1);
- return 0;
- }
- if (strncmp(argv[1],"part",4) == 0) {
- int dev, ok;
- for (ok=0, dev=0; dev<CONFIG_SYS_SCSI_MAX_DEVICE; ++dev) {
- if (scsi_dev_desc[dev].type!=DEV_TYPE_UNKNOWN) {
- ok++;
- if (dev)
- printf("\n");
- debug ("print_part of %x\n",dev);
- part_print(&scsi_dev_desc[dev]);
- }
- }
- if (!ok)
- printf("\nno SCSI devices available\n");
- return 1;
+ if (strncmp(argv[1], "res", 3) == 0) {
+ printf("\nReset SCSI\n");
+ scsi_bus_reset();
+ scsi_scan(1);
+ return 0;
+ }
+ if (strncmp(argv[1], "inf", 3) == 0) {
+ blk_list_devices(IF_TYPE_SCSI);
+ return 0;
+ }
+ if (strncmp(argv[1], "dev", 3) == 0) {
+ if (blk_print_device_num(IF_TYPE_SCSI, scsi_curr_dev)) {
+ printf("\nno SCSI devices available\n");
+ return CMD_RET_FAILURE;
}
- return CMD_RET_USAGE;
+
+ return 0;
+ }
+ if (strncmp(argv[1], "scan", 4) == 0) {
+ scsi_scan(1);
+ return 0;
+ }
+ if (strncmp(argv[1], "part", 4) == 0) {
+ if (blk_list_part(IF_TYPE_SCSI))
+ printf("\nno SCSI devices available\n");
+ return 0;
+ }
+ return CMD_RET_USAGE;
case 3:
- if (strncmp(argv[1],"dev",3) == 0) {
- int dev = (int)simple_strtoul(argv[2], NULL, 10);
- printf ("\nSCSI device %d: ", dev);
- if (dev >= CONFIG_SYS_SCSI_MAX_DEVICE) {
- printf("unknown device\n");
- return 1;
- }
- printf ("\n Device %d: ", dev);
- dev_print(&scsi_dev_desc[dev]);
- if(scsi_dev_desc[dev].type == DEV_TYPE_UNKNOWN) {
- return 1;
- }
+ if (strncmp(argv[1], "dev", 3) == 0) {
+ int dev = (int)simple_strtoul(argv[2], NULL, 10);
+
+ if (!blk_show_device(IF_TYPE_SCSI, dev)) {
scsi_curr_dev = dev;
printf("... is now current device\n");
- return 0;
+ } else {
+ return CMD_RET_FAILURE;
}
- if (strncmp(argv[1],"part",4) == 0) {
- int dev = (int)simple_strtoul(argv[2], NULL, 10);
- if(scsi_dev_desc[dev].type != DEV_TYPE_UNKNOWN) {
- part_print(&scsi_dev_desc[dev]);
- }
- else {
- printf ("\nSCSI device %d not available\n", dev);
- }
- return 1;
- }
- return CMD_RET_USAGE;
- default:
- /* at least 4 args */
- if (strcmp(argv[1],"read") == 0) {
- ulong addr = simple_strtoul(argv[2], NULL, 16);
- ulong blk = simple_strtoul(argv[3], NULL, 16);
- ulong cnt = simple_strtoul(argv[4], NULL, 16);
- ulong n;
- printf ("\nSCSI read: device %d block # %ld, count %ld ... ",
- scsi_curr_dev, blk, cnt);
- n = scsi_read(&scsi_dev_desc[scsi_curr_dev],
- blk, cnt, (ulong *)addr);
- printf ("%ld blocks read: %s\n",n,(n==cnt) ? "OK" : "ERROR");
- return 0;
- } else if (strcmp(argv[1], "write") == 0) {
- ulong addr = simple_strtoul(argv[2], NULL, 16);
- ulong blk = simple_strtoul(argv[3], NULL, 16);
- ulong cnt = simple_strtoul(argv[4], NULL, 16);
- ulong n;
- printf("\nSCSI write: device %d block # %ld, "
- "count %ld ... ",
- scsi_curr_dev, blk, cnt);
- n = scsi_write(&scsi_dev_desc[scsi_curr_dev],
- blk, cnt, (ulong *)addr);
- printf("%ld blocks written: %s\n", n,
- (n == cnt) ? "OK" : "ERROR");
- return 0;
+ return 0;
+ }
+ if (strncmp(argv[1], "part", 4) == 0) {
+ int dev = (int)simple_strtoul(argv[2], NULL, 10);
+
+ if (blk_print_part_devnum(IF_TYPE_SCSI, dev)) {
+ printf("\nSCSI device %d not available\n",
+ dev);
+ return CMD_RET_FAILURE;
}
+ return 0;
+ }
+ return CMD_RET_USAGE;
+ default:
+ /* at least 4 args */
+ if (strcmp(argv[1], "read") == 0) {
+ ulong addr = simple_strtoul(argv[2], NULL, 16);
+ ulong blk = simple_strtoul(argv[3], NULL, 16);
+ ulong cnt = simple_strtoul(argv[4], NULL, 16);
+ ulong n;
+
+ printf("\nSCSI read: device %d block # %ld, count %ld ... ",
+ scsi_curr_dev, blk, cnt);
+ n = blk_read_devnum(IF_TYPE_SCSI, scsi_curr_dev, blk,
+ cnt, (ulong *)addr);
+ printf("%ld blocks read: %s\n", n,
+ n == cnt ? "OK" : "ERROR");
+ return 0;
+ } else if (strcmp(argv[1], "write") == 0) {
+ ulong addr = simple_strtoul(argv[2], NULL, 16);
+ ulong blk = simple_strtoul(argv[3], NULL, 16);
+ ulong cnt = simple_strtoul(argv[4], NULL, 16);
+ ulong n;
+
+ printf("\nSCSI write: device %d block # %ld, count %ld ... ",
+ scsi_curr_dev, blk, cnt);
+ n = blk_write_devnum(IF_TYPE_SCSI, scsi_curr_dev, blk,
+ cnt, (ulong *)addr);
+ printf("%ld blocks written: %s\n", n,
+ n == cnt ? "OK" : "ERROR");
+ return 0;
+ }
} /* switch */
return CMD_RET_USAGE;
}
"boot from SCSI device",
"loadAddr dev:part"
);
-#endif
-
-/****************************************************************************************
- * scsi_read
- */
-
-/* almost the maximum amount of the scsi_ext command.. */
-#define SCSI_MAX_READ_BLK 0xFFFF
-#define SCSI_LBA48_READ 0xFFFFFFF
-
-static ulong scsi_read(struct blk_desc *block_dev, lbaint_t blknr,
- lbaint_t blkcnt, void *buffer)
-{
- int device = block_dev->devnum;
- lbaint_t start, blks;
- uintptr_t buf_addr;
- unsigned short smallblks = 0;
- ccb* pccb=(ccb *)&tempccb;
- device&=0xff;
- /* Setup device
- */
- pccb->target=scsi_dev_desc[device].target;
- pccb->lun=scsi_dev_desc[device].lun;
- buf_addr=(unsigned long)buffer;
- start=blknr;
- blks=blkcnt;
- debug("\nscsi_read: dev %d startblk " LBAF
- ", blccnt " LBAF " buffer %lx\n",
- device, start, blks, (unsigned long)buffer);
- do {
- pccb->pdata=(unsigned char *)buf_addr;
-#ifdef CONFIG_SYS_64BIT_LBA
- if (start > SCSI_LBA48_READ) {
- unsigned long blocks;
- blocks = min_t(lbaint_t, blks, SCSI_MAX_READ_BLK);
- pccb->datalen = scsi_dev_desc[device].blksz * blocks;
- scsi_setup_read16(pccb, start, blocks);
- start += blocks;
- blks -= blocks;
- } else
-#endif
- if (blks > SCSI_MAX_READ_BLK) {
- pccb->datalen=scsi_dev_desc[device].blksz * SCSI_MAX_READ_BLK;
- smallblks=SCSI_MAX_READ_BLK;
- scsi_setup_read_ext(pccb,start,smallblks);
- start+=SCSI_MAX_READ_BLK;
- blks-=SCSI_MAX_READ_BLK;
- }
- else {
- pccb->datalen=scsi_dev_desc[device].blksz * blks;
- smallblks=(unsigned short) blks;
- scsi_setup_read_ext(pccb,start,smallblks);
- start+=blks;
- blks=0;
- }
- debug("scsi_read_ext: startblk " LBAF
- ", blccnt %x buffer %" PRIXPTR "\n",
- start, smallblks, buf_addr);
- if (scsi_exec(pccb) != true) {
- scsi_print_error(pccb);
- blkcnt-=blks;
- break;
- }
- buf_addr+=pccb->datalen;
- } while(blks!=0);
- debug("scsi_read_ext: end startblk " LBAF
- ", blccnt %x buffer %" PRIXPTR "\n", start, smallblks, buf_addr);
- return(blkcnt);
-}
-
-/*******************************************************************************
- * scsi_write
- */
-
-/* Almost the maximum amount of the scsi_ext command.. */
-#define SCSI_MAX_WRITE_BLK 0xFFFF
-
-static ulong scsi_write(struct blk_desc *block_dev, lbaint_t blknr,
- lbaint_t blkcnt, const void *buffer)
-{
- int device = block_dev->devnum;
- lbaint_t start, blks;
- uintptr_t buf_addr;
- unsigned short smallblks;
- ccb* pccb = (ccb *)&tempccb;
- device &= 0xff;
- /* Setup device
- */
- pccb->target = scsi_dev_desc[device].target;
- pccb->lun = scsi_dev_desc[device].lun;
- buf_addr = (unsigned long)buffer;
- start = blknr;
- blks = blkcnt;
- debug("\n%s: dev %d startblk " LBAF ", blccnt " LBAF " buffer %lx\n",
- __func__, device, start, blks, (unsigned long)buffer);
- do {
- pccb->pdata = (unsigned char *)buf_addr;
- if (blks > SCSI_MAX_WRITE_BLK) {
- pccb->datalen = (scsi_dev_desc[device].blksz *
- SCSI_MAX_WRITE_BLK);
- smallblks = SCSI_MAX_WRITE_BLK;
- scsi_setup_write_ext(pccb, start, smallblks);
- start += SCSI_MAX_WRITE_BLK;
- blks -= SCSI_MAX_WRITE_BLK;
- } else {
- pccb->datalen = scsi_dev_desc[device].blksz * blks;
- smallblks = (unsigned short)blks;
- scsi_setup_write_ext(pccb, start, smallblks);
- start += blks;
- blks = 0;
- }
- debug("%s: startblk " LBAF ", blccnt %x buffer %" PRIXPTR "\n",
- __func__, start, smallblks, buf_addr);
- if (scsi_exec(pccb) != true) {
- scsi_print_error(pccb);
- blkcnt -= blks;
- break;
- }
- buf_addr += pccb->datalen;
- } while (blks != 0);
- debug("%s: end startblk " LBAF ", blccnt %x buffer %" PRIXPTR "\n",
- __func__, start, smallblks, buf_addr);
- return blkcnt;
-}
-
-/* copy src to dest, skipping leading and trailing blanks
- * and null terminate the string
- */
-void scsi_ident_cpy (unsigned char *dest, unsigned char *src, unsigned int len)
-{
- int start,end;
-
- start=0;
- while(start<len) {
- if(src[start]!=' ')
- break;
- start++;
- }
- end=len-1;
- while(end>start) {
- if(src[end]!=' ')
- break;
- end--;
- }
- for( ; start<=end; start++) {
- *dest++=src[start];
- }
- *dest='\0';
-}
-
-
-/* Trim trailing blanks, and NUL-terminate string
- */
-void scsi_trim_trail (unsigned char *str, unsigned int len)
-{
- unsigned char *p = str + len - 1;
-
- while (len-- > 0) {
- *p-- = '\0';
- if (*p != ' ') {
- return;
- }
- }
-}
-
-int scsi_read_capacity(ccb *pccb, lbaint_t *capacity, unsigned long *blksz)
-{
- *capacity = 0;
-
- memset(pccb->cmd, 0, sizeof(pccb->cmd));
- pccb->cmd[0] = SCSI_RD_CAPAC10;
- pccb->cmd[1] = pccb->lun << 5;
- pccb->cmdlen = 10;
- pccb->msgout[0] = SCSI_IDENTIFY; /* NOT USED */
-
- pccb->datalen = 8;
- if (scsi_exec(pccb) != true)
- return 1;
-
- *capacity = ((lbaint_t)pccb->pdata[0] << 24) |
- ((lbaint_t)pccb->pdata[1] << 16) |
- ((lbaint_t)pccb->pdata[2] << 8) |
- ((lbaint_t)pccb->pdata[3]);
-
- if (*capacity != 0xffffffff) {
- /* Read capacity (10) was sufficient for this drive. */
- *blksz = ((unsigned long)pccb->pdata[4] << 24) |
- ((unsigned long)pccb->pdata[5] << 16) |
- ((unsigned long)pccb->pdata[6] << 8) |
- ((unsigned long)pccb->pdata[7]);
- return 0;
- }
-
- /* Read capacity (10) was insufficient. Use read capacity (16). */
-
- memset(pccb->cmd, 0, sizeof(pccb->cmd));
- pccb->cmd[0] = SCSI_RD_CAPAC16;
- pccb->cmd[1] = 0x10;
- pccb->cmdlen = 16;
- pccb->msgout[0] = SCSI_IDENTIFY; /* NOT USED */
-
- pccb->datalen = 16;
- if (scsi_exec(pccb) != true)
- return 1;
-
- *capacity = ((uint64_t)pccb->pdata[0] << 56) |
- ((uint64_t)pccb->pdata[1] << 48) |
- ((uint64_t)pccb->pdata[2] << 40) |
- ((uint64_t)pccb->pdata[3] << 32) |
- ((uint64_t)pccb->pdata[4] << 24) |
- ((uint64_t)pccb->pdata[5] << 16) |
- ((uint64_t)pccb->pdata[6] << 8) |
- ((uint64_t)pccb->pdata[7]);
-
- *blksz = ((uint64_t)pccb->pdata[8] << 56) |
- ((uint64_t)pccb->pdata[9] << 48) |
- ((uint64_t)pccb->pdata[10] << 40) |
- ((uint64_t)pccb->pdata[11] << 32) |
- ((uint64_t)pccb->pdata[12] << 24) |
- ((uint64_t)pccb->pdata[13] << 16) |
- ((uint64_t)pccb->pdata[14] << 8) |
- ((uint64_t)pccb->pdata[15]);
-
- return 0;
-}
-
-
-/************************************************************************************
- * Some setup (fill-in) routines
- */
-void scsi_setup_test_unit_ready(ccb * pccb)
-{
- pccb->cmd[0]=SCSI_TST_U_RDY;
- pccb->cmd[1]=pccb->lun<<5;
- pccb->cmd[2]=0;
- pccb->cmd[3]=0;
- pccb->cmd[4]=0;
- pccb->cmd[5]=0;
- pccb->cmdlen=6;
- pccb->msgout[0]=SCSI_IDENTIFY; /* NOT USED */
-}
-
-#ifdef CONFIG_SYS_64BIT_LBA
-void scsi_setup_read16(ccb * pccb, lbaint_t start, unsigned long blocks)
-{
- pccb->cmd[0] = SCSI_READ16;
- pccb->cmd[1] = pccb->lun<<5;
- pccb->cmd[2] = ((unsigned char) (start >> 56)) & 0xff;
- pccb->cmd[3] = ((unsigned char) (start >> 48)) & 0xff;
- pccb->cmd[4] = ((unsigned char) (start >> 40)) & 0xff;
- pccb->cmd[5] = ((unsigned char) (start >> 32)) & 0xff;
- pccb->cmd[6] = ((unsigned char) (start >> 24)) & 0xff;
- pccb->cmd[7] = ((unsigned char) (start >> 16)) & 0xff;
- pccb->cmd[8] = ((unsigned char) (start >> 8)) & 0xff;
- pccb->cmd[9] = ((unsigned char) (start)) & 0xff;
- pccb->cmd[10] = 0;
- pccb->cmd[11] = ((unsigned char) (blocks >> 24)) & 0xff;
- pccb->cmd[12] = ((unsigned char) (blocks >> 16)) & 0xff;
- pccb->cmd[13] = ((unsigned char) (blocks >> 8)) & 0xff;
- pccb->cmd[14] = (unsigned char) blocks & 0xff;
- pccb->cmd[15] = 0;
- pccb->cmdlen = 16;
- pccb->msgout[0] = SCSI_IDENTIFY; /* NOT USED */
- debug ("scsi_setup_read16: cmd: %02X %02X "
- "startblk %02X%02X%02X%02X%02X%02X%02X%02X "
- "blccnt %02X%02X%02X%02X\n",
- pccb->cmd[0], pccb->cmd[1],
- pccb->cmd[2], pccb->cmd[3], pccb->cmd[4], pccb->cmd[5],
- pccb->cmd[6], pccb->cmd[7], pccb->cmd[8], pccb->cmd[9],
- pccb->cmd[11], pccb->cmd[12], pccb->cmd[13], pccb->cmd[14]);
-}
-#endif
-
-void scsi_setup_read_ext(ccb * pccb, lbaint_t start, unsigned short blocks)
-{
- pccb->cmd[0]=SCSI_READ10;
- pccb->cmd[1]=pccb->lun<<5;
- pccb->cmd[2]=((unsigned char) (start>>24))&0xff;
- pccb->cmd[3]=((unsigned char) (start>>16))&0xff;
- pccb->cmd[4]=((unsigned char) (start>>8))&0xff;
- pccb->cmd[5]=((unsigned char) (start))&0xff;
- pccb->cmd[6]=0;
- pccb->cmd[7]=((unsigned char) (blocks>>8))&0xff;
- pccb->cmd[8]=(unsigned char) blocks & 0xff;
- pccb->cmd[6]=0;
- pccb->cmdlen=10;
- pccb->msgout[0]=SCSI_IDENTIFY; /* NOT USED */
- debug ("scsi_setup_read_ext: cmd: %02X %02X startblk %02X%02X%02X%02X blccnt %02X%02X\n",
- pccb->cmd[0],pccb->cmd[1],
- pccb->cmd[2],pccb->cmd[3],pccb->cmd[4],pccb->cmd[5],
- pccb->cmd[7],pccb->cmd[8]);
-}
-
-void scsi_setup_write_ext(ccb *pccb, lbaint_t start, unsigned short blocks)
-{
- pccb->cmd[0] = SCSI_WRITE10;
- pccb->cmd[1] = pccb->lun << 5;
- pccb->cmd[2] = ((unsigned char) (start>>24)) & 0xff;
- pccb->cmd[3] = ((unsigned char) (start>>16)) & 0xff;
- pccb->cmd[4] = ((unsigned char) (start>>8)) & 0xff;
- pccb->cmd[5] = ((unsigned char) (start)) & 0xff;
- pccb->cmd[6] = 0;
- pccb->cmd[7] = ((unsigned char) (blocks>>8)) & 0xff;
- pccb->cmd[8] = (unsigned char)blocks & 0xff;
- pccb->cmd[9] = 0;
- pccb->cmdlen = 10;
- pccb->msgout[0] = SCSI_IDENTIFY; /* NOT USED */
- debug("%s: cmd: %02X %02X startblk %02X%02X%02X%02X blccnt %02X%02X\n",
- __func__,
- pccb->cmd[0], pccb->cmd[1],
- pccb->cmd[2], pccb->cmd[3], pccb->cmd[4], pccb->cmd[5],
- pccb->cmd[7], pccb->cmd[8]);
-}
-
-void scsi_setup_read6(ccb * pccb, lbaint_t start, unsigned short blocks)
-{
- pccb->cmd[0]=SCSI_READ6;
- pccb->cmd[1]=pccb->lun<<5 | (((unsigned char)(start>>16))&0x1f);
- pccb->cmd[2]=((unsigned char) (start>>8))&0xff;
- pccb->cmd[3]=((unsigned char) (start))&0xff;
- pccb->cmd[4]=(unsigned char) blocks & 0xff;
- pccb->cmd[5]=0;
- pccb->cmdlen=6;
- pccb->msgout[0]=SCSI_IDENTIFY; /* NOT USED */
- debug ("scsi_setup_read6: cmd: %02X %02X startblk %02X%02X blccnt %02X\n",
- pccb->cmd[0],pccb->cmd[1],
- pccb->cmd[2],pccb->cmd[3],pccb->cmd[4]);
-}
-
-
-void scsi_setup_inquiry(ccb * pccb)
-{
- pccb->cmd[0]=SCSI_INQUIRY;
- pccb->cmd[1]=pccb->lun<<5;
- pccb->cmd[2]=0;
- pccb->cmd[3]=0;
- if(pccb->datalen>255)
- pccb->cmd[4]=255;
- else
- pccb->cmd[4]=(unsigned char)pccb->datalen;
- pccb->cmd[5]=0;
- pccb->cmdlen=6;
- pccb->msgout[0]=SCSI_IDENTIFY; /* NOT USED */
-}
int devno, ok = 0;
if (argc == 2) {
for (devno = 0; ; ++devno) {
- stor_dev = usb_stor_get_dev(devno);
+ stor_dev = blk_get_devnum_by_type(IF_TYPE_USB,
+ devno);
if (stor_dev == NULL)
break;
if (stor_dev->type != DEV_TYPE_UNKNOWN) {
}
} else {
devno = simple_strtoul(argv[2], NULL, 16);
- stor_dev = usb_stor_get_dev(devno);
+ stor_dev = blk_get_devnum_by_type(IF_TYPE_USB, devno);
if (stor_dev != NULL &&
stor_dev->type != DEV_TYPE_UNKNOWN) {
ok++;
unsigned long n;
printf("\nUSB read: device %d block # %ld, count %ld"
" ... ", usb_stor_curr_dev, blk, cnt);
- stor_dev = usb_stor_get_dev(usb_stor_curr_dev);
+ stor_dev = blk_get_devnum_by_type(IF_TYPE_USB,
+ usb_stor_curr_dev);
n = blk_dread(stor_dev, blk, cnt, (ulong *)addr);
printf("%ld blocks read: %s\n", n,
(n == cnt) ? "OK" : "ERROR");
unsigned long n;
printf("\nUSB write: device %d block # %ld, count %ld"
" ... ", usb_stor_curr_dev, blk, cnt);
- stor_dev = usb_stor_get_dev(usb_stor_curr_dev);
+ stor_dev = blk_get_devnum_by_type(IF_TYPE_USB,
+ usb_stor_curr_dev);
n = blk_dwrite(stor_dev, blk, cnt, (ulong *)addr);
printf("%ld blocks write: %s\n", n,
(n == cnt) ? "OK" : "ERROR");
if (argc == 3) {
int dev = (int)simple_strtoul(argv[2], NULL, 10);
printf("\nUSB device %d: ", dev);
- stor_dev = usb_stor_get_dev(dev);
+ stor_dev = blk_get_devnum_by_type(IF_TYPE_USB, dev);
if (stor_dev == NULL) {
printf("unknown device\n");
return 1;
return 0;
} else {
printf("\nUSB device %d: ", usb_stor_curr_dev);
- stor_dev = usb_stor_get_dev(usb_stor_curr_dev);
+ stor_dev = blk_get_devnum_by_type(IF_TYPE_USB,
+ usb_stor_curr_dev);
dev_print(stor_dev);
if (stor_dev->type == DEV_TYPE_UNKNOWN)
return 1;
obj-$(CONFIG_LCD_DT_SIMPLEFB) += lcd_simplefb.o
obj-$(CONFIG_LYNXKDI) += lynxkdi.o
obj-$(CONFIG_MENU) += menu.o
+obj-$(CONFIG_CMD_SATA) += sata.o
+obj-$(CONFIG_SCSI) += scsi.o
obj-$(CONFIG_UPDATE_TFTP) += update.o
obj-$(CONFIG_DFU_TFTP) += update.o
obj-$(CONFIG_USB_KEYBOARD) += usb_kbd.o
obj-$(CONFIG_ENV_IS_IN_SPI_FLASH) += env_sf.o
obj-$(CONFIG_ENV_IS_IN_FLASH) += env_flash.o
endif
+ifdef CONFIG_SPL_SATA_SUPPORT
+obj-$(CONFIG_SCSI) += scsi.o
+endif
endif
#environment
obj-y += env_common.o
ifdef CONFIG_SYS_MALLOC_F_LEN
obj-y += malloc_simple.o
endif
+obj-$(CONFIG_CMD_IDE) += ide.o
obj-y += image.o
obj-$(CONFIG_ANDROID_BOOT_IMAGE) += image-android.o
obj-$(CONFIG_$(SPL_)OF_LIBFDT) += image-fdt.o
endif
endif
+ifdef CONFIG_CMD_EEPROM_LAYOUT
+obj-y += eeprom/eeprom_field.o eeprom/eeprom_layout.o
+endif
# We always have this since drivers/ddr/fs/interactive.c needs it
obj-$(CONFIG_CMDLINE) += cli_simple.o
}
#endif
-#if defined(CONFIG_CMD_SCSI)
+#if defined(CONFIG_SCSI)
static int initr_scsi(void)
{
puts("SCSI: ");
initr_ambapp_print,
#endif
#endif
-#ifdef CONFIG_CMD_SCSI
+#ifdef CONFIG_SCSI
INIT_FUNC_WATCHDOG_RESET
initr_scsi,
#endif
#endif
#if IMAGE_ENABLE_FIT
+#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_XILINX)
+ /* find bitstreams */
+ ret = boot_get_fpga(argc, argv, &images, IH_ARCH_DEFAULT,
+ NULL, NULL);
+ if (ret) {
+ printf("FPGA image is corrupted or invalid\n");
+ return 1;
+ }
+#endif
+
/* find all of the loadables */
ret = boot_get_loadable(argc, argv, &images, IH_ARCH_DEFAULT,
NULL, NULL);
* fulfill the user's request.
*/
if (m == NULL) {
+ size_t extra, extra2;
/*
* Use bytes not nb, since mALLOc internally calls request2size too, and
* each call increases the size to allocate, to account for the header.
/* Aligned -> return it */
if ((((unsigned long)(m)) % alignment) == 0)
return m;
- /* Otherwise, fail */
+ /*
+ * Otherwise, try again, requesting enough extra space to be able to
+ * acquire alignment.
+ */
fREe(m);
- m = NULL;
+ /* Add in extra bytes to match misalignment of unexpanded allocation */
+ extra = alignment - (((unsigned long)(m)) % alignment);
+ m = (char*)(mALLOc(bytes + extra));
+ /*
+ * m might not be the same as before. Validate that the previous value of
+ * extra still works for the current value of m.
+ * If (!m), extra2=alignment so
+ */
+ if (m) {
+ extra2 = alignment - (((unsigned long)(m)) % alignment);
+ if (extra2 > extra) {
+ fREe(m);
+ m = NULL;
+ }
+ }
+ /* Fall through to original NULL check and chunk splitting logic */
}
if (m == NULL) return NULL; /* propagate failure */
--- /dev/null
+/*
+ * (C) Copyright 2009-2016 CompuLab, Ltd.
+ *
+ * Authors: Nikita Kiryanov <nikita@compulab.co.il>
+ * Igor Grinberg <grinberg@compulab.co.il>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/string.h>
+#include <eeprom_field.h>
+
+static void __eeprom_field_print_bin(const struct eeprom_field *field,
+ char *delimiter, bool reverse)
+{
+ int i;
+ int from = reverse ? field->size - 1 : 0;
+ int to = reverse ? 0 : field->size - 1;
+
+ printf(PRINT_FIELD_SEGMENT, field->name);
+ for (i = from; i != to; reverse ? i-- : i++)
+ printf("%02x%s", field->buf[i], delimiter);
+
+ printf("%02x\n", field->buf[i]);
+}
+
+static int __eeprom_field_update_bin(struct eeprom_field *field,
+ const char *value, bool reverse)
+{
+ int len = strlen(value);
+ int k, j, i = reverse ? len - 1 : 0;
+ unsigned char byte;
+ char *endptr;
+
+ /* each two characters in the string fit in one byte */
+ if (len > field->size * 2)
+ return -1;
+
+ memset(field->buf, 0, field->size);
+
+ /* i - string iterator, j - buf iterator */
+ for (j = 0; j < field->size; j++) {
+ byte = 0;
+ char tmp[3] = { 0, 0, 0 };
+
+ if ((reverse && i < 0) || (!reverse && i >= len))
+ break;
+
+ for (k = 0; k < 2; k++) {
+ if (reverse && i == 0) {
+ tmp[k] = value[i];
+ break;
+ }
+
+ tmp[k] = value[reverse ? i - 1 + k : i + k];
+ }
+
+ byte = simple_strtoul(tmp, &endptr, 0);
+ if (*endptr != '\0' || byte < 0)
+ return -1;
+
+ field->buf[j] = byte;
+ i = reverse ? i - 2 : i + 2;
+ }
+
+ return 0;
+}
+
+static int __eeprom_field_update_bin_delim(struct eeprom_field *field,
+ char *value, char *delimiter)
+{
+ int count = 0;
+ int i, val;
+ const char *tmp = value;
+ char *tok;
+ char *endptr;
+
+ tmp = strstr(tmp, delimiter);
+ while (tmp != NULL) {
+ count++;
+ tmp++;
+ tmp = strstr(tmp, delimiter);
+ }
+
+ if (count > field->size)
+ return -1;
+
+ tok = strtok(value, delimiter);
+ for (i = 0; tok && i < field->size; i++) {
+ val = simple_strtoul(tok, &endptr, 0);
+ if (*endptr != '\0')
+ return -1;
+
+ /* here we assume that each tok is no more than byte long */
+ field->buf[i] = (unsigned char)val;
+ tok = strtok(NULL, delimiter);
+ }
+
+ return 0;
+}
+
+/**
+ * eeprom_field_print_bin() - print a field which contains binary data
+ *
+ * Treat the field data as simple binary data, and print it as two digit
+ * hexadecimal values.
+ * Sample output:
+ * Field Name 0102030405060708090a
+ *
+ * @field: an initialized field to print
+ */
+void eeprom_field_print_bin(const struct eeprom_field *field)
+{
+ __eeprom_field_print_bin(field, "", false);
+}
+
+/**
+ * eeprom_field_update_bin() - Update field with new data in binary form
+ *
+ * @field: an initialized field
+ * @value: a string of values (i.e. "10b234a")
+ */
+int eeprom_field_update_bin(struct eeprom_field *field, char *value)
+{
+ return __eeprom_field_update_bin(field, value, false);
+}
+
+/**
+ * eeprom_field_update_reserved() - Update reserved field with new data in
+ * binary form
+ *
+ * @field: an initialized field
+ * @value: a space delimited string of byte values (i.e. "1 02 3 0x4")
+ */
+int eeprom_field_update_reserved(struct eeprom_field *field, char *value)
+{
+ return __eeprom_field_update_bin_delim(field, value, " ");
+}
+
+/**
+ * eeprom_field_print_bin_rev() - print a field which contains binary data in
+ * reverse order
+ *
+ * Treat the field data as simple binary data, and print it in reverse order
+ * as two digit hexadecimal values.
+ *
+ * Data in field:
+ * 0102030405060708090a
+ * Sample output:
+ * Field Name 0a090807060504030201
+ *
+ * @field: an initialized field to print
+ */
+void eeprom_field_print_bin_rev(const struct eeprom_field *field)
+{
+ __eeprom_field_print_bin(field, "", true);
+}
+
+/**
+ * eeprom_field_update_bin_rev() - Update field with new data in binary form,
+ * storing it in reverse
+ *
+ * This function takes a string of byte values, and stores them
+ * in the field in the reverse order. i.e. if the input string was "1234",
+ * "3412" will be written to the field.
+ *
+ * @field: an initialized field
+ * @value: a string of byte values
+ */
+int eeprom_field_update_bin_rev(struct eeprom_field *field, char *value)
+{
+ return __eeprom_field_update_bin(field, value, true);
+}
+
+/**
+ * eeprom_field_print_mac_addr() - print a field which contains a mac address
+ *
+ * Treat the field data as simple binary data, and print it formatted as a MAC
+ * address.
+ * Sample output:
+ * Field Name 01:02:03:04:05:06
+ *
+ * @field: an initialized field to print
+ */
+void eeprom_field_print_mac(const struct eeprom_field *field)
+{
+ __eeprom_field_print_bin(field, ":", false);
+}
+
+/**
+ * eeprom_field_update_mac() - Update a mac address field which contains binary
+ * data
+ *
+ * @field: an initialized field
+ * @value: a colon delimited string of byte values (i.e. "1:02:3:ff")
+ */
+int eeprom_field_update_mac(struct eeprom_field *field, char *value)
+{
+ return __eeprom_field_update_bin_delim(field, value, ":");
+}
+
+/**
+ * eeprom_field_print_ascii() - print a field which contains ASCII data
+ * @field: an initialized field to print
+ */
+void eeprom_field_print_ascii(const struct eeprom_field *field)
+{
+ char format[8];
+
+ sprintf(format, "%%.%ds\n", field->size);
+ printf(PRINT_FIELD_SEGMENT, field->name);
+ printf(format, field->buf);
+}
+
+/**
+ * eeprom_field_update_ascii() - Update field with new data in ASCII form
+ * @field: an initialized field
+ * @value: the new string data
+ *
+ * Returns 0 on success, -1 of failure (new string too long).
+ */
+int eeprom_field_update_ascii(struct eeprom_field *field, char *value)
+{
+ if (strlen(value) >= field->size) {
+ printf("%s: new data too long\n", field->name);
+ return -1;
+ }
+
+ strncpy((char *)field->buf, value, field->size - 1);
+ field->buf[field->size - 1] = '\0';
+
+ return 0;
+}
+
+/**
+ * eeprom_field_print_reserved() - print the "Reserved fields" field
+ *
+ * Print a notice that the following field_size bytes are reserved.
+ *
+ * Sample output:
+ * Reserved fields (64 bytes)
+ *
+ * @field: an initialized field to print
+ */
+void eeprom_field_print_reserved(const struct eeprom_field *field)
+{
+ printf(PRINT_FIELD_SEGMENT, "Reserved fields\t");
+ printf("(%d bytes)\n", field->size);
+}
--- /dev/null
+/*
+ * (C) Copyright 2009-2016 CompuLab, Ltd.
+ *
+ * Authors: Nikita Kiryanov <nikita@compulab.co.il>
+ * Igor Grinberg <grinberg@compulab.co.il>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/kernel.h>
+#include <eeprom_layout.h>
+#include <eeprom_field.h>
+
+#define NO_LAYOUT_FIELDS "Unknown layout. Dumping raw data\n"
+
+struct eeprom_field layout_unknown[1] = {
+ { NO_LAYOUT_FIELDS, 256, NULL, eeprom_field_print_bin,
+ eeprom_field_update_bin },
+};
+
+/*
+ * eeprom_layout_detect() - detect layout based on the contents of the data.
+ * @data: Pointer to the data to be analyzed.
+ *
+ * Returns: the detected layout version.
+ */
+__weak int eeprom_layout_detect(unsigned char *data)
+{
+ return LAYOUT_VERSION_UNRECOGNIZED;
+}
+
+/*
+ * __eeprom_layout_assign() - set the layout fields
+ * @layout: A pointer to an existing struct layout.
+ * @layout_version: The version number of the desired layout
+ */
+__weak void __eeprom_layout_assign(struct eeprom_layout *layout,
+ int layout_version)
+{
+ layout->fields = layout_unknown;
+ layout->num_of_fields = ARRAY_SIZE(layout_unknown);
+}
+void eeprom_layout_assign(struct eeprom_layout *layout, int layout_version) \
+ __attribute__((weak, alias("__eeprom_layout_assign")));
+
+/*
+ * eeprom_layout_print() - print the layout and the data which is assigned to it
+ * @layout: A pointer to an existing struct layout.
+ */
+static void eeprom_layout_print(const struct eeprom_layout *layout)
+{
+ int i;
+ struct eeprom_field *fields = layout->fields;
+
+ for (i = 0; i < layout->num_of_fields; i++)
+ fields[i].print(&fields[i]);
+}
+
+/*
+ * eeprom_layout_update_field() - update a single field in the layout data.
+ * @layout: A pointer to an existing struct layout.
+ * @field_name: The name of the field to update.
+ * @new_data: The new field data (a string. Format depends on the field)
+ *
+ * Returns: 0 on success, negative error value on failure.
+ */
+static int eeprom_layout_update_field(struct eeprom_layout *layout,
+ char *field_name, char *new_data)
+{
+ int i, err;
+ struct eeprom_field *fields = layout->fields;
+
+ if (new_data == NULL)
+ return 0;
+
+ if (field_name == NULL)
+ return -1;
+
+ for (i = 0; i < layout->num_of_fields; i++) {
+ if (fields[i].name == RESERVED_FIELDS ||
+ strcmp(fields[i].name, field_name))
+ continue;
+
+ err = fields[i].update(&fields[i], new_data);
+ if (err)
+ printf("Invalid data for field %s\n", field_name);
+
+ return err;
+ }
+
+ printf("No such field '%s'\n", field_name);
+
+ return -1;
+}
+
+/*
+ * eeprom_layout_setup() - setup layout struct with the layout data and
+ * metadata as dictated by layout_version
+ * @layout: A pointer to an existing struct layout.
+ * @buf: A buffer initialized with the eeprom data.
+ * @buf_size: Size of buf in bytes.
+ * @layout version: The version number of the layout.
+ */
+void eeprom_layout_setup(struct eeprom_layout *layout, unsigned char *buf,
+ unsigned int buf_size, int layout_version)
+{
+ int i;
+
+ if (layout_version == LAYOUT_VERSION_AUTODETECT)
+ layout->layout_version = eeprom_layout_detect(buf);
+ else
+ layout->layout_version = layout_version;
+
+ eeprom_layout_assign(layout, layout_version);
+ layout->data = buf;
+ for (i = 0; i < layout->num_of_fields; i++) {
+ layout->fields[i].buf = buf;
+ buf += layout->fields[i].size;
+ }
+
+ layout->data_size = buf_size;
+ layout->print = eeprom_layout_print;
+ layout->update = eeprom_layout_update_field;
+}
dev = 0;
#endif
- env_mmc_orig_hwpart = mmc->block_dev.hwpart;
- ret = mmc_select_hwpart(dev, part);
+ env_mmc_orig_hwpart = mmc_get_blk_desc(mmc)->hwpart;
+ ret = blk_select_hwpart_devnum(IF_TYPE_MMC, dev, part);
if (ret)
puts("MMC partition switch failed\n");
#ifdef CONFIG_SPL_BUILD
dev = 0;
#endif
- mmc_select_hwpart(dev, env_mmc_orig_hwpart);
+ blk_select_hwpart_devnum(IF_TYPE_MMC, dev, env_mmc_orig_hwpart);
#endif
}
--- /dev/null
+/*
+ * (C) Copyright 2000-2011
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <ata.h>
+#include <dm.h>
+#include <ide.h>
+#include <watchdog.h>
+#include <asm/io.h>
+
+#ifdef __PPC__
+# define EIEIO __asm__ volatile ("eieio")
+# define SYNC __asm__ volatile ("sync")
+#else
+# define EIEIO /* nothing */
+# define SYNC /* nothing */
+#endif
+
+/* Current offset for IDE0 / IDE1 bus access */
+ulong ide_bus_offset[CONFIG_SYS_IDE_MAXBUS] = {
+#if defined(CONFIG_SYS_ATA_IDE0_OFFSET)
+ CONFIG_SYS_ATA_IDE0_OFFSET,
+#endif
+#if defined(CONFIG_SYS_ATA_IDE1_OFFSET) && (CONFIG_SYS_IDE_MAXBUS > 1)
+ CONFIG_SYS_ATA_IDE1_OFFSET,
+#endif
+};
+
+static int ide_bus_ok[CONFIG_SYS_IDE_MAXBUS];
+
+struct blk_desc ide_dev_desc[CONFIG_SYS_IDE_MAXDEVICE];
+
+#define IDE_TIME_OUT 2000 /* 2 sec timeout */
+
+#define ATAPI_TIME_OUT 7000 /* 7 sec timeout (5 sec seems to work...) */
+
+#define IDE_SPIN_UP_TIME_OUT 5000 /* 5 sec spin-up timeout */
+
+#ifndef CONFIG_SYS_ATA_PORT_ADDR
+#define CONFIG_SYS_ATA_PORT_ADDR(port) (port)
+#endif
+
+#ifndef CONFIG_IDE_LED /* define LED macros, they are not used anyways */
+# define DEVICE_LED(x) 0
+# define LED_IDE1 1
+# define LED_IDE2 2
+#endif
+
+#ifdef CONFIG_IDE_RESET
+extern void ide_set_reset(int idereset);
+
+static void ide_reset(void)
+{
+ int i;
+
+ for (i = 0; i < CONFIG_SYS_IDE_MAXBUS; ++i)
+ ide_bus_ok[i] = 0;
+ for (i = 0; i < CONFIG_SYS_IDE_MAXDEVICE; ++i)
+ ide_dev_desc[i].type = DEV_TYPE_UNKNOWN;
+
+ ide_set_reset(1); /* assert reset */
+
+ /* the reset signal shall be asserted for et least 25 us */
+ udelay(25);
+
+ WATCHDOG_RESET();
+
+ /* de-assert RESET signal */
+ ide_set_reset(0);
+
+ /* wait 250 ms */
+ for (i = 0; i < 250; ++i)
+ udelay(1000);
+}
+#else
+#define ide_reset() /* dummy */
+#endif /* CONFIG_IDE_RESET */
+
+/*
+ * Wait until Busy bit is off, or timeout (in ms)
+ * Return last status
+ */
+static uchar ide_wait(int dev, ulong t)
+{
+ ulong delay = 10 * t; /* poll every 100 us */
+ uchar c;
+
+ while ((c = ide_inb(dev, ATA_STATUS)) & ATA_STAT_BUSY) {
+ udelay(100);
+ if (delay-- == 0)
+ break;
+ }
+ return c;
+}
+
+/*
+ * copy src to dest, skipping leading and trailing blanks and null
+ * terminate the string
+ * "len" is the size of available memory including the terminating '\0'
+ */
+static void ident_cpy(unsigned char *dst, unsigned char *src,
+ unsigned int len)
+{
+ unsigned char *end, *last;
+
+ last = dst;
+ end = src + len - 1;
+
+ /* reserve space for '\0' */
+ if (len < 2)
+ goto OUT;
+
+ /* skip leading white space */
+ while ((*src) && (src < end) && (*src == ' '))
+ ++src;
+
+ /* copy string, omitting trailing white space */
+ while ((*src) && (src < end)) {
+ *dst++ = *src;
+ if (*src++ != ' ')
+ last = dst;
+ }
+OUT:
+ *last = '\0';
+}
+
+#ifdef CONFIG_ATAPI
+/****************************************************************************
+ * ATAPI Support
+ */
+
+#if defined(CONFIG_IDE_SWAP_IO)
+/* since ATAPI may use commands with not 4 bytes alligned length
+ * we have our own transfer functions, 2 bytes alligned */
+__weak void ide_output_data_shorts(int dev, ushort *sect_buf, int shorts)
+{
+ ushort *dbuf;
+ volatile ushort *pbuf;
+
+ pbuf = (ushort *)(ATA_CURR_BASE(dev) + ATA_DATA_REG);
+ dbuf = (ushort *)sect_buf;
+
+ debug("in output data shorts base for read is %lx\n",
+ (unsigned long) pbuf);
+
+ while (shorts--) {
+ EIEIO;
+ *pbuf = *dbuf++;
+ }
+}
+
+__weak void ide_input_data_shorts(int dev, ushort *sect_buf, int shorts)
+{
+ ushort *dbuf;
+ volatile ushort *pbuf;
+
+ pbuf = (ushort *)(ATA_CURR_BASE(dev) + ATA_DATA_REG);
+ dbuf = (ushort *)sect_buf;
+
+ debug("in input data shorts base for read is %lx\n",
+ (unsigned long) pbuf);
+
+ while (shorts--) {
+ EIEIO;
+ *dbuf++ = *pbuf;
+ }
+}
+
+#else /* ! CONFIG_IDE_SWAP_IO */
+__weak void ide_output_data_shorts(int dev, ushort *sect_buf, int shorts)
+{
+ outsw(ATA_CURR_BASE(dev) + ATA_DATA_REG, sect_buf, shorts);
+}
+
+__weak void ide_input_data_shorts(int dev, ushort *sect_buf, int shorts)
+{
+ insw(ATA_CURR_BASE(dev) + ATA_DATA_REG, sect_buf, shorts);
+}
+
+#endif /* CONFIG_IDE_SWAP_IO */
+
+/*
+ * Wait until (Status & mask) == res, or timeout (in ms)
+ * Return last status
+ * This is used since some ATAPI CD ROMs clears their Busy Bit first
+ * and then they set their DRQ Bit
+ */
+static uchar atapi_wait_mask(int dev, ulong t, uchar mask, uchar res)
+{
+ ulong delay = 10 * t; /* poll every 100 us */
+ uchar c;
+
+ /* prevents to read the status before valid */
+ c = ide_inb(dev, ATA_DEV_CTL);
+
+ while (((c = ide_inb(dev, ATA_STATUS)) & mask) != res) {
+ /* break if error occurs (doesn't make sense to wait more) */
+ if ((c & ATA_STAT_ERR) == ATA_STAT_ERR)
+ break;
+ udelay(100);
+ if (delay-- == 0)
+ break;
+ }
+ return c;
+}
+
+/*
+ * issue an atapi command
+ */
+unsigned char atapi_issue(int device, unsigned char *ccb, int ccblen,
+ unsigned char *buffer, int buflen)
+{
+ unsigned char c, err, mask, res;
+ int n;
+
+ ide_led(DEVICE_LED(device), 1); /* LED on */
+
+ /* Select device
+ */
+ mask = ATA_STAT_BUSY | ATA_STAT_DRQ;
+ res = 0;
+ ide_outb(device, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(device));
+ c = atapi_wait_mask(device, ATAPI_TIME_OUT, mask, res);
+ if ((c & mask) != res) {
+ printf("ATAPI_ISSUE: device %d not ready status %X\n", device,
+ c);
+ err = 0xFF;
+ goto AI_OUT;
+ }
+ /* write taskfile */
+ ide_outb(device, ATA_ERROR_REG, 0); /* no DMA, no overlaped */
+ ide_outb(device, ATA_SECT_CNT, 0);
+ ide_outb(device, ATA_SECT_NUM, 0);
+ ide_outb(device, ATA_CYL_LOW, (unsigned char) (buflen & 0xFF));
+ ide_outb(device, ATA_CYL_HIGH,
+ (unsigned char) ((buflen >> 8) & 0xFF));
+ ide_outb(device, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(device));
+
+ ide_outb(device, ATA_COMMAND, ATAPI_CMD_PACKET);
+ udelay(50);
+
+ mask = ATA_STAT_DRQ | ATA_STAT_BUSY | ATA_STAT_ERR;
+ res = ATA_STAT_DRQ;
+ c = atapi_wait_mask(device, ATAPI_TIME_OUT, mask, res);
+
+ if ((c & mask) != res) { /* DRQ must be 1, BSY 0 */
+ printf("ATAPI_ISSUE: Error (no IRQ) before sending ccb dev %d status 0x%02x\n",
+ device, c);
+ err = 0xFF;
+ goto AI_OUT;
+ }
+
+ /* write command block */
+ ide_output_data_shorts(device, (unsigned short *)ccb, ccblen / 2);
+
+ /* ATAPI Command written wait for completition */
+ udelay(5000); /* device must set bsy */
+
+ mask = ATA_STAT_DRQ | ATA_STAT_BUSY | ATA_STAT_ERR;
+ /*
+ * if no data wait for DRQ = 0 BSY = 0
+ * if data wait for DRQ = 1 BSY = 0
+ */
+ res = 0;
+ if (buflen)
+ res = ATA_STAT_DRQ;
+ c = atapi_wait_mask(device, ATAPI_TIME_OUT, mask, res);
+ if ((c & mask) != res) {
+ if (c & ATA_STAT_ERR) {
+ err = (ide_inb(device, ATA_ERROR_REG)) >> 4;
+ debug("atapi_issue 1 returned sense key %X status %02X\n",
+ err, c);
+ } else {
+ printf("ATAPI_ISSUE: (no DRQ) after sending ccb (%x) status 0x%02x\n",
+ ccb[0], c);
+ err = 0xFF;
+ }
+ goto AI_OUT;
+ }
+ n = ide_inb(device, ATA_CYL_HIGH);
+ n <<= 8;
+ n += ide_inb(device, ATA_CYL_LOW);
+ if (n > buflen) {
+ printf("ERROR, transfer bytes %d requested only %d\n", n,
+ buflen);
+ err = 0xff;
+ goto AI_OUT;
+ }
+ if ((n == 0) && (buflen < 0)) {
+ printf("ERROR, transfer bytes %d requested %d\n", n, buflen);
+ err = 0xff;
+ goto AI_OUT;
+ }
+ if (n != buflen) {
+ debug("WARNING, transfer bytes %d not equal with requested %d\n",
+ n, buflen);
+ }
+ if (n != 0) { /* data transfer */
+ debug("ATAPI_ISSUE: %d Bytes to transfer\n", n);
+ /* we transfer shorts */
+ n >>= 1;
+ /* ok now decide if it is an in or output */
+ if ((ide_inb(device, ATA_SECT_CNT) & 0x02) == 0) {
+ debug("Write to device\n");
+ ide_output_data_shorts(device, (unsigned short *)buffer,
+ n);
+ } else {
+ debug("Read from device @ %p shorts %d\n", buffer, n);
+ ide_input_data_shorts(device, (unsigned short *)buffer,
+ n);
+ }
+ }
+ udelay(5000); /* seems that some CD ROMs need this... */
+ mask = ATA_STAT_BUSY | ATA_STAT_ERR;
+ res = 0;
+ c = atapi_wait_mask(device, ATAPI_TIME_OUT, mask, res);
+ if ((c & ATA_STAT_ERR) == ATA_STAT_ERR) {
+ err = (ide_inb(device, ATA_ERROR_REG) >> 4);
+ debug("atapi_issue 2 returned sense key %X status %X\n", err,
+ c);
+ } else {
+ err = 0;
+ }
+AI_OUT:
+ ide_led(DEVICE_LED(device), 0); /* LED off */
+ return err;
+}
+
+/*
+ * sending the command to atapi_issue. If an status other than good
+ * returns, an request_sense will be issued
+ */
+
+#define ATAPI_DRIVE_NOT_READY 100
+#define ATAPI_UNIT_ATTN 10
+
+unsigned char atapi_issue_autoreq(int device,
+ unsigned char *ccb,
+ int ccblen,
+ unsigned char *buffer, int buflen)
+{
+ unsigned char sense_data[18], sense_ccb[12];
+ unsigned char res, key, asc, ascq;
+ int notready, unitattn;
+
+ unitattn = ATAPI_UNIT_ATTN;
+ notready = ATAPI_DRIVE_NOT_READY;
+
+retry:
+ res = atapi_issue(device, ccb, ccblen, buffer, buflen);
+ if (res == 0)
+ return 0; /* Ok */
+
+ if (res == 0xFF)
+ return 0xFF; /* error */
+
+ debug("(auto_req)atapi_issue returned sense key %X\n", res);
+
+ memset(sense_ccb, 0, sizeof(sense_ccb));
+ memset(sense_data, 0, sizeof(sense_data));
+ sense_ccb[0] = ATAPI_CMD_REQ_SENSE;
+ sense_ccb[4] = 18; /* allocation Length */
+
+ res = atapi_issue(device, sense_ccb, 12, sense_data, 18);
+ key = (sense_data[2] & 0xF);
+ asc = (sense_data[12]);
+ ascq = (sense_data[13]);
+
+ debug("ATAPI_CMD_REQ_SENSE returned %x\n", res);
+ debug(" Sense page: %02X key %02X ASC %02X ASCQ %02X\n",
+ sense_data[0], key, asc, ascq);
+
+ if ((key == 0))
+ return 0; /* ok device ready */
+
+ if ((key == 6) || (asc == 0x29) || (asc == 0x28)) { /* Unit Attention */
+ if (unitattn-- > 0) {
+ udelay(200 * 1000);
+ goto retry;
+ }
+ printf("Unit Attention, tried %d\n", ATAPI_UNIT_ATTN);
+ goto error;
+ }
+ if ((asc == 0x4) && (ascq == 0x1)) {
+ /* not ready, but will be ready soon */
+ if (notready-- > 0) {
+ udelay(200 * 1000);
+ goto retry;
+ }
+ printf("Drive not ready, tried %d times\n",
+ ATAPI_DRIVE_NOT_READY);
+ goto error;
+ }
+ if (asc == 0x3a) {
+ debug("Media not present\n");
+ goto error;
+ }
+
+ printf("ERROR: Unknown Sense key %02X ASC %02X ASCQ %02X\n", key, asc,
+ ascq);
+error:
+ debug("ERROR Sense key %02X ASC %02X ASCQ %02X\n", key, asc, ascq);
+ return 0xFF;
+}
+
+/*
+ * atapi_read:
+ * we transfer only one block per command, since the multiple DRQ per
+ * command is not yet implemented
+ */
+#define ATAPI_READ_MAX_BYTES 2048 /* we read max 2kbytes */
+#define ATAPI_READ_BLOCK_SIZE 2048 /* assuming CD part */
+#define ATAPI_READ_MAX_BLOCK (ATAPI_READ_MAX_BYTES/ATAPI_READ_BLOCK_SIZE)
+
+ulong atapi_read(struct blk_desc *block_dev, lbaint_t blknr, lbaint_t blkcnt,
+ void *buffer)
+{
+ int device = block_dev->devnum;
+ ulong n = 0;
+ unsigned char ccb[12]; /* Command descriptor block */
+ ulong cnt;
+
+ debug("atapi_read dev %d start " LBAF " blocks " LBAF
+ " buffer at %lX\n", device, blknr, blkcnt, (ulong) buffer);
+
+ do {
+ if (blkcnt > ATAPI_READ_MAX_BLOCK)
+ cnt = ATAPI_READ_MAX_BLOCK;
+ else
+ cnt = blkcnt;
+
+ ccb[0] = ATAPI_CMD_READ_12;
+ ccb[1] = 0; /* reserved */
+ ccb[2] = (unsigned char) (blknr >> 24) & 0xFF; /* MSB Block */
+ ccb[3] = (unsigned char) (blknr >> 16) & 0xFF; /* */
+ ccb[4] = (unsigned char) (blknr >> 8) & 0xFF;
+ ccb[5] = (unsigned char) blknr & 0xFF; /* LSB Block */
+ ccb[6] = (unsigned char) (cnt >> 24) & 0xFF; /* MSB Block cnt */
+ ccb[7] = (unsigned char) (cnt >> 16) & 0xFF;
+ ccb[8] = (unsigned char) (cnt >> 8) & 0xFF;
+ ccb[9] = (unsigned char) cnt & 0xFF; /* LSB Block */
+ ccb[10] = 0; /* reserved */
+ ccb[11] = 0; /* reserved */
+
+ if (atapi_issue_autoreq(device, ccb, 12,
+ (unsigned char *)buffer,
+ cnt * ATAPI_READ_BLOCK_SIZE)
+ == 0xFF) {
+ return n;
+ }
+ n += cnt;
+ blkcnt -= cnt;
+ blknr += cnt;
+ buffer += (cnt * ATAPI_READ_BLOCK_SIZE);
+ } while (blkcnt > 0);
+ return n;
+}
+
+static void atapi_inquiry(struct blk_desc *dev_desc)
+{
+ unsigned char ccb[12]; /* Command descriptor block */
+ unsigned char iobuf[64]; /* temp buf */
+ unsigned char c;
+ int device;
+
+ device = dev_desc->devnum;
+ dev_desc->type = DEV_TYPE_UNKNOWN; /* not yet valid */
+ dev_desc->block_read = atapi_read;
+
+ memset(ccb, 0, sizeof(ccb));
+ memset(iobuf, 0, sizeof(iobuf));
+
+ ccb[0] = ATAPI_CMD_INQUIRY;
+ ccb[4] = 40; /* allocation Legnth */
+ c = atapi_issue_autoreq(device, ccb, 12, (unsigned char *)iobuf, 40);
+
+ debug("ATAPI_CMD_INQUIRY returned %x\n", c);
+ if (c != 0)
+ return;
+
+ /* copy device ident strings */
+ ident_cpy((unsigned char *)dev_desc->vendor, &iobuf[8], 8);
+ ident_cpy((unsigned char *)dev_desc->product, &iobuf[16], 16);
+ ident_cpy((unsigned char *)dev_desc->revision, &iobuf[32], 5);
+
+ dev_desc->lun = 0;
+ dev_desc->lba = 0;
+ dev_desc->blksz = 0;
+ dev_desc->log2blksz = LOG2_INVALID(typeof(dev_desc->log2blksz));
+ dev_desc->type = iobuf[0] & 0x1f;
+
+ if ((iobuf[1] & 0x80) == 0x80)
+ dev_desc->removable = 1;
+ else
+ dev_desc->removable = 0;
+
+ memset(ccb, 0, sizeof(ccb));
+ memset(iobuf, 0, sizeof(iobuf));
+ ccb[0] = ATAPI_CMD_START_STOP;
+ ccb[4] = 0x03; /* start */
+
+ c = atapi_issue_autoreq(device, ccb, 12, (unsigned char *)iobuf, 0);
+
+ debug("ATAPI_CMD_START_STOP returned %x\n", c);
+ if (c != 0)
+ return;
+
+ memset(ccb, 0, sizeof(ccb));
+ memset(iobuf, 0, sizeof(iobuf));
+ c = atapi_issue_autoreq(device, ccb, 12, (unsigned char *)iobuf, 0);
+
+ debug("ATAPI_CMD_UNIT_TEST_READY returned %x\n", c);
+ if (c != 0)
+ return;
+
+ memset(ccb, 0, sizeof(ccb));
+ memset(iobuf, 0, sizeof(iobuf));
+ ccb[0] = ATAPI_CMD_READ_CAP;
+ c = atapi_issue_autoreq(device, ccb, 12, (unsigned char *)iobuf, 8);
+ debug("ATAPI_CMD_READ_CAP returned %x\n", c);
+ if (c != 0)
+ return;
+
+ debug("Read Cap: LBA %02X%02X%02X%02X blksize %02X%02X%02X%02X\n",
+ iobuf[0], iobuf[1], iobuf[2], iobuf[3],
+ iobuf[4], iobuf[5], iobuf[6], iobuf[7]);
+
+ dev_desc->lba = ((unsigned long) iobuf[0] << 24) +
+ ((unsigned long) iobuf[1] << 16) +
+ ((unsigned long) iobuf[2] << 8) + ((unsigned long) iobuf[3]);
+ dev_desc->blksz = ((unsigned long) iobuf[4] << 24) +
+ ((unsigned long) iobuf[5] << 16) +
+ ((unsigned long) iobuf[6] << 8) + ((unsigned long) iobuf[7]);
+ dev_desc->log2blksz = LOG2(dev_desc->blksz);
+#ifdef CONFIG_LBA48
+ /* ATAPI devices cannot use 48bit addressing (ATA/ATAPI v7) */
+ dev_desc->lba48 = 0;
+#endif
+ return;
+}
+
+#endif /* CONFIG_ATAPI */
+
+static void ide_ident(struct blk_desc *dev_desc)
+{
+ unsigned char c;
+ hd_driveid_t iop;
+
+#ifdef CONFIG_ATAPI
+ int retries = 0;
+#endif
+ int device;
+
+ device = dev_desc->devnum;
+ printf(" Device %d: ", device);
+
+ ide_led(DEVICE_LED(device), 1); /* LED on */
+ /* Select device
+ */
+ ide_outb(device, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(device));
+ dev_desc->if_type = IF_TYPE_IDE;
+#ifdef CONFIG_ATAPI
+
+ retries = 0;
+
+ /* Warning: This will be tricky to read */
+ while (retries <= 1) {
+ /* check signature */
+ if ((ide_inb(device, ATA_SECT_CNT) == 0x01) &&
+ (ide_inb(device, ATA_SECT_NUM) == 0x01) &&
+ (ide_inb(device, ATA_CYL_LOW) == 0x14) &&
+ (ide_inb(device, ATA_CYL_HIGH) == 0xEB)) {
+ /* ATAPI Signature found */
+ dev_desc->if_type = IF_TYPE_ATAPI;
+ /*
+ * Start Ident Command
+ */
+ ide_outb(device, ATA_COMMAND, ATAPI_CMD_IDENT);
+ /*
+ * Wait for completion - ATAPI devices need more time
+ * to become ready
+ */
+ c = ide_wait(device, ATAPI_TIME_OUT);
+ } else
+#endif
+ {
+ /*
+ * Start Ident Command
+ */
+ ide_outb(device, ATA_COMMAND, ATA_CMD_IDENT);
+
+ /*
+ * Wait for completion
+ */
+ c = ide_wait(device, IDE_TIME_OUT);
+ }
+ ide_led(DEVICE_LED(device), 0); /* LED off */
+
+ if (((c & ATA_STAT_DRQ) == 0) ||
+ ((c & (ATA_STAT_FAULT | ATA_STAT_ERR)) != 0)) {
+#ifdef CONFIG_ATAPI
+ {
+ /*
+ * Need to soft reset the device
+ * in case it's an ATAPI...
+ */
+ debug("Retrying...\n");
+ ide_outb(device, ATA_DEV_HD,
+ ATA_LBA | ATA_DEVICE(device));
+ udelay(100000);
+ ide_outb(device, ATA_COMMAND, 0x08);
+ udelay(500000); /* 500 ms */
+ }
+ /*
+ * Select device
+ */
+ ide_outb(device, ATA_DEV_HD,
+ ATA_LBA | ATA_DEVICE(device));
+ retries++;
+#else
+ return;
+#endif
+ }
+#ifdef CONFIG_ATAPI
+ else
+ break;
+ } /* see above - ugly to read */
+
+ if (retries == 2) /* Not found */
+ return;
+#endif
+
+ ide_input_swap_data(device, (ulong *)&iop, ATA_SECTORWORDS);
+
+ ident_cpy((unsigned char *)dev_desc->revision, iop.fw_rev,
+ sizeof(dev_desc->revision));
+ ident_cpy((unsigned char *)dev_desc->vendor, iop.model,
+ sizeof(dev_desc->vendor));
+ ident_cpy((unsigned char *)dev_desc->product, iop.serial_no,
+ sizeof(dev_desc->product));
+#ifdef __LITTLE_ENDIAN
+ /*
+ * firmware revision, model, and serial number have Big Endian Byte
+ * order in Word. Convert all three to little endian.
+ *
+ * See CF+ and CompactFlash Specification Revision 2.0:
+ * 6.2.1.6: Identify Drive, Table 39 for more details
+ */
+
+ strswab(dev_desc->revision);
+ strswab(dev_desc->vendor);
+ strswab(dev_desc->product);
+#endif /* __LITTLE_ENDIAN */
+
+ if ((iop.config & 0x0080) == 0x0080)
+ dev_desc->removable = 1;
+ else
+ dev_desc->removable = 0;
+
+#ifdef CONFIG_ATAPI
+ if (dev_desc->if_type == IF_TYPE_ATAPI) {
+ atapi_inquiry(dev_desc);
+ return;
+ }
+#endif /* CONFIG_ATAPI */
+
+#ifdef __BIG_ENDIAN
+ /* swap shorts */
+ dev_desc->lba = (iop.lba_capacity << 16) | (iop.lba_capacity >> 16);
+#else /* ! __BIG_ENDIAN */
+ /*
+ * do not swap shorts on little endian
+ *
+ * See CF+ and CompactFlash Specification Revision 2.0:
+ * 6.2.1.6: Identfy Drive, Table 39, Word Address 57-58 for details.
+ */
+ dev_desc->lba = iop.lba_capacity;
+#endif /* __BIG_ENDIAN */
+
+#ifdef CONFIG_LBA48
+ if (iop.command_set_2 & 0x0400) { /* LBA 48 support */
+ dev_desc->lba48 = 1;
+ dev_desc->lba = (unsigned long long) iop.lba48_capacity[0] |
+ ((unsigned long long) iop.lba48_capacity[1] << 16) |
+ ((unsigned long long) iop.lba48_capacity[2] << 32) |
+ ((unsigned long long) iop.lba48_capacity[3] << 48);
+ } else {
+ dev_desc->lba48 = 0;
+ }
+#endif /* CONFIG_LBA48 */
+ /* assuming HD */
+ dev_desc->type = DEV_TYPE_HARDDISK;
+ dev_desc->blksz = ATA_BLOCKSIZE;
+ dev_desc->log2blksz = LOG2(dev_desc->blksz);
+ dev_desc->lun = 0; /* just to fill something in... */
+
+#if 0 /* only used to test the powersaving mode,
+ * if enabled, the drive goes after 5 sec
+ * in standby mode */
+ ide_outb(device, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(device));
+ c = ide_wait(device, IDE_TIME_OUT);
+ ide_outb(device, ATA_SECT_CNT, 1);
+ ide_outb(device, ATA_LBA_LOW, 0);
+ ide_outb(device, ATA_LBA_MID, 0);
+ ide_outb(device, ATA_LBA_HIGH, 0);
+ ide_outb(device, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(device));
+ ide_outb(device, ATA_COMMAND, 0xe3);
+ udelay(50);
+ c = ide_wait(device, IDE_TIME_OUT); /* can't take over 500 ms */
+#endif
+}
+
+__weak void ide_led(uchar led, uchar status)
+{
+#if defined(CONFIG_IDE_LED) && defined(PER8_BASE) /* required by LED_PORT */
+ static uchar led_buffer; /* Buffer for current LED status */
+
+ uchar *led_port = LED_PORT;
+
+ if (status) /* switch LED on */
+ led_buffer |= led;
+ else /* switch LED off */
+ led_buffer &= ~led;
+
+ *led_port = led_buffer;
+#endif
+}
+
+__weak void ide_outb(int dev, int port, unsigned char val)
+{
+ debug("ide_outb (dev= %d, port= 0x%x, val= 0x%02x) : @ 0x%08lx\n",
+ dev, port, val,
+ (ATA_CURR_BASE(dev) + CONFIG_SYS_ATA_PORT_ADDR(port)));
+
+#if defined(CONFIG_IDE_AHB)
+ if (port) {
+ /* write command */
+ ide_write_register(dev, port, val);
+ } else {
+ /* write data */
+ outb(val, (ATA_CURR_BASE(dev)));
+ }
+#else
+ outb(val, (ATA_CURR_BASE(dev) + CONFIG_SYS_ATA_PORT_ADDR(port)));
+#endif
+}
+
+__weak unsigned char ide_inb(int dev, int port)
+{
+ uchar val;
+
+#if defined(CONFIG_IDE_AHB)
+ val = ide_read_register(dev, port);
+#else
+ val = inb((ATA_CURR_BASE(dev) + CONFIG_SYS_ATA_PORT_ADDR(port)));
+#endif
+
+ debug("ide_inb (dev= %d, port= 0x%x) : @ 0x%08lx -> 0x%02x\n",
+ dev, port,
+ (ATA_CURR_BASE(dev) + CONFIG_SYS_ATA_PORT_ADDR(port)), val);
+ return val;
+}
+
+void ide_init(void)
+{
+ unsigned char c;
+ int i, bus;
+
+#ifdef CONFIG_IDE_8xx_PCCARD
+ extern int ide_devices_found; /* Initialized in check_ide_device() */
+#endif /* CONFIG_IDE_8xx_PCCARD */
+
+#ifdef CONFIG_IDE_PREINIT
+ WATCHDOG_RESET();
+
+ if (ide_preinit()) {
+ puts("ide_preinit failed\n");
+ return;
+ }
+#endif /* CONFIG_IDE_PREINIT */
+
+ WATCHDOG_RESET();
+
+ /*
+ * Reset the IDE just to be sure.
+ * Light LED's to show
+ */
+ ide_led((LED_IDE1 | LED_IDE2), 1); /* LED's on */
+
+ /* ATAPI Drives seems to need a proper IDE Reset */
+ ide_reset();
+
+#ifdef CONFIG_IDE_INIT_POSTRESET
+ WATCHDOG_RESET();
+
+ if (ide_init_postreset()) {
+ puts("ide_preinit_postreset failed\n");
+ return;
+ }
+#endif /* CONFIG_IDE_INIT_POSTRESET */
+
+ /*
+ * Wait for IDE to get ready.
+ * According to spec, this can take up to 31 seconds!
+ */
+ for (bus = 0; bus < CONFIG_SYS_IDE_MAXBUS; ++bus) {
+ int dev =
+ bus * (CONFIG_SYS_IDE_MAXDEVICE /
+ CONFIG_SYS_IDE_MAXBUS);
+
+#ifdef CONFIG_IDE_8xx_PCCARD
+ /* Skip non-ide devices from probing */
+ if ((ide_devices_found & (1 << bus)) == 0) {
+ ide_led((LED_IDE1 | LED_IDE2), 0); /* LED's off */
+ continue;
+ }
+#endif
+ printf("Bus %d: ", bus);
+
+ ide_bus_ok[bus] = 0;
+
+ /* Select device
+ */
+ udelay(100000); /* 100 ms */
+ ide_outb(dev, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(dev));
+ udelay(100000); /* 100 ms */
+ i = 0;
+ do {
+ udelay(10000); /* 10 ms */
+
+ c = ide_inb(dev, ATA_STATUS);
+ i++;
+ if (i > (ATA_RESET_TIME * 100)) {
+ puts("** Timeout **\n");
+ /* LED's off */
+ ide_led((LED_IDE1 | LED_IDE2), 0);
+ return;
+ }
+ if ((i >= 100) && ((i % 100) == 0))
+ putc('.');
+
+ } while (c & ATA_STAT_BUSY);
+
+ if (c & (ATA_STAT_BUSY | ATA_STAT_FAULT)) {
+ puts("not available ");
+ debug("Status = 0x%02X ", c);
+#ifndef CONFIG_ATAPI /* ATAPI Devices do not set DRDY */
+ } else if ((c & ATA_STAT_READY) == 0) {
+ puts("not available ");
+ debug("Status = 0x%02X ", c);
+#endif
+ } else {
+ puts("OK ");
+ ide_bus_ok[bus] = 1;
+ }
+ WATCHDOG_RESET();
+ }
+
+ putc('\n');
+
+ ide_led((LED_IDE1 | LED_IDE2), 0); /* LED's off */
+
+ for (i = 0; i < CONFIG_SYS_IDE_MAXDEVICE; ++i) {
+ int led = (IDE_BUS(i) == 0) ? LED_IDE1 : LED_IDE2;
+ ide_dev_desc[i].type = DEV_TYPE_UNKNOWN;
+ ide_dev_desc[i].if_type = IF_TYPE_IDE;
+ ide_dev_desc[i].devnum = i;
+ ide_dev_desc[i].part_type = PART_TYPE_UNKNOWN;
+ ide_dev_desc[i].blksz = 0;
+ ide_dev_desc[i].log2blksz =
+ LOG2_INVALID(typeof(ide_dev_desc[i].log2blksz));
+ ide_dev_desc[i].lba = 0;
+#ifndef CONFIG_BLK
+ ide_dev_desc[i].block_read = ide_read;
+ ide_dev_desc[i].block_write = ide_write;
+#endif
+ if (!ide_bus_ok[IDE_BUS(i)])
+ continue;
+ ide_led(led, 1); /* LED on */
+ ide_ident(&ide_dev_desc[i]);
+ ide_led(led, 0); /* LED off */
+ dev_print(&ide_dev_desc[i]);
+
+ if ((ide_dev_desc[i].lba > 0) && (ide_dev_desc[i].blksz > 0)) {
+ /* initialize partition type */
+ part_init(&ide_dev_desc[i]);
+ }
+ }
+ WATCHDOG_RESET();
+}
+
+/* We only need to swap data if we are running on a big endian cpu. */
+#if defined(__LITTLE_ENDIAN)
+__weak void ide_input_swap_data(int dev, ulong *sect_buf, int words)
+{
+ ide_input_data(dev, sect_buf, words);
+}
+#else
+__weak void ide_input_swap_data(int dev, ulong *sect_buf, int words)
+{
+ volatile ushort *pbuf =
+ (ushort *)(ATA_CURR_BASE(dev) + ATA_DATA_REG);
+ ushort *dbuf = (ushort *)sect_buf;
+
+ debug("in input swap data base for read is %lx\n",
+ (unsigned long) pbuf);
+
+ while (words--) {
+#ifdef __MIPS__
+ *dbuf++ = swab16p((u16 *)pbuf);
+ *dbuf++ = swab16p((u16 *)pbuf);
+#else
+ *dbuf++ = ld_le16(pbuf);
+ *dbuf++ = ld_le16(pbuf);
+#endif /* !MIPS */
+ }
+}
+#endif /* __LITTLE_ENDIAN */
+
+
+#if defined(CONFIG_IDE_SWAP_IO)
+__weak void ide_output_data(int dev, const ulong *sect_buf, int words)
+{
+ ushort *dbuf;
+ volatile ushort *pbuf;
+
+ pbuf = (ushort *)(ATA_CURR_BASE(dev) + ATA_DATA_REG);
+ dbuf = (ushort *)sect_buf;
+ while (words--) {
+ EIEIO;
+ *pbuf = *dbuf++;
+ EIEIO;
+ *pbuf = *dbuf++;
+ }
+}
+#else /* ! CONFIG_IDE_SWAP_IO */
+__weak void ide_output_data(int dev, const ulong *sect_buf, int words)
+{
+#if defined(CONFIG_IDE_AHB)
+ ide_write_data(dev, sect_buf, words);
+#else
+ outsw(ATA_CURR_BASE(dev) + ATA_DATA_REG, sect_buf, words << 1);
+#endif
+}
+#endif /* CONFIG_IDE_SWAP_IO */
+
+#if defined(CONFIG_IDE_SWAP_IO)
+__weak void ide_input_data(int dev, ulong *sect_buf, int words)
+{
+ ushort *dbuf;
+ volatile ushort *pbuf;
+
+ pbuf = (ushort *)(ATA_CURR_BASE(dev) + ATA_DATA_REG);
+ dbuf = (ushort *)sect_buf;
+
+ debug("in input data base for read is %lx\n", (unsigned long) pbuf);
+
+ while (words--) {
+ EIEIO;
+ *dbuf++ = *pbuf;
+ EIEIO;
+ *dbuf++ = *pbuf;
+ }
+}
+#else /* ! CONFIG_IDE_SWAP_IO */
+__weak void ide_input_data(int dev, ulong *sect_buf, int words)
+{
+#if defined(CONFIG_IDE_AHB)
+ ide_read_data(dev, sect_buf, words);
+#else
+ insw(ATA_CURR_BASE(dev) + ATA_DATA_REG, sect_buf, words << 1);
+#endif
+}
+
+#endif /* CONFIG_IDE_SWAP_IO */
+
+#ifdef CONFIG_BLK
+ulong ide_read(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
+ void *buffer)
+#else
+ulong ide_read(struct blk_desc *block_dev, lbaint_t blknr, lbaint_t blkcnt,
+ void *buffer)
+#endif
+{
+#ifdef CONFIG_BLK
+ struct blk_desc *block_dev = dev_get_uclass_platdata(dev);
+#endif
+ int device = block_dev->devnum;
+ ulong n = 0;
+ unsigned char c;
+ unsigned char pwrsave = 0; /* power save */
+
+#ifdef CONFIG_LBA48
+ unsigned char lba48 = 0;
+
+ if (blknr & 0x0000fffff0000000ULL) {
+ /* more than 28 bits used, use 48bit mode */
+ lba48 = 1;
+ }
+#endif
+ debug("ide_read dev %d start " LBAF ", blocks " LBAF " buffer at %lX\n",
+ device, blknr, blkcnt, (ulong) buffer);
+
+ ide_led(DEVICE_LED(device), 1); /* LED on */
+
+ /* Select device
+ */
+ ide_outb(device, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(device));
+ c = ide_wait(device, IDE_TIME_OUT);
+
+ if (c & ATA_STAT_BUSY) {
+ printf("IDE read: device %d not ready\n", device);
+ goto IDE_READ_E;
+ }
+
+ /* first check if the drive is in Powersaving mode, if yes,
+ * increase the timeout value */
+ ide_outb(device, ATA_COMMAND, ATA_CMD_CHK_PWR);
+ udelay(50);
+
+ c = ide_wait(device, IDE_TIME_OUT); /* can't take over 500 ms */
+
+ if (c & ATA_STAT_BUSY) {
+ printf("IDE read: device %d not ready\n", device);
+ goto IDE_READ_E;
+ }
+ if ((c & ATA_STAT_ERR) == ATA_STAT_ERR) {
+ printf("No Powersaving mode %X\n", c);
+ } else {
+ c = ide_inb(device, ATA_SECT_CNT);
+ debug("Powersaving %02X\n", c);
+ if (c == 0)
+ pwrsave = 1;
+ }
+
+
+ while (blkcnt-- > 0) {
+ c = ide_wait(device, IDE_TIME_OUT);
+
+ if (c & ATA_STAT_BUSY) {
+ printf("IDE read: device %d not ready\n", device);
+ break;
+ }
+#ifdef CONFIG_LBA48
+ if (lba48) {
+ /* write high bits */
+ ide_outb(device, ATA_SECT_CNT, 0);
+ ide_outb(device, ATA_LBA_LOW, (blknr >> 24) & 0xFF);
+#ifdef CONFIG_SYS_64BIT_LBA
+ ide_outb(device, ATA_LBA_MID, (blknr >> 32) & 0xFF);
+ ide_outb(device, ATA_LBA_HIGH, (blknr >> 40) & 0xFF);
+#else
+ ide_outb(device, ATA_LBA_MID, 0);
+ ide_outb(device, ATA_LBA_HIGH, 0);
+#endif
+ }
+#endif
+ ide_outb(device, ATA_SECT_CNT, 1);
+ ide_outb(device, ATA_LBA_LOW, (blknr >> 0) & 0xFF);
+ ide_outb(device, ATA_LBA_MID, (blknr >> 8) & 0xFF);
+ ide_outb(device, ATA_LBA_HIGH, (blknr >> 16) & 0xFF);
+
+#ifdef CONFIG_LBA48
+ if (lba48) {
+ ide_outb(device, ATA_DEV_HD,
+ ATA_LBA | ATA_DEVICE(device));
+ ide_outb(device, ATA_COMMAND, ATA_CMD_READ_EXT);
+
+ } else
+#endif
+ {
+ ide_outb(device, ATA_DEV_HD, ATA_LBA |
+ ATA_DEVICE(device) | ((blknr >> 24) & 0xF));
+ ide_outb(device, ATA_COMMAND, ATA_CMD_READ);
+ }
+
+ udelay(50);
+
+ if (pwrsave) {
+ /* may take up to 4 sec */
+ c = ide_wait(device, IDE_SPIN_UP_TIME_OUT);
+ pwrsave = 0;
+ } else {
+ /* can't take over 500 ms */
+ c = ide_wait(device, IDE_TIME_OUT);
+ }
+
+ if ((c & (ATA_STAT_DRQ | ATA_STAT_BUSY | ATA_STAT_ERR)) !=
+ ATA_STAT_DRQ) {
+ printf("Error (no IRQ) dev %d blk " LBAF
+ ": status %#02x\n", device, blknr, c);
+ break;
+ }
+
+ ide_input_data(device, buffer, ATA_SECTORWORDS);
+ (void) ide_inb(device, ATA_STATUS); /* clear IRQ */
+
+ ++n;
+ ++blknr;
+ buffer += ATA_BLOCKSIZE;
+ }
+IDE_READ_E:
+ ide_led(DEVICE_LED(device), 0); /* LED off */
+ return n;
+}
+
+#ifdef CONFIG_BLK
+ulong ide_write(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
+ const void *buffer)
+#else
+ulong ide_write(struct blk_desc *block_dev, lbaint_t blknr, lbaint_t blkcnt,
+ const void *buffer)
+#endif
+{
+#ifdef CONFIG_BLK
+ struct blk_desc *block_dev = dev_get_uclass_platdata(dev);
+#endif
+ int device = block_dev->devnum;
+ ulong n = 0;
+ unsigned char c;
+
+#ifdef CONFIG_LBA48
+ unsigned char lba48 = 0;
+
+ if (blknr & 0x0000fffff0000000ULL) {
+ /* more than 28 bits used, use 48bit mode */
+ lba48 = 1;
+ }
+#endif
+
+ ide_led(DEVICE_LED(device), 1); /* LED on */
+
+ /* Select device
+ */
+ ide_outb(device, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(device));
+
+ while (blkcnt-- > 0) {
+ c = ide_wait(device, IDE_TIME_OUT);
+
+ if (c & ATA_STAT_BUSY) {
+ printf("IDE read: device %d not ready\n", device);
+ goto WR_OUT;
+ }
+#ifdef CONFIG_LBA48
+ if (lba48) {
+ /* write high bits */
+ ide_outb(device, ATA_SECT_CNT, 0);
+ ide_outb(device, ATA_LBA_LOW, (blknr >> 24) & 0xFF);
+#ifdef CONFIG_SYS_64BIT_LBA
+ ide_outb(device, ATA_LBA_MID, (blknr >> 32) & 0xFF);
+ ide_outb(device, ATA_LBA_HIGH, (blknr >> 40) & 0xFF);
+#else
+ ide_outb(device, ATA_LBA_MID, 0);
+ ide_outb(device, ATA_LBA_HIGH, 0);
+#endif
+ }
+#endif
+ ide_outb(device, ATA_SECT_CNT, 1);
+ ide_outb(device, ATA_LBA_LOW, (blknr >> 0) & 0xFF);
+ ide_outb(device, ATA_LBA_MID, (blknr >> 8) & 0xFF);
+ ide_outb(device, ATA_LBA_HIGH, (blknr >> 16) & 0xFF);
+
+#ifdef CONFIG_LBA48
+ if (lba48) {
+ ide_outb(device, ATA_DEV_HD,
+ ATA_LBA | ATA_DEVICE(device));
+ ide_outb(device, ATA_COMMAND, ATA_CMD_WRITE_EXT);
+
+ } else
+#endif
+ {
+ ide_outb(device, ATA_DEV_HD, ATA_LBA |
+ ATA_DEVICE(device) | ((blknr >> 24) & 0xF));
+ ide_outb(device, ATA_COMMAND, ATA_CMD_WRITE);
+ }
+
+ udelay(50);
+
+ /* can't take over 500 ms */
+ c = ide_wait(device, IDE_TIME_OUT);
+
+ if ((c & (ATA_STAT_DRQ | ATA_STAT_BUSY | ATA_STAT_ERR)) !=
+ ATA_STAT_DRQ) {
+ printf("Error (no IRQ) dev %d blk " LBAF
+ ": status %#02x\n", device, blknr, c);
+ goto WR_OUT;
+ }
+
+ ide_output_data(device, buffer, ATA_SECTORWORDS);
+ c = ide_inb(device, ATA_STATUS); /* clear IRQ */
+ ++n;
+ ++blknr;
+ buffer += ATA_BLOCKSIZE;
+ }
+WR_OUT:
+ ide_led(DEVICE_LED(device), 0); /* LED off */
+ return n;
+}
+
+#if defined(CONFIG_OF_IDE_FIXUP)
+int ide_device_present(int dev)
+{
+ if (dev >= CONFIG_SYS_IDE_MAXBUS)
+ return 0;
+ return ide_dev_desc[dev].type == DEV_TYPE_UNKNOWN ? 0 : 1;
+}
+#endif
+
+#ifdef CONFIG_BLK
+static const struct blk_ops ide_blk_ops = {
+ .read = ide_read,
+ .write = ide_write,
+};
+
+U_BOOT_DRIVER(ide_blk) = {
+ .name = "ide_blk",
+ .id = UCLASS_BLK,
+ .ops = &ide_blk_ops,
+};
+#else
+U_BOOT_LEGACY_BLK(ide) = {
+ .if_typename = "ide",
+ .if_type = IF_TYPE_IDE,
+ .max_devs = CONFIG_SYS_IDE_MAXDEVICE,
+ .desc = ide_dev_desc,
+};
+#endif
}
if ((type == IH_TYPE_KERNEL) || (type == IH_TYPE_STANDALONE) ||
- (type == IH_TYPE_FIRMWARE) || (type == IH_TYPE_RAMDISK)) {
+ (type == IH_TYPE_FIRMWARE) || (type == IH_TYPE_RAMDISK) ||
+ (type == IH_TYPE_FPGA)) {
ret = fit_image_get_load(fit, image_noffset, &load);
printf("%s Load Address: ", p);
if (ret)
ret = fdt_setprop(fit, noffset, FIT_TIMESTAMP_PROP, &t,
sizeof(uint32_t));
if (ret) {
- printf("Can't set '%s' property for '%s' node (%s)\n",
- FIT_TIMESTAMP_PROP, fit_get_name(fit, noffset, NULL),
- fdt_strerror(ret));
+ debug("Can't set '%s' property for '%s' node (%s)\n",
+ FIT_TIMESTAMP_PROP, fit_get_name(fit, noffset, NULL),
+ fdt_strerror(ret));
return ret == -FDT_ERR_NOSPACE ? -ENOSPC : -1;
}
if (uname)
printf("%s FDT: %s\n", p, uname);
+ uname = (char *)fdt_getprop(fit, noffset, FIT_FPGA_PROP, NULL);
+ if (uname)
+ printf("%s FPGA: %s\n", p, uname);
+
/* Print out all of the specified loadables */
for (loadables_index = 0;
fdt_get_string_index(fit, noffset,
return FIT_SETUP_PROP;
case IH_TYPE_LOADABLE:
return FIT_LOADABLE_PROP;
+ case IH_TYPE_FPGA:
+ return FIT_FPGA_PROP;
}
return "unknown";
fit_image_check_type(fit, noffset,
IH_TYPE_KERNEL_NOLOAD));
- os_ok = image_type == IH_TYPE_FLATDT ||
+ os_ok = image_type == IH_TYPE_FLATDT || IH_TYPE_FPGA ||
fit_image_check_os(fit, noffset, IH_OS_LINUX) ||
fit_image_check_os(fit, noffset, IH_OS_OPENRTOS);
#if IMAGE_ENABLE_FIT || IMAGE_ENABLE_OF_LIBFDT
#include <libfdt.h>
#include <fdt_support.h>
+#include <fpga.h>
+#include <xilinx.h>
#endif
#include <u-boot/md5.h>
{ IH_TYPE_RKSD, "rksd", "Rockchip SD Boot Image" },
{ IH_TYPE_RKSPI, "rkspi", "Rockchip SPI Boot Image" },
{ IH_TYPE_ZYNQIMAGE, "zynqimage", "Xilinx Zynq Boot Image" },
+ { IH_TYPE_ZYNQMPIMAGE, "zynqmpimage", "Xilinx ZynqMP Boot Image" },
+ { IH_TYPE_FPGA, "fpga", "FPGA Image" },
{ -1, "", "", },
};
}
#if IMAGE_ENABLE_FIT
+#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_XILINX)
+int boot_get_fpga(int argc, char * const argv[], bootm_headers_t *images,
+ uint8_t arch, const ulong *ld_start, ulong * const ld_len)
+{
+ ulong tmp_img_addr, img_data, img_len;
+ void *buf;
+ int conf_noffset;
+ int fit_img_result;
+ char *uname, *name;
+ int err;
+ int devnum = 0; /* TODO support multi fpga platforms */
+ const fpga_desc * const desc = fpga_get_desc(devnum);
+ xilinx_desc *desc_xilinx = desc->devdesc;
+
+ /* Check to see if the images struct has a FIT configuration */
+ if (!genimg_has_config(images)) {
+ debug("## FIT configuration was not specified\n");
+ return 0;
+ }
+
+ /*
+ * Obtain the os FIT header from the images struct
+ * copy from dataflash if needed
+ */
+ tmp_img_addr = map_to_sysmem(images->fit_hdr_os);
+ tmp_img_addr = genimg_get_image(tmp_img_addr);
+ buf = map_sysmem(tmp_img_addr, 0);
+ /*
+ * Check image type. For FIT images get FIT node
+ * and attempt to locate a generic binary.
+ */
+ switch (genimg_get_format(buf)) {
+ case IMAGE_FORMAT_FIT:
+ conf_noffset = fit_conf_get_node(buf, images->fit_uname_cfg);
+
+ err = fdt_get_string_index(buf, conf_noffset, FIT_FPGA_PROP, 0,
+ (const char **)&uname);
+ if (err < 0) {
+ debug("## FPGA image is not specified\n");
+ return 0;
+ }
+ fit_img_result = fit_image_load(images,
+ tmp_img_addr,
+ (const char **)&uname,
+ &(images->fit_uname_cfg),
+ arch,
+ IH_TYPE_FPGA,
+ BOOTSTAGE_ID_FPGA_INIT,
+ FIT_LOAD_OPTIONAL_NON_ZERO,
+ &img_data, &img_len);
+
+ debug("FPGA image (%s) loaded to 0x%lx/size 0x%lx\n",
+ uname, img_data, img_len);
+
+ if (fit_img_result < 0) {
+ /* Something went wrong! */
+ return fit_img_result;
+ }
+
+ if (img_len >= desc_xilinx->size) {
+ name = "full";
+ err = fpga_loadbitstream(devnum, (char *)img_data,
+ img_len, BIT_FULL);
+ if (err)
+ err = fpga_load(devnum, (const void *)img_data,
+ img_len, BIT_FULL);
+ } else {
+ name = "partial";
+ err = fpga_loadbitstream(devnum, (char *)img_data,
+ img_len, BIT_PARTIAL);
+ if (err)
+ err = fpga_load(devnum, (const void *)img_data,
+ img_len, BIT_PARTIAL);
+ }
+
+ printf(" Programming %s bitstream... ", name);
+ if (err)
+ printf("failed\n");
+ else
+ printf("OK\n");
+ break;
+ default:
+ printf("The given image format is not supported (corrupt?)\n");
+ return 1;
+ }
+
+ return 0;
+}
+#endif
+
int boot_get_loadable(int argc, char * const argv[], bootm_headers_t *images,
uint8_t arch, const ulong *ld_start, ulong * const ld_len)
{
--- /dev/null
+/*
+ * Copyright (C) 2000-2005, DENX Software Engineering
+ * Wolfgang Denk <wd@denx.de>
+ * Copyright (C) Procsys. All rights reserved.
+ * Mushtaq Khan <mushtaq_k@procsys.com>
+ * <mushtaqk_921@yahoo.co.in>
+ * Copyright (C) 2008 Freescale Semiconductor, Inc.
+ * Dave Liu <daveliu@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <sata.h>
+
+struct blk_desc sata_dev_desc[CONFIG_SYS_SATA_MAX_DEVICE];
+
+#ifdef CONFIG_PARTITIONS
+struct blk_desc *sata_get_dev(int dev)
+{
+ return (dev < CONFIG_SYS_SATA_MAX_DEVICE) ? &sata_dev_desc[dev] : NULL;
+}
+#endif
+
+#ifdef CONFIG_BLK
+static unsigned long sata_bread(struct udevice *dev, lbaint_t start,
+ lbaint_t blkcnt, void *dst)
+{
+ return -ENOSYS;
+}
+
+static unsigned long sata_bwrite(struct udevice *dev, lbaint_t start,
+ lbaint_t blkcnt, const void *buffer)
+{
+ return -ENOSYS;
+}
+#else
+static unsigned long sata_bread(struct blk_desc *block_dev, lbaint_t start,
+ lbaint_t blkcnt, void *dst)
+{
+ return sata_read(block_dev->devnum, start, blkcnt, dst);
+}
+
+static unsigned long sata_bwrite(struct blk_desc *block_dev, lbaint_t start,
+ lbaint_t blkcnt, const void *buffer)
+{
+ return sata_write(block_dev->devnum, start, blkcnt, buffer);
+}
+#endif
+
+int __sata_initialize(void)
+{
+ int rc;
+ int i;
+
+ for (i = 0; i < CONFIG_SYS_SATA_MAX_DEVICE; i++) {
+ memset(&sata_dev_desc[i], 0, sizeof(struct blk_desc));
+ sata_dev_desc[i].if_type = IF_TYPE_SATA;
+ sata_dev_desc[i].devnum = i;
+ sata_dev_desc[i].part_type = PART_TYPE_UNKNOWN;
+ sata_dev_desc[i].type = DEV_TYPE_HARDDISK;
+ sata_dev_desc[i].lba = 0;
+ sata_dev_desc[i].blksz = 512;
+ sata_dev_desc[i].log2blksz = LOG2(sata_dev_desc[i].blksz);
+#ifndef CONFIG_BLK
+ sata_dev_desc[i].block_read = sata_bread;
+ sata_dev_desc[i].block_write = sata_bwrite;
+#endif
+ rc = init_sata(i);
+ if (!rc) {
+ rc = scan_sata(i);
+ if (!rc && sata_dev_desc[i].lba > 0 &&
+ sata_dev_desc[i].blksz > 0)
+ part_init(&sata_dev_desc[i]);
+ }
+ }
+
+ return rc;
+}
+int sata_initialize(void) __attribute__((weak, alias("__sata_initialize")));
+
+__weak int __sata_stop(void)
+{
+ int i, err = 0;
+
+ for (i = 0; i < CONFIG_SYS_SATA_MAX_DEVICE; i++)
+ err |= reset_sata(i);
+
+ if (err)
+ printf("Could not reset some SATA devices\n");
+
+ return err;
+}
+int sata_stop(void) __attribute__((weak, alias("__sata_stop")));
+
+#ifdef CONFIG_BLK
+static const struct blk_ops sata_blk_ops = {
+ .read = sata_bread,
+ .write = sata_bwrite,
+};
+
+U_BOOT_DRIVER(sata_blk) = {
+ .name = "sata_blk",
+ .id = UCLASS_BLK,
+ .ops = &sata_blk_ops,
+};
+#else
+U_BOOT_LEGACY_BLK(sata) = {
+ .if_typename = "sata",
+ .if_type = IF_TYPE_SATA,
+ .max_devs = CONFIG_SYS_SATA_MAX_DEVICE,
+ .desc = sata_dev_desc,
+};
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2001
+ * Denis Peter, MPL AG Switzerland
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <inttypes.h>
+#include <pci.h>
+#include <scsi.h>
+
+#ifdef CONFIG_SCSI_DEV_LIST
+#define SCSI_DEV_LIST CONFIG_SCSI_DEV_LIST
+#else
+#ifdef CONFIG_SCSI_SYM53C8XX
+#define SCSI_VEND_ID 0x1000
+#ifndef CONFIG_SCSI_DEV_ID
+#define SCSI_DEV_ID 0x0001
+#else
+#define SCSI_DEV_ID CONFIG_SCSI_DEV_ID
+#endif
+#elif defined CONFIG_SATA_ULI5288
+
+#define SCSI_VEND_ID 0x10b9
+#define SCSI_DEV_ID 0x5288
+
+#elif !defined(CONFIG_SCSI_AHCI_PLAT)
+#error no scsi device defined
+#endif
+#define SCSI_DEV_LIST {SCSI_VEND_ID, SCSI_DEV_ID}
+#endif
+
+#if defined(CONFIG_PCI) && !defined(CONFIG_SCSI_AHCI_PLAT)
+const struct pci_device_id scsi_device_list[] = { SCSI_DEV_LIST };
+#endif
+static ccb tempccb; /* temporary scsi command buffer */
+
+static unsigned char tempbuff[512]; /* temporary data buffer */
+
+static int scsi_max_devs; /* number of highest available scsi device */
+
+static int scsi_curr_dev; /* current device */
+
+static struct blk_desc scsi_dev_desc[CONFIG_SYS_SCSI_MAX_DEVICE];
+
+/* almost the maximum amount of the scsi_ext command.. */
+#define SCSI_MAX_READ_BLK 0xFFFF
+#define SCSI_LBA48_READ 0xFFFFFFF
+
+#ifdef CONFIG_SYS_64BIT_LBA
+void scsi_setup_read16(ccb *pccb, lbaint_t start, unsigned long blocks)
+{
+ pccb->cmd[0] = SCSI_READ16;
+ pccb->cmd[1] = pccb->lun << 5;
+ pccb->cmd[2] = (unsigned char)(start >> 56) & 0xff;
+ pccb->cmd[3] = (unsigned char)(start >> 48) & 0xff;
+ pccb->cmd[4] = (unsigned char)(start >> 40) & 0xff;
+ pccb->cmd[5] = (unsigned char)(start >> 32) & 0xff;
+ pccb->cmd[6] = (unsigned char)(start >> 24) & 0xff;
+ pccb->cmd[7] = (unsigned char)(start >> 16) & 0xff;
+ pccb->cmd[8] = (unsigned char)(start >> 8) & 0xff;
+ pccb->cmd[9] = (unsigned char)start & 0xff;
+ pccb->cmd[10] = 0;
+ pccb->cmd[11] = (unsigned char)(blocks >> 24) & 0xff;
+ pccb->cmd[12] = (unsigned char)(blocks >> 16) & 0xff;
+ pccb->cmd[13] = (unsigned char)(blocks >> 8) & 0xff;
+ pccb->cmd[14] = (unsigned char)blocks & 0xff;
+ pccb->cmd[15] = 0;
+ pccb->cmdlen = 16;
+ pccb->msgout[0] = SCSI_IDENTIFY; /* NOT USED */
+ debug("scsi_setup_read16: cmd: %02X %02X startblk %02X%02X%02X%02X%02X%02X%02X%02X blccnt %02X%02X%02X%02X\n",
+ pccb->cmd[0], pccb->cmd[1],
+ pccb->cmd[2], pccb->cmd[3], pccb->cmd[4], pccb->cmd[5],
+ pccb->cmd[6], pccb->cmd[7], pccb->cmd[8], pccb->cmd[9],
+ pccb->cmd[11], pccb->cmd[12], pccb->cmd[13], pccb->cmd[14]);
+}
+#endif
+
+void scsi_setup_read_ext(ccb *pccb, lbaint_t start, unsigned short blocks)
+{
+ pccb->cmd[0] = SCSI_READ10;
+ pccb->cmd[1] = pccb->lun << 5;
+ pccb->cmd[2] = (unsigned char)(start >> 24) & 0xff;
+ pccb->cmd[3] = (unsigned char)(start >> 16) & 0xff;
+ pccb->cmd[4] = (unsigned char)(start >> 8) & 0xff;
+ pccb->cmd[5] = (unsigned char)start & 0xff;
+ pccb->cmd[6] = 0;
+ pccb->cmd[7] = (unsigned char)(blocks >> 8) & 0xff;
+ pccb->cmd[8] = (unsigned char)blocks & 0xff;
+ pccb->cmd[6] = 0;
+ pccb->cmdlen = 10;
+ pccb->msgout[0] = SCSI_IDENTIFY; /* NOT USED */
+ debug("scsi_setup_read_ext: cmd: %02X %02X startblk %02X%02X%02X%02X blccnt %02X%02X\n",
+ pccb->cmd[0], pccb->cmd[1],
+ pccb->cmd[2], pccb->cmd[3], pccb->cmd[4], pccb->cmd[5],
+ pccb->cmd[7], pccb->cmd[8]);
+}
+
+void scsi_setup_write_ext(ccb *pccb, lbaint_t start, unsigned short blocks)
+{
+ pccb->cmd[0] = SCSI_WRITE10;
+ pccb->cmd[1] = pccb->lun << 5;
+ pccb->cmd[2] = (unsigned char)(start >> 24) & 0xff;
+ pccb->cmd[3] = (unsigned char)(start >> 16) & 0xff;
+ pccb->cmd[4] = (unsigned char)(start >> 8) & 0xff;
+ pccb->cmd[5] = (unsigned char)start & 0xff;
+ pccb->cmd[6] = 0;
+ pccb->cmd[7] = ((unsigned char)(blocks >> 8)) & 0xff;
+ pccb->cmd[8] = (unsigned char)blocks & 0xff;
+ pccb->cmd[9] = 0;
+ pccb->cmdlen = 10;
+ pccb->msgout[0] = SCSI_IDENTIFY; /* NOT USED */
+ debug("%s: cmd: %02X %02X startblk %02X%02X%02X%02X blccnt %02X%02X\n",
+ __func__,
+ pccb->cmd[0], pccb->cmd[1],
+ pccb->cmd[2], pccb->cmd[3], pccb->cmd[4], pccb->cmd[5],
+ pccb->cmd[7], pccb->cmd[8]);
+}
+
+void scsi_setup_read6(ccb *pccb, lbaint_t start, unsigned short blocks)
+{
+ pccb->cmd[0] = SCSI_READ6;
+ pccb->cmd[1] = pccb->lun << 5 | ((unsigned char)(start >> 16) & 0x1f);
+ pccb->cmd[2] = (unsigned char)(start >> 8) & 0xff;
+ pccb->cmd[3] = (unsigned char)start & 0xff;
+ pccb->cmd[4] = (unsigned char)blocks & 0xff;
+ pccb->cmd[5] = 0;
+ pccb->cmdlen = 6;
+ pccb->msgout[0] = SCSI_IDENTIFY; /* NOT USED */
+ debug("scsi_setup_read6: cmd: %02X %02X startblk %02X%02X blccnt %02X\n",
+ pccb->cmd[0], pccb->cmd[1],
+ pccb->cmd[2], pccb->cmd[3], pccb->cmd[4]);
+}
+
+
+void scsi_setup_inquiry(ccb *pccb)
+{
+ pccb->cmd[0] = SCSI_INQUIRY;
+ pccb->cmd[1] = pccb->lun << 5;
+ pccb->cmd[2] = 0;
+ pccb->cmd[3] = 0;
+ if (pccb->datalen > 255)
+ pccb->cmd[4] = 255;
+ else
+ pccb->cmd[4] = (unsigned char)pccb->datalen;
+ pccb->cmd[5] = 0;
+ pccb->cmdlen = 6;
+ pccb->msgout[0] = SCSI_IDENTIFY; /* NOT USED */
+}
+
+#ifdef CONFIG_BLK
+static ulong scsi_read(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
+ void *buffer)
+#else
+static ulong scsi_read(struct blk_desc *block_dev, lbaint_t blknr,
+ lbaint_t blkcnt, void *buffer)
+#endif
+{
+#ifdef CONFIG_BLK
+ struct blk_desc *block_dev = dev_get_uclass_platdata(dev);
+#endif
+ int device = block_dev->devnum;
+ lbaint_t start, blks;
+ uintptr_t buf_addr;
+ unsigned short smallblks = 0;
+ ccb *pccb = (ccb *)&tempccb;
+ device &= 0xff;
+
+ /* Setup device */
+ pccb->target = scsi_dev_desc[device].target;
+ pccb->lun = scsi_dev_desc[device].lun;
+ buf_addr = (unsigned long)buffer;
+ start = blknr;
+ blks = blkcnt;
+ debug("\nscsi_read: dev %d startblk " LBAF
+ ", blccnt " LBAF " buffer %lx\n",
+ device, start, blks, (unsigned long)buffer);
+ do {
+ pccb->pdata = (unsigned char *)buf_addr;
+#ifdef CONFIG_SYS_64BIT_LBA
+ if (start > SCSI_LBA48_READ) {
+ unsigned long blocks;
+ blocks = min_t(lbaint_t, blks, SCSI_MAX_READ_BLK);
+ pccb->datalen = scsi_dev_desc[device].blksz * blocks;
+ scsi_setup_read16(pccb, start, blocks);
+ start += blocks;
+ blks -= blocks;
+ } else
+#endif
+ if (blks > SCSI_MAX_READ_BLK) {
+ pccb->datalen = scsi_dev_desc[device].blksz *
+ SCSI_MAX_READ_BLK;
+ smallblks = SCSI_MAX_READ_BLK;
+ scsi_setup_read_ext(pccb, start, smallblks);
+ start += SCSI_MAX_READ_BLK;
+ blks -= SCSI_MAX_READ_BLK;
+ } else {
+ pccb->datalen = scsi_dev_desc[device].blksz * blks;
+ smallblks = (unsigned short)blks;
+ scsi_setup_read_ext(pccb, start, smallblks);
+ start += blks;
+ blks = 0;
+ }
+ debug("scsi_read_ext: startblk " LBAF
+ ", blccnt %x buffer %" PRIXPTR "\n",
+ start, smallblks, buf_addr);
+ if (scsi_exec(pccb) != true) {
+ scsi_print_error(pccb);
+ blkcnt -= blks;
+ break;
+ }
+ buf_addr += pccb->datalen;
+ } while (blks != 0);
+ debug("scsi_read_ext: end startblk " LBAF
+ ", blccnt %x buffer %" PRIXPTR "\n", start, smallblks, buf_addr);
+ return blkcnt;
+}
+
+/*******************************************************************************
+ * scsi_write
+ */
+
+/* Almost the maximum amount of the scsi_ext command.. */
+#define SCSI_MAX_WRITE_BLK 0xFFFF
+
+#ifdef CONFIG_BLK
+static ulong scsi_write(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
+ const void *buffer)
+#else
+static ulong scsi_write(struct blk_desc *block_dev, lbaint_t blknr,
+ lbaint_t blkcnt, const void *buffer)
+#endif
+{
+#ifdef CONFIG_BLK
+ struct blk_desc *block_dev = dev_get_uclass_platdata(dev);
+#endif
+ int device = block_dev->devnum;
+ lbaint_t start, blks;
+ uintptr_t buf_addr;
+ unsigned short smallblks;
+ ccb *pccb = (ccb *)&tempccb;
+
+ device &= 0xff;
+
+ /* Setup device */
+ pccb->target = scsi_dev_desc[device].target;
+ pccb->lun = scsi_dev_desc[device].lun;
+ buf_addr = (unsigned long)buffer;
+ start = blknr;
+ blks = blkcnt;
+ debug("\n%s: dev %d startblk " LBAF ", blccnt " LBAF " buffer %lx\n",
+ __func__, device, start, blks, (unsigned long)buffer);
+ do {
+ pccb->pdata = (unsigned char *)buf_addr;
+ if (blks > SCSI_MAX_WRITE_BLK) {
+ pccb->datalen = (scsi_dev_desc[device].blksz *
+ SCSI_MAX_WRITE_BLK);
+ smallblks = SCSI_MAX_WRITE_BLK;
+ scsi_setup_write_ext(pccb, start, smallblks);
+ start += SCSI_MAX_WRITE_BLK;
+ blks -= SCSI_MAX_WRITE_BLK;
+ } else {
+ pccb->datalen = scsi_dev_desc[device].blksz * blks;
+ smallblks = (unsigned short)blks;
+ scsi_setup_write_ext(pccb, start, smallblks);
+ start += blks;
+ blks = 0;
+ }
+ debug("%s: startblk " LBAF ", blccnt %x buffer %" PRIXPTR "\n",
+ __func__, start, smallblks, buf_addr);
+ if (scsi_exec(pccb) != true) {
+ scsi_print_error(pccb);
+ blkcnt -= blks;
+ break;
+ }
+ buf_addr += pccb->datalen;
+ } while (blks != 0);
+ debug("%s: end startblk " LBAF ", blccnt %x buffer %" PRIXPTR "\n",
+ __func__, start, smallblks, buf_addr);
+ return blkcnt;
+}
+
+int scsi_get_disk_count(void)
+{
+ return scsi_max_devs;
+}
+
+#if defined(CONFIG_PCI) && !defined(CONFIG_SCSI_AHCI_PLAT)
+void scsi_init(void)
+{
+ int busdevfunc = -1;
+ int i;
+ /*
+ * Find a device from the list, this driver will support a single
+ * controller.
+ */
+ for (i = 0; i < ARRAY_SIZE(scsi_device_list); i++) {
+ /* get PCI Device ID */
+#ifdef CONFIG_DM_PCI
+ struct udevice *dev;
+ int ret;
+
+ ret = dm_pci_find_device(scsi_device_list[i].vendor,
+ scsi_device_list[i].device, 0, &dev);
+ if (!ret) {
+ busdevfunc = dm_pci_get_bdf(dev);
+ break;
+ }
+#else
+ busdevfunc = pci_find_device(scsi_device_list[i].vendor,
+ scsi_device_list[i].device,
+ 0);
+#endif
+ if (busdevfunc != -1)
+ break;
+ }
+
+ if (busdevfunc == -1) {
+ printf("Error: SCSI Controller(s) ");
+ for (i = 0; i < ARRAY_SIZE(scsi_device_list); i++) {
+ printf("%04X:%04X ",
+ scsi_device_list[i].vendor,
+ scsi_device_list[i].device);
+ }
+ printf("not found\n");
+ return;
+ }
+#ifdef DEBUG
+ else {
+ printf("SCSI Controller (%04X,%04X) found (%d:%d:%d)\n",
+ scsi_device_list[i].vendor,
+ scsi_device_list[i].device,
+ (busdevfunc >> 16) & 0xFF,
+ (busdevfunc >> 11) & 0x1F,
+ (busdevfunc >> 8) & 0x7);
+ }
+#endif
+ bootstage_start(BOOTSTAGE_ID_ACCUM_SCSI, "ahci");
+ scsi_low_level_init(busdevfunc);
+ scsi_scan(1);
+ bootstage_accum(BOOTSTAGE_ID_ACCUM_SCSI);
+}
+#endif
+
+/* copy src to dest, skipping leading and trailing blanks
+ * and null terminate the string
+ */
+void scsi_ident_cpy(unsigned char *dest, unsigned char *src, unsigned int len)
+{
+ int start, end;
+
+ start = 0;
+ while (start < len) {
+ if (src[start] != ' ')
+ break;
+ start++;
+ }
+ end = len-1;
+ while (end > start) {
+ if (src[end] != ' ')
+ break;
+ end--;
+ }
+ for (; start <= end; start++)
+ *dest ++= src[start];
+ *dest = '\0';
+}
+
+
+/* Trim trailing blanks, and NUL-terminate string
+ */
+void scsi_trim_trail(unsigned char *str, unsigned int len)
+{
+ unsigned char *p = str + len - 1;
+
+ while (len-- > 0) {
+ *p-- = '\0';
+ if (*p != ' ')
+ return;
+ }
+}
+
+int scsi_read_capacity(ccb *pccb, lbaint_t *capacity, unsigned long *blksz)
+{
+ *capacity = 0;
+
+ memset(pccb->cmd, '\0', sizeof(pccb->cmd));
+ pccb->cmd[0] = SCSI_RD_CAPAC10;
+ pccb->cmd[1] = pccb->lun << 5;
+ pccb->cmdlen = 10;
+ pccb->msgout[0] = SCSI_IDENTIFY; /* NOT USED */
+
+ pccb->datalen = 8;
+ if (scsi_exec(pccb) != true)
+ return 1;
+
+ *capacity = ((lbaint_t)pccb->pdata[0] << 24) |
+ ((lbaint_t)pccb->pdata[1] << 16) |
+ ((lbaint_t)pccb->pdata[2] << 8) |
+ ((lbaint_t)pccb->pdata[3]);
+
+ if (*capacity != 0xffffffff) {
+ /* Read capacity (10) was sufficient for this drive. */
+ *blksz = ((unsigned long)pccb->pdata[4] << 24) |
+ ((unsigned long)pccb->pdata[5] << 16) |
+ ((unsigned long)pccb->pdata[6] << 8) |
+ ((unsigned long)pccb->pdata[7]);
+ return 0;
+ }
+
+ /* Read capacity (10) was insufficient. Use read capacity (16). */
+ memset(pccb->cmd, '\0', sizeof(pccb->cmd));
+ pccb->cmd[0] = SCSI_RD_CAPAC16;
+ pccb->cmd[1] = 0x10;
+ pccb->cmdlen = 16;
+ pccb->msgout[0] = SCSI_IDENTIFY; /* NOT USED */
+
+ pccb->datalen = 16;
+ if (scsi_exec(pccb) != true)
+ return 1;
+
+ *capacity = ((uint64_t)pccb->pdata[0] << 56) |
+ ((uint64_t)pccb->pdata[1] << 48) |
+ ((uint64_t)pccb->pdata[2] << 40) |
+ ((uint64_t)pccb->pdata[3] << 32) |
+ ((uint64_t)pccb->pdata[4] << 24) |
+ ((uint64_t)pccb->pdata[5] << 16) |
+ ((uint64_t)pccb->pdata[6] << 8) |
+ ((uint64_t)pccb->pdata[7]);
+
+ *blksz = ((uint64_t)pccb->pdata[8] << 56) |
+ ((uint64_t)pccb->pdata[9] << 48) |
+ ((uint64_t)pccb->pdata[10] << 40) |
+ ((uint64_t)pccb->pdata[11] << 32) |
+ ((uint64_t)pccb->pdata[12] << 24) |
+ ((uint64_t)pccb->pdata[13] << 16) |
+ ((uint64_t)pccb->pdata[14] << 8) |
+ ((uint64_t)pccb->pdata[15]);
+
+ return 0;
+}
+
+
+/*
+ * Some setup (fill-in) routines
+ */
+void scsi_setup_test_unit_ready(ccb *pccb)
+{
+ pccb->cmd[0] = SCSI_TST_U_RDY;
+ pccb->cmd[1] = pccb->lun << 5;
+ pccb->cmd[2] = 0;
+ pccb->cmd[3] = 0;
+ pccb->cmd[4] = 0;
+ pccb->cmd[5] = 0;
+ pccb->cmdlen = 6;
+ pccb->msgout[0] = SCSI_IDENTIFY; /* NOT USED */
+}
+
+/*
+ * (re)-scan the scsi bus and reports scsi device info
+ * to the user if mode = 1
+ */
+void scsi_scan(int mode)
+{
+ unsigned char i, perq, modi, lun;
+ lbaint_t capacity;
+ unsigned long blksz;
+ ccb *pccb = (ccb *)&tempccb;
+
+ if (mode == 1)
+ printf("scanning bus for devices...\n");
+ for (i = 0; i < CONFIG_SYS_SCSI_MAX_DEVICE; i++) {
+ scsi_dev_desc[i].target = 0xff;
+ scsi_dev_desc[i].lun = 0xff;
+ scsi_dev_desc[i].lba = 0;
+ scsi_dev_desc[i].blksz = 0;
+ scsi_dev_desc[i].log2blksz =
+ LOG2_INVALID(typeof(scsi_dev_desc[i].log2blksz));
+ scsi_dev_desc[i].type = DEV_TYPE_UNKNOWN;
+ scsi_dev_desc[i].vendor[0] = 0;
+ scsi_dev_desc[i].product[0] = 0;
+ scsi_dev_desc[i].revision[0] = 0;
+ scsi_dev_desc[i].removable = false;
+ scsi_dev_desc[i].if_type = IF_TYPE_SCSI;
+ scsi_dev_desc[i].devnum = i;
+ scsi_dev_desc[i].part_type = PART_TYPE_UNKNOWN;
+#ifndef CONFIG_BLK
+ scsi_dev_desc[i].block_read = scsi_read;
+ scsi_dev_desc[i].block_write = scsi_write;
+#endif
+ }
+ scsi_max_devs = 0;
+ for (i = 0; i < CONFIG_SYS_SCSI_MAX_SCSI_ID; i++) {
+ pccb->target = i;
+ for (lun = 0; lun < CONFIG_SYS_SCSI_MAX_LUN; lun++) {
+ pccb->lun = lun;
+ pccb->pdata = (unsigned char *)&tempbuff;
+ pccb->datalen = 512;
+ scsi_setup_inquiry(pccb);
+ if (scsi_exec(pccb) != true) {
+ if (pccb->contr_stat == SCSI_SEL_TIME_OUT) {
+ /*
+ * selection timeout => assuming no
+ * device present
+ */
+ debug("Selection timeout ID %d\n",
+ pccb->target);
+ continue;
+ }
+ scsi_print_error(pccb);
+ continue;
+ }
+ perq = tempbuff[0];
+ modi = tempbuff[1];
+ if ((perq & 0x1f) == 0x1f)
+ continue; /* skip unknown devices */
+ if ((modi & 0x80) == 0x80) /* drive is removable */
+ scsi_dev_desc[scsi_max_devs].removable = true;
+ /* get info for this device */
+ scsi_ident_cpy((unsigned char *)&scsi_dev_desc
+ [scsi_max_devs].vendor[0],
+ &tempbuff[8], 8);
+ scsi_ident_cpy((unsigned char *)&scsi_dev_desc
+ [scsi_max_devs].product[0],
+ &tempbuff[16], 16);
+ scsi_ident_cpy((unsigned char *)&scsi_dev_desc
+ [scsi_max_devs].revision[0],
+ &tempbuff[32], 4);
+ scsi_dev_desc[scsi_max_devs].target = pccb->target;
+ scsi_dev_desc[scsi_max_devs].lun = pccb->lun;
+
+ pccb->datalen = 0;
+ scsi_setup_test_unit_ready(pccb);
+ if (scsi_exec(pccb) != true) {
+ if (scsi_dev_desc[scsi_max_devs].removable) {
+ scsi_dev_desc[scsi_max_devs].type =
+ perq;
+ goto removable;
+ }
+ scsi_print_error(pccb);
+ continue;
+ }
+ if (scsi_read_capacity(pccb, &capacity, &blksz)) {
+ scsi_print_error(pccb);
+ continue;
+ }
+ scsi_dev_desc[scsi_max_devs].lba = capacity;
+ scsi_dev_desc[scsi_max_devs].blksz = blksz;
+ scsi_dev_desc[scsi_max_devs].log2blksz =
+ LOG2(scsi_dev_desc[scsi_max_devs].blksz);
+ scsi_dev_desc[scsi_max_devs].type = perq;
+ part_init(&scsi_dev_desc[scsi_max_devs]);
+removable:
+ if (mode == 1) {
+ printf(" Device %d: ", scsi_max_devs);
+ dev_print(&scsi_dev_desc[scsi_max_devs]);
+ } /* if mode */
+ scsi_max_devs++;
+ } /* next LUN */
+ }
+ if (scsi_max_devs > 0)
+ scsi_curr_dev = 0;
+ else
+ scsi_curr_dev = -1;
+
+ printf("Found %d device(s).\n", scsi_max_devs);
+#ifndef CONFIG_SPL_BUILD
+ setenv_ulong("scsidevs", scsi_max_devs);
+#endif
+}
+
+#ifdef CONFIG_BLK
+static const struct blk_ops scsi_blk_ops = {
+ .read = scsi_read,
+ .write = scsi_write,
+};
+
+U_BOOT_DRIVER(scsi_blk) = {
+ .name = "scsi_blk",
+ .id = UCLASS_BLK,
+ .ops = &scsi_blk_ops,
+};
+#else
+U_BOOT_LEGACY_BLK(scsi) = {
+ .if_typename = "sata",
+ .if_type = IF_TYPE_SCSI,
+ .max_devs = CONFIG_SYS_SCSI_MAX_DEVICE,
+ .desc = scsi_dev_desc,
+};
+#endif
/* Nothing to do! */
}
+__weak void spl_board_prepare_for_boot(void)
+{
+ /* Nothing to do! */
+}
+
void spl_set_header_raw_uboot(void)
{
spl_image.size = CONFIG_SYS_MONITOR_LEN;
spl_image.name = "U-Boot";
}
-void spl_parse_image_header(const struct image_header *header)
+int spl_parse_image_header(const struct image_header *header)
{
u32 header_size = sizeof(struct image_header);
* is bad, and thus should be skipped silently.
*/
panic("** no mkimage signature but raw image not supported");
+#elif defined(CONFIG_SPL_ABORT_ON_RAW_IMAGE)
+ /* Signature not found, proceed to other boot methods. */
+ return -EINVAL;
#else
/* Signature not found - assume u-boot.bin */
debug("mkimage signature not found - ih_magic = %x\n",
spl_set_header_raw_uboot();
#endif
}
+ return 0;
}
__weak void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
image_entry();
}
+#ifndef CONFIG_SPL_LOAD_FIT_ADDRESS
+# define CONFIG_SPL_LOAD_FIT_ADDRESS 0
+#endif
+
#ifdef CONFIG_SPL_RAM_DEVICE
+static ulong spl_ram_load_read(struct spl_load_info *load, ulong sector,
+ ulong count, void *buf)
+{
+ debug("%s: sector %lx, count %lx, buf %lx\n",
+ __func__, sector, count, (ulong)buf);
+ memcpy(buf, (void *)(CONFIG_SPL_LOAD_FIT_ADDRESS + sector), count);
+ return count;
+}
+
static int spl_ram_load_image(void)
{
- const struct image_header *header;
+ struct image_header *header;
- /*
- * Get the header. It will point to an address defined by handoff
- * which will tell where the image located inside the flash. For
- * now, it will temporary fixed to address pointed by U-Boot.
- */
- header = (struct image_header *)
- (CONFIG_SYS_TEXT_BASE - sizeof(struct image_header));
+ header = (struct image_header *)CONFIG_SPL_LOAD_FIT_ADDRESS;
- spl_parse_image_header(header);
+ if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) &&
+ image_get_magic(header) == FDT_MAGIC) {
+ struct spl_load_info load;
+
+ debug("Found FIT\n");
+ load.bl_len = 1;
+ load.read = spl_ram_load_read;
+ spl_load_simple_fit(&load, 0, header);
+ } else {
+ debug("Legacy image\n");
+ /*
+ * Get the header. It will point to an address defined by
+ * handoff which will tell where the image located inside
+ * the flash. For now, it will temporary fixed to address
+ * pointed by U-Boot.
+ */
+ header = (struct image_header *)
+ (CONFIG_SYS_TEXT_BASE - sizeof(struct image_header));
+
+ spl_parse_image_header(header);
+ }
return 0;
}
#endif
debug("loaded - jumping to U-Boot...");
+ spl_board_prepare_for_boot();
jump_to_image_no_args(&spl_image);
}
goto end;
}
- spl_parse_image_header(header);
+ err = spl_parse_image_header(header);
+ if (err < 0) {
+ puts("spl: ext4fs_read failed\n");
+ goto end;
+ }
err = ext4fs_read((char *)spl_image.load_addr, filelen, &actlen);
if (err <= 0)
goto end;
- spl_parse_image_header(header);
+ err = spl_parse_image_header(header);
+ if (err)
+ goto end;
err = file_fat_read(filename, (u8 *)spl_image.load_addr, 0);
node >= 0;
node = fdt_next_subnode(fdt, node)) {
name = fdt_getprop(fdt, node, "description", &len);
- if (!name)
+ if (!name) {
+#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
+ printf("%s: Missing FDT description in DTB\n",
+ __func__);
+#endif
return -EINVAL;
+ }
if (board_fit_config_name_match(name))
continue;
{
u32 image_size_sectors;
unsigned long count;
+ int ret;
+
+ ret = spl_parse_image_header(header);
+ if (ret)
+ return ret;
- spl_parse_image_header(header);
/* convert size to sectors - round up */
image_size_sectors = (spl_image.size + mmc->read_bl_len - 1) /
mmc->read_bl_len;
if (part == 7)
part = 0;
- err = mmc_switch_part(0, part);
+ err = blk_dselect_hwpart(mmc_get_blk_desc(mmc), part);
if (err) {
#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
puts("spl: mmc partition switch failed\n");
if (err)
return err;
- spl_parse_image_header(header);
+ err = spl_parse_image_header(header);
+ if (err)
+ return err;
+
return nand_spl_load_image(offset, spl_image.size,
(void *)(unsigned long)spl_image.load_addr);
}
/* load linux */
nand_spl_load_image(CONFIG_SYS_NAND_SPL_KERNEL_OFFS,
sizeof(*header), (void *)header);
- spl_parse_image_header(header);
+ err = spl_parse_image_header(header);
+ if (err)
+ return err;
if (header->ih_os == IH_OS_LINUX) {
/* happy - was a linux */
err = nand_spl_load_image(
printf("Problem booting with BOOTP\n");
return rv;
}
- spl_parse_image_header((struct image_header *)load_addr);
-
- return 0;
+ return spl_parse_image_header((struct image_header *)load_addr);
}
int spl_nor_load_image(void)
{
+ int ret;
/*
* Loading of the payload to SDRAM is done with skipping of
* the mkimage header in this SPL NOR driver
if (image_get_os(header) == IH_OS_LINUX) {
/* happy - was a Linux */
- spl_parse_image_header(header);
+ ret = spl_parse_image_header(header);
+ if (ret)
+ return ret;
memcpy((void *)spl_image.load_addr,
(void *)(CONFIG_SYS_OS_BASE +
* Load real U-Boot from its location in NOR flash to its
* defined location in SDRAM
*/
- spl_parse_image_header(
+ ret = spl_parse_image_header(
(const struct image_header *)CONFIG_SYS_UBOOT_BASE);
+ if (ret)
+ return ret;
memcpy((void *)(unsigned long)spl_image.load_addr,
(void *)(CONFIG_SYS_UBOOT_BASE + sizeof(struct image_header)),
int spl_onenand_load_image(void)
{
struct image_header *header;
+ int ret;
debug("spl: onenand\n");
/* Load u-boot */
onenand_spl_load_image(CONFIG_SYS_ONENAND_U_BOOT_OFFS,
CONFIG_SYS_ONENAND_PAGE_SIZE, (void *)header);
- spl_parse_image_header(header);
+ ret = spl_parse_image_header(header);
+ if (ret)
+ return ret;
onenand_spl_load_image(CONFIG_SYS_ONENAND_U_BOOT_OFFS,
spl_image.size, (void *)spl_image.load_addr);
} else {
/* try to recognize storage devices immediately */
scsi_scan(0);
- stor_dev = scsi_get_dev(0);
+ stor_dev = blk_get_devnum_by_type(IF_TYPE_SCSI, 0);
if (!stor_dev)
return -ENODEV;
}
#ifdef CONFIG_USB_STORAGE
/* try to recognize storage devices immediately */
usb_stor_curr_dev = usb_stor_scan(1);
- stor_dev = usb_stor_get_dev(usb_stor_curr_dev);
+ stor_dev = blk_get_devnum_by_type(IF_TYPE_USB, usb_stor_curr_dev);
if (!stor_dev)
return -ENODEV;
#endif
if (!ret) {
while ((res =
xyzModem_stream_read(buf, BUF_SIZE, &err)) > 0) {
- if (addr == 0)
- spl_parse_image_header((struct image_header *)buf);
+ if (addr == 0) {
+ ret = spl_parse_image_header((struct image_header *)buf);
+ if (ret)
+ return ret;
+ }
store_addr = addr + spl_image.load_addr;
size += res;
addr += res;
#endif
void uhci_show_temp_int_td(void);
-#ifdef CONFIG_PARTITIONS
-struct blk_desc *usb_stor_get_dev(int index)
-{
-#ifdef CONFIG_BLK
- struct udevice *dev;
- int ret;
-
- ret = blk_get_device(IF_TYPE_USB, index, &dev);
- if (ret)
- return NULL;
- return dev_get_uclass_platdata(dev);
-#else
- return (index < usb_max_devs) ? &usb_dev_desc[index] : NULL;
-#endif
-}
-#endif
-
static void usb_show_progress(void)
{
debug(".");
#ifdef CONFIG_BLK
struct us_data *data;
- char dev_name[30], *str;
int ret;
#else
int start;
for (lun = 0; lun <= max_lun; lun++) {
struct blk_desc *blkdev;
struct udevice *dev;
+ char str[10];
- snprintf(dev_name, sizeof(dev_name), "%s.lun%d",
- udev->dev->name, lun);
- str = strdup(dev_name);
- if (!str)
- return -ENOMEM;
- ret = blk_create_device(udev->dev, "usb_storage_blk", str,
- IF_TYPE_USB, usb_max_devs, 512, 0, &dev);
+ snprintf(str, sizeof(str), "lun%d", lun);
+ ret = blk_create_devicef(udev->dev, "usb_storage_blk", str,
+ IF_TYPE_USB, usb_max_devs, 512, 0,
+ &dev);
if (ret) {
debug("Cannot bind driver\n");
return ret;
.id = UCLASS_BLK,
.ops = &usb_storage_ops,
};
+#else
+U_BOOT_LEGACY_BLK(usb) = {
+ .if_typename = "usb",
+ .if_type = IF_TYPE_USB,
+ .max_devs = USB_MAX_STOR_DEV,
+ .desc = usb_dev_desc,
+};
#endif
CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
CONFIG_G_DNL_VENDOR_NUM=0x0403
CONFIG_G_DNL_PRODUCT_NUM=0xbd00
+CONFIG_DM_ETH=y
CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
CONFIG_G_DNL_VENDOR_NUM=0x0403
CONFIG_G_DNL_PRODUCT_NUM=0xbd00
+CONFIG_DM_ETH=y
--- /dev/null
+CONFIG_MIPS=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_DM_SERIAL=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_ARCH_ATH79=y
+CONFIG_DEFAULT_DEVICE_TREE="ap121"
+CONFIG_SYS_PROMPT="ap121 # "
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_CRC32 is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_DATAFLASH=y
+CONFIG_SPI_FLASH_MTD=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_AR933X_PINCTRL=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_AR933X=y
+CONFIG_DEBUG_UART_BASE=0xb8020000
+CONFIG_DEBUG_UART_CLOCK=25000000
+CONFIG_DEBUG_UART_BOARD_INIT=y
+CONFIG_AR933X_UART=y
+CONFIG_ATH79_SPI=y
+CONFIG_USE_PRIVATE_LIBGCC=y
+CONFIG_OF_LIBFDT=y
--- /dev/null
+CONFIG_MIPS=y
+CONFIG_SYS_MALLOC_F_LEN=0x800
+CONFIG_DM_SERIAL=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_ARCH_ATH79=y
+CONFIG_TARGET_AP143=y
+CONFIG_DEFAULT_DEVICE_TREE="ap143"
+CONFIG_SYS_PROMPT="ap143 # "
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_CRC32 is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_DATAFLASH=y
+CONFIG_SPI_FLASH_MTD=y
+CONFIG_PINCTRL=y
+CONFIG_QCA953X_PINCTRL=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_BASE=0xb8020000
+CONFIG_DEBUG_UART_CLOCK=25000000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_DEBUG_UART_BOARD_INIT=y
+CONFIG_SYS_NS16550=y
+CONFIG_ATH79_SPI=y
+CONFIG_USE_PRIVATE_LIBGCC=y
+CONFIG_OF_LIBFDT=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_CLK=y
+CONFIG_SYS_I2C_DW=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_SYS_NS16550=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_CLK=y
+CONFIG_SYS_I2C_DW=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_SYS_NS16550=y
CONFIG_VGA_BIOS_ADDR=0xfffa0000
CONFIG_GENERATE_PIRQ_TABLE=y
CONFIG_GENERATE_MP_TABLE=y
+CONFIG_GENERATE_ACPI_TABLE=y
+CONFIG_SEABIOS=y
CONFIG_FIT=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
CONFIG_HAVE_VGA_BIOS=y
CONFIG_GENERATE_PIRQ_TABLE=y
CONFIG_GENERATE_MP_TABLE=y
+CONFIG_GENERATE_ACPI_TABLE=y
+CONFIG_SEABIOS=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_BOOTSTAGE=y
CONFIG_GENERATE_PIRQ_TABLE=y
CONFIG_GENERATE_MP_TABLE=y
CONFIG_FIT=y
-CONFIG_BOOTSTAGE=y
-CONFIG_BOOTSTAGE_REPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_CPU=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_NFS is not set
CONFIG_CMD_PING=y
CONFIG_CMD_TIME=y
-CONFIG_CMD_BOOTSTAGE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
CONFIG_G_DNL_VENDOR_NUM=0x0451
CONFIG_G_DNL_PRODUCT_NUM=0xd022
+CONFIG_DM_ETH=y
CONFIG_TARGET_GALILEO=y
CONFIG_ENABLE_MRC_CACHE=y
CONFIG_GENERATE_PIRQ_TABLE=y
+CONFIG_GENERATE_MP_TABLE=y
CONFIG_FIT=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
CONFIG_HUSH_PARSER=y
+CONFIG_CMD_CPU=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
+CONFIG_CPU=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_OF_LIBFDT=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-lpuart"
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_OF_LIBFDT=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,LPUART"
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
CONFIG_SYS_NS16550=y
CONFIG_RSA=y
CONFIG_OF_LIBFDT=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_OF_LIBFDT=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GREPENV=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-lpuart"
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_OF_LIBFDT=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
CONFIG_SYS_EXTRA_OPTIONS="LPUART"
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_OF_LIBFDT=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_ARM=y
CONFIG_TARGET_LS1021AQDS=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
+CONFIG_OF_LIBFDT=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT"
CONFIG_HUSH_PARSER=y
CONFIG_TARGET_LS1021AQDS=y
CONFIG_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
+CONFIG_OF_LIBFDT=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SD_BOOT_QSPI"
CONFIG_HUSH_PARSER=y
CONFIG_SYS_NS16550=y
CONFIG_RSA=y
CONFIG_OF_LIBFDT=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart"
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_OF_LIBFDT=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GREPENV=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-lpuart"
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_OF_LIBFDT=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
CONFIG_SYS_EXTRA_OPTIONS="LPUART"
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart"
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_OF_LIBFDT=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
CONFIG_SPL=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_OF_LIBFDT=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SD_BOOT_QSPI"
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_HAVE_VGA_BIOS=y
CONFIG_GENERATE_PIRQ_TABLE=y
CONFIG_GENERATE_MP_TABLE=y
+CONFIG_GENERATE_ACPI_TABLE=y
+CONFIG_SEABIOS=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_BOOTSTAGE=y
CONFIG_ARCH_MX6=y
CONFIG_TARGET_PICO_IMX6UL=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/technexion/pico-imx6ul/imximage.cfg"
+CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_MEMTEST=y
# CONFIG_CMD_NFS is not set
CONFIG_CMD_PING=y
CONFIG_CMD_TIME=y
+CONFIG_CMD_QFW=y
CONFIG_CMD_BOOTSTAGE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_AT91=y
+CONFIG_TARGET_SAMA5D2_PTC=y
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2,SYS_USE_NANDFLASH"
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+# CONFIG_CMD_FPGA is not set
+CONFIG_SPI_FLASH=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_AT91=y
+CONFIG_TARGET_SAMA5D2_PTC=y
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2,SYS_USE_SERIALFLASH"
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+# CONFIG_CMD_FPGA is not set
+CONFIG_SPI_FLASH=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_ATMEL_USBA=y
CONFIG_OF_LIBFDT=y
+CONFIG_FIT=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_ATMEL_USBA=y
CONFIG_OF_LIBFDT=y
+CONFIG_FIT=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_OF_LIBFDT=y
+CONFIG_FIT=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_OF_LIBFDT=y
+CONFIG_FIT=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_ATMEL_USBA=y
CONFIG_OF_LIBFDT=y
+CONFIG_FIT=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_ATMEL_USBA=y
CONFIG_OF_LIBFDT=y
+CONFIG_FIT=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_ATMEL_USBA=y
CONFIG_OF_LIBFDT=y
+CONFIG_FIT=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_ATMEL_USBA=y
CONFIG_OF_LIBFDT=y
+CONFIG_FIT=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_ATMEL_USBA=y
CONFIG_OF_LIBFDT=y
+CONFIG_FIT=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_ATMEL_USBA=y
CONFIG_OF_LIBFDT=y
+CONFIG_FIT=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_ATMEL_USBA=y
CONFIG_OF_LIBFDT=y
+CONFIG_FIT=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_ATMEL_USBA=y
CONFIG_OF_LIBFDT=y
+CONFIG_FIT=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_ATMEL_USBA=y
CONFIG_OF_LIBFDT=y
+CONFIG_FIT=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_MMC=y
CONFIG_PCI=y
CONFIG_DEFAULT_DEVICE_TREE="sandbox"
CONFIG_I8042_KEYB=y
CONFIG_CMD_TIME=y
CONFIG_CMD_TIMER=y
CONFIG_CMD_SOUND=y
+CONFIG_CMD_QFW=y
CONFIG_CMD_BOOTSTAGE=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
CONFIG_SPL_PWRSEQ=y
CONFIG_RESET=y
CONFIG_DM_MMC=y
+CONFIG_SANDBOX_MMC=y
CONFIG_SPI_FLASH_SANDBOX=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y
--- /dev/null
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_PCI=y
+CONFIG_DEFAULT_DEVICE_TREE="sandbox"
+CONFIG_I8042_KEYB=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_BOOTSTAGE=y
+CONFIG_BOOTSTAGE_REPORT=y
+CONFIG_BOOTSTAGE_USER_COUNT=0x20
+CONFIG_BOOTSTAGE_FDT=y
+CONFIG_BOOTSTAGE_STASH=y
+CONFIG_BOOTSTAGE_STASH_ADDR=0x0
+CONFIG_BOOTSTAGE_STASH_SIZE=0x4096
+CONFIG_CONSOLE_RECORD=y
+CONFIG_CONSOLE_RECORD_OUT_SIZE=0x1000
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_CPU=y
+CONFIG_CMD_LICENSE=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_GREPENV=y
+CONFIG_LOOPW=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MX_CYCLIC=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_DEMO=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_REMOTEPROC=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_TFTPSRV=y
+CONFIG_CMD_RARP=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CDP=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_DNS=y
+CONFIG_CMD_LINK_LOCAL=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_SOUND=y
+CONFIG_CMD_BOOTSTAGE=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_TPM=y
+CONFIG_CMD_TPM_TEST=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_HOSTFILE=y
+CONFIG_NETCONSOLE=y
+CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_SYSCON=y
+CONFIG_DEVRES=y
+CONFIG_DEBUG_DEVRES=y
+CONFIG_ADC=y
+CONFIG_ADC_SANDBOX=y
+CONFIG_CLK=y
+CONFIG_CPU=y
+CONFIG_DM_DEMO=y
+CONFIG_DM_DEMO_SIMPLE=y
+CONFIG_DM_DEMO_SHAPE=y
+CONFIG_PM8916_GPIO=y
+CONFIG_SANDBOX_GPIO=y
+CONFIG_DM_I2C_COMPAT=y
+CONFIG_I2C_CROS_EC_TUNNEL=y
+CONFIG_I2C_CROS_EC_LDO=y
+CONFIG_DM_I2C_GPIO=y
+CONFIG_SYS_I2C_SANDBOX=y
+CONFIG_I2C_MUX=y
+CONFIG_SPL_I2C_MUX=y
+CONFIG_I2C_ARB_GPIO_CHALLENGE=y
+CONFIG_CROS_EC_KEYB=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_CMD_CROS_EC=y
+CONFIG_CROS_EC=y
+CONFIG_CROS_EC_I2C=y
+CONFIG_CROS_EC_LPC=y
+CONFIG_CROS_EC_SANDBOX=y
+CONFIG_CROS_EC_SPI=y
+CONFIG_PWRSEQ=y
+CONFIG_SPL_PWRSEQ=y
+CONFIG_RESET=y
+CONFIG_DM_MMC=y
+CONFIG_SPI_FLASH_SANDBOX=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_DM_ETH=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCI_SANDBOX=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_ROCKCHIP_PINCTRL=y
+CONFIG_ROCKCHIP_3036_PINCTRL=y
+CONFIG_PINCTRL_SANDBOX=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_ACT8846=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_PMIC_MAX77686=y
+CONFIG_PMIC_PM8916=y
+CONFIG_PMIC_RK808=y
+CONFIG_PMIC_S2MPS11=y
+CONFIG_DM_PMIC_SANDBOX=y
+CONFIG_PMIC_S5M8767=y
+CONFIG_PMIC_TPS65090=y
+CONFIG_DM_REGULATOR=y
+CONFIG_REGULATOR_ACT8846=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_MAX77686=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_REGULATOR_RK808=y
+CONFIG_REGULATOR_S5M8767=y
+CONFIG_DM_REGULATOR_SANDBOX=y
+CONFIG_REGULATOR_TPS65090=y
+CONFIG_RAM=y
+CONFIG_REMOTEPROC_SANDBOX=y
+CONFIG_DM_RTC=y
+CONFIG_SANDBOX_SERIAL=y
+CONFIG_SOUND=y
+CONFIG_SOUND_SANDBOX=y
+CONFIG_SANDBOX_SPI=y
+CONFIG_SPMI=y
+CONFIG_SPMI_SANDBOX=y
+CONFIG_TIMER=y
+CONFIG_TIMER_EARLY=y
+CONFIG_SANDBOX_TIMER=y
+CONFIG_TPM_TIS_SANDBOX=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EMUL=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_SYS_USB_EVENT_POLL=y
+CONFIG_DM_VIDEO=y
+CONFIG_CONSOLE_ROTATION=y
+CONFIG_CONSOLE_TRUETYPE=y
+CONFIG_CONSOLE_TRUETYPE_CANTORAONE=y
+CONFIG_VIDEO_SANDBOX_SDL=y
+CONFIG_CMD_DHRYSTONE=y
+CONFIG_TPM=y
+CONFIG_LZ4=y
+CONFIG_ERRNO_STR=y
+CONFIG_UNIT_TEST=y
+CONFIG_UT_TIME=y
+CONFIG_UT_DM=y
+CONFIG_UT_ENV=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DWAPB_GPIO=y
+CONFIG_SYS_I2C_DW=y
CONFIG_DM_MMC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DWAPB_GPIO=y
+CONFIG_SYS_I2C_DW=y
CONFIG_DM_MMC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_DWAPB_GPIO=y
+CONFIG_SYS_I2C_DW=y
CONFIG_DM_MMC=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_DWAPB_GPIO=y
+CONFIG_SYS_I2C_DW=y
CONFIG_DM_MMC=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DWAPB_GPIO=y
+CONFIG_SYS_I2C_DW=y
CONFIG_DM_MMC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DWAPB_GPIO=y
+CONFIG_SYS_I2C_DW=y
CONFIG_DM_MMC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DWAPB_GPIO=y
+CONFIG_SYS_I2C_DW=y
CONFIG_DM_MMC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_SYS_I2C_DW=y
CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_SYS_I2C_DW=y
CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_SYS_I2C_DW=y
CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_SYS_I2C_DW=y
CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_SYS_I2C_DW=y
CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_SYS_I2C_DW=y
CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_SYS_I2C_DW=y
CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_SYS_I2C_DW=y
CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_SYS_I2C_DW=y
CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_SYS_I2C_DW=y
CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_SYS_I2C_DW=y
CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_SYS_I2C_DW=y
CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_SYS_I2C_DW=y
CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_SYS_I2C_DW=y
CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_SYS_I2C_DW=y
CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_SYS_I2C_DW=y
CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_SYS_I2C_DW=y
CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_SYS_I2C_DW=y
CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_SYS_I2C_DW=y
CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_SYS_I2C_DW=y
CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
--- /dev/null
+CONFIG_MIPS=y
+CONFIG_ARCH_ATH79=y
+CONFIG_BOARD_TPLINK_WDR4300=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SYS_NS16550=y
+CONFIG_DM_SERIAL=y
+CONFIG_DEFAULT_DEVICE_TREE="tplink_wdr4300"
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_CMD_NET=y
+CONFIG_CMD_NFS=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM_ETH=y
+CONFIG_AG7XXX=y
+CONFIG_CLK=y
+CONFIG_CMD_USB=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_STORAGE=y
+CONFIG_ATH79_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_DATAFLASH=y
+CONFIG_SPI_FLASH_MTD=y
+CONFIG_PINCTRL=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_SYS_I2C_DW=y
CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_USE_TINY_PRINTF=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_EMBED=y
CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
CONFIG_SYS_I2C_CADENCE=y
CONFIG_DM_MMC=y
CONFIG_ZYNQ_SDHCI=y
CONFIG_NAND_ARASAN=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
CONFIG_DM_ETH=y
CONFIG_ZYNQ_GEM=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_ZYNQ=y
+CONFIG_DEBUG_UART_BASE=0xff000000
+CONFIG_DEBUG_UART_CLOCK=25000000
+CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_USB=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GADGET=y
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm015-dc1"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
+CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="ZynqMP> "
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_EMBED=y
CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
CONFIG_SYS_I2C_CADENCE=y
CONFIG_DM_MMC=y
CONFIG_ZYNQ_SDHCI=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DM_ETH=y
CONFIG_ZYNQ_GEM=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_ZYNQ=y
+CONFIG_DEBUG_UART_BASE=0xff000000
+CONFIG_DEBUG_UART_CLOCK=100000000
+CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_USB=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GADGET=y
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm016-dc2"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
+CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="ZynqMP> "
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_EMBED=y
CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
CONFIG_SYS_I2C_CADENCE=y
CONFIG_DM_MMC=y
CONFIG_NAND_ARASAN=y
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm019-dc5"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
+CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="ZynqMP> "
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_EMBED=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
CONFIG_SYS_I2C_CADENCE=y
CONFIG_DM_MMC=y
CONFIG_ZYNQ_SDHCI=y
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu102"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
+CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="ZynqMP> "
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_EMBED=y
CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
CONFIG_DM_MMC=y
CONFIG_ZYNQ_SDHCI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DM_ETH=y
CONFIG_ZYNQ_GEM=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_ZYNQ=y
+CONFIG_DEBUG_UART_BASE=0xff000000
+CONFIG_DEBUG_UART_CLOCK=100000000
+CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_USB=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GADGET=y
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu102-revB"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
+CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="ZynqMP> "
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_EMBED=y
CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
CONFIG_DM_MMC=y
CONFIG_ZYNQ_SDHCI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DM_ETH=y
CONFIG_ZYNQ_GEM=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_ZYNQ=y
+CONFIG_DEBUG_UART_BASE=0xff000000
+CONFIG_DEBUG_UART_CLOCK=100000000
+CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_USB=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GADGET=y
CONFIG_ARM=y
+CONFIG_SYS_CONFIG_NAME="zynq_microzed"
CONFIG_ARCH_ZYNQ=y
-CONFIG_TARGET_ZYNQ_MICROZED=y
CONFIG_DEFAULT_DEVICE_TREE="zynq-microzed"
CONFIG_SPL=y
CONFIG_FIT=y
CONFIG_ARM=y
+CONFIG_SYS_CONFIG_NAME="zynq_picozed"
CONFIG_ARCH_ZYNQ=y
-CONFIG_TARGET_ZYNQ_PICOZED=y
CONFIG_DEFAULT_DEVICE_TREE="zynq-picozed"
CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_ARM=y
+CONFIG_SYS_CONFIG_NAME="zynq_zc70x"
CONFIG_ARCH_ZYNQ=y
CONFIG_DEFAULT_DEVICE_TREE="zynq-zc702"
CONFIG_SPL=y
CONFIG_ARM=y
+CONFIG_SYS_CONFIG_NAME="zynq_zc70x"
CONFIG_ARCH_ZYNQ=y
-CONFIG_TARGET_ZYNQ_ZC706=y
CONFIG_DEFAULT_DEVICE_TREE="zynq-zc706"
CONFIG_SPL=y
CONFIG_FIT=y
CONFIG_ARM=y
+CONFIG_SYS_CONFIG_NAME="zynq_zc770"
CONFIG_ARCH_ZYNQ=y
-CONFIG_TARGET_ZYNQ_ZC770=y
CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm010"
CONFIG_SPL=y
CONFIG_FIT=y
CONFIG_ARM=y
+CONFIG_SYS_CONFIG_NAME="zynq_zc770"
CONFIG_ARCH_ZYNQ=y
-CONFIG_TARGET_ZYNQ_ZC770=y
CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm011"
CONFIG_SPL=y
CONFIG_FIT=y
CONFIG_ARM=y
+CONFIG_SYS_CONFIG_NAME="zynq_zc770"
CONFIG_ARCH_ZYNQ=y
-CONFIG_TARGET_ZYNQ_ZC770=y
CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm012"
CONFIG_SPL=y
CONFIG_FIT=y
CONFIG_ARM=y
+CONFIG_SYS_CONFIG_NAME="zynq_zc770"
CONFIG_ARCH_ZYNQ=y
-CONFIG_TARGET_ZYNQ_ZC770=y
CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm013"
CONFIG_SPL=y
CONFIG_FIT=y
CONFIG_ARM=y
+CONFIG_SYS_CONFIG_NAME="zynq_zed"
CONFIG_ARCH_ZYNQ=y
-CONFIG_TARGET_ZYNQ_ZED=y
CONFIG_DEFAULT_DEVICE_TREE="zynq-zed"
CONFIG_SPL=y
CONFIG_FIT=y
CONFIG_ARM=y
+CONFIG_SYS_CONFIG_NAME="zynq_zybo"
CONFIG_ARCH_ZYNQ=y
-CONFIG_TARGET_ZYNQ_ZYBO=y
CONFIG_DEFAULT_DEVICE_TREE="zynq-zybo"
CONFIG_SPL=y
CONFIG_FIT=y
#define PRINTF(fmt,args...)
#endif
-const struct block_drvr block_drvr[] = {
-#if defined(CONFIG_CMD_IDE)
- { .name = "ide", .get_dev = ide_get_dev, },
-#endif
-#if defined(CONFIG_CMD_SATA)
- {.name = "sata", .get_dev = sata_get_dev, },
-#endif
-#if defined(CONFIG_CMD_SCSI)
- { .name = "scsi", .get_dev = scsi_get_dev, },
-#endif
-#if defined(CONFIG_CMD_USB) && defined(CONFIG_USB_STORAGE)
- { .name = "usb", .get_dev = usb_stor_get_dev, },
-#endif
-#if defined(CONFIG_MMC)
- {
- .name = "mmc",
- .get_dev = mmc_get_dev,
- .select_hwpart = mmc_select_hwpart,
- },
-#endif
-#if defined(CONFIG_SYSTEMACE)
- { .name = "ace", .get_dev = systemace_get_dev, },
-#endif
-#if defined(CONFIG_SANDBOX)
- { .name = "host", .get_dev = host_get_dev, },
-#endif
- { },
-};
-
DECLARE_GLOBAL_DATA_PTR;
#ifdef HAVE_BLOCK_DEVICE
static struct blk_desc *get_dev_hwpart(const char *ifname, int dev, int hwpart)
{
- const struct block_drvr *drvr = block_drvr;
- struct blk_desc* (*reloc_get_dev)(int dev);
- int (*select_hwpart)(int dev_num, int hwpart);
- char *name;
+ struct blk_desc *dev_desc;
int ret;
- if (!ifname)
+ dev_desc = blk_get_devnum_by_typename(ifname, dev);
+ if (!dev_desc) {
+ debug("%s: No device for iface '%s', dev %d\n", __func__,
+ ifname, dev);
return NULL;
-
- name = drvr->name;
-#ifdef CONFIG_NEEDS_MANUAL_RELOC
- name += gd->reloc_off;
-#endif
- while (drvr->name) {
- name = drvr->name;
- reloc_get_dev = drvr->get_dev;
- select_hwpart = drvr->select_hwpart;
-#ifdef CONFIG_NEEDS_MANUAL_RELOC
- name += gd->reloc_off;
- reloc_get_dev += gd->reloc_off;
- if (select_hwpart)
- select_hwpart += gd->reloc_off;
-#endif
- if (strncmp(ifname, name, strlen(name)) == 0) {
- struct blk_desc *dev_desc = reloc_get_dev(dev);
- if (!dev_desc)
- return NULL;
- if (hwpart == 0 && !select_hwpart)
- return dev_desc;
- if (!select_hwpart)
- return NULL;
- ret = select_hwpart(dev_desc->devnum, hwpart);
- if (ret < 0)
- return NULL;
- return dev_desc;
- }
- drvr++;
}
- return NULL;
+ ret = blk_dselect_hwpart(dev_desc, hwpart);
+ if (ret) {
+ debug("%s: Failed to select h/w partition: err-%d\n", __func__,
+ ret);
+ return NULL;
+ }
+
+ return dev_desc;
}
struct blk_desc *blk_get_dev(const char *ifname, int dev)
if (*ep) {
printf("** Bad device specification %s %s **\n",
ifname, dev_str);
- dev = -1;
+ dev = -EINVAL;
goto cleanup;
}
if (*ep) {
printf("** Bad HW partition specification %s %s **\n",
ifname, hwpart_str);
- dev = -1;
+ dev = -EINVAL;
goto cleanup;
}
}
*dev_desc = get_dev_hwpart(ifname, dev, hwpart);
if (!(*dev_desc) || ((*dev_desc)->type == DEV_TYPE_UNKNOWN)) {
printf("** Bad device %s %s **\n", ifname, dev_hwpart_str);
- dev = -1;
+ dev = -ENOENT;
goto cleanup;
}
'bare metal', U-Boot acts like a BIOS replacement. The following platforms
are supported:
- - Bayley Bay
+ - Bayley Bay CRB
+ - Congatec QEVAL 2.0 & conga-QA3/E3845
- Cougar Canyon 2 CRB
- Crown Bay CRB
- Galileo
000000 descriptor.bin Hard-coded to 0 in ifdtool
001000 me.bin Set by the descriptor
500000 <spare>
+6ef000 Environment CONFIG_ENV_OFFSET
6f0000 MRC cache CONFIG_ENABLE_MRC_CACHE
700000 u-boot-dtb.bin CONFIG_SYS_TEXT_BASE
790000 vga.bin CONFIG_VGA_BIOS_ADDR
7c0000 fsp.bin CONFIG_FSP_ADDR
7f8000 <spare> (depends on size of fsp.bin)
-7fe000 Environment CONFIG_ENV_OFFSET
7ff800 U-Boot 16-bit boot CONFIG_SYS_X86_START16
Overall ROM image size is controlled by CONFIG_ROM_SIZE.
Multicore is also supported by QEMU via '-smp n' where n is the number of cores
to instantiate. Note, the maximum supported CPU number in QEMU is 255.
-The fw_cfg interface in QEMU also provides information about kernel data, initrd,
-command-line arguments and more. U-Boot supports directly accessing these informtion
-from fw_cfg interface, this saves the time of loading them from hard disk or
-network again, through emulated devices. To use it , simply providing them in
-QEMU command line:
+The fw_cfg interface in QEMU also provides information about kernel data,
+initrd, command-line arguments and more. U-Boot supports directly accessing
+these informtion from fw_cfg interface, which saves the time of loading them
+from hard disk or network again, through emulated devices. To use it , simply
+providing them in QEMU command line:
$ qemu-system-i386 -nographic -bios path/to/u-boot.rom -m 1024 -kernel /path/to/bzImage
-append 'root=/dev/ram console=ttyS0' -initrd /path/to/initrd -smp 8
Note: -initrd and -smp are both optional
-Then start QEMU, in U-Boot command line use the following U-Boot command to setup kernel:
+Then start QEMU, in U-Boot command line use the following U-Boot command to
+setup kernel:
=> qfw
qfw - QEMU firmware interface
=> qfw load
loading kernel to address 01000000 size 5d9d30 initrd 04000000 size 1b1ab50
-Here the kernel (bzImage) is loaded to 01000000 and initrd is to 04000000. Then, 'zboot'
-can be used to boot the kernel:
+Here the kernel (bzImage) is loaded to 01000000 and initrd is to 04000000. Then,
+'zboot' can be used to boot the kernel:
=> zboot 02000000 - 04000000 1b1ab50
--------------
As an example of how to set up your boot flow with U-Boot, here are
instructions for starting Ubuntu from U-Boot. These instructions have been
-tested on Minnowboard MAX with a SATA driver but are equally applicable on
-other platforms and other media. There are really only four steps and its a
+tested on Minnowboard MAX with a SATA drive but are equally applicable on
+other platforms and other media. There are really only four steps and it's a
very simple script, but a more detailed explanation is provided here for
completeness.
It could also use the grub.cfg file (/efi/ubuntu/grub.cfg) to obtain the
GUID. If you figure these out, please post patches to this README.
-Firstly, you will need Ubunutu installed on an available disk. It should be
+Firstly, you will need Ubuntu installed on an available disk. It should be
possible to make U-Boot start a USB start-up disk but for now let's assume
that you used another boot loader to install Ubuntu.
Loading bzImage at address 100000 (5805728 bytes)
Magic signature found
Initial RAM disk at linear address 0x04000000, size 19215259 bytes
- Kernel command line: "console=ttyS0,115200 root=/dev/disk/by-partuuid/965c59ee-1822-4326-90d2-b02446050059 ro"
+ Kernel command line: "root=/dev/disk/by-partuuid/965c59ee-1822-4326-90d2-b02446050059 ro"
Starting kernel ...
240,329 ahci
1,422,704 vesa display
-Now the kernel actually starts:
+Now the kernel actually starts: (if you want to examine kernel boot up message
+on the serial console, append "console=ttyS0,115200" to the kernel command line)
[ 0.000000] Initializing cgroup subsys cpuset
[ 0.000000] Initializing cgroup subsys cpu
[ 0.000000] Initializing cgroup subsys cpuacct
[ 0.000000] Linux version 3.13.0-58-generic (buildd@allspice) (gcc version 4.8.2 (Ubuntu 4.8.2-19ubuntu1) ) #97-Ubuntu SMP Wed Jul 8 02:56:15 UTC 2015 (Ubuntu 3.13.0-58.97-generic 3.13.11-ckt22)
- [ 0.000000] Command line: console=ttyS0,115200 root=/dev/disk/by-partuuid/965c59ee-1822-4326-90d2-b02446050059 ro
+ [ 0.000000] Command line: root=/dev/disk/by-partuuid/965c59ee-1822-4326-90d2-b02446050059 ro console=ttyS0,115200
It continues for a long time. Along the way you will see it pick up your
ramdisk:
The \ is to tell the shell not to evaluate ${filesize} as part of the setenv
command.
-You will also need to add this to your board configuration file, e.g.
-include/configs/minnowmax.h:
-
- #define CONFIG_BOOTDELAY 2
-
-Now when you reset your board it wait a few seconds (in case you want to
-interrupt) and then should boot straight into Ubuntu.
-
You can also bake this behaviour into your build by hard-coding the
environment variables if you add this to minnowmax.h:
This is also tested on Intel Crown Bay board with a PCIe graphics card, booting
SeaBIOS then chain-loading a GRUB on a USB drive, then Linux kernel finally.
+If you are using Intel Integrated Graphics Device (IGD) as the primary display
+device on your board, SeaBIOS needs to be patched manually to get its VGA ROM
+loaded and run by SeaBIOS. SeaBIOS locates VGA ROM via the PCI expansion ROM
+register, but IGD device does not have its VGA ROM mapped by this register.
+Its VGA ROM is packaged as part of u-boot.rom at a configurable flash address
+which is unknown to SeaBIOS. An example patch is needed for SeaBIOS below:
+
+diff --git a/src/optionroms.c b/src/optionroms.c
+index 65f7fe0..c7b6f5e 100644
+--- a/src/optionroms.c
++++ b/src/optionroms.c
+@@ -324,6 +324,8 @@ init_pcirom(struct pci_device *pci, int isvga, u64 *sources)
+ rom = deploy_romfile(file);
+ else if (RunPCIroms > 1 || (RunPCIroms == 1 && isvga))
+ rom = map_pcirom(pci);
++ if (pci->bdf == pci_to_bdf(0, 2, 0))
++ rom = (struct rom_header *)0xfff90000;
+ if (! rom)
+ // No ROM present.
+ return;
+
+Note: the patch above expects IGD device is at PCI b.d.f 0.2.0 and its VGA ROM
+is at 0xfff90000 which corresponds to CONFIG_VGA_BIOS_ADDR on Minnowboard MAX.
+Change these two accordingly if this is not the case on your board.
Development Flow
----------------
to U-Boot. This should go at the top of each file and list the coreboot
filename where the code originated.
+Debugging ACPI issues with Windows:
+
+Windows might cache system information and only detect ACPI changes if you
+modify the ACPI table versions. So tweak them liberally when debugging ACPI
+issues with Windows.
+
+ACPI Support Status
+-------------------
+Advanced Configuration and Power Interface (ACPI) [16] aims to establish
+industry-standard interfaces enabling OS-directed configuration, power
+management, and thermal management of mobile, desktop, and server platforms.
+
+Linux can boot without ACPI with "acpi=off" command line parameter, but
+with ACPI the kernel gains the capabilities to handle power management.
+For Windows, ACPI is a must-have firmware feature since Windows Vista.
+CONFIG_GENERATE_ACPI_TABLE is the config option to turn on ACPI support in
+U-Boot. This requires Intel ACPI compiler to be installed on your host to
+compile ACPI DSDT table written in ASL format to AML format. You can get
+the compiler via "apt-get install iasl" if you are on Ubuntu or download
+the source from [17] to compile one by yourself.
+
+Current ACPI support in U-Boot is not complete. More features will be added
+in the future. The status as of today is:
+
+ * Support generating RSDT, XSDT, FACS, FADT, MADT, MCFG tables.
+ * Support one static DSDT table only, compiled by Intel ACPI compiler.
+ * Support S0/S5, reboot and shutdown from OS.
+ * Support booting a pre-installed Ubuntu distribution via 'zboot' command.
+ * Support installing and booting Ubuntu 14.04 (or above) from U-Boot with
+ the help of SeaBIOS using legacy interface (non-UEFI mode).
+ * Support installing and booting Windows 8.1/10 from U-Boot with the help
+ of SeaBIOS using legacy interface (non-UEFI mode).
+ * Support ACPI interrupts with SCI only.
+
+Features not supported so far (to make it a complete ACPI solution):
+ * S3 (Suspend to RAM), S4 (Suspend to Disk).
+
+Features that are optional:
+ * ACPI global NVS support. We may need it to simplify ASL code logic if
+ utilizing NVS variables. Most likely we will need this sooner or later.
+ * Dynamic AML bytecodes insertion at run-time. We may need this to support
+ SSDT table generation and DSDT fix up.
+ * SMI support. Since U-Boot is a modern bootloader, we don't want to bring
+ those legacy stuff into U-Boot. ACPI spec allows a system that does not
+ support SMI (a legacy-free system).
+
+So far ACPI is enabled on BayTrail based boards. Testing was done by booting
+a pre-installed Ubuntu 14.04 from a SATA drive. Installing Ubuntu 14.04 and
+Windows 8.1/10 to a SATA drive and booting from there is also tested. Most
+devices seem to work correctly and the board can respond a reboot/shutdown
+command from the OS.
TODO List
---------
- Audio
- Chrome OS verified boot
-- SMI and ACPI support, to provide platform info and facilities to Linux
References
----------
[13] http://events.linuxfoundation.org/sites/events/files/slides/elce-2014.pdf
[14] http://www.seabios.org/SeaBIOS
[15] doc/device-tree-bindings/misc/intel,irq-router.txt
+[16] http://www.acpi.info
+[17] https://www.acpica.org/downloads
"ibase": IRQ routing is in the memory-mapped IBASE register block
- intel,ibase-offset : IBASE register offset in the interrupt router's PCI
configuration space, required only if intel,pirq-config = "ibase".
+- intel,actl-8bit : If ACTL (ACPI control) register width is 8-bit, this must
+ be specified. The 8-bit ACTL register is seen on ICH series chipset, like
+ ICH9/Panther Point/etc. On Atom chipset it is a 32-bit register.
+- intel,actl-addr : ACTL (ACPI control) register offset. ACTL can be either
+ in the interrupt router's PCI configuration space, or IBASE.
- intel,pirq-link : Specifies the PIRQ link information with two cells. The
first cell is the register offset that controls the first PIRQ link routing.
The second cell is the total number of PIRQ links the router supports.
--- /dev/null
+* Texas Instruments - dp83867 Giga bit ethernet phy
+
+Required properties:
+ - reg - The ID number for the phy, usually a small integer
+ - ti,rx-internal-delay - RGMII Recieve Clock Delay - see dt-bindings/net/ti-dp83867.h
+ for applicable values
+ - ti,tx-internal-delay - RGMII Transmit Clock Delay - see dt-bindings/net/ti-dp83867.h
+ for applicable values
+ - ti,fifo-depth - Transmitt FIFO depth- see dt-bindings/net/ti-dp83867.h
+ for applicable values
+
+Default child nodes are standard Ethernet PHY device
+nodes as described in doc/devicetree/bindings/net/ethernet.txt
+
+Example:
+
+ ethernet-phy@0 {
+ reg = <0>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
+ ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+ };
+
+Datasheet can be found:
+http://www.ti.com/product/DP83867IR/datasheet
--- /dev/null
+* Qualcomm Atheros AR9330 High-Speed UART
+
+Required properties:
+
+- compatible: Must be "qca,ar9330-uart"
+
+- reg: Specifies the physical base address of the controller and
+ the length of the memory mapped region.
+
+Additional requirements:
+
+ Each UART port must have an alias correctly numbered in "aliases"
+ node.
+
+Example:
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ uart0: uart@18020000 {
+ compatible = "qca,ar9330-uart";
+ reg = <0x18020000 0x14>;
+ };
--- /dev/null
+Binding for Qualcomm Atheros AR7xxx/AR9xxx SPI controller
+
+Required properties:
+- compatible: has to be "qca,<soc-type>-spi", "qca,ar7100-spi" as fallback.
+- reg: Base address and size of the controllers memory area
+- #address-cells: <1>, as required by generic SPI binding.
+- #size-cells: <0>, also as required by generic SPI binding.
+
+Child nodes as per the generic SPI binding.
+
+Example:
+
+ spi@1f000000 {
+ compatible = "qca,ar9132-spi", "qca,ar7100-spi";
+ reg = <0x1f000000 0x10>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
--- /dev/null
+/*
+ * U-Boot uImage source file with multiple kernels, ramdisks and FDT blobs
+ * This example makes use of the 'loadables' field
+ */
+
+/dts-v1/;
+
+/ {
+ description = "Configuration to load fpga before Kernel";
+ #address-cells = <1>;
+
+ images {
+ fdt@1 {
+ description = "zc706";
+ data = /incbin/("/tftpboot/devicetree.dtb");
+ type = "flat_dt";
+ arch = "arm";
+ compression = "none";
+ load = <0x10000000>;
+ hash@1 {
+ algo = "md5";
+ };
+ };
+
+ fpga@1 {
+ description = "FPGA";
+ data = /incbin/("/tftpboot/download.bit");
+ type = "fpga";
+ arch = "arm";
+ compression = "none";
+ load = <0x30000000>;
+ hash@1 {
+ algo = "md5";
+ };
+ };
+
+ linux_kernel@1 {
+ description = "Linux";
+ data = /incbin/("/tftpboot/zImage");
+ type = "kernel";
+ arch = "arm";
+ os = "linux";
+ compression = "none";
+ load = <0x8000>;
+ entry = <0x8000>;
+ hash@1 {
+ algo = "md5";
+ };
+ };
+ };
+
+ configurations {
+ default = "config@2";
+ config@1 {
+ description = "Linux";
+ kernel = "linux_kernel@1";
+ fdt = "fdt@1";
+ };
+
+ config@2 {
+ description = "Linux with fpga";
+ kernel = "linux_kernel@1";
+ fdt = "fdt@1";
+ fpga = "fpga@1";
+ };
+ };
+};
|- kernel = "kernel sub-node unit name"
|- ramdisk = "ramdisk sub-node unit name"
|- fdt = "fdt sub-node unit-name"
+ |- fpga = "fpga sub-node unit-name"
|- loadables = "loadables sub-node unit-name"
"fdt type").
- setup : Unit name of the corresponding setup binary (used for booting
an x86 kernel). This contains the setup.bin file built by the kernel.
+ - fpga : Unit name of the corresponding fpga bitstream blob
+ (component image node of a "fpga type").
- loadables : Unit name containing a list of additional binaries to be
loaded at their given locations. "loadables" is a comma-separated list
of strings. U-Boot will load each binary at its given start-address.
obj-$(CONFIG_SPL_USB_HOST_SUPPORT) += usb/host/
obj-$(CONFIG_OMAP_USB_PHY) += usb/phy/
obj-$(CONFIG_SPL_SATA_SUPPORT) += block/
+obj-$(CONFIG_SPL_USB_HOST_SUPPORT) += block/
+obj-$(CONFIG_SPL_MMC_SUPPORT) += block/
else
be partitioned into several areas, called 'partitions' in U-Boot.
A filesystem can be placed in each partition.
-config DISK
- bool "Support disk controllers with driver model"
+config AHCI
+ bool "Support SATA controllers with driver model"
depends on DM
- default y if DM
help
This enables a uclass for disk controllers in U-Boot. Various driver
types can use this, such as AHCI/SATA. It does not provide any standard
obj-$(CONFIG_BLK) += blk-uclass.o
-obj-$(CONFIG_DISK) += disk-uclass.o
+ifndef CONFIG_BLK
+obj-y += blk_legacy.o
+endif
+
+obj-$(CONFIG_AHCI) += ahci-uclass.o
obj-$(CONFIG_SCSI_AHCI) += ahci.o
obj-$(CONFIG_DWC_AHSATA) += dwc_ahsata.o
obj-$(CONFIG_FSL_SATA) += fsl_sata.o
obj-$(CONFIG_SATA_SIL3114) += sata_sil3114.o
obj-$(CONFIG_SATA_SIL) += sata_sil.o
obj-$(CONFIG_IDE_SIL680) += sil680.o
-obj-$(CONFIG_SANDBOX) += sandbox.o
+obj-$(CONFIG_SANDBOX) += sandbox.o sandbox_scsi.o sata_sandbox.o
obj-$(CONFIG_SCSI_SYM53C8XX) += sym53c8xx.o
obj-$(CONFIG_SYSTEMACE) += systemace.o
obj-$(CONFIG_BLOCK_CACHE) += blkcache.o
--- /dev/null
+/*
+ * Copyright (c) 2015 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+
+UCLASS_DRIVER(ahci) = {
+ .id = UCLASS_AHCI,
+ .name = "ahci",
+};
#include <dm/device-internal.h>
#include <dm/lists.h>
+static const char *if_typename_str[IF_TYPE_COUNT] = {
+ [IF_TYPE_IDE] = "ide",
+ [IF_TYPE_SCSI] = "scsi",
+ [IF_TYPE_ATAPI] = "atapi",
+ [IF_TYPE_USB] = "usb",
+ [IF_TYPE_DOC] = "doc",
+ [IF_TYPE_MMC] = "mmc",
+ [IF_TYPE_SD] = "sd",
+ [IF_TYPE_SATA] = "sata",
+ [IF_TYPE_HOST] = "host",
+ [IF_TYPE_SYSTEMACE] = "ace",
+};
+
+static enum uclass_id if_type_uclass_id[IF_TYPE_COUNT] = {
+ [IF_TYPE_IDE] = UCLASS_INVALID,
+ [IF_TYPE_SCSI] = UCLASS_INVALID,
+ [IF_TYPE_ATAPI] = UCLASS_INVALID,
+ [IF_TYPE_USB] = UCLASS_MASS_STORAGE,
+ [IF_TYPE_DOC] = UCLASS_INVALID,
+ [IF_TYPE_MMC] = UCLASS_MMC,
+ [IF_TYPE_SD] = UCLASS_INVALID,
+ [IF_TYPE_SATA] = UCLASS_AHCI,
+ [IF_TYPE_HOST] = UCLASS_ROOT,
+ [IF_TYPE_SYSTEMACE] = UCLASS_INVALID,
+};
+
+static enum if_type if_typename_to_iftype(const char *if_typename)
+{
+ int i;
+
+ for (i = 0; i < IF_TYPE_COUNT; i++) {
+ if (if_typename_str[i] &&
+ !strcmp(if_typename, if_typename_str[i]))
+ return i;
+ }
+
+ return IF_TYPE_UNKNOWN;
+}
+
+static enum uclass_id if_type_to_uclass_id(enum if_type if_type)
+{
+ return if_type_uclass_id[if_type];
+}
+
+struct blk_desc *blk_get_devnum_by_type(enum if_type if_type, int devnum)
+{
+ struct blk_desc *desc;
+ struct udevice *dev;
+ int ret;
+
+ ret = blk_get_device(if_type, devnum, &dev);
+ if (ret)
+ return NULL;
+ desc = dev_get_uclass_platdata(dev);
+
+ return desc;
+}
+
+/*
+ * This function is complicated with driver model. We look up the interface
+ * name in a local table. This gives us an interface type which we can match
+ * against the uclass of the block device's parent.
+ */
+struct blk_desc *blk_get_devnum_by_typename(const char *if_typename, int devnum)
+{
+ enum uclass_id uclass_id;
+ enum if_type if_type;
+ struct udevice *dev;
+ struct uclass *uc;
+ int ret;
+
+ if_type = if_typename_to_iftype(if_typename);
+ if (if_type == IF_TYPE_UNKNOWN) {
+ debug("%s: Unknown interface type '%s'\n", __func__,
+ if_typename);
+ return NULL;
+ }
+ uclass_id = if_type_to_uclass_id(if_type);
+ if (uclass_id == UCLASS_INVALID) {
+ debug("%s: Unknown uclass for interface type'\n",
+ if_typename_str[if_type]);
+ return NULL;
+ }
+
+ ret = uclass_get(UCLASS_BLK, &uc);
+ if (ret)
+ return NULL;
+ uclass_foreach_dev(dev, uc) {
+ struct blk_desc *desc = dev_get_uclass_platdata(dev);
+
+ debug("%s: if_type=%d, devnum=%d: %s, %d, %d\n", __func__,
+ if_type, devnum, dev->name, desc->if_type, desc->devnum);
+ if (desc->devnum != devnum)
+ continue;
+
+ /* Find out the parent device uclass */
+ if (device_get_uclass_id(dev->parent) != uclass_id) {
+ debug("%s: parent uclass %d, this dev %d\n", __func__,
+ device_get_uclass_id(dev->parent), uclass_id);
+ continue;
+ }
+
+ if (device_probe(dev))
+ return NULL;
+
+ debug("%s: Device desc %p\n", __func__, desc);
+ return desc;
+ }
+ debug("%s: No device found\n", __func__);
+
+ return NULL;
+}
+
+/**
+ * get_desc() - Get the block device descriptor for the given device number
+ *
+ * @if_type: Interface type
+ * @devnum: Device number (0 = first)
+ * @descp: Returns block device descriptor on success
+ * @return 0 on success, -ENODEV if there is no such device and no device
+ * with a higher device number, -ENOENT if there is no such device but there
+ * is one with a higher number, or other -ve on other error.
+ */
+static int get_desc(enum if_type if_type, int devnum, struct blk_desc **descp)
+{
+ bool found_more = false;
+ struct udevice *dev;
+ struct uclass *uc;
+ int ret;
+
+ *descp = NULL;
+ ret = uclass_get(UCLASS_BLK, &uc);
+ if (ret)
+ return ret;
+ uclass_foreach_dev(dev, uc) {
+ struct blk_desc *desc = dev_get_uclass_platdata(dev);
+
+ debug("%s: if_type=%d, devnum=%d: %s, %d, %d\n", __func__,
+ if_type, devnum, dev->name, desc->if_type, desc->devnum);
+ if (desc->if_type == if_type) {
+ if (desc->devnum == devnum) {
+ ret = device_probe(dev);
+ if (ret)
+ return ret;
+
+ } else if (desc->devnum > devnum) {
+ found_more = true;
+ }
+ }
+ }
+
+ return found_more ? -ENOENT : -ENODEV;
+}
+
+int blk_select_hwpart_devnum(enum if_type if_type, int devnum, int hwpart)
+{
+ struct udevice *dev;
+ int ret;
+
+ ret = blk_get_device(if_type, devnum, &dev);
+ if (ret)
+ return ret;
+
+ return blk_select_hwpart(dev, hwpart);
+}
+
+int blk_list_part(enum if_type if_type)
+{
+ struct blk_desc *desc;
+ int devnum, ok;
+ int ret;
+
+ for (ok = 0, devnum = 0;; ++devnum) {
+ ret = get_desc(if_type, devnum, &desc);
+ if (ret == -ENODEV)
+ break;
+ else if (ret)
+ continue;
+ if (desc->part_type != PART_TYPE_UNKNOWN) {
+ ++ok;
+ if (devnum)
+ putc('\n');
+ part_print(desc);
+ }
+ }
+ if (!ok)
+ return -ENODEV;
+
+ return 0;
+}
+
+int blk_print_part_devnum(enum if_type if_type, int devnum)
+{
+ struct blk_desc *desc;
+ int ret;
+
+ ret = get_desc(if_type, devnum, &desc);
+ if (ret)
+ return ret;
+ if (desc->type == DEV_TYPE_UNKNOWN)
+ return -ENOENT;
+ part_print(desc);
+
+ return 0;
+}
+
+void blk_list_devices(enum if_type if_type)
+{
+ struct blk_desc *desc;
+ int ret;
+ int i;
+
+ for (i = 0;; ++i) {
+ ret = get_desc(if_type, i, &desc);
+ if (ret == -ENODEV)
+ break;
+ else if (ret)
+ continue;
+ if (desc->type == DEV_TYPE_UNKNOWN)
+ continue; /* list only known devices */
+ printf("Device %d: ", i);
+ dev_print(desc);
+ }
+}
+
+int blk_print_device_num(enum if_type if_type, int devnum)
+{
+ struct blk_desc *desc;
+ int ret;
+
+ ret = get_desc(if_type, devnum, &desc);
+ if (ret)
+ return ret;
+ printf("\nIDE device %d: ", devnum);
+ dev_print(desc);
+
+ return 0;
+}
+
+int blk_show_device(enum if_type if_type, int devnum)
+{
+ struct blk_desc *desc;
+ int ret;
+
+ printf("\nDevice %d: ", devnum);
+ ret = get_desc(if_type, devnum, &desc);
+ if (ret == -ENODEV || ret == -ENOENT) {
+ printf("unknown device\n");
+ return -ENODEV;
+ }
+ if (ret)
+ return ret;
+ dev_print(desc);
+
+ if (desc->type == DEV_TYPE_UNKNOWN)
+ return -ENOENT;
+
+ return 0;
+}
+
+ulong blk_read_devnum(enum if_type if_type, int devnum, lbaint_t start,
+ lbaint_t blkcnt, void *buffer)
+{
+ struct blk_desc *desc;
+ ulong n;
+ int ret;
+
+ ret = get_desc(if_type, devnum, &desc);
+ if (ret)
+ return ret;
+ n = blk_dread(desc, start, blkcnt, buffer);
+ if (IS_ERR_VALUE(n))
+ return n;
+
+ /* flush cache after read */
+ flush_cache((ulong)buffer, blkcnt * desc->blksz);
+
+ return n;
+}
+
+ulong blk_write_devnum(enum if_type if_type, int devnum, lbaint_t start,
+ lbaint_t blkcnt, const void *buffer)
+{
+ struct blk_desc *desc;
+ int ret;
+
+ ret = get_desc(if_type, devnum, &desc);
+ if (ret)
+ return ret;
+ return blk_dwrite(desc, start, blkcnt, buffer);
+}
+
+int blk_select_hwpart(struct udevice *dev, int hwpart)
+{
+ const struct blk_ops *ops = blk_get_ops(dev);
+
+ if (!ops)
+ return -ENOSYS;
+ if (!ops->select_hwpart)
+ return 0;
+
+ return ops->select_hwpart(dev, hwpart);
+}
+
+int blk_dselect_hwpart(struct blk_desc *desc, int hwpart)
+{
+ return blk_select_hwpart(desc->bdev, hwpart);
+}
+
int blk_first_device(int if_type, struct udevice **devp)
{
struct blk_desc *desc;
return 0;
}
+int blk_find_max_devnum(enum if_type if_type)
+{
+ struct udevice *dev;
+ int max_devnum = -ENODEV;
+ struct uclass *uc;
+ int ret;
+
+ ret = uclass_get(UCLASS_BLK, &uc);
+ if (ret)
+ return ret;
+ uclass_foreach_dev(dev, uc) {
+ struct blk_desc *desc = dev_get_uclass_platdata(dev);
+
+ if (desc->if_type == if_type && desc->devnum > max_devnum)
+ max_devnum = desc->devnum;
+ }
+
+ return max_devnum;
+}
+
int blk_create_device(struct udevice *parent, const char *drv_name,
const char *name, int if_type, int devnum, int blksz,
lbaint_t size, struct udevice **devp)
struct udevice *dev;
int ret;
+ if (devnum == -1) {
+ ret = blk_find_max_devnum(if_type);
+ if (ret == -ENODEV)
+ devnum = 0;
+ else if (ret < 0)
+ return ret;
+ else
+ devnum = ret + 1;
+ }
ret = device_bind_driver(parent, drv_name, name, &dev);
if (ret)
return ret;
return 0;
}
+int blk_create_devicef(struct udevice *parent, const char *drv_name,
+ const char *name, int if_type, int devnum, int blksz,
+ lbaint_t size, struct udevice **devp)
+{
+ char dev_name[30], *str;
+ int ret;
+
+ snprintf(dev_name, sizeof(dev_name), "%s.%s", parent->name, name);
+ str = strdup(dev_name);
+ if (!str)
+ return -ENOMEM;
+
+ ret = blk_create_device(parent, drv_name, str, if_type, devnum,
+ blksz, size, devp);
+ if (ret) {
+ free(str);
+ return ret;
+ }
+ device_set_name_alloced(*devp);
+
+ return ret;
+}
+
int blk_unbind_all(int if_type)
{
struct uclass *uc;
--- /dev/null
+/*
+ * Copyright (C) 2016 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/err.h>
+
+struct blk_driver *blk_driver_lookup_type(int if_type)
+{
+ struct blk_driver *drv = ll_entry_start(struct blk_driver, blk_driver);
+ const int n_ents = ll_entry_count(struct blk_driver, blk_driver);
+ struct blk_driver *entry;
+
+ for (entry = drv; entry != drv + n_ents; entry++) {
+ if (if_type == entry->if_type)
+ return entry;
+ }
+
+ /* Not found */
+ return NULL;
+}
+
+static struct blk_driver *blk_driver_lookup_typename(const char *if_typename)
+{
+ struct blk_driver *drv = ll_entry_start(struct blk_driver, blk_driver);
+ const int n_ents = ll_entry_count(struct blk_driver, blk_driver);
+ struct blk_driver *entry;
+
+ for (entry = drv; entry != drv + n_ents; entry++) {
+ if (!strcmp(if_typename, entry->if_typename))
+ return entry;
+ }
+
+ /* Not found */
+ return NULL;
+}
+
+/**
+ * get_desc() - Get the block device descriptor for the given device number
+ *
+ * @drv: Legacy block driver
+ * @devnum: Device number (0 = first)
+ * @descp: Returns block device descriptor on success
+ * @return 0 on success, -ENODEV if there is no such device, -ENOSYS if the
+ * driver does not provide a way to find a device, or other -ve on other
+ * error.
+ */
+static int get_desc(struct blk_driver *drv, int devnum, struct blk_desc **descp)
+{
+ if (drv->desc) {
+ if (devnum < 0 || devnum >= drv->max_devs)
+ return -ENODEV;
+ *descp = &drv->desc[devnum];
+ return 0;
+ }
+ if (!drv->get_dev)
+ return -ENOSYS;
+
+ return drv->get_dev(devnum, descp);
+}
+
+#ifdef HAVE_BLOCK_DEVICE
+int blk_list_part(enum if_type if_type)
+{
+ struct blk_driver *drv;
+ struct blk_desc *desc;
+ int devnum, ok;
+ bool first = true;
+
+ drv = blk_driver_lookup_type(if_type);
+ if (!drv)
+ return -ENOSYS;
+ for (ok = 0, devnum = 0; devnum < drv->max_devs; ++devnum) {
+ if (get_desc(drv, devnum, &desc))
+ continue;
+ if (desc->part_type != PART_TYPE_UNKNOWN) {
+ ++ok;
+ if (!first)
+ putc('\n');
+ part_print(desc);
+ first = false;
+ }
+ }
+ if (!ok)
+ return -ENODEV;
+
+ return 0;
+}
+
+int blk_print_part_devnum(enum if_type if_type, int devnum)
+{
+ struct blk_driver *drv = blk_driver_lookup_type(if_type);
+ struct blk_desc *desc;
+ int ret;
+
+ if (!drv)
+ return -ENOSYS;
+ ret = get_desc(drv, devnum, &desc);
+ if (ret)
+ return ret;
+ if (desc->type == DEV_TYPE_UNKNOWN)
+ return -ENOENT;
+ part_print(desc);
+
+ return 0;
+}
+
+void blk_list_devices(enum if_type if_type)
+{
+ struct blk_driver *drv = blk_driver_lookup_type(if_type);
+ struct blk_desc *desc;
+ int i;
+
+ if (!drv)
+ return;
+ for (i = 0; i < drv->max_devs; ++i) {
+ if (get_desc(drv, i, &desc))
+ continue;
+ if (desc->type == DEV_TYPE_UNKNOWN)
+ continue; /* list only known devices */
+ printf("Device %d: ", i);
+ dev_print(desc);
+ }
+}
+
+int blk_print_device_num(enum if_type if_type, int devnum)
+{
+ struct blk_driver *drv = blk_driver_lookup_type(if_type);
+ struct blk_desc *desc;
+ int ret;
+
+ if (!drv)
+ return -ENOSYS;
+ ret = get_desc(drv, devnum, &desc);
+ if (ret)
+ return ret;
+ printf("\n%s device %d: ", drv->if_typename, devnum);
+ dev_print(desc);
+
+ return 0;
+}
+
+int blk_show_device(enum if_type if_type, int devnum)
+{
+ struct blk_driver *drv = blk_driver_lookup_type(if_type);
+ struct blk_desc *desc;
+ int ret;
+
+ if (!drv)
+ return -ENOSYS;
+ printf("\nDevice %d: ", devnum);
+ if (devnum >= drv->max_devs) {
+ puts("unknown device\n");
+ return -ENODEV;
+ }
+ ret = get_desc(drv, devnum, &desc);
+ if (ret)
+ return ret;
+ dev_print(desc);
+
+ if (desc->type == DEV_TYPE_UNKNOWN)
+ return -ENOENT;
+
+ return 0;
+}
+#endif /* HAVE_BLOCK_DEVICE */
+
+struct blk_desc *blk_get_devnum_by_type(enum if_type if_type, int devnum)
+{
+ struct blk_driver *drv = blk_driver_lookup_type(if_type);
+ struct blk_desc *desc;
+
+ if (!drv)
+ return NULL;
+
+ if (get_desc(drv, devnum, &desc))
+ return NULL;
+
+ return desc;
+}
+
+int blk_dselect_hwpart(struct blk_desc *desc, int hwpart)
+{
+ struct blk_driver *drv = blk_driver_lookup_type(desc->if_type);
+
+ if (!drv)
+ return -ENOSYS;
+ if (drv->select_hwpart)
+ return drv->select_hwpart(desc, hwpart);
+
+ return 0;
+}
+
+struct blk_desc *blk_get_devnum_by_typename(const char *if_typename, int devnum)
+{
+ struct blk_driver *drv = blk_driver_lookup_typename(if_typename);
+ struct blk_desc *desc;
+
+ if (!drv)
+ return NULL;
+
+ if (get_desc(drv, devnum, &desc))
+ return NULL;
+
+ return desc;
+}
+
+ulong blk_read_devnum(enum if_type if_type, int devnum, lbaint_t start,
+ lbaint_t blkcnt, void *buffer)
+{
+ struct blk_driver *drv = blk_driver_lookup_type(if_type);
+ struct blk_desc *desc;
+ ulong n;
+ int ret;
+
+ if (!drv)
+ return -ENOSYS;
+ ret = get_desc(drv, devnum, &desc);
+ if (ret)
+ return ret;
+ n = desc->block_read(desc, start, blkcnt, buffer);
+ if (IS_ERR_VALUE(n))
+ return n;
+
+ /* flush cache after read */
+ flush_cache((ulong)buffer, blkcnt * desc->blksz);
+
+ return n;
+}
+
+ulong blk_write_devnum(enum if_type if_type, int devnum, lbaint_t start,
+ lbaint_t blkcnt, const void *buffer)
+{
+ struct blk_driver *drv = blk_driver_lookup_type(if_type);
+ struct blk_desc *desc;
+ int ret;
+
+ if (!drv)
+ return -ENOSYS;
+ ret = get_desc(drv, devnum, &desc);
+ if (ret)
+ return ret;
+ return desc->block_write(desc, start, blkcnt, buffer);
+}
+
+int blk_select_hwpart_devnum(enum if_type if_type, int devnum, int hwpart)
+{
+ struct blk_driver *drv = blk_driver_lookup_type(if_type);
+ struct blk_desc *desc;
+ int ret;
+
+ if (!drv)
+ return -ENOSYS;
+ ret = get_desc(drv, devnum, &desc);
+ if (ret)
+ return ret;
+ return drv->select_hwpart(desc, hwpart);
+}
+++ /dev/null
-/*
- * Copyright (c) 2015 Google, Inc
- * Written by Simon Glass <sjg@chromium.org>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <dm.h>
-
-UCLASS_DRIVER(disk) = {
- .id = UCLASS_DISK,
- .name = "disk",
-};
DECLARE_GLOBAL_DATA_PTR;
+#ifndef CONFIG_BLK
+static struct host_block_dev host_devices[CONFIG_HOST_MAX_DEVICES];
+
+static struct host_block_dev *find_host_device(int dev)
+{
+ if (dev >= 0 && dev < CONFIG_HOST_MAX_DEVICES)
+ return &host_devices[dev];
+
+ return NULL;
+}
+#endif
+
+#ifdef CONFIG_BLK
static unsigned long host_block_read(struct udevice *dev,
unsigned long start, lbaint_t blkcnt,
void *buffer)
struct host_block_dev *host_dev = dev_get_priv(dev);
struct blk_desc *block_dev = dev_get_uclass_platdata(dev);
+#else
+static unsigned long host_block_read(struct blk_desc *block_dev,
+ unsigned long start, lbaint_t blkcnt,
+ void *buffer)
+{
+ int dev = block_dev->devnum;
+ struct host_block_dev *host_dev = find_host_device(dev);
+
+ if (!host_dev)
+ return -1;
+#endif
+
if (os_lseek(host_dev->fd, start * block_dev->blksz, OS_SEEK_SET) ==
-1) {
printf("ERROR: Invalid block %lx\n", start);
return -1;
}
+#ifdef CONFIG_BLK
static unsigned long host_block_write(struct udevice *dev,
unsigned long start, lbaint_t blkcnt,
const void *buffer)
{
struct host_block_dev *host_dev = dev_get_priv(dev);
struct blk_desc *block_dev = dev_get_uclass_platdata(dev);
+#else
+static unsigned long host_block_write(struct blk_desc *block_dev,
+ unsigned long start, lbaint_t blkcnt,
+ const void *buffer)
+{
+ int dev = block_dev->devnum;
+ struct host_block_dev *host_dev = find_host_device(dev);
+#endif
if (os_lseek(host_dev->fd, start * block_dev->blksz, OS_SEEK_SET) ==
-1) {
return -1;
}
+#ifdef CONFIG_BLK
int host_dev_bind(int devnum, char *filename)
{
struct host_block_dev *host_dev;
free(str);
return ret;
}
+#else
+int host_dev_bind(int dev, char *filename)
+{
+ struct host_block_dev *host_dev = find_host_device(dev);
+
+ if (!host_dev)
+ return -1;
+ if (host_dev->blk_dev.priv) {
+ os_close(host_dev->fd);
+ host_dev->blk_dev.priv = NULL;
+ }
+ if (host_dev->filename)
+ free(host_dev->filename);
+ if (filename && *filename) {
+ host_dev->filename = strdup(filename);
+ } else {
+ host_dev->filename = NULL;
+ return 0;
+ }
+
+ host_dev->fd = os_open(host_dev->filename, OS_O_RDWR);
+ if (host_dev->fd == -1) {
+ printf("Failed to access host backing file '%s'\n",
+ host_dev->filename);
+ return 1;
+ }
+
+ struct blk_desc *blk_dev = &host_dev->blk_dev;
+ blk_dev->if_type = IF_TYPE_HOST;
+ blk_dev->priv = host_dev;
+ blk_dev->blksz = 512;
+ blk_dev->lba = os_lseek(host_dev->fd, 0, OS_SEEK_END) / blk_dev->blksz;
+ blk_dev->block_read = host_block_read;
+ blk_dev->block_write = host_block_write;
+ blk_dev->devnum = dev;
+ blk_dev->part_type = PART_TYPE_UNKNOWN;
+ part_init(blk_dev);
+
+ return 0;
+}
+#endif
int host_get_dev_err(int devnum, struct blk_desc **blk_devp)
{
+#ifdef CONFIG_BLK
struct udevice *dev;
int ret;
if (ret)
return ret;
*blk_devp = dev_get_uclass_platdata(dev);
+#else
+ struct host_block_dev *host_dev = find_host_device(devnum);
- return 0;
-}
+ if (!host_dev)
+ return -ENODEV;
-struct blk_desc *host_get_dev(int dev)
-{
- struct blk_desc *blk_dev;
+ if (!host_dev->blk_dev.priv)
+ return -ENOENT;
- if (host_get_dev_err(dev, &blk_dev))
- return NULL;
+ *blk_devp = &host_dev->blk_dev;
+#endif
- return blk_dev;
+ return 0;
}
+#ifdef CONFIG_BLK
static const struct blk_ops sandbox_host_blk_ops = {
.read = host_block_read,
.write = host_block_write,
.ops = &sandbox_host_blk_ops,
.priv_auto_alloc_size = sizeof(struct host_block_dev),
};
+#else
+U_BOOT_LEGACY_BLK(sandbox_host) = {
+ .if_typename = "host",
+ .if_type = IF_TYPE_HOST,
+ .max_devs = CONFIG_HOST_MAX_DEVICES,
+ .get_dev = host_get_dev_err,
+};
+#endif
--- /dev/null
+/*
+ * Copyright (C) 2015 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * This file contains dummy implementations of SCSI functions requried so
+ * that CONFIG_SCSI can be enabled for sandbox.
+ */
+
+#include <common.h>
+#include <scsi.h>
+
+void scsi_bus_reset(void)
+{
+}
+
+void scsi_init(void)
+{
+}
+
+int scsi_exec(ccb *pccb)
+{
+ return 0;
+}
+
+void scsi_print_error(ccb *pccb)
+{
+}
--- /dev/null
+/*
+ * Copyright (C) 2015 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+
+int init_sata(int dev)
+{
+ return 0;
+}
+
+int reset_sata(int dev)
+{
+ return 0;
+}
+
+int scan_sata(int dev)
+{
+ return 0;
+}
+
+ulong sata_read(int dev, ulong blknr, lbaint_t blkcnt, void *buffer)
+{
+ return 0;
+}
+
+ulong sata_write(int dev, ulong blknr, lbaint_t blkcnt, const void *buffer)
+{
+ return 0;
+}
#define PRINTF(fmt,args...)
#endif
-#if defined(CONFIG_CMD_SCSI) && defined(CONFIG_SCSI_SYM53C8XX)
+#if defined(CONFIG_SCSI) && defined(CONFIG_SCSI_SYM53C8XX)
#undef SCSI_SINGLE_STEP
/*
#include <common.h>
#include <command.h>
-#include <systemace.h>
+#include <dm.h>
#include <part.h>
#include <asm/io.h>
return in16(base + off);
}
-static unsigned long systemace_read(struct blk_desc *block_dev,
- unsigned long start, lbaint_t blkcnt,
- void *buffer);
-
+#ifndef CONFIG_BLK
static struct blk_desc systemace_dev = { 0 };
+#endif
static int get_cf_lock(void)
{
ace_writew((val & 0xffff), 0x18);
}
-#ifdef CONFIG_PARTITIONS
-struct blk_desc *systemace_get_dev(int dev)
-{
- /* The first time through this, the systemace_dev object is
- not yet initialized. In that case, fill it in. */
- if (systemace_dev.blksz == 0) {
- systemace_dev.if_type = IF_TYPE_UNKNOWN;
- systemace_dev.devnum = 0;
- systemace_dev.part_type = PART_TYPE_UNKNOWN;
- systemace_dev.type = DEV_TYPE_HARDDISK;
- systemace_dev.blksz = 512;
- systemace_dev.log2blksz = LOG2(systemace_dev.blksz);
- systemace_dev.removable = 1;
- systemace_dev.block_read = systemace_read;
-
- /*
- * Ensure the correct bus mode (8/16 bits) gets enabled
- */
- ace_writew(width == 8 ? 0 : 0x0001, 0);
-
- part_init(&systemace_dev);
-
- }
-
- return &systemace_dev;
-}
-#endif
-
/*
* This function is called (by dereferencing the block_read pointer in
* the dev_desc) to read blocks of data. The return value is the
* number of blocks read. A zero return indicates an error.
*/
+#ifdef CONFIG_BLK
+static unsigned long systemace_read(struct udevice *dev, unsigned long start,
+ lbaint_t blkcnt, void *buffer)
+#else
static unsigned long systemace_read(struct blk_desc *block_dev,
unsigned long start, lbaint_t blkcnt,
void *buffer)
+#endif
{
int retry;
unsigned blk_countdown;
return blkcnt;
}
+
+#ifdef CONFIG_BLK
+static int systemace_bind(struct udevice *dev)
+{
+ struct blk_desc *bdesc;
+ struct udevice *bdev;
+ int ret;
+
+ ret = blk_create_devicef(dev, "systemace_blk", "blk", IF_TYPE_SYSTEMACE,
+ -1, 512, 0, &bdev);
+ if (ret) {
+ debug("Cannot create block device\n");
+ return ret;
+ }
+ bdesc = dev_get_uclass_platdata(bdev);
+ bdesc->removable = 1;
+ bdesc->part_type = PART_TYPE_UNKNOWN;
+ bdesc->log2blksz = LOG2(bdesc->blksz);
+
+ /* Ensure the correct bus mode (8/16 bits) gets enabled */
+ ace_writew(width == 8 ? 0 : 0x0001, 0);
+
+ return 0;
+}
+
+static const struct blk_ops systemace_blk_ops = {
+ .read = systemace_read,
+};
+
+U_BOOT_DRIVER(systemace_blk) = {
+ .name = "systemace_blk",
+ .id = UCLASS_BLK,
+ .ops = &systemace_blk_ops,
+ .bind = systemace_bind,
+};
+#else
+static int systemace_get_dev(int dev, struct blk_desc **descp)
+{
+ /* The first time through this, the systemace_dev object is
+ not yet initialized. In that case, fill it in. */
+ if (systemace_dev.blksz == 0) {
+ systemace_dev.if_type = IF_TYPE_UNKNOWN;
+ systemace_dev.devnum = 0;
+ systemace_dev.part_type = PART_TYPE_UNKNOWN;
+ systemace_dev.type = DEV_TYPE_HARDDISK;
+ systemace_dev.blksz = 512;
+ systemace_dev.log2blksz = LOG2(systemace_dev.blksz);
+ systemace_dev.removable = 1;
+ systemace_dev.block_read = systemace_read;
+
+ /*
+ * Ensure the correct bus mode (8/16 bits) gets enabled
+ */
+ ace_writew(width == 8 ? 0 : 0x0001, 0);
+
+ part_init(&systemace_dev);
+ }
+ *descp = &systemace_dev;
+
+ return 0;
+}
+
+U_BOOT_LEGACY_BLK(systemace) = {
+ .if_typename = "ace",
+ .if_type = IF_TYPE_SYSTEMACE,
+ .max_devs = 1,
+ .get_dev = systemace_get_dev,
+};
+#endif
devres_release_all(dev);
+ if (dev->flags & DM_NAME_ALLOCED)
+ free((char *)dev->name);
free(dev);
return 0;
#if CONFIG_IS_ENABLED(OF_CONTROL)
int index;
- index = fdt_find_string(gd->fdt_blob, dev->parent->of_offset,
- "reg-names", name);
+ index = fdt_find_string(gd->fdt_blob, dev->of_offset, "reg-names",
+ name);
if (index < 0)
return index;
return list_is_last(&dev->sibling_node, &parent->child_head);
}
+void device_set_name_alloced(struct udevice *dev)
+{
+ dev->flags |= DM_NAME_ALLOCED;
+}
+
int device_set_name(struct udevice *dev, const char *name)
{
name = strdup(name);
if (!name)
return -ENOMEM;
dev->name = name;
+ device_set_name_alloced(dev);
return 0;
}
+
+bool of_device_is_compatible(struct udevice *dev, const char *compat)
+{
+ const void *fdt = gd->fdt_blob;
+
+ return !fdt_node_check_compatible(fdt, dev->of_offset, compat);
+}
+
+bool of_machine_is_compatible(const char *compat)
+{
+ const void *fdt = gd->fdt_blob;
+
+ return !fdt_node_check_compatible(fdt, 0, compat);
+}
dm_dbg(" - found match at '%s'\n", entry->name);
ret = device_bind(parent, entry, name, NULL, offset, &dev);
+ if (ret == -ENODEV) {
+ dm_dbg("Driver '%s' refuses to bind\n", entry->name);
+ continue;
+ }
if (ret) {
dm_warn("Error binding driver '%s': %d\n", entry->name,
ret);
#define CIRC_CNT(head, tail, size) (((head) - (tail)) & (size - 1))
#define CIRC_SPACE(head, tail, size) CIRC_CNT((tail), (head) + 1, (size))
-struct jobring jr;
+uint32_t sec_offset[CONFIG_SYS_FSL_MAX_NUM_OF_SEC] = {
+ 0,
+#if defined(CONFIG_PPC_C29X)
+ CONFIG_SYS_FSL_SEC_IDX_OFFSET,
+ 2 * CONFIG_SYS_FSL_SEC_IDX_OFFSET
+#endif
+};
+
+#define SEC_ADDR(idx) \
+ ((CONFIG_SYS_FSL_SEC_ADDR + sec_offset[idx]))
+
+#define SEC_JR0_ADDR(idx) \
+ (SEC_ADDR(idx) + \
+ (CONFIG_SYS_FSL_JR0_OFFSET - CONFIG_SYS_FSL_SEC_OFFSET))
+
+struct jobring jr0[CONFIG_SYS_FSL_MAX_NUM_OF_SEC];
-static inline void start_jr0(void)
+static inline void start_jr0(uint8_t sec_idx)
{
- ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
+ ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
u32 ctpr_ms = sec_in32(&sec->ctpr_ms);
u32 scfgr = sec_in32(&sec->scfgr);
}
}
-static inline void jr_reset_liodn(void)
+static inline void jr_reset_liodn(uint8_t sec_idx)
{
- ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
+ ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
sec_out32(&sec->jrliodnr[0].ls, 0);
}
-static inline void jr_disable_irq(void)
+static inline void jr_disable_irq(uint8_t sec_idx)
{
- struct jr_regs *regs = (struct jr_regs *)CONFIG_SYS_FSL_JR0_ADDR;
+ struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
uint32_t jrcfg = sec_in32(®s->jrcfg1);
jrcfg = jrcfg | JR_INTMASK;
sec_out32(®s->jrcfg1, jrcfg);
}
-static void jr_initregs(void)
+static void jr_initregs(uint8_t sec_idx)
{
- struct jr_regs *regs = (struct jr_regs *)CONFIG_SYS_FSL_JR0_ADDR;
- phys_addr_t ip_base = virt_to_phys((void *)jr.input_ring);
- phys_addr_t op_base = virt_to_phys((void *)jr.output_ring);
+ struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
+ struct jobring *jr = &jr0[sec_idx];
+ phys_addr_t ip_base = virt_to_phys((void *)jr->input_ring);
+ phys_addr_t op_base = virt_to_phys((void *)jr->output_ring);
#ifdef CONFIG_PHYS_64BIT
sec_out32(®s->irba_h, ip_base >> 32);
sec_out32(®s->ors, JR_SIZE);
sec_out32(®s->irs, JR_SIZE);
- if (!jr.irq)
- jr_disable_irq();
+ if (!jr->irq)
+ jr_disable_irq(sec_idx);
}
-static int jr_init(void)
+static int jr_init(uint8_t sec_idx)
{
- memset(&jr, 0, sizeof(struct jobring));
+ struct jobring *jr = &jr0[sec_idx];
- jr.jq_id = DEFAULT_JR_ID;
- jr.irq = DEFAULT_IRQ;
+ memset(jr, 0, sizeof(struct jobring));
+
+ jr->jq_id = DEFAULT_JR_ID;
+ jr->irq = DEFAULT_IRQ;
#ifdef CONFIG_FSL_CORENET
- jr.liodn = DEFAULT_JR_LIODN;
+ jr->liodn = DEFAULT_JR_LIODN;
#endif
- jr.size = JR_SIZE;
- jr.input_ring = (dma_addr_t *)memalign(ARCH_DMA_MINALIGN,
+ jr->size = JR_SIZE;
+ jr->input_ring = (dma_addr_t *)memalign(ARCH_DMA_MINALIGN,
JR_SIZE * sizeof(dma_addr_t));
- if (!jr.input_ring)
+ if (!jr->input_ring)
return -1;
- jr.op_size = roundup(JR_SIZE * sizeof(struct op_ring),
- ARCH_DMA_MINALIGN);
- jr.output_ring =
- (struct op_ring *)memalign(ARCH_DMA_MINALIGN, jr.op_size);
- if (!jr.output_ring)
+ jr->op_size = roundup(JR_SIZE * sizeof(struct op_ring),
+ ARCH_DMA_MINALIGN);
+ jr->output_ring =
+ (struct op_ring *)memalign(ARCH_DMA_MINALIGN, jr->op_size);
+ if (!jr->output_ring)
return -1;
- memset(jr.input_ring, 0, JR_SIZE * sizeof(dma_addr_t));
- memset(jr.output_ring, 0, jr.op_size);
+ memset(jr->input_ring, 0, JR_SIZE * sizeof(dma_addr_t));
+ memset(jr->output_ring, 0, jr->op_size);
- start_jr0();
+ start_jr0(sec_idx);
- jr_initregs();
+ jr_initregs(sec_idx);
return 0;
}
-static int jr_sw_cleanup(void)
+static int jr_sw_cleanup(uint8_t sec_idx)
{
- jr.head = 0;
- jr.tail = 0;
- jr.read_idx = 0;
- jr.write_idx = 0;
- memset(jr.info, 0, sizeof(jr.info));
- memset(jr.input_ring, 0, jr.size * sizeof(dma_addr_t));
- memset(jr.output_ring, 0, jr.size * sizeof(struct op_ring));
+ struct jobring *jr = &jr0[sec_idx];
+
+ jr->head = 0;
+ jr->tail = 0;
+ jr->read_idx = 0;
+ jr->write_idx = 0;
+ memset(jr->info, 0, sizeof(jr->info));
+ memset(jr->input_ring, 0, jr->size * sizeof(dma_addr_t));
+ memset(jr->output_ring, 0, jr->size * sizeof(struct op_ring));
return 0;
}
-static int jr_hw_reset(void)
+static int jr_hw_reset(uint8_t sec_idx)
{
- struct jr_regs *regs = (struct jr_regs *)CONFIG_SYS_FSL_JR0_ADDR;
+ struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
uint32_t timeout = 100000;
uint32_t jrint, jrcr;
/* -1 --- error, can't enqueue -- no space available */
static int jr_enqueue(uint32_t *desc_addr,
void (*callback)(uint32_t status, void *arg),
- void *arg)
+ void *arg, uint8_t sec_idx)
{
- struct jr_regs *regs = (struct jr_regs *)CONFIG_SYS_FSL_JR0_ADDR;
- int head = jr.head;
+ struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
+ struct jobring *jr = &jr0[sec_idx];
+ int head = jr->head;
uint32_t desc_word;
int length = desc_len(desc_addr);
int i;
phys_addr_t desc_phys_addr = virt_to_phys(desc_addr);
- if (sec_in32(®s->irsa) == 0 ||
- CIRC_SPACE(jr.head, jr.tail, jr.size) <= 0)
- return -1;
-
- jr.info[head].desc_phys_addr = desc_phys_addr;
- jr.info[head].callback = (void *)callback;
- jr.info[head].arg = arg;
- jr.info[head].op_done = 0;
+ jr->info[head].desc_phys_addr = desc_phys_addr;
+ jr->info[head].callback = (void *)callback;
+ jr->info[head].arg = arg;
+ jr->info[head].op_done = 0;
- unsigned long start = (unsigned long)&jr.info[head] &
+ unsigned long start = (unsigned long)&jr->info[head] &
~(ARCH_DMA_MINALIGN - 1);
- unsigned long end = ALIGN((unsigned long)&jr.info[head] +
+ unsigned long end = ALIGN((unsigned long)&jr->info[head] +
sizeof(struct jr_info), ARCH_DMA_MINALIGN);
flush_dcache_range(start, end);
* depend on endianness of SEC block.
*/
#ifdef CONFIG_SYS_FSL_SEC_LE
- addr_lo = (uint32_t *)(&jr.input_ring[head]);
- addr_hi = (uint32_t *)(&jr.input_ring[head]) + 1;
+ addr_lo = (uint32_t *)(&jr->input_ring[head]);
+ addr_hi = (uint32_t *)(&jr->input_ring[head]) + 1;
#elif defined(CONFIG_SYS_FSL_SEC_BE)
- addr_hi = (uint32_t *)(&jr.input_ring[head]);
- addr_lo = (uint32_t *)(&jr.input_ring[head]) + 1;
+ addr_hi = (uint32_t *)(&jr->input_ring[head]);
+ addr_lo = (uint32_t *)(&jr->input_ring[head]) + 1;
#endif /* ifdef CONFIG_SYS_FSL_SEC_LE */
sec_out32(addr_hi, (uint32_t)(desc_phys_addr >> 32));
#else
/* Write the 32 bit Descriptor address on Input Ring. */
- sec_out32(&jr.input_ring[head], desc_phys_addr);
+ sec_out32(&jr->input_ring[head], desc_phys_addr);
#endif /* ifdef CONFIG_PHYS_64BIT */
- start = (unsigned long)&jr.input_ring[head] & ~(ARCH_DMA_MINALIGN - 1);
- end = ALIGN((unsigned long)&jr.input_ring[head] +
+ start = (unsigned long)&jr->input_ring[head] & ~(ARCH_DMA_MINALIGN - 1);
+ end = ALIGN((unsigned long)&jr->input_ring[head] +
sizeof(dma_addr_t), ARCH_DMA_MINALIGN);
flush_dcache_range(start, end);
- jr.head = (head + 1) & (jr.size - 1);
+ jr->head = (head + 1) & (jr->size - 1);
/* Invalidate output ring */
- start = (unsigned long)jr.output_ring &
+ start = (unsigned long)jr->output_ring &
~(ARCH_DMA_MINALIGN - 1);
- end = ALIGN((unsigned long)jr.output_ring + jr.op_size,
- ARCH_DMA_MINALIGN);
+ end = ALIGN((unsigned long)jr->output_ring + jr->op_size,
+ ARCH_DMA_MINALIGN);
invalidate_dcache_range(start, end);
sec_out32(®s->irja, 1);
return 0;
}
-static int jr_dequeue(void)
+static int jr_dequeue(int sec_idx)
{
- struct jr_regs *regs = (struct jr_regs *)CONFIG_SYS_FSL_JR0_ADDR;
- int head = jr.head;
- int tail = jr.tail;
+ struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
+ struct jobring *jr = &jr0[sec_idx];
+ int head = jr->head;
+ int tail = jr->tail;
int idx, i, found;
void (*callback)(uint32_t status, void *arg);
void *arg = NULL;
uint32_t *addr;
#endif
- while (sec_in32(®s->orsf) && CIRC_CNT(jr.head, jr.tail, jr.size)) {
+ while (sec_in32(®s->orsf) && CIRC_CNT(jr->head, jr->tail,
+ jr->size)) {
found = 0;
* depend on endianness of SEC block.
*/
#ifdef CONFIG_SYS_FSL_SEC_LE
- addr_lo = (uint32_t *)(&jr.output_ring[jr.tail].desc);
- addr_hi = (uint32_t *)(&jr.output_ring[jr.tail].desc) + 1;
+ addr_lo = (uint32_t *)(&jr->output_ring[jr->tail].desc);
+ addr_hi = (uint32_t *)(&jr->output_ring[jr->tail].desc) + 1;
#elif defined(CONFIG_SYS_FSL_SEC_BE)
- addr_hi = (uint32_t *)(&jr.output_ring[jr.tail].desc);
- addr_lo = (uint32_t *)(&jr.output_ring[jr.tail].desc) + 1;
+ addr_hi = (uint32_t *)(&jr->output_ring[jr->tail].desc);
+ addr_lo = (uint32_t *)(&jr->output_ring[jr->tail].desc) + 1;
#endif /* ifdef CONFIG_SYS_FSL_SEC_LE */
op_desc = ((u64)sec_in32(addr_hi) << 32) |
#else
/* Read the 32 bit Descriptor address from Output Ring. */
- addr = (uint32_t *)&jr.output_ring[jr.tail].desc;
+ addr = (uint32_t *)&jr->output_ring[jr->tail].desc;
op_desc = sec_in32(addr);
#endif /* ifdef CONFIG_PHYS_64BIT */
- uint32_t status = sec_in32(&jr.output_ring[jr.tail].status);
+ uint32_t status = sec_in32(&jr->output_ring[jr->tail].status);
- for (i = 0; CIRC_CNT(head, tail + i, jr.size) >= 1; i++) {
- idx = (tail + i) & (jr.size - 1);
- if (op_desc == jr.info[idx].desc_phys_addr) {
+ for (i = 0; CIRC_CNT(head, tail + i, jr->size) >= 1; i++) {
+ idx = (tail + i) & (jr->size - 1);
+ if (op_desc == jr->info[idx].desc_phys_addr) {
found = 1;
break;
}
if (!found)
return -1;
- jr.info[idx].op_done = 1;
- callback = (void *)jr.info[idx].callback;
- arg = jr.info[idx].arg;
+ jr->info[idx].op_done = 1;
+ callback = (void *)jr->info[idx].callback;
+ arg = jr->info[idx].arg;
/* When the job on tail idx gets done, increment
* tail till the point where job completed out of oredr has
*/
if (idx == tail)
do {
- tail = (tail + 1) & (jr.size - 1);
- } while (jr.info[tail].op_done);
+ tail = (tail + 1) & (jr->size - 1);
+ } while (jr->info[tail].op_done);
- jr.tail = tail;
- jr.read_idx = (jr.read_idx + 1) & (jr.size - 1);
+ jr->tail = tail;
+ jr->read_idx = (jr->read_idx + 1) & (jr->size - 1);
sec_out32(®s->orjr, 1);
- jr.info[idx].op_done = 0;
+ jr->info[idx].op_done = 0;
callback(status, arg);
}
x->done = 1;
}
-int run_descriptor_jr(uint32_t *desc)
+static inline int run_descriptor_jr_idx(uint32_t *desc, uint8_t sec_idx)
{
unsigned long long timeval = get_ticks();
unsigned long long timeout = usec2ticks(CONFIG_SEC_DEQ_TIMEOUT);
memset(&op, 0, sizeof(op));
- ret = jr_enqueue(desc, desc_done, &op);
+ ret = jr_enqueue(desc, desc_done, &op, sec_idx);
if (ret) {
debug("Error in SEC enq\n");
ret = JQ_ENQ_ERR;
timeval = get_ticks();
timeout = usec2ticks(CONFIG_SEC_DEQ_TIMEOUT);
while (op.done != 1) {
- ret = jr_dequeue();
+ ret = jr_dequeue(sec_idx);
if (ret) {
debug("Error in SEC deq\n");
ret = JQ_DEQ_ERR;
return ret;
}
-int jr_reset(void)
+int run_descriptor_jr(uint32_t *desc)
+{
+ return run_descriptor_jr_idx(desc, 0);
+}
+
+static inline int jr_reset_sec(uint8_t sec_idx)
{
- if (jr_hw_reset() < 0)
+ if (jr_hw_reset(sec_idx) < 0)
return -1;
/* Clean up the jobring structure maintained by software */
- jr_sw_cleanup();
+ jr_sw_cleanup(sec_idx);
return 0;
}
-int sec_reset(void)
+int jr_reset(void)
{
- ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
+ return jr_reset_sec(0);
+}
+
+static inline int sec_reset_idx(uint8_t sec_idx)
+{
+ ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
uint32_t mcfgr = sec_in32(&sec->mcfgr);
uint32_t timeout = 100000;
return 0;
}
-static int instantiate_rng(void)
+static int instantiate_rng(uint8_t sec_idx)
{
struct result op;
u32 *desc;
u32 rdsta_val;
int ret = 0;
- ccsr_sec_t __iomem *sec =
- (ccsr_sec_t __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
+ ccsr_sec_t __iomem *sec = (ccsr_sec_t __iomem *)SEC_ADDR(sec_idx);
struct rng4tst __iomem *rng =
(struct rng4tst __iomem *)&sec->rng;
flush_dcache_range((unsigned long)desc,
(unsigned long)desc + size);
- ret = run_descriptor_jr(desc);
+ ret = run_descriptor_jr_idx(desc, sec_idx);
if (ret)
printf("RNG: Instantiation failed with error %x\n", ret);
return ret;
}
-static u8 get_rng_vid(void)
+int sec_reset(void)
+{
+ return sec_reset_idx(0);
+}
+
+static u8 get_rng_vid(uint8_t sec_idx)
{
- ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
+ ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
u32 cha_vid = sec_in32(&sec->chavid_ls);
return (cha_vid & SEC_CHAVID_RNG_LS_MASK) >> SEC_CHAVID_LS_RNG_SHIFT;
* By default, the TRNG runs for 200 clocks per sample;
* 1200 clocks per sample generates better entropy.
*/
-static void kick_trng(int ent_delay)
+static void kick_trng(int ent_delay, uint8_t sec_idx)
{
- ccsr_sec_t __iomem *sec =
- (ccsr_sec_t __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
+ ccsr_sec_t __iomem *sec = (ccsr_sec_t __iomem *)SEC_ADDR(sec_idx);
struct rng4tst __iomem *rng =
(struct rng4tst __iomem *)&sec->rng;
u32 val;
sec_clrbits32(&rng->rtmctl, RTMCTL_PRGM);
}
-static int rng_init(void)
+static int rng_init(uint8_t sec_idx)
{
int ret, ent_delay = RTSDCTL_ENT_DLY_MIN;
- ccsr_sec_t __iomem *sec =
- (ccsr_sec_t __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
+ ccsr_sec_t __iomem *sec = (ccsr_sec_t __iomem *)SEC_ADDR(sec_idx);
struct rng4tst __iomem *rng =
(struct rng4tst __iomem *)&sec->rng;
* Also, if a handle was instantiated, do not change
* the TRNG parameters.
*/
- kick_trng(ent_delay);
+ kick_trng(ent_delay, sec_idx);
ent_delay += 400;
/*
* if instantiate_rng(...) fails, the loop will rerun
* interval, leading to a sucessful initialization of
* the RNG.
*/
- ret = instantiate_rng();
+ ret = instantiate_rng(sec_idx);
} while ((ret == -1) && (ent_delay < RTSDCTL_ENT_DLY_MAX));
if (ret) {
printf("RNG: Failed to instantiate RNG\n");
return ret;
}
-int sec_init(void)
+int sec_init_idx(uint8_t sec_idx)
{
- ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
+ ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
uint32_t mcr = sec_in32(&sec->mcfgr);
int ret = 0;
uint32_t liodn_s;
#endif
+ if (!(sec_idx < CONFIG_SYS_FSL_MAX_NUM_OF_SEC)) {
+ printf("SEC initialization failed\n");
+ return -1;
+ }
+
/*
* Modifying CAAM Read/Write Attributes
* For LS2080A
liodn_s = (liodnr & JRSLIODN_MASK) >> JRSLIODN_SHIFT;
#endif
- ret = jr_init();
+ ret = jr_init(sec_idx);
if (ret < 0) {
printf("SEC initialization failed\n");
return -1;
pamu_enable();
#endif
- if (get_rng_vid() >= 4) {
- if (rng_init() < 0) {
- printf("RNG instantiation failed\n");
+ if (get_rng_vid(sec_idx) >= 4) {
+ if (rng_init(sec_idx) < 0) {
+ printf("SEC%u: RNG instantiation failed\n", sec_idx);
return -1;
}
- printf("SEC: RNG instantiated\n");
+ printf("SEC%u: RNG instantiated\n", sec_idx);
}
return ret;
}
+
+int sec_init(void)
+{
+ return sec_init_idx(0);
+}
/* This ring can be on the stack */
struct jr_info info[JR_SIZE];
struct op_ring *output_ring;
+ /* Offset in CCSR to the SEC engine to which this JR belongs */
+ uint32_t sec_offset;
+
};
struct result {
u32 vref_seq2[3] = {0xc0, 0xf0, 0x70}; /* for range 2 */
u32 *vref_seq = vref_seq1;
#endif
-#ifdef CONFIG_SYS_FSL_ERRATUM_A009942
+#if defined(CONFIG_SYS_FSL_ERRATUM_A009942) | \
+ defined(CONFIG_SYS_FSL_ERRATUM_A010165)
ulong ddr_freq;
u32 tmp;
#endif
/* Disable DRAM VRef training */
ddr_out32(&ddr->ddr_cdr2,
regs->ddr_cdr2 & ~DDR_CDR2_VREF_TRAIN_EN);
- /* Disable deskew */
- ddr_out32(&ddr->debug[28], 0x400);
+ /* disable transmit bit deskew */
+ temp32 = ddr_in32(&ddr->debug[28]);
+ temp32 |= DDR_TX_BD_DIS;
+ ddr_out32(&ddr->debug[28], temp32);
/* Disable D_INIT */
ddr_out32(&ddr->sdram_cfg_2,
regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT);
}
#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009801
+ temp32 = ddr_in32(&ddr->debug[25]);
+ temp32 &= ~DDR_CAS_TO_PRE_SUB_MASK;
+ temp32 |= 9 << DDR_CAS_TO_PRE_SUB_SHIFT;
+ ddr_out32(&ddr->debug[25], temp32);
+#endif
+
#ifdef CONFIG_SYS_FSL_ERRATUM_A009942
ddr_freq = get_ddr_freq(ctrl_num) / 1000000;
tmp = ddr_in32(&ddr->debug[28]);
ddr_out32(&ddr->debug[28], tmp | 0x0060007b);
#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A010165
+ ddr_freq = get_ddr_freq(ctrl_num) / 1000000;
+ if ((ddr_freq > 1900) && (ddr_freq < 2300)) {
+ tmp = ddr_in32(&ddr->debug[28]);
+ ddr_out32(&ddr->debug[28], tmp | 0x000a0000);
+ }
+#endif
/*
* For RDIMMs, JEDEC spec requires clocks to be stable before reset is
* deasserted. Clocks start when any chip select is enabled and clock
debug("MR6 = 0x%08x\n", temp32);
}
ddr_out32(&ddr->sdram_md_cntl, 0);
- ddr_out32(&ddr->debug[28], 0); /* Enable deskew */
+ temp32 = ddr_in32(&ddr->debug[28]);
+ temp32 &= ~DDR_TX_BD_DIS; /* Enable deskew */
+ ddr_out32(&ddr->debug[28], temp32);
ddr_out32(&ddr->debug[1], 0x400); /* restart deskew */
/* wait for idle */
timeout = 40;
return (device_width == 0) ? 8 : 16;
}
-float ddr3_get_device_size(u32 cs)
+static int ddr3_get_device_size(u32 cs)
{
u32 device_size_low, device_size_high, device_size;
u32 data, cs_low_offset, cs_high_offset;
switch (device_size) {
case 0:
- return 2;
+ return 2048;
case 2:
- return 0.5;
+ return 512;
case 3:
- return 1;
+ return 1024;
case 4:
- return 4;
+ return 4096;
case 5:
- return 8;
+ return 8192;
case 1:
default:
DEBUG_INIT_C("Error: Wrong device size of Cs: ", cs, 1);
* Small value will give wrong emem size in
* ddr3_calc_mem_cs_size
*/
- return 0.01;
+ return 0;
}
}
int ddr3_calc_mem_cs_size(u32 cs, u32 *cs_size)
{
- float cs_mem_size;
+ int cs_mem_size;
/* Calculate in GiB */
cs_mem_size = ((ddr3_get_bus_width() / ddr3_get_device_width(cs)) *
*/
cs_mem_size *= DDR_CONTROLLER_BUS_WIDTH_MULTIPLIER;
- if (cs_mem_size == 0.125) {
- *cs_size = 128 << 20;
- } else if (cs_mem_size == 0.25) {
- *cs_size = 256 << 20;
- } else if (cs_mem_size == 0.5) {
- *cs_size = 512 << 20;
- } else if (cs_mem_size == 1) {
- *cs_size = 1 << 30;
- } else if (cs_mem_size == 2) {
- *cs_size = 2 << 30;
- } else {
+ if (!cs_mem_size || (cs_mem_size == 64) || (cs_mem_size == 4096)) {
DEBUG_INIT_C("Error: Wrong Memory size of Cs: ", cs, 1);
return MV_BAD_VALUE;
}
+ *cs_size = cs_mem_size << 20;
return MV_OK;
}
if (dfu->data.mmc.hw_partition >= 0) {
part_num_bkp = mmc->block_dev.hwpart;
- ret = mmc_select_hwpart(dfu->data.mmc.dev_num,
- dfu->data.mmc.hw_partition);
+ ret = blk_select_hwpart_devnum(IF_TYPE_MMC,
+ dfu->data.mmc.dev_num,
+ dfu->data.mmc.hw_partition);
if (ret)
return ret;
}
if (n != blk_count) {
error("MMC operation failed");
if (dfu->data.mmc.hw_partition >= 0)
- mmc_select_hwpart(dfu->data.mmc.dev_num, part_num_bkp);
+ blk_select_hwpart_devnum(IF_TYPE_MMC,
+ dfu->data.mmc.dev_num,
+ part_num_bkp);
return -EIO;
}
if (dfu->data.mmc.hw_partition >= 0) {
- ret = mmc_select_hwpart(dfu->data.mmc.dev_num, part_num_bkp);
+ ret = blk_select_hwpart_devnum(IF_TYPE_MMC,
+ dfu->data.mmc.dev_num,
+ part_num_bkp);
if (ret)
return ret;
}
}
/*
- * fgpa_init is usually called from misc_init_r() and MUST be called
+ * fpga_init is usually called from misc_init_r() and MUST be called
* before any of the other fpga functions are used.
*/
void fpga_init(void)
--- /dev/null
+/*
+ * Take drivers/gpio/gpio-74x164.c as reference.
+ *
+ * 74Hx164 - Generic serial-in/parallel-out 8-bits shift register GPIO driver
+ *
+ * Copyright (C) 2016 Peng Fan <van.freenix@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <dm.h>
+#include <fdtdec.h>
+#include <malloc.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <spi.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * struct gen_74x164_chip - Data for 74Hx164
+ *
+ * @oe: OE pin
+ * @nregs: number of registers
+ * @buffer: buffer for chained chips
+ */
+#define GEN_74X164_NUMBER_GPIOS 8
+
+struct gen_74x164_priv {
+ struct gpio_desc oe;
+ u32 nregs;
+ /*
+ * Since the nregs are chained, every byte sent will make
+ * the previous byte shift to the next register in the
+ * chain. Thus, the first byte sent will end up in the last
+ * register at the end of the transfer. So, to have a logical
+ * numbering, store the bytes in reverse order.
+ */
+ u8 *buffer;
+};
+
+static int gen_74x164_write_conf(struct udevice *dev)
+{
+ struct gen_74x164_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ ret = dm_spi_claim_bus(dev);
+ if (ret)
+ return ret;
+
+ ret = dm_spi_xfer(dev, priv->nregs * 8, priv->buffer, NULL,
+ SPI_XFER_BEGIN | SPI_XFER_END);
+
+ dm_spi_release_bus(dev);
+
+ return ret;
+}
+
+static int gen_74x164_get_value(struct udevice *dev, unsigned offset)
+{
+ struct gen_74x164_priv *priv = dev_get_priv(dev);
+ uint bank = priv->nregs - 1 - offset / 8;
+ uint pin = offset % 8;
+
+ return (priv->buffer[bank] >> pin) & 0x1;
+}
+
+static int gen_74x164_set_value(struct udevice *dev, unsigned offset,
+ int value)
+{
+ struct gen_74x164_priv *priv = dev_get_priv(dev);
+ uint bank = priv->nregs - 1 - offset / 8;
+ uint pin = offset % 8;
+ int ret;
+
+ if (value)
+ priv->buffer[bank] |= 1 << pin;
+ else
+ priv->buffer[bank] &= ~(1 << pin);
+
+ ret = gen_74x164_write_conf(dev);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static int gen_74x164_direction_input(struct udevice *dev, unsigned offset)
+{
+ return -ENOSYS;
+}
+
+static int gen_74x164_direction_output(struct udevice *dev, unsigned offset,
+ int value)
+{
+ return gen_74x164_set_value(dev, offset, value);
+}
+
+static int gen_74x164_get_function(struct udevice *dev, unsigned offset)
+{
+ return GPIOF_OUTPUT;
+}
+
+static int gen_74x164_xlate(struct udevice *dev, struct gpio_desc *desc,
+ struct fdtdec_phandle_args *args)
+{
+ desc->offset = args->args[0];
+ desc->flags = args->args[1] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0;
+
+ return 0;
+}
+
+static const struct dm_gpio_ops gen_74x164_ops = {
+ .direction_input = gen_74x164_direction_input,
+ .direction_output = gen_74x164_direction_output,
+ .get_value = gen_74x164_get_value,
+ .set_value = gen_74x164_set_value,
+ .get_function = gen_74x164_get_function,
+ .xlate = gen_74x164_xlate,
+};
+
+static int gen_74x164_probe(struct udevice *dev)
+{
+ struct gen_74x164_priv *priv = dev_get_priv(dev);
+ struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+ char *str, name[32];
+ int ret;
+ const void *fdt = gd->fdt_blob;
+ int node = dev->of_offset;
+
+ snprintf(name, sizeof(name), "%s_", dev->name);
+ str = strdup(name);
+ if (!str)
+ return -ENOMEM;
+
+ /*
+ * See Linux kernel:
+ * Documentation/devicetree/bindings/gpio/gpio-74x164.txt
+ */
+ priv->nregs = fdtdec_get_int(fdt, node, "registers-number", 1);
+ priv->buffer = calloc(priv->nregs, sizeof(u8));
+ if (!priv->buffer) {
+ ret = -ENOMEM;
+ goto free_str;
+ }
+
+ ret = fdtdec_get_byte_array(fdt, node, "registers-default",
+ priv->buffer, priv->nregs);
+ if (ret)
+ dev_dbg(dev, "No registers-default property\n");
+
+ ret = gpio_request_by_name(dev, "oe-gpios", 0, &priv->oe,
+ GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
+ if (ret) {
+ dev_err(dev, "No oe-pins property\n");
+ goto free_buf;
+ }
+
+ uc_priv->bank_name = str;
+ uc_priv->gpio_count = priv->nregs * 8;
+
+ ret = gen_74x164_write_conf(dev);
+ if (ret)
+ goto free_buf;
+
+ dev_dbg(dev, "%s is ready\n", dev->name);
+
+ return 0;
+
+free_buf:
+ free(priv->buffer);
+free_str:
+ free(str);
+ return ret;
+}
+
+static const struct udevice_id gen_74x164_ids[] = {
+ { .compatible = "fairchild,74hc595" },
+ { }
+};
+
+U_BOOT_DRIVER(74x164) = {
+ .name = "74x164",
+ .id = UCLASS_GPIO,
+ .ops = &gen_74x164_ops,
+ .probe = gen_74x164_probe,
+ .priv_auto_alloc_size = sizeof(struct gen_74x164_priv),
+ .of_match = gen_74x164_ids,
+};
help
Supports GPIO access on Zynq SoC.
+config DM_74X164
+ bool "74x164 serial-in/parallel-out 8-bits shift register"
+ depends on DM_GPIO
+ help
+ Driver for 74x164 compatible serial-in/parallel-out 8-outputs
+ shift registers, such as 74lv165, 74hc595.
+ This driver can be used to provide access to more gpio outputs.
+
+config DM_PCA953X
+ bool "PCA95[357]x, PCA9698, TCA64xx, and MAX7310 I/O ports"
+ depends on DM_GPIO
+ help
+ Say yes here to provide access to several register-oriented
+ SMBus I/O expanders, made mostly by NXP or TI. Compatible
+ models include:
+
+ 4 bits: pca9536, pca9537
+
+ 8 bits: max7310, max7315, pca6107, pca9534, pca9538, pca9554,
+ pca9556, pca9557, pca9574, tca6408, xra1202
+
+ 16 bits: max7312, max7313, pca9535, pca9539, pca9555, pca9575,
+ tca6416
+
+ 24 bits: tca6424
+
+ 40 bits: pca9505, pca9698
+
+ Now, max 24 bits chips and PCA953X compatible chips are
+ supported
endmenu
endif
obj-$(CONFIG_DM_GPIO) += gpio-uclass.o
+obj-$(CONFIG_DM_PCA953X) += pca953x_gpio.o
+obj-$(CONFIG_DM_74X164) += 74x164_gpio.o
+
obj-$(CONFIG_AT91_GPIO) += at91_gpio.o
obj-$(CONFIG_ATMEL_PIO4) += atmel_pio4.o
obj-$(CONFIG_INTEL_ICH6_GPIO) += intel_ich6_gpio.o
#include <common.h>
#include <dm.h>
+#include <dt-bindings/gpio/gpio.h>
#include <errno.h>
#include <fdtdec.h>
#include <malloc.h>
return 0;
}
+int gpio_xlate_offs_flags(struct udevice *dev,
+ struct gpio_desc *desc,
+ struct fdtdec_phandle_args *args)
+{
+ if (args->args_count < 1)
+ return -EINVAL;
+
+ desc->offset = args->args[0];
+
+ if (args->args_count < 2)
+ return 0;
+
+ if (args->args[1] & GPIO_ACTIVE_LOW)
+ desc->flags = GPIOD_ACTIVE_LOW;
+
+ return 0;
+}
+
static int gpio_find_and_xlate(struct gpio_desc *desc,
struct fdtdec_phandle_args *args)
{
struct dm_gpio_ops *ops = gpio_get_ops(desc->dev);
- /* Use the first argument as the offset by default */
- if (args->args_count > 0)
- desc->offset = args->args[0];
+ if (ops->xlate)
+ return ops->xlate(desc->dev, desc, args);
else
- desc->offset = -1;
- desc->flags = 0;
-
- return ops->xlate ? ops->xlate(desc->dev, desc, args) : 0;
+ return gpio_xlate_offs_flags(desc->dev, desc, args);
}
int dm_gpio_request(struct gpio_desc *desc, const char *label)
desc->dev = NULL;
desc->offset = 0;
+ desc->flags = 0;
ret = fdtdec_parse_phandle_with_args(blob, node, list_name,
"#gpio-cells", 0, index, &args);
if (ret) {
return 0;
}
-static int broadwell_gpio_xlate(struct udevice *dev, struct gpio_desc *desc,
- struct fdtdec_phandle_args *args)
-{
- desc->offset = args->args[0];
- desc->flags = args->args[1] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0;
-
- return 0;
-}
-
static const struct dm_gpio_ops gpio_broadwell_ops = {
.request = broadwell_gpio_request,
.direction_input = broadwell_gpio_direction_input,
.get_value = broadwell_gpio_get_value,
.set_value = broadwell_gpio_set_value,
.get_function = broadwell_gpio_get_function,
- .xlate = broadwell_gpio_xlate,
};
static const struct udevice_id intel_broadwell_gpio_ids[] = {
#include <asm/io.h>
#include <asm/errno.h>
#include <malloc.h>
-#include <dt-bindings/gpio/gpio.h>
DECLARE_GLOBAL_DATA_PTR;
return GPIOF_INPUT;
}
-static int omap_gpio_xlate(struct udevice *dev, struct gpio_desc *desc,
- struct fdtdec_phandle_args *args)
-{
- desc->offset = args->args[0];
- desc->flags = args->args[1] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0;
-
- return 0;
-}
-
static const struct dm_gpio_ops gpio_omap_ops = {
.direction_input = omap_gpio_direction_input,
.direction_output = omap_gpio_direction_output,
.get_value = omap_gpio_get_value,
.set_value = omap_gpio_set_value,
.get_function = omap_gpio_get_function,
- .xlate = omap_gpio_xlate,
};
static int omap_gpio_probe(struct udevice *dev)
--- /dev/null
+/*
+ * Take linux kernel driver drivers/gpio/gpio-pca953x.c for reference.
+ *
+ * Copyright (C) 2016 Peng Fan <van.freenix@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ */
+
+/*
+ * Note:
+ * The driver's compatible table is borrowed from Linux Kernel,
+ * but now max supported gpio pins is 24 and only PCA953X_TYPE
+ * is supported. PCA957X_TYPE is not supported now.
+ * Also the Polarity Inversion feature is not supported now.
+ *
+ * TODO:
+ * 1. Support PCA957X_TYPE
+ * 2. Support max 40 gpio pins
+ * 3. Support Plolarity Inversion
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <dm.h>
+#include <fdtdec.h>
+#include <i2c.h>
+#include <malloc.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <dt-bindings/gpio/gpio.h>
+
+#define PCA953X_INPUT 0
+#define PCA953X_OUTPUT 1
+#define PCA953X_INVERT 2
+#define PCA953X_DIRECTION 3
+
+#define PCA_GPIO_MASK 0x00FF
+#define PCA_INT 0x0100
+#define PCA953X_TYPE 0x1000
+#define PCA957X_TYPE 0x2000
+#define PCA_TYPE_MASK 0xF000
+#define PCA_CHIP_TYPE(x) ((x) & PCA_TYPE_MASK)
+
+enum {
+ PCA953X_DIRECTION_IN,
+ PCA953X_DIRECTION_OUT,
+};
+
+#define MAX_BANK 3
+#define BANK_SZ 8
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * struct pca953x_info - Data for pca953x
+ *
+ * @dev: udevice structure for the device
+ * @addr: i2c slave address
+ * @invert: Polarity inversion or not
+ * @gpio_count: the number of gpio pins that the device supports
+ * @chip_type: indicate the chip type,PCA953X or PCA957X
+ * @bank_count: the number of banks that the device supports
+ * @reg_output: array to hold the value of output registers
+ * @reg_direction: array to hold the value of direction registers
+ */
+struct pca953x_info {
+ struct udevice *dev;
+ int addr;
+ int invert;
+ int gpio_count;
+ int chip_type;
+ int bank_count;
+ u8 reg_output[MAX_BANK];
+ u8 reg_direction[MAX_BANK];
+};
+
+static int pca953x_write_single(struct udevice *dev, int reg, u8 val,
+ int offset)
+{
+ struct pca953x_info *info = dev_get_platdata(dev);
+ int bank_shift = fls((info->gpio_count - 1) / BANK_SZ);
+ int off = offset / BANK_SZ;
+ int ret = 0;
+
+ ret = dm_i2c_write(dev, (reg << bank_shift) + off, &val, 1);
+ if (ret) {
+ dev_err(dev, "%s error\n", __func__);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int pca953x_read_single(struct udevice *dev, int reg, u8 *val,
+ int offset)
+{
+ struct pca953x_info *info = dev_get_platdata(dev);
+ int bank_shift = fls((info->gpio_count - 1) / BANK_SZ);
+ int off = offset / BANK_SZ;
+ int ret;
+ u8 byte;
+
+ ret = dm_i2c_read(dev, (reg << bank_shift) + off, &byte, 1);
+ if (ret) {
+ dev_err(dev, "%s error\n", __func__);
+ return ret;
+ }
+
+ *val = byte;
+
+ return 0;
+}
+
+static int pca953x_read_regs(struct udevice *dev, int reg, u8 *val)
+{
+ struct pca953x_info *info = dev_get_platdata(dev);
+ int ret = 0;
+
+ if (info->gpio_count <= 8) {
+ ret = dm_i2c_read(dev, reg, val, 1);
+ } else if (info->gpio_count <= 16) {
+ ret = dm_i2c_read(dev, reg << 1, val, info->bank_count);
+ } else {
+ dev_err(dev, "Unsupported now\n");
+ return -EINVAL;
+ }
+
+ return ret;
+}
+
+static int pca953x_is_output(struct udevice *dev, int offset)
+{
+ struct pca953x_info *info = dev_get_platdata(dev);
+
+ int bank = offset / BANK_SZ;
+ int off = offset % BANK_SZ;
+
+ /*0: output; 1: input */
+ return !(info->reg_direction[bank] & (1 << off));
+}
+
+static int pca953x_get_value(struct udevice *dev, unsigned offset)
+{
+ int ret;
+ u8 val = 0;
+
+ ret = pca953x_read_single(dev, PCA953X_INPUT, &val, offset);
+ if (ret)
+ return ret;
+
+ return (val >> offset) & 0x1;
+}
+
+static int pca953x_set_value(struct udevice *dev, unsigned offset,
+ int value)
+{
+ struct pca953x_info *info = dev_get_platdata(dev);
+ int bank = offset / BANK_SZ;
+ int off = offset % BANK_SZ;
+ u8 val;
+ int ret;
+
+ if (value)
+ val = info->reg_output[bank] | (1 << off);
+ else
+ val = info->reg_output[bank] & ~(1 << off);
+
+ ret = pca953x_write_single(dev, PCA953X_OUTPUT, val, offset);
+ if (ret)
+ return ret;
+
+ info->reg_output[bank] = val;
+
+ return 0;
+}
+
+static int pca953x_set_direction(struct udevice *dev, unsigned offset, int dir)
+{
+ struct pca953x_info *info = dev_get_platdata(dev);
+ int bank = offset / BANK_SZ;
+ int off = offset % BANK_SZ;
+ u8 val;
+ int ret;
+
+ if (dir == PCA953X_DIRECTION_IN)
+ val = info->reg_direction[bank] | (1 << off);
+ else
+ val = info->reg_direction[bank] & ~(1 << off);
+
+ ret = pca953x_write_single(dev, PCA953X_DIRECTION, val, offset);
+ if (ret)
+ return ret;
+
+ info->reg_direction[bank] = val;
+
+ return 0;
+}
+
+static int pca953x_direction_input(struct udevice *dev, unsigned offset)
+{
+ return pca953x_set_direction(dev, offset, PCA953X_DIRECTION_IN);
+}
+
+static int pca953x_direction_output(struct udevice *dev, unsigned offset,
+ int value)
+{
+ /* Configure output value. */
+ pca953x_set_value(dev, offset, value);
+
+ /* Configure direction as output. */
+ pca953x_set_direction(dev, offset, PCA953X_DIRECTION_OUT);
+
+ return 0;
+}
+
+static int pca953x_get_function(struct udevice *dev, unsigned offset)
+{
+ if (pca953x_is_output(dev, offset))
+ return GPIOF_OUTPUT;
+ else
+ return GPIOF_INPUT;
+}
+
+static int pca953x_xlate(struct udevice *dev, struct gpio_desc *desc,
+ struct fdtdec_phandle_args *args)
+{
+ desc->offset = args->args[0];
+ desc->flags = args->args[1] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0;
+
+ return 0;
+}
+
+static const struct dm_gpio_ops pca953x_ops = {
+ .direction_input = pca953x_direction_input,
+ .direction_output = pca953x_direction_output,
+ .get_value = pca953x_get_value,
+ .set_value = pca953x_set_value,
+ .get_function = pca953x_get_function,
+ .xlate = pca953x_xlate,
+};
+
+static int pca953x_probe(struct udevice *dev)
+{
+ struct pca953x_info *info = dev_get_platdata(dev);
+ struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+ struct dm_i2c_chip *chip = dev_get_parent_platdata(dev);
+ char name[32], *str;
+ int addr;
+ ulong driver_data;
+ int ret;
+
+ if (!info) {
+ dev_err(dev, "platdata not ready\n");
+ return -ENOMEM;
+ }
+
+ if (!chip) {
+ dev_err(dev, "i2c not ready\n");
+ return -ENODEV;
+ }
+
+ addr = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "reg", 0);
+ if (addr == 0)
+ return -ENODEV;
+
+ info->addr = addr;
+
+ driver_data = dev_get_driver_data(dev);
+
+ info->gpio_count = driver_data & PCA_GPIO_MASK;
+ if (info->gpio_count > MAX_BANK * BANK_SZ) {
+ dev_err(dev, "Max support %d pins now\n", MAX_BANK * BANK_SZ);
+ return -EINVAL;
+ }
+
+ info->chip_type = PCA_CHIP_TYPE(driver_data);
+ if (info->chip_type != PCA953X_TYPE) {
+ dev_err(dev, "Only support PCA953X chip type now.\n");
+ return -EINVAL;
+ }
+
+ info->bank_count = DIV_ROUND_UP(info->gpio_count, BANK_SZ);
+
+ ret = pca953x_read_regs(dev, PCA953X_OUTPUT, info->reg_output);
+ if (ret) {
+ dev_err(dev, "Error reading output register\n");
+ return ret;
+ }
+
+ ret = pca953x_read_regs(dev, PCA953X_DIRECTION, info->reg_direction);
+ if (ret) {
+ dev_err(dev, "Error reading direction register\n");
+ return ret;
+ }
+
+ snprintf(name, sizeof(name), "gpio@%x_", info->addr);
+ str = strdup(name);
+ if (!str)
+ return -ENOMEM;
+ uc_priv->bank_name = str;
+ uc_priv->gpio_count = info->gpio_count;
+
+ dev_dbg(dev, "%s is ready\n", str);
+
+ return 0;
+}
+
+#define OF_953X(__nrgpio, __int) (ulong)(__nrgpio | PCA953X_TYPE | __int)
+#define OF_957X(__nrgpio, __int) (ulong)(__nrgpio | PCA957X_TYPE | __int)
+
+static const struct udevice_id pca953x_ids[] = {
+ { .compatible = "nxp,pca9505", .data = OF_953X(40, PCA_INT), },
+ { .compatible = "nxp,pca9534", .data = OF_953X(8, PCA_INT), },
+ { .compatible = "nxp,pca9535", .data = OF_953X(16, PCA_INT), },
+ { .compatible = "nxp,pca9536", .data = OF_953X(4, 0), },
+ { .compatible = "nxp,pca9537", .data = OF_953X(4, PCA_INT), },
+ { .compatible = "nxp,pca9538", .data = OF_953X(8, PCA_INT), },
+ { .compatible = "nxp,pca9539", .data = OF_953X(16, PCA_INT), },
+ { .compatible = "nxp,pca9554", .data = OF_953X(8, PCA_INT), },
+ { .compatible = "nxp,pca9555", .data = OF_953X(16, PCA_INT), },
+ { .compatible = "nxp,pca9556", .data = OF_953X(8, 0), },
+ { .compatible = "nxp,pca9557", .data = OF_953X(8, 0), },
+ { .compatible = "nxp,pca9574", .data = OF_957X(8, PCA_INT), },
+ { .compatible = "nxp,pca9575", .data = OF_957X(16, PCA_INT), },
+ { .compatible = "nxp,pca9698", .data = OF_953X(40, 0), },
+
+ { .compatible = "maxim,max7310", .data = OF_953X(8, 0), },
+ { .compatible = "maxim,max7312", .data = OF_953X(16, PCA_INT), },
+ { .compatible = "maxim,max7313", .data = OF_953X(16, PCA_INT), },
+ { .compatible = "maxim,max7315", .data = OF_953X(8, PCA_INT), },
+
+ { .compatible = "ti,pca6107", .data = OF_953X(8, PCA_INT), },
+ { .compatible = "ti,tca6408", .data = OF_953X(8, PCA_INT), },
+ { .compatible = "ti,tca6416", .data = OF_953X(16, PCA_INT), },
+ { .compatible = "ti,tca6424", .data = OF_953X(24, PCA_INT), },
+
+ { .compatible = "onsemi,pca9654", .data = OF_953X(8, PCA_INT), },
+
+ { .compatible = "exar,xra1202", .data = OF_953X(8, 0), },
+ { }
+};
+
+U_BOOT_DRIVER(pca953x) = {
+ .name = "pca953x",
+ .id = UCLASS_GPIO,
+ .ops = &pca953x_ops,
+ .probe = pca953x_probe,
+ .platdata_auto_alloc_size = sizeof(struct pca953x_info),
+ .of_match = pca953x_ids,
+};
#include <asm/io.h>
#include <asm/gpio.h>
#include <linux/compat.h>
-#include <dt-bindings/gpio/gpio.h>
#include <mach/pic32.h>
DECLARE_GLOBAL_DATA_PTR;
return 0;
}
-static int pic32_gpio_xlate(struct udevice *dev, struct gpio_desc *desc,
- struct fdtdec_phandle_args *args)
-{
- desc->flags = args->args[1] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0;
-
- return 0;
-}
-
static int pic32_gpio_get_function(struct udevice *dev, unsigned offset)
{
int ret = GPIOF_UNUSED;
.get_value = pic32_gpio_get_value,
.set_value = pic32_gpio_set_value,
.get_function = pic32_gpio_get_function,
- .xlate = pic32_gpio_xlate,
};
static int pic32_gpio_probe(struct udevice *dev)
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <dm/pinctrl.h>
-#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clock/rk3288-cru.h>
enum {
#endif
}
-static int rockchip_gpio_xlate(struct udevice *dev, struct gpio_desc *desc,
- struct fdtdec_phandle_args *args)
-{
- desc->offset = args->args[0];
- desc->flags = args->args[1] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0;
-
- return 0;
-}
-
static int rockchip_gpio_probe(struct udevice *dev)
{
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
.get_value = rockchip_gpio_get_value,
.set_value = rockchip_gpio_set_value,
.get_function = rockchip_gpio_get_function,
- .xlate = rockchip_gpio_xlate,
};
static const struct udevice_id rockchip_gpio_ids[] = {
#include <asm/io.h>
#include <asm/gpio.h>
#include <dm/device-internal.h>
-#include <dt-bindings/gpio/gpio.h>
DECLARE_GLOBAL_DATA_PTR;
return GPIOF_FUNC;
}
-static int exynos_gpio_xlate(struct udevice *dev, struct gpio_desc *desc,
- struct fdtdec_phandle_args *args)
-{
- desc->offset = args->args[0];
- desc->flags = args->args[1] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0;
-
- return 0;
-}
-
static const struct dm_gpio_ops gpio_exynos_ops = {
.direction_input = exynos_gpio_direction_input,
.direction_output = exynos_gpio_direction_output,
.get_value = exynos_gpio_get_value,
.set_value = exynos_gpio_set_value,
.get_function = exynos_gpio_get_function,
- .xlate = exynos_gpio_xlate,
};
static int gpio_exynos_probe(struct udevice *dev)
return 0;
}
+static int zynq_gpio_get_function(struct udevice *dev, unsigned offset)
+{
+ u32 reg;
+ unsigned int bank_num, bank_pin_num;
+ struct zynq_gpio_privdata *priv = dev_get_priv(dev);
+
+ if (check_gpio(offset, dev) < 0)
+ return -1;
+
+ zynq_gpio_get_bank_pin(offset, &bank_num, &bank_pin_num, dev);
+
+ /* set the GPIO pin as output */
+ reg = readl(priv->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
+ reg &= BIT(bank_pin_num);
+ if (reg)
+ return GPIOF_OUTPUT;
+ else
+ return GPIOF_INPUT;
+}
+
static const struct dm_gpio_ops gpio_zynq_ops = {
.direction_input = zynq_gpio_direction_input,
.direction_output = zynq_gpio_direction_output,
.get_value = zynq_gpio_get_value,
.set_value = zynq_gpio_set_value,
+ .get_function = zynq_gpio_get_function,
+
};
static const struct udevice_id zynq_gpio_ids[] = {
bindings are supported.
Binding info: doc/device-tree-bindings/i2c/i2c-gpio.txt
+config SYS_I2C_FSL
+ bool "Freescale I2C bus driver"
+ depends on DM_I2C
+ help
+ Add support for Freescale I2C busses as used on MPC8240, MPC8245, and
+ MPC85xx processors.
+
config SYS_I2C_CADENCE
tristate "Cadence I2C Controller"
depends on DM_I2C && (ARCH_ZYNQ || ARM64)
Say yes here to select Cadence I2C Host Controller. This controller is
e.g. used by Xilinx Zynq.
+config SYS_I2C_DW
+ bool "Designware I2C Controller"
+ default n
+ help
+ Say yes here to select the Designware I2C Host Controller. This
+ controller is used in various SoCs, e.g. the ST SPEAr, Altera
+ SoCFPGA, Synopsys ARC700 and some Intel x86 SoCs.
+
+config SYS_I2C_DW_ENABLE_STATUS_UNSUPPORTED
+ bool "DW I2C Enable Status Register not supported"
+ depends on SYS_I2C_DW && (TARGET_SPEAR300 || TARGET_SPEAR310 || \
+ TARGET_SPEAR320 || TARGET_SPEAR600 || TARGET_X600)
+ default y
+ help
+ Some versions of the Designware I2C controller do not support the
+ enable status register. This config option can be enabled in such
+ cases.
+
config SYS_I2C_INTEL
bool "Intel I2C/SMBUS driver"
depends on DM_I2C
struct dw_scl_sda_cfg *scl_sda_cfg;
};
+#ifdef CONFIG_SYS_I2C_DW_ENABLE_STATUS_UNSUPPORTED
+static void dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
+{
+ u32 ena = enable ? IC_ENABLE_0B : 0;
+
+ writel(ena, &i2c_base->ic_enable);
+}
+#else
static void dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
{
u32 ena = enable ? IC_ENABLE_0B : 0;
printf("timeout in %sabling I2C adapter\n", enable ? "en" : "dis");
}
+#endif
/*
* i2c_set_bus_speed - Set the i2c speed
#include <i2c.h> /* Functional interface */
#include <asm/io.h>
#include <asm/fsl_i2c.h> /* HW definitions */
+#include <dm.h>
+#include <mapmem.h>
/* The maximum number of microseconds we will wait until another master has
* released the bus. If not defined in the board header file, then use a
DECLARE_GLOBAL_DATA_PTR;
-static const struct fsl_i2c *i2c_dev[4] = {
- (struct fsl_i2c *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C_OFFSET),
+#ifndef CONFIG_DM_I2C
+static const struct fsl_i2c_base *i2c_base[4] = {
+ (struct fsl_i2c_base *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C_OFFSET),
#ifdef CONFIG_SYS_FSL_I2C2_OFFSET
- (struct fsl_i2c *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C2_OFFSET),
+ (struct fsl_i2c_base *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C2_OFFSET),
#endif
#ifdef CONFIG_SYS_FSL_I2C3_OFFSET
- (struct fsl_i2c *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C3_OFFSET),
+ (struct fsl_i2c_base *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C3_OFFSET),
#endif
#ifdef CONFIG_SYS_FSL_I2C4_OFFSET
- (struct fsl_i2c *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C4_OFFSET)
+ (struct fsl_i2c_base *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C4_OFFSET)
#endif
};
+#endif
/* I2C speed map for a DFSR value of 1 */
/**
* Set the I2C bus speed for a given I2C device
*
- * @param dev: the I2C device
+ * @param base: the I2C device registers
* @i2c_clk: I2C bus clock frequency
* @speed: the desired speed of the bus
*
*
* The return value is the actual bus speed that is set.
*/
-static unsigned int set_i2c_bus_speed(const struct fsl_i2c *dev,
+static unsigned int set_i2c_bus_speed(const struct fsl_i2c_base *base,
unsigned int i2c_clk, unsigned int speed)
{
unsigned short divider = min(i2c_clk / speed, (unsigned int)USHRT_MAX);
debug("divider:%d, est_div:%ld, DFSR:%d\n", divider, est_div, dfsr);
debug("FDR:0x%.2x, speed:%d\n", fdr, speed);
#endif
- writeb(dfsr, &dev->dfsrr); /* set default filter */
- writeb(fdr, &dev->fdr); /* set bus speed */
+ writeb(dfsr, &base->dfsrr); /* set default filter */
+ writeb(fdr, &base->fdr); /* set bus speed */
#else
unsigned int i;
fdr = fsl_i2c_speed_map[i].fdr;
speed = i2c_clk / fsl_i2c_speed_map[i].divider;
- writeb(fdr, &dev->fdr); /* set bus speed */
+ writeb(fdr, &base->fdr); /* set bus speed */
break;
}
return speed;
}
+#ifndef CONFIG_DM_I2C
static unsigned int get_i2c_clock(int bus)
{
if (bus)
else
return gd->arch.i2c1_clk; /* I2C1 clock */
}
+#endif
-static int fsl_i2c_fixup(const struct fsl_i2c *dev)
+static int fsl_i2c_fixup(const struct fsl_i2c_base *base)
{
const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT);
unsigned long long timeval = 0;
flags = I2C_CR_BIT6;
#endif
- writeb(I2C_CR_MEN | I2C_CR_MSTA, &dev->cr);
+ writeb(I2C_CR_MEN | I2C_CR_MSTA, &base->cr);
timeval = get_ticks();
- while (!(readb(&dev->sr) & I2C_SR_MBB)) {
+ while (!(readb(&base->sr) & I2C_SR_MBB)) {
if ((get_ticks() - timeval) > timeout)
goto err;
}
- if (readb(&dev->sr) & I2C_SR_MAL) {
+ if (readb(&base->sr) & I2C_SR_MAL) {
/* SDA is stuck low */
- writeb(0, &dev->cr);
+ writeb(0, &base->cr);
udelay(100);
- writeb(I2C_CR_MSTA | flags, &dev->cr);
- writeb(I2C_CR_MEN | I2C_CR_MSTA | flags, &dev->cr);
+ writeb(I2C_CR_MSTA | flags, &base->cr);
+ writeb(I2C_CR_MEN | I2C_CR_MSTA | flags, &base->cr);
}
- readb(&dev->dr);
+ readb(&base->dr);
timeval = get_ticks();
- while (!(readb(&dev->sr) & I2C_SR_MIF)) {
+ while (!(readb(&base->sr) & I2C_SR_MIF)) {
if ((get_ticks() - timeval) > timeout)
goto err;
}
ret = 0;
err:
- writeb(I2C_CR_MEN | flags, &dev->cr);
- writeb(0, &dev->sr);
+ writeb(I2C_CR_MEN | flags, &base->cr);
+ writeb(0, &base->sr);
udelay(100);
return ret;
}
-static void fsl_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
+static void __i2c_init(const struct fsl_i2c_base *base, int speed, int
+ slaveadd, int i2c_clk, int busnum)
{
- const struct fsl_i2c *dev;
const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT);
unsigned long long timeval;
*/
i2c_init_board();
#endif
- dev = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
-
- writeb(0, &dev->cr); /* stop I2C controller */
+ writeb(0, &base->cr); /* stop I2C controller */
udelay(5); /* let it shutdown in peace */
- set_i2c_bus_speed(dev, get_i2c_clock(adap->hwadapnr), speed);
- writeb(slaveadd << 1, &dev->adr);/* write slave address */
- writeb(0x0, &dev->sr); /* clear status register */
- writeb(I2C_CR_MEN, &dev->cr); /* start I2C controller */
+ set_i2c_bus_speed(base, i2c_clk, speed);
+ writeb(slaveadd << 1, &base->adr);/* write slave address */
+ writeb(0x0, &base->sr); /* clear status register */
+ writeb(I2C_CR_MEN, &base->cr); /* start I2C controller */
timeval = get_ticks();
- while (readb(&dev->sr) & I2C_SR_MBB) {
+ while (readb(&base->sr) & I2C_SR_MBB) {
if ((get_ticks() - timeval) < timeout)
continue;
- if (fsl_i2c_fixup(dev))
+ if (fsl_i2c_fixup(base))
debug("i2c_init: BUS#%d failed to init\n",
- adap->hwadapnr);
+ busnum);
break;
}
}
static int
-i2c_wait4bus(struct i2c_adapter *adap)
+i2c_wait4bus(const struct fsl_i2c_base *base)
{
- struct fsl_i2c *dev = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
unsigned long long timeval = get_ticks();
const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT);
- while (readb(&dev->sr) & I2C_SR_MBB) {
+ while (readb(&base->sr) & I2C_SR_MBB) {
if ((get_ticks() - timeval) > timeout)
return -1;
}
return 0;
}
-static __inline__ int
-i2c_wait(struct i2c_adapter *adap, int write)
+static inline int
+i2c_wait(const struct fsl_i2c_base *base, int write)
{
u32 csr;
unsigned long long timeval = get_ticks();
const unsigned long long timeout = usec2ticks(CONFIG_I2C_TIMEOUT);
- struct fsl_i2c *dev = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
do {
- csr = readb(&dev->sr);
+ csr = readb(&base->sr);
if (!(csr & I2C_SR_MIF))
continue;
/* Read again to allow register to stabilise */
- csr = readb(&dev->sr);
+ csr = readb(&base->sr);
- writeb(0x0, &dev->sr);
+ writeb(0x0, &base->sr);
if (csr & I2C_SR_MAL) {
debug("i2c_wait: MAL\n");
return -1;
}
-static __inline__ int
-i2c_write_addr(struct i2c_adapter *adap, u8 dev, u8 dir, int rsta)
+static inline int
+i2c_write_addr(const struct fsl_i2c_base *base, u8 dev, u8 dir, int rsta)
{
- struct fsl_i2c *device = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
-
writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX
| (rsta ? I2C_CR_RSTA : 0),
- &device->cr);
+ &base->cr);
- writeb((dev << 1) | dir, &device->dr);
+ writeb((dev << 1) | dir, &base->dr);
- if (i2c_wait(adap, I2C_WRITE_BIT) < 0)
+ if (i2c_wait(base, I2C_WRITE_BIT) < 0)
return 0;
return 1;
}
-static __inline__ int
-__i2c_write(struct i2c_adapter *adap, u8 *data, int length)
+static inline int
+__i2c_write_data(const struct fsl_i2c_base *base, u8 *data, int length)
{
- struct fsl_i2c *dev = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
int i;
for (i = 0; i < length; i++) {
- writeb(data[i], &dev->dr);
+ writeb(data[i], &base->dr);
- if (i2c_wait(adap, I2C_WRITE_BIT) < 0)
+ if (i2c_wait(base, I2C_WRITE_BIT) < 0)
break;
}
return i;
}
-static __inline__ int
-__i2c_read(struct i2c_adapter *adap, u8 *data, int length)
+static inline int
+__i2c_read_data(const struct fsl_i2c_base *base, u8 *data, int length)
{
- struct fsl_i2c *dev = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
int i;
writeb(I2C_CR_MEN | I2C_CR_MSTA | ((length == 1) ? I2C_CR_TXAK : 0),
- &dev->cr);
+ &base->cr);
/* dummy read */
- readb(&dev->dr);
+ readb(&base->dr);
for (i = 0; i < length; i++) {
- if (i2c_wait(adap, I2C_READ_BIT) < 0)
+ if (i2c_wait(base, I2C_READ_BIT) < 0)
break;
/* Generate ack on last next to last byte */
if (i == length - 2)
writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_TXAK,
- &dev->cr);
+ &base->cr);
/* Do not generate stop on last byte */
if (i == length - 1)
writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX,
- &dev->cr);
+ &base->cr);
- data[i] = readb(&dev->dr);
+ data[i] = readb(&base->dr);
}
return i;
}
static int
-fsl_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr, int alen, u8 *data,
- int length)
+__i2c_read(const struct fsl_i2c_base *base, u8 chip_addr, u8 *offset, int olen,
+ u8 *data, int dlen)
{
- struct fsl_i2c *device = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
- int i = -1; /* signal error */
- u8 *a = (u8*)&addr;
- int len = alen * -1;
+ int ret = -1; /* signal error */
- if (i2c_wait4bus(adap) < 0)
+ if (i2c_wait4bus(base) < 0)
return -1;
- /* To handle the need of I2C devices that require to write few bytes
- * (more than 4 bytes of address as in the case of else part)
- * of data before reading, Negative equivalent of length(bytes to write)
- * is passed, but used the +ve part of len for writing data
+ /* Some drivers use offset lengths in excess of 4 bytes. These drivers
+ * adhere to the following convention:
+ * - the offset length is passed as negative (that is, the absolute
+ * value of olen is the actual offset length)
+ * - the offset itself is passed in data, which is overwritten by the
+ * subsequent read operation
*/
- if (alen < 0) {
- /* Generate a START and send the Address and
- * the Tx Bytes to the slave.
- * "START: Address: Write bytes data[len]"
- * IF part supports writing any number of bytes in contrast
- * to the else part, which supports writing address offset
- * of upto 4 bytes only.
- * bytes that need to be written are passed in
- * "data", which will eventually keep the data READ,
- * after writing the len bytes out of it
- */
- if (i2c_write_addr(adap, dev, I2C_WRITE_BIT, 0) != 0)
- i = __i2c_write(adap, data, len);
-
- if (i != len)
+ if (olen < 0) {
+ if (i2c_write_addr(base, chip_addr, I2C_WRITE_BIT, 0) != 0)
+ ret = __i2c_write_data(base, data, -olen);
+
+ if (ret != -olen)
return -1;
- if (length && i2c_write_addr(adap, dev, I2C_READ_BIT, 1) != 0)
- i = __i2c_read(adap, data, length);
+ if (dlen && i2c_write_addr(base, chip_addr,
+ I2C_READ_BIT, 1) != 0)
+ ret = __i2c_read_data(base, data, dlen);
} else {
- if ((!length || alen > 0) &&
- i2c_write_addr(adap, dev, I2C_WRITE_BIT, 0) != 0 &&
- __i2c_write(adap, &a[4 - alen], alen) == alen)
- i = 0; /* No error so far */
-
- if (length &&
- i2c_write_addr(adap, dev, I2C_READ_BIT, alen ? 1 : 0) != 0)
- i = __i2c_read(adap, data, length);
+ if ((!dlen || olen > 0) &&
+ i2c_write_addr(base, chip_addr, I2C_WRITE_BIT, 0) != 0 &&
+ __i2c_write_data(base, offset, olen) == olen)
+ ret = 0; /* No error so far */
+
+ if (dlen && i2c_write_addr(base, chip_addr, I2C_READ_BIT,
+ olen ? 1 : 0) != 0)
+ ret = __i2c_read_data(base, data, dlen);
}
- writeb(I2C_CR_MEN, &device->cr);
+ writeb(I2C_CR_MEN, &base->cr);
- if (i2c_wait4bus(adap)) /* Wait until STOP */
+ if (i2c_wait4bus(base)) /* Wait until STOP */
debug("i2c_read: wait4bus timed out\n");
- if (i == length)
- return 0;
+ if (ret == dlen)
+ return 0;
return -1;
}
static int
-fsl_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr, int alen,
- u8 *data, int length)
+__i2c_write(const struct fsl_i2c_base *base, u8 chip_addr, u8 *offset, int olen,
+ u8 *data, int dlen)
{
- struct fsl_i2c *device = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
- int i = -1; /* signal error */
- u8 *a = (u8*)&addr;
+ int ret = -1; /* signal error */
- if (i2c_wait4bus(adap) < 0)
+ if (i2c_wait4bus(base) < 0)
return -1;
- if (i2c_write_addr(adap, dev, I2C_WRITE_BIT, 0) != 0 &&
- __i2c_write(adap, &a[4 - alen], alen) == alen) {
- i = __i2c_write(adap, data, length);
+ if (i2c_write_addr(base, chip_addr, I2C_WRITE_BIT, 0) != 0 &&
+ __i2c_write_data(base, offset, olen) == olen) {
+ ret = __i2c_write_data(base, data, dlen);
}
- writeb(I2C_CR_MEN, &device->cr);
- if (i2c_wait4bus(adap)) /* Wait until STOP */
+ writeb(I2C_CR_MEN, &base->cr);
+ if (i2c_wait4bus(base)) /* Wait until STOP */
debug("i2c_write: wait4bus timed out\n");
- if (i == length)
- return 0;
+ if (ret == dlen)
+ return 0;
return -1;
}
static int
-fsl_i2c_probe(struct i2c_adapter *adap, uchar chip)
+__i2c_probe_chip(const struct fsl_i2c_base *base, uchar chip)
{
- struct fsl_i2c *dev = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
/* For unknow reason the controller will ACK when
* probing for a slave with the same address, so skip
* it.
*/
- if (chip == (readb(&dev->adr) >> 1))
+ if (chip == (readb(&base->adr) >> 1))
return -1;
- return fsl_i2c_read(adap, chip, 0, 0, NULL, 0);
+ return __i2c_read(base, chip, 0, 0, NULL, 0);
}
-static unsigned int fsl_i2c_set_bus_speed(struct i2c_adapter *adap,
- unsigned int speed)
+static unsigned int __i2c_set_bus_speed(const struct fsl_i2c_base *base,
+ unsigned int speed, int i2c_clk)
{
- struct fsl_i2c *dev = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
-
- writeb(0, &dev->cr); /* stop controller */
- set_i2c_bus_speed(dev, get_i2c_clock(adap->hwadapnr), speed);
- writeb(I2C_CR_MEN, &dev->cr); /* start controller */
+ writeb(0, &base->cr); /* stop controller */
+ set_i2c_bus_speed(base, i2c_clk, speed);
+ writeb(I2C_CR_MEN, &base->cr); /* start controller */
return 0;
}
+#ifndef CONFIG_DM_I2C
+static void fsl_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
+{
+ __i2c_init(i2c_base[adap->hwadapnr], speed, slaveadd,
+ get_i2c_clock(adap->hwadapnr), adap->hwadapnr);
+}
+
+static int
+fsl_i2c_probe_chip(struct i2c_adapter *adap, uchar chip)
+{
+ return __i2c_probe_chip(i2c_base[adap->hwadapnr], chip);
+}
+
+static int
+fsl_i2c_read(struct i2c_adapter *adap, u8 chip_addr, uint offset, int olen,
+ u8 *data, int dlen)
+{
+ u8 *o = (u8 *)&offset;
+ return __i2c_read(i2c_base[adap->hwadapnr], chip_addr, &o[4 - olen],
+ olen, data, dlen);
+}
+
+static int
+fsl_i2c_write(struct i2c_adapter *adap, u8 chip_addr, uint offset, int olen,
+ u8 *data, int dlen)
+{
+ u8 *o = (u8 *)&offset;
+ return __i2c_write(i2c_base[adap->hwadapnr], chip_addr, &o[4 - olen],
+ olen, data, dlen);
+}
+
+static unsigned int fsl_i2c_set_bus_speed(struct i2c_adapter *adap,
+ unsigned int speed)
+{
+ return __i2c_set_bus_speed(i2c_base[adap->hwadapnr], speed,
+ get_i2c_clock(adap->hwadapnr));
+}
+
/*
* Register fsl i2c adapters
*/
-U_BOOT_I2C_ADAP_COMPLETE(fsl_0, fsl_i2c_init, fsl_i2c_probe, fsl_i2c_read,
+U_BOOT_I2C_ADAP_COMPLETE(fsl_0, fsl_i2c_init, fsl_i2c_probe_chip, fsl_i2c_read,
fsl_i2c_write, fsl_i2c_set_bus_speed,
CONFIG_SYS_FSL_I2C_SPEED, CONFIG_SYS_FSL_I2C_SLAVE,
0)
#ifdef CONFIG_SYS_FSL_I2C2_OFFSET
-U_BOOT_I2C_ADAP_COMPLETE(fsl_1, fsl_i2c_init, fsl_i2c_probe, fsl_i2c_read,
+U_BOOT_I2C_ADAP_COMPLETE(fsl_1, fsl_i2c_init, fsl_i2c_probe_chip, fsl_i2c_read,
fsl_i2c_write, fsl_i2c_set_bus_speed,
CONFIG_SYS_FSL_I2C2_SPEED, CONFIG_SYS_FSL_I2C2_SLAVE,
1)
#endif
#ifdef CONFIG_SYS_FSL_I2C3_OFFSET
-U_BOOT_I2C_ADAP_COMPLETE(fsl_2, fsl_i2c_init, fsl_i2c_probe, fsl_i2c_read,
+U_BOOT_I2C_ADAP_COMPLETE(fsl_2, fsl_i2c_init, fsl_i2c_probe_chip, fsl_i2c_read,
fsl_i2c_write, fsl_i2c_set_bus_speed,
CONFIG_SYS_FSL_I2C3_SPEED, CONFIG_SYS_FSL_I2C3_SLAVE,
2)
#endif
#ifdef CONFIG_SYS_FSL_I2C4_OFFSET
-U_BOOT_I2C_ADAP_COMPLETE(fsl_3, fsl_i2c_init, fsl_i2c_probe, fsl_i2c_read,
+U_BOOT_I2C_ADAP_COMPLETE(fsl_3, fsl_i2c_init, fsl_i2c_probe_chip, fsl_i2c_read,
fsl_i2c_write, fsl_i2c_set_bus_speed,
CONFIG_SYS_FSL_I2C4_SPEED, CONFIG_SYS_FSL_I2C4_SLAVE,
3)
#endif
+#else /* CONFIG_DM_I2C */
+static int fsl_i2c_probe_chip(struct udevice *bus, u32 chip_addr,
+ u32 chip_flags)
+{
+ struct fsl_i2c_dev *dev = dev_get_priv(bus);
+ return __i2c_probe_chip(dev->base, chip_addr);
+}
+
+static int fsl_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
+{
+ struct fsl_i2c_dev *dev = dev_get_priv(bus);
+ return __i2c_set_bus_speed(dev->base, speed, dev->i2c_clk);
+}
+
+static int fsl_i2c_ofdata_to_platdata(struct udevice *bus)
+{
+ struct fsl_i2c_dev *dev = dev_get_priv(bus);
+ u64 reg;
+ u32 addr, size;
+
+ reg = fdtdec_get_addr(gd->fdt_blob, bus->of_offset, "reg");
+ addr = reg >> 32;
+ size = reg & 0xFFFFFFFF;
+
+ dev->base = map_sysmem(CONFIG_SYS_IMMR + addr, size);
+
+ if (!dev->base)
+ return -ENOMEM;
+
+ dev->index = fdtdec_get_int(gd->fdt_blob, bus->of_offset,
+ "cell-index", -1);
+ dev->slaveadd = fdtdec_get_int(gd->fdt_blob, bus->of_offset,
+ "u-boot,i2c-slave-addr", 0x7f);
+ dev->speed = fdtdec_get_int(gd->fdt_blob, bus->of_offset,
+ "clock-frequency", 400000);
+
+ dev->i2c_clk = dev->index ? gd->arch.i2c2_clk : gd->arch.i2c1_clk;
+
+ return 0;
+}
+
+static int fsl_i2c_probe(struct udevice *bus)
+{
+ struct fsl_i2c_dev *dev = dev_get_priv(bus);
+ __i2c_init(dev->base, dev->speed, dev->slaveadd, dev->i2c_clk,
+ dev->index);
+ return 0;
+}
+
+static int fsl_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
+{
+ struct fsl_i2c_dev *dev = dev_get_priv(bus);
+ struct i2c_msg *dmsg, *omsg, dummy;
+
+ memset(&dummy, 0, sizeof(struct i2c_msg));
+
+ /* We expect either two messages (one with an offset and one with the
+ * actucal data) or one message (just data) */
+ if (nmsgs > 2 || nmsgs == 0) {
+ debug("%s: Only one or two messages are supported.", __func__);
+ return -1;
+ }
+
+ omsg = nmsgs == 1 ? &dummy : msg;
+ dmsg = nmsgs == 1 ? msg : msg + 1;
+
+ if (dmsg->flags & I2C_M_RD)
+ return __i2c_read(dev->base, dmsg->addr, omsg->buf, omsg->len,
+ dmsg->buf, dmsg->len);
+ else
+ return __i2c_write(dev->base, dmsg->addr, omsg->buf, omsg->len,
+ dmsg->buf, dmsg->len);
+}
+
+static const struct dm_i2c_ops fsl_i2c_ops = {
+ .xfer = fsl_i2c_xfer,
+ .probe_chip = fsl_i2c_probe_chip,
+ .set_bus_speed = fsl_i2c_set_bus_speed,
+};
+
+static const struct udevice_id fsl_i2c_ids[] = {
+ { .compatible = "fsl-i2c", },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(i2c_fsl) = {
+ .name = "i2c_fsl",
+ .id = UCLASS_I2C,
+ .of_match = fsl_i2c_ids,
+ .probe = fsl_i2c_probe,
+ .ofdata_to_platdata = fsl_i2c_ofdata_to_platdata,
+ .priv_auto_alloc_size = sizeof(struct fsl_i2c_dev),
+ .ops = &fsl_i2c_ops,
+};
+
+#endif /* CONFIG_DM_I2C */
struct i2c_cdns_bus {
int id;
+ unsigned int input_freq;
struct cdns_i2c_regs __iomem *regs; /* register base */
};
-
-/** cdns_i2c_probe() - Probe method
- * @dev: udevice pointer
- *
- * DM callback called when device is probed
- */
-static int cdns_i2c_probe(struct udevice *dev)
-{
- struct i2c_cdns_bus *bus = dev_get_priv(dev);
-
- bus->regs = (struct cdns_i2c_regs *)dev_get_addr(dev);
- if (!bus->regs)
- return -ENOMEM;
-
- /* TODO: Calculate dividers based on CPU_CLK_1X */
- /* 111MHz / ( (3 * 17) * 22 ) = ~100KHz */
- writel((16 << CDNS_I2C_CONTROL_DIV_B_SHIFT) |
- (2 << CDNS_I2C_CONTROL_DIV_A_SHIFT), &bus->regs->control);
-
- /* Enable master mode, ack, and 7-bit addressing */
- setbits_le32(&bus->regs->control, CDNS_I2C_CONTROL_MS |
- CDNS_I2C_CONTROL_ACKEN | CDNS_I2C_CONTROL_NEA);
-
- debug("%s bus %d at %p\n", __func__, dev->seq, bus->regs);
-
- return 0;
-}
-
-static int cdns_i2c_remove(struct udevice *dev)
-{
- struct i2c_cdns_bus *bus = dev_get_priv(dev);
-
- debug("%s bus %d at %p\n", __func__, dev->seq, bus->regs);
-
- unmap_sysmem(bus->regs);
-
- return 0;
-}
-
/* Wait for an interrupt */
static u32 cdns_i2c_wait(struct cdns_i2c_regs *cdns_i2c, u32 mask)
{
return int_status & mask;
}
+#define CDNS_I2C_DIVA_MAX 4
+#define CDNS_I2C_DIVB_MAX 64
+
+static int cdns_i2c_calc_divs(unsigned long *f, unsigned long input_clk,
+ unsigned int *a, unsigned int *b)
+{
+ unsigned long fscl = *f, best_fscl = *f, actual_fscl, temp;
+ unsigned int div_a, div_b, calc_div_a = 0, calc_div_b = 0;
+ unsigned int last_error, current_error;
+
+ /* calculate (divisor_a+1) x (divisor_b+1) */
+ temp = input_clk / (22 * fscl);
+
+ /*
+ * If the calculated value is negative or 0CDNS_I2C_DIVA_MAX,
+ * the fscl input is out of range. Return error.
+ */
+ if (!temp || (temp > (CDNS_I2C_DIVA_MAX * CDNS_I2C_DIVB_MAX)))
+ return -EINVAL;
+
+ last_error = -1;
+ for (div_a = 0; div_a < CDNS_I2C_DIVA_MAX; div_a++) {
+ div_b = DIV_ROUND_UP(input_clk, 22 * fscl * (div_a + 1));
+
+ if ((div_b < 1) || (div_b > CDNS_I2C_DIVB_MAX))
+ continue;
+ div_b--;
+
+ actual_fscl = input_clk / (22 * (div_a + 1) * (div_b + 1));
+
+ if (actual_fscl > fscl)
+ continue;
+
+ current_error = ((actual_fscl > fscl) ? (actual_fscl - fscl) :
+ (fscl - actual_fscl));
+
+ if (last_error > current_error) {
+ calc_div_a = div_a;
+ calc_div_b = div_b;
+ best_fscl = actual_fscl;
+ last_error = current_error;
+ }
+ }
+
+ *a = calc_div_a;
+ *b = calc_div_b;
+ *f = best_fscl;
+
+ return 0;
+}
+
static int cdns_i2c_set_bus_speed(struct udevice *dev, unsigned int speed)
{
- if (speed != 100000) {
- printf("%s, failed to set clock speed to %u\n", __func__,
- speed);
+ struct i2c_cdns_bus *bus = dev_get_priv(dev);
+ u32 div_a = 0, div_b = 0;
+ unsigned long speed_p = speed;
+ int ret = 0;
+
+ if (speed > 400000) {
+ debug("%s, failed to set clock speed to %u\n", __func__,
+ speed);
return -EINVAL;
}
+ ret = cdns_i2c_calc_divs(&speed_p, bus->input_freq, &div_a, &div_b);
+ if (ret)
+ return ret;
+
+ debug("%s: div_a: %d, div_b: %d, input freq: %d, speed: %d/%ld\n",
+ __func__, div_a, div_b, bus->input_freq, speed, speed_p);
+
+ writel((div_b << CDNS_I2C_CONTROL_DIV_B_SHIFT) |
+ (div_a << CDNS_I2C_CONTROL_DIV_A_SHIFT), &bus->regs->control);
+
+ /* Enable master mode, ack, and 7-bit addressing */
+ setbits_le32(&bus->regs->control, CDNS_I2C_CONTROL_MS |
+ CDNS_I2C_CONTROL_ACKEN | CDNS_I2C_CONTROL_NEA);
+
return 0;
}
return 0;
}
+static int cdns_i2c_ofdata_to_platdata(struct udevice *dev)
+{
+ struct i2c_cdns_bus *i2c_bus = dev_get_priv(dev);
+
+ i2c_bus->regs = (struct cdns_i2c_regs *)dev_get_addr(dev);
+ if (!i2c_bus->regs)
+ return -ENOMEM;
+
+ i2c_bus->input_freq = 100000000; /* TODO hardcode input freq for now */
+
+ return 0;
+}
+
static const struct dm_i2c_ops cdns_i2c_ops = {
.xfer = cdns_i2c_xfer,
.probe_chip = cdns_i2c_probe_chip,
.name = "i2c-cdns",
.id = UCLASS_I2C,
.of_match = cdns_i2c_of_match,
- .probe = cdns_i2c_probe,
- .remove = cdns_i2c_remove,
+ .ofdata_to_platdata = cdns_i2c_ofdata_to_platdata,
.priv_auto_alloc_size = sizeof(struct i2c_cdns_bus),
.ops = &cdns_i2c_ops,
};
I2C multimaster arbitration scheme using GPIOs and a challenge &
response mechanism where masters have to claim the bus by asserting
a GPIO.
+
+config I2C_MUX_PCA954x
+ tristate "TI PCA954x I2C Mux/switches"
+ depends on I2C_MUX
+ help
+ If you say yes here you get support for the TI PCA954x
+ I2C mux/switch devices. It is x width I2C multiplexer which enables to
+ paritioning I2C bus and connect multiple devices with the same address
+ to the same I2C controller where driver handles proper routing to
+ target i2c device. PCA9544 and PCA9548 are supported.
#
obj-$(CONFIG_I2C_ARB_GPIO_CHALLENGE) += i2c-arb-gpio-challenge.o
obj-$(CONFIG_$(SPL_)I2C_MUX) += i2c-mux-uclass.o
+obj-$(CONFIG_I2C_MUX_PCA954x) += pca954x.o
--- /dev/null
+/*
+ * Copyright (C) 2015 - 2016 Xilinx, Inc.
+ * Written by Michal Simek
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <i2c.h>
+#include <asm/gpio.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct pca954x_priv {
+ u32 addr; /* I2C mux address */
+ u32 width; /* I2C mux width - number of busses */
+};
+
+static int pca954x_deselect(struct udevice *mux, struct udevice *bus,
+ uint channel)
+{
+ struct pca954x_priv *priv = dev_get_priv(mux);
+ uchar byte = 0;
+
+ return dm_i2c_write(mux, priv->addr, &byte, 1);
+}
+
+static int pca954x_select(struct udevice *mux, struct udevice *bus,
+ uint channel)
+{
+ struct pca954x_priv *priv = dev_get_priv(mux);
+ uchar byte = 1 << channel;
+
+ return dm_i2c_write(mux, priv->addr, &byte, 1);
+}
+
+static const struct i2c_mux_ops pca954x_ops = {
+ .select = pca954x_select,
+ .deselect = pca954x_deselect,
+};
+
+static const struct udevice_id pca954x_ids[] = {
+ { .compatible = "nxp,pca9548", .data = (ulong)8 },
+ { .compatible = "nxp,pca9544", .data = (ulong)4 },
+ { }
+};
+
+static int pca954x_ofdata_to_platdata(struct udevice *dev)
+{
+ struct pca954x_priv *priv = dev_get_priv(dev);
+
+ priv->addr = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "reg", 0);
+ if (!priv->addr) {
+ debug("MUX not found\n");
+ return -ENODEV;
+ }
+ priv->width = dev_get_driver_data(dev);
+
+ if (!priv->width) {
+ debug("No I2C MUX width specified\n");
+ return -EINVAL;
+ }
+
+ debug("Device %s at 0x%x with width %d\n",
+ dev->name, priv->addr, priv->width);
+
+ return 0;
+}
+
+U_BOOT_DRIVER(pca954x) = {
+ .name = "pca954x",
+ .id = UCLASS_I2C_MUX,
+ .of_match = pca954x_ids,
+ .ops = &pca954x_ops,
+ .ofdata_to_platdata = pca954x_ofdata_to_platdata,
+ .priv_auto_alloc_size = sizeof(struct pca954x_priv),
+};
MVTWSI_ERROR_TIMEOUT, control, status, expected_status);
}
-/*
- * These flags are ORed to any write to the control register
- * They allow global setting of TWSIEN and ACK.
- * By default none are set.
- * twsi_start() sets TWSIEN (in case the controller was disabled)
- * twsi_recv() sets ACK or resets it depending on expected status.
- */
-static u8 twsi_control_flags = MVTWSI_CONTROL_TWSIEN;
-
/*
* Assert the START condition, either in a single I2C transaction
* or inside back-to-back ones (repeated starts).
*/
-static int twsi_start(struct i2c_adapter *adap, int expected_status)
+static int twsi_start(struct i2c_adapter *adap, int expected_status, u8 *flags)
{
struct mvtwsi_registers *twsi = twsi_get_base(adap);
/* globally set TWSIEN in case it was not */
- twsi_control_flags |= MVTWSI_CONTROL_TWSIEN;
+ *flags |= MVTWSI_CONTROL_TWSIEN;
/* assert START */
- writel(twsi_control_flags | MVTWSI_CONTROL_START |
+ writel(*flags | MVTWSI_CONTROL_START |
MVTWSI_CONTROL_CLEAR_IFLG, &twsi->control);
/* wait for controller to process START */
return twsi_wait(adap, expected_status);
/*
* Send a byte (i2c address or data).
*/
-static int twsi_send(struct i2c_adapter *adap, u8 byte, int expected_status)
+static int twsi_send(struct i2c_adapter *adap, u8 byte, int expected_status,
+ u8 *flags)
{
struct mvtwsi_registers *twsi = twsi_get_base(adap);
/* put byte in data register for sending */
writel(byte, &twsi->data);
/* clear any pending interrupt -- that'll cause sending */
- writel(twsi_control_flags | MVTWSI_CONTROL_CLEAR_IFLG, &twsi->control);
+ writel(*flags | MVTWSI_CONTROL_CLEAR_IFLG, &twsi->control);
/* wait for controller to receive byte and check ACK */
return twsi_wait(adap, expected_status);
}
* Receive a byte.
* Global mvtwsi_control_flags variable says if we should ack or nak.
*/
-static int twsi_recv(struct i2c_adapter *adap, u8 *byte)
+static int twsi_recv(struct i2c_adapter *adap, u8 *byte, u8 *flags)
{
struct mvtwsi_registers *twsi = twsi_get_base(adap);
int expected_status, status;
/* compute expected status based on ACK bit in global control flags */
- if (twsi_control_flags & MVTWSI_CONTROL_ACK)
+ if (*flags & MVTWSI_CONTROL_ACK)
expected_status = MVTWSI_STATUS_DATA_R_ACK;
else
expected_status = MVTWSI_STATUS_DATA_R_NAK;
/* acknowledge *previous state* and launch receive */
- writel(twsi_control_flags | MVTWSI_CONTROL_CLEAR_IFLG, &twsi->control);
+ writel(*flags | MVTWSI_CONTROL_CLEAR_IFLG, &twsi->control);
/* wait for controller to receive byte and assert ACK or NAK */
status = twsi_wait(adap, expected_status);
/* if we did receive expected byte then store it */
static void twsi_reset(struct i2c_adapter *adap)
{
struct mvtwsi_registers *twsi = twsi_get_base(adap);
- /* ensure controller will be enabled by any twsi*() function */
- twsi_control_flags = MVTWSI_CONTROL_TWSIEN;
+
/* reset controller */
writel(0, &twsi->soft_reset);
/* wait 2 ms -- this is what the Marvell LSP does */
* Expected address status will derive from direction bit (bit 0) in addr.
*/
static int i2c_begin(struct i2c_adapter *adap, int expected_start_status,
- u8 addr)
+ u8 addr, u8 *flags)
{
int status, expected_addr_status;
else /* writing */
expected_addr_status = MVTWSI_STATUS_ADDR_W_ACK;
/* assert START */
- status = twsi_start(adap, expected_start_status);
+ status = twsi_start(adap, expected_start_status, flags);
/* send out the address if the start went well */
if (status == 0)
- status = twsi_send(adap, addr, expected_addr_status);
+ status = twsi_send(adap, addr, expected_addr_status,
+ flags);
/* return ok or status of first failure to caller */
return status;
}
static int twsi_i2c_probe(struct i2c_adapter *adap, uchar chip)
{
u8 dummy_byte;
+ u8 flags = 0;
int status;
/* begin i2c read */
- status = i2c_begin(adap, MVTWSI_STATUS_START, (chip << 1) | 1);
+ status = i2c_begin(adap, MVTWSI_STATUS_START, (chip << 1) | 1, &flags);
/* dummy read was accepted: receive byte but NAK it. */
if (status == 0)
- status = twsi_recv(adap, &dummy_byte);
+ status = twsi_recv(adap, &dummy_byte, &flags);
/* Stop transaction */
twsi_stop(adap, 0);
/* return 0 or status of first failure */
int alen, uchar *data, int length)
{
int status;
+ u8 flags = 0;
/* begin i2c write to send the address bytes */
- status = i2c_begin(adap, MVTWSI_STATUS_START, (chip << 1));
+ status = i2c_begin(adap, MVTWSI_STATUS_START, (chip << 1), &flags);
/* send addr bytes */
while ((status == 0) && alen--)
status = twsi_send(adap, addr >> (8*alen),
- MVTWSI_STATUS_DATA_W_ACK);
+ MVTWSI_STATUS_DATA_W_ACK, &flags);
/* begin i2c read to receive eeprom data bytes */
if (status == 0)
status = i2c_begin(adap, MVTWSI_STATUS_REPEATED_START,
- (chip << 1) | 1);
+ (chip << 1) | 1, &flags);
/* prepare ACK if at least one byte must be received */
if (length > 0)
- twsi_control_flags |= MVTWSI_CONTROL_ACK;
+ flags |= MVTWSI_CONTROL_ACK;
/* now receive actual bytes */
while ((status == 0) && length--) {
/* reset NAK if we if no more to read now */
if (length == 0)
- twsi_control_flags &= ~MVTWSI_CONTROL_ACK;
+ flags &= ~MVTWSI_CONTROL_ACK;
/* read current byte */
- status = twsi_recv(adap, data++);
+ status = twsi_recv(adap, data++, &flags);
}
/* Stop transaction */
status = twsi_stop(adap, status);
int alen, uchar *data, int length)
{
int status;
+ u8 flags = 0;
/* begin i2c write to send the eeprom adress bytes then data bytes */
- status = i2c_begin(adap, MVTWSI_STATUS_START, (chip << 1));
+ status = i2c_begin(adap, MVTWSI_STATUS_START, (chip << 1), &flags);
/* send addr bytes */
while ((status == 0) && alen--)
status = twsi_send(adap, addr >> (8*alen),
- MVTWSI_STATUS_DATA_W_ACK);
+ MVTWSI_STATUS_DATA_W_ACK, &flags);
/* send data bytes */
while ((status == 0) && (length-- > 0))
- status = twsi_send(adap, *(data++), MVTWSI_STATUS_DATA_W_ACK);
+ status = twsi_send(adap, *(data++), MVTWSI_STATUS_DATA_W_ACK,
+ &flags);
/* Stop transaction */
status = twsi_stop(adap, status);
/* return 0 or status of first failure */
legacy UART or other devices in the Winbond Super IO chips
on X86 platforms.
+config QFW
+ bool
+ help
+ Hidden option to enable QEMU fw_cfg interface. This will be selected by
+ either CONFIG_CMD_QFW or CONFIG_GENERATE_ACPI_TABLE.
+
endmenu
obj-$(CONFIG_RESET) += reset-uclass.o
obj-$(CONFIG_FSL_DEVICE_DISABLE) += fsl_devdis.o
obj-$(CONFIG_WINBOND_W83627) += winbond_w83627.o
+obj-$(CONFIG_QFW) += qfw.o
--- /dev/null
+/*
+ * (C) Copyright 2015 Miao Yan <yanmiaobest@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <errno.h>
+#include <malloc.h>
+#include <qfw.h>
+#include <asm/io.h>
+#ifdef CONFIG_GENERATE_ACPI_TABLE
+#include <asm/tables.h>
+#endif
+#include <linux/list.h>
+
+static bool fwcfg_present;
+static bool fwcfg_dma_present;
+static struct fw_cfg_arch_ops *fwcfg_arch_ops;
+
+static LIST_HEAD(fw_list);
+
+#ifdef CONFIG_GENERATE_ACPI_TABLE
+/*
+ * This function allocates memory for ACPI tables
+ *
+ * @entry : BIOS linker command entry which tells where to allocate memory
+ * (either high memory or low memory)
+ * @addr : The address that should be used for low memory allcation. If the
+ * memory allocation request is 'ZONE_HIGH' then this parameter will
+ * be ignored.
+ * @return: 0 on success, or negative value on failure
+ */
+static int bios_linker_allocate(struct bios_linker_entry *entry, u32 *addr)
+{
+ uint32_t size, align;
+ struct fw_file *file;
+ unsigned long aligned_addr;
+
+ align = le32_to_cpu(entry->alloc.align);
+ /* align must be power of 2 */
+ if (align & (align - 1)) {
+ printf("error: wrong alignment %u\n", align);
+ return -EINVAL;
+ }
+
+ file = qemu_fwcfg_find_file(entry->alloc.file);
+ if (!file) {
+ printf("error: can't find file %s\n", entry->alloc.file);
+ return -ENOENT;
+ }
+
+ size = be32_to_cpu(file->cfg.size);
+
+ /*
+ * ZONE_HIGH means we need to allocate from high memory, since
+ * malloc space is already at the end of RAM, so we directly use it.
+ * If allocation zone is ZONE_FSEG, then we use the 'addr' passed
+ * in which is low memory
+ */
+ if (entry->alloc.zone == BIOS_LINKER_LOADER_ALLOC_ZONE_HIGH) {
+ aligned_addr = (unsigned long)memalign(align, size);
+ if (!aligned_addr) {
+ printf("error: allocating resource\n");
+ return -ENOMEM;
+ }
+ } else if (entry->alloc.zone == BIOS_LINKER_LOADER_ALLOC_ZONE_FSEG) {
+ aligned_addr = ALIGN(*addr, align);
+ } else {
+ printf("error: invalid allocation zone\n");
+ return -EINVAL;
+ }
+
+ debug("bios_linker_allocate: allocate file %s, size %u, zone %d, align %u, addr 0x%lx\n",
+ file->cfg.name, size, entry->alloc.zone, align, aligned_addr);
+
+ qemu_fwcfg_read_entry(be16_to_cpu(file->cfg.select),
+ size, (void *)aligned_addr);
+ file->addr = aligned_addr;
+
+ /* adjust address for low memory allocation */
+ if (entry->alloc.zone == BIOS_LINKER_LOADER_ALLOC_ZONE_FSEG)
+ *addr = (aligned_addr + size);
+
+ return 0;
+}
+
+/*
+ * This function patches ACPI tables previously loaded
+ * by bios_linker_allocate()
+ *
+ * @entry : BIOS linker command entry which tells how to patch
+ * ACPI tables
+ * @return: 0 on success, or negative value on failure
+ */
+static int bios_linker_add_pointer(struct bios_linker_entry *entry)
+{
+ struct fw_file *dest, *src;
+ uint32_t offset = le32_to_cpu(entry->pointer.offset);
+ uint64_t pointer = 0;
+
+ dest = qemu_fwcfg_find_file(entry->pointer.dest_file);
+ if (!dest || !dest->addr)
+ return -ENOENT;
+ src = qemu_fwcfg_find_file(entry->pointer.src_file);
+ if (!src || !src->addr)
+ return -ENOENT;
+
+ debug("bios_linker_add_pointer: dest->addr 0x%lx, src->addr 0x%lx, offset 0x%x size %u, 0x%llx\n",
+ dest->addr, src->addr, offset, entry->pointer.size, pointer);
+
+ memcpy(&pointer, (char *)dest->addr + offset, entry->pointer.size);
+ pointer = le64_to_cpu(pointer);
+ pointer += (unsigned long)src->addr;
+ pointer = cpu_to_le64(pointer);
+ memcpy((char *)dest->addr + offset, &pointer, entry->pointer.size);
+
+ return 0;
+}
+
+/*
+ * This function updates checksum fields of ACPI tables previously loaded
+ * by bios_linker_allocate()
+ *
+ * @entry : BIOS linker command entry which tells where to update ACPI table
+ * checksums
+ * @return: 0 on success, or negative value on failure
+ */
+static int bios_linker_add_checksum(struct bios_linker_entry *entry)
+{
+ struct fw_file *file;
+ uint8_t *data, cksum = 0;
+ uint8_t *cksum_start;
+
+ file = qemu_fwcfg_find_file(entry->cksum.file);
+ if (!file || !file->addr)
+ return -ENOENT;
+
+ data = (uint8_t *)(file->addr + le32_to_cpu(entry->cksum.offset));
+ cksum_start = (uint8_t *)(file->addr + le32_to_cpu(entry->cksum.start));
+ cksum = table_compute_checksum(cksum_start,
+ le32_to_cpu(entry->cksum.length));
+ *data = cksum;
+
+ return 0;
+}
+
+/* This function loads and patches ACPI tables provided by QEMU */
+u32 write_acpi_tables(u32 addr)
+{
+ int i, ret = 0;
+ struct fw_file *file;
+ struct bios_linker_entry *table_loader;
+ struct bios_linker_entry *entry;
+ uint32_t size;
+
+ /* make sure fw_list is loaded */
+ ret = qemu_fwcfg_read_firmware_list();
+ if (ret) {
+ printf("error: can't read firmware file list\n");
+ return addr;
+ }
+
+ file = qemu_fwcfg_find_file("etc/table-loader");
+ if (!file) {
+ printf("error: can't find etc/table-loader\n");
+ return addr;
+ }
+
+ size = be32_to_cpu(file->cfg.size);
+ if ((size % sizeof(*entry)) != 0) {
+ printf("error: table-loader maybe corrupted\n");
+ return addr;
+ }
+
+ table_loader = malloc(size);
+ if (!table_loader) {
+ printf("error: no memory for table-loader\n");
+ return addr;
+ }
+
+ qemu_fwcfg_read_entry(be16_to_cpu(file->cfg.select),
+ size, table_loader);
+
+ for (i = 0; i < (size / sizeof(*entry)); i++) {
+ entry = table_loader + i;
+ switch (le32_to_cpu(entry->command)) {
+ case BIOS_LINKER_LOADER_COMMAND_ALLOCATE:
+ ret = bios_linker_allocate(entry, &addr);
+ if (ret)
+ goto out;
+ break;
+ case BIOS_LINKER_LOADER_COMMAND_ADD_POINTER:
+ ret = bios_linker_add_pointer(entry);
+ if (ret)
+ goto out;
+ break;
+ case BIOS_LINKER_LOADER_COMMAND_ADD_CHECKSUM:
+ ret = bios_linker_add_checksum(entry);
+ if (ret)
+ goto out;
+ break;
+ default:
+ break;
+ }
+ }
+
+out:
+ if (ret) {
+ struct fw_cfg_file_iter iter;
+ for (file = qemu_fwcfg_file_iter_init(&iter);
+ !qemu_fwcfg_file_iter_end(&iter);
+ file = qemu_fwcfg_file_iter_next(&iter)) {
+ if (file->addr) {
+ free((void *)file->addr);
+ file->addr = 0;
+ }
+ }
+ }
+
+ free(table_loader);
+ return addr;
+}
+#endif
+
+/* Read configuration item using fw_cfg PIO interface */
+static void qemu_fwcfg_read_entry_pio(uint16_t entry,
+ uint32_t size, void *address)
+{
+ debug("qemu_fwcfg_read_entry_pio: entry 0x%x, size %u address %p\n",
+ entry, size, address);
+
+ return fwcfg_arch_ops->arch_read_pio(entry, size, address);
+}
+
+/* Read configuration item using fw_cfg DMA interface */
+static void qemu_fwcfg_read_entry_dma(uint16_t entry,
+ uint32_t size, void *address)
+{
+ struct fw_cfg_dma_access dma;
+
+ dma.length = cpu_to_be32(size);
+ dma.address = cpu_to_be64((uintptr_t)address);
+ dma.control = cpu_to_be32(FW_CFG_DMA_READ);
+
+ /*
+ * writting FW_CFG_INVALID will cause read operation to resume at
+ * last offset, otherwise read will start at offset 0
+ */
+ if (entry != FW_CFG_INVALID)
+ dma.control |= cpu_to_be32(FW_CFG_DMA_SELECT | (entry << 16));
+
+ barrier();
+
+ debug("qemu_fwcfg_read_entry_dma: entry 0x%x, size %u address %p, control 0x%x\n",
+ entry, size, address, be32_to_cpu(dma.control));
+
+ fwcfg_arch_ops->arch_read_dma(&dma);
+}
+
+bool qemu_fwcfg_present(void)
+{
+ return fwcfg_present;
+}
+
+bool qemu_fwcfg_dma_present(void)
+{
+ return fwcfg_dma_present;
+}
+
+void qemu_fwcfg_read_entry(uint16_t entry, uint32_t length, void *address)
+{
+ if (fwcfg_dma_present)
+ qemu_fwcfg_read_entry_dma(entry, length, address);
+ else
+ qemu_fwcfg_read_entry_pio(entry, length, address);
+}
+
+int qemu_fwcfg_online_cpus(void)
+{
+ uint16_t nb_cpus;
+
+ if (!fwcfg_present)
+ return -ENODEV;
+
+ qemu_fwcfg_read_entry(FW_CFG_NB_CPUS, 2, &nb_cpus);
+
+ return le16_to_cpu(nb_cpus);
+}
+
+int qemu_fwcfg_read_firmware_list(void)
+{
+ int i;
+ uint32_t count;
+ struct fw_file *file;
+ struct list_head *entry;
+
+ /* don't read it twice */
+ if (!list_empty(&fw_list))
+ return 0;
+
+ qemu_fwcfg_read_entry(FW_CFG_FILE_DIR, 4, &count);
+ if (!count)
+ return 0;
+
+ count = be32_to_cpu(count);
+ for (i = 0; i < count; i++) {
+ file = malloc(sizeof(*file));
+ if (!file) {
+ printf("error: allocating resource\n");
+ goto err;
+ }
+ qemu_fwcfg_read_entry(FW_CFG_INVALID,
+ sizeof(struct fw_cfg_file), &file->cfg);
+ file->addr = 0;
+ list_add_tail(&file->list, &fw_list);
+ }
+
+ return 0;
+
+err:
+ list_for_each(entry, &fw_list) {
+ file = list_entry(entry, struct fw_file, list);
+ free(file);
+ }
+
+ return -ENOMEM;
+}
+
+struct fw_file *qemu_fwcfg_find_file(const char *name)
+{
+ struct list_head *entry;
+ struct fw_file *file;
+
+ list_for_each(entry, &fw_list) {
+ file = list_entry(entry, struct fw_file, list);
+ if (!strcmp(file->cfg.name, name))
+ return file;
+ }
+
+ return NULL;
+}
+
+struct fw_file *qemu_fwcfg_file_iter_init(struct fw_cfg_file_iter *iter)
+{
+ iter->entry = fw_list.next;
+ return list_entry((struct list_head *)iter->entry,
+ struct fw_file, list);
+}
+
+struct fw_file *qemu_fwcfg_file_iter_next(struct fw_cfg_file_iter *iter)
+{
+ iter->entry = ((struct list_head *)iter->entry)->next;
+ return list_entry((struct list_head *)iter->entry,
+ struct fw_file, list);
+}
+
+bool qemu_fwcfg_file_iter_end(struct fw_cfg_file_iter *iter)
+{
+ return iter->entry == &fw_list;
+}
+
+void qemu_fwcfg_init(struct fw_cfg_arch_ops *ops)
+{
+ uint32_t qemu;
+ uint32_t dma_enabled;
+
+ fwcfg_present = false;
+ fwcfg_dma_present = false;
+ fwcfg_arch_ops = NULL;
+
+ if (!ops || !ops->arch_read_pio || !ops->arch_read_dma)
+ return;
+ fwcfg_arch_ops = ops;
+
+ qemu_fwcfg_read_entry_pio(FW_CFG_SIGNATURE, 4, &qemu);
+ if (be32_to_cpu(qemu) == QEMU_FW_CFG_SIGNATURE)
+ fwcfg_present = true;
+
+ if (fwcfg_present) {
+ qemu_fwcfg_read_entry_pio(FW_CFG_ID, 1, &dma_enabled);
+ if (dma_enabled & FW_CFG_DMA_ENABLED)
+ fwcfg_dma_present = true;
+ }
+}
config MMC
bool "Enable MMC support"
- depends on ARCH_SUNXI
+ depends on ARCH_SUNXI || SANDBOX
help
TODO: Move all architectures to use this option
help
This selects support for the SD/MMC Host Controller on UniPhier SoCs.
+config SANDBOX_MMC
+ bool "Sandbox MMC support"
+ depends on MMC && SANDBOX
+ help
+ This select a dummy sandbox MMC driver. At present this does nothing
+ other than allow sandbox to be build with MMC support. This
+ improves build coverage for sandbox and makes it easier to detect
+ MMC build errors with sandbox.
+
endmenu
# SPDX-License-Identifier: GPL-2.0+
#
-obj-$(CONFIG_DM_MMC) += mmc-uclass.o
+ifdef CONFIG_DM_MMC
+obj-$(CONFIG_GENERIC_MMC) += mmc-uclass.o
+endif
+
+ifndef CONFIG_BLK
+obj-$(CONFIG_GENERIC_MMC) += mmc_legacy.o
+endif
obj-$(CONFIG_ARM_PL180_MMCI) += arm_pl180_mmci.o
obj-$(CONFIG_ATMEL_SDHCI) += atmel_sdhci.o
obj-$(CONFIG_SUPPORT_EMMC_RPMB) += rpmb.o
obj-$(CONFIG_S3C_SDI) += s3c_sdi.o
obj-$(CONFIG_S5P_SDHCI) += s5p_sdhci.o
+ifdef CONFIG_BLK
+ifdef CONFIG_GENERIC_MMC
obj-$(CONFIG_SANDBOX) += sandbox_mmc.o
+endif
+endif
obj-$(CONFIG_SDHCI) += sdhci.o
obj-$(CONFIG_SH_MMCIF) += sh_mmcif.o
obj-$(CONFIG_SH_SDHI) += sh_sdhi.o
return upriv->mmc;
}
+#ifdef CONFIG_BLK
+struct mmc *find_mmc_device(int dev_num)
+{
+ struct udevice *dev, *mmc_dev;
+ int ret;
+
+ ret = blk_get_device(IF_TYPE_MMC, dev_num, &dev);
+
+ if (ret) {
+#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
+ printf("MMC Device %d not found\n", dev_num);
+#endif
+ return NULL;
+ }
+
+ mmc_dev = dev_get_parent(dev);
+
+ return mmc_get_mmc_dev(mmc_dev);
+}
+
+int get_mmc_num(void)
+{
+ return max(blk_find_max_devnum(IF_TYPE_MMC), 0);
+}
+
+int mmc_get_next_devnum(void)
+{
+ int ret;
+
+ ret = get_mmc_num();
+ if (ret < 0)
+ return ret;
+
+ return ret + 1;
+}
+
+struct blk_desc *mmc_get_blk_desc(struct mmc *mmc)
+{
+ struct blk_desc *desc;
+ struct udevice *dev;
+
+ device_find_first_child(mmc->dev, &dev);
+ if (!dev)
+ return NULL;
+ desc = dev_get_uclass_platdata(dev);
+
+ return desc;
+}
+
+void mmc_do_preinit(void)
+{
+ struct udevice *dev;
+ struct uclass *uc;
+ int ret;
+
+ ret = uclass_get(UCLASS_MMC, &uc);
+ if (ret)
+ return;
+ uclass_foreach_dev(dev, uc) {
+ struct mmc *m = mmc_get_mmc_dev(dev);
+
+ if (!m)
+ continue;
+#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
+ mmc_set_preinit(m, 1);
+#endif
+ if (m->preinit)
+ mmc_start_init(m);
+ }
+}
+
+#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
+void print_mmc_devices(char separator)
+{
+ struct udevice *dev;
+ char *mmc_type;
+ bool first = true;
+
+ for (uclass_first_device(UCLASS_MMC, &dev);
+ dev;
+ uclass_next_device(&dev)) {
+ struct mmc *m = mmc_get_mmc_dev(dev);
+
+ if (!first) {
+ printf("%c", separator);
+ if (separator != '\n')
+ puts(" ");
+ }
+ if (m->has_init)
+ mmc_type = IS_SD(m) ? "SD" : "eMMC";
+ else
+ mmc_type = NULL;
+
+ printf("%s: %d", m->cfg->name, mmc_get_blk_desc(m)->devnum);
+ if (mmc_type)
+ printf(" (%s)", mmc_type);
+ }
+
+ printf("\n");
+}
+
+#else
+void print_mmc_devices(char separator) { }
+#endif
+#endif /* CONFIG_BLK */
+
U_BOOT_DRIVER(mmc) = {
.name = "mmc",
.id = UCLASS_MMC,
#include <div64.h>
#include "mmc_private.h"
-static struct list_head mmc_devices;
-static int cur_dev_num = -1;
-
__weak int board_mmc_getwp(struct mmc *mmc)
{
return -1;
return mmc_send_cmd(mmc, &cmd, NULL);
}
-struct mmc *find_mmc_device(int dev_num)
-{
- struct mmc *m;
- struct list_head *entry;
-
- list_for_each(entry, &mmc_devices) {
- m = list_entry(entry, struct mmc, link);
-
- if (m->block_dev.devnum == dev_num)
- return m;
- }
-
-#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
- printf("MMC Device %d not found\n", dev_num);
-#endif
-
- return NULL;
-}
-
static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start,
lbaint_t blkcnt)
{
return blkcnt;
}
+#ifdef CONFIG_BLK
+static ulong mmc_bread(struct udevice *dev, lbaint_t start, lbaint_t blkcnt,
+ void *dst)
+#else
static ulong mmc_bread(struct blk_desc *block_dev, lbaint_t start,
lbaint_t blkcnt, void *dst)
+#endif
{
+#ifdef CONFIG_BLK
+ struct blk_desc *block_dev = dev_get_uclass_platdata(dev);
+#endif
int dev_num = block_dev->devnum;
int err;
lbaint_t cur, blocks_todo = blkcnt;
if (!mmc)
return 0;
- err = mmc_select_hwpart(dev_num, block_dev->hwpart);
+ err = blk_dselect_hwpart(block_dev, block_dev->hwpart);
if (err < 0)
return 0;
- if ((start + blkcnt) > mmc->block_dev.lba) {
+ if ((start + blkcnt) > block_dev->lba) {
#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
printf("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n",
- start + blkcnt, mmc->block_dev.lba);
+ start + blkcnt, block_dev->lba);
#endif
return 0;
}
return -1;
}
- mmc->block_dev.lba = lldiv(mmc->capacity, mmc->read_bl_len);
+ mmc_get_blk_desc(mmc)->lba = lldiv(mmc->capacity, mmc->read_bl_len);
return 0;
}
-int mmc_select_hwpart(int dev_num, int hwpart)
+static int mmc_switch_part(struct mmc *mmc, unsigned int part_num)
{
- struct mmc *mmc = find_mmc_device(dev_num);
int ret;
- if (!mmc)
- return -ENODEV;
+ ret = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF,
+ (mmc->part_config & ~PART_ACCESS_MASK)
+ | (part_num & PART_ACCESS_MASK));
- if (mmc->block_dev.hwpart == hwpart)
+ /*
+ * Set the capacity if the switch succeeded or was intended
+ * to return to representing the raw device.
+ */
+ if ((ret == 0) || ((ret == -ENODEV) && (part_num == 0))) {
+ ret = mmc_set_capacity(mmc, part_num);
+ mmc_get_blk_desc(mmc)->hwpart = part_num;
+ }
+
+ return ret;
+}
+
+#ifdef CONFIG_BLK
+static int mmc_select_hwpart(struct udevice *bdev, int hwpart)
+{
+ struct udevice *mmc_dev = dev_get_parent(bdev);
+ struct mmc *mmc = mmc_get_mmc_dev(mmc_dev);
+ struct blk_desc *desc = dev_get_uclass_platdata(bdev);
+ int ret;
+
+ if (desc->hwpart == hwpart)
return 0;
- if (mmc->part_config == MMCPART_NOAVAILABLE) {
- printf("Card doesn't support part_switch\n");
+ if (mmc->part_config == MMCPART_NOAVAILABLE)
return -EMEDIUMTYPE;
- }
- ret = mmc_switch_part(dev_num, hwpart);
+ ret = mmc_switch_part(mmc, hwpart);
if (ret)
return ret;
return 0;
}
-
-
-int mmc_switch_part(int dev_num, unsigned int part_num)
+#else
+static int mmc_select_hwpartp(struct blk_desc *desc, int hwpart)
{
- struct mmc *mmc = find_mmc_device(dev_num);
+ struct mmc *mmc = find_mmc_device(desc->devnum);
int ret;
if (!mmc)
- return -1;
+ return -ENODEV;
- ret = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF,
- (mmc->part_config & ~PART_ACCESS_MASK)
- | (part_num & PART_ACCESS_MASK));
+ if (mmc->block_dev.hwpart == hwpart)
+ return 0;
- /*
- * Set the capacity if the switch succeeded or was intended
- * to return to representing the raw device.
- */
- if ((ret == 0) || ((ret == -ENODEV) && (part_num == 0))) {
- ret = mmc_set_capacity(mmc, part_num);
- mmc->block_dev.hwpart = part_num;
- }
+ if (mmc->part_config == MMCPART_NOAVAILABLE)
+ return -EMEDIUMTYPE;
- return ret;
+ ret = mmc_switch_part(mmc, hwpart);
+ if (ret)
+ return ret;
+
+ return 0;
}
+#endif
int mmc_hwpart_config(struct mmc *mmc,
const struct mmc_hwpart_conf *conf,
int timeout = 1000;
bool has_parts = false;
bool part_completed;
+ struct blk_desc *bdesc;
#ifdef CONFIG_MMC_SPI_CRC_ON
if (mmc_host_is_spi(mmc)) { /* enable CRC check for spi */
mmc->wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
}
- err = mmc_set_capacity(mmc, mmc->block_dev.hwpart);
+ err = mmc_set_capacity(mmc, mmc_get_blk_desc(mmc)->hwpart);
if (err)
return err;
}
/* fill in device description */
- mmc->block_dev.lun = 0;
- mmc->block_dev.hwpart = 0;
- mmc->block_dev.type = 0;
- mmc->block_dev.blksz = mmc->read_bl_len;
- mmc->block_dev.log2blksz = LOG2(mmc->block_dev.blksz);
- mmc->block_dev.lba = lldiv(mmc->capacity, mmc->read_bl_len);
+ bdesc = mmc_get_blk_desc(mmc);
+ bdesc->lun = 0;
+ bdesc->hwpart = 0;
+ bdesc->type = 0;
+ bdesc->blksz = mmc->read_bl_len;
+ bdesc->log2blksz = LOG2(bdesc->blksz);
+ bdesc->lba = lldiv(mmc->capacity, mmc->read_bl_len);
#if !defined(CONFIG_SPL_BUILD) || \
(defined(CONFIG_SPL_LIBCOMMON_SUPPORT) && \
!defined(CONFIG_USE_TINY_PRINTF))
- sprintf(mmc->block_dev.vendor, "Man %06x Snr %04x%04x",
+ sprintf(bdesc->vendor, "Man %06x Snr %04x%04x",
mmc->cid[0] >> 24, (mmc->cid[2] & 0xffff),
(mmc->cid[3] >> 16) & 0xffff);
- sprintf(mmc->block_dev.product, "%c%c%c%c%c%c", mmc->cid[0] & 0xff,
+ sprintf(bdesc->product, "%c%c%c%c%c%c", mmc->cid[0] & 0xff,
(mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff,
(mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff,
(mmc->cid[2] >> 24) & 0xff);
- sprintf(mmc->block_dev.revision, "%d.%d", (mmc->cid[2] >> 20) & 0xf,
+ sprintf(bdesc->revision, "%d.%d", (mmc->cid[2] >> 20) & 0xf,
(mmc->cid[2] >> 16) & 0xf);
#else
- mmc->block_dev.vendor[0] = 0;
- mmc->block_dev.product[0] = 0;
- mmc->block_dev.revision[0] = 0;
+ bdesc->vendor[0] = 0;
+ bdesc->product[0] = 0;
+ bdesc->revision[0] = 0;
#endif
#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBDISK_SUPPORT)
- part_init(&mmc->block_dev);
+ part_init(bdesc);
#endif
return 0;
return -1;
}
+#ifdef CONFIG_BLK
+int mmc_bind(struct udevice *dev, struct mmc *mmc, const struct mmc_config *cfg)
+{
+ struct blk_desc *bdesc;
+ struct udevice *bdev;
+ int ret;
+
+ ret = blk_create_devicef(dev, "mmc_blk", "blk", IF_TYPE_MMC, -1, 512,
+ 0, &bdev);
+ if (ret) {
+ debug("Cannot create block device\n");
+ return ret;
+ }
+ bdesc = dev_get_uclass_platdata(bdev);
+ mmc->cfg = cfg;
+ mmc->priv = dev;
+
+ /* the following chunk was from mmc_register() */
+
+ /* Setup dsr related values */
+ mmc->dsr_imp = 0;
+ mmc->dsr = 0xffffffff;
+ /* Setup the universal parts of the block interface just once */
+ bdesc->removable = 1;
+
+ /* setup initial part type */
+ bdesc->part_type = mmc->cfg->part_type;
+ mmc->dev = dev;
+
+ return 0;
+}
+
+int mmc_unbind(struct udevice *dev)
+{
+ struct udevice *bdev;
+
+ device_find_first_child(dev, &bdev);
+ if (bdev) {
+ device_remove(bdev);
+ device_unbind(bdev);
+ }
+
+ return 0;
+}
+
+#else
struct mmc *mmc_create(const struct mmc_config *cfg, void *priv)
{
+ struct blk_desc *bdesc;
struct mmc *mmc;
/* quick validation */
mmc->dsr_imp = 0;
mmc->dsr = 0xffffffff;
/* Setup the universal parts of the block interface just once */
- mmc->block_dev.if_type = IF_TYPE_MMC;
- mmc->block_dev.devnum = cur_dev_num++;
- mmc->block_dev.removable = 1;
- mmc->block_dev.block_read = mmc_bread;
- mmc->block_dev.block_write = mmc_bwrite;
- mmc->block_dev.block_erase = mmc_berase;
+ bdesc = mmc_get_blk_desc(mmc);
+ bdesc->if_type = IF_TYPE_MMC;
+ bdesc->removable = 1;
+ bdesc->devnum = mmc_get_next_devnum();
+ bdesc->block_read = mmc_bread;
+ bdesc->block_write = mmc_bwrite;
+ bdesc->block_erase = mmc_berase;
/* setup initial part type */
- mmc->block_dev.part_type = mmc->cfg->part_type;
-
- INIT_LIST_HEAD(&mmc->link);
-
- list_add_tail(&mmc->link, &mmc_devices);
+ bdesc->part_type = mmc->cfg->part_type;
+ mmc_list_add(mmc);
return mmc;
}
/* only freeing memory for now */
free(mmc);
}
+#endif
-#ifdef CONFIG_PARTITIONS
-struct blk_desc *mmc_get_dev(int dev)
+#ifndef CONFIG_BLK
+static int mmc_get_dev(int dev, struct blk_desc **descp)
{
struct mmc *mmc = find_mmc_device(dev);
- if (!mmc || mmc_init(mmc))
- return NULL;
+ int ret;
- return &mmc->block_dev;
+ if (!mmc)
+ return -ENODEV;
+ ret = mmc_init(mmc);
+ if (ret)
+ return ret;
+
+ *descp = &mmc->block_dev;
+
+ return 0;
}
#endif
return err;
/* The internal partition reset to user partition(0) at every CMD0*/
- mmc->block_dev.hwpart = 0;
+ mmc_get_blk_desc(mmc)->hwpart = 0;
/* Test for SD version 2 */
err = mmc_send_if_cond(mmc);
{
int err = 0;
unsigned start;
+#ifdef CONFIG_DM_MMC
+ struct mmc_uclass_priv *upriv = dev_get_uclass_priv(mmc->dev);
+ upriv->mmc = mmc;
+#endif
if (mmc->has_init)
return 0;
return -1;
}
-#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
-
-void print_mmc_devices(char separator)
-{
- struct mmc *m;
- struct list_head *entry;
- char *mmc_type;
-
- list_for_each(entry, &mmc_devices) {
- m = list_entry(entry, struct mmc, link);
-
- if (m->has_init)
- mmc_type = IS_SD(m) ? "SD" : "eMMC";
- else
- mmc_type = NULL;
-
- printf("%s: %d", m->cfg->name, m->block_dev.devnum);
- if (mmc_type)
- printf(" (%s)", mmc_type);
-
- if (entry->next != &mmc_devices) {
- printf("%c", separator);
- if (separator != '\n')
- puts (" ");
- }
- }
-
- printf("\n");
-}
-
-#else
-void print_mmc_devices(char separator) { }
-#endif
-
-int get_mmc_num(void)
-{
- return cur_dev_num;
-}
-
void mmc_set_preinit(struct mmc *mmc, int preinit)
{
mmc->preinit = preinit;
}
-static void do_preinit(void)
-{
- struct mmc *m;
- struct list_head *entry;
-
- list_for_each(entry, &mmc_devices) {
- m = list_entry(entry, struct mmc, link);
-
-#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
- mmc_set_preinit(m, 1);
-#endif
- if (m->preinit)
- mmc_start_init(m);
- }
-}
-
#if defined(CONFIG_DM_MMC) && defined(CONFIG_SPL_BUILD)
static int mmc_probe(bd_t *bis)
{
return 0;
initialized = 1;
- INIT_LIST_HEAD (&mmc_devices);
- cur_dev_num = 0;
-
+#ifndef CONFIG_BLK
+ mmc_list_init();
+#endif
ret = mmc_probe(bis);
if (ret)
return ret;
print_mmc_devices(',');
#endif
- do_preinit();
+ mmc_do_preinit();
return 0;
}
enable);
}
#endif
+
+#ifdef CONFIG_BLK
+static const struct blk_ops mmc_blk_ops = {
+ .read = mmc_bread,
+ .write = mmc_bwrite,
+ .select_hwpart = mmc_select_hwpart,
+};
+
+U_BOOT_DRIVER(mmc_blk) = {
+ .name = "mmc_blk",
+ .id = UCLASS_BLK,
+ .ops = &mmc_blk_ops,
+};
+#else
+U_BOOT_LEGACY_BLK(mmc) = {
+ .if_typename = "mmc",
+ .if_type = IF_TYPE_MMC,
+ .max_devs = -1,
+ .get_dev = mmc_get_dev,
+ .select_hwpart = mmc_select_hwpartp,
+};
+#endif
--- /dev/null
+/*
+ * Copyright (C) 2016 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <mmc.h>
+
+static struct list_head mmc_devices;
+static int cur_dev_num = -1;
+
+struct mmc *find_mmc_device(int dev_num)
+{
+ struct mmc *m;
+ struct list_head *entry;
+
+ list_for_each(entry, &mmc_devices) {
+ m = list_entry(entry, struct mmc, link);
+
+ if (m->block_dev.devnum == dev_num)
+ return m;
+ }
+
+#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
+ printf("MMC Device %d not found\n", dev_num);
+#endif
+
+ return NULL;
+}
+
+int mmc_get_next_devnum(void)
+{
+ return cur_dev_num++;
+}
+
+struct blk_desc *mmc_get_blk_desc(struct mmc *mmc)
+{
+ return &mmc->block_dev;
+}
+
+int get_mmc_num(void)
+{
+ return cur_dev_num;
+}
+
+void mmc_do_preinit(void)
+{
+ struct mmc *m;
+ struct list_head *entry;
+
+ list_for_each(entry, &mmc_devices) {
+ m = list_entry(entry, struct mmc, link);
+
+#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
+ mmc_set_preinit(m, 1);
+#endif
+ if (m->preinit)
+ mmc_start_init(m);
+ }
+}
+
+void mmc_list_init(void)
+{
+ INIT_LIST_HEAD(&mmc_devices);
+ cur_dev_num = 0;
+}
+
+void mmc_list_add(struct mmc *mmc)
+{
+ INIT_LIST_HEAD(&mmc->link);
+
+ list_add_tail(&mmc->link, &mmc_devices);
+}
+
+#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
+void print_mmc_devices(char separator)
+{
+ struct mmc *m;
+ struct list_head *entry;
+ char *mmc_type;
+
+ list_for_each(entry, &mmc_devices) {
+ m = list_entry(entry, struct mmc, link);
+
+ if (m->has_init)
+ mmc_type = IS_SD(m) ? "SD" : "eMMC";
+ else
+ mmc_type = NULL;
+
+ printf("%s: %d", m->cfg->name, m->block_dev.devnum);
+ if (mmc_type)
+ printf(" (%s)", mmc_type);
+
+ if (entry->next != &mmc_devices) {
+ printf("%c", separator);
+ if (separator != '\n')
+ puts(" ");
+ }
+ }
+
+ printf("\n");
+}
+
+#else
+void print_mmc_devices(char separator) { }
+#endif
unsigned long mmc_berase(struct blk_desc *block_dev, lbaint_t start,
lbaint_t blkcnt);
-unsigned long mmc_bwrite(struct blk_desc *block_dev, lbaint_t start,
- lbaint_t blkcnt, const void *src);
+#ifdef CONFIG_BLK
+ulong mmc_bwrite(struct udevice *dev, lbaint_t start, lbaint_t blkcnt,
+ const void *src);
+#else
+ulong mmc_bwrite(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt,
+ const void *src);
+#endif
#else /* CONFIG_SPL_BUILD */
#endif /* CONFIG_SPL_BUILD */
+/**
+ * mmc_get_next_devnum() - Get the next available MMC device number
+ *
+ * @return next available device number (0 = first), or -ve on error
+ */
+int mmc_get_next_devnum(void);
+
+/**
+ * mmc_do_preinit() - Get an MMC device ready for use
+ */
+void mmc_do_preinit(void);
+
+/**
+ * mmc_list_init() - Set up the list of MMC devices
+ */
+void mmc_list_init(void);
+
+/**
+ * mmc_list_add() - Add a new MMC device to the list of devices
+ *
+ * @mmc: Device to add
+ */
+void mmc_list_add(struct mmc *mmc);
+
#endif /* _MMC_PRIVATE_H_ */
#include <config.h>
#include <common.h>
+#include <dm.h>
#include <part.h>
#include <div64.h>
#include <linux/math64.h>
if (!mmc)
return -1;
- err = mmc_select_hwpart(dev_num, block_dev->hwpart);
+ err = blk_select_hwpart_devnum(IF_TYPE_MMC, dev_num,
+ block_dev->hwpart);
if (err < 0)
return -1;
struct mmc_data data;
int timeout = 1000;
- if ((start + blkcnt) > mmc->block_dev.lba) {
+ if ((start + blkcnt) > mmc_get_blk_desc(mmc)->lba) {
printf("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n",
- start + blkcnt, mmc->block_dev.lba);
+ start + blkcnt, mmc_get_blk_desc(mmc)->lba);
return 0;
}
return blkcnt;
}
+#ifdef CONFIG_BLK
+ulong mmc_bwrite(struct udevice *dev, lbaint_t start, lbaint_t blkcnt,
+ const void *src)
+#else
ulong mmc_bwrite(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt,
const void *src)
+#endif
{
+#ifdef CONFIG_BLK
+ struct blk_desc *block_dev = dev_get_uclass_platdata(dev);
+#endif
int dev_num = block_dev->devnum;
lbaint_t cur, blocks_todo = blkcnt;
int err;
if (!mmc)
return 0;
- err = mmc_select_hwpart(dev_num, block_dev->hwpart);
+ err = blk_select_hwpart_devnum(IF_TYPE_MMC, dev_num, block_dev->hwpart);
if (err < 0)
return 0;
gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN);
#endif
+ mmc->dev = dev;
upriv->mmc = mmc;
return 0;
return ret;
}
- return add_sdhci(host, f_min_max[1], f_min_max[0]);
+ ret = add_sdhci(host, f_min_max[1], f_min_max[0]);
+ if (ret)
+ return ret;
+ host->mmc->dev = dev;
+
+ return 0;
}
static const struct udevice_id pic32_sdhci_ids[] = {
if (ret)
return ret;
+ host->mmc->dev = dev;
upriv->mmc = host->mmc;
return 0;
#include <common.h>
#include <dm.h>
#include <errno.h>
+#include <fdtdec.h>
#include <mmc.h>
#include <asm/test.h>
DECLARE_GLOBAL_DATA_PTR;
+struct sandbox_mmc_plat {
+ struct mmc_config cfg;
+ struct mmc mmc;
+};
+
+/**
+ * sandbox_mmc_send_cmd() - Emulate SD commands
+ *
+ * This emulate an SD card version 2. Single-block reads result in zero data.
+ * Multiple-block reads return a test string.
+ */
+static int sandbox_mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
+ struct mmc_data *data)
+{
+ switch (cmd->cmdidx) {
+ case MMC_CMD_ALL_SEND_CID:
+ break;
+ case SD_CMD_SEND_RELATIVE_ADDR:
+ cmd->response[0] = 0 << 16; /* mmc->rca */
+ case MMC_CMD_GO_IDLE_STATE:
+ break;
+ case SD_CMD_SEND_IF_COND:
+ cmd->response[0] = 0xaa;
+ break;
+ case MMC_CMD_SEND_STATUS:
+ cmd->response[0] = MMC_STATUS_RDY_FOR_DATA;
+ break;
+ case MMC_CMD_SELECT_CARD:
+ break;
+ case MMC_CMD_SEND_CSD:
+ cmd->response[0] = 0;
+ cmd->response[1] = 10 << 16; /* 1 << block_len */
+ break;
+ case SD_CMD_SWITCH_FUNC: {
+ u32 *resp = (u32 *)data->dest;
+
+ resp[7] = cpu_to_be32(SD_HIGHSPEED_BUSY);
+ break;
+ }
+ case MMC_CMD_READ_SINGLE_BLOCK:
+ memset(data->dest, '\0', data->blocksize);
+ break;
+ case MMC_CMD_READ_MULTIPLE_BLOCK:
+ strcpy(data->dest, "this is a test");
+ break;
+ case MMC_CMD_STOP_TRANSMISSION:
+ break;
+ case SD_CMD_APP_SEND_OP_COND:
+ cmd->response[0] = OCR_BUSY | OCR_HCS;
+ cmd->response[1] = 0;
+ cmd->response[2] = 0;
+ break;
+ case MMC_CMD_APP_CMD:
+ break;
+ case MMC_CMD_SET_BLOCKLEN:
+ debug("block len %d\n", cmd->cmdarg);
+ break;
+ case SD_CMD_APP_SEND_SCR: {
+ u32 *scr = (u32 *)data->dest;
+
+ scr[0] = cpu_to_be32(2 << 24 | 1 << 15); /* SD version 3 */
+ break;
+ }
+ default:
+ debug("%s: Unknown command %d\n", __func__, cmd->cmdidx);
+ break;
+ }
+
+ return 0;
+}
+
+static void sandbox_mmc_set_ios(struct mmc *mmc)
+{
+}
+
+static int sandbox_mmc_init(struct mmc *mmc)
+{
+ return 0;
+}
+
+static int sandbox_mmc_getcd(struct mmc *mmc)
+{
+ return 1;
+}
+
+static const struct mmc_ops sandbox_mmc_ops = {
+ .send_cmd = sandbox_mmc_send_cmd,
+ .set_ios = sandbox_mmc_set_ios,
+ .init = sandbox_mmc_init,
+ .getcd = sandbox_mmc_getcd,
+};
+
+int sandbox_mmc_probe(struct udevice *dev)
+{
+ struct sandbox_mmc_plat *plat = dev_get_platdata(dev);
+
+ return mmc_init(&plat->mmc);
+}
+
+int sandbox_mmc_bind(struct udevice *dev)
+{
+ struct sandbox_mmc_plat *plat = dev_get_platdata(dev);
+ struct mmc_config *cfg = &plat->cfg;
+ int ret;
+
+ cfg->name = dev->name;
+ cfg->ops = &sandbox_mmc_ops;
+ cfg->host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_8BIT;
+ cfg->voltages = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34;
+ cfg->f_min = 1000000;
+ cfg->f_max = 52000000;
+ cfg->b_max = U32_MAX;
+
+ ret = mmc_bind(dev, &plat->mmc, cfg);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+int sandbox_mmc_unbind(struct udevice *dev)
+{
+ mmc_unbind(dev);
+
+ return 0;
+}
+
static const struct udevice_id sandbox_mmc_ids[] = {
{ .compatible = "sandbox,mmc" },
{ }
};
-U_BOOT_DRIVER(warm_mmc_sandbox) = {
+U_BOOT_DRIVER(mmc_sandbox) = {
.name = "mmc_sandbox",
.id = UCLASS_MMC,
.of_match = sandbox_mmc_ids,
+ .bind = sandbox_mmc_bind,
+ .unbind = sandbox_mmc_unbind,
+ .probe = sandbox_mmc_probe,
+ .platdata_auto_alloc_size = sizeof(struct sandbox_mmc_plat),
};
return ret;
upriv->mmc = host->mmc;
+ host->mmc->dev = dev;
return 0;
}
return -EIO;
upriv->mmc = priv->mmc;
+ priv->mmc->dev = dev;
return 0;
}
CONFIG_ZYNQ_SDHCI_MIN_FREQ);
upriv->mmc = host->mmc;
+ host->mmc->dev = dev;
return 0;
}
NOR flash to parallel flash interface. Please find details on the
"Embedded Peripherals IP User Guide" of Altera.
+config FLASH_PIC32
+ bool "Microchip PIC32 Flash driver"
+ depends on MACH_PIC32 && MTD
+ help
+ This enables access to Microchip PIC32 internal non-CFI flash
+ chips through PIC32 Non-Volatile-Memory Controller.
+
endmenu
source "drivers/mtd/nand/Kconfig"
obj-$(CONFIG_FTSMC020) += ftsmc020.o
obj-$(CONFIG_FLASH_CFI_LEGACY) += jedec_flash.o
obj-$(CONFIG_MW_EEPROM) += mw_eeprom.o
+obj-$(CONFIG_FLASH_PIC32) += pic32_flash.o
obj-$(CONFIG_ST_SMI) += st_smi.o
obj-$(CONFIG_STM32_FLASH) += stm32_flash.o
--- /dev/null
+/*
+ * Copyright (C) 2015
+ * Cristian Birsan <cristian.birsan@microchip.com>
+ * Purna Chandra Mandal <purna.mandal@microchip.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <fdt_support.h>
+#include <flash.h>
+#include <mach/pic32.h>
+#include <wait_bit.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* NVM Controller registers */
+struct pic32_reg_nvm {
+ struct pic32_reg_atomic ctrl;
+ struct pic32_reg_atomic key;
+ struct pic32_reg_atomic addr;
+ struct pic32_reg_atomic data;
+};
+
+/* NVM operations */
+#define NVMOP_NOP 0
+#define NVMOP_WORD_WRITE 1
+#define NVMOP_PAGE_ERASE 4
+
+/* NVM control bits */
+#define NVM_WR BIT(15)
+#define NVM_WREN BIT(14)
+#define NVM_WRERR BIT(13)
+#define NVM_LVDERR BIT(12)
+
+/* NVM programming unlock register */
+#define LOCK_KEY 0x0
+#define UNLOCK_KEY1 0xaa996655
+#define UNLOCK_KEY2 0x556699aa
+
+/*
+ * PIC32 flash banks consist of number of pages, each page
+ * into number of rows and rows into number of words.
+ * Here we will maintain page information instead of sector.
+ */
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
+static struct pic32_reg_nvm *nvm_regs_p;
+
+static inline void flash_initiate_operation(u32 nvmop)
+{
+ /* set operation */
+ writel(nvmop, &nvm_regs_p->ctrl.raw);
+
+ /* enable flash write */
+ writel(NVM_WREN, &nvm_regs_p->ctrl.set);
+
+ /* unlock sequence */
+ writel(LOCK_KEY, &nvm_regs_p->key.raw);
+ writel(UNLOCK_KEY1, &nvm_regs_p->key.raw);
+ writel(UNLOCK_KEY2, &nvm_regs_p->key.raw);
+
+ /* initiate operation */
+ writel(NVM_WR, &nvm_regs_p->ctrl.set);
+}
+
+static int flash_wait_till_busy(const char *func, ulong timeout)
+{
+ int ret = wait_for_bit(__func__, &nvm_regs_p->ctrl.raw,
+ NVM_WR, false, timeout, false);
+
+ return ret ? ERR_TIMOUT : ERR_OK;
+}
+
+static inline int flash_complete_operation(void)
+{
+ u32 tmp;
+
+ tmp = readl(&nvm_regs_p->ctrl.raw);
+ if (tmp & NVM_WRERR) {
+ printf("Error in Block Erase - Lock Bit may be set!\n");
+ flash_initiate_operation(NVMOP_NOP);
+ return ERR_PROTECTED;
+ }
+
+ if (tmp & NVM_LVDERR) {
+ printf("Error in Block Erase - low-vol detected!\n");
+ flash_initiate_operation(NVMOP_NOP);
+ return ERR_NOT_ERASED;
+ }
+
+ /* disable flash write or erase operation */
+ writel(NVM_WREN, &nvm_regs_p->ctrl.clr);
+
+ return ERR_OK;
+}
+
+/*
+ * Erase flash sectors, returns:
+ * ERR_OK - OK
+ * ERR_INVAL - invalid sector arguments
+ * ERR_TIMOUT - write timeout
+ * ERR_NOT_ERASED - Flash not erased
+ * ERR_UNKNOWN_FLASH_VENDOR - incorrect flash
+ */
+int flash_erase(flash_info_t *info, int s_first, int s_last)
+{
+ ulong sect_start, sect_end, flags;
+ int prot, sect;
+ int rc;
+
+ if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_MCHP) {
+ printf("Can't erase unknown flash type %08lx - aborted\n",
+ info->flash_id);
+ return ERR_UNKNOWN_FLASH_VENDOR;
+ }
+
+ if ((s_first < 0) || (s_first > s_last)) {
+ printf("- no sectors to erase\n");
+ return ERR_INVAL;
+ }
+
+ prot = 0;
+ for (sect = s_first; sect <= s_last; ++sect) {
+ if (info->protect[sect])
+ prot++;
+ }
+
+ if (prot)
+ printf("- Warning: %d protected sectors will not be erased!\n",
+ prot);
+ else
+ printf("\n");
+
+ /* erase on unprotected sectors */
+ for (sect = s_first; sect <= s_last; sect++) {
+ if (info->protect[sect])
+ continue;
+
+ /* disable interrupts */
+ flags = disable_interrupts();
+
+ /* write destination page address (physical) */
+ sect_start = CPHYSADDR(info->start[sect]);
+ writel(sect_start, &nvm_regs_p->addr.raw);
+
+ /* page erase */
+ flash_initiate_operation(NVMOP_PAGE_ERASE);
+
+ /* wait */
+ rc = flash_wait_till_busy(__func__,
+ CONFIG_SYS_FLASH_ERASE_TOUT);
+
+ /* re-enable interrupts if necessary */
+ if (flags)
+ enable_interrupts();
+
+ if (rc != ERR_OK)
+ return rc;
+
+ rc = flash_complete_operation();
+ if (rc != ERR_OK)
+ return rc;
+
+ /*
+ * flash content is updated but cache might contain stale
+ * data, so invalidate dcache.
+ */
+ sect_end = info->start[sect] + info->size / info->sector_count;
+ invalidate_dcache_range(info->start[sect], sect_end);
+ }
+
+ printf(" done\n");
+ return ERR_OK;
+}
+
+int page_erase(flash_info_t *info, int sect)
+{
+ return 0;
+}
+
+/* Write a word to flash */
+static int write_word(flash_info_t *info, ulong dest, ulong word)
+{
+ ulong flags;
+ int rc;
+
+ /* read flash to check if it is sufficiently erased */
+ if ((readl((void __iomem *)dest) & word) != word) {
+ printf("Error, Flash not erased!\n");
+ return ERR_NOT_ERASED;
+ }
+
+ /* disable interrupts */
+ flags = disable_interrupts();
+
+ /* update destination page address (physical) */
+ writel(CPHYSADDR(dest), &nvm_regs_p->addr.raw);
+ writel(word, &nvm_regs_p->data.raw);
+
+ /* word write */
+ flash_initiate_operation(NVMOP_WORD_WRITE);
+
+ /* wait for operation to complete */
+ rc = flash_wait_till_busy(__func__, CONFIG_SYS_FLASH_WRITE_TOUT);
+
+ /* re-enable interrupts if necessary */
+ if (flags)
+ enable_interrupts();
+
+ if (rc != ERR_OK)
+ return rc;
+
+ return flash_complete_operation();
+}
+
+/*
+ * Copy memory to flash, returns:
+ * ERR_OK - OK
+ * ERR_TIMOUT - write timeout
+ * ERR_NOT_ERASED - Flash not erased
+ */
+int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+ ulong dst, tmp_le, len = cnt;
+ int i, l, rc;
+ uchar *cp;
+
+ /* get lower word aligned address */
+ dst = (addr & ~3);
+
+ /* handle unaligned start bytes */
+ l = addr - dst;
+ if (l != 0) {
+ tmp_le = 0;
+ for (i = 0, cp = (uchar *)dst; i < l; ++i, ++cp)
+ tmp_le |= *cp << (i * 8);
+
+ for (; (i < 4) && (cnt > 0); ++i, ++src, --cnt, ++cp)
+ tmp_le |= *src << (i * 8);
+
+ for (; (cnt == 0) && (i < 4); ++i, ++cp)
+ tmp_le |= *cp << (i * 8);
+
+ rc = write_word(info, dst, tmp_le);
+ if (rc)
+ goto out;
+
+ dst += 4;
+ }
+
+ /* handle word aligned part */
+ while (cnt >= 4) {
+ tmp_le = src[0] | src[1] << 8 | src[2] << 16 | src[3] << 24;
+ rc = write_word(info, dst, tmp_le);
+ if (rc)
+ goto out;
+ src += 4;
+ dst += 4;
+ cnt -= 4;
+ }
+
+ if (cnt == 0) {
+ rc = ERR_OK;
+ goto out;
+ }
+
+ /* handle unaligned tail bytes */
+ tmp_le = 0;
+ for (i = 0, cp = (uchar *)dst; (i < 4) && (cnt > 0); ++i, ++cp) {
+ tmp_le |= *src++ << (i * 8);
+ --cnt;
+ }
+
+ for (; i < 4; ++i, ++cp)
+ tmp_le |= *cp << (i * 8);
+
+ rc = write_word(info, dst, tmp_le);
+out:
+ /*
+ * flash content updated by nvm controller but CPU cache might
+ * have stale data, so invalidate dcache.
+ */
+ invalidate_dcache_range(addr, addr + len);
+
+ printf(" done\n");
+ return rc;
+}
+
+void flash_print_info(flash_info_t *info)
+{
+ int i;
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf("missing or unknown FLASH type\n");
+ return;
+ }
+
+ switch (info->flash_id & FLASH_VENDMASK) {
+ case FLASH_MAN_MCHP:
+ printf("Microchip Technology ");
+ break;
+ default:
+ printf("Unknown Vendor ");
+ break;
+ }
+
+ switch (info->flash_id & FLASH_TYPEMASK) {
+ case FLASH_MCHP100T:
+ printf("Internal (8 Mbit, 64 x 16k)\n");
+ break;
+ default:
+ printf("Unknown Chip Type\n");
+ break;
+ }
+
+ printf(" Size: %ld MB in %d Sectors\n",
+ info->size >> 20, info->sector_count);
+
+ printf(" Sector Start Addresses:");
+ for (i = 0; i < info->sector_count; ++i) {
+ if ((i % 5) == 0)
+ printf("\n ");
+
+ printf(" %08lX%s", info->start[i],
+ info->protect[i] ? " (RO)" : " ");
+ }
+ printf("\n");
+}
+
+unsigned long flash_init(void)
+{
+ unsigned long size = 0;
+ struct udevice *dev;
+ int bank;
+
+ /* probe every MTD device */
+ for (uclass_first_device(UCLASS_MTD, &dev); dev;
+ uclass_next_device(&dev)) {
+ /* nop */
+ }
+
+ /* calc total flash size */
+ for (bank = 0; bank < CONFIG_SYS_MAX_FLASH_BANKS; ++bank)
+ size += flash_info[bank].size;
+
+ return size;
+}
+
+static void pic32_flash_bank_init(flash_info_t *info,
+ ulong base, ulong size)
+{
+ ulong sect_size;
+ int sect;
+
+ /* device & manufacturer code */
+ info->flash_id = FLASH_MAN_MCHP | FLASH_MCHP100T;
+ info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+ info->size = size;
+
+ /* update sector (i.e page) info */
+ sect_size = info->size / info->sector_count;
+ for (sect = 0; sect < info->sector_count; sect++) {
+ info->start[sect] = base;
+ /* protect each sector by default */
+ info->protect[sect] = 1;
+ base += sect_size;
+ }
+}
+
+static int pic32_flash_probe(struct udevice *dev)
+{
+ void *blob = (void *)gd->fdt_blob;
+ int node = dev->of_offset;
+ const char *list, *end;
+ const fdt32_t *cell;
+ unsigned long addr, size;
+ int parent, addrc, sizec;
+ flash_info_t *info;
+ int len, idx;
+
+ /*
+ * decode regs. there are multiple reg tuples, and they need to
+ * match with reg-names.
+ */
+ parent = fdt_parent_offset(blob, node);
+ of_bus_default_count_cells(blob, parent, &addrc, &sizec);
+ list = fdt_getprop(blob, node, "reg-names", &len);
+ if (!list)
+ return -ENOENT;
+
+ end = list + len;
+ cell = fdt_getprop(blob, node, "reg", &len);
+ if (!cell)
+ return -ENOENT;
+
+ for (idx = 0, info = &flash_info[0]; list < end;) {
+ addr = fdt_translate_address((void *)blob, node, cell + idx);
+ size = fdt_addr_to_cpu(cell[idx + addrc]);
+ len = strlen(list);
+ if (!strncmp(list, "nvm", len)) {
+ /* NVM controller */
+ nvm_regs_p = ioremap(addr, size);
+ } else if (!strncmp(list, "bank", 4)) {
+ /* Flash bank: use kseg0 cached address */
+ pic32_flash_bank_init(info, CKSEG0ADDR(addr), size);
+ info++;
+ }
+ idx += addrc + sizec;
+ list += len + 1;
+ }
+
+ /* disable flash write/erase operations */
+ writel(NVM_WREN, &nvm_regs_p->ctrl.clr);
+
+#if (CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE)
+ /* monitor protection ON by default */
+ flash_protect(FLAG_PROTECT_SET,
+ CONFIG_SYS_MONITOR_BASE,
+ CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
+ &flash_info[0]);
+#endif
+
+#ifdef CONFIG_ENV_IS_IN_FLASH
+ /* ENV protection ON by default */
+ flash_protect(FLAG_PROTECT_SET,
+ CONFIG_ENV_ADDR,
+ CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
+ &flash_info[0]);
+#endif
+ return 0;
+}
+
+static const struct udevice_id pic32_flash_ids[] = {
+ { .compatible = "microchip,pic32mzda-flash" },
+ {}
+};
+
+U_BOOT_DRIVER(pic32_flash) = {
+ .name = "pic32_flash",
+ .id = UCLASS_MTD,
+ .of_match = pic32_flash_ids,
+ .probe = pic32_flash_probe,
+};
const void *buf);
#endif
+#ifdef CONFIG_SPI_FLASH_SPANSION
+/* Used for Spansion S25FS-S family flash only. */
+#define CMD_SPANSION_RDAR 0x65 /* Read any device register */
+#define CMD_SPANSION_WRAR 0x71 /* Write any device register */
+#endif
/**
* struct spi_flash_params - SPI/QSPI flash device params structure
*
}
#endif /* CONFIG_IS_ENABLED(OF_CONTROL) */
+#ifdef CONFIG_SPI_FLASH_SPANSION
+static int spansion_s25fss_disable_4KB_erase(struct spi_slave *spi)
+{
+ u8 cmd[4];
+ u32 offset = 0x800004; /* CR3V register offset */
+ u8 cr3v;
+ int ret;
+
+ cmd[0] = CMD_SPANSION_RDAR;
+ cmd[1] = offset >> 16;
+ cmd[2] = offset >> 8;
+ cmd[3] = offset >> 0;
+
+ ret = spi_flash_cmd_read(spi, cmd, 4, &cr3v, 1);
+ if (ret)
+ return -EIO;
+ /* CR3V bit3: 4-KB Erase */
+ if (cr3v & 0x8)
+ return 0;
+
+ cmd[0] = CMD_SPANSION_WRAR;
+ cr3v |= 0x8;
+ ret = spi_flash_cmd_write(spi, cmd, 4, &cr3v, 1);
+ if (ret)
+ return -EIO;
+
+ cmd[0] = CMD_SPANSION_RDAR;
+ ret = spi_flash_cmd_read(spi, cmd, 4, &cr3v, 1);
+ if (ret)
+ return -EIO;
+ if (!(cr3v & 0x8))
+ return -EFAULT;
+
+ return 0;
+}
+#endif
+
int spi_flash_scan(struct spi_flash *flash)
{
struct spi_slave *spi = flash->spi;
return -EPROTONOSUPPORT;
}
+#ifdef CONFIG_SPI_FLASH_SPANSION
+ /*
+ * The S25FS-S family physical sectors may be configured as a
+ * hybrid combination of eight 4-kB parameter sectors
+ * at the top or bottom of the address space with all
+ * but one of the remaining sectors being uniform size.
+ * The Parameter Sector Erase commands (20h or 21h) must
+ * be used to erase the 4-kB parameter sectors individually.
+ * The Sector (uniform sector) Erase commands (D8h or DCh)
+ * must be used to erase any of the remaining
+ * sectors, including the portion of highest or lowest address
+ * sector that is not overlaid by the parameter sectors.
+ * The uniform sector erase command has no effect on parameter sectors.
+ */
+ if (jedec == 0x0219 && (ext_jedec & 0xff00) == 0x4d00) {
+ int ret;
+ u8 id[6];
+
+ /* Read the ID codes again, 6 bytes */
+ ret = spi_flash_cmd(flash->spi, CMD_READ_ID, id, sizeof(id));
+ if (ret)
+ return -EIO;
+
+ ret = memcmp(id, idcode, 5);
+ if (ret)
+ return -EIO;
+
+ /* 0x81: S25FS-S family 0x80: S25FL-S family */
+ if (id[5] == 0x81) {
+ ret = spansion_s25fss_disable_4KB_erase(spi);
+ if (ret)
+ return ret;
+ }
+ }
+#endif
/* Flash powers up read-only, so clear BP# bits */
if (idcode[0] == SPI_FLASH_CFI_MFR_ATMEL ||
idcode[0] == SPI_FLASH_CFI_MFR_MACRONIX ||
static int spi_load_image_os(struct spi_flash *flash,
struct image_header *header)
{
+ int err;
+
/* Read for a header, parse or error out. */
spi_flash_read(flash, CONFIG_SYS_SPI_KERNEL_OFFS, 0x40,
(void *)header);
if (image_get_magic(header) != IH_MAGIC)
return -1;
- spl_parse_image_header(header);
+ err = spl_parse_image_header(header);
+ if (err)
+ return err;
spi_flash_read(flash, CONFIG_SYS_SPI_KERNEL_OFFS,
spl_image.size, (void *)spl_image.load_addr);
if (err)
return err;
- spl_parse_image_header(header);
+ err = spl_parse_image_header(header);
+ if (err)
+ return err;
err = spi_flash_read(flash, CONFIG_SYS_SPI_U_BOOT_OFFS,
spl_image.size, (void *)spl_image.load_addr);
}
obj-$(CONFIG_SMC911X) += smc911x.o
obj-$(CONFIG_DRIVER_TI_EMAC) += davinci_emac.o
obj-$(CONFIG_TSEC_ENET) += tsec.o fsl_mdio.o
-obj-$(CONFIG_DRIVER_TI_CPSW) += cpsw.o
+obj-$(CONFIG_DRIVER_TI_CPSW) += cpsw.o cpsw-common.o
obj-$(CONFIG_FMAN_ENET) += fsl_mdio.o
obj-$(CONFIG_TSI108_ETH) += tsi108_eth.o
obj-$(CONFIG_ULI526X) += uli526x.o
--- /dev/null
+/*
+ * CPSW common - libs used across TI ethernet devices.
+ *
+ * Copyright (C) 2016, Texas Instruments, Incorporated
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <fdt_support.h>
+#include <asm/io.h>
+#include <cpsw.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define CTRL_MAC_REG(offset, id) ((offset) + 0x8 * (id))
+
+static int davinci_emac_3517_get_macid(struct udevice *dev, u16 offset,
+ int slave, u8 *mac_addr)
+{
+ void *fdt = (void *)gd->fdt_blob;
+ int node = dev->of_offset;
+ u32 macid_lsb;
+ u32 macid_msb;
+ fdt32_t gmii = 0;
+ int syscon;
+ u32 addr;
+
+ syscon = fdtdec_lookup_phandle(fdt, node, "syscon");
+ if (syscon < 0) {
+ error("Syscon offset not found\n");
+ return -ENOENT;
+ }
+
+ addr = (u32)map_physmem(fdt_translate_address(fdt, syscon, &gmii),
+ sizeof(u32), MAP_NOCACHE);
+ if (addr == FDT_ADDR_T_NONE) {
+ error("Not able to get syscon address to get mac efuse address\n");
+ return -ENOENT;
+ }
+
+ addr += CTRL_MAC_REG(offset, slave);
+
+ /* try reading mac address from efuse */
+ macid_lsb = readl(addr);
+ macid_msb = readl(addr + 4);
+
+ mac_addr[0] = (macid_msb >> 16) & 0xff;
+ mac_addr[1] = (macid_msb >> 8) & 0xff;
+ mac_addr[2] = macid_msb & 0xff;
+ mac_addr[3] = (macid_lsb >> 16) & 0xff;
+ mac_addr[4] = (macid_lsb >> 8) & 0xff;
+ mac_addr[5] = macid_lsb & 0xff;
+
+ return 0;
+}
+
+static int cpsw_am33xx_cm_get_macid(struct udevice *dev, u16 offset, int slave,
+ u8 *mac_addr)
+{
+ void *fdt = (void *)gd->fdt_blob;
+ int node = dev->of_offset;
+ u32 macid_lo;
+ u32 macid_hi;
+ fdt32_t gmii = 0;
+ int syscon;
+ u32 addr;
+
+ syscon = fdtdec_lookup_phandle(fdt, node, "syscon");
+ if (syscon < 0) {
+ error("Syscon offset not found\n");
+ return -ENOENT;
+ }
+
+ addr = (u32)map_physmem(fdt_translate_address(fdt, syscon, &gmii),
+ sizeof(u32), MAP_NOCACHE);
+ if (addr == FDT_ADDR_T_NONE) {
+ error("Not able to get syscon address to get mac efuse address\n");
+ return -ENOENT;
+ }
+
+ addr += CTRL_MAC_REG(offset, slave);
+
+ /* try reading mac address from efuse */
+ macid_lo = readl(addr);
+ macid_hi = readl(addr + 4);
+
+ mac_addr[5] = (macid_lo >> 8) & 0xff;
+ mac_addr[4] = macid_lo & 0xff;
+ mac_addr[3] = (macid_hi >> 24) & 0xff;
+ mac_addr[2] = (macid_hi >> 16) & 0xff;
+ mac_addr[1] = (macid_hi >> 8) & 0xff;
+ mac_addr[0] = macid_hi & 0xff;
+
+ return 0;
+}
+
+int ti_cm_get_macid(struct udevice *dev, int slave, u8 *mac_addr)
+{
+ if (of_machine_is_compatible("ti,dm8148"))
+ return cpsw_am33xx_cm_get_macid(dev, 0x630, slave, mac_addr);
+
+ if (of_machine_is_compatible("ti,am33xx"))
+ return cpsw_am33xx_cm_get_macid(dev, 0x630, slave, mac_addr);
+
+ if (of_device_is_compatible(dev, "ti,am3517-emac"))
+ return davinci_emac_3517_get_macid(dev, 0x110, slave, mac_addr);
+
+ if (of_device_is_compatible(dev, "ti,dm816-emac"))
+ return cpsw_am33xx_cm_get_macid(dev, 0x30, slave, mac_addr);
+
+ if (of_machine_is_compatible("ti,am4372"))
+ return cpsw_am33xx_cm_get_macid(dev, 0x630, slave, mac_addr);
+
+ if (of_machine_is_compatible("ti,dra7"))
+ return davinci_emac_3517_get_macid(dev, 0x514, slave, mac_addr);
+
+ dev_err(dev, "incompatible machine/device type for reading mac address\n");
+ return -ENOENT;
+}
#include <phy.h>
#include <asm/arch/cpu.h>
#include <dm.h>
+#include <fdt_support.h>
DECLARE_GLOBAL_DATA_PTR;
phydev->supported &= supported;
phydev->advertising = phydev->supported;
+#ifdef CONFIG_DM_ETH
+ if (slave->data->phy_of_handle)
+ phydev->dev->of_offset = slave->data->phy_of_handle;
+#endif
+
priv->phydev = phydev;
phy_config(phydev);
.stop = cpsw_eth_stop,
};
+static inline fdt_addr_t cpsw_get_addr_by_node(const void *fdt, int node)
+{
+ return fdtdec_get_addr_size_auto_noparent(fdt, node, "reg", 0, NULL);
+}
+
static int cpsw_eth_ofdata_to_platdata(struct udevice *dev)
{
struct eth_pdata *pdata = dev_get_platdata(dev);
int node = dev->of_offset;
int subnode;
int slave_index = 0;
- uint32_t mac_hi, mac_lo;
- fdt32_t gmii = 0;
int active_slave;
+ int ret;
pdata->iobase = dev_get_addr(dev);
priv->data.version = CPSW_CTRL_VERSION_2;
name = fdt_get_name(fdt, subnode, &len);
if (!strncmp(name, "mdio", 4)) {
- priv->data.mdio_base = fdtdec_get_addr(fdt, subnode,
- "reg");
+ u32 mdio_base;
+
+ mdio_base = cpsw_get_addr_by_node(fdt, subnode);
+ if (mdio_base == FDT_ADDR_T_NONE) {
+ error("Not able to get MDIO address space\n");
+ return -ENOENT;
+ }
+ priv->data.mdio_base = mdio_base;
}
if (!strncmp(name, "slave", 5)) {
u32 phy_id[2];
- if (slave_index >= priv->data.slaves) {
- printf("error: num slaves and slave nodes did not match\n");
- return -EINVAL;
- }
+ if (slave_index >= priv->data.slaves)
+ continue;
phy_mode = fdt_getprop(fdt, subnode, "phy-mode", NULL);
if (phy_mode)
priv->data.slave_data[slave_index].phy_if =
phy_get_interface_by_name(phy_mode);
- fdtdec_get_int_array(fdt, subnode, "phy_id", phy_id, 2);
- priv->data.slave_data[slave_index].phy_addr = phy_id[1];
+
+ priv->data.slave_data[slave_index].phy_of_handle =
+ fdtdec_lookup_phandle(fdt, subnode,
+ "phy-handle");
+
+ if (priv->data.slave_data[slave_index].phy_of_handle >= 0) {
+ priv->data.slave_data[slave_index].phy_addr =
+ fdtdec_get_int(gd->fdt_blob,
+ priv->data.slave_data[slave_index].phy_of_handle,
+ "reg", -1);
+ } else {
+ fdtdec_get_int_array(fdt, subnode, "phy_id",
+ phy_id, 2);
+ priv->data.slave_data[slave_index].phy_addr =
+ phy_id[1];
+ }
slave_index++;
}
if (!strncmp(name, "cpsw-phy-sel", 12)) {
- priv->data.gmii_sel = fdtdec_get_addr(fdt, subnode,
- "reg");
+ priv->data.gmii_sel = cpsw_get_addr_by_node(fdt,
+ subnode);
+
+ if (priv->data.gmii_sel == FDT_ADDR_T_NONE) {
+ error("Not able to get gmii_sel reg address\n");
+ return -ENOENT;
+ }
}
}
priv->data.slave_data[1].sliver_reg_ofs = CPSW_SLIVER1_OFFSET;
}
- subnode = fdtdec_lookup_phandle(fdt, node, "syscon");
- priv->data.mac_id = fdt_translate_address((void *)fdt, subnode, &gmii);
- priv->data.mac_id += AM335X_GMII_SEL_OFFSET;
- priv->data.mac_id += active_slave * 8;
-
- /* try reading mac address from efuse */
- mac_lo = readl(priv->data.mac_id);
- mac_hi = readl(priv->data.mac_id + 4);
- pdata->enetaddr[0] = mac_hi & 0xFF;
- pdata->enetaddr[1] = (mac_hi & 0xFF00) >> 8;
- pdata->enetaddr[2] = (mac_hi & 0xFF0000) >> 16;
- pdata->enetaddr[3] = (mac_hi & 0xFF000000) >> 24;
- pdata->enetaddr[4] = mac_lo & 0xFF;
- pdata->enetaddr[5] = (mac_lo & 0xFF00) >> 8;
+ ret = ti_cm_get_macid(dev, active_slave, pdata->enetaddr);
+ if (ret < 0) {
+ error("cpsw read efuse mac failed\n");
+ return ret;
+ }
pdata->phy_interface = priv->data.slave_data[active_slave].phy_if;
if (pdata->phy_interface == -1) {
writel(RGMII_MODE_ENABLE, priv->data.gmii_sel);
break;
}
+
return 0;
}
static int bcm54xx_startup(struct phy_device *phydev)
{
+ int ret;
+
/* Read the Status (2x to make sure link is right) */
- genphy_update_link(phydev);
- bcm54xx_parse_status(phydev);
+ ret = genphy_update_link(phydev);
+ if (ret)
+ return ret;
- return 0;
+ return bcm54xx_parse_status(phydev);
}
/* Broadcom BCM5482S */
static int bcm_cygnus_startup(struct phy_device *phydev)
{
+ int ret;
+
/* Read the Status (2x to make sure link is right) */
- genphy_update_link(phydev);
- genphy_parse_link(phydev);
+ ret = genphy_update_link(phydev);
+ if (ret)
+ return ret;
- return 0;
+ return genphy_parse_link(phydev);
}
static int bcm_cygnus_config(struct phy_device *phydev)
*/
static int bcm5482_startup(struct phy_device *phydev)
{
+ int ret;
+
if (bcm5482_is_serdes(phydev)) {
bcm5482_parse_serdes_sr(phydev);
phydev->port = PORT_FIBRE;
- } else {
- /* Wait for auto-negotiation to complete or fail */
- genphy_update_link(phydev);
- /* Parse BCM54xx copper aux status register */
- bcm54xx_parse_status(phydev);
+ return 0;
}
- return 0;
+ /* Wait for auto-negotiation to complete or fail */
+ ret = genphy_update_link(phydev);
+ if (ret)
+ return ret;
+
+ /* Parse BCM54xx copper aux status register */
+ return bcm54xx_parse_status(phydev);
}
static struct phy_driver BCM5461S_driver = {
static int dm9161_startup(struct phy_device *phydev)
{
- genphy_update_link(phydev);
- dm9161_parse_status(phydev);
+ int ret;
- return 0;
+ ret = genphy_update_link(phydev);
+ if (ret)
+ return ret;
+
+ return dm9161_parse_status(phydev);
}
static struct phy_driver DM9161_driver = {
static int et1011c_startup(struct phy_device *phydev)
{
- genphy_update_link(phydev);
- et1011c_parse_status(phydev);
- return 0;
+ int ret;
+
+ ret = genphy_update_link(phydev);
+ if (ret)
+ return ret;
+
+ return et1011c_parse_status(phydev);
}
static struct phy_driver et1011c_driver = {
static int lxt971_startup(struct phy_device *phydev)
{
- genphy_update_link(phydev);
- lxt971_parse_status(phydev);
+ int ret;
- return 0;
+ ret = genphy_update_link(phydev);
+ if (ret)
+ return ret;
+
+ return lxt971_parse_status(phydev);
}
static struct phy_driver LXT971_driver = {
/* Parse the 88E1011's status register for speed and duplex
* information
*/
-static uint m88e1xxx_parse_status(struct phy_device *phydev)
+static int m88e1xxx_parse_status(struct phy_device *phydev)
{
unsigned int speed;
unsigned int mii_reg;
if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
puts(" TIMEOUT !\n");
phydev->link = 0;
- break;
+ return -ETIMEDOUT;
}
if ((i++ % 1000) == 0)
static int m88e1011s_startup(struct phy_device *phydev)
{
- genphy_update_link(phydev);
- m88e1xxx_parse_status(phydev);
+ int ret;
- return 0;
+ ret = genphy_update_link(phydev);
+ if (ret)
+ return ret;
+
+ return m88e1xxx_parse_status(phydev);
}
/* Marvell 88E1111S */
/* Change Page Number */
phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0000);
- genphy_config_aneg(phydev);
-
- phy_reset(phydev);
-
- return 0;
+ return genphy_config_aneg(phydev);
}
static int m88e1118_startup(struct phy_device *phydev)
{
+ int ret;
+
/* Change Page Number */
phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0000);
- genphy_update_link(phydev);
- m88e1xxx_parse_status(phydev);
+ ret = genphy_update_link(phydev);
+ if (ret)
+ return ret;
- return 0;
+ return m88e1xxx_parse_status(phydev);
}
/* Marvell 88E1121R */
static int m88e1145_startup(struct phy_device *phydev)
{
- genphy_update_link(phydev);
+ int ret;
+
+ ret = genphy_update_link(phydev);
+ if (ret)
+ return ret;
+
phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_LED_CONTROL,
MIIM_88E1145_PHY_LED_DIRECT);
- m88e1xxx_parse_status(phydev);
-
- return 0;
+ return m88e1xxx_parse_status(phydev);
}
/* Marvell 88E1149S */
static int ksz90xx_startup(struct phy_device *phydev)
{
unsigned phy_ctl;
- genphy_update_link(phydev);
+ int ret;
+
+ ret = genphy_update_link(phydev);
+ if (ret)
+ return ret;
+
phy_ctl = phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ90xx_PHY_CTL);
if (phy_ctl & MIIM_KSZ90xx_PHYCTL_DUPLEX)
/*
+ * (C) Copyright 2015
+ * Elecsys Corporation <www.elecsyscorp.com>
+ * Kevin Smith <kevin.smith@elecsyscorp.com>
+ *
+ * Original driver:
* (C) Copyright 2009
* Marvell Semiconductor <www.marvell.com>
* Prafulla Wadaskar <prafulla@marvell.com>
* SPDX-License-Identifier: GPL-2.0+
*/
+/*
+ * PHY driver for mv88e61xx ethernet switches.
+ *
+ * This driver configures the mv88e61xx for basic use as a PHY. The switch
+ * supports a VLAN configuration that determines how traffic will be routed
+ * between the ports. This driver uses a simple configuration that routes
+ * traffic from each PHY port only to the CPU port, and from the CPU port to
+ * any PHY port.
+ *
+ * The configuration determines which PHY ports to activate using the
+ * CONFIG_MV88E61XX_PHY_PORTS bitmask. Setting bit 0 will activate port 0, bit
+ * 1 activates port 1, etc. Do not set the bit for the port the CPU is
+ * connected to unless it is connected over a PHY interface (not MII).
+ *
+ * This driver was written for and tested on the mv88e6176 with an SGMII
+ * connection. Other configurations should be supported, but some additions or
+ * changes may be required.
+ */
+
#include <common.h>
+
+#include <bitfield.h>
+#include <errno.h>
+#include <malloc.h>
+#include <miiphy.h>
#include <netdev.h>
-#include "mv88e61xx.h"
+
+#define PHY_AUTONEGOTIATE_TIMEOUT 5000
+
+#define PORT_COUNT 7
+#define PORT_MASK ((1 << PORT_COUNT) - 1)
+
+/* Device addresses */
+#define DEVADDR_PHY(p) (p)
+#define DEVADDR_PORT(p) (0x10 + (p))
+#define DEVADDR_SERDES 0x0F
+#define DEVADDR_GLOBAL_1 0x1B
+#define DEVADDR_GLOBAL_2 0x1C
+
+/* SMI indirection registers for multichip addressing mode */
+#define SMI_CMD_REG 0x00
+#define SMI_DATA_REG 0x01
+
+/* Global registers */
+#define GLOBAL1_STATUS 0x00
+#define GLOBAL1_CTRL 0x04
+#define GLOBAL1_MON_CTRL 0x1A
+
+/* Global 2 registers */
+#define GLOBAL2_REG_PHY_CMD 0x18
+#define GLOBAL2_REG_PHY_DATA 0x19
+
+/* Port registers */
+#define PORT_REG_STATUS 0x00
+#define PORT_REG_PHYS_CTRL 0x01
+#define PORT_REG_SWITCH_ID 0x03
+#define PORT_REG_CTRL 0x04
+#define PORT_REG_VLAN_MAP 0x06
+#define PORT_REG_VLAN_ID 0x07
+
+/* Phy registers */
+#define PHY_REG_CTRL1 0x10
+#define PHY_REG_STATUS1 0x11
+#define PHY_REG_PAGE 0x16
+
+/* Serdes registers */
+#define SERDES_REG_CTRL_1 0x10
+
+/* Phy page numbers */
+#define PHY_PAGE_COPPER 0
+#define PHY_PAGE_SERDES 1
+
+/* Register fields */
+#define GLOBAL1_CTRL_SWRESET BIT(15)
+
+#define GLOBAL1_MON_CTRL_CPUDEST_SHIFT 4
+#define GLOBAL1_MON_CTRL_CPUDEST_WIDTH 4
+
+#define PORT_REG_STATUS_LINK BIT(11)
+#define PORT_REG_STATUS_DUPLEX BIT(10)
+
+#define PORT_REG_STATUS_SPEED_SHIFT 8
+#define PORT_REG_STATUS_SPEED_WIDTH 2
+#define PORT_REG_STATUS_SPEED_10 0
+#define PORT_REG_STATUS_SPEED_100 1
+#define PORT_REG_STATUS_SPEED_1000 2
+
+#define PORT_REG_STATUS_CMODE_MASK 0xF
+#define PORT_REG_STATUS_CMODE_100BASE_X 0x8
+#define PORT_REG_STATUS_CMODE_1000BASE_X 0x9
+#define PORT_REG_STATUS_CMODE_SGMII 0xa
+
+#define PORT_REG_PHYS_CTRL_LINK_VALUE BIT(5)
+#define PORT_REG_PHYS_CTRL_LINK_FORCE BIT(4)
+
+#define PORT_REG_CTRL_PSTATE_SHIFT 0
+#define PORT_REG_CTRL_PSTATE_WIDTH 2
+
+#define PORT_REG_VLAN_ID_DEF_VID_SHIFT 0
+#define PORT_REG_VLAN_ID_DEF_VID_WIDTH 12
+
+#define PORT_REG_VLAN_MAP_TABLE_SHIFT 0
+#define PORT_REG_VLAN_MAP_TABLE_WIDTH 11
+
+#define SERDES_REG_CTRL_1_FORCE_LINK BIT(10)
+
+#define PHY_REG_CTRL1_ENERGY_DET_SHIFT 8
+#define PHY_REG_CTRL1_ENERGY_DET_WIDTH 2
+
+/* Field values */
+#define PORT_REG_CTRL_PSTATE_DISABLED 0
+#define PORT_REG_CTRL_PSTATE_FORWARD 3
+
+#define PHY_REG_CTRL1_ENERGY_DET_OFF 0
+#define PHY_REG_CTRL1_ENERGY_DET_SENSE_ONLY 2
+#define PHY_REG_CTRL1_ENERGY_DET_SENSE_XMIT 3
+
+/* PHY Status Register */
+#define PHY_REG_STATUS1_SPEED 0xc000
+#define PHY_REG_STATUS1_GBIT 0x8000
+#define PHY_REG_STATUS1_100 0x4000
+#define PHY_REG_STATUS1_DUPLEX 0x2000
+#define PHY_REG_STATUS1_SPDDONE 0x0800
+#define PHY_REG_STATUS1_LINK 0x0400
+#define PHY_REG_STATUS1_ENERGY 0x0010
/*
- * Uncomment either of the following line for local debug control;
- * otherwise global debug control will apply.
+ * Macros for building commands for indirect addressing modes. These are valid
+ * for both the indirect multichip addressing mode and the PHY indirection
+ * required for the writes to any PHY register.
*/
+#define SMI_BUSY BIT(15)
+#define SMI_CMD_CLAUSE_22 BIT(12)
+#define SMI_CMD_CLAUSE_22_OP_READ (2 << 10)
+#define SMI_CMD_CLAUSE_22_OP_WRITE (1 << 10)
+
+#define SMI_CMD_READ (SMI_BUSY | SMI_CMD_CLAUSE_22 | \
+ SMI_CMD_CLAUSE_22_OP_READ)
+#define SMI_CMD_WRITE (SMI_BUSY | SMI_CMD_CLAUSE_22 | \
+ SMI_CMD_CLAUSE_22_OP_WRITE)
+
+#define SMI_CMD_ADDR_SHIFT 5
+#define SMI_CMD_ADDR_WIDTH 5
+#define SMI_CMD_REG_SHIFT 0
+#define SMI_CMD_REG_WIDTH 5
+
+/* Check for required macros */
+#ifndef CONFIG_MV88E61XX_PHY_PORTS
+#error Define CONFIG_MV88E61XX_PHY_PORTS to indicate which physical ports \
+ to activate
+#endif
+#ifndef CONFIG_MV88E61XX_CPU_PORT
+#error Define CONFIG_MV88E61XX_CPU_PORT to the port the CPU is attached to
+#endif
-/* #undef DEBUG */
-/* #define DEBUG */
+/* ID register values for different switch models */
+#define PORT_SWITCH_ID_6172 0x1720
+#define PORT_SWITCH_ID_6176 0x1760
+#define PORT_SWITCH_ID_6240 0x2400
+#define PORT_SWITCH_ID_6352 0x3520
-#ifdef CONFIG_MV88E61XX_MULTICHIP_ADRMODE
-/* Chip Address mode
- * The Switch support two modes of operation
- * 1. single chip mode and
- * 2. Multi-chip mode
- * Refer section 9.2 &9.3 in chip datasheet-02 for more details
- *
- * By default single chip mode is configured
- * multichip mode operation can be configured in board header
- */
-static int mv88e61xx_busychk_multic(char *name, u32 devaddr)
+struct mv88e61xx_phy_priv {
+ struct mii_dev *mdio_bus;
+ int smi_addr;
+ int id;
+};
+
+static inline int smi_cmd(int cmd, int addr, int reg)
{
- u16 reg = 0;
- u32 timeout = MV88E61XX_PHY_TIMEOUT;
+ cmd = bitfield_replace(cmd, SMI_CMD_ADDR_SHIFT, SMI_CMD_ADDR_WIDTH,
+ addr);
+ cmd = bitfield_replace(cmd, SMI_CMD_REG_SHIFT, SMI_CMD_REG_WIDTH, reg);
+ return cmd;
+}
- /* Poll till SMIBusy bit is clear */
- do {
- miiphy_read(name, devaddr, 0x0, ®);
- if (timeout-- == 0) {
- printf("SMI busy timeout\n");
- return -1;
- }
- } while (reg & (1 << 15));
- return 0;
+static inline int smi_cmd_read(int addr, int reg)
+{
+ return smi_cmd(SMI_CMD_READ, addr, reg);
}
-static void mv88e61xx_switch_write(char *name, u32 phy_adr,
- u32 reg_ofs, u16 data)
+static inline int smi_cmd_write(int addr, int reg)
{
- u16 mii_dev_addr;
+ return smi_cmd(SMI_CMD_WRITE, addr, reg);
+}
- /* command to read PHY dev address */
- if (miiphy_read(name, 0xEE, 0xEE, &mii_dev_addr)) {
- printf("Error..could not read PHY dev address\n");
- return;
- }
- mv88e61xx_busychk_multic(name, mii_dev_addr);
- /* Write data to Switch indirect data register */
- miiphy_write(name, mii_dev_addr, 0x1, data);
- /* Write command to Switch indirect command register (write) */
- miiphy_write(name, mii_dev_addr, 0x0,
- reg_ofs | (phy_adr << 5) | (1 << 10) | (1 << 12) | (1 <<
- 15));
+__weak int mv88e61xx_hw_reset(struct phy_device *phydev)
+{
+ return 0;
}
-static void mv88e61xx_switch_read(char *name, u32 phy_adr,
- u32 reg_ofs, u16 *data)
+/* Wait for the current SMI indirect command to complete */
+static int mv88e61xx_smi_wait(struct mii_dev *bus, int smi_addr)
{
- u16 mii_dev_addr;
+ int val;
+ u32 timeout = 100;
- /* command to read PHY dev address */
- if (miiphy_read(name, 0xEE, 0xEE, &mii_dev_addr)) {
- printf("Error..could not read PHY dev address\n");
- return;
- }
- mv88e61xx_busychk_multic(name, mii_dev_addr);
- /* Write command to Switch indirect command register (read) */
- miiphy_write(name, mii_dev_addr, 0x0,
- reg_ofs | (phy_adr << 5) | (1 << 11) | (1 << 12) | (1 <<
- 15));
- mv88e61xx_busychk_multic(name, mii_dev_addr);
- /* Read data from Switch indirect data register */
- miiphy_read(name, mii_dev_addr, 0x1, data);
+ do {
+ val = bus->read(bus, smi_addr, MDIO_DEVAD_NONE, SMI_CMD_REG);
+ if (val >= 0 && (val & SMI_BUSY) == 0)
+ return 0;
+
+ mdelay(1);
+ } while (--timeout);
+
+ puts("SMI busy timeout\n");
+ return -ETIMEDOUT;
}
-#endif /* CONFIG_MV88E61XX_MULTICHIP_ADRMODE */
/*
- * Convenience macros for switch device/port reads/writes
- * These macros output valid 'mv88e61xx' U_BOOT_CMDs
+ * The mv88e61xx has three types of addresses: the smi bus address, the device
+ * address, and the register address. The smi bus address distinguishes it on
+ * the smi bus from other PHYs or switches. The device address determines
+ * which on-chip register set you are reading/writing (the various PHYs, their
+ * associated ports, or global configuration registers). The register address
+ * is the offset of the register you are reading/writing.
+ *
+ * When the mv88e61xx is hardware configured to have address zero, it behaves in
+ * single-chip addressing mode, where it responds to all SMI addresses, using
+ * the smi address as its device address. This obviously only works when this
+ * is the only chip on the SMI bus. This allows the driver to access device
+ * registers without using indirection. When the chip is configured to a
+ * non-zero address, it only responds to that SMI address and requires indirect
+ * writes to access the different device addresses.
*/
-
-#ifndef DEBUG
-#define WR_SWITCH_REG wr_switch_reg
-#define RD_SWITCH_REG rd_switch_reg
-#define WR_SWITCH_PORT_REG(n, p, r, d) \
- WR_SWITCH_REG(n, (MV88E61XX_PRT_OFST+p), r, d)
-#define RD_SWITCH_PORT_REG(n, p, r, d) \
- RD_SWITCH_REG(n, (MV88E61XX_PRT_OFST+p), r, d)
-#else
-static void WR_SWITCH_REG(char *name, u32 dev_adr, u32 reg_ofs, u16 data)
+static int mv88e61xx_reg_read(struct phy_device *phydev, int dev, int reg)
{
- printf("mv88e61xx %s dev %02x reg %02x write %04x\n",
- name, dev_adr, reg_ofs, data);
- wr_switch_reg(name, dev_adr, reg_ofs, data);
+ struct mv88e61xx_phy_priv *priv = phydev->priv;
+ struct mii_dev *mdio_bus = priv->mdio_bus;
+ int smi_addr = priv->smi_addr;
+ int res;
+
+ /* In single-chip mode, the device can be addressed directly */
+ if (smi_addr == 0)
+ return mdio_bus->read(mdio_bus, dev, MDIO_DEVAD_NONE, reg);
+
+ /* Wait for the bus to become free */
+ res = mv88e61xx_smi_wait(mdio_bus, smi_addr);
+ if (res < 0)
+ return res;
+
+ /* Issue the read command */
+ res = mdio_bus->write(mdio_bus, smi_addr, MDIO_DEVAD_NONE, SMI_CMD_REG,
+ smi_cmd_read(dev, reg));
+ if (res < 0)
+ return res;
+
+ /* Wait for the read command to complete */
+ res = mv88e61xx_smi_wait(mdio_bus, smi_addr);
+ if (res < 0)
+ return res;
+
+ /* Read the data */
+ res = mdio_bus->read(mdio_bus, smi_addr, MDIO_DEVAD_NONE, SMI_DATA_REG);
+ if (res < 0)
+ return res;
+
+ return bitfield_extract(res, 0, 16);
}
-static void RD_SWITCH_REG(char *name, u32 dev_adr, u32 reg_ofs, u16 *data)
+
+/* See the comment above mv88e61xx_reg_read */
+static int mv88e61xx_reg_write(struct phy_device *phydev, int dev, int reg,
+ u16 val)
{
- rd_switch_reg(name, dev_adr, reg_ofs, data);
- printf("mv88e61xx %s dev %02x reg %02x read %04x\n",
- name, dev_adr, reg_ofs, *data);
+ struct mv88e61xx_phy_priv *priv = phydev->priv;
+ struct mii_dev *mdio_bus = priv->mdio_bus;
+ int smi_addr = priv->smi_addr;
+ int res;
+
+ /* In single-chip mode, the device can be addressed directly */
+ if (smi_addr == 0) {
+ return mdio_bus->write(mdio_bus, dev, MDIO_DEVAD_NONE, reg,
+ val);
+ }
+
+ /* Wait for the bus to become free */
+ res = mv88e61xx_smi_wait(mdio_bus, smi_addr);
+ if (res < 0)
+ return res;
+
+ /* Set the data to write */
+ res = mdio_bus->write(mdio_bus, smi_addr, MDIO_DEVAD_NONE,
+ SMI_DATA_REG, val);
+ if (res < 0)
+ return res;
+
+ /* Issue the write command */
+ res = mdio_bus->write(mdio_bus, smi_addr, MDIO_DEVAD_NONE, SMI_CMD_REG,
+ smi_cmd_write(dev, reg));
+ if (res < 0)
+ return res;
+
+ /* Wait for the write command to complete */
+ res = mv88e61xx_smi_wait(mdio_bus, smi_addr);
+ if (res < 0)
+ return res;
+
+ return 0;
}
-static void WR_SWITCH_PORT_REG(char *name, u32 prt_adr, u32 reg_ofs,
- u16 data)
+
+static int mv88e61xx_phy_wait(struct phy_device *phydev)
{
- printf("mv88e61xx %s port %02x reg %02x write %04x\n",
- name, prt_adr, reg_ofs, data);
- wr_switch_reg(name, (MV88E61XX_PRT_OFST+prt_adr), reg_ofs, data);
+ int val;
+ u32 timeout = 100;
+
+ do {
+ val = mv88e61xx_reg_read(phydev, DEVADDR_GLOBAL_2,
+ GLOBAL2_REG_PHY_CMD);
+ if (val >= 0 && (val & SMI_BUSY) == 0)
+ return 0;
+
+ mdelay(1);
+ } while (--timeout);
+
+ return -ETIMEDOUT;
}
-static void RD_SWITCH_PORT_REG(char *name, u32 prt_adr, u32 reg_ofs,
- u16 *data)
+
+static int mv88e61xx_phy_read_indirect(struct mii_dev *smi_wrapper, int dev,
+ int devad, int reg)
{
- rd_switch_reg(name, (MV88E61XX_PRT_OFST+prt_adr), reg_ofs, data);
- printf("mv88e61xx %s port %02x reg %02x read %04x\n",
- name, prt_adr, reg_ofs, *data);
+ struct phy_device *phydev;
+ int res;
+
+ phydev = (struct phy_device *)smi_wrapper->priv;
+
+ /* Issue command to read */
+ res = mv88e61xx_reg_write(phydev, DEVADDR_GLOBAL_2,
+ GLOBAL2_REG_PHY_CMD,
+ smi_cmd_read(dev, reg));
+
+ /* Wait for data to be read */
+ res = mv88e61xx_phy_wait(phydev);
+ if (res < 0)
+ return res;
+
+ /* Read retrieved data */
+ return mv88e61xx_reg_read(phydev, DEVADDR_GLOBAL_2,
+ GLOBAL2_REG_PHY_DATA);
}
-#endif
-/*
- * Local functions to read/write registers on the switch PHYs.
- * NOTE! This goes through switch, not direct miiphy, writes and reads!
- */
+static int mv88e61xx_phy_write_indirect(struct mii_dev *smi_wrapper, int dev,
+ int devad, int reg, u16 data)
+{
+ struct phy_device *phydev;
+ int res;
+
+ phydev = (struct phy_device *)smi_wrapper->priv;
+
+ /* Set the data to write */
+ res = mv88e61xx_reg_write(phydev, DEVADDR_GLOBAL_2,
+ GLOBAL2_REG_PHY_DATA, data);
+ if (res < 0)
+ return res;
+ /* Issue the write command */
+ res = mv88e61xx_reg_write(phydev, DEVADDR_GLOBAL_2,
+ GLOBAL2_REG_PHY_CMD,
+ smi_cmd_write(dev, reg));
+ if (res < 0)
+ return res;
+
+ /* Wait for command to complete */
+ return mv88e61xx_phy_wait(phydev);
+}
-/*
- * Make sure SMIBusy bit cleared before another
- * SMI operation can take place
- */
-static int mv88e61xx_busychk(char *name)
+/* Wrapper function to make calls to phy_read_indirect simpler */
+static int mv88e61xx_phy_read(struct phy_device *phydev, int phy, int reg)
{
- u16 reg = 0;
- u32 timeout = MV88E61XX_PHY_TIMEOUT;
- do {
- rd_switch_reg(name, MV88E61XX_GLB2REG_DEVADR,
- MV88E61XX_PHY_CMD, ®);
- if (timeout-- == 0) {
- printf("SMI busy timeout\n");
- return -1;
- }
- } while (reg & 1 << 15); /* busy mask */
- return 0;
+ return mv88e61xx_phy_read_indirect(phydev->bus, DEVADDR_PHY(phy),
+ MDIO_DEVAD_NONE, reg);
}
-static inline int mv88e61xx_switch_miiphy_write(char *name, u32 phy,
- u32 reg, u16 data)
+/* Wrapper function to make calls to phy_read_indirect simpler */
+static int mv88e61xx_phy_write(struct phy_device *phydev, int phy,
+ int reg, u16 val)
{
- /* write switch data reg then cmd reg then check completion */
- wr_switch_reg(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_DATA,
- data);
- wr_switch_reg(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_CMD,
- (MV88E61XX_PHY_WRITE_CMD | (phy << 5) | reg));
- return mv88e61xx_busychk(name);
+ return mv88e61xx_phy_write_indirect(phydev->bus, DEVADDR_PHY(phy),
+ MDIO_DEVAD_NONE, reg, val);
}
-static inline int mv88e61xx_switch_miiphy_read(char *name, u32 phy,
- u32 reg, u16 *data)
+static int mv88e61xx_port_read(struct phy_device *phydev, u8 port, u8 reg)
{
- /* write switch cmd reg, check for completion */
- wr_switch_reg(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_CMD,
- (MV88E61XX_PHY_READ_CMD | (phy << 5) | reg));
- if (mv88e61xx_busychk(name))
- return -1;
- /* read switch data reg and return success */
- rd_switch_reg(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_DATA, data);
- return 0;
+ return mv88e61xx_reg_read(phydev, DEVADDR_PORT(port), reg);
}
-/*
- * Convenience macros for switch PHY reads/writes
- */
+static int mv88e61xx_port_write(struct phy_device *phydev, u8 port, u8 reg,
+ u16 val)
+{
+ return mv88e61xx_reg_write(phydev, DEVADDR_PORT(port), reg, val);
+}
-#ifndef DEBUG
-#define WR_SWITCH_PHY_REG mv88e61xx_switch_miiphy_write
-#define RD_SWITCH_PHY_REG mv88e61xx_switch_miiphy_read
-#else
-static inline int WR_SWITCH_PHY_REG(char *name, u32 phy_adr,
- u32 reg_ofs, u16 data)
-{
- int r = mv88e61xx_switch_miiphy_write(name, phy_adr, reg_ofs, data);
- if (r)
- printf("** ERROR writing mv88e61xx %s phy %02x reg %02x\n",
- name, phy_adr, reg_ofs);
- else
- printf("mv88e61xx %s phy %02x reg %02x write %04x\n",
- name, phy_adr, reg_ofs, data);
- return r;
+static int mv88e61xx_set_page(struct phy_device *phydev, u8 phy, u8 page)
+{
+ return mv88e61xx_phy_write(phydev, phy, PHY_REG_PAGE, page);
}
-static inline int RD_SWITCH_PHY_REG(char *name, u32 phy_adr,
- u32 reg_ofs, u16 *data)
+
+static int mv88e61xx_get_switch_id(struct phy_device *phydev)
{
- int r = mv88e61xx_switch_miiphy_read(name, phy_adr, reg_ofs, data);
- if (r)
- printf("** ERROR reading mv88e61xx %s phy %02x reg %02x\n",
- name, phy_adr, reg_ofs);
- else
- printf("mv88e61xx %s phy %02x reg %02x read %04x\n",
- name, phy_adr, reg_ofs, *data);
- return r;
+ int res;
+
+ res = mv88e61xx_port_read(phydev, 0, PORT_REG_SWITCH_ID);
+ if (res < 0)
+ return res;
+ return res & 0xfff0;
}
-#endif
-static void mv88e61xx_port_vlan_config(struct mv88e61xx_config *swconfig)
-{
- u32 prt;
- u16 reg;
- char *name = swconfig->name;
- u32 port_mask = swconfig->ports_enabled;
-
- /* apply internal vlan config */
- for (prt = 0; prt < MV88E61XX_MAX_PORTS_NUM; prt++) {
- /* only for enabled ports */
- if ((1 << prt) & port_mask) {
- /* take vlan map from swconfig */
- u8 vlanmap = swconfig->vlancfg[prt];
- /* remove disabled ports from vlan map */
- vlanmap &= swconfig->ports_enabled;
- /* apply vlan map to port */
- RD_SWITCH_PORT_REG(name, prt,
- MV88E61XX_PRT_VMAP_REG, ®);
- reg &= ~((1 << MV88E61XX_MAX_PORTS_NUM) - 1);
- reg |= vlanmap;
- WR_SWITCH_PORT_REG(name, prt,
- MV88E61XX_PRT_VMAP_REG, reg);
- }
+static bool mv88e61xx_6352_family(struct phy_device *phydev)
+{
+ struct mv88e61xx_phy_priv *priv = phydev->priv;
+
+ switch (priv->id) {
+ case PORT_SWITCH_ID_6172:
+ case PORT_SWITCH_ID_6176:
+ case PORT_SWITCH_ID_6240:
+ case PORT_SWITCH_ID_6352:
+ return true;
}
+ return false;
}
-/*
- * Power up the specified port and reset PHY
- */
-static int mv88361xx_powerup(struct mv88e61xx_config *swconfig, u32 phy)
+static int mv88e61xx_get_cmode(struct phy_device *phydev, u8 port)
{
- char *name = swconfig->name;
+ int res;
- /* Write Copper Specific control reg1 (0x10) for-
- * Enable Phy power up
- * Energy Detect on (sense&Xmit NLP Periodically
- * reset other settings default
- */
- if (WR_SWITCH_PHY_REG(name, phy, 0x10, 0x3360))
- return -1;
+ res = mv88e61xx_port_read(phydev, port, PORT_REG_STATUS);
+ if (res < 0)
+ return res;
+ return res & PORT_REG_STATUS_CMODE_MASK;
+}
- /* Write PHY ctrl reg (0x0) to apply
- * Phy reset (set bit 15 low)
- * reset other default values
- */
- if (WR_SWITCH_PHY_REG(name, phy, 0x00, 0x9140))
- return -1;
+static int mv88e61xx_parse_status(struct phy_device *phydev)
+{
+ unsigned int speed;
+ unsigned int mii_reg;
+
+ mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, PHY_REG_STATUS1);
+
+ if ((mii_reg & PHY_REG_STATUS1_LINK) &&
+ !(mii_reg & PHY_REG_STATUS1_SPDDONE)) {
+ int i = 0;
+
+ puts("Waiting for PHY realtime link");
+ while (!(mii_reg & PHY_REG_STATUS1_SPDDONE)) {
+ /* Timeout reached ? */
+ if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
+ puts(" TIMEOUT !\n");
+ phydev->link = 0;
+ break;
+ }
+
+ if ((i++ % 1000) == 0)
+ putc('.');
+ udelay(1000);
+ mii_reg = phy_read(phydev, MDIO_DEVAD_NONE,
+ PHY_REG_STATUS1);
+ }
+ puts(" done\n");
+ udelay(500000); /* another 500 ms (results in faster booting) */
+ } else {
+ if (mii_reg & PHY_REG_STATUS1_LINK)
+ phydev->link = 1;
+ else
+ phydev->link = 0;
+ }
+
+ if (mii_reg & PHY_REG_STATUS1_DUPLEX)
+ phydev->duplex = DUPLEX_FULL;
+ else
+ phydev->duplex = DUPLEX_HALF;
+
+ speed = mii_reg & PHY_REG_STATUS1_SPEED;
+
+ switch (speed) {
+ case PHY_REG_STATUS1_GBIT:
+ phydev->speed = SPEED_1000;
+ break;
+ case PHY_REG_STATUS1_100:
+ phydev->speed = SPEED_100;
+ break;
+ default:
+ phydev->speed = SPEED_10;
+ break;
+ }
return 0;
}
-/*
- * Default Setup for LED[0]_Control (ref: Table 46 Datasheet-3)
- * is set to "On-1000Mb/s Link, Off Else"
- * This function sets it to "On-Link, Blink-Activity, Off-NoLink"
- *
- * This is optional settings may be needed on some boards
- * to setup PHY LEDs default configuration to detect 10/100/1000Mb/s
- * Link status
- */
-static int mv88361xx_led_init(struct mv88e61xx_config *swconfig, u32 phy)
+static int mv88e61xx_switch_reset(struct phy_device *phydev)
{
- char *name = swconfig->name;
+ int time;
+ int val;
+ u8 port;
+
+ /* Disable all ports */
+ for (port = 0; port < PORT_COUNT; port++) {
+ val = mv88e61xx_port_read(phydev, port, PORT_REG_CTRL);
+ if (val < 0)
+ return val;
+ val = bitfield_replace(val, PORT_REG_CTRL_PSTATE_SHIFT,
+ PORT_REG_CTRL_PSTATE_WIDTH,
+ PORT_REG_CTRL_PSTATE_DISABLED);
+ val = mv88e61xx_port_write(phydev, port, PORT_REG_CTRL, val);
+ if (val < 0)
+ return val;
+ }
- if (swconfig->led_init != MV88E61XX_LED_INIT_EN)
- return 0;
+ /* Wait 2 ms for queues to drain */
+ udelay(2000);
+
+ /* Reset switch */
+ val = mv88e61xx_reg_read(phydev, DEVADDR_GLOBAL_1, GLOBAL1_CTRL);
+ if (val < 0)
+ return val;
+ val |= GLOBAL1_CTRL_SWRESET;
+ val = mv88e61xx_reg_write(phydev, DEVADDR_GLOBAL_1,
+ GLOBAL1_CTRL, val);
+ if (val < 0)
+ return val;
+
+ /* Wait up to 1 second for switch reset complete */
+ for (time = 1000; time; time--) {
+ val = mv88e61xx_reg_read(phydev, DEVADDR_GLOBAL_1,
+ GLOBAL1_CTRL);
+ if (val >= 0 && ((val & GLOBAL1_CTRL_SWRESET) == 0))
+ break;
+ udelay(1000);
+ }
+ if (!time)
+ return -ETIMEDOUT;
- /* set page address to 3 */
- if (WR_SWITCH_PHY_REG(name, phy, 0x16, 0x0003))
- return -1;
+ return 0;
+}
- /*
- * set LED Func Ctrl reg
- * value 0x0001 = LED[0] On-Link, Blink-Activity, Off-NoLink
- */
- if (WR_SWITCH_PHY_REG(name, phy, 0x10, 0x0001))
- return -1;
+static int mv88e61xx_serdes_init(struct phy_device *phydev)
+{
+ int val;
- /* set page address to 0 */
- if (WR_SWITCH_PHY_REG(name, phy, 0x16, 0x0000))
- return -1;
+ val = mv88e61xx_set_page(phydev, DEVADDR_SERDES, PHY_PAGE_SERDES);
+ if (val < 0)
+ return val;
+
+ /* Power up serdes module */
+ val = mv88e61xx_phy_read(phydev, DEVADDR_SERDES, MII_BMCR);
+ if (val < 0)
+ return val;
+ val &= ~(BMCR_PDOWN);
+ val = mv88e61xx_phy_write(phydev, DEVADDR_SERDES, MII_BMCR, val);
+ if (val < 0)
+ return val;
return 0;
}
-/*
- * Reverse Transmit polarity for Media Dependent Interface
- * Pins (MDIP) bits in Copper Specific Control Register 3
- * (Page 0, Reg 20 for each phy (except cpu port)
- * Reference: Section 1.1 Switch datasheet-3
- *
- * This is optional settings may be needed on some boards
- * for PHY<->magnetics h/w tuning
- */
-static int mv88361xx_reverse_mdipn(struct mv88e61xx_config *swconfig, u32 phy)
+static int mv88e61xx_port_enable(struct phy_device *phydev, u8 port)
{
- char *name = swconfig->name;
+ int val;
+
+ val = mv88e61xx_port_read(phydev, port, PORT_REG_CTRL);
+ if (val < 0)
+ return val;
+ val = bitfield_replace(val, PORT_REG_CTRL_PSTATE_SHIFT,
+ PORT_REG_CTRL_PSTATE_WIDTH,
+ PORT_REG_CTRL_PSTATE_FORWARD);
+ val = mv88e61xx_port_write(phydev, port, PORT_REG_CTRL, val);
+ if (val < 0)
+ return val;
- if (swconfig->mdip != MV88E61XX_MDIP_REVERSE)
- return 0;
+ return 0;
+}
- /*Reverse MDIP/N[3:0] bits */
- if (WR_SWITCH_PHY_REG(name, phy, 0x14, 0x000f))
- return -1;
+static int mv88e61xx_port_set_vlan(struct phy_device *phydev, u8 port,
+ u8 mask)
+{
+ int val;
+
+ /* Set VID to port number plus one */
+ val = mv88e61xx_port_read(phydev, port, PORT_REG_VLAN_ID);
+ if (val < 0)
+ return val;
+ val = bitfield_replace(val, PORT_REG_VLAN_ID_DEF_VID_SHIFT,
+ PORT_REG_VLAN_ID_DEF_VID_WIDTH,
+ port + 1);
+ val = mv88e61xx_port_write(phydev, port, PORT_REG_VLAN_ID, val);
+ if (val < 0)
+ return val;
+
+ /* Set VID mask */
+ val = mv88e61xx_port_read(phydev, port, PORT_REG_VLAN_MAP);
+ if (val < 0)
+ return val;
+ val = bitfield_replace(val, PORT_REG_VLAN_MAP_TABLE_SHIFT,
+ PORT_REG_VLAN_MAP_TABLE_WIDTH,
+ mask);
+ val = mv88e61xx_port_write(phydev, port, PORT_REG_VLAN_MAP, val);
+ if (val < 0)
+ return val;
return 0;
}
-/*
- * Marvell 88E61XX Switch initialization
- */
-int mv88e61xx_switch_initialize(struct mv88e61xx_config *swconfig)
+static int mv88e61xx_read_port_config(struct phy_device *phydev, u8 port)
{
- u32 prt;
- u16 reg;
- char *idstr;
- char *name = swconfig->name;
- int time;
-
- if (miiphy_set_current_dev(name)) {
- printf("%s failed\n", __FUNCTION__);
- return -1;
+ int res;
+ int val;
+ bool forced = false;
+
+ val = mv88e61xx_port_read(phydev, port, PORT_REG_STATUS);
+ if (val < 0)
+ return val;
+ if (!(val & PORT_REG_STATUS_LINK)) {
+ /* Temporarily force link to read port configuration */
+ u32 timeout = 100;
+ forced = true;
+
+ val = mv88e61xx_port_read(phydev, port, PORT_REG_PHYS_CTRL);
+ if (val < 0)
+ return val;
+ val |= (PORT_REG_PHYS_CTRL_LINK_FORCE |
+ PORT_REG_PHYS_CTRL_LINK_VALUE);
+ val = mv88e61xx_port_write(phydev, port, PORT_REG_PHYS_CTRL,
+ val);
+ if (val < 0)
+ return val;
+
+ /* Wait for status register to reflect forced link */
+ do {
+ val = mv88e61xx_port_read(phydev, port,
+ PORT_REG_STATUS);
+ if (val < 0)
+ goto unforce;
+ if (val & PORT_REG_STATUS_LINK)
+ break;
+ } while (--timeout);
+
+ if (timeout == 0) {
+ res = -ETIMEDOUT;
+ goto unforce;
+ }
}
- if (!(swconfig->cpuport & ((1 << 4) | (1 << 5)))) {
- swconfig->cpuport = (1 << 5);
- printf("Invalid cpu port config, using default port5\n");
- }
+ if (val & PORT_REG_STATUS_DUPLEX)
+ phydev->duplex = DUPLEX_FULL;
+ else
+ phydev->duplex = DUPLEX_HALF;
- RD_SWITCH_PORT_REG(name, 0, MII_PHYSID2, ®);
- switch (reg &= 0xfff0) {
- case 0x1610:
- idstr = "88E6161";
- break;
- case 0x1650:
- idstr = "88E6165";
+ val = bitfield_extract(val, PORT_REG_STATUS_SPEED_SHIFT,
+ PORT_REG_STATUS_SPEED_WIDTH);
+ switch (val) {
+ case PORT_REG_STATUS_SPEED_1000:
+ phydev->speed = SPEED_1000;
break;
- case 0x1210:
- idstr = "88E6123";
- /* ports 2,3,4 not available */
- swconfig->ports_enabled &= 0x023;
+ case PORT_REG_STATUS_SPEED_100:
+ phydev->speed = SPEED_100;
break;
default:
- /* Could not detect switch id */
- idstr = "88E61??";
+ phydev->speed = SPEED_10;
break;
}
- /* be sure all ports are disabled */
- for (prt = 0; prt < MV88E61XX_MAX_PORTS_NUM; prt++) {
- RD_SWITCH_PORT_REG(name, prt, MV88E61XX_PRT_CTRL_REG, ®);
- reg &= ~0x3;
- WR_SWITCH_PORT_REG(name, prt, MV88E61XX_PRT_CTRL_REG, reg);
+ res = 0;
+
+unforce:
+ if (forced) {
+ val = mv88e61xx_port_read(phydev, port, PORT_REG_PHYS_CTRL);
+ if (val < 0)
+ return val;
+ val &= ~(PORT_REG_PHYS_CTRL_LINK_FORCE |
+ PORT_REG_PHYS_CTRL_LINK_VALUE);
+ val = mv88e61xx_port_write(phydev, port, PORT_REG_PHYS_CTRL,
+ val);
+ if (val < 0)
+ return val;
}
- /* wait 2 ms for queues to drain */
- udelay(2000);
-
- /* reset switch */
- RD_SWITCH_REG(name, MV88E61XX_GLBREG_DEVADR, MV88E61XX_SGCR, ®);
- reg |= 0x8000;
- WR_SWITCH_REG(name, MV88E61XX_GLBREG_DEVADR, MV88E61XX_SGCR, reg);
+ return res;
+}
- /* wait up to 1 second for switch reset complete */
- for (time = 1000; time; time--) {
- RD_SWITCH_REG(name, MV88E61XX_GLBREG_DEVADR, MV88E61XX_SGSR,
- ®);
- if ((reg & 0xc800) == 0xc800)
- break;
- udelay(1000);
- }
- if (!time)
- return -1;
-
- /* Port based VLANs configuration */
- mv88e61xx_port_vlan_config(swconfig);
-
- if (swconfig->rgmii_delay == MV88E61XX_RGMII_DELAY_EN) {
- /*
- * Enable RGMII delay on Tx and Rx for CPU port
- * Ref: sec 9.5 of chip datasheet-02
- */
- /*Force port link down */
- WR_SWITCH_PORT_REG(name, 5, MV88E61XX_PCS_CTRL_REG, 0x10);
- /* configure port RGMII delay */
- WR_SWITCH_PORT_REG(name, 4,
- MV88E61XX_RGMII_TIMECTRL_REG, 0x81e7);
- RD_SWITCH_PORT_REG(name, 5,
- MV88E61XX_RGMII_TIMECTRL_REG, ®);
- WR_SWITCH_PORT_REG(name, 5,
- MV88E61XX_RGMII_TIMECTRL_REG, reg | 0x18);
- WR_SWITCH_PORT_REG(name, 4,
- MV88E61XX_RGMII_TIMECTRL_REG, 0xc1e7);
- /* Force port to RGMII FDX 1000Base then up */
- WR_SWITCH_PORT_REG(name, 5, MV88E61XX_PCS_CTRL_REG, 0x1e);
- WR_SWITCH_PORT_REG(name, 5, MV88E61XX_PCS_CTRL_REG, 0x3e);
+static int mv88e61xx_set_cpu_port(struct phy_device *phydev)
+{
+ int val;
+
+ /* Set CPUDest */
+ val = mv88e61xx_reg_read(phydev, DEVADDR_GLOBAL_1, GLOBAL1_MON_CTRL);
+ if (val < 0)
+ return val;
+ val = bitfield_replace(val, GLOBAL1_MON_CTRL_CPUDEST_SHIFT,
+ GLOBAL1_MON_CTRL_CPUDEST_WIDTH,
+ CONFIG_MV88E61XX_CPU_PORT);
+ val = mv88e61xx_reg_write(phydev, DEVADDR_GLOBAL_1,
+ GLOBAL1_MON_CTRL, val);
+ if (val < 0)
+ return val;
+
+ /* Allow CPU to route to any port */
+ val = PORT_MASK & ~(1 << CONFIG_MV88E61XX_CPU_PORT);
+ val = mv88e61xx_port_set_vlan(phydev, CONFIG_MV88E61XX_CPU_PORT, val);
+ if (val < 0)
+ return val;
+
+ /* Enable CPU port */
+ val = mv88e61xx_port_enable(phydev, CONFIG_MV88E61XX_CPU_PORT);
+ if (val < 0)
+ return val;
+
+ val = mv88e61xx_read_port_config(phydev, CONFIG_MV88E61XX_CPU_PORT);
+ if (val < 0)
+ return val;
+
+ /* If CPU is connected to serdes, initialize serdes */
+ if (mv88e61xx_6352_family(phydev)) {
+ val = mv88e61xx_get_cmode(phydev, CONFIG_MV88E61XX_CPU_PORT);
+ if (val < 0)
+ return val;
+ if (val == PORT_REG_STATUS_CMODE_100BASE_X ||
+ val == PORT_REG_STATUS_CMODE_1000BASE_X ||
+ val == PORT_REG_STATUS_CMODE_SGMII) {
+ val = mv88e61xx_serdes_init(phydev);
+ if (val < 0)
+ return val;
+ }
}
- for (prt = 0; prt < MV88E61XX_MAX_PORTS_NUM; prt++) {
-
- /* configure port's PHY */
- if (!((1 << prt) & swconfig->cpuport)) {
- /* port 4 has phy 6, not 4 */
- int phy = (prt == 4) ? 6 : prt;
- if (mv88361xx_powerup(swconfig, phy))
- return -1;
- if (mv88361xx_reverse_mdipn(swconfig, phy))
- return -1;
- if (mv88361xx_led_init(swconfig, phy))
- return -1;
- }
+ return 0;
+}
- /* set port VID to port+1 except for cpu port */
- if (!((1 << prt) & swconfig->cpuport)) {
- RD_SWITCH_PORT_REG(name, prt,
- MV88E61XX_PRT_VID_REG, ®);
- WR_SWITCH_PORT_REG(name, prt,
- MV88E61XX_PRT_VID_REG,
- (reg & ~1023) | (prt+1));
- }
+static int mv88e61xx_switch_init(struct phy_device *phydev)
+{
+ static int init;
+ int res;
- /*Program port state */
- RD_SWITCH_PORT_REG(name, prt,
- MV88E61XX_PRT_CTRL_REG, ®);
- WR_SWITCH_PORT_REG(name, prt,
- MV88E61XX_PRT_CTRL_REG,
- reg | (swconfig->portstate & 0x03));
+ if (init)
+ return 0;
- }
+ res = mv88e61xx_switch_reset(phydev);
+ if (res < 0)
+ return res;
+
+ res = mv88e61xx_set_cpu_port(phydev);
+ if (res < 0)
+ return res;
+
+ init = 1;
- printf("%s Initialized on %s\n", idstr, name);
return 0;
}
-#ifdef CONFIG_MV88E61XX_CMD
-static int
-do_switch(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int mv88e61xx_phy_enable(struct phy_device *phydev, u8 phy)
{
- char *name, *endp;
- int write = 0;
- enum { dev, prt, phy } target = dev;
- u32 addrlo, addrhi, addr;
- u32 reglo, reghi, reg;
- u16 data, rdata;
+ int val;
- if (argc < 7)
- return -1;
+ val = mv88e61xx_phy_read(phydev, phy, MII_BMCR);
+ if (val < 0)
+ return val;
+ val &= ~(BMCR_PDOWN);
+ val = mv88e61xx_phy_write(phydev, phy, MII_BMCR, val);
+ if (val < 0)
+ return val;
- name = argv[1];
+ return 0;
+}
- if (strcmp(argv[2], "phy") == 0)
- target = phy;
- else if (strcmp(argv[2], "port") == 0)
- target = prt;
- else if (strcmp(argv[2], "dev") != 0)
- return 1;
+static int mv88e61xx_phy_setup(struct phy_device *phydev, u8 phy)
+{
+ int val;
- addrlo = simple_strtoul(argv[3], &endp, 16);
+ /*
+ * Enable energy-detect sensing on PHY, used to determine when a PHY
+ * port is physically connected
+ */
+ val = mv88e61xx_phy_read(phydev, phy, PHY_REG_CTRL1);
+ if (val < 0)
+ return val;
+ val = bitfield_replace(val, PHY_REG_CTRL1_ENERGY_DET_SHIFT,
+ PHY_REG_CTRL1_ENERGY_DET_WIDTH,
+ PHY_REG_CTRL1_ENERGY_DET_SENSE_XMIT);
+ val = mv88e61xx_phy_write(phydev, phy, PHY_REG_CTRL1, val);
+ if (val < 0)
+ return val;
- if (!*endp) {
- addrhi = addrlo;
- } else {
- while (*endp < '0' || *endp > '9')
- endp++;
- addrhi = simple_strtoul(endp, NULL, 16);
- }
+ return 0;
+}
- reglo = simple_strtoul(argv[5], &endp, 16);
- if (!*endp) {
- reghi = reglo;
- } else {
- while (*endp < '0' || *endp > '9')
- endp++;
- reghi = simple_strtoul(endp, NULL, 16);
+static int mv88e61xx_phy_config_port(struct phy_device *phydev, u8 phy)
+{
+ int val;
+
+ val = mv88e61xx_port_enable(phydev, phy);
+ if (val < 0)
+ return val;
+
+ val = mv88e61xx_port_set_vlan(phydev, phy,
+ 1 << CONFIG_MV88E61XX_CPU_PORT);
+ if (val < 0)
+ return val;
+
+ return 0;
+}
+
+static int mv88e61xx_probe(struct phy_device *phydev)
+{
+ struct mii_dev *smi_wrapper;
+ struct mv88e61xx_phy_priv *priv;
+ int res;
+
+ res = mv88e61xx_hw_reset(phydev);
+ if (res < 0)
+ return res;
+
+ priv = malloc(sizeof(*priv));
+ if (!priv)
+ return -ENOMEM;
+
+ memset(priv, 0, sizeof(*priv));
+
+ /*
+ * This device requires indirect reads/writes to the PHY registers
+ * which the generic PHY code can't handle. Make a wrapper MII device
+ * to handle reads/writes
+ */
+ smi_wrapper = mdio_alloc();
+ if (!smi_wrapper) {
+ free(priv);
+ return -ENOMEM;
}
- if (strcmp(argv[6], "write") == 0)
- write = 1;
- else if (strcmp(argv[6], "read") != 0)
- return 1;
-
- data = simple_strtoul(argv[7], NULL, 16);
-
- for (addr = addrlo; addr <= addrhi; addr++) {
- for (reg = reglo; reg <= reghi; reg++) {
- if (write) {
- if (target == phy)
- mv88e61xx_switch_miiphy_write(
- name, addr, reg, data);
- else if (target == prt)
- wr_switch_reg(name,
- addr+MV88E61XX_PRT_OFST,
- reg, data);
- else
- wr_switch_reg(name, addr, reg, data);
- } else {
- if (target == phy)
- mv88e61xx_switch_miiphy_read(
- name, addr, reg, &rdata);
- else if (target == prt)
- rd_switch_reg(name,
- addr+MV88E61XX_PRT_OFST,
- reg, &rdata);
- else
- rd_switch_reg(name, addr, reg, &rdata);
- printf("%s %s %s %02x %s %02x %s %04x\n",
- argv[0], argv[1], argv[2], addr,
- argv[4], reg, argv[6], rdata);
- if (write && argc == 7 && rdata != data)
- return 1;
+ /*
+ * Store the mdio bus in the private data, as we are going to replace
+ * the bus with the wrapper bus
+ */
+ priv->mdio_bus = phydev->bus;
+
+ /*
+ * Store the smi bus address in private data. This lets us use the
+ * phydev addr field for device address instead, as the genphy code
+ * expects.
+ */
+ priv->smi_addr = phydev->addr;
+
+ /*
+ * Store the phy_device in the wrapper mii device. This lets us get it
+ * back when genphy functions call phy_read/phy_write.
+ */
+ smi_wrapper->priv = phydev;
+ strncpy(smi_wrapper->name, "indirect mii", sizeof(smi_wrapper->name));
+ smi_wrapper->read = mv88e61xx_phy_read_indirect;
+ smi_wrapper->write = mv88e61xx_phy_write_indirect;
+
+ /* Replace the bus with the wrapper device */
+ phydev->bus = smi_wrapper;
+
+ phydev->priv = priv;
+
+ priv->id = mv88e61xx_get_switch_id(phydev);
+
+ return 0;
+}
+
+static int mv88e61xx_phy_config(struct phy_device *phydev)
+{
+ int res;
+ int i;
+ int ret = -1;
+
+ res = mv88e61xx_switch_init(phydev);
+ if (res < 0)
+ return res;
+
+ for (i = 0; i < PORT_COUNT; i++) {
+ if ((1 << i) & CONFIG_MV88E61XX_PHY_PORTS) {
+ phydev->addr = i;
+
+ res = mv88e61xx_phy_enable(phydev, i);
+ if (res < 0) {
+ printf("Error enabling PHY %i\n", i);
+ continue;
+ }
+ res = mv88e61xx_phy_setup(phydev, i);
+ if (res < 0) {
+ printf("Error setting up PHY %i\n", i);
+ continue;
}
+ res = mv88e61xx_phy_config_port(phydev, i);
+ if (res < 0) {
+ printf("Error configuring PHY %i\n", i);
+ continue;
+ }
+
+ res = genphy_config_aneg(phydev);
+ if (res < 0) {
+ printf("Error setting PHY %i autoneg\n", i);
+ continue;
+ }
+ res = phy_reset(phydev);
+ if (res < 0) {
+ printf("Error resetting PHY %i\n", i);
+ continue;
+ }
+
+ /* Return success if any PHY succeeds */
+ ret = 0;
}
}
+
+ return ret;
+}
+
+static int mv88e61xx_phy_is_connected(struct phy_device *phydev)
+{
+ int val;
+
+ val = mv88e61xx_phy_read(phydev, phydev->addr, PHY_REG_STATUS1);
+ if (val < 0)
+ return 0;
+
+ /*
+ * After reset, the energy detect signal remains high for a few seconds
+ * regardless of whether a cable is connected. This function will
+ * return false positives during this time.
+ */
+ return (val & PHY_REG_STATUS1_ENERGY) == 0;
+}
+
+static int mv88e61xx_phy_startup(struct phy_device *phydev)
+{
+ int i;
+ int link = 0;
+ int res;
+ int speed = phydev->speed;
+ int duplex = phydev->duplex;
+
+ for (i = 0; i < PORT_COUNT; i++) {
+ if ((1 << i) & CONFIG_MV88E61XX_PHY_PORTS) {
+ phydev->addr = i;
+ if (!mv88e61xx_phy_is_connected(phydev))
+ continue;
+ res = genphy_update_link(phydev);
+ if (res < 0)
+ continue;
+ res = mv88e61xx_parse_status(phydev);
+ if (res < 0)
+ continue;
+ link = (link || phydev->link);
+ }
+ }
+ phydev->link = link;
+
+ /* Restore CPU interface speed and duplex after it was changed for
+ * other ports */
+ phydev->speed = speed;
+ phydev->duplex = duplex;
+
+ return 0;
+}
+
+static struct phy_driver mv88e61xx_driver = {
+ .name = "Marvell MV88E61xx",
+ .uid = 0x01410eb1,
+ .mask = 0xfffffff0,
+ .features = PHY_GBIT_FEATURES,
+ .probe = mv88e61xx_probe,
+ .config = mv88e61xx_phy_config,
+ .startup = mv88e61xx_phy_startup,
+ .shutdown = &genphy_shutdown,
+};
+
+int phy_mv88e61xx_init(void)
+{
+ phy_register(&mv88e61xx_driver);
+
return 0;
}
-U_BOOT_CMD(mv88e61xx, 8, 0, do_switch,
- "Read or write mv88e61xx switch registers",
- "<ethdevice> dev|port|phy <addr> reg <reg> write <data>\n"
- "<ethdevice> dev|port|phy <addr> reg <reg> read [<data>]\n"
- " - read/write switch device, port or phy at (addr,reg)\n"
- " addr=0..0x1C for dev, 0..5 for port or phy.\n"
- " reg=0..0x1F.\n"
- " data=0..0xFFFF (tested if present against actual read).\n"
- " All numeric parameters are assumed to be hex.\n"
- " <addr> and <<reg> arguments can be ranges (x..y)"
-);
-#endif /* CONFIG_MV88E61XX_CMD */
+/*
+ * Overload weak get_phy_id definition since we need non-standard functions
+ * to read PHY registers
+ */
+int get_phy_id(struct mii_dev *bus, int smi_addr, int devad, u32 *phy_id)
+{
+ struct phy_device temp_phy;
+ struct mv88e61xx_phy_priv temp_priv;
+ struct mii_dev temp_mii;
+ int val;
+
+ /*
+ * Buid temporary data structures that the chip reading code needs to
+ * read the ID
+ */
+ temp_priv.mdio_bus = bus;
+ temp_priv.smi_addr = smi_addr;
+ temp_phy.priv = &temp_priv;
+ temp_mii.priv = &temp_phy;
+
+ val = mv88e61xx_phy_read_indirect(&temp_mii, 0, devad, MII_PHYSID1);
+ if (val < 0)
+ return -EIO;
+
+ *phy_id = val << 16;
+
+ val = mv88e61xx_phy_read_indirect(&temp_mii, 0, devad, MII_PHYSID2);
+ if (val < 0)
+ return -EIO;
+
+ *phy_id |= (val & 0xffff);
+
+ return 0;
+}
+++ /dev/null
-/*
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Prafulla Wadaskar <prafulla@marvell.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _MV88E61XX_H
-#define _MV88E61XX_H
-
-#include <miiphy.h>
-
-#define MV88E61XX_CPU_PORT 0x5
-
-#define MV88E61XX_PHY_TIMEOUT 100000
-
-/* port dev-addr (= port + 0x10) */
-#define MV88E61XX_PRT_OFST 0x10
-/* port registers */
-#define MV88E61XX_PCS_CTRL_REG 0x1
-#define MV88E61XX_PRT_CTRL_REG 0x4
-#define MV88E61XX_PRT_VMAP_REG 0x6
-#define MV88E61XX_PRT_VID_REG 0x7
-#define MV88E61XX_RGMII_TIMECTRL_REG 0x1A
-
-/* global registers dev-addr */
-#define MV88E61XX_GLBREG_DEVADR 0x1B
-/* global registers */
-#define MV88E61XX_SGSR 0x00
-#define MV88E61XX_SGCR 0x04
-
-/* global 2 registers dev-addr */
-#define MV88E61XX_GLB2REG_DEVADR 0x1C
-/* global 2 registers */
-#define MV88E61XX_PHY_CMD 0x18
-#define MV88E61XX_PHY_DATA 0x19
-/* global 2 phy commands */
-#define MV88E61XX_PHY_WRITE_CMD 0x9400
-#define MV88E61XX_PHY_READ_CMD 0x9800
-
-#define MV88E61XX_BUSY_OFST 15
-#define MV88E61XX_MODE_OFST 12
-#define MV88E61XX_OP_OFST 10
-#define MV88E61XX_ADDR_OFST 5
-
-#ifdef CONFIG_MV88E61XX_MULTICHIP_ADRMODE
-static int mv88e61xx_busychk_multic(char *name, u32 devaddr);
-static void mv88e61xx_switch_write(char *name, u32 phy_adr,
- u32 reg_ofs, u16 data);
-static void mv88e61xx_switch_read(char *name, u32 phy_adr,
- u32 reg_ofs, u16 *data);
-#define wr_switch_reg mv88e61xx_switch_write
-#define rd_switch_reg mv88e61xx_switch_read
-#else
-/* switch appears a s simple PHY and can thus use miiphy */
-#define wr_switch_reg miiphy_write
-#define rd_switch_reg miiphy_read
-#endif /* CONFIG_MV88E61XX_MULTICHIP_ADRMODE */
-
-#endif /* _MV88E61XX_H */
static int dp83865_startup(struct phy_device *phydev)
{
- genphy_update_link(phydev);
- dp83865_parse_status(phydev);
+ int ret;
- return 0;
+ ret = genphy_update_link(phydev);
+ if (ret)
+ return ret;
+
+ return dp83865_parse_status(phydev);
}
static int dp83848_startup(struct phy_device *phydev)
{
- genphy_update_link(phydev);
- dp83848_parse_status(phydev);
+ int ret;
- return 0;
+ ret = genphy_update_link(phydev);
+ if (ret)
+ return ret;
+
+ return dp83848_parse_status(phydev);
}
static struct phy_driver DP83848_driver = {
if (i > PHY_ANEG_TIMEOUT) {
printf(" TIMEOUT !\n");
phydev->link = 0;
- return 0;
+ return -ETIMEDOUT;
}
if (ctrlc()) {
int genphy_startup(struct phy_device *phydev)
{
- genphy_update_link(phydev);
- genphy_parse_link(phydev);
+ int ret;
- return 0;
+ ret = genphy_update_link(phydev);
+ if (ret)
+ return ret;
+
+ return genphy_parse_link(phydev);
}
int genphy_shutdown(struct phy_device *phydev)
int phy_init(void)
{
+#ifdef CONFIG_MV88E61XX_SWITCH
+ phy_mv88e61xx_init();
+#endif
#ifdef CONFIG_PHY_AQUANTIA
phy_aquantia_init();
#endif
int phy_config(struct phy_device *phydev)
{
/* Invoke an optional board-specific helper */
- board_phy_config(phydev);
-
- return 0;
+ return board_phy_config(phydev);
}
int phy_shutdown(struct phy_device *phydev)
static int rtl8211x_startup(struct phy_device *phydev)
{
+ int ret;
+
/* Read the Status (2x to make sure link is right) */
- genphy_update_link(phydev);
- rtl8211x_parse_status(phydev);
+ ret = genphy_update_link(phydev);
+ if (ret)
+ return ret;
- return 0;
+ return rtl8211x_parse_status(phydev);
}
static int rtl8211e_startup(struct phy_device *phydev)
{
- genphy_update_link(phydev);
- genphy_parse_link(phydev);
+ int ret;
- return 0;
+ ret = genphy_update_link(phydev);
+ if (ret)
+ return ret;
+
+ return genphy_parse_link(phydev);
}
static int rtl8211f_startup(struct phy_device *phydev)
{
+ int ret;
+
+ /* Read the Status (2x to make sure link is right) */
+ ret = genphy_update_link(phydev);
+ if (ret)
+ return ret;
/* Read the Status (2x to make sure link is right) */
- genphy_update_link(phydev);
- rtl8211f_parse_status(phydev);
- return 0;
+ return rtl8211f_parse_status(phydev);
}
/* Support for RTL8211B PHY */
static int smsc_startup(struct phy_device *phydev)
{
- genphy_update_link(phydev);
- smsc_parse_status(phydev);
- return 0;
+ int ret;
+
+ ret = genphy_update_link(phydev);
+ if (ret)
+ return ret;
+
+ return smsc_parse_status(phydev);
}
static struct phy_driver lan8700_driver = {
*/
#include <common.h>
#include <phy.h>
+#include <linux/compat.h>
+#include <malloc.h>
+
+#include <fdtdec.h>
+#include <dm.h>
+#include <dt-bindings/net/ti-dp83867.h>
+
+DECLARE_GLOBAL_DATA_PTR;
/* TI DP83867 */
#define DP83867_DEVADDR 0x1f
#define MII_MMD_CTRL_INCR_RDWT 0x8000 /* post increment on reads & writes */
#define MII_MMD_CTRL_INCR_ON_WT 0xC000 /* post increment on writes only */
+/* User setting - can be taken from DTS */
+#define DEFAULT_RX_ID_DELAY DP83867_RGMIIDCTL_2_25_NS
+#define DEFAULT_TX_ID_DELAY DP83867_RGMIIDCTL_2_75_NS
+#define DEFAULT_FIFO_DEPTH DP83867_PHYCR_FIFO_DEPTH_4_B_NIB
+
+struct dp83867_private {
+ int rx_id_delay;
+ int tx_id_delay;
+ int fifo_depth;
+};
+
/**
* phy_read_mmd_indirect - reads data from the MMD registers
* @phydev: The PHY device bus
phy_write(phydev, addr, MII_MMD_DATA, data);
}
+#if defined(CONFIG_DM_ETH)
/**
- * phy_interface_is_rgmii - Convenience function for testing if a PHY interface
- * is RGMII (all variants)
+ * dp83867_data_init - Convenience function for setting PHY specific data
+ *
* @phydev: the phy_device struct
*/
-static inline bool phy_interface_is_rgmii(struct phy_device *phydev)
+static int dp83867_of_init(struct phy_device *phydev)
{
- return phydev->interface >= PHY_INTERFACE_MODE_RGMII &&
- phydev->interface <= PHY_INTERFACE_MODE_RGMII_TXID;
+ struct dp83867_private *dp83867 = phydev->priv;
+ struct udevice *dev = phydev->dev;
+
+ dp83867->rx_id_delay = fdtdec_get_uint(gd->fdt_blob, dev->of_offset,
+ "ti,rx-internal-delay", -1);
+
+ dp83867->tx_id_delay = fdtdec_get_uint(gd->fdt_blob, dev->of_offset,
+ "ti,tx-internal-delay", -1);
+
+ dp83867->fifo_depth = fdtdec_get_uint(gd->fdt_blob, dev->of_offset,
+ "ti,fifo-depth", -1);
+
+ return 0;
}
+#else
+static int dp83867_of_init(struct phy_device *phydev)
+{
+ struct dp83867_private *dp83867 = phydev->priv;
-/* User setting - can be taken from DTS */
-#define RX_ID_DELAY 8
-#define TX_ID_DELAY 0xa
-#define FIFO_DEPTH 1
+ dp83867->rx_id_delay = DEFAULT_RX_ID_DELAY;
+ dp83867->tx_id_delay = DEFAULT_TX_ID_DELAY;
+ dp83867->fifo_depth = DEFAULT_FIFO_DEPTH;
+
+ return 0;
+}
+#endif
static int dp83867_config(struct phy_device *phydev)
{
+ struct dp83867_private *dp83867;
unsigned int val, delay, cfg2;
int ret;
+ if (!phydev->priv) {
+ dp83867 = kzalloc(sizeof(*dp83867), GFP_KERNEL);
+ if (!dp83867)
+ return -ENOMEM;
+
+ phydev->priv = dp83867;
+ ret = dp83867_of_init(phydev);
+ if (ret)
+ goto err_out;
+ } else {
+ dp83867 = (struct dp83867_private *)phydev->priv;
+ }
+
/* Restart the PHY. */
val = phy_read(phydev, MDIO_DEVAD_NONE, DP83867_CTRL);
phy_write(phydev, MDIO_DEVAD_NONE, DP83867_CTRL,
if (phy_interface_is_rgmii(phydev)) {
ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL,
(DP83867_MDI_CROSSOVER_AUTO << DP83867_MDI_CROSSOVER) |
- (FIFO_DEPTH << DP83867_PHYCR_FIFO_DEPTH_SHIFT));
+ (dp83867->fifo_depth << DP83867_PHYCR_FIFO_DEPTH_SHIFT));
if (ret)
- return ret;
- } else {
+ goto err_out;
+ } else if (phy_interface_is_sgmii(phydev)) {
phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR,
(BMCR_ANENABLE | BMCR_FULLDPLX | BMCR_SPEED1000));
DP83867_PHYCTRL_SGMIIEN |
(DP83867_MDI_CROSSOVER_MDIX <<
DP83867_MDI_CROSSOVER) |
- (FIFO_DEPTH << DP83867_PHYCTRL_RXFIFO_SHIFT) |
- (FIFO_DEPTH << DP83867_PHYCTRL_TXFIFO_SHIFT));
+ (dp83867->fifo_depth << DP83867_PHYCTRL_RXFIFO_SHIFT) |
+ (dp83867->fifo_depth << DP83867_PHYCTRL_TXFIFO_SHIFT));
phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_BISCR, 0x0);
}
phy_write_mmd_indirect(phydev, DP83867_RGMIICTL,
DP83867_DEVADDR, phydev->addr, val);
- delay = (RX_ID_DELAY |
- (TX_ID_DELAY << DP83867_RGMII_TX_CLK_DELAY_SHIFT));
+ delay = (dp83867->rx_id_delay |
+ (dp83867->tx_id_delay << DP83867_RGMII_TX_CLK_DELAY_SHIFT));
phy_write_mmd_indirect(phydev, DP83867_RGMIIDCTL,
DP83867_DEVADDR, phydev->addr, delay);
genphy_config_aneg(phydev);
return 0;
+
+err_out:
+ kfree(dp83867);
+ return ret;
}
static struct phy_driver DP83867_driver = {
static int vitesse_startup(struct phy_device *phydev)
{
- genphy_update_link(phydev);
- vitesse_parse_status(phydev);
+ int ret;
- return 0;
+ ret = genphy_update_link(phydev);
+ if (ret)
+ return ret;
+ return vitesse_parse_status(phydev);
}
static int cis8204_config(struct phy_device *phydev)
static int setup_phy(struct udevice *dev)
{
- int i;
+ int i, ret;
u16 phyreg;
struct xemaclite *emaclite = dev_get_priv(dev);
struct phy_device *phydev;
phydev->advertising = supported;
emaclite->phydev = phydev;
phy_config(phydev);
- phy_startup(phydev);
+ ret = phy_startup(phydev);
+ if (ret)
+ return ret;
if (!phydev->link) {
printf("%s: No link.\n", phydev->dev->name);
struct zynq_gem_regs *iobase;
phy_interface_t interface;
struct phy_device *phydev;
+ int phy_of_handle;
struct mii_dev *bus;
};
priv->phydev->supported = supported | ADVERTISED_Pause |
ADVERTISED_Asym_Pause;
priv->phydev->advertising = priv->phydev->supported;
- phy_config(priv->phydev);
- return 0;
+ if (priv->phy_of_handle > 0)
+ priv->phydev->dev->of_offset = priv->phy_of_handle;
+
+ return phy_config(priv->phydev);
}
static int zynq_gem_init(struct udevice *dev)
{
u32 i, nwconfig;
+ int ret;
unsigned long clk_rate = 0;
struct zynq_gem_priv *priv = dev_get_priv(dev);
struct zynq_gem_regs *regs = priv->iobase;
priv->init++;
}
- phy_startup(priv->phydev);
+ ret = phy_startup(priv->phydev);
+ if (ret)
+ return ret;
if (!priv->phydev->link) {
printf("%s: No link.\n", priv->phydev->dev->name);
{
struct eth_pdata *pdata = dev_get_platdata(dev);
struct zynq_gem_priv *priv = dev_get_priv(dev);
- int offset = 0;
const char *phy_mode;
pdata->iobase = (phys_addr_t)dev_get_addr(dev);
priv->emio = 0;
priv->phyaddr = -1;
- offset = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset,
- "phy-handle");
- if (offset > 0)
- priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1);
+ priv->phy_of_handle = fdtdec_lookup_phandle(gd->fdt_blob,
+ dev->of_offset, "phy-handle");
+ if (priv->phy_of_handle > 0)
+ priv->phyaddr = fdtdec_get_int(gd->fdt_blob,
+ priv->phy_of_handle, "reg", -1);
phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL);
if (phy_mode)
int bus;
for (hose = pci_get_hose_head(); hose; hose = hose->next) {
-#ifdef CONFIG_SYS_SCSI_SCAN_BUS_REVERSE
- for (bus = hose->last_busno; bus >= hose->first_busno; bus--) {
-#else
for (bus = hose->first_busno; bus <= hose->last_busno; bus++) {
-#endif
bdf = pci_hose_find_devices(hose, bus, ids, &index);
if (bdf != -1)
return bdf;
if PINCTRL || SPL_PINCTRL
+config AR933X_PINCTRL
+ bool "QCA/Athores ar933x pin control driver"
+ depends on DM && SOC_AR933X
+ help
+ Support pin multiplexing control on QCA/Athores ar933x SoCs.
+ The driver is controlled by a device tree node which contains
+ both the GPIO definitions and pin control functions for each
+ available multiplex function.
+
+config QCA953X_PINCTRL
+ bool "QCA/Athores qca953x pin control driver"
+ depends on DM && SOC_QCA953X
+ help
+ Support pin multiplexing control on QCA/Athores qca953x SoCs.
+ The driver is controlled by a device tree node which contains
+ both the GPIO definitions and pin control functions for each
+ available multiplex function.
+
config ROCKCHIP_PINCTRL
bool "Rockchip pin control driver"
depends on DM
obj-$(CONFIG_$(SPL_)PINCTRL_GENERIC) += pinctrl-generic.o
obj-y += nxp/
+obj-$(CONFIG_ARCH_ATH79) += ath79/
obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
obj-$(CONFIG_PINCTRL_SANDBOX) += pinctrl-sandbox.o
--- /dev/null
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-$(CONFIG_AR933X_PINCTRL) += pinctrl_ar933x.o
+obj-$(CONFIG_QCA953x_PINCTRL) += pinctrl_qca953x.o
--- /dev/null
+/*
+ * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <dm/pinctrl.h>
+#include <mach/ar71xx_regs.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+enum periph_id {
+ PERIPH_ID_UART0,
+ PERIPH_ID_SPI0,
+ PERIPH_ID_NONE = -1,
+};
+
+struct ar933x_pinctrl_priv {
+ void __iomem *regs;
+};
+
+static void pinctrl_ar933x_spi_config(struct ar933x_pinctrl_priv *priv, int cs)
+{
+ switch (cs) {
+ case 0:
+ clrsetbits_be32(priv->regs + AR71XX_GPIO_REG_OE,
+ AR933X_GPIO(4), AR933X_GPIO(3) |
+ AR933X_GPIO(5) | AR933X_GPIO(2));
+ setbits_be32(priv->regs + AR71XX_GPIO_REG_FUNC,
+ AR933X_GPIO_FUNC_SPI_EN |
+ AR933X_GPIO_FUNC_RES_TRUE);
+ break;
+ }
+}
+
+static void pinctrl_ar933x_uart_config(struct ar933x_pinctrl_priv *priv, int uart_id)
+{
+ switch (uart_id) {
+ case PERIPH_ID_UART0:
+ clrsetbits_be32(priv->regs + AR71XX_GPIO_REG_OE,
+ AR933X_GPIO(9), AR933X_GPIO(10));
+ setbits_be32(priv->regs + AR71XX_GPIO_REG_FUNC,
+ AR933X_GPIO_FUNC_UART_EN |
+ AR933X_GPIO_FUNC_RES_TRUE);
+ break;
+ }
+}
+
+static int ar933x_pinctrl_request(struct udevice *dev, int func, int flags)
+{
+ struct ar933x_pinctrl_priv *priv = dev_get_priv(dev);
+
+ debug("%s: func=%x, flags=%x\n", __func__, func, flags);
+ switch (func) {
+ case PERIPH_ID_SPI0:
+ pinctrl_ar933x_spi_config(priv, flags);
+ break;
+ case PERIPH_ID_UART0:
+ pinctrl_ar933x_uart_config(priv, func);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int ar933x_pinctrl_get_periph_id(struct udevice *dev,
+ struct udevice *periph)
+{
+ u32 cell[2];
+ int ret;
+
+ ret = fdtdec_get_int_array(gd->fdt_blob, periph->of_offset,
+ "interrupts", cell, ARRAY_SIZE(cell));
+ if (ret < 0)
+ return -EINVAL;
+
+ switch (cell[0]) {
+ case 128:
+ return PERIPH_ID_UART0;
+ case 129:
+ return PERIPH_ID_SPI0;
+ }
+ return -ENOENT;
+}
+
+static int ar933x_pinctrl_set_state_simple(struct udevice *dev,
+ struct udevice *periph)
+{
+ int func;
+
+ func = ar933x_pinctrl_get_periph_id(dev, periph);
+ if (func < 0)
+ return func;
+ return ar933x_pinctrl_request(dev, func, 0);
+}
+
+static struct pinctrl_ops ar933x_pinctrl_ops = {
+ .set_state_simple = ar933x_pinctrl_set_state_simple,
+ .request = ar933x_pinctrl_request,
+ .get_periph_id = ar933x_pinctrl_get_periph_id,
+};
+
+static int ar933x_pinctrl_probe(struct udevice *dev)
+{
+ struct ar933x_pinctrl_priv *priv = dev_get_priv(dev);
+ fdt_addr_t addr;
+
+ addr = dev_get_addr(dev);
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ priv->regs = map_physmem(addr,
+ AR71XX_GPIO_SIZE,
+ MAP_NOCACHE);
+ return 0;
+}
+
+static const struct udevice_id ar933x_pinctrl_ids[] = {
+ { .compatible = "qca,ar933x-pinctrl" },
+ { }
+};
+
+U_BOOT_DRIVER(pinctrl_ar933x) = {
+ .name = "pinctrl_ar933x",
+ .id = UCLASS_PINCTRL,
+ .of_match = ar933x_pinctrl_ids,
+ .priv_auto_alloc_size = sizeof(struct ar933x_pinctrl_priv),
+ .ops = &ar933x_pinctrl_ops,
+ .probe = ar933x_pinctrl_probe,
+};
--- /dev/null
+/*
+ * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <dm/pinctrl.h>
+#include <mach/ar71xx_regs.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+enum periph_id {
+ PERIPH_ID_UART0,
+ PERIPH_ID_SPI0,
+ PERIPH_ID_NONE = -1,
+};
+
+struct qca953x_pinctrl_priv {
+ void __iomem *regs;
+};
+
+static void pinctrl_qca953x_spi_config(struct qca953x_pinctrl_priv *priv, int cs)
+{
+ switch (cs) {
+ case 0:
+ clrsetbits_be32(priv->regs + AR71XX_GPIO_REG_OE,
+ QCA953X_GPIO(5) | QCA953X_GPIO(6) |
+ QCA953X_GPIO(7), QCA953X_GPIO(8));
+
+ clrsetbits_be32(priv->regs + QCA953X_GPIO_REG_OUT_FUNC1,
+ QCA953X_GPIO_MUX_MASK(8) |
+ QCA953X_GPIO_MUX_MASK(16) |
+ QCA953X_GPIO_MUX_MASK(24),
+ (QCA953X_GPIO_OUT_MUX_SPI_CS0 << 8) |
+ (QCA953X_GPIO_OUT_MUX_SPI_CLK << 16) |
+ (QCA953X_GPIO_OUT_MUX_SPI_MOSI << 24));
+
+ clrsetbits_be32(priv->regs + QCA953X_GPIO_REG_IN_ENABLE0,
+ QCA953X_GPIO_MUX_MASK(0),
+ QCA953X_GPIO_IN_MUX_SPI_DATA_IN);
+
+ setbits_be32(priv->regs + AR71XX_GPIO_REG_OUT,
+ QCA953X_GPIO(8));
+ break;
+ }
+}
+
+static void pinctrl_qca953x_uart_config(struct qca953x_pinctrl_priv *priv, int uart_id)
+{
+ switch (uart_id) {
+ case PERIPH_ID_UART0:
+ clrsetbits_be32(priv->regs + AR71XX_GPIO_REG_OE,
+ QCA953X_GPIO(9), QCA953X_GPIO(10));
+
+ clrsetbits_be32(priv->regs + QCA953X_GPIO_REG_OUT_FUNC2,
+ QCA953X_GPIO_MUX_MASK(16),
+ QCA953X_GPIO_OUT_MUX_UART0_SOUT << 16);
+
+ clrsetbits_be32(priv->regs + QCA953X_GPIO_REG_IN_ENABLE0,
+ QCA953X_GPIO_MUX_MASK(8),
+ QCA953X_GPIO_IN_MUX_UART0_SIN << 8);
+
+ setbits_be32(priv->regs + AR71XX_GPIO_REG_OUT,
+ QCA953X_GPIO(10));
+ break;
+ }
+}
+
+static int qca953x_pinctrl_request(struct udevice *dev, int func, int flags)
+{
+ struct qca953x_pinctrl_priv *priv = dev_get_priv(dev);
+
+ debug("%s: func=%x, flags=%x\n", __func__, func, flags);
+ switch (func) {
+ case PERIPH_ID_SPI0:
+ pinctrl_qca953x_spi_config(priv, flags);
+ break;
+ case PERIPH_ID_UART0:
+ pinctrl_qca953x_uart_config(priv, func);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int qca953x_pinctrl_get_periph_id(struct udevice *dev,
+ struct udevice *periph)
+{
+ u32 cell[2];
+ int ret;
+
+ ret = fdtdec_get_int_array(gd->fdt_blob, periph->of_offset,
+ "interrupts", cell, ARRAY_SIZE(cell));
+ if (ret < 0)
+ return -EINVAL;
+
+ switch (cell[0]) {
+ case 128:
+ return PERIPH_ID_UART0;
+ case 129:
+ return PERIPH_ID_SPI0;
+ }
+ return -ENOENT;
+}
+
+static int qca953x_pinctrl_set_state_simple(struct udevice *dev,
+ struct udevice *periph)
+{
+ int func;
+
+ func = qca953x_pinctrl_get_periph_id(dev, periph);
+ if (func < 0)
+ return func;
+ return qca953x_pinctrl_request(dev, func, 0);
+}
+
+static struct pinctrl_ops qca953x_pinctrl_ops = {
+ .set_state_simple = qca953x_pinctrl_set_state_simple,
+ .request = qca953x_pinctrl_request,
+ .get_periph_id = qca953x_pinctrl_get_periph_id,
+};
+
+static int qca953x_pinctrl_probe(struct udevice *dev)
+{
+ struct qca953x_pinctrl_priv *priv = dev_get_priv(dev);
+ fdt_addr_t addr;
+
+ addr = dev_get_addr(dev);
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ priv->regs = map_physmem(addr,
+ AR71XX_GPIO_SIZE,
+ MAP_NOCACHE);
+ return 0;
+}
+
+static const struct udevice_id qca953x_pinctrl_ids[] = {
+ { .compatible = "qca,qca953x-pinctrl" },
+ { }
+};
+
+U_BOOT_DRIVER(pinctrl_qca953x) = {
+ .name = "pinctrl_qca953x",
+ .id = UCLASS_PINCTRL,
+ .of_match = qca953x_pinctrl_ids,
+ .priv_auto_alloc_size = sizeof(struct qca953x_pinctrl_priv),
+ .ops = &qca953x_pinctrl_ops,
+ .probe = qca953x_pinctrl_probe,
+};
You will need to provide parameters to make this work. The driver will
be available until the real driver model serial is running.
+config DEBUG_UART_AR933X
+ bool "QCA/Atheros ar933x"
+ depends on AR933X_UART
+ help
+ Select this to enable a debug UART using the ar933x uart driver.
+ You will need to provide parameters to make this work. The
+ driver will be available until the real driver model serial is
+ running.
+
config DEBUG_UART_NS16550
bool "ns16550"
help
Select this to enable an UART for Altera devices. Please find
details on the "Embedded Peripherals IP User Guide" of Altera.
+config AR933X_UART
+ bool "QCA/Atheros ar933x UART support"
+ depends on DM_SERIAL && SOC_AR933X
+ help
+ Select this to enable UART support for QCA/Atheros ar933x
+ devices. This driver uses driver model and requires a device
+ tree binding to operate, please refer to the document at
+ doc/device-tree-bindings/serial/qca,ar9330-uart.txt.
+
config FSL_LPUART
bool "Freescale LPUART support"
help
obj-$(CONFIG_ALTERA_UART) += altera_uart.o
obj-$(CONFIG_ALTERA_JTAG_UART) += altera_jtag_uart.o
+obj-$(CONFIG_AR933X_UART) += serial_ar933x.o
obj-$(CONFIG_ARM_DCC) += arm_dcc.o
obj-$(CONFIG_ATMEL_USART) += atmel_usart.o
obj-$(CONFIG_EFI_APP) += serial_efi.o
* (C) Copyright 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew, Tsi-Chung.Liew@freescale.com.
*
+ * Modified to add device model (DM) support
+ * (C) Copyright 2015 Angelo Dureghello <angelo@sysam.it>
+ *
* SPDX-License-Identifier: GPL-2.0+
*/
*/
#include <common.h>
+#include <dm.h>
+#include <dm/platform_data/serial_coldfire.h>
#include <serial.h>
#include <linux/compiler.h>
-
#include <asm/immap.h>
#include <asm/uart.h>
extern void uart_port_conf(int port);
-static int mcf_serial_init(void)
+static int mcf_serial_init_common(uart_t *uart, int port_idx, int baudrate)
{
- volatile uart_t *uart;
u32 counter;
- uart = (volatile uart_t *)(CONFIG_SYS_UART_BASE);
-
- uart_port_conf(CONFIG_SYS_UART_PORT);
+ uart_port_conf(port_idx);
/* write to SICR: SIM2 = uart mode,dcd does not affect rx */
- uart->ucr = UART_UCR_RESET_RX;
- uart->ucr = UART_UCR_RESET_TX;
- uart->ucr = UART_UCR_RESET_ERROR;
- uart->ucr = UART_UCR_RESET_MR;
+ writeb(UART_UCR_RESET_RX, &uart->ucr);
+ writeb(UART_UCR_RESET_TX, &uart->ucr);
+ writeb(UART_UCR_RESET_ERROR, &uart->ucr);
+ writeb(UART_UCR_RESET_MR, &uart->ucr);
__asm__("nop");
- uart->uimr = 0;
+ writeb(0, &uart->uimr);
/* write to CSR: RX/TX baud rate from timers */
- uart->ucsr = (UART_UCSR_RCS_SYS_CLK | UART_UCSR_TCS_SYS_CLK);
+ writeb(UART_UCSR_RCS_SYS_CLK | UART_UCSR_TCS_SYS_CLK, &uart->ucsr);
- uart->umr = (UART_UMR_BC_8 | UART_UMR_PM_NONE);
- uart->umr = UART_UMR_SB_STOP_BITS_1;
+ writeb(UART_UMR_BC_8 | UART_UMR_PM_NONE, &uart->umr);
+ writeb(UART_UMR_SB_STOP_BITS_1, &uart->umr);
/* Setting up BaudRate */
- counter = (u32) ((gd->bus_clk / 32) + (gd->baudrate / 2));
- counter = counter / gd->baudrate;
+ counter = (u32) ((gd->bus_clk / 32) + (baudrate / 2));
+ counter = counter / baudrate;
/* write to CTUR: divide counter upper byte */
- uart->ubg1 = (u8) ((counter & 0xff00) >> 8);
+ writeb((u8)((counter & 0xff00) >> 8), &uart->ubg1);
/* write to CTLR: divide counter lower byte */
- uart->ubg2 = (u8) (counter & 0x00ff);
+ writeb((u8)(counter & 0x00ff), &uart->ubg2);
- uart->ucr = (UART_UCR_RX_ENABLED | UART_UCR_TX_ENABLED);
+ writeb(UART_UCR_RX_ENABLED | UART_UCR_TX_ENABLED, &uart->ucr);
return (0);
}
+static void mcf_serial_setbrg_common(uart_t *uart, int baudrate)
+{
+ u32 counter;
+
+ /* Setting up BaudRate */
+ counter = (u32) ((gd->bus_clk / 32) + (baudrate / 2));
+ counter = counter / baudrate;
+
+ /* write to CTUR: divide counter upper byte */
+ writeb(((counter & 0xff00) >> 8), &uart->ubg1);
+ /* write to CTLR: divide counter lower byte */
+ writeb((counter & 0x00ff), &uart->ubg2);
+
+ writeb(UART_UCR_RESET_RX, &uart->ucr);
+ writeb(UART_UCR_RESET_TX, &uart->ucr);
+
+ writeb(UART_UCR_RX_ENABLED | UART_UCR_TX_ENABLED, &uart->ucr);
+}
+
+#ifndef CONFIG_DM_SERIAL
+
+static int mcf_serial_init(void)
+{
+ uart_t *uart_base;
+ int port_idx;
+
+ uart_base = (uart_t *)CONFIG_SYS_UART_BASE;
+ port_idx = CONFIG_SYS_UART_PORT;
+
+ return mcf_serial_init_common(uart_base, port_idx, gd->baudrate);
+}
+
static void mcf_serial_putc(const char c)
{
- volatile uart_t *uart = (volatile uart_t *)(CONFIG_SYS_UART_BASE);
+ uart_t *uart = (uart_t *)CONFIG_SYS_UART_BASE;
if (c == '\n')
serial_putc('\r');
/* Wait for last character to go. */
- while (!(uart->usr & UART_USR_TXRDY)) ;
+ while (!(readb(&uart->usr) & UART_USR_TXRDY))
+ ;
- uart->utb = c;
+ writeb(c, &uart->utb);
}
static int mcf_serial_getc(void)
{
- volatile uart_t *uart = (volatile uart_t *)(CONFIG_SYS_UART_BASE);
+ uart_t *uart = (uart_t *)CONFIG_SYS_UART_BASE;
/* Wait for a character to arrive. */
- while (!(uart->usr & UART_USR_RXRDY)) ;
- return uart->urb;
-}
-
-static int mcf_serial_tstc(void)
-{
- volatile uart_t *uart = (volatile uart_t *)(CONFIG_SYS_UART_BASE);
+ while (!(readb(&uart->usr) & UART_USR_RXRDY))
+ ;
- return (uart->usr & UART_USR_RXRDY);
+ return readb(&uart->urb);
}
static void mcf_serial_setbrg(void)
{
- volatile uart_t *uart = (volatile uart_t *)(CONFIG_SYS_UART_BASE);
- u32 counter;
-
- /* Setting up BaudRate */
- counter = (u32) ((gd->bus_clk / 32) + (gd->baudrate / 2));
- counter = counter / gd->baudrate;
+ uart_t *uart = (uart_t *)CONFIG_SYS_UART_BASE;
- /* write to CTUR: divide counter upper byte */
- uart->ubg1 = ((counter & 0xff00) >> 8);
- /* write to CTLR: divide counter lower byte */
- uart->ubg2 = (counter & 0x00ff);
+ mcf_serial_setbrg_common(uart, gd->baudrate);
+}
- uart->ucr = UART_UCR_RESET_RX;
- uart->ucr = UART_UCR_RESET_TX;
+static int mcf_serial_tstc(void)
+{
+ uart_t *uart = (uart_t *)CONFIG_SYS_UART_BASE;
- uart->ucr = UART_UCR_RX_ENABLED | UART_UCR_TX_ENABLED;
+ return readb(&uart->usr) & UART_USR_RXRDY;
}
static struct serial_device mcf_serial_drv = {
{
return &mcf_serial_drv;
}
+
+#endif
+
+#ifdef CONFIG_DM_SERIAL
+
+static int coldfire_serial_probe(struct udevice *dev)
+{
+ struct coldfire_serial_platdata *plat = dev->platdata;
+
+ return mcf_serial_init_common((uart_t *)plat->base,
+ plat->port, plat->baudrate);
+}
+
+static int coldfire_serial_putc(struct udevice *dev, const char ch)
+{
+ struct coldfire_serial_platdata *plat = dev->platdata;
+ uart_t *uart = (uart_t *)plat->base;
+
+ /* Wait for last character to go. */
+ if (!(readb(&uart->usr) & UART_USR_TXRDY))
+ return -EAGAIN;
+
+ writeb(ch, &uart->utb);
+
+ return 0;
+}
+
+static int coldfire_serial_getc(struct udevice *dev)
+{
+ struct coldfire_serial_platdata *plat = dev->platdata;
+ uart_t *uart = (uart_t *)(plat->base);
+
+ /* Wait for a character to arrive. */
+ if (!(readb(&uart->usr) & UART_USR_RXRDY))
+ return -EAGAIN;
+
+ return readb(&uart->urb);
+}
+
+int coldfire_serial_setbrg(struct udevice *dev, int baudrate)
+{
+ struct coldfire_serial_platdata *plat = dev->platdata;
+ uart_t *uart = (uart_t *)(plat->base);
+
+ mcf_serial_setbrg_common(uart, baudrate);
+
+ return 0;
+}
+
+static int coldfire_serial_pending(struct udevice *dev, bool input)
+{
+ struct coldfire_serial_platdata *plat = dev->platdata;
+ uart_t *uart = (uart_t *)(plat->base);
+
+ if (input)
+ return readb(&uart->usr) & UART_USR_RXRDY ? 1 : 0;
+ else
+ return readb(&uart->usr) & UART_USR_TXRDY ? 0 : 1;
+
+ return 0;
+}
+
+static const struct dm_serial_ops coldfire_serial_ops = {
+ .putc = coldfire_serial_putc,
+ .pending = coldfire_serial_pending,
+ .getc = coldfire_serial_getc,
+ .setbrg = coldfire_serial_setbrg,
+};
+
+U_BOOT_DRIVER(serial_coldfire) = {
+ .name = "serial_coldfire",
+ .id = UCLASS_SERIAL,
+ .probe = coldfire_serial_probe,
+ .ops = &coldfire_serial_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
+#endif
--- /dev/null
+/*
+ * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <div64.h>
+#include <errno.h>
+#include <serial.h>
+#include <asm/io.h>
+#include <asm/addrspace.h>
+#include <asm/types.h>
+#include <dm/pinctrl.h>
+#include <mach/ar71xx_regs.h>
+
+#define AR933X_UART_DATA_REG 0x00
+#define AR933X_UART_CS_REG 0x04
+#define AR933X_UART_CLK_REG 0x08
+
+#define AR933X_UART_DATA_TX_RX_MASK 0xff
+#define AR933X_UART_DATA_RX_CSR BIT(8)
+#define AR933X_UART_DATA_TX_CSR BIT(9)
+#define AR933X_UART_CS_IF_MODE_S 2
+#define AR933X_UART_CS_IF_MODE_M 0x3
+#define AR933X_UART_CS_IF_MODE_DTE 1
+#define AR933X_UART_CS_IF_MODE_DCE 2
+#define AR933X_UART_CS_TX_RDY_ORIDE BIT(7)
+#define AR933X_UART_CS_RX_RDY_ORIDE BIT(8)
+#define AR933X_UART_CLK_STEP_M 0xffff
+#define AR933X_UART_CLK_SCALE_M 0xfff
+#define AR933X_UART_CLK_SCALE_S 16
+#define AR933X_UART_CLK_STEP_S 0
+
+struct ar933x_serial_priv {
+ void __iomem *regs;
+};
+
+/*
+ * Baudrate algorithm come from Linux/drivers/tty/serial/ar933x_uart.c
+ * baudrate = (clk / (scale + 1)) * (step * (1 / 2^17))
+ */
+static u32 ar933x_serial_get_baud(u32 clk, u32 scale, u32 step)
+{
+ u64 t;
+ u32 div;
+
+ div = (2 << 16) * (scale + 1);
+ t = clk;
+ t *= step;
+ t += (div / 2);
+ do_div(t, div);
+
+ return t;
+}
+
+static void ar933x_serial_get_scale_step(u32 clk, u32 baud,
+ u32 *scale, u32 *step)
+{
+ u32 tscale, baudrate;
+ long min_diff;
+
+ *scale = 0;
+ *step = 0;
+
+ min_diff = baud;
+ for (tscale = 0; tscale < AR933X_UART_CLK_SCALE_M; tscale++) {
+ u64 tstep;
+ int diff;
+
+ tstep = baud * (tscale + 1);
+ tstep *= (2 << 16);
+ do_div(tstep, clk);
+
+ if (tstep > AR933X_UART_CLK_STEP_M)
+ break;
+
+ baudrate = ar933x_serial_get_baud(clk, tscale, tstep);
+ diff = abs(baudrate - baud);
+ if (diff < min_diff) {
+ min_diff = diff;
+ *scale = tscale;
+ *step = tstep;
+ }
+ }
+}
+
+static int ar933x_serial_setbrg(struct udevice *dev, int baudrate)
+{
+ struct ar933x_serial_priv *priv = dev_get_priv(dev);
+ u32 val, scale, step;
+
+ val = get_serial_clock();
+ ar933x_serial_get_scale_step(val, baudrate, &scale, &step);
+
+ val = (scale & AR933X_UART_CLK_SCALE_M)
+ << AR933X_UART_CLK_SCALE_S;
+ val |= (step & AR933X_UART_CLK_STEP_M)
+ << AR933X_UART_CLK_STEP_S;
+ writel(val, priv->regs + AR933X_UART_CLK_REG);
+
+ return 0;
+}
+
+static int ar933x_serial_putc(struct udevice *dev, const char c)
+{
+ struct ar933x_serial_priv *priv = dev_get_priv(dev);
+ u32 data;
+
+ data = readl(priv->regs + AR933X_UART_DATA_REG);
+ if (!(data & AR933X_UART_DATA_TX_CSR))
+ return -EAGAIN;
+
+ data = (u32)c | AR933X_UART_DATA_TX_CSR;
+ writel(data, priv->regs + AR933X_UART_DATA_REG);
+
+ return 0;
+}
+
+static int ar933x_serial_getc(struct udevice *dev)
+{
+ struct ar933x_serial_priv *priv = dev_get_priv(dev);
+ u32 data;
+
+ data = readl(priv->regs + AR933X_UART_DATA_REG);
+ if (!(data & AR933X_UART_DATA_RX_CSR))
+ return -EAGAIN;
+
+ writel(AR933X_UART_DATA_RX_CSR, priv->regs + AR933X_UART_DATA_REG);
+ return data & AR933X_UART_DATA_TX_RX_MASK;
+}
+
+static int ar933x_serial_pending(struct udevice *dev, bool input)
+{
+ struct ar933x_serial_priv *priv = dev_get_priv(dev);
+ u32 data;
+
+ data = readl(priv->regs + AR933X_UART_DATA_REG);
+ if (input)
+ return (data & AR933X_UART_DATA_RX_CSR) ? 1 : 0;
+ else
+ return (data & AR933X_UART_DATA_TX_CSR) ? 0 : 1;
+}
+
+static int ar933x_serial_probe(struct udevice *dev)
+{
+ struct ar933x_serial_priv *priv = dev_get_priv(dev);
+ fdt_addr_t addr;
+ u32 val;
+
+ addr = dev_get_addr(dev);
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ priv->regs = map_physmem(addr, AR933X_UART_SIZE,
+ MAP_NOCACHE);
+
+ /*
+ * UART controller configuration:
+ * - no DMA
+ * - no interrupt
+ * - DCE mode
+ * - no flow control
+ * - set RX ready oride
+ * - set TX ready oride
+ */
+ val = (AR933X_UART_CS_IF_MODE_DCE << AR933X_UART_CS_IF_MODE_S) |
+ AR933X_UART_CS_TX_RDY_ORIDE | AR933X_UART_CS_RX_RDY_ORIDE;
+ writel(val, priv->regs + AR933X_UART_CS_REG);
+ return 0;
+}
+
+static const struct dm_serial_ops ar933x_serial_ops = {
+ .putc = ar933x_serial_putc,
+ .pending = ar933x_serial_pending,
+ .getc = ar933x_serial_getc,
+ .setbrg = ar933x_serial_setbrg,
+};
+
+static const struct udevice_id ar933x_serial_ids[] = {
+ { .compatible = "qca,ar9330-uart" },
+ { }
+};
+
+U_BOOT_DRIVER(serial_ar933x) = {
+ .name = "serial_ar933x",
+ .id = UCLASS_SERIAL,
+ .of_match = ar933x_serial_ids,
+ .priv_auto_alloc_size = sizeof(struct ar933x_serial_priv),
+ .probe = ar933x_serial_probe,
+ .ops = &ar933x_serial_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
+
+#ifdef CONFIG_DEBUG_UART_AR933X
+
+#include <debug_uart.h>
+
+static inline void _debug_uart_init(void)
+{
+ void __iomem *regs = (void *)CONFIG_DEBUG_UART_BASE;
+ u32 val, scale, step;
+
+ /*
+ * UART controller configuration:
+ * - no DMA
+ * - no interrupt
+ * - DCE mode
+ * - no flow control
+ * - set RX ready oride
+ * - set TX ready oride
+ */
+ val = (AR933X_UART_CS_IF_MODE_DCE << AR933X_UART_CS_IF_MODE_S) |
+ AR933X_UART_CS_TX_RDY_ORIDE | AR933X_UART_CS_RX_RDY_ORIDE;
+ writel(val, regs + AR933X_UART_CS_REG);
+
+ ar933x_serial_get_scale_step(CONFIG_DEBUG_UART_CLOCK,
+ CONFIG_BAUDRATE, &scale, &step);
+
+ val = (scale & AR933X_UART_CLK_SCALE_M)
+ << AR933X_UART_CLK_SCALE_S;
+ val |= (step & AR933X_UART_CLK_STEP_M)
+ << AR933X_UART_CLK_STEP_S;
+ writel(val, regs + AR933X_UART_CLK_REG);
+}
+
+static inline void _debug_uart_putc(int c)
+{
+ void __iomem *regs = (void *)CONFIG_DEBUG_UART_BASE;
+ u32 data;
+
+ do {
+ data = readl(regs + AR933X_UART_DATA_REG);
+ } while (!(data & AR933X_UART_DATA_TX_CSR));
+
+ data = (u32)c | AR933X_UART_DATA_TX_CSR;
+ writel(data, regs + AR933X_UART_DATA_REG);
+}
+
+DEBUG_UART_FUNCS
+
+#endif
IP core. Please find details on the "Embedded Peripherals IP
User Guide" of Altera.
+config ATH79_SPI
+ bool "Atheros SPI driver"
+ depends on ARCH_ATH79
+ help
+ Enable the Atheros ar7xxx/ar9xxx SoC SPI driver, it was used
+ to access SPI NOR flash and other SPI peripherals. This driver
+ uses driver model and requires a device tree binding to operate.
+ please refer to doc/device-tree-bindings/spi/spi-ath79.txt.
+
config CADENCE_QSPI
bool "Cadence QSPI driver"
help
obj-$(CONFIG_ALTERA_SPI) += altera_spi.o
obj-$(CONFIG_ARMADA100_SPI) += armada100_spi.o
+obj-$(CONFIG_ATH79_SPI) += ath79_spi.o
obj-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o
obj-$(CONFIG_ATMEL_SPI) += atmel_spi.o
obj-$(CONFIG_BFIN_SPI) += bfin_spi.o
--- /dev/null
+/*
+ * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <spi.h>
+#include <dm.h>
+#include <div64.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <asm/addrspace.h>
+#include <asm/types.h>
+#include <dm/pinctrl.h>
+#include <mach/ar71xx_regs.h>
+
+/* CLOCK_DIVIDER = 3 (SPI clock = 200 / 8 ~ 25 MHz) */
+#define ATH79_SPI_CLK_DIV(x) (((x) >> 1) - 1)
+#define ATH79_SPI_RRW_DELAY_FACTOR 12000
+#define ATH79_SPI_MHZ (1000 * 1000)
+
+struct ath79_spi_priv {
+ void __iomem *regs;
+ u32 rrw_delay;
+};
+
+static void spi_cs_activate(struct udevice *dev)
+{
+ struct udevice *bus = dev_get_parent(dev);
+ struct ath79_spi_priv *priv = dev_get_priv(bus);
+
+ writel(AR71XX_SPI_FS_GPIO, priv->regs + AR71XX_SPI_REG_FS);
+ writel(AR71XX_SPI_IOC_CS_ALL, priv->regs + AR71XX_SPI_REG_IOC);
+}
+
+static void spi_cs_deactivate(struct udevice *dev)
+{
+ struct udevice *bus = dev_get_parent(dev);
+ struct ath79_spi_priv *priv = dev_get_priv(bus);
+
+ writel(AR71XX_SPI_IOC_CS_ALL, priv->regs + AR71XX_SPI_REG_IOC);
+ writel(0, priv->regs + AR71XX_SPI_REG_FS);
+}
+
+static int ath79_spi_claim_bus(struct udevice *dev)
+{
+ return 0;
+}
+
+static int ath79_spi_release_bus(struct udevice *dev)
+{
+ return 0;
+}
+
+static int ath79_spi_xfer(struct udevice *dev, unsigned int bitlen,
+ const void *dout, void *din, unsigned long flags)
+{
+ struct udevice *bus = dev_get_parent(dev);
+ struct ath79_spi_priv *priv = dev_get_priv(bus);
+ struct dm_spi_slave_platdata *slave = dev_get_parent_platdata(dev);
+ u8 *rx = din;
+ const u8 *tx = dout;
+ u8 curbyte, curbitlen, restbits;
+ u32 bytes = bitlen / 8;
+ u32 out, in;
+ u64 tick;
+
+ if (flags & SPI_XFER_BEGIN)
+ spi_cs_activate(dev);
+
+ restbits = (bitlen % 8);
+ if (restbits)
+ bytes++;
+
+ out = AR71XX_SPI_IOC_CS_ALL & ~(AR71XX_SPI_IOC_CS(slave->cs));
+ while (bytes > 0) {
+ bytes--;
+ curbyte = 0;
+ if (tx)
+ curbyte = *tx++;
+
+ if (restbits && !bytes) {
+ curbitlen = restbits;
+ curbyte <<= 8 - restbits;
+ } else {
+ curbitlen = 8;
+ }
+
+ for (curbyte <<= (8 - curbitlen); curbitlen; curbitlen--) {
+ if (curbyte & 0x80)
+ out |= AR71XX_SPI_IOC_DO;
+ else
+ out &= ~(AR71XX_SPI_IOC_DO);
+
+ writel(out, priv->regs + AR71XX_SPI_REG_IOC);
+
+ /* delay for low level */
+ if (priv->rrw_delay) {
+ tick = get_ticks() + priv->rrw_delay;
+ while (get_ticks() < tick)
+ /*NOP*/;
+ }
+
+ writel(out | AR71XX_SPI_IOC_CLK,
+ priv->regs + AR71XX_SPI_REG_IOC);
+
+ /* delay for high level */
+ if (priv->rrw_delay) {
+ tick = get_ticks() + priv->rrw_delay;
+ while (get_ticks() < tick)
+ /*NOP*/;
+ }
+
+ curbyte <<= 1;
+ }
+
+ if (!bytes)
+ writel(out, priv->regs + AR71XX_SPI_REG_IOC);
+
+ in = readl(priv->regs + AR71XX_SPI_REG_RDS);
+ if (rx) {
+ if (restbits && !bytes)
+ *rx++ = (in << (8 - restbits));
+ else
+ *rx++ = in;
+ }
+ }
+
+ if (flags & SPI_XFER_END)
+ spi_cs_deactivate(dev);
+
+ return 0;
+}
+
+
+static int ath79_spi_set_speed(struct udevice *bus, uint speed)
+{
+ struct ath79_spi_priv *priv = dev_get_priv(bus);
+ u32 val, div = 0;
+ u64 time;
+
+ if (speed)
+ div = get_bus_freq(0) / speed;
+
+ if (div > 63)
+ div = 63;
+
+ if (div < 5)
+ div = 5;
+
+ /* calculate delay */
+ time = get_tbclk();
+ do_div(time, speed / 2);
+ val = get_bus_freq(0) / ATH79_SPI_MHZ;
+ val = ATH79_SPI_RRW_DELAY_FACTOR / val;
+ if (time > val)
+ priv->rrw_delay = time - val + 1;
+ else
+ priv->rrw_delay = 0;
+
+ writel(AR71XX_SPI_FS_GPIO, priv->regs + AR71XX_SPI_REG_FS);
+ clrsetbits_be32(priv->regs + AR71XX_SPI_REG_CTRL,
+ AR71XX_SPI_CTRL_DIV_MASK,
+ ATH79_SPI_CLK_DIV(div));
+ writel(0, priv->regs + AR71XX_SPI_REG_FS);
+ return 0;
+}
+
+static int ath79_spi_set_mode(struct udevice *bus, uint mode)
+{
+ return 0;
+}
+
+static int ath79_spi_probe(struct udevice *bus)
+{
+ struct ath79_spi_priv *priv = dev_get_priv(bus);
+ fdt_addr_t addr;
+
+ addr = dev_get_addr(bus);
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ priv->regs = map_physmem(addr,
+ AR71XX_SPI_SIZE,
+ MAP_NOCACHE);
+
+ /* Init SPI Hardware, disable remap, set clock */
+ writel(AR71XX_SPI_FS_GPIO, priv->regs + AR71XX_SPI_REG_FS);
+ writel(AR71XX_SPI_CTRL_RD | ATH79_SPI_CLK_DIV(8),
+ priv->regs + AR71XX_SPI_REG_CTRL);
+ writel(0, priv->regs + AR71XX_SPI_REG_FS);
+
+ return 0;
+}
+
+static int ath79_cs_info(struct udevice *bus, uint cs,
+ struct spi_cs_info *info)
+{
+ /* Always allow activity on CS 0/1/2 */
+ if (cs >= 3)
+ return -ENODEV;
+
+ return 0;
+}
+
+static const struct dm_spi_ops ath79_spi_ops = {
+ .claim_bus = ath79_spi_claim_bus,
+ .release_bus = ath79_spi_release_bus,
+ .xfer = ath79_spi_xfer,
+ .set_speed = ath79_spi_set_speed,
+ .set_mode = ath79_spi_set_mode,
+ .cs_info = ath79_cs_info,
+};
+
+static const struct udevice_id ath79_spi_ids[] = {
+ { .compatible = "qca,ar7100-spi" },
+ {}
+};
+
+U_BOOT_DRIVER(ath79_spi) = {
+ .name = "ath79_spi",
+ .id = UCLASS_SPI,
+ .of_match = ath79_spi_ids,
+ .ops = &ath79_spi_ops,
+ .priv_auto_alloc_size = sizeof(struct ath79_spi_priv),
+ .probe = ath79_spi_probe,
+};
#define SEQID_RDEAR 11
#define SEQID_WREAR 12
#endif
+#define SEQID_WRAR 13
+#define SEQID_RDAR 14
/* QSPI CMD */
#define QSPI_CMD_PP 0x02 /* Page program (up to 256 bytes) */
#define QSPI_CMD_BRRD 0x16 /* Bank register read */
#define QSPI_CMD_BRWR 0x17 /* Bank register write */
+/* Used for Spansion S25FS-S family flash only. */
+#define QSPI_CMD_RDAR 0x65 /* Read any device register */
+#define QSPI_CMD_WRAR 0x71 /* Write any device register */
+
/* 4-byte address QSPI CMD - used on Spansion and some Macronix flashes */
#define QSPI_CMD_FAST_READ_4B 0x0c /* Read data bytes (high frequency) */
#define QSPI_CMD_PP_4B 0x12 /* Page program (up to 256 bytes) */
struct fsl_qspi_platdata {
u32 flags;
u32 speed_hz;
- u32 reg_base;
- u32 amba_base;
- u32 amba_total_size;
+ fdt_addr_t reg_base;
+ fdt_addr_t amba_base;
+ fdt_size_t amba_total_size;
u32 flash_num;
u32 num_chipselect;
};
PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
PAD1(LUT_PAD1) | INSTR1(LUT_WRITE));
#endif
+
+ /*
+ * Read any device register.
+ * Used for Spansion S25FS-S family flash only.
+ */
+ lut_base = SEQID_RDAR * 4;
+ qspi_write32(priv->flags, ®s->lut[lut_base],
+ OPRND0(QSPI_CMD_RDAR) | PAD0(LUT_PAD1) |
+ INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
+ PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
+ qspi_write32(priv->flags, ®s->lut[lut_base + 1],
+ OPRND0(8) | PAD0(LUT_PAD1) | INSTR0(LUT_DUMMY) |
+ OPRND1(1) | PAD1(LUT_PAD1) |
+ INSTR1(LUT_READ));
+
+ /*
+ * Write any device register.
+ * Used for Spansion S25FS-S family flash only.
+ */
+ lut_base = SEQID_WRAR * 4;
+ qspi_write32(priv->flags, ®s->lut[lut_base],
+ OPRND0(QSPI_CMD_WRAR) | PAD0(LUT_PAD1) |
+ INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
+ PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
+ qspi_write32(priv->flags, ®s->lut[lut_base + 1],
+ OPRND0(1) | PAD0(LUT_PAD1) | INSTR0(LUT_WRITE));
+
/* Lock the LUT */
qspi_write32(priv->flags, ®s->lutkey, LUT_KEY_VALUE);
qspi_write32(priv->flags, ®s->lckcr, QSPI_LCKCR_LOCK);
qspi_write32(priv->flags, ®s->mcr, mcr_reg);
}
-#ifndef CONFIG_SYS_FSL_QSPI_AHB
/* If not use AHB read, read data from ip interface */
static void qspi_op_read(struct fsl_qspi_priv *priv, u32 *rxbuf, u32 len)
{
u32 mcr_reg, data;
int i, size;
u32 to_or_from;
+ u32 seqid;
+
+ if (priv->cur_seqid == QSPI_CMD_RDAR)
+ seqid = SEQID_RDAR;
+ else
+ seqid = SEQID_FAST_READ;
mcr_reg = qspi_read32(priv->flags, ®s->mcr);
qspi_write32(priv->flags, ®s->mcr,
RX_BUFFER_SIZE : len;
qspi_write32(priv->flags, ®s->ipcr,
- (SEQID_FAST_READ << QSPI_IPCR_SEQID_SHIFT) |
+ (seqid << QSPI_IPCR_SEQID_SHIFT) |
size);
while (qspi_read32(priv->flags, ®s->sr) & QSPI_SR_BUSY_MASK)
;
while ((RX_BUFFER_SIZE >= size) && (size > 0)) {
data = qspi_read32(priv->flags, ®s->rbdr[i]);
data = qspi_endian_xchg(data);
- memcpy(rxbuf, &data, 4);
+ if (size < 4)
+ memcpy(rxbuf, &data, size);
+ else
+ memcpy(rxbuf, &data, 4);
rxbuf++;
size -= 4;
i++;
qspi_write32(priv->flags, ®s->mcr, mcr_reg);
}
-#endif
static void qspi_op_write(struct fsl_qspi_priv *priv, u8 *txbuf, u32 len)
{
/* Default is page programming */
seqid = SEQID_PP;
+ if (priv->cur_seqid == QSPI_CMD_WRAR)
+ seqid = SEQID_WRAR;
#ifdef CONFIG_SPI_FLASH_BAR
if (priv->cur_seqid == QSPI_CMD_BRWR)
seqid = SEQID_BRWR;
return 0;
}
- if (priv->cur_seqid == QSPI_CMD_FAST_READ) {
+ if (priv->cur_seqid == QSPI_CMD_FAST_READ ||
+ priv->cur_seqid == QSPI_CMD_RDAR) {
priv->sf_addr = swab32(txbuf) & OFFSET_BITS_MASK;
} else if ((priv->cur_seqid == QSPI_CMD_SE) ||
(priv->cur_seqid == QSPI_CMD_BE_4K)) {
priv->sf_addr = swab32(txbuf) & OFFSET_BITS_MASK;
qspi_op_erase(priv);
- } else if (priv->cur_seqid == QSPI_CMD_PP) {
+ } else if (priv->cur_seqid == QSPI_CMD_PP ||
+ priv->cur_seqid == QSPI_CMD_WRAR) {
wr_sfaddr = swab32(txbuf) & OFFSET_BITS_MASK;
} else if ((priv->cur_seqid == QSPI_CMD_BRWR) ||
(priv->cur_seqid == QSPI_CMD_WREAR)) {
#else
qspi_op_read(priv, din, bytes);
#endif
+ } else if (priv->cur_seqid == QSPI_CMD_RDAR) {
+ qspi_op_read(priv, din, bytes);
} else if (priv->cur_seqid == QSPI_CMD_RDID)
qspi_op_rdid(priv, din, bytes);
else if (priv->cur_seqid == QSPI_CMD_RDSR)
static int fsl_qspi_probe(struct udevice *bus)
{
- u32 total_size;
+ u32 amba_size_per_chip;
struct fsl_qspi_platdata *plat = dev_get_platdata(bus);
struct fsl_qspi_priv *priv = dev_get_priv(bus);
struct dm_spi_bus *dm_spi_bus;
+ int i;
dm_spi_bus = bus->uclass_priv;
priv->flags = plat->flags;
priv->speed_hz = plat->speed_hz;
- priv->amba_base[0] = plat->amba_base;
- priv->amba_total_size = plat->amba_total_size;
+ /*
+ * QSPI SFADR width is 32bits, the max dest addr is 4GB-1.
+ * AMBA memory zone should be located on the 0~4GB space
+ * even on a 64bits cpu.
+ */
+ priv->amba_base[0] = (u32)plat->amba_base;
+ priv->amba_total_size = (u32)plat->amba_total_size;
priv->flash_num = plat->flash_num;
priv->num_chipselect = plat->num_chipselect;
qspi_cfg_smpr(priv, ~(QSPI_SMPR_FSDLY_MASK | QSPI_SMPR_DDRSMP_MASK |
QSPI_SMPR_FSPHS_MASK | QSPI_SMPR_HSENA_MASK), 0);
- total_size = FSL_QSPI_FLASH_SIZE * FSL_QSPI_FLASH_NUM;
+ /*
+ * Assign AMBA memory zone for every chipselect
+ * QuadSPI has two channels, every channel has two chipselects.
+ * If the property 'num-cs' in dts is 2, the AMBA memory will be divided
+ * into two parts and assign to every channel. This indicate that every
+ * channel only has one valid chipselect.
+ * If the property 'num-cs' in dts is 4, the AMBA memory will be divided
+ * into four parts and assign to every chipselect.
+ * Every channel will has two valid chipselects.
+ */
+ amba_size_per_chip = priv->amba_total_size >>
+ (priv->num_chipselect >> 1);
+ for (i = 1 ; i < priv->num_chipselect ; i++)
+ priv->amba_base[i] =
+ amba_size_per_chip + priv->amba_base[i - 1];
+
/*
* Any read access to non-implemented addresses will provide
* undefined results.
* setting the size of these devices to 0. This would ensure
* that the complete memory map is assigned to only one flash device.
*/
- qspi_write32(priv->flags, &priv->regs->sfa1ad,
- FSL_QSPI_FLASH_SIZE | priv->amba_base[0]);
- qspi_write32(priv->flags, &priv->regs->sfa2ad,
- FSL_QSPI_FLASH_SIZE | priv->amba_base[0]);
- qspi_write32(priv->flags, &priv->regs->sfb1ad,
- total_size | priv->amba_base[0]);
- qspi_write32(priv->flags, &priv->regs->sfb2ad,
- total_size | priv->amba_base[0]);
+ qspi_write32(priv->flags, &priv->regs->sfa1ad, priv->amba_base[1]);
+ switch (priv->num_chipselect) {
+ case 2:
+ qspi_write32(priv->flags, &priv->regs->sfa2ad,
+ priv->amba_base[1]);
+ qspi_write32(priv->flags, &priv->regs->sfb1ad,
+ priv->amba_base[1] + amba_size_per_chip);
+ qspi_write32(priv->flags, &priv->regs->sfb2ad,
+ priv->amba_base[1] + amba_size_per_chip);
+ break;
+ case 4:
+ qspi_write32(priv->flags, &priv->regs->sfa2ad,
+ priv->amba_base[2]);
+ qspi_write32(priv->flags, &priv->regs->sfb1ad,
+ priv->amba_base[3]);
+ qspi_write32(priv->flags, &priv->regs->sfb2ad,
+ priv->amba_base[3] + amba_size_per_chip);
+ break;
+ default:
+ debug("Error: Unsupported chipselect number %u!\n",
+ priv->num_chipselect);
+ qspi_module_disable(priv, 1);
+ return -EINVAL;
+ }
qspi_set_lut(priv);
static int fsl_qspi_ofdata_to_platdata(struct udevice *bus)
{
- struct reg_data {
- u32 addr;
- u32 size;
- } regs_data[2];
+ struct fdt_resource res_regs, res_mem;
struct fsl_qspi_platdata *plat = bus->platdata;
const void *blob = gd->fdt_blob;
int node = bus->of_offset;
if (fdtdec_get_bool(blob, node, "big-endian"))
plat->flags |= QSPI_FLAG_REGMAP_ENDIAN_BIG;
- ret = fdtdec_get_int_array(blob, node, "reg", (u32 *)regs_data,
- sizeof(regs_data)/sizeof(u32));
+ ret = fdt_get_named_resource(blob, node, "reg", "reg-names",
+ "QuadSPI", &res_regs);
+ if (ret) {
+ debug("Error: can't get regs base addresses(ret = %d)!\n", ret);
+ return -ENOMEM;
+ }
+ ret = fdt_get_named_resource(blob, node, "reg", "reg-names",
+ "QuadSPI-memory", &res_mem);
if (ret) {
- debug("Error: can't get base addresses (ret = %d)!\n", ret);
+ debug("Error: can't get AMBA base addresses(ret = %d)!\n", ret);
return -ENOMEM;
}
plat->num_chipselect = fdtdec_get_int(blob, node, "num-cs",
FSL_QSPI_MAX_CHIPSELECT_NUM);
- plat->reg_base = regs_data[0].addr;
- plat->amba_base = regs_data[1].addr;
- plat->amba_total_size = regs_data[1].size;
+ plat->reg_base = res_regs.start;
+ plat->amba_base = res_mem.start;
+ plat->amba_total_size = res_mem.end - res_mem.start + 1;
plat->flash_num = flash_num;
- debug("%s: regs=<0x%x> <0x%x, 0x%x>, max-frequency=%d, endianess=%s\n",
+ debug("%s: regs=<0x%llx> <0x%llx, 0x%llx>, max-frequency=%d, endianess=%s\n",
__func__,
- plat->reg_base,
- plat->amba_base,
- plat->amba_total_size,
+ (u64)plat->reg_base,
+ (u64)plat->amba_base,
+ (u64)plat->amba_total_size,
plat->speed_hz,
plat->flags & QSPI_FLAG_REGMAP_ENDIAN_BIG ? "be" : "le"
);
bus = dev->parent;
priv = dev_get_priv(bus);
- priv->cur_amba_base =
- priv->amba_base[0] + FSL_QSPI_FLASH_SIZE * slave_plat->cs;
+ priv->cur_amba_base = priv->amba_base[slave_plat->cs];
qspi_module_disable(priv, 0);
#define OMAP3_MCSPI4_BASE 0x480BA000
#endif
+#define OMAP4_MCSPI_REG_OFFSET 0x100
+
+struct omap2_mcspi_platform_config {
+ unsigned int regs_offset;
+};
+
/* per-register bitmasks */
#define OMAP3_MCSPI_SYSCONFIG_SMARTIDLE (2 << 3)
#define OMAP3_MCSPI_SYSCONFIG_ENAWAKEUP BIT(2)
const void *blob = gd->fdt_blob;
int node = dev->of_offset;
- priv->regs = (struct mcspi *)dev_get_addr(dev);
+ struct omap2_mcspi_platform_config* data =
+ (struct omap2_mcspi_platform_config*)dev_get_driver_data(dev);
+
+ priv->regs = (struct mcspi *)(dev_get_addr(dev) + data->regs_offset);
priv->pin_dir = fdtdec_get_uint(blob, node, "ti,pindir-d0-out-d1-in",
MCSPI_PINDIR_D0_IN_D1_OUT);
priv->wordlen = SPI_DEFAULT_WORDLEN;
*/
};
+static struct omap2_mcspi_platform_config omap2_pdata = {
+ .regs_offset = 0,
+};
+
+static struct omap2_mcspi_platform_config omap4_pdata = {
+ .regs_offset = OMAP4_MCSPI_REG_OFFSET,
+};
+
static const struct udevice_id omap3_spi_ids[] = {
- { .compatible = "ti,omap2-mcspi" },
- { .compatible = "ti,omap4-mcspi" },
+ { .compatible = "ti,omap2-mcspi", .data = (ulong)&omap2_pdata },
+ { .compatible = "ti,omap4-mcspi", .data = (ulong)&omap4_pdata },
{ }
};
struct gpio_desc mosi;
struct gpio_desc miso;
int spi_delay_us;
+ int flags;
};
+#define SPI_MASTER_NO_RX BIT(0)
+#define SPI_MASTER_NO_TX BIT(1)
+
struct soft_spi_priv {
unsigned int mode;
};
static int soft_spi_scl(struct udevice *dev, int bit)
{
- struct soft_spi_platdata *plat = dev->platdata;
+ struct udevice *bus = dev_get_parent(dev);
+ struct soft_spi_platdata *plat = dev_get_platdata(bus);
dm_gpio_set_value(&plat->sclk, bit);
static int soft_spi_sda(struct udevice *dev, int bit)
{
- struct soft_spi_platdata *plat = dev->platdata;
+ struct udevice *bus = dev_get_parent(dev);
+ struct soft_spi_platdata *plat = dev_get_platdata(bus);
dm_gpio_set_value(&plat->mosi, bit);
static int soft_spi_cs_activate(struct udevice *dev)
{
- struct soft_spi_platdata *plat = dev->platdata;
+ struct udevice *bus = dev_get_parent(dev);
+ struct soft_spi_platdata *plat = dev_get_platdata(bus);
dm_gpio_set_value(&plat->cs, 0);
dm_gpio_set_value(&plat->sclk, 0);
static int soft_spi_cs_deactivate(struct udevice *dev)
{
- struct soft_spi_platdata *plat = dev->platdata;
+ struct udevice *bus = dev_get_parent(dev);
+ struct soft_spi_platdata *plat = dev_get_platdata(bus);
dm_gpio_set_value(&plat->cs, 0);
static int soft_spi_xfer(struct udevice *dev, unsigned int bitlen,
const void *dout, void *din, unsigned long flags)
{
- struct soft_spi_priv *priv = dev_get_priv(dev);
- struct soft_spi_platdata *plat = dev->platdata;
+ struct udevice *bus = dev_get_parent(dev);
+ struct soft_spi_priv *priv = dev_get_priv(bus);
+ struct soft_spi_platdata *plat = dev_get_platdata(bus);
uchar tmpdin = 0;
uchar tmpdout = 0;
const u8 *txd = dout;
if (!cpha)
soft_spi_scl(dev, 0);
- soft_spi_sda(dev, tmpdout & 0x80);
+ if ((plat->flags & SPI_MASTER_NO_TX) == 0)
+ soft_spi_sda(dev, !!(tmpdout & 0x80));
udelay(plat->spi_delay_us);
if (cpha)
soft_spi_scl(dev, 0);
else
soft_spi_scl(dev, 1);
tmpdin <<= 1;
- tmpdin |= dm_gpio_get_value(&plat->miso);
+ if ((plat->flags & SPI_MASTER_NO_RX) == 0)
+ tmpdin |= dm_gpio_get_value(&plat->miso);
tmpdout <<= 1;
udelay(plat->spi_delay_us);
if (cpha)
struct spi_slave *slave = dev_get_parent_priv(dev);
struct soft_spi_platdata *plat = dev->platdata;
int cs_flags, clk_flags;
+ int ret;
cs_flags = (slave->mode & SPI_CS_HIGH) ? 0 : GPIOD_ACTIVE_LOW;
clk_flags = (slave->mode & SPI_CPOL) ? GPIOD_ACTIVE_LOW : 0;
- if (gpio_request_by_name(dev, "cs-gpio", 0, &plat->cs,
+
+ if (gpio_request_by_name(dev, "cs-gpios", 0, &plat->cs,
GPIOD_IS_OUT | cs_flags) ||
- gpio_request_by_name(dev, "sclk-gpio", 0, &plat->sclk,
- GPIOD_IS_OUT | clk_flags) ||
- gpio_request_by_name(dev, "mosi-gpio", 0, &plat->mosi,
- GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE) ||
- gpio_request_by_name(dev, "miso-gpio", 0, &plat->miso,
- GPIOD_IS_IN))
+ gpio_request_by_name(dev, "gpio-sck", 0, &plat->sclk,
+ GPIOD_IS_OUT | clk_flags))
+ return -EINVAL;
+
+ ret = gpio_request_by_name(dev, "gpio-mosi", 0, &plat->mosi,
+ GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
+ if (ret)
+ plat->flags |= SPI_MASTER_NO_TX;
+
+ ret = gpio_request_by_name(dev, "gpio-miso", 0, &plat->miso,
+ GPIOD_IS_IN);
+ if (ret)
+ plat->flags |= SPI_MASTER_NO_RX;
+
+ if ((plat->flags & (SPI_MASTER_NO_RX | SPI_MASTER_NO_TX)) ==
+ (SPI_MASTER_NO_RX | SPI_MASTER_NO_TX))
return -EINVAL;
return 0;
}
static const struct udevice_id soft_spi_ids[] = {
- { .compatible = "u-boot,soft-spi" },
+ { .compatible = "spi-gpio" },
{ }
};
return 0;
}
-int spi_claim_bus(struct spi_slave *slave)
+int dm_spi_claim_bus(struct udevice *dev)
{
- struct udevice *dev = slave->dev;
struct udevice *bus = dev->parent;
struct dm_spi_ops *ops = spi_get_ops(bus);
struct dm_spi_bus *spi = dev_get_uclass_priv(bus);
+ struct spi_slave *slave = dev_get_parent_priv(dev);
int speed;
int ret;
return ops->claim_bus ? ops->claim_bus(dev) : 0;
}
-void spi_release_bus(struct spi_slave *slave)
+void dm_spi_release_bus(struct udevice *dev)
{
- struct udevice *dev = slave->dev;
struct udevice *bus = dev->parent;
struct dm_spi_ops *ops = spi_get_ops(bus);
ops->release_bus(dev);
}
-int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
- const void *dout, void *din, unsigned long flags)
+int dm_spi_xfer(struct udevice *dev, unsigned int bitlen,
+ const void *dout, void *din, unsigned long flags)
{
- struct udevice *dev = slave->dev;
struct udevice *bus = dev->parent;
if (bus->uclass->uc_drv->id != UCLASS_SPI)
return spi_get_ops(bus)->xfer(dev, bitlen, dout, din, flags);
}
+int spi_claim_bus(struct spi_slave *slave)
+{
+ return dm_spi_claim_bus(slave->dev);
+}
+
+void spi_release_bus(struct spi_slave *slave)
+{
+ dm_spi_release_bus(slave->dev);
+}
+
+int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
+ const void *dout, void *din, unsigned long flags)
+{
+ return dm_spi_xfer(slave->dev, bitlen, dout, din, flags);
+}
+
static int spi_post_bind(struct udevice *dev)
{
/* Scan the bus for devices */
# SPDX-License-Identifier: GPL-2.0+
#
+obj-$(CONFIG_DM_USB) += common.o
obj-$(CONFIG_USB_EHCI_FSL) += fsl-dt-fixup.o
obj-$(CONFIG_USB_XHCI_FSL) += fsl-dt-fixup.o
--- /dev/null
+/*
+ * Provides code common for host and device side USB.
+ *
+ * (C) Copyright 2016
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <libfdt.h>
+#include <linux/usb/otg.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const char *const usb_dr_modes[] = {
+ [USB_DR_MODE_UNKNOWN] = "",
+ [USB_DR_MODE_HOST] = "host",
+ [USB_DR_MODE_PERIPHERAL] = "peripheral",
+ [USB_DR_MODE_OTG] = "otg",
+};
+
+enum usb_dr_mode usb_get_dr_mode(int node)
+{
+ const void *fdt = gd->fdt_blob;
+ const char *dr_mode;
+ int i;
+
+ dr_mode = fdt_getprop(fdt, node, "dr_mode", NULL);
+ if (!dr_mode) {
+ error("usb dr_mode not found\n");
+ return USB_DR_MODE_UNKNOWN;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(usb_dr_modes); i++)
+ if (!strcmp(dr_mode, usb_dr_modes[i]))
+ return i;
+
+ return USB_DR_MODE_UNKNOWN;
+}
*/
__raw_writel((div / 16) << 16, DI_BS_CLKGEN1(clk->id));
- clk->rate = (u64)(clk->parent->rate * 16) / div;
+ do_div(parent_rate, div);
+
+ clk->rate = parent_rate;
return 0;
}
static int tegra_lcd_bind(struct udevice *dev)
{
struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
+ const void *blob = gd->fdt_blob;
+ int node = dev->of_offset;
+ int rgb;
+
+ rgb = fdt_subnode_offset(blob, node, "rgb");
+ if ((rgb < 0) || !fdtdec_get_is_enabled(blob, rgb))
+ return -ENODEV;
plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT *
(1 << LCD_MAX_LOG2_BPP) / 8;
config OF_LIST
string "List of device tree files to include for DT control"
depends on SPL_LOAD_FIT
+ default DEFAULT_DEVICE_TREE
help
This option specifies a list of device tree files to use for DT
control. These will be packaged into a FIT. At run-time, SPL will
LOAD_ADDR = 0x1000000
endif
ifeq ($(ARCH),mips)
+ifdef CONFIG_64BIT
+LOAD_ADDR = 0xffffffff80200000
+else
LOAD_ADDR = 0x80200000
endif
+endif
# Resulting ELF and binary exectuables will be named demo and demo.bin
extra-y = demo
ldr pc, [ip]
#elif defined(CONFIG_MIPS)
+#include <asm/asm.h>
.text
.globl __start
.ent __start
__start:
- sw $sp, search_hint
+ PTR_S $sp, search_hint
b main
.end __start
.globl syscall
.ent syscall
syscall:
- sw $ra, return_addr
- lw $t9, syscall_ptr
+ PTR_S $ra, return_addr
+ PTR_L $t9, syscall_ptr
jalr $t9
nop
- lw $ra, return_addr
+ PTR_L $ra, return_addr
jr $ra
nop
.end syscall
return_addr:
- .align 4
+ .align 8
.long 0
#else
#error No support for this arch!
.globl syscall_ptr
syscall_ptr:
- .align 4
+ .align 8
.long 0
.globl search_hint
{
int c;
- if (!syscall(API_GETC, NULL, (uint32_t)&c))
+ if (!syscall(API_GETC, NULL, &c))
return -1;
return c;
{
int t;
- if (!syscall(API_TSTC, NULL, (uint32_t)&t))
+ if (!syscall(API_TSTC, NULL, &t))
return -1;
return t;
void ub_putc(char c)
{
- syscall(API_PUTC, NULL, (uint32_t)&c);
+ syscall(API_PUTC, NULL, &c);
}
void ub_puts(const char *s)
{
- syscall(API_PUTS, NULL, (uint32_t)s);
+ syscall(API_PUTS, NULL, s);
}
/****************************************
si.mr_no = UB_MAX_MR;
memset(&mr, 0, sizeof(mr));
- if (!syscall(API_GET_SYS_INFO, &err, (u_int32_t)&si))
+ if (!syscall(API_GET_SYS_INFO, &err, &si))
return NULL;
return ((err) ? NULL : &si);
{
char *value;
- if (!syscall(API_ENV_GET, NULL, (uint32_t)name, (uint32_t)&value))
+ if (!syscall(API_ENV_GET, NULL, name, &value))
return NULL;
return value;
void ub_env_set(const char *name, char *value)
{
- syscall(API_ENV_SET, NULL, (uint32_t)name, (uint32_t)value);
+ syscall(API_ENV_SET, NULL, name, value);
}
static char env_name[256];
* 'name=val' string), since the API_ENUM_ENV call uses envmatch()
* internally, which handles such case
*/
- if (!syscall(API_ENV_ENUM, NULL, (uint32_t)last, (uint32_t)&env))
+ if (!syscall(API_ENV_ENUM, NULL, last, &env))
return NULL;
if (!env)
{
int err = 0;
- if (!syscall(API_DISPLAY_GET_INFO, &err, (uint32_t)type, (uint32_t)di))
+ if (!syscall(API_DISPLAY_GET_INFO, &err, type, di))
return API_ESYSC;
return err;
: : "i"(offsetof(gd_t, jt)), "i"(FO(x)) : "ip");
#endif
#elif defined(CONFIG_MIPS)
+#ifdef CONFIG_CPU_MIPS64
+/*
+ * k0 ($26) holds the pointer to the global_data; t9 ($25) is a call-
+ * clobbered register that is also used to set gp ($26). Note that the
+ * jr instruction also executes the instruction immediately following
+ * it; however, GCC/mips generates an additional `nop' after each asm
+ * statement
+ */
+#define EXPORT_FUNC(f, a, x, ...) \
+ asm volatile ( \
+" .globl " #x "\n" \
+#x ":\n" \
+" ld $25, %0($26)\n" \
+" ld $25, %1($25)\n" \
+" jr $25\n" \
+ : : "i"(offsetof(gd_t, jt)), "i"(FO(x)) : "t9");
+#else
/*
* k0 ($26) holds the pointer to the global_data; t9 ($25) is a call-
* clobbered register that is also used to set gp ($26). Note that the
" lw $25, %1($25)\n" \
" jr $25\n" \
: : "i"(offsetof(gd_t, jt)), "i"(FO(x)) : "t9");
+#endif
#elif defined(CONFIG_NIOS2)
/*
* gp holds the pointer to the global_data, r8 is call-clobbered
#if defined(CONFIG_CMD_IDE) || \
defined(CONFIG_CMD_SATA) || \
- defined(CONFIG_CMD_SCSI) || \
+ defined(CONFIG_SCSI) || \
defined(CONFIG_CMD_USB) || \
defined(CONFIG_MMC)
printf("Interface: ");
struct fdtdec_phandle_args;
+/**
+ * gpio_xlate_offs_flags() - implementation for common use of dm_gpio_ops.xlate
+ *
+ * This routine sets the offset field to args[0] and the flags field to
+ * GPIOD_ACTIVE_LOW if the GPIO_ACTIVE_LOW flag is present in args[1].
+ *
+ */
+int gpio_xlate_offs_flags(struct udevice *dev, struct gpio_desc *desc,
+ struct fdtdec_phandle_args *args);
+
/**
* struct struct dm_gpio_ops - Driver model GPIO operations
*
*
* @desc->dev to @dev
* @desc->flags to 0
- * @desc->offset to the value of the first argument in args, if any,
- * otherwise -1 (which is invalid)
+ * @desc->offset to 0
*
- * This method is optional so if the above defaults suit it can be
- * omitted. Typical behaviour is to set up the GPIOD_ACTIVE_LOW flag
- * in desc->flags.
+ * This method is optional and defaults to gpio_xlate_offs_flags,
+ * which will parse offset and the GPIO_ACTIVE_LOW flag in the first
+ * two arguments.
*
* Note that @dev is passed in as a parameter to follow driver model
* uclass conventions, even though it is already available as
#define ATA_BLOCKSIZE 512 /* bytes */
#define ATA_BLOCKSHIFT 9 /* 2 ^ ATA_BLOCKSIZESHIFT = 512 */
-#define ATA_SECTORWORDS (512 / sizeof(unsigned long))
+#define ATA_SECTORWORDS (512 / sizeof(uint32_t))
#ifndef ATA_RESET_TIME
#define ATA_RESET_TIME 60 /* spec allows up to 31 seconds */
IF_TYPE_SD,
IF_TYPE_SATA,
IF_TYPE_HOST,
+ IF_TYPE_SYSTEMACE,
IF_TYPE_COUNT, /* Number of interface types */
};
char product[20+1]; /* IDE Serial no, SCSI product */
char revision[8+1]; /* firmware revision */
#ifdef CONFIG_BLK
+ /*
+ * For now we have a few functions which take struct blk_desc as a
+ * parameter. This field allows them to look up the associated
+ * device. Once these functions are removed we can drop this field.
+ */
struct udevice *bdev;
#else
unsigned long (*block_read)(struct blk_desc *block_dev,
*/
unsigned long (*erase)(struct udevice *dev, lbaint_t start,
lbaint_t blkcnt);
+
+ /**
+ * select_hwpart() - select a particular hardware partition
+ *
+ * Some devices (e.g. MMC) can support partitioning at the hardware
+ * level. This is quite separate from the normal idea of
+ * software-based partitions. MMC hardware partitions must be
+ * explicitly selected. Once selected only the region of the device
+ * covered by that partition is accessible.
+ *
+ * The MMC standard provides for two boot partitions (numbered 1 and 2),
+ * rpmb (3), and up to 4 addition general-purpose partitions (4-7).
+ *
+ * @desc: Block device to update
+ * @hwpart: Hardware partition number to select. 0 means the raw
+ * device, 1 is the first partition, 2 is the second, etc.
+ * @return 0 if OK, -ve on error
+ */
+ int (*select_hwpart)(struct udevice *dev, int hwpart);
};
#define blk_get_ops(dev) ((struct blk_ops *)(dev)->driver->ops)
* @drv_name: Driver name to use for the block device
* @name: Name for the device
* @if_type: Interface type (enum if_type_t)
- * @devnum: Device number, specific to the interface type
+ * @devnum: Device number, specific to the interface type, or -1 to
+ * allocate the next available number
* @blksz: Block size of the device in bytes (typically 512)
* @size: Total size of the device in bytes
* @devp: the new device (which has not been probed)
const char *name, int if_type, int devnum, int blksz,
lbaint_t size, struct udevice **devp);
+/**
+ * blk_create_devicef() - Create a new named block device
+ *
+ * @parent: Parent of the new device
+ * @drv_name: Driver name to use for the block device
+ * @name: Name for the device (parent name is prepended)
+ * @if_type: Interface type (enum if_type_t)
+ * @devnum: Device number, specific to the interface type, or -1 to
+ * allocate the next available number
+ * @blksz: Block size of the device in bytes (typically 512)
+ * @size: Total size of the device in bytes
+ * @devp: the new device (which has not been probed)
+ */
+int blk_create_devicef(struct udevice *parent, const char *drv_name,
+ const char *name, int if_type, int devnum, int blksz,
+ lbaint_t size, struct udevice **devp);
+
/**
* blk_prepare_device() - Prepare a block device for use
*
*/
int blk_unbind_all(int if_type);
+/**
+ * blk_find_max_devnum() - find the maximum device number for an interface type
+ *
+ * Finds the last allocated device number for an interface type @if_type. The
+ * next number is safe to use for a newly allocated device.
+ *
+ * @if_type: Interface type to scan
+ * @return maximum device number found, or -ENODEV if none, or other -ve on
+ * error
+ */
+int blk_find_max_devnum(enum if_type if_type);
+
+/**
+ * blk_select_hwpart() - select a hardware partition
+ *
+ * Select a hardware partition if the device supports it (typically MMC does)
+ *
+ * @dev: Device to update
+ * @hwpart: Partition number to select
+ * @return 0 if OK, -ve on error
+ */
+int blk_select_hwpart(struct udevice *dev, int hwpart);
+
#else
#include <errno.h>
/*
blkcache_invalidate(block_dev->if_type, block_dev->devnum);
return block_dev->block_erase(block_dev, start, blkcnt);
}
+
+/**
+ * struct blk_driver - Driver for block interface types
+ *
+ * This provides access to the block devices for each interface type. One
+ * driver should be provided using U_BOOT_LEGACY_BLK() for each interface
+ * type that is to be supported.
+ *
+ * @if_typename: Interface type name
+ * @if_type: Interface type
+ * @max_devs: Maximum number of devices supported
+ * @desc: Pointer to list of devices for this interface type,
+ * or NULL to use @get_dev() instead
+ */
+struct blk_driver {
+ const char *if_typename;
+ enum if_type if_type;
+ int max_devs;
+ struct blk_desc *desc;
+ /**
+ * get_dev() - get a pointer to a block device given its number
+ *
+ * Each interface allocates its own devices and typically
+ * struct blk_desc is contained with the interface's data structure.
+ * There is no global numbering for block devices. This method allows
+ * the device for an interface type to be obtained when @desc is NULL.
+ *
+ * @devnum: Device number (0 for first device on that interface,
+ * 1 for second, etc.
+ * @descp: Returns pointer to the block device on success
+ * @return 0 if OK, -ve on error
+ */
+ int (*get_dev)(int devnum, struct blk_desc **descp);
+
+ /**
+ * select_hwpart() - Select a hardware partition
+ *
+ * Some devices (e.g. MMC) can support partitioning at the hardware
+ * level. This is quite separate from the normal idea of
+ * software-based partitions. MMC hardware partitions must be
+ * explicitly selected. Once selected only the region of the device
+ * covered by that partition is accessible.
+ *
+ * The MMC standard provides for two boot partitions (numbered 1 and 2),
+ * rpmb (3), and up to 4 addition general-purpose partitions (4-7).
+ * Partition 0 is the main user-data partition.
+ *
+ * @desc: Block device descriptor
+ * @hwpart: Hardware partition number to select. 0 means the main
+ * user-data partition, 1 is the first partition, 2 is
+ * the second, etc.
+ * @return 0 if OK, other value for an error
+ */
+ int (*select_hwpart)(struct blk_desc *desc, int hwpart);
+};
+
+/*
+ * Declare a new U-Boot legacy block driver. New drivers should use driver
+ * model (UCLASS_BLK).
+ */
+#define U_BOOT_LEGACY_BLK(__name) \
+ ll_entry_declare(struct blk_driver, __name, blk_driver)
+
+struct blk_driver *blk_driver_lookup_type(int if_type);
+
#endif /* !CONFIG_BLK */
+/**
+ * blk_get_devnum_by_typename() - Get a block device by type and number
+ *
+ * This looks through the available block devices of the given type, returning
+ * the one with the given @devnum.
+ *
+ * @if_type: Block device type
+ * @devnum: Device number
+ * @return point to block device descriptor, or NULL if not found
+ */
+struct blk_desc *blk_get_devnum_by_type(enum if_type if_type, int devnum);
+
+/**
+ * blk_get_devnum_by_type() - Get a block device by type name, and number
+ *
+ * This looks up the block device type based on @if_typename, then calls
+ * blk_get_devnum_by_type().
+ *
+ * @if_typename: Block device type name
+ * @devnum: Device number
+ * @return point to block device descriptor, or NULL if not found
+ */
+struct blk_desc *blk_get_devnum_by_typename(const char *if_typename,
+ int devnum);
+
+/**
+ * blk_dselect_hwpart() - select a hardware partition
+ *
+ * This selects a hardware partition (such as is supported by MMC). The block
+ * device size may change as this effectively points the block device to a
+ * partition at the hardware level. See the select_hwpart() method above.
+ *
+ * @desc: Block device descriptor for the device to select
+ * @hwpart: Partition number to select
+ * @return 0 if OK, -ve on error
+ */
+int blk_dselect_hwpart(struct blk_desc *desc, int hwpart);
+
+/**
+ * blk_list_part() - list the partitions for block devices of a given type
+ *
+ * This looks up the partition type for each block device of type @if_type,
+ * then displays a list of partitions.
+ *
+ * @if_type: Block device type
+ * @return 0 if OK, -ENODEV if there is none of that type
+ */
+int blk_list_part(enum if_type if_type);
+
+/**
+ * blk_list_devices() - list the block devices of a given type
+ *
+ * This lists each block device of the type @if_type, showing the capacity
+ * as well as type-specific information.
+ *
+ * @if_type: Block device type
+ */
+void blk_list_devices(enum if_type if_type);
+
+/**
+ * blk_show_device() - show information about a given block device
+ *
+ * This shows the block device capacity as well as type-specific information.
+ *
+ * @if_type: Block device type
+ * @devnum: Device number
+ * @return 0 if OK, -ENODEV for invalid device number
+ */
+int blk_show_device(enum if_type if_type, int devnum);
+
+/**
+ * blk_print_device_num() - show information about a given block device
+ *
+ * This is similar to blk_show_device() but returns an error if the block
+ * device type is unknown.
+ *
+ * @if_type: Block device type
+ * @devnum: Device number
+ * @return 0 if OK, -ENODEV for invalid device number, -ENOENT if the block
+ * device is not connected
+ */
+int blk_print_device_num(enum if_type if_type, int devnum);
+
+/**
+ * blk_print_part_devnum() - print the partition information for a device
+ *
+ * @if_type: Block device type
+ * @devnum: Device number
+ * @return 0 if OK, -ENOENT if the block device is not connected, -ENOSYS if
+ * the interface type is not supported, other -ve on other error
+ */
+int blk_print_part_devnum(enum if_type if_type, int devnum);
+
+/**
+ * blk_read_devnum() - read blocks from a device
+ *
+ * @if_type: Block device type
+ * @devnum: Device number
+ * @blkcnt: Number of blocks to read
+ * @buffer: Address to write data to
+ * @return number of blocks read, or -ve error number on error
+ */
+ulong blk_read_devnum(enum if_type if_type, int devnum, lbaint_t start,
+ lbaint_t blkcnt, void *buffer);
+
+/**
+ * blk_write_devnum() - write blocks to a device
+ *
+ * @if_type: Block device type
+ * @devnum: Device number
+ * @blkcnt: Number of blocks to write
+ * @buffer: Address to read data from
+ * @return number of blocks written, or -ve error number on error
+ */
+ulong blk_write_devnum(enum if_type if_type, int devnum, lbaint_t start,
+ lbaint_t blkcnt, const void *buffer);
+
+/**
+ * blk_select_hwpart_devnum() - select a hardware partition
+ *
+ * This is similar to blk_dselect_hwpart() but it looks up the interface and
+ * device number.
+ *
+ * @if_type: Block device type
+ * @devnum: Device number
+ * @hwpart: Partition number to select
+ * @return 0 if OK, -ve on error
+ */
+int blk_select_hwpart_devnum(enum if_type if_type, int devnum, int hwpart);
+
#endif
BOOTSTAGE_ID_ACCUM_SCSI,
BOOTSTAGE_ID_ACCUM_SPI,
BOOTSTAGE_ID_ACCUM_DECOMP,
+ BOOTSTAGE_ID_FPGA_INIT,
/* a few spare for the user, from here */
BOOTSTAGE_ID_USER,
#define CONFIG_CMD_READ /* Read data from partition */
#define CONFIG_CMD_SANDBOX /* sb command to access sandbox features */
#define CONFIG_CMD_SAVES /* save S record dump */
-#define CONFIG_CMD_SCSI /* SCSI Support */
+#define CONFIG_SCSI /* SCSI Support */
#define CONFIG_CMD_SDRAM /* SDRAM DIMM SPD info printout */
#define CONFIG_CMD_TERMINAL /* built-in Serial Terminal */
#define CONFIG_CMD_UBI /* UBI Support */
BOOT_TARGET_DEVICES_references_SATA_without_CONFIG_CMD_SATA
#endif
-#ifdef CONFIG_CMD_SCSI
+#ifdef CONFIG_SCSI
#define BOOTENV_RUN_SCSI_INIT "run scsi_init; "
#define BOOTENV_SET_SCSI_NEED_INIT "setenv scsi_need_init; "
#define BOOTENV_SHARED_SCSI \
#define BOOTENV_SET_SCSI_NEED_INIT
#define BOOTENV_SHARED_SCSI
#define BOOTENV_DEV_SCSI \
- BOOT_TARGET_DEVICES_references_SCSI_without_CONFIG_CMD_SCSI
+ BOOT_TARGET_DEVICES_references_SCSI_without_CONFIG_SCSI
#define BOOTENV_DEV_NAME_SCSI \
- BOOT_TARGET_DEVICES_references_SCSI_without_CONFIG_CMD_SCSI
+ BOOT_TARGET_DEVICES_references_SCSI_without_CONFIG_SCSI
#endif
#ifdef CONFIG_CMD_IDE
/* Rather than repeat this expression each time, add a define for it */
#if defined(CONFIG_CMD_IDE) || \
defined(CONFIG_CMD_SATA) || \
- defined(CONFIG_CMD_SCSI) || \
+ defined(CONFIG_SCSI) || \
defined(CONFIG_CMD_USB) || \
defined(CONFIG_CMD_PART) || \
defined(CONFIG_CMD_GPT) || \
#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI
- #define CONFIG_CMD_SCSI
+ #define CONFIG_SCSI
#endif
/*
#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI
-#define CONFIG_CMD_SCSI
+#define CONFIG_SCSI
#endif
/*
#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI
-#define CONFIG_CMD_SCSI
+#define CONFIG_SCSI
#endif
#define CONFIG_WATCHDOG /* watchdog enabled */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#undef CONFIG_SYS_SCSI_SCAN_BUS_REVERSE
-
#define CONFIG_PCI_PNP /* do pci plug-and-play */
#undef CONFIG_EEPRO100
#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI
- #define CONFIG_CMD_SCSI
+ #define CONFIG_SCSI
#endif
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_FDC
-#define CONFIG_CMD_SCSI
+#define CONFIG_SCSI
#define CONFIG_CMD_DATE
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_SAVES
/* SATA */
#define CONFIG_BOARD_LATE_INIT
-#define CONFIG_CMD_SCSI
+#define CONFIG_SCSI
#define CONFIG_LIBATA
#define CONFIG_SCSI_AHCI
#define CONFIG_SCSI_AHCI_PLAT
--- /dev/null
+/*
+ * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_SYS_TEXT_BASE 0x9f000000
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_BOARD_EARLY_INIT_F
+
+#define CONFIG_SYS_HZ 1000
+#define CONFIG_SYS_MHZ 200
+#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000)
+
+/* Cache Configuration */
+#define CONFIG_SYS_DCACHE_SIZE 0x8000
+#define CONFIG_SYS_ICACHE_SIZE 0x10000
+#define CONFIG_SYS_CACHELINE_SIZE 32
+
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SYS_MALLOC_LEN 0x40000
+#define CONFIG_SYS_BOOTPARAMS_LEN 0x20000
+
+#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CONFIG_SYS_LOAD_ADDR 0x81000000
+
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000
+#define CONFIG_SYS_INIT_RAM_SIZE 0x8000
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE - 1)
+
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE \
+ {9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_BOOTDELAY 3
+#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
+ "root=/dev/mtdblock2 " \
+ "rootfstype=squashfs"
+#define CONFIG_BOOTCOMMAND "sf probe;" \
+ "mtdparts default;" \
+ "bootm 0x9f300000"
+#define CONFIG_LZMA
+
+#define MTDIDS_DEFAULT "nor0=spi-flash.0"
+#define MTDPARTS_DEFAULT "mtdparts=spi-flash.0:" \
+ "256k(u-boot),64k(u-boot-env)," \
+ "2752k(rootfs),896k(uImage)," \
+ "64k(NVRAM),64k(ART)"
+
+#define CONFIG_ENV_SPI_MAX_HZ 25000000
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_OFFSET 0x40000
+#define CONFIG_ENV_SECT_SIZE 0x10000
+#define CONFIG_ENV_SIZE 0x10000
+
+/*
+ * Command
+ */
+#define CONFIG_CMD_MTDPARTS
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_CBSIZE 256
+#define CONFIG_SYS_MAXARGS 16
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_AUTO_COMPLETE
+
+/*
+ * Diagnostics
+ */
+#define CONFIG_SYS_MEMTEST_START 0x80100000
+#define CONFIG_SYS_MEMTEST_END 0x83f00000
+#define CONFIG_CMD_MEMTEST
+
+#endif /* __CONFIG_H */
--- /dev/null
+/*
+ * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_SYS_TEXT_BASE 0x9f000000
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_BOARD_EARLY_INIT_F
+
+#define CONFIG_SYS_HZ 1000
+#define CONFIG_SYS_MHZ 325
+#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000)
+
+/* Cache Configuration */
+#define CONFIG_SYS_DCACHE_SIZE 0x8000
+#define CONFIG_SYS_ICACHE_SIZE 0x10000
+#define CONFIG_SYS_CACHELINE_SIZE 32
+
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SYS_MALLOC_LEN 0x40000
+#define CONFIG_SYS_BOOTPARAMS_LEN 0x20000
+
+#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CONFIG_SYS_LOAD_ADDR 0x81000000
+
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000
+#define CONFIG_SYS_INIT_RAM_SIZE 0x2000
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE - 1)
+
+/*
+ * Serial Port
+ */
+#define CONFIG_SYS_NS16550_CLK 25000000
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE \
+ {9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_BOOTDELAY 3
+#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
+ "root=/dev/mtdblock2 " \
+ "rootfstype=squashfs"
+#define CONFIG_BOOTCOMMAND "sf probe;" \
+ "mtdparts default;" \
+ "bootm 0x9f300000"
+#define CONFIG_LZMA
+
+#define MTDIDS_DEFAULT "nor0=spi-flash.0"
+#define MTDPARTS_DEFAULT "mtdparts=spi-flash.0:" \
+ "256k(u-boot),64k(u-boot-env)," \
+ "2752k(rootfs),896k(uImage)," \
+ "64k(NVRAM),64k(ART)"
+
+#define CONFIG_ENV_SPI_MAX_HZ 25000000
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_OFFSET 0x40000
+#define CONFIG_ENV_SECT_SIZE 0x10000
+#define CONFIG_ENV_SIZE 0x10000
+
+/*
+ * Command
+ */
+#define CONFIG_CMD_MTDPARTS
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_CBSIZE 256
+#define CONFIG_SYS_MAXARGS 16
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_AUTO_COMPLETE
+
+/*
+ * Diagnostics
+ */
+#define CONFIG_SYS_MEMTEST_START 0x80100000
+#define CONFIG_SYS_MEMTEST_END 0x83f00000
+#define CONFIG_CMD_MEMTEST
+
+#endif /* __CONFIG_H */
* I2C configuration
*/
#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_DW
#define CONFIG_I2C_ENV_EEPROM_BUS 2
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_SYS_I2C_SPEED1 100000
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_BMP_LOGO
+/* EEPROM */
+#define CONFIG_CMD_EEPROM
+#define CONFIG_ENV_EEPROM_IS_ON_I2C
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
+#define CONFIG_SYS_EEPROM_SIZE 256
+
+#define CONFIG_CMD_EEPROM_LAYOUT
+#define CONFIG_EEPROM_LAYOUT_HELP_STRING "v2, v3"
+
#endif /* __CONFIG_CM_FX6_H */
#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
#define STATUS_LED_BOOT 0
+/* EEPROM */
+#define CONFIG_CMD_EEPROM
+#define CONFIG_ENV_EEPROM_IS_ON_I2C
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
+#define CONFIG_SYS_EEPROM_SIZE 256
+
+#define CONFIG_CMD_EEPROM_LAYOUT
+#define CONFIG_EEPROM_LAYOUT_HELP_STRING "v2, v3"
+
#ifndef CONFIG_SPL_BUILD
/*
* Enable PCA9555 at I2C0-0x26.
#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
+/* EEPROM */
+#define CONFIG_CMD_EEPROM
+#define CONFIG_ENV_EEPROM_IS_ON_I2C
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
+#define CONFIG_SYS_EEPROM_SIZE 256
+
+#define CONFIG_CMD_EEPROM_LAYOUT
+#define CONFIG_EEPROM_LAYOUT_HELP_STRING "legacy, v1, v2, v3"
+
#endif /* __CONFIG_H */
#define CONFIG_OMAP3_SPI
+/* EEPROM */
+#define CONFIG_CMD_EEPROM
+#define CONFIG_ENV_EEPROM_IS_ON_I2C
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
+#define CONFIG_SYS_EEPROM_SIZE 256
+
+#define CONFIG_CMD_EEPROM_LAYOUT
+#define CONFIG_EEPROM_LAYOUT_HELP_STRING "v1, v2, v3"
+
#endif /* __CONFIG_H */
#define CONFIG_SPL_I2C_SUPPORT
#define CONFIG_SPL_POWER_SUPPORT
+/* EEPROM */
+#define CONFIG_CMD_EEPROM
+#define CONFIG_ENV_EEPROM_IS_ON_I2C
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
+#define CONFIG_SYS_EEPROM_SIZE 256
+
+#define CONFIG_CMD_EEPROM_LAYOUT
+#define CONFIG_EEPROM_LAYOUT_HELP_STRING "v2, v3"
+
#endif /* __CONFIG_CM_T43_H */
#define CONFIG_SPL_SATA_BOOT_DEVICE 0
#define CONFIG_SYS_SATA_FAT_BOOT_PARTITION 1
-#define CONFIG_CMD_SCSI
+#define CONFIG_SCSI
#define CONFIG_LIBATA
#define CONFIG_SCSI_AHCI
#define CONFIG_SCSI_AHCI_PLAT
/* Enabled commands */
+/* EEPROM */
+#define CONFIG_CMD_EEPROM
+#define CONFIG_ENV_EEPROM_IS_ON_I2C
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
+#define CONFIG_SYS_EEPROM_SIZE 256
+
+#define CONFIG_CMD_EEPROM_LAYOUT
+#define CONFIG_EEPROM_LAYOUT_HELP_STRING "v2, v3"
+
/* USB Networking options */
#define CONFIG_USB_HOST_ETHER
#define CONFIG_USB_ETHER_SMSC95XX
#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
#define CONFIG_CMD_ENV
#define CONFIG_CMD_PCI
-#define CONFIG_CMD_SCSI
+#define CONFIG_SCSI
/* I2C */
#define CONFIG_SYS_I2C
/* SATA */
#define CONFIG_BOARD_LATE_INIT
-#define CONFIG_CMD_SCSI
+#define CONFIG_SCSI
#define CONFIG_LIBATA
#define CONFIG_SCSI_AHCI
#define CONFIG_SCSI_AHCI_PLAT
#undef CONFIG_VIDEO
#undef CONFIG_CFB_CONSOLE
#undef CONFIG_SCSI_AHCI
-#undef CONFIG_CMD_SCSI
+#undef CONFIG_SCSI
#undef CONFIG_INTEL_ICH6_GPIO
#undef CONFIG_USB_EHCI_PCI
/* SATA is not supported in Quark SoC */
#undef CONFIG_SCSI_AHCI
-#undef CONFIG_CMD_SCSI
+#undef CONFIG_SCSI
/* Video is not supported in Quark SoC */
#undef CONFIG_VIDEO
/*
* Command line configuration.
*/
-#define CONFIG_CMD_SCSI
+#define CONFIG_SCSI
#define CONFIG_BOOT_RETRY_TIME -1
#define CONFIG_RESET_TO_RETRY
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 800 /* 400 KB */
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SYS_MONITOR_LEN (CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS/2*1024)
+#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
+#define CONFIG_SPL_EXT_SUPPORT
#endif
/* SATA support */
#if defined(CONFIG_SPL_SATA_SUPPORT)
#define CONFIG_SPL_SATA_BOOT_DEVICE 0
#define CONFIG_SYS_SATA_FAT_BOOT_PARTITION 1
+#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
+#define CONFIG_SPL_EXT_SUPPORT
#endif
/* Define the payload for FAT/EXT support */
#define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \
"earlycon=uart8250,mmio,0x21c0500"
+#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
+#define CONFIG_BOOTCOMMAND "sf probe && sf read $kernel_load " \
+ "e0000 f00000 && bootm $kernel_load"
+#else
#define CONFIG_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \
"$kernel_size && bootm $kernel_load"
+#endif
#define CONFIG_BOOTDELAY 10
/* Monitor Command Prompt */
#define CONFIG_LIBATA
#define CONFIG_SCSI_AHCI
#define CONFIG_SCSI_AHCI_PLAT
-#define CONFIG_CMD_SCSI
+#define CONFIG_SCSI
#define CONFIG_DOS_PARTITION
#define CONFIG_BOARD_LATE_INIT
#define CONFIG_PHY_VITESSE
#define CONFIG_PHY_REALTEK
#define CONFIG_PHY_AQUANTIA
+#define AQR105_IRQ_MASK 0x40000000
#define RGMII_PHY1_ADDR 0x1
#define RGMII_PHY2_ADDR 0x2
#define CONFIG_USB_STORAGE
#endif
+/* SATA */
+#define CONFIG_LIBATA
+#define CONFIG_SCSI_AHCI
+#define CONFIG_CMD_SCSI
+#ifndef CONFIG_CMD_FAT
+#define CONFIG_CMD_FAT
+#endif
+#ifndef CONFIG_CMD_EXT2
+#define CONFIG_CMD_EXT2
+#endif
+#define CONFIG_DOS_PARTITION
+#define CONFIG_BOARD_LATE_INIT
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID 2
+#define CONFIG_SYS_SCSI_MAX_LUN 2
+#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
+ CONFIG_SYS_SCSI_MAX_LUN)
+#define SCSI_VEND_ID 0x1b4b
+#define SCSI_DEV_ID 0x9170
+#define CONFIG_SCSI_DEV_LIST {SCSI_VEND_ID, SCSI_DEV_ID}
+#define CONFIG_PCI
+
#include <asm/fsl_secure_boot.h>
#endif /* __LS1043ARDB_H__ */
/* We need architecture specific misc initializations */
#define CONFIG_ARCH_MISC_INIT
+#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
+
/* Link Definitions */
#ifdef CONFIG_SPL
#define CONFIG_SYS_TEXT_BASE 0x80400000
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
+/* Hash command with SHA acceleration supported in hardware */
+#ifdef CONFIG_FSL_CAAM
+#define CONFIG_CMD_HASH
+#define CONFIG_SHA_HW_ACCEL
+#endif
+
#endif /* __LS2_COMMON_H */
#define CONFIG_LIBATA
#define CONFIG_SCSI_AHCI
#define CONFIG_SCSI_AHCI_PLAT
-#define CONFIG_CMD_SCSI
+#define CONFIG_SCSI
#define CONFIG_DOS_PARTITION
#define CONFIG_BOARD_LATE_INIT
#define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf
#define CONFIG_MII /* MII PHY management */
-#define CONFIG_ETHPRIME "DPNI1"
+#define CONFIG_ETHPRIME "DPMAC1@xgmii"
#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
#endif
#define CONFIG_LIBATA
#define CONFIG_SCSI_AHCI
#define CONFIG_SCSI_AHCI_PLAT
-#define CONFIG_CMD_SCSI
+#define CONFIG_SCSI
#define CONFIG_DOS_PARTITION
#define CONFIG_BOARD_LATE_INIT
#define AQR405_IRQ_MASK 0x36
#define CONFIG_MII
-#define CONFIG_ETHPRIME "DPNI1"
+#define CONFIG_ETHPRIME "DPMAC1@xgmii"
#define CONFIG_PHY_GIGE
#define CONFIG_PHY_AQUANTIA
#endif
#define CONFIG_X86EMU_RAW_IO
#define CONFIG_ENV_SECT_SIZE 0x1000
-#define CONFIG_ENV_OFFSET 0x007fe000
+#define CONFIG_ENV_OFFSET 0x006ef000
#endif /* __CONFIG_H */
/* SPL */
#define CONFIG_SPL_FAT_SUPPORT
-#define CONFIG_SPL_EXT_SUPPORT
#define CONFIG_SPL_MMC_SUPPORT
#include "imx6_spl.h" /* common IMX6 SPL configuration */
#define CONFIG_USB_EHCI_MX6
#define CONFIG_USB_STORAGE
#define CONFIG_USB_KEYBOARD
+#define CONFIG_SYS_STDIO_DEREGISTER
#define CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP
#define CONFIG_USB_HOST_ETHER
#define CONFIG_USB_ETHER_ASIX
/* Max time to hold reset on this board, see doc/README.omap-reset-time */
#define CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC 16296
-#define CONFIG_CMD_SCSI
+#define CONFIG_SCSI
#define CONFIG_LIBATA
#define CONFIG_SCSI_AHCI
#define CONFIG_SCSI_AHCI_PLAT
#define CONFIG_CMD_IDE
#define CONFIG_DOS_PARTITION
+#ifdef CONFIG_SYS_BIG_ENDIAN
+#define CONFIG_IDE_SWAP_IO
+#endif
+
#define CONFIG_SYS_IDE_MAXBUS 2
#define CONFIG_SYS_ATA_IDE0_OFFSET 0x1f0
#define CONFIG_SYS_ATA_IDE1_OFFSET 0x170
#define CONFIG_CMD_IDE
#define CONFIG_DOS_PARTITION
+#ifdef CONFIG_SYS_BIG_ENDIAN
+#define CONFIG_IDE_SWAP_IO
+#endif
+
#define CONFIG_SYS_IDE_MAXBUS 2
#define CONFIG_SYS_ATA_IDE0_OFFSET 0x1f0
#define CONFIG_SYS_ATA_IDE1_OFFSET 0x170
#define CONFIG_ATAPI
#undef CONFIG_SCSI_AHCI
-#undef CONFIG_CMD_SCSI
+#undef CONFIG_SCSI
#else
#define CONFIG_SCSI_DEV_LIST \
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_AHCI}
--- /dev/null
+/*
+ * Configuration settings for the SAMA5D2 PTC Engineering board.
+ *
+ * Copyright (C) 2016 Atmel
+ * Wenyou Yang <wenyou.yang@atmel.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* No NOR flash, this definition should put before common header */
+#define CONFIG_SYS_NO_FLASH
+
+#include "at91-sama5_common.h"
+
+/* serial console */
+#define CONFIG_ATMEL_USART
+#define CONFIG_USART_BASE ATMEL_BASE_UART0
+#define CONFIG_USART_ID ATMEL_ID_UART0
+
+#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS
+#define CONFIG_SYS_SDRAM_SIZE 0x20000000
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_INIT_SP_ADDR 0x210000
+#else
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE)
+#endif
+
+#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
+
+#undef CONFIG_AT91_GPIO
+#define CONFIG_ATMEL_PIO4
+
+/* SDRAM */
+#define CONFIG_NR_DRAM_BANKS 1
+
+/* SerialFlash */
+#ifdef CONFIG_CMD_SF
+#define CONFIG_ATMEL_SPI
+#define CONFIG_SPI_FLASH_ATMEL
+#define CONFIG_SF_DEFAULT_BUS 0
+#define CONFIG_SF_DEFAULT_CS 0
+#define CONFIG_SF_DEFAULT_SPEED 30000000
+#endif
+
+/* NAND flash */
+#define CONFIG_CMD_NAND
+
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_NAND_ATMEL
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
+/* our ALE is AD21 */
+#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
+/* our CLE is AD22 */
+#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+/* PMECC & PMERRLOC */
+#define CONFIG_ATMEL_NAND_HWECC
+#define CONFIG_ATMEL_NAND_HW_PMECC
+#define CONFIG_CMD_NAND_TRIMFFS
+#endif
+
+/* USB */
+#define CONFIG_CMD_USB
+
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_ATMEL
+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
+#define CONFIG_USB_STORAGE
+#endif
+
+/* USB device */
+#define CONFIG_USB_GADGET
+#define CONFIG_USB_GADGET_DUALSPEED
+#define CONFIG_USB_GADGET_ATMEL_USBA
+#define CONFIG_USB_ETHER
+#define CONFIG_USB_ETH_RNDIS
+#define CONFIG_USBNET_MANUFACTURER "Atmel SAMA5D2_PTC"
+
+#if defined(CONFIG_CMD_USB)
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
+/* Ethernet Hardware */
+#define CONFIG_MACB
+#define CONFIG_RMII
+#define CONFIG_NET_RETRY_COUNT 20
+#define CONFIG_MACB_SEARCH_PHY
+
+#ifdef CONFIG_SYS_USE_NANDFLASH
+#undef CONFIG_ENV_OFFSET
+#undef CONFIG_ENV_OFFSET_REDUND
+#undef CONFIG_BOOTCOMMAND
+/* u-boot env in nand flash */
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET 0x200000
+#define CONFIG_ENV_OFFSET_REDUND 0x400000
+#define CONFIG_BOOTCOMMAND "nand read 0x21000000 0xb80000 0x80000;" \
+ "nand read 0x22000000 0x600000 0x600000;" \
+ "bootz 0x22000000 - 0x21000000"
+#endif
+
+#undef CONFIG_BOOTARGS
+#define CONFIG_BOOTARGS \
+ "console=ttyS0,57600 earlyprintk " \
+ "mtdparts=atmel_nand:6M(bootstrap)ro, 6M(kernel)ro,-(rootfs) " \
+ "rootfstype=ubifs ubi.mtd=2 root=ubi0:rootfs"
+
+/* SPL */
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_TEXT_BASE 0x200000
+#define CONFIG_SPL_MAX_SIZE 0x10000
+#define CONFIG_SPL_BSS_START_ADDR 0x20000000
+#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
+#define CONFIG_SYS_SPL_MALLOC_START 0x20080000
+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
+
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_GPIO_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+
+#define CONFIG_SPL_BOARD_INIT
+#define CONFIG_SYS_MONITOR_LEN (512 << 10)
+
+#ifdef CONFIG_SYS_USE_SERIALFLASH
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_LOAD
+#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000
+
+#elif CONFIG_SYS_USE_NANDFLASH
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_PMECC_CAP 8
+#define CONFIG_PMECC_SECTOR_SIZE 512
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_SIZE 0x1000
+#define CONFIG_SYS_NAND_PAGE_COUNT 64
+#define CONFIG_SYS_NAND_OOBSIZE 224
+#define CONFIG_SYS_NAND_BLOCK_SIZE 0x40000
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
+#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
+#endif
+
+#endif
#define CONFIG_CMD_LZMADEC
#define CONFIG_CMD_DATE
+#define CONFIG_CMD_IDE
+#define CONFIG_SYS_IDE_MAXBUS 1
+#define CONFIG_SYS_ATA_IDE0_OFFSET 0
+#define CONFIG_SYS_IDE_MAXDEVICE 2
+#define CONFIG_SYS_ATA_BASE_ADDR 0x100
+#define CONFIG_SYS_ATA_DATA_OFFSET 0
+#define CONFIG_SYS_ATA_REG_OFFSET 1
+#define CONFIG_SYS_ATA_ALT_OFFSET 2
+#define CONFIG_SYS_ATA_STRIDE 4
+
+#define CONFIG_SCSI
+#define CONFIG_SCSI_AHCI_PLAT
+#define CONFIG_SYS_SCSI_MAX_DEVICE 2
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID 8
+#define CONFIG_SYS_SCSI_MAX_LUN 4
+
+#define CONFIG_CMD_SATA
+#define CONFIG_SYS_SATA_MAX_DEVICE 2
+
+#define CONFIG_SYSTEMACE
+#define CONFIG_SYS_SYSTEMACE_WIDTH 16
+#define CONFIG_SYS_SYSTEMACE_BASE 0
+
+#define CONFIG_GENERIC_MMC
+
#endif
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#undef CONFIG_SYS_SCSI_SCAN_BUS_REVERSE
-
#define CONFIG_PCI_PNP /* do pci plug-and-play */
#undef CONFIG_EEPRO100
* I2C support
*/
#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_DW
#define CONFIG_SYS_I2C_BUS_MAX 4
#define CONFIG_SYS_I2C_BASE SOCFPGA_I2C0_ADDRESS
#define CONFIG_SYS_I2C_BASE1 SOCFPGA_I2C1_ADDRESS
/* I2C driver configuration */
#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_DW
#if defined(CONFIG_SPEAR600)
#define CONFIG_SYS_I2C_BASE 0xD0200000
#elif defined(CONFIG_SPEAR300)
#define CONFIG_SYS_SCSI_MAX_LUN 1
#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
CONFIG_SYS_SCSI_MAX_LUN)
-#define CONFIG_CMD_SCSI
+#define CONFIG_SCSI
#endif
#define CONFIG_SETUP_MEMORY_TAGS
#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */
+#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
#define CONFIG_SYS_ALT_MEMTEST
#define CONFIG_PREBOOT
#ifdef CONFIG_SPL_BUILD
#undef CONFIG_DM_MMC
#undef CONFIG_TIMER
+#undef CONFIG_DM_ETH
#endif
#endif /* __CONFIG_TI_OMAP5_COMMON_H */
--- /dev/null
+/*
+ * Copyright (C) 2016 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_SYS_TEXT_BASE 0xa1000000
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_BOARD_EARLY_INIT_F
+
+#define CONFIG_SYS_HZ 1000
+#define CONFIG_SYS_MHZ 280
+#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000)
+
+/* Cache Configuration */
+#define CONFIG_SYS_DCACHE_SIZE 0x8000
+#define CONFIG_SYS_ICACHE_SIZE 0x10000
+#define CONFIG_SYS_CACHELINE_SIZE 32
+
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SYS_MALLOC_LEN 0x40000
+#define CONFIG_SYS_BOOTPARAMS_LEN 0x20000
+
+#define CONFIG_SYS_SDRAM_BASE 0xa0000000
+#define CONFIG_SYS_LOAD_ADDR 0xa1000000
+#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
+
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000
+#define CONFIG_SYS_INIT_RAM_SIZE 0x8000
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)
+
+/*
+ * Serial Port
+ */
+#define CONFIG_SYS_NS16550_CLK 40000000
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE \
+ {9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_BOOTDELAY 3
+#define CONFIG_BOOTARGS \
+ "console=ttyS0,115200 root=/dev/mtdblock2 rootfstype=squashfs"
+#define CONFIG_BOOTCOMMAND \
+ "dhcp 192.168.1.1:wdr4300.fit && bootm $loadaddr"
+#define CONFIG_LZMA
+
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_SIZE 0x10000
+
+/*
+ * Command
+ */
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */
+#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+ /* Boot argument buffer size */
+#define CONFIG_VERSION_VARIABLE /* U-BOOT version */
+#define CONFIG_AUTO_COMPLETE /* Command auto complete */
+#define CONFIG_CMDLINE_EDITING /* Command history etc */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+/* USB, USB storage, USB ethernet */
+#define CONFIG_EHCI_MMIO_BIG_ENDIAN
+#define CONFIG_EHCI_DESC_BIG_ENDIAN
+#define CONFIG_EHCI_IS_TDI
+
+#define CONFIG_DOS_PARTITION
+
+/*
+ * Diagnostics
+ */
+#define CONFIG_SYS_MEMTEST_START 0x80100000
+#define CONFIG_SYS_MEMTEST_END 0x83f00000
+#define CONFIG_CMD_MEMTEST
+
+#define CONFIG_USE_PRIVATE_LIBGCC
+
+#define CONFIG_CMD_MII
+#define CONFIG_PHY_GIGE
+
+#endif /* __CONFIG_H */
#define CONFIG_SPL_MMC_SUPPORT
#define CONFIG_SPL_SPI_SUPPORT
#define CONFIG_SPL_FAT_SUPPORT
-#define CONFIG_SPL_EXT_SUPPORT
/* common IMX6 SPL configuration */
#include "imx6_spl.h"
/* I2C config options */
#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_DW
#define CONFIG_SYS_I2C_BASE 0xD0200000
#define CONFIG_SYS_I2C_SPEED 400000
#define CONFIG_SYS_I2C_SLAVE 0x02
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_PCI
#define CONFIG_CMD_GETTIME
-#define CONFIG_CMD_SCSI
+#define CONFIG_SCSI
#define CONFIG_CMD_ZBOOT
#define CONFIG_HOSTNAME x86
#define CONFIG_BOOTFILE "bzImage"
#define CONFIG_LOADADDR 0x1000000
-#define CONFIG_RAMDISK_ADDR 0x4000000
+#define CONFIG_RAMDISK_ADDR 0x4000000
+#ifdef CONFIG_GENERATE_ACPI_TABLE
+#define CONFIG_OTHBOOTARGS "othbootargs=\0"
+#else
+#define CONFIG_OTHBOOTARGS "othbootargs=acpi=off\0"
+#endif
#define CONFIG_EXTRA_ENV_SETTINGS \
CONFIG_STD_DEVICES_SETTINGS \
"pciconfighost=1\0" \
"netdev=eth0\0" \
"consoledev=ttyS0\0" \
- "othbootargs=acpi=off\0" \
+ CONFIG_OTHBOOTARGS \
"ramdiskaddr=0x4000000\0" \
"ramdiskfile=initramfs.gz\0"
# define CONFIG_IDENT_STRING " Xilinx ZynqMP"
#endif
-#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_INIT_SP_ADDR 0xfffffffc
/* Generic Timer Definitions - setup in EL3. Setup by ATF for other cases */
#if !defined(COUNTER_FREQUENCY)
#define CONFIG_CMD_ENV
#define CONFIG_DOS_PARTITION
#define CONFIG_EFI_PARTITION
+#ifndef CONFIG_SPL_BUILD
+# define CONFIG_ISO_PARTITION
+#endif
#define CONFIG_MP
/* BOOTP options */
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_MAY_FAIL
#define CONFIG_BOOTP_SERVERIP
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_PXE
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_PXE_CLIENTARCH 0x100
+
+/* Diff from config_distro_defaults.h */
+#define CONFIG_SUPPORT_RAW_INITRD
+#define CONFIG_ENV_VARS_UBOOT_CONFIG
+#define CONFIG_AUTO_COMPLETE
+
+/* PXE */
+#define CONFIG_CMD_PXE
+#define CONFIG_MENU
#if defined(CONFIG_ZYNQ_SDHCI)
# define CONFIG_MMC
# define CONFIG_GENERIC_MMC
+# define CONFIG_SUPPORT_EMMC_BOOT
# define CONFIG_SDHCI
# ifndef CONFIG_ZYNQ_SDHCI_MAX_FREQ
# define CONFIG_ZYNQ_SDHCI_MAX_FREQ 200000000
#endif
/* Initial environment variables */
+#ifndef CONFIG_EXTRA_ENV_SETTINGS
#define CONFIG_EXTRA_ENV_SETTINGS \
"kernel_addr=0x80000\0" \
"fdt_addr=0x7000000\0" \
"load mmc $sdbootdev:$partid $kernel_addr Image && " \
"booti $kernel_addr - $fdt_addr\0" \
DFU_ALT_INFO
+#endif
-#define CONFIG_PREBOOT "run bootargs"
#define CONFIG_BOOTCOMMAND "run $modeboot"
#define CONFIG_BOOTDELAY 3
#define CONFIG_SYS_SCSI_MAX_LUN 1
#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
CONFIG_SYS_SCSI_MAX_LUN)
-#define CONFIG_CMD_SCSI
+#define CONFIG_SCSI
#endif
#define CONFIG_SYS_BOOTM_LEN (60 * 1024 * 1024)
#define CONFIG_BOARD_EARLY_INIT_R
#define CONFIG_CLOCKS
+#define CONFIG_SPL_TEXT_BASE 0xfffc0000
+#define CONFIG_SPL_MAX_SIZE 0x20000
+
+/* Just random location in OCM */
+#define CONFIG_SPL_BSS_START_ADDR 0x1000000
+#define CONFIG_SPL_BSS_MAX_SIZE 0x2000000
+
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_BOARD_INIT
+#define CONFIG_SPL_RAM_DEVICE
+
+#define CONFIG_SPL_OS_BOOT
+/* u-boot is like dtb */
+#define CONFIG_SPL_FS_LOAD_ARGS_NAME "u-boot.bin"
+#define CONFIG_SYS_SPL_ARGS_ADDR 0x8000000
+
+/* ATF is my kernel image */
+#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "atf.ub"
+
+/* FIT load address for RAM boot */
+#define CONFIG_SPL_LOAD_FIT_ADDRESS 0x10000000
+
+/* MMC support */
+#ifdef CONFIG_ZYNQ_SDHCI
+# define CONFIG_SPL_MMC_SUPPORT
+# define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
+# define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0 /* unused */
+# define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0 /* unused */
+# define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0 /* unused */
+# define CONFIG_SPL_LIBDISK_SUPPORT
+# define CONFIG_SPL_FAT_SUPPORT
+# define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
+#endif
+
#endif /* __XILINX_ZYNQMP_H */
#define CONFIG_IDENT_STRING " Xilinx ZynqMP ZCU102"
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_CMD_EEPROM
+#define CONFIG_ZYNQ_EEPROM_BUS 5
+#define CONFIG_ZYNQ_GEM_EEPROM_ADDR 0x54
+#define CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET 0x20
+
#define CONFIG_KERNEL_FDT_OFST_SIZE \
"kernel_offset=0x180000\0" \
"fdt_offset=0x100000\0" \
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_LIBDISK_SUPPORT
#define CONFIG_SPL_FAT_SUPPORT
-#ifdef CONFIG_OF_SEPARATE
-# define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.img"
-#else
-# define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
-#endif
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
#endif
/* Disable dcache for SPL just for sure */
u32 sliver_reg_ofs;
int phy_addr;
int phy_if;
+ int phy_of_handle;
};
enum {
};
int cpsw_register(struct cpsw_platform_data *data);
+int ti_cm_get_macid(struct udevice *dev, int slave, u8 *mac_addr);
#endif /* _CPSW_H_ */
/* Device is bound */
#define DM_FLAG_BOUND (1 << 6)
+/* Device name is allocated and should be freed on unbind() */
+#define DM_NAME_ALLOCED (1 << 7)
+
/**
* struct udevice - An instance of a driver
*
* this is unnecessary but for probed devices which don't get a useful name
* this function can be helpful.
*
+ * The name is allocated and will be freed automatically when the device is
+ * unbound.
+ *
* @dev: Device to update
* @name: New name (this string is allocated new memory and attached to
* the device)
*/
int device_set_name(struct udevice *dev, const char *name);
+/**
+ * device_set_name_alloced() - note that a device name is allocated
+ *
+ * This sets the DM_NAME_ALLOCED flag for the device, so that when it is
+ * unbound the name will be freed. This avoids memory leaks.
+ *
+ * @dev: Device to update
+ */
+void device_set_name_alloced(struct udevice *dev);
+
+/**
+ * of_device_is_compatible() - check if the device is compatible with the compat
+ *
+ * This allows to check whether the device is comaptible with the compat.
+ *
+ * @dev: udevice pointer for which compatible needs to be verified.
+ * @compat: Compatible string which needs to verified in the given
+ * device
+ * @return true if OK, false if the compatible is not found
+ */
+bool of_device_is_compatible(struct udevice *dev, const char *compat);
+
+/**
+ * of_machine_is_compatible() - check if the machine is compatible with
+ * the compat
+ *
+ * This allows to check whether the machine is comaptible with the compat.
+ *
+ * @compat: Compatible string which needs to verified
+ * @return true if OK, false if the compatible is not found
+ */
+bool of_machine_is_compatible(const char *compat);
+
/**
* device_is_on_pci_bus - Test if a device is on a PCI bus
*
--- /dev/null
+/*
+ * Copyright (c) 2015 Angelo Dureghello <angelo@sysam.it>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __serial_coldfire_h
+#define __serial_coldfire_h
+
+/*
+ * struct coldfire_serial_platdata - information about a coldfire port
+ *
+ * @base: Uart port base register address
+ * @port: Uart port index, for cpu with pinmux for uart / gpio
+ * baudrtatre: Uart port baudrate
+ */
+struct coldfire_serial_platdata {
+ unsigned long base;
+ int port;
+ int baudrate;
+};
+
+#endif /* __serial_coldfire_h */
/* U-Boot uclasses start here - in alphabetical order */
UCLASS_ADC, /* Analog-to-digital converter */
+ UCLASS_AHCI, /* SATA disk controller */
UCLASS_BLK, /* Block device */
UCLASS_CLK, /* Clock source, e.g. used by peripherals */
UCLASS_CPU, /* CPU, typically part of an SoC */
UCLASS_CROS_EC, /* Chrome OS EC */
- UCLASS_DISK, /* Disk controller, e.g. SATA */
UCLASS_DISPLAY, /* Display (e.g. DisplayPort, HDMI) */
UCLASS_DMA, /* Direct Memory Access */
UCLASS_RAM, /* RAM controller */
--- /dev/null
+/*
+ * TI DP83867 PHY drivers
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ *
+ */
+
+#ifndef _DT_BINDINGS_TI_DP83867_H
+#define _DT_BINDINGS_TI_DP83867_H
+
+/* PHY CTRL bits */
+#define DP83867_PHYCR_FIFO_DEPTH_3_B_NIB 0x00
+#define DP83867_PHYCR_FIFO_DEPTH_4_B_NIB 0x01
+#define DP83867_PHYCR_FIFO_DEPTH_6_B_NIB 0x02
+#define DP83867_PHYCR_FIFO_DEPTH_8_B_NIB 0x03
+
+/* RGMIIDCTL internal delay for rx and tx */
+#define DP83867_RGMIIDCTL_250_PS 0x0
+#define DP83867_RGMIIDCTL_500_PS 0x1
+#define DP83867_RGMIIDCTL_750_PS 0x2
+#define DP83867_RGMIIDCTL_1_NS 0x3
+#define DP83867_RGMIIDCTL_1_25_NS 0x4
+#define DP83867_RGMIIDCTL_1_50_NS 0x5
+#define DP83867_RGMIIDCTL_1_75_NS 0x6
+#define DP83867_RGMIIDCTL_2_00_NS 0x7
+#define DP83867_RGMIIDCTL_2_25_NS 0x8
+#define DP83867_RGMIIDCTL_2_50_NS 0x9
+#define DP83867_RGMIIDCTL_2_75_NS 0xa
+#define DP83867_RGMIIDCTL_3_00_NS 0xb
+#define DP83867_RGMIIDCTL_3_25_NS 0xc
+#define DP83867_RGMIIDCTL_3_50_NS 0xd
+#define DP83867_RGMIIDCTL_3_75_NS 0xe
+#define DP83867_RGMIIDCTL_4_00_NS 0xf
+
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2009-2016 CompuLab, Ltd.
+ *
+ * Authors: Nikita Kiryanov <nikita@compulab.co.il>
+ * Igor Grinberg <grinberg@compulab.co.il>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _FIELD_
+#define _FIELD_
+
+#define PRINT_FIELD_SEGMENT "%-30s"
+
+struct eeprom_field {
+ char *name;
+ int size;
+ unsigned char *buf;
+
+ void (*print)(const struct eeprom_field *eeprom_field);
+ int (*update)(struct eeprom_field *eeprom_field, char *value);
+};
+
+void eeprom_field_print_bin(const struct eeprom_field *field);
+int eeprom_field_update_bin(struct eeprom_field *field, char *value);
+
+void eeprom_field_print_bin_rev(const struct eeprom_field *field);
+int eeprom_field_update_bin_rev(struct eeprom_field *field, char *value);
+
+void eeprom_field_print_mac(const struct eeprom_field *field);
+int eeprom_field_update_mac(struct eeprom_field *field, char *value);
+
+void eeprom_field_print_ascii(const struct eeprom_field *field);
+int eeprom_field_update_ascii(struct eeprom_field *field, char *value);
+
+void eeprom_field_print_reserved(const struct eeprom_field *field);
+int eeprom_field_update_reserved(struct eeprom_field *field, char *value);
+
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2009-2016 CompuLab, Ltd.
+ *
+ * Authors: Nikita Kiryanov <nikita@compulab.co.il>
+ * Igor Grinberg <grinberg@compulab.co.il>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _LAYOUT_
+#define _LAYOUT_
+
+#define RESERVED_FIELDS NULL
+#define LAYOUT_VERSION_UNRECOGNIZED -1
+#define LAYOUT_VERSION_AUTODETECT -2
+
+struct eeprom_layout {
+ struct eeprom_field *fields;
+ int num_of_fields;
+ int layout_version;
+ unsigned char *data;
+ int data_size;
+ void (*print)(const struct eeprom_layout *eeprom_layout);
+ int (*update)(struct eeprom_layout *eeprom_layout, char *field_name,
+ char *new_data);
+};
+
+void eeprom_layout_setup(struct eeprom_layout *layout, unsigned char *buf,
+ unsigned int buf_size, int layout_version);
+__weak void __eeprom_layout_assign(struct eeprom_layout *layout,
+ int layout_version);
+
+#endif
#define FLASH_STM800DT 0x00D7 /* STM M29W800DT (1M = 64K x 16, top) */
#define FLASH_STM800DB 0x005B /* STM M29W800DB (1M = 64K x 16, bottom)*/
+#define FLASH_MCHP100T 0x0060 /* MCHP internal (1M = 64K x 16) */
+#define FLASH_MCHP100B 0x0061 /* MCHP internal (1M = 64K x 16) */
+
#define FLASH_28F400_T 0x0062 /* MT 28F400B3 ID ( 4M = 256K x 16 ) */
#define FLASH_28F400_B 0x0063 /* MT 28F400B3 ID ( 4M = 256K x 16 ) */
#define FLASH_MAN_SHARP 0x00500000
#define FLASH_MAN_ATM 0x00600000
#define FLASH_MAN_CFI 0x01000000
-
+#define FLASH_MAN_MCHP 0x02000000 /* Microchip Technology */
#define FLASH_TYPEMASK 0x0000FFFF /* extract FLASH type information */
#define FLASH_VENDMASK 0xFFFF0000 /* extract FLASH vendor information */
#define WR_DATA_DELAY_SHIFT 10
#endif
+/* DDR_EOR register */
+#define DDR_EOR_RD_REOD_DIS 0x07000000
+#define DDR_EOR_WD_REOD_DIS 0x00100000
+
/* DDR_MD_CNTL */
#define MD_CNTL_MD_EN 0x80000000
#define MD_CNTL_CS_SEL_CS0 0x00000000
#define DDR_MR5_CA_PARITY_LAT_4_CLK 0x1 /* for DDR4-1600/1866/2133 */
#define DDR_MR5_CA_PARITY_LAT_5_CLK 0x2 /* for DDR4-2400 */
+/* DEBUG_26 register */
+#define DDR_CAS_TO_PRE_SUB_MASK 0x0000f000 /* CAS to preamble subtract value */
+#define DDR_CAS_TO_PRE_SUB_SHIFT 12
+
+/* DEBUG_29 register */
+#define DDR_TX_BD_DIS (1 << 10) /* Transmit Bit Deskew Disable */
+
#if (defined(CONFIG_SYS_FSL_DDR_VER) && \
(CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7))
#endif
-int sec_init(void);
-
/* blob_dek:
* Encapsulates the src in a secure blob and stores it dst
* @src: reference to the plaintext
*/
int blob_dek(const u8 *src, u8 *dst, u8 len);
+#if defined(CONFIG_PPC_C29X)
+int sec_init_idx(uint8_t);
+#endif
+int sec_init(void);
#endif
#endif /* __FSL_SEC_H */
void ide_init(void);
struct blk_desc;
+struct udevice;
+#ifdef CONFIG_BLK
+ulong ide_read(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
+ void *buffer);
+ulong ide_write(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
+ const void *buffer);
+#else
ulong ide_read(struct blk_desc *block_dev, lbaint_t blknr, lbaint_t blkcnt,
void *buffer);
ulong ide_write(struct blk_desc *block_dev, lbaint_t blknr, lbaint_t blkcnt,
const void *buffer);
+#endif
#ifdef CONFIG_IDE_PREINIT
int ide_preinit(void);
#define IH_TYPE_RKSD 24 /* Rockchip SD card */
#define IH_TYPE_RKSPI 25 /* Rockchip SPI image */
#define IH_TYPE_ZYNQIMAGE 26 /* Xilinx Zynq Boot Image */
+#define IH_TYPE_ZYNQMPIMAGE 27 /* Xilinx ZynqMP Boot Image */
+#define IH_TYPE_FPGA 28 /* FPGA Image */
-#define IH_TYPE_COUNT 27 /* Number of image types */
+#define IH_TYPE_COUNT 29 /* Number of image types */
/*
* Compression Types
int genimg_has_config(bootm_headers_t *images);
ulong genimg_get_image(ulong img_addr);
+int boot_get_fpga(int argc, char * const argv[], bootm_headers_t *images,
+ uint8_t arch, const ulong *ld_start, ulong * const ld_len);
int boot_get_ramdisk(int argc, char * const argv[], bootm_headers_t *images,
uint8_t arch, ulong *rd_start, ulong *rd_end);
#define FIT_LOADABLE_PROP "loadables"
#define FIT_DEFAULT_PROP "default"
#define FIT_SETUP_PROP "setup"
+#define FIT_FPGA_PROP "fpga"
#define FIT_MAX_HASH_LEN HASH_MAX_DIGEST_SIZE
#define writew(val, addr) iotrace_writew(val, (const void *)(addr))
#undef readb
-#define readb(addr) iotrace_readb((const void *)(addr))
+#define readb(addr) iotrace_readb((const void *)(uintptr_t)addr)
#undef writeb
-#define writeb(val, addr) iotrace_writeb(val, (const void *)(addr))
+#define writeb(val, addr) \
+ iotrace_writeb(val, (const void *)(uintptr_t)addr)
#endif
USB_DR_MODE_OTG,
};
+/**
+ * usb_get_dr_mode() - Get dual role mode for given device
+ * @node: Node offset to the given device
+ *
+ * The function gets phy interface string from property 'dr_mode',
+ * and returns the correspondig enum usb_dr_mode
+ */
+enum usb_dr_mode usb_get_dr_mode(int node);
+
#endif /* __LINUX_USB_OTG_H */
/* TODO struct mmc should be in mmc_private but it's hard to fix right now */
struct mmc {
+#ifndef CONFIG_BLK
struct list_head link;
+#endif
const struct mmc_config *cfg; /* provided configuration */
uint version;
void *priv;
u64 capacity_gp[4];
u64 enh_user_start;
u64 enh_user_size;
+#ifndef CONFIG_BLK
struct blk_desc block_dev;
+#endif
char op_cond_pending; /* 1 if we are waiting on an op_cond command */
char init_in_progress; /* 1 if we have done mmc_start_init() */
char preinit; /* start init as early as possible */
int ddr_mode;
+#ifdef CONFIG_DM_MMC
+ struct udevice *dev; /* Device for this MMC controller */
+#endif
};
struct mmc_hwpart_conf {
int mmc_register(struct mmc *mmc);
struct mmc *mmc_create(const struct mmc_config *cfg, void *priv);
+
+/**
+ * mmc_bind() - Set up a new MMC device ready for probing
+ *
+ * A child block device is bound with the IF_TYPE_MMC interface type. This
+ * allows the device to be used with CONFIG_BLK
+ *
+ * @dev: MMC device to set up
+ * @mmc: MMC struct
+ * @cfg: MMC configuration
+ * @return 0 if OK, -ve on error
+ */
+int mmc_bind(struct udevice *dev, struct mmc *mmc,
+ const struct mmc_config *cfg);
void mmc_destroy(struct mmc *mmc);
+
+/**
+ * mmc_unbind() - Unbind a MMC device's child block device
+ *
+ * @dev: MMC device
+ * @return 0 if OK, -ve on error
+ */
+int mmc_unbind(struct udevice *dev);
int mmc_initialize(bd_t *bis);
int mmc_init(struct mmc *mmc);
int mmc_read(struct mmc *mmc, u64 src, uchar *dst, int size);
int mmc_set_dev(int dev_num);
void print_mmc_devices(char separator);
int get_mmc_num(void);
-int mmc_switch_part(int dev_num, unsigned int part_num);
int mmc_hwpart_config(struct mmc *mmc, const struct mmc_hwpart_conf *conf,
enum mmc_hwpart_conf_mode mode);
int mmc_getcd(struct mmc *mmc);
#define CONFIG_SYS_MMC_MAX_BLK_COUNT 65535
#endif
+/**
+ * mmc_get_blk_desc() - Get the block descriptor for an MMC device
+ *
+ * @mmc: MMC device
+ * @return block device if found, else NULL
+ */
+struct blk_desc *mmc_get_blk_desc(struct mmc *mmc);
+
#endif /* _MMC_H_ */
return num;
}
-/*
- * Boards with mv88e61xx switch can use this by defining
- * CONFIG_MV88E61XX_SWITCH in respective board configheader file
- * the stuct and enums here are used to specify switch configuration params
- */
-#if defined(CONFIG_MV88E61XX_SWITCH)
-
-/* constants for any 88E61xx switch */
-#define MV88E61XX_MAX_PORTS_NUM 6
-
-enum mv88e61xx_cfg_mdip {
- MV88E61XX_MDIP_NOCHANGE,
- MV88E61XX_MDIP_REVERSE
-};
-
-enum mv88e61xx_cfg_ledinit {
- MV88E61XX_LED_INIT_DIS,
- MV88E61XX_LED_INIT_EN
-};
-
-enum mv88e61xx_cfg_rgmiid {
- MV88E61XX_RGMII_DELAY_DIS,
- MV88E61XX_RGMII_DELAY_EN
-};
-
-enum mv88e61xx_cfg_prtstt {
- MV88E61XX_PORTSTT_DISABLED,
- MV88E61XX_PORTSTT_BLOCKING,
- MV88E61XX_PORTSTT_LEARNING,
- MV88E61XX_PORTSTT_FORWARDING
-};
-
-struct mv88e61xx_config {
- char *name;
- u8 vlancfg[MV88E61XX_MAX_PORTS_NUM];
- enum mv88e61xx_cfg_rgmiid rgmii_delay;
- enum mv88e61xx_cfg_prtstt portstate;
- enum mv88e61xx_cfg_ledinit led_init;
- enum mv88e61xx_cfg_mdip mdip;
- u32 ports_enabled;
- u8 cpuport;
-};
-
-/*
- * Common mappings for Internal VLANs
- * These mappings consider that all ports are useable; the driver
- * will mask inexistent/unused ports.
- */
-
-/* Switch mode : routes any port to any port */
-#define MV88E61XX_VLANCFG_SWITCH { 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F }
-
-/* Router mode: routes only CPU port 5 to/from non-CPU ports 0-4 */
-#define MV88E61XX_VLANCFG_ROUTER { 0x20, 0x20, 0x20, 0x20, 0x20, 0x1F }
-
-int mv88e61xx_switch_initialize(struct mv88e61xx_config *swconfig);
-#endif /* CONFIG_MV88E61XX_SWITCH */
-
struct mii_dev *fec_get_miibus(uint32_t base_addr, int dev_id);
#ifdef CONFIG_PHYLIB
struct phy_device;
struct block_drvr {
char *name;
- struct blk_desc* (*get_dev)(int dev);
int (*select_hwpart)(int dev_num, int hwpart);
};
* error occurred.
*/
struct blk_desc *blk_get_dev(const char *ifname, int dev);
-struct blk_desc *ide_get_dev(int dev);
-struct blk_desc *sata_get_dev(int dev);
-struct blk_desc *scsi_get_dev(int dev);
-struct blk_desc *usb_stor_get_dev(int dev);
-struct blk_desc *mmc_get_dev(int dev);
-/**
- * mmc_select_hwpart() - Select the MMC hardware partiion on an MMC device
- *
- * MMC devices can support partitioning at the hardware level. This is quite
- * separate from the normal idea of software-based partitions. MMC hardware
- * partitions must be explicitly selected. Once selected only the region of
- * the device covered by that partition is accessible.
- *
- * The MMC standard provides for two boot partitions (numbered 1 and 2),
- * rpmb (3), and up to 4 addition general-purpose partitions (4-7).
- *
- * @dev_num: Block device number (struct blk_desc->dev value)
- * @hwpart: Hardware partition number to select. 0 means the raw device,
- * 1 is the first partition, 2 is the second, etc.
- * @return 0 if OK, other value for an error
- */
-int mmc_select_hwpart(int dev_num, int hwpart);
-struct blk_desc *systemace_get_dev(int dev);
struct blk_desc *mg_disk_get_dev(int dev);
-struct blk_desc *host_get_dev(int dev);
int host_get_dev_err(int dev, struct blk_desc **blk_devp);
/* disk/part.c */
#else
static inline struct blk_desc *blk_get_dev(const char *ifname, int dev)
{ return NULL; }
-static inline struct blk_desc *ide_get_dev(int dev) { return NULL; }
-static inline struct blk_desc *sata_get_dev(int dev) { return NULL; }
-static inline struct blk_desc *scsi_get_dev(int dev) { return NULL; }
-static inline struct blk_desc *usb_stor_get_dev(int dev) { return NULL; }
-static inline struct blk_desc *mmc_get_dev(int dev) { return NULL; }
-static inline int mmc_select_hwpart(int dev_num, int hwpart) { return -1; }
-static inline struct blk_desc *systemace_get_dev(int dev) { return NULL; }
static inline struct blk_desc *mg_disk_get_dev(int dev) { return NULL; }
-static inline struct blk_desc *host_get_dev(int dev) { return NULL; }
static inline int part_get_info(struct blk_desc *dev_desc, int part,
disk_partition_t *info) { return -1; }
int gen10g_shutdown(struct phy_device *phydev);
int gen10g_discover_mmds(struct phy_device *phydev);
+int phy_mv88e61xx_init(void);
int phy_aquantia_init(void);
int phy_atheros_init(void);
int phy_broadcom_init(void);
*/
int phy_get_interface_by_name(const char *str);
+/**
+ * phy_interface_is_rgmii - Convenience function for testing if a PHY interface
+ * is RGMII (all variants)
+ * @phydev: the phy_device struct
+ */
+static inline bool phy_interface_is_rgmii(struct phy_device *phydev)
+{
+ return phydev->interface >= PHY_INTERFACE_MODE_RGMII &&
+ phydev->interface <= PHY_INTERFACE_MODE_RGMII_TXID;
+}
+
+/**
+ * phy_interface_is_sgmii - Convenience function for testing if a PHY interface
+ * is SGMII (all variants)
+ * @phydev: the phy_device struct
+ */
+static inline bool phy_interface_is_sgmii(struct phy_device *phydev)
+{
+ return phydev->interface >= PHY_INTERFACE_MODE_SGMII &&
+ phydev->interface <= PHY_INTERFACE_MODE_QSGMII;
+}
+
/* PHY UIDs for various PHYs that are referenced in external code */
#define PHY_UID_CS4340 0x13e51002
#define PHY_UID_TN2020 0x00a19410
--- /dev/null
+/*
+ * (C) Copyright 2015 Miao Yan <yanmiaobest@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __FW_CFG__
+#define __FW_CFG__
+
+#include <linux/list.h>
+
+enum qemu_fwcfg_items {
+ FW_CFG_SIGNATURE = 0x00,
+ FW_CFG_ID = 0x01,
+ FW_CFG_UUID = 0x02,
+ FW_CFG_RAM_SIZE = 0x03,
+ FW_CFG_NOGRAPHIC = 0x04,
+ FW_CFG_NB_CPUS = 0x05,
+ FW_CFG_MACHINE_ID = 0x06,
+ FW_CFG_KERNEL_ADDR = 0x07,
+ FW_CFG_KERNEL_SIZE = 0x08,
+ FW_CFG_KERNEL_CMDLINE = 0x09,
+ FW_CFG_INITRD_ADDR = 0x0a,
+ FW_CFG_INITRD_SIZE = 0x0b,
+ FW_CFG_BOOT_DEVICE = 0x0c,
+ FW_CFG_NUMA = 0x0d,
+ FW_CFG_BOOT_MENU = 0x0e,
+ FW_CFG_MAX_CPUS = 0x0f,
+ FW_CFG_KERNEL_ENTRY = 0x10,
+ FW_CFG_KERNEL_DATA = 0x11,
+ FW_CFG_INITRD_DATA = 0x12,
+ FW_CFG_CMDLINE_ADDR = 0x13,
+ FW_CFG_CMDLINE_SIZE = 0x14,
+ FW_CFG_CMDLINE_DATA = 0x15,
+ FW_CFG_SETUP_ADDR = 0x16,
+ FW_CFG_SETUP_SIZE = 0x17,
+ FW_CFG_SETUP_DATA = 0x18,
+ FW_CFG_FILE_DIR = 0x19,
+ FW_CFG_FILE_FIRST = 0x20,
+ FW_CFG_WRITE_CHANNEL = 0x4000,
+ FW_CFG_ARCH_LOCAL = 0x8000,
+ FW_CFG_INVALID = 0xffff,
+};
+
+enum {
+ BIOS_LINKER_LOADER_COMMAND_ALLOCATE = 0x1,
+ BIOS_LINKER_LOADER_COMMAND_ADD_POINTER = 0x2,
+ BIOS_LINKER_LOADER_COMMAND_ADD_CHECKSUM = 0x3,
+};
+
+enum {
+ BIOS_LINKER_LOADER_ALLOC_ZONE_HIGH = 0x1,
+ BIOS_LINKER_LOADER_ALLOC_ZONE_FSEG = 0x2,
+};
+
+#define FW_CFG_FILE_SLOTS 0x10
+#define FW_CFG_MAX_ENTRY (FW_CFG_FILE_FIRST + FW_CFG_FILE_SLOTS)
+#define FW_CFG_ENTRY_MASK ~(FW_CFG_WRITE_CHANNEL | FW_CFG_ARCH_LOCAL)
+
+#define FW_CFG_MAX_FILE_PATH 56
+#define BIOS_LINKER_LOADER_FILESZ FW_CFG_MAX_FILE_PATH
+
+#define QEMU_FW_CFG_SIGNATURE (('Q' << 24) | ('E' << 16) | ('M' << 8) | 'U')
+
+#define FW_CFG_DMA_ERROR (1 << 0)
+#define FW_CFG_DMA_READ (1 << 1)
+#define FW_CFG_DMA_SKIP (1 << 2)
+#define FW_CFG_DMA_SELECT (1 << 3)
+
+#define FW_CFG_DMA_ENABLED (1 << 1)
+
+struct fw_cfg_file {
+ __be32 size;
+ __be16 select;
+ __be16 reserved;
+ char name[FW_CFG_MAX_FILE_PATH];
+};
+
+struct fw_file {
+ struct fw_cfg_file cfg; /* firmware file information */
+ unsigned long addr; /* firmware file in-memory address */
+ struct list_head list; /* list node to link to fw_list */
+};
+
+struct fw_cfg_file_iter {
+ struct list_head *entry; /* structure to iterate file list */
+};
+
+struct fw_cfg_dma_access {
+ __be32 control;
+ __be32 length;
+ __be64 address;
+};
+
+struct fw_cfg_arch_ops {
+ void (*arch_read_pio)(uint16_t selector, uint32_t size,
+ void *address);
+ void (*arch_read_dma)(struct fw_cfg_dma_access *dma);
+};
+
+struct bios_linker_entry {
+ __le32 command;
+ union {
+ /*
+ * COMMAND_ALLOCATE - allocate a table from @alloc.file
+ * subject to @alloc.align alignment (must be power of 2)
+ * and @alloc.zone (can be HIGH or FSEG) requirements.
+ *
+ * Must appear exactly once for each file, and before
+ * this file is referenced by any other command.
+ */
+ struct {
+ char file[BIOS_LINKER_LOADER_FILESZ];
+ __le32 align;
+ uint8_t zone;
+ } alloc;
+
+ /*
+ * COMMAND_ADD_POINTER - patch the table (originating from
+ * @dest_file) at @pointer.offset, by adding a pointer to the
+ * table originating from @src_file. 1,2,4 or 8 byte unsigned
+ * addition is used depending on @pointer.size.
+ */
+ struct {
+ char dest_file[BIOS_LINKER_LOADER_FILESZ];
+ char src_file[BIOS_LINKER_LOADER_FILESZ];
+ __le32 offset;
+ uint8_t size;
+ } pointer;
+
+ /*
+ * COMMAND_ADD_CHECKSUM - calculate checksum of the range
+ * specified by @cksum_start and @cksum_length fields,
+ * and then add the value at @cksum.offset.
+ * Checksum simply sums -X for each byte X in the range
+ * using 8-bit math.
+ */
+ struct {
+ char file[BIOS_LINKER_LOADER_FILESZ];
+ __le32 offset;
+ __le32 start;
+ __le32 length;
+ } cksum;
+
+ /* padding */
+ char pad[124];
+ };
+} __packed;
+
+/**
+ * Initialize QEMU fw_cfg interface
+ *
+ * @ops: arch specific read operations
+ */
+void qemu_fwcfg_init(struct fw_cfg_arch_ops *ops);
+
+void qemu_fwcfg_read_entry(uint16_t entry, uint32_t length, void *address);
+int qemu_fwcfg_read_firmware_list(void);
+struct fw_file *qemu_fwcfg_find_file(const char *name);
+
+/**
+ * Get system cpu number
+ *
+ * @return: cpu number in system
+ */
+int qemu_fwcfg_online_cpus(void);
+
+/* helper functions to iterate firmware file list */
+struct fw_file *qemu_fwcfg_file_iter_init(struct fw_cfg_file_iter *iter);
+struct fw_file *qemu_fwcfg_file_iter_next(struct fw_cfg_file_iter *iter);
+bool qemu_fwcfg_file_iter_end(struct fw_cfg_file_iter *iter);
+
+bool qemu_fwcfg_present(void);
+bool qemu_fwcfg_dma_present(void);
+
+#endif
struct udevice *bus, struct udevice *slave,
struct udevice **emulp);
+/**
+ * Claim the bus and prepare it for communication with a given slave.
+ *
+ * This must be called before doing any transfers with a SPI slave. It
+ * will enable and initialize any SPI hardware as necessary, and make
+ * sure that the SCK line is in the correct idle state. It is not
+ * allowed to claim the same bus for several slaves without releasing
+ * the bus in between.
+ *
+ * @dev: The SPI slave device
+ *
+ * Returns: 0 if the bus was claimed successfully, or a negative value
+ * if it wasn't.
+ */
+int dm_spi_claim_bus(struct udevice *dev);
+
+/**
+ * Release the SPI bus
+ *
+ * This must be called once for every call to dm_spi_claim_bus() after
+ * all transfers have finished. It may disable any SPI hardware as
+ * appropriate.
+ *
+ * @slave: The SPI slave device
+ */
+void dm_spi_release_bus(struct udevice *dev);
+
+/**
+ * SPI transfer
+ *
+ * This writes "bitlen" bits out the SPI MOSI port and simultaneously clocks
+ * "bitlen" bits in the SPI MISO port. That's just the way SPI works.
+ *
+ * The source of the outgoing bits is the "dout" parameter and the
+ * destination of the input bits is the "din" parameter. Note that "dout"
+ * and "din" can point to the same memory location, in which case the
+ * input data overwrites the output data (since both are buffered by
+ * temporary variables, this is OK).
+ *
+ * dm_spi_xfer() interface:
+ * @dev: The SPI slave device which will be sending/receiving the data.
+ * @bitlen: How many bits to write and read.
+ * @dout: Pointer to a string of bits to send out. The bits are
+ * held in a byte array and are sent MSB first.
+ * @din: Pointer to a string of bits that will be filled in.
+ * @flags: A bitwise combination of SPI_XFER_* flags.
+ *
+ * Returns: 0 on success, not 0 on failure
+ */
+int dm_spi_xfer(struct udevice *dev, unsigned int bitlen,
+ const void *dout, void *din, unsigned long flags);
+
/* Access the operations for a SPI device */
#define spi_get_ops(dev) ((struct dm_spi_ops *)(dev)->driver->ops)
#define spi_emul_get_ops(dev) ((struct dm_spi_emul_ops *)(dev)->driver->ops)
u32 spl_boot_device(void);
u32 spl_boot_mode(void);
void spl_set_header_raw_uboot(void);
-void spl_parse_image_header(const struct image_header *header);
+int spl_parse_image_header(const struct image_header *header);
void spl_board_prepare_for_linux(void);
+void spl_board_prepare_for_boot(void);
void __noreturn jump_to_image_linux(void *arg);
int spl_start_uboot(void);
void spl_display_print(void);
+++ /dev/null
-#ifndef __SYSTEMACE_H
-#define __SYSTEMACE_H
-/*
- * Copyright (c) 2004 Picture Elements, Inc.
- * Stephen Williams (steve@picturel.com)
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifdef CONFIG_SYSTEMACE
-
-# include <part.h>
-
-struct blk_desc *systemace_get_dev(int dev);
-
-#endif /* CONFIG_SYSTEMACE */
-#endif /* __SYSTEMACE_H */
#ifdef CONFIG_USB_STORAGE
#define USB_MAX_STOR_DEV 7
-struct blk_desc *usb_stor_get_dev(int index);
int usb_stor_scan(int mode);
int usb_stor_info(void);
*/
#include <common.h>
+#include <blk.h>
#include <efi_loader.h>
#include <inttypes.h>
#include <part.h>
};
static void efi_disk_add_dev(char *name,
- const struct block_drvr *cur_drvr,
+ const struct blk_driver *cur_drvr,
const struct blk_desc *desc,
int dev_index,
lbaint_t offset)
diskobj->parent.protocols[1].open = efi_disk_open_dp;
diskobj->parent.handle = diskobj;
diskobj->ops = block_io_disk_template;
- diskobj->ifname = cur_drvr->name;
+ diskobj->ifname = cur_drvr->if_typename;
diskobj->dev_index = dev_index;
diskobj->offset = offset;
}
static int efi_disk_create_eltorito(struct blk_desc *desc,
- const struct block_drvr *cur_drvr,
+ const struct blk_driver *cur_drvr,
int diskid)
{
int disks = 0;
return 0;
while (!part_get_info(desc, part, &info)) {
- snprintf(devname, sizeof(devname), "%s%d:%d", cur_drvr->name,
- diskid, part);
+ snprintf(devname, sizeof(devname), "%s%d:%d",
+ cur_drvr->if_typename, diskid, part);
efi_disk_add_dev(devname, cur_drvr, desc, diskid, info.start);
part++;
disks++;
*/
int efi_disk_register(void)
{
- const struct block_drvr *cur_drvr;
- int i;
+ const struct blk_driver *cur_drvr;
+ int i, if_type;
int disks = 0;
/* Search for all available disk devices */
- for (cur_drvr = block_drvr; cur_drvr->name; cur_drvr++) {
- printf("Scanning disks on %s...\n", cur_drvr->name);
+ for (if_type = 0; if_type < IF_TYPE_COUNT; if_type++) {
+ cur_drvr = blk_driver_lookup_type(if_type);
+ if (!cur_drvr)
+ continue;
+
+ printf("Scanning disks on %s...\n", cur_drvr->if_typename);
for (i = 0; i < 4; i++) {
struct blk_desc *desc;
char devname[32] = { 0 }; /* dp->str is u16[32] long */
- desc = blk_get_dev(cur_drvr->name, i);
+ desc = blk_get_devnum_by_type(if_type, i);
if (!desc)
continue;
if (desc->type == DEV_TYPE_UNKNOWN)
continue;
snprintf(devname, sizeof(devname), "%s%d",
- cur_drvr->name, i);
+ cur_drvr->if_typename, i);
efi_disk_add_dev(devname, cur_drvr, desc, i, 0);
disks++;
# ACPI
# ---------------------------------------------------------------------------
-quiet_cmd_acpi_c_asl= ASL $@
+quiet_cmd_acpi_c_asl= ASL $<
cmd_acpi_c_asl= \
- $(CPP) -x assembler-with-cpp -P -o $<.tmp $<; \
- iasl -p $< -tc -va $<.tmp; \
+ $(CPP) -x assembler-with-cpp -P $(UBOOTINCLUDE) -o $<.tmp $<; \
+ iasl -p $< -tc $<.tmp $(if $(KBUILD_VERBOSE:1=), >/dev/null); \
mv $(patsubst %.asl,%.hex,$<) $@
-$(obj)/%.c: $(src)/%.asl
+$(obj)/dsdt.c: $(src)/dsdt.asl
$(call cmd,acpi_c_asl)
# Bzip2
boot.bin: $(obj)/u-boot-spl.bin FORCE
$(call if_changed,mkimage)
else
+ifdef CONFIG_ARCH_ZYNQ
MKIMAGEFLAGS_boot.bin = -T zynqimage
+endif
+ifdef CONFIG_ARCH_ZYNQMP
+MKIMAGEFLAGS_boot.bin = -T zynqmpimage
+endif
spl/boot.bin: $(obj)/u-boot-spl.bin FORCE
$(call if_changed,mkimage)
ALL-y += $(obj)/boot.bin
endif
+ALL-(CONFIG_ARCH_ZYNQMP) += $(obj)/boot.bin
+
all: $(ALL-y)
quiet_cmd_cat = CAT $@
perror(filename);
exit(2);
}
- fstat(fd, &st);
+ if (fstat(fd, &st) < 0) {
+ fprintf(stderr, "fixdep: error fstat'ing config file: ");
+ perror(filename);
+ exit(2);
+ }
if (st.st_size == 0) {
close(fd);
return;
ut_asserteq_ptr(usb_dev, dev_get_parent(dev));
/* Check we have one block device for each mass storage device */
- ut_asserteq(3, count_blk_devices());
+ ut_asserteq(4, count_blk_devices());
/* Now go around again, making sure the old devices were unbound */
ut_assertok(usb_stop());
ut_assertok(usb_init());
- ut_asserteq(3, count_blk_devices());
+ ut_asserteq(4, count_blk_devices());
ut_assertok(usb_stop());
return 0;
return 0;
}
DM_TEST(dm_test_mmc_base, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+
+static int dm_test_mmc_blk(struct unit_test_state *uts)
+{
+ struct udevice *dev;
+ struct blk_desc *dev_desc;
+ char cmp[1024];
+
+ ut_assertok(uclass_get_device(UCLASS_MMC, 0, &dev));
+ ut_assertok(blk_get_device_by_str("mmc", "0", &dev_desc));
+
+ /* Read a few blocks and look for the string we expect */
+ ut_asserteq(512, dev_desc->blksz);
+ memset(cmp, '\0', sizeof(cmp));
+ ut_asserteq(2, blk_dread(dev_desc, 0, 2, cmp));
+ ut_assertok(strcmp(cmp, "this is a test"));
+
+ return 0;
+}
+DM_TEST(dm_test_mmc_blk, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
common/hash.o \
ublimage.o \
zynqimage.o \
+ zynqmpimage.o \
$(LIBFDT_OBJS) \
$(RSA_OBJS-y)
will build commits in us-buildman that are not in upstream/master.
+Building Faster
+===============
+
+By default, buildman executes 'make mrproper' prior to building the first
+commit for each board. This causes everything to be built from scratch. If you
+trust the build system's incremental build capabilities, you can pass the -I
+flag to skip the 'make mproper' invocation, which will reduce the amount of
+work 'make' does, and hence speed up the build. This flag will speed up any
+buildman invocation, since it reduces the amount of work done on any build.
+
+One possible application of buildman is as part of a continual edit, build,
+edit, build, ... cycle; repeatedly applying buildman to the same change or
+series of changes while making small incremental modifications to the source
+each time. This provides quick feedback regarding the correctness of recent
+modifications. In this scenario, buildman's default choice of build directory
+causes more build work to be performed than strictly necessary.
+
+By default, each buildman thread uses a single directory for all builds. When a
+thread builds multiple boards, the configuration built in this directory will
+cycle through various different configurations, one per board built by the
+thread. Variations in the configuration will force a rebuild of affected source
+files when a thread switches between boards. Ideally, such buildman-induced
+rebuilds would not happen, thus allowing the build to operate as efficiently as
+the build system and source changes allow. buildman's -P flag may be used to
+enable this; -P causes each board to be built in a separate (board-specific)
+directory, thus avoiding any buildman-induced configuration changes in any
+build directory.
+
+U-Boot's build system embeds information such as a build timestamp into the
+final binary. This information varies each time U-Boot is built. This causes
+various files to be rebuilt even if no source changes are made, which in turn
+requires that the final U-Boot binary be re-linked. This unnecessary work can
+be avoided by turning off the timestamp feature. This can be achieved by
+setting the SOURCE_DATE_EPOCH environment variable to 0.
+
+Combining all of these options together yields the command-line shown below.
+This will provide the quickest possible feedback regarding the current content
+of the source tree, thus allowing rapid tested evolution of the code.
+
+ SOURCE_DATE_EPOCH=0 ./tools/buildman/buildman -I -P tegra
+
+
Other options
=============
def __init__(self, toolchains, base_dir, git_dir, num_threads, num_jobs,
gnu_make='make', checkout=True, show_unknown=True, step=1,
- no_subdirs=False, full_path=False, verbose_build=False):
+ no_subdirs=False, full_path=False, verbose_build=False,
+ incremental=False, per_board_out_dir=False):
"""Create a new Builder object
Args:
full_path: Return the full path in CROSS_COMPILE and don't set
PATH
verbose_build: Run build with V=1 and don't use 'make -s'
+ incremental: Always perform incremental builds; don't run make
+ mrproper when configuring
+ per_board_out_dir: Build in a separate persistent directory per
+ board rather than a thread-specific directory
"""
self.toolchains = toolchains
self.base_dir = base_dir
self.queue = Queue.Queue()
self.out_queue = Queue.Queue()
for i in range(self.num_threads):
- t = builderthread.BuilderThread(self, i)
+ t = builderthread.BuilderThread(self, i, incremental,
+ per_board_out_dir)
t.setDaemon(True)
t.start()
self.threads.append(t)
thread_num: Our thread number (0-n-1), used to decide on a
temporary directory
"""
- def __init__(self, builder, thread_num):
+ def __init__(self, builder, thread_num, incremental, per_board_out_dir):
"""Set up a new builder thread"""
threading.Thread.__init__(self)
self.builder = builder
self.thread_num = thread_num
+ self.incremental = incremental
+ self.per_board_out_dir = per_board_out_dir
def Make(self, commit, brd, stage, cwd, *args, **kwargs):
"""Run 'make' on a particular commit and board.
if self.builder.in_tree:
out_dir = work_dir
else:
- out_dir = os.path.join(work_dir, 'build')
+ if self.per_board_out_dir:
+ out_rel_dir = os.path.join('..', brd.target)
+ else:
+ out_rel_dir = 'build'
+ out_dir = os.path.join(work_dir, out_rel_dir)
# Check if the job was already completed last time
done_file = self.builder.GetDoneFile(commit_upto, brd.target)
#
# Symlinks can confuse U-Boot's Makefile since
# we may use '..' in our path, so remove them.
- work_dir = os.path.realpath(work_dir)
- args.append('O=%s/build' % work_dir)
+ out_dir = os.path.realpath(out_dir)
+ args.append('O=%s' % out_dir)
cwd = None
src_dir = os.getcwd()
else:
- args.append('O=build')
+ args.append('O=%s' % out_rel_dir)
if self.builder.verbose_build:
args.append('V=1')
else:
# If we need to reconfigure, do that now
if do_config:
- result = self.Make(commit, brd, 'mrproper', cwd,
- 'mrproper', *args, env=env)
- config_out = result.combined
+ config_out = ''
+ if not self.incremental:
+ result = self.Make(commit, brd, 'mrproper', cwd,
+ 'mrproper', *args, env=env)
+ config_out += result.combined
result = self.Make(commit, brd, 'config', cwd,
*(args + config_args), env=env)
config_out += result.combined
parser.add_option('-i', '--in-tree', dest='in_tree',
action='store_true', default=False,
help='Build in the source tree instead of a separate directory')
+ parser.add_option('-I', '--incremental', action='store_true',
+ default=False, help='Do not run make mrproper (when reconfiguring)')
parser.add_option('-j', '--jobs', dest='jobs', type='int',
default=None, help='Number of jobs to run at once (passed to make)')
parser.add_option('-k', '--keep-outputs', action='store_true',
default=False, help='Do a rough build, with limited warning resolution')
parser.add_option('-p', '--full-path', action='store_true',
default=False, help="Use full toolchain path in CROSS_COMPILE")
+ parser.add_option('-P', '--per-board-out-dir', action='store_true',
+ default=False, help="Use an O= (output) directory per board rather than per thread")
parser.add_option('-s', '--summary', action='store_true',
default=False, help='Show a build summary')
parser.add_option('-S', '--show-sizes', action='store_true',
options.threads, options.jobs, gnu_make=gnu_make, checkout=True,
show_unknown=options.show_unknown, step=options.step,
no_subdirs=options.no_subdirs, full_path=options.full_path,
- verbose_build=options.verbose_build)
+ verbose_build=options.verbose_build,
+ incremental=options.incremental,
+ per_board_out_dir=options.per_board_out_dir,)
builder.force_config_on_failure = not options.quick
if make_func:
builder.do_make = make_func
* successful
*/
if ((*curr)->print_header) {
- (*curr)->print_header(ptr);
+ if (!params->quiet)
+ (*curr)->print_header(ptr);
} else {
fprintf(stderr,
"%s: print_header undefined for %s\n",
struct content_info *content_head; /* List of files to include */
struct content_info *content_tail;
bool external_data; /* Store data outside the FIT */
+ bool quiet; /* Don't output text in normal operation */
};
/*
d = d2;
d->write_dcd_command.tag = DCD_CHECK_DATA_COMMAND_TAG;
d->write_dcd_command.length = cpu_to_be16(4);
- d->write_dcd_command.param = DCD_CHECK_BITS_SET_PARAM;
+ d->write_dcd_command.param = DCD_CHECK_BITS_CLR_PARAM;
break;
default:
break;
int opt;
while ((opt = getopt(argc, argv,
- "a:A:b:cC:d:D:e:Ef:Fk:K:ln:O:rR:sT:vVx")) != -1) {
+ "a:A:b:cC:d:D:e:Ef:Fk:K:ln:O:rR:qsT:vVx")) != -1) {
switch (opt) {
case 'a':
params.addr = strtoull(optarg, &ptr, 16);
if (params.os < 0)
usage("Invalid operating system");
break;
+ case 'q':
+ params.quiet = 1;
+ break;
case 'r':
params.require_keys = 1;
break;
--- /dev/null
+/*
+ * Copyright (C) 2016 Michal Simek <michals@xilinx.com>
+ * Copyright (C) 2015 Nathan Rossi <nathan@nathanrossi.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * The following Boot Header format/structures and values are defined in the
+ * following documents:
+ * * ug1085 ZynqMP TRM (Chapter 9, Table 9-3)
+ *
+ * Expected Header Size = 0x9C0
+ * Forced as 'little' endian, 32-bit words
+ *
+ * 0x 0 - Interrupt table (8 words)
+ * ... (Default value = 0xeafffffe)
+ * 0x 1f
+ * 0x 20 - Width detection
+ * * DEFAULT_WIDTHDETECTION 0xaa995566
+ * 0x 24 - Image identifier
+ * * DEFAULT_IMAGEIDENTIFIER 0x584c4e58
+ * 0x 28 - Encryption
+ * * 0x00000000 - None
+ * * 0xa5c3c5a3 - eFuse
+ * * 0xa5c3c5a7 - obfuscated key in eFUSE
+ * * 0x3a5c3c5a - bbRam
+ * * 0xa35c7ca5 - obfuscated key in boot header
+ * 0x 2C - Image load
+ * 0x 30 - Image offset
+ * 0x 34 - PFW image length
+ * 0x 38 - Total PFW image length
+ * 0x 3C - Image length
+ * 0x 40 - Total image length
+ * 0x 44 - Image attributes
+ * 0x 48 - Header checksum
+ * 0x 4c - Obfuscated key
+ * ...
+ * 0x 68
+ * 0x 6c - Reserved
+ * 0x 70 - User defined
+ * ...
+ * 0x 9c
+ * 0x a0 - Secure header initialization vector
+ * ...
+ * 0x a8
+ * 0x ac - Obfuscated key initialization vector
+ * ...
+ * 0x b4
+ * 0x b8 - Register Initialization, 511 Address and Data word pairs
+ * * List is terminated with an address of 0xffffffff or
+ * ... * at the max number of entries
+ * 0x8b4
+ * 0x8b8 - Reserved
+ * ...
+ * 0x9bf
+ * 0x9c0 - Data/Image starts here or above
+ */
+
+#include "imagetool.h"
+#include "mkimage.h"
+#include <image.h>
+
+#define HEADER_INTERRUPT_DEFAULT (cpu_to_le32(0xeafffffe))
+#define HEADER_REGINIT_NULL (cpu_to_le32(0xffffffff))
+#define HEADER_WIDTHDETECTION (cpu_to_le32(0xaa995566))
+#define HEADER_IMAGEIDENTIFIER (cpu_to_le32(0x584c4e58))
+
+enum {
+ ENCRYPTION_EFUSE = 0xa5c3c5a3,
+ ENCRYPTION_OEFUSE = 0xa5c3c5a7,
+ ENCRYPTION_BBRAM = 0x3a5c3c5a,
+ ENCRYPTION_OBBRAM = 0xa35c7ca5,
+ ENCRYPTION_NONE = 0x0,
+};
+
+struct zynqmp_reginit {
+ uint32_t address;
+ uint32_t data;
+};
+
+#define HEADER_INTERRUPT_VECTORS 8
+#define HEADER_REGINITS 256
+
+struct zynqmp_header {
+ uint32_t interrupt_vectors[HEADER_INTERRUPT_VECTORS]; /* 0x0 */
+ uint32_t width_detection; /* 0x20 */
+ uint32_t image_identifier; /* 0x24 */
+ uint32_t encryption; /* 0x28 */
+ uint32_t image_load; /* 0x2c */
+ uint32_t image_offset; /* 0x30 */
+ uint32_t pfw_image_length; /* 0x34 */
+ uint32_t total_pfw_image_length; /* 0x38 */
+ uint32_t image_size; /* 0x3c */
+ uint32_t image_stored_size; /* 0x40 */
+ uint32_t image_attributes; /* 0x44 */
+ uint32_t checksum; /* 0x48 */
+ uint32_t __reserved1[27]; /* 0x4c */
+ struct zynqmp_reginit register_init[HEADER_REGINITS]; /* 0xb8 */
+ uint32_t __reserved4[66]; /* 0x9c0 */
+};
+
+static struct zynqmp_header zynqmpimage_header;
+
+static uint32_t zynqmpimage_checksum(struct zynqmp_header *ptr)
+{
+ uint32_t checksum = 0;
+
+ if (ptr == NULL)
+ return 0;
+
+ checksum += le32_to_cpu(ptr->width_detection);
+ checksum += le32_to_cpu(ptr->image_identifier);
+ checksum += le32_to_cpu(ptr->encryption);
+ checksum += le32_to_cpu(ptr->image_load);
+ checksum += le32_to_cpu(ptr->image_offset);
+ checksum += le32_to_cpu(ptr->pfw_image_length);
+ checksum += le32_to_cpu(ptr->total_pfw_image_length);
+ checksum += le32_to_cpu(ptr->image_size);
+ checksum += le32_to_cpu(ptr->image_stored_size);
+ checksum += le32_to_cpu(ptr->image_attributes);
+ checksum = ~checksum;
+
+ return cpu_to_le32(checksum);
+}
+
+static void zynqmpimage_default_header(struct zynqmp_header *ptr)
+{
+ int i;
+
+ if (ptr == NULL)
+ return;
+
+ ptr->width_detection = HEADER_WIDTHDETECTION;
+ ptr->image_attributes = 0x800;
+ ptr->image_identifier = HEADER_IMAGEIDENTIFIER;
+ ptr->encryption = cpu_to_le32(ENCRYPTION_NONE);
+
+ /* Setup not-supported/constant/reserved fields */
+ for (i = 0; i < HEADER_INTERRUPT_VECTORS; i++)
+ ptr->interrupt_vectors[i] = HEADER_INTERRUPT_DEFAULT;
+
+ for (i = 0; i < HEADER_REGINITS; i++) {
+ ptr->register_init[i].address = HEADER_REGINIT_NULL;
+ ptr->register_init[i].data = 0;
+ }
+
+ /*
+ * Certain reserved fields are required to be set to 0, ensure they are
+ * set as such.
+ */
+ ptr->pfw_image_length = 0x0;
+ ptr->total_pfw_image_length = 0x0;
+}
+
+/* mkimage glue functions */
+static int zynqmpimage_verify_header(unsigned char *ptr, int image_size,
+ struct image_tool_params *params)
+{
+ struct zynqmp_header *zynqhdr = (struct zynqmp_header *)ptr;
+
+ if (image_size < sizeof(struct zynqmp_header))
+ return -1;
+
+ if (zynqhdr->width_detection != HEADER_WIDTHDETECTION)
+ return -1;
+ if (zynqhdr->image_identifier != HEADER_IMAGEIDENTIFIER)
+ return -1;
+
+ if (zynqmpimage_checksum(zynqhdr) != zynqhdr->checksum)
+ return -1;
+
+ return 0;
+}
+
+static void zynqmpimage_print_header(const void *ptr)
+{
+ struct zynqmp_header *zynqhdr = (struct zynqmp_header *)ptr;
+ int i;
+
+ printf("Image Type : Xilinx Zynq Boot Image support\n");
+ printf("Image Offset : 0x%08x\n", le32_to_cpu(zynqhdr->image_offset));
+ printf("Image Size : %lu bytes (%lu bytes packed)\n",
+ (unsigned long)le32_to_cpu(zynqhdr->image_size),
+ (unsigned long)le32_to_cpu(zynqhdr->image_stored_size));
+ printf("Image Load : 0x%08x\n", le32_to_cpu(zynqhdr->image_load));
+ printf("Checksum : 0x%08x\n", le32_to_cpu(zynqhdr->checksum));
+
+ for (i = 0; i < HEADER_INTERRUPT_VECTORS; i++) {
+ if (zynqhdr->interrupt_vectors[i] == HEADER_INTERRUPT_DEFAULT)
+ continue;
+
+ printf("Modified Interrupt Vector Address [%d]: 0x%08x\n", i,
+ le32_to_cpu(zynqhdr->interrupt_vectors[i]));
+ }
+
+ for (i = 0; i < HEADER_REGINITS; i++) {
+ if (zynqhdr->register_init[i].address == HEADER_REGINIT_NULL)
+ break;
+
+ if (i == 0)
+ printf("Custom Register Initialization:\n");
+
+ printf(" @ 0x%08x -> 0x%08x\n",
+ le32_to_cpu(zynqhdr->register_init[i].address),
+ le32_to_cpu(zynqhdr->register_init[i].data));
+ }
+}
+
+static int zynqmpimage_check_params(struct image_tool_params *params)
+{
+ if (!params)
+ return 0;
+
+ if (params->addr != 0x0) {
+ fprintf(stderr, "Error: Load Address cannot be specified.\n");
+ return -1;
+ }
+
+ /*
+ * If the entry point is specified ensure it is 64 byte aligned.
+ */
+ if (params->eflag && (params->ep % 64 != 0)) {
+ fprintf(stderr,
+ "Error: Entry Point must be aligned to a 64-byte boundary.\n");
+ return -1;
+ }
+
+ return !(params->lflag || params->dflag);
+}
+
+static int zynqmpimage_check_image_types(uint8_t type)
+{
+ if (type == IH_TYPE_ZYNQMPIMAGE)
+ return EXIT_SUCCESS;
+ return EXIT_FAILURE;
+}
+
+static void zynqmpimage_set_header(void *ptr, struct stat *sbuf, int ifd,
+ struct image_tool_params *params)
+{
+ struct zynqmp_header *zynqhdr = (struct zynqmp_header *)ptr;
+ zynqmpimage_default_header(zynqhdr);
+
+ /* place image directly after header */
+ zynqhdr->image_offset =
+ cpu_to_le32((uint32_t)sizeof(struct zynqmp_header));
+ zynqhdr->image_size = cpu_to_le32(params->file_size -
+ sizeof(struct zynqmp_header));
+ zynqhdr->image_stored_size = zynqhdr->image_size;
+ zynqhdr->image_load = 0xfffc0000;
+ if (params->eflag)
+ zynqhdr->image_load = cpu_to_le32((uint32_t)params->ep);
+
+ zynqhdr->checksum = zynqmpimage_checksum(zynqhdr);
+}
+
+U_BOOT_IMAGE_TYPE(
+ zynqmpimage,
+ "Xilinx ZynqMP Boot Image support",
+ sizeof(struct zynqmp_header),
+ (void *)&zynqmpimage_header,
+ zynqmpimage_check_params,
+ zynqmpimage_verify_header,
+ zynqmpimage_print_header,
+ zynqmpimage_set_header,
+ NULL,
+ zynqmpimage_check_image_types,
+ NULL,
+ NULL
+);
projects / oweals / u-boot.git / commitdiff