The actual board name is draco and dxr2 is the target name.
In the future we'll have different targets based on draco board.
All changes are purely non-functional and basically rename dxr2
to draco.
One style fix in board.c that existed already before.
Signed-off-by: Samuel Egli <samuel.egli@siemens.com>
Reviewed-by: Roger Meier <r.meier@siemens.com>
Cc: Heiko Schocher <hs@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
--- /dev/null
+#
+# Makefile
+#
+# (C) Copyright 2013 Siemens Schweiz AG
+# (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
+#
+# Based on:
+# u-boot:/board/ti/am335x/Makefile
+# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+ifdef CONFIG_SPL_BUILD
+obj-y := mux.o
+endif
+
+obj-y += board.o
+ifndef CONFIG_SPL_BUILD
+obj-y += ../common/factoryset.o
+endif
--- /dev/null
+/*
+ * Board functions for TI AM335X based draco board
+ * (C) Copyright 2013 Siemens Schweiz AG
+ * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Based on:
+ *
+ * Board functions for TI AM335X based boards
+ * u-boot:/board/ti/am335x/board.c
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <spl.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/omap.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/io.h>
+#include <asm/emif.h>
+#include <asm/gpio.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <cpsw.h>
+#include <watchdog.h>
+#include "board.h"
+#include "../common/factoryset.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_SPL_BUILD
+static struct draco_baseboard_id __attribute__((section(".data"))) settings;
+
+#if DDR_PLL_FREQ == 303
+/* Default@303MHz-i0 */
+const struct ddr3_data ddr3_default = {
+ 0x33524444, 0x56312e35, 0x0080, 0x0000, 0x003A, 0x003F, 0x009F,
+ 0x0079, 0x0888A39B, 0x26247FDA, 0x501F821F, 0x00100206, 0x61A44A32,
+ 0x0000093B, 0x0000014A,
+ "default name @303MHz \0",
+ "default marking \0",
+};
+#elif DDR_PLL_FREQ == 400
+/* Default@400MHz-i0 */
+const struct ddr3_data ddr3_default = {
+ 0x33524444, 0x56312e35, 0x0080, 0x0000, 0x0039, 0x0046, 0x00ab,
+ 0x0080, 0x0AAAA4DB, 0x26307FDA, 0x501F821F, 0x00100207, 0x61A45232,
+ 0x00000618, 0x0000014A,
+ "default name @400MHz \0",
+ "default marking \0",
+};
+#endif
+
+static void set_default_ddr3_timings(void)
+{
+ printf("Set default DDR3 settings\n");
+ settings.ddr3 = ddr3_default;
+}
+
+static void print_ddr3_timings(void)
+{
+ printf("\nDDR3\n");
+ printf("clock:\t\t%d MHz\n", DDR_PLL_FREQ);
+ printf("device:\t\t%s\n", settings.ddr3.manu_name);
+ printf("marking:\t%s\n", settings.ddr3.manu_marking);
+ printf("timing parameters\n");
+ printf("diff\teeprom\tdefault\n");
+ PRINTARGS(magic);
+ PRINTARGS(version);
+ PRINTARGS(ddr3_sratio);
+ PRINTARGS(iclkout);
+
+ PRINTARGS(dt0rdsratio0);
+ PRINTARGS(dt0wdsratio0);
+ PRINTARGS(dt0fwsratio0);
+ PRINTARGS(dt0wrsratio0);
+
+ PRINTARGS(sdram_tim1);
+ PRINTARGS(sdram_tim2);
+ PRINTARGS(sdram_tim3);
+
+ PRINTARGS(emif_ddr_phy_ctlr_1);
+
+ PRINTARGS(sdram_config);
+ PRINTARGS(ref_ctrl);
+ PRINTARGS(ioctr_val);
+}
+
+static void print_chip_data(void)
+{
+ printf("\nCPU BOARD\n");
+ printf("device: \t'%s'\n", settings.chip.sdevname);
+ printf("hw version: \t'%s'\n", settings.chip.shwver);
+}
+#endif /* CONFIG_SPL_BUILD */
+
+/*
+ * Read header information from EEPROM into global structure.
+ */
+static int read_eeprom(void)
+{
+ /* Check if baseboard eeprom is available */
+ if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
+ printf("Could not probe the EEPROM; something fundamentally wrong on the I2C bus.\n");
+ return 1;
+ }
+
+#ifdef CONFIG_SPL_BUILD
+ /* Read Siemens eeprom data (DDR3) */
+ if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, EEPROM_ADDR_DDR3, 2,
+ (uchar *)&settings.ddr3, sizeof(struct ddr3_data))) {
+ printf("Could not read the EEPROM; something fundamentally wrong on the I2C bus.\nUse default DDR3 timings\n");
+ set_default_ddr3_timings();
+ }
+ /* Read Siemens eeprom data (CHIP) */
+ if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, EEPROM_ADDR_CHIP, 2,
+ (uchar *)&settings.chip, sizeof(settings.chip)))
+ printf("Could not read chip settings\n");
+
+ if (ddr3_default.magic == settings.ddr3.magic &&
+ ddr3_default.version == settings.ddr3.version) {
+ printf("Using DDR3 settings from EEPROM\n");
+ } else {
+ if (ddr3_default.magic != settings.ddr3.magic)
+ printf("Warning: No valid DDR3 data in eeprom.\n");
+ if (ddr3_default.version != settings.ddr3.version)
+ printf("Warning: DDR3 data version does not match.\n");
+
+ printf("Using default settings\n");
+ set_default_ddr3_timings();
+ }
+
+ if (MAGIC_CHIP == settings.chip.magic)
+ print_chip_data();
+ else
+ printf("Warning: No chip data in eeprom\n");
+
+ print_ddr3_timings();
+#endif
+ return 0;
+}
+
+#ifdef CONFIG_SPL_BUILD
+static void board_init_ddr(void)
+{
+struct emif_regs draco_ddr3_emif_reg_data = {
+ .zq_config = 0x50074BE4,
+};
+
+struct ddr_data draco_ddr3_data = {
+};
+
+struct cmd_control draco_ddr3_cmd_ctrl_data = {
+};
+
+struct ctrl_ioregs draco_ddr3_ioregs = {
+};
+
+ /* pass values from eeprom */
+ draco_ddr3_emif_reg_data.sdram_tim1 = settings.ddr3.sdram_tim1;
+ draco_ddr3_emif_reg_data.sdram_tim2 = settings.ddr3.sdram_tim2;
+ draco_ddr3_emif_reg_data.sdram_tim3 = settings.ddr3.sdram_tim3;
+ draco_ddr3_emif_reg_data.emif_ddr_phy_ctlr_1 =
+ settings.ddr3.emif_ddr_phy_ctlr_1;
+ draco_ddr3_emif_reg_data.sdram_config = settings.ddr3.sdram_config;
+ draco_ddr3_emif_reg_data.ref_ctrl = settings.ddr3.ref_ctrl;
+
+ draco_ddr3_data.datardsratio0 = settings.ddr3.dt0rdsratio0;
+ draco_ddr3_data.datawdsratio0 = settings.ddr3.dt0wdsratio0;
+ draco_ddr3_data.datafwsratio0 = settings.ddr3.dt0fwsratio0;
+ draco_ddr3_data.datawrsratio0 = settings.ddr3.dt0wrsratio0;
+
+ draco_ddr3_cmd_ctrl_data.cmd0csratio = settings.ddr3.ddr3_sratio;
+ draco_ddr3_cmd_ctrl_data.cmd0iclkout = settings.ddr3.iclkout;
+ draco_ddr3_cmd_ctrl_data.cmd1csratio = settings.ddr3.ddr3_sratio;
+ draco_ddr3_cmd_ctrl_data.cmd1iclkout = settings.ddr3.iclkout;
+ draco_ddr3_cmd_ctrl_data.cmd2csratio = settings.ddr3.ddr3_sratio;
+ draco_ddr3_cmd_ctrl_data.cmd2iclkout = settings.ddr3.iclkout;
+
+ draco_ddr3_ioregs.cm0ioctl = settings.ddr3.ioctr_val,
+ draco_ddr3_ioregs.cm1ioctl = settings.ddr3.ioctr_val,
+ draco_ddr3_ioregs.cm2ioctl = settings.ddr3.ioctr_val,
+ draco_ddr3_ioregs.dt0ioctl = settings.ddr3.ioctr_val,
+ draco_ddr3_ioregs.dt1ioctl = settings.ddr3.ioctr_val,
+
+ config_ddr(DDR_PLL_FREQ, &draco_ddr3_ioregs, &draco_ddr3_data,
+ &draco_ddr3_cmd_ctrl_data, &draco_ddr3_emif_reg_data, 0);
+}
+
+static void spl_siemens_board_init(void)
+{
+ return;
+}
+#endif /* if def CONFIG_SPL_BUILD */
+
+#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
+ (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
+static void cpsw_control(int enabled)
+{
+ /* VTP can be added here */
+
+ return;
+}
+
+static struct cpsw_slave_data cpsw_slaves[] = {
+ {
+ .slave_reg_ofs = 0x208,
+ .sliver_reg_ofs = 0xd80,
+ .phy_addr = 0,
+ .phy_if = PHY_INTERFACE_MODE_MII,
+ },
+};
+
+static struct cpsw_platform_data cpsw_data = {
+ .mdio_base = CPSW_MDIO_BASE,
+ .cpsw_base = CPSW_BASE,
+ .mdio_div = 0xff,
+ .channels = 4,
+ .cpdma_reg_ofs = 0x800,
+ .slaves = 1,
+ .slave_data = cpsw_slaves,
+ .ale_reg_ofs = 0xd00,
+ .ale_entries = 1024,
+ .host_port_reg_ofs = 0x108,
+ .hw_stats_reg_ofs = 0x900,
+ .bd_ram_ofs = 0x2000,
+ .mac_control = (1 << 5),
+ .control = cpsw_control,
+ .host_port_num = 0,
+ .version = CPSW_CTRL_VERSION_2,
+};
+
+#if defined(CONFIG_DRIVER_TI_CPSW) || \
+ (defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET))
+int board_eth_init(bd_t *bis)
+{
+ struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+ int n = 0;
+ int rv;
+
+ factoryset_setenv();
+
+ /* Set rgmii mode and enable rmii clock to be sourced from chip */
+ writel((RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE), &cdev->miisel);
+
+ rv = cpsw_register(&cpsw_data);
+ if (rv < 0)
+ printf("Error %d registering CPSW switch\n", rv);
+ else
+ n += rv;
+ return n;
+}
+
+static int do_switch_reset(cmd_tbl_t *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ /* Reset SMSC LAN9303 switch for default configuration */
+ gpio_request(GPIO_LAN9303_NRST, "nRST");
+ gpio_direction_output(GPIO_LAN9303_NRST, 0);
+ /* assert active low reset for 200us */
+ udelay(200);
+ gpio_set_value(GPIO_LAN9303_NRST, 1);
+
+ return 0;
+};
+
+U_BOOT_CMD(
+ switch_rst, CONFIG_SYS_MAXARGS, 1, do_switch_reset,
+ "Reset LAN9303 switch via its reset pin",
+ ""
+);
+#endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */
+#endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */
+
+#include "../common/board.c"
--- /dev/null
+/*
+ * board.h
+ *
+ * (C) Copyright 2013 Siemens Schweiz AG
+ * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Based on:
+ * TI AM335x boards information header
+ * u-boot:/board/ti/am335x/board.h
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+#define PARGS3(x) settings.ddr3.x-ddr3_default.x, \
+ settings.ddr3.x, ddr3_default.x
+#define PRINTARGS(y) printf("%x, %8x, %8x : "#y"\n", PARGS3(y))
+#define MAGIC_CHIP 0x50494843
+
+/* Automatic generated definition */
+/* Wed, 16 Apr 2014 16:50:41 +0200 */
+/* From file: draco/ddr3-data-universal-default@303MHz-i0-ES3.txt */
+struct ddr3_data {
+ unsigned int magic; /* 0x33524444 */
+ unsigned int version; /* 0x56312e35 */
+ unsigned short int ddr3_sratio; /* 0x0080 */
+ unsigned short int iclkout; /* 0x0000 */
+ unsigned short int dt0rdsratio0; /* 0x003A */
+ unsigned short int dt0wdsratio0; /* 0x003F */
+ unsigned short int dt0fwsratio0; /* 0x009F */
+ unsigned short int dt0wrsratio0; /* 0x0079 */
+ unsigned int sdram_tim1; /* 0x0888A39B */
+ unsigned int sdram_tim2; /* 0x26247FDA */
+ unsigned int sdram_tim3; /* 0x501F821F */
+ unsigned int emif_ddr_phy_ctlr_1; /* 0x00100206 */
+ unsigned int sdram_config; /* 0x61A44A32 */
+ unsigned int ref_ctrl; /* 0x0000093B */
+ unsigned int ioctr_val; /* 0x0000014A */
+ char manu_name[32]; /* "default@303MHz \0" */
+ char manu_marking[32]; /* "default \0" */
+};
+
+struct chip_data {
+ unsigned int magic;
+ char sdevname[16];
+ char shwver[7];
+};
+
+struct draco_baseboard_id {
+ struct ddr3_data ddr3;
+ struct chip_data chip;
+};
+
+/*
+ * We have three pin mux functions that must exist. We must be able to enable
+ * uart0, for initial output and i2c0 to read the main EEPROM. We then have a
+ * main pinmux function that can be overridden to enable all other pinmux that
+ * is required on the board.
+ */
+void enable_uart0_pin_mux(void);
+void enable_uart1_pin_mux(void);
+void enable_uart2_pin_mux(void);
+void enable_uart3_pin_mux(void);
+void enable_uart4_pin_mux(void);
+void enable_uart5_pin_mux(void);
+void enable_i2c0_pin_mux(void);
+void enable_board_pin_mux(void);
+#endif
--- /dev/null
+/*
+ * pinmux setup for siemens draco board
+ *
+ * (C) Copyright 2013 Siemens Schweiz AG
+ * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Based on:
+ * u-boot:/board/ti/am335x/mux.c
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/mux.h>
+#include <asm/io.h>
+#include <i2c.h>
+#include "board.h"
+
+static struct module_pin_mux uart0_pin_mux[] = {
+ {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
+ {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
+ {-1},
+};
+
+static struct module_pin_mux uart3_pin_mux[] = {
+ {OFFSET(spi0_cs1), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART3_RXD */
+ {OFFSET(ecap0_in_pwm0_out), (MODE(1) | PULLUDEN)}, /* UART3_TXD */
+ {-1},
+};
+
+static struct module_pin_mux i2c0_pin_mux[] = {
+ {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
+ PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
+ {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
+ PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
+ {-1},
+};
+
+static struct module_pin_mux nand_pin_mux[] = {
+ {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */
+ {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */
+ {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */
+ {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */
+ {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */
+ {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */
+ {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */
+ {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */
+ {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
+ {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */
+ {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */
+ {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */
+ {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */
+ {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */
+ {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */
+ {-1},
+};
+
+static struct module_pin_mux gpios_pin_mux[] = {
+ /* DFU button GPIO0_27*/
+ {OFFSET(gpmc_ad11), (MODE(7) | PULLUDEN | RXACTIVE)},
+ {OFFSET(gpmc_csn3), MODE(7) }, /* LED0 GPIO2_0 */
+ {OFFSET(emu0), MODE(7)}, /* LED1 GPIO3_7 */
+ /* Triacs in HW Rev 2 */
+ {OFFSET(uart1_ctsn), MODE(7) | PULLUDDIS | RXACTIVE}, /* Y5 GPIO0_12*/
+ {OFFSET(mmc0_dat1), MODE(7) | PULLUDDIS | RXACTIVE}, /* Y3 GPIO2_28*/
+ {OFFSET(mmc0_dat2), MODE(7) | PULLUDDIS | RXACTIVE}, /* Y7 GPIO2_27*/
+ /* Triacs initial HW Rev */
+ {OFFSET(gpmc_csn1), MODE(7) | RXACTIVE | PULLUDDIS}, /* 1_30 Y0 */
+ {OFFSET(gpmc_be1n), MODE(7) | RXACTIVE | PULLUDDIS}, /* 1_28 Y1 */
+ {OFFSET(gpmc_csn2), MODE(7) | RXACTIVE | PULLUDDIS}, /* 1_31 Y2 */
+ {OFFSET(lcd_data15), MODE(7) | RXACTIVE | PULLUDDIS}, /* 0_11 Y3 */
+ {OFFSET(lcd_data14), MODE(7) | RXACTIVE | PULLUDDIS}, /* 0_10 Y4 */
+ {OFFSET(gpmc_clk), MODE(7) | RXACTIVE | PULLUDDIS}, /* 2_1 Y5 */
+ {OFFSET(emu1), MODE(7) | RXACTIVE | PULLUDDIS}, /* 3_8 Y6 */
+ {OFFSET(gpmc_ad15), MODE(7) | RXACTIVE | PULLUDDIS}, /* 1_15 Y7 */
+ /* Remaining pins that were not used in this file */
+ {OFFSET(gpmc_ad8), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(gpmc_ad9), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(gpmc_a0), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(gpmc_a1), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(gpmc_a2), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(gpmc_a3), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(gpmc_a4), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(gpmc_a5), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(gpmc_a6), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(gpmc_a7), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(gpmc_a8), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(gpmc_a9), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(gpmc_a10), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(gpmc_a11), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(lcd_data0), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(lcd_data2), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(lcd_data3), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(lcd_data4), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(lcd_data5), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(lcd_data6), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(lcd_data7), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(lcd_data8), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(lcd_data9), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(lcd_vsync), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(lcd_hsync), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(lcd_pclk), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(lcd_ac_bias_en), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(mmc0_dat3), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(mmc0_dat0), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(mmc0_clk), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(mmc0_cmd), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(spi0_sclk), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(spi0_d0), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(spi0_d1), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(spi0_cs0), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(uart0_ctsn), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(uart0_rtsn), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(uart1_rtsn), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(uart1_rxd), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(uart1_txd), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(mcasp0_aclkx), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(mcasp0_fsx), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(mcasp0_axr0), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(mcasp0_ahclkr), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(mcasp0_aclkr), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(mcasp0_fsr), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(mcasp0_axr1), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(mcasp0_ahclkx), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(xdma_event_intr0), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(xdma_event_intr1), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(nresetin_out), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(porz), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(nnmi), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(osc0_in), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(osc0_out), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(rsvd1), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(tms), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(tdi), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(tdo), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(tck), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ntrst), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(osc1_in), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(osc1_out), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(pmic_power_en), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(rtc_porz), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(rsvd2), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ext_wakeup), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(enz_kaldo_1p8v), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(usb0_dm), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(usb0_dp), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(usb0_ce), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(usb0_id), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(usb0_vbus), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(usb0_drvvbus), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(usb1_dm), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(usb1_dp), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(usb1_ce), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(usb1_id), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(usb1_vbus), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(usb1_drvvbus), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_resetn), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_csn0), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_cke), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_ck), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_nck), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_casn), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_rasn), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_wen), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_ba0), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_ba1), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_ba2), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_a0), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_a1), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_a2), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_a3), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_a4), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_a5), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_a6), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_a7), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_a8), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_a9), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_a10), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_a11), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_a12), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_a13), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_a14), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_a15), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_odt), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_d0), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_d1), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_d2), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_d3), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_d4), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_d5), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_d6), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_d7), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_d8), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_d9), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_d10), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_d11), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_d12), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_d13), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_d14), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_d15), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_dqm0), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_dqm1), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_dqs0), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_dqsn0), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_dqs1), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_dqsn1), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_vref), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_vtp), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_strben0), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_strben1), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ain7), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ain6), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ain5), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ain4), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ain3), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ain2), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ain1), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ain0), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(vrefp), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(vrefn), MODE(7) | RXACTIVE | PULLUDDIS},
+ /* nRST for SMSC LAN9303 switch - GPIO2_24 */
+ {OFFSET(lcd_pclk), MODE(7) }, /* LAN9303 nRST */
+ {-1},
+};
+
+static struct module_pin_mux ethernet_pin_mux[] = {
+ {OFFSET(mii1_col), (MODE(3) | RXACTIVE)},
+ {OFFSET(mii1_crs), (MODE(1) | RXACTIVE)},
+ {OFFSET(mii1_rxerr), (MODE(1) | RXACTIVE)},
+ {OFFSET(mii1_txen), (MODE(1))},
+ {OFFSET(mii1_rxdv), (MODE(3) | RXACTIVE)},
+ {OFFSET(mii1_txd3), (MODE(7) | RXACTIVE)},
+ {OFFSET(mii1_txd2), (MODE(7) | RXACTIVE)},
+ {OFFSET(mii1_txd1), (MODE(1))},
+ {OFFSET(mii1_txd0), (MODE(1))},
+ {OFFSET(mii1_txclk), (MODE(1) | RXACTIVE)},
+ {OFFSET(mii1_rxclk), (MODE(1) | RXACTIVE)},
+ {OFFSET(mii1_rxd3), (MODE(1) | RXACTIVE)},
+ {OFFSET(mii1_rxd2), (MODE(1))},
+ {OFFSET(mii1_rxd1), (MODE(1) | RXACTIVE)},
+ {OFFSET(mii1_rxd0), (MODE(1) | RXACTIVE)},
+ {OFFSET(rmii1_refclk), (MODE(0) | RXACTIVE)},
+ {OFFSET(mdio_data), (MODE(0) | RXACTIVE | PULLUP_EN)},
+ {OFFSET(mdio_clk), (MODE(0) | PULLUP_EN)},
+ {-1},
+};
+
+void enable_uart0_pin_mux(void)
+{
+ configure_module_pin_mux(uart0_pin_mux);
+}
+
+void enable_uart3_pin_mux(void)
+{
+ configure_module_pin_mux(uart3_pin_mux);
+}
+
+void enable_i2c0_pin_mux(void)
+{
+ configure_module_pin_mux(i2c0_pin_mux);
+}
+
+void enable_board_pin_mux(void)
+{
+ enable_uart3_pin_mux();
+ configure_module_pin_mux(nand_pin_mux);
+ configure_module_pin_mux(ethernet_pin_mux);
+ configure_module_pin_mux(gpios_pin_mux);
+}
+++ /dev/null
-#
-# Makefile
-#
-# (C) Copyright 2013 Siemens Schweiz AG
-# (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
-#
-# Based on:
-# u-boot:/board/ti/am335x/Makefile
-# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-ifdef CONFIG_SPL_BUILD
-obj-y := mux.o
-endif
-
-obj-y += board.o
-ifndef CONFIG_SPL_BUILD
-obj-y += ../common/factoryset.o
-endif
+++ /dev/null
-/*
- * Board functions for TI AM335X based dxr2 board
- * (C) Copyright 2013 Siemens Schweiz AG
- * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
- *
- * Based on:
- *
- * Board functions for TI AM335X based boards
- * u-boot:/board/ti/am335x/board.c
- *
- * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <errno.h>
-#include <spl.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/omap.h>
-#include <asm/arch/ddr_defs.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/mmc_host_def.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/io.h>
-#include <asm/emif.h>
-#include <asm/gpio.h>
-#include <i2c.h>
-#include <miiphy.h>
-#include <cpsw.h>
-#include <watchdog.h>
-#include "board.h"
-#include "../common/factoryset.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifdef CONFIG_SPL_BUILD
-static struct dxr2_baseboard_id __attribute__((section(".data"))) settings;
-
-#if DDR_PLL_FREQ == 303
-/* Default@303MHz-i0 */
-const struct ddr3_data ddr3_default = {
- 0x33524444, 0x56312e35, 0x0080, 0x0000, 0x003A, 0x003F, 0x009F,
- 0x0079, 0x0888A39B, 0x26247FDA, 0x501F821F, 0x00100206, 0x61A44A32,
- 0x0000093B, 0x0000014A,
- "default name @303MHz \0",
- "default marking \0",
-};
-#elif DDR_PLL_FREQ == 400
-/* Default@400MHz-i0 */
-const struct ddr3_data ddr3_default = {
- 0x33524444, 0x56312e35, 0x0080, 0x0000, 0x0039, 0x0046, 0x00ab,
- 0x0080, 0x0AAAA4DB, 0x26307FDA, 0x501F821F, 0x00100207, 0x61A45232,
- 0x00000618, 0x0000014A,
- "default name @400MHz \0",
- "default marking \0",
-};
-#endif
-
-static void set_default_ddr3_timings(void)
-{
- printf("Set default DDR3 settings\n");
- settings.ddr3 = ddr3_default;
-}
-
-static void print_ddr3_timings(void)
-{
- printf("\nDDR3\n");
- printf("clock:\t\t%d MHz\n", DDR_PLL_FREQ);
- printf("device:\t\t%s\n", settings.ddr3.manu_name);
- printf("marking:\t%s\n", settings.ddr3.manu_marking);
- printf("timing parameters\n");
- printf("diff\teeprom\tdefault\n");
- PRINTARGS(magic);
- PRINTARGS(version);
- PRINTARGS(ddr3_sratio);
- PRINTARGS(iclkout);
-
- PRINTARGS(dt0rdsratio0);
- PRINTARGS(dt0wdsratio0);
- PRINTARGS(dt0fwsratio0);
- PRINTARGS(dt0wrsratio0);
-
- PRINTARGS(sdram_tim1);
- PRINTARGS(sdram_tim2);
- PRINTARGS(sdram_tim3);
-
- PRINTARGS(emif_ddr_phy_ctlr_1);
-
- PRINTARGS(sdram_config);
- PRINTARGS(ref_ctrl);
- PRINTARGS(ioctr_val);
-}
-
-static void print_chip_data(void)
-{
- printf("\nCPU BOARD\n");
- printf("device: \t'%s'\n", settings.chip.sdevname);
- printf("hw version: \t'%s'\n", settings.chip.shwver);
-}
-#endif /* CONFIG_SPL_BUILD */
-
-/*
- * Read header information from EEPROM into global structure.
- */
-static int read_eeprom(void)
-{
- /* Check if baseboard eeprom is available */
- if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
- printf("Could not probe the EEPROM; something fundamentally wrong on the I2C bus.\n");
- return 1;
- }
-
-#ifdef CONFIG_SPL_BUILD
- /* Read Siemens eeprom data (DDR3) */
- if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, EEPROM_ADDR_DDR3, 2,
- (uchar *)&settings.ddr3, sizeof(struct ddr3_data))) {
- printf("Could not read the EEPROM; something fundamentally wrong on the I2C bus.\nUse default DDR3 timings\n");
- set_default_ddr3_timings();
- }
- /* Read Siemens eeprom data (CHIP) */
- if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, EEPROM_ADDR_CHIP, 2,
- (uchar *)&settings.chip, sizeof(settings.chip)))
- printf("Could not read chip settings\n");
-
- if (ddr3_default.magic == settings.ddr3.magic &&
- ddr3_default.version == settings.ddr3.version) {
- printf("Using DDR3 settings from EEPROM\n");
- } else {
- if (ddr3_default.magic != settings.ddr3.magic)
- printf("Warning: No valid DDR3 data in eeprom.\n");
- if (ddr3_default.version != settings.ddr3.version)
- printf("Warning: DDR3 data version does not match.\n");
-
- printf("Using default settings\n");
- set_default_ddr3_timings();
- }
-
- if (MAGIC_CHIP == settings.chip.magic) {
- print_chip_data();
- } else {
- printf("Warning: No chip data in eeprom\n");
- }
-
- print_ddr3_timings();
-#endif
- return 0;
-}
-
-#ifdef CONFIG_SPL_BUILD
-static void board_init_ddr(void)
-{
-struct emif_regs dxr2_ddr3_emif_reg_data = {
- .zq_config = 0x50074BE4,
-};
-
-struct ddr_data dxr2_ddr3_data = {
-};
-
-struct cmd_control dxr2_ddr3_cmd_ctrl_data = {
-};
-
-struct ctrl_ioregs dxr2_ddr3_ioregs = {
-};
-
- /* pass values from eeprom */
- dxr2_ddr3_emif_reg_data.sdram_tim1 = settings.ddr3.sdram_tim1;
- dxr2_ddr3_emif_reg_data.sdram_tim2 = settings.ddr3.sdram_tim2;
- dxr2_ddr3_emif_reg_data.sdram_tim3 = settings.ddr3.sdram_tim3;
- dxr2_ddr3_emif_reg_data.emif_ddr_phy_ctlr_1 =
- settings.ddr3.emif_ddr_phy_ctlr_1;
- dxr2_ddr3_emif_reg_data.sdram_config = settings.ddr3.sdram_config;
- dxr2_ddr3_emif_reg_data.ref_ctrl = settings.ddr3.ref_ctrl;
-
- dxr2_ddr3_data.datardsratio0 = settings.ddr3.dt0rdsratio0;
- dxr2_ddr3_data.datawdsratio0 = settings.ddr3.dt0wdsratio0;
- dxr2_ddr3_data.datafwsratio0 = settings.ddr3.dt0fwsratio0;
- dxr2_ddr3_data.datawrsratio0 = settings.ddr3.dt0wrsratio0;
-
- dxr2_ddr3_cmd_ctrl_data.cmd0csratio = settings.ddr3.ddr3_sratio;
- dxr2_ddr3_cmd_ctrl_data.cmd0iclkout = settings.ddr3.iclkout;
- dxr2_ddr3_cmd_ctrl_data.cmd1csratio = settings.ddr3.ddr3_sratio;
- dxr2_ddr3_cmd_ctrl_data.cmd1iclkout = settings.ddr3.iclkout;
- dxr2_ddr3_cmd_ctrl_data.cmd2csratio = settings.ddr3.ddr3_sratio;
- dxr2_ddr3_cmd_ctrl_data.cmd2iclkout = settings.ddr3.iclkout;
-
- dxr2_ddr3_ioregs.cm0ioctl = settings.ddr3.ioctr_val,
- dxr2_ddr3_ioregs.cm1ioctl = settings.ddr3.ioctr_val,
- dxr2_ddr3_ioregs.cm2ioctl = settings.ddr3.ioctr_val,
- dxr2_ddr3_ioregs.dt0ioctl = settings.ddr3.ioctr_val,
- dxr2_ddr3_ioregs.dt1ioctl = settings.ddr3.ioctr_val,
-
- config_ddr(DDR_PLL_FREQ, &dxr2_ddr3_ioregs, &dxr2_ddr3_data,
- &dxr2_ddr3_cmd_ctrl_data, &dxr2_ddr3_emif_reg_data, 0);
-}
-
-static void spl_siemens_board_init(void)
-{
- return;
-}
-#endif /* if def CONFIG_SPL_BUILD */
-
-#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
- (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
-static void cpsw_control(int enabled)
-{
- /* VTP can be added here */
-
- return;
-}
-
-static struct cpsw_slave_data cpsw_slaves[] = {
- {
- .slave_reg_ofs = 0x208,
- .sliver_reg_ofs = 0xd80,
- .phy_addr = 0,
- .phy_if = PHY_INTERFACE_MODE_MII,
- },
-};
-
-static struct cpsw_platform_data cpsw_data = {
- .mdio_base = CPSW_MDIO_BASE,
- .cpsw_base = CPSW_BASE,
- .mdio_div = 0xff,
- .channels = 4,
- .cpdma_reg_ofs = 0x800,
- .slaves = 1,
- .slave_data = cpsw_slaves,
- .ale_reg_ofs = 0xd00,
- .ale_entries = 1024,
- .host_port_reg_ofs = 0x108,
- .hw_stats_reg_ofs = 0x900,
- .bd_ram_ofs = 0x2000,
- .mac_control = (1 << 5),
- .control = cpsw_control,
- .host_port_num = 0,
- .version = CPSW_CTRL_VERSION_2,
-};
-
-#if defined(CONFIG_DRIVER_TI_CPSW) || \
- (defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET))
-int board_eth_init(bd_t *bis)
-{
- struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
- int n = 0;
- int rv;
-
- factoryset_setenv();
-
- /* Set rgmii mode and enable rmii clock to be sourced from chip */
- writel((RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE), &cdev->miisel);
-
- rv = cpsw_register(&cpsw_data);
- if (rv < 0)
- printf("Error %d registering CPSW switch\n", rv);
- else
- n += rv;
- return n;
-}
-
-static int do_switch_reset(cmd_tbl_t *cmdtp, int flag, int argc,
- char *const argv[])
-{
- /* Reset SMSC LAN9303 switch for default configuration */
- gpio_request(GPIO_LAN9303_NRST, "nRST");
- gpio_direction_output(GPIO_LAN9303_NRST, 0);
- /* assert active low reset for 200us */
- udelay(200);
- gpio_set_value(GPIO_LAN9303_NRST, 1);
-
- return 0;
-};
-
-U_BOOT_CMD(
- switch_rst, CONFIG_SYS_MAXARGS, 1, do_switch_reset,
- "Reset LAN9303 switch via its reset pin",
- ""
-);
-#endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */
-#endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */
-
-#include "../common/board.c"
+++ /dev/null
-/*
- * board.h
- *
- * (C) Copyright 2013 Siemens Schweiz AG
- * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
- *
- * Based on:
- * TI AM335x boards information header
- * u-boot:/board/ti/am335x/board.h
- *
- * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _BOARD_H_
-#define _BOARD_H_
-
-#define PARGS3(x) settings.ddr3.x-ddr3_default.x, \
- settings.ddr3.x, ddr3_default.x
-#define PRINTARGS(y) printf("%x, %8x, %8x : "#y"\n", PARGS3(y))
-#define MAGIC_CHIP 0x50494843
-
-/* Automatic generated definition */
-/* Wed, 16 Apr 2014 16:50:41 +0200 */
-/* From file: draco/ddr3-data-universal-default@303MHz-i0-ES3.txt */
-struct ddr3_data {
- unsigned int magic; /* 0x33524444 */
- unsigned int version; /* 0x56312e35 */
- unsigned short int ddr3_sratio; /* 0x0080 */
- unsigned short int iclkout; /* 0x0000 */
- unsigned short int dt0rdsratio0; /* 0x003A */
- unsigned short int dt0wdsratio0; /* 0x003F */
- unsigned short int dt0fwsratio0; /* 0x009F */
- unsigned short int dt0wrsratio0; /* 0x0079 */
- unsigned int sdram_tim1; /* 0x0888A39B */
- unsigned int sdram_tim2; /* 0x26247FDA */
- unsigned int sdram_tim3; /* 0x501F821F */
- unsigned int emif_ddr_phy_ctlr_1; /* 0x00100206 */
- unsigned int sdram_config; /* 0x61A44A32 */
- unsigned int ref_ctrl; /* 0x0000093B */
- unsigned int ioctr_val; /* 0x0000014A */
- char manu_name[32]; /* "default@303MHz \0" */
- char manu_marking[32]; /* "default \0" */
-};
-
-struct chip_data {
- unsigned int magic;
- char sdevname[16];
- char shwver[7];
-};
-
-struct dxr2_baseboard_id {
- struct ddr3_data ddr3;
- struct chip_data chip;
-};
-
-/*
- * We have three pin mux functions that must exist. We must be able to enable
- * uart0, for initial output and i2c0 to read the main EEPROM. We then have a
- * main pinmux function that can be overridden to enable all other pinmux that
- * is required on the board.
- */
-void enable_uart0_pin_mux(void);
-void enable_uart1_pin_mux(void);
-void enable_uart2_pin_mux(void);
-void enable_uart3_pin_mux(void);
-void enable_uart4_pin_mux(void);
-void enable_uart5_pin_mux(void);
-void enable_i2c0_pin_mux(void);
-void enable_board_pin_mux(void);
-#endif
+++ /dev/null
-/*
- * pinmux setup for siemens dxr2 board
- *
- * (C) Copyright 2013 Siemens Schweiz AG
- * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
- *
- * Based on:
- * u-boot:/board/ti/am335x/mux.c
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/mux.h>
-#include <asm/io.h>
-#include <i2c.h>
-#include "board.h"
-
-static struct module_pin_mux uart0_pin_mux[] = {
- {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
- {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
- {-1},
-};
-
-static struct module_pin_mux uart3_pin_mux[] = {
- {OFFSET(spi0_cs1), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART3_RXD */
- {OFFSET(ecap0_in_pwm0_out), (MODE(1) | PULLUDEN)}, /* UART3_TXD */
- {-1},
-};
-
-static struct module_pin_mux i2c0_pin_mux[] = {
- {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
- PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
- {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
- PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
- {-1},
-};
-
-static struct module_pin_mux nand_pin_mux[] = {
- {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */
- {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */
- {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */
- {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */
- {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */
- {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */
- {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */
- {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */
- {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
- {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */
- {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */
- {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */
- {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */
- {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */
- {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */
- {-1},
-};
-
-static struct module_pin_mux gpios_pin_mux[] = {
- /* DFU button GPIO0_27*/
- {OFFSET(gpmc_ad11), (MODE(7) | PULLUDEN | RXACTIVE)},
- {OFFSET(gpmc_csn3), MODE(7) }, /* LED0 GPIO2_0 */
- {OFFSET(emu0), MODE(7)}, /* LED1 GPIO3_7 */
- /* Triacs in HW Rev 2 */
- {OFFSET(uart1_ctsn), MODE(7) | PULLUDDIS | RXACTIVE}, /* Y5 GPIO0_12*/
- {OFFSET(mmc0_dat1), MODE(7) | PULLUDDIS | RXACTIVE}, /* Y3 GPIO2_28*/
- {OFFSET(mmc0_dat2), MODE(7) | PULLUDDIS | RXACTIVE}, /* Y7 GPIO2_27*/
- /* Triacs initial HW Rev */
- {OFFSET(gpmc_csn1), MODE(7) | RXACTIVE | PULLUDDIS}, /* 1_30 Y0 */
- {OFFSET(gpmc_be1n), MODE(7) | RXACTIVE | PULLUDDIS}, /* 1_28 Y1 */
- {OFFSET(gpmc_csn2), MODE(7) | RXACTIVE | PULLUDDIS}, /* 1_31 Y2 */
- {OFFSET(lcd_data15), MODE(7) | RXACTIVE | PULLUDDIS}, /* 0_11 Y3 */
- {OFFSET(lcd_data14), MODE(7) | RXACTIVE | PULLUDDIS}, /* 0_10 Y4 */
- {OFFSET(gpmc_clk), MODE(7) | RXACTIVE | PULLUDDIS}, /* 2_1 Y5 */
- {OFFSET(emu1), MODE(7) | RXACTIVE | PULLUDDIS}, /* 3_8 Y6 */
- {OFFSET(gpmc_ad15), MODE(7) | RXACTIVE | PULLUDDIS}, /* 1_15 Y7 */
- /* Remaining pins that were not used in this file */
- {OFFSET(gpmc_ad8), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(gpmc_ad9), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(gpmc_a0), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(gpmc_a1), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(gpmc_a2), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(gpmc_a3), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(gpmc_a4), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(gpmc_a5), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(gpmc_a6), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(gpmc_a7), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(gpmc_a8), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(gpmc_a9), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(gpmc_a10), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(gpmc_a11), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(lcd_data0), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(lcd_data2), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(lcd_data3), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(lcd_data4), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(lcd_data5), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(lcd_data6), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(lcd_data7), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(lcd_data8), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(lcd_data9), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(lcd_vsync), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(lcd_hsync), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(lcd_pclk), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(lcd_ac_bias_en), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(mmc0_dat3), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(mmc0_dat0), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(mmc0_clk), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(mmc0_cmd), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(spi0_sclk), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(spi0_d0), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(spi0_d1), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(spi0_cs0), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(uart0_ctsn), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(uart0_rtsn), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(uart1_rtsn), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(uart1_rxd), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(uart1_txd), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(mcasp0_aclkx), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(mcasp0_fsx), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(mcasp0_axr0), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(mcasp0_ahclkr), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(mcasp0_aclkr), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(mcasp0_fsr), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(mcasp0_axr1), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(mcasp0_ahclkx), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(xdma_event_intr0), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(xdma_event_intr1), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(nresetin_out), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(porz), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(nnmi), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(osc0_in), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(osc0_out), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(rsvd1), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(tms), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(tdi), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(tdo), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(tck), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(ntrst), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(osc1_in), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(osc1_out), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(pmic_power_en), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(rtc_porz), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(rsvd2), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(ext_wakeup), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(enz_kaldo_1p8v), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(usb0_dm), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(usb0_dp), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(usb0_ce), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(usb0_id), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(usb0_vbus), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(usb0_drvvbus), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(usb1_dm), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(usb1_dp), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(usb1_ce), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(usb1_id), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(usb1_vbus), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(usb1_drvvbus), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(ddr_resetn), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(ddr_csn0), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(ddr_cke), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(ddr_ck), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(ddr_nck), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(ddr_casn), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(ddr_rasn), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(ddr_wen), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(ddr_ba0), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(ddr_ba1), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(ddr_ba2), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(ddr_a0), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(ddr_a1), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(ddr_a2), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(ddr_a3), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(ddr_a4), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(ddr_a5), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(ddr_a6), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(ddr_a7), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(ddr_a8), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(ddr_a9), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(ddr_a10), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(ddr_a11), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(ddr_a12), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(ddr_a13), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(ddr_a14), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(ddr_a15), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(ddr_odt), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(ddr_d0), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(ddr_d1), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(ddr_d2), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(ddr_d3), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(ddr_d4), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(ddr_d5), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(ddr_d6), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(ddr_d7), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(ddr_d8), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(ddr_d9), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(ddr_d10), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(ddr_d11), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(ddr_d12), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(ddr_d13), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(ddr_d14), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(ddr_d15), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(ddr_dqm0), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(ddr_dqm1), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(ddr_dqs0), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(ddr_dqsn0), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(ddr_dqs1), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(ddr_dqsn1), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(ddr_vref), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(ddr_vtp), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(ddr_strben0), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(ddr_strben1), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(ain7), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(ain6), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(ain5), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(ain4), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(ain3), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(ain2), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(ain1), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(ain0), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(vrefp), MODE(7) | RXACTIVE | PULLUDDIS},
- {OFFSET(vrefn), MODE(7) | RXACTIVE | PULLUDDIS},
- /* nRST for SMSC LAN9303 switch - GPIO2_24 */
- {OFFSET(lcd_pclk), MODE(7) }, /* LAN9303 nRST */
- {-1},
-};
-
-static struct module_pin_mux ethernet_pin_mux[] = {
- {OFFSET(mii1_col), (MODE(3) | RXACTIVE)},
- {OFFSET(mii1_crs), (MODE(1) | RXACTIVE)},
- {OFFSET(mii1_rxerr), (MODE(1) | RXACTIVE)},
- {OFFSET(mii1_txen), (MODE(1))},
- {OFFSET(mii1_rxdv), (MODE(3) | RXACTIVE)},
- {OFFSET(mii1_txd3), (MODE(7) | RXACTIVE)},
- {OFFSET(mii1_txd2), (MODE(7) | RXACTIVE)},
- {OFFSET(mii1_txd1), (MODE(1))},
- {OFFSET(mii1_txd0), (MODE(1))},
- {OFFSET(mii1_txclk), (MODE(1) | RXACTIVE)},
- {OFFSET(mii1_rxclk), (MODE(1) | RXACTIVE)},
- {OFFSET(mii1_rxd3), (MODE(1) | RXACTIVE)},
- {OFFSET(mii1_rxd2), (MODE(1))},
- {OFFSET(mii1_rxd1), (MODE(1) | RXACTIVE)},
- {OFFSET(mii1_rxd0), (MODE(1) | RXACTIVE)},
- {OFFSET(rmii1_refclk), (MODE(0) | RXACTIVE)},
- {OFFSET(mdio_data), (MODE(0) | RXACTIVE | PULLUP_EN)},
- {OFFSET(mdio_clk), (MODE(0) | PULLUP_EN)},
- {-1},
-};
-
-void enable_uart0_pin_mux(void)
-{
- configure_module_pin_mux(uart0_pin_mux);
-}
-
-void enable_uart3_pin_mux(void)
-{
- configure_module_pin_mux(uart3_pin_mux);
-}
-
-void enable_i2c0_pin_mux(void)
-{
- configure_module_pin_mux(i2c0_pin_mux);
-}
-
-void enable_board_pin_mux(void)
-{
- enable_uart3_pin_mux();
- configure_module_pin_mux(nand_pin_mux);
- configure_module_pin_mux(ethernet_pin_mux);
- configure_module_pin_mux(gpios_pin_mux);
-}
Active arm armv7 am33xx isee igep0033 am335x_igep0033 - Enric Balletbo i Serra <eballetbo@iseebcn.com>
Active arm armv7 am33xx phytec pcm051 pcm051_rev1 pcm051:REV1 Lars Poeschel <poeschel@lemonage.de>
Active arm armv7 am33xx phytec pcm051 pcm051_rev3 pcm051:REV3 Lars Poeschel <poeschel@lemonage.de>
-Active arm armv7 am33xx siemens dxr2 dxr2 - Roger Meier <r.meier@siemens.com>
+Active arm armv7 am33xx siemens draco dxr2 - Roger Meier <r.meier@siemens.com>
Active arm armv7 am33xx siemens pxm2 pxm2 - Roger Meier <r.meier@siemens.com>
Active arm armv7 am33xx siemens rut rut - Roger Meier <r.meier@siemens.com>
Active arm armv7 am33xx silica pengwyn pengwyn - Lothar Felten <lothar.felten@gmail.com>
projects / oweals / u-boot.git / commitdiff