ARM: uniphier: add more init code for PXs3

Add the boot device table and reset deassertion for eMMC.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

diff --git a/arch/arm/mach-uniphier/board_init.c b/arch/arm/mach-uniphier/board_init.c
index 2564a02a62305cc2fb8e75cf4507b9e62e6cfcf8..e05d6bffd5ce3f5fd55873e6cdfaf61db95146d0 100644 (file)
--- a/arch/arm/mach-uniphier/board_init.c
+++ b/arch/arm/mach-uniphier/board_init.c
@@ -175,6 +175,7 @@ static const struct uniphier_initdata uniphier_initdata[] = {
                .nand_2cs = false,
                .sbc_init = uniphier_pxs2_sbc_init,
                .pll_init = uniphier_pxs3_pll_init,
+               .clk_init = uniphier_pxs3_clk_init,
        },
 #endif
 };

diff --git a/arch/arm/mach-uniphier/boot-device/Makefile b/arch/arm/mach-uniphier/boot-device/Makefile
index a54d2acb109e7dc9295dff2f1d0b32846176927e..abb58a729aa31eda3ff193860426baa2f663c5b1 100644 (file)
--- a/arch/arm/mach-uniphier/boot-device/Makefile
+++ b/arch/arm/mach-uniphier/boot-device/Makefile
@@ -13,6 +13,7 @@ obj-$(CONFIG_ARCH_UNIPHIER_PXS2)      += boot-device-pxs2.o
 obj-$(CONFIG_ARCH_UNIPHIER_LD6B)       += boot-device-pxs2.o
 obj-$(CONFIG_ARCH_UNIPHIER_LD11)       += boot-device-ld11.o
 obj-$(CONFIG_ARCH_UNIPHIER_LD20)       += boot-device-ld11.o
+obj-$(CONFIG_ARCH_UNIPHIER_PXS3)       += boot-device-pxs3.o
 
 ifdef CONFIG_SPL_BUILD
 obj-$(CONFIG_SPL_BOARD_LOAD_IMAGE)     += spl_board.o

diff --git a/arch/arm/mach-uniphier/boot-device/boot-device-pxs3.c b/arch/arm/mach-uniphier/boot-device/boot-device-pxs3.c
new file mode 100644 (file)
index 0000000..fe45a01
--- /dev/null
+++ b/arch/arm/mach-uniphier/boot-device/boot-device-pxs3.c
@@ -0,0 +1,41 @@
+/*
+ * Copyright (C) 2017 Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+
+#include "../sg-regs.h"
+#include "boot-device.h"
+
+const struct uniphier_boot_device uniphier_pxs3_boot_device_table[] = {
+       {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC  8, EraseSize 128KB, Addr 5)"},
+       {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 5)"},
+       {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC  8, EraseSize 256KB, Addr 5)"},
+       {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 256KB, Addr 5)"},
+       {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC  8, EraseSize 512KB, Addr 5)"},
+       {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 512KB, Addr 5)"},
+       {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC  8, ONFI,            Addr 5)"},
+       {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI,            Addr 5)"},
+       {BOOT_DEVICE_MMC1, "eMMC (Legacy,         4bit, 1.8V, Training Off)"},
+       {BOOT_DEVICE_MMC1, "eMMC (Legacy,         4bit, 1.8V, Training On)"},
+       {BOOT_DEVICE_MMC1, "eMMC (Legacy,         8bit, 1.8V, Training Off)"},
+       {BOOT_DEVICE_MMC1, "eMMC (Legacy,         8bit, 1.8V, Training On)"},
+       {BOOT_DEVICE_MMC1, "eMMC (High Speed SDR, 8bit, 1.8V, Training Off)"},
+       {BOOT_DEVICE_MMC1, "eMMC (High Speed SDR, 8bit, 1.8V, Training On)"},
+       {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC  8, ONFI,            Addr 5, BBM Last Page)"},
+       {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI,            Addr 5, BBM Last Page)"},
+};
+
+const unsigned uniphier_pxs3_boot_device_count =
+                               ARRAY_SIZE(uniphier_pxs3_boot_device_table);
+
+int uniphier_pxs3_boot_device_is_usb(u32 pinmon)
+{
+       return !!(readl(SG_PINMON2) & BIT(31));
+}

diff --git a/arch/arm/mach-uniphier/boot-device/boot-device.c b/arch/arm/mach-uniphier/boot-device/boot-device.c
index 00809777b24ae1ec73b03029b39d5cee8bf60423..094f77b4d10e465462c968ca32a0df706b30a13c 100644 (file)
--- a/arch/arm/mach-uniphier/boot-device/boot-device.c
+++ b/arch/arm/mach-uniphier/boot-device/boot-device.c
@@ -115,6 +115,16 @@ static const struct uniphier_boot_device_info uniphier_boot_device_info[] = {
                .have_internal_stm = 1,
        },
 #endif
+#if defined(CONFIG_ARCH_UNIPHIER_PXS3)
+       {
+               .soc_id = UNIPHIER_PXS3_ID,
+               .boot_device_sel_shift = 1,
+               .boot_device_table = uniphier_pxs3_boot_device_table,
+               .boot_device_count = &uniphier_pxs3_boot_device_count,
+               .boot_device_is_usb = uniphier_pxs3_boot_device_is_usb,
+               .have_internal_stm = 0,
+       },
+#endif
 };
 UNIPHIER_DEFINE_SOCDATA_FUNC(uniphier_get_boot_device_info,
                             uniphier_boot_device_info)

diff --git a/arch/arm/mach-uniphier/boot-device/boot-device.h b/arch/arm/mach-uniphier/boot-device/boot-device.h
index f3fb2f32a881b19a9b5c2a85448bcce6d5a8274a..c4ce3e50a378c4593b840c46762a5116c5ee52b2 100644 (file)
--- a/arch/arm/mach-uniphier/boot-device/boot-device.h
+++ b/arch/arm/mach-uniphier/boot-device/boot-device.h
@@ -18,16 +18,19 @@ extern const struct uniphier_boot_device uniphier_ld4_boot_device_table[];
 extern const struct uniphier_boot_device uniphier_pro5_boot_device_table[];
 extern const struct uniphier_boot_device uniphier_pxs2_boot_device_table[];
 extern const struct uniphier_boot_device uniphier_ld11_boot_device_table[];
+extern const struct uniphier_boot_device uniphier_pxs3_boot_device_table[];
 
 extern const unsigned int uniphier_sld3_boot_device_count;
 extern const unsigned int uniphier_ld4_boot_device_count;
 extern const unsigned int uniphier_pro5_boot_device_count;
 extern const unsigned int uniphier_pxs2_boot_device_count;
 extern const unsigned int uniphier_ld11_boot_device_count;
+extern const unsigned int uniphier_pxs3_boot_device_count;
 
 int uniphier_pxs2_boot_device_is_usb(u32 pinmon);
 int uniphier_ld11_boot_device_is_usb(u32 pinmon);
 int uniphier_ld20_boot_device_is_usb(u32 pinmon);
+int uniphier_pxs3_boot_device_is_usb(u32 pinmon);
 
 unsigned int uniphier_pxs2_boot_device_fixup(unsigned int mode);
 unsigned int uniphier_ld11_boot_device_fixup(unsigned int mode);

diff --git a/arch/arm/mach-uniphier/clk/Makefile b/arch/arm/mach-uniphier/clk/Makefile
index 41341970ec057dd1d91b632f162b1510a74ab324..dad035d03a88841586cb09bc41362101cefe37c7 100644 (file)
--- a/arch/arm/mach-uniphier/clk/Makefile
+++ b/arch/arm/mach-uniphier/clk/Makefile
@@ -25,7 +25,7 @@ obj-$(CONFIG_ARCH_UNIPHIER_PXS2)      += clk-pxs2.o
 obj-$(CONFIG_ARCH_UNIPHIER_LD6B)       += clk-pxs2.o
 obj-$(CONFIG_ARCH_UNIPHIER_LD11)       += clk-ld11.o pll-ld11.o
 obj-$(CONFIG_ARCH_UNIPHIER_LD20)       += clk-ld20.o pll-ld20.o
-obj-$(CONFIG_ARCH_UNIPHIER_PXS3)       += pll-pxs3.o
+obj-$(CONFIG_ARCH_UNIPHIER_PXS3)       += clk-pxs3.o pll-pxs3.o
 
 endif
 

diff --git a/arch/arm/mach-uniphier/clk/clk-pxs3.c b/arch/arm/mach-uniphier/clk/clk-pxs3.c
new file mode 100644 (file)
index 0000000..2dee857
--- /dev/null
+++ b/arch/arm/mach-uniphier/clk/clk-pxs3.c
@@ -0,0 +1,17 @@
+/*
+ * Copyright (C) 2017 Socionext Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <linux/io.h>
+
+#include "../init.h"
+
+#define SDCTRL_EMMC_HW_RESET   0x59810280
+
+void uniphier_pxs3_clk_init(void)
+{
+       /* TODO: use "mmc-pwrseq-emmc" */
+       writel(1, SDCTRL_EMMC_HW_RESET);
+}

diff --git a/arch/arm/mach-uniphier/init.h b/arch/arm/mach-uniphier/init.h
index 4803d08038c8124de2469a276408e30e50897ec2..d413d00f951b403235ff4326d041a39321fec121 100644 (file)
--- a/arch/arm/mach-uniphier/init.h
+++ b/arch/arm/mach-uniphier/init.h
@@ -119,6 +119,7 @@ void uniphier_pro5_clk_init(void);
 void uniphier_pxs2_clk_init(void);
 void uniphier_ld11_clk_init(void);
 void uniphier_ld20_clk_init(void);
+void uniphier_pxs3_clk_init(void);
 
 unsigned int uniphier_boot_device_raw(void);
 int uniphier_have_internal_stm(void);

diff --git a/arch/arm/mach-uniphier/sg-regs.h b/arch/arm/mach-uniphier/sg-regs.h
index dc94084c899593d493398c7e7c09c9ffd048b143..029da91f8f8bab05428c9732879f823767a24e3f 100644 (file)
--- a/arch/arm/mach-uniphier/sg-regs.h
+++ b/arch/arm/mach-uniphier/sg-regs.h
@@ -70,6 +70,7 @@
 
 /* Pin Monitor */
 #define SG_PINMON0                     (SG_DBG_BASE | 0x0100)
+#define SG_PINMON2                     (SG_DBG_BASE | 0x0108)
 
 #define SG_PINMON0_CLK_MODE_UPLLSRC_MASK       (0x3 << 19)
 #define SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT    (0x0 << 19)