ARM FREESCALE IMX
M: Stefano Babic <sbabic@denx.de>
M: Fabio Estevam <fabio.estevam@nxp.com>
+R: NXP Linux Team <linux-imx@nxp.com>
S: Maintained
T: git git://git.denx.de/u-boot-imx.git
F: arch/arm/cpu/arm1136/mx*/
M: Patrick Delaunay <patrick.delaunay@st.com>
M: Christophe Kerello <christophe.kerello@st.com>
M: Patrice Chotard <patrice.chotard@st.com>
+L: uboot-stm32@st-md-mailman.stormreply.com (moderated for non-subscribers)
S: Maintained
F: arch/arm/mach-stm32mp
F: drivers/clk/clk_stm32mp1.c
VERSION = 2018
PATCHLEVEL = 11
SUBLEVEL =
-EXTRAVERSION = -rc3
+EXTRAVERSION =
NAME =
# *DOCUMENTATION*
config TARGET_AXS103
bool "Support Synopsys Designware SDP board AXS103"
-config TARGET_EMDK
- bool "Synopsys EM Development kit"
+config TARGET_EMSDP
+ bool "Synopsys EM Software Development Platform"
select CPU_ARCEM6
config TARGET_HSDK
source "board/abilis/tb100/Kconfig"
source "board/synopsys/Kconfig"
source "board/synopsys/axs10x/Kconfig"
-source "board/synopsys/emdk/Kconfig"
+source "board/synopsys/emsdp/Kconfig"
source "board/synopsys/hsdk/Kconfig"
source "board/synopsys/iot_devkit/Kconfig"
dtb-$(CONFIG_TARGET_AXS103) += axs103.dtb
dtb-$(CONFIG_TARGET_NSIM) += nsim.dtb
dtb-$(CONFIG_TARGET_TB100) += abilis_tb100.dtb
-dtb-$(CONFIG_TARGET_EMDK) += emdk.dtb
+dtb-$(CONFIG_TARGET_EMSDP) += emsdp.dtb
dtb-$(CONFIG_TARGET_HSDK) += hsdk.dtb
dtb-$(CONFIG_TARGET_IOT_DEVKIT) += iot_devkit.dtb
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2018 Synopsys, Inc. All rights reserved.
- */
-/dts-v1/;
-
-#include "skeleton.dtsi"
-
-/ {
- model = "snps,emdk";
-
- #address-cells = <1>;
- #size-cells = <1>;
-
- aliases {
- console = &uart0;
- };
-
- cpu_card {
- core_clk: core_clk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <40000000>;
- u-boot,dm-pre-reloc;
- };
- };
-
- uart0: serial0@f0004000 {
- compatible = "snps,dw-apb-uart";
- clock-frequency = <100000000>;
- reg = <0xf0004000 0x1000>;
- reg-shift = <2>;
- reg-io-width = <4>;
- };
-};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Synopsys, Inc. All rights reserved.
+ */
+/dts-v1/;
+
+#include "skeleton.dtsi"
+
+/ {
+ model = "snps,emsdp";
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ aliases {
+ console = &uart0;
+ };
+
+ cpu_card {
+ core_clk: core_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <40000000>;
+ u-boot,dm-pre-reloc;
+ };
+ };
+
+ uart0: serial0@f0004000 {
+ compatible = "snps,dw-apb-uart";
+ clock-frequency = <100000000>;
+ reg = <0xf0004000 0x1000>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ };
+};
select SPL_SPI_SUPPORT if DM_SPI
select SPL_WATCHDOG_SUPPORT
select SUPPORT_SPL
- select SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE
select SYS_NS16550
select SYS_THUMB_BUILD if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
imply CMD_DM
imply DM_SPI_FLASH
imply FAT_WRITE
imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
+ imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE
config ARCH_SUNXI
bool "Support sunxi (Allwinner) SoCs"
u-boot,dm-pre-reloc;
#address-cells = <1>;
#size-cells = <1>;
- compatible = "n25q128a13", "jedec,spi-nor";
+ compatible = "n25q128a13", "jedec,spi-nor", "spi-flash";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <27777777>;
};
spi1: spi@10680 {
status = "okay";
- fpga@2 {
+ fpga@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spi-generic-device";
- reg = <2>; /* Chip select 2 */
+ reg = <0>; /* Chip select 0 */
spi-max-frequency = <27777777>;
};
};
chosen {
stdout-path = &uart5;
};
+
+ aliases {
+ ethernet0 = &mac0;
+ ethernet1 = &mac1;
+ };
};
&uart5 {
u-boot,dm-pre-reloc;
status = "okay";
};
+
+&mac0 {
+ status = "okay";
+
+ phy-mode = "rgmii";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mac1link_default &pinctrl_mdio1_default>;
+};
+
+&mac1 {
+ status = "okay";
+
+ phy-mode = "rgmii";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mac2link_default &pinctrl_mdio2_default>;
+};
#size-cells = <1>;
interrupt-parent = <&vic>;
+ aliases {
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ i2c5 = &i2c5;
+ i2c6 = &i2c6;
+ i2c7 = &i2c7;
+ i2c8 = &i2c8;
+ i2c9 = &i2c9;
+ i2c10 = &i2c10;
+ i2c11 = &i2c11;
+ i2c12 = &i2c12;
+ i2c13 = &i2c13;
+ serial0 = &uart1;
+ serial1 = &uart2;
+ serial2 = &uart3;
+ serial3 = &uart4;
+ serial4 = &uart5;
+ serial5 = &vuart;
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
};
};
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x80000000 0>;
+ };
+
ahb {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
+ fmc: flash-controller@1e620000 {
+ reg = < 0x1e620000 0xc4
+ 0x20000000 0x10000000 >;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "aspeed,ast2500-fmc";
+ status = "disabled";
+ interrupts = <19>;
+ flash@0 {
+ reg = < 0 >;
+ compatible = "jedec,spi-nor";
+ status = "disabled";
+ };
+ flash@1 {
+ reg = < 1 >;
+ compatible = "jedec,spi-nor";
+ status = "disabled";
+ };
+ flash@2 {
+ reg = < 2 >;
+ compatible = "jedec,spi-nor";
+ status = "disabled";
+ };
+ };
+
+ spi1: flash-controller@1e630000 {
+ reg = < 0x1e630000 0xc4
+ 0x30000000 0x08000000 >;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "aspeed,ast2500-spi";
+ status = "disabled";
+ flash@0 {
+ reg = < 0 >;
+ compatible = "jedec,spi-nor";
+ status = "disabled";
+ };
+ flash@1 {
+ reg = < 1 >;
+ compatible = "jedec,spi-nor";
+ status = "disabled";
+ };
+ };
+
+ spi2: flash-controller@1e631000 {
+ reg = < 0x1e631000 0xc4
+ 0x38000000 0x08000000 >;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "aspeed,ast2500-spi";
+ status = "disabled";
+ flash@0 {
+ reg = < 0 >;
+ compatible = "jedec,spi-nor";
+ status = "disabled";
+ };
+ flash@1 {
+ reg = < 1 >;
+ compatible = "jedec,spi-nor";
+ status = "disabled";
+ };
+ };
+
vic: interrupt-controller@1e6c0080 {
compatible = "aspeed,ast2400-vic";
interrupt-controller;
};
mac0: ethernet@1e660000 {
- compatible = "faraday,ftgmac100";
+ compatible = "aspeed,ast2500-mac", "faraday,ftgmac100";
reg = <0x1e660000 0x180>;
interrupts = <2>;
- no-hw-checksum;
status = "disabled";
};
mac1: ethernet@1e680000 {
- compatible = "faraday,ftgmac100";
+ compatible = "aspeed,ast2500-mac", "faraday,ftgmac100";
reg = <0x1e680000 0x180>;
interrupts = <3>;
- no-hw-checksum;
+ status = "disabled";
+ };
+
+ ehci0: usb@1e6a1000 {
+ compatible = "aspeed,ast2500-ehci", "generic-ehci";
+ reg = <0x1e6a1000 0x100>;
+ interrupts = <5>;
+ status = "disabled";
+ };
+
+ ehci1: usb@1e6a3000 {
+ compatible = "aspeed,ast2500-ehci", "generic-ehci";
+ reg = <0x1e6a3000 0x100>;
+ interrupts = <13>;
+ status = "disabled";
+ };
+
+ uhci: usb@1e6b0000 {
+ compatible = "aspeed,ast2500-uhci", "generic-uhci";
+ reg = <0x1e6b0000 0x100>;
+ interrupts = <14>;
+ #ports = <2>;
status = "disabled";
};
#size-cells = <1>;
ranges;
- clk_clkin: clk_clkin@1e6e2070 {
- #clock-cells = <0>;
- compatible = "aspeed,g5-clkin-clock";
- reg = <0x1e6e2070 0x04>;
- };
-
syscon: syscon@1e6e2000 {
compatible = "aspeed,g5-scu", "syscon", "simple-mfd";
reg = <0x1e6e2000 0x1a8>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
pinctrl: pinctrl {
compatible = "aspeed,g5-pinctrl";
aspeed,external-nodes = <&gfx &lhc>;
- pinctrl_acpi_default: acpi_default {
- function = "ACPI";
- groups = "ACPI";
- };
+ };
+ };
- pinctrl_adc0_default: adc0_default {
- function = "ADC0";
- groups = "ADC0";
- };
+ rng: hwrng@1e6e2078 {
+ compatible = "timeriomem_rng";
+ reg = <0x1e6e2078 0x4>;
+ period = <1>;
+ quality = <100>;
+ };
- pinctrl_adc1_default: adc1_default {
- function = "ADC1";
- groups = "ADC1";
- };
+ gfx: display@1e6e6000 {
+ compatible = "aspeed,ast2500-gfx", "syscon";
+ reg = <0x1e6e6000 0x1000>;
+ reg-io-width = <4>;
+ };
- pinctrl_adc10_default: adc10_default {
- function = "ADC10";
- groups = "ADC10";
- };
+ adc: adc@1e6e9000 {
+ compatible = "aspeed,ast2500-adc";
+ reg = <0x1e6e9000 0xb0>;
+ #io-channel-cells = <1>;
+ status = "disabled";
+ };
- pinctrl_adc11_default: adc11_default {
- function = "ADC11";
- groups = "ADC11";
- };
+ sram@1e720000 {
+ compatible = "mmio-sram";
+ reg = <0x1e720000 0x9000>; // 36K
+ };
- pinctrl_adc12_default: adc12_default {
- function = "ADC12";
- groups = "ADC12";
- };
+ gpio: gpio@1e780000 {
+ #gpio-cells = <2>;
+ gpio-controller;
+ compatible = "aspeed,ast2500-gpio";
+ reg = <0x1e780000 0x1000>;
+ interrupts = <20>;
+ gpio-ranges = <&pinctrl 0 0 220>;
+ interrupt-controller;
+ };
- pinctrl_adc13_default: adc13_default {
- function = "ADC13";
- groups = "ADC13";
- };
+ timer: timer@1e782000 {
+ /* This timer is a Faraday FTTMR010 derivative */
+ compatible = "aspeed,ast2400-timer";
+ reg = <0x1e782000 0x90>;
+ };
- pinctrl_adc14_default: adc14_default {
- function = "ADC14";
- groups = "ADC14";
- };
+ uart1: serial@1e783000 {
+ compatible = "ns16550a";
+ reg = <0x1e783000 0x20>;
+ reg-shift = <2>;
+ interrupts = <9>;
+ no-loopback-test;
+ status = "disabled";
+ };
- pinctrl_adc15_default: adc15_default {
- function = "ADC15";
- groups = "ADC15";
- };
+ uart5: serial@1e784000 {
+ compatible = "ns16550a";
+ reg = <0x1e784000 0x20>;
+ reg-shift = <2>;
+ interrupts = <10>;
+ no-loopback-test;
+ status = "disabled";
+ };
- pinctrl_adc2_default: adc2_default {
- function = "ADC2";
- groups = "ADC2";
- };
+ wdt1: watchdog@1e785000 {
+ compatible = "aspeed,wdt";
+ reg = <0x1e785000 0x1c>;
+ interrupts = <27>;
+ };
- pinctrl_adc3_default: adc3_default {
- function = "ADC3";
- groups = "ADC3";
- };
+ wdt2: watchdog@1e785020 {
+ compatible = "aspeed,wdt";
+ reg = <0x1e785020 0x1c>;
+ interrupts = <27>;
+ status = "disabled";
+ };
- pinctrl_adc4_default: adc4_default {
- function = "ADC4";
- groups = "ADC4";
- };
+ wdt3: watchdog@1e785040 {
+ compatible = "aspeed,wdt";
+ reg = <0x1e785040 0x1c>;
+ status = "disabled";
+ };
- pinctrl_adc5_default: adc5_default {
- function = "ADC5";
- groups = "ADC5";
- };
+ pwm_tacho: pwm-tacho-controller@1e786000 {
+ compatible = "aspeed,ast2500-pwm-tacho";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x1e786000 0x1000>;
+ status = "disabled";
+ };
- pinctrl_adc6_default: adc6_default {
- function = "ADC6";
- groups = "ADC6";
- };
+ vuart: serial@1e787000 {
+ compatible = "aspeed,ast2500-vuart";
+ reg = <0x1e787000 0x40>;
+ reg-shift = <2>;
+ interrupts = <8>;
+ no-loopback-test;
+ status = "disabled";
+ };
- pinctrl_adc7_default: adc7_default {
- function = "ADC7";
- groups = "ADC7";
- };
+ lpc: lpc@1e789000 {
+ compatible = "aspeed,ast2500-lpc", "simple-mfd";
+ reg = <0x1e789000 0x1000>;
- pinctrl_adc8_default: adc8_default {
- function = "ADC8";
- groups = "ADC8";
- };
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x1e789000 0x1000>;
- pinctrl_adc9_default: adc9_default {
- function = "ADC9";
- groups = "ADC9";
- };
+ lpc_bmc: lpc-bmc@0 {
+ compatible = "aspeed,ast2500-lpc-bmc";
+ reg = <0x0 0x80>;
+ };
- pinctrl_bmcint_default: bmcint_default {
- function = "BMCINT";
- groups = "BMCINT";
- };
+ lpc_host: lpc-host@80 {
+ compatible = "aspeed,ast2500-lpc-host", "simple-mfd", "syscon";
+ reg = <0x80 0x1e0>;
+ reg-io-width = <4>;
- pinctrl_ddcclk_default: ddcclk_default {
- function = "DDCCLK";
- groups = "DDCCLK";
- };
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x80 0x1e0>;
- pinctrl_ddcdat_default: ddcdat_default {
- function = "DDCDAT";
- groups = "DDCDAT";
+ lpc_ctrl: lpc-ctrl@0 {
+ compatible = "aspeed,ast2500-lpc-ctrl";
+ reg = <0x0 0x80>;
+ status = "disabled";
};
- pinctrl_espi_default: espi_default {
- function = "ESPI";
- groups = "ESPI";
+ lpc_snoop: lpc-snoop@0 {
+ compatible = "aspeed,ast2500-lpc-snoop";
+ reg = <0x0 0x80>;
+ interrupts = <8>;
+ status = "disabled";
};
- pinctrl_fwspics1_default: fwspics1_default {
- function = "FWSPICS1";
- groups = "FWSPICS1";
+ lhc: lhc@20 {
+ compatible = "aspeed,ast2500-lhc";
+ reg = <0x20 0x24 0x48 0x8>;
};
- pinctrl_fwspics2_default: fwspics2_default {
- function = "FWSPICS2";
- groups = "FWSPICS2";
+ lpc_reset: reset-controller@18 {
+ compatible = "aspeed,ast2500-lpc-reset";
+ reg = <0x18 0x4>;
+ #reset-cells = <1>;
};
- pinctrl_gpid0_default: gpid0_default {
- function = "GPID0";
- groups = "GPID0";
+ ibt: ibt@c0 {
+ compatible = "aspeed,ast2500-ibt-bmc";
+ reg = <0xc0 0x18>;
+ interrupts = <8>;
+ status = "disabled";
};
+ };
+ };
- pinctrl_gpid2_default: gpid2_default {
- function = "GPID2";
- groups = "GPID2";
- };
+ uart2: serial@1e78d000 {
+ compatible = "ns16550a";
+ reg = <0x1e78d000 0x20>;
+ reg-shift = <2>;
+ interrupts = <32>;
+ no-loopback-test;
+ status = "disabled";
+ };
- pinctrl_gpid4_default: gpid4_default {
- function = "GPID4";
- groups = "GPID4";
- };
+ uart3: serial@1e78e000 {
+ compatible = "ns16550a";
+ reg = <0x1e78e000 0x20>;
+ reg-shift = <2>;
+ interrupts = <33>;
+ no-loopback-test;
+ status = "disabled";
+ };
- pinctrl_gpid6_default: gpid6_default {
- function = "GPID6";
- groups = "GPID6";
- };
+ uart4: serial@1e78f000 {
+ compatible = "ns16550a";
+ reg = <0x1e78f000 0x20>;
+ reg-shift = <2>;
+ interrupts = <34>;
+ no-loopback-test;
+ status = "disabled";
+ };
- pinctrl_gpie0_default: gpie0_default {
- function = "GPIE0";
- groups = "GPIE0";
- };
+ i2c: i2c@1e78a000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x1e78a000 0x1000>;
+ };
+ };
+ };
+};
- pinctrl_gpie2_default: gpie2_default {
- function = "GPIE2";
- groups = "GPIE2";
- };
+&i2c {
+ i2c_ic: interrupt-controller@0 {
+ #interrupt-cells = <1>;
+ compatible = "aspeed,ast2500-i2c-ic";
+ reg = <0x0 0x40>;
+ interrupts = <12>;
+ interrupt-controller;
+ };
- pinctrl_gpie4_default: gpie4_default {
- function = "GPIE4";
- groups = "GPIE4";
- };
+ i2c0: i2c-bus@40 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #interrupt-cells = <1>;
+
+ reg = <0x40 0x40>;
+ compatible = "aspeed,ast2500-i2c-bus";
+ bus-frequency = <100000>;
+ interrupts = <0>;
+ interrupt-parent = <&i2c_ic>;
+ status = "disabled";
+ /* Does not need pinctrl properties */
+ };
- pinctrl_gpie6_default: gpie6_default {
- function = "GPIE6";
- groups = "GPIE6";
- };
+ i2c1: i2c-bus@80 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #interrupt-cells = <1>;
+
+ reg = <0x80 0x40>;
+ compatible = "aspeed,ast2500-i2c-bus";
+ bus-frequency = <100000>;
+ interrupts = <1>;
+ interrupt-parent = <&i2c_ic>;
+ status = "disabled";
+ /* Does not need pinctrl properties */
+ };
- pinctrl_i2c10_default: i2c10_default {
- function = "I2C10";
- groups = "I2C10";
- };
+ i2c2: i2c-bus@c0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #interrupt-cells = <1>;
+
+ reg = <0xc0 0x40>;
+ compatible = "aspeed,ast2500-i2c-bus";
+ bus-frequency = <100000>;
+ interrupts = <2>;
+ interrupt-parent = <&i2c_ic>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3_default>;
+ status = "disabled";
+ };
- pinctrl_i2c11_default: i2c11_default {
- function = "I2C11";
- groups = "I2C11";
- };
+ i2c3: i2c-bus@100 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #interrupt-cells = <1>;
+
+ reg = <0x100 0x40>;
+ compatible = "aspeed,ast2500-i2c-bus";
+ bus-frequency = <100000>;
+ interrupts = <3>;
+ interrupt-parent = <&i2c_ic>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c4_default>;
+ status = "disabled";
+ };
- pinctrl_i2c12_default: i2c12_default {
- function = "I2C12";
- groups = "I2C12";
- };
+ i2c4: i2c-bus@140 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #interrupt-cells = <1>;
+
+ reg = <0x140 0x40>;
+ compatible = "aspeed,ast2500-i2c-bus";
+ bus-frequency = <100000>;
+ interrupts = <4>;
+ interrupt-parent = <&i2c_ic>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c5_default>;
+ status = "disabled";
+ };
- pinctrl_i2c13_default: i2c13_default {
- function = "I2C13";
- groups = "I2C13";
- };
+ i2c5: i2c-bus@180 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #interrupt-cells = <1>;
+
+ reg = <0x180 0x40>;
+ compatible = "aspeed,ast2500-i2c-bus";
+ bus-frequency = <100000>;
+ interrupts = <5>;
+ interrupt-parent = <&i2c_ic>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c6_default>;
+ status = "disabled";
+ };
- pinctrl_i2c14_default: i2c14_default {
- function = "I2C14";
- groups = "I2C14";
- };
+ i2c6: i2c-bus@1c0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #interrupt-cells = <1>;
+
+ reg = <0x1c0 0x40>;
+ compatible = "aspeed,ast2500-i2c-bus";
+ bus-frequency = <100000>;
+ interrupts = <6>;
+ interrupt-parent = <&i2c_ic>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c7_default>;
+ status = "disabled";
+ };
- pinctrl_i2c3_default: i2c3_default {
- function = "I2C3";
- groups = "I2C3";
- };
+ i2c7: i2c-bus@300 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #interrupt-cells = <1>;
+
+ reg = <0x300 0x40>;
+ compatible = "aspeed,ast2500-i2c-bus";
+ bus-frequency = <100000>;
+ interrupts = <7>;
+ interrupt-parent = <&i2c_ic>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c8_default>;
+ status = "disabled";
+ };
- pinctrl_i2c4_default: i2c4_default {
- function = "I2C4";
- groups = "I2C4";
- };
+ i2c8: i2c-bus@340 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #interrupt-cells = <1>;
+
+ reg = <0x340 0x40>;
+ compatible = "aspeed,ast2500-i2c-bus";
+ bus-frequency = <100000>;
+ interrupts = <8>;
+ interrupt-parent = <&i2c_ic>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c9_default>;
+ status = "disabled";
+ };
- pinctrl_i2c5_default: i2c5_default {
- function = "I2C5";
- groups = "I2C5";
- };
+ i2c9: i2c-bus@380 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #interrupt-cells = <1>;
+
+ reg = <0x380 0x40>;
+ compatible = "aspeed,ast2500-i2c-bus";
+ bus-frequency = <100000>;
+ interrupts = <9>;
+ interrupt-parent = <&i2c_ic>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c10_default>;
+ status = "disabled";
+ };
- pinctrl_i2c6_default: i2c6_default {
- function = "I2C6";
- groups = "I2C6";
- };
+ i2c10: i2c-bus@3c0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #interrupt-cells = <1>;
+
+ reg = <0x3c0 0x40>;
+ compatible = "aspeed,ast2500-i2c-bus";
+ bus-frequency = <100000>;
+ interrupts = <10>;
+ interrupt-parent = <&i2c_ic>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c11_default>;
+ status = "disabled";
+ };
- pinctrl_i2c7_default: i2c7_default {
- function = "I2C7";
- groups = "I2C7";
- };
+ i2c11: i2c-bus@400 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #interrupt-cells = <1>;
+
+ reg = <0x400 0x40>;
+ compatible = "aspeed,ast2500-i2c-bus";
+ bus-frequency = <100000>;
+ interrupts = <11>;
+ interrupt-parent = <&i2c_ic>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c12_default>;
+ status = "disabled";
+ };
- pinctrl_i2c8_default: i2c8_default {
- function = "I2C8";
- groups = "I2C8";
- };
+ i2c12: i2c-bus@440 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #interrupt-cells = <1>;
+
+ reg = <0x440 0x40>;
+ compatible = "aspeed,ast2500-i2c-bus";
+ bus-frequency = <100000>;
+ interrupts = <12>;
+ interrupt-parent = <&i2c_ic>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c13_default>;
+ status = "disabled";
+ };
- pinctrl_i2c9_default: i2c9_default {
- function = "I2C9";
- groups = "I2C9";
- };
+ i2c13: i2c-bus@480 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #interrupt-cells = <1>;
+
+ reg = <0x480 0x40>;
+ compatible = "aspeed,ast2500-i2c-bus";
+ bus-frequency = <100000>;
+ interrupts = <13>;
+ interrupt-parent = <&i2c_ic>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c14_default>;
+ status = "disabled";
+ };
+};
- pinctrl_lad0_default: lad0_default {
- function = "LAD0";
- groups = "LAD0";
- };
+&pinctrl {
+ pinctrl_acpi_default: acpi_default {
+ function = "ACPI";
+ groups = "ACPI";
+ };
- pinctrl_lad1_default: lad1_default {
- function = "LAD1";
- groups = "LAD1";
- };
+ pinctrl_adc0_default: adc0_default {
+ function = "ADC0";
+ groups = "ADC0";
+ };
- pinctrl_lad2_default: lad2_default {
- function = "LAD2";
- groups = "LAD2";
- };
+ pinctrl_adc1_default: adc1_default {
+ function = "ADC1";
+ groups = "ADC1";
+ };
- pinctrl_lad3_default: lad3_default {
- function = "LAD3";
- groups = "LAD3";
- };
+ pinctrl_adc10_default: adc10_default {
+ function = "ADC10";
+ groups = "ADC10";
+ };
- pinctrl_lclk_default: lclk_default {
- function = "LCLK";
- groups = "LCLK";
- };
+ pinctrl_adc11_default: adc11_default {
+ function = "ADC11";
+ groups = "ADC11";
+ };
- pinctrl_lframe_default: lframe_default {
- function = "LFRAME";
- groups = "LFRAME";
- };
+ pinctrl_adc12_default: adc12_default {
+ function = "ADC12";
+ groups = "ADC12";
+ };
- pinctrl_lpchc_default: lpchc_default {
- function = "LPCHC";
- groups = "LPCHC";
- };
+ pinctrl_adc13_default: adc13_default {
+ function = "ADC13";
+ groups = "ADC13";
+ };
- pinctrl_lpcpd_default: lpcpd_default {
- function = "LPCPD";
- groups = "LPCPD";
- };
+ pinctrl_adc14_default: adc14_default {
+ function = "ADC14";
+ groups = "ADC14";
+ };
- pinctrl_lpcplus_default: lpcplus_default {
- function = "LPCPLUS";
- groups = "LPCPLUS";
- };
+ pinctrl_adc15_default: adc15_default {
+ function = "ADC15";
+ groups = "ADC15";
+ };
- pinctrl_lpcpme_default: lpcpme_default {
- function = "LPCPME";
- groups = "LPCPME";
- };
+ pinctrl_adc2_default: adc2_default {
+ function = "ADC2";
+ groups = "ADC2";
+ };
- pinctrl_lpcrst_default: lpcrst_default {
- function = "LPCRST";
- groups = "LPCRST";
- };
+ pinctrl_adc3_default: adc3_default {
+ function = "ADC3";
+ groups = "ADC3";
+ };
- pinctrl_lpcsmi_default: lpcsmi_default {
- function = "LPCSMI";
- groups = "LPCSMI";
- };
+ pinctrl_adc4_default: adc4_default {
+ function = "ADC4";
+ groups = "ADC4";
+ };
- pinctrl_lsirq_default: lsirq_default {
- function = "LSIRQ";
- groups = "LSIRQ";
- };
+ pinctrl_adc5_default: adc5_default {
+ function = "ADC5";
+ groups = "ADC5";
+ };
- pinctrl_mac1link_default: mac1link_default {
- function = "MAC1LINK";
- groups = "MAC1LINK";
- };
+ pinctrl_adc6_default: adc6_default {
+ function = "ADC6";
+ groups = "ADC6";
+ };
- pinctrl_mac2link_default: mac2link_default {
- function = "MAC2LINK";
- groups = "MAC2LINK";
- };
+ pinctrl_adc7_default: adc7_default {
+ function = "ADC7";
+ groups = "ADC7";
+ };
- pinctrl_mdio1_default: mdio1_default {
- function = "MDIO1";
- groups = "MDIO1";
- };
+ pinctrl_adc8_default: adc8_default {
+ function = "ADC8";
+ groups = "ADC8";
+ };
- pinctrl_mdio2_default: mdio2_default {
- function = "MDIO2";
- groups = "MDIO2";
- };
+ pinctrl_adc9_default: adc9_default {
+ function = "ADC9";
+ groups = "ADC9";
+ };
- pinctrl_ncts1_default: ncts1_default {
- function = "NCTS1";
- groups = "NCTS1";
- };
+ pinctrl_bmcint_default: bmcint_default {
+ function = "BMCINT";
+ groups = "BMCINT";
+ };
- pinctrl_ncts2_default: ncts2_default {
- function = "NCTS2";
- groups = "NCTS2";
- };
+ pinctrl_ddcclk_default: ddcclk_default {
+ function = "DDCCLK";
+ groups = "DDCCLK";
+ };
- pinctrl_ncts3_default: ncts3_default {
- function = "NCTS3";
- groups = "NCTS3";
- };
+ pinctrl_ddcdat_default: ddcdat_default {
+ function = "DDCDAT";
+ groups = "DDCDAT";
+ };
- pinctrl_ncts4_default: ncts4_default {
- function = "NCTS4";
- groups = "NCTS4";
- };
+ pinctrl_espi_default: espi_default {
+ function = "ESPI";
+ groups = "ESPI";
+ };
- pinctrl_ndcd1_default: ndcd1_default {
- function = "NDCD1";
- groups = "NDCD1";
- };
+ pinctrl_fwspics1_default: fwspics1_default {
+ function = "FWSPICS1";
+ groups = "FWSPICS1";
+ };
- pinctrl_ndcd2_default: ndcd2_default {
- function = "NDCD2";
- groups = "NDCD2";
- };
+ pinctrl_fwspics2_default: fwspics2_default {
+ function = "FWSPICS2";
+ groups = "FWSPICS2";
+ };
- pinctrl_ndcd3_default: ndcd3_default {
- function = "NDCD3";
- groups = "NDCD3";
- };
+ pinctrl_gpid0_default: gpid0_default {
+ function = "GPID0";
+ groups = "GPID0";
+ };
- pinctrl_ndcd4_default: ndcd4_default {
- function = "NDCD4";
- groups = "NDCD4";
- };
+ pinctrl_gpid2_default: gpid2_default {
+ function = "GPID2";
+ groups = "GPID2";
+ };
- pinctrl_ndsr1_default: ndsr1_default {
- function = "NDSR1";
- groups = "NDSR1";
- };
+ pinctrl_gpid4_default: gpid4_default {
+ function = "GPID4";
+ groups = "GPID4";
+ };
- pinctrl_ndsr2_default: ndsr2_default {
- function = "NDSR2";
- groups = "NDSR2";
- };
+ pinctrl_gpid6_default: gpid6_default {
+ function = "GPID6";
+ groups = "GPID6";
+ };
- pinctrl_ndsr3_default: ndsr3_default {
- function = "NDSR3";
- groups = "NDSR3";
- };
+ pinctrl_gpie0_default: gpie0_default {
+ function = "GPIE0";
+ groups = "GPIE0";
+ };
- pinctrl_ndsr4_default: ndsr4_default {
- function = "NDSR4";
- groups = "NDSR4";
- };
+ pinctrl_gpie2_default: gpie2_default {
+ function = "GPIE2";
+ groups = "GPIE2";
+ };
- pinctrl_ndtr1_default: ndtr1_default {
- function = "NDTR1";
- groups = "NDTR1";
- };
+ pinctrl_gpie4_default: gpie4_default {
+ function = "GPIE4";
+ groups = "GPIE4";
+ };
- pinctrl_ndtr2_default: ndtr2_default {
- function = "NDTR2";
- groups = "NDTR2";
- };
+ pinctrl_gpie6_default: gpie6_default {
+ function = "GPIE6";
+ groups = "GPIE6";
+ };
- pinctrl_ndtr3_default: ndtr3_default {
- function = "NDTR3";
- groups = "NDTR3";
- };
+ pinctrl_i2c10_default: i2c10_default {
+ function = "I2C10";
+ groups = "I2C10";
+ };
- pinctrl_ndtr4_default: ndtr4_default {
- function = "NDTR4";
- groups = "NDTR4";
- };
+ pinctrl_i2c11_default: i2c11_default {
+ function = "I2C11";
+ groups = "I2C11";
+ };
- pinctrl_nri1_default: nri1_default {
- function = "NRI1";
- groups = "NRI1";
- };
+ pinctrl_i2c12_default: i2c12_default {
+ function = "I2C12";
+ groups = "I2C12";
+ };
- pinctrl_nri2_default: nri2_default {
- function = "NRI2";
- groups = "NRI2";
- };
+ pinctrl_i2c13_default: i2c13_default {
+ function = "I2C13";
+ groups = "I2C13";
+ };
- pinctrl_nri3_default: nri3_default {
- function = "NRI3";
- groups = "NRI3";
- };
+ pinctrl_i2c14_default: i2c14_default {
+ function = "I2C14";
+ groups = "I2C14";
+ };
- pinctrl_nri4_default: nri4_default {
- function = "NRI4";
- groups = "NRI4";
- };
+ pinctrl_i2c3_default: i2c3_default {
+ function = "I2C3";
+ groups = "I2C3";
+ };
- pinctrl_nrts1_default: nrts1_default {
- function = "NRTS1";
- groups = "NRTS1";
- };
+ pinctrl_i2c4_default: i2c4_default {
+ function = "I2C4";
+ groups = "I2C4";
+ };
- pinctrl_nrts2_default: nrts2_default {
- function = "NRTS2";
- groups = "NRTS2";
- };
+ pinctrl_i2c5_default: i2c5_default {
+ function = "I2C5";
+ groups = "I2C5";
+ };
- pinctrl_nrts3_default: nrts3_default {
- function = "NRTS3";
- groups = "NRTS3";
- };
+ pinctrl_i2c6_default: i2c6_default {
+ function = "I2C6";
+ groups = "I2C6";
+ };
- pinctrl_nrts4_default: nrts4_default {
- function = "NRTS4";
- groups = "NRTS4";
- };
+ pinctrl_i2c7_default: i2c7_default {
+ function = "I2C7";
+ groups = "I2C7";
+ };
- pinctrl_oscclk_default: oscclk_default {
- function = "OSCCLK";
- groups = "OSCCLK";
- };
+ pinctrl_i2c8_default: i2c8_default {
+ function = "I2C8";
+ groups = "I2C8";
+ };
- pinctrl_pewake_default: pewake_default {
- function = "PEWAKE";
- groups = "PEWAKE";
- };
+ pinctrl_i2c9_default: i2c9_default {
+ function = "I2C9";
+ groups = "I2C9";
+ };
- pinctrl_pnor_default: pnor_default {
- function = "PNOR";
- groups = "PNOR";
- };
+ pinctrl_lad0_default: lad0_default {
+ function = "LAD0";
+ groups = "LAD0";
+ };
- pinctrl_pwm0_default: pwm0_default {
- function = "PWM0";
- groups = "PWM0";
- };
+ pinctrl_lad1_default: lad1_default {
+ function = "LAD1";
+ groups = "LAD1";
+ };
- pinctrl_pwm1_default: pwm1_default {
- function = "PWM1";
- groups = "PWM1";
- };
+ pinctrl_lad2_default: lad2_default {
+ function = "LAD2";
+ groups = "LAD2";
+ };
- pinctrl_pwm2_default: pwm2_default {
- function = "PWM2";
- groups = "PWM2";
- };
+ pinctrl_lad3_default: lad3_default {
+ function = "LAD3";
+ groups = "LAD3";
+ };
- pinctrl_pwm3_default: pwm3_default {
- function = "PWM3";
- groups = "PWM3";
- };
+ pinctrl_lclk_default: lclk_default {
+ function = "LCLK";
+ groups = "LCLK";
+ };
- pinctrl_pwm4_default: pwm4_default {
- function = "PWM4";
- groups = "PWM4";
- };
+ pinctrl_lframe_default: lframe_default {
+ function = "LFRAME";
+ groups = "LFRAME";
+ };
- pinctrl_pwm5_default: pwm5_default {
- function = "PWM5";
- groups = "PWM5";
- };
+ pinctrl_lpchc_default: lpchc_default {
+ function = "LPCHC";
+ groups = "LPCHC";
+ };
- pinctrl_pwm6_default: pwm6_default {
- function = "PWM6";
- groups = "PWM6";
- };
+ pinctrl_lpcpd_default: lpcpd_default {
+ function = "LPCPD";
+ groups = "LPCPD";
+ };
- pinctrl_pwm7_default: pwm7_default {
- function = "PWM7";
- groups = "PWM7";
- };
+ pinctrl_lpcplus_default: lpcplus_default {
+ function = "LPCPLUS";
+ groups = "LPCPLUS";
+ };
- pinctrl_rgmii1_default: rgmii1_default {
- function = "RGMII1";
- groups = "RGMII1";
- };
+ pinctrl_lpcpme_default: lpcpme_default {
+ function = "LPCPME";
+ groups = "LPCPME";
+ };
- pinctrl_rgmii2_default: rgmii2_default {
- function = "RGMII2";
- groups = "RGMII2";
- };
+ pinctrl_lpcrst_default: lpcrst_default {
+ function = "LPCRST";
+ groups = "LPCRST";
+ };
- pinctrl_rmii1_default: rmii1_default {
- function = "RMII1";
- groups = "RMII1";
- };
+ pinctrl_lpcsmi_default: lpcsmi_default {
+ function = "LPCSMI";
+ groups = "LPCSMI";
+ };
- pinctrl_rmii2_default: rmii2_default {
- function = "RMII2";
- groups = "RMII2";
- };
+ pinctrl_lsirq_default: lsirq_default {
+ function = "LSIRQ";
+ groups = "LSIRQ";
+ };
- pinctrl_rxd1_default: rxd1_default {
- function = "RXD1";
- groups = "RXD1";
- };
+ pinctrl_mac1link_default: mac1link_default {
+ function = "MAC1LINK";
+ groups = "MAC1LINK";
+ };
- pinctrl_rxd2_default: rxd2_default {
- function = "RXD2";
- groups = "RXD2";
- };
+ pinctrl_mac2link_default: mac2link_default {
+ function = "MAC2LINK";
+ groups = "MAC2LINK";
+ };
- pinctrl_rxd3_default: rxd3_default {
- function = "RXD3";
- groups = "RXD3";
- };
+ pinctrl_mdio1_default: mdio1_default {
+ function = "MDIO1";
+ groups = "MDIO1";
+ };
- pinctrl_rxd4_default: rxd4_default {
- function = "RXD4";
- groups = "RXD4";
- };
+ pinctrl_mdio2_default: mdio2_default {
+ function = "MDIO2";
+ groups = "MDIO2";
+ };
- pinctrl_salt1_default: salt1_default {
- function = "SALT1";
- groups = "SALT1";
- };
+ pinctrl_ncts1_default: ncts1_default {
+ function = "NCTS1";
+ groups = "NCTS1";
+ };
- pinctrl_salt10_default: salt10_default {
- function = "SALT10";
- groups = "SALT10";
- };
+ pinctrl_ncts2_default: ncts2_default {
+ function = "NCTS2";
+ groups = "NCTS2";
+ };
- pinctrl_salt11_default: salt11_default {
- function = "SALT11";
- groups = "SALT11";
- };
+ pinctrl_ncts3_default: ncts3_default {
+ function = "NCTS3";
+ groups = "NCTS3";
+ };
- pinctrl_salt12_default: salt12_default {
- function = "SALT12";
- groups = "SALT12";
- };
+ pinctrl_ncts4_default: ncts4_default {
+ function = "NCTS4";
+ groups = "NCTS4";
+ };
- pinctrl_salt13_default: salt13_default {
- function = "SALT13";
- groups = "SALT13";
- };
+ pinctrl_ndcd1_default: ndcd1_default {
+ function = "NDCD1";
+ groups = "NDCD1";
+ };
- pinctrl_salt14_default: salt14_default {
- function = "SALT14";
- groups = "SALT14";
- };
+ pinctrl_ndcd2_default: ndcd2_default {
+ function = "NDCD2";
+ groups = "NDCD2";
+ };
- pinctrl_salt2_default: salt2_default {
- function = "SALT2";
- groups = "SALT2";
- };
+ pinctrl_ndcd3_default: ndcd3_default {
+ function = "NDCD3";
+ groups = "NDCD3";
+ };
- pinctrl_salt3_default: salt3_default {
- function = "SALT3";
- groups = "SALT3";
- };
+ pinctrl_ndcd4_default: ndcd4_default {
+ function = "NDCD4";
+ groups = "NDCD4";
+ };
- pinctrl_salt4_default: salt4_default {
- function = "SALT4";
- groups = "SALT4";
- };
+ pinctrl_ndsr1_default: ndsr1_default {
+ function = "NDSR1";
+ groups = "NDSR1";
+ };
- pinctrl_salt5_default: salt5_default {
- function = "SALT5";
- groups = "SALT5";
- };
+ pinctrl_ndsr2_default: ndsr2_default {
+ function = "NDSR2";
+ groups = "NDSR2";
+ };
- pinctrl_salt6_default: salt6_default {
- function = "SALT6";
- groups = "SALT6";
- };
+ pinctrl_ndsr3_default: ndsr3_default {
+ function = "NDSR3";
+ groups = "NDSR3";
+ };
- pinctrl_salt7_default: salt7_default {
- function = "SALT7";
- groups = "SALT7";
- };
+ pinctrl_ndsr4_default: ndsr4_default {
+ function = "NDSR4";
+ groups = "NDSR4";
+ };
- pinctrl_salt8_default: salt8_default {
- function = "SALT8";
- groups = "SALT8";
- };
+ pinctrl_ndtr1_default: ndtr1_default {
+ function = "NDTR1";
+ groups = "NDTR1";
+ };
- pinctrl_salt9_default: salt9_default {
- function = "SALT9";
- groups = "SALT9";
- };
+ pinctrl_ndtr2_default: ndtr2_default {
+ function = "NDTR2";
+ groups = "NDTR2";
+ };
- pinctrl_scl1_default: scl1_default {
- function = "SCL1";
- groups = "SCL1";
- };
+ pinctrl_ndtr3_default: ndtr3_default {
+ function = "NDTR3";
+ groups = "NDTR3";
+ };
- pinctrl_scl2_default: scl2_default {
- function = "SCL2";
- groups = "SCL2";
- };
+ pinctrl_ndtr4_default: ndtr4_default {
+ function = "NDTR4";
+ groups = "NDTR4";
+ };
- pinctrl_sd1_default: sd1_default {
- function = "SD1";
- groups = "SD1";
- };
+ pinctrl_nri1_default: nri1_default {
+ function = "NRI1";
+ groups = "NRI1";
+ };
- pinctrl_sd2_default: sd2_default {
- function = "SD2";
- groups = "SD2";
- };
+ pinctrl_nri2_default: nri2_default {
+ function = "NRI2";
+ groups = "NRI2";
+ };
- pinctrl_sda1_default: sda1_default {
- function = "SDA1";
- groups = "SDA1";
- };
+ pinctrl_nri3_default: nri3_default {
+ function = "NRI3";
+ groups = "NRI3";
+ };
- pinctrl_sda2_default: sda2_default {
- function = "SDA2";
- groups = "SDA2";
- };
+ pinctrl_nri4_default: nri4_default {
+ function = "NRI4";
+ groups = "NRI4";
+ };
- pinctrl_sgps1_default: sgps1_default {
- function = "SGPS1";
- groups = "SGPS1";
- };
+ pinctrl_nrts1_default: nrts1_default {
+ function = "NRTS1";
+ groups = "NRTS1";
+ };
- pinctrl_sgps2_default: sgps2_default {
- function = "SGPS2";
- groups = "SGPS2";
- };
+ pinctrl_nrts2_default: nrts2_default {
+ function = "NRTS2";
+ groups = "NRTS2";
+ };
- pinctrl_sioonctrl_default: sioonctrl_default {
- function = "SIOONCTRL";
- groups = "SIOONCTRL";
- };
+ pinctrl_nrts3_default: nrts3_default {
+ function = "NRTS3";
+ groups = "NRTS3";
+ };
- pinctrl_siopbi_default: siopbi_default {
- function = "SIOPBI";
- groups = "SIOPBI";
- };
+ pinctrl_nrts4_default: nrts4_default {
+ function = "NRTS4";
+ groups = "NRTS4";
+ };
- pinctrl_siopbo_default: siopbo_default {
- function = "SIOPBO";
- groups = "SIOPBO";
- };
+ pinctrl_oscclk_default: oscclk_default {
+ function = "OSCCLK";
+ groups = "OSCCLK";
+ };
- pinctrl_siopwreq_default: siopwreq_default {
- function = "SIOPWREQ";
- groups = "SIOPWREQ";
- };
+ pinctrl_pewake_default: pewake_default {
+ function = "PEWAKE";
+ groups = "PEWAKE";
+ };
- pinctrl_siopwrgd_default: siopwrgd_default {
- function = "SIOPWRGD";
- groups = "SIOPWRGD";
- };
+ pinctrl_pnor_default: pnor_default {
+ function = "PNOR";
+ groups = "PNOR";
+ };
- pinctrl_sios3_default: sios3_default {
- function = "SIOS3";
- groups = "SIOS3";
- };
+ pinctrl_pwm0_default: pwm0_default {
+ function = "PWM0";
+ groups = "PWM0";
+ };
- pinctrl_sios5_default: sios5_default {
- function = "SIOS5";
- groups = "SIOS5";
- };
+ pinctrl_pwm1_default: pwm1_default {
+ function = "PWM1";
+ groups = "PWM1";
+ };
- pinctrl_siosci_default: siosci_default {
- function = "SIOSCI";
- groups = "SIOSCI";
- };
+ pinctrl_pwm2_default: pwm2_default {
+ function = "PWM2";
+ groups = "PWM2";
+ };
- pinctrl_spi1_default: spi1_default {
- function = "SPI1";
- groups = "SPI1";
- };
+ pinctrl_pwm3_default: pwm3_default {
+ function = "PWM3";
+ groups = "PWM3";
+ };
- pinctrl_spi1cs1_default: spi1cs1_default {
- function = "SPI1CS1";
- groups = "SPI1CS1";
- };
+ pinctrl_pwm4_default: pwm4_default {
+ function = "PWM4";
+ groups = "PWM4";
+ };
- pinctrl_spi1debug_default: spi1debug_default {
- function = "SPI1DEBUG";
- groups = "SPI1DEBUG";
- };
+ pinctrl_pwm5_default: pwm5_default {
+ function = "PWM5";
+ groups = "PWM5";
+ };
- pinctrl_spi1passthru_default: spi1passthru_default {
- function = "SPI1PASSTHRU";
- groups = "SPI1PASSTHRU";
- };
+ pinctrl_pwm6_default: pwm6_default {
+ function = "PWM6";
+ groups = "PWM6";
+ };
- pinctrl_spi2ck_default: spi2ck_default {
- function = "SPI2CK";
- groups = "SPI2CK";
- };
+ pinctrl_pwm7_default: pwm7_default {
+ function = "PWM7";
+ groups = "PWM7";
+ };
- pinctrl_spi2cs0_default: spi2cs0_default {
- function = "SPI2CS0";
- groups = "SPI2CS0";
- };
+ pinctrl_rgmii1_default: rgmii1_default {
+ function = "RGMII1";
+ groups = "RGMII1";
+ };
- pinctrl_spi2cs1_default: spi2cs1_default {
- function = "SPI2CS1";
- groups = "SPI2CS1";
- };
+ pinctrl_rgmii2_default: rgmii2_default {
+ function = "RGMII2";
+ groups = "RGMII2";
+ };
- pinctrl_spi2miso_default: spi2miso_default {
- function = "SPI2MISO";
- groups = "SPI2MISO";
- };
+ pinctrl_rmii1_default: rmii1_default {
+ function = "RMII1";
+ groups = "RMII1";
+ };
- pinctrl_spi2mosi_default: spi2mosi_default {
- function = "SPI2MOSI";
- groups = "SPI2MOSI";
- };
+ pinctrl_rmii2_default: rmii2_default {
+ function = "RMII2";
+ groups = "RMII2";
+ };
- pinctrl_timer3_default: timer3_default {
- function = "TIMER3";
- groups = "TIMER3";
- };
+ pinctrl_rxd1_default: rxd1_default {
+ function = "RXD1";
+ groups = "RXD1";
+ };
- pinctrl_timer4_default: timer4_default {
- function = "TIMER4";
- groups = "TIMER4";
- };
+ pinctrl_rxd2_default: rxd2_default {
+ function = "RXD2";
+ groups = "RXD2";
+ };
- pinctrl_timer5_default: timer5_default {
- function = "TIMER5";
- groups = "TIMER5";
- };
+ pinctrl_rxd3_default: rxd3_default {
+ function = "RXD3";
+ groups = "RXD3";
+ };
- pinctrl_timer6_default: timer6_default {
- function = "TIMER6";
- groups = "TIMER6";
- };
+ pinctrl_rxd4_default: rxd4_default {
+ function = "RXD4";
+ groups = "RXD4";
+ };
- pinctrl_timer7_default: timer7_default {
- function = "TIMER7";
- groups = "TIMER7";
- };
+ pinctrl_salt1_default: salt1_default {
+ function = "SALT1";
+ groups = "SALT1";
+ };
- pinctrl_timer8_default: timer8_default {
- function = "TIMER8";
- groups = "TIMER8";
- };
+ pinctrl_salt10_default: salt10_default {
+ function = "SALT10";
+ groups = "SALT10";
+ };
- pinctrl_txd1_default: txd1_default {
- function = "TXD1";
- groups = "TXD1";
- };
+ pinctrl_salt11_default: salt11_default {
+ function = "SALT11";
+ groups = "SALT11";
+ };
- pinctrl_txd2_default: txd2_default {
- function = "TXD2";
- groups = "TXD2";
- };
+ pinctrl_salt12_default: salt12_default {
+ function = "SALT12";
+ groups = "SALT12";
+ };
- pinctrl_txd3_default: txd3_default {
- function = "TXD3";
- groups = "TXD3";
- };
+ pinctrl_salt13_default: salt13_default {
+ function = "SALT13";
+ groups = "SALT13";
+ };
- pinctrl_txd4_default: txd4_default {
- function = "TXD4";
- groups = "TXD4";
- };
+ pinctrl_salt14_default: salt14_default {
+ function = "SALT14";
+ groups = "SALT14";
+ };
- pinctrl_uart6_default: uart6_default {
- function = "UART6";
- groups = "UART6";
- };
+ pinctrl_salt2_default: salt2_default {
+ function = "SALT2";
+ groups = "SALT2";
+ };
- pinctrl_usbcki_default: usbcki_default {
- function = "USBCKI";
- groups = "USBCKI";
- };
+ pinctrl_salt3_default: salt3_default {
+ function = "SALT3";
+ groups = "SALT3";
+ };
- pinctrl_vgabiosrom_default: vgabiosrom_default {
- function = "VGABIOSROM";
- groups = "VGABIOSROM";
- };
+ pinctrl_salt4_default: salt4_default {
+ function = "SALT4";
+ groups = "SALT4";
+ };
- pinctrl_vgahs_default: vgahs_default {
- function = "VGAHS";
- groups = "VGAHS";
- };
+ pinctrl_salt5_default: salt5_default {
+ function = "SALT5";
+ groups = "SALT5";
+ };
- pinctrl_vgavs_default: vgavs_default {
- function = "VGAVS";
- groups = "VGAVS";
- };
+ pinctrl_salt6_default: salt6_default {
+ function = "SALT6";
+ groups = "SALT6";
+ };
- pinctrl_vpi24_default: vpi24_default {
- function = "VPI24";
- groups = "VPI24";
- };
+ pinctrl_salt7_default: salt7_default {
+ function = "SALT7";
+ groups = "SALT7";
+ };
- pinctrl_vpo_default: vpo_default {
- function = "VPO";
- groups = "VPO";
- };
+ pinctrl_salt8_default: salt8_default {
+ function = "SALT8";
+ groups = "SALT8";
+ };
- pinctrl_wdtrst1_default: wdtrst1_default {
- function = "WDTRST1";
- groups = "WDTRST1";
- };
+ pinctrl_salt9_default: salt9_default {
+ function = "SALT9";
+ groups = "SALT9";
+ };
- pinctrl_wdtrst2_default: wdtrst2_default {
- function = "WDTRST2";
- groups = "WDTRST2";
- };
+ pinctrl_scl1_default: scl1_default {
+ function = "SCL1";
+ groups = "SCL1";
+ };
- };
- };
+ pinctrl_scl2_default: scl2_default {
+ function = "SCL2";
+ groups = "SCL2";
+ };
- clk_hpll: clk_hpll@1e6e2024 {
- #clock-cells = <0>;
- compatible = "aspeed,g5-hpll-clock";
- reg = <0x1e6e2024 0x4>;
- clocks = <&clk_clkin>;
- };
+ pinctrl_sd1_default: sd1_default {
+ function = "SD1";
+ groups = "SD1";
+ };
- clk_ahb: clk_ahb@1e6e2070 {
- #clock-cells = <0>;
- compatible = "aspeed,g5-ahb-clock";
- reg = <0x1e6e2070 0x4>;
- clocks = <&clk_hpll>;
- };
+ pinctrl_sd2_default: sd2_default {
+ function = "SD2";
+ groups = "SD2";
+ };
- clk_apb: clk_apb@1e6e2008 {
- #clock-cells = <0>;
- compatible = "aspeed,g5-apb-clock";
- reg = <0x1e6e2008 0x4>;
- clocks = <&clk_hpll>;
- };
+ pinctrl_sda1_default: sda1_default {
+ function = "SDA1";
+ groups = "SDA1";
+ };
- clk_uart: clk_uart@1e6e2008 {
- #clock-cells = <0>;
- compatible = "aspeed,uart-clock";
- reg = <0x1e6e202c 0x4>;
- };
+ pinctrl_sda2_default: sda2_default {
+ function = "SDA2";
+ groups = "SDA2";
+ };
- gfx: display@1e6e6000 {
- compatible = "aspeed,ast2500-gfx", "syscon";
- reg = <0x1e6e6000 0x1000>;
- reg-io-width = <4>;
- };
+ pinctrl_sgps1_default: sgps1_default {
+ function = "SGPS1";
+ groups = "SGPS1";
+ };
- sram@1e720000 {
- compatible = "mmio-sram";
- reg = <0x1e720000 0x9000>; // 36K
- };
+ pinctrl_sgps2_default: sgps2_default {
+ function = "SGPS2";
+ groups = "SGPS2";
+ };
- gpio: gpio@1e780000 {
- #gpio-cells = <2>;
- gpio-controller;
- compatible = "aspeed,ast2500-gpio";
- reg = <0x1e780000 0x1000>;
- interrupts = <20>;
- gpio-ranges = <&pinctrl 0 0 220>;
- interrupt-controller;
- };
+ pinctrl_sioonctrl_default: sioonctrl_default {
+ function = "SIOONCTRL";
+ groups = "SIOONCTRL";
+ };
- timer: timer@1e782000 {
- compatible = "aspeed,ast2400-timer";
- reg = <0x1e782000 0x90>;
- // The moxart_timer driver registers only one
- // interrupt and assumes it's for timer 1
- //interrupts = <16 17 18 35 36 37 38 39>;
- interrupts = <16>;
- clocks = <&clk_apb>;
- };
+ pinctrl_siopbi_default: siopbi_default {
+ function = "SIOPBI";
+ groups = "SIOPBI";
+ };
+ pinctrl_siopbo_default: siopbo_default {
+ function = "SIOPBO";
+ groups = "SIOPBO";
+ };
- wdt1: wdt@1e785000 {
- compatible = "aspeed,wdt";
- reg = <0x1e785000 0x1c>;
- interrupts = <27>;
- };
+ pinctrl_siopwreq_default: siopwreq_default {
+ function = "SIOPWREQ";
+ groups = "SIOPWREQ";
+ };
- wdt2: wdt@1e785020 {
- compatible = "aspeed,wdt";
- reg = <0x1e785020 0x1c>;
- interrupts = <27>;
- status = "disabled";
- };
+ pinctrl_siopwrgd_default: siopwrgd_default {
+ function = "SIOPWRGD";
+ groups = "SIOPWRGD";
+ };
- wdt3: wdt@1e785040 {
- compatible = "aspeed,wdt";
- reg = <0x1e785074 0x1c>;
- status = "disabled";
- };
+ pinctrl_sios3_default: sios3_default {
+ function = "SIOS3";
+ groups = "SIOS3";
+ };
- uart1: serial@1e783000 {
- compatible = "ns16550a";
- reg = <0x1e783000 0x1000>;
- reg-shift = <2>;
- interrupts = <9>;
- clocks = <&clk_uart>;
- no-loopback-test;
- status = "disabled";
- };
+ pinctrl_sios5_default: sios5_default {
+ function = "SIOS5";
+ groups = "SIOS5";
+ };
- lpc: lpc@1e789000 {
- compatible = "aspeed,ast2500-lpc", "simple-mfd";
- reg = <0x1e789000 0x1000>;
+ pinctrl_siosci_default: siosci_default {
+ function = "SIOSCI";
+ groups = "SIOSCI";
+ };
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x1e789000 0x1000>;
+ pinctrl_spi1_default: spi1_default {
+ function = "SPI1";
+ groups = "SPI1";
+ };
- lpc_bmc: lpc-bmc@0 {
- compatible = "aspeed,ast2500-lpc-bmc";
- reg = <0x0 0x80>;
- };
+ pinctrl_spi1cs1_default: spi1cs1_default {
+ function = "SPI1CS1";
+ groups = "SPI1CS1";
+ };
- lpc_host: lpc-host@80 {
- compatible = "aspeed,ast2500-lpc-host", "simple-mfd", "syscon";
- reg = <0x80 0x1e0>;
+ pinctrl_spi1debug_default: spi1debug_default {
+ function = "SPI1DEBUG";
+ groups = "SPI1DEBUG";
+ };
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x80 0x1e0>;
+ pinctrl_spi1passthru_default: spi1passthru_default {
+ function = "SPI1PASSTHRU";
+ groups = "SPI1PASSTHRU";
+ };
- reg-io-width = <4>;
+ pinctrl_spi2ck_default: spi2ck_default {
+ function = "SPI2CK";
+ groups = "SPI2CK";
+ };
- lhc: lhc@20 {
- compatible = "aspeed,ast2500-lhc";
- reg = <0x20 0x24 0x48 0x8>;
- };
- };
- };
+ pinctrl_spi2cs0_default: spi2cs0_default {
+ function = "SPI2CS0";
+ groups = "SPI2CS0";
+ };
- uart2: serial@1e78d000 {
- compatible = "ns16550a";
- reg = <0x1e78d000 0x1000>;
- reg-shift = <2>;
- interrupts = <32>;
- clocks = <&clk_uart>;
- no-loopback-test;
- status = "disabled";
- };
+ pinctrl_spi2cs1_default: spi2cs1_default {
+ function = "SPI2CS1";
+ groups = "SPI2CS1";
+ };
- uart3: serial@1e78e000 {
- compatible = "ns16550a";
- reg = <0x1e78e000 0x1000>;
- reg-shift = <2>;
- interrupts = <33>;
- clocks = <&clk_uart>;
- no-loopback-test;
- status = "disabled";
- };
+ pinctrl_spi2miso_default: spi2miso_default {
+ function = "SPI2MISO";
+ groups = "SPI2MISO";
+ };
- uart4: serial@1e78f000 {
- compatible = "ns16550a";
- reg = <0x1e78f000 0x1000>;
- reg-shift = <2>;
- interrupts = <34>;
- clocks = <&clk_uart>;
- no-loopback-test;
- status = "disabled";
- };
+ pinctrl_spi2mosi_default: spi2mosi_default {
+ function = "SPI2MOSI";
+ groups = "SPI2MOSI";
+ };
- uart5: serial@1e784000 {
- compatible = "ns16550a";
- reg = <0x1e784000 0x1000>;
- reg-shift = <2>;
- interrupts = <10>;
- clocks = <&clk_uart>;
- current-speed = <38400>;
- no-loopback-test;
- status = "disabled";
- };
+ pinctrl_timer3_default: timer3_default {
+ function = "TIMER3";
+ groups = "TIMER3";
+ };
- uart6: serial@1e787000 {
- compatible = "ns16550a";
- reg = <0x1e787000 0x1000>;
- reg-shift = <2>;
- interrupts = <10>;
- clocks = <&clk_uart>;
- no-loopback-test;
- status = "disabled";
- };
- };
+ pinctrl_timer4_default: timer4_default {
+ function = "TIMER4";
+ groups = "TIMER4";
+ };
+
+ pinctrl_timer5_default: timer5_default {
+ function = "TIMER5";
+ groups = "TIMER5";
+ };
+
+ pinctrl_timer6_default: timer6_default {
+ function = "TIMER6";
+ groups = "TIMER6";
+ };
+
+ pinctrl_timer7_default: timer7_default {
+ function = "TIMER7";
+ groups = "TIMER7";
+ };
+
+ pinctrl_timer8_default: timer8_default {
+ function = "TIMER8";
+ groups = "TIMER8";
+ };
+
+ pinctrl_txd1_default: txd1_default {
+ function = "TXD1";
+ groups = "TXD1";
+ };
+
+ pinctrl_txd2_default: txd2_default {
+ function = "TXD2";
+ groups = "TXD2";
+ };
+
+ pinctrl_txd3_default: txd3_default {
+ function = "TXD3";
+ groups = "TXD3";
+ };
+
+ pinctrl_txd4_default: txd4_default {
+ function = "TXD4";
+ groups = "TXD4";
+ };
+
+ pinctrl_uart6_default: uart6_default {
+ function = "UART6";
+ groups = "UART6";
+ };
+
+ pinctrl_usbcki_default: usbcki_default {
+ function = "USBCKI";
+ groups = "USBCKI";
+ };
+
+ pinctrl_usb2ah_default: usb2ah_default {
+ function = "USB2AH";
+ groups = "USB2AH";
+ };
+
+ pinctrl_usb11bhid_default: usb11bhid_default {
+ function = "USB11BHID";
+ groups = "USB11BHID";
+ };
+
+ pinctrl_usb2bh_default: usb2bh_default {
+ function = "USB2BH";
+ groups = "USB2BH";
+ };
+
+ pinctrl_vgabiosrom_default: vgabiosrom_default {
+ function = "VGABIOSROM";
+ groups = "VGABIOSROM";
+ };
+
+ pinctrl_vgahs_default: vgahs_default {
+ function = "VGAHS";
+ groups = "VGAHS";
+ };
+
+ pinctrl_vgavs_default: vgavs_default {
+ function = "VGAVS";
+ groups = "VGAVS";
+ };
+
+ pinctrl_vpi24_default: vpi24_default {
+ function = "VPI24";
+ groups = "VPI24";
+ };
+
+ pinctrl_vpo_default: vpo_default {
+ function = "VPO";
+ groups = "VPO";
+ };
+
+ pinctrl_wdtrst1_default: wdtrst1_default {
+ function = "WDTRST1";
+ groups = "WDTRST1";
+ };
+
+ pinctrl_wdtrst2_default: wdtrst2_default {
+ function = "WDTRST2";
+ groups = "WDTRST2";
};
};
stdout-path = &lpuart0;
};
- regulators {
- compatible = "simple-bus";
-
- reg_usdhc2_vmmc: usdhc2-vmmc {
- compatible = "regulator-fixed";
- regulator-name = "SD1_SPWR";
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- gpio = <&gpio4 19 GPIO_ACTIVE_HIGH>;
- off-on-delay = <3480>;
- enable-active-high;
- };
+ reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
+ compatible = "regulator-fixed";
+ regulator-name = "SD1_SPWR";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ gpio = <&gpio4 19 GPIO_ACTIVE_HIGH>;
+ off-on-delay = <3480>;
+ enable-active-high;
};
};
/* MDIO clock output frequency */
#define EMAC_MDIO_CLOCK_FREQ 2500000 /* 2.5 MHz */
-/* MII Status Register */
-#define MII_STATUS_REG 1
-#define MII_STATUS_LINK_MASK 0x4
-
-#define MDIO_CONTROL_IDLE 0x80000000
-#define MDIO_CONTROL_ENABLE 0x40000000
-#define MDIO_CONTROL_FAULT_ENABLE 0x40000
-#define MDIO_CONTROL_FAULT 0x80000
-#define MDIO_USERACCESS0_GO 0x80000000
-#define MDIO_USERACCESS0_WRITE_READ 0x0
-#define MDIO_USERACCESS0_WRITE_WRITE 0x40000000
-#define MDIO_USERACCESS0_ACK 0x20000000
-
#define EMAC_MACCONTROL_MIIEN_ENABLE 0x20
#define EMAC_MACCONTROL_FULLDUPLEX_ENABLE 0x1
#define EMAC_MACCONTROL_GIGABIT_ENABLE BIT(7)
u32 userphysel1;
};
-struct eth_priv_t {
- char int_name[32];
- int rx_flow;
- int phy_addr;
- int slave_port;
- int sgmii_link_type;
- phy_interface_t phy_if;
- struct phy_device *phy_dev;
-};
-
-int keystone2_emac_initialize(struct eth_priv_t *eth_priv);
-void sgmii_serdes_setup_156p25mhz(void);
-void sgmii_serdes_shutdown(void);
-
#endif /* _KEYSTONE_NET_H_ */
#include <net.h>
#include <dp83848.h>
#include <asm/arch/emac_defs.h>
-#include "../../../drivers/net/davinci_emac.h"
+#include "../../../drivers/net/ti/davinci_emac.h"
#ifdef CONFIG_DRIVER_TI_EMAC
#include <net.h>
#include <miiphy.h>
#include <asm/arch/emac_defs.h>
-#include "../../../drivers/net/davinci_emac.h"
+#include "../../../drivers/net/ti/davinci_emac.h"
#ifdef CONFIG_DRIVER_TI_EMAC
#include <net.h>
#include <asm/arch/emac_defs.h>
#include <asm/io.h>
-#include "../../../drivers/net/davinci_emac.h"
+#include "../../../drivers/net/ti/davinci_emac.h"
int ksz8873_is_phy_connected(int phy_addr)
{
#include <miiphy.h>
#include <lxt971a.h>
#include <asm/arch/emac_defs.h>
-#include "../../../drivers/net/davinci_emac.h"
+#include "../../../drivers/net/ti/davinci_emac.h"
#ifdef CONFIG_DRIVER_TI_EMAC
obj-$(CONFIG_CMD_DEKBLOB) += cmd_dek.o
endif
+ifneq ($(CONFIG_BOARD_SIZE_LIMIT),)
+BOARD_SIZE_CHECK = \
+ @actual=`wc -c $@ | awk '{print $$1}'`; \
+ limit=`printf "%d" $(CONFIG_BOARD_SIZE_LIMIT)`; \
+ if test $$actual -gt $$limit; then \
+ echo "$@ exceeds file size limit:" >&2 ; \
+ echo " limit: $$limit bytes" >&2 ; \
+ echo " actual: $$actual bytes" >&2 ; \
+ echo " excess: $$((actual - limit)) bytes" >&2; \
+ exit 1; \
+ fi
+else
+BOARD_SIZE_CHECK =
+endif
+
PLUGIN = board/$(BOARDDIR)/plugin
ifeq ($(CONFIG_USE_IMXIMG_PLUGIN),y)
u-boot.imx: u-boot.bin u-boot.cfgout $(PLUGIN).bin FORCE
$(call if_changed,mkimage)
+ $(BOARD_SIZE_CHECK)
ifeq ($(CONFIG_OF_SEPARATE),y)
MKIMAGEFLAGS_u-boot-dtb.imx = -n $(filter-out $(PLUGIN).bin $< $(PHONY),$^) \
{
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+ /*
+ * If this function is used in a common MX6 spl implementation
+ * we have to ensure that it is only called for suitable cpu types,
+ * otherwise it breaks hardware parts like enet1, can1, can2, etc.
+ */
+ if (!is_mx6dqp() && !is_mx6dq() && !is_mx6sdl())
+ return;
+
/* enable AXI cache for VDOA/VPU/IPU */
writel(0xF00000CF, &iomux->gpr[4]);
if (is_mx6dqp()) {
#define REG_CPUCS_WIN_WIN0_CS(x) (((x) & 0x3) << 2)
#define REG_CPUCS_WIN_SIZE(x) (((x) & 0xff) << 24)
-#define SDRAM_SIZE_MAX 0xc0000000
+#ifndef MVEBU_SDRAM_SIZE_MAX
+#define MVEBU_SDRAM_SIZE_MAX 0xc0000000
+#endif
#define SCRUB_MAGIC 0xbeefdead
* address space left for the internal registers etc.
*/
size += mvebu_sdram_bs(i);
- if (size > SDRAM_SIZE_MAX)
- size = SDRAM_SIZE_MAX;
+ if (size > MVEBU_SDRAM_SIZE_MAX)
+ size = MVEBU_SDRAM_SIZE_MAX;
}
for (; i < CONFIG_NR_DRAM_BANKS; i++) {
/* Clip the banksize to 1GiB if it exceeds the max size */
size += gd->bd->bi_dram[i].size;
- if (size > SDRAM_SIZE_MAX)
+ if (size > MVEBU_SDRAM_SIZE_MAX)
mvebu_sdram_bs_set(i, 0x40000000);
}
MVEBU_SOC_UNKNOWN,
};
+#define MVEBU_SDRAM_SIZE_MAX 0xc0000000
+
/*
* Default Device Address MAP BAR values
*/
-#define MBUS_PCI_MEM_BASE 0xE8000000
+#define MBUS_PCI_MEM_BASE MVEBU_SDRAM_SIZE_MAX
#define MBUS_PCI_MEM_SIZE (128 << 20)
#define MBUS_PCI_IO_BASE 0xF1100000
#define MBUS_PCI_IO_SIZE (64 << 10)
#include <common.h>
#include <asm/io.h>
+/* R-Car Gen3 caches are enabled in memmap-gen3.c */
+#ifndef CONFIG_RCAR_GEN3
#ifdef CONFIG_ARCH_CPU_INIT
int arch_cpu_init(void)
{
dcache_enable();
}
#endif
+#endif
#ifdef CONFIG_DISPLAY_CPUINFO
static u32 __rmobile_get_cpu_type(void)
#include <common.h>
#include <asm/armv8/mmu.h>
-static struct mm_region gen3_mem_map[] = {
+#define GEN3_NR_REGIONS 16
+
+static struct mm_region gen3_mem_map[GEN3_NR_REGIONS] = {
{
.virt = 0x0UL,
.phys = 0x0UL,
};
struct mm_region *mem_map = gen3_mem_map;
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void enable_caches(void)
+{
+ u64 start, size;
+ int bank, i = 0;
+
+ /* Create map for RPC access */
+ gen3_mem_map[i].virt = 0x0ULL;
+ gen3_mem_map[i].phys = 0x0ULL;
+ gen3_mem_map[i].size = 0x40000000ULL;
+ gen3_mem_map[i].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN;
+ i++;
+
+ /* Generate entires for DRAM in 32bit address space */
+ for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
+ start = gd->bd->bi_dram[bank].start;
+ size = gd->bd->bi_dram[bank].size;
+
+ /* Skip empty DRAM banks */
+ if (!size)
+ continue;
+
+ /* Skip DRAM above 4 GiB */
+ if (start >> 32ULL)
+ continue;
+
+ /* Mark memory reserved by ATF as cacheable too. */
+ if (start == 0x48000000) {
+ start = 0x40000000ULL;
+ size += 0x08000000ULL;
+ }
+
+ gen3_mem_map[i].virt = start;
+ gen3_mem_map[i].phys = start;
+ gen3_mem_map[i].size = size;
+ gen3_mem_map[i].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE;
+ i++;
+ }
+
+ /* Create map for register access */
+ gen3_mem_map[i].virt = 0xc0000000ULL;
+ gen3_mem_map[i].phys = 0xc0000000ULL;
+ gen3_mem_map[i].size = 0x40000000ULL;
+ gen3_mem_map[i].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN;
+ i++;
+
+ /* Generate entires for DRAM in 64bit address space */
+ for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
+ start = gd->bd->bi_dram[bank].start;
+ size = gd->bd->bi_dram[bank].size;
+
+ /* Skip empty DRAM banks */
+ if (!size)
+ continue;
+
+ /* Skip DRAM below 4 GiB */
+ if (!(start >> 32ULL))
+ continue;
+
+ gen3_mem_map[i].virt = start;
+ gen3_mem_map[i].phys = start;
+ gen3_mem_map[i].size = size;
+ gen3_mem_map[i].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE;
+ i++;
+ }
+
+ /* Zero out the remaining regions. */
+ for (; i < GEN3_NR_REGIONS; i++) {
+ gen3_mem_map[i].virt = 0;
+ gen3_mem_map[i].phys = 0;
+ gen3_mem_map[i].size = 0;
+ gen3_mem_map[i].attrs = 0;
+ }
+
+ icache_enable();
+ dcache_enable();
+}
Normally this is CKSEG0. If the MIPS system needs to move this block
to some SRAM or ScratchPad RAM, adapt this option accordingly.
+config MIPS_RELOCATION_TABLE_SIZE
+ hex "Relocation table size"
+ range 0x100 0x10000
+ default "0x8000"
+ ---help---
+ A table of relocation data will be appended to the U-Boot binary
+ and parsed in relocate_code() to fix up all offsets in the relocated
+ U-Boot.
+
+ This option allows the amount of space reserved for the table to be
+ adjusted in a range from 256 up to 64k. The default is 32k and should
+ be ok in most cases. Reduce this value to shrink the size of U-Boot
+ binary.
+
+ The build will fail and a valid size suggested if this is too small.
+
+ If unsure, leave at the default value.
+
endmenu
menu "OS boot interface"
# MODFLAGS += -mlong-calls
#
ifndef CONFIG_SPL_BUILD
-OBJCOPYFLAGS += -j .got -j .rel -j .padding -j .dtb.init.rodata
+OBJCOPYFLAGS += -j .data.reloc -j .dtb.init.rodata
LDFLAGS_FINAL += --emit-relocs
endif
__image_copy_end = .;
__init_end = .;
- /*
- * .rel must come last so that the mips-relocs tool can shrink
- * the section size & the PT_LOAD program header filesz.
- */
- .rel : {
+ .data.reloc : {
__rel_start = .;
- BYTE(0x0)
- . += (32 * 1024) - 1;
+ /*
+ * Space for relocation table
+ * This needs to be filled so that the
+ * mips-reloc tool can overwrite the content.
+ * An invalid value is left at the start of the
+ * section to abort relocation if the table
+ * has not been filled in.
+ */
+ LONG(0xFFFFFFFF);
+ FILL(0);
+ . += CONFIG_MIPS_RELOCATION_TABLE_SIZE - 4;
}
+ . = ALIGN(4);
_end = .;
.bss __rel_start (OVERLAY) : {
select SYS_FSL_ERRATUM_A004477
select SYS_FSL_ERRATUM_A004508
select SYS_FSL_ERRATUM_A005125
+ select SYS_FSL_ERRATUM_A005275
select SYS_FSL_ERRATUM_A006261
select SYS_FSL_ERRATUM_A007075
select SYS_FSL_ERRATUM_ESDHC111
select FSL_LAW
select SYS_FSL_ERRATUM_A004510
select SYS_FSL_ERRATUM_A004849
+ select SYS_FSL_ERRATUM_A005275
select SYS_FSL_ERRATUM_A006261
select SYS_FSL_ERRATUM_CPU_A003999
select SYS_FSL_ERRATUM_DDR_A003
select SYS_FSL_DDR_VER_44
select SYS_FSL_ERRATUM_A004510
select SYS_FSL_ERRATUM_A004849
+ select SYS_FSL_ERRATUM_A005275
select SYS_FSL_ERRATUM_A005812
select SYS_FSL_ERRATUM_A006261
select SYS_FSL_ERRATUM_CPU_A003999
select FSL_LAW
select SYS_FSL_DDR_VER_44
select SYS_FSL_ERRATUM_A004510
+ select SYS_FSL_ERRATUM_A005275
select SYS_FSL_ERRATUM_A006261
select SYS_FSL_ERRATUM_DDR_A003
select SYS_FSL_ERRATUM_DDR_A003474
select SYS_FSL_DDR_VER_44
select SYS_FSL_ERRATUM_A004510
select SYS_FSL_ERRATUM_A004699
+ select SYS_FSL_ERRATUM_A005275
select SYS_FSL_ERRATUM_A005812
select SYS_FSL_ERRATUM_A006261
select SYS_FSL_ERRATUM_DDR_A003
config SYS_FSL_ERRATUM_A005871
bool
+config SYS_FSL_ERRATUM_A005275
+ bool
+
config SYS_FSL_ERRATUM_A006261
bool
(SVR_REV(svr) <= CONFIG_SYS_FSL_A004447_SVR_REV))
puts("Work-around for Erratum I2C-A004447 enabled\n");
#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A005275
+ if (has_erratum_a005275())
+ puts("Work-around for Erratum A005275 enabled\n");
+#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A006261
if (has_erratum_a006261())
puts("Work-around for Erratum A006261 enabled\n");
#define FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_MII 0x20000000
#define FSL_CORENET_RCWSR13_EC2 0x0c000000 /* bits 420..421 */
#define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII 0x00000000
-#define FSL_CORENET_RCWSR13_EC2_FM1_GPIO 0x10000000
-#define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_MII 0x20000000
+#define FSL_CORENET_RCWSR13_EC2_FM1_GPIO 0x04000000
#define FSL_CORENET_RCWSR13_MAC2_GMII_SEL 0x00000080
#define FSL_CORENET_RCWSR13_MAC2_GMII_SEL_L2_SWITCH 0x00000000
-#define FSL_CORENET_RCWSR13_MAC2_GMII_SEL_ENET_PORT 0x80000000
+#define FSL_CORENET_RCWSR13_MAC2_GMII_SEL_ENET_PORT 0x00000080
#define CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET 0x28
#define PXCKEN_MASK 0x80000000
#define PXCK_MASK 0x00FF0000
OperationRegion(GNVS, SystemMemory, ACPI_GNVS_ADDR, ACPI_GNVS_SIZE)
Field(GNVS, ByteAcc, NoLock, Preserve)
{
- Offset (0x00),
PCNT, 8, /* processor count */
IURE, 8, /* internal UART enabled */
}
OperationRegion(GNVS, SystemMemory, ACPI_GNVS_ADDR, ACPI_GNVS_SIZE)
Field(GNVS, ByteAcc, NoLock, Preserve)
{
- Offset (0x00),
PCNT, 8, /* processor count */
}
OperationRegion(GNVS, SystemMemory, ACPI_GNVS_ADDR, ACPI_GNVS_SIZE)
Field(GNVS, ByteAcc, NoLock, Preserve)
{
- Offset (0x00),
PCNT, 8, /* processor count */
}
+++ /dev/null
-U-Boot for the NXP i.MX8MQ EVK board
-
-Quick Start
-===========
-
-- Build U-Boot
-- Build the ARM Trusted firmware binary
-- Get DDR firmware and mkimage tool
-- Generate flash.bin using imx-mkimage
-- Flash the binary into the SD card
-- Boot
-
-Build U-Boot
-============
-
-$ make mx8mq_evk_defconfig
-$ make
-
-Get and Build the ARM Trusted firmware
-======================================
-
-$ git clone https://source.codeaurora.org/external/imx/imx-atf
-$ cd imx-atf/
-$ git checkout origin/imx_4.9.51_imx8m_beta
-$ make PLAT=imx8mq bl31
-
-Get the DDR firmware and mkimage tool
-==============================
-
-$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-7.2.bin
-$ chmod +x firmware-imx-7.2.bin
-$ ./firmware-imx-7.2.bin
-
-Download the imx-mkimage tool:
-
-$ git clone https://source.codeaurora.org/external/imx/imx-mkimage/
-$ cd imx-mkimage/
-$ git checkout origin/imx_4.9.51_imx8m_beta
-
-
-Generate flash.bin using imx-mkimage
-====================================
-
-Copy the following binaries to imx-mkimage/iMX8M folder:
-
-$ cp imx-atf/build/imx8mq/release/bl31.bin imx-mkimage/iMX8M/
-$ cp u-boot/u-boot-nodtb.bin imx-mkimage/iMX8M/
-$ cp u-boot/spl/u-boot-spl.bin imx-mkimage/iMX8M/
-$ cp u-boot/arch/arm/dts/fsl-imx8mq-evk.dtb imx-mkimage/iMX8M/
-
-Copy the following firmwares to imx-mkimage/iMX8 folder :
-
-$ cp firmware-imx-7.2/firmware/ddr/synopsys/lpddr4_pmu_train_1d_dmem.bin imx-mkimage/iMX8M/
-$ cp firmware-imx-7.2/firmware/ddr/synopsys/lpddr4_pmu_train_1d_imem.bin imx-mkimage/iMX8M/
-$ cp firmware-imx-7.2/firmware/ddr/synopsys/lpddr4_pmu_train_2d_dmem.bin imx-mkimage/iMX8M/
-$ cp firmware-imx-7.2/firmware/ddr/synopsys/lpddr4_pmu_train_2d_imem.bin imx-mkimage/iMX8M/
-
-If you want to run with HDMI, copy signed_hdmi_imx8m.bin to imx-mkimage/iMX8M.
-
-Before generating the flash.bin, transfer the mkimage generated by U-Boot to iMX8M folder:
-
-$ cp u-boot/tools/mkimage imx-mkimage/iMX8M/
-$ mv imx-mkimage/iMX8M/mkimage imx-mkimage/iMX8M/mkimage_uboot
-
-$ cd imx-mkimage/
-$ make SOC=iMX8M flash_spl_uboot
-
-Or for using HDMI:
-
-$ make SOC=iMX8M flash_hdmi_spl_uboot
-
-Flash the binary into the SD card
-=================================
-
-Burn the flash.bin binary to SD card offset 33KB:
-
-$ sudo dd if=iMX8M/flash.bin of=/dev/sd[x] bs=1024 seek=33
-
-Boot
-====
-Set Boot switch SW801: 1100 and Bmode: 10 to boot from Micro SD.
STM32MP1 BOARD
M: Patrick Delaunay <patrick.delaunay@st.com>
+L: uboot-stm32@st-md-mailman.stormreply.com (moderated for non-subscribers)
S: Maintained
F: board/st/stm32mp1
F: include/configs/stm32mp1.h
+++ /dev/null
-if TARGET_EMDK
-
-config SYS_BOARD
- default "emdk"
-
-config SYS_VENDOR
- default "synopsys"
-
-config SYS_CONFIG_NAME
- default "emdk"
-
-endif
+++ /dev/null
-EM DEVELOPMENT KIT BOARD
-M: Alexey Brodkin <abrodkin@synopsys.com>
-S: Maintained
-F: board/synopsys/emdk/
-F: configs/emdk_defconfig
+++ /dev/null
-#
-# Copyright (C) 2018 Synopsys, Inc. All rights reserved.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += emdk.o
+++ /dev/null
-================================================================================
-Useful notes on bulding and using of U-Boot on ARC EM Development Kit (AKA EMDK)
-================================================================================
-
- BOARD OVERVIEW
-
- The DesignWare ARC EM Development Kit is FPGA-bases platform for rapid
- software development on the ARC EM family of processors.
-
- Since this board is based on FPGA it's possible to load and use different
- versions of ARC EM CPUs. U-Boot is built to be run on the simplest
- possible configuration which means the same one binary will work on more
- advanced configurations as well.
-
- The board has the following features useful for U-Boot:
- * On-board 2-channel FTDI TTL-to-USB converter
- - The first channel is used for serial debug port (which makes it possible
- to use a serial connection on pretty much any host machine be it
- Windows, Linux or Mac).
- On Linux machine typucally FTDI serial port would be /dev/ttyUSB0.
- There's no HW flow-control and baud-rate is 115200.
-
- - The second channel is used for built-in Digilent USB JTAG probe.
- That means no extra hardware is required to access ARC core from a
- debugger on development host. Both proprietary MetaWare debugger and
- open source OpenOCD + GDB client are supported.
-
- - Also with help of this FTDI chip it is possible to reset entire
- board with help of a special `rff-ftdi-reset` utility, see:
- https://github.com/foss-for-synopsys-dwc-arc-processors/rff-ftdi-reset
-
- * Micro SD-card slot
- - U-Boot expects to see the very first partition on the card formatted as
- FAT file-system and uses it for keeping its environment in `uboot.env`
- file. Note uboot.env is not just a text file but it is auto-generated
- file created by U-Boot on invocation of `saveenv` command.
- It contains a checksum which makes this saved environment invalid in
- case of maual modification.
-
- - There might be more useful files on that first FAT partition like
- user applications, data files etc.
-
- * 256 KiB of "ROM"
- - This so-called "ROM" is a part of FPGA image and even though it
- might be unlocked for writes its initial content will be restored
- on the next power-on.
-
-
- BUILDING U-BOOT
-
- 1. Configure U-Boot:
- ------------------------->8----------------------
- make emdk_defconfig
- ------------------------->8----------------------
-
- 2. To build Elf file (for example to be used with host debugger via JTAG
- connection to the target board):
- ------------------------->8----------------------
- make mdbtrick
- ------------------------->8----------------------
-
- This will produce `u-boot` Elf file.
-
- 3. To build binary image to be put in "ROM":
- ------------------------->8----------------------
- make u-boot.bin
- ------------------------->8----------------------
-
-
- EXECUTING U-BOOT
-
- 1. The EMDK board is supposed to auto-start U-Boot image stored in ROM on
- power-on. For that make sure VCCIO DIP-switches are all in "off" state.
-
- 2. Though it is possible to load U-Boot as a simple Elf file via JTAG right
- in "ROM" and start it from the debugger. One important note here we first
- need to enable writes into "ROM" by writing 1 to 0xf0001000.
-
- 2.1. In case of proprietary MetaWare debugger run:
- ------------------------->8----------------------
- mdb -dll=opxdarc.so -OK -preloadexec="eval *(int*)0xf0001000=0" u-boot
- ------------------------->8----------------------
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2018 Synopsys, Inc. All rights reserved.
- */
-
-#include <common.h>
-#include <dwmmc.h>
-#include <malloc.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define ARC_PERIPHERAL_BASE 0xF0000000
-#define SDIO_BASE (ARC_PERIPHERAL_BASE + 0x10000)
-
-int board_mmc_init(bd_t *bis)
-{
- struct dwmci_host *host = NULL;
-
- host = malloc(sizeof(struct dwmci_host));
- if (!host) {
- printf("dwmci_host malloc fail!\n");
- return 1;
- }
-
- memset(host, 0, sizeof(struct dwmci_host));
- host->name = "Synopsys Mobile storage";
- host->ioaddr = (void *)SDIO_BASE;
- host->buswidth = 4;
- host->dev_index = 0;
- host->bus_hz = 50000000;
-
- add_dwmci(host, host->bus_hz / 2, 400000);
-
- return 0;
-}
-
-int board_mmc_getcd(struct mmc *mmc)
-{
- struct dwmci_host *host = mmc->priv;
-
- return !(dwmci_readl(host, DWMCI_CDETECT) & 1);
-}
-
-#define CREG_BASE 0xF0001000
-#define CREG_BOOT_OFFSET 0
-#define CREG_BOOT_WP_OFFSET 8
-
-#define CGU_BASE 0xF0000000
-#define CGU_IP_SW_RESET 0x0FF0
-
-void reset_cpu(ulong addr)
-{
- writel(1, (u32 *)(CGU_BASE + CGU_IP_SW_RESET));
- while (1)
- ; /* loop forever till reset */
-}
-
-static int do_emdk_rom(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
-{
- u32 creg_boot = readl((u32 *)(CREG_BASE + CREG_BOOT_OFFSET));
-
- if (!strcmp(argv[1], "unlock"))
- creg_boot &= ~BIT(CREG_BOOT_WP_OFFSET);
- else if (!strcmp(argv[1], "lock"))
- creg_boot |= BIT(CREG_BOOT_WP_OFFSET);
- else
- return CMD_RET_USAGE;
-
- writel(creg_boot, (u32 *)(CREG_BASE + CREG_BOOT_OFFSET));
-
- return CMD_RET_SUCCESS;
-}
-
-cmd_tbl_t cmd_emdk[] = {
- U_BOOT_CMD_MKENT(rom, 2, 0, do_emdk_rom, "", ""),
-};
-
-static int do_emdk(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
-{
- cmd_tbl_t *c;
-
- c = find_cmd_tbl(argv[1], cmd_emdk, ARRAY_SIZE(cmd_emdk));
-
- /* Strip off leading 'emdk' command */
- argc--;
- argv++;
-
- if (c == NULL || argc > c->maxargs)
- return CMD_RET_USAGE;
-
- return c->cmd(cmdtp, flag, argc, argv);
-}
-
-U_BOOT_CMD(
- emdk, CONFIG_SYS_MAXARGS, 0, do_emdk,
- "Synopsys EMDK specific commands",
- "rom unlock - Unlock non-volatile memory for writing\n"
- "emdk rom lock - Lock non-volatile memory to prevent writing\n"
-);
--- /dev/null
+if TARGET_EMSDP
+
+config SYS_BOARD
+ default "emsdp"
+
+config SYS_VENDOR
+ default "synopsys"
+
+config SYS_CONFIG_NAME
+ default "emsdp"
+
+endif
--- /dev/null
+EM DEVELOPMENT KIT BOARD
+M: Alexey Brodkin <abrodkin@synopsys.com>
+S: Maintained
+F: arch/arc/dts/emsdp.dts
+F: board/synopsys/emsdp/
+F: configs/emsdp_defconfig
--- /dev/null
+#
+# Copyright (C) 2018 Synopsys, Inc. All rights reserved.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += emsdp.o
--- /dev/null
+================================================================================
+Useful notes on bulding and using of U-Boot on
+ARC EM Software Development Platform (AKA EMSDP)
+================================================================================
+
+ BOARD OVERVIEW
+
+ The DesignWare ARC EM Software Development Platform is FPGA-bases platform
+ for rapid software development on the ARC EM family of processors.
+
+ Since this board is based on FPGA it's possible to load and use different
+ versions of ARC EM CPUs. U-Boot is built to be run on the simplest
+ possible configuration which means the same one binary will work on more
+ advanced configurations as well.
+
+ The board has the following features useful for U-Boot:
+ * On-board 2-channel FTDI TTL-to-USB converter
+ - The first channel is used for serial debug port (which makes it possible
+ to use a serial connection on pretty much any host machine be it
+ Windows, Linux or Mac).
+ On Linux machine typucally FTDI serial port would be /dev/ttyUSB0.
+ There's no HW flow-control and baud-rate is 115200.
+
+ - The second channel is used for built-in Digilent USB JTAG probe.
+ That means no extra hardware is required to access ARC core from a
+ debugger on development host. Both proprietary MetaWare debugger and
+ open source OpenOCD + GDB client are supported.
+
+ - Also with help of this FTDI chip it is possible to reset entire
+ board with help of a special `rff-ftdi-reset` utility, see:
+ https://github.com/foss-for-synopsys-dwc-arc-processors/rff-ftdi-reset
+
+ * Micro SD-card slot
+ - U-Boot expects to see the very first partition on the card formatted as
+ FAT file-system and uses it for keeping its environment in `uboot.env`
+ file. Note uboot.env is not just a text file but it is auto-generated
+ file created by U-Boot on invocation of `saveenv` command.
+ It contains a checksum which makes this saved environment invalid in
+ case of maual modification.
+
+ - There might be more useful files on that first FAT partition like
+ user applications, data files etc.
+
+ * 256 KiB of "ROM"
+ - This so-called "ROM" is a part of FPGA image and even though it
+ might be unlocked for writes its initial content will be restored
+ on the next power-on.
+
+
+ BUILDING U-BOOT
+
+ 1. Configure U-Boot:
+ ------------------------->8----------------------
+ make emsdp_defconfig
+ ------------------------->8----------------------
+
+ 2. To build Elf file (for example to be used with host debugger via JTAG
+ connection to the target board):
+ ------------------------->8----------------------
+ make mdbtrick
+ ------------------------->8----------------------
+
+ This will produce `u-boot` Elf file.
+
+ 3. To build binary image to be put in "ROM":
+ ------------------------->8----------------------
+ make u-boot.bin
+ ------------------------->8----------------------
+
+
+ EXECUTING U-BOOT
+
+ 1. The EMSDP board is supposed to auto-start U-Boot image stored in ROM on
+ power-on. For that make sure VCCIO DIP-switches are all in "off" state.
+
+ 2. Though it is possible to load U-Boot as a simple Elf file via JTAG right
+ in "ROM" and start it from the debugger. One important note here we first
+ need to enable writes into "ROM" by writing 1 to 0xf0001000.
+
+ 2.1. In case of proprietary MetaWare debugger run:
+ ------------------------->8----------------------
+ mdb -dll=opxdarc.so -OK -preloadexec="eval *(int*)0xf0001000=0" u-boot
+ ------------------------->8----------------------
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Synopsys, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <dwmmc.h>
+#include <malloc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define ARC_PERIPHERAL_BASE 0xF0000000
+#define SDIO_BASE (ARC_PERIPHERAL_BASE + 0x10000)
+
+int board_mmc_init(bd_t *bis)
+{
+ struct dwmci_host *host = NULL;
+
+ host = malloc(sizeof(struct dwmci_host));
+ if (!host) {
+ printf("dwmci_host malloc fail!\n");
+ return 1;
+ }
+
+ memset(host, 0, sizeof(struct dwmci_host));
+ host->name = "Synopsys Mobile storage";
+ host->ioaddr = (void *)SDIO_BASE;
+ host->buswidth = 4;
+ host->dev_index = 0;
+ host->bus_hz = 50000000;
+
+ add_dwmci(host, host->bus_hz / 2, 400000);
+
+ return 0;
+}
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ struct dwmci_host *host = mmc->priv;
+
+ return !(dwmci_readl(host, DWMCI_CDETECT) & 1);
+}
+
+#define CREG_BASE 0xF0001000
+#define CREG_BOOT_OFFSET 0
+#define CREG_BOOT_WP_OFFSET 8
+
+#define CGU_BASE 0xF0000000
+#define CGU_IP_SW_RESET 0x0FF0
+
+void reset_cpu(ulong addr)
+{
+ writel(1, (u32 *)(CGU_BASE + CGU_IP_SW_RESET));
+ while (1)
+ ; /* loop forever till reset */
+}
+
+static int do_emsdp_rom(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+ u32 creg_boot = readl((u32 *)(CREG_BASE + CREG_BOOT_OFFSET));
+
+ if (!strcmp(argv[1], "unlock"))
+ creg_boot &= ~BIT(CREG_BOOT_WP_OFFSET);
+ else if (!strcmp(argv[1], "lock"))
+ creg_boot |= BIT(CREG_BOOT_WP_OFFSET);
+ else
+ return CMD_RET_USAGE;
+
+ writel(creg_boot, (u32 *)(CREG_BASE + CREG_BOOT_OFFSET));
+
+ return CMD_RET_SUCCESS;
+}
+
+cmd_tbl_t cmd_emsdp[] = {
+ U_BOOT_CMD_MKENT(rom, 2, 0, do_emsdp_rom, "", ""),
+};
+
+static int do_emsdp(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+ cmd_tbl_t *c;
+
+ c = find_cmd_tbl(argv[1], cmd_emsdp, ARRAY_SIZE(cmd_emsdp));
+
+ /* Strip off leading 'emsdp' command */
+ argc--;
+ argv++;
+
+ if (c == NULL || argc > c->maxargs)
+ return CMD_RET_USAGE;
+
+ return c->cmd(cmdtp, flag, argc, argv);
+}
+
+U_BOOT_CMD(
+ emsdp, CONFIG_SYS_MAXARGS, 0, do_emsdp,
+ "Synopsys EMSDP specific commands",
+ "rom unlock - Unlock non-volatile memory for writing\n"
+ "emsdp rom lock - Lock non-volatile memory to prevent writing\n"
+);
--- /dev/null
+================================================================================
+Useful notes on bulding and using of U-Boot on
+ARC IoT Development Kit (AKA IoTDK)
+================================================================================
+
+ BOARD OVERVIEW
+
+ The DesignWare ARC IoT Development Kit is a versatile platform that includes
+ the necessary hardware and software to accelerate software development and
+ debugging of sensor fusion, voice recognition and face detection designs.
+
+ The ARC IoT Development Kit includes a silicon implementation of the
+ ARC Data Fusion IP Subsystem running at 144 MHz on SMIC's
+ 55-nm ultra-low power process, and a rich set of peripherals commonly used
+ in IoT designs such as USB, UART, SPI, I2C, PWM, SDIO and ADCs.
+
+ The board is shipped with pre-installed U-Boot in non-volatile memory
+ (eFlash) so on power-on user sees U-Boot start header and command line
+ prompt which might be used for U-Boot environment fine-tuning, manual
+ loading and execution of user application binaries etc.
+
+ The board has the following features useful for U-Boot:
+ * On-board 2-channel FTDI TTL-to-USB converter
+ - The first channel is used for serial debug port (which makes it possible
+ to use a serial connection on pretty much any host machine be it
+ Windows, Linux or Mac).
+ On Linux machine typucally FTDI serial port would be /dev/ttyUSB0.
+ There's no HW flow-control and baud-rate is 115200.
+
+ - The second channel is used for built-in Digilent USB JTAG probe.
+ That means no extra hardware is required to access ARC core from a
+ debugger on development host. Both proprietary MetaWare debugger and
+ open source OpenOCD + GDB client are supported.
+
+ - Also with help of this FTDI chip it is possible to reset entire
+ board with help of a special `rff-ftdi-reset` utility, see:
+ https://github.com/foss-for-synopsys-dwc-arc-processors/rff-ftdi-reset
+
+ * Micro SD-card slot
+ - U-Boot expects to see the very first partition on the card formatted as
+ FAT file-system and uses it for keeping its environment in `uboot.env`
+ file. Note uboot.env is not just a text file but it is auto-generated
+ file created by U-Boot on invocation of `saveenv` command.
+ It contains a checksum which makes this saved environment invalid in
+ case of maual modification.
+
+ - There might be more useful files on that first FAT partition like
+ user applications, data files etc.
+
+ * USB OTG connector
+ - U-Boot may access USB mass-storage devices attached to this connector.
+ Note only FAT file-system is supported. It might be used for storing
+ user application binaries as well as micro SD-card mentioned above.
+
+ * The following memories are avaialble on the board:
+ - eFlash: 256 KiB @ 0x0000_0000
+ A non-volatile memory from which ARC core may execute code directly.
+ Still is is not direcly writable, thus this is not an ordinary RAM.
+
+ - ICCM: 256 KiB @ 0x2000_0000
+ Instruction Closely Coupled Memory - fast on-chip memory primary used
+ for code being executed, still data could be placed in this memory too.
+ In that sense it's just a general purpose RAM.
+
+ - SRAM: 128 KiB @ 0x3000_0000
+ On-chip SRAM. From user perspective is the same as ICCM above.
+
+ - DCCM: 128 KiB @ 0x8000_0000
+ Data Closely Coupled Memory is similar to ICCM with a major difference -
+ ARC core cannot execute code from DCCM. So this is very special RAM
+ only suitable for data.
+
+ BUILDING U-BOOT
+
+ 1. Configure U-Boot:
+ ------------------------->8----------------------
+ make iot_devkit_defconfig
+ ------------------------->8----------------------
+
+ 2. To build Elf file (for example to be used with host debugger via JTAG
+ connection to the target board):
+ ------------------------->8----------------------
+ make mdbtrick
+ ------------------------->8----------------------
+
+ This will produce `u-boot` Elf file.
+
+ 3. To build binary image to be put in "ROM":
+ ------------------------->8----------------------
+ make u-boot.bin
+ ------------------------->8----------------------
+
+
+ EXECUTING U-BOOT
+
+ 1. The IoTDK board is supposed to auto-start U-Boot image stored in eFlash on
+ power-on. Note it's possible to update that image - follow instructions in
+ user's manual.
+
+ 2. Though it is possible to load and start U-Boot as a simple Elf file
+ via JTAG right in ICCM. For that it's required to re-configure U-Boot
+ so it gets linked to ICCM address 0x2000_0000 (remember eFlash is not
+ direcly writable).
+ Run U-Boot's configuration utility with "make menuconfig", go to
+ "Boot images" and change "Text Base" from default 0x00000000 to
+ 0x20000000. Exit & save new configuration. Now run "make mdbtrick" to
+ build new Elf.
+
+ 2.1. In case of proprietary MetaWare debugger run:
+ ------------------------->8----------------------
+ mdb -digilent u-boot
+ ------------------------->8----------------------
+
+ USING U-BOOT
+
+ Note due to limited memory size it's supposed that user will run binary
+ images of their applications instead of loading Elf files.
+
+ 1. To load and start application binary from micro SD-card execute
+ the following commands in U-Boot's shell:
+ ------------------------->8----------------------
+ fatload mmc 0 0x20000000 yourapp.bin
+ go 0x20000000
+ ------------------------->8----------------------
+
+ 2. To load and start application binary from USB mass-storage device execute
+ the following commands in U-Boot's shell:
+ ------------------------->8----------------------
+ usb start
+ fatload usb 0x20000000 yourapp.bin
+ go 0x20000000
+ ------------------------->8----------------------
+
+ 3. To have a sequence of commands executed on U-Boot start put those
+ commands in "bootcmd" with semicolon between them.
+ For example to get (1) done automatically:
+ ------------------------->8----------------------
+ setenv bootcmd fatload mmc 0 0x20000000 yourapp.bin\; go 0x20000000
+ saveenv
+ ------------------------->8----------------------
+
+ 4. To reboot the board just run:
+ ------------------------->8----------------------
+ reset
+ ------------------------->8----------------------
return 0;
}
-#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
-#ifndef CONFIG_DM_ETH
-int get_eth_env_param(char *env_name)
-{
- char *env;
- int res = -1;
-
- env = env_get(env_name);
- if (env)
- res = simple_strtol(env, NULL, 0);
-
- return res;
-}
-
-int board_eth_init(bd_t *bis)
-{
- int j;
- int res;
- int port_num;
- char link_type_name[32];
-
- if (cpu_is_k2g())
- writel(KS2_ETHERNET_RGMII, KS2_ETHERNET_CFG);
-
- /* By default, select PA PLL clock as PA clock source */
-#ifndef CONFIG_SOC_K2G
- if (psc_enable_module(KS2_LPSC_PA))
- return -1;
-#endif
- if (psc_enable_module(KS2_LPSC_CPGMAC))
- return -1;
- if (psc_enable_module(KS2_LPSC_CRYPTO))
- return -1;
-
- if (cpu_is_k2e() || cpu_is_k2l())
- pll_pa_clk_sel();
-
- port_num = get_num_eth_ports();
-
- for (j = 0; j < port_num; j++) {
- sprintf(link_type_name, "sgmii%d_link_type", j);
- res = get_eth_env_param(link_type_name);
- if (res >= 0)
- eth_priv_cfg[j].sgmii_link_type = res;
-
- keystone2_emac_initialize(ð_priv_cfg[j]);
- }
-
- return 0;
-}
-#endif
-#endif
-
#ifdef CONFIG_SPL_BUILD
void spl_board_init(void)
{
#include <asm/ti-common/keystone_net.h>
#include "../common/board_detect.h"
-extern struct eth_priv_t eth_priv_cfg[];
-
#if defined(CONFIG_TI_I2C_BOARD_DETECT)
static inline int board_is_k2g_gp(void)
{
}
#endif
-int get_num_eth_ports(void);
void spl_init_keystone_plls(void);
#endif
return data;
}
-#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
-struct eth_priv_t eth_priv_cfg[] = {
- {
- .int_name = "K2E_EMAC0",
- .rx_flow = 0,
- .phy_addr = 0,
- .slave_port = 1,
- .sgmii_link_type = SGMII_LINK_MAC_PHY,
- .phy_if = PHY_INTERFACE_MODE_SGMII,
- },
- {
- .int_name = "K2E_EMAC1",
- .rx_flow = 8,
- .phy_addr = 1,
- .slave_port = 2,
- .sgmii_link_type = SGMII_LINK_MAC_PHY,
- .phy_if = PHY_INTERFACE_MODE_SGMII,
- },
- {
- .int_name = "K2E_EMAC2",
- .rx_flow = 16,
- .phy_addr = 2,
- .slave_port = 3,
- .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
- .phy_if = PHY_INTERFACE_MODE_SGMII,
- },
- {
- .int_name = "K2E_EMAC3",
- .rx_flow = 24,
- .phy_addr = 3,
- .slave_port = 4,
- .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
- .phy_if = PHY_INTERFACE_MODE_SGMII,
- },
- {
- .int_name = "K2E_EMAC4",
- .rx_flow = 32,
- .phy_addr = 4,
- .slave_port = 5,
- .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
- .phy_if = PHY_INTERFACE_MODE_SGMII,
- },
- {
- .int_name = "K2E_EMAC5",
- .rx_flow = 40,
- .phy_addr = 5,
- .slave_port = 6,
- .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
- .phy_if = PHY_INTERFACE_MODE_SGMII,
- },
- {
- .int_name = "K2E_EMAC6",
- .rx_flow = 48,
- .phy_addr = 6,
- .slave_port = 7,
- .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
- .phy_if = PHY_INTERFACE_MODE_SGMII,
- },
- {
- .int_name = "K2E_EMAC7",
- .rx_flow = 56,
- .phy_addr = 7,
- .slave_port = 8,
- .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
- .phy_if = PHY_INTERFACE_MODE_SGMII,
- },
-};
-
-int get_num_eth_ports(void)
-{
- return sizeof(eth_priv_cfg) / sizeof(struct eth_priv_t);
-}
-#endif
-
#if defined(CONFIG_MULTI_DTB_FIT)
int board_fit_config_name_match(const char *name)
{
}
#endif
-#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
-struct eth_priv_t eth_priv_cfg[] = {
- {
- .int_name = "K2G_EMAC",
- .rx_flow = 0,
- .phy_addr = 0,
- .slave_port = 1,
- .sgmii_link_type = SGMII_LINK_MAC_PHY,
- .phy_if = PHY_INTERFACE_MODE_RGMII,
- },
-};
-
-int get_num_eth_ports(void)
-{
- return sizeof(eth_priv_cfg) / sizeof(struct eth_priv_t);
-}
-#endif
-
#ifdef CONFIG_TI_SECURE_DEVICE
void board_pmmc_image_process(ulong pmmc_image, size_t pmmc_size)
{
return data;
}
-#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
-struct eth_priv_t eth_priv_cfg[] = {
- {
- .int_name = "K2HK_EMAC",
- .rx_flow = 22,
- .phy_addr = 0,
- .slave_port = 1,
- .sgmii_link_type = SGMII_LINK_MAC_PHY,
- .phy_if = PHY_INTERFACE_MODE_SGMII,
- },
- {
- .int_name = "K2HK_EMAC1",
- .rx_flow = 23,
- .phy_addr = 1,
- .slave_port = 2,
- .sgmii_link_type = SGMII_LINK_MAC_PHY,
- .phy_if = PHY_INTERFACE_MODE_SGMII,
- },
- {
- .int_name = "K2HK_EMAC2",
- .rx_flow = 24,
- .phy_addr = 2,
- .slave_port = 3,
- .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
- .phy_if = PHY_INTERFACE_MODE_SGMII,
- },
- {
- .int_name = "K2HK_EMAC3",
- .rx_flow = 25,
- .phy_addr = 3,
- .slave_port = 4,
- .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
- .phy_if = PHY_INTERFACE_MODE_SGMII,
- },
-};
-
-int get_num_eth_ports(void)
-{
- return sizeof(eth_priv_cfg) / sizeof(struct eth_priv_t);
-}
-#endif
-
#ifdef CONFIG_BOARD_EARLY_INIT_F
int board_early_init_f(void)
{
return data;
}
-#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
-struct eth_priv_t eth_priv_cfg[] = {
- {
- .int_name = "K2L_EMAC",
- .rx_flow = 0,
- .phy_addr = 0,
- .slave_port = 1,
- .sgmii_link_type = SGMII_LINK_MAC_PHY,
- .phy_if = PHY_INTERFACE_MODE_SGMII,
- },
- {
- .int_name = "K2L_EMAC1",
- .rx_flow = 8,
- .phy_addr = 1,
- .slave_port = 2,
- .sgmii_link_type = SGMII_LINK_MAC_PHY,
- .phy_if = PHY_INTERFACE_MODE_SGMII,
- },
- {
- .int_name = "K2L_EMAC2",
- .rx_flow = 16,
- .phy_addr = 2,
- .slave_port = 3,
- .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
- .phy_if = PHY_INTERFACE_MODE_SGMII,
- },
- {
- .int_name = "K2L_EMAC3",
- .rx_flow = 32,
- .phy_addr = 3,
- .slave_port = 4,
- .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
- .phy_if = PHY_INTERFACE_MODE_SGMII,
- },
-};
-
-int get_num_eth_ports(void)
-{
- return sizeof(eth_priv_cfg) / sizeof(struct eth_priv_t);
-}
-#endif
-
#ifdef CONFIG_BOARD_EARLY_INIT_F
int board_early_init_f(void)
{
config MTDIDS_DEFAULT
string "Default MTD IDs"
- depends on CMD_MTD || CMD_MTDPARTS || CMD_NAND || CMD_FLASH
+ depends on MTD_PARTITIONS || CMD_MTDPARTS || CMD_NAND || CMD_FLASH
help
Defines a default MTD IDs list for use with MTD partitions in the
Linux MTD command line partitions format.
config MTDPARTS_DEFAULT
string "Default MTD partition scheme"
- depends on CMD_MTD || CMD_MTDPARTS || CMD_NAND || CMD_FLASH
+ depends on MTD_PARTITIONS || CMD_MTDPARTS || CMD_NAND || CMD_FLASH
help
Defines a default MTD partitioning scheme in the Linux MTD command
line partitions format
config CMD_UBI
tristate "Enable UBI - Unsorted block images commands"
- select CMD_MTDPARTS
select CRC32
select MTD_UBI
help
obj-$(CONFIG_CMD_ADC) += adc.o
obj-$(CONFIG_CMD_ARMFLASH) += armflash.o
obj-y += blk_common.o
-obj-$(CONFIG_SOURCE) += source.o
obj-$(CONFIG_CMD_SOURCE) += source.o
obj-$(CONFIG_CMD_BDI) += bdinfo.o
obj-$(CONFIG_CMD_BEDBUG) += bedbug.o
if (argc != 4)
return CMD_RET_USAGE;
- id = (int)simple_strtoul(argv[1], NULL, 3);
+ id = (int)simple_strtoul(argv[1], NULL, 10);
addr = simple_strtoul(argv[2], NULL, 16);
size = simple_strtoul(argv[3], NULL, 16);
if (argc != 2)
return CMD_RET_USAGE;
- id = (int)simple_strtoul(argv[1], NULL, 3);
+ id = (int)simple_strtoul(argv[1], NULL, 10);
if (!rproc_is_initialized()) {
printf("\tRemote Processors are not initialized\n");
int ubi_detach(void)
{
- if (mtdparts_init() != 0) {
- printf("Error initializing mtdparts!\n");
- return 1;
- }
-
#ifdef CONFIG_CMD_UBIFS
/*
* Automatically unmount UBIFS partition when user
obj-$(CONFIG_$(SPL_)LOG) += log.o
obj-$(CONFIG_$(SPL_)LOG_CONSOLE) += log_console.o
obj-y += s_record.o
-obj-y += xyzModem.o
+obj-$(CONFIG_CMD_LOADB) += xyzModem.o
+obj-$(CONFIG_$(SPL_TPL_)YMODEM_SUPPORT) += xyzModem.o
obj-$(CONFIG_AVB_VERIFY) += avb_verify.o
#include <common.h>
#include <console.h>
-#include <cpu.h>
#include <dm.h>
#include <environment.h>
#include <fdtdec.h>
}
#endif
-#if defined(CONFIG_DISPLAY_CPUINFO) && CONFIG_IS_ENABLED(CPU)
-static int print_cpuinfo(void)
-{
- struct udevice *dev;
- char desc[512];
- int ret;
-
- ret = uclass_first_device_err(UCLASS_CPU, &dev);
- if (ret) {
- debug("%s: Could not get CPU device (err = %d)\n",
- __func__, ret);
- return ret;
- }
-
- ret = cpu_get_desc(dev, desc, sizeof(desc));
- if (ret) {
- debug("%s: Could not get CPU description (err = %d)\n",
- dev->name, ret);
- return ret;
- }
-
- printf("%s", desc);
-
- return 0;
-}
-#endif
-
static int announce_dram_init(void)
{
puts("DRAM: ");
#include <errno.h>
#include <image.h>
#include <linux/libfdt.h>
-#include <spl.h>
ulong fdt_getprop_u32(const void *fdt, int node, const char *prop)
{
}
if (dflt_conf_node != -ENOENT) {
- debug("Selecting default config '%s'", dflt_conf_desc);
+ debug("Selecting default config '%s'\n", dflt_conf_desc);
return dflt_conf_node;
}
spl_image->os = IH_OS_U_BOOT;
spl_image->name = "U-Boot";
- debug("spl: payload image: %.*s load addr: 0x%lx size: %d\n",
- (int)sizeof(spl_image->name), spl_image->name,
- spl_image->load_addr, spl_image->size);
+ debug("spl: payload image: %32s load addr: 0x%lx size: %d\n",
+ spl_image->name, spl_image->load_addr, spl_image->size);
#ifdef CONFIG_SPL_FIT_SIGNATURE
images.verify = 1;
}
spl_image->os = image_get_os(header);
spl_image->name = image_get_name(header);
- debug("spl: payload image: %.*s load addr: 0x%lx size: %d\n",
- IH_NMLEN, spl_image->name,
- spl_image->load_addr, spl_image->size);
+ debug("spl: payload image: %32s load addr: 0x%lx size: %d\n",
+ spl_image->name, spl_image->load_addr, spl_image->size);
#else
/* LEGACY image not supported */
debug("Legacy boot image support not enabled, proceeding to other boot methods\n");
image_entry_noargs_t image_entry =
(image_entry_noargs_t)spl_image->entry_point;
- debug("image entry point: 0x%lX\n", spl_image->entry_point);
+ debug("image entry point: 0x%lx\n", spl_image->entry_point);
image_entry();
}
debug("Unsupported OS image.. Jumping nevertheless..\n");
}
#if CONFIG_VAL(SYS_MALLOC_F_LEN) && !defined(CONFIG_SYS_SPL_MALLOC_SIZE)
- debug("SPL malloc() used %#lx bytes (%ld KB)\n", gd->malloc_ptr,
+ debug("SPL malloc() used 0x%lx bytes (%ld KB)\n", gd->malloc_ptr,
gd->malloc_ptr / 1024);
#endif
#ifdef CONFIG_BOOTSTAGE_STASH
CONFIG_ENV_IS_IN_NAND=y
CONFIG_FSL_CAAM=y
# CONFIG_MMC is not set
-CONFIG_MTD_PARTITIONS=y
CONFIG_NAND=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_FSL_CAAM=y
# CONFIG_MMC is not set
-CONFIG_MTD_PARTITIONS=y
CONFIG_NAND=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_FSL_CAAM=y
# CONFIG_MMC is not set
-CONFIG_MTD_PARTITIONS=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_MARVELL=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_FSL_CAAM=y
# CONFIG_MMC is not set
-CONFIG_MTD_PARTITIONS=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_MARVELL=y
CONFIG_MTDPARTS_DEFAULT="mtdparts=88000000.nor:256k(dtb),7m(kernel),55m(fs),1m(uboot);ff800000.flash:1m(uboot),8m(kernel),512k(dtb),-(fs)"
CONFIG_DM=y
CONFIG_FSL_ESDHC=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_FSL_CAAM=y
CONFIG_FSL_ESDHC=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_MTDPARTS_DEFAULT="mtdparts=88000000.nor:256k(dtb),7m(kernel),55m(fs),1m(uboot);ff800000.flash:1m(uboot),8m(kernel),512k(dtb),-(fs)"
CONFIG_DM=y
CONFIG_FSL_ESDHC=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_FSL_CAAM=y
CONFIG_FSL_ESDHC=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_MTDPARTS_DEFAULT="mtdparts=88000000.nor:256k(dtb),7m(kernel),55m(fs),1m(uboot);ff800000.flash:1m(uboot),8m(kernel),512k(dtb),-(fs)"
CONFIG_DM=y
CONFIG_FSL_ESDHC=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_FSL_CAAM=y
CONFIG_FSL_ESDHC=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_MTDPARTS_DEFAULT="mtdparts=88000000.nor:256k(dtb),7m(kernel),55m(fs),1m(uboot);ff800000.flash:1m(uboot),8m(kernel),512k(dtb),-(fs)"
CONFIG_DM=y
CONFIG_FSL_ESDHC=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_FSL_CAAM=y
CONFIG_FSL_ESDHC=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_MTDPARTS_DEFAULT="mtdparts=88000000.nor:256k(dtb),7m(kernel),55m(fs),1m(uboot);ff800000.flash:1m(uboot),8m(kernel),512k(dtb),-(fs)"
CONFIG_DM=y
CONFIG_FSL_ESDHC=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_FSL_CAAM=y
CONFIG_FSL_ESDHC=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_MTDPARTS_DEFAULT="mtdparts=88000000.nor:256k(dtb),7m(kernel),55m(fs),1m(uboot);ff800000.flash:1m(uboot),8m(kernel),512k(dtb),-(fs)"
CONFIG_DM=y
CONFIG_FSL_ESDHC=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_FSL_CAAM=y
CONFIG_FSL_ESDHC=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_MTDPARTS_DEFAULT="mtdparts=88000000.nor:256k(dtb),7m(kernel),55m(fs),1m(uboot);ff800000.flash:1m(uboot),8m(kernel),512k(dtb),-(fs)"
CONFIG_DM=y
CONFIG_FSL_ESDHC=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_FSL_CAAM=y
CONFIG_FSL_ESDHC=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_MTDPARTS_DEFAULT="mtdparts=88000000.nor:256k(dtb),7m(kernel),55m(fs),1m(uboot);ff800000.flash:1m(uboot),8m(kernel),512k(dtb),-(fs)"
CONFIG_DM=y
CONFIG_FSL_ESDHC=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_FSL_CAAM=y
CONFIG_FSL_ESDHC=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=sunxi-nand.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=sunxi-nand.0:256k(spl),256k(spl-backup),2m(uboot),2m(uboot-backup),-(UBI)"
CONFIG_DEFAULT_DEVICE_TREE="sun5i-gr8-chip-pro"
CONFIG_NR_DRAM_BANKS=1
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MTDPARTS=y
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_DEFAULT_DEVICE_TREE="sun8i-r16-nintendo-nes-classic-edition"
CONFIG_MTDPARTS_DEFAULT="mtdparts=ec000000.nor:128k(dtb),6016k(kernel),57088k(fs),1m(vsc7385-firmware),1280k(u-boot)"
CONFIG_ENV_IS_IN_NAND=y
CONFIG_FSL_ESDHC=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_MTDPARTS_DEFAULT="mtdparts=ec000000.nor:128k(dtb),6016k(kernel),57088k(fs),1m(vsc7385-firmware),1280k(u-boot)"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_FSL_ESDHC=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_MTDPARTS_DEFAULT="mtdparts=ec000000.nor:128k(dtb),6016k(kernel),57088k(fs),1m(vsc7385-firmware),1280k(u-boot)"
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_FSL_ESDHC=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_MTDPARTS_DEFAULT="mtdparts=ec000000.nor:128k(dtb),6016k(kernel),57088k(fs),1m(vsc7385-firmware),1280k(u-boot)"
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_FSL_ESDHC=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_MTDPARTS_DEFAULT="mtdparts=fef000000.nor:256k(vsc7385-firmware),256k(dtb),4608k(kernel),9728k(fs),256k(qe-ucode-firmware),1280k(u-boot)"
CONFIG_ENV_IS_IN_NAND=y
CONFIG_FSL_ESDHC=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_MTDPARTS_DEFAULT="mtdparts=fef000000.nor:256k(vsc7385-firmware),256k(dtb),4608k(kernel),9728k(fs),256k(qe-ucode-firmware),1280k(u-boot)"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_FSL_ESDHC=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_MTDPARTS_DEFAULT="mtdparts=fef000000.nor:256k(vsc7385-firmware),256k(dtb),4608k(kernel),9728k(fs),256k(qe-ucode-firmware),1280k(u-boot)"
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_FSL_ESDHC=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_MTDPARTS_DEFAULT="mtdparts=fef000000.nor:256k(vsc7385-firmware),256k(dtb),4608k(kernel),9728k(fs),256k(qe-ucode-firmware),1280k(u-boot)"
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_FSL_ESDHC=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_MTDPARTS_DEFAULT="mtdparts=ef000000.nor:256k(vsc7385-firmware),256k(dtb),4608k(kernel),9728k(fs),256k(qe-ucode-firmware),1280k(u-boot)"
CONFIG_ENV_IS_IN_NAND=y
CONFIG_FSL_ESDHC=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_MTDPARTS_DEFAULT="mtdparts=ef000000.nor:256k(vsc7385-firmware),256k(dtb),4608k(kernel),9728k(fs),256k(qe-ucode-firmware),1280k(u-boot)"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_FSL_ESDHC=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_MTDPARTS_DEFAULT="mtdparts=ef000000.nor:256k(vsc7385-firmware),256k(dtb),4608k(kernel),9728k(fs),256k(qe-ucode-firmware),1280k(u-boot)"
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_FSL_ESDHC=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_MTDPARTS_DEFAULT="mtdparts=ef000000.nor:256k(vsc7385-firmware),256k(dtb),4608k(kernel),9728k(fs),256k(qe-ucode-firmware),1280k(u-boot)"
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_FSL_ESDHC=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:48m(ramdisk),14m(diagnostic),2m(dink),6m(kernel),58112k(fs),512k(dtb),768k(u-boot)"
CONFIG_ENV_IS_IN_NAND=y
CONFIG_FSL_ESDHC=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_FLASH_CFI_MTD=y
CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:48m(ramdisk),14m(diagnostic),2m(dink),6m(kernel),58112k(fs),512k(dtb),768k(u-boot)"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_FSL_ESDHC=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_FLASH_CFI_MTD=y
CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:48m(ramdisk),14m(diagnostic),2m(dink),6m(kernel),58112k(fs),512k(dtb),768k(u-boot)"
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_FSL_ESDHC=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_FLASH_CFI_MTD=y
CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:48m(ramdisk),14m(diagnostic),2m(dink),6m(kernel),58112k(fs),512k(dtb),768k(u-boot)"
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_FSL_ESDHC=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_FLASH_CFI_MTD=y
CONFIG_MTDPARTS_DEFAULT="mtdparts=e8000000.nor:48m(ramdisk),14m(diagnostic),2m(dink),6m(kernel),58112k(fs),512k(dtb),768k(u-boot)"
CONFIG_ENV_IS_IN_NAND=y
CONFIG_FSL_ESDHC=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_FLASH_CFI_MTD=y
CONFIG_MTDPARTS_DEFAULT="mtdparts=e8000000.nor:48m(ramdisk),14m(diagnostic),2m(dink),6m(kernel),58112k(fs),512k(dtb),768k(u-boot)"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_FSL_ESDHC=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_FLASH_CFI_MTD=y
CONFIG_MTDPARTS_DEFAULT="mtdparts=e8000000.nor:48m(ramdisk),14m(diagnostic),2m(dink),6m(kernel),58112k(fs),512k(dtb),768k(u-boot)"
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_FSL_ESDHC=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_FLASH_CFI_MTD=y
CONFIG_MTDPARTS_DEFAULT="mtdparts=e8000000.nor:48m(ramdisk),14m(diagnostic),2m(dink),6m(kernel),58112k(fs),512k(dtb),768k(u-boot)"
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_FSL_ESDHC=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_FLASH_CFI_MTD=y
CONFIG_MTDPARTS_DEFAULT="mtdparts=fef000000.nor:256k(vsc7385-firmware),256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)"
CONFIG_ENV_IS_IN_NAND=y
CONFIG_FSL_ESDHC=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_MTDPARTS_DEFAULT="mtdparts=fef000000.nor:256k(vsc7385-firmware),256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_FSL_ESDHC=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_MTDPARTS_DEFAULT="mtdparts=fef000000.nor:256k(vsc7385-firmware),256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)"
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_FSL_ESDHC=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_MTDPARTS_DEFAULT="mtdparts=fef000000.nor:256k(vsc7385-firmware),256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)"
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_FSL_ESDHC=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_MTDPARTS_DEFAULT="mtdparts=ef000000.nor:256k(vsc7385-firmware),256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)"
CONFIG_ENV_IS_IN_NAND=y
CONFIG_FSL_ESDHC=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_MTDPARTS_DEFAULT="mtdparts=ef000000.nor:256k(vsc7385-firmware),256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_FSL_ESDHC=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_MTDPARTS_DEFAULT="mtdparts=ef000000.nor:256k(vsc7385-firmware),256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)"
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_FSL_ESDHC=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_MTDPARTS_DEFAULT="mtdparts=ef000000.nor:256k(vsc7385-firmware),256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)"
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_FSL_ESDHC=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_FSL_CAAM=y
CONFIG_FSL_ESDHC=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_FSL_CAAM=y
CONFIG_FSL_ESDHC=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel),128k(dtb),-(user)"
CONFIG_DM=y
CONFIG_FSL_ESDHC=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_FSL_CAAM=y
CONFIG_FSL_ESDHC=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_FSL_CAAM=y
CONFIG_FSL_ESDHC=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)"
CONFIG_DM=y
CONFIG_FSL_ESDHC=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_FSL_CAAM=y
CONFIG_FSL_ESDHC=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_FSL_ESDHC=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_FSL_ESDHC=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_DM=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_FSL_ESDHC=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_FSL_ESDHC=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_FSL_ESDHC=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_FSL_ESDHC=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_FSL_ESDHC=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_DM=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_FSL_ESDHC=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_FSL_ESDHC=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_FSL_ESDHC=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_FSL_CAAM=y
CONFIG_FSL_ESDHC=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_FSL_CAAM=y
CONFIG_FSL_ESDHC=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)"
CONFIG_DM=y
CONFIG_FSL_ESDHC=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_FSL_CAAM=y
CONFIG_FSL_ESDHC=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_FSL_CAAM=y
CONFIG_FSL_ESDHC=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_FSL_CAAM=y
CONFIG_FSL_ESDHC=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_DM=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_FSL_ESDHC=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_FSL_ESDHC=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_FSL_ESDHC=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_FSL_ESDHC=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_DM=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_FSL_ESDHC=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_FSL_ESDHC=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_FSL_ESDHC=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_FSL_CAAM=y
CONFIG_FSL_ESDHC=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_FSL_CAAM=y
CONFIG_FSL_ESDHC=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)"
CONFIG_DM=y
CONFIG_FSL_ESDHC=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_FSL_CAAM=y
CONFIG_FSL_ESDHC=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_FSL_CAAM=y
CONFIG_FSL_ESDHC=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SPL_DM=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_FSL_ESDHC=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_FSL_ESDHC=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_FSL_ESDHC=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_FSL_ESDHC=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_FSL_ESDHC=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_DM=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_FSL_ESDHC=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_FSL_ESDHC=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_FSL_CAAM=y
CONFIG_FSL_ESDHC=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_FSL_CAAM=y
CONFIG_FSL_ESDHC=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel),128k(dtb),-(user)"
CONFIG_DM=y
CONFIG_FSL_ESDHC=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_FSL_CAAM=y
CONFIG_FSL_ESDHC=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_FSL_CAAM=y
CONFIG_FSL_ESDHC=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_FSL_CAAM=y
CONFIG_FSL_ESDHC=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_FSL_CAAM=y
CONFIG_FSL_ESDHC=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
# CONFIG_CMD_IRQ is not set
CONFIG_DM=y
CONFIG_FSL_ESDHC=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_FSL_CAAM=y
CONFIG_FSL_ESDHC=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_FSL_CAAM=y
CONFIG_FSL_ESDHC=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_FSL_CAAM=y
CONFIG_FSL_ESDHC=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_FSL_CAAM=y
CONFIG_FSL_ESDHC=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_FSL_CAAM=y
CONFIG_FSL_ESDHC=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_FSL_CAAM=y
CONFIG_FSL_ESDHC=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_SATA_SIL3114=y
CONFIG_FSL_ESDHC=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_MTD_DEVICE=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_RENESAS_SDHI=y
CONFIG_MTD=y
CONFIG_MTD_DEVICE=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:128k(SPL),128k(SPL.backup1),128k(SPL.backup2),128k(SPL.backup3),1920k(u-boot),-(UBI)"
CONFIG_CMD_UBI=y
CONFIG_PHY_ADDR_ENABLE=y
CONFIG_DRIVER_TI_CPSW=y
CONFIG_MII=y
-CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DRIVER_TI_CPSW=y
CONFIG_MII=y
-CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
CONFIG_DRIVER_TI_CPSW=y
CONFIG_PHY_GIGE=y
CONFIG_MII=y
-CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_TIMER=y
CONFIG_DRIVER_TI_CPSW=y
CONFIG_PHY_GIGE=y
CONFIG_MII=y
-CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_TIMER=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DRIVER_TI_CPSW=y
CONFIG_MII=y
-CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DRIVER_TI_CPSW=y
CONFIG_MII=y
-CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
CONFIG_DRIVER_TI_CPSW=y
CONFIG_PHY_GIGE=y
CONFIG_MII=y
-CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_TIMER=y
CONFIG_DRIVER_TI_CPSW=y
CONFIG_PHY_GIGE=y
CONFIG_MII=y
-CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_TIMER=y
CONFIG_CMD_SPI=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(SPL),-(UBI)"
CONFIG_CMD_UBI=y
CONFIG_MTD_UBI_FASTMAP=y
CONFIG_DRIVER_TI_CPSW=y
CONFIG_MII=y
-CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_FAT_WRITE=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_TPS65910=y
CONFIG_CONS_INDEX=4
-CONFIG_SYS_NS16550=y
CONFIG_SPI=y
# CONFIG_USE_TINY_PRINTF is not set
# CONFIG_EFI_LOADER is not set
CONFIG_PHY_ADDR_ENABLE=y
CONFIG_DRIVER_TI_CPSW=y
CONFIG_MII=y
-CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_FAT_WRITE=y
CONFIG_PHY_ADDR_ENABLE=y
CONFIG_DRIVER_TI_CPSW=y
CONFIG_MII=y
-CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_FAT_WRITE=y
CONFIG_PHY_ADDR_ENABLE=y
CONFIG_DRIVER_TI_CPSW=y
CONFIG_MII=y
-CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_FAT_WRITE=y
CONFIG_PHY_ADDR_ENABLE=y
CONFIG_DRIVER_TI_CPSW=y
CONFIG_MII=y
-CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_FAT_WRITE=y
CONFIG_PHY_ADDR_ENABLE=y
CONFIG_DRIVER_TI_CPSW=y
CONFIG_MII=y
-CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_FAT_WRITE=y
CONFIG_PHY_ADDR_ENABLE=y
CONFIG_DRIVER_TI_CPSW=y
CONFIG_MII=y
-CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_FAT_WRITE=y
CONFIG_MMC_OMAP_HS=y
CONFIG_DRIVER_TI_CPSW=y
CONFIG_MII=y
-CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_FAT_WRITE=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_CACHE=y
# CONFIG_CMD_TIME is not set
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(MLO),1920k(u-boot),256k(u-boot-env),8m(kernel),512k(dtb),-(rootfs)"
CONFIG_CMD_UBI=y
CONFIG_SPL_NAND_SIMPLE=y
CONFIG_MII=y
CONFIG_DRIVER_TI_EMAC=y
-# CONFIG_TWL4030_POWER is not set
CONFIG_PINCTRL=y
CONFIG_PINCTRL_SINGLE=y
+# CONFIG_TWL4030_POWER is not set
CONFIG_CONS_INDEX=3
-CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y
CONFIG_PHY_GIGE=y
CONFIG_MII=y
CONFIG_DM_SERIAL=y
-CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_TI_QSPI=y
CONFIG_TIMER=y
CONFIG_PHY_GIGE=y
CONFIG_MII=y
CONFIG_DM_SERIAL=y
-CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_TI_QSPI=y
CONFIG_TIMER=y
CONFIG_PHY_GIGE=y
CONFIG_MII=y
CONFIG_DM_SERIAL=y
-CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_TI_QSPI=y
CONFIG_TIMER=y
CONFIG_PHY_GIGE=y
CONFIG_MII=y
CONFIG_DM_SERIAL=y
-CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_TI_QSPI=y
CONFIG_TIMER=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_PALMAS=y
CONFIG_DM_SERIAL=y
-CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_TI_QSPI=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_PALMAS=y
CONFIG_DM_SERIAL=y
-CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_TI_QSPI=y
CONFIG_CMD_DATE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=mxc_nand.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=mxc_nand.0:1M(u-boot)ro,512K(env),512K(env2),512K(firmware),512K(dtb),5M(kernel),-(rootfs)"
CONFIG_CMD_UBI=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand"
CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:128k(bootstrap),1024k(boot),768k(env),-(root)"
CONFIG_CMD_UBI=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_CMD_UBI=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_FSL_ESDHC=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_CMD_UBI=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_FSL_ESDHC=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_CMD_UBI=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_FSL_ESDHC=y
CONFIG_AT91_GPIO=y
CONFIG_DM_MMC=y
CONFIG_GENERIC_ATMEL_MCI=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_NAND=y
CONFIG_NAND_ATMEL=y
CONFIG_DM_SPI_FLASH=y
CONFIG_AT91_GPIO=y
CONFIG_DM_MMC=y
CONFIG_GENERIC_ATMEL_MCI=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_NAND_ATMEL=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_AT91_GPIO=y
CONFIG_DM_MMC=y
CONFIG_GENERIC_ATMEL_MCI=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_NAND=y
CONFIG_NAND_ATMEL=y
CONFIG_DM_SPI_FLASH=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_CMD_UBI=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9g35ek"
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_CMD_UBI=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9g35ek"
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_CMD_UBI=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9g35ek"
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_CMD_UBI=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9g35ek"
CONFIG_BOOTDELAY=1
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot>"
+CONFIG_EFI_PARTITION=y
CONFIG_OF_PRIOR_STAGE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_BCMSTB=y
-CONFIG_CONS_INDEX=1
-CONFIG_EFI_LOADER=n
-CONFIG_EFI_PARTITION=y
+# CONFIG_EFI_LOADER is not set
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_BCMSTB=y
-CONFIG_CONS_INDEX=1
-CONFIG_EFI_LOADER=n
-CONFIG_SPI=y
+CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI=y
CONFIG_DM_SPI=y
-CONFIG_DM_SPI_FLASH=y
CONFIG_BCMSTB_SPI=y
+# CONFIG_EFI_LOADER is not set
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DRIVER_TI_CPSW=y
CONFIG_MII=y
-CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DRIVER_TI_CPSW=y
CONFIG_MII=y
-CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
CONFIG_DRIVER_TI_CPSW=y
# CONFIG_NETDEVICES is not set
CONFIG_DM_SERIAL=y
-CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_MUSB_HOST=y
CONFIG_DRIVER_TI_CPSW=y
# CONFIG_NETDEVICES is not set
CONFIG_DM_SERIAL=y
-CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_MUSB_HOST=y
CONFIG_DRIVER_TI_CPSW=y
# CONFIG_NETDEVICES is not set
CONFIG_DM_SERIAL=y
-CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_NAND=y
CONFIG_SPL_NAND_SIMPLE=y
CONFIG_CONS_INDEX=2
-CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_FAT_WRITE=y
CONFIG_NAND=y
CONFIG_DRIVER_TI_CPSW=y
CONFIG_MII=y
-CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_SPL_TIMER=y
-CONFIG_TIMER_EARLY=y
CONFIG_TPM_TIS_LPC=y
CONFIG_USB_STORAGE=y
CONFIG_USB_KEYBOARD=y
CONFIG_CROS_EC_LPC=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
-CONFIG_TIMER_EARLY=y
CONFIG_TPM_TIS_LPC=y
CONFIG_USB_STORAGE=y
CONFIG_USB_KEYBOARD=y
CONFIG_DM_KEYBOARD=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_NAND=y
CONFIG_NAND_MXS=y
CONFIG_SPI_FLASH=y
CONFIG_NAND=y
CONFIG_DRIVER_TI_CPSW=y
CONFIG_MII=y
-CONFIG_SYS_NS16550=y
CONFIG_FAT_WRITE=y
CONFIG_OF_LIBFDT=y
CONFIG_LED_STATUS_BOOT_ENABLE=y
CONFIG_LED_STATUS_BOOT=0
CONFIG_MMC_OMAP_HS=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_NAND=y
CONFIG_MII=y
CONFIG_SMC911X=y
CONFIG_LED_STATUS_BOOT=0
CONFIG_TWL4030_LED=y
CONFIG_MMC_OMAP_HS=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_NAND=y
CONFIG_SPL_NAND_SIMPLE=y
CONFIG_SMC911X=y
CONFIG_DRIVER_TI_CPSW=y
CONFIG_MII=y
CONFIG_DM_SERIAL=y
-CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_BMP=y
CONFIG_CMD_CACHE=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand"
CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:512k(mx6ull-bcb),1536k(u-boot1)ro,1536k(u-boot2)ro,512k(u-boot-env),-(ubi)"
CONFIG_CMD_UBI=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand"
CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:512k(mx7-bcb),1536k(u-boot1)ro,1536k(u-boot2)ro,512k(u-boot-env),-(ubi)"
CONFIG_CMD_UBI=y
CONFIG_DM_I2C=y
CONFIG_FSL_ESDHC=y
CONFIG_NAND=y
-CONFIG_NAND_MXS=y
CONFIG_MTD_UBI_FASTMAP=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=tegra_nand"
CONFIG_MTDPARTS_DEFAULT="mtdparts=tegra_nand:2m(u-boot)ro,1m(u-boot-env),1m(cfgblock)ro,-(ubi)"
CONFIG_CMD_UBI=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
+# CONFIG_CMDLINE_EDITING is not set
# CONFIG_AUTO_COMPLETE is not set
CONFIG_SYS_PROMPT="Colibri VFxx # "
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_FUSE=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_MMC=y
-CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_MII=y
CONFIG_DM_SERIAL=y
CONFIG_FSL_LPUART=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_FSL_DSPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_VIDEO=y
CONFIG_SYS_CONSOLE_FG_COL=0x00
CONFIG_OF_LIBFDT_OVERLAY=y
+# CONFIG_EFI_UNICODE_CAPITALIZATION is not set
CONFIG_CLK_AT91=y
CONFIG_DFU_NAND=y
# CONFIG_MMC is not set
-CONFIG_MTD_PARTITIONS=y
CONFIG_NAND=y
CONFIG_NAND_ATMEL=y
CONFIG_PHYLIB=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL=y
-CONFIG_SPL_DM=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
# CONFIG_CMD_FS_GENERIC is not set
CONFIG_CMD_DIAG=y
CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="da850-evm"
CONFIG_SPL_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="da850-evm"
CONFIG_SPL_OF_PLATDATA=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_DM=y
+CONFIG_SPL_DM=y
CONFIG_DA8XX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_DM_I2C_COMPAT=y
CONFIG_SYS_I2C_DAVINCI=y
CONFIG_MTD_DEVICE=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL=y
-CONFIG_SPL_DM=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_CMD_DIAG=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
-CONFIG_SPL_OF_PLATDATA=y
CONFIG_DEFAULT_DEVICE_TREE="da850-evm"
+CONFIG_SPL_OF_PLATDATA=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_DM=y
+CONFIG_SPL_DM=y
CONFIG_DM_GPIO=y
CONFIG_DA8XX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DAVINCI=y
CONFIG_DM_MMC=y
CONFIG_MTD_DEVICE=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_PINCTRL=y
-CONFIG_PINCTRL_SINGLE=y
CONFIG_SPI_FLASH_MTD=y
CONFIG_MII=y
CONFIG_DRIVER_TI_EMAC=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_SINGLE=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL=y
-CONFIG_SPL_DM=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_DEFAULT_DEVICE_TREE="da850-evm"
-CONFIG_SPL_OF_CONTROL=y
-CONFIG_SPL_OF_PLATDATA=y
CONFIG_SYS_EXTRA_OPTIONS="MAC_ADDR_IN_SPIFLASH"
CONFIG_BOOTDELAY=3
CONFIG_VERSION_VARIABLE=y
CONFIG_MTDPARTS_DEFAULT="mtdparts=nand512:128k(u-boot env),512k(u-boot),128k(spl-os),8m(kernel),-(rootfs)"
CONFIG_CMD_DIAG=y
CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="da850-evm"
+CONFIG_SPL_OF_PLATDATA=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_DM=y
+CONFIG_SPL_DM=y
CONFIG_DM_GPIO=y
CONFIG_DA8XX_GPIO=y
CONFIG_DM_I2C=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_NAND=y
CONFIG_NAND_DAVINCI=y
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
CONFIG_SPL_NAND_SIMPLE=y
CONFIG_CONS_INDEX=3
-CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_SYS_BOOTCOUNT_ADDR=0x020CC068
CONFIG_FSL_ESDHC=y
CONFIG_MTD_DEVICE=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_DFU_SF=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD_DEVICE=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_CMD_JFFS2=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=orion_nand"
CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:896k(u-boot),128k(u-boot-env),5m(kernel),-(rootfs)"
CONFIG_CMD_UBI=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_CMD_JFFS2=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:1m(uboot),-(root)"
CONFIG_CMD_UBI=y
CONFIG_ISO_PARTITION=y
CONFIG_DM_REGULATOR_LP873X=y
CONFIG_DM_SCSI=y
CONFIG_DM_SERIAL=y
-CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_TI_QSPI=y
CONFIG_DM_REGULATOR_LP873X=y
CONFIG_DM_SCSI=y
CONFIG_DM_SERIAL=y
-CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_TI_QSPI=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_EXT2=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:128k(spl),128k(spl.backup1),128k(spl.backup2),128k(spl.backup3),1920k(u-boot),512k(u-boot.env0),512k(u-boot.env1),512k(mtdoops),-(rootfs)"
CONFIG_CMD_UBI=y
CONFIG_MTD_UBI_FASTMAP=y
CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1
CONFIG_DRIVER_TI_CPSW=y
-CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
CONFIG_USB_GADGET_VENDOR_NUM=0x18d1
CONFIG_USB_GADGET_PRODUCT_NUM=0xd00d
CONFIG_CI_UDC=y
-CONFIG_USB_GADGET_DUALSPEED=n
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_ETHER_ASIX88179=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_CMD_JFFS2=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_CMD_UBI=y
CONFIG_ISO_PARTITION=y
CONFIG_DEFAULT_DEVICE_TREE="armada-xp-synology-ds414"
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_BMP=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_CMD_DIAG=y
CONFIG_CMD_UBI=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(xloader-nand),1024k(uboot-nand),256k(params-nand),5120k(kernel),-(ubifs)"
CONFIG_CMD_UBI=y
+++ /dev/null
-CONFIG_ARC=y
-CONFIG_ISA_ARCV2=y
-CONFIG_CPU_ARCEM6=y
-CONFIG_TARGET_EMDK=y
-CONFIG_SYS_TEXT_BASE=0x00000000
-CONFIG_SYS_CLK_FREQ=40000000
-# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
-CONFIG_VERSION_VARIABLE=y
-CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PROMPT="emdk# "
-# CONFIG_CMD_BOOTD is not set
-# CONFIG_CMD_XIMG is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_FAT=y
-CONFIG_OF_CONTROL=y
-CONFIG_OF_EMBED=y
-CONFIG_DEFAULT_DEVICE_TREE="emdk"
-CONFIG_ENV_IS_IN_FAT=y
-CONFIG_ENV_FAT_INTERFACE="mmc"
-CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
-# CONFIG_NET is not set
-CONFIG_DM=y
-CONFIG_MMC=y
-CONFIG_MMC_DW=y
-CONFIG_DM_SERIAL=y
-CONFIG_SYS_NS16550=y
-CONFIG_FS_FAT_MAX_CLUSTSIZE=4096
-CONFIG_USE_PRIVATE_LIBGCC=y
-CONFIG_PANIC_HANG=y
--- /dev/null
+CONFIG_ARC=y
+CONFIG_ISA_ARCV2=y
+CONFIG_CPU_ARCEM6=y
+CONFIG_TARGET_EMSDP=y
+CONFIG_SYS_TEXT_BASE=0x00000000
+CONFIG_SYS_CLK_FREQ=40000000
+# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
+CONFIG_VERSION_VARIABLE=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="emsdp# "
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_XIMG is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="emsdp"
+CONFIG_ENV_IS_IN_FAT=y
+CONFIG_ENV_FAT_INTERFACE="mmc"
+CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
+# CONFIG_NET is not set
+CONFIG_DM=y
+CONFIG_MMC=y
+CONFIG_MMC_DW=y
+CONFIG_DM_SERIAL=y
+CONFIG_SYS_NS16550=y
+CONFIG_FS_FAT_MAX_CLUSTSIZE=4096
+CONFIG_USE_PRIVATE_LIBGCC=y
+CONFIG_PANIC_HANG=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_EXT2=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand2=omap2-nand_concat"
CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand_concat:512k(spl),512k(spl.backup1),512k(spl.backup2),512k(spl.backup3),7680k(u-boot),2048k(u-boot.env0),2048k(u-boot.env1),2048k(mtdoops),-(rootfs)"
CONFIG_CMD_UBI=y
CONFIG_MTD_UBI_FASTMAP=y
CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1
CONFIG_DRIVER_TI_CPSW=y
-CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_CMD_JFFS2=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=atmel_nand"
CONFIG_MTDPARTS_DEFAULT="mtdparts=atmel_nand:-(root)"
CONFIG_CMD_REISER=y
CONFIG_SYSRESET=y
CONFIG_TIMER=y
CONFIG_WDT=y
+CONFIG_NETDEVICES=y
+CONFIG_PHY=y
+CONFIG_DM_ETH=y
+CONFIG_FTGMAC100=y
+CONFIG_PHY_REALTEK=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_MXC_GPIO=y
# CONFIG_MMC is not set
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_CMD_SPI=y
# CONFIG_CMD_NET is not set
CONFIG_CMD_TIME=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="spi-nand0=spi-nand0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=spi-nand0:-(ubi)"
CONFIG_CMD_UBI=y
CONFIG_CMD_SPI=y
# CONFIG_CMD_NET is not set
CONFIG_CMD_TIME=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="spi-nand0=spi-nand0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=spi-nand0:-(ubi)"
CONFIG_CMD_UBI=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_FAT=y
CONFIG_CMD_JFFS2=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=orion_nand"
CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:1m(uboot),6M(uImage),-(root)"
CONFIG_CMD_UBI=y
CONFIG_RENESAS_SDHI=y
CONFIG_MTD=y
CONFIG_MTD_DEVICE=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_FAT=y
CONFIG_CMD_JFFS2=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=orion_nand"
CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:896K(uboot),128K(uboot_env),-@1M(root)"
CONFIG_CMD_UBI=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=nand"
CONFIG_MTDPARTS_DEFAULT="mtdparts=nand:16m(uboot),1m(env),-(rootfs)"
CONFIG_CMD_UBI=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=nand"
CONFIG_MTDPARTS_DEFAULT="mtdparts=nand:16m(uboot),1m(env),-(rootfs)"
CONFIG_CMD_UBI=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=nand"
CONFIG_MTDPARTS_DEFAULT="mtdparts=nand:16m(uboot),1m(env),-(rootfs)"
CONFIG_CMD_UBI=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=tegra_nand"
CONFIG_MTDPARTS_DEFAULT="mtdparts=tegra_nand:2m(u-boot)ro,1m(u-boot-env),1m(cfgblock)ro,-(ubi)"
CONFIG_CMD_UBI=y
CONFIG_ENV_FAT_DEVICE_AND_PART="1:1"
CONFIG_MMC_DW=y
CONFIG_MMC_DW_K3=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_CONS_INDEX=4
CONFIG_USB=y
CONFIG_USB_DWC2=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_CMD_JFFS2=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:0xe0000@0x0(uboot),0x20000@0xe0000(uboot_env),-@0x100000(root)"
CONFIG_CMD_UBI=y
CONFIG_ISO_PARTITION=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_CMD_JFFS2=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:0x80000@0x0(uboot),0x20000@0x80000(uboot_env),-@0xa0000(rootfs)"
CONFIG_CMD_UBI=y
CONFIG_ISO_PARTITION=y
CONFIG_CMD_SNTP=y
CONFIG_CMD_DATE=y
CONFIG_CMD_JFFS2=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nor0=ff800000.flash,nand0=e1000000.flash"
CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:7m(dum),768k(BOOT-BIN),128k(BOOT-ENV),128k(BOOT-REDENV);e1000000.flash:-(ubi)"
CONFIG_CMD_UBI=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_CMD_UBI=y
# CONFIG_CMD_UBIFS is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SMC911X_BASE=0x2C000000
CONFIG_SMC911X_32_BIT=y
CONFIG_CONS_INDEX=3
-CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_CMD_UBI=y
# CONFIG_CMD_UBIFS is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SMC911X_BASE=0x2C000000
CONFIG_SMC911X_32_BIT=y
CONFIG_CONS_INDEX=3
-CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand"
CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:2m(spl),2m(uboot),1m(env),8m(kernel),1m(dtb),-(rootfs)"
CONFIG_CMD_UBI=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand"
CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:2m(spl),2m(uboot),1m(env),8m(kernel),1m(dtb),-(rootfs)"
CONFIG_CMD_UBI=y
# CONFIG_CMD_LED is not set
CONFIG_CMD_PMIC=y
CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand"
CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:2m(spl),2m(uboot),1m(env),16m(kernel),1m(dtb),-(fs)"
CONFIG_CMD_UBI=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand"
CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:2m(spl),2m(uboot),1m(env),8m(kernel),1m(dtb),-(rootfs)"
CONFIG_CMD_UBI=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand"
CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:2m(spl),2m(uboot),1m(env),8m(kernel),1m(dtb),-(rootfs)"
CONFIG_CMD_UBI=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand"
CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:2m(spl),2m(uboot),1m(env),8m(kernel),1m(dtb),-(rootfs)"
CONFIG_CMD_UBI=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand"
CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:2m(spl),2m(uboot),1m(env),8m(kernel),1m(dtb),-(rootfs)"
CONFIG_CMD_UBI=y
CONFIG_ARM=y
CONFIG_ARCH_IMX8=y
CONFIG_SYS_TEXT_BASE=0x80020000
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx8qxp_mek/imximage.cfg"
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_IMX8QXP_MEK=y
CONFIG_NR_DRAM_BANKS=3
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx8qxp_mek/imximage.cfg"
CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_CMD_CPU=y
# CONFIG_CMD_IMPORTENV is not set
CONFIG_CMD_CLK=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=davinci_nand.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=davinci_nand.0:128k(u-boot-env),1408k(u-boot),128k(bootparms),384k(factory-info),4M(kernel),-(rootfs)"
CONFIG_CMD_DIAG=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
+CONFIG_DRIVER_TI_KEYSTONE_NET=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
+CONFIG_DRIVER_TI_KEYSTONE_NET=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
+CONFIG_DRIVER_TI_KEYSTONE_NET=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
+CONFIG_DRIVER_TI_KEYSTONE_NET=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
+CONFIG_DRIVER_TI_KEYSTONE_NET=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
+CONFIG_DRIVER_TI_KEYSTONE_NET=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
+CONFIG_DRIVER_TI_KEYSTONE_NET=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
+CONFIG_DRIVER_TI_KEYSTONE_NET=y
CONFIG_DEBUG_UART_BASE=0xc81004c0
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_IDENT_STRING=" khadas-vim2"
-CONFIG_DEFAULT_DEVICE_TREE="meson-gxm-khadas-vim2"
CONFIG_DEBUG_UART=y
CONFIG_OF_BOARD_SETUP=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_REGULATOR=y
-CONFIG_ADC=y
-CONFIG_SARADC_MESON=y
CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="meson-gxm-khadas-vim2"
CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SARADC_MESON=y
CONFIG_DM_GPIO=y
-CONFIG_DM_REGULATOR=y
-CONFIG_DM_REGULATOR_FIXED=y
-CONFIG_DM_RESET=y
CONFIG_DM_MMC=y
CONFIG_MMC_MESON_GX=y
+CONFIG_MTD=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_PHY=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_MESON_GXL=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_RESET=y
CONFIG_DEBUG_UART_MESON=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_DEBUG_UART_SKIP_INIT=y
CONFIG_MESON_SERIAL=y
-CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3_OF_SIMPLE=y
CONFIG_USB_DWC3=y
CONFIG_USB_STORAGE=y
-CONFIG_PHY=y
-CONFIG_MESON_GXL_USB_PHY=y
-CONFIG_MTD=y
+CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_JFFS2=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=orion_nand"
CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:-(ubi0);"
CONFIG_CMD_UBI=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_JFFS2=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=orion_nand"
CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:-(ubi0);"
CONFIG_CMD_UBI=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_JFFS2=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=orion_nand"
CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:-(ubi0);"
CONFIG_CMD_UBI=y
CONFIG_MP=y
# CONFIG_CMD_HASH is not set
CONFIG_CMD_JFFS2=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=fsl_elbc_nand"
CONFIG_MTDPARTS_DEFAULT="mtdparts=fsl_elbc_nand:-(ubi0);"
# CONFIG_CMD_IRQ is not set
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_JFFS2=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nor0=boot,nand0=app"
CONFIG_MTDPARTS_DEFAULT="mtdparts=boot:768k(u-boot),128k(env),128k(envred),-(ubi0);app:-(ubi1);"
CONFIG_CMD_UBI=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_JFFS2=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=orion_nand"
CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:-(ubi0);"
CONFIG_CMD_UBI=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_JFFS2=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nor0=boot"
CONFIG_MTDPARTS_DEFAULT="mtdparts=boot:768k(u-boot),128k(env),128k(envred),-(ubi0);"
CONFIG_CMD_UBI=y
CONFIG_MP=y
# CONFIG_CMD_HASH is not set
CONFIG_CMD_JFFS2=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=fsl_elbc_nand"
CONFIG_MTDPARTS_DEFAULT="mtdparts=fsl_elbc_nand:-(ubi0);"
# CONFIG_CMD_IRQ is not set
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_JFFS2=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=orion_nand"
CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:-(ubi0);"
CONFIG_CMD_UBI=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_JFFS2=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nor0=boot"
CONFIG_MTDPARTS_DEFAULT="mtdparts=boot:768k(u-boot),128k(env),128k(envred),-(ubi0);"
CONFIG_CMD_UBI=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_JFFS2=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=orion_nand"
CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:-(ubi0);"
CONFIG_CMD_UBI=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_JFFS2=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nor0=boot"
CONFIG_MTDPARTS_DEFAULT="mtdparts=boot:768k(u-boot),128k(env),128k(envred),-(ubi0);"
CONFIG_CMD_UBI=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_JFFS2=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=orion_nand"
CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:-(ubi0);"
CONFIG_CMD_UBI=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_JFFS2=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nor0=boot,nand0=app"
CONFIG_MTDPARTS_DEFAULT="mtdparts=boot:768k(u-boot),256k(qe-fw),128k(env),128k(envred),-(ubi0);app:-(ubi1);"
CONFIG_CMD_DIAG=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_JFFS2=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nor0=boot"
CONFIG_MTDPARTS_DEFAULT="mtdparts=boot:768k(u-boot),128k(env),128k(envred),-(ubi0);"
CONFIG_CMD_UBI=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_JFFS2=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nor0=boot"
CONFIG_MTDPARTS_DEFAULT="mtdparts=boot:768k(u-boot),128k(env),128k(envred),-(ubi0);"
CONFIG_CMD_DIAG=y
CONFIG_RENESAS_SDHI=y
CONFIG_MTD=y
CONFIG_MTD_DEVICE=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_RENESAS_SDHI=y
CONFIG_MTD=y
CONFIG_MTD_DEVICE=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_VIDEO_FSL_DCU_FB=y
CONFIG_VIDEO=y
# CONFIG_VIDEO_SW_CURSOR is not set
-CONFIG_BLK=y
-CONFIG_DM_MMC=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_VIDEO_FSL_DCU_FB=y
CONFIG_VIDEO=y
# CONFIG_VIDEO_SW_CURSOR is not set
-CONFIG_BLK=y
-CONFIG_DM_MMC=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
CONFIG_PHYLIB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
-CONFIG_BLK=y
-CONFIG_DM_MMC=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
CONFIG_PHYLIB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
-CONFIG_BLK=y
-CONFIG_DM_MMC=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
-CONFIG_BLK=y
-CONFIG_DM_MMC=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
-CONFIG_BLK=y
-CONFIG_DM_MMC=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
CONFIG_PHYLIB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
-CONFIG_BLK=y
-CONFIG_DM_MMC=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb"
CONFIG_DM=y
+CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
-CONFIG_BLK=y
-CONFIG_DM_MMC=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
-CONFIG_BLK=y
-CONFIG_DM_MMC=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
CONFIG_PHYLIB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
-CONFIG_BLK=y
-CONFIG_DM_MMC=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SCSI_AHCI=y
+CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_RSA=y
CONFIG_RSA_SOFTWARE_EXP=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
-CONFIG_BLK=y
-CONFIG_DM_MMC=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SCSI_AHCI=y
+CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
-CONFIG_BLK=y
-CONFIG_DM_MMC=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SCSI_AHCI=y
+CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_USB_DWC3=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
-CONFIG_BLK=y
-CONFIG_DM_MMC=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SCSI_AHCI=y
+CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
-CONFIG_PHY_AQUANTIA=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_PCI=y
CONFIG_RSA=y
CONFIG_RSA_SOFTWARE_EXP=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
-CONFIG_BLK=y
-CONFIG_DM_MMC=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SCSI_AHCI=y
+CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
-CONFIG_PHY_AQUANTIA=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_PCI=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
-CONFIG_BLK=y
-CONFIG_DM_MMC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
-CONFIG_PHY_AQUANTIA=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_PCI=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SCSI_AHCI=y
+CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
-CONFIG_PHY_AQUANTIA=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_PCI=y
CONFIG_USB_DWC3=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
-CONFIG_BLK=y
-CONFIG_DM_MMC=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
-CONFIG_BLK=y
-CONFIG_DM_MMC=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_PHYLIB=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
-CONFIG_BLK=y
-CONFIG_DM_MMC=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_PHYLIB=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
-CONFIG_BLK=y
-CONFIG_DM_MMC=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
+CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_PHYLIB=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
-CONFIG_BLK=y
-CONFIG_DM_MMC=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2088a-rdb-qspi"
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
+CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_RSA=y
CONFIG_RSA_SOFTWARE_EXP=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
-CONFIG_BLK=y
-CONFIG_DM_MMC=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
-CONFIG_BLK=y
-CONFIG_DM_MMC=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=mxc_nand"
CONFIG_MTDPARTS_DEFAULT="mtdparts=mxc_nand:1m(u-boot),512k(env1),512k(env2),-(ubi)"
CONFIG_CMD_UBI=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_DM=y
CONFIG_FSL_ESDHC=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_MTD_DEVICE=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_DM=y
CONFIG_FSL_ESDHC=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_MTD_DEVICE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_CMD_JFFS2=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(MLO),1m(u-boot),256k(env1),256k(env2),6m(kernel),6m(k_recovery),8m(fs_recovery),-(common_data)"
CONFIG_CMD_UBI=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_JFFS2=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=orion_nand"
CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:-(ubi0);"
CONFIG_CMD_UBI=y
CONFIG_XILINX_GPIO=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_MTD_DEVICE=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(MLO),1m(u-boot),256k(env1),256k(env2),8m(ubisystem),-(rootfs)"
CONFIG_CMD_UBI=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand"
CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:3m(bootloader)ro,512k(environment),512k(redundant-environment),4m(kernel),512k(fdt),8m(ramdisk),-(filesystem)"
CONFIG_CMD_UBI=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand"
CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:3m(bootloader)ro,512k(environment),512k(redundant-environment),4m(kernel),512k(fdt),8m(ramdisk),-(filesystem)"
CONFIG_CMD_UBI=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand"
CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:3m(bootloader)ro,512k(environment),512k(redundant-environment),4m(kernel),512k(fdt),8m(ramdisk),-(filesystem)"
CONFIG_CMD_UBI=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand"
CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:3m(bootloader)ro,512k(environment),512k(redundant-environment),4m(kernel),512k(fdt),8m(ramdisk),-(filesystem)"
CONFIG_CMD_UBI=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_MXC_GPIO=y
CONFIG_FSL_ESDHC=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_FSL_ESDHC=y
CONFIG_NAND=y
CONFIG_NAND_MXS=y
-CONFIG_DM_SPI=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_SPI=y
+CONFIG_DM_SPI=y
CONFIG_FSL_QSPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
-CONFIG_CMD_SF=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PART=y
CONFIG_CMD_PCI=y
+CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
-CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_FSL_QSPI=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_MII=y
CONFIG_PCI=y
CONFIG_DM_REGULATOR_PFUZE100=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_QSPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_TARGET_MX6UL_14X14_EVK=y
-CONFIG_DEFAULT_DEVICE_TREE="imx6ul-14x14-evk"
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL=y
CONFIG_CMD_PING=y
CONFIG_CMD_BMP=y
CONFIG_CMD_CACHE=y
-CONFIG_CMD_NET=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6ul-14x14-evk"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
-CONFIG_DM_SPI=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_FSL_ESDHC=y
+CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
+CONFIG_DM_ETH=y
CONFIG_MII=y
-CONFIG_SPI=y
-CONFIG_SOFT_SPI=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_SOFT_SPI=y
CONFIG_FSL_QSPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_VIDEO=y
-CONFIG_DM_ETH=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_TARGET_MX6UL_9X9_EVK=y
-CONFIG_DEFAULT_DEVICE_TREE="imx6ul-9x9-evk"
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL=y
CONFIG_CMD_PING=y
CONFIG_CMD_BMP=y
CONFIG_CMD_CACHE=y
-CONFIG_CMD_NET=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6ul-9x9-evk"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
-CONFIG_DM_SPI=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_FSL_ESDHC=y
+CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
+CONFIG_DM_ETH=y
CONFIG_MII=y
-CONFIG_SPI=y
-CONFIG_SOFT_SPI=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_DM_PMIC=y
CONFIG_DM_REGULATOR_PFUZE100=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_SOFT_SPI=y
CONFIG_FSL_QSPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_VIDEO=y
-CONFIG_DM_ETH=y
# CONFIG_ARMV7_VIRT is not set
CONFIG_IMX_RDC=y
CONFIG_IMX_BOOTAUX=y
-# CONFIG_CMD_BMODE is not set
-CONFIG_DEFAULT_DEVICE_TREE="imx7d-sdb-qspi"
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7dsabresd/imximage.cfg"
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="imx7d-sdb-qspi"
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_DM_GPIO=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS200_SUPPORT=y
CONFIG_FSL_ESDHC=y
-CONFIG_FSL_QSPI=y
+CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_BAR=y
-CONFIG_MII=y
CONFIG_PHYLIB=y
+CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX7=y
CONFIG_DM_PMIC=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
-CONFIG_DM_SPI_FLASH=y
CONFIG_SOFT_SPI=y
+CONFIG_FSL_QSPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_FAT=y
CONFIG_CMD_JFFS2=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_CMD_UBI=y
CONFIG_ISO_PARTITION=y
CONFIG_EFI_PARTITION=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_CMD_JFFS2=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:0xe0000@0x0(uboot),0x20000@0xe0000(uboot_env),0x100000@0x100000(second_stage_uboot),-@0x200000(root)"
CONFIG_CMD_UBI=y
CONFIG_ISO_PARTITION=y
CONFIG_CMD_NAND=y
CONFIG_CMD_NAND_LOCK_UNLOCK=y
CONFIG_CMD_CACHE=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(MLO),1792k(u-boot),128k(spl-os),128k(u-boot-env),6m(kernel),-(fs)"
CONFIG_CMD_UBI=y
CONFIG_CMD_NAND=y
CONFIG_CMD_NAND_LOCK_UNLOCK=y
CONFIG_CMD_CACHE=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0,nor0=physmap-flash.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(MLO),1792k(u-boot),128k(spl-os),128k(u-boot-env),6m(kernel),-(fs);physmap-flash.0:-(nor)"
CONFIG_CMD_UBI=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FS_UUID=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(spl),1920k(u-boot),128k(u-boot-env),128k(dtb),6m(kernel),-(rootfs)"
CONFIG_CMD_UBI=y
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000
CONFIG_SPL_NAND_SIMPLE=y
-CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FS_UUID=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(spl),1920k(u-boot),128k(u-boot-env),128k(dtb),6m(kernel),-(rootfs)"
CONFIG_CMD_UBI=y
CONFIG_SMC911X=y
CONFIG_SMC911X_BASE=0x2C000000
CONFIG_SMC911X_32_BIT=y
-CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_CMD_NAND=y
CONFIG_CMD_NAND_LOCK_UNLOCK=y
CONFIG_CMD_CACHE=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(MLO),1792k(u-boot),128k(spl-os),128k(u-boot-env),6m(kernel),-(fs)"
CONFIG_CMD_UBI=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_SPECIFY_CONSOLE_INDEX=y
-CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_CMD_NAND=y
CONFIG_CMD_NAND_LOCK_UNLOCK=y
CONFIG_CMD_CACHE=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0,nor0=physmap-flash.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(MLO),1792k(u-boot),128k(spl-os),128k(u-boot-env),6m(kernel),-(fs);physmap-flash.0:-(nor)"
CONFIG_CMD_UBI=y
# CONFIG_CMD_NFS is not set
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(xloader),1792k(u-boot),256k(environ),8m(linux),-(rootfs)"
CONFIG_CMD_UBI=y
CONFIG_SMC911X_BASE=0x2C000000
CONFIG_SMC911X_32_BIT=y
CONFIG_CONS_INDEX=3
-CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
# CONFIG_CMD_NET is not set
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(xloader),1920k(uboot),128k(uboot-env),10m(boot),-(rootfs)"
CONFIG_CMD_UBI=y
CONFIG_NAND=y
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
CONFIG_DM_SERIAL=y
-CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_FAT_WRITE=y
CONFIG_SMC911X=y
CONFIG_SMC911X_BASE=0x08000000
CONFIG_SMC911X_32_BIT=y
-CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
# CONFIG_CMD_GPIO is not set
CONFIG_CMD_NAND=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_MTDPARTS=y
CONFIG_CMD_DIAG=y
CONFIG_CMD_UBI=y
CONFIG_OF_CONTROL=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_CMD_JFFS2=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=nand_mtd"
CONFIG_MTDPARTS_DEFAULT="mtdparts=nand_mtd:0x100000@0x000000(uboot),0x400000@0x100000(uImage),0x1fb00000@0x500000(rootfs)"
CONFIG_CMD_UBI=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_CMD_JFFS2=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=nand_mtd"
CONFIG_MTDPARTS_DEFAULT="mtdparts=nand_mtd:0x100000@0x000000(uboot),0x400000@0x100000(uImage),0x1fb00000@0x500000(rootfs)"
CONFIG_CMD_UBI=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_CMD_JFFS2=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=nand_mtd"
CONFIG_MTDPARTS_DEFAULT="mtdparts=nand_mtd:0x100000@0x000000(uboot),0x400000@0x100000(uImage),0x1fb00000@0x500000(rootfs)"
CONFIG_CMD_UBI=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DRIVER_TI_CPSW=y
CONFIG_MII=y
-CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DRIVER_TI_CPSW=y
CONFIG_MII=y
-CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
CONFIG_CMD_SF=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=nand"
CONFIG_MTDPARTS_DEFAULT="mtdparts=nand:16m(uboot),1m(env),-(rootfs)"
CONFIG_CMD_UBI=y
CONFIG_NAND=y
CONFIG_DRIVER_TI_CPSW=y
CONFIG_MII=y
-CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DRIVER_TI_CPSW=y
CONFIG_MII=y
-CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_FAT_WRITE=y
CONFIG_CMD_SF=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand"
CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:-(nand);spi2.0:1024k(bootloader),64k(env1),64k(env2),-(rescue)"
CONFIG_CMD_UBI=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand"
CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:14M(spl),2M(uboot),512k(env1),512k(env2),495M(ubi0),14M(res0),2M(res1),512k(res2),512k(res3),-(ubi1)"
CONFIG_CMD_UBI=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand"
CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:14M(spl),2M(uboot),512k(env1),512k(env2),-(ubi)"
CONFIG_CMD_UBI=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_CMD_JFFS2=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_CMD_UBI=y
CONFIG_ISO_PARTITION=y
CONFIG_OF_CONTROL=y
CONFIG_RENESAS_SDHI=y
CONFIG_MTD=y
CONFIG_MTD_DEVICE=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_JFFS2=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=orion_nand"
CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:-(ubi0);"
CONFIG_CMD_UBI=y
CONFIG_CMD_TIME=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:128k(spl),128k(spl.backup1),128k(spl.backup2),128k(spl.backup3),1920k(u-boot),128k(uboot.env),5120k(kernel_a),5120k(kernel_b),8192k(mtdoops),-(rootfs)"
CONFIG_CMD_UBI=y
CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1
CONFIG_DRIVER_TI_CPSW=y
CONFIG_MII=y
-CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
CONFIG_CMD_BOOTEFI_SELFTEST=y
CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
-CONFIG_CMD_DATE=y
CONFIG_OF_BOARD=y
CONFIG_SCSI_AHCI=y
CONFIG_AHCI_PCI=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_PCIE_ECAM_GENERIC=y
-CONFIG_RTC_PL031=y
CONFIG_SCSI=y
CONFIG_DM_SCSI=y
CONFIG_SYSRESET=y
CONFIG_CMD_BOOTEFI_SELFTEST=y
CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
-CONFIG_CMD_DATE=y
CONFIG_OF_BOARD=y
CONFIG_SCSI_AHCI=y
CONFIG_AHCI_PCI=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_PCIE_ECAM_GENERIC=y
-CONFIG_RTC_PL031=y
CONFIG_SCSI=y
CONFIG_DM_SCSI=y
CONFIG_SYSRESET=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_EXT2=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:128k(spl),128k(spl.backup1),128k(spl.backup2),128k(spl.backup3),1920k(u-boot),512k(u-boot.env0),512k(u-boot.env1),300m(rootfs),512k(mtdoops),-(configuration)"
CONFIG_CMD_UBI=y
CONFIG_MTD_UBI_FASTMAP=y
CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1
CONFIG_DRIVER_TI_CPSW=y
-CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
CONFIG_CMD_TIME=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:128k(spl),128k(spl.backup1),128k(spl.backup2),128k(spl.backup3),1920k(u-boot),128k(uboot.env),5120k(kernel_a),5120k(kernel_b),8192k(mtdoops),-(rootfs)"
CONFIG_CMD_UBI=y
CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1
CONFIG_DRIVER_TI_CPSW=y
CONFIG_MII=y
-CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_S5P=y
CONFIG_MTD_DEVICE=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_DM_PMIC=y
CONFIG_DM_PMIC_MAX8998=y
CONFIG_USB=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d2_ptc_ek"
-CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_IS_IN_FAT=y
CONFIG_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_CLK=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_CMD_UBI=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_CMD_UBI=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_SANDBOX64=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_NR_DRAM_BANKS=1
-CONFIG_ANDROID_BOOT_IMAGE=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
CONFIG_DEBUG_UART=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_NR_DRAM_BANKS=1
-CONFIG_ANDROID_BOOT_IMAGE=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
CONFIG_CMD_CPU=y
CONFIG_CMD_LICENSE=y
CONFIG_CMD_BOOTZ=y
-CONFIG_CMD_BOOTEFI_SELFTEST=y
# CONFIG_CMD_ELF is not set
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
CONFIG_CONSOLE_TRUETYPE=y
CONFIG_CONSOLE_TRUETYPE_CANTORAONE=y
CONFIG_VIDEO_SANDBOX_SDL=y
+CONFIG_OSD=y
+CONFIG_SANDBOX_OSD=y
CONFIG_W1=y
CONFIG_W1_GPIO=y
CONFIG_W1_EEPROM=y
CONFIG_W1_EEPROM_SANDBOX=y
-CONFIG_OSD=y
-CONFIG_SANDBOX_OSD=y
CONFIG_WDT=y
CONFIG_WDT_SANDBOX=y
CONFIG_FS_CBFS=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_NR_DRAM_BANKS=1
-CONFIG_ANDROID_BOOT_IMAGE=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
CONFIG_SANDBOX_SPL=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_NR_DRAM_BANKS=1
-CONFIG_ANDROID_BOOT_IMAGE=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_FAT=y
CONFIG_CMD_JFFS2=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=orion_nand"
CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:512K(uboot),512K(env),4M(kernel),-(rootfs)"
CONFIG_CMD_UBI=y
CONFIG_RENESAS_SDHI=y
CONFIG_MTD=y
CONFIG_MTD_DEVICE=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_CLK_AT91=y
CONFIG_DFU_NAND=y
# CONFIG_MMC is not set
-CONFIG_MTD_PARTITIONS=y
CONFIG_NAND=y
CONFIG_NAND_ATMEL=y
CONFIG_PHYLIB=y
CONFIG_ENV_IS_IN_ONENAND=y
# CONFIG_MMC is not set
CONFIG_MTD_DEVICE=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_SMC911X=y
CONFIG_SMC911X_BASE=0x98800300
CONFIG_TWL4030_INPUT=y
CONFIG_MMC_OMAP_HS=y
CONFIG_CONS_INDEX=3
-CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_MUSB_GADGET=y
CONFIG_USB_MUSB_OMAP2PLUS=y
CONFIG_DWAPB_GPIO=y
CONFIG_DM_MMC=y
CONFIG_MTD_DEVICE=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_MII=y
CONFIG_DM_MMC=y
CONFIG_MMC_DW=y
CONFIG_MTD_DEVICE=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_DM_ETH=y
CONFIG_PHY_GIGE=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_DM_MMC=y
CONFIG_MMC_DW=y
CONFIG_MTD_DEVICE=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH=y
CONFIG_DM_MMC=y
CONFIG_MMC_DW=y
CONFIG_MTD_DEVICE=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_MTD_DEVICE=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_PHY_GIGE=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_MII=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_MTD_DEVICE=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_NAND=y
CONFIG_PHY_GIGE=y
CONFIG_ETH_DESIGNWARE=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_MTD_DEVICE=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_PHY_GIGE=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_MII=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_MTD_DEVICE=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_NAND=y
CONFIG_PHY_GIGE=y
CONFIG_ETH_DESIGNWARE=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_MTD_DEVICE=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_PHY_GIGE=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_MII=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_MTD_DEVICE=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_NAND=y
CONFIG_PHY_GIGE=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_SYS_I2C_DW=y
# CONFIG_MMC is not set
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_MTD_DEVICE=y
CONFIG_FLASH_CFI_DRIVER=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_MTD_DEVICE=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_PHY_GIGE=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_MII=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_MTD_DEVICE=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_NAND=y
CONFIG_PHY_GIGE=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_SYS_I2C_DW=y
# CONFIG_MMC is not set
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_MTD_DEVICE=y
CONFIG_FLASH_CFI_DRIVER=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_MTD_DEVICE=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_PHY_GIGE=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_MII=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_MTD_DEVICE=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_NAND=y
CONFIG_PHY_GIGE=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_SYS_I2C_DW=y
# CONFIG_MMC is not set
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_MTD_DEVICE=y
CONFIG_FLASH_CFI_DRIVER=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_MTD_DEVICE=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_PHY_GIGE=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_MII=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_MTD_DEVICE=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_NAND=y
CONFIG_PHY_GIGE=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_SYS_I2C_DW=y
# CONFIG_MMC is not set
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_MTD_DEVICE=y
CONFIG_FLASH_CFI_DRIVER=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_MTD_DEVICE=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_PHY_GIGE=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_MII=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_MTD_DEVICE=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_NAND=y
CONFIG_PHY_GIGE=y
CONFIG_ETH_DESIGNWARE=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_MTD_DEVICE=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_PHY_GIGE=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_MII=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_MTD_DEVICE=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_NAND=y
CONFIG_PHY_GIGE=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_RENESAS_SDHI=y
CONFIG_MTD=y
CONFIG_MTD_DEVICE=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_JFFS2=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nor0=boot"
CONFIG_MTDPARTS_DEFAULT="mtdparts=boot:768k(u-boot),128k(env),128k(envred),-(ubi0);"
CONFIG_CMD_UBI=y
CONFIG_CLK_AT91=y
CONFIG_DFU_NAND=y
# CONFIG_MMC is not set
-CONFIG_MTD_PARTITIONS=y
CONFIG_NAND=y
CONFIG_NAND_ATMEL=y
CONFIG_SPI_FLASH=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_EXT2=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:128k(spl),128k(spl.backup1),128k(spl.backup2),128k(spl.backup3),1920k(u-boot),512k(u-boot.env0),512k(u-boot.env1),512k(mtdoops),-(rootfs)"
CONFIG_CMD_UBI=y
CONFIG_MTD_UBI_FASTMAP=y
CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1
CONFIG_DRIVER_TI_CPSW=y
-CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand"
CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:16M(uboot),512k(env1),512k(env2),-(ubi)"
CONFIG_CMD_UBI=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:128k(SPL),1m(u-boot),384k(u-boot-env1),1152k(mtdoops),384k(u-boot-env2),5m(kernel),2m(fdt),-(ubi)"
CONFIG_CMD_UBI=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:128k(SPL),1m(u-boot),384k(u-boot-env1),1152k(mtdoops),384k(u-boot-env2),5m(kernel),2m(fdt),-(ubi)"
CONFIG_CMD_UBI=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_JFFS2=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nor0=boot"
CONFIG_MTDPARTS_DEFAULT="mtdparts=boot:768k(u-boot),128k(env),128k(envred),-(ubi0);"
CONFIG_CMD_UBI=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_EARLY_INIT_R=y
-CONFIG_OF_BOARD_FIXUP=y
CONFIG_CMD_CLK=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_I2C=y
CONFIG_CMD_BTRFS=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_MAC_PARTITION=y
+CONFIG_OF_BOARD_FIXUP=y
CONFIG_DEFAULT_DEVICE_TREE="armada-3720-turris-mox"
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_CLK=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_PHY_GIGE=y
CONFIG_MVNETA=y
-CONFIG_MVEBU_COMPHY_SUPPORT=y
-CONFIG_PINCTRL=y
-CONFIG_PINCTRL_ARMADA_37XX=y
-CONFIG_DM_REGULATOR_FIXED=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_PCI_AARDVARK=y
# CONFIG_PCI_PNP is not set
+CONFIG_MVEBU_COMPHY_SUPPORT=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_ARMADA_37XX=y
+CONFIG_DM_REGULATOR_FIXED=y
# CONFIG_SPL_SERIAL_PRESENT is not set
CONFIG_DEBUG_MVEBU_A3700_UART=y
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_JFFS2=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nor0=boot"
CONFIG_MTDPARTS_DEFAULT="mtdparts=boot:768k(u-boot),128k(env),128k(envred),-(ubi0);"
CONFIG_CMD_UBI=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(MLO),1m(u-boot),256k(env1),256k(env2),6m(kernel),-(rootfs)"
CONFIG_CMD_UBI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
-CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd"
CONFIG_BOOTDELAY=3
-CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SATA=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_DM=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
# CONFIG_CMD_MISC is not set
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=uniphier-nand.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=uniphier-nand.0:1m(firmware),-(UBI)"
CONFIG_CMD_UBI=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
# CONFIG_CMD_MISC is not set
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=uniphier-nand.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=uniphier-nand.0:1m(firmware),-(UBI)"
CONFIG_CMD_UBI=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
# CONFIG_CMD_MISC is not set
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=uniphier-nand.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=uniphier-nand.0:1m(firmware),-(UBI)"
CONFIG_CMD_UBI=y
CONFIG_CMD_SNTP=y
CONFIG_CMD_FAT=y
CONFIG_CMD_JFFS2=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="onenand0=onenand"
CONFIG_MTDPARTS_DEFAULT="mtdparts=onenand:128k(u-boot),128k(env),20m(kernel),-(rootfs)"
CONFIG_CMD_UBI=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_MISC is not set
CONFIG_CMD_JFFS2=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="onenand0=onenand"
CONFIG_MTDPARTS_DEFAULT="mtdparts=onenand:128k(u-boot),128k(env),20m(kernel),-(rootfs)"
CONFIG_CMD_UBI=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
CONFIG_CMD_JFFS2=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="onenand0=onenand"
CONFIG_MTDPARTS_DEFAULT="mtdparts=onenand:128k(u-boot),128k(env),20m(kernel),-(rootfs)"
CONFIG_CMD_UBI=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_MISC is not set
CONFIG_CMD_JFFS2=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="onenand0=onenand"
CONFIG_MTDPARTS_DEFAULT="mtdparts=onenand:128k(u-boot),128k(env),20m(kernel),-(rootfs)"
CONFIG_CMD_UBI=y
CONFIG_CMD_SNTP=y
CONFIG_CMD_FAT=y
CONFIG_CMD_JFFS2=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="onenand0=onenand"
CONFIG_MTDPARTS_DEFAULT="mtdparts=onenand:128k(u-boot),128k(env),20m(kernel),-(rootfs)"
CONFIG_CMD_UBI=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_MISC is not set
CONFIG_CMD_JFFS2=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="onenand0=onenand"
CONFIG_MTDPARTS_DEFAULT="mtdparts=onenand:128k(u-boot),128k(env),20m(kernel),-(rootfs)"
CONFIG_CMD_UBI=y
CONFIG_ARM=y
CONFIG_ARCH_MX7=y
-CONFIG_SECURE_BOOT=y
CONFIG_SYS_TEXT_BASE=0x87800000
+CONFIG_SECURE_BOOT=y
CONFIG_TARGET_WARP7=y
CONFIG_ARMV7_BOOT_SEC_DEFAULT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/warp7/imximage.cfg"
CONFIG_CMD_PART=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
-CONFIG_CMD_SETEXPR=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DFU_MMC=y
CONFIG_FSL_ESDHC=y
+CONFIG_OPTEE=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_MXC_USB_OTG_HACTIVE=y
CONFIG_USB_ETH_CDC=y
CONFIG_USBNET_HOST_ADDR="de:ad:be:af:00:00"
CONFIG_OF_LIBFDT=y
-CONFIG_OPTEE=y
+CONFIG_OPTEE_LOAD_ADDR=0x84000000
CONFIG_OPTEE_TZDRAM_SIZE=0x3000000
CONFIG_OPTEE_TZDRAM_BASE=0x9d000000
-CONFIG_OPTEE_LOAD_ADDR=0x84000000
CONFIG_BOOTM_OPTEE=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_ENV_IS_IN_NAND=y
-CONFIG_MTD_DEVICE=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_NAND=y
CONFIG_NAND_ATMEL=y
CONFIG_LZMA=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_MXC_GPIO=y
CONFIG_FSL_ESDHC=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_MXC_GPIO=y
CONFIG_FSL_ESDHC=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_CMD_DATE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=nand"
CONFIG_MTDPARTS_DEFAULT="mtdparts=nand:64M(ubi0),64M(ubi1)"
CONFIG_CMD_UBI=y
--- /dev/null
+* MediaTek Frame Engine Ethernet controller
+
+Required properties:
+- compatible: should be "mediatek,mt7628-eth"
+- reg: address and length of the register set for the frame
+ engine ethernet controller and the internal switch.
+- syscon: phandle to the system controller
+
+Example:
+
+eth@10100000 {
+ compatible = "mediatek,mt7628-eth";
+ reg = <0x10100000 0x10000
+ 0x10110000 0x8000>;
+
+ syscon = <&sysc>;
+};
return rate;
}
+struct ast2500_clock_config {
+ ulong input_rate;
+ ulong rate;
+ struct ast2500_div_config cfg;
+};
+
+static const struct ast2500_clock_config ast2500_clock_config_defaults[] = {
+ { 24000000, 250000000, { .num = 124, .denum = 1, .post_div = 5 } },
+};
+
+static bool ast2500_get_clock_config_default(ulong input_rate,
+ ulong requested_rate,
+ struct ast2500_div_config *cfg)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(ast2500_clock_config_defaults); i++) {
+ const struct ast2500_clock_config *default_cfg =
+ &ast2500_clock_config_defaults[i];
+ if (default_cfg->input_rate == input_rate &&
+ default_cfg->rate == requested_rate) {
+ *cfg = default_cfg->cfg;
+ return true;
+ }
+ }
+
+ return false;
+}
+
/*
* @input_rate - the rate of input clock in Hz
* @requested_rate - desired output rate in Hz
ulong delta = rate_khz;
ulong new_rate_khz = 0;
+ /*
+ * Look for a well known frequency first.
+ */
+ if (ast2500_get_clock_config_default(input_rate, requested_rate, cfg))
+ return requested_rate;
+
for (; it.denum <= max_vals.denum; ++it.denum) {
for (it.post_div = 0; it.post_div <= max_vals.post_div;
++it.post_div) {
/*
* The values and the meaning of the next three
* parameters are undocumented. Taken from Aspeed SDK.
+ *
+ * TODO(clg@kaod.org): the SIP and SIC values depend on the
+ * Numerator value
*/
const u32 d2_pll_ext_param = 0x2c;
const u32 d2_pll_sip = 0x11;
break;
case PLL_D2PLL:
ast2500_configure_d2pll(priv->scu, D2PLL_DEFAULT_RATE);
+ break;
default:
return -ENOENT;
}
config DFU_NAND
bool "NAND back end for DFU"
+ depends on CMD_MTDPARTS
help
This option enables using DFU to read and write to NAND based
storage.
*/
int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
{
- unsigned long status;
+ int status;
/* disable all signals from hps peripheral controller to fpga */
writel(0, &system_manager_base->fpgaintf_en_global);
*/
int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
{
- unsigned long status;
+ int status;
if ((uint32_t)rbf_data & 0x3) {
puts("FPGA: Unaligned data, realign to 32bit boundary.\n");
struct ofnode_phandle_args *args)
{
desc->offset = args->args[0];
- desc->flags = args->args[1] & (GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0);
+ desc->flags = args->args[1] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0;
return 0;
}
} else if (mask & DWMCI_INTMSK_RE) {
debug("%s: Response Error.\n", __func__);
return -EIO;
+ } else if ((cmd->resp_type & MMC_RSP_CRC) &&
+ (mask & DWMCI_INTMSK_RCRC)) {
+ debug("%s: Response CRC Error.\n", __func__);
+ return -EIO;
}
#define RENESAS_SDHI_SCC_RVSREQ_RVSERR BIT(2)
#define RENESAS_SDHI_SCC_SMPCMP 0x818
#define RENESAS_SDHI_SCC_TMPPORT2 0x81c
+#define RENESAS_SDHI_SCC_TMPPORT2_HS400EN BIT(31)
+#define RENESAS_SDHI_SCC_TMPPORT2_HS400OSEL BIT(4)
#define RENESAS_SDHI_MAX_TAP 3
tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
/* Set sampling clock selection range */
- tmio_sd_writel(priv, 0x8 << RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT,
- RENESAS_SDHI_SCC_DTCNTL);
-
- reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_DTCNTL);
- reg |= RENESAS_SDHI_SCC_DTCNTL_TAPEN;
- tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_DTCNTL);
+ tmio_sd_writel(priv, (0x8 << RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) |
+ RENESAS_SDHI_SCC_DTCNTL_TAPEN,
+ RENESAS_SDHI_SCC_DTCNTL);
reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_CKSEL);
reg |= RENESAS_SDHI_SCC_CKSEL_DTSEL;
reg &= ~RENESAS_SDHI_SCC_CKSEL_DTSEL;
tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_CKSEL);
+ reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_TMPPORT2);
+ reg &= ~(RENESAS_SDHI_SCC_TMPPORT2_HS400EN |
+ RENESAS_SDHI_SCC_TMPPORT2_HS400OSEL);
+ tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_TMPPORT2);
+
reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
reg |= TMIO_SD_CLKCTL_SCLKEN;
tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
struct tmio_sd_priv *priv = dev_get_priv(dev);
- renesas_sdhi_reset_tuning(priv);
+ if (priv->caps & TMIO_SD_CAP_RCAR_UHS)
+ renesas_sdhi_reset_tuning(priv);
#endif
return ret;
}
+#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
+static int renesas_sdhi_wait_dat0(struct udevice *dev, int state, int timeout)
+{
+ int ret = -ETIMEDOUT;
+ bool dat0_high;
+ bool target_dat0_high = !!state;
+ struct tmio_sd_priv *priv = dev_get_priv(dev);
+
+ timeout = DIV_ROUND_UP(timeout, 10); /* check every 10 us. */
+ while (timeout--) {
+ dat0_high = !!(tmio_sd_readl(priv, TMIO_SD_INFO2) & TMIO_SD_INFO2_DAT0);
+ if (dat0_high == target_dat0_high) {
+ ret = 0;
+ break;
+ }
+ udelay(10);
+ }
+
+ return ret;
+}
+#endif
+
static const struct dm_mmc_ops renesas_sdhi_ops = {
.send_cmd = tmio_sd_send_cmd,
.set_ios = renesas_sdhi_set_ios,
.get_cd = tmio_sd_get_cd,
-#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
+#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
.execute_tuning = renesas_sdhi_execute_tuning,
#endif
+#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
+ .wait_dat0 = renesas_sdhi_wait_dat0,
+#endif
};
#define RENESAS_GEN2_QUIRKS TMIO_SD_CAP_RCAR_GEN2
ret = tmio_sd_probe(dev, quirks);
#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
- if (!ret)
+ if (!ret && (priv->caps & TMIO_SD_CAP_RCAR_UHS))
renesas_sdhi_reset_tuning(priv);
#endif
return ret;
invalidate_dcache_range(addr, addr + size);
}
-static int tmio_sd_check_error(struct udevice *dev)
+static int tmio_sd_check_error(struct udevice *dev, struct mmc_cmd *cmd)
{
struct tmio_sd_priv *priv = dev_get_priv(dev);
u32 info2 = tmio_sd_readl(priv, TMIO_SD_INFO2);
if (info2 & (TMIO_SD_INFO2_ERR_END | TMIO_SD_INFO2_ERR_CRC |
TMIO_SD_INFO2_ERR_IDX)) {
- dev_err(dev, "communication out of sync\n");
+ if ((cmd->cmdidx != MMC_CMD_SEND_TUNING_BLOCK) &&
+ (cmd->cmdidx != MMC_CMD_SEND_TUNING_BLOCK_HS200))
+ dev_err(dev, "communication out of sync\n");
return -EILSEQ;
}
return 0;
}
-static int tmio_sd_wait_for_irq(struct udevice *dev, unsigned int reg,
- u32 flag)
+static int tmio_sd_wait_for_irq(struct udevice *dev, struct mmc_cmd *cmd,
+ unsigned int reg, u32 flag)
{
struct tmio_sd_priv *priv = dev_get_priv(dev);
long wait = 1000000;
return -ETIMEDOUT;
}
- ret = tmio_sd_check_error(dev);
+ ret = tmio_sd_check_error(dev, cmd);
if (ret)
return ret;
tmio_pio_read_fifo(32, l)
tmio_pio_read_fifo(16, w)
-static int tmio_sd_pio_read_one_block(struct udevice *dev, char *pbuf,
- uint blocksize)
+static int tmio_sd_pio_read_one_block(struct udevice *dev, struct mmc_cmd *cmd,
+ char *pbuf, uint blocksize)
{
struct tmio_sd_priv *priv = dev_get_priv(dev);
int ret;
/* wait until the buffer is filled with data */
- ret = tmio_sd_wait_for_irq(dev, TMIO_SD_INFO2,
- TMIO_SD_INFO2_BRE);
+ ret = tmio_sd_wait_for_irq(dev, cmd, TMIO_SD_INFO2,
+ TMIO_SD_INFO2_BRE);
if (ret)
return ret;
tmio_pio_write_fifo(32, l)
tmio_pio_write_fifo(16, w)
-static int tmio_sd_pio_write_one_block(struct udevice *dev,
+static int tmio_sd_pio_write_one_block(struct udevice *dev, struct mmc_cmd *cmd,
const char *pbuf, uint blocksize)
{
struct tmio_sd_priv *priv = dev_get_priv(dev);
int ret;
/* wait until the buffer becomes empty */
- ret = tmio_sd_wait_for_irq(dev, TMIO_SD_INFO2,
- TMIO_SD_INFO2_BWE);
+ ret = tmio_sd_wait_for_irq(dev, cmd, TMIO_SD_INFO2,
+ TMIO_SD_INFO2_BWE);
if (ret)
return ret;
return 0;
}
-static int tmio_sd_pio_xfer(struct udevice *dev, struct mmc_data *data)
+static int tmio_sd_pio_xfer(struct udevice *dev, struct mmc_cmd *cmd,
+ struct mmc_data *data)
{
const char *src = data->src;
char *dest = data->dest;
for (i = 0; i < data->blocks; i++) {
if (data->flags & MMC_DATA_READ)
- ret = tmio_sd_pio_read_one_block(dev, dest,
+ ret = tmio_sd_pio_read_one_block(dev, cmd, dest,
data->blocksize);
else
- ret = tmio_sd_pio_write_one_block(dev, src,
+ ret = tmio_sd_pio_write_one_block(dev, cmd, src,
data->blocksize);
if (ret)
return ret;
cmd->cmdidx, tmp, cmd->cmdarg);
tmio_sd_writel(priv, tmp, TMIO_SD_CMD);
- ret = tmio_sd_wait_for_irq(dev, TMIO_SD_INFO1,
- TMIO_SD_INFO1_RSP);
+ ret = tmio_sd_wait_for_irq(dev, cmd, TMIO_SD_INFO1,
+ TMIO_SD_INFO1_RSP);
if (ret)
return ret;
tmio_sd_addr_is_dmaable(data->src))
ret = tmio_sd_dma_xfer(dev, data);
else
- ret = tmio_sd_pio_xfer(dev, data);
+ ret = tmio_sd_pio_xfer(dev, cmd, data);
+ if (ret)
+ return ret;
- ret = tmio_sd_wait_for_irq(dev, TMIO_SD_INFO1,
- TMIO_SD_INFO1_CMP);
+ ret = tmio_sd_wait_for_irq(dev, cmd, TMIO_SD_INFO1,
+ TMIO_SD_INFO1_CMP);
if (ret)
return ret;
}
- tmio_sd_wait_for_irq(dev, TMIO_SD_INFO2, TMIO_SD_INFO2_SCLKDIVEN);
-
- return ret;
+ return tmio_sd_wait_for_irq(dev, cmd, TMIO_SD_INFO2,
+ TMIO_SD_INFO2_SCLKDIVEN);
}
static int tmio_sd_set_bus_width(struct tmio_sd_priv *priv,
#endif
#ifdef CONFIG_PINCTRL
- switch (mmc->selected_mode) {
- case MMC_LEGACY:
- case SD_LEGACY:
- case MMC_HS:
- case SD_HS:
- case MMC_HS_52:
- case MMC_DDR_52:
- pinctrl_select_state(dev, "default");
- break;
- case UHS_SDR12:
- case UHS_SDR25:
- case UHS_SDR50:
- case UHS_DDR50:
- case UHS_SDR104:
- case MMC_HS_200:
+ if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180)
pinctrl_select_state(dev, "state_uhs");
- break;
- default:
- break;
- }
+ else
+ pinctrl_select_state(dev, "default");
#endif
}
dev_dbg(dev, "clock %uHz, DDRmode %d, width %u\n",
mmc->clock, mmc->ddr_mode, mmc->bus_width);
+ tmio_sd_set_clk_rate(priv, mmc);
ret = tmio_sd_set_bus_width(priv, mmc);
if (ret)
return ret;
tmio_sd_set_ddr_mode(priv, mmc);
- tmio_sd_set_clk_rate(priv, mmc);
tmio_sd_set_pins(dev);
return 0;
#ifdef CONFIG_DM_REGULATOR
device_get_supply_regulator(dev, "vqmmc-supply", &priv->vqmmc_dev);
+ if (priv->vqmmc_dev)
+ regulator_set_value(priv->vqmmc_dev, 3300000);
#endif
ret = mmc_of_parse(dev, &plat->cfg);
Adds the MTD device infrastructure from the Linux kernel.
Needed for mtdparts command support.
-config MTD_PARTITIONS
- bool "Add MTD Partioning infrastructure"
- help
- Adds the MTD partitioning infrastructure from the Linux
- kernel. Needed for UBI support.
-
config FLASH_CFI_DRIVER
bool "Enable CFI Flash driver"
help
#endif
#if defined(CONFIG_MTD_PARTITIONS)
+extern void board_mtdparts_default(const char **mtdids,
+ const char **mtdparts);
+
+static const char *get_mtdids(void)
+{
+ __maybe_unused const char *mtdparts = NULL;
+ const char *mtdids = env_get("mtdids");
+
+ if (mtdids)
+ return mtdids;
+
+#if defined(CONFIG_SYS_MTDPARTS_RUNTIME)
+ board_mtdparts_default(&mtdids, &mtdparts);
+#elif defined(MTDIDS_DEFAULT)
+ mtdids = MTDIDS_DEFAULT;
+#elif defined(CONFIG_MTDIDS_DEFAULT)
+ mtdids = CONFIG_MTDIDS_DEFAULT;
+#endif
+
+ if (mtdids)
+ env_set("mtdids", mtdids);
+
+ return mtdids;
+}
+
+#define MTDPARTS_MAXLEN 512
+
+static const char *get_mtdparts(void)
+{
+ __maybe_unused const char *mtdids = NULL;
+ static char tmp_parts[MTDPARTS_MAXLEN];
+ static bool use_defaults = true;
+ const char *mtdparts = NULL;
+
+ if (gd->flags & GD_FLG_ENV_READY)
+ mtdparts = env_get("mtdparts");
+ else if (env_get_f("mtdparts", tmp_parts, sizeof(tmp_parts)) != -1)
+ mtdparts = tmp_parts;
+
+ if (mtdparts || !use_defaults)
+ return mtdparts;
+
+#if defined(CONFIG_SYS_MTDPARTS_RUNTIME)
+ board_mtdparts_default(&mtdids, &mtdparts);
+#elif defined(MTDPARTS_DEFAULT)
+ mtdparts = MTDPARTS_DEFAULT;
+#elif defined(CONFIG_MTDPARTS_DEFAULT)
+ mtdparts = CONFIG_MTDPARTS_DEFAULT;
+#endif
+
+ if (mtdparts)
+ env_set("mtdparts", mtdparts);
+
+ use_defaults = false;
+
+ return mtdparts;
+}
+
int mtd_probe_devices(void)
{
static char *old_mtdparts;
static char *old_mtdids;
- const char *mtdparts = env_get("mtdparts");
- const char *mtdids = env_get("mtdids");
+ const char *mtdparts = get_mtdparts();
+ const char *mtdids = get_mtdids();
bool remaining_partitions = true;
struct mtd_info *mtd;
This is currently implemented in net/eth-uclass.c
Look in include/net.h for details.
-config DRIVER_TI_CPSW
- bool "TI Common Platform Ethernet Switch"
- select PHYLIB
- help
- This driver supports the TI three port switch gigabit ethernet
- subsystem found in the TI SoCs.
-
menuconfig NETDEVICES
bool "Network device support"
depends on NET
help
This MAC is present in Andestech SoCs.
+config FTGMAC100
+ bool "Ftgmac100 Ethernet Support"
+ depends on DM_ETH
+ select PHYLIB
+ help
+ This driver supports the Faraday's FTGMAC100 Gigabit SoC
+ Ethernet controller that can be found on Aspeed SoCs (which
+ include NCSI).
+
+ It is fully compliant with IEEE 802.3 specification for
+ 10/100 Mbps Ethernet and IEEE 802.3z specification for 1000
+ Mbps Ethernet and includes Reduced Media Independent
+ Interface (RMII) and Reduced Gigabit Media Independent
+ Interface (RGMII) interfaces. It adopts an AHB bus interface
+ and integrates a link list DMA engine with direct M-Bus
+ accesses for transmitting and receiving packets. It has
+ independent TX/RX fifos, supports half and full duplex (1000
+ Mbps mode only supports full duplex), flow control for full
+ duplex and backpressure for half duplex.
+
+ The FTGMAC100 also implements IP, TCP, UDP checksum offloads
+ and supports IEEE 802.1Q VLAN tag insertion and removal. It
+ offers high-priority transmit queue for QoS and CoS
+ applications.
+
+
config MVGBE
bool "Marvell Orion5x/Kirkwood network interface support"
depends on KIRKWOOD || ORION5X
The Cadence MACB ethernet interface was used on Zynq platform.
Say Y to enable support for the MACB/GEM in Zynq chip.
+config MT7628_ETH
+ bool "MediaTek MT7628 Ethernet Interface"
+ depends on ARCH_MT7620
+ help
+ The MediaTek MT7628 ethernet interface is used on MT7628 and
+ MT7688 based boards.
+
config PCH_GBE
bool "Intel Platform Controller Hub EG20T GMAC driver"
depends on DM_ETH && DM_PCI
help
This driver supports the Ethernet for Renesas SH and ARM SoCs.
-config DRIVER_TI_EMAC
- bool "TI Davinci EMAC"
- help
- Support for davinci emac
+source "drivers/net/ti/Kconfig"
config XILINX_AXIEMAC
depends on DM_ETH && (MICROBLAZE || ARCH_ZYNQ || ARCH_ZYNQMP)
obj-$(CONFIG_FTMAC110) += ftmac110.o
obj-$(CONFIG_FTMAC100) += ftmac100.o
obj-$(CONFIG_GMAC_ROCKCHIP) += gmac_rockchip.o
-obj-$(CONFIG_DRIVER_TI_KEYSTONE_NET) += keystone_net.o
obj-$(CONFIG_KS8851_MLL) += ks8851_mll.o
obj-$(CONFIG_LAN91C96) += lan91c96.o
obj-$(CONFIG_LPC32XX_ETH) += lpc32xx_eth.o
obj-$(CONFIG_MACB) += macb.o
obj-$(CONFIG_MCFFEC) += mcffec.o mcfmii.o
obj-$(CONFIG_MPC8XX_FEC) += mpc8xx_fec.o
+obj-$(CONFIG_MT7628_ETH) += mt7628-eth.o
obj-$(CONFIG_MVGBE) += mvgbe.o
obj-$(CONFIG_MVNETA) += mvneta.o
obj-$(CONFIG_MVPP2) += mvpp2.o
obj-$(CONFIG_RENESAS_RAVB) += ravb.o
obj-$(CONFIG_SMC91111) += smc91111.o
obj-$(CONFIG_SMC911X) += smc911x.o
-obj-$(CONFIG_DRIVER_TI_EMAC) += davinci_emac.o
obj-$(CONFIG_TSEC_ENET) += tsec.o fsl_mdio.o
-obj-$(CONFIG_DRIVER_TI_CPSW) += cpsw.o cpsw-common.o
obj-$(CONFIG_FMAN_ENET) += fsl_mdio.o
obj-$(CONFIG_ULI526X) += uli526x.o
obj-$(CONFIG_VSC7385_ENET) += vsc7385.o
obj-$(CONFIG_DWC_ETH_QOS) += dwc_eth_qos.o
obj-$(CONFIG_FSL_PFE) += pfe_eth/
obj-$(CONFIG_SNI_AVE) += sni_ave.o
+obj-y += ti/
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * CPSW common - libs used across TI ethernet devices.
- *
- * Copyright (C) 2016, Texas Instruments, Incorporated
- */
-
-#include <common.h>
-#include <dm.h>
-#include <environment.h>
-#include <fdt_support.h>
-#include <asm/io.h>
-#include <cpsw.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define CTRL_MAC_REG(offset, id) ((offset) + 0x8 * (id))
-
-static int davinci_emac_3517_get_macid(struct udevice *dev, u16 offset,
- int slave, u8 *mac_addr)
-{
- void *fdt = (void *)gd->fdt_blob;
- int node = dev_of_offset(dev);
- u32 macid_lsb;
- u32 macid_msb;
- fdt32_t gmii = 0;
- int syscon;
- u32 addr;
-
- syscon = fdtdec_lookup_phandle(fdt, node, "syscon");
- if (syscon < 0) {
- pr_err("Syscon offset not found\n");
- return -ENOENT;
- }
-
- addr = (u32)map_physmem(fdt_translate_address(fdt, syscon, &gmii),
- sizeof(u32), MAP_NOCACHE);
- if (addr == FDT_ADDR_T_NONE) {
- pr_err("Not able to get syscon address to get mac efuse address\n");
- return -ENOENT;
- }
-
- addr += CTRL_MAC_REG(offset, slave);
-
- /* try reading mac address from efuse */
- macid_lsb = readl(addr);
- macid_msb = readl(addr + 4);
-
- mac_addr[0] = (macid_msb >> 16) & 0xff;
- mac_addr[1] = (macid_msb >> 8) & 0xff;
- mac_addr[2] = macid_msb & 0xff;
- mac_addr[3] = (macid_lsb >> 16) & 0xff;
- mac_addr[4] = (macid_lsb >> 8) & 0xff;
- mac_addr[5] = macid_lsb & 0xff;
-
- return 0;
-}
-
-static int cpsw_am33xx_cm_get_macid(struct udevice *dev, u16 offset, int slave,
- u8 *mac_addr)
-{
- void *fdt = (void *)gd->fdt_blob;
- int node = dev_of_offset(dev);
- u32 macid_lo;
- u32 macid_hi;
- fdt32_t gmii = 0;
- int syscon;
- u32 addr;
-
- syscon = fdtdec_lookup_phandle(fdt, node, "syscon");
- if (syscon < 0) {
- pr_err("Syscon offset not found\n");
- return -ENOENT;
- }
-
- addr = (u32)map_physmem(fdt_translate_address(fdt, syscon, &gmii),
- sizeof(u32), MAP_NOCACHE);
- if (addr == FDT_ADDR_T_NONE) {
- pr_err("Not able to get syscon address to get mac efuse address\n");
- return -ENOENT;
- }
-
- addr += CTRL_MAC_REG(offset, slave);
-
- /* try reading mac address from efuse */
- macid_lo = readl(addr);
- macid_hi = readl(addr + 4);
-
- mac_addr[5] = (macid_lo >> 8) & 0xff;
- mac_addr[4] = macid_lo & 0xff;
- mac_addr[3] = (macid_hi >> 24) & 0xff;
- mac_addr[2] = (macid_hi >> 16) & 0xff;
- mac_addr[1] = (macid_hi >> 8) & 0xff;
- mac_addr[0] = macid_hi & 0xff;
-
- return 0;
-}
-
-int ti_cm_get_macid(struct udevice *dev, int slave, u8 *mac_addr)
-{
- if (of_machine_is_compatible("ti,dm8148"))
- return cpsw_am33xx_cm_get_macid(dev, 0x630, slave, mac_addr);
-
- if (of_machine_is_compatible("ti,am33xx"))
- return cpsw_am33xx_cm_get_macid(dev, 0x630, slave, mac_addr);
-
- if (device_is_compatible(dev, "ti,am3517-emac"))
- return davinci_emac_3517_get_macid(dev, 0x110, slave, mac_addr);
-
- if (device_is_compatible(dev, "ti,dm816-emac"))
- return cpsw_am33xx_cm_get_macid(dev, 0x30, slave, mac_addr);
-
- if (of_machine_is_compatible("ti,am43"))
- return cpsw_am33xx_cm_get_macid(dev, 0x630, slave, mac_addr);
-
- if (of_machine_is_compatible("ti,dra7"))
- return davinci_emac_3517_get_macid(dev, 0x514, slave, mac_addr);
-
- dev_err(dev, "incompatible machine/device type for reading mac address\n");
- return -ENOENT;
-}
+++ /dev/null
-/*
- * CPSW Ethernet Switch Driver
- *
- * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <common.h>
-#include <command.h>
-#include <net.h>
-#include <miiphy.h>
-#include <malloc.h>
-#include <net.h>
-#include <netdev.h>
-#include <cpsw.h>
-#include <linux/errno.h>
-#include <asm/gpio.h>
-#include <asm/io.h>
-#include <phy.h>
-#include <asm/arch/cpu.h>
-#include <dm.h>
-#include <fdt_support.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define BITMASK(bits) (BIT(bits) - 1)
-#define PHY_REG_MASK 0x1f
-#define PHY_ID_MASK 0x1f
-#define NUM_DESCS (PKTBUFSRX * 2)
-#define PKT_MIN 60
-#define PKT_MAX (1500 + 14 + 4 + 4)
-#define CLEAR_BIT 1
-#define GIGABITEN BIT(7)
-#define FULLDUPLEXEN BIT(0)
-#define MIIEN BIT(15)
-
-/* reg offset */
-#define CPSW_HOST_PORT_OFFSET 0x108
-#define CPSW_SLAVE0_OFFSET 0x208
-#define CPSW_SLAVE1_OFFSET 0x308
-#define CPSW_SLAVE_SIZE 0x100
-#define CPSW_CPDMA_OFFSET 0x800
-#define CPSW_HW_STATS 0x900
-#define CPSW_STATERAM_OFFSET 0xa00
-#define CPSW_CPTS_OFFSET 0xc00
-#define CPSW_ALE_OFFSET 0xd00
-#define CPSW_SLIVER0_OFFSET 0xd80
-#define CPSW_SLIVER1_OFFSET 0xdc0
-#define CPSW_BD_OFFSET 0x2000
-#define CPSW_MDIO_DIV 0xff
-
-#define AM335X_GMII_SEL_OFFSET 0x630
-
-/* DMA Registers */
-#define CPDMA_TXCONTROL 0x004
-#define CPDMA_RXCONTROL 0x014
-#define CPDMA_SOFTRESET 0x01c
-#define CPDMA_RXFREE 0x0e0
-#define CPDMA_TXHDP_VER1 0x100
-#define CPDMA_TXHDP_VER2 0x200
-#define CPDMA_RXHDP_VER1 0x120
-#define CPDMA_RXHDP_VER2 0x220
-#define CPDMA_TXCP_VER1 0x140
-#define CPDMA_TXCP_VER2 0x240
-#define CPDMA_RXCP_VER1 0x160
-#define CPDMA_RXCP_VER2 0x260
-
-/* Descriptor mode bits */
-#define CPDMA_DESC_SOP BIT(31)
-#define CPDMA_DESC_EOP BIT(30)
-#define CPDMA_DESC_OWNER BIT(29)
-#define CPDMA_DESC_EOQ BIT(28)
-
-/*
- * This timeout definition is a worst-case ultra defensive measure against
- * unexpected controller lock ups. Ideally, we should never ever hit this
- * scenario in practice.
- */
-#define MDIO_TIMEOUT 100 /* msecs */
-#define CPDMA_TIMEOUT 100 /* msecs */
-
-struct cpsw_mdio_regs {
- u32 version;
- u32 control;
-#define CONTROL_IDLE BIT(31)
-#define CONTROL_ENABLE BIT(30)
-
- u32 alive;
- u32 link;
- u32 linkintraw;
- u32 linkintmasked;
- u32 __reserved_0[2];
- u32 userintraw;
- u32 userintmasked;
- u32 userintmaskset;
- u32 userintmaskclr;
- u32 __reserved_1[20];
-
- struct {
- u32 access;
- u32 physel;
-#define USERACCESS_GO BIT(31)
-#define USERACCESS_WRITE BIT(30)
-#define USERACCESS_ACK BIT(29)
-#define USERACCESS_READ (0)
-#define USERACCESS_DATA (0xffff)
- } user[0];
-};
-
-struct cpsw_regs {
- u32 id_ver;
- u32 control;
- u32 soft_reset;
- u32 stat_port_en;
- u32 ptype;
-};
-
-struct cpsw_slave_regs {
- u32 max_blks;
- u32 blk_cnt;
- u32 flow_thresh;
- u32 port_vlan;
- u32 tx_pri_map;
-#ifdef CONFIG_AM33XX
- u32 gap_thresh;
-#elif defined(CONFIG_TI814X)
- u32 ts_ctl;
- u32 ts_seq_ltype;
- u32 ts_vlan;
-#endif
- u32 sa_lo;
- u32 sa_hi;
-};
-
-struct cpsw_host_regs {
- u32 max_blks;
- u32 blk_cnt;
- u32 flow_thresh;
- u32 port_vlan;
- u32 tx_pri_map;
- u32 cpdma_tx_pri_map;
- u32 cpdma_rx_chan_map;
-};
-
-struct cpsw_sliver_regs {
- u32 id_ver;
- u32 mac_control;
- u32 mac_status;
- u32 soft_reset;
- u32 rx_maxlen;
- u32 __reserved_0;
- u32 rx_pause;
- u32 tx_pause;
- u32 __reserved_1;
- u32 rx_pri_map;
-};
-
-#define ALE_ENTRY_BITS 68
-#define ALE_ENTRY_WORDS DIV_ROUND_UP(ALE_ENTRY_BITS, 32)
-
-/* ALE Registers */
-#define ALE_CONTROL 0x08
-#define ALE_UNKNOWNVLAN 0x18
-#define ALE_TABLE_CONTROL 0x20
-#define ALE_TABLE 0x34
-#define ALE_PORTCTL 0x40
-
-#define ALE_TABLE_WRITE BIT(31)
-
-#define ALE_TYPE_FREE 0
-#define ALE_TYPE_ADDR 1
-#define ALE_TYPE_VLAN 2
-#define ALE_TYPE_VLAN_ADDR 3
-
-#define ALE_UCAST_PERSISTANT 0
-#define ALE_UCAST_UNTOUCHED 1
-#define ALE_UCAST_OUI 2
-#define ALE_UCAST_TOUCHED 3
-
-#define ALE_MCAST_FWD 0
-#define ALE_MCAST_BLOCK_LEARN_FWD 1
-#define ALE_MCAST_FWD_LEARN 2
-#define ALE_MCAST_FWD_2 3
-
-enum cpsw_ale_port_state {
- ALE_PORT_STATE_DISABLE = 0x00,
- ALE_PORT_STATE_BLOCK = 0x01,
- ALE_PORT_STATE_LEARN = 0x02,
- ALE_PORT_STATE_FORWARD = 0x03,
-};
-
-/* ALE unicast entry flags - passed into cpsw_ale_add_ucast() */
-#define ALE_SECURE 1
-#define ALE_BLOCKED 2
-
-struct cpsw_slave {
- struct cpsw_slave_regs *regs;
- struct cpsw_sliver_regs *sliver;
- int slave_num;
- u32 mac_control;
- struct cpsw_slave_data *data;
-};
-
-struct cpdma_desc {
- /* hardware fields */
- u32 hw_next;
- u32 hw_buffer;
- u32 hw_len;
- u32 hw_mode;
- /* software fields */
- u32 sw_buffer;
- u32 sw_len;
-};
-
-struct cpdma_chan {
- struct cpdma_desc *head, *tail;
- void *hdp, *cp, *rxfree;
-};
-
-/* AM33xx SoC specific definitions for the CONTROL port */
-#define AM33XX_GMII_SEL_MODE_MII 0
-#define AM33XX_GMII_SEL_MODE_RMII 1
-#define AM33XX_GMII_SEL_MODE_RGMII 2
-
-#define AM33XX_GMII_SEL_RGMII1_IDMODE BIT(4)
-#define AM33XX_GMII_SEL_RGMII2_IDMODE BIT(5)
-#define AM33XX_GMII_SEL_RMII1_IO_CLK_EN BIT(6)
-#define AM33XX_GMII_SEL_RMII2_IO_CLK_EN BIT(7)
-
-#define GMII_SEL_MODE_MASK 0x3
-
-#define desc_write(desc, fld, val) __raw_writel((u32)(val), &(desc)->fld)
-#define desc_read(desc, fld) __raw_readl(&(desc)->fld)
-#define desc_read_ptr(desc, fld) ((void *)__raw_readl(&(desc)->fld))
-
-#define chan_write(chan, fld, val) __raw_writel((u32)(val), (chan)->fld)
-#define chan_read(chan, fld) __raw_readl((chan)->fld)
-#define chan_read_ptr(chan, fld) ((void *)__raw_readl((chan)->fld))
-
-#define for_active_slave(slave, priv) \
- slave = (priv)->slaves + (priv)->data.active_slave; if (slave)
-#define for_each_slave(slave, priv) \
- for (slave = (priv)->slaves; slave != (priv)->slaves + \
- (priv)->data.slaves; slave++)
-
-struct cpsw_priv {
-#ifdef CONFIG_DM_ETH
- struct udevice *dev;
-#else
- struct eth_device *dev;
-#endif
- struct cpsw_platform_data data;
- int host_port;
-
- struct cpsw_regs *regs;
- void *dma_regs;
- struct cpsw_host_regs *host_port_regs;
- void *ale_regs;
-
- struct cpdma_desc *descs;
- struct cpdma_desc *desc_free;
- struct cpdma_chan rx_chan, tx_chan;
-
- struct cpsw_slave *slaves;
- struct phy_device *phydev;
- struct mii_dev *bus;
-
- u32 phy_mask;
-};
-
-static inline int cpsw_ale_get_field(u32 *ale_entry, u32 start, u32 bits)
-{
- int idx;
-
- idx = start / 32;
- start -= idx * 32;
- idx = 2 - idx; /* flip */
- return (ale_entry[idx] >> start) & BITMASK(bits);
-}
-
-static inline void cpsw_ale_set_field(u32 *ale_entry, u32 start, u32 bits,
- u32 value)
-{
- int idx;
-
- value &= BITMASK(bits);
- idx = start / 32;
- start -= idx * 32;
- idx = 2 - idx; /* flip */
- ale_entry[idx] &= ~(BITMASK(bits) << start);
- ale_entry[idx] |= (value << start);
-}
-
-#define DEFINE_ALE_FIELD(name, start, bits) \
-static inline int cpsw_ale_get_##name(u32 *ale_entry) \
-{ \
- return cpsw_ale_get_field(ale_entry, start, bits); \
-} \
-static inline void cpsw_ale_set_##name(u32 *ale_entry, u32 value) \
-{ \
- cpsw_ale_set_field(ale_entry, start, bits, value); \
-}
-
-DEFINE_ALE_FIELD(entry_type, 60, 2)
-DEFINE_ALE_FIELD(mcast_state, 62, 2)
-DEFINE_ALE_FIELD(port_mask, 66, 3)
-DEFINE_ALE_FIELD(ucast_type, 62, 2)
-DEFINE_ALE_FIELD(port_num, 66, 2)
-DEFINE_ALE_FIELD(blocked, 65, 1)
-DEFINE_ALE_FIELD(secure, 64, 1)
-DEFINE_ALE_FIELD(mcast, 40, 1)
-
-/* The MAC address field in the ALE entry cannot be macroized as above */
-static inline void cpsw_ale_get_addr(u32 *ale_entry, u8 *addr)
-{
- int i;
-
- for (i = 0; i < 6; i++)
- addr[i] = cpsw_ale_get_field(ale_entry, 40 - 8*i, 8);
-}
-
-static inline void cpsw_ale_set_addr(u32 *ale_entry, const u8 *addr)
-{
- int i;
-
- for (i = 0; i < 6; i++)
- cpsw_ale_set_field(ale_entry, 40 - 8*i, 8, addr[i]);
-}
-
-static int cpsw_ale_read(struct cpsw_priv *priv, int idx, u32 *ale_entry)
-{
- int i;
-
- __raw_writel(idx, priv->ale_regs + ALE_TABLE_CONTROL);
-
- for (i = 0; i < ALE_ENTRY_WORDS; i++)
- ale_entry[i] = __raw_readl(priv->ale_regs + ALE_TABLE + 4 * i);
-
- return idx;
-}
-
-static int cpsw_ale_write(struct cpsw_priv *priv, int idx, u32 *ale_entry)
-{
- int i;
-
- for (i = 0; i < ALE_ENTRY_WORDS; i++)
- __raw_writel(ale_entry[i], priv->ale_regs + ALE_TABLE + 4 * i);
-
- __raw_writel(idx | ALE_TABLE_WRITE, priv->ale_regs + ALE_TABLE_CONTROL);
-
- return idx;
-}
-
-static int cpsw_ale_match_addr(struct cpsw_priv *priv, const u8 *addr)
-{
- u32 ale_entry[ALE_ENTRY_WORDS];
- int type, idx;
-
- for (idx = 0; idx < priv->data.ale_entries; idx++) {
- u8 entry_addr[6];
-
- cpsw_ale_read(priv, idx, ale_entry);
- type = cpsw_ale_get_entry_type(ale_entry);
- if (type != ALE_TYPE_ADDR && type != ALE_TYPE_VLAN_ADDR)
- continue;
- cpsw_ale_get_addr(ale_entry, entry_addr);
- if (memcmp(entry_addr, addr, 6) == 0)
- return idx;
- }
- return -ENOENT;
-}
-
-static int cpsw_ale_match_free(struct cpsw_priv *priv)
-{
- u32 ale_entry[ALE_ENTRY_WORDS];
- int type, idx;
-
- for (idx = 0; idx < priv->data.ale_entries; idx++) {
- cpsw_ale_read(priv, idx, ale_entry);
- type = cpsw_ale_get_entry_type(ale_entry);
- if (type == ALE_TYPE_FREE)
- return idx;
- }
- return -ENOENT;
-}
-
-static int cpsw_ale_find_ageable(struct cpsw_priv *priv)
-{
- u32 ale_entry[ALE_ENTRY_WORDS];
- int type, idx;
-
- for (idx = 0; idx < priv->data.ale_entries; idx++) {
- cpsw_ale_read(priv, idx, ale_entry);
- type = cpsw_ale_get_entry_type(ale_entry);
- if (type != ALE_TYPE_ADDR && type != ALE_TYPE_VLAN_ADDR)
- continue;
- if (cpsw_ale_get_mcast(ale_entry))
- continue;
- type = cpsw_ale_get_ucast_type(ale_entry);
- if (type != ALE_UCAST_PERSISTANT &&
- type != ALE_UCAST_OUI)
- return idx;
- }
- return -ENOENT;
-}
-
-static int cpsw_ale_add_ucast(struct cpsw_priv *priv, const u8 *addr,
- int port, int flags)
-{
- u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
- int idx;
-
- cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_ADDR);
- cpsw_ale_set_addr(ale_entry, addr);
- cpsw_ale_set_ucast_type(ale_entry, ALE_UCAST_PERSISTANT);
- cpsw_ale_set_secure(ale_entry, (flags & ALE_SECURE) ? 1 : 0);
- cpsw_ale_set_blocked(ale_entry, (flags & ALE_BLOCKED) ? 1 : 0);
- cpsw_ale_set_port_num(ale_entry, port);
-
- idx = cpsw_ale_match_addr(priv, addr);
- if (idx < 0)
- idx = cpsw_ale_match_free(priv);
- if (idx < 0)
- idx = cpsw_ale_find_ageable(priv);
- if (idx < 0)
- return -ENOMEM;
-
- cpsw_ale_write(priv, idx, ale_entry);
- return 0;
-}
-
-static int cpsw_ale_add_mcast(struct cpsw_priv *priv, const u8 *addr,
- int port_mask)
-{
- u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
- int idx, mask;
-
- idx = cpsw_ale_match_addr(priv, addr);
- if (idx >= 0)
- cpsw_ale_read(priv, idx, ale_entry);
-
- cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_ADDR);
- cpsw_ale_set_addr(ale_entry, addr);
- cpsw_ale_set_mcast_state(ale_entry, ALE_MCAST_FWD_2);
-
- mask = cpsw_ale_get_port_mask(ale_entry);
- port_mask |= mask;
- cpsw_ale_set_port_mask(ale_entry, port_mask);
-
- if (idx < 0)
- idx = cpsw_ale_match_free(priv);
- if (idx < 0)
- idx = cpsw_ale_find_ageable(priv);
- if (idx < 0)
- return -ENOMEM;
-
- cpsw_ale_write(priv, idx, ale_entry);
- return 0;
-}
-
-static inline void cpsw_ale_control(struct cpsw_priv *priv, int bit, int val)
-{
- u32 tmp, mask = BIT(bit);
-
- tmp = __raw_readl(priv->ale_regs + ALE_CONTROL);
- tmp &= ~mask;
- tmp |= val ? mask : 0;
- __raw_writel(tmp, priv->ale_regs + ALE_CONTROL);
-}
-
-#define cpsw_ale_enable(priv, val) cpsw_ale_control(priv, 31, val)
-#define cpsw_ale_clear(priv, val) cpsw_ale_control(priv, 30, val)
-#define cpsw_ale_vlan_aware(priv, val) cpsw_ale_control(priv, 2, val)
-
-static inline void cpsw_ale_port_state(struct cpsw_priv *priv, int port,
- int val)
-{
- int offset = ALE_PORTCTL + 4 * port;
- u32 tmp, mask = 0x3;
-
- tmp = __raw_readl(priv->ale_regs + offset);
- tmp &= ~mask;
- tmp |= val & mask;
- __raw_writel(tmp, priv->ale_regs + offset);
-}
-
-static struct cpsw_mdio_regs *mdio_regs;
-
-/* wait until hardware is ready for another user access */
-static inline u32 wait_for_user_access(void)
-{
- u32 reg = 0;
- int timeout = MDIO_TIMEOUT;
-
- while (timeout-- &&
- ((reg = __raw_readl(&mdio_regs->user[0].access)) & USERACCESS_GO))
- udelay(10);
-
- if (timeout == -1) {
- printf("wait_for_user_access Timeout\n");
- return -ETIMEDOUT;
- }
- return reg;
-}
-
-/* wait until hardware state machine is idle */
-static inline void wait_for_idle(void)
-{
- int timeout = MDIO_TIMEOUT;
-
- while (timeout-- &&
- ((__raw_readl(&mdio_regs->control) & CONTROL_IDLE) == 0))
- udelay(10);
-
- if (timeout == -1)
- printf("wait_for_idle Timeout\n");
-}
-
-static int cpsw_mdio_read(struct mii_dev *bus, int phy_id,
- int dev_addr, int phy_reg)
-{
- int data;
- u32 reg;
-
- if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK)
- return -EINVAL;
-
- wait_for_user_access();
- reg = (USERACCESS_GO | USERACCESS_READ | (phy_reg << 21) |
- (phy_id << 16));
- __raw_writel(reg, &mdio_regs->user[0].access);
- reg = wait_for_user_access();
-
- data = (reg & USERACCESS_ACK) ? (reg & USERACCESS_DATA) : -1;
- return data;
-}
-
-static int cpsw_mdio_write(struct mii_dev *bus, int phy_id, int dev_addr,
- int phy_reg, u16 data)
-{
- u32 reg;
-
- if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK)
- return -EINVAL;
-
- wait_for_user_access();
- reg = (USERACCESS_GO | USERACCESS_WRITE | (phy_reg << 21) |
- (phy_id << 16) | (data & USERACCESS_DATA));
- __raw_writel(reg, &mdio_regs->user[0].access);
- wait_for_user_access();
-
- return 0;
-}
-
-static void cpsw_mdio_init(const char *name, u32 mdio_base, u32 div)
-{
- struct mii_dev *bus = mdio_alloc();
-
- mdio_regs = (struct cpsw_mdio_regs *)mdio_base;
-
- /* set enable and clock divider */
- __raw_writel(div | CONTROL_ENABLE, &mdio_regs->control);
-
- /*
- * wait for scan logic to settle:
- * the scan time consists of (a) a large fixed component, and (b) a
- * small component that varies with the mii bus frequency. These
- * were estimated using measurements at 1.1 and 2.2 MHz on tnetv107x
- * silicon. Since the effect of (b) was found to be largely
- * negligible, we keep things simple here.
- */
- udelay(1000);
-
- bus->read = cpsw_mdio_read;
- bus->write = cpsw_mdio_write;
- strcpy(bus->name, name);
-
- mdio_register(bus);
-}
-
-/* Set a self-clearing bit in a register, and wait for it to clear */
-static inline void setbit_and_wait_for_clear32(void *addr)
-{
- __raw_writel(CLEAR_BIT, addr);
- while (__raw_readl(addr) & CLEAR_BIT)
- ;
-}
-
-#define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \
- ((mac)[2] << 16) | ((mac)[3] << 24))
-#define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8))
-
-static void cpsw_set_slave_mac(struct cpsw_slave *slave,
- struct cpsw_priv *priv)
-{
-#ifdef CONFIG_DM_ETH
- struct eth_pdata *pdata = dev_get_platdata(priv->dev);
-
- writel(mac_hi(pdata->enetaddr), &slave->regs->sa_hi);
- writel(mac_lo(pdata->enetaddr), &slave->regs->sa_lo);
-#else
- __raw_writel(mac_hi(priv->dev->enetaddr), &slave->regs->sa_hi);
- __raw_writel(mac_lo(priv->dev->enetaddr), &slave->regs->sa_lo);
-#endif
-}
-
-static int cpsw_slave_update_link(struct cpsw_slave *slave,
- struct cpsw_priv *priv, int *link)
-{
- struct phy_device *phy;
- u32 mac_control = 0;
- int ret = -ENODEV;
-
- phy = priv->phydev;
- if (!phy)
- goto out;
-
- ret = phy_startup(phy);
- if (ret)
- goto out;
-
- if (link)
- *link = phy->link;
-
- if (phy->link) { /* link up */
- mac_control = priv->data.mac_control;
- if (phy->speed == 1000)
- mac_control |= GIGABITEN;
- if (phy->duplex == DUPLEX_FULL)
- mac_control |= FULLDUPLEXEN;
- if (phy->speed == 100)
- mac_control |= MIIEN;
- }
-
- if (mac_control == slave->mac_control)
- goto out;
-
- if (mac_control) {
- printf("link up on port %d, speed %d, %s duplex\n",
- slave->slave_num, phy->speed,
- (phy->duplex == DUPLEX_FULL) ? "full" : "half");
- } else {
- printf("link down on port %d\n", slave->slave_num);
- }
-
- __raw_writel(mac_control, &slave->sliver->mac_control);
- slave->mac_control = mac_control;
-
-out:
- return ret;
-}
-
-static int cpsw_update_link(struct cpsw_priv *priv)
-{
- int ret = -ENODEV;
- struct cpsw_slave *slave;
-
- for_active_slave(slave, priv)
- ret = cpsw_slave_update_link(slave, priv, NULL);
-
- return ret;
-}
-
-static inline u32 cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num)
-{
- if (priv->host_port == 0)
- return slave_num + 1;
- else
- return slave_num;
-}
-
-static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv)
-{
- u32 slave_port;
-
- setbit_and_wait_for_clear32(&slave->sliver->soft_reset);
-
- /* setup priority mapping */
- __raw_writel(0x76543210, &slave->sliver->rx_pri_map);
- __raw_writel(0x33221100, &slave->regs->tx_pri_map);
-
- /* setup max packet size, and mac address */
- __raw_writel(PKT_MAX, &slave->sliver->rx_maxlen);
- cpsw_set_slave_mac(slave, priv);
-
- slave->mac_control = 0; /* no link yet */
-
- /* enable forwarding */
- slave_port = cpsw_get_slave_port(priv, slave->slave_num);
- cpsw_ale_port_state(priv, slave_port, ALE_PORT_STATE_FORWARD);
-
- cpsw_ale_add_mcast(priv, net_bcast_ethaddr, 1 << slave_port);
-
- priv->phy_mask |= 1 << slave->data->phy_addr;
-}
-
-static struct cpdma_desc *cpdma_desc_alloc(struct cpsw_priv *priv)
-{
- struct cpdma_desc *desc = priv->desc_free;
-
- if (desc)
- priv->desc_free = desc_read_ptr(desc, hw_next);
- return desc;
-}
-
-static void cpdma_desc_free(struct cpsw_priv *priv, struct cpdma_desc *desc)
-{
- if (desc) {
- desc_write(desc, hw_next, priv->desc_free);
- priv->desc_free = desc;
- }
-}
-
-static int cpdma_submit(struct cpsw_priv *priv, struct cpdma_chan *chan,
- void *buffer, int len)
-{
- struct cpdma_desc *desc, *prev;
- u32 mode;
-
- desc = cpdma_desc_alloc(priv);
- if (!desc)
- return -ENOMEM;
-
- if (len < PKT_MIN)
- len = PKT_MIN;
-
- mode = CPDMA_DESC_OWNER | CPDMA_DESC_SOP | CPDMA_DESC_EOP;
-
- desc_write(desc, hw_next, 0);
- desc_write(desc, hw_buffer, buffer);
- desc_write(desc, hw_len, len);
- desc_write(desc, hw_mode, mode | len);
- desc_write(desc, sw_buffer, buffer);
- desc_write(desc, sw_len, len);
-
- if (!chan->head) {
- /* simple case - first packet enqueued */
- chan->head = desc;
- chan->tail = desc;
- chan_write(chan, hdp, desc);
- goto done;
- }
-
- /* not the first packet - enqueue at the tail */
- prev = chan->tail;
- desc_write(prev, hw_next, desc);
- chan->tail = desc;
-
- /* next check if EOQ has been triggered already */
- if (desc_read(prev, hw_mode) & CPDMA_DESC_EOQ)
- chan_write(chan, hdp, desc);
-
-done:
- if (chan->rxfree)
- chan_write(chan, rxfree, 1);
- return 0;
-}
-
-static int cpdma_process(struct cpsw_priv *priv, struct cpdma_chan *chan,
- void **buffer, int *len)
-{
- struct cpdma_desc *desc = chan->head;
- u32 status;
-
- if (!desc)
- return -ENOENT;
-
- status = desc_read(desc, hw_mode);
-
- if (len)
- *len = status & 0x7ff;
-
- if (buffer)
- *buffer = desc_read_ptr(desc, sw_buffer);
-
- if (status & CPDMA_DESC_OWNER) {
- if (chan_read(chan, hdp) == 0) {
- if (desc_read(desc, hw_mode) & CPDMA_DESC_OWNER)
- chan_write(chan, hdp, desc);
- }
-
- return -EBUSY;
- }
-
- chan->head = desc_read_ptr(desc, hw_next);
- chan_write(chan, cp, desc);
-
- cpdma_desc_free(priv, desc);
- return 0;
-}
-
-static int _cpsw_init(struct cpsw_priv *priv, u8 *enetaddr)
-{
- struct cpsw_slave *slave;
- int i, ret;
-
- /* soft reset the controller and initialize priv */
- setbit_and_wait_for_clear32(&priv->regs->soft_reset);
-
- /* initialize and reset the address lookup engine */
- cpsw_ale_enable(priv, 1);
- cpsw_ale_clear(priv, 1);
- cpsw_ale_vlan_aware(priv, 0); /* vlan unaware mode */
-
- /* setup host port priority mapping */
- __raw_writel(0x76543210, &priv->host_port_regs->cpdma_tx_pri_map);
- __raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map);
-
- /* disable priority elevation and enable statistics on all ports */
- __raw_writel(0, &priv->regs->ptype);
-
- /* enable statistics collection only on the host port */
- __raw_writel(BIT(priv->host_port), &priv->regs->stat_port_en);
- __raw_writel(0x7, &priv->regs->stat_port_en);
-
- cpsw_ale_port_state(priv, priv->host_port, ALE_PORT_STATE_FORWARD);
-
- cpsw_ale_add_ucast(priv, enetaddr, priv->host_port, ALE_SECURE);
- cpsw_ale_add_mcast(priv, net_bcast_ethaddr, 1 << priv->host_port);
-
- for_active_slave(slave, priv)
- cpsw_slave_init(slave, priv);
-
- ret = cpsw_update_link(priv);
- if (ret)
- goto out;
-
- /* init descriptor pool */
- for (i = 0; i < NUM_DESCS; i++) {
- desc_write(&priv->descs[i], hw_next,
- (i == (NUM_DESCS - 1)) ? 0 : &priv->descs[i+1]);
- }
- priv->desc_free = &priv->descs[0];
-
- /* initialize channels */
- if (priv->data.version == CPSW_CTRL_VERSION_2) {
- memset(&priv->rx_chan, 0, sizeof(struct cpdma_chan));
- priv->rx_chan.hdp = priv->dma_regs + CPDMA_RXHDP_VER2;
- priv->rx_chan.cp = priv->dma_regs + CPDMA_RXCP_VER2;
- priv->rx_chan.rxfree = priv->dma_regs + CPDMA_RXFREE;
-
- memset(&priv->tx_chan, 0, sizeof(struct cpdma_chan));
- priv->tx_chan.hdp = priv->dma_regs + CPDMA_TXHDP_VER2;
- priv->tx_chan.cp = priv->dma_regs + CPDMA_TXCP_VER2;
- } else {
- memset(&priv->rx_chan, 0, sizeof(struct cpdma_chan));
- priv->rx_chan.hdp = priv->dma_regs + CPDMA_RXHDP_VER1;
- priv->rx_chan.cp = priv->dma_regs + CPDMA_RXCP_VER1;
- priv->rx_chan.rxfree = priv->dma_regs + CPDMA_RXFREE;
-
- memset(&priv->tx_chan, 0, sizeof(struct cpdma_chan));
- priv->tx_chan.hdp = priv->dma_regs + CPDMA_TXHDP_VER1;
- priv->tx_chan.cp = priv->dma_regs + CPDMA_TXCP_VER1;
- }
-
- /* clear dma state */
- setbit_and_wait_for_clear32(priv->dma_regs + CPDMA_SOFTRESET);
-
- if (priv->data.version == CPSW_CTRL_VERSION_2) {
- for (i = 0; i < priv->data.channels; i++) {
- __raw_writel(0, priv->dma_regs + CPDMA_RXHDP_VER2 + 4
- * i);
- __raw_writel(0, priv->dma_regs + CPDMA_RXFREE + 4
- * i);
- __raw_writel(0, priv->dma_regs + CPDMA_RXCP_VER2 + 4
- * i);
- __raw_writel(0, priv->dma_regs + CPDMA_TXHDP_VER2 + 4
- * i);
- __raw_writel(0, priv->dma_regs + CPDMA_TXCP_VER2 + 4
- * i);
- }
- } else {
- for (i = 0; i < priv->data.channels; i++) {
- __raw_writel(0, priv->dma_regs + CPDMA_RXHDP_VER1 + 4
- * i);
- __raw_writel(0, priv->dma_regs + CPDMA_RXFREE + 4
- * i);
- __raw_writel(0, priv->dma_regs + CPDMA_RXCP_VER1 + 4
- * i);
- __raw_writel(0, priv->dma_regs + CPDMA_TXHDP_VER1 + 4
- * i);
- __raw_writel(0, priv->dma_regs + CPDMA_TXCP_VER1 + 4
- * i);
-
- }
- }
-
- __raw_writel(1, priv->dma_regs + CPDMA_TXCONTROL);
- __raw_writel(1, priv->dma_regs + CPDMA_RXCONTROL);
-
- /* submit rx descs */
- for (i = 0; i < PKTBUFSRX; i++) {
- ret = cpdma_submit(priv, &priv->rx_chan, net_rx_packets[i],
- PKTSIZE);
- if (ret < 0) {
- printf("error %d submitting rx desc\n", ret);
- break;
- }
- }
-
-out:
- return ret;
-}
-
-static int cpsw_reap_completed_packets(struct cpsw_priv *priv)
-{
- int timeout = CPDMA_TIMEOUT;
-
- /* reap completed packets */
- while (timeout-- &&
- (cpdma_process(priv, &priv->tx_chan, NULL, NULL) >= 0))
- ;
-
- return timeout;
-}
-
-static void _cpsw_halt(struct cpsw_priv *priv)
-{
- cpsw_reap_completed_packets(priv);
-
- writel(0, priv->dma_regs + CPDMA_TXCONTROL);
- writel(0, priv->dma_regs + CPDMA_RXCONTROL);
-
- /* soft reset the controller and initialize priv */
- setbit_and_wait_for_clear32(&priv->regs->soft_reset);
-
- /* clear dma state */
- setbit_and_wait_for_clear32(priv->dma_regs + CPDMA_SOFTRESET);
-
-}
-
-static int _cpsw_send(struct cpsw_priv *priv, void *packet, int length)
-{
- int timeout;
-
- flush_dcache_range((unsigned long)packet,
- (unsigned long)packet + ALIGN(length, PKTALIGN));
-
- timeout = cpsw_reap_completed_packets(priv);
- if (timeout == -1) {
- printf("cpdma_process timeout\n");
- return -ETIMEDOUT;
- }
-
- return cpdma_submit(priv, &priv->tx_chan, packet, length);
-}
-
-static int _cpsw_recv(struct cpsw_priv *priv, uchar **pkt)
-{
- void *buffer;
- int len;
- int ret;
-
- ret = cpdma_process(priv, &priv->rx_chan, &buffer, &len);
- if (ret < 0)
- return ret;
-
- invalidate_dcache_range((unsigned long)buffer,
- (unsigned long)buffer + PKTSIZE_ALIGN);
- *pkt = buffer;
-
- return len;
-}
-
-static void cpsw_slave_setup(struct cpsw_slave *slave, int slave_num,
- struct cpsw_priv *priv)
-{
- void *regs = priv->regs;
- struct cpsw_slave_data *data = priv->data.slave_data + slave_num;
- slave->slave_num = slave_num;
- slave->data = data;
- slave->regs = regs + data->slave_reg_ofs;
- slave->sliver = regs + data->sliver_reg_ofs;
-}
-
-static int cpsw_phy_init(struct cpsw_priv *priv, struct cpsw_slave *slave)
-{
- struct phy_device *phydev;
- u32 supported = PHY_GBIT_FEATURES;
-
- phydev = phy_connect(priv->bus,
- slave->data->phy_addr,
- priv->dev,
- slave->data->phy_if);
-
- if (!phydev)
- return -1;
-
- phydev->supported &= supported;
- phydev->advertising = phydev->supported;
-
-#ifdef CONFIG_DM_ETH
- if (slave->data->phy_of_handle)
- phydev->node = offset_to_ofnode(slave->data->phy_of_handle);
-#endif
-
- priv->phydev = phydev;
- phy_config(phydev);
-
- return 1;
-}
-
-static void cpsw_phy_addr_update(struct cpsw_priv *priv)
-{
- struct cpsw_platform_data *data = &priv->data;
- u16 alive = mdio_regs->alive & GENMASK(15, 0);
- int active = data->active_slave;
- int new_addr = ffs(alive) - 1;
-
- /*
- * If there is only one phy alive and its address does not match
- * that of active slave, then phy address can safely be updated.
- */
- if (hweight16(alive) == 1 &&
- data->slave_data[active].phy_addr != new_addr) {
- printf("Updated phy address for CPSW#%d, old: %d, new: %d\n",
- active, data->slave_data[active].phy_addr, new_addr);
- data->slave_data[active].phy_addr = new_addr;
- }
-}
-
-int _cpsw_register(struct cpsw_priv *priv)
-{
- struct cpsw_slave *slave;
- struct cpsw_platform_data *data = &priv->data;
- void *regs = (void *)data->cpsw_base;
-
- priv->slaves = malloc(sizeof(struct cpsw_slave) * data->slaves);
- if (!priv->slaves) {
- return -ENOMEM;
- }
-
- priv->host_port = data->host_port_num;
- priv->regs = regs;
- priv->host_port_regs = regs + data->host_port_reg_ofs;
- priv->dma_regs = regs + data->cpdma_reg_ofs;
- priv->ale_regs = regs + data->ale_reg_ofs;
- priv->descs = (void *)regs + data->bd_ram_ofs;
-
- int idx = 0;
-
- for_each_slave(slave, priv) {
- cpsw_slave_setup(slave, idx, priv);
- idx = idx + 1;
- }
-
- cpsw_mdio_init(priv->dev->name, data->mdio_base, data->mdio_div);
-
- cpsw_phy_addr_update(priv);
-
- priv->bus = miiphy_get_dev_by_name(priv->dev->name);
- for_active_slave(slave, priv)
- cpsw_phy_init(priv, slave);
-
- return 0;
-}
-
-#ifndef CONFIG_DM_ETH
-static int cpsw_init(struct eth_device *dev, bd_t *bis)
-{
- struct cpsw_priv *priv = dev->priv;
-
- return _cpsw_init(priv, dev->enetaddr);
-}
-
-static void cpsw_halt(struct eth_device *dev)
-{
- struct cpsw_priv *priv = dev->priv;
-
- return _cpsw_halt(priv);
-}
-
-static int cpsw_send(struct eth_device *dev, void *packet, int length)
-{
- struct cpsw_priv *priv = dev->priv;
-
- return _cpsw_send(priv, packet, length);
-}
-
-static int cpsw_recv(struct eth_device *dev)
-{
- struct cpsw_priv *priv = dev->priv;
- uchar *pkt = NULL;
- int len;
-
- len = _cpsw_recv(priv, &pkt);
-
- if (len > 0) {
- net_process_received_packet(pkt, len);
- cpdma_submit(priv, &priv->rx_chan, pkt, PKTSIZE);
- }
-
- return len;
-}
-
-int cpsw_register(struct cpsw_platform_data *data)
-{
- struct cpsw_priv *priv;
- struct eth_device *dev;
- int ret;
-
- dev = calloc(sizeof(*dev), 1);
- if (!dev)
- return -ENOMEM;
-
- priv = calloc(sizeof(*priv), 1);
- if (!priv) {
- free(dev);
- return -ENOMEM;
- }
-
- priv->dev = dev;
- priv->data = *data;
-
- strcpy(dev->name, "cpsw");
- dev->iobase = 0;
- dev->init = cpsw_init;
- dev->halt = cpsw_halt;
- dev->send = cpsw_send;
- dev->recv = cpsw_recv;
- dev->priv = priv;
-
- eth_register(dev);
-
- ret = _cpsw_register(priv);
- if (ret < 0) {
- eth_unregister(dev);
- free(dev);
- free(priv);
- return ret;
- }
-
- return 1;
-}
-#else
-static int cpsw_eth_start(struct udevice *dev)
-{
- struct eth_pdata *pdata = dev_get_platdata(dev);
- struct cpsw_priv *priv = dev_get_priv(dev);
-
- return _cpsw_init(priv, pdata->enetaddr);
-}
-
-static int cpsw_eth_send(struct udevice *dev, void *packet, int length)
-{
- struct cpsw_priv *priv = dev_get_priv(dev);
-
- return _cpsw_send(priv, packet, length);
-}
-
-static int cpsw_eth_recv(struct udevice *dev, int flags, uchar **packetp)
-{
- struct cpsw_priv *priv = dev_get_priv(dev);
-
- return _cpsw_recv(priv, packetp);
-}
-
-static int cpsw_eth_free_pkt(struct udevice *dev, uchar *packet,
- int length)
-{
- struct cpsw_priv *priv = dev_get_priv(dev);
-
- return cpdma_submit(priv, &priv->rx_chan, packet, PKTSIZE);
-}
-
-static void cpsw_eth_stop(struct udevice *dev)
-{
- struct cpsw_priv *priv = dev_get_priv(dev);
-
- return _cpsw_halt(priv);
-}
-
-
-static int cpsw_eth_probe(struct udevice *dev)
-{
- struct cpsw_priv *priv = dev_get_priv(dev);
-
- priv->dev = dev;
-
- return _cpsw_register(priv);
-}
-
-static const struct eth_ops cpsw_eth_ops = {
- .start = cpsw_eth_start,
- .send = cpsw_eth_send,
- .recv = cpsw_eth_recv,
- .free_pkt = cpsw_eth_free_pkt,
- .stop = cpsw_eth_stop,
-};
-
-static inline fdt_addr_t cpsw_get_addr_by_node(const void *fdt, int node)
-{
- return fdtdec_get_addr_size_auto_noparent(fdt, node, "reg", 0, NULL,
- false);
-}
-
-static void cpsw_gmii_sel_am3352(struct cpsw_priv *priv,
- phy_interface_t phy_mode)
-{
- u32 reg;
- u32 mask;
- u32 mode = 0;
- bool rgmii_id = false;
- int slave = priv->data.active_slave;
-
- reg = readl(priv->data.gmii_sel);
-
- switch (phy_mode) {
- case PHY_INTERFACE_MODE_RMII:
- mode = AM33XX_GMII_SEL_MODE_RMII;
- break;
-
- case PHY_INTERFACE_MODE_RGMII:
- mode = AM33XX_GMII_SEL_MODE_RGMII;
- break;
- case PHY_INTERFACE_MODE_RGMII_ID:
- case PHY_INTERFACE_MODE_RGMII_RXID:
- case PHY_INTERFACE_MODE_RGMII_TXID:
- mode = AM33XX_GMII_SEL_MODE_RGMII;
- rgmii_id = true;
- break;
-
- case PHY_INTERFACE_MODE_MII:
- default:
- mode = AM33XX_GMII_SEL_MODE_MII;
- break;
- };
-
- mask = GMII_SEL_MODE_MASK << (slave * 2) | BIT(slave + 6);
- mode <<= slave * 2;
-
- if (priv->data.rmii_clock_external) {
- if (slave == 0)
- mode |= AM33XX_GMII_SEL_RMII1_IO_CLK_EN;
- else
- mode |= AM33XX_GMII_SEL_RMII2_IO_CLK_EN;
- }
-
- if (rgmii_id) {
- if (slave == 0)
- mode |= AM33XX_GMII_SEL_RGMII1_IDMODE;
- else
- mode |= AM33XX_GMII_SEL_RGMII2_IDMODE;
- }
-
- reg &= ~mask;
- reg |= mode;
-
- writel(reg, priv->data.gmii_sel);
-}
-
-static void cpsw_gmii_sel_dra7xx(struct cpsw_priv *priv,
- phy_interface_t phy_mode)
-{
- u32 reg;
- u32 mask;
- u32 mode = 0;
- int slave = priv->data.active_slave;
-
- reg = readl(priv->data.gmii_sel);
-
- switch (phy_mode) {
- case PHY_INTERFACE_MODE_RMII:
- mode = AM33XX_GMII_SEL_MODE_RMII;
- break;
-
- case PHY_INTERFACE_MODE_RGMII:
- case PHY_INTERFACE_MODE_RGMII_ID:
- case PHY_INTERFACE_MODE_RGMII_RXID:
- case PHY_INTERFACE_MODE_RGMII_TXID:
- mode = AM33XX_GMII_SEL_MODE_RGMII;
- break;
-
- case PHY_INTERFACE_MODE_MII:
- default:
- mode = AM33XX_GMII_SEL_MODE_MII;
- break;
- };
-
- switch (slave) {
- case 0:
- mask = GMII_SEL_MODE_MASK;
- break;
- case 1:
- mask = GMII_SEL_MODE_MASK << 4;
- mode <<= 4;
- break;
- default:
- dev_err(priv->dev, "invalid slave number...\n");
- return;
- }
-
- if (priv->data.rmii_clock_external)
- dev_err(priv->dev, "RMII External clock is not supported\n");
-
- reg &= ~mask;
- reg |= mode;
-
- writel(reg, priv->data.gmii_sel);
-}
-
-static void cpsw_phy_sel(struct cpsw_priv *priv, const char *compat,
- phy_interface_t phy_mode)
-{
- if (!strcmp(compat, "ti,am3352-cpsw-phy-sel"))
- cpsw_gmii_sel_am3352(priv, phy_mode);
- if (!strcmp(compat, "ti,am43xx-cpsw-phy-sel"))
- cpsw_gmii_sel_am3352(priv, phy_mode);
- else if (!strcmp(compat, "ti,dra7xx-cpsw-phy-sel"))
- cpsw_gmii_sel_dra7xx(priv, phy_mode);
-}
-
-static int cpsw_eth_ofdata_to_platdata(struct udevice *dev)
-{
- struct eth_pdata *pdata = dev_get_platdata(dev);
- struct cpsw_priv *priv = dev_get_priv(dev);
- struct gpio_desc *mode_gpios;
- const char *phy_mode;
- const char *phy_sel_compat = NULL;
- const void *fdt = gd->fdt_blob;
- int node = dev_of_offset(dev);
- int subnode;
- int slave_index = 0;
- int active_slave;
- int num_mode_gpios;
- int ret;
-
- pdata->iobase = devfdt_get_addr(dev);
- priv->data.version = CPSW_CTRL_VERSION_2;
- priv->data.bd_ram_ofs = CPSW_BD_OFFSET;
- priv->data.ale_reg_ofs = CPSW_ALE_OFFSET;
- priv->data.cpdma_reg_ofs = CPSW_CPDMA_OFFSET;
- priv->data.mdio_div = CPSW_MDIO_DIV;
- priv->data.host_port_reg_ofs = CPSW_HOST_PORT_OFFSET,
-
- pdata->phy_interface = -1;
-
- priv->data.cpsw_base = pdata->iobase;
- priv->data.channels = fdtdec_get_int(fdt, node, "cpdma_channels", -1);
- if (priv->data.channels <= 0) {
- printf("error: cpdma_channels not found in dt\n");
- return -ENOENT;
- }
-
- priv->data.slaves = fdtdec_get_int(fdt, node, "slaves", -1);
- if (priv->data.slaves <= 0) {
- printf("error: slaves not found in dt\n");
- return -ENOENT;
- }
- priv->data.slave_data = malloc(sizeof(struct cpsw_slave_data) *
- priv->data.slaves);
-
- priv->data.ale_entries = fdtdec_get_int(fdt, node, "ale_entries", -1);
- if (priv->data.ale_entries <= 0) {
- printf("error: ale_entries not found in dt\n");
- return -ENOENT;
- }
-
- priv->data.bd_ram_ofs = fdtdec_get_int(fdt, node, "bd_ram_size", -1);
- if (priv->data.bd_ram_ofs <= 0) {
- printf("error: bd_ram_size not found in dt\n");
- return -ENOENT;
- }
-
- priv->data.mac_control = fdtdec_get_int(fdt, node, "mac_control", -1);
- if (priv->data.mac_control <= 0) {
- printf("error: ale_entries not found in dt\n");
- return -ENOENT;
- }
-
- num_mode_gpios = gpio_get_list_count(dev, "mode-gpios");
- if (num_mode_gpios > 0) {
- mode_gpios = malloc(sizeof(struct gpio_desc) *
- num_mode_gpios);
- gpio_request_list_by_name(dev, "mode-gpios", mode_gpios,
- num_mode_gpios, GPIOD_IS_OUT);
- free(mode_gpios);
- }
-
- active_slave = fdtdec_get_int(fdt, node, "active_slave", 0);
- priv->data.active_slave = active_slave;
-
- fdt_for_each_subnode(subnode, fdt, node) {
- int len;
- const char *name;
-
- name = fdt_get_name(fdt, subnode, &len);
- if (!strncmp(name, "mdio", 4)) {
- u32 mdio_base;
-
- mdio_base = cpsw_get_addr_by_node(fdt, subnode);
- if (mdio_base == FDT_ADDR_T_NONE) {
- pr_err("Not able to get MDIO address space\n");
- return -ENOENT;
- }
- priv->data.mdio_base = mdio_base;
- }
-
- if (!strncmp(name, "slave", 5)) {
- u32 phy_id[2];
-
- if (slave_index >= priv->data.slaves)
- continue;
- phy_mode = fdt_getprop(fdt, subnode, "phy-mode", NULL);
- if (phy_mode)
- priv->data.slave_data[slave_index].phy_if =
- phy_get_interface_by_name(phy_mode);
-
- priv->data.slave_data[slave_index].phy_of_handle =
- fdtdec_lookup_phandle(fdt, subnode,
- "phy-handle");
-
- if (priv->data.slave_data[slave_index].phy_of_handle >= 0) {
- priv->data.slave_data[slave_index].phy_addr =
- fdtdec_get_int(gd->fdt_blob,
- priv->data.slave_data[slave_index].phy_of_handle,
- "reg", -1);
- } else {
- fdtdec_get_int_array(fdt, subnode, "phy_id",
- phy_id, 2);
- priv->data.slave_data[slave_index].phy_addr =
- phy_id[1];
- }
- slave_index++;
- }
-
- if (!strncmp(name, "cpsw-phy-sel", 12)) {
- priv->data.gmii_sel = cpsw_get_addr_by_node(fdt,
- subnode);
-
- if (priv->data.gmii_sel == FDT_ADDR_T_NONE) {
- pr_err("Not able to get gmii_sel reg address\n");
- return -ENOENT;
- }
-
- if (fdt_get_property(fdt, subnode, "rmii-clock-ext",
- NULL))
- priv->data.rmii_clock_external = true;
-
- phy_sel_compat = fdt_getprop(fdt, subnode, "compatible",
- NULL);
- if (!phy_sel_compat) {
- pr_err("Not able to get gmii_sel compatible\n");
- return -ENOENT;
- }
- }
- }
-
- priv->data.slave_data[0].slave_reg_ofs = CPSW_SLAVE0_OFFSET;
- priv->data.slave_data[0].sliver_reg_ofs = CPSW_SLIVER0_OFFSET;
-
- if (priv->data.slaves == 2) {
- priv->data.slave_data[1].slave_reg_ofs = CPSW_SLAVE1_OFFSET;
- priv->data.slave_data[1].sliver_reg_ofs = CPSW_SLIVER1_OFFSET;
- }
-
- ret = ti_cm_get_macid(dev, active_slave, pdata->enetaddr);
- if (ret < 0) {
- pr_err("cpsw read efuse mac failed\n");
- return ret;
- }
-
- pdata->phy_interface = priv->data.slave_data[active_slave].phy_if;
- if (pdata->phy_interface == -1) {
- debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
- return -EINVAL;
- }
-
- /* Select phy interface in control module */
- cpsw_phy_sel(priv, phy_sel_compat, pdata->phy_interface);
-
- return 0;
-}
-
-int cpsw_get_slave_phy_addr(struct udevice *dev, int slave)
-{
- struct cpsw_priv *priv = dev_get_priv(dev);
- struct cpsw_platform_data *data = &priv->data;
-
- return data->slave_data[slave].phy_addr;
-}
-
-static const struct udevice_id cpsw_eth_ids[] = {
- { .compatible = "ti,cpsw" },
- { .compatible = "ti,am335x-cpsw" },
- { }
-};
-
-U_BOOT_DRIVER(eth_cpsw) = {
- .name = "eth_cpsw",
- .id = UCLASS_ETH,
- .of_match = cpsw_eth_ids,
- .ofdata_to_platdata = cpsw_eth_ofdata_to_platdata,
- .probe = cpsw_eth_probe,
- .ops = &cpsw_eth_ops,
- .priv_auto_alloc_size = sizeof(struct cpsw_priv),
- .platdata_auto_alloc_size = sizeof(struct eth_pdata),
- .flags = DM_FLAG_ALLOC_PRIV_DMA,
-};
-#endif /* CONFIG_DM_ETH */
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Ethernet driver for TI TMS320DM644x (DaVinci) chips.
- *
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * Parts shamelessly stolen from TI's dm644x_emac.c. Original copyright
- * follows:
- *
- * ----------------------------------------------------------------------------
- *
- * dm644x_emac.c
- *
- * TI DaVinci (DM644X) EMAC peripheral driver source for DV-EVM
- *
- * Copyright (C) 2005 Texas Instruments.
- *
- * ----------------------------------------------------------------------------
- *
- * Modifications:
- * ver. 1.0: Sep 2005, Anant Gole - Created EMAC version for uBoot.
- * ver 1.1: Nov 2005, Anant Gole - Extended the RX logic for multiple descriptors
- */
-#include <common.h>
-#include <command.h>
-#include <net.h>
-#include <miiphy.h>
-#include <malloc.h>
-#include <netdev.h>
-#include <linux/compiler.h>
-#include <asm/arch/emac_defs.h>
-#include <asm/io.h>
-#include "davinci_emac.h"
-
-unsigned int emac_dbg = 0;
-#define debug_emac(fmt,args...) if (emac_dbg) printf(fmt,##args)
-
-#ifdef EMAC_HW_RAM_ADDR
-static inline unsigned long BD_TO_HW(unsigned long x)
-{
- if (x == 0)
- return 0;
-
- return x - EMAC_WRAPPER_RAM_ADDR + EMAC_HW_RAM_ADDR;
-}
-
-static inline unsigned long HW_TO_BD(unsigned long x)
-{
- if (x == 0)
- return 0;
-
- return x - EMAC_HW_RAM_ADDR + EMAC_WRAPPER_RAM_ADDR;
-}
-#else
-#define BD_TO_HW(x) (x)
-#define HW_TO_BD(x) (x)
-#endif
-
-#ifdef DAVINCI_EMAC_GIG_ENABLE
-#define emac_gigabit_enable(phy_addr) davinci_eth_gigabit_enable(phy_addr)
-#else
-#define emac_gigabit_enable(phy_addr) /* no gigabit to enable */
-#endif
-
-#if !defined(CONFIG_SYS_EMAC_TI_CLKDIV)
-#define CONFIG_SYS_EMAC_TI_CLKDIV ((EMAC_MDIO_BUS_FREQ / \
- EMAC_MDIO_CLOCK_FREQ) - 1)
-#endif
-
-static void davinci_eth_mdio_enable(void);
-
-static int gen_init_phy(int phy_addr);
-static int gen_is_phy_connected(int phy_addr);
-static int gen_get_link_speed(int phy_addr);
-static int gen_auto_negotiate(int phy_addr);
-
-void eth_mdio_enable(void)
-{
- davinci_eth_mdio_enable();
-}
-
-/* EMAC Addresses */
-static volatile emac_regs *adap_emac = (emac_regs *)EMAC_BASE_ADDR;
-static volatile ewrap_regs *adap_ewrap = (ewrap_regs *)EMAC_WRAPPER_BASE_ADDR;
-static volatile mdio_regs *adap_mdio = (mdio_regs *)EMAC_MDIO_BASE_ADDR;
-
-/* EMAC descriptors */
-static volatile emac_desc *emac_rx_desc = (emac_desc *)(EMAC_WRAPPER_RAM_ADDR + EMAC_RX_DESC_BASE);
-static volatile emac_desc *emac_tx_desc = (emac_desc *)(EMAC_WRAPPER_RAM_ADDR + EMAC_TX_DESC_BASE);
-static volatile emac_desc *emac_rx_active_head = 0;
-static volatile emac_desc *emac_rx_active_tail = 0;
-static int emac_rx_queue_active = 0;
-
-/* Receive packet buffers */
-static unsigned char emac_rx_buffers[EMAC_MAX_RX_BUFFERS * EMAC_RXBUF_SIZE]
- __aligned(ARCH_DMA_MINALIGN);
-
-#ifndef CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT
-#define CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT 3
-#endif
-
-/* PHY address for a discovered PHY (0xff - not found) */
-static u_int8_t active_phy_addr[CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT];
-
-/* number of PHY found active */
-static u_int8_t num_phy;
-
-phy_t phy[CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT];
-
-static int davinci_eth_set_mac_addr(struct eth_device *dev)
-{
- unsigned long mac_hi;
- unsigned long mac_lo;
-
- /*
- * Set MAC Addresses & Init multicast Hash to 0 (disable any multicast
- * receive)
- * Using channel 0 only - other channels are disabled
- * */
- writel(0, &adap_emac->MACINDEX);
- mac_hi = (dev->enetaddr[3] << 24) |
- (dev->enetaddr[2] << 16) |
- (dev->enetaddr[1] << 8) |
- (dev->enetaddr[0]);
- mac_lo = (dev->enetaddr[5] << 8) |
- (dev->enetaddr[4]);
-
- writel(mac_hi, &adap_emac->MACADDRHI);
-#if defined(DAVINCI_EMAC_VERSION2)
- writel(mac_lo | EMAC_MAC_ADDR_IS_VALID | EMAC_MAC_ADDR_MATCH,
- &adap_emac->MACADDRLO);
-#else
- writel(mac_lo, &adap_emac->MACADDRLO);
-#endif
-
- writel(0, &adap_emac->MACHASH1);
- writel(0, &adap_emac->MACHASH2);
-
- /* Set source MAC address - REQUIRED */
- writel(mac_hi, &adap_emac->MACSRCADDRHI);
- writel(mac_lo, &adap_emac->MACSRCADDRLO);
-
-
- return 0;
-}
-
-static void davinci_eth_mdio_enable(void)
-{
- u_int32_t clkdiv;
-
- clkdiv = CONFIG_SYS_EMAC_TI_CLKDIV;
-
- writel((clkdiv & 0xff) |
- MDIO_CONTROL_ENABLE |
- MDIO_CONTROL_FAULT |
- MDIO_CONTROL_FAULT_ENABLE,
- &adap_mdio->CONTROL);
-
- while (readl(&adap_mdio->CONTROL) & MDIO_CONTROL_IDLE)
- ;
-}
-
-/*
- * Tries to find an active connected PHY. Returns 1 if address if found.
- * If no active PHY (or more than one PHY) found returns 0.
- * Sets active_phy_addr variable.
- */
-static int davinci_eth_phy_detect(void)
-{
- u_int32_t phy_act_state;
- int i;
- int j;
- unsigned int count = 0;
-
- for (i = 0; i < CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT; i++)
- active_phy_addr[i] = 0xff;
-
- udelay(1000);
- phy_act_state = readl(&adap_mdio->ALIVE);
-
- if (phy_act_state == 0)
- return 0; /* No active PHYs */
-
- debug_emac("davinci_eth_phy_detect(), ALIVE = 0x%08x\n", phy_act_state);
-
- for (i = 0, j = 0; i < 32; i++)
- if (phy_act_state & (1 << i)) {
- count++;
- if (count <= CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT) {
- active_phy_addr[j++] = i;
- } else {
- printf("%s: to many PHYs detected.\n",
- __func__);
- count = 0;
- break;
- }
- }
-
- num_phy = count;
-
- return count;
-}
-
-
-/* Read a PHY register via MDIO inteface. Returns 1 on success, 0 otherwise */
-int davinci_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t *data)
-{
- int tmp;
-
- while (readl(&adap_mdio->USERACCESS0) & MDIO_USERACCESS0_GO)
- ;
-
- writel(MDIO_USERACCESS0_GO |
- MDIO_USERACCESS0_WRITE_READ |
- ((reg_num & 0x1f) << 21) |
- ((phy_addr & 0x1f) << 16),
- &adap_mdio->USERACCESS0);
-
- /* Wait for command to complete */
- while ((tmp = readl(&adap_mdio->USERACCESS0)) & MDIO_USERACCESS0_GO)
- ;
-
- if (tmp & MDIO_USERACCESS0_ACK) {
- *data = tmp & 0xffff;
- return 1;
- }
-
- return 0;
-}
-
-/* Write to a PHY register via MDIO inteface. Blocks until operation is complete. */
-int davinci_eth_phy_write(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t data)
-{
-
- while (readl(&adap_mdio->USERACCESS0) & MDIO_USERACCESS0_GO)
- ;
-
- writel(MDIO_USERACCESS0_GO |
- MDIO_USERACCESS0_WRITE_WRITE |
- ((reg_num & 0x1f) << 21) |
- ((phy_addr & 0x1f) << 16) |
- (data & 0xffff),
- &adap_mdio->USERACCESS0);
-
- /* Wait for command to complete */
- while (readl(&adap_mdio->USERACCESS0) & MDIO_USERACCESS0_GO)
- ;
-
- return 1;
-}
-
-/* PHY functions for a generic PHY */
-static int gen_init_phy(int phy_addr)
-{
- int ret = 1;
-
- if (gen_get_link_speed(phy_addr)) {
- /* Try another time */
- ret = gen_get_link_speed(phy_addr);
- }
-
- return(ret);
-}
-
-static int gen_is_phy_connected(int phy_addr)
-{
- u_int16_t dummy;
-
- return davinci_eth_phy_read(phy_addr, MII_PHYSID1, &dummy);
-}
-
-static int get_active_phy(void)
-{
- int i;
-
- for (i = 0; i < num_phy; i++)
- if (phy[i].get_link_speed(active_phy_addr[i]))
- return i;
-
- return -1; /* Return error if no link */
-}
-
-static int gen_get_link_speed(int phy_addr)
-{
- u_int16_t tmp;
-
- if (davinci_eth_phy_read(phy_addr, MII_STATUS_REG, &tmp) &&
- (tmp & 0x04)) {
-#if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \
- defined(CONFIG_MACH_DAVINCI_DA850_EVM)
- davinci_eth_phy_read(phy_addr, MII_LPA, &tmp);
-
- /* Speed doesn't matter, there is no setting for it in EMAC. */
- if (tmp & (LPA_100FULL | LPA_10FULL)) {
- /* set EMAC for Full Duplex */
- writel(EMAC_MACCONTROL_MIIEN_ENABLE |
- EMAC_MACCONTROL_FULLDUPLEX_ENABLE,
- &adap_emac->MACCONTROL);
- } else {
- /*set EMAC for Half Duplex */
- writel(EMAC_MACCONTROL_MIIEN_ENABLE,
- &adap_emac->MACCONTROL);
- }
-
- if (tmp & (LPA_100FULL | LPA_100HALF))
- writel(readl(&adap_emac->MACCONTROL) |
- EMAC_MACCONTROL_RMIISPEED_100,
- &adap_emac->MACCONTROL);
- else
- writel(readl(&adap_emac->MACCONTROL) &
- ~EMAC_MACCONTROL_RMIISPEED_100,
- &adap_emac->MACCONTROL);
-#endif
- return(1);
- }
-
- return(0);
-}
-
-static int gen_auto_negotiate(int phy_addr)
-{
- u_int16_t tmp;
- u_int16_t val;
- unsigned long cntr = 0;
-
- if (!davinci_eth_phy_read(phy_addr, MII_BMCR, &tmp))
- return 0;
-
- val = tmp | BMCR_FULLDPLX | BMCR_ANENABLE |
- BMCR_SPEED100;
- davinci_eth_phy_write(phy_addr, MII_BMCR, val);
-
- if (!davinci_eth_phy_read(phy_addr, MII_ADVERTISE, &val))
- return 0;
-
- val |= (ADVERTISE_100FULL | ADVERTISE_100HALF | ADVERTISE_10FULL |
- ADVERTISE_10HALF);
- davinci_eth_phy_write(phy_addr, MII_ADVERTISE, val);
-
- if (!davinci_eth_phy_read(phy_addr, MII_BMCR, &tmp))
- return(0);
-
-#ifdef DAVINCI_EMAC_GIG_ENABLE
- davinci_eth_phy_read(phy_addr, MII_CTRL1000, &val);
- val |= PHY_1000BTCR_1000FD;
- val &= ~PHY_1000BTCR_1000HD;
- davinci_eth_phy_write(phy_addr, MII_CTRL1000, val);
- davinci_eth_phy_read(phy_addr, MII_CTRL1000, &val);
-#endif
-
- /* Restart Auto_negotiation */
- tmp |= BMCR_ANRESTART;
- davinci_eth_phy_write(phy_addr, MII_BMCR, tmp);
-
- /*check AutoNegotiate complete */
- do {
- udelay(40000);
- if (!davinci_eth_phy_read(phy_addr, MII_BMSR, &tmp))
- return 0;
-
- if (tmp & BMSR_ANEGCOMPLETE)
- break;
-
- cntr++;
- } while (cntr < 200);
-
- if (!davinci_eth_phy_read(phy_addr, MII_BMSR, &tmp))
- return(0);
-
- if (!(tmp & BMSR_ANEGCOMPLETE))
- return(0);
-
- return(gen_get_link_speed(phy_addr));
-}
-/* End of generic PHY functions */
-
-
-#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
-static int davinci_mii_phy_read(struct mii_dev *bus, int addr, int devad,
- int reg)
-{
- unsigned short value = 0;
- int retval = davinci_eth_phy_read(addr, reg, &value);
-
- return retval ? value : -EIO;
-}
-
-static int davinci_mii_phy_write(struct mii_dev *bus, int addr, int devad,
- int reg, u16 value)
-{
- return davinci_eth_phy_write(addr, reg, value) ? 0 : 1;
-}
-#endif
-
-static void __attribute__((unused)) davinci_eth_gigabit_enable(int phy_addr)
-{
- u_int16_t data;
-
- if (davinci_eth_phy_read(phy_addr, 0, &data)) {
- if (data & (1 << 6)) { /* speed selection MSB */
- /*
- * Check if link detected is giga-bit
- * If Gigabit mode detected, enable gigbit in MAC
- */
- writel(readl(&adap_emac->MACCONTROL) |
- EMAC_MACCONTROL_GIGFORCE |
- EMAC_MACCONTROL_GIGABIT_ENABLE,
- &adap_emac->MACCONTROL);
- }
- }
-}
-
-/* Eth device open */
-static int davinci_eth_open(struct eth_device *dev, bd_t *bis)
-{
- dv_reg_p addr;
- u_int32_t clkdiv, cnt, mac_control;
- uint16_t __maybe_unused lpa_val;
- volatile emac_desc *rx_desc;
- int index;
-
- debug_emac("+ emac_open\n");
-
- /* Reset EMAC module and disable interrupts in wrapper */
- writel(1, &adap_emac->SOFTRESET);
- while (readl(&adap_emac->SOFTRESET) != 0)
- ;
-#if defined(DAVINCI_EMAC_VERSION2)
- writel(1, &adap_ewrap->softrst);
- while (readl(&adap_ewrap->softrst) != 0)
- ;
-#else
- writel(0, &adap_ewrap->EWCTL);
- for (cnt = 0; cnt < 5; cnt++) {
- clkdiv = readl(&adap_ewrap->EWCTL);
- }
-#endif
-
-#if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \
- defined(CONFIG_MACH_DAVINCI_DA850_EVM)
- adap_ewrap->c0rxen = adap_ewrap->c1rxen = adap_ewrap->c2rxen = 0;
- adap_ewrap->c0txen = adap_ewrap->c1txen = adap_ewrap->c2txen = 0;
- adap_ewrap->c0miscen = adap_ewrap->c1miscen = adap_ewrap->c2miscen = 0;
-#endif
- rx_desc = emac_rx_desc;
-
- writel(1, &adap_emac->TXCONTROL);
- writel(1, &adap_emac->RXCONTROL);
-
- davinci_eth_set_mac_addr(dev);
-
- /* Set DMA 8 TX / 8 RX Head pointers to 0 */
- addr = &adap_emac->TX0HDP;
- for (cnt = 0; cnt < 8; cnt++)
- writel(0, addr++);
-
- addr = &adap_emac->RX0HDP;
- for (cnt = 0; cnt < 8; cnt++)
- writel(0, addr++);
-
- /* Clear Statistics (do this before setting MacControl register) */
- addr = &adap_emac->RXGOODFRAMES;
- for(cnt = 0; cnt < EMAC_NUM_STATS; cnt++)
- writel(0, addr++);
-
- /* No multicast addressing */
- writel(0, &adap_emac->MACHASH1);
- writel(0, &adap_emac->MACHASH2);
-
- /* Create RX queue and set receive process in place */
- emac_rx_active_head = emac_rx_desc;
- for (cnt = 0; cnt < EMAC_MAX_RX_BUFFERS; cnt++) {
- rx_desc->next = BD_TO_HW((u_int32_t)(rx_desc + 1));
- rx_desc->buffer = &emac_rx_buffers[cnt * EMAC_RXBUF_SIZE];
- rx_desc->buff_off_len = EMAC_MAX_ETHERNET_PKT_SIZE;
- rx_desc->pkt_flag_len = EMAC_CPPI_OWNERSHIP_BIT;
- rx_desc++;
- }
-
- /* Finalize the rx desc list */
- rx_desc--;
- rx_desc->next = 0;
- emac_rx_active_tail = rx_desc;
- emac_rx_queue_active = 1;
-
- /* Enable TX/RX */
- writel(EMAC_MAX_ETHERNET_PKT_SIZE, &adap_emac->RXMAXLEN);
- writel(0, &adap_emac->RXBUFFEROFFSET);
-
- /*
- * No fancy configs - Use this for promiscous debug
- * - EMAC_RXMBPENABLE_RXCAFEN_ENABLE
- */
- writel(EMAC_RXMBPENABLE_RXBROADEN, &adap_emac->RXMBPENABLE);
-
- /* Enable ch 0 only */
- writel(1, &adap_emac->RXUNICASTSET);
-
- /* Init MDIO & get link state */
- clkdiv = CONFIG_SYS_EMAC_TI_CLKDIV;
- writel((clkdiv & 0xff) | MDIO_CONTROL_ENABLE | MDIO_CONTROL_FAULT,
- &adap_mdio->CONTROL);
-
- /* We need to wait for MDIO to start */
- udelay(1000);
-
- index = get_active_phy();
- if (index == -1)
- return(0);
-
- /* Enable MII interface */
- mac_control = EMAC_MACCONTROL_MIIEN_ENABLE;
-#ifdef DAVINCI_EMAC_GIG_ENABLE
- davinci_eth_phy_read(active_phy_addr[index], MII_STAT1000, &lpa_val);
- if (lpa_val & PHY_1000BTSR_1000FD) {
- debug_emac("eth_open : gigabit negotiated\n");
- mac_control |= EMAC_MACCONTROL_FULLDUPLEX_ENABLE;
- mac_control |= EMAC_MACCONTROL_GIGABIT_ENABLE;
- }
-#endif
-
- davinci_eth_phy_read(active_phy_addr[index], MII_LPA, &lpa_val);
- if (lpa_val & (LPA_100FULL | LPA_10FULL))
- /* set EMAC for Full Duplex */
- mac_control |= EMAC_MACCONTROL_FULLDUPLEX_ENABLE;
-#if defined(CONFIG_SOC_DA8XX) || \
- (defined(CONFIG_OMAP34XX) && defined(CONFIG_DRIVER_TI_EMAC_USE_RMII))
- mac_control |= EMAC_MACCONTROL_RMIISPEED_100;
-#endif
- writel(mac_control, &adap_emac->MACCONTROL);
- /* Start receive process */
- writel(BD_TO_HW((u_int32_t)emac_rx_desc), &adap_emac->RX0HDP);
-
- debug_emac("- emac_open\n");
-
- return(1);
-}
-
-/* EMAC Channel Teardown */
-static void davinci_eth_ch_teardown(int ch)
-{
- dv_reg dly = 0xff;
- dv_reg cnt;
-
- debug_emac("+ emac_ch_teardown\n");
-
- if (ch == EMAC_CH_TX) {
- /* Init TX channel teardown */
- writel(0, &adap_emac->TXTEARDOWN);
- do {
- /*
- * Wait here for Tx teardown completion interrupt to
- * occur. Note: A task delay can be called here to pend
- * rather than occupying CPU cycles - anyway it has
- * been found that teardown takes very few cpu cycles
- * and does not affect functionality
- */
- dly--;
- udelay(1);
- if (dly == 0)
- break;
- cnt = readl(&adap_emac->TX0CP);
- } while (cnt != 0xfffffffc);
- writel(cnt, &adap_emac->TX0CP);
- writel(0, &adap_emac->TX0HDP);
- } else {
- /* Init RX channel teardown */
- writel(0, &adap_emac->RXTEARDOWN);
- do {
- /*
- * Wait here for Rx teardown completion interrupt to
- * occur. Note: A task delay can be called here to pend
- * rather than occupying CPU cycles - anyway it has
- * been found that teardown takes very few cpu cycles
- * and does not affect functionality
- */
- dly--;
- udelay(1);
- if (dly == 0)
- break;
- cnt = readl(&adap_emac->RX0CP);
- } while (cnt != 0xfffffffc);
- writel(cnt, &adap_emac->RX0CP);
- writel(0, &adap_emac->RX0HDP);
- }
-
- debug_emac("- emac_ch_teardown\n");
-}
-
-/* Eth device close */
-static void davinci_eth_close(struct eth_device *dev)
-{
- debug_emac("+ emac_close\n");
-
- davinci_eth_ch_teardown(EMAC_CH_TX); /* TX Channel teardown */
- if (readl(&adap_emac->RXCONTROL) & 1)
- davinci_eth_ch_teardown(EMAC_CH_RX); /* RX Channel teardown */
-
- /* Reset EMAC module and disable interrupts in wrapper */
- writel(1, &adap_emac->SOFTRESET);
-#if defined(DAVINCI_EMAC_VERSION2)
- writel(1, &adap_ewrap->softrst);
-#else
- writel(0, &adap_ewrap->EWCTL);
-#endif
-
-#if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \
- defined(CONFIG_MACH_DAVINCI_DA850_EVM)
- adap_ewrap->c0rxen = adap_ewrap->c1rxen = adap_ewrap->c2rxen = 0;
- adap_ewrap->c0txen = adap_ewrap->c1txen = adap_ewrap->c2txen = 0;
- adap_ewrap->c0miscen = adap_ewrap->c1miscen = adap_ewrap->c2miscen = 0;
-#endif
- debug_emac("- emac_close\n");
-}
-
-static int tx_send_loop = 0;
-
-/*
- * This function sends a single packet on the network and returns
- * positive number (number of bytes transmitted) or negative for error
- */
-static int davinci_eth_send_packet (struct eth_device *dev,
- void *packet, int length)
-{
- int ret_status = -1;
- int index;
- tx_send_loop = 0;
-
- index = get_active_phy();
- if (index == -1) {
- printf(" WARN: emac_send_packet: No link\n");
- return (ret_status);
- }
-
- /* Check packet size and if < EMAC_MIN_ETHERNET_PKT_SIZE, pad it up */
- if (length < EMAC_MIN_ETHERNET_PKT_SIZE) {
- length = EMAC_MIN_ETHERNET_PKT_SIZE;
- }
-
- /* Populate the TX descriptor */
- emac_tx_desc->next = 0;
- emac_tx_desc->buffer = (u_int8_t *) packet;
- emac_tx_desc->buff_off_len = (length & 0xffff);
- emac_tx_desc->pkt_flag_len = ((length & 0xffff) |
- EMAC_CPPI_SOP_BIT |
- EMAC_CPPI_OWNERSHIP_BIT |
- EMAC_CPPI_EOP_BIT);
-
- flush_dcache_range((unsigned long)packet,
- (unsigned long)packet + ALIGN(length, PKTALIGN));
-
- /* Send the packet */
- writel(BD_TO_HW((unsigned long)emac_tx_desc), &adap_emac->TX0HDP);
-
- /* Wait for packet to complete or link down */
- while (1) {
- if (!phy[index].get_link_speed(active_phy_addr[index])) {
- davinci_eth_ch_teardown (EMAC_CH_TX);
- return (ret_status);
- }
-
- if (readl(&adap_emac->TXINTSTATRAW) & 0x01) {
- ret_status = length;
- break;
- }
- tx_send_loop++;
- }
-
- return (ret_status);
-}
-
-/*
- * This function handles receipt of a packet from the network
- */
-static int davinci_eth_rcv_packet (struct eth_device *dev)
-{
- volatile emac_desc *rx_curr_desc;
- volatile emac_desc *curr_desc;
- volatile emac_desc *tail_desc;
- int status, ret = -1;
-
- rx_curr_desc = emac_rx_active_head;
- if (!rx_curr_desc)
- return 0;
- status = rx_curr_desc->pkt_flag_len;
- if ((status & EMAC_CPPI_OWNERSHIP_BIT) == 0) {
- if (status & EMAC_CPPI_RX_ERROR_FRAME) {
- /* Error in packet - discard it and requeue desc */
- printf ("WARN: emac_rcv_pkt: Error in packet\n");
- } else {
- unsigned long tmp = (unsigned long)rx_curr_desc->buffer;
- unsigned short len =
- rx_curr_desc->buff_off_len & 0xffff;
-
- invalidate_dcache_range(tmp, tmp + ALIGN(len, PKTALIGN));
- net_process_received_packet(rx_curr_desc->buffer, len);
- ret = len;
- }
-
- /* Ack received packet descriptor */
- writel(BD_TO_HW((ulong)rx_curr_desc), &adap_emac->RX0CP);
- curr_desc = rx_curr_desc;
- emac_rx_active_head =
- (volatile emac_desc *) (HW_TO_BD(rx_curr_desc->next));
-
- if (status & EMAC_CPPI_EOQ_BIT) {
- if (emac_rx_active_head) {
- writel(BD_TO_HW((ulong)emac_rx_active_head),
- &adap_emac->RX0HDP);
- } else {
- emac_rx_queue_active = 0;
- printf ("INFO:emac_rcv_packet: RX Queue not active\n");
- }
- }
-
- /* Recycle RX descriptor */
- rx_curr_desc->buff_off_len = EMAC_MAX_ETHERNET_PKT_SIZE;
- rx_curr_desc->pkt_flag_len = EMAC_CPPI_OWNERSHIP_BIT;
- rx_curr_desc->next = 0;
-
- if (emac_rx_active_head == 0) {
- printf ("INFO: emac_rcv_pkt: active queue head = 0\n");
- emac_rx_active_head = curr_desc;
- emac_rx_active_tail = curr_desc;
- if (emac_rx_queue_active != 0) {
- writel(BD_TO_HW((ulong)emac_rx_active_head),
- &adap_emac->RX0HDP);
- printf ("INFO: emac_rcv_pkt: active queue head = 0, HDP fired\n");
- emac_rx_queue_active = 1;
- }
- } else {
- tail_desc = emac_rx_active_tail;
- emac_rx_active_tail = curr_desc;
- tail_desc->next = BD_TO_HW((ulong) curr_desc);
- status = tail_desc->pkt_flag_len;
- if (status & EMAC_CPPI_EOQ_BIT) {
- writel(BD_TO_HW((ulong)curr_desc),
- &adap_emac->RX0HDP);
- status &= ~EMAC_CPPI_EOQ_BIT;
- tail_desc->pkt_flag_len = status;
- }
- }
- return (ret);
- }
- return (0);
-}
-
-/*
- * This function initializes the emac hardware. It does NOT initialize
- * EMAC modules power or pin multiplexors, that is done by board_init()
- * much earlier in bootup process. Returns 1 on success, 0 otherwise.
- */
-int davinci_emac_initialize(void)
-{
- u_int32_t phy_id;
- u_int16_t tmp;
- int i;
- int ret;
- struct eth_device *dev;
-
- dev = malloc(sizeof *dev);
-
- if (dev == NULL)
- return -1;
-
- memset(dev, 0, sizeof *dev);
- strcpy(dev->name, "DaVinci-EMAC");
-
- dev->iobase = 0;
- dev->init = davinci_eth_open;
- dev->halt = davinci_eth_close;
- dev->send = davinci_eth_send_packet;
- dev->recv = davinci_eth_rcv_packet;
- dev->write_hwaddr = davinci_eth_set_mac_addr;
-
- eth_register(dev);
-
- davinci_eth_mdio_enable();
-
- /* let the EMAC detect the PHYs */
- udelay(5000);
-
- for (i = 0; i < 256; i++) {
- if (readl(&adap_mdio->ALIVE))
- break;
- udelay(1000);
- }
-
- if (i >= 256) {
- printf("No ETH PHY detected!!!\n");
- return(0);
- }
-
- /* Find if PHY(s) is/are connected */
- ret = davinci_eth_phy_detect();
- if (!ret)
- return(0);
- else
- debug_emac(" %d ETH PHY detected\n", ret);
-
- /* Get PHY ID and initialize phy_ops for a detected PHY */
- for (i = 0; i < num_phy; i++) {
- if (!davinci_eth_phy_read(active_phy_addr[i], MII_PHYSID1,
- &tmp)) {
- active_phy_addr[i] = 0xff;
- continue;
- }
-
- phy_id = (tmp << 16) & 0xffff0000;
-
- if (!davinci_eth_phy_read(active_phy_addr[i], MII_PHYSID2,
- &tmp)) {
- active_phy_addr[i] = 0xff;
- continue;
- }
-
- phy_id |= tmp & 0x0000ffff;
-
- switch (phy_id) {
-#ifdef PHY_KSZ8873
- case PHY_KSZ8873:
- sprintf(phy[i].name, "KSZ8873 @ 0x%02x",
- active_phy_addr[i]);
- phy[i].init = ksz8873_init_phy;
- phy[i].is_phy_connected = ksz8873_is_phy_connected;
- phy[i].get_link_speed = ksz8873_get_link_speed;
- phy[i].auto_negotiate = ksz8873_auto_negotiate;
- break;
-#endif
-#ifdef PHY_LXT972
- case PHY_LXT972:
- sprintf(phy[i].name, "LXT972 @ 0x%02x",
- active_phy_addr[i]);
- phy[i].init = lxt972_init_phy;
- phy[i].is_phy_connected = lxt972_is_phy_connected;
- phy[i].get_link_speed = lxt972_get_link_speed;
- phy[i].auto_negotiate = lxt972_auto_negotiate;
- break;
-#endif
-#ifdef PHY_DP83848
- case PHY_DP83848:
- sprintf(phy[i].name, "DP83848 @ 0x%02x",
- active_phy_addr[i]);
- phy[i].init = dp83848_init_phy;
- phy[i].is_phy_connected = dp83848_is_phy_connected;
- phy[i].get_link_speed = dp83848_get_link_speed;
- phy[i].auto_negotiate = dp83848_auto_negotiate;
- break;
-#endif
-#ifdef PHY_ET1011C
- case PHY_ET1011C:
- sprintf(phy[i].name, "ET1011C @ 0x%02x",
- active_phy_addr[i]);
- phy[i].init = gen_init_phy;
- phy[i].is_phy_connected = gen_is_phy_connected;
- phy[i].get_link_speed = et1011c_get_link_speed;
- phy[i].auto_negotiate = gen_auto_negotiate;
- break;
-#endif
- default:
- sprintf(phy[i].name, "GENERIC @ 0x%02x",
- active_phy_addr[i]);
- phy[i].init = gen_init_phy;
- phy[i].is_phy_connected = gen_is_phy_connected;
- phy[i].get_link_speed = gen_get_link_speed;
- phy[i].auto_negotiate = gen_auto_negotiate;
- }
-
- debug("Ethernet PHY: %s\n", phy[i].name);
-
- int retval;
- struct mii_dev *mdiodev = mdio_alloc();
- if (!mdiodev)
- return -ENOMEM;
- strncpy(mdiodev->name, phy[i].name, MDIO_NAME_LEN);
- mdiodev->read = davinci_mii_phy_read;
- mdiodev->write = davinci_mii_phy_write;
-
- retval = mdio_register(mdiodev);
- if (retval < 0)
- return retval;
-#ifdef DAVINCI_EMAC_GIG_ENABLE
-#define PHY_CONF_REG 22
- /* Enable PHY to clock out TX_CLK */
- davinci_eth_phy_read(active_phy_addr[i], PHY_CONF_REG, &tmp);
- tmp |= PHY_CONF_TXCLKEN;
- davinci_eth_phy_write(active_phy_addr[i], PHY_CONF_REG, tmp);
- davinci_eth_phy_read(active_phy_addr[i], PHY_CONF_REG, &tmp);
-#endif
- }
-
-#if defined(CONFIG_TI816X) || (defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \
- defined(CONFIG_MACH_DAVINCI_DA850_EVM) && \
- !defined(CONFIG_DRIVER_TI_EMAC_RMII_NO_NEGOTIATE))
- for (i = 0; i < num_phy; i++) {
- if (phy[i].is_phy_connected(i))
- phy[i].auto_negotiate(i);
- }
-#endif
- return(1);
-}
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2011 Ilya Yanok, Emcraft Systems
- *
- * Based on: mach-davinci/emac_defs.h
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- */
-
-#ifndef _DAVINCI_EMAC_H_
-#define _DAVINCI_EMAC_H_
-/* Ethernet Min/Max packet size */
-#define EMAC_MIN_ETHERNET_PKT_SIZE 60
-#define EMAC_MAX_ETHERNET_PKT_SIZE 1518
-/* Buffer size (should be aligned on 32 byte and cache line) */
-#define EMAC_RXBUF_SIZE ALIGN(ALIGN(EMAC_MAX_ETHERNET_PKT_SIZE, 32),\
- ARCH_DMA_MINALIGN)
-
-/* Number of RX packet buffers
- * NOTE: Only 1 buffer supported as of now
- */
-#define EMAC_MAX_RX_BUFFERS 10
-
-
-/***********************************************
- ******** Internally used macros ***************
- ***********************************************/
-
-#define EMAC_CH_TX 1
-#define EMAC_CH_RX 0
-
-/* Each descriptor occupies 4 words, lets start RX desc's at 0 and
- * reserve space for 64 descriptors max
- */
-#define EMAC_RX_DESC_BASE 0x0
-#define EMAC_TX_DESC_BASE 0x1000
-
-/* EMAC Teardown value */
-#define EMAC_TEARDOWN_VALUE 0xfffffffc
-
-/* MII Status Register */
-#define MII_STATUS_REG 1
-/* PHY Configuration register */
-#define PHY_CONF_TXCLKEN (1 << 5)
-
-/* Number of statistics registers */
-#define EMAC_NUM_STATS 36
-
-
-/* EMAC Descriptor */
-typedef volatile struct _emac_desc
-{
- u_int32_t next; /* Pointer to next descriptor
- in chain */
- u_int8_t *buffer; /* Pointer to data buffer */
- u_int32_t buff_off_len; /* Buffer Offset(MSW) and Length(LSW) */
- u_int32_t pkt_flag_len; /* Packet Flags(MSW) and Length(LSW) */
-} emac_desc;
-
-/* CPPI bit positions */
-#define EMAC_CPPI_SOP_BIT (0x80000000)
-#define EMAC_CPPI_EOP_BIT (0x40000000)
-#define EMAC_CPPI_OWNERSHIP_BIT (0x20000000)
-#define EMAC_CPPI_EOQ_BIT (0x10000000)
-#define EMAC_CPPI_TEARDOWN_COMPLETE_BIT (0x08000000)
-#define EMAC_CPPI_PASS_CRC_BIT (0x04000000)
-
-#define EMAC_CPPI_RX_ERROR_FRAME (0x03fc0000)
-
-#define EMAC_MACCONTROL_MIIEN_ENABLE (0x20)
-#define EMAC_MACCONTROL_FULLDUPLEX_ENABLE (0x1)
-#define EMAC_MACCONTROL_GIGABIT_ENABLE (1 << 7)
-#define EMAC_MACCONTROL_GIGFORCE (1 << 17)
-#define EMAC_MACCONTROL_RMIISPEED_100 (1 << 15)
-
-#define EMAC_MAC_ADDR_MATCH (1 << 19)
-#define EMAC_MAC_ADDR_IS_VALID (1 << 20)
-
-#define EMAC_RXMBPENABLE_RXCAFEN_ENABLE (0x200000)
-#define EMAC_RXMBPENABLE_RXBROADEN (0x2000)
-
-
-#define MDIO_CONTROL_IDLE (0x80000000)
-#define MDIO_CONTROL_ENABLE (0x40000000)
-#define MDIO_CONTROL_FAULT_ENABLE (0x40000)
-#define MDIO_CONTROL_FAULT (0x80000)
-#define MDIO_USERACCESS0_GO (0x80000000)
-#define MDIO_USERACCESS0_WRITE_READ (0x0)
-#define MDIO_USERACCESS0_WRITE_WRITE (0x40000000)
-#define MDIO_USERACCESS0_ACK (0x20000000)
-
-/* Ethernet MAC Registers Structure */
-typedef struct {
- dv_reg TXIDVER;
- dv_reg TXCONTROL;
- dv_reg TXTEARDOWN;
- u_int8_t RSVD0[4];
- dv_reg RXIDVER;
- dv_reg RXCONTROL;
- dv_reg RXTEARDOWN;
- u_int8_t RSVD1[100];
- dv_reg TXINTSTATRAW;
- dv_reg TXINTSTATMASKED;
- dv_reg TXINTMASKSET;
- dv_reg TXINTMASKCLEAR;
- dv_reg MACINVECTOR;
- u_int8_t RSVD2[12];
- dv_reg RXINTSTATRAW;
- dv_reg RXINTSTATMASKED;
- dv_reg RXINTMASKSET;
- dv_reg RXINTMASKCLEAR;
- dv_reg MACINTSTATRAW;
- dv_reg MACINTSTATMASKED;
- dv_reg MACINTMASKSET;
- dv_reg MACINTMASKCLEAR;
- u_int8_t RSVD3[64];
- dv_reg RXMBPENABLE;
- dv_reg RXUNICASTSET;
- dv_reg RXUNICASTCLEAR;
- dv_reg RXMAXLEN;
- dv_reg RXBUFFEROFFSET;
- dv_reg RXFILTERLOWTHRESH;
- u_int8_t RSVD4[8];
- dv_reg RX0FLOWTHRESH;
- dv_reg RX1FLOWTHRESH;
- dv_reg RX2FLOWTHRESH;
- dv_reg RX3FLOWTHRESH;
- dv_reg RX4FLOWTHRESH;
- dv_reg RX5FLOWTHRESH;
- dv_reg RX6FLOWTHRESH;
- dv_reg RX7FLOWTHRESH;
- dv_reg RX0FREEBUFFER;
- dv_reg RX1FREEBUFFER;
- dv_reg RX2FREEBUFFER;
- dv_reg RX3FREEBUFFER;
- dv_reg RX4FREEBUFFER;
- dv_reg RX5FREEBUFFER;
- dv_reg RX6FREEBUFFER;
- dv_reg RX7FREEBUFFER;
- dv_reg MACCONTROL;
- dv_reg MACSTATUS;
- dv_reg EMCONTROL;
- dv_reg FIFOCONTROL;
- dv_reg MACCONFIG;
- dv_reg SOFTRESET;
- u_int8_t RSVD5[88];
- dv_reg MACSRCADDRLO;
- dv_reg MACSRCADDRHI;
- dv_reg MACHASH1;
- dv_reg MACHASH2;
- dv_reg BOFFTEST;
- dv_reg TPACETEST;
- dv_reg RXPAUSE;
- dv_reg TXPAUSE;
- u_int8_t RSVD6[16];
- dv_reg RXGOODFRAMES;
- dv_reg RXBCASTFRAMES;
- dv_reg RXMCASTFRAMES;
- dv_reg RXPAUSEFRAMES;
- dv_reg RXCRCERRORS;
- dv_reg RXALIGNCODEERRORS;
- dv_reg RXOVERSIZED;
- dv_reg RXJABBER;
- dv_reg RXUNDERSIZED;
- dv_reg RXFRAGMENTS;
- dv_reg RXFILTERED;
- dv_reg RXQOSFILTERED;
- dv_reg RXOCTETS;
- dv_reg TXGOODFRAMES;
- dv_reg TXBCASTFRAMES;
- dv_reg TXMCASTFRAMES;
- dv_reg TXPAUSEFRAMES;
- dv_reg TXDEFERRED;
- dv_reg TXCOLLISION;
- dv_reg TXSINGLECOLL;
- dv_reg TXMULTICOLL;
- dv_reg TXEXCESSIVECOLL;
- dv_reg TXLATECOLL;
- dv_reg TXUNDERRUN;
- dv_reg TXCARRIERSENSE;
- dv_reg TXOCTETS;
- dv_reg FRAME64;
- dv_reg FRAME65T127;
- dv_reg FRAME128T255;
- dv_reg FRAME256T511;
- dv_reg FRAME512T1023;
- dv_reg FRAME1024TUP;
- dv_reg NETOCTETS;
- dv_reg RXSOFOVERRUNS;
- dv_reg RXMOFOVERRUNS;
- dv_reg RXDMAOVERRUNS;
- u_int8_t RSVD7[624];
- dv_reg MACADDRLO;
- dv_reg MACADDRHI;
- dv_reg MACINDEX;
- u_int8_t RSVD8[244];
- dv_reg TX0HDP;
- dv_reg TX1HDP;
- dv_reg TX2HDP;
- dv_reg TX3HDP;
- dv_reg TX4HDP;
- dv_reg TX5HDP;
- dv_reg TX6HDP;
- dv_reg TX7HDP;
- dv_reg RX0HDP;
- dv_reg RX1HDP;
- dv_reg RX2HDP;
- dv_reg RX3HDP;
- dv_reg RX4HDP;
- dv_reg RX5HDP;
- dv_reg RX6HDP;
- dv_reg RX7HDP;
- dv_reg TX0CP;
- dv_reg TX1CP;
- dv_reg TX2CP;
- dv_reg TX3CP;
- dv_reg TX4CP;
- dv_reg TX5CP;
- dv_reg TX6CP;
- dv_reg TX7CP;
- dv_reg RX0CP;
- dv_reg RX1CP;
- dv_reg RX2CP;
- dv_reg RX3CP;
- dv_reg RX4CP;
- dv_reg RX5CP;
- dv_reg RX6CP;
- dv_reg RX7CP;
-} emac_regs;
-
-/* EMAC Wrapper Registers Structure */
-typedef struct {
-#ifdef DAVINCI_EMAC_VERSION2
- dv_reg idver;
- dv_reg softrst;
- dv_reg emctrl;
- dv_reg c0rxthreshen;
- dv_reg c0rxen;
- dv_reg c0txen;
- dv_reg c0miscen;
- dv_reg c1rxthreshen;
- dv_reg c1rxen;
- dv_reg c1txen;
- dv_reg c1miscen;
- dv_reg c2rxthreshen;
- dv_reg c2rxen;
- dv_reg c2txen;
- dv_reg c2miscen;
- dv_reg c0rxthreshstat;
- dv_reg c0rxstat;
- dv_reg c0txstat;
- dv_reg c0miscstat;
- dv_reg c1rxthreshstat;
- dv_reg c1rxstat;
- dv_reg c1txstat;
- dv_reg c1miscstat;
- dv_reg c2rxthreshstat;
- dv_reg c2rxstat;
- dv_reg c2txstat;
- dv_reg c2miscstat;
- dv_reg c0rximax;
- dv_reg c0tximax;
- dv_reg c1rximax;
- dv_reg c1tximax;
- dv_reg c2rximax;
- dv_reg c2tximax;
-#else
- u_int8_t RSVD0[4100];
- dv_reg EWCTL;
- dv_reg EWINTTCNT;
-#endif
-} ewrap_regs;
-
-/* EMAC MDIO Registers Structure */
-typedef struct {
- dv_reg VERSION;
- dv_reg CONTROL;
- dv_reg ALIVE;
- dv_reg LINK;
- dv_reg LINKINTRAW;
- dv_reg LINKINTMASKED;
- u_int8_t RSVD0[8];
- dv_reg USERINTRAW;
- dv_reg USERINTMASKED;
- dv_reg USERINTMASKSET;
- dv_reg USERINTMASKCLEAR;
- u_int8_t RSVD1[80];
- dv_reg USERACCESS0;
- dv_reg USERPHYSEL0;
- dv_reg USERACCESS1;
- dv_reg USERPHYSEL1;
-} mdio_regs;
-
-int davinci_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t *data);
-int davinci_eth_phy_write(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t data);
-
-typedef struct {
- char name[64];
- int (*init)(int phy_addr);
- int (*is_phy_connected)(int phy_addr);
- int (*get_link_speed)(int phy_addr);
- int (*auto_negotiate)(int phy_addr);
-} phy_t;
-
-#endif /* _DAVINCI_EMAC_H_ */
if ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) ==
FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII)
return PHY_INTERFACE_MODE_RGMII;
- else if ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) ==
- FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_MII)
- return PHY_INTERFACE_MODE_MII;
}
switch (port) {
*
* (C) Copyright 2010 Andes Technology
* Macpaul Lin <macpaul@andestech.com>
+ *
+ * Copyright (C) 2018, IBM Corporation.
*/
-#include <config.h>
-#include <common.h>
-#include <malloc.h>
+#include <clk.h>
+#include <dm.h>
+#include <miiphy.h>
#include <net.h>
-#include <asm/io.h>
-#include <asm/dma-mapping.h>
-#include <linux/mii.h>
+#include <wait_bit.h>
+#include <linux/io.h>
+#include <linux/iopoll.h>
#include "ftgmac100.h"
-#define ETH_ZLEN 60
-#define CFG_XBUF_SIZE 1536
+/* Min frame ethernet frame size without FCS */
+#define ETH_ZLEN 60
-/* RBSR - hw default init value is also 0x640 */
-#define RBSR_DEFAULT_VALUE 0x640
+/* Receive Buffer Size Register - HW default is 0x640 */
+#define FTGMAC100_RBSR_DEFAULT 0x640
/* PKTBUFSTX/PKTBUFSRX must both be power of 2 */
#define PKTBUFSTX 4 /* must be power of 2 */
+/* Timeout for transmit */
+#define FTGMAC100_TX_TIMEOUT_MS 1000
+
+/* Timeout for a mdio read/write operation */
+#define FTGMAC100_MDIO_TIMEOUT_USEC 10000
+
+/*
+ * MDC clock cycle threshold
+ *
+ * 20us * 100 = 2ms > (1 / 2.5Mhz) * 0x34
+ */
+#define MDC_CYCTHR 0x34
+
+/*
+ * ftgmac100 model variants
+ */
+enum ftgmac100_model {
+ FTGMAC100_MODEL_FARADAY,
+ FTGMAC100_MODEL_ASPEED,
+};
+
+/**
+ * struct ftgmac100_data - private data for the FTGMAC100 driver
+ *
+ * @iobase: The base address of the hardware registers
+ * @txdes: The array of transmit descriptors
+ * @rxdes: The array of receive descriptors
+ * @tx_index: Transmit descriptor index in @txdes
+ * @rx_index: Receive descriptor index in @rxdes
+ * @phy_addr: The PHY interface address to use
+ * @phydev: The PHY device backing the MAC
+ * @bus: The mdio bus
+ * @phy_mode: The mode of the PHY interface (rgmii, rmii, ...)
+ * @max_speed: Maximum speed of Ethernet connection supported by MAC
+ * @clks: The bulk of clocks assigned to the device in the DT
+ * @rxdes0_edorr_mask: The bit number identifying the end of the RX ring buffer
+ * @txdes0_edotr_mask: The bit number identifying the end of the TX ring buffer
+ */
struct ftgmac100_data {
- ulong txdes_dma;
- struct ftgmac100_txdes *txdes;
- ulong rxdes_dma;
- struct ftgmac100_rxdes *rxdes;
+ struct ftgmac100 *iobase;
+
+ struct ftgmac100_txdes txdes[PKTBUFSTX];
+ struct ftgmac100_rxdes rxdes[PKTBUFSRX];
int tx_index;
int rx_index;
- int phy_addr;
+
+ u32 phy_addr;
+ struct phy_device *phydev;
+ struct mii_dev *bus;
+ u32 phy_mode;
+ u32 max_speed;
+
+ struct clk_bulk clks;
+
+ /* End of RX/TX ring buffer bits. Depend on model */
+ u32 rxdes0_edorr_mask;
+ u32 txdes0_edotr_mask;
};
/*
* struct mii_bus functions
*/
-static int ftgmac100_mdiobus_read(struct eth_device *dev, int phy_addr,
- int regnum)
+static int ftgmac100_mdio_read(struct mii_dev *bus, int phy_addr, int dev_addr,
+ int reg_addr)
{
- struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase;
+ struct ftgmac100_data *priv = bus->priv;
+ struct ftgmac100 *ftgmac100 = priv->iobase;
int phycr;
- int i;
-
- phycr = readl(&ftgmac100->phycr);
-
- /* preserve MDC cycle threshold */
- phycr &= FTGMAC100_PHYCR_MDC_CYCTHR_MASK;
-
- phycr |= FTGMAC100_PHYCR_PHYAD(phy_addr)
- | FTGMAC100_PHYCR_REGAD(regnum)
- | FTGMAC100_PHYCR_MIIRD;
+ int data;
+ int ret;
+ phycr = FTGMAC100_PHYCR_MDC_CYCTHR(MDC_CYCTHR) |
+ FTGMAC100_PHYCR_PHYAD(phy_addr) |
+ FTGMAC100_PHYCR_REGAD(reg_addr) |
+ FTGMAC100_PHYCR_MIIRD;
writel(phycr, &ftgmac100->phycr);
- for (i = 0; i < 10; i++) {
- phycr = readl(&ftgmac100->phycr);
-
- if ((phycr & FTGMAC100_PHYCR_MIIRD) == 0) {
- int data;
-
- data = readl(&ftgmac100->phydata);
- return FTGMAC100_PHYDATA_MIIRDATA(data);
- }
-
- mdelay(10);
+ ret = readl_poll_timeout(&ftgmac100->phycr, phycr,
+ !(phycr & FTGMAC100_PHYCR_MIIRD),
+ FTGMAC100_MDIO_TIMEOUT_USEC);
+ if (ret) {
+ pr_err("%s: mdio read failed (phy:%d reg:%x)\n",
+ priv->phydev->dev->name, phy_addr, reg_addr);
+ return ret;
}
- debug("mdio read timed out\n");
- return -1;
+ data = readl(&ftgmac100->phydata);
+
+ return FTGMAC100_PHYDATA_MIIRDATA(data);
}
-static int ftgmac100_mdiobus_write(struct eth_device *dev, int phy_addr,
- int regnum, u16 value)
+static int ftgmac100_mdio_write(struct mii_dev *bus, int phy_addr, int dev_addr,
+ int reg_addr, u16 value)
{
- struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase;
+ struct ftgmac100_data *priv = bus->priv;
+ struct ftgmac100 *ftgmac100 = priv->iobase;
int phycr;
int data;
- int i;
-
- phycr = readl(&ftgmac100->phycr);
-
- /* preserve MDC cycle threshold */
- phycr &= FTGMAC100_PHYCR_MDC_CYCTHR_MASK;
-
- phycr |= FTGMAC100_PHYCR_PHYAD(phy_addr)
- | FTGMAC100_PHYCR_REGAD(regnum)
- | FTGMAC100_PHYCR_MIIWR;
+ int ret;
+ phycr = FTGMAC100_PHYCR_MDC_CYCTHR(MDC_CYCTHR) |
+ FTGMAC100_PHYCR_PHYAD(phy_addr) |
+ FTGMAC100_PHYCR_REGAD(reg_addr) |
+ FTGMAC100_PHYCR_MIIWR;
data = FTGMAC100_PHYDATA_MIIWDATA(value);
writel(data, &ftgmac100->phydata);
writel(phycr, &ftgmac100->phycr);
- for (i = 0; i < 10; i++) {
- phycr = readl(&ftgmac100->phycr);
-
- if ((phycr & FTGMAC100_PHYCR_MIIWR) == 0) {
- debug("(phycr & FTGMAC100_PHYCR_MIIWR) == 0: " \
- "phy_addr: %x\n", phy_addr);
- return 0;
- }
-
- mdelay(1);
+ ret = readl_poll_timeout(&ftgmac100->phycr, phycr,
+ !(phycr & FTGMAC100_PHYCR_MIIWR),
+ FTGMAC100_MDIO_TIMEOUT_USEC);
+ if (ret) {
+ pr_err("%s: mdio write failed (phy:%d reg:%x)\n",
+ priv->phydev->dev->name, phy_addr, reg_addr);
}
- debug("mdio write timed out\n");
- return -1;
-}
-
-int ftgmac100_phy_read(struct eth_device *dev, int addr, int reg, u16 *value)
-{
- *value = ftgmac100_mdiobus_read(dev , addr, reg);
-
- if (*value == -1)
- return -1;
-
- return 0;
+ return ret;
}
-int ftgmac100_phy_write(struct eth_device *dev, int addr, int reg, u16 value)
+static int ftgmac100_mdio_init(struct udevice *dev)
{
- if (ftgmac100_mdiobus_write(dev, addr, reg, value) == -1)
- return -1;
-
- return 0;
-}
-
-static int ftgmac100_phy_reset(struct eth_device *dev)
-{
- struct ftgmac100_data *priv = dev->priv;
- int i;
- u16 status, adv;
-
- adv = ADVERTISE_CSMA | ADVERTISE_ALL;
-
- ftgmac100_phy_write(dev, priv->phy_addr, MII_ADVERTISE, adv);
-
- printf("%s: Starting autonegotiation...\n", dev->name);
-
- ftgmac100_phy_write(dev, priv->phy_addr,
- MII_BMCR, (BMCR_ANENABLE | BMCR_ANRESTART));
-
- for (i = 0; i < 100000 / 100; i++) {
- ftgmac100_phy_read(dev, priv->phy_addr, MII_BMSR, &status);
-
- if (status & BMSR_ANEGCOMPLETE)
- break;
- mdelay(1);
+ struct ftgmac100_data *priv = dev_get_priv(dev);
+ struct mii_dev *bus;
+ int ret;
+
+ bus = mdio_alloc();
+ if (!bus)
+ return -ENOMEM;
+
+ bus->read = ftgmac100_mdio_read;
+ bus->write = ftgmac100_mdio_write;
+ bus->priv = priv;
+
+ ret = mdio_register_seq(bus, dev->seq);
+ if (ret) {
+ free(bus);
+ return ret;
}
- if (status & BMSR_ANEGCOMPLETE) {
- printf("%s: Autonegotiation complete\n", dev->name);
- } else {
- printf("%s: Autonegotiation timed out (status=0x%04x)\n",
- dev->name, status);
- return 0;
- }
+ priv->bus = bus;
- return 1;
+ return 0;
}
-static int ftgmac100_phy_init(struct eth_device *dev)
+static int ftgmac100_phy_adjust_link(struct ftgmac100_data *priv)
{
- struct ftgmac100_data *priv = dev->priv;
-
- int phy_addr;
- u16 phy_id, status, adv, lpa, stat_ge;
- int media, speed, duplex;
- int i;
+ struct ftgmac100 *ftgmac100 = priv->iobase;
+ struct phy_device *phydev = priv->phydev;
+ u32 maccr;
- /* Check if the PHY is up to snuff... */
- for (phy_addr = 0; phy_addr < CONFIG_PHY_MAX_ADDR; phy_addr++) {
-
- ftgmac100_phy_read(dev, phy_addr, MII_PHYSID1, &phy_id);
-
- /*
- * When it is unable to found PHY,
- * the interface usually return 0xffff or 0x0000
- */
- if (phy_id != 0xffff && phy_id != 0x0) {
- printf("%s: found PHY at 0x%02x\n",
- dev->name, phy_addr);
- priv->phy_addr = phy_addr;
- break;
- }
+ if (!phydev->link) {
+ dev_err(phydev->dev, "No link\n");
+ return -EREMOTEIO;
}
- if (phy_id == 0xffff || phy_id == 0x0) {
- printf("%s: no PHY present\n", dev->name);
- return 0;
- }
-
- ftgmac100_phy_read(dev, priv->phy_addr, MII_BMSR, &status);
-
- if (!(status & BMSR_LSTATUS)) {
- /* Try to re-negotiate if we don't have link already. */
- ftgmac100_phy_reset(dev);
-
- for (i = 0; i < 100000 / 100; i++) {
- ftgmac100_phy_read(dev, priv->phy_addr,
- MII_BMSR, &status);
- if (status & BMSR_LSTATUS)
- break;
- udelay(100);
- }
- }
-
- if (!(status & BMSR_LSTATUS)) {
- printf("%s: link down\n", dev->name);
- return 0;
- }
-
-#ifdef CONFIG_FTGMAC100_EGIGA
- /* 1000 Base-T Status Register */
- ftgmac100_phy_read(dev, priv->phy_addr,
- MII_STAT1000, &stat_ge);
-
- speed = (stat_ge & (LPA_1000FULL | LPA_1000HALF)
- ? 1 : 0);
-
- duplex = ((stat_ge & LPA_1000FULL)
- ? 1 : 0);
-
- if (speed) { /* Speed is 1000 */
- printf("%s: link up, 1000bps %s-duplex\n",
- dev->name, duplex ? "full" : "half");
- return 0;
- }
-#endif
-
- ftgmac100_phy_read(dev, priv->phy_addr, MII_ADVERTISE, &adv);
- ftgmac100_phy_read(dev, priv->phy_addr, MII_LPA, &lpa);
-
- media = mii_nway_result(lpa & adv);
- speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF) ? 1 : 0);
- duplex = (media & ADVERTISE_FULL) ? 1 : 0;
-
- printf("%s: link up, %sMbps %s-duplex\n",
- dev->name, speed ? "100" : "10", duplex ? "full" : "half");
-
- return 1;
-}
-
-static int ftgmac100_update_link_speed(struct eth_device *dev)
-{
- struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase;
- struct ftgmac100_data *priv = dev->priv;
-
- unsigned short stat_fe;
- unsigned short stat_ge;
- unsigned int maccr;
-
-#ifdef CONFIG_FTGMAC100_EGIGA
- /* 1000 Base-T Status Register */
- ftgmac100_phy_read(dev, priv->phy_addr, MII_STAT1000, &stat_ge);
-#endif
-
- ftgmac100_phy_read(dev, priv->phy_addr, MII_BMSR, &stat_fe);
-
- if (!(stat_fe & BMSR_LSTATUS)) /* link status up? */
- return 0;
-
/* read MAC control register and clear related bits */
maccr = readl(&ftgmac100->maccr) &
~(FTGMAC100_MACCR_GIGA_MODE |
FTGMAC100_MACCR_FAST_MODE |
FTGMAC100_MACCR_FULLDUP);
-#ifdef CONFIG_FTGMAC100_EGIGA
- if (stat_ge & LPA_1000FULL) {
- /* set gmac for 1000BaseTX and Full Duplex */
- maccr |= FTGMAC100_MACCR_GIGA_MODE | FTGMAC100_MACCR_FULLDUP;
- }
-
- if (stat_ge & LPA_1000HALF) {
- /* set gmac for 1000BaseTX and Half Duplex */
+ if (phy_interface_is_rgmii(phydev) && phydev->speed == 1000)
maccr |= FTGMAC100_MACCR_GIGA_MODE;
- }
-#endif
-
- if (stat_fe & BMSR_100FULL) {
- /* set MII for 100BaseTX and Full Duplex */
- maccr |= FTGMAC100_MACCR_FAST_MODE | FTGMAC100_MACCR_FULLDUP;
- }
- if (stat_fe & BMSR_10FULL) {
- /* set MII for 10BaseT and Full Duplex */
- maccr |= FTGMAC100_MACCR_FULLDUP;
- }
-
- if (stat_fe & BMSR_100HALF) {
- /* set MII for 100BaseTX and Half Duplex */
+ if (phydev->speed == 100)
maccr |= FTGMAC100_MACCR_FAST_MODE;
- }
- if (stat_fe & BMSR_10HALF) {
- /* set MII for 10BaseT and Half Duplex */
- /* we have already clear these bits, do nothing */
- ;
- }
+ if (phydev->duplex)
+ maccr |= FTGMAC100_MACCR_FULLDUP;
/* update MII config into maccr */
writel(maccr, &ftgmac100->maccr);
- return 1;
+ return 0;
+}
+
+static int ftgmac100_phy_init(struct udevice *dev)
+{
+ struct ftgmac100_data *priv = dev_get_priv(dev);
+ struct phy_device *phydev;
+ int ret;
+
+ phydev = phy_connect(priv->bus, priv->phy_addr, dev, priv->phy_mode);
+ if (!phydev)
+ return -ENODEV;
+
+ phydev->supported &= PHY_GBIT_FEATURES;
+ if (priv->max_speed) {
+ ret = phy_set_supported(phydev, priv->max_speed);
+ if (ret)
+ return ret;
+ }
+ phydev->advertising = phydev->supported;
+ priv->phydev = phydev;
+ phy_config(phydev);
+
+ return 0;
}
/*
* Reset MAC
*/
-static void ftgmac100_reset(struct eth_device *dev)
+static void ftgmac100_reset(struct ftgmac100_data *priv)
{
- struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase;
+ struct ftgmac100 *ftgmac100 = priv->iobase;
debug("%s()\n", __func__);
- writel(FTGMAC100_MACCR_SW_RST, &ftgmac100->maccr);
+ setbits_le32(&ftgmac100->maccr, FTGMAC100_MACCR_SW_RST);
while (readl(&ftgmac100->maccr) & FTGMAC100_MACCR_SW_RST)
;
/*
* Set MAC address
*/
-static void ftgmac100_set_mac(struct eth_device *dev,
- const unsigned char *mac)
+static int ftgmac100_set_mac(struct ftgmac100_data *priv,
+ const unsigned char *mac)
{
- struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase;
+ struct ftgmac100 *ftgmac100 = priv->iobase;
unsigned int maddr = mac[0] << 8 | mac[1];
unsigned int laddr = mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5];
writel(maddr, &ftgmac100->mac_madr);
writel(laddr, &ftgmac100->mac_ladr);
-}
-
-static void ftgmac100_set_mac_from_env(struct eth_device *dev)
-{
- eth_env_get_enetaddr("ethaddr", dev->enetaddr);
- ftgmac100_set_mac(dev, dev->enetaddr);
+ return 0;
}
/*
* disable transmitter, receiver
*/
-static void ftgmac100_halt(struct eth_device *dev)
+static void ftgmac100_stop(struct udevice *dev)
{
- struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase;
+ struct ftgmac100_data *priv = dev_get_priv(dev);
+ struct ftgmac100 *ftgmac100 = priv->iobase;
debug("%s()\n", __func__);
writel(0, &ftgmac100->maccr);
+
+ phy_shutdown(priv->phydev);
}
-static int ftgmac100_init(struct eth_device *dev, bd_t *bd)
+static int ftgmac100_start(struct udevice *dev)
{
- struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase;
- struct ftgmac100_data *priv = dev->priv;
- struct ftgmac100_txdes *txdes;
- struct ftgmac100_rxdes *rxdes;
+ struct eth_pdata *plat = dev_get_platdata(dev);
+ struct ftgmac100_data *priv = dev_get_priv(dev);
+ struct ftgmac100 *ftgmac100 = priv->iobase;
+ struct phy_device *phydev = priv->phydev;
unsigned int maccr;
- void *buf;
+ ulong start, end;
+ int ret;
int i;
debug("%s()\n", __func__);
- if (!priv->txdes) {
- txdes = dma_alloc_coherent(
- sizeof(*txdes) * PKTBUFSTX, &priv->txdes_dma);
- if (!txdes)
- panic("ftgmac100: out of memory\n");
- memset(txdes, 0, sizeof(*txdes) * PKTBUFSTX);
- priv->txdes = txdes;
- }
- txdes = priv->txdes;
-
- if (!priv->rxdes) {
- rxdes = dma_alloc_coherent(
- sizeof(*rxdes) * PKTBUFSRX, &priv->rxdes_dma);
- if (!rxdes)
- panic("ftgmac100: out of memory\n");
- memset(rxdes, 0, sizeof(*rxdes) * PKTBUFSRX);
- priv->rxdes = rxdes;
- }
- rxdes = priv->rxdes;
+ ftgmac100_reset(priv);
/* set the ethernet address */
- ftgmac100_set_mac_from_env(dev);
+ ftgmac100_set_mac(priv, plat->enetaddr);
/* disable all interrupts */
writel(0, &ftgmac100->ier);
priv->tx_index = 0;
priv->rx_index = 0;
- txdes[PKTBUFSTX - 1].txdes0 = FTGMAC100_TXDES0_EDOTR;
- rxdes[PKTBUFSRX - 1].rxdes0 = FTGMAC100_RXDES0_EDORR;
-
for (i = 0; i < PKTBUFSTX; i++) {
- /* TXBUF_BADR */
- if (!txdes[i].txdes2) {
- buf = memalign(ARCH_DMA_MINALIGN, CFG_XBUF_SIZE);
- if (!buf)
- panic("ftgmac100: out of memory\n");
- txdes[i].txdes3 = virt_to_phys(buf);
- txdes[i].txdes2 = (uint)buf;
- }
- txdes[i].txdes1 = 0;
+ priv->txdes[i].txdes3 = 0;
+ priv->txdes[i].txdes0 = 0;
}
+ priv->txdes[PKTBUFSTX - 1].txdes0 = priv->txdes0_edotr_mask;
+
+ start = (ulong)&priv->txdes[0];
+ end = start + roundup(sizeof(priv->txdes), ARCH_DMA_MINALIGN);
+ flush_dcache_range(start, end);
for (i = 0; i < PKTBUFSRX; i++) {
- /* RXBUF_BADR */
- if (!rxdes[i].rxdes2) {
- buf = net_rx_packets[i];
- rxdes[i].rxdes3 = virt_to_phys(buf);
- rxdes[i].rxdes2 = (uint)buf;
- }
- rxdes[i].rxdes0 &= ~FTGMAC100_RXDES0_RXPKT_RDY;
+ priv->rxdes[i].rxdes3 = (unsigned int)net_rx_packets[i];
+ priv->rxdes[i].rxdes0 = 0;
}
+ priv->rxdes[PKTBUFSRX - 1].rxdes0 = priv->rxdes0_edorr_mask;
+
+ start = (ulong)&priv->rxdes[0];
+ end = start + roundup(sizeof(priv->rxdes), ARCH_DMA_MINALIGN);
+ flush_dcache_range(start, end);
/* transmit ring */
- writel(priv->txdes_dma, &ftgmac100->txr_badr);
+ writel((u32)priv->txdes, &ftgmac100->txr_badr);
/* receive ring */
- writel(priv->rxdes_dma, &ftgmac100->rxr_badr);
+ writel((u32)priv->rxdes, &ftgmac100->rxr_badr);
/* poll receive descriptor automatically */
writel(FTGMAC100_APTC_RXPOLL_CNT(1), &ftgmac100->aptc);
/* config receive buffer size register */
- writel(FTGMAC100_RBSR_SIZE(RBSR_DEFAULT_VALUE), &ftgmac100->rbsr);
+ writel(FTGMAC100_RBSR_SIZE(FTGMAC100_RBSR_DEFAULT), &ftgmac100->rbsr);
/* enable transmitter, receiver */
maccr = FTGMAC100_MACCR_TXMAC_EN |
writel(maccr, &ftgmac100->maccr);
- if (!ftgmac100_phy_init(dev)) {
- if (!ftgmac100_update_link_speed(dev))
- return -1;
+ ret = phy_startup(phydev);
+ if (ret) {
+ dev_err(phydev->dev, "Could not start PHY\n");
+ return ret;
}
+ ret = ftgmac100_phy_adjust_link(priv);
+ if (ret) {
+ dev_err(phydev->dev, "Could not adjust link\n");
+ return ret;
+ }
+
+ printf("%s: link up, %d Mbps %s-duplex mac:%pM\n", phydev->dev->name,
+ phydev->speed, phydev->duplex ? "full" : "half", plat->enetaddr);
+
+ return 0;
+}
+
+static int ftgmac100_free_pkt(struct udevice *dev, uchar *packet, int length)
+{
+ struct ftgmac100_data *priv = dev_get_priv(dev);
+ struct ftgmac100_rxdes *curr_des = &priv->rxdes[priv->rx_index];
+ ulong des_start = (ulong)curr_des;
+ ulong des_end = des_start +
+ roundup(sizeof(*curr_des), ARCH_DMA_MINALIGN);
+
+ /* Release buffer to DMA and flush descriptor */
+ curr_des->rxdes0 &= ~FTGMAC100_RXDES0_RXPKT_RDY;
+ flush_dcache_range(des_start, des_end);
+
+ /* Move to next descriptor */
+ priv->rx_index = (priv->rx_index + 1) % PKTBUFSRX;
+
return 0;
}
/*
* Get a data block via Ethernet
*/
-static int ftgmac100_recv(struct eth_device *dev)
+static int ftgmac100_recv(struct udevice *dev, int flags, uchar **packetp)
{
- struct ftgmac100_data *priv = dev->priv;
- struct ftgmac100_rxdes *curr_des;
+ struct ftgmac100_data *priv = dev_get_priv(dev);
+ struct ftgmac100_rxdes *curr_des = &priv->rxdes[priv->rx_index];
unsigned short rxlen;
+ ulong des_start = (ulong)curr_des;
+ ulong des_end = des_start +
+ roundup(sizeof(*curr_des), ARCH_DMA_MINALIGN);
+ ulong data_start = curr_des->rxdes3;
+ ulong data_end;
- curr_des = &priv->rxdes[priv->rx_index];
+ invalidate_dcache_range(des_start, des_end);
if (!(curr_des->rxdes0 & FTGMAC100_RXDES0_RXPKT_RDY))
- return -1;
+ return -EAGAIN;
if (curr_des->rxdes0 & (FTGMAC100_RXDES0_RX_ERR |
FTGMAC100_RXDES0_CRC_ERR |
FTGMAC100_RXDES0_FTL |
FTGMAC100_RXDES0_RUNT |
FTGMAC100_RXDES0_RX_ODD_NB)) {
- return -1;
+ return -EAGAIN;
}
rxlen = FTGMAC100_RXDES0_VDBC(curr_des->rxdes0);
debug("%s(): RX buffer %d, %x received\n",
__func__, priv->rx_index, rxlen);
- /* invalidate d-cache */
- dma_map_single((void *)curr_des->rxdes2, rxlen, DMA_FROM_DEVICE);
+ /* Invalidate received data */
+ data_end = data_start + roundup(rxlen, ARCH_DMA_MINALIGN);
+ invalidate_dcache_range(data_start, data_end);
+ *packetp = (uchar *)data_start;
- /* pass the packet up to the protocol layers. */
- net_process_received_packet((void *)curr_des->rxdes2, rxlen);
+ return rxlen;
+}
- /* release buffer to DMA */
- curr_des->rxdes0 &= ~FTGMAC100_RXDES0_RXPKT_RDY;
+static u32 ftgmac100_read_txdesc(const void *desc)
+{
+ const struct ftgmac100_txdes *txdes = desc;
+ ulong des_start = (ulong)txdes;
+ ulong des_end = des_start + roundup(sizeof(*txdes), ARCH_DMA_MINALIGN);
- priv->rx_index = (priv->rx_index + 1) % PKTBUFSRX;
+ invalidate_dcache_range(des_start, des_end);
- return 0;
+ return txdes->txdes0;
}
+BUILD_WAIT_FOR_BIT(ftgmac100_txdone, u32, ftgmac100_read_txdesc)
+
/*
* Send a data block via Ethernet
*/
-static int ftgmac100_send(struct eth_device *dev, void *packet, int length)
+static int ftgmac100_send(struct udevice *dev, void *packet, int length)
{
- struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase;
- struct ftgmac100_data *priv = dev->priv;
+ struct ftgmac100_data *priv = dev_get_priv(dev);
+ struct ftgmac100 *ftgmac100 = priv->iobase;
struct ftgmac100_txdes *curr_des = &priv->txdes[priv->tx_index];
+ ulong des_start = (ulong)curr_des;
+ ulong des_end = des_start +
+ roundup(sizeof(*curr_des), ARCH_DMA_MINALIGN);
+ ulong data_start;
+ ulong data_end;
+ int rc;
+
+ invalidate_dcache_range(des_start, des_end);
if (curr_des->txdes0 & FTGMAC100_TXDES0_TXDMA_OWN) {
- debug("%s(): no TX descriptor available\n", __func__);
- return -1;
+ dev_err(dev, "no TX descriptor available\n");
+ return -EPERM;
}
debug("%s(%x, %x)\n", __func__, (int)packet, length);
length = (length < ETH_ZLEN) ? ETH_ZLEN : length;
- memcpy((void *)curr_des->txdes2, (void *)packet, length);
- dma_map_single((void *)curr_des->txdes2, length, DMA_TO_DEVICE);
+ curr_des->txdes3 = (unsigned int)packet;
- /* only one descriptor on TXBUF */
- curr_des->txdes0 &= FTGMAC100_TXDES0_EDOTR;
+ /* Flush data to be sent */
+ data_start = curr_des->txdes3;
+ data_end = data_start + roundup(length, ARCH_DMA_MINALIGN);
+ flush_dcache_range(data_start, data_end);
+
+ /* Only one segment on TXBUF */
+ curr_des->txdes0 &= priv->txdes0_edotr_mask;
curr_des->txdes0 |= FTGMAC100_TXDES0_FTS |
FTGMAC100_TXDES0_LTS |
FTGMAC100_TXDES0_TXBUF_SIZE(length) |
FTGMAC100_TXDES0_TXDMA_OWN ;
- /* start transmit */
+ /* Flush modified buffer descriptor */
+ flush_dcache_range(des_start, des_end);
+
+ /* Start transmit */
writel(1, &ftgmac100->txpd);
+ rc = wait_for_bit_ftgmac100_txdone(curr_des,
+ FTGMAC100_TXDES0_TXDMA_OWN, false,
+ FTGMAC100_TX_TIMEOUT_MS, true);
+ if (rc)
+ return rc;
+
debug("%s(): packet sent\n", __func__);
+ /* Move to next descriptor */
priv->tx_index = (priv->tx_index + 1) % PKTBUFSTX;
return 0;
}
-int ftgmac100_initialize(bd_t *bd)
+static int ftgmac100_write_hwaddr(struct udevice *dev)
{
- struct eth_device *dev;
- struct ftgmac100_data *priv;
+ struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct ftgmac100_data *priv = dev_get_priv(dev);
- dev = malloc(sizeof *dev);
- if (!dev) {
- printf("%s(): failed to allocate dev\n", __func__);
- goto out;
+ return ftgmac100_set_mac(priv, pdata->enetaddr);
+}
+
+static int ftgmac100_ofdata_to_platdata(struct udevice *dev)
+{
+ struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct ftgmac100_data *priv = dev_get_priv(dev);
+ const char *phy_mode;
+
+ pdata->iobase = devfdt_get_addr(dev);
+ pdata->phy_interface = -1;
+ phy_mode = dev_read_string(dev, "phy-mode");
+ if (phy_mode)
+ pdata->phy_interface = phy_get_interface_by_name(phy_mode);
+ if (pdata->phy_interface == -1) {
+ dev_err(dev, "Invalid PHY interface '%s'\n", phy_mode);
+ return -EINVAL;
}
- /* Transmit and receive descriptors should align to 16 bytes */
- priv = memalign(16, sizeof(struct ftgmac100_data));
- if (!priv) {
- printf("%s(): failed to allocate priv\n", __func__);
- goto free_dev;
+ pdata->max_speed = dev_read_u32_default(dev, "max-speed", 0);
+
+ if (dev_get_driver_data(dev) == FTGMAC100_MODEL_ASPEED) {
+ priv->rxdes0_edorr_mask = BIT(30);
+ priv->txdes0_edotr_mask = BIT(30);
+ } else {
+ priv->rxdes0_edorr_mask = BIT(15);
+ priv->txdes0_edotr_mask = BIT(15);
}
- memset(dev, 0, sizeof(*dev));
- memset(priv, 0, sizeof(*priv));
+ return clk_get_bulk(dev, &priv->clks);
+}
- strcpy(dev->name, "FTGMAC100");
- dev->iobase = CONFIG_FTGMAC100_BASE;
- dev->init = ftgmac100_init;
- dev->halt = ftgmac100_halt;
- dev->send = ftgmac100_send;
- dev->recv = ftgmac100_recv;
- dev->priv = priv;
+static int ftgmac100_probe(struct udevice *dev)
+{
+ struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct ftgmac100_data *priv = dev_get_priv(dev);
+ int ret;
+
+ priv->iobase = (struct ftgmac100 *)pdata->iobase;
+ priv->phy_mode = pdata->phy_interface;
+ priv->max_speed = pdata->max_speed;
+ priv->phy_addr = 0;
- eth_register(dev);
+ ret = clk_enable_bulk(&priv->clks);
+ if (ret)
+ goto out;
- ftgmac100_reset(dev);
+ ret = ftgmac100_mdio_init(dev);
+ if (ret) {
+ dev_err(dev, "Failed to initialize mdiobus: %d\n", ret);
+ goto out;
+ }
- return 1;
+ ret = ftgmac100_phy_init(dev);
+ if (ret) {
+ dev_err(dev, "Failed to initialize PHY: %d\n", ret);
+ goto out;
+ }
-free_dev:
- free(dev);
out:
+ if (ret)
+ clk_release_bulk(&priv->clks);
+
+ return ret;
+}
+
+static int ftgmac100_remove(struct udevice *dev)
+{
+ struct ftgmac100_data *priv = dev_get_priv(dev);
+
+ free(priv->phydev);
+ mdio_unregister(priv->bus);
+ mdio_free(priv->bus);
+ clk_release_bulk(&priv->clks);
+
return 0;
}
+
+static const struct eth_ops ftgmac100_ops = {
+ .start = ftgmac100_start,
+ .send = ftgmac100_send,
+ .recv = ftgmac100_recv,
+ .stop = ftgmac100_stop,
+ .free_pkt = ftgmac100_free_pkt,
+ .write_hwaddr = ftgmac100_write_hwaddr,
+};
+
+static const struct udevice_id ftgmac100_ids[] = {
+ { .compatible = "faraday,ftgmac100", .data = FTGMAC100_MODEL_FARADAY },
+ { .compatible = "aspeed,ast2500-mac", .data = FTGMAC100_MODEL_ASPEED },
+ { }
+};
+
+U_BOOT_DRIVER(ftgmac100) = {
+ .name = "ftgmac100",
+ .id = UCLASS_ETH,
+ .of_match = ftgmac100_ids,
+ .ofdata_to_platdata = ftgmac100_ofdata_to_platdata,
+ .probe = ftgmac100_probe,
+ .remove = ftgmac100_remove,
+ .ops = &ftgmac100_ops,
+ .priv_auto_alloc_size = sizeof(struct ftgmac100_data),
+ .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+ .flags = DM_FLAG_ALLOC_PRIV_DMA,
+};
/*
* Interrupt status register & interrupt enable register
*/
-#define FTGMAC100_INT_RPKT_BUF (1 << 0)
-#define FTGMAC100_INT_RPKT_FIFO (1 << 1)
-#define FTGMAC100_INT_NO_RXBUF (1 << 2)
-#define FTGMAC100_INT_RPKT_LOST (1 << 3)
-#define FTGMAC100_INT_XPKT_ETH (1 << 4)
-#define FTGMAC100_INT_XPKT_FIFO (1 << 5)
-#define FTGMAC100_INT_NO_NPTXBUF (1 << 6)
-#define FTGMAC100_INT_XPKT_LOST (1 << 7)
-#define FTGMAC100_INT_AHB_ERR (1 << 8)
-#define FTGMAC100_INT_PHYSTS_CHG (1 << 9)
-#define FTGMAC100_INT_NO_HPTXBUF (1 << 10)
+#define FTGMAC100_INT_RPKT_BUF BIT(0)
+#define FTGMAC100_INT_RPKT_FIFO BIT(1)
+#define FTGMAC100_INT_NO_RXBUF BIT(2)
+#define FTGMAC100_INT_RPKT_LOST BIT(3)
+#define FTGMAC100_INT_XPKT_ETH BIT(4)
+#define FTGMAC100_INT_XPKT_FIFO BIT(5)
+#define FTGMAC100_INT_NO_NPTXBUF BIT(6)
+#define FTGMAC100_INT_XPKT_LOST BIT(7)
+#define FTGMAC100_INT_AHB_ERR BIT(8)
+#define FTGMAC100_INT_PHYSTS_CHG BIT(9)
+#define FTGMAC100_INT_NO_HPTXBUF BIT(10)
/*
* Interrupt timer control register
*/
#define FTGMAC100_ITC_RXINT_CNT(x) (((x) & 0xf) << 0)
#define FTGMAC100_ITC_RXINT_THR(x) (((x) & 0x7) << 4)
-#define FTGMAC100_ITC_RXINT_TIME_SEL (1 << 7)
+#define FTGMAC100_ITC_RXINT_TIME_SEL BIT(7)
#define FTGMAC100_ITC_TXINT_CNT(x) (((x) & 0xf) << 8)
#define FTGMAC100_ITC_TXINT_THR(x) (((x) & 0x7) << 12)
-#define FTGMAC100_ITC_TXINT_TIME_SEL (1 << 15)
+#define FTGMAC100_ITC_TXINT_TIME_SEL BIT(15)
/*
* Automatic polling timer control register
*/
#define FTGMAC100_APTC_RXPOLL_CNT(x) (((x) & 0xf) << 0)
-#define FTGMAC100_APTC_RXPOLL_TIME_SEL (1 << 4)
+#define FTGMAC100_APTC_RXPOLL_TIME_SEL BIT(4)
#define FTGMAC100_APTC_TXPOLL_CNT(x) (((x) & 0xf) << 8)
-#define FTGMAC100_APTC_TXPOLL_TIME_SEL (1 << 12)
+#define FTGMAC100_APTC_TXPOLL_TIME_SEL BIT(12)
/*
* DMA burst length and arbitration control register
*/
#define FTGMAC100_DBLAC_RXFIFO_LTHR(x) (((x) & 0x7) << 0)
#define FTGMAC100_DBLAC_RXFIFO_HTHR(x) (((x) & 0x7) << 3)
-#define FTGMAC100_DBLAC_RX_THR_EN (1 << 6)
+#define FTGMAC100_DBLAC_RX_THR_EN BIT(6)
#define FTGMAC100_DBLAC_RXBURST_SIZE(x) (((x) & 0x3) << 8)
#define FTGMAC100_DBLAC_TXBURST_SIZE(x) (((x) & 0x3) << 10)
#define FTGMAC100_DBLAC_RXDES_SIZE(x) (((x) & 0xf) << 12)
#define FTGMAC100_DBLAC_TXDES_SIZE(x) (((x) & 0xf) << 16)
#define FTGMAC100_DBLAC_IFG_CNT(x) (((x) & 0x7) << 20)
-#define FTGMAC100_DBLAC_IFG_INC (1 << 23)
+#define FTGMAC100_DBLAC_IFG_INC BIT(23)
/*
* DMA FIFO status register
#define FTGMAC100_DMAFIFOS_TXDMA1_SM(dmafifos) (((dmafifos) >> 12) & 0xf)
#define FTGMAC100_DMAFIFOS_TXDMA2_SM(dmafifos) (((dmafifos) >> 16) & 0x3)
#define FTGMAC100_DMAFIFOS_TXDMA3_SM(dmafifos) (((dmafifos) >> 18) & 0xf)
-#define FTGMAC100_DMAFIFOS_RXFIFO_EMPTY (1 << 26)
-#define FTGMAC100_DMAFIFOS_TXFIFO_EMPTY (1 << 27)
-#define FTGMAC100_DMAFIFOS_RXDMA_GRANT (1 << 28)
-#define FTGMAC100_DMAFIFOS_TXDMA_GRANT (1 << 29)
-#define FTGMAC100_DMAFIFOS_RXDMA_REQ (1 << 30)
-#define FTGMAC100_DMAFIFOS_TXDMA_REQ (1 << 31)
+#define FTGMAC100_DMAFIFOS_RXFIFO_EMPTY BIT(26)
+#define FTGMAC100_DMAFIFOS_TXFIFO_EMPTY BIT(27)
+#define FTGMAC100_DMAFIFOS_RXDMA_GRANT BIT(28)
+#define FTGMAC100_DMAFIFOS_TXDMA_GRANT BIT(29)
+#define FTGMAC100_DMAFIFOS_RXDMA_REQ BIT(30)
+#define FTGMAC100_DMAFIFOS_TXDMA_REQ BIT(31)
/*
* Receive buffer size register
/*
* MAC control register
*/
-#define FTGMAC100_MACCR_TXDMA_EN (1 << 0)
-#define FTGMAC100_MACCR_RXDMA_EN (1 << 1)
-#define FTGMAC100_MACCR_TXMAC_EN (1 << 2)
-#define FTGMAC100_MACCR_RXMAC_EN (1 << 3)
-#define FTGMAC100_MACCR_RM_VLAN (1 << 4)
-#define FTGMAC100_MACCR_HPTXR_EN (1 << 5)
-#define FTGMAC100_MACCR_LOOP_EN (1 << 6)
-#define FTGMAC100_MACCR_ENRX_IN_HALFTX (1 << 7)
-#define FTGMAC100_MACCR_FULLDUP (1 << 8)
-#define FTGMAC100_MACCR_GIGA_MODE (1 << 9)
-#define FTGMAC100_MACCR_CRC_APD (1 << 10)
-#define FTGMAC100_MACCR_RX_RUNT (1 << 12)
-#define FTGMAC100_MACCR_JUMBO_LF (1 << 13)
-#define FTGMAC100_MACCR_RX_ALL (1 << 14)
-#define FTGMAC100_MACCR_HT_MULTI_EN (1 << 15)
-#define FTGMAC100_MACCR_RX_MULTIPKT (1 << 16)
-#define FTGMAC100_MACCR_RX_BROADPKT (1 << 17)
-#define FTGMAC100_MACCR_DISCARD_CRCERR (1 << 18)
-#define FTGMAC100_MACCR_FAST_MODE (1 << 19)
-#define FTGMAC100_MACCR_SW_RST (1 << 31)
+#define FTGMAC100_MACCR_TXDMA_EN BIT(0)
+#define FTGMAC100_MACCR_RXDMA_EN BIT(1)
+#define FTGMAC100_MACCR_TXMAC_EN BIT(2)
+#define FTGMAC100_MACCR_RXMAC_EN BIT(3)
+#define FTGMAC100_MACCR_RM_VLAN BIT(4)
+#define FTGMAC100_MACCR_HPTXR_EN BIT(5)
+#define FTGMAC100_MACCR_LOOP_EN BIT(6)
+#define FTGMAC100_MACCR_ENRX_IN_HALFTX BIT(7)
+#define FTGMAC100_MACCR_FULLDUP BIT(8)
+#define FTGMAC100_MACCR_GIGA_MODE BIT(9)
+#define FTGMAC100_MACCR_CRC_APD BIT(10)
+#define FTGMAC100_MACCR_RX_RUNT BIT(12)
+#define FTGMAC100_MACCR_JUMBO_LF BIT(13)
+#define FTGMAC100_MACCR_RX_ALL BIT(14)
+#define FTGMAC100_MACCR_HT_MULTI_EN BIT(15)
+#define FTGMAC100_MACCR_RX_MULTIPKT BIT(16)
+#define FTGMAC100_MACCR_RX_BROADPKT BIT(17)
+#define FTGMAC100_MACCR_DISCARD_CRCERR BIT(18)
+#define FTGMAC100_MACCR_FAST_MODE BIT(19)
+#define FTGMAC100_MACCR_SW_RST BIT(31)
/*
* PHY control register
#define FTGMAC100_PHYCR_MDC_CYCTHR(x) ((x) & 0x3f)
#define FTGMAC100_PHYCR_PHYAD(x) (((x) & 0x1f) << 16)
#define FTGMAC100_PHYCR_REGAD(x) (((x) & 0x1f) << 21)
-#define FTGMAC100_PHYCR_MIIRD (1 << 26)
-#define FTGMAC100_PHYCR_MIIWR (1 << 27)
+#define FTGMAC100_PHYCR_MIIRD BIT(26)
+#define FTGMAC100_PHYCR_MIIWR BIT(27)
/*
* PHY data register
unsigned int txdes1;
unsigned int txdes2; /* not used by HW */
unsigned int txdes3; /* TXBUF_BADR */
-} __attribute__ ((aligned(16)));
+} __aligned(16);
#define FTGMAC100_TXDES0_TXBUF_SIZE(x) ((x) & 0x3fff)
-#define FTGMAC100_TXDES0_EDOTR (1 << 15)
-#define FTGMAC100_TXDES0_CRC_ERR (1 << 19)
-#define FTGMAC100_TXDES0_LTS (1 << 28)
-#define FTGMAC100_TXDES0_FTS (1 << 29)
-#define FTGMAC100_TXDES0_TXDMA_OWN (1 << 31)
+#define FTGMAC100_TXDES0_EDOTR BIT(15)
+#define FTGMAC100_TXDES0_CRC_ERR BIT(19)
+#define FTGMAC100_TXDES0_LTS BIT(28)
+#define FTGMAC100_TXDES0_FTS BIT(29)
+#define FTGMAC100_TXDES0_TXDMA_OWN BIT(31)
#define FTGMAC100_TXDES1_VLANTAG_CI(x) ((x) & 0xffff)
-#define FTGMAC100_TXDES1_INS_VLANTAG (1 << 16)
-#define FTGMAC100_TXDES1_TCP_CHKSUM (1 << 17)
-#define FTGMAC100_TXDES1_UDP_CHKSUM (1 << 18)
-#define FTGMAC100_TXDES1_IP_CHKSUM (1 << 19)
-#define FTGMAC100_TXDES1_LLC (1 << 22)
-#define FTGMAC100_TXDES1_TX2FIC (1 << 30)
-#define FTGMAC100_TXDES1_TXIC (1 << 31)
+#define FTGMAC100_TXDES1_INS_VLANTAG BIT(16)
+#define FTGMAC100_TXDES1_TCP_CHKSUM BIT(17)
+#define FTGMAC100_TXDES1_UDP_CHKSUM BIT(18)
+#define FTGMAC100_TXDES1_IP_CHKSUM BIT(19)
+#define FTGMAC100_TXDES1_LLC BIT(22)
+#define FTGMAC100_TXDES1_TX2FIC BIT(30)
+#define FTGMAC100_TXDES1_TXIC BIT(31)
/*
* Receive descriptor, aligned to 16 bytes
unsigned int rxdes1;
unsigned int rxdes2; /* not used by HW */
unsigned int rxdes3; /* RXBUF_BADR */
-} __attribute__ ((aligned(16)));
+} __aligned(16);
#define FTGMAC100_RXDES0_VDBC(x) ((x) & 0x3fff)
-#define FTGMAC100_RXDES0_EDORR (1 << 15)
-#define FTGMAC100_RXDES0_MULTICAST (1 << 16)
-#define FTGMAC100_RXDES0_BROADCAST (1 << 17)
-#define FTGMAC100_RXDES0_RX_ERR (1 << 18)
-#define FTGMAC100_RXDES0_CRC_ERR (1 << 19)
-#define FTGMAC100_RXDES0_FTL (1 << 20)
-#define FTGMAC100_RXDES0_RUNT (1 << 21)
-#define FTGMAC100_RXDES0_RX_ODD_NB (1 << 22)
-#define FTGMAC100_RXDES0_FIFO_FULL (1 << 23)
-#define FTGMAC100_RXDES0_PAUSE_OPCODE (1 << 24)
-#define FTGMAC100_RXDES0_PAUSE_FRAME (1 << 25)
-#define FTGMAC100_RXDES0_LRS (1 << 28)
-#define FTGMAC100_RXDES0_FRS (1 << 29)
-#define FTGMAC100_RXDES0_RXPKT_RDY (1 << 31)
+#define FTGMAC100_RXDES0_EDORR BIT(15)
+#define FTGMAC100_RXDES0_MULTICAST BIT(16)
+#define FTGMAC100_RXDES0_BROADCAST BIT(17)
+#define FTGMAC100_RXDES0_RX_ERR BIT(18)
+#define FTGMAC100_RXDES0_CRC_ERR BIT(19)
+#define FTGMAC100_RXDES0_FTL BIT(20)
+#define FTGMAC100_RXDES0_RUNT BIT(21)
+#define FTGMAC100_RXDES0_RX_ODD_NB BIT(22)
+#define FTGMAC100_RXDES0_FIFO_FULL BIT(23)
+#define FTGMAC100_RXDES0_PAUSE_OPCODE BIT(24)
+#define FTGMAC100_RXDES0_PAUSE_FRAME BIT(25)
+#define FTGMAC100_RXDES0_LRS BIT(28)
+#define FTGMAC100_RXDES0_FRS BIT(29)
+#define FTGMAC100_RXDES0_RXPKT_RDY BIT(31)
#define FTGMAC100_RXDES1_VLANTAG_CI 0xffff
#define FTGMAC100_RXDES1_PROT_MASK (0x3 << 20)
#define FTGMAC100_RXDES1_PROT_IP (0x1 << 20)
#define FTGMAC100_RXDES1_PROT_TCPIP (0x2 << 20)
#define FTGMAC100_RXDES1_PROT_UDPIP (0x3 << 20)
-#define FTGMAC100_RXDES1_LLC (1 << 22)
-#define FTGMAC100_RXDES1_DF (1 << 23)
-#define FTGMAC100_RXDES1_VLANTAG_AVAIL (1 << 24)
-#define FTGMAC100_RXDES1_TCP_CHKSUM_ERR (1 << 25)
-#define FTGMAC100_RXDES1_UDP_CHKSUM_ERR (1 << 26)
-#define FTGMAC100_RXDES1_IP_CHKSUM_ERR (1 << 27)
+#define FTGMAC100_RXDES1_LLC BIT(22)
+#define FTGMAC100_RXDES1_DF BIT(23)
+#define FTGMAC100_RXDES1_VLANTAG_AVAIL BIT(24)
+#define FTGMAC100_RXDES1_TCP_CHKSUM_ERR BIT(25)
+#define FTGMAC100_RXDES1_UDP_CHKSUM_ERR BIT(26)
+#define FTGMAC100_RXDES1_IP_CHKSUM_ERR BIT(27)
#endif /* __FTGMAC100_H */
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Ethernet driver for TI K2HK EVM.
- *
- * (C) Copyright 2012-2014
- * Texas Instruments Incorporated, <www.ti.com>
- */
-#include <common.h>
-#include <command.h>
-#include <console.h>
-
-#include <dm.h>
-#include <dm/lists.h>
-
-#include <net.h>
-#include <phy.h>
-#include <errno.h>
-#include <miiphy.h>
-#include <malloc.h>
-#include <asm/ti-common/keystone_nav.h>
-#include <asm/ti-common/keystone_net.h>
-#include <asm/ti-common/keystone_serdes.h>
-#include <asm/arch/psc_defs.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifndef CONFIG_DM_ETH
-unsigned int emac_open;
-static struct mii_dev *mdio_bus;
-static unsigned int sys_has_mdio = 1;
-#endif
-
-#ifdef KEYSTONE2_EMAC_GIG_ENABLE
-#define emac_gigabit_enable(x) keystone2_eth_gigabit_enable(x)
-#else
-#define emac_gigabit_enable(x) /* no gigabit to enable */
-#endif
-
-#define RX_BUFF_NUMS 24
-#define RX_BUFF_LEN 1520
-#define MAX_SIZE_STREAM_BUFFER RX_BUFF_LEN
-#define SGMII_ANEG_TIMEOUT 4000
-
-static u8 rx_buffs[RX_BUFF_NUMS * RX_BUFF_LEN] __aligned(16);
-
-#ifndef CONFIG_DM_ETH
-struct rx_buff_desc net_rx_buffs = {
- .buff_ptr = rx_buffs,
- .num_buffs = RX_BUFF_NUMS,
- .buff_len = RX_BUFF_LEN,
- .rx_flow = 22,
-};
-#endif
-
-#ifdef CONFIG_DM_ETH
-
-enum link_type {
- LINK_TYPE_SGMII_MAC_TO_MAC_AUTO = 0,
- LINK_TYPE_SGMII_MAC_TO_PHY_MODE = 1,
- LINK_TYPE_SGMII_MAC_TO_MAC_FORCED_MODE = 2,
- LINK_TYPE_SGMII_MAC_TO_FIBRE_MODE = 3,
- LINK_TYPE_SGMII_MAC_TO_PHY_NO_MDIO_MODE = 4,
- LINK_TYPE_RGMII_LINK_MAC_PHY = 5,
- LINK_TYPE_RGMII_LINK_MAC_MAC_FORCED = 6,
- LINK_TYPE_RGMII_LINK_MAC_PHY_NO_MDIO = 7,
- LINK_TYPE_10G_MAC_TO_PHY_MODE = 10,
- LINK_TYPE_10G_MAC_TO_MAC_FORCED_MODE = 11,
-};
-
-#define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \
- ((mac)[2] << 16) | ((mac)[3] << 24))
-#define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8))
-
-#ifdef CONFIG_KSNET_NETCP_V1_0
-
-#define EMAC_EMACSW_BASE_OFS 0x90800
-#define EMAC_EMACSW_PORT_BASE_OFS (EMAC_EMACSW_BASE_OFS + 0x60)
-
-/* CPSW Switch slave registers */
-#define CPGMACSL_REG_SA_LO 0x10
-#define CPGMACSL_REG_SA_HI 0x14
-
-#define DEVICE_EMACSW_BASE(base, x) ((base) + EMAC_EMACSW_PORT_BASE_OFS + \
- (x) * 0x30)
-
-#elif defined CONFIG_KSNET_NETCP_V1_5
-
-#define EMAC_EMACSW_PORT_BASE_OFS 0x222000
-
-/* CPSW Switch slave registers */
-#define CPGMACSL_REG_SA_LO 0x308
-#define CPGMACSL_REG_SA_HI 0x30c
-
-#define DEVICE_EMACSW_BASE(base, x) ((base) + EMAC_EMACSW_PORT_BASE_OFS + \
- (x) * 0x1000)
-
-#endif
-
-
-struct ks2_eth_priv {
- struct udevice *dev;
- struct phy_device *phydev;
- struct mii_dev *mdio_bus;
- int phy_addr;
- phy_interface_t phy_if;
- int sgmii_link_type;
- void *mdio_base;
- struct rx_buff_desc net_rx_buffs;
- struct pktdma_cfg *netcp_pktdma;
- void *hd;
- int slave_port;
- enum link_type link_type;
- bool emac_open;
- bool has_mdio;
-};
-#endif
-
-/* MDIO */
-
-static int keystone2_mdio_reset(struct mii_dev *bus)
-{
- u_int32_t clkdiv;
- struct mdio_regs *adap_mdio = bus->priv;
-
- clkdiv = (EMAC_MDIO_BUS_FREQ / EMAC_MDIO_CLOCK_FREQ) - 1;
-
- writel((clkdiv & 0xffff) | MDIO_CONTROL_ENABLE |
- MDIO_CONTROL_FAULT | MDIO_CONTROL_FAULT_ENABLE,
- &adap_mdio->control);
-
- while (readl(&adap_mdio->control) & MDIO_CONTROL_IDLE)
- ;
-
- return 0;
-}
-
-/**
- * keystone2_mdio_read - read a PHY register via MDIO interface.
- * Blocks until operation is complete.
- */
-static int keystone2_mdio_read(struct mii_dev *bus,
- int addr, int devad, int reg)
-{
- int tmp;
- struct mdio_regs *adap_mdio = bus->priv;
-
- while (readl(&adap_mdio->useraccess0) & MDIO_USERACCESS0_GO)
- ;
-
- writel(MDIO_USERACCESS0_GO | MDIO_USERACCESS0_WRITE_READ |
- ((reg & 0x1f) << 21) | ((addr & 0x1f) << 16),
- &adap_mdio->useraccess0);
-
- /* Wait for command to complete */
- while ((tmp = readl(&adap_mdio->useraccess0)) & MDIO_USERACCESS0_GO)
- ;
-
- if (tmp & MDIO_USERACCESS0_ACK)
- return tmp & 0xffff;
-
- return -1;
-}
-
-/**
- * keystone2_mdio_write - write to a PHY register via MDIO interface.
- * Blocks until operation is complete.
- */
-static int keystone2_mdio_write(struct mii_dev *bus,
- int addr, int devad, int reg, u16 val)
-{
- struct mdio_regs *adap_mdio = bus->priv;
-
- while (readl(&adap_mdio->useraccess0) & MDIO_USERACCESS0_GO)
- ;
-
- writel(MDIO_USERACCESS0_GO | MDIO_USERACCESS0_WRITE_WRITE |
- ((reg & 0x1f) << 21) | ((addr & 0x1f) << 16) |
- (val & 0xffff), &adap_mdio->useraccess0);
-
- /* Wait for command to complete */
- while (readl(&adap_mdio->useraccess0) & MDIO_USERACCESS0_GO)
- ;
-
- return 0;
-}
-
-#ifndef CONFIG_DM_ETH
-static void __attribute__((unused))
- keystone2_eth_gigabit_enable(struct eth_device *dev)
-{
- u_int16_t data;
- struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv;
-
- if (sys_has_mdio) {
- data = keystone2_mdio_read(mdio_bus, eth_priv->phy_addr,
- MDIO_DEVAD_NONE, 0);
- /* speed selection MSB */
- if (!(data & (1 << 6)))
- return;
- }
-
- /*
- * Check if link detected is giga-bit
- * If Gigabit mode detected, enable gigbit in MAC
- */
- writel(readl(DEVICE_EMACSL_BASE(eth_priv->slave_port - 1) +
- CPGMACSL_REG_CTL) |
- EMAC_MACCONTROL_GIGFORCE | EMAC_MACCONTROL_GIGABIT_ENABLE,
- DEVICE_EMACSL_BASE(eth_priv->slave_port - 1) + CPGMACSL_REG_CTL);
-}
-#else
-static void __attribute__((unused))
- keystone2_eth_gigabit_enable(struct udevice *dev)
-{
- struct ks2_eth_priv *priv = dev_get_priv(dev);
- u_int16_t data;
-
- if (priv->has_mdio) {
- data = keystone2_mdio_read(priv->mdio_bus, priv->phy_addr,
- MDIO_DEVAD_NONE, 0);
- /* speed selection MSB */
- if (!(data & (1 << 6)))
- return;
- }
-
- /*
- * Check if link detected is giga-bit
- * If Gigabit mode detected, enable gigbit in MAC
- */
- writel(readl(DEVICE_EMACSL_BASE(priv->slave_port - 1) +
- CPGMACSL_REG_CTL) |
- EMAC_MACCONTROL_GIGFORCE | EMAC_MACCONTROL_GIGABIT_ENABLE,
- DEVICE_EMACSL_BASE(priv->slave_port - 1) + CPGMACSL_REG_CTL);
-}
-#endif
-
-#ifdef CONFIG_SOC_K2G
-int keystone_rgmii_config(struct phy_device *phy_dev)
-{
- unsigned int i, status;
-
- i = 0;
- do {
- if (i > SGMII_ANEG_TIMEOUT) {
- puts(" TIMEOUT !\n");
- phy_dev->link = 0;
- return 0;
- }
-
- if (ctrlc()) {
- puts("user interrupt!\n");
- phy_dev->link = 0;
- return -EINTR;
- }
-
- if ((i++ % 500) == 0)
- printf(".");
-
- udelay(1000); /* 1 ms */
- status = readl(RGMII_STATUS_REG);
- } while (!(status & RGMII_REG_STATUS_LINK));
-
- puts(" done\n");
-
- return 0;
-}
-#else
-int keystone_sgmii_config(struct phy_device *phy_dev, int port, int interface)
-{
- unsigned int i, status, mask;
- unsigned int mr_adv_ability, control;
-
- switch (interface) {
- case SGMII_LINK_MAC_MAC_AUTONEG:
- mr_adv_ability = (SGMII_REG_MR_ADV_ENABLE |
- SGMII_REG_MR_ADV_LINK |
- SGMII_REG_MR_ADV_FULL_DUPLEX |
- SGMII_REG_MR_ADV_GIG_MODE);
- control = (SGMII_REG_CONTROL_MASTER |
- SGMII_REG_CONTROL_AUTONEG);
-
- break;
- case SGMII_LINK_MAC_PHY:
- case SGMII_LINK_MAC_PHY_FORCED:
- mr_adv_ability = SGMII_REG_MR_ADV_ENABLE;
- control = SGMII_REG_CONTROL_AUTONEG;
-
- break;
- case SGMII_LINK_MAC_MAC_FORCED:
- mr_adv_ability = (SGMII_REG_MR_ADV_ENABLE |
- SGMII_REG_MR_ADV_LINK |
- SGMII_REG_MR_ADV_FULL_DUPLEX |
- SGMII_REG_MR_ADV_GIG_MODE);
- control = SGMII_REG_CONTROL_MASTER;
-
- break;
- case SGMII_LINK_MAC_FIBER:
- mr_adv_ability = 0x20;
- control = SGMII_REG_CONTROL_AUTONEG;
-
- break;
- default:
- mr_adv_ability = SGMII_REG_MR_ADV_ENABLE;
- control = SGMII_REG_CONTROL_AUTONEG;
- }
-
- __raw_writel(0, SGMII_CTL_REG(port));
-
- /*
- * Wait for the SerDes pll to lock,
- * but don't trap if lock is never read
- */
- for (i = 0; i < 1000; i++) {
- udelay(2000);
- status = __raw_readl(SGMII_STATUS_REG(port));
- if ((status & SGMII_REG_STATUS_LOCK) != 0)
- break;
- }
-
- __raw_writel(mr_adv_ability, SGMII_MRADV_REG(port));
- __raw_writel(control, SGMII_CTL_REG(port));
-
-
- mask = SGMII_REG_STATUS_LINK;
-
- if (control & SGMII_REG_CONTROL_AUTONEG)
- mask |= SGMII_REG_STATUS_AUTONEG;
-
- status = __raw_readl(SGMII_STATUS_REG(port));
- if ((status & mask) == mask)
- return 0;
-
- printf("\n%s Waiting for SGMII auto negotiation to complete",
- phy_dev->dev->name);
- while ((status & mask) != mask) {
- /*
- * Timeout reached ?
- */
- if (i > SGMII_ANEG_TIMEOUT) {
- puts(" TIMEOUT !\n");
- phy_dev->link = 0;
- return 0;
- }
-
- if (ctrlc()) {
- puts("user interrupt!\n");
- phy_dev->link = 0;
- return -EINTR;
- }
-
- if ((i++ % 500) == 0)
- printf(".");
-
- udelay(1000); /* 1 ms */
- status = __raw_readl(SGMII_STATUS_REG(port));
- }
- puts(" done\n");
-
- return 0;
-}
-#endif
-
-int mac_sl_reset(u32 port)
-{
- u32 i, v;
-
- if (port >= DEVICE_N_GMACSL_PORTS)
- return GMACSL_RET_INVALID_PORT;
-
- /* Set the soft reset bit */
- writel(CPGMAC_REG_RESET_VAL_RESET,
- DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RESET);
-
- /* Wait for the bit to clear */
- for (i = 0; i < DEVICE_EMACSL_RESET_POLL_COUNT; i++) {
- v = readl(DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RESET);
- if ((v & CPGMAC_REG_RESET_VAL_RESET_MASK) !=
- CPGMAC_REG_RESET_VAL_RESET)
- return GMACSL_RET_OK;
- }
-
- /* Timeout on the reset */
- return GMACSL_RET_WARN_RESET_INCOMPLETE;
-}
-
-int mac_sl_config(u_int16_t port, struct mac_sl_cfg *cfg)
-{
- u32 v, i;
- int ret = GMACSL_RET_OK;
-
- if (port >= DEVICE_N_GMACSL_PORTS)
- return GMACSL_RET_INVALID_PORT;
-
- if (cfg->max_rx_len > CPGMAC_REG_MAXLEN_LEN) {
- cfg->max_rx_len = CPGMAC_REG_MAXLEN_LEN;
- ret = GMACSL_RET_WARN_MAXLEN_TOO_BIG;
- }
-
- /* Must wait if the device is undergoing reset */
- for (i = 0; i < DEVICE_EMACSL_RESET_POLL_COUNT; i++) {
- v = readl(DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RESET);
- if ((v & CPGMAC_REG_RESET_VAL_RESET_MASK) !=
- CPGMAC_REG_RESET_VAL_RESET)
- break;
- }
-
- if (i == DEVICE_EMACSL_RESET_POLL_COUNT)
- return GMACSL_RET_CONFIG_FAIL_RESET_ACTIVE;
-
- writel(cfg->max_rx_len, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_MAXLEN);
- writel(cfg->ctl, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_CTL);
-
-#ifndef CONFIG_SOC_K2HK
- /* Map RX packet flow priority to 0 */
- writel(0, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RX_PRI_MAP);
-#endif
-
- return ret;
-}
-
-int ethss_config(u32 ctl, u32 max_pkt_size)
-{
- u32 i;
-
- /* Max length register */
- writel(max_pkt_size, DEVICE_CPSW_BASE + CPSW_REG_MAXLEN);
-
- /* Control register */
- writel(ctl, DEVICE_CPSW_BASE + CPSW_REG_CTL);
-
- /* All statistics enabled by default */
- writel(CPSW_REG_VAL_STAT_ENABLE_ALL,
- DEVICE_CPSW_BASE + CPSW_REG_STAT_PORT_EN);
-
- /* Reset and enable the ALE */
- writel(CPSW_REG_VAL_ALE_CTL_RESET_AND_ENABLE |
- CPSW_REG_VAL_ALE_CTL_BYPASS,
- DEVICE_CPSW_BASE + CPSW_REG_ALE_CONTROL);
-
- /* All ports put into forward mode */
- for (i = 0; i < DEVICE_CPSW_NUM_PORTS; i++)
- writel(CPSW_REG_VAL_PORTCTL_FORWARD_MODE,
- DEVICE_CPSW_BASE + CPSW_REG_ALE_PORTCTL(i));
-
- return 0;
-}
-
-int ethss_start(void)
-{
- int i;
- struct mac_sl_cfg cfg;
-
- cfg.max_rx_len = MAX_SIZE_STREAM_BUFFER;
- cfg.ctl = GMACSL_ENABLE | GMACSL_RX_ENABLE_EXT_CTL;
-
- for (i = 0; i < DEVICE_N_GMACSL_PORTS; i++) {
- mac_sl_reset(i);
- mac_sl_config(i, &cfg);
- }
-
- return 0;
-}
-
-int ethss_stop(void)
-{
- int i;
-
- for (i = 0; i < DEVICE_N_GMACSL_PORTS; i++)
- mac_sl_reset(i);
-
- return 0;
-}
-
-struct ks2_serdes ks2_serdes_sgmii_156p25mhz = {
- .clk = SERDES_CLOCK_156P25M,
- .rate = SERDES_RATE_5G,
- .rate_mode = SERDES_QUARTER_RATE,
- .intf = SERDES_PHY_SGMII,
- .loopback = 0,
-};
-
-#ifndef CONFIG_SOC_K2G
-static void keystone2_net_serdes_setup(void)
-{
- ks2_serdes_init(CONFIG_KSNET_SERDES_SGMII_BASE,
- &ks2_serdes_sgmii_156p25mhz,
- CONFIG_KSNET_SERDES_LANES_PER_SGMII);
-
-#if defined(CONFIG_SOC_K2E) || defined(CONFIG_SOC_K2L)
- ks2_serdes_init(CONFIG_KSNET_SERDES_SGMII2_BASE,
- &ks2_serdes_sgmii_156p25mhz,
- CONFIG_KSNET_SERDES_LANES_PER_SGMII);
-#endif
-
- /* wait till setup */
- udelay(5000);
-}
-#endif
-
-#ifndef CONFIG_DM_ETH
-
-int keystone2_eth_read_mac_addr(struct eth_device *dev)
-{
- struct eth_priv_t *eth_priv;
- u32 maca = 0;
- u32 macb = 0;
-
- eth_priv = (struct eth_priv_t *)dev->priv;
-
- /* Read the e-fuse mac address */
- if (eth_priv->slave_port == 1) {
- maca = __raw_readl(MAC_ID_BASE_ADDR);
- macb = __raw_readl(MAC_ID_BASE_ADDR + 4);
- }
-
- dev->enetaddr[0] = (macb >> 8) & 0xff;
- dev->enetaddr[1] = (macb >> 0) & 0xff;
- dev->enetaddr[2] = (maca >> 24) & 0xff;
- dev->enetaddr[3] = (maca >> 16) & 0xff;
- dev->enetaddr[4] = (maca >> 8) & 0xff;
- dev->enetaddr[5] = (maca >> 0) & 0xff;
-
- return 0;
-}
-
-int32_t cpmac_drv_send(u32 *buffer, int num_bytes, int slave_port_num)
-{
- if (num_bytes < EMAC_MIN_ETHERNET_PKT_SIZE)
- num_bytes = EMAC_MIN_ETHERNET_PKT_SIZE;
-
- return ksnav_send(&netcp_pktdma, buffer,
- num_bytes, (slave_port_num) << 16);
-}
-
-/* Eth device open */
-static int keystone2_eth_open(struct eth_device *dev, bd_t *bis)
-{
- struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv;
- struct phy_device *phy_dev = eth_priv->phy_dev;
-
- debug("+ emac_open\n");
-
- net_rx_buffs.rx_flow = eth_priv->rx_flow;
-
- sys_has_mdio =
- (eth_priv->sgmii_link_type == SGMII_LINK_MAC_PHY) ? 1 : 0;
-
- if (sys_has_mdio)
- keystone2_mdio_reset(mdio_bus);
-
-#ifdef CONFIG_SOC_K2G
- keystone_rgmii_config(phy_dev);
-#else
- keystone_sgmii_config(phy_dev, eth_priv->slave_port - 1,
- eth_priv->sgmii_link_type);
-#endif
-
- udelay(10000);
-
- /* On chip switch configuration */
- ethss_config(target_get_switch_ctl(), SWITCH_MAX_PKT_SIZE);
-
- /* TODO: add error handling code */
- if (qm_init()) {
- printf("ERROR: qm_init()\n");
- return -1;
- }
- if (ksnav_init(&netcp_pktdma, &net_rx_buffs)) {
- qm_close();
- printf("ERROR: netcp_init()\n");
- return -1;
- }
-
- /*
- * Streaming switch configuration. If not present this
- * statement is defined to void in target.h.
- * If present this is usually defined to a series of register writes
- */
- hw_config_streaming_switch();
-
- if (sys_has_mdio) {
- keystone2_mdio_reset(mdio_bus);
-
- phy_startup(phy_dev);
- if (phy_dev->link == 0) {
- ksnav_close(&netcp_pktdma);
- qm_close();
- return -1;
- }
- }
-
- emac_gigabit_enable(dev);
-
- ethss_start();
-
- debug("- emac_open\n");
-
- emac_open = 1;
-
- return 0;
-}
-
-/* Eth device close */
-void keystone2_eth_close(struct eth_device *dev)
-{
- struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv;
- struct phy_device *phy_dev = eth_priv->phy_dev;
-
- debug("+ emac_close\n");
-
- if (!emac_open)
- return;
-
- ethss_stop();
-
- ksnav_close(&netcp_pktdma);
- qm_close();
- phy_shutdown(phy_dev);
-
- emac_open = 0;
-
- debug("- emac_close\n");
-}
-
-/*
- * This function sends a single packet on the network and returns
- * positive number (number of bytes transmitted) or negative for error
- */
-static int keystone2_eth_send_packet(struct eth_device *dev,
- void *packet, int length)
-{
- int ret_status = -1;
- struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv;
- struct phy_device *phy_dev = eth_priv->phy_dev;
-
- genphy_update_link(phy_dev);
- if (phy_dev->link == 0)
- return -1;
-
- if (cpmac_drv_send((u32 *)packet, length, eth_priv->slave_port) != 0)
- return ret_status;
-
- return length;
-}
-
-/*
- * This function handles receipt of a packet from the network
- */
-static int keystone2_eth_rcv_packet(struct eth_device *dev)
-{
- void *hd;
- int pkt_size;
- u32 *pkt;
-
- hd = ksnav_recv(&netcp_pktdma, &pkt, &pkt_size);
- if (hd == NULL)
- return 0;
-
- net_process_received_packet((uchar *)pkt, pkt_size);
-
- ksnav_release_rxhd(&netcp_pktdma, hd);
-
- return pkt_size;
-}
-
-#ifdef CONFIG_MCAST_TFTP
-static int keystone2_eth_bcast_addr(struct eth_device *dev, u32 ip, u8 set)
-{
- return 0;
-}
-#endif
-
-/*
- * This function initializes the EMAC hardware.
- */
-int keystone2_emac_initialize(struct eth_priv_t *eth_priv)
-{
- int res;
- struct eth_device *dev;
- struct phy_device *phy_dev;
- struct mdio_regs *adap_mdio = (struct mdio_regs *)EMAC_MDIO_BASE_ADDR;
-
- dev = malloc(sizeof(struct eth_device));
- if (dev == NULL)
- return -1;
-
- memset(dev, 0, sizeof(struct eth_device));
-
- strcpy(dev->name, eth_priv->int_name);
- dev->priv = eth_priv;
-
- keystone2_eth_read_mac_addr(dev);
-
- dev->iobase = 0;
- dev->init = keystone2_eth_open;
- dev->halt = keystone2_eth_close;
- dev->send = keystone2_eth_send_packet;
- dev->recv = keystone2_eth_rcv_packet;
-#ifdef CONFIG_MCAST_TFTP
- dev->mcast = keystone2_eth_bcast_addr;
-#endif
-
- eth_register(dev);
-
- /* Register MDIO bus if it's not registered yet */
- if (!mdio_bus) {
- mdio_bus = mdio_alloc();
- mdio_bus->read = keystone2_mdio_read;
- mdio_bus->write = keystone2_mdio_write;
- mdio_bus->reset = keystone2_mdio_reset;
- mdio_bus->priv = (void *)EMAC_MDIO_BASE_ADDR;
- strcpy(mdio_bus->name, "ethernet-mdio");
-
- res = mdio_register(mdio_bus);
- if (res)
- return res;
- }
-
-#ifndef CONFIG_SOC_K2G
- keystone2_net_serdes_setup();
-#endif
-
- /* Create phy device and bind it with driver */
-#ifdef CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE
- phy_dev = phy_connect(mdio_bus, eth_priv->phy_addr,
- dev, eth_priv->phy_if);
- phy_config(phy_dev);
-#else
- phy_dev = phy_find_by_mask(mdio_bus, 1 << eth_priv->phy_addr,
- eth_priv->phy_if);
- phy_dev->dev = dev;
-#endif
- eth_priv->phy_dev = phy_dev;
-
- return 0;
-}
-
-#else
-
-static int ks2_eth_start(struct udevice *dev)
-{
- struct ks2_eth_priv *priv = dev_get_priv(dev);
-
-#ifdef CONFIG_SOC_K2G
- keystone_rgmii_config(priv->phydev);
-#else
- keystone_sgmii_config(priv->phydev, priv->slave_port - 1,
- priv->sgmii_link_type);
-#endif
-
- udelay(10000);
-
- /* On chip switch configuration */
- ethss_config(target_get_switch_ctl(), SWITCH_MAX_PKT_SIZE);
-
- qm_init();
-
- if (ksnav_init(priv->netcp_pktdma, &priv->net_rx_buffs)) {
- pr_err("ksnav_init failed\n");
- goto err_knav_init;
- }
-
- /*
- * Streaming switch configuration. If not present this
- * statement is defined to void in target.h.
- * If present this is usually defined to a series of register writes
- */
- hw_config_streaming_switch();
-
- if (priv->has_mdio) {
- keystone2_mdio_reset(priv->mdio_bus);
-
- phy_startup(priv->phydev);
- if (priv->phydev->link == 0) {
- pr_err("phy startup failed\n");
- goto err_phy_start;
- }
- }
-
- emac_gigabit_enable(dev);
-
- ethss_start();
-
- priv->emac_open = true;
-
- return 0;
-
-err_phy_start:
- ksnav_close(priv->netcp_pktdma);
-err_knav_init:
- qm_close();
-
- return -EFAULT;
-}
-
-static int ks2_eth_send(struct udevice *dev, void *packet, int length)
-{
- struct ks2_eth_priv *priv = dev_get_priv(dev);
-
- genphy_update_link(priv->phydev);
- if (priv->phydev->link == 0)
- return -1;
-
- if (length < EMAC_MIN_ETHERNET_PKT_SIZE)
- length = EMAC_MIN_ETHERNET_PKT_SIZE;
-
- return ksnav_send(priv->netcp_pktdma, (u32 *)packet,
- length, (priv->slave_port) << 16);
-}
-
-static int ks2_eth_recv(struct udevice *dev, int flags, uchar **packetp)
-{
- struct ks2_eth_priv *priv = dev_get_priv(dev);
- int pkt_size;
- u32 *pkt = NULL;
-
- priv->hd = ksnav_recv(priv->netcp_pktdma, &pkt, &pkt_size);
- if (priv->hd == NULL)
- return -EAGAIN;
-
- *packetp = (uchar *)pkt;
-
- return pkt_size;
-}
-
-static int ks2_eth_free_pkt(struct udevice *dev, uchar *packet,
- int length)
-{
- struct ks2_eth_priv *priv = dev_get_priv(dev);
-
- ksnav_release_rxhd(priv->netcp_pktdma, priv->hd);
-
- return 0;
-}
-
-static void ks2_eth_stop(struct udevice *dev)
-{
- struct ks2_eth_priv *priv = dev_get_priv(dev);
-
- if (!priv->emac_open)
- return;
- ethss_stop();
-
- ksnav_close(priv->netcp_pktdma);
- qm_close();
- phy_shutdown(priv->phydev);
- priv->emac_open = false;
-}
-
-int ks2_eth_read_rom_hwaddr(struct udevice *dev)
-{
- struct ks2_eth_priv *priv = dev_get_priv(dev);
- struct eth_pdata *pdata = dev_get_platdata(dev);
- u32 maca = 0;
- u32 macb = 0;
-
- /* Read the e-fuse mac address */
- if (priv->slave_port == 1) {
- maca = __raw_readl(MAC_ID_BASE_ADDR);
- macb = __raw_readl(MAC_ID_BASE_ADDR + 4);
- }
-
- pdata->enetaddr[0] = (macb >> 8) & 0xff;
- pdata->enetaddr[1] = (macb >> 0) & 0xff;
- pdata->enetaddr[2] = (maca >> 24) & 0xff;
- pdata->enetaddr[3] = (maca >> 16) & 0xff;
- pdata->enetaddr[4] = (maca >> 8) & 0xff;
- pdata->enetaddr[5] = (maca >> 0) & 0xff;
-
- return 0;
-}
-
-int ks2_eth_write_hwaddr(struct udevice *dev)
-{
- struct ks2_eth_priv *priv = dev_get_priv(dev);
- struct eth_pdata *pdata = dev_get_platdata(dev);
-
- writel(mac_hi(pdata->enetaddr),
- DEVICE_EMACSW_BASE(pdata->iobase, priv->slave_port - 1) +
- CPGMACSL_REG_SA_HI);
- writel(mac_lo(pdata->enetaddr),
- DEVICE_EMACSW_BASE(pdata->iobase, priv->slave_port - 1) +
- CPGMACSL_REG_SA_LO);
-
- return 0;
-}
-
-static int ks2_eth_probe(struct udevice *dev)
-{
- struct ks2_eth_priv *priv = dev_get_priv(dev);
- struct mii_dev *mdio_bus;
- int ret;
-
- priv->dev = dev;
-
- /* These clock enables has to be moved to common location */
- if (cpu_is_k2g())
- writel(KS2_ETHERNET_RGMII, KS2_ETHERNET_CFG);
-
- /* By default, select PA PLL clock as PA clock source */
-#ifndef CONFIG_SOC_K2G
- if (psc_enable_module(KS2_LPSC_PA))
- return -EACCES;
-#endif
- if (psc_enable_module(KS2_LPSC_CPGMAC))
- return -EACCES;
- if (psc_enable_module(KS2_LPSC_CRYPTO))
- return -EACCES;
-
- if (cpu_is_k2e() || cpu_is_k2l())
- pll_pa_clk_sel();
-
-
- priv->net_rx_buffs.buff_ptr = rx_buffs;
- priv->net_rx_buffs.num_buffs = RX_BUFF_NUMS;
- priv->net_rx_buffs.buff_len = RX_BUFF_LEN;
-
- if (priv->slave_port == 1) {
- /*
- * Register MDIO bus for slave 0 only, other slave have
- * to re-use the same
- */
- mdio_bus = mdio_alloc();
- if (!mdio_bus) {
- pr_err("MDIO alloc failed\n");
- return -ENOMEM;
- }
- priv->mdio_bus = mdio_bus;
- mdio_bus->read = keystone2_mdio_read;
- mdio_bus->write = keystone2_mdio_write;
- mdio_bus->reset = keystone2_mdio_reset;
- mdio_bus->priv = priv->mdio_base;
- sprintf(mdio_bus->name, "ethernet-mdio");
-
- ret = mdio_register(mdio_bus);
- if (ret) {
- pr_err("MDIO bus register failed\n");
- return ret;
- }
- } else {
- /* Get the MDIO bus from slave 0 device */
- struct ks2_eth_priv *parent_priv;
-
- parent_priv = dev_get_priv(dev->parent);
- priv->mdio_bus = parent_priv->mdio_bus;
- }
-
-#ifndef CONFIG_SOC_K2G
- keystone2_net_serdes_setup();
-#endif
-
- priv->netcp_pktdma = &netcp_pktdma;
-
- if (priv->has_mdio) {
- priv->phydev = phy_connect(priv->mdio_bus, priv->phy_addr,
- dev, priv->phy_if);
- phy_config(priv->phydev);
- }
-
- return 0;
-}
-
-int ks2_eth_remove(struct udevice *dev)
-{
- struct ks2_eth_priv *priv = dev_get_priv(dev);
-
- free(priv->phydev);
- mdio_unregister(priv->mdio_bus);
- mdio_free(priv->mdio_bus);
-
- return 0;
-}
-
-static const struct eth_ops ks2_eth_ops = {
- .start = ks2_eth_start,
- .send = ks2_eth_send,
- .recv = ks2_eth_recv,
- .free_pkt = ks2_eth_free_pkt,
- .stop = ks2_eth_stop,
- .read_rom_hwaddr = ks2_eth_read_rom_hwaddr,
- .write_hwaddr = ks2_eth_write_hwaddr,
-};
-
-static int ks2_eth_bind_slaves(struct udevice *dev, int gbe, int *gbe_0)
-{
- const void *fdt = gd->fdt_blob;
- struct udevice *sl_dev;
- int interfaces;
- int sec_slave;
- int slave;
- int ret;
- char *slave_name;
-
- interfaces = fdt_subnode_offset(fdt, gbe, "interfaces");
- fdt_for_each_subnode(slave, fdt, interfaces) {
- int slave_no;
-
- slave_no = fdtdec_get_int(fdt, slave, "slave-port", -ENOENT);
- if (slave_no == -ENOENT)
- continue;
-
- if (slave_no == 0) {
- /* This is the current eth device */
- *gbe_0 = slave;
- } else {
- /* Slave devices to be registered */
- slave_name = malloc(20);
- snprintf(slave_name, 20, "netcp@slave-%d", slave_no);
- ret = device_bind_driver_to_node(dev, "eth_ks2_sl",
- slave_name, offset_to_ofnode(slave),
- &sl_dev);
- if (ret) {
- pr_err("ks2_net - not able to bind slave interfaces\n");
- return ret;
- }
- }
- }
-
- sec_slave = fdt_subnode_offset(fdt, gbe, "secondary-slave-ports");
- fdt_for_each_subnode(slave, fdt, sec_slave) {
- int slave_no;
-
- slave_no = fdtdec_get_int(fdt, slave, "slave-port", -ENOENT);
- if (slave_no == -ENOENT)
- continue;
-
- /* Slave devices to be registered */
- slave_name = malloc(20);
- snprintf(slave_name, 20, "netcp@slave-%d", slave_no);
- ret = device_bind_driver_to_node(dev, "eth_ks2_sl", slave_name,
- offset_to_ofnode(slave), &sl_dev);
- if (ret) {
- pr_err("ks2_net - not able to bind slave interfaces\n");
- return ret;
- }
- }
-
- return 0;
-}
-
-static int ks2_eth_parse_slave_interface(int netcp, int slave,
- struct ks2_eth_priv *priv,
- struct eth_pdata *pdata)
-{
- const void *fdt = gd->fdt_blob;
- int mdio;
- int phy;
- int dma_count;
- u32 dma_channel[8];
-
- priv->slave_port = fdtdec_get_int(fdt, slave, "slave-port", -1);
- priv->net_rx_buffs.rx_flow = priv->slave_port * 8;
-
- /* U-Boot slave port number starts with 1 instead of 0 */
- priv->slave_port += 1;
-
- dma_count = fdtdec_get_int_array_count(fdt, netcp,
- "ti,navigator-dmas",
- dma_channel, 8);
-
- if (dma_count > (2 * priv->slave_port)) {
- int dma_idx;
-
- dma_idx = priv->slave_port * 2 - 1;
- priv->net_rx_buffs.rx_flow = dma_channel[dma_idx];
- }
-
- priv->link_type = fdtdec_get_int(fdt, slave, "link-interface", -1);
-
- phy = fdtdec_lookup_phandle(fdt, slave, "phy-handle");
- if (phy >= 0) {
- priv->phy_addr = fdtdec_get_int(fdt, phy, "reg", -1);
-
- mdio = fdt_parent_offset(fdt, phy);
- if (mdio < 0) {
- pr_err("mdio dt not found\n");
- return -ENODEV;
- }
- priv->mdio_base = (void *)fdtdec_get_addr(fdt, mdio, "reg");
- }
-
- if (priv->link_type == LINK_TYPE_SGMII_MAC_TO_PHY_MODE) {
- priv->phy_if = PHY_INTERFACE_MODE_SGMII;
- pdata->phy_interface = priv->phy_if;
- priv->sgmii_link_type = SGMII_LINK_MAC_PHY;
- priv->has_mdio = true;
- } else if (priv->link_type == LINK_TYPE_RGMII_LINK_MAC_PHY) {
- priv->phy_if = PHY_INTERFACE_MODE_RGMII;
- pdata->phy_interface = priv->phy_if;
- priv->has_mdio = true;
- }
-
- return 0;
-}
-
-static int ks2_sl_eth_ofdata_to_platdata(struct udevice *dev)
-{
- struct ks2_eth_priv *priv = dev_get_priv(dev);
- struct eth_pdata *pdata = dev_get_platdata(dev);
- const void *fdt = gd->fdt_blob;
- int slave = dev_of_offset(dev);
- int interfaces;
- int gbe;
- int netcp_devices;
- int netcp;
-
- interfaces = fdt_parent_offset(fdt, slave);
- gbe = fdt_parent_offset(fdt, interfaces);
- netcp_devices = fdt_parent_offset(fdt, gbe);
- netcp = fdt_parent_offset(fdt, netcp_devices);
-
- ks2_eth_parse_slave_interface(netcp, slave, priv, pdata);
-
- pdata->iobase = fdtdec_get_addr(fdt, netcp, "reg");
-
- return 0;
-}
-
-static int ks2_eth_ofdata_to_platdata(struct udevice *dev)
-{
- struct ks2_eth_priv *priv = dev_get_priv(dev);
- struct eth_pdata *pdata = dev_get_platdata(dev);
- const void *fdt = gd->fdt_blob;
- int gbe_0 = -ENODEV;
- int netcp_devices;
- int gbe;
-
- netcp_devices = fdt_subnode_offset(fdt, dev_of_offset(dev),
- "netcp-devices");
- gbe = fdt_subnode_offset(fdt, netcp_devices, "gbe");
-
- ks2_eth_bind_slaves(dev, gbe, &gbe_0);
-
- ks2_eth_parse_slave_interface(dev_of_offset(dev), gbe_0, priv, pdata);
-
- pdata->iobase = devfdt_get_addr(dev);
-
- return 0;
-}
-
-static const struct udevice_id ks2_eth_ids[] = {
- { .compatible = "ti,netcp-1.0" },
- { }
-};
-
-U_BOOT_DRIVER(eth_ks2_slave) = {
- .name = "eth_ks2_sl",
- .id = UCLASS_ETH,
- .ofdata_to_platdata = ks2_sl_eth_ofdata_to_platdata,
- .probe = ks2_eth_probe,
- .remove = ks2_eth_remove,
- .ops = &ks2_eth_ops,
- .priv_auto_alloc_size = sizeof(struct ks2_eth_priv),
- .platdata_auto_alloc_size = sizeof(struct eth_pdata),
- .flags = DM_FLAG_ALLOC_PRIV_DMA,
-};
-
-U_BOOT_DRIVER(eth_ks2) = {
- .name = "eth_ks2",
- .id = UCLASS_ETH,
- .of_match = ks2_eth_ids,
- .ofdata_to_platdata = ks2_eth_ofdata_to_platdata,
- .probe = ks2_eth_probe,
- .remove = ks2_eth_remove,
- .ops = &ks2_eth_ops,
- .priv_auto_alloc_size = sizeof(struct ks2_eth_priv),
- .platdata_auto_alloc_size = sizeof(struct eth_pdata),
- .flags = DM_FLAG_ALLOC_PRIV_DMA,
-};
-#endif
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * MediaTek ethernet IP driver for U-Boot
+ *
+ * Copyright (C) 2018 Stefan Roese <sr@denx.de>
+ *
+ * This code is mostly based on the code extracted from this MediaTek
+ * github repository:
+ *
+ * https://github.com/MediaTek-Labs/linkit-smart-uboot.git
+ *
+ * I was not able to find a specific license or other developers
+ * copyrights here, so I can't add them here.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <malloc.h>
+#include <miiphy.h>
+#include <net.h>
+#include <regmap.h>
+#include <syscon.h>
+#include <wait_bit.h>
+#include <asm/io.h>
+#include <linux/bitfield.h>
+#include <linux/err.h>
+
+/* System controller register */
+#define MT7628_RSTCTRL_REG 0x34
+#define RSTCTRL_EPHY_RST BIT(24)
+
+#define MT7628_AGPIO_CFG_REG 0x3c
+#define MT7628_EPHY_GPIO_AIO_EN GENMASK(20, 17)
+#define MT7628_EPHY_P0_DIS BIT(16)
+
+#define MT7628_GPIO2_MODE_REG 0x64
+
+/* Ethernet frame engine register */
+#define PDMA_RELATED 0x0800
+
+#define TX_BASE_PTR0 (PDMA_RELATED + 0x000)
+#define TX_MAX_CNT0 (PDMA_RELATED + 0x004)
+#define TX_CTX_IDX0 (PDMA_RELATED + 0x008)
+#define TX_DTX_IDX0 (PDMA_RELATED + 0x00c)
+
+#define RX_BASE_PTR0 (PDMA_RELATED + 0x100)
+#define RX_MAX_CNT0 (PDMA_RELATED + 0x104)
+#define RX_CALC_IDX0 (PDMA_RELATED + 0x108)
+
+#define PDMA_GLO_CFG (PDMA_RELATED + 0x204)
+#define PDMA_RST_IDX (PDMA_RELATED + 0x208)
+#define DLY_INT_CFG (PDMA_RELATED + 0x20c)
+
+#define SDM_RELATED 0x0c00
+
+#define SDM_MAC_ADRL (SDM_RELATED + 0x0c) /* MAC address LSB */
+#define SDM_MAC_ADRH (SDM_RELATED + 0x10) /* MAC Address MSB */
+
+#define RST_DTX_IDX0 BIT(0)
+#define RST_DRX_IDX0 BIT(16)
+
+#define TX_DMA_EN BIT(0)
+#define TX_DMA_BUSY BIT(1)
+#define RX_DMA_EN BIT(2)
+#define RX_DMA_BUSY BIT(3)
+#define TX_WB_DDONE BIT(6)
+
+/* Ethernet switch register */
+#define MT7628_SWITCH_FCT0 0x0008
+#define MT7628_SWITCH_PFC1 0x0014
+#define MT7628_SWITCH_FPA 0x0084
+#define MT7628_SWITCH_SOCPC 0x008c
+#define MT7628_SWITCH_POC0 0x0090
+#define MT7628_SWITCH_POC2 0x0098
+#define MT7628_SWITCH_SGC 0x009c
+#define MT7628_SWITCH_PCR0 0x00c0
+#define PCR0_PHY_ADDR GENMASK(4, 0)
+#define PCR0_PHY_REG GENMASK(12, 8)
+#define PCR0_WT_PHY_CMD BIT(13)
+#define PCR0_RD_PHY_CMD BIT(14)
+#define PCR0_WT_DATA GENMASK(31, 16)
+
+#define MT7628_SWITCH_PCR1 0x00c4
+#define PCR1_WT_DONE BIT(0)
+#define PCR1_RD_RDY BIT(1)
+#define PCR1_RD_DATA GENMASK(31, 16)
+
+#define MT7628_SWITCH_FPA1 0x00c8
+#define MT7628_SWITCH_FCT2 0x00cc
+#define MT7628_SWITCH_SGC2 0x00e4
+#define MT7628_SWITCH_BMU_CTRL 0x0110
+
+/* rxd2 */
+#define RX_DMA_DONE BIT(31)
+#define RX_DMA_LSO BIT(30)
+#define RX_DMA_PLEN0 GENMASK(29, 16)
+#define RX_DMA_TAG BIT(15)
+
+struct fe_rx_dma {
+ unsigned int rxd1;
+ unsigned int rxd2;
+ unsigned int rxd3;
+ unsigned int rxd4;
+} __packed __aligned(4);
+
+#define TX_DMA_PLEN0 GENMASK(29, 16)
+#define TX_DMA_LS1 BIT(14)
+#define TX_DMA_LS0 BIT(30)
+#define TX_DMA_DONE BIT(31)
+
+#define TX_DMA_INS_VLAN_MT7621 BIT(16)
+#define TX_DMA_INS_VLAN BIT(7)
+#define TX_DMA_INS_PPPOE BIT(12)
+#define TX_DMA_PN GENMASK(26, 24)
+
+struct fe_tx_dma {
+ unsigned int txd1;
+ unsigned int txd2;
+ unsigned int txd3;
+ unsigned int txd4;
+} __packed __aligned(4);
+
+#define NUM_RX_DESC 256
+#define NUM_TX_DESC 4
+
+#define PADDING_LENGTH 60
+
+#define MTK_QDMA_PAGE_SIZE 2048
+
+#define CONFIG_MDIO_TIMEOUT 100
+#define CONFIG_DMA_STOP_TIMEOUT 100
+#define CONFIG_TX_DMA_TIMEOUT 100
+
+#define LINK_DELAY_TIME 500 /* 500 ms */
+#define LINK_TIMEOUT 10000 /* 10 seconds */
+
+struct mt7628_eth_dev {
+ void __iomem *base; /* frame engine base address */
+ void __iomem *eth_sw_base; /* switch base address */
+ struct regmap *sysctrl_regmap; /* system-controller reg-map */
+
+ struct mii_dev *bus;
+
+ struct fe_tx_dma *tx_ring;
+ struct fe_rx_dma *rx_ring;
+
+ u8 *rx_buf[NUM_RX_DESC];
+
+ /* Point to the next RXD DMA wants to use in RXD Ring0 */
+ int rx_dma_idx;
+ /* Point to the next TXD in TXD Ring0 CPU wants to use */
+ int tx_dma_idx;
+};
+
+static int mdio_wait_read(struct mt7628_eth_dev *priv, u32 mask, bool mask_set)
+{
+ void __iomem *base = priv->eth_sw_base;
+ int ret;
+
+ ret = wait_for_bit_le32(base + MT7628_SWITCH_PCR1, mask, mask_set,
+ CONFIG_MDIO_TIMEOUT, false);
+ if (ret) {
+ printf("MDIO operation timeout!\n");
+ return -ETIMEDOUT;
+ }
+
+ return 0;
+}
+
+static int mii_mgr_read(struct mt7628_eth_dev *priv,
+ u32 phy_addr, u32 phy_register, u32 *read_data)
+{
+ void __iomem *base = priv->eth_sw_base;
+ u32 status = 0;
+ u32 ret;
+
+ *read_data = 0xffff;
+ /* Make sure previous read operation is complete */
+ ret = mdio_wait_read(priv, PCR1_RD_RDY, false);
+ if (ret)
+ return ret;
+
+ writel(PCR0_RD_PHY_CMD |
+ FIELD_PREP(PCR0_PHY_REG, phy_register) |
+ FIELD_PREP(PCR0_PHY_ADDR, phy_addr),
+ base + MT7628_SWITCH_PCR0);
+
+ /* Make sure previous read operation is complete */
+ ret = mdio_wait_read(priv, PCR1_RD_RDY, true);
+ if (ret)
+ return ret;
+
+ status = readl(base + MT7628_SWITCH_PCR1);
+ *read_data = FIELD_GET(PCR1_RD_DATA, status);
+
+ return 0;
+}
+
+static int mii_mgr_write(struct mt7628_eth_dev *priv,
+ u32 phy_addr, u32 phy_register, u32 write_data)
+{
+ void __iomem *base = priv->eth_sw_base;
+ u32 data;
+ int ret;
+
+ /* Make sure previous write operation is complete */
+ ret = mdio_wait_read(priv, PCR1_WT_DONE, false);
+ if (ret)
+ return ret;
+
+ data = FIELD_PREP(PCR0_WT_DATA, write_data) |
+ FIELD_PREP(PCR0_PHY_REG, phy_register) |
+ FIELD_PREP(PCR0_PHY_ADDR, phy_addr) |
+ PCR0_WT_PHY_CMD;
+ writel(data, base + MT7628_SWITCH_PCR0);
+
+ return mdio_wait_read(priv, PCR1_WT_DONE, true);
+}
+
+static int mt7628_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
+{
+ u32 val;
+ int ret;
+
+ ret = mii_mgr_read(bus->priv, addr, reg, &val);
+ if (ret)
+ return ret;
+
+ return val;
+}
+
+static int mt7628_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
+ u16 value)
+{
+ return mii_mgr_write(bus->priv, addr, reg, value);
+}
+
+static void mt7628_ephy_init(struct mt7628_eth_dev *priv)
+{
+ int i;
+
+ mii_mgr_write(priv, 0, 31, 0x2000); /* change G2 page */
+ mii_mgr_write(priv, 0, 26, 0x0000);
+
+ for (i = 0; i < 5; i++) {
+ mii_mgr_write(priv, i, 31, 0x8000); /* change L0 page */
+ mii_mgr_write(priv, i, 0, 0x3100);
+
+ /* EEE disable */
+ mii_mgr_write(priv, i, 30, 0xa000);
+ mii_mgr_write(priv, i, 31, 0xa000); /* change L2 page */
+ mii_mgr_write(priv, i, 16, 0x0606);
+ mii_mgr_write(priv, i, 23, 0x0f0e);
+ mii_mgr_write(priv, i, 24, 0x1610);
+ mii_mgr_write(priv, i, 30, 0x1f15);
+ mii_mgr_write(priv, i, 28, 0x6111);
+ }
+
+ /* 100Base AOI setting */
+ mii_mgr_write(priv, 0, 31, 0x5000); /* change G5 page */
+ mii_mgr_write(priv, 0, 19, 0x004a);
+ mii_mgr_write(priv, 0, 20, 0x015a);
+ mii_mgr_write(priv, 0, 21, 0x00ee);
+ mii_mgr_write(priv, 0, 22, 0x0033);
+ mii_mgr_write(priv, 0, 23, 0x020a);
+ mii_mgr_write(priv, 0, 24, 0x0000);
+ mii_mgr_write(priv, 0, 25, 0x024a);
+ mii_mgr_write(priv, 0, 26, 0x035a);
+ mii_mgr_write(priv, 0, 27, 0x02ee);
+ mii_mgr_write(priv, 0, 28, 0x0233);
+ mii_mgr_write(priv, 0, 29, 0x000a);
+ mii_mgr_write(priv, 0, 30, 0x0000);
+
+ /* Fix EPHY idle state abnormal behavior */
+ mii_mgr_write(priv, 0, 31, 0x4000); /* change G4 page */
+ mii_mgr_write(priv, 0, 29, 0x000d);
+ mii_mgr_write(priv, 0, 30, 0x0500);
+}
+
+static void rt305x_esw_init(struct mt7628_eth_dev *priv)
+{
+ void __iomem *base = priv->eth_sw_base;
+
+ /*
+ * FC_RLS_TH=200, FC_SET_TH=160
+ * DROP_RLS=120, DROP_SET_TH=80
+ */
+ writel(0xc8a07850, base + MT7628_SWITCH_FCT0);
+ writel(0x00000000, base + MT7628_SWITCH_SGC2);
+ writel(0x00405555, base + MT7628_SWITCH_PFC1);
+ writel(0x00007f7f, base + MT7628_SWITCH_POC0);
+ writel(0x00007f7f, base + MT7628_SWITCH_POC2); /* disable VLAN */
+ writel(0x0002500c, base + MT7628_SWITCH_FCT2);
+ /* hashing algorithm=XOR48, aging interval=300sec */
+ writel(0x0008a301, base + MT7628_SWITCH_SGC);
+ writel(0x02404040, base + MT7628_SWITCH_SOCPC);
+
+ /* Ext PHY Addr=0x1f */
+ writel(0x3f502b28, base + MT7628_SWITCH_FPA1);
+ writel(0x00000000, base + MT7628_SWITCH_FPA);
+ /* 1us cycle number=125 (FE's clock=125Mhz) */
+ writel(0x7d000000, base + MT7628_SWITCH_BMU_CTRL);
+
+ /* Configure analog GPIO setup */
+ regmap_update_bits(priv->sysctrl_regmap, MT7628_AGPIO_CFG_REG,
+ MT7628_EPHY_P0_DIS, MT7628_EPHY_GPIO_AIO_EN);
+
+ /* Reset PHY */
+ regmap_update_bits(priv->sysctrl_regmap, MT7628_RSTCTRL_REG,
+ 0, RSTCTRL_EPHY_RST);
+ regmap_update_bits(priv->sysctrl_regmap, MT7628_RSTCTRL_REG,
+ RSTCTRL_EPHY_RST, 0);
+ mdelay(10);
+
+ /* Set P0 EPHY LED mode */
+ regmap_update_bits(priv->sysctrl_regmap, MT7628_GPIO2_MODE_REG,
+ 0x0ffc0ffc, 0x05540554);
+ mdelay(10);
+
+ mt7628_ephy_init(priv);
+}
+
+static void eth_dma_start(struct mt7628_eth_dev *priv)
+{
+ void __iomem *base = priv->base;
+
+ setbits_le32(base + PDMA_GLO_CFG, TX_WB_DDONE | RX_DMA_EN | TX_DMA_EN);
+}
+
+static void eth_dma_stop(struct mt7628_eth_dev *priv)
+{
+ void __iomem *base = priv->base;
+ int ret;
+
+ clrbits_le32(base + PDMA_GLO_CFG, TX_WB_DDONE | RX_DMA_EN | TX_DMA_EN);
+
+ /* Wait for DMA to stop */
+ ret = wait_for_bit_le32(base + PDMA_GLO_CFG,
+ RX_DMA_BUSY | TX_DMA_BUSY, false,
+ CONFIG_DMA_STOP_TIMEOUT, false);
+ if (ret)
+ printf("DMA stop timeout error!\n");
+}
+
+static int mt7628_eth_write_hwaddr(struct udevice *dev)
+{
+ struct mt7628_eth_dev *priv = dev_get_priv(dev);
+ void __iomem *base = priv->base;
+ u8 *addr = ((struct eth_pdata *)dev_get_platdata(dev))->enetaddr;
+ u32 val;
+
+ /* Set MAC address. */
+ val = addr[0];
+ val = (val << 8) | addr[1];
+ writel(val, base + SDM_MAC_ADRH);
+
+ val = addr[2];
+ val = (val << 8) | addr[3];
+ val = (val << 8) | addr[4];
+ val = (val << 8) | addr[5];
+ writel(val, base + SDM_MAC_ADRL);
+
+ return 0;
+}
+
+static int mt7628_eth_send(struct udevice *dev, void *packet, int length)
+{
+ struct mt7628_eth_dev *priv = dev_get_priv(dev);
+ void __iomem *base = priv->base;
+ int ret;
+ int idx;
+ int i;
+
+ idx = priv->tx_dma_idx;
+
+ /* Pad message to a minimum length */
+ if (length < PADDING_LENGTH) {
+ char *p = (char *)packet;
+
+ for (i = 0; i < PADDING_LENGTH - length; i++)
+ p[length + i] = 0;
+ length = PADDING_LENGTH;
+ }
+
+ /* Check if buffer is ready for next TX DMA */
+ ret = wait_for_bit_le32(&priv->tx_ring[idx].txd2, TX_DMA_DONE, true,
+ CONFIG_TX_DMA_TIMEOUT, false);
+ if (ret) {
+ printf("TX: DMA still busy on buffer %d\n", idx);
+ return ret;
+ }
+
+ flush_dcache_range((u32)packet, (u32)packet + length);
+
+ priv->tx_ring[idx].txd1 = CPHYSADDR(packet);
+ priv->tx_ring[idx].txd2 &= ~TX_DMA_PLEN0;
+ priv->tx_ring[idx].txd2 |= FIELD_PREP(TX_DMA_PLEN0, length);
+ priv->tx_ring[idx].txd2 &= ~TX_DMA_DONE;
+
+ idx = (idx + 1) % NUM_TX_DESC;
+
+ /* Make sure the writes executed at this place */
+ wmb();
+ writel(idx, base + TX_CTX_IDX0);
+
+ priv->tx_dma_idx = idx;
+
+ return 0;
+}
+
+static int mt7628_eth_recv(struct udevice *dev, int flags, uchar **packetp)
+{
+ struct mt7628_eth_dev *priv = dev_get_priv(dev);
+ u32 rxd_info;
+ int length;
+ int idx;
+
+ idx = priv->rx_dma_idx;
+
+ rxd_info = priv->rx_ring[idx].rxd2;
+ if ((rxd_info & RX_DMA_DONE) == 0)
+ return -EAGAIN;
+
+ length = FIELD_GET(RX_DMA_PLEN0, priv->rx_ring[idx].rxd2);
+ if (length == 0 || length > MTK_QDMA_PAGE_SIZE) {
+ printf("%s: invalid length (%d bytes)\n", __func__, length);
+ return -EIO;
+ }
+
+ *packetp = priv->rx_buf[idx];
+ invalidate_dcache_range((u32)*packetp, (u32)*packetp + length);
+
+ priv->rx_ring[idx].rxd4 = 0;
+ priv->rx_ring[idx].rxd2 = RX_DMA_LSO;
+
+ /* Make sure the writes executed at this place */
+ wmb();
+
+ return length;
+}
+
+static int mt7628_eth_free_pkt(struct udevice *dev, uchar *packet, int length)
+{
+ struct mt7628_eth_dev *priv = dev_get_priv(dev);
+ void __iomem *base = priv->base;
+ int idx;
+
+ idx = priv->rx_dma_idx;
+
+ /* Move point to next RXD which wants to alloc */
+ writel(idx, base + RX_CALC_IDX0);
+
+ /* Update to Next packet point that was received */
+ idx = (idx + 1) % NUM_RX_DESC;
+
+ priv->rx_dma_idx = idx;
+
+ return 0;
+}
+
+static int phy_link_up(struct mt7628_eth_dev *priv)
+{
+ u32 val;
+
+ mii_mgr_read(priv, 0x00, MII_BMSR, &val);
+ return !!(val & BMSR_LSTATUS);
+}
+
+static int mt7628_eth_start(struct udevice *dev)
+{
+ struct mt7628_eth_dev *priv = dev_get_priv(dev);
+ void __iomem *base = priv->base;
+ uchar packet[MTK_QDMA_PAGE_SIZE];
+ uchar *packetp;
+ int i;
+
+ for (i = 0; i < NUM_RX_DESC; i++) {
+ memset((void *)&priv->rx_ring[i], 0, sizeof(priv->rx_ring[0]));
+ priv->rx_ring[i].rxd2 |= RX_DMA_LSO;
+ priv->rx_ring[i].rxd1 = CPHYSADDR(priv->rx_buf[i]);
+ }
+
+ for (i = 0; i < NUM_TX_DESC; i++) {
+ memset((void *)&priv->tx_ring[i], 0, sizeof(priv->tx_ring[0]));
+ priv->tx_ring[i].txd2 = TX_DMA_LS0 | TX_DMA_DONE;
+ priv->tx_ring[i].txd4 = FIELD_PREP(TX_DMA_PN, 1);
+ }
+
+ priv->rx_dma_idx = 0;
+ priv->tx_dma_idx = 0;
+
+ /* Make sure the writes executed at this place */
+ wmb();
+
+ /* disable delay interrupt */
+ writel(0, base + DLY_INT_CFG);
+
+ clrbits_le32(base + PDMA_GLO_CFG, 0xffff0000);
+
+ /* Tell the adapter where the TX/RX rings are located. */
+ writel(CPHYSADDR(&priv->rx_ring[0]), base + RX_BASE_PTR0);
+ writel(CPHYSADDR((u32)&priv->tx_ring[0]), base + TX_BASE_PTR0);
+
+ writel(NUM_RX_DESC, base + RX_MAX_CNT0);
+ writel(NUM_TX_DESC, base + TX_MAX_CNT0);
+
+ writel(priv->tx_dma_idx, base + TX_CTX_IDX0);
+ writel(RST_DTX_IDX0, base + PDMA_RST_IDX);
+
+ writel(NUM_RX_DESC - 1, base + RX_CALC_IDX0);
+ writel(RST_DRX_IDX0, base + PDMA_RST_IDX);
+
+ /* Make sure the writes executed at this place */
+ wmb();
+ eth_dma_start(priv);
+
+ /* Check if link is not up yet */
+ if (!phy_link_up(priv)) {
+ /* Wait for link to come up */
+
+ printf("Waiting for link to come up .");
+ for (i = 0; i < (LINK_TIMEOUT / LINK_DELAY_TIME); i++) {
+ mdelay(LINK_DELAY_TIME);
+ if (phy_link_up(priv)) {
+ mdelay(100); /* Ensure all is ready */
+ break;
+ }
+
+ printf(".");
+ }
+
+ if (phy_link_up(priv))
+ printf(" done\n");
+ else
+ printf(" timeout! Trying anyways\n");
+ }
+
+ /*
+ * The integrated switch seems to queue some received ethernet
+ * packets in some FIFO. Lets read the already queued packets
+ * out by using the receive routine, so that these old messages
+ * are dropped before the new xfer starts.
+ */
+ packetp = &packet[0];
+ while (mt7628_eth_recv(dev, 0, &packetp) != -EAGAIN)
+ mt7628_eth_free_pkt(dev, packetp, 0);
+
+ return 0;
+}
+
+static void mt7628_eth_stop(struct udevice *dev)
+{
+ struct mt7628_eth_dev *priv = dev_get_priv(dev);
+
+ eth_dma_stop(priv);
+}
+
+static int mt7628_eth_probe(struct udevice *dev)
+{
+ struct mt7628_eth_dev *priv = dev_get_priv(dev);
+ struct udevice *syscon;
+ struct mii_dev *bus;
+ int ret;
+ int i;
+
+ /* Save frame-engine base address for later use */
+ priv->base = dev_remap_addr_index(dev, 0);
+ if (IS_ERR(priv->base))
+ return PTR_ERR(priv->base);
+
+ /* Save switch base address for later use */
+ priv->eth_sw_base = dev_remap_addr_index(dev, 1);
+ if (IS_ERR(priv->eth_sw_base))
+ return PTR_ERR(priv->eth_sw_base);
+
+ /* Get system controller regmap */
+ ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev,
+ "syscon", &syscon);
+ if (ret) {
+ pr_err("unable to find syscon device\n");
+ return ret;
+ }
+
+ priv->sysctrl_regmap = syscon_get_regmap(syscon);
+ if (!priv->sysctrl_regmap) {
+ pr_err("unable to find regmap\n");
+ return -ENODEV;
+ }
+
+ /* Put rx and tx rings into KSEG1 area (uncached) */
+ priv->tx_ring = (struct fe_tx_dma *)
+ KSEG1ADDR(memalign(ARCH_DMA_MINALIGN,
+ sizeof(*priv->tx_ring) * NUM_TX_DESC));
+ priv->rx_ring = (struct fe_rx_dma *)
+ KSEG1ADDR(memalign(ARCH_DMA_MINALIGN,
+ sizeof(*priv->rx_ring) * NUM_RX_DESC));
+
+ for (i = 0; i < NUM_RX_DESC; i++)
+ priv->rx_buf[i] = memalign(PKTALIGN, MTK_QDMA_PAGE_SIZE);
+
+ bus = mdio_alloc();
+ if (!bus) {
+ printf("Failed to allocate MDIO bus\n");
+ return -ENOMEM;
+ }
+
+ bus->read = mt7628_mdio_read;
+ bus->write = mt7628_mdio_write;
+ snprintf(bus->name, sizeof(bus->name), dev->name);
+ bus->priv = (void *)priv;
+
+ ret = mdio_register(bus);
+ if (ret)
+ return ret;
+
+ /* Switch configuration */
+ rt305x_esw_init(priv);
+
+ return 0;
+}
+
+static const struct eth_ops mt7628_eth_ops = {
+ .start = mt7628_eth_start,
+ .send = mt7628_eth_send,
+ .recv = mt7628_eth_recv,
+ .free_pkt = mt7628_eth_free_pkt,
+ .stop = mt7628_eth_stop,
+ .write_hwaddr = mt7628_eth_write_hwaddr,
+};
+
+static const struct udevice_id mt7628_eth_ids[] = {
+ { .compatible = "mediatek,mt7628-eth" },
+ { }
+};
+
+U_BOOT_DRIVER(mt7628_eth) = {
+ .name = "mt7628_eth",
+ .id = UCLASS_ETH,
+ .of_match = mt7628_eth_ids,
+ .probe = mt7628_eth_probe,
+ .ops = &mt7628_eth_ops,
+ .priv_auto_alloc_size = sizeof(struct mt7628_eth_dev),
+ .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+};
#include <miiphy.h>
#include <bitfield.h>
+#include <time.h>
+#include <linux/delay.h>
/* Microsemi PHY ID's */
#define PHY_ID_VSC8530 0x00070560
#define PHY_ID_VSC8531 0x00070570
#define PHY_ID_VSC8540 0x00070760
#define PHY_ID_VSC8541 0x00070770
+#define PHY_ID_VSC8574 0x000704a0
+#define PHY_ID_VSC8584 0x000707c0
/* Microsemi VSC85xx PHY Register Pages */
#define MSCC_EXT_PAGE_ACCESS 31 /* Page Access Register */
#define MSCC_PHY_PAGE_TEST 0x2A30 /* TEST Page registers */
#define MSCC_PHY_PAGE_TR 0x52B5 /* Token Ring Page registers */
+/* Std Page Register 18 */
+#define MSCC_PHY_BYPASS_CONTROL 18
+#define PARALLEL_DET_IGNORE_ADVERTISED BIT(3)
+
+/* Std Page Register 22 */
+#define MSCC_PHY_EXT_CNTL_STATUS 22
+#define SMI_BROADCAST_WR_EN BIT(0)
+
+/* Std Page Register 24 */
+#define MSCC_PHY_EXT_PHY_CNTL_2 24
+
/* Std Page Register 28 - PHY AUX Control/Status */
#define MIIM_AUX_CNTRL_STAT_REG 28
#define MIIM_AUX_CNTRL_STAT_ACTIPHY_TO (0x0004)
#define MAC_IF_SELECTION_RGMII (2)
#define MAC_IF_SELECTION_POS (11)
#define MAC_IF_SELECTION_WIDTH (2)
+#define VSC8584_MAC_IF_SELECTION_MASK BIT(12)
+#define VSC8584_MAC_IF_SELECTION_SGMII 0
+#define VSC8584_MAC_IF_SELECTION_1000BASEX 1
+#define VSC8584_MAC_IF_SELECTION_POS 12
+#define MEDIA_OP_MODE_MASK GENMASK(10, 8)
+#define MEDIA_OP_MODE_COPPER 0
+#define MEDIA_OP_MODE_SERDES 1
+#define MEDIA_OP_MODE_1000BASEX 2
+#define MEDIA_OP_MODE_100BASEFX 3
+#define MEDIA_OP_MODE_AMS_COPPER_SERDES 5
+#define MEDIA_OP_MODE_AMS_COPPER_1000BASEX 6
+#define MEDIA_OP_MODE_AMS_COPPER_100BASEFX 7
+#define MEDIA_OP_MODE_POS 8
+
+/* Extended Page 1 Register 20E1 */
+#define MSCC_PHY_ACTIPHY_CNTL 20
+#define PHY_ADDR_REVERSED BIT(9)
+
+/* Extended Page 1 Register 23E1 */
+
+#define MSCC_PHY_EXT_PHY_CNTL_4 23
+#define PHY_CNTL_4_ADDR_POS 11
+
+/* Extended Page 1 Register 25E1 */
+#define MSCC_PHY_VERIPHY_CNTL_2 25
+
+/* Extended Page 1 Register 26E1 */
+#define MSCC_PHY_VERIPHY_CNTL_3 26
+
+/* Extended Page 2 Register 16E2 */
+#define MSCC_PHY_CU_PMD_TX_CNTL 16
/* Extended Page 2 Register 20E2 */
#define MSCC_PHY_RGMII_CNTL_REG 20
#define RMII_CLK_OUT_ENABLE_WIDTH (1)
#define RMII_CLK_OUT_ENABLE_MASK (0x10)
+/* Extended Page 3 Register 22E3 */
+#define MSCC_PHY_SERDES_TX_CRC_ERR_CNT 22
+
+/* Extended page GPIO register 00G */
+#define MSCC_DW8051_CNTL_STATUS 0
+#define MICRO_NSOFT_RESET BIT(15)
+#define RUN_FROM_INT_ROM BIT(14)
+#define AUTOINC_ADDR BIT(13)
+#define PATCH_RAM_CLK BIT(12)
+#define MICRO_PATCH_EN BIT(7)
+#define DW8051_CLK_EN BIT(4)
+#define MICRO_CLK_EN BIT(3)
+#define MICRO_CLK_DIVIDE(x) ((x) >> 1)
+#define MSCC_DW8051_VLD_MASK 0xf1ff
+
+/* Extended page GPIO register 09G */
+#define MSCC_TRAP_ROM_ADDR(x) ((x) * 2 + 1)
+#define MSCC_TRAP_ROM_ADDR_SERDES_INIT 0x3eb7
+
+/* Extended page GPIO register 10G */
+#define MSCC_PATCH_RAM_ADDR(x) (((x) + 1) * 2)
+#define MSCC_PATCH_RAM_ADDR_SERDES_INIT 0x4012
+
+/* Extended page GPIO register 11G */
+#define MSCC_INT_MEM_ADDR 11
+
+/* Extended page GPIO register 12G */
+#define MSCC_INT_MEM_CNTL 12
+#define READ_SFR (BIT(14) | BIT(13))
+#define READ_PRAM BIT(14)
+#define READ_ROM BIT(13)
+#define READ_RAM (0x00 << 13)
+#define INT_MEM_WRITE_EN BIT(12)
+#define EN_PATCH_RAM_TRAP_ADDR(x) BIT((x) + 7)
+#define INT_MEM_DATA_M GENMASK(7, 0)
+#define INT_MEM_DATA(x) (INT_MEM_DATA_M & (x))
+
+/* Extended page GPIO register 18G */
+#define MSCC_PHY_PROC_CMD 18
+#define PROC_CMD_NCOMPLETED BIT(15)
+#define PROC_CMD_FAILED BIT(14)
+#define PROC_CMD_SGMII_PORT(x) ((x) << 8)
+#define PROC_CMD_FIBER_PORT(x) BIT(8 + (x) % 4)
+#define PROC_CMD_QSGMII_PORT (BIT(11) | BIT(10))
+#define PROC_CMD_RST_CONF_PORT BIT(7)
+#define PROC_CMD_RECONF_PORT (0 << 7)
+#define PROC_CMD_READ_MOD_WRITE_PORT BIT(6)
+#define PROC_CMD_WRITE BIT(6)
+#define PROC_CMD_READ (0 << 6)
+#define PROC_CMD_FIBER_DISABLE BIT(5)
+#define PROC_CMD_FIBER_100BASE_FX BIT(4)
+#define PROC_CMD_FIBER_1000BASE_X (0 << 4)
+#define PROC_CMD_SGMII_MAC (BIT(5) | BIT(4))
+#define PROC_CMD_QSGMII_MAC BIT(5)
+#define PROC_CMD_NO_MAC_CONF (0x00 << 4)
+#define PROC_CMD_1588_DEFAULT_INIT BIT(4)
+#define PROC_CMD_NOP GENMASK(3, 0)
+#define PROC_CMD_PHY_INIT (BIT(3) | BIT(1))
+#define PROC_CMD_CRC16 BIT(3)
+#define PROC_CMD_FIBER_MEDIA_CONF BIT(0)
+#define PROC_CMD_MCB_ACCESS_MAC_CONF (0x0000 << 0)
+#define PROC_CMD_NCOMPLETED_TIMEOUT_MS 500
+
+/* Extended page GPIO register 19G */
+#define MSCC_PHY_MAC_CFG_FASTLINK 19
+#define MAC_CFG_MASK GENMASK(15, 14)
+#define MAC_CFG_SGMII (0x00 << 14)
+#define MAC_CFG_QSGMII BIT(14)
+
+/* Test Registers */
+#define MSCC_PHY_TEST_PAGE_5 5
+
+#define MSCC_PHY_TEST_PAGE_8 8
+#define TR_CLK_DISABLE BIT(15)
+
+#define MSCC_PHY_TEST_PAGE_9 9
+#define MSCC_PHY_TEST_PAGE_20 20
+#define MSCC_PHY_TEST_PAGE_24 24
+
/* Token Ring Page 0x52B5 Registers */
#define MSCC_PHY_REG_TR_ADDR_16 16
#define MSCC_PHY_REG_TR_DATA_17 17
#define MSCC_PHY_RESET_TIMEOUT (100)
#define MSCC_PHY_MICRO_TIMEOUT (500)
+#define VSC8584_REVB 0x0001
+#define MSCC_DEV_REV_MASK GENMASK(3, 0)
+
+#define MSCC_VSC8574_REVB_INT8051_FW_START_ADDR 0x4000
+#define MSCC_VSC8574_REVB_INT8051_FW_CRC 0x29e8
+
+#define MSCC_VSC8584_REVB_INT8051_FW_START_ADDR 0xe800
+#define MSCC_VSC8584_REVB_INT8051_FW_CRC 0xfb48
+
/* RGMII/GMII Clock Delay (Skew) Options */ enum vsc_phy_rgmii_skew {
VSC_PHY_RGMII_DELAY_200_PS,
VSC_PHY_RGMII_DELAY_800_PS,
VSC_PHY_CLK_SLEW_RATE_7,
};
+struct vsc85xx_priv {
+ int (*config_pre)(struct phy_device *phydev);
+};
+
+static void vsc8584_csr_write(struct mii_dev *bus, int phy0, u16 addr, u32 val)
+{
+ bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_DATA_18,
+ val >> 16);
+ bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_DATA_17,
+ val & GENMASK(15, 0));
+ bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_ADDR_16,
+ MSCC_PHY_TR_16_WRITE | addr);
+}
+
+static int vsc8584_cmd(struct mii_dev *bus, int phy, u16 val)
+{
+ unsigned long deadline;
+ u16 reg_val;
+
+ bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS,
+ MSCC_PHY_PAGE_GPIO);
+
+ bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_PHY_PROC_CMD,
+ PROC_CMD_NCOMPLETED | val);
+
+ deadline = timer_get_us() + PROC_CMD_NCOMPLETED_TIMEOUT_MS * 1000;
+ do {
+ reg_val = bus->read(bus, phy, MDIO_DEVAD_NONE,
+ MSCC_PHY_PROC_CMD);
+ } while (timer_get_us() <= deadline &&
+ (reg_val & PROC_CMD_NCOMPLETED) &&
+ !(reg_val & PROC_CMD_FAILED));
+
+ bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS,
+ MSCC_PHY_PAGE_STD);
+
+ if (reg_val & PROC_CMD_FAILED)
+ return -EIO;
+ if (reg_val & PROC_CMD_NCOMPLETED)
+ return -ETIMEDOUT;
+
+ return 0;
+}
+
+static int vsc8584_micro_deassert_reset(struct mii_dev *bus, int phy,
+ bool patch_en)
+{
+ u32 enable, release;
+
+ bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS,
+ MSCC_PHY_PAGE_GPIO);
+
+ enable = RUN_FROM_INT_ROM | MICRO_CLK_EN | DW8051_CLK_EN;
+ release = MICRO_NSOFT_RESET | RUN_FROM_INT_ROM | DW8051_CLK_EN |
+ MICRO_CLK_EN;
+
+ if (patch_en) {
+ enable |= MICRO_PATCH_EN;
+ release |= MICRO_PATCH_EN;
+
+ /* Clear all patches */
+ bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_INT_MEM_CNTL,
+ READ_RAM);
+ }
+
+ /*
+ * Enable 8051 Micro clock; CLEAR/SET patch present; disable PRAM clock
+ * override and addr. auto-incr; operate at 125 MHz
+ */
+ bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS, enable);
+ /* Release 8051 Micro SW reset */
+ bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS, release);
+
+ bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS,
+ MSCC_PHY_PAGE_STD);
+
+ return 0;
+}
+
+static int vsc8584_micro_assert_reset(struct mii_dev *bus, int phy)
+{
+ int ret;
+ u16 reg;
+
+ ret = vsc8584_cmd(bus, phy, PROC_CMD_NOP);
+ if (ret)
+ return ret;
+
+ bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS,
+ MSCC_PHY_PAGE_GPIO);
+
+ reg = bus->read(bus, phy, MDIO_DEVAD_NONE, MSCC_INT_MEM_CNTL);
+ reg &= ~EN_PATCH_RAM_TRAP_ADDR(4);
+ bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_INT_MEM_CNTL, reg);
+
+ bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_TRAP_ROM_ADDR(4), 0x005b);
+ bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_PATCH_RAM_ADDR(4), 0x005b);
+
+ reg = bus->read(bus, phy, MDIO_DEVAD_NONE, MSCC_INT_MEM_CNTL);
+ reg |= EN_PATCH_RAM_TRAP_ADDR(4);
+ bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_INT_MEM_CNTL, reg);
+
+ bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_PHY_PROC_CMD, PROC_CMD_NOP);
+
+ reg = bus->read(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS);
+ reg &= ~MICRO_NSOFT_RESET;
+ bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS, reg);
+
+ bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_PHY_PROC_CMD,
+ PROC_CMD_MCB_ACCESS_MAC_CONF | PROC_CMD_SGMII_PORT(0) |
+ PROC_CMD_NO_MAC_CONF | PROC_CMD_READ);
+
+ reg = bus->read(bus, phy, MDIO_DEVAD_NONE, MSCC_INT_MEM_CNTL);
+ reg &= ~EN_PATCH_RAM_TRAP_ADDR(4);
+ bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_INT_MEM_CNTL, reg);
+
+ bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS,
+ MSCC_PHY_PAGE_STD);
+
+ return 0;
+}
+
+static const u8 fw_patch_vsc8574[] = {
+ 0x46, 0x4a, 0x02, 0x43, 0x37, 0x02, 0x46, 0x26, 0x02, 0x46, 0x77, 0x02,
+ 0x45, 0x60, 0x02, 0x45, 0xaf, 0xed, 0xff, 0xe5, 0xfc, 0x54, 0x38, 0x64,
+ 0x20, 0x70, 0x08, 0x65, 0xff, 0x70, 0x04, 0xed, 0x44, 0x80, 0xff, 0x22,
+ 0x8f, 0x19, 0x7b, 0xbb, 0x7d, 0x0e, 0x7f, 0x04, 0x12, 0x3d, 0xd7, 0xef,
+ 0x4e, 0x60, 0x03, 0x02, 0x41, 0xf9, 0xe4, 0xf5, 0x1a, 0x74, 0x01, 0x7e,
+ 0x00, 0xa8, 0x1a, 0x08, 0x80, 0x05, 0xc3, 0x33, 0xce, 0x33, 0xce, 0xd8,
+ 0xf9, 0xff, 0xef, 0x55, 0x19, 0x70, 0x03, 0x02, 0x41, 0xed, 0x85, 0x1a,
+ 0xfb, 0x7b, 0xbb, 0xe4, 0xfd, 0xff, 0x12, 0x3d, 0xd7, 0xef, 0x4e, 0x60,
+ 0x03, 0x02, 0x41, 0xed, 0xe5, 0x1a, 0x54, 0x02, 0x75, 0x1d, 0x00, 0x25,
+ 0xe0, 0x25, 0xe0, 0xf5, 0x1c, 0xe4, 0x78, 0xc5, 0xf6, 0xd2, 0x0a, 0x12,
+ 0x41, 0xfa, 0x7b, 0xff, 0x7d, 0x12, 0x7f, 0x07, 0x12, 0x3d, 0xd7, 0xef,
+ 0x4e, 0x60, 0x03, 0x02, 0x41, 0xe7, 0xc2, 0x0a, 0x74, 0xc7, 0x25, 0x1a,
+ 0xf9, 0x74, 0xe7, 0x25, 0x1a, 0xf8, 0xe6, 0x27, 0xf5, 0x1b, 0xe5, 0x1d,
+ 0x24, 0x5b, 0x12, 0x45, 0xea, 0x12, 0x3e, 0xda, 0x7b, 0xfc, 0x7d, 0x11,
+ 0x7f, 0x07, 0x12, 0x3d, 0xd7, 0x78, 0xcc, 0xef, 0xf6, 0x78, 0xc1, 0xe6,
+ 0xfe, 0xef, 0xd3, 0x9e, 0x40, 0x06, 0x78, 0xcc, 0xe6, 0x78, 0xc1, 0xf6,
+ 0x12, 0x41, 0xfa, 0x7b, 0xec, 0x7d, 0x12, 0x7f, 0x07, 0x12, 0x3d, 0xd7,
+ 0x78, 0xcb, 0xef, 0xf6, 0xbf, 0x07, 0x06, 0x78, 0xc3, 0x76, 0x1a, 0x80,
+ 0x1f, 0x78, 0xc5, 0xe6, 0xff, 0x60, 0x0f, 0xc3, 0xe5, 0x1b, 0x9f, 0xff,
+ 0x78, 0xcb, 0xe6, 0x85, 0x1b, 0xf0, 0xa4, 0x2f, 0x80, 0x07, 0x78, 0xcb,
+ 0xe6, 0x85, 0x1b, 0xf0, 0xa4, 0x78, 0xc3, 0xf6, 0xe4, 0x78, 0xc2, 0xf6,
+ 0x78, 0xc2, 0xe6, 0xff, 0xc3, 0x08, 0x96, 0x40, 0x03, 0x02, 0x41, 0xd1,
+ 0xef, 0x54, 0x03, 0x60, 0x33, 0x14, 0x60, 0x46, 0x24, 0xfe, 0x60, 0x42,
+ 0x04, 0x70, 0x4b, 0xef, 0x24, 0x02, 0xff, 0xe4, 0x33, 0xfe, 0xef, 0x78,
+ 0x02, 0xce, 0xa2, 0xe7, 0x13, 0xce, 0x13, 0xd8, 0xf8, 0xff, 0xe5, 0x1d,
+ 0x24, 0x5c, 0xcd, 0xe5, 0x1c, 0x34, 0xf0, 0xcd, 0x2f, 0xff, 0xed, 0x3e,
+ 0xfe, 0x12, 0x46, 0x0d, 0x7d, 0x11, 0x80, 0x0b, 0x78, 0xc2, 0xe6, 0x70,
+ 0x04, 0x7d, 0x11, 0x80, 0x02, 0x7d, 0x12, 0x7f, 0x07, 0x12, 0x3e, 0x9a,
+ 0x8e, 0x1e, 0x8f, 0x1f, 0x80, 0x03, 0xe5, 0x1e, 0xff, 0x78, 0xc5, 0xe6,
+ 0x06, 0x24, 0xcd, 0xf8, 0xa6, 0x07, 0x78, 0xc2, 0x06, 0xe6, 0xb4, 0x1a,
+ 0x0a, 0xe5, 0x1d, 0x24, 0x5c, 0x12, 0x45, 0xea, 0x12, 0x3e, 0xda, 0x78,
+ 0xc5, 0xe6, 0x65, 0x1b, 0x70, 0x82, 0x75, 0xdb, 0x20, 0x75, 0xdb, 0x28,
+ 0x12, 0x46, 0x02, 0x12, 0x46, 0x02, 0xe5, 0x1a, 0x12, 0x45, 0xf5, 0xe5,
+ 0x1a, 0xc3, 0x13, 0x12, 0x45, 0xf5, 0x78, 0xc5, 0x16, 0xe6, 0x24, 0xcd,
+ 0xf8, 0xe6, 0xff, 0x7e, 0x08, 0x1e, 0xef, 0xa8, 0x06, 0x08, 0x80, 0x02,
+ 0xc3, 0x13, 0xd8, 0xfc, 0xfd, 0xc4, 0x33, 0x54, 0xe0, 0xf5, 0xdb, 0xef,
+ 0xa8, 0x06, 0x08, 0x80, 0x02, 0xc3, 0x13, 0xd8, 0xfc, 0xfd, 0xc4, 0x33,
+ 0x54, 0xe0, 0x44, 0x08, 0xf5, 0xdb, 0xee, 0x70, 0xd8, 0x78, 0xc5, 0xe6,
+ 0x70, 0xc8, 0x75, 0xdb, 0x10, 0x02, 0x40, 0xfd, 0x78, 0xc2, 0xe6, 0xc3,
+ 0x94, 0x17, 0x50, 0x0e, 0xe5, 0x1d, 0x24, 0x62, 0x12, 0x42, 0x08, 0xe5,
+ 0x1d, 0x24, 0x5c, 0x12, 0x42, 0x08, 0x20, 0x0a, 0x03, 0x02, 0x40, 0x76,
+ 0x05, 0x1a, 0xe5, 0x1a, 0xc3, 0x94, 0x04, 0x50, 0x03, 0x02, 0x40, 0x3a,
+ 0x22, 0xe5, 0x1d, 0x24, 0x5c, 0xff, 0xe5, 0x1c, 0x34, 0xf0, 0xfe, 0x12,
+ 0x46, 0x0d, 0x22, 0xff, 0xe5, 0x1c, 0x34, 0xf0, 0xfe, 0x12, 0x46, 0x0d,
+ 0x22, 0xe4, 0xf5, 0x19, 0x12, 0x46, 0x43, 0x20, 0xe7, 0x1e, 0x7b, 0xfe,
+ 0x12, 0x42, 0xf9, 0xef, 0xc4, 0x33, 0x33, 0x54, 0xc0, 0xff, 0xc0, 0x07,
+ 0x7b, 0x54, 0x12, 0x42, 0xf9, 0xd0, 0xe0, 0x4f, 0xff, 0x74, 0x2a, 0x25,
+ 0x19, 0xf8, 0xa6, 0x07, 0x12, 0x46, 0x43, 0x20, 0xe7, 0x03, 0x02, 0x42,
+ 0xdf, 0x54, 0x03, 0x64, 0x03, 0x70, 0x03, 0x02, 0x42, 0xcf, 0x7b, 0xcb,
+ 0x12, 0x43, 0x2c, 0x8f, 0xfb, 0x7b, 0x30, 0x7d, 0x03, 0xe4, 0xff, 0x12,
+ 0x3d, 0xd7, 0xc3, 0xef, 0x94, 0x02, 0xee, 0x94, 0x00, 0x50, 0x2a, 0x12,
+ 0x42, 0xec, 0xef, 0x4e, 0x70, 0x23, 0x12, 0x43, 0x04, 0x60, 0x0a, 0x12,
+ 0x43, 0x12, 0x70, 0x0c, 0x12, 0x43, 0x1f, 0x70, 0x07, 0x12, 0x46, 0x39,
+ 0x7b, 0x03, 0x80, 0x07, 0x12, 0x46, 0x39, 0x12, 0x46, 0x43, 0xfb, 0x7a,
+ 0x00, 0x7d, 0x54, 0x80, 0x3e, 0x12, 0x42, 0xec, 0xef, 0x4e, 0x70, 0x24,
+ 0x12, 0x43, 0x04, 0x60, 0x0a, 0x12, 0x43, 0x12, 0x70, 0x0f, 0x12, 0x43,
+ 0x1f, 0x70, 0x0a, 0x12, 0x46, 0x39, 0xe4, 0xfb, 0xfa, 0x7d, 0xee, 0x80,
+ 0x1e, 0x12, 0x46, 0x39, 0x7b, 0x01, 0x7a, 0x00, 0x7d, 0xee, 0x80, 0x13,
+ 0x12, 0x46, 0x39, 0x12, 0x46, 0x43, 0x54, 0x40, 0xfe, 0xc4, 0x13, 0x13,
+ 0x54, 0x03, 0xfb, 0x7a, 0x00, 0x7d, 0xee, 0x12, 0x38, 0xbd, 0x7b, 0xff,
+ 0x12, 0x43, 0x2c, 0xef, 0x4e, 0x70, 0x07, 0x74, 0x2a, 0x25, 0x19, 0xf8,
+ 0xe4, 0xf6, 0x05, 0x19, 0xe5, 0x19, 0xc3, 0x94, 0x02, 0x50, 0x03, 0x02,
+ 0x42, 0x15, 0x22, 0xe5, 0x19, 0x24, 0x17, 0xfd, 0x7b, 0x20, 0x7f, 0x04,
+ 0x12, 0x3d, 0xd7, 0x22, 0xe5, 0x19, 0x24, 0x17, 0xfd, 0x7f, 0x04, 0x12,
+ 0x3d, 0xd7, 0x22, 0x7b, 0x22, 0x7d, 0x18, 0x7f, 0x06, 0x12, 0x3d, 0xd7,
+ 0xef, 0x64, 0x01, 0x4e, 0x22, 0x7d, 0x1c, 0xe4, 0xff, 0x12, 0x3e, 0x9a,
+ 0xef, 0x54, 0x1b, 0x64, 0x0a, 0x22, 0x7b, 0xcc, 0x7d, 0x10, 0xff, 0x12,
+ 0x3d, 0xd7, 0xef, 0x64, 0x01, 0x4e, 0x22, 0xe5, 0x19, 0x24, 0x17, 0xfd,
+ 0x7f, 0x04, 0x12, 0x3d, 0xd7, 0x22, 0xd2, 0x08, 0x75, 0xfb, 0x03, 0xab,
+ 0x7e, 0xaa, 0x7d, 0x7d, 0x19, 0x7f, 0x03, 0x12, 0x3e, 0xda, 0xe5, 0x7e,
+ 0x54, 0x0f, 0x24, 0xf3, 0x60, 0x03, 0x02, 0x43, 0xe9, 0x12, 0x46, 0x5a,
+ 0x12, 0x46, 0x61, 0xd8, 0xfb, 0xff, 0x20, 0xe2, 0x35, 0x13, 0x92, 0x0c,
+ 0xef, 0xa2, 0xe1, 0x92, 0x0b, 0x30, 0x0c, 0x2a, 0xe4, 0xf5, 0x10, 0x7b,
+ 0xfe, 0x12, 0x43, 0xff, 0xef, 0xc4, 0x33, 0x33, 0x54, 0xc0, 0xff, 0xc0,
+ 0x07, 0x7b, 0x54, 0x12, 0x43, 0xff, 0xd0, 0xe0, 0x4f, 0xff, 0x74, 0x2a,
+ 0x25, 0x10, 0xf8, 0xa6, 0x07, 0x05, 0x10, 0xe5, 0x10, 0xc3, 0x94, 0x02,
+ 0x40, 0xd9, 0x12, 0x46, 0x5a, 0x12, 0x46, 0x61, 0xd8, 0xfb, 0x54, 0x05,
+ 0x64, 0x04, 0x70, 0x27, 0x78, 0xc4, 0xe6, 0x78, 0xc6, 0xf6, 0xe5, 0x7d,
+ 0xff, 0x33, 0x95, 0xe0, 0xef, 0x54, 0x0f, 0x78, 0xc4, 0xf6, 0x12, 0x44,
+ 0x0a, 0x20, 0x0c, 0x0c, 0x12, 0x46, 0x5a, 0x12, 0x46, 0x61, 0xd8, 0xfb,
+ 0x13, 0x92, 0x0d, 0x22, 0xc2, 0x0d, 0x22, 0x12, 0x46, 0x5a, 0x12, 0x46,
+ 0x61, 0xd8, 0xfb, 0x54, 0x05, 0x64, 0x05, 0x70, 0x1e, 0x78, 0xc4, 0x7d,
+ 0xb8, 0x12, 0x43, 0xf5, 0x78, 0xc1, 0x7d, 0x74, 0x12, 0x43, 0xf5, 0xe4,
+ 0x78, 0xc1, 0xf6, 0x22, 0x7b, 0x01, 0x7a, 0x00, 0x7d, 0xee, 0x7f, 0x92,
+ 0x12, 0x38, 0xbd, 0x22, 0xe6, 0xfb, 0x7a, 0x00, 0x7f, 0x92, 0x12, 0x38,
+ 0xbd, 0x22, 0xe5, 0x10, 0x24, 0x17, 0xfd, 0x7f, 0x04, 0x12, 0x3d, 0xd7,
+ 0x22, 0x78, 0xc1, 0xe6, 0xfb, 0x7a, 0x00, 0x7d, 0x74, 0x7f, 0x92, 0x12,
+ 0x38, 0xbd, 0xe4, 0x78, 0xc1, 0xf6, 0xf5, 0x11, 0x74, 0x01, 0x7e, 0x00,
+ 0xa8, 0x11, 0x08, 0x80, 0x05, 0xc3, 0x33, 0xce, 0x33, 0xce, 0xd8, 0xf9,
+ 0xff, 0x78, 0xc4, 0xe6, 0xfd, 0xef, 0x5d, 0x60, 0x44, 0x85, 0x11, 0xfb,
+ 0xe5, 0x11, 0x54, 0x02, 0x25, 0xe0, 0x25, 0xe0, 0xfe, 0xe4, 0x24, 0x5b,
+ 0xfb, 0xee, 0x12, 0x45, 0xed, 0x12, 0x3e, 0xda, 0x7b, 0x40, 0x7d, 0x11,
+ 0x7f, 0x07, 0x12, 0x3d, 0xd7, 0x74, 0xc7, 0x25, 0x11, 0xf8, 0xa6, 0x07,
+ 0x7b, 0x11, 0x7d, 0x12, 0x7f, 0x07, 0x12, 0x3d, 0xd7, 0xef, 0x4e, 0x60,
+ 0x09, 0x74, 0xe7, 0x25, 0x11, 0xf8, 0x76, 0x04, 0x80, 0x07, 0x74, 0xe7,
+ 0x25, 0x11, 0xf8, 0x76, 0x0a, 0x05, 0x11, 0xe5, 0x11, 0xc3, 0x94, 0x04,
+ 0x40, 0x9a, 0x78, 0xc6, 0xe6, 0x70, 0x15, 0x78, 0xc4, 0xe6, 0x60, 0x10,
+ 0x75, 0xd9, 0x38, 0x75, 0xdb, 0x10, 0x7d, 0xfe, 0x12, 0x44, 0xb8, 0x7d,
+ 0x76, 0x12, 0x44, 0xb8, 0x79, 0xc6, 0xe7, 0x78, 0xc4, 0x66, 0xff, 0x60,
+ 0x03, 0x12, 0x40, 0x25, 0x78, 0xc4, 0xe6, 0x70, 0x09, 0xfb, 0xfa, 0x7d,
+ 0xfe, 0x7f, 0x8e, 0x12, 0x38, 0xbd, 0x22, 0x7b, 0x01, 0x7a, 0x00, 0x7f,
+ 0x8e, 0x12, 0x38, 0xbd, 0x22, 0xe4, 0xf5, 0xfb, 0x7d, 0x1c, 0xe4, 0xff,
+ 0x12, 0x3e, 0x9a, 0xad, 0x07, 0xac, 0x06, 0xec, 0x54, 0xc0, 0xff, 0xed,
+ 0x54, 0x3f, 0x4f, 0xf5, 0x20, 0x30, 0x06, 0x2c, 0x30, 0x01, 0x08, 0xa2,
+ 0x04, 0x72, 0x03, 0x92, 0x07, 0x80, 0x21, 0x30, 0x04, 0x06, 0x7b, 0xcc,
+ 0x7d, 0x11, 0x80, 0x0d, 0x30, 0x03, 0x06, 0x7b, 0xcc, 0x7d, 0x10, 0x80,
+ 0x04, 0x7b, 0x66, 0x7d, 0x16, 0xe4, 0xff, 0x12, 0x3d, 0xd7, 0xee, 0x4f,
+ 0x24, 0xff, 0x92, 0x07, 0xaf, 0xfb, 0x74, 0x26, 0x2f, 0xf8, 0xe6, 0xff,
+ 0xa6, 0x20, 0x20, 0x07, 0x39, 0x8f, 0x20, 0x30, 0x07, 0x34, 0x30, 0x00,
+ 0x31, 0x20, 0x04, 0x2e, 0x20, 0x03, 0x2b, 0xe4, 0xf5, 0xff, 0x75, 0xfc,
+ 0xc2, 0xe5, 0xfc, 0x30, 0xe0, 0xfb, 0xaf, 0xfe, 0xef, 0x20, 0xe3, 0x1a,
+ 0xae, 0xfd, 0x44, 0x08, 0xf5, 0xfe, 0x75, 0xfc, 0x80, 0xe5, 0xfc, 0x30,
+ 0xe0, 0xfb, 0x8f, 0xfe, 0x8e, 0xfd, 0x75, 0xfc, 0x80, 0xe5, 0xfc, 0x30,
+ 0xe0, 0xfb, 0x05, 0xfb, 0xaf, 0xfb, 0xef, 0xc3, 0x94, 0x04, 0x50, 0x03,
+ 0x02, 0x44, 0xc5, 0xe4, 0xf5, 0xfb, 0x22, 0xe5, 0x7e, 0x54, 0x0f, 0x64,
+ 0x01, 0x70, 0x23, 0xe5, 0x7e, 0x30, 0xe4, 0x1e, 0x90, 0x47, 0xd0, 0xe0,
+ 0x44, 0x02, 0xf0, 0x54, 0xfb, 0xf0, 0x90, 0x47, 0xd4, 0xe0, 0x44, 0x04,
+ 0xf0, 0x7b, 0x03, 0x7d, 0x5b, 0x7f, 0x5d, 0x12, 0x36, 0x29, 0x7b, 0x0e,
+ 0x80, 0x1c, 0x90, 0x47, 0xd0, 0xe0, 0x54, 0xfd, 0xf0, 0x44, 0x04, 0xf0,
+ 0x90, 0x47, 0xd4, 0xe0, 0x54, 0xfb, 0xf0, 0x7b, 0x02, 0x7d, 0x5b, 0x7f,
+ 0x5d, 0x12, 0x36, 0x29, 0x7b, 0x06, 0x7d, 0x60, 0x7f, 0x63, 0x12, 0x36,
+ 0x29, 0x22, 0xe5, 0x7e, 0x30, 0xe5, 0x35, 0x30, 0xe4, 0x0b, 0x7b, 0x02,
+ 0x7d, 0x33, 0x7f, 0x35, 0x12, 0x36, 0x29, 0x80, 0x10, 0x7b, 0x01, 0x7d,
+ 0x33, 0x7f, 0x35, 0x12, 0x36, 0x29, 0x90, 0x47, 0xd2, 0xe0, 0x44, 0x04,
+ 0xf0, 0x90, 0x47, 0xd2, 0xe0, 0x54, 0xf7, 0xf0, 0x90, 0x47, 0xd1, 0xe0,
+ 0x44, 0x10, 0xf0, 0x7b, 0x05, 0x7d, 0x84, 0x7f, 0x86, 0x12, 0x36, 0x29,
+ 0x22, 0xfb, 0xe5, 0x1c, 0x34, 0xf0, 0xfa, 0x7d, 0x10, 0x7f, 0x07, 0x22,
+ 0x54, 0x01, 0xc4, 0x33, 0x54, 0xe0, 0xf5, 0xdb, 0x44, 0x08, 0xf5, 0xdb,
+ 0x22, 0xf5, 0xdb, 0x75, 0xdb, 0x08, 0xf5, 0xdb, 0x75, 0xdb, 0x08, 0x22,
+ 0xab, 0x07, 0xaa, 0x06, 0x7d, 0x10, 0x7f, 0x07, 0x12, 0x3e, 0xda, 0x7b,
+ 0xff, 0x7d, 0x10, 0x7f, 0x07, 0x12, 0x3d, 0xd7, 0xef, 0x4e, 0x60, 0xf3,
+ 0x22, 0x12, 0x44, 0xc2, 0x30, 0x0c, 0x03, 0x12, 0x42, 0x12, 0x78, 0xc4,
+ 0xe6, 0xff, 0x60, 0x03, 0x12, 0x40, 0x25, 0x22, 0xe5, 0x19, 0x24, 0x17,
+ 0x54, 0x1f, 0x44, 0x80, 0xff, 0x22, 0x74, 0x2a, 0x25, 0x19, 0xf8, 0xe6,
+ 0x22, 0x12, 0x46, 0x72, 0x12, 0x46, 0x68, 0x90, 0x47, 0xfa, 0xe0, 0x54,
+ 0xf8, 0x44, 0x02, 0xf0, 0x22, 0xe5, 0x7e, 0xae, 0x7d, 0x78, 0x04, 0x22,
+ 0xce, 0xa2, 0xe7, 0x13, 0xce, 0x13, 0x22, 0xe4, 0x78, 0xc4, 0xf6, 0xc2,
+ 0x0d, 0x78, 0xc1, 0xf6, 0x22, 0xc2, 0x0c, 0xc2, 0x0b, 0x22, 0x22,
+};
+
+static const u8 fw_patch_vsc8584[] = {
+ 0xe8, 0x59, 0x02, 0xe8, 0x12, 0x02, 0xe8, 0x42, 0x02, 0xe8, 0x5a, 0x02,
+ 0xe8, 0x5b, 0x02, 0xe8, 0x5c, 0xe5, 0x69, 0x54, 0x0f, 0x24, 0xf7, 0x60,
+ 0x27, 0x24, 0xfc, 0x60, 0x23, 0x24, 0x08, 0x70, 0x14, 0xe5, 0x69, 0xae,
+ 0x68, 0x78, 0x04, 0xce, 0xa2, 0xe7, 0x13, 0xce, 0x13, 0xd8, 0xf8, 0x7e,
+ 0x00, 0x54, 0x0f, 0x80, 0x00, 0x7b, 0x01, 0x7a, 0x00, 0x7d, 0xee, 0x7f,
+ 0x92, 0x12, 0x50, 0xee, 0x22, 0xe4, 0xf5, 0x10, 0x85, 0x10, 0xfb, 0x7d,
+ 0x1c, 0xe4, 0xff, 0x12, 0x59, 0xea, 0x05, 0x10, 0xe5, 0x10, 0xc3, 0x94,
+ 0x04, 0x40, 0xed, 0x22, 0x22, 0x22, 0x22, 0x22,
+};
+
+static int vsc8584_get_fw_crc(struct mii_dev *bus, int phy, u16 start,
+ u16 *crc, const u8 *fw_patch, int fw_size)
+{
+ int ret;
+
+ bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS,
+ MSCC_PHY_PAGE_EXT1);
+
+ bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_PHY_VERIPHY_CNTL_2, start);
+ /* Add one byte to size for the one added by the patch_fw function */
+ bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_PHY_VERIPHY_CNTL_3,
+ fw_size + 1);
+
+ ret = vsc8584_cmd(bus, phy, PROC_CMD_CRC16);
+ if (ret)
+ goto out;
+
+ bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS,
+ MSCC_PHY_PAGE_EXT1);
+
+ *crc = bus->read(bus, phy, MDIO_DEVAD_NONE, MSCC_PHY_VERIPHY_CNTL_2);
+
+out:
+ bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS,
+ MSCC_PHY_PAGE_STD);
+
+ return ret;
+}
+
+static int vsc8584_patch_fw(struct mii_dev *bus, int phy, const u8 *fw_patch,
+ int fw_size)
+{
+ int i, ret;
+
+ ret = vsc8584_micro_assert_reset(bus, phy);
+ if (ret) {
+ pr_err("%s: failed to assert reset of micro\n", __func__);
+ return ret;
+ }
+
+ bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS,
+ MSCC_PHY_PAGE_GPIO);
+
+ /*
+ * Hold 8051 Micro in SW Reset, Enable auto incr address and patch clock
+ * Disable the 8051 Micro clock
+ */
+ bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS,
+ RUN_FROM_INT_ROM | AUTOINC_ADDR | PATCH_RAM_CLK |
+ MICRO_CLK_EN | MICRO_CLK_DIVIDE(2));
+ bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_INT_MEM_CNTL, READ_PRAM |
+ INT_MEM_WRITE_EN | INT_MEM_DATA(2));
+ bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_INT_MEM_ADDR, 0x0000);
+
+ for (i = 0; i < fw_size; i++)
+ bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_INT_MEM_CNTL,
+ READ_PRAM | INT_MEM_WRITE_EN | fw_patch[i]);
+
+ /* Clear internal memory access */
+ bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_INT_MEM_CNTL, READ_RAM);
+
+ bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS,
+ MSCC_PHY_PAGE_STD);
+
+ return 0;
+}
+
+static bool vsc8574_is_serdes_init(struct mii_dev *bus, int phy)
+{
+ u16 reg;
+ bool ret;
+
+ bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS,
+ MSCC_PHY_PAGE_GPIO);
+
+ reg = bus->read(bus, phy, MDIO_DEVAD_NONE, MSCC_TRAP_ROM_ADDR(1));
+ if (reg != MSCC_TRAP_ROM_ADDR_SERDES_INIT) {
+ ret = false;
+ goto out;
+ }
+
+ reg = bus->read(bus, phy, MDIO_DEVAD_NONE, MSCC_PATCH_RAM_ADDR(1));
+ if (reg != MSCC_PATCH_RAM_ADDR_SERDES_INIT) {
+ ret = false;
+ goto out;
+ }
+
+ reg = bus->read(bus, phy, MDIO_DEVAD_NONE, MSCC_INT_MEM_CNTL);
+ if (reg != EN_PATCH_RAM_TRAP_ADDR(1)) {
+ ret = false;
+ goto out;
+ }
+
+ reg = bus->read(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS);
+ if ((MICRO_NSOFT_RESET | RUN_FROM_INT_ROM | DW8051_CLK_EN |
+ MICRO_CLK_EN) != (reg & MSCC_DW8051_VLD_MASK)) {
+ ret = false;
+ goto out;
+ }
+
+ ret = true;
+
+out:
+ bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS,
+ MSCC_PHY_PAGE_GPIO);
+
+ return ret;
+}
+
+static int vsc8574_config_pre_init(struct phy_device *phydev)
+{
+ struct mii_dev *bus = phydev->bus;
+ u16 crc, reg, phy0, addr;
+ bool serdes_init;
+ int ret;
+
+ phy_write(phydev, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS,
+ MSCC_PHY_PAGE_EXT1);
+ addr = phy_read(phydev, MDIO_DEVAD_NONE, MSCC_PHY_EXT_PHY_CNTL_4);
+ addr >>= PHY_CNTL_4_ADDR_POS;
+
+ reg = phy_read(phydev, MDIO_DEVAD_NONE, MSCC_PHY_ACTIPHY_CNTL);
+ if (reg & PHY_ADDR_REVERSED)
+ phy0 = phydev->addr + addr;
+ else
+ phy0 = phydev->addr - addr;
+
+ bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS,
+ MSCC_PHY_PAGE_STD);
+
+ /* all writes below are broadcasted to all PHYs in the same package */
+ reg = bus->read(bus, phy0, MDIO_DEVAD_NONE, MSCC_PHY_EXT_CNTL_STATUS);
+ reg |= SMI_BROADCAST_WR_EN;
+ bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_PHY_EXT_CNTL_STATUS, reg);
+
+ /*
+ * The below register writes are tweaking analog and electrical
+ * configuration that were determined through characterization by PHY
+ * engineers. These don't mean anything more than "these are the best
+ * values".
+ */
+ bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_PHY_EXT_PHY_CNTL_2, 0x0040);
+
+ bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS,
+ MSCC_PHY_PAGE_TEST);
+
+ bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_PHY_TEST_PAGE_20, 0x4320);
+ bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_PHY_TEST_PAGE_24, 0x0c00);
+ bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_PHY_TEST_PAGE_9, 0x18ca);
+ bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_PHY_TEST_PAGE_5, 0x1b20);
+
+ reg = bus->read(bus, phy0, MDIO_DEVAD_NONE, MSCC_PHY_TEST_PAGE_8);
+ reg |= TR_CLK_DISABLE;
+ bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_PHY_TEST_PAGE_8, reg);
+
+ bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS,
+ MSCC_PHY_PAGE_TR);
+
+ vsc8584_csr_write(bus, phy0, 0x0fae, 0x000401bd);
+ vsc8584_csr_write(bus, phy0, 0x0fac, 0x000f000f);
+ vsc8584_csr_write(bus, phy0, 0x17a0, 0x00a0f147);
+ vsc8584_csr_write(bus, phy0, 0x0fe4, 0x00052f54);
+ vsc8584_csr_write(bus, phy0, 0x1792, 0x0027303d);
+ vsc8584_csr_write(bus, phy0, 0x07fe, 0x00000704);
+ vsc8584_csr_write(bus, phy0, 0x0fe0, 0x00060150);
+ vsc8584_csr_write(bus, phy0, 0x0f82, 0x0012b00a);
+ vsc8584_csr_write(bus, phy0, 0x0f80, 0x00000d74);
+ vsc8584_csr_write(bus, phy0, 0x02e0, 0x00000012);
+ vsc8584_csr_write(bus, phy0, 0x03a2, 0x00050208);
+ vsc8584_csr_write(bus, phy0, 0x03b2, 0x00009186);
+ vsc8584_csr_write(bus, phy0, 0x0fb0, 0x000e3700);
+ vsc8584_csr_write(bus, phy0, 0x1688, 0x00049f81);
+ vsc8584_csr_write(bus, phy0, 0x0fd2, 0x0000ffff);
+ vsc8584_csr_write(bus, phy0, 0x168a, 0x00039fa2);
+ vsc8584_csr_write(bus, phy0, 0x1690, 0x0020640b);
+ vsc8584_csr_write(bus, phy0, 0x0258, 0x00002220);
+ vsc8584_csr_write(bus, phy0, 0x025a, 0x00002a20);
+ vsc8584_csr_write(bus, phy0, 0x025c, 0x00003060);
+ vsc8584_csr_write(bus, phy0, 0x025e, 0x00003fa0);
+ vsc8584_csr_write(bus, phy0, 0x03a6, 0x0000e0f0);
+ vsc8584_csr_write(bus, phy0, 0x0f92, 0x00001489);
+ vsc8584_csr_write(bus, phy0, 0x16a2, 0x00007000);
+ vsc8584_csr_write(bus, phy0, 0x16a6, 0x00071448);
+ vsc8584_csr_write(bus, phy0, 0x16a0, 0x00eeffdd);
+ vsc8584_csr_write(bus, phy0, 0x0fe8, 0x0091b06c);
+ vsc8584_csr_write(bus, phy0, 0x0fea, 0x00041600);
+ vsc8584_csr_write(bus, phy0, 0x16b0, 0x00eeff00);
+ vsc8584_csr_write(bus, phy0, 0x16b2, 0x00007000);
+ vsc8584_csr_write(bus, phy0, 0x16b4, 0x00000814);
+ vsc8584_csr_write(bus, phy0, 0x0f90, 0x00688980);
+ vsc8584_csr_write(bus, phy0, 0x03a4, 0x0000d8f0);
+ vsc8584_csr_write(bus, phy0, 0x0fc0, 0x00000400);
+ vsc8584_csr_write(bus, phy0, 0x07fa, 0x0050100f);
+ vsc8584_csr_write(bus, phy0, 0x0796, 0x00000003);
+ vsc8584_csr_write(bus, phy0, 0x07f8, 0x00c3ff98);
+ vsc8584_csr_write(bus, phy0, 0x0fa4, 0x0018292a);
+ vsc8584_csr_write(bus, phy0, 0x168c, 0x00d2c46f);
+ vsc8584_csr_write(bus, phy0, 0x17a2, 0x00000620);
+ vsc8584_csr_write(bus, phy0, 0x16a4, 0x0013132f);
+ vsc8584_csr_write(bus, phy0, 0x16a8, 0x00000000);
+ vsc8584_csr_write(bus, phy0, 0x0ffc, 0x00c0a028);
+ vsc8584_csr_write(bus, phy0, 0x0fec, 0x00901c09);
+ vsc8584_csr_write(bus, phy0, 0x0fee, 0x0004a6a1);
+ vsc8584_csr_write(bus, phy0, 0x0ffe, 0x00b01807);
+
+ bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS,
+ MSCC_PHY_PAGE_EXT2);
+
+ bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_PHY_CU_PMD_TX_CNTL, 0x028e);
+
+ bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS,
+ MSCC_PHY_PAGE_TR);
+
+ vsc8584_csr_write(bus, phy0, 0x0486, 0x0008a518);
+ vsc8584_csr_write(bus, phy0, 0x0488, 0x006dc696);
+ vsc8584_csr_write(bus, phy0, 0x048a, 0x00000912);
+ vsc8584_csr_write(bus, phy0, 0x048e, 0x00000db6);
+ vsc8584_csr_write(bus, phy0, 0x049c, 0x00596596);
+ vsc8584_csr_write(bus, phy0, 0x049e, 0x00000514);
+ vsc8584_csr_write(bus, phy0, 0x04a2, 0x00410280);
+ vsc8584_csr_write(bus, phy0, 0x04a4, 0x00000000);
+ vsc8584_csr_write(bus, phy0, 0x04a6, 0x00000000);
+ vsc8584_csr_write(bus, phy0, 0x04a8, 0x00000000);
+ vsc8584_csr_write(bus, phy0, 0x04aa, 0x00000000);
+ vsc8584_csr_write(bus, phy0, 0x04ae, 0x007df7dd);
+ vsc8584_csr_write(bus, phy0, 0x04b0, 0x006d95d4);
+ vsc8584_csr_write(bus, phy0, 0x04b2, 0x00492410);
+
+ bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS,
+ MSCC_PHY_PAGE_TEST);
+
+ reg = bus->read(bus, phy0, MDIO_DEVAD_NONE, MSCC_PHY_TEST_PAGE_8);
+ reg &= ~TR_CLK_DISABLE;
+ bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_PHY_TEST_PAGE_8, reg);
+
+ bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS,
+ MSCC_PHY_PAGE_STD);
+
+ /* end of write broadcasting */
+ reg = bus->read(bus, phy0, MDIO_DEVAD_NONE, MSCC_PHY_EXT_CNTL_STATUS);
+ reg &= ~SMI_BROADCAST_WR_EN;
+ bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_PHY_EXT_CNTL_STATUS, reg);
+
+ ret = vsc8584_get_fw_crc(bus, phy0,
+ MSCC_VSC8574_REVB_INT8051_FW_START_ADDR, &crc,
+ fw_patch_vsc8574,
+ ARRAY_SIZE(fw_patch_vsc8574));
+ if (ret)
+ goto out;
+
+ if (crc == MSCC_VSC8574_REVB_INT8051_FW_CRC) {
+ serdes_init = vsc8574_is_serdes_init(bus, phy0);
+
+ if (!serdes_init) {
+ ret = vsc8584_micro_assert_reset(bus, phy0);
+ if (ret) {
+ pr_err("failed to assert reset of micro\n");
+ return ret;
+ }
+ }
+ } else {
+ pr_debug("FW CRC is not the expected one, patching FW\n");
+
+ serdes_init = false;
+
+ if (vsc8584_patch_fw(bus, phy0, fw_patch_vsc8574,
+ ARRAY_SIZE(fw_patch_vsc8574)))
+ pr_warn("failed to patch FW, expect non-optimal device\n");
+ }
+
+ if (!serdes_init) {
+ bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS,
+ MSCC_PHY_PAGE_GPIO);
+
+ bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_TRAP_ROM_ADDR(1),
+ MSCC_TRAP_ROM_ADDR_SERDES_INIT);
+ bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_PATCH_RAM_ADDR(1),
+ MSCC_PATCH_RAM_ADDR_SERDES_INIT);
+
+ bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_INT_MEM_CNTL,
+ EN_PATCH_RAM_TRAP_ADDR(1));
+
+ vsc8584_micro_deassert_reset(bus, phy0, false);
+
+ ret = vsc8584_get_fw_crc(bus, phy0,
+ MSCC_VSC8574_REVB_INT8051_FW_START_ADDR,
+ &crc, fw_patch_vsc8574,
+ ARRAY_SIZE(fw_patch_vsc8574));
+ if (ret)
+ goto out;
+
+ if (crc != MSCC_VSC8574_REVB_INT8051_FW_CRC)
+ pr_warn("FW CRC after patching is not the expected one, expect non-optimal device\n");
+ }
+
+ bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS,
+ MSCC_PHY_PAGE_GPIO);
+
+ ret = vsc8584_cmd(bus, phy0, PROC_CMD_1588_DEFAULT_INIT |
+ PROC_CMD_PHY_INIT);
+
+out:
+ bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS,
+ MSCC_PHY_PAGE_STD);
+
+ return ret;
+}
+
+static int vsc8584_config_pre_init(struct phy_device *phydev)
+{
+ struct mii_dev *bus = phydev->bus;
+ u16 reg, crc, phy0, addr;
+ int ret;
+
+ if ((phydev->phy_id & MSCC_DEV_REV_MASK) != VSC8584_REVB) {
+ pr_warn("VSC8584 revA not officially supported, skipping firmware patching. Use at your own risk.\n");
+ return 0;
+ }
+
+ phy_write(phydev, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS,
+ MSCC_PHY_PAGE_EXT1);
+ addr = phy_read(phydev, MDIO_DEVAD_NONE, MSCC_PHY_EXT_PHY_CNTL_4);
+ addr >>= PHY_CNTL_4_ADDR_POS;
+
+ reg = phy_read(phydev, MDIO_DEVAD_NONE, MSCC_PHY_ACTIPHY_CNTL);
+ if (reg & PHY_ADDR_REVERSED)
+ phy0 = phydev->addr + addr;
+ else
+ phy0 = phydev->addr - addr;
+
+ bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS,
+ MSCC_PHY_PAGE_STD);
+
+ /* all writes below are broadcasted to all PHYs in the same package */
+ reg = bus->read(bus, phy0, MDIO_DEVAD_NONE, MSCC_PHY_EXT_CNTL_STATUS);
+ reg |= SMI_BROADCAST_WR_EN;
+ bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_PHY_EXT_CNTL_STATUS, reg);
+
+ /*
+ * The below register writes are tweaking analog and electrical
+ * configuration that were determined through characterization by PHY
+ * engineers. These don't mean anything more than "these are the best
+ * values".
+ */
+ reg = bus->read(bus, phy0, MDIO_DEVAD_NONE, MSCC_PHY_BYPASS_CONTROL);
+ reg |= PARALLEL_DET_IGNORE_ADVERTISED;
+ bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_PHY_BYPASS_CONTROL, reg);
+
+ bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS,
+ MSCC_PHY_PAGE_EXT3);
+
+ bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_PHY_SERDES_TX_CRC_ERR_CNT,
+ 0x2000);
+
+ bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS,
+ MSCC_PHY_PAGE_TEST);
+
+ bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_PHY_TEST_PAGE_5, 0x1f20);
+
+ reg = bus->read(bus, phy0, MDIO_DEVAD_NONE, MSCC_PHY_TEST_PAGE_8);
+ reg |= TR_CLK_DISABLE;
+ bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_PHY_TEST_PAGE_8, reg);
+
+ bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS,
+ MSCC_PHY_PAGE_TR);
+
+ bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_ADDR_16, 0xafa4);
+
+ reg = bus->read(bus, phy0, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_DATA_18);
+ reg &= ~0x007f;
+ reg |= 0x0019;
+ bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_DATA_18, reg);
+
+ bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_ADDR_16, 0x8fa4);
+
+ vsc8584_csr_write(bus, phy0, 0x07fa, 0x0050100f);
+ vsc8584_csr_write(bus, phy0, 0x1688, 0x00049f81);
+ vsc8584_csr_write(bus, phy0, 0x0f90, 0x00688980);
+ vsc8584_csr_write(bus, phy0, 0x03a4, 0x0000d8f0);
+ vsc8584_csr_write(bus, phy0, 0x0fc0, 0x00000400);
+ vsc8584_csr_write(bus, phy0, 0x0f82, 0x0012b002);
+ vsc8584_csr_write(bus, phy0, 0x1686, 0x00000004);
+ vsc8584_csr_write(bus, phy0, 0x168c, 0x00d2c46f);
+ vsc8584_csr_write(bus, phy0, 0x17a2, 0x00000620);
+ vsc8584_csr_write(bus, phy0, 0x16a0, 0x00eeffdd);
+ vsc8584_csr_write(bus, phy0, 0x16a6, 0x00071448);
+ vsc8584_csr_write(bus, phy0, 0x16a4, 0x0013132f);
+ vsc8584_csr_write(bus, phy0, 0x16a8, 0x00000000);
+ vsc8584_csr_write(bus, phy0, 0x0ffc, 0x00c0a028);
+ vsc8584_csr_write(bus, phy0, 0x0fe8, 0x0091b06c);
+ vsc8584_csr_write(bus, phy0, 0x0fea, 0x00041600);
+ vsc8584_csr_write(bus, phy0, 0x0f80, 0x00fffaff);
+ vsc8584_csr_write(bus, phy0, 0x0fec, 0x00901809);
+ vsc8584_csr_write(bus, phy0, 0x0ffe, 0x00b01007);
+ vsc8584_csr_write(bus, phy0, 0x16b0, 0x00eeff00);
+ vsc8584_csr_write(bus, phy0, 0x16b2, 0x00007000);
+ vsc8584_csr_write(bus, phy0, 0x16b4, 0x00000814);
+
+ bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS,
+ MSCC_PHY_PAGE_EXT2);
+
+ bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_PHY_CU_PMD_TX_CNTL, 0x028e);
+
+ bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS,
+ MSCC_PHY_PAGE_TR);
+
+ vsc8584_csr_write(bus, phy0, 0x0486, 0x0008a518);
+ vsc8584_csr_write(bus, phy0, 0x0488, 0x006dc696);
+ vsc8584_csr_write(bus, phy0, 0x048a, 0x00000912);
+
+ bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS,
+ MSCC_PHY_PAGE_TEST);
+
+ reg = bus->read(bus, phy0, MDIO_DEVAD_NONE, MSCC_PHY_TEST_PAGE_8);
+ reg &= ~TR_CLK_DISABLE;
+ bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_PHY_TEST_PAGE_8, reg);
+
+ bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS,
+ MSCC_PHY_PAGE_STD);
+
+ /* end of write broadcasting */
+ reg = bus->read(bus, phy0, MDIO_DEVAD_NONE, MSCC_PHY_EXT_CNTL_STATUS);
+ reg &= ~SMI_BROADCAST_WR_EN;
+ bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_PHY_EXT_CNTL_STATUS, reg);
+
+ ret = vsc8584_get_fw_crc(bus, phy0,
+ MSCC_VSC8584_REVB_INT8051_FW_START_ADDR, &crc,
+ fw_patch_vsc8584,
+ ARRAY_SIZE(fw_patch_vsc8584));
+ if (ret)
+ goto out;
+
+ if (crc != MSCC_VSC8584_REVB_INT8051_FW_CRC) {
+ debug("FW CRC is not the expected one, patching FW...\n");
+ if (vsc8584_patch_fw(bus, phy0, fw_patch_vsc8584,
+ ARRAY_SIZE(fw_patch_vsc8584)))
+ pr_warn("failed to patch FW, expect non-optimal device\n");
+ }
+
+ vsc8584_micro_deassert_reset(bus, phy0, false);
+
+ ret = vsc8584_get_fw_crc(bus, phy0,
+ MSCC_VSC8584_REVB_INT8051_FW_START_ADDR, &crc,
+ fw_patch_vsc8584,
+ ARRAY_SIZE(fw_patch_vsc8584));
+ if (ret)
+ goto out;
+
+ if (crc != MSCC_VSC8584_REVB_INT8051_FW_CRC)
+ pr_warn("FW CRC after patching is not the expected one, expect non-optimal device\n");
+
+ ret = vsc8584_micro_assert_reset(bus, phy0);
+ if (ret)
+ goto out;
+
+ vsc8584_micro_deassert_reset(bus, phy0, true);
+
+out:
+ bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS,
+ MSCC_PHY_PAGE_STD);
+
+ return ret;
+}
static int mscc_vsc8531_vsc8541_init_scripts(struct phy_device *phydev)
{
return genphy_config_aneg(phydev);
}
+static int vsc8584_config_init(struct phy_device *phydev)
+{
+ struct vsc85xx_priv *priv = phydev->priv;
+ int ret;
+ u16 addr;
+ u16 reg_val;
+ u16 val;
+
+ phy_write(phydev, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS,
+ MSCC_PHY_PAGE_EXT1);
+ addr = phy_read(phydev, MDIO_DEVAD_NONE, MSCC_PHY_EXT_PHY_CNTL_4);
+ addr >>= PHY_CNTL_4_ADDR_POS;
+
+ ret = priv->config_pre(phydev);
+ if (ret)
+ return ret;
+
+ phy_write(phydev, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS,
+ MSCC_PHY_PAGE_GPIO);
+
+ if (phydev->interface == PHY_INTERFACE_MODE_QSGMII)
+ val = MAC_CFG_QSGMII;
+ else
+ val = MAC_CFG_SGMII;
+
+ reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MSCC_PHY_MAC_CFG_FASTLINK);
+ reg_val &= ~MAC_CFG_MASK;
+ reg_val |= val;
+ ret = phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_MAC_CFG_FASTLINK,
+ reg_val);
+ if (ret)
+ return ret;
+
+ reg_val = PROC_CMD_MCB_ACCESS_MAC_CONF | PROC_CMD_RST_CONF_PORT |
+ PROC_CMD_READ_MOD_WRITE_PORT;
+ if (phydev->interface == PHY_INTERFACE_MODE_QSGMII)
+ reg_val |= PROC_CMD_QSGMII_MAC;
+ else
+ reg_val |= PROC_CMD_SGMII_MAC;
+
+ ret = vsc8584_cmd(phydev->bus, phydev->addr, reg_val);
+ if (ret)
+ return ret;
+
+ mdelay(10);
+
+ /* Disable SerDes for 100Base-FX */
+ ret = vsc8584_cmd(phydev->bus, phydev->addr, PROC_CMD_FIBER_MEDIA_CONF |
+ PROC_CMD_FIBER_PORT(addr) | PROC_CMD_FIBER_DISABLE |
+ PROC_CMD_READ_MOD_WRITE_PORT |
+ PROC_CMD_RST_CONF_PORT | PROC_CMD_FIBER_100BASE_FX);
+ if (ret)
+ return ret;
+
+ /* Disable SerDes for 1000Base-X */
+ ret = vsc8584_cmd(phydev->bus, phydev->addr, PROC_CMD_FIBER_MEDIA_CONF |
+ PROC_CMD_FIBER_PORT(addr) | PROC_CMD_FIBER_DISABLE |
+ PROC_CMD_READ_MOD_WRITE_PORT |
+ PROC_CMD_RST_CONF_PORT | PROC_CMD_FIBER_1000BASE_X);
+ if (ret)
+ return ret;
+
+ phy_write(phydev, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS,
+ MSCC_PHY_PAGE_STD);
+ reg_val = phy_read(phydev, MDIO_DEVAD_NONE,
+ MSCC_PHY_EXT_PHY_CNTL_1_REG);
+ reg_val &= ~(MEDIA_OP_MODE_MASK | VSC8584_MAC_IF_SELECTION_MASK);
+ reg_val |= MEDIA_OP_MODE_COPPER |
+ (VSC8584_MAC_IF_SELECTION_SGMII <<
+ VSC8584_MAC_IF_SELECTION_POS);
+ ret = phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_EXT_PHY_CNTL_1_REG,
+ reg_val);
+
+ ret = mscc_phy_soft_reset(phydev);
+ if (ret != 0)
+ return ret;
+
+ return genphy_config(phydev);
+}
+
+static struct vsc85xx_priv vsc8574_priv = {
+ .config_pre = vsc8574_config_pre_init,
+};
+
+static int vsc8574_config(struct phy_device *phydev)
+{
+ phydev->priv = &vsc8574_priv;
+
+ return vsc8584_config_init(phydev);
+}
+
+static struct vsc85xx_priv vsc8584_priv = {
+ .config_pre = vsc8584_config_pre_init,
+};
+
+static int vsc8584_config(struct phy_device *phydev)
+{
+ phydev->priv = &vsc8584_priv;
+
+ return vsc8584_config_init(phydev);
+}
+
static struct phy_driver VSC8530_driver = {
.name = "Microsemi VSC8530",
.uid = PHY_ID_VSC8530,
.shutdown = &genphy_shutdown,
};
+static struct phy_driver VSC8574_driver = {
+ .name = "Microsemi VSC8574",
+ .uid = PHY_ID_VSC8574,
+ .mask = 0x000ffff0,
+ .features = PHY_GBIT_FEATURES,
+ .config = &vsc8574_config,
+ .startup = &mscc_startup,
+ .shutdown = &genphy_shutdown,
+};
+
+static struct phy_driver VSC8584_driver = {
+ .name = "Microsemi VSC8584",
+ .uid = PHY_ID_VSC8584,
+ .mask = 0x000ffff0,
+ .features = PHY_GBIT_FEATURES,
+ .config = &vsc8584_config,
+ .startup = &mscc_startup,
+ .shutdown = &genphy_shutdown,
+};
+
int phy_mscc_init(void)
{
phy_register(&VSC8530_driver);
phy_register(&VSC8531_driver);
phy_register(&VSC8540_driver);
phy_register(&VSC8541_driver);
+ phy_register(&VSC8574_driver);
+ phy_register(&VSC8584_driver);
return 0;
}
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+
+config DRIVER_TI_CPSW
+ bool "TI Common Platform Ethernet Switch"
+ select PHYLIB
+ help
+ This driver supports the TI three port switch gigabit ethernet
+ subsystem found in the TI SoCs.
+
+config DRIVER_TI_EMAC
+ bool "TI Davinci EMAC"
+ help
+ Support for davinci emac
+
+config DRIVER_TI_KEYSTONE_NET
+ bool "TI Keystone 2 Ethernet"
+ help
+ This driver supports the TI Keystone 2 Ethernet subsystem
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+
+obj-$(CONFIG_DRIVER_TI_CPSW) += cpsw.o cpsw-common.o cpsw_mdio.o
+obj-$(CONFIG_DRIVER_TI_EMAC) += davinci_emac.o
+obj-$(CONFIG_DRIVER_TI_KEYSTONE_NET) += keystone_net.o cpsw_mdio.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * CPSW common - libs used across TI ethernet devices.
+ *
+ * Copyright (C) 2016, Texas Instruments, Incorporated
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <asm/io.h>
+#include <cpsw.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define CTRL_MAC_REG(offset, id) ((offset) + 0x8 * (id))
+
+static int davinci_emac_3517_get_macid(struct udevice *dev, u16 offset,
+ int slave, u8 *mac_addr)
+{
+ void *fdt = (void *)gd->fdt_blob;
+ int node = dev_of_offset(dev);
+ u32 macid_lsb;
+ u32 macid_msb;
+ fdt32_t gmii = 0;
+ int syscon;
+ u32 addr;
+
+ syscon = fdtdec_lookup_phandle(fdt, node, "syscon");
+ if (syscon < 0) {
+ pr_err("Syscon offset not found\n");
+ return -ENOENT;
+ }
+
+ addr = (u32)map_physmem(fdt_translate_address(fdt, syscon, &gmii),
+ sizeof(u32), MAP_NOCACHE);
+ if (addr == FDT_ADDR_T_NONE) {
+ pr_err("Not able to get syscon address to get mac efuse address\n");
+ return -ENOENT;
+ }
+
+ addr += CTRL_MAC_REG(offset, slave);
+
+ /* try reading mac address from efuse */
+ macid_lsb = readl(addr);
+ macid_msb = readl(addr + 4);
+
+ mac_addr[0] = (macid_msb >> 16) & 0xff;
+ mac_addr[1] = (macid_msb >> 8) & 0xff;
+ mac_addr[2] = macid_msb & 0xff;
+ mac_addr[3] = (macid_lsb >> 16) & 0xff;
+ mac_addr[4] = (macid_lsb >> 8) & 0xff;
+ mac_addr[5] = macid_lsb & 0xff;
+
+ return 0;
+}
+
+static int cpsw_am33xx_cm_get_macid(struct udevice *dev, u16 offset, int slave,
+ u8 *mac_addr)
+{
+ void *fdt = (void *)gd->fdt_blob;
+ int node = dev_of_offset(dev);
+ u32 macid_lo;
+ u32 macid_hi;
+ fdt32_t gmii = 0;
+ int syscon;
+ u32 addr;
+
+ syscon = fdtdec_lookup_phandle(fdt, node, "syscon");
+ if (syscon < 0) {
+ pr_err("Syscon offset not found\n");
+ return -ENOENT;
+ }
+
+ addr = (u32)map_physmem(fdt_translate_address(fdt, syscon, &gmii),
+ sizeof(u32), MAP_NOCACHE);
+ if (addr == FDT_ADDR_T_NONE) {
+ pr_err("Not able to get syscon address to get mac efuse address\n");
+ return -ENOENT;
+ }
+
+ addr += CTRL_MAC_REG(offset, slave);
+
+ /* try reading mac address from efuse */
+ macid_lo = readl(addr);
+ macid_hi = readl(addr + 4);
+
+ mac_addr[5] = (macid_lo >> 8) & 0xff;
+ mac_addr[4] = macid_lo & 0xff;
+ mac_addr[3] = (macid_hi >> 24) & 0xff;
+ mac_addr[2] = (macid_hi >> 16) & 0xff;
+ mac_addr[1] = (macid_hi >> 8) & 0xff;
+ mac_addr[0] = macid_hi & 0xff;
+
+ return 0;
+}
+
+int ti_cm_get_macid(struct udevice *dev, int slave, u8 *mac_addr)
+{
+ if (of_machine_is_compatible("ti,dm8148"))
+ return cpsw_am33xx_cm_get_macid(dev, 0x630, slave, mac_addr);
+
+ if (of_machine_is_compatible("ti,am33xx"))
+ return cpsw_am33xx_cm_get_macid(dev, 0x630, slave, mac_addr);
+
+ if (device_is_compatible(dev, "ti,am3517-emac"))
+ return davinci_emac_3517_get_macid(dev, 0x110, slave, mac_addr);
+
+ if (device_is_compatible(dev, "ti,dm816-emac"))
+ return cpsw_am33xx_cm_get_macid(dev, 0x30, slave, mac_addr);
+
+ if (of_machine_is_compatible("ti,am43"))
+ return cpsw_am33xx_cm_get_macid(dev, 0x630, slave, mac_addr);
+
+ if (of_machine_is_compatible("ti,dra7"))
+ return davinci_emac_3517_get_macid(dev, 0x514, slave, mac_addr);
+
+ dev_err(dev, "incompatible machine/device type for reading mac address\n");
+ return -ENOENT;
+}
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * CPSW Ethernet Switch Driver
+ *
+ * Copyright (C) 2010-2018 Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+#include <common.h>
+#include <command.h>
+#include <net.h>
+#include <miiphy.h>
+#include <malloc.h>
+#include <net.h>
+#include <netdev.h>
+#include <cpsw.h>
+#include <linux/errno.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <phy.h>
+#include <asm/arch/cpu.h>
+#include <dm.h>
+#include <fdt_support.h>
+
+#include "cpsw_mdio.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define BITMASK(bits) (BIT(bits) - 1)
+#define NUM_DESCS (PKTBUFSRX * 2)
+#define PKT_MIN 60
+#define PKT_MAX (1500 + 14 + 4 + 4)
+#define CLEAR_BIT 1
+#define GIGABITEN BIT(7)
+#define FULLDUPLEXEN BIT(0)
+#define MIIEN BIT(15)
+
+/* reg offset */
+#define CPSW_HOST_PORT_OFFSET 0x108
+#define CPSW_SLAVE0_OFFSET 0x208
+#define CPSW_SLAVE1_OFFSET 0x308
+#define CPSW_SLAVE_SIZE 0x100
+#define CPSW_CPDMA_OFFSET 0x800
+#define CPSW_HW_STATS 0x900
+#define CPSW_STATERAM_OFFSET 0xa00
+#define CPSW_CPTS_OFFSET 0xc00
+#define CPSW_ALE_OFFSET 0xd00
+#define CPSW_SLIVER0_OFFSET 0xd80
+#define CPSW_SLIVER1_OFFSET 0xdc0
+#define CPSW_BD_OFFSET 0x2000
+#define CPSW_MDIO_DIV 0xff
+
+#define AM335X_GMII_SEL_OFFSET 0x630
+
+/* DMA Registers */
+#define CPDMA_TXCONTROL 0x004
+#define CPDMA_RXCONTROL 0x014
+#define CPDMA_SOFTRESET 0x01c
+#define CPDMA_RXFREE 0x0e0
+#define CPDMA_TXHDP_VER1 0x100
+#define CPDMA_TXHDP_VER2 0x200
+#define CPDMA_RXHDP_VER1 0x120
+#define CPDMA_RXHDP_VER2 0x220
+#define CPDMA_TXCP_VER1 0x140
+#define CPDMA_TXCP_VER2 0x240
+#define CPDMA_RXCP_VER1 0x160
+#define CPDMA_RXCP_VER2 0x260
+
+/* Descriptor mode bits */
+#define CPDMA_DESC_SOP BIT(31)
+#define CPDMA_DESC_EOP BIT(30)
+#define CPDMA_DESC_OWNER BIT(29)
+#define CPDMA_DESC_EOQ BIT(28)
+
+/*
+ * This timeout definition is a worst-case ultra defensive measure against
+ * unexpected controller lock ups. Ideally, we should never ever hit this
+ * scenario in practice.
+ */
+#define CPDMA_TIMEOUT 100 /* msecs */
+
+struct cpsw_regs {
+ u32 id_ver;
+ u32 control;
+ u32 soft_reset;
+ u32 stat_port_en;
+ u32 ptype;
+};
+
+struct cpsw_slave_regs {
+ u32 max_blks;
+ u32 blk_cnt;
+ u32 flow_thresh;
+ u32 port_vlan;
+ u32 tx_pri_map;
+#ifdef CONFIG_AM33XX
+ u32 gap_thresh;
+#elif defined(CONFIG_TI814X)
+ u32 ts_ctl;
+ u32 ts_seq_ltype;
+ u32 ts_vlan;
+#endif
+ u32 sa_lo;
+ u32 sa_hi;
+};
+
+struct cpsw_host_regs {
+ u32 max_blks;
+ u32 blk_cnt;
+ u32 flow_thresh;
+ u32 port_vlan;
+ u32 tx_pri_map;
+ u32 cpdma_tx_pri_map;
+ u32 cpdma_rx_chan_map;
+};
+
+struct cpsw_sliver_regs {
+ u32 id_ver;
+ u32 mac_control;
+ u32 mac_status;
+ u32 soft_reset;
+ u32 rx_maxlen;
+ u32 __reserved_0;
+ u32 rx_pause;
+ u32 tx_pause;
+ u32 __reserved_1;
+ u32 rx_pri_map;
+};
+
+#define ALE_ENTRY_BITS 68
+#define ALE_ENTRY_WORDS DIV_ROUND_UP(ALE_ENTRY_BITS, 32)
+
+/* ALE Registers */
+#define ALE_CONTROL 0x08
+#define ALE_UNKNOWNVLAN 0x18
+#define ALE_TABLE_CONTROL 0x20
+#define ALE_TABLE 0x34
+#define ALE_PORTCTL 0x40
+
+#define ALE_TABLE_WRITE BIT(31)
+
+#define ALE_TYPE_FREE 0
+#define ALE_TYPE_ADDR 1
+#define ALE_TYPE_VLAN 2
+#define ALE_TYPE_VLAN_ADDR 3
+
+#define ALE_UCAST_PERSISTANT 0
+#define ALE_UCAST_UNTOUCHED 1
+#define ALE_UCAST_OUI 2
+#define ALE_UCAST_TOUCHED 3
+
+#define ALE_MCAST_FWD 0
+#define ALE_MCAST_BLOCK_LEARN_FWD 1
+#define ALE_MCAST_FWD_LEARN 2
+#define ALE_MCAST_FWD_2 3
+
+enum cpsw_ale_port_state {
+ ALE_PORT_STATE_DISABLE = 0x00,
+ ALE_PORT_STATE_BLOCK = 0x01,
+ ALE_PORT_STATE_LEARN = 0x02,
+ ALE_PORT_STATE_FORWARD = 0x03,
+};
+
+/* ALE unicast entry flags - passed into cpsw_ale_add_ucast() */
+#define ALE_SECURE 1
+#define ALE_BLOCKED 2
+
+struct cpsw_slave {
+ struct cpsw_slave_regs *regs;
+ struct cpsw_sliver_regs *sliver;
+ int slave_num;
+ u32 mac_control;
+ struct cpsw_slave_data *data;
+};
+
+struct cpdma_desc {
+ /* hardware fields */
+ u32 hw_next;
+ u32 hw_buffer;
+ u32 hw_len;
+ u32 hw_mode;
+ /* software fields */
+ u32 sw_buffer;
+ u32 sw_len;
+};
+
+struct cpdma_chan {
+ struct cpdma_desc *head, *tail;
+ void *hdp, *cp, *rxfree;
+};
+
+/* AM33xx SoC specific definitions for the CONTROL port */
+#define AM33XX_GMII_SEL_MODE_MII 0
+#define AM33XX_GMII_SEL_MODE_RMII 1
+#define AM33XX_GMII_SEL_MODE_RGMII 2
+
+#define AM33XX_GMII_SEL_RGMII1_IDMODE BIT(4)
+#define AM33XX_GMII_SEL_RGMII2_IDMODE BIT(5)
+#define AM33XX_GMII_SEL_RMII1_IO_CLK_EN BIT(6)
+#define AM33XX_GMII_SEL_RMII2_IO_CLK_EN BIT(7)
+
+#define GMII_SEL_MODE_MASK 0x3
+
+#define desc_write(desc, fld, val) __raw_writel((u32)(val), &(desc)->fld)
+#define desc_read(desc, fld) __raw_readl(&(desc)->fld)
+#define desc_read_ptr(desc, fld) ((void *)__raw_readl(&(desc)->fld))
+
+#define chan_write(chan, fld, val) __raw_writel((u32)(val), (chan)->fld)
+#define chan_read(chan, fld) __raw_readl((chan)->fld)
+#define chan_read_ptr(chan, fld) ((void *)__raw_readl((chan)->fld))
+
+#define for_active_slave(slave, priv) \
+ slave = (priv)->slaves + (priv)->data.active_slave; if (slave)
+#define for_each_slave(slave, priv) \
+ for (slave = (priv)->slaves; slave != (priv)->slaves + \
+ (priv)->data.slaves; slave++)
+
+struct cpsw_priv {
+#ifdef CONFIG_DM_ETH
+ struct udevice *dev;
+#else
+ struct eth_device *dev;
+#endif
+ struct cpsw_platform_data data;
+ int host_port;
+
+ struct cpsw_regs *regs;
+ void *dma_regs;
+ struct cpsw_host_regs *host_port_regs;
+ void *ale_regs;
+
+ struct cpdma_desc *descs;
+ struct cpdma_desc *desc_free;
+ struct cpdma_chan rx_chan, tx_chan;
+
+ struct cpsw_slave *slaves;
+ struct phy_device *phydev;
+ struct mii_dev *bus;
+
+ u32 phy_mask;
+};
+
+static inline int cpsw_ale_get_field(u32 *ale_entry, u32 start, u32 bits)
+{
+ int idx;
+
+ idx = start / 32;
+ start -= idx * 32;
+ idx = 2 - idx; /* flip */
+ return (ale_entry[idx] >> start) & BITMASK(bits);
+}
+
+static inline void cpsw_ale_set_field(u32 *ale_entry, u32 start, u32 bits,
+ u32 value)
+{
+ int idx;
+
+ value &= BITMASK(bits);
+ idx = start / 32;
+ start -= idx * 32;
+ idx = 2 - idx; /* flip */
+ ale_entry[idx] &= ~(BITMASK(bits) << start);
+ ale_entry[idx] |= (value << start);
+}
+
+#define DEFINE_ALE_FIELD(name, start, bits) \
+static inline int cpsw_ale_get_##name(u32 *ale_entry) \
+{ \
+ return cpsw_ale_get_field(ale_entry, start, bits); \
+} \
+static inline void cpsw_ale_set_##name(u32 *ale_entry, u32 value) \
+{ \
+ cpsw_ale_set_field(ale_entry, start, bits, value); \
+}
+
+DEFINE_ALE_FIELD(entry_type, 60, 2)
+DEFINE_ALE_FIELD(mcast_state, 62, 2)
+DEFINE_ALE_FIELD(port_mask, 66, 3)
+DEFINE_ALE_FIELD(ucast_type, 62, 2)
+DEFINE_ALE_FIELD(port_num, 66, 2)
+DEFINE_ALE_FIELD(blocked, 65, 1)
+DEFINE_ALE_FIELD(secure, 64, 1)
+DEFINE_ALE_FIELD(mcast, 40, 1)
+
+/* The MAC address field in the ALE entry cannot be macroized as above */
+static inline void cpsw_ale_get_addr(u32 *ale_entry, u8 *addr)
+{
+ int i;
+
+ for (i = 0; i < 6; i++)
+ addr[i] = cpsw_ale_get_field(ale_entry, 40 - 8*i, 8);
+}
+
+static inline void cpsw_ale_set_addr(u32 *ale_entry, const u8 *addr)
+{
+ int i;
+
+ for (i = 0; i < 6; i++)
+ cpsw_ale_set_field(ale_entry, 40 - 8*i, 8, addr[i]);
+}
+
+static int cpsw_ale_read(struct cpsw_priv *priv, int idx, u32 *ale_entry)
+{
+ int i;
+
+ __raw_writel(idx, priv->ale_regs + ALE_TABLE_CONTROL);
+
+ for (i = 0; i < ALE_ENTRY_WORDS; i++)
+ ale_entry[i] = __raw_readl(priv->ale_regs + ALE_TABLE + 4 * i);
+
+ return idx;
+}
+
+static int cpsw_ale_write(struct cpsw_priv *priv, int idx, u32 *ale_entry)
+{
+ int i;
+
+ for (i = 0; i < ALE_ENTRY_WORDS; i++)
+ __raw_writel(ale_entry[i], priv->ale_regs + ALE_TABLE + 4 * i);
+
+ __raw_writel(idx | ALE_TABLE_WRITE, priv->ale_regs + ALE_TABLE_CONTROL);
+
+ return idx;
+}
+
+static int cpsw_ale_match_addr(struct cpsw_priv *priv, const u8 *addr)
+{
+ u32 ale_entry[ALE_ENTRY_WORDS];
+ int type, idx;
+
+ for (idx = 0; idx < priv->data.ale_entries; idx++) {
+ u8 entry_addr[6];
+
+ cpsw_ale_read(priv, idx, ale_entry);
+ type = cpsw_ale_get_entry_type(ale_entry);
+ if (type != ALE_TYPE_ADDR && type != ALE_TYPE_VLAN_ADDR)
+ continue;
+ cpsw_ale_get_addr(ale_entry, entry_addr);
+ if (memcmp(entry_addr, addr, 6) == 0)
+ return idx;
+ }
+ return -ENOENT;
+}
+
+static int cpsw_ale_match_free(struct cpsw_priv *priv)
+{
+ u32 ale_entry[ALE_ENTRY_WORDS];
+ int type, idx;
+
+ for (idx = 0; idx < priv->data.ale_entries; idx++) {
+ cpsw_ale_read(priv, idx, ale_entry);
+ type = cpsw_ale_get_entry_type(ale_entry);
+ if (type == ALE_TYPE_FREE)
+ return idx;
+ }
+ return -ENOENT;
+}
+
+static int cpsw_ale_find_ageable(struct cpsw_priv *priv)
+{
+ u32 ale_entry[ALE_ENTRY_WORDS];
+ int type, idx;
+
+ for (idx = 0; idx < priv->data.ale_entries; idx++) {
+ cpsw_ale_read(priv, idx, ale_entry);
+ type = cpsw_ale_get_entry_type(ale_entry);
+ if (type != ALE_TYPE_ADDR && type != ALE_TYPE_VLAN_ADDR)
+ continue;
+ if (cpsw_ale_get_mcast(ale_entry))
+ continue;
+ type = cpsw_ale_get_ucast_type(ale_entry);
+ if (type != ALE_UCAST_PERSISTANT &&
+ type != ALE_UCAST_OUI)
+ return idx;
+ }
+ return -ENOENT;
+}
+
+static int cpsw_ale_add_ucast(struct cpsw_priv *priv, const u8 *addr,
+ int port, int flags)
+{
+ u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
+ int idx;
+
+ cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_ADDR);
+ cpsw_ale_set_addr(ale_entry, addr);
+ cpsw_ale_set_ucast_type(ale_entry, ALE_UCAST_PERSISTANT);
+ cpsw_ale_set_secure(ale_entry, (flags & ALE_SECURE) ? 1 : 0);
+ cpsw_ale_set_blocked(ale_entry, (flags & ALE_BLOCKED) ? 1 : 0);
+ cpsw_ale_set_port_num(ale_entry, port);
+
+ idx = cpsw_ale_match_addr(priv, addr);
+ if (idx < 0)
+ idx = cpsw_ale_match_free(priv);
+ if (idx < 0)
+ idx = cpsw_ale_find_ageable(priv);
+ if (idx < 0)
+ return -ENOMEM;
+
+ cpsw_ale_write(priv, idx, ale_entry);
+ return 0;
+}
+
+static int cpsw_ale_add_mcast(struct cpsw_priv *priv, const u8 *addr,
+ int port_mask)
+{
+ u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
+ int idx, mask;
+
+ idx = cpsw_ale_match_addr(priv, addr);
+ if (idx >= 0)
+ cpsw_ale_read(priv, idx, ale_entry);
+
+ cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_ADDR);
+ cpsw_ale_set_addr(ale_entry, addr);
+ cpsw_ale_set_mcast_state(ale_entry, ALE_MCAST_FWD_2);
+
+ mask = cpsw_ale_get_port_mask(ale_entry);
+ port_mask |= mask;
+ cpsw_ale_set_port_mask(ale_entry, port_mask);
+
+ if (idx < 0)
+ idx = cpsw_ale_match_free(priv);
+ if (idx < 0)
+ idx = cpsw_ale_find_ageable(priv);
+ if (idx < 0)
+ return -ENOMEM;
+
+ cpsw_ale_write(priv, idx, ale_entry);
+ return 0;
+}
+
+static inline void cpsw_ale_control(struct cpsw_priv *priv, int bit, int val)
+{
+ u32 tmp, mask = BIT(bit);
+
+ tmp = __raw_readl(priv->ale_regs + ALE_CONTROL);
+ tmp &= ~mask;
+ tmp |= val ? mask : 0;
+ __raw_writel(tmp, priv->ale_regs + ALE_CONTROL);
+}
+
+#define cpsw_ale_enable(priv, val) cpsw_ale_control(priv, 31, val)
+#define cpsw_ale_clear(priv, val) cpsw_ale_control(priv, 30, val)
+#define cpsw_ale_vlan_aware(priv, val) cpsw_ale_control(priv, 2, val)
+
+static inline void cpsw_ale_port_state(struct cpsw_priv *priv, int port,
+ int val)
+{
+ int offset = ALE_PORTCTL + 4 * port;
+ u32 tmp, mask = 0x3;
+
+ tmp = __raw_readl(priv->ale_regs + offset);
+ tmp &= ~mask;
+ tmp |= val & mask;
+ __raw_writel(tmp, priv->ale_regs + offset);
+}
+
+/* Set a self-clearing bit in a register, and wait for it to clear */
+static inline void setbit_and_wait_for_clear32(void *addr)
+{
+ __raw_writel(CLEAR_BIT, addr);
+ while (__raw_readl(addr) & CLEAR_BIT)
+ ;
+}
+
+#define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \
+ ((mac)[2] << 16) | ((mac)[3] << 24))
+#define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8))
+
+static void cpsw_set_slave_mac(struct cpsw_slave *slave,
+ struct cpsw_priv *priv)
+{
+#ifdef CONFIG_DM_ETH
+ struct eth_pdata *pdata = dev_get_platdata(priv->dev);
+
+ writel(mac_hi(pdata->enetaddr), &slave->regs->sa_hi);
+ writel(mac_lo(pdata->enetaddr), &slave->regs->sa_lo);
+#else
+ __raw_writel(mac_hi(priv->dev->enetaddr), &slave->regs->sa_hi);
+ __raw_writel(mac_lo(priv->dev->enetaddr), &slave->regs->sa_lo);
+#endif
+}
+
+static int cpsw_slave_update_link(struct cpsw_slave *slave,
+ struct cpsw_priv *priv, int *link)
+{
+ struct phy_device *phy;
+ u32 mac_control = 0;
+ int ret = -ENODEV;
+
+ phy = priv->phydev;
+ if (!phy)
+ goto out;
+
+ ret = phy_startup(phy);
+ if (ret)
+ goto out;
+
+ if (link)
+ *link = phy->link;
+
+ if (phy->link) { /* link up */
+ mac_control = priv->data.mac_control;
+ if (phy->speed == 1000)
+ mac_control |= GIGABITEN;
+ if (phy->duplex == DUPLEX_FULL)
+ mac_control |= FULLDUPLEXEN;
+ if (phy->speed == 100)
+ mac_control |= MIIEN;
+ }
+
+ if (mac_control == slave->mac_control)
+ goto out;
+
+ if (mac_control) {
+ printf("link up on port %d, speed %d, %s duplex\n",
+ slave->slave_num, phy->speed,
+ (phy->duplex == DUPLEX_FULL) ? "full" : "half");
+ } else {
+ printf("link down on port %d\n", slave->slave_num);
+ }
+
+ __raw_writel(mac_control, &slave->sliver->mac_control);
+ slave->mac_control = mac_control;
+
+out:
+ return ret;
+}
+
+static int cpsw_update_link(struct cpsw_priv *priv)
+{
+ int ret = -ENODEV;
+ struct cpsw_slave *slave;
+
+ for_active_slave(slave, priv)
+ ret = cpsw_slave_update_link(slave, priv, NULL);
+
+ return ret;
+}
+
+static inline u32 cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num)
+{
+ if (priv->host_port == 0)
+ return slave_num + 1;
+ else
+ return slave_num;
+}
+
+static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv)
+{
+ u32 slave_port;
+
+ setbit_and_wait_for_clear32(&slave->sliver->soft_reset);
+
+ /* setup priority mapping */
+ __raw_writel(0x76543210, &slave->sliver->rx_pri_map);
+ __raw_writel(0x33221100, &slave->regs->tx_pri_map);
+
+ /* setup max packet size, and mac address */
+ __raw_writel(PKT_MAX, &slave->sliver->rx_maxlen);
+ cpsw_set_slave_mac(slave, priv);
+
+ slave->mac_control = 0; /* no link yet */
+
+ /* enable forwarding */
+ slave_port = cpsw_get_slave_port(priv, slave->slave_num);
+ cpsw_ale_port_state(priv, slave_port, ALE_PORT_STATE_FORWARD);
+
+ cpsw_ale_add_mcast(priv, net_bcast_ethaddr, 1 << slave_port);
+
+ priv->phy_mask |= 1 << slave->data->phy_addr;
+}
+
+static struct cpdma_desc *cpdma_desc_alloc(struct cpsw_priv *priv)
+{
+ struct cpdma_desc *desc = priv->desc_free;
+
+ if (desc)
+ priv->desc_free = desc_read_ptr(desc, hw_next);
+ return desc;
+}
+
+static void cpdma_desc_free(struct cpsw_priv *priv, struct cpdma_desc *desc)
+{
+ if (desc) {
+ desc_write(desc, hw_next, priv->desc_free);
+ priv->desc_free = desc;
+ }
+}
+
+static int cpdma_submit(struct cpsw_priv *priv, struct cpdma_chan *chan,
+ void *buffer, int len)
+{
+ struct cpdma_desc *desc, *prev;
+ u32 mode;
+
+ desc = cpdma_desc_alloc(priv);
+ if (!desc)
+ return -ENOMEM;
+
+ if (len < PKT_MIN)
+ len = PKT_MIN;
+
+ mode = CPDMA_DESC_OWNER | CPDMA_DESC_SOP | CPDMA_DESC_EOP;
+
+ desc_write(desc, hw_next, 0);
+ desc_write(desc, hw_buffer, buffer);
+ desc_write(desc, hw_len, len);
+ desc_write(desc, hw_mode, mode | len);
+ desc_write(desc, sw_buffer, buffer);
+ desc_write(desc, sw_len, len);
+
+ if (!chan->head) {
+ /* simple case - first packet enqueued */
+ chan->head = desc;
+ chan->tail = desc;
+ chan_write(chan, hdp, desc);
+ goto done;
+ }
+
+ /* not the first packet - enqueue at the tail */
+ prev = chan->tail;
+ desc_write(prev, hw_next, desc);
+ chan->tail = desc;
+
+ /* next check if EOQ has been triggered already */
+ if (desc_read(prev, hw_mode) & CPDMA_DESC_EOQ)
+ chan_write(chan, hdp, desc);
+
+done:
+ if (chan->rxfree)
+ chan_write(chan, rxfree, 1);
+ return 0;
+}
+
+static int cpdma_process(struct cpsw_priv *priv, struct cpdma_chan *chan,
+ void **buffer, int *len)
+{
+ struct cpdma_desc *desc = chan->head;
+ u32 status;
+
+ if (!desc)
+ return -ENOENT;
+
+ status = desc_read(desc, hw_mode);
+
+ if (len)
+ *len = status & 0x7ff;
+
+ if (buffer)
+ *buffer = desc_read_ptr(desc, sw_buffer);
+
+ if (status & CPDMA_DESC_OWNER) {
+ if (chan_read(chan, hdp) == 0) {
+ if (desc_read(desc, hw_mode) & CPDMA_DESC_OWNER)
+ chan_write(chan, hdp, desc);
+ }
+
+ return -EBUSY;
+ }
+
+ chan->head = desc_read_ptr(desc, hw_next);
+ chan_write(chan, cp, desc);
+
+ cpdma_desc_free(priv, desc);
+ return 0;
+}
+
+static int _cpsw_init(struct cpsw_priv *priv, u8 *enetaddr)
+{
+ struct cpsw_slave *slave;
+ int i, ret;
+
+ /* soft reset the controller and initialize priv */
+ setbit_and_wait_for_clear32(&priv->regs->soft_reset);
+
+ /* initialize and reset the address lookup engine */
+ cpsw_ale_enable(priv, 1);
+ cpsw_ale_clear(priv, 1);
+ cpsw_ale_vlan_aware(priv, 0); /* vlan unaware mode */
+
+ /* setup host port priority mapping */
+ __raw_writel(0x76543210, &priv->host_port_regs->cpdma_tx_pri_map);
+ __raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map);
+
+ /* disable priority elevation and enable statistics on all ports */
+ __raw_writel(0, &priv->regs->ptype);
+
+ /* enable statistics collection only on the host port */
+ __raw_writel(BIT(priv->host_port), &priv->regs->stat_port_en);
+ __raw_writel(0x7, &priv->regs->stat_port_en);
+
+ cpsw_ale_port_state(priv, priv->host_port, ALE_PORT_STATE_FORWARD);
+
+ cpsw_ale_add_ucast(priv, enetaddr, priv->host_port, ALE_SECURE);
+ cpsw_ale_add_mcast(priv, net_bcast_ethaddr, 1 << priv->host_port);
+
+ for_active_slave(slave, priv)
+ cpsw_slave_init(slave, priv);
+
+ ret = cpsw_update_link(priv);
+ if (ret)
+ goto out;
+
+ /* init descriptor pool */
+ for (i = 0; i < NUM_DESCS; i++) {
+ desc_write(&priv->descs[i], hw_next,
+ (i == (NUM_DESCS - 1)) ? 0 : &priv->descs[i+1]);
+ }
+ priv->desc_free = &priv->descs[0];
+
+ /* initialize channels */
+ if (priv->data.version == CPSW_CTRL_VERSION_2) {
+ memset(&priv->rx_chan, 0, sizeof(struct cpdma_chan));
+ priv->rx_chan.hdp = priv->dma_regs + CPDMA_RXHDP_VER2;
+ priv->rx_chan.cp = priv->dma_regs + CPDMA_RXCP_VER2;
+ priv->rx_chan.rxfree = priv->dma_regs + CPDMA_RXFREE;
+
+ memset(&priv->tx_chan, 0, sizeof(struct cpdma_chan));
+ priv->tx_chan.hdp = priv->dma_regs + CPDMA_TXHDP_VER2;
+ priv->tx_chan.cp = priv->dma_regs + CPDMA_TXCP_VER2;
+ } else {
+ memset(&priv->rx_chan, 0, sizeof(struct cpdma_chan));
+ priv->rx_chan.hdp = priv->dma_regs + CPDMA_RXHDP_VER1;
+ priv->rx_chan.cp = priv->dma_regs + CPDMA_RXCP_VER1;
+ priv->rx_chan.rxfree = priv->dma_regs + CPDMA_RXFREE;
+
+ memset(&priv->tx_chan, 0, sizeof(struct cpdma_chan));
+ priv->tx_chan.hdp = priv->dma_regs + CPDMA_TXHDP_VER1;
+ priv->tx_chan.cp = priv->dma_regs + CPDMA_TXCP_VER1;
+ }
+
+ /* clear dma state */
+ setbit_and_wait_for_clear32(priv->dma_regs + CPDMA_SOFTRESET);
+
+ if (priv->data.version == CPSW_CTRL_VERSION_2) {
+ for (i = 0; i < priv->data.channels; i++) {
+ __raw_writel(0, priv->dma_regs + CPDMA_RXHDP_VER2 + 4
+ * i);
+ __raw_writel(0, priv->dma_regs + CPDMA_RXFREE + 4
+ * i);
+ __raw_writel(0, priv->dma_regs + CPDMA_RXCP_VER2 + 4
+ * i);
+ __raw_writel(0, priv->dma_regs + CPDMA_TXHDP_VER2 + 4
+ * i);
+ __raw_writel(0, priv->dma_regs + CPDMA_TXCP_VER2 + 4
+ * i);
+ }
+ } else {
+ for (i = 0; i < priv->data.channels; i++) {
+ __raw_writel(0, priv->dma_regs + CPDMA_RXHDP_VER1 + 4
+ * i);
+ __raw_writel(0, priv->dma_regs + CPDMA_RXFREE + 4
+ * i);
+ __raw_writel(0, priv->dma_regs + CPDMA_RXCP_VER1 + 4
+ * i);
+ __raw_writel(0, priv->dma_regs + CPDMA_TXHDP_VER1 + 4
+ * i);
+ __raw_writel(0, priv->dma_regs + CPDMA_TXCP_VER1 + 4
+ * i);
+
+ }
+ }
+
+ __raw_writel(1, priv->dma_regs + CPDMA_TXCONTROL);
+ __raw_writel(1, priv->dma_regs + CPDMA_RXCONTROL);
+
+ /* submit rx descs */
+ for (i = 0; i < PKTBUFSRX; i++) {
+ ret = cpdma_submit(priv, &priv->rx_chan, net_rx_packets[i],
+ PKTSIZE);
+ if (ret < 0) {
+ printf("error %d submitting rx desc\n", ret);
+ break;
+ }
+ }
+
+out:
+ return ret;
+}
+
+static int cpsw_reap_completed_packets(struct cpsw_priv *priv)
+{
+ int timeout = CPDMA_TIMEOUT;
+
+ /* reap completed packets */
+ while (timeout-- &&
+ (cpdma_process(priv, &priv->tx_chan, NULL, NULL) >= 0))
+ ;
+
+ return timeout;
+}
+
+static void _cpsw_halt(struct cpsw_priv *priv)
+{
+ cpsw_reap_completed_packets(priv);
+
+ writel(0, priv->dma_regs + CPDMA_TXCONTROL);
+ writel(0, priv->dma_regs + CPDMA_RXCONTROL);
+
+ /* soft reset the controller and initialize priv */
+ setbit_and_wait_for_clear32(&priv->regs->soft_reset);
+
+ /* clear dma state */
+ setbit_and_wait_for_clear32(priv->dma_regs + CPDMA_SOFTRESET);
+
+}
+
+static int _cpsw_send(struct cpsw_priv *priv, void *packet, int length)
+{
+ int timeout;
+
+ flush_dcache_range((unsigned long)packet,
+ (unsigned long)packet + ALIGN(length, PKTALIGN));
+
+ timeout = cpsw_reap_completed_packets(priv);
+ if (timeout == -1) {
+ printf("cpdma_process timeout\n");
+ return -ETIMEDOUT;
+ }
+
+ return cpdma_submit(priv, &priv->tx_chan, packet, length);
+}
+
+static int _cpsw_recv(struct cpsw_priv *priv, uchar **pkt)
+{
+ void *buffer;
+ int len;
+ int ret;
+
+ ret = cpdma_process(priv, &priv->rx_chan, &buffer, &len);
+ if (ret < 0)
+ return ret;
+
+ invalidate_dcache_range((unsigned long)buffer,
+ (unsigned long)buffer + PKTSIZE_ALIGN);
+ *pkt = buffer;
+
+ return len;
+}
+
+static void cpsw_slave_setup(struct cpsw_slave *slave, int slave_num,
+ struct cpsw_priv *priv)
+{
+ void *regs = priv->regs;
+ struct cpsw_slave_data *data = priv->data.slave_data + slave_num;
+ slave->slave_num = slave_num;
+ slave->data = data;
+ slave->regs = regs + data->slave_reg_ofs;
+ slave->sliver = regs + data->sliver_reg_ofs;
+}
+
+static int cpsw_phy_init(struct cpsw_priv *priv, struct cpsw_slave *slave)
+{
+ struct phy_device *phydev;
+ u32 supported = PHY_GBIT_FEATURES;
+
+ phydev = phy_connect(priv->bus,
+ slave->data->phy_addr,
+ priv->dev,
+ slave->data->phy_if);
+
+ if (!phydev)
+ return -1;
+
+ phydev->supported &= supported;
+ phydev->advertising = phydev->supported;
+
+#ifdef CONFIG_DM_ETH
+ if (slave->data->phy_of_handle)
+ phydev->node = offset_to_ofnode(slave->data->phy_of_handle);
+#endif
+
+ priv->phydev = phydev;
+ phy_config(phydev);
+
+ return 1;
+}
+
+static void cpsw_phy_addr_update(struct cpsw_priv *priv)
+{
+ struct cpsw_platform_data *data = &priv->data;
+ u16 alive = cpsw_mdio_get_alive(priv->bus);
+ int active = data->active_slave;
+ int new_addr = ffs(alive) - 1;
+
+ /*
+ * If there is only one phy alive and its address does not match
+ * that of active slave, then phy address can safely be updated.
+ */
+ if (hweight16(alive) == 1 &&
+ data->slave_data[active].phy_addr != new_addr) {
+ printf("Updated phy address for CPSW#%d, old: %d, new: %d\n",
+ active, data->slave_data[active].phy_addr, new_addr);
+ data->slave_data[active].phy_addr = new_addr;
+ }
+}
+
+int _cpsw_register(struct cpsw_priv *priv)
+{
+ struct cpsw_slave *slave;
+ struct cpsw_platform_data *data = &priv->data;
+ void *regs = (void *)data->cpsw_base;
+
+ priv->slaves = malloc(sizeof(struct cpsw_slave) * data->slaves);
+ if (!priv->slaves) {
+ return -ENOMEM;
+ }
+
+ priv->host_port = data->host_port_num;
+ priv->regs = regs;
+ priv->host_port_regs = regs + data->host_port_reg_ofs;
+ priv->dma_regs = regs + data->cpdma_reg_ofs;
+ priv->ale_regs = regs + data->ale_reg_ofs;
+ priv->descs = (void *)regs + data->bd_ram_ofs;
+
+ int idx = 0;
+
+ for_each_slave(slave, priv) {
+ cpsw_slave_setup(slave, idx, priv);
+ idx = idx + 1;
+ }
+
+ priv->bus = cpsw_mdio_init(priv->dev->name, data->mdio_base, 0, 0);
+ if (!priv->bus)
+ return -EFAULT;
+
+ cpsw_phy_addr_update(priv);
+
+ for_active_slave(slave, priv)
+ cpsw_phy_init(priv, slave);
+
+ return 0;
+}
+
+#ifndef CONFIG_DM_ETH
+static int cpsw_init(struct eth_device *dev, bd_t *bis)
+{
+ struct cpsw_priv *priv = dev->priv;
+
+ return _cpsw_init(priv, dev->enetaddr);
+}
+
+static void cpsw_halt(struct eth_device *dev)
+{
+ struct cpsw_priv *priv = dev->priv;
+
+ return _cpsw_halt(priv);
+}
+
+static int cpsw_send(struct eth_device *dev, void *packet, int length)
+{
+ struct cpsw_priv *priv = dev->priv;
+
+ return _cpsw_send(priv, packet, length);
+}
+
+static int cpsw_recv(struct eth_device *dev)
+{
+ struct cpsw_priv *priv = dev->priv;
+ uchar *pkt = NULL;
+ int len;
+
+ len = _cpsw_recv(priv, &pkt);
+
+ if (len > 0) {
+ net_process_received_packet(pkt, len);
+ cpdma_submit(priv, &priv->rx_chan, pkt, PKTSIZE);
+ }
+
+ return len;
+}
+
+int cpsw_register(struct cpsw_platform_data *data)
+{
+ struct cpsw_priv *priv;
+ struct eth_device *dev;
+ int ret;
+
+ dev = calloc(sizeof(*dev), 1);
+ if (!dev)
+ return -ENOMEM;
+
+ priv = calloc(sizeof(*priv), 1);
+ if (!priv) {
+ free(dev);
+ return -ENOMEM;
+ }
+
+ priv->dev = dev;
+ priv->data = *data;
+
+ strcpy(dev->name, "cpsw");
+ dev->iobase = 0;
+ dev->init = cpsw_init;
+ dev->halt = cpsw_halt;
+ dev->send = cpsw_send;
+ dev->recv = cpsw_recv;
+ dev->priv = priv;
+
+ eth_register(dev);
+
+ ret = _cpsw_register(priv);
+ if (ret < 0) {
+ eth_unregister(dev);
+ free(dev);
+ free(priv);
+ return ret;
+ }
+
+ return 1;
+}
+#else
+static int cpsw_eth_start(struct udevice *dev)
+{
+ struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct cpsw_priv *priv = dev_get_priv(dev);
+
+ return _cpsw_init(priv, pdata->enetaddr);
+}
+
+static int cpsw_eth_send(struct udevice *dev, void *packet, int length)
+{
+ struct cpsw_priv *priv = dev_get_priv(dev);
+
+ return _cpsw_send(priv, packet, length);
+}
+
+static int cpsw_eth_recv(struct udevice *dev, int flags, uchar **packetp)
+{
+ struct cpsw_priv *priv = dev_get_priv(dev);
+
+ return _cpsw_recv(priv, packetp);
+}
+
+static int cpsw_eth_free_pkt(struct udevice *dev, uchar *packet,
+ int length)
+{
+ struct cpsw_priv *priv = dev_get_priv(dev);
+
+ return cpdma_submit(priv, &priv->rx_chan, packet, PKTSIZE);
+}
+
+static void cpsw_eth_stop(struct udevice *dev)
+{
+ struct cpsw_priv *priv = dev_get_priv(dev);
+
+ return _cpsw_halt(priv);
+}
+
+
+static int cpsw_eth_probe(struct udevice *dev)
+{
+ struct cpsw_priv *priv = dev_get_priv(dev);
+
+ priv->dev = dev;
+
+ return _cpsw_register(priv);
+}
+
+static const struct eth_ops cpsw_eth_ops = {
+ .start = cpsw_eth_start,
+ .send = cpsw_eth_send,
+ .recv = cpsw_eth_recv,
+ .free_pkt = cpsw_eth_free_pkt,
+ .stop = cpsw_eth_stop,
+};
+
+static inline fdt_addr_t cpsw_get_addr_by_node(const void *fdt, int node)
+{
+ return fdtdec_get_addr_size_auto_noparent(fdt, node, "reg", 0, NULL,
+ false);
+}
+
+static void cpsw_gmii_sel_am3352(struct cpsw_priv *priv,
+ phy_interface_t phy_mode)
+{
+ u32 reg;
+ u32 mask;
+ u32 mode = 0;
+ bool rgmii_id = false;
+ int slave = priv->data.active_slave;
+
+ reg = readl(priv->data.gmii_sel);
+
+ switch (phy_mode) {
+ case PHY_INTERFACE_MODE_RMII:
+ mode = AM33XX_GMII_SEL_MODE_RMII;
+ break;
+
+ case PHY_INTERFACE_MODE_RGMII:
+ mode = AM33XX_GMII_SEL_MODE_RGMII;
+ break;
+ case PHY_INTERFACE_MODE_RGMII_ID:
+ case PHY_INTERFACE_MODE_RGMII_RXID:
+ case PHY_INTERFACE_MODE_RGMII_TXID:
+ mode = AM33XX_GMII_SEL_MODE_RGMII;
+ rgmii_id = true;
+ break;
+
+ case PHY_INTERFACE_MODE_MII:
+ default:
+ mode = AM33XX_GMII_SEL_MODE_MII;
+ break;
+ };
+
+ mask = GMII_SEL_MODE_MASK << (slave * 2) | BIT(slave + 6);
+ mode <<= slave * 2;
+
+ if (priv->data.rmii_clock_external) {
+ if (slave == 0)
+ mode |= AM33XX_GMII_SEL_RMII1_IO_CLK_EN;
+ else
+ mode |= AM33XX_GMII_SEL_RMII2_IO_CLK_EN;
+ }
+
+ if (rgmii_id) {
+ if (slave == 0)
+ mode |= AM33XX_GMII_SEL_RGMII1_IDMODE;
+ else
+ mode |= AM33XX_GMII_SEL_RGMII2_IDMODE;
+ }
+
+ reg &= ~mask;
+ reg |= mode;
+
+ writel(reg, priv->data.gmii_sel);
+}
+
+static void cpsw_gmii_sel_dra7xx(struct cpsw_priv *priv,
+ phy_interface_t phy_mode)
+{
+ u32 reg;
+ u32 mask;
+ u32 mode = 0;
+ int slave = priv->data.active_slave;
+
+ reg = readl(priv->data.gmii_sel);
+
+ switch (phy_mode) {
+ case PHY_INTERFACE_MODE_RMII:
+ mode = AM33XX_GMII_SEL_MODE_RMII;
+ break;
+
+ case PHY_INTERFACE_MODE_RGMII:
+ case PHY_INTERFACE_MODE_RGMII_ID:
+ case PHY_INTERFACE_MODE_RGMII_RXID:
+ case PHY_INTERFACE_MODE_RGMII_TXID:
+ mode = AM33XX_GMII_SEL_MODE_RGMII;
+ break;
+
+ case PHY_INTERFACE_MODE_MII:
+ default:
+ mode = AM33XX_GMII_SEL_MODE_MII;
+ break;
+ };
+
+ switch (slave) {
+ case 0:
+ mask = GMII_SEL_MODE_MASK;
+ break;
+ case 1:
+ mask = GMII_SEL_MODE_MASK << 4;
+ mode <<= 4;
+ break;
+ default:
+ dev_err(priv->dev, "invalid slave number...\n");
+ return;
+ }
+
+ if (priv->data.rmii_clock_external)
+ dev_err(priv->dev, "RMII External clock is not supported\n");
+
+ reg &= ~mask;
+ reg |= mode;
+
+ writel(reg, priv->data.gmii_sel);
+}
+
+static void cpsw_phy_sel(struct cpsw_priv *priv, const char *compat,
+ phy_interface_t phy_mode)
+{
+ if (!strcmp(compat, "ti,am3352-cpsw-phy-sel"))
+ cpsw_gmii_sel_am3352(priv, phy_mode);
+ if (!strcmp(compat, "ti,am43xx-cpsw-phy-sel"))
+ cpsw_gmii_sel_am3352(priv, phy_mode);
+ else if (!strcmp(compat, "ti,dra7xx-cpsw-phy-sel"))
+ cpsw_gmii_sel_dra7xx(priv, phy_mode);
+}
+
+static int cpsw_eth_ofdata_to_platdata(struct udevice *dev)
+{
+ struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct cpsw_priv *priv = dev_get_priv(dev);
+ struct gpio_desc *mode_gpios;
+ const char *phy_mode;
+ const char *phy_sel_compat = NULL;
+ const void *fdt = gd->fdt_blob;
+ int node = dev_of_offset(dev);
+ int subnode;
+ int slave_index = 0;
+ int active_slave;
+ int num_mode_gpios;
+ int ret;
+
+ pdata->iobase = devfdt_get_addr(dev);
+ priv->data.version = CPSW_CTRL_VERSION_2;
+ priv->data.bd_ram_ofs = CPSW_BD_OFFSET;
+ priv->data.ale_reg_ofs = CPSW_ALE_OFFSET;
+ priv->data.cpdma_reg_ofs = CPSW_CPDMA_OFFSET;
+ priv->data.mdio_div = CPSW_MDIO_DIV;
+ priv->data.host_port_reg_ofs = CPSW_HOST_PORT_OFFSET,
+
+ pdata->phy_interface = -1;
+
+ priv->data.cpsw_base = pdata->iobase;
+ priv->data.channels = fdtdec_get_int(fdt, node, "cpdma_channels", -1);
+ if (priv->data.channels <= 0) {
+ printf("error: cpdma_channels not found in dt\n");
+ return -ENOENT;
+ }
+
+ priv->data.slaves = fdtdec_get_int(fdt, node, "slaves", -1);
+ if (priv->data.slaves <= 0) {
+ printf("error: slaves not found in dt\n");
+ return -ENOENT;
+ }
+ priv->data.slave_data = malloc(sizeof(struct cpsw_slave_data) *
+ priv->data.slaves);
+
+ priv->data.ale_entries = fdtdec_get_int(fdt, node, "ale_entries", -1);
+ if (priv->data.ale_entries <= 0) {
+ printf("error: ale_entries not found in dt\n");
+ return -ENOENT;
+ }
+
+ priv->data.bd_ram_ofs = fdtdec_get_int(fdt, node, "bd_ram_size", -1);
+ if (priv->data.bd_ram_ofs <= 0) {
+ printf("error: bd_ram_size not found in dt\n");
+ return -ENOENT;
+ }
+
+ priv->data.mac_control = fdtdec_get_int(fdt, node, "mac_control", -1);
+ if (priv->data.mac_control <= 0) {
+ printf("error: ale_entries not found in dt\n");
+ return -ENOENT;
+ }
+
+ num_mode_gpios = gpio_get_list_count(dev, "mode-gpios");
+ if (num_mode_gpios > 0) {
+ mode_gpios = malloc(sizeof(struct gpio_desc) *
+ num_mode_gpios);
+ gpio_request_list_by_name(dev, "mode-gpios", mode_gpios,
+ num_mode_gpios, GPIOD_IS_OUT);
+ free(mode_gpios);
+ }
+
+ active_slave = fdtdec_get_int(fdt, node, "active_slave", 0);
+ priv->data.active_slave = active_slave;
+
+ fdt_for_each_subnode(subnode, fdt, node) {
+ int len;
+ const char *name;
+
+ name = fdt_get_name(fdt, subnode, &len);
+ if (!strncmp(name, "mdio", 4)) {
+ u32 mdio_base;
+
+ mdio_base = cpsw_get_addr_by_node(fdt, subnode);
+ if (mdio_base == FDT_ADDR_T_NONE) {
+ pr_err("Not able to get MDIO address space\n");
+ return -ENOENT;
+ }
+ priv->data.mdio_base = mdio_base;
+ }
+
+ if (!strncmp(name, "slave", 5)) {
+ u32 phy_id[2];
+
+ if (slave_index >= priv->data.slaves)
+ continue;
+ phy_mode = fdt_getprop(fdt, subnode, "phy-mode", NULL);
+ if (phy_mode)
+ priv->data.slave_data[slave_index].phy_if =
+ phy_get_interface_by_name(phy_mode);
+
+ priv->data.slave_data[slave_index].phy_of_handle =
+ fdtdec_lookup_phandle(fdt, subnode,
+ "phy-handle");
+
+ if (priv->data.slave_data[slave_index].phy_of_handle >= 0) {
+ priv->data.slave_data[slave_index].phy_addr =
+ fdtdec_get_int(gd->fdt_blob,
+ priv->data.slave_data[slave_index].phy_of_handle,
+ "reg", -1);
+ } else {
+ fdtdec_get_int_array(fdt, subnode, "phy_id",
+ phy_id, 2);
+ priv->data.slave_data[slave_index].phy_addr =
+ phy_id[1];
+ }
+ slave_index++;
+ }
+
+ if (!strncmp(name, "cpsw-phy-sel", 12)) {
+ priv->data.gmii_sel = cpsw_get_addr_by_node(fdt,
+ subnode);
+
+ if (priv->data.gmii_sel == FDT_ADDR_T_NONE) {
+ pr_err("Not able to get gmii_sel reg address\n");
+ return -ENOENT;
+ }
+
+ if (fdt_get_property(fdt, subnode, "rmii-clock-ext",
+ NULL))
+ priv->data.rmii_clock_external = true;
+
+ phy_sel_compat = fdt_getprop(fdt, subnode, "compatible",
+ NULL);
+ if (!phy_sel_compat) {
+ pr_err("Not able to get gmii_sel compatible\n");
+ return -ENOENT;
+ }
+ }
+ }
+
+ priv->data.slave_data[0].slave_reg_ofs = CPSW_SLAVE0_OFFSET;
+ priv->data.slave_data[0].sliver_reg_ofs = CPSW_SLIVER0_OFFSET;
+
+ if (priv->data.slaves == 2) {
+ priv->data.slave_data[1].slave_reg_ofs = CPSW_SLAVE1_OFFSET;
+ priv->data.slave_data[1].sliver_reg_ofs = CPSW_SLIVER1_OFFSET;
+ }
+
+ ret = ti_cm_get_macid(dev, active_slave, pdata->enetaddr);
+ if (ret < 0) {
+ pr_err("cpsw read efuse mac failed\n");
+ return ret;
+ }
+
+ pdata->phy_interface = priv->data.slave_data[active_slave].phy_if;
+ if (pdata->phy_interface == -1) {
+ debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
+ return -EINVAL;
+ }
+
+ /* Select phy interface in control module */
+ cpsw_phy_sel(priv, phy_sel_compat, pdata->phy_interface);
+
+ return 0;
+}
+
+int cpsw_get_slave_phy_addr(struct udevice *dev, int slave)
+{
+ struct cpsw_priv *priv = dev_get_priv(dev);
+ struct cpsw_platform_data *data = &priv->data;
+
+ return data->slave_data[slave].phy_addr;
+}
+
+static const struct udevice_id cpsw_eth_ids[] = {
+ { .compatible = "ti,cpsw" },
+ { .compatible = "ti,am335x-cpsw" },
+ { }
+};
+
+U_BOOT_DRIVER(eth_cpsw) = {
+ .name = "eth_cpsw",
+ .id = UCLASS_ETH,
+ .of_match = cpsw_eth_ids,
+ .ofdata_to_platdata = cpsw_eth_ofdata_to_platdata,
+ .probe = cpsw_eth_probe,
+ .ops = &cpsw_eth_ops,
+ .priv_auto_alloc_size = sizeof(struct cpsw_priv),
+ .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+ .flags = DM_FLAG_ALLOC_PRIV_DMA,
+};
+#endif /* CONFIG_DM_ETH */
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * CPSW MDIO generic driver for TI AMxx/K2x/EMAC devices.
+ *
+ * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <miiphy.h>
+#include <wait_bit.h>
+
+struct cpsw_mdio_regs {
+ u32 version;
+ u32 control;
+#define CONTROL_IDLE BIT(31)
+#define CONTROL_ENABLE BIT(30)
+#define CONTROL_FAULT BIT(19)
+#define CONTROL_FAULT_ENABLE BIT(18)
+#define CONTROL_DIV_MASK GENMASK(15, 0)
+
+ u32 alive;
+ u32 link;
+ u32 linkintraw;
+ u32 linkintmasked;
+ u32 __reserved_0[2];
+ u32 userintraw;
+ u32 userintmasked;
+ u32 userintmaskset;
+ u32 userintmaskclr;
+ u32 __reserved_1[20];
+
+ struct {
+ u32 access;
+ u32 physel;
+#define USERACCESS_GO BIT(31)
+#define USERACCESS_WRITE BIT(30)
+#define USERACCESS_ACK BIT(29)
+#define USERACCESS_READ (0)
+#define USERACCESS_PHY_REG_SHIFT (21)
+#define USERACCESS_PHY_ADDR_SHIFT (16)
+#define USERACCESS_DATA GENMASK(15, 0)
+ } user[0];
+};
+
+#define CPSW_MDIO_DIV_DEF 0xff
+#define PHY_REG_MASK 0x1f
+#define PHY_ID_MASK 0x1f
+
+/*
+ * This timeout definition is a worst-case ultra defensive measure against
+ * unexpected controller lock ups. Ideally, we should never ever hit this
+ * scenario in practice.
+ */
+#define CPSW_MDIO_TIMEOUT 100 /* msecs */
+
+struct cpsw_mdio {
+ struct cpsw_mdio_regs *regs;
+ struct mii_dev *bus;
+ int div;
+};
+
+/* wait until hardware is ready for another user access */
+static int cpsw_mdio_wait_for_user_access(struct cpsw_mdio *mdio)
+{
+ return wait_for_bit_le32(&mdio->regs->user[0].access,
+ USERACCESS_GO, false,
+ CPSW_MDIO_TIMEOUT, false);
+}
+
+static int cpsw_mdio_read(struct mii_dev *bus, int phy_id,
+ int dev_addr, int phy_reg)
+{
+ struct cpsw_mdio *mdio = bus->priv;
+ int data, ret;
+ u32 reg;
+
+ if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK)
+ return -EINVAL;
+
+ ret = cpsw_mdio_wait_for_user_access(mdio);
+ if (ret)
+ return ret;
+ reg = (USERACCESS_GO | USERACCESS_READ |
+ (phy_reg << USERACCESS_PHY_REG_SHIFT) |
+ (phy_id << USERACCESS_PHY_ADDR_SHIFT));
+ writel(reg, &mdio->regs->user[0].access);
+ ret = cpsw_mdio_wait_for_user_access(mdio);
+ if (ret)
+ return ret;
+
+ reg = readl(&mdio->regs->user[0].access);
+ data = (reg & USERACCESS_ACK) ? (reg & USERACCESS_DATA) : -1;
+ return data;
+}
+
+static int cpsw_mdio_write(struct mii_dev *bus, int phy_id, int dev_addr,
+ int phy_reg, u16 data)
+{
+ struct cpsw_mdio *mdio = bus->priv;
+ u32 reg;
+ int ret;
+
+ if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK)
+ return -EINVAL;
+
+ ret = cpsw_mdio_wait_for_user_access(mdio);
+ if (ret)
+ return ret;
+ reg = (USERACCESS_GO | USERACCESS_WRITE |
+ (phy_reg << USERACCESS_PHY_REG_SHIFT) |
+ (phy_id << USERACCESS_PHY_ADDR_SHIFT) |
+ (data & USERACCESS_DATA));
+ writel(reg, &mdio->regs->user[0].access);
+
+ return cpsw_mdio_wait_for_user_access(mdio);
+}
+
+u32 cpsw_mdio_get_alive(struct mii_dev *bus)
+{
+ struct cpsw_mdio *mdio = bus->priv;
+ u32 val;
+
+ val = readl(&mdio->regs->control);
+ return val & GENMASK(15, 0);
+}
+
+struct mii_dev *cpsw_mdio_init(const char *name, u32 mdio_base,
+ u32 bus_freq, int fck_freq)
+{
+ struct cpsw_mdio *cpsw_mdio;
+ int ret;
+
+ cpsw_mdio = calloc(1, sizeof(*cpsw_mdio));
+ if (!cpsw_mdio) {
+ debug("failed to alloc cpsw_mdio\n");
+ return NULL;
+ }
+
+ cpsw_mdio->bus = mdio_alloc();
+ if (!cpsw_mdio->bus) {
+ debug("failed to alloc mii bus\n");
+ free(cpsw_mdio);
+ return NULL;
+ }
+
+ cpsw_mdio->regs = (struct cpsw_mdio_regs *)mdio_base;
+
+ if (!bus_freq || !fck_freq)
+ cpsw_mdio->div = CPSW_MDIO_DIV_DEF;
+ else
+ cpsw_mdio->div = (fck_freq / bus_freq) - 1;
+ cpsw_mdio->div &= CONTROL_DIV_MASK;
+
+ /* set enable and clock divider */
+ writel(cpsw_mdio->div | CONTROL_ENABLE | CONTROL_FAULT |
+ CONTROL_FAULT_ENABLE, &cpsw_mdio->regs->control);
+ wait_for_bit_le32(&cpsw_mdio->regs->control,
+ CONTROL_IDLE, false, CPSW_MDIO_TIMEOUT, true);
+
+ /*
+ * wait for scan logic to settle:
+ * the scan time consists of (a) a large fixed component, and (b) a
+ * small component that varies with the mii bus frequency. These
+ * were estimated using measurements at 1.1 and 2.2 MHz on tnetv107x
+ * silicon. Since the effect of (b) was found to be largely
+ * negligible, we keep things simple here.
+ */
+ mdelay(1);
+
+ cpsw_mdio->bus->read = cpsw_mdio_read;
+ cpsw_mdio->bus->write = cpsw_mdio_write;
+ cpsw_mdio->bus->priv = cpsw_mdio;
+ snprintf(cpsw_mdio->bus->name, sizeof(cpsw_mdio->bus->name), name);
+
+ ret = mdio_register(cpsw_mdio->bus);
+ if (ret < 0) {
+ debug("failed to register mii bus\n");
+ goto free_bus;
+ }
+
+ return cpsw_mdio->bus;
+
+free_bus:
+ mdio_free(cpsw_mdio->bus);
+ free(cpsw_mdio);
+ return NULL;
+}
+
+void cpsw_mdio_free(struct mii_dev *bus)
+{
+ struct cpsw_mdio *mdio = bus->priv;
+ u32 reg;
+
+ /* disable mdio */
+ reg = readl(&mdio->regs->control);
+ reg &= ~CONTROL_ENABLE;
+ writel(reg, &mdio->regs->control);
+
+ mdio_unregister(bus);
+ mdio_free(bus);
+ free(mdio);
+}
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * CPSW MDIO generic driver API for TI AMxx/K2x/EMAC devices.
+ *
+ * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+#ifndef CPSW_MDIO_H_
+#define CPSW_MDIO_H_
+
+struct cpsw_mdio;
+
+struct mii_dev *cpsw_mdio_init(const char *name, u32 mdio_base,
+ u32 bus_freq, int fck_freq);
+void cpsw_mdio_free(struct mii_dev *bus);
+u32 cpsw_mdio_get_alive(struct mii_dev *bus);
+
+#endif /* CPSW_MDIO_H_ */
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Ethernet driver for TI TMS320DM644x (DaVinci) chips.
+ *
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * Parts shamelessly stolen from TI's dm644x_emac.c. Original copyright
+ * follows:
+ *
+ * ----------------------------------------------------------------------------
+ *
+ * dm644x_emac.c
+ *
+ * TI DaVinci (DM644X) EMAC peripheral driver source for DV-EVM
+ *
+ * Copyright (C) 2005 Texas Instruments.
+ *
+ * ----------------------------------------------------------------------------
+ *
+ * Modifications:
+ * ver. 1.0: Sep 2005, Anant Gole - Created EMAC version for uBoot.
+ * ver 1.1: Nov 2005, Anant Gole - Extended the RX logic for multiple descriptors
+ */
+#include <common.h>
+#include <command.h>
+#include <net.h>
+#include <miiphy.h>
+#include <malloc.h>
+#include <netdev.h>
+#include <linux/compiler.h>
+#include <asm/arch/emac_defs.h>
+#include <asm/io.h>
+#include "davinci_emac.h"
+
+unsigned int emac_dbg = 0;
+#define debug_emac(fmt,args...) if (emac_dbg) printf(fmt,##args)
+
+#ifdef EMAC_HW_RAM_ADDR
+static inline unsigned long BD_TO_HW(unsigned long x)
+{
+ if (x == 0)
+ return 0;
+
+ return x - EMAC_WRAPPER_RAM_ADDR + EMAC_HW_RAM_ADDR;
+}
+
+static inline unsigned long HW_TO_BD(unsigned long x)
+{
+ if (x == 0)
+ return 0;
+
+ return x - EMAC_HW_RAM_ADDR + EMAC_WRAPPER_RAM_ADDR;
+}
+#else
+#define BD_TO_HW(x) (x)
+#define HW_TO_BD(x) (x)
+#endif
+
+#ifdef DAVINCI_EMAC_GIG_ENABLE
+#define emac_gigabit_enable(phy_addr) davinci_eth_gigabit_enable(phy_addr)
+#else
+#define emac_gigabit_enable(phy_addr) /* no gigabit to enable */
+#endif
+
+#if !defined(CONFIG_SYS_EMAC_TI_CLKDIV)
+#define CONFIG_SYS_EMAC_TI_CLKDIV ((EMAC_MDIO_BUS_FREQ / \
+ EMAC_MDIO_CLOCK_FREQ) - 1)
+#endif
+
+static void davinci_eth_mdio_enable(void);
+
+static int gen_init_phy(int phy_addr);
+static int gen_is_phy_connected(int phy_addr);
+static int gen_get_link_speed(int phy_addr);
+static int gen_auto_negotiate(int phy_addr);
+
+void eth_mdio_enable(void)
+{
+ davinci_eth_mdio_enable();
+}
+
+/* EMAC Addresses */
+static volatile emac_regs *adap_emac = (emac_regs *)EMAC_BASE_ADDR;
+static volatile ewrap_regs *adap_ewrap = (ewrap_regs *)EMAC_WRAPPER_BASE_ADDR;
+static volatile mdio_regs *adap_mdio = (mdio_regs *)EMAC_MDIO_BASE_ADDR;
+
+/* EMAC descriptors */
+static volatile emac_desc *emac_rx_desc = (emac_desc *)(EMAC_WRAPPER_RAM_ADDR + EMAC_RX_DESC_BASE);
+static volatile emac_desc *emac_tx_desc = (emac_desc *)(EMAC_WRAPPER_RAM_ADDR + EMAC_TX_DESC_BASE);
+static volatile emac_desc *emac_rx_active_head = 0;
+static volatile emac_desc *emac_rx_active_tail = 0;
+static int emac_rx_queue_active = 0;
+
+/* Receive packet buffers */
+static unsigned char emac_rx_buffers[EMAC_MAX_RX_BUFFERS * EMAC_RXBUF_SIZE]
+ __aligned(ARCH_DMA_MINALIGN);
+
+#ifndef CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT
+#define CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT 3
+#endif
+
+/* PHY address for a discovered PHY (0xff - not found) */
+static u_int8_t active_phy_addr[CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT];
+
+/* number of PHY found active */
+static u_int8_t num_phy;
+
+phy_t phy[CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT];
+
+static int davinci_eth_set_mac_addr(struct eth_device *dev)
+{
+ unsigned long mac_hi;
+ unsigned long mac_lo;
+
+ /*
+ * Set MAC Addresses & Init multicast Hash to 0 (disable any multicast
+ * receive)
+ * Using channel 0 only - other channels are disabled
+ * */
+ writel(0, &adap_emac->MACINDEX);
+ mac_hi = (dev->enetaddr[3] << 24) |
+ (dev->enetaddr[2] << 16) |
+ (dev->enetaddr[1] << 8) |
+ (dev->enetaddr[0]);
+ mac_lo = (dev->enetaddr[5] << 8) |
+ (dev->enetaddr[4]);
+
+ writel(mac_hi, &adap_emac->MACADDRHI);
+#if defined(DAVINCI_EMAC_VERSION2)
+ writel(mac_lo | EMAC_MAC_ADDR_IS_VALID | EMAC_MAC_ADDR_MATCH,
+ &adap_emac->MACADDRLO);
+#else
+ writel(mac_lo, &adap_emac->MACADDRLO);
+#endif
+
+ writel(0, &adap_emac->MACHASH1);
+ writel(0, &adap_emac->MACHASH2);
+
+ /* Set source MAC address - REQUIRED */
+ writel(mac_hi, &adap_emac->MACSRCADDRHI);
+ writel(mac_lo, &adap_emac->MACSRCADDRLO);
+
+
+ return 0;
+}
+
+static void davinci_eth_mdio_enable(void)
+{
+ u_int32_t clkdiv;
+
+ clkdiv = CONFIG_SYS_EMAC_TI_CLKDIV;
+
+ writel((clkdiv & 0xff) |
+ MDIO_CONTROL_ENABLE |
+ MDIO_CONTROL_FAULT |
+ MDIO_CONTROL_FAULT_ENABLE,
+ &adap_mdio->CONTROL);
+
+ while (readl(&adap_mdio->CONTROL) & MDIO_CONTROL_IDLE)
+ ;
+}
+
+/*
+ * Tries to find an active connected PHY. Returns 1 if address if found.
+ * If no active PHY (or more than one PHY) found returns 0.
+ * Sets active_phy_addr variable.
+ */
+static int davinci_eth_phy_detect(void)
+{
+ u_int32_t phy_act_state;
+ int i;
+ int j;
+ unsigned int count = 0;
+
+ for (i = 0; i < CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT; i++)
+ active_phy_addr[i] = 0xff;
+
+ udelay(1000);
+ phy_act_state = readl(&adap_mdio->ALIVE);
+
+ if (phy_act_state == 0)
+ return 0; /* No active PHYs */
+
+ debug_emac("davinci_eth_phy_detect(), ALIVE = 0x%08x\n", phy_act_state);
+
+ for (i = 0, j = 0; i < 32; i++)
+ if (phy_act_state & (1 << i)) {
+ count++;
+ if (count <= CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT) {
+ active_phy_addr[j++] = i;
+ } else {
+ printf("%s: to many PHYs detected.\n",
+ __func__);
+ count = 0;
+ break;
+ }
+ }
+
+ num_phy = count;
+
+ return count;
+}
+
+
+/* Read a PHY register via MDIO inteface. Returns 1 on success, 0 otherwise */
+int davinci_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t *data)
+{
+ int tmp;
+
+ while (readl(&adap_mdio->USERACCESS0) & MDIO_USERACCESS0_GO)
+ ;
+
+ writel(MDIO_USERACCESS0_GO |
+ MDIO_USERACCESS0_WRITE_READ |
+ ((reg_num & 0x1f) << 21) |
+ ((phy_addr & 0x1f) << 16),
+ &adap_mdio->USERACCESS0);
+
+ /* Wait for command to complete */
+ while ((tmp = readl(&adap_mdio->USERACCESS0)) & MDIO_USERACCESS0_GO)
+ ;
+
+ if (tmp & MDIO_USERACCESS0_ACK) {
+ *data = tmp & 0xffff;
+ return 1;
+ }
+
+ return 0;
+}
+
+/* Write to a PHY register via MDIO inteface. Blocks until operation is complete. */
+int davinci_eth_phy_write(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t data)
+{
+
+ while (readl(&adap_mdio->USERACCESS0) & MDIO_USERACCESS0_GO)
+ ;
+
+ writel(MDIO_USERACCESS0_GO |
+ MDIO_USERACCESS0_WRITE_WRITE |
+ ((reg_num & 0x1f) << 21) |
+ ((phy_addr & 0x1f) << 16) |
+ (data & 0xffff),
+ &adap_mdio->USERACCESS0);
+
+ /* Wait for command to complete */
+ while (readl(&adap_mdio->USERACCESS0) & MDIO_USERACCESS0_GO)
+ ;
+
+ return 1;
+}
+
+/* PHY functions for a generic PHY */
+static int gen_init_phy(int phy_addr)
+{
+ int ret = 1;
+
+ if (gen_get_link_speed(phy_addr)) {
+ /* Try another time */
+ ret = gen_get_link_speed(phy_addr);
+ }
+
+ return(ret);
+}
+
+static int gen_is_phy_connected(int phy_addr)
+{
+ u_int16_t dummy;
+
+ return davinci_eth_phy_read(phy_addr, MII_PHYSID1, &dummy);
+}
+
+static int get_active_phy(void)
+{
+ int i;
+
+ for (i = 0; i < num_phy; i++)
+ if (phy[i].get_link_speed(active_phy_addr[i]))
+ return i;
+
+ return -1; /* Return error if no link */
+}
+
+static int gen_get_link_speed(int phy_addr)
+{
+ u_int16_t tmp;
+
+ if (davinci_eth_phy_read(phy_addr, MII_STATUS_REG, &tmp) &&
+ (tmp & 0x04)) {
+#if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \
+ defined(CONFIG_MACH_DAVINCI_DA850_EVM)
+ davinci_eth_phy_read(phy_addr, MII_LPA, &tmp);
+
+ /* Speed doesn't matter, there is no setting for it in EMAC. */
+ if (tmp & (LPA_100FULL | LPA_10FULL)) {
+ /* set EMAC for Full Duplex */
+ writel(EMAC_MACCONTROL_MIIEN_ENABLE |
+ EMAC_MACCONTROL_FULLDUPLEX_ENABLE,
+ &adap_emac->MACCONTROL);
+ } else {
+ /*set EMAC for Half Duplex */
+ writel(EMAC_MACCONTROL_MIIEN_ENABLE,
+ &adap_emac->MACCONTROL);
+ }
+
+ if (tmp & (LPA_100FULL | LPA_100HALF))
+ writel(readl(&adap_emac->MACCONTROL) |
+ EMAC_MACCONTROL_RMIISPEED_100,
+ &adap_emac->MACCONTROL);
+ else
+ writel(readl(&adap_emac->MACCONTROL) &
+ ~EMAC_MACCONTROL_RMIISPEED_100,
+ &adap_emac->MACCONTROL);
+#endif
+ return(1);
+ }
+
+ return(0);
+}
+
+static int gen_auto_negotiate(int phy_addr)
+{
+ u_int16_t tmp;
+ u_int16_t val;
+ unsigned long cntr = 0;
+
+ if (!davinci_eth_phy_read(phy_addr, MII_BMCR, &tmp))
+ return 0;
+
+ val = tmp | BMCR_FULLDPLX | BMCR_ANENABLE |
+ BMCR_SPEED100;
+ davinci_eth_phy_write(phy_addr, MII_BMCR, val);
+
+ if (!davinci_eth_phy_read(phy_addr, MII_ADVERTISE, &val))
+ return 0;
+
+ val |= (ADVERTISE_100FULL | ADVERTISE_100HALF | ADVERTISE_10FULL |
+ ADVERTISE_10HALF);
+ davinci_eth_phy_write(phy_addr, MII_ADVERTISE, val);
+
+ if (!davinci_eth_phy_read(phy_addr, MII_BMCR, &tmp))
+ return(0);
+
+#ifdef DAVINCI_EMAC_GIG_ENABLE
+ davinci_eth_phy_read(phy_addr, MII_CTRL1000, &val);
+ val |= PHY_1000BTCR_1000FD;
+ val &= ~PHY_1000BTCR_1000HD;
+ davinci_eth_phy_write(phy_addr, MII_CTRL1000, val);
+ davinci_eth_phy_read(phy_addr, MII_CTRL1000, &val);
+#endif
+
+ /* Restart Auto_negotiation */
+ tmp |= BMCR_ANRESTART;
+ davinci_eth_phy_write(phy_addr, MII_BMCR, tmp);
+
+ /*check AutoNegotiate complete */
+ do {
+ udelay(40000);
+ if (!davinci_eth_phy_read(phy_addr, MII_BMSR, &tmp))
+ return 0;
+
+ if (tmp & BMSR_ANEGCOMPLETE)
+ break;
+
+ cntr++;
+ } while (cntr < 200);
+
+ if (!davinci_eth_phy_read(phy_addr, MII_BMSR, &tmp))
+ return(0);
+
+ if (!(tmp & BMSR_ANEGCOMPLETE))
+ return(0);
+
+ return(gen_get_link_speed(phy_addr));
+}
+/* End of generic PHY functions */
+
+
+#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
+static int davinci_mii_phy_read(struct mii_dev *bus, int addr, int devad,
+ int reg)
+{
+ unsigned short value = 0;
+ int retval = davinci_eth_phy_read(addr, reg, &value);
+
+ return retval ? value : -EIO;
+}
+
+static int davinci_mii_phy_write(struct mii_dev *bus, int addr, int devad,
+ int reg, u16 value)
+{
+ return davinci_eth_phy_write(addr, reg, value) ? 0 : 1;
+}
+#endif
+
+static void __attribute__((unused)) davinci_eth_gigabit_enable(int phy_addr)
+{
+ u_int16_t data;
+
+ if (davinci_eth_phy_read(phy_addr, 0, &data)) {
+ if (data & (1 << 6)) { /* speed selection MSB */
+ /*
+ * Check if link detected is giga-bit
+ * If Gigabit mode detected, enable gigbit in MAC
+ */
+ writel(readl(&adap_emac->MACCONTROL) |
+ EMAC_MACCONTROL_GIGFORCE |
+ EMAC_MACCONTROL_GIGABIT_ENABLE,
+ &adap_emac->MACCONTROL);
+ }
+ }
+}
+
+/* Eth device open */
+static int davinci_eth_open(struct eth_device *dev, bd_t *bis)
+{
+ dv_reg_p addr;
+ u_int32_t clkdiv, cnt, mac_control;
+ uint16_t __maybe_unused lpa_val;
+ volatile emac_desc *rx_desc;
+ int index;
+
+ debug_emac("+ emac_open\n");
+
+ /* Reset EMAC module and disable interrupts in wrapper */
+ writel(1, &adap_emac->SOFTRESET);
+ while (readl(&adap_emac->SOFTRESET) != 0)
+ ;
+#if defined(DAVINCI_EMAC_VERSION2)
+ writel(1, &adap_ewrap->softrst);
+ while (readl(&adap_ewrap->softrst) != 0)
+ ;
+#else
+ writel(0, &adap_ewrap->EWCTL);
+ for (cnt = 0; cnt < 5; cnt++) {
+ clkdiv = readl(&adap_ewrap->EWCTL);
+ }
+#endif
+
+#if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \
+ defined(CONFIG_MACH_DAVINCI_DA850_EVM)
+ adap_ewrap->c0rxen = adap_ewrap->c1rxen = adap_ewrap->c2rxen = 0;
+ adap_ewrap->c0txen = adap_ewrap->c1txen = adap_ewrap->c2txen = 0;
+ adap_ewrap->c0miscen = adap_ewrap->c1miscen = adap_ewrap->c2miscen = 0;
+#endif
+ rx_desc = emac_rx_desc;
+
+ writel(1, &adap_emac->TXCONTROL);
+ writel(1, &adap_emac->RXCONTROL);
+
+ davinci_eth_set_mac_addr(dev);
+
+ /* Set DMA 8 TX / 8 RX Head pointers to 0 */
+ addr = &adap_emac->TX0HDP;
+ for (cnt = 0; cnt < 8; cnt++)
+ writel(0, addr++);
+
+ addr = &adap_emac->RX0HDP;
+ for (cnt = 0; cnt < 8; cnt++)
+ writel(0, addr++);
+
+ /* Clear Statistics (do this before setting MacControl register) */
+ addr = &adap_emac->RXGOODFRAMES;
+ for(cnt = 0; cnt < EMAC_NUM_STATS; cnt++)
+ writel(0, addr++);
+
+ /* No multicast addressing */
+ writel(0, &adap_emac->MACHASH1);
+ writel(0, &adap_emac->MACHASH2);
+
+ /* Create RX queue and set receive process in place */
+ emac_rx_active_head = emac_rx_desc;
+ for (cnt = 0; cnt < EMAC_MAX_RX_BUFFERS; cnt++) {
+ rx_desc->next = BD_TO_HW((u_int32_t)(rx_desc + 1));
+ rx_desc->buffer = &emac_rx_buffers[cnt * EMAC_RXBUF_SIZE];
+ rx_desc->buff_off_len = EMAC_MAX_ETHERNET_PKT_SIZE;
+ rx_desc->pkt_flag_len = EMAC_CPPI_OWNERSHIP_BIT;
+ rx_desc++;
+ }
+
+ /* Finalize the rx desc list */
+ rx_desc--;
+ rx_desc->next = 0;
+ emac_rx_active_tail = rx_desc;
+ emac_rx_queue_active = 1;
+
+ /* Enable TX/RX */
+ writel(EMAC_MAX_ETHERNET_PKT_SIZE, &adap_emac->RXMAXLEN);
+ writel(0, &adap_emac->RXBUFFEROFFSET);
+
+ /*
+ * No fancy configs - Use this for promiscous debug
+ * - EMAC_RXMBPENABLE_RXCAFEN_ENABLE
+ */
+ writel(EMAC_RXMBPENABLE_RXBROADEN, &adap_emac->RXMBPENABLE);
+
+ /* Enable ch 0 only */
+ writel(1, &adap_emac->RXUNICASTSET);
+
+ /* Init MDIO & get link state */
+ clkdiv = CONFIG_SYS_EMAC_TI_CLKDIV;
+ writel((clkdiv & 0xff) | MDIO_CONTROL_ENABLE | MDIO_CONTROL_FAULT,
+ &adap_mdio->CONTROL);
+
+ /* We need to wait for MDIO to start */
+ udelay(1000);
+
+ index = get_active_phy();
+ if (index == -1)
+ return(0);
+
+ /* Enable MII interface */
+ mac_control = EMAC_MACCONTROL_MIIEN_ENABLE;
+#ifdef DAVINCI_EMAC_GIG_ENABLE
+ davinci_eth_phy_read(active_phy_addr[index], MII_STAT1000, &lpa_val);
+ if (lpa_val & PHY_1000BTSR_1000FD) {
+ debug_emac("eth_open : gigabit negotiated\n");
+ mac_control |= EMAC_MACCONTROL_FULLDUPLEX_ENABLE;
+ mac_control |= EMAC_MACCONTROL_GIGABIT_ENABLE;
+ }
+#endif
+
+ davinci_eth_phy_read(active_phy_addr[index], MII_LPA, &lpa_val);
+ if (lpa_val & (LPA_100FULL | LPA_10FULL))
+ /* set EMAC for Full Duplex */
+ mac_control |= EMAC_MACCONTROL_FULLDUPLEX_ENABLE;
+#if defined(CONFIG_SOC_DA8XX) || \
+ (defined(CONFIG_OMAP34XX) && defined(CONFIG_DRIVER_TI_EMAC_USE_RMII))
+ mac_control |= EMAC_MACCONTROL_RMIISPEED_100;
+#endif
+ writel(mac_control, &adap_emac->MACCONTROL);
+ /* Start receive process */
+ writel(BD_TO_HW((u_int32_t)emac_rx_desc), &adap_emac->RX0HDP);
+
+ debug_emac("- emac_open\n");
+
+ return(1);
+}
+
+/* EMAC Channel Teardown */
+static void davinci_eth_ch_teardown(int ch)
+{
+ dv_reg dly = 0xff;
+ dv_reg cnt;
+
+ debug_emac("+ emac_ch_teardown\n");
+
+ if (ch == EMAC_CH_TX) {
+ /* Init TX channel teardown */
+ writel(0, &adap_emac->TXTEARDOWN);
+ do {
+ /*
+ * Wait here for Tx teardown completion interrupt to
+ * occur. Note: A task delay can be called here to pend
+ * rather than occupying CPU cycles - anyway it has
+ * been found that teardown takes very few cpu cycles
+ * and does not affect functionality
+ */
+ dly--;
+ udelay(1);
+ if (dly == 0)
+ break;
+ cnt = readl(&adap_emac->TX0CP);
+ } while (cnt != 0xfffffffc);
+ writel(cnt, &adap_emac->TX0CP);
+ writel(0, &adap_emac->TX0HDP);
+ } else {
+ /* Init RX channel teardown */
+ writel(0, &adap_emac->RXTEARDOWN);
+ do {
+ /*
+ * Wait here for Rx teardown completion interrupt to
+ * occur. Note: A task delay can be called here to pend
+ * rather than occupying CPU cycles - anyway it has
+ * been found that teardown takes very few cpu cycles
+ * and does not affect functionality
+ */
+ dly--;
+ udelay(1);
+ if (dly == 0)
+ break;
+ cnt = readl(&adap_emac->RX0CP);
+ } while (cnt != 0xfffffffc);
+ writel(cnt, &adap_emac->RX0CP);
+ writel(0, &adap_emac->RX0HDP);
+ }
+
+ debug_emac("- emac_ch_teardown\n");
+}
+
+/* Eth device close */
+static void davinci_eth_close(struct eth_device *dev)
+{
+ debug_emac("+ emac_close\n");
+
+ davinci_eth_ch_teardown(EMAC_CH_TX); /* TX Channel teardown */
+ if (readl(&adap_emac->RXCONTROL) & 1)
+ davinci_eth_ch_teardown(EMAC_CH_RX); /* RX Channel teardown */
+
+ /* Reset EMAC module and disable interrupts in wrapper */
+ writel(1, &adap_emac->SOFTRESET);
+#if defined(DAVINCI_EMAC_VERSION2)
+ writel(1, &adap_ewrap->softrst);
+#else
+ writel(0, &adap_ewrap->EWCTL);
+#endif
+
+#if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \
+ defined(CONFIG_MACH_DAVINCI_DA850_EVM)
+ adap_ewrap->c0rxen = adap_ewrap->c1rxen = adap_ewrap->c2rxen = 0;
+ adap_ewrap->c0txen = adap_ewrap->c1txen = adap_ewrap->c2txen = 0;
+ adap_ewrap->c0miscen = adap_ewrap->c1miscen = adap_ewrap->c2miscen = 0;
+#endif
+ debug_emac("- emac_close\n");
+}
+
+static int tx_send_loop = 0;
+
+/*
+ * This function sends a single packet on the network and returns
+ * positive number (number of bytes transmitted) or negative for error
+ */
+static int davinci_eth_send_packet (struct eth_device *dev,
+ void *packet, int length)
+{
+ int ret_status = -1;
+ int index;
+ tx_send_loop = 0;
+
+ index = get_active_phy();
+ if (index == -1) {
+ printf(" WARN: emac_send_packet: No link\n");
+ return (ret_status);
+ }
+
+ /* Check packet size and if < EMAC_MIN_ETHERNET_PKT_SIZE, pad it up */
+ if (length < EMAC_MIN_ETHERNET_PKT_SIZE) {
+ length = EMAC_MIN_ETHERNET_PKT_SIZE;
+ }
+
+ /* Populate the TX descriptor */
+ emac_tx_desc->next = 0;
+ emac_tx_desc->buffer = (u_int8_t *) packet;
+ emac_tx_desc->buff_off_len = (length & 0xffff);
+ emac_tx_desc->pkt_flag_len = ((length & 0xffff) |
+ EMAC_CPPI_SOP_BIT |
+ EMAC_CPPI_OWNERSHIP_BIT |
+ EMAC_CPPI_EOP_BIT);
+
+ flush_dcache_range((unsigned long)packet,
+ (unsigned long)packet + ALIGN(length, PKTALIGN));
+
+ /* Send the packet */
+ writel(BD_TO_HW((unsigned long)emac_tx_desc), &adap_emac->TX0HDP);
+
+ /* Wait for packet to complete or link down */
+ while (1) {
+ if (!phy[index].get_link_speed(active_phy_addr[index])) {
+ davinci_eth_ch_teardown (EMAC_CH_TX);
+ return (ret_status);
+ }
+
+ if (readl(&adap_emac->TXINTSTATRAW) & 0x01) {
+ ret_status = length;
+ break;
+ }
+ tx_send_loop++;
+ }
+
+ return (ret_status);
+}
+
+/*
+ * This function handles receipt of a packet from the network
+ */
+static int davinci_eth_rcv_packet (struct eth_device *dev)
+{
+ volatile emac_desc *rx_curr_desc;
+ volatile emac_desc *curr_desc;
+ volatile emac_desc *tail_desc;
+ int status, ret = -1;
+
+ rx_curr_desc = emac_rx_active_head;
+ if (!rx_curr_desc)
+ return 0;
+ status = rx_curr_desc->pkt_flag_len;
+ if ((status & EMAC_CPPI_OWNERSHIP_BIT) == 0) {
+ if (status & EMAC_CPPI_RX_ERROR_FRAME) {
+ /* Error in packet - discard it and requeue desc */
+ printf ("WARN: emac_rcv_pkt: Error in packet\n");
+ } else {
+ unsigned long tmp = (unsigned long)rx_curr_desc->buffer;
+ unsigned short len =
+ rx_curr_desc->buff_off_len & 0xffff;
+
+ invalidate_dcache_range(tmp, tmp + ALIGN(len, PKTALIGN));
+ net_process_received_packet(rx_curr_desc->buffer, len);
+ ret = len;
+ }
+
+ /* Ack received packet descriptor */
+ writel(BD_TO_HW((ulong)rx_curr_desc), &adap_emac->RX0CP);
+ curr_desc = rx_curr_desc;
+ emac_rx_active_head =
+ (volatile emac_desc *) (HW_TO_BD(rx_curr_desc->next));
+
+ if (status & EMAC_CPPI_EOQ_BIT) {
+ if (emac_rx_active_head) {
+ writel(BD_TO_HW((ulong)emac_rx_active_head),
+ &adap_emac->RX0HDP);
+ } else {
+ emac_rx_queue_active = 0;
+ printf ("INFO:emac_rcv_packet: RX Queue not active\n");
+ }
+ }
+
+ /* Recycle RX descriptor */
+ rx_curr_desc->buff_off_len = EMAC_MAX_ETHERNET_PKT_SIZE;
+ rx_curr_desc->pkt_flag_len = EMAC_CPPI_OWNERSHIP_BIT;
+ rx_curr_desc->next = 0;
+
+ if (emac_rx_active_head == 0) {
+ printf ("INFO: emac_rcv_pkt: active queue head = 0\n");
+ emac_rx_active_head = curr_desc;
+ emac_rx_active_tail = curr_desc;
+ if (emac_rx_queue_active != 0) {
+ writel(BD_TO_HW((ulong)emac_rx_active_head),
+ &adap_emac->RX0HDP);
+ printf ("INFO: emac_rcv_pkt: active queue head = 0, HDP fired\n");
+ emac_rx_queue_active = 1;
+ }
+ } else {
+ tail_desc = emac_rx_active_tail;
+ emac_rx_active_tail = curr_desc;
+ tail_desc->next = BD_TO_HW((ulong) curr_desc);
+ status = tail_desc->pkt_flag_len;
+ if (status & EMAC_CPPI_EOQ_BIT) {
+ writel(BD_TO_HW((ulong)curr_desc),
+ &adap_emac->RX0HDP);
+ status &= ~EMAC_CPPI_EOQ_BIT;
+ tail_desc->pkt_flag_len = status;
+ }
+ }
+ return (ret);
+ }
+ return (0);
+}
+
+/*
+ * This function initializes the emac hardware. It does NOT initialize
+ * EMAC modules power or pin multiplexors, that is done by board_init()
+ * much earlier in bootup process. Returns 1 on success, 0 otherwise.
+ */
+int davinci_emac_initialize(void)
+{
+ u_int32_t phy_id;
+ u_int16_t tmp;
+ int i;
+ int ret;
+ struct eth_device *dev;
+
+ dev = malloc(sizeof *dev);
+
+ if (dev == NULL)
+ return -1;
+
+ memset(dev, 0, sizeof *dev);
+ strcpy(dev->name, "DaVinci-EMAC");
+
+ dev->iobase = 0;
+ dev->init = davinci_eth_open;
+ dev->halt = davinci_eth_close;
+ dev->send = davinci_eth_send_packet;
+ dev->recv = davinci_eth_rcv_packet;
+ dev->write_hwaddr = davinci_eth_set_mac_addr;
+
+ eth_register(dev);
+
+ davinci_eth_mdio_enable();
+
+ /* let the EMAC detect the PHYs */
+ udelay(5000);
+
+ for (i = 0; i < 256; i++) {
+ if (readl(&adap_mdio->ALIVE))
+ break;
+ udelay(1000);
+ }
+
+ if (i >= 256) {
+ printf("No ETH PHY detected!!!\n");
+ return(0);
+ }
+
+ /* Find if PHY(s) is/are connected */
+ ret = davinci_eth_phy_detect();
+ if (!ret)
+ return(0);
+ else
+ debug_emac(" %d ETH PHY detected\n", ret);
+
+ /* Get PHY ID and initialize phy_ops for a detected PHY */
+ for (i = 0; i < num_phy; i++) {
+ if (!davinci_eth_phy_read(active_phy_addr[i], MII_PHYSID1,
+ &tmp)) {
+ active_phy_addr[i] = 0xff;
+ continue;
+ }
+
+ phy_id = (tmp << 16) & 0xffff0000;
+
+ if (!davinci_eth_phy_read(active_phy_addr[i], MII_PHYSID2,
+ &tmp)) {
+ active_phy_addr[i] = 0xff;
+ continue;
+ }
+
+ phy_id |= tmp & 0x0000ffff;
+
+ switch (phy_id) {
+#ifdef PHY_KSZ8873
+ case PHY_KSZ8873:
+ sprintf(phy[i].name, "KSZ8873 @ 0x%02x",
+ active_phy_addr[i]);
+ phy[i].init = ksz8873_init_phy;
+ phy[i].is_phy_connected = ksz8873_is_phy_connected;
+ phy[i].get_link_speed = ksz8873_get_link_speed;
+ phy[i].auto_negotiate = ksz8873_auto_negotiate;
+ break;
+#endif
+#ifdef PHY_LXT972
+ case PHY_LXT972:
+ sprintf(phy[i].name, "LXT972 @ 0x%02x",
+ active_phy_addr[i]);
+ phy[i].init = lxt972_init_phy;
+ phy[i].is_phy_connected = lxt972_is_phy_connected;
+ phy[i].get_link_speed = lxt972_get_link_speed;
+ phy[i].auto_negotiate = lxt972_auto_negotiate;
+ break;
+#endif
+#ifdef PHY_DP83848
+ case PHY_DP83848:
+ sprintf(phy[i].name, "DP83848 @ 0x%02x",
+ active_phy_addr[i]);
+ phy[i].init = dp83848_init_phy;
+ phy[i].is_phy_connected = dp83848_is_phy_connected;
+ phy[i].get_link_speed = dp83848_get_link_speed;
+ phy[i].auto_negotiate = dp83848_auto_negotiate;
+ break;
+#endif
+#ifdef PHY_ET1011C
+ case PHY_ET1011C:
+ sprintf(phy[i].name, "ET1011C @ 0x%02x",
+ active_phy_addr[i]);
+ phy[i].init = gen_init_phy;
+ phy[i].is_phy_connected = gen_is_phy_connected;
+ phy[i].get_link_speed = et1011c_get_link_speed;
+ phy[i].auto_negotiate = gen_auto_negotiate;
+ break;
+#endif
+ default:
+ sprintf(phy[i].name, "GENERIC @ 0x%02x",
+ active_phy_addr[i]);
+ phy[i].init = gen_init_phy;
+ phy[i].is_phy_connected = gen_is_phy_connected;
+ phy[i].get_link_speed = gen_get_link_speed;
+ phy[i].auto_negotiate = gen_auto_negotiate;
+ }
+
+ debug("Ethernet PHY: %s\n", phy[i].name);
+
+ int retval;
+ struct mii_dev *mdiodev = mdio_alloc();
+ if (!mdiodev)
+ return -ENOMEM;
+ strncpy(mdiodev->name, phy[i].name, MDIO_NAME_LEN);
+ mdiodev->read = davinci_mii_phy_read;
+ mdiodev->write = davinci_mii_phy_write;
+
+ retval = mdio_register(mdiodev);
+ if (retval < 0)
+ return retval;
+#ifdef DAVINCI_EMAC_GIG_ENABLE
+#define PHY_CONF_REG 22
+ /* Enable PHY to clock out TX_CLK */
+ davinci_eth_phy_read(active_phy_addr[i], PHY_CONF_REG, &tmp);
+ tmp |= PHY_CONF_TXCLKEN;
+ davinci_eth_phy_write(active_phy_addr[i], PHY_CONF_REG, tmp);
+ davinci_eth_phy_read(active_phy_addr[i], PHY_CONF_REG, &tmp);
+#endif
+ }
+
+#if defined(CONFIG_TI816X) || (defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \
+ defined(CONFIG_MACH_DAVINCI_DA850_EVM) && \
+ !defined(CONFIG_DRIVER_TI_EMAC_RMII_NO_NEGOTIATE))
+ for (i = 0; i < num_phy; i++) {
+ if (phy[i].is_phy_connected(i))
+ phy[i].auto_negotiate(i);
+ }
+#endif
+ return(1);
+}
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2011 Ilya Yanok, Emcraft Systems
+ *
+ * Based on: mach-davinci/emac_defs.h
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ */
+
+#ifndef _DAVINCI_EMAC_H_
+#define _DAVINCI_EMAC_H_
+/* Ethernet Min/Max packet size */
+#define EMAC_MIN_ETHERNET_PKT_SIZE 60
+#define EMAC_MAX_ETHERNET_PKT_SIZE 1518
+/* Buffer size (should be aligned on 32 byte and cache line) */
+#define EMAC_RXBUF_SIZE ALIGN(ALIGN(EMAC_MAX_ETHERNET_PKT_SIZE, 32),\
+ ARCH_DMA_MINALIGN)
+
+/* Number of RX packet buffers
+ * NOTE: Only 1 buffer supported as of now
+ */
+#define EMAC_MAX_RX_BUFFERS 10
+
+
+/***********************************************
+ ******** Internally used macros ***************
+ ***********************************************/
+
+#define EMAC_CH_TX 1
+#define EMAC_CH_RX 0
+
+/* Each descriptor occupies 4 words, lets start RX desc's at 0 and
+ * reserve space for 64 descriptors max
+ */
+#define EMAC_RX_DESC_BASE 0x0
+#define EMAC_TX_DESC_BASE 0x1000
+
+/* EMAC Teardown value */
+#define EMAC_TEARDOWN_VALUE 0xfffffffc
+
+/* MII Status Register */
+#define MII_STATUS_REG 1
+/* PHY Configuration register */
+#define PHY_CONF_TXCLKEN (1 << 5)
+
+/* Number of statistics registers */
+#define EMAC_NUM_STATS 36
+
+
+/* EMAC Descriptor */
+typedef volatile struct _emac_desc
+{
+ u_int32_t next; /* Pointer to next descriptor
+ in chain */
+ u_int8_t *buffer; /* Pointer to data buffer */
+ u_int32_t buff_off_len; /* Buffer Offset(MSW) and Length(LSW) */
+ u_int32_t pkt_flag_len; /* Packet Flags(MSW) and Length(LSW) */
+} emac_desc;
+
+/* CPPI bit positions */
+#define EMAC_CPPI_SOP_BIT (0x80000000)
+#define EMAC_CPPI_EOP_BIT (0x40000000)
+#define EMAC_CPPI_OWNERSHIP_BIT (0x20000000)
+#define EMAC_CPPI_EOQ_BIT (0x10000000)
+#define EMAC_CPPI_TEARDOWN_COMPLETE_BIT (0x08000000)
+#define EMAC_CPPI_PASS_CRC_BIT (0x04000000)
+
+#define EMAC_CPPI_RX_ERROR_FRAME (0x03fc0000)
+
+#define EMAC_MACCONTROL_MIIEN_ENABLE (0x20)
+#define EMAC_MACCONTROL_FULLDUPLEX_ENABLE (0x1)
+#define EMAC_MACCONTROL_GIGABIT_ENABLE (1 << 7)
+#define EMAC_MACCONTROL_GIGFORCE (1 << 17)
+#define EMAC_MACCONTROL_RMIISPEED_100 (1 << 15)
+
+#define EMAC_MAC_ADDR_MATCH (1 << 19)
+#define EMAC_MAC_ADDR_IS_VALID (1 << 20)
+
+#define EMAC_RXMBPENABLE_RXCAFEN_ENABLE (0x200000)
+#define EMAC_RXMBPENABLE_RXBROADEN (0x2000)
+
+
+#define MDIO_CONTROL_IDLE (0x80000000)
+#define MDIO_CONTROL_ENABLE (0x40000000)
+#define MDIO_CONTROL_FAULT_ENABLE (0x40000)
+#define MDIO_CONTROL_FAULT (0x80000)
+#define MDIO_USERACCESS0_GO (0x80000000)
+#define MDIO_USERACCESS0_WRITE_READ (0x0)
+#define MDIO_USERACCESS0_WRITE_WRITE (0x40000000)
+#define MDIO_USERACCESS0_ACK (0x20000000)
+
+/* Ethernet MAC Registers Structure */
+typedef struct {
+ dv_reg TXIDVER;
+ dv_reg TXCONTROL;
+ dv_reg TXTEARDOWN;
+ u_int8_t RSVD0[4];
+ dv_reg RXIDVER;
+ dv_reg RXCONTROL;
+ dv_reg RXTEARDOWN;
+ u_int8_t RSVD1[100];
+ dv_reg TXINTSTATRAW;
+ dv_reg TXINTSTATMASKED;
+ dv_reg TXINTMASKSET;
+ dv_reg TXINTMASKCLEAR;
+ dv_reg MACINVECTOR;
+ u_int8_t RSVD2[12];
+ dv_reg RXINTSTATRAW;
+ dv_reg RXINTSTATMASKED;
+ dv_reg RXINTMASKSET;
+ dv_reg RXINTMASKCLEAR;
+ dv_reg MACINTSTATRAW;
+ dv_reg MACINTSTATMASKED;
+ dv_reg MACINTMASKSET;
+ dv_reg MACINTMASKCLEAR;
+ u_int8_t RSVD3[64];
+ dv_reg RXMBPENABLE;
+ dv_reg RXUNICASTSET;
+ dv_reg RXUNICASTCLEAR;
+ dv_reg RXMAXLEN;
+ dv_reg RXBUFFEROFFSET;
+ dv_reg RXFILTERLOWTHRESH;
+ u_int8_t RSVD4[8];
+ dv_reg RX0FLOWTHRESH;
+ dv_reg RX1FLOWTHRESH;
+ dv_reg RX2FLOWTHRESH;
+ dv_reg RX3FLOWTHRESH;
+ dv_reg RX4FLOWTHRESH;
+ dv_reg RX5FLOWTHRESH;
+ dv_reg RX6FLOWTHRESH;
+ dv_reg RX7FLOWTHRESH;
+ dv_reg RX0FREEBUFFER;
+ dv_reg RX1FREEBUFFER;
+ dv_reg RX2FREEBUFFER;
+ dv_reg RX3FREEBUFFER;
+ dv_reg RX4FREEBUFFER;
+ dv_reg RX5FREEBUFFER;
+ dv_reg RX6FREEBUFFER;
+ dv_reg RX7FREEBUFFER;
+ dv_reg MACCONTROL;
+ dv_reg MACSTATUS;
+ dv_reg EMCONTROL;
+ dv_reg FIFOCONTROL;
+ dv_reg MACCONFIG;
+ dv_reg SOFTRESET;
+ u_int8_t RSVD5[88];
+ dv_reg MACSRCADDRLO;
+ dv_reg MACSRCADDRHI;
+ dv_reg MACHASH1;
+ dv_reg MACHASH2;
+ dv_reg BOFFTEST;
+ dv_reg TPACETEST;
+ dv_reg RXPAUSE;
+ dv_reg TXPAUSE;
+ u_int8_t RSVD6[16];
+ dv_reg RXGOODFRAMES;
+ dv_reg RXBCASTFRAMES;
+ dv_reg RXMCASTFRAMES;
+ dv_reg RXPAUSEFRAMES;
+ dv_reg RXCRCERRORS;
+ dv_reg RXALIGNCODEERRORS;
+ dv_reg RXOVERSIZED;
+ dv_reg RXJABBER;
+ dv_reg RXUNDERSIZED;
+ dv_reg RXFRAGMENTS;
+ dv_reg RXFILTERED;
+ dv_reg RXQOSFILTERED;
+ dv_reg RXOCTETS;
+ dv_reg TXGOODFRAMES;
+ dv_reg TXBCASTFRAMES;
+ dv_reg TXMCASTFRAMES;
+ dv_reg TXPAUSEFRAMES;
+ dv_reg TXDEFERRED;
+ dv_reg TXCOLLISION;
+ dv_reg TXSINGLECOLL;
+ dv_reg TXMULTICOLL;
+ dv_reg TXEXCESSIVECOLL;
+ dv_reg TXLATECOLL;
+ dv_reg TXUNDERRUN;
+ dv_reg TXCARRIERSENSE;
+ dv_reg TXOCTETS;
+ dv_reg FRAME64;
+ dv_reg FRAME65T127;
+ dv_reg FRAME128T255;
+ dv_reg FRAME256T511;
+ dv_reg FRAME512T1023;
+ dv_reg FRAME1024TUP;
+ dv_reg NETOCTETS;
+ dv_reg RXSOFOVERRUNS;
+ dv_reg RXMOFOVERRUNS;
+ dv_reg RXDMAOVERRUNS;
+ u_int8_t RSVD7[624];
+ dv_reg MACADDRLO;
+ dv_reg MACADDRHI;
+ dv_reg MACINDEX;
+ u_int8_t RSVD8[244];
+ dv_reg TX0HDP;
+ dv_reg TX1HDP;
+ dv_reg TX2HDP;
+ dv_reg TX3HDP;
+ dv_reg TX4HDP;
+ dv_reg TX5HDP;
+ dv_reg TX6HDP;
+ dv_reg TX7HDP;
+ dv_reg RX0HDP;
+ dv_reg RX1HDP;
+ dv_reg RX2HDP;
+ dv_reg RX3HDP;
+ dv_reg RX4HDP;
+ dv_reg RX5HDP;
+ dv_reg RX6HDP;
+ dv_reg RX7HDP;
+ dv_reg TX0CP;
+ dv_reg TX1CP;
+ dv_reg TX2CP;
+ dv_reg TX3CP;
+ dv_reg TX4CP;
+ dv_reg TX5CP;
+ dv_reg TX6CP;
+ dv_reg TX7CP;
+ dv_reg RX0CP;
+ dv_reg RX1CP;
+ dv_reg RX2CP;
+ dv_reg RX3CP;
+ dv_reg RX4CP;
+ dv_reg RX5CP;
+ dv_reg RX6CP;
+ dv_reg RX7CP;
+} emac_regs;
+
+/* EMAC Wrapper Registers Structure */
+typedef struct {
+#ifdef DAVINCI_EMAC_VERSION2
+ dv_reg idver;
+ dv_reg softrst;
+ dv_reg emctrl;
+ dv_reg c0rxthreshen;
+ dv_reg c0rxen;
+ dv_reg c0txen;
+ dv_reg c0miscen;
+ dv_reg c1rxthreshen;
+ dv_reg c1rxen;
+ dv_reg c1txen;
+ dv_reg c1miscen;
+ dv_reg c2rxthreshen;
+ dv_reg c2rxen;
+ dv_reg c2txen;
+ dv_reg c2miscen;
+ dv_reg c0rxthreshstat;
+ dv_reg c0rxstat;
+ dv_reg c0txstat;
+ dv_reg c0miscstat;
+ dv_reg c1rxthreshstat;
+ dv_reg c1rxstat;
+ dv_reg c1txstat;
+ dv_reg c1miscstat;
+ dv_reg c2rxthreshstat;
+ dv_reg c2rxstat;
+ dv_reg c2txstat;
+ dv_reg c2miscstat;
+ dv_reg c0rximax;
+ dv_reg c0tximax;
+ dv_reg c1rximax;
+ dv_reg c1tximax;
+ dv_reg c2rximax;
+ dv_reg c2tximax;
+#else
+ u_int8_t RSVD0[4100];
+ dv_reg EWCTL;
+ dv_reg EWINTTCNT;
+#endif
+} ewrap_regs;
+
+/* EMAC MDIO Registers Structure */
+typedef struct {
+ dv_reg VERSION;
+ dv_reg CONTROL;
+ dv_reg ALIVE;
+ dv_reg LINK;
+ dv_reg LINKINTRAW;
+ dv_reg LINKINTMASKED;
+ u_int8_t RSVD0[8];
+ dv_reg USERINTRAW;
+ dv_reg USERINTMASKED;
+ dv_reg USERINTMASKSET;
+ dv_reg USERINTMASKCLEAR;
+ u_int8_t RSVD1[80];
+ dv_reg USERACCESS0;
+ dv_reg USERPHYSEL0;
+ dv_reg USERACCESS1;
+ dv_reg USERPHYSEL1;
+} mdio_regs;
+
+int davinci_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t *data);
+int davinci_eth_phy_write(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t data);
+
+typedef struct {
+ char name[64];
+ int (*init)(int phy_addr);
+ int (*is_phy_connected)(int phy_addr);
+ int (*get_link_speed)(int phy_addr);
+ int (*auto_negotiate)(int phy_addr);
+} phy_t;
+
+#endif /* _DAVINCI_EMAC_H_ */
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Ethernet driver for TI K2HK EVM.
+ *
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ */
+#include <common.h>
+#include <command.h>
+#include <console.h>
+
+#include <dm.h>
+#include <dm/lists.h>
+
+#include <net.h>
+#include <phy.h>
+#include <errno.h>
+#include <miiphy.h>
+#include <malloc.h>
+#include <asm/ti-common/keystone_nav.h>
+#include <asm/ti-common/keystone_net.h>
+#include <asm/ti-common/keystone_serdes.h>
+#include <asm/arch/psc_defs.h>
+
+#include "cpsw_mdio.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef KEYSTONE2_EMAC_GIG_ENABLE
+#define emac_gigabit_enable(x) keystone2_eth_gigabit_enable(x)
+#else
+#define emac_gigabit_enable(x) /* no gigabit to enable */
+#endif
+
+#define RX_BUFF_NUMS 24
+#define RX_BUFF_LEN 1520
+#define MAX_SIZE_STREAM_BUFFER RX_BUFF_LEN
+#define SGMII_ANEG_TIMEOUT 4000
+
+static u8 rx_buffs[RX_BUFF_NUMS * RX_BUFF_LEN] __aligned(16);
+
+enum link_type {
+ LINK_TYPE_SGMII_MAC_TO_MAC_AUTO = 0,
+ LINK_TYPE_SGMII_MAC_TO_PHY_MODE = 1,
+ LINK_TYPE_SGMII_MAC_TO_MAC_FORCED_MODE = 2,
+ LINK_TYPE_SGMII_MAC_TO_FIBRE_MODE = 3,
+ LINK_TYPE_SGMII_MAC_TO_PHY_NO_MDIO_MODE = 4,
+ LINK_TYPE_RGMII_LINK_MAC_PHY = 5,
+ LINK_TYPE_RGMII_LINK_MAC_MAC_FORCED = 6,
+ LINK_TYPE_RGMII_LINK_MAC_PHY_NO_MDIO = 7,
+ LINK_TYPE_10G_MAC_TO_PHY_MODE = 10,
+ LINK_TYPE_10G_MAC_TO_MAC_FORCED_MODE = 11,
+};
+
+#define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \
+ ((mac)[2] << 16) | ((mac)[3] << 24))
+#define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8))
+
+#ifdef CONFIG_KSNET_NETCP_V1_0
+
+#define EMAC_EMACSW_BASE_OFS 0x90800
+#define EMAC_EMACSW_PORT_BASE_OFS (EMAC_EMACSW_BASE_OFS + 0x60)
+
+/* CPSW Switch slave registers */
+#define CPGMACSL_REG_SA_LO 0x10
+#define CPGMACSL_REG_SA_HI 0x14
+
+#define DEVICE_EMACSW_BASE(base, x) ((base) + EMAC_EMACSW_PORT_BASE_OFS + \
+ (x) * 0x30)
+
+#elif defined(CONFIG_KSNET_NETCP_V1_5)
+
+#define EMAC_EMACSW_PORT_BASE_OFS 0x222000
+
+/* CPSW Switch slave registers */
+#define CPGMACSL_REG_SA_LO 0x308
+#define CPGMACSL_REG_SA_HI 0x30c
+
+#define DEVICE_EMACSW_BASE(base, x) ((base) + EMAC_EMACSW_PORT_BASE_OFS + \
+ (x) * 0x1000)
+
+#endif
+
+
+struct ks2_eth_priv {
+ struct udevice *dev;
+ struct phy_device *phydev;
+ struct mii_dev *mdio_bus;
+ int phy_addr;
+ phy_interface_t phy_if;
+ int sgmii_link_type;
+ void *mdio_base;
+ struct rx_buff_desc net_rx_buffs;
+ struct pktdma_cfg *netcp_pktdma;
+ void *hd;
+ int slave_port;
+ enum link_type link_type;
+ bool emac_open;
+ bool has_mdio;
+};
+
+static void __attribute__((unused))
+ keystone2_eth_gigabit_enable(struct udevice *dev)
+{
+ struct ks2_eth_priv *priv = dev_get_priv(dev);
+
+ /*
+ * Check if link detected is giga-bit
+ * If Gigabit mode detected, enable gigbit in MAC
+ */
+ if (priv->has_mdio) {
+ if (priv->phydev->speed != 1000)
+ return;
+ }
+
+ writel(readl(DEVICE_EMACSL_BASE(priv->slave_port - 1) +
+ CPGMACSL_REG_CTL) |
+ EMAC_MACCONTROL_GIGFORCE | EMAC_MACCONTROL_GIGABIT_ENABLE,
+ DEVICE_EMACSL_BASE(priv->slave_port - 1) + CPGMACSL_REG_CTL);
+}
+
+#ifdef CONFIG_SOC_K2G
+int keystone_rgmii_config(struct phy_device *phy_dev)
+{
+ unsigned int i, status;
+
+ i = 0;
+ do {
+ if (i > SGMII_ANEG_TIMEOUT) {
+ puts(" TIMEOUT !\n");
+ phy_dev->link = 0;
+ return 0;
+ }
+
+ if (ctrlc()) {
+ puts("user interrupt!\n");
+ phy_dev->link = 0;
+ return -EINTR;
+ }
+
+ if ((i++ % 500) == 0)
+ printf(".");
+
+ udelay(1000); /* 1 ms */
+ status = readl(RGMII_STATUS_REG);
+ } while (!(status & RGMII_REG_STATUS_LINK));
+
+ puts(" done\n");
+
+ return 0;
+}
+#else
+int keystone_sgmii_config(struct phy_device *phy_dev, int port, int interface)
+{
+ unsigned int i, status, mask;
+ unsigned int mr_adv_ability, control;
+
+ switch (interface) {
+ case SGMII_LINK_MAC_MAC_AUTONEG:
+ mr_adv_ability = (SGMII_REG_MR_ADV_ENABLE |
+ SGMII_REG_MR_ADV_LINK |
+ SGMII_REG_MR_ADV_FULL_DUPLEX |
+ SGMII_REG_MR_ADV_GIG_MODE);
+ control = (SGMII_REG_CONTROL_MASTER |
+ SGMII_REG_CONTROL_AUTONEG);
+
+ break;
+ case SGMII_LINK_MAC_PHY:
+ case SGMII_LINK_MAC_PHY_FORCED:
+ mr_adv_ability = SGMII_REG_MR_ADV_ENABLE;
+ control = SGMII_REG_CONTROL_AUTONEG;
+
+ break;
+ case SGMII_LINK_MAC_MAC_FORCED:
+ mr_adv_ability = (SGMII_REG_MR_ADV_ENABLE |
+ SGMII_REG_MR_ADV_LINK |
+ SGMII_REG_MR_ADV_FULL_DUPLEX |
+ SGMII_REG_MR_ADV_GIG_MODE);
+ control = SGMII_REG_CONTROL_MASTER;
+
+ break;
+ case SGMII_LINK_MAC_FIBER:
+ mr_adv_ability = 0x20;
+ control = SGMII_REG_CONTROL_AUTONEG;
+
+ break;
+ default:
+ mr_adv_ability = SGMII_REG_MR_ADV_ENABLE;
+ control = SGMII_REG_CONTROL_AUTONEG;
+ }
+
+ __raw_writel(0, SGMII_CTL_REG(port));
+
+ /*
+ * Wait for the SerDes pll to lock,
+ * but don't trap if lock is never read
+ */
+ for (i = 0; i < 1000; i++) {
+ udelay(2000);
+ status = __raw_readl(SGMII_STATUS_REG(port));
+ if ((status & SGMII_REG_STATUS_LOCK) != 0)
+ break;
+ }
+
+ __raw_writel(mr_adv_ability, SGMII_MRADV_REG(port));
+ __raw_writel(control, SGMII_CTL_REG(port));
+
+
+ mask = SGMII_REG_STATUS_LINK;
+
+ if (control & SGMII_REG_CONTROL_AUTONEG)
+ mask |= SGMII_REG_STATUS_AUTONEG;
+
+ status = __raw_readl(SGMII_STATUS_REG(port));
+ if ((status & mask) == mask)
+ return 0;
+
+ printf("\n%s Waiting for SGMII auto negotiation to complete",
+ phy_dev->dev->name);
+ while ((status & mask) != mask) {
+ /*
+ * Timeout reached ?
+ */
+ if (i > SGMII_ANEG_TIMEOUT) {
+ puts(" TIMEOUT !\n");
+ phy_dev->link = 0;
+ return 0;
+ }
+
+ if (ctrlc()) {
+ puts("user interrupt!\n");
+ phy_dev->link = 0;
+ return -EINTR;
+ }
+
+ if ((i++ % 500) == 0)
+ printf(".");
+
+ udelay(1000); /* 1 ms */
+ status = __raw_readl(SGMII_STATUS_REG(port));
+ }
+ puts(" done\n");
+
+ return 0;
+}
+#endif
+
+int mac_sl_reset(u32 port)
+{
+ u32 i, v;
+
+ if (port >= DEVICE_N_GMACSL_PORTS)
+ return GMACSL_RET_INVALID_PORT;
+
+ /* Set the soft reset bit */
+ writel(CPGMAC_REG_RESET_VAL_RESET,
+ DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RESET);
+
+ /* Wait for the bit to clear */
+ for (i = 0; i < DEVICE_EMACSL_RESET_POLL_COUNT; i++) {
+ v = readl(DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RESET);
+ if ((v & CPGMAC_REG_RESET_VAL_RESET_MASK) !=
+ CPGMAC_REG_RESET_VAL_RESET)
+ return GMACSL_RET_OK;
+ }
+
+ /* Timeout on the reset */
+ return GMACSL_RET_WARN_RESET_INCOMPLETE;
+}
+
+int mac_sl_config(u_int16_t port, struct mac_sl_cfg *cfg)
+{
+ u32 v, i;
+ int ret = GMACSL_RET_OK;
+
+ if (port >= DEVICE_N_GMACSL_PORTS)
+ return GMACSL_RET_INVALID_PORT;
+
+ if (cfg->max_rx_len > CPGMAC_REG_MAXLEN_LEN) {
+ cfg->max_rx_len = CPGMAC_REG_MAXLEN_LEN;
+ ret = GMACSL_RET_WARN_MAXLEN_TOO_BIG;
+ }
+
+ /* Must wait if the device is undergoing reset */
+ for (i = 0; i < DEVICE_EMACSL_RESET_POLL_COUNT; i++) {
+ v = readl(DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RESET);
+ if ((v & CPGMAC_REG_RESET_VAL_RESET_MASK) !=
+ CPGMAC_REG_RESET_VAL_RESET)
+ break;
+ }
+
+ if (i == DEVICE_EMACSL_RESET_POLL_COUNT)
+ return GMACSL_RET_CONFIG_FAIL_RESET_ACTIVE;
+
+ writel(cfg->max_rx_len, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_MAXLEN);
+ writel(cfg->ctl, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_CTL);
+
+#ifndef CONFIG_SOC_K2HK
+ /* Map RX packet flow priority to 0 */
+ writel(0, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RX_PRI_MAP);
+#endif
+
+ return ret;
+}
+
+int ethss_config(u32 ctl, u32 max_pkt_size)
+{
+ u32 i;
+
+ /* Max length register */
+ writel(max_pkt_size, DEVICE_CPSW_BASE + CPSW_REG_MAXLEN);
+
+ /* Control register */
+ writel(ctl, DEVICE_CPSW_BASE + CPSW_REG_CTL);
+
+ /* All statistics enabled by default */
+ writel(CPSW_REG_VAL_STAT_ENABLE_ALL,
+ DEVICE_CPSW_BASE + CPSW_REG_STAT_PORT_EN);
+
+ /* Reset and enable the ALE */
+ writel(CPSW_REG_VAL_ALE_CTL_RESET_AND_ENABLE |
+ CPSW_REG_VAL_ALE_CTL_BYPASS,
+ DEVICE_CPSW_BASE + CPSW_REG_ALE_CONTROL);
+
+ /* All ports put into forward mode */
+ for (i = 0; i < DEVICE_CPSW_NUM_PORTS; i++)
+ writel(CPSW_REG_VAL_PORTCTL_FORWARD_MODE,
+ DEVICE_CPSW_BASE + CPSW_REG_ALE_PORTCTL(i));
+
+ return 0;
+}
+
+int ethss_start(void)
+{
+ int i;
+ struct mac_sl_cfg cfg;
+
+ cfg.max_rx_len = MAX_SIZE_STREAM_BUFFER;
+ cfg.ctl = GMACSL_ENABLE | GMACSL_RX_ENABLE_EXT_CTL;
+
+ for (i = 0; i < DEVICE_N_GMACSL_PORTS; i++) {
+ mac_sl_reset(i);
+ mac_sl_config(i, &cfg);
+ }
+
+ return 0;
+}
+
+int ethss_stop(void)
+{
+ int i;
+
+ for (i = 0; i < DEVICE_N_GMACSL_PORTS; i++)
+ mac_sl_reset(i);
+
+ return 0;
+}
+
+struct ks2_serdes ks2_serdes_sgmii_156p25mhz = {
+ .clk = SERDES_CLOCK_156P25M,
+ .rate = SERDES_RATE_5G,
+ .rate_mode = SERDES_QUARTER_RATE,
+ .intf = SERDES_PHY_SGMII,
+ .loopback = 0,
+};
+
+#ifndef CONFIG_SOC_K2G
+static void keystone2_net_serdes_setup(void)
+{
+ ks2_serdes_init(CONFIG_KSNET_SERDES_SGMII_BASE,
+ &ks2_serdes_sgmii_156p25mhz,
+ CONFIG_KSNET_SERDES_LANES_PER_SGMII);
+
+#if defined(CONFIG_SOC_K2E) || defined(CONFIG_SOC_K2L)
+ ks2_serdes_init(CONFIG_KSNET_SERDES_SGMII2_BASE,
+ &ks2_serdes_sgmii_156p25mhz,
+ CONFIG_KSNET_SERDES_LANES_PER_SGMII);
+#endif
+
+ /* wait till setup */
+ udelay(5000);
+}
+#endif
+
+static int ks2_eth_start(struct udevice *dev)
+{
+ struct ks2_eth_priv *priv = dev_get_priv(dev);
+
+#ifdef CONFIG_SOC_K2G
+ keystone_rgmii_config(priv->phydev);
+#else
+ keystone_sgmii_config(priv->phydev, priv->slave_port - 1,
+ priv->sgmii_link_type);
+#endif
+
+ udelay(10000);
+
+ /* On chip switch configuration */
+ ethss_config(target_get_switch_ctl(), SWITCH_MAX_PKT_SIZE);
+
+ qm_init();
+
+ if (ksnav_init(priv->netcp_pktdma, &priv->net_rx_buffs)) {
+ pr_err("ksnav_init failed\n");
+ goto err_knav_init;
+ }
+
+ /*
+ * Streaming switch configuration. If not present this
+ * statement is defined to void in target.h.
+ * If present this is usually defined to a series of register writes
+ */
+ hw_config_streaming_switch();
+
+ if (priv->has_mdio) {
+ phy_startup(priv->phydev);
+ if (priv->phydev->link == 0) {
+ pr_err("phy startup failed\n");
+ goto err_phy_start;
+ }
+ }
+
+ emac_gigabit_enable(dev);
+
+ ethss_start();
+
+ priv->emac_open = true;
+
+ return 0;
+
+err_phy_start:
+ ksnav_close(priv->netcp_pktdma);
+err_knav_init:
+ qm_close();
+
+ return -EFAULT;
+}
+
+static int ks2_eth_send(struct udevice *dev, void *packet, int length)
+{
+ struct ks2_eth_priv *priv = dev_get_priv(dev);
+
+ genphy_update_link(priv->phydev);
+ if (priv->phydev->link == 0)
+ return -1;
+
+ if (length < EMAC_MIN_ETHERNET_PKT_SIZE)
+ length = EMAC_MIN_ETHERNET_PKT_SIZE;
+
+ return ksnav_send(priv->netcp_pktdma, (u32 *)packet,
+ length, (priv->slave_port) << 16);
+}
+
+static int ks2_eth_recv(struct udevice *dev, int flags, uchar **packetp)
+{
+ struct ks2_eth_priv *priv = dev_get_priv(dev);
+ int pkt_size;
+ u32 *pkt = NULL;
+
+ priv->hd = ksnav_recv(priv->netcp_pktdma, &pkt, &pkt_size);
+ if (priv->hd == NULL)
+ return -EAGAIN;
+
+ *packetp = (uchar *)pkt;
+
+ return pkt_size;
+}
+
+static int ks2_eth_free_pkt(struct udevice *dev, uchar *packet,
+ int length)
+{
+ struct ks2_eth_priv *priv = dev_get_priv(dev);
+
+ ksnav_release_rxhd(priv->netcp_pktdma, priv->hd);
+
+ return 0;
+}
+
+static void ks2_eth_stop(struct udevice *dev)
+{
+ struct ks2_eth_priv *priv = dev_get_priv(dev);
+
+ if (!priv->emac_open)
+ return;
+ ethss_stop();
+
+ ksnav_close(priv->netcp_pktdma);
+ qm_close();
+ phy_shutdown(priv->phydev);
+ priv->emac_open = false;
+}
+
+int ks2_eth_read_rom_hwaddr(struct udevice *dev)
+{
+ struct ks2_eth_priv *priv = dev_get_priv(dev);
+ struct eth_pdata *pdata = dev_get_platdata(dev);
+ u32 maca = 0;
+ u32 macb = 0;
+
+ /* Read the e-fuse mac address */
+ if (priv->slave_port == 1) {
+ maca = __raw_readl(MAC_ID_BASE_ADDR);
+ macb = __raw_readl(MAC_ID_BASE_ADDR + 4);
+ }
+
+ pdata->enetaddr[0] = (macb >> 8) & 0xff;
+ pdata->enetaddr[1] = (macb >> 0) & 0xff;
+ pdata->enetaddr[2] = (maca >> 24) & 0xff;
+ pdata->enetaddr[3] = (maca >> 16) & 0xff;
+ pdata->enetaddr[4] = (maca >> 8) & 0xff;
+ pdata->enetaddr[5] = (maca >> 0) & 0xff;
+
+ return 0;
+}
+
+int ks2_eth_write_hwaddr(struct udevice *dev)
+{
+ struct ks2_eth_priv *priv = dev_get_priv(dev);
+ struct eth_pdata *pdata = dev_get_platdata(dev);
+
+ writel(mac_hi(pdata->enetaddr),
+ DEVICE_EMACSW_BASE(pdata->iobase, priv->slave_port - 1) +
+ CPGMACSL_REG_SA_HI);
+ writel(mac_lo(pdata->enetaddr),
+ DEVICE_EMACSW_BASE(pdata->iobase, priv->slave_port - 1) +
+ CPGMACSL_REG_SA_LO);
+
+ return 0;
+}
+
+static int ks2_eth_probe(struct udevice *dev)
+{
+ struct ks2_eth_priv *priv = dev_get_priv(dev);
+ struct mii_dev *mdio_bus;
+
+ priv->dev = dev;
+ priv->emac_open = false;
+
+ /* These clock enables has to be moved to common location */
+ if (cpu_is_k2g())
+ writel(KS2_ETHERNET_RGMII, KS2_ETHERNET_CFG);
+
+ /* By default, select PA PLL clock as PA clock source */
+#ifndef CONFIG_SOC_K2G
+ if (psc_enable_module(KS2_LPSC_PA))
+ return -EACCES;
+#endif
+ if (psc_enable_module(KS2_LPSC_CPGMAC))
+ return -EACCES;
+ if (psc_enable_module(KS2_LPSC_CRYPTO))
+ return -EACCES;
+
+ if (cpu_is_k2e() || cpu_is_k2l())
+ pll_pa_clk_sel();
+
+ priv->net_rx_buffs.buff_ptr = rx_buffs;
+ priv->net_rx_buffs.num_buffs = RX_BUFF_NUMS;
+ priv->net_rx_buffs.buff_len = RX_BUFF_LEN;
+
+ if (priv->slave_port == 1) {
+#ifndef CONFIG_SOC_K2G
+ keystone2_net_serdes_setup();
+#endif
+ /*
+ * Register MDIO bus for slave 0 only, other slave have
+ * to re-use the same
+ */
+ mdio_bus = cpsw_mdio_init("ethernet-mdio",
+ (u32)priv->mdio_base,
+ EMAC_MDIO_CLOCK_FREQ,
+ EMAC_MDIO_BUS_FREQ);
+ if (!mdio_bus) {
+ pr_err("MDIO alloc failed\n");
+ return -ENOMEM;
+ }
+ priv->mdio_bus = mdio_bus;
+ } else {
+ /* Get the MDIO bus from slave 0 device */
+ struct ks2_eth_priv *parent_priv;
+
+ parent_priv = dev_get_priv(dev->parent);
+ priv->mdio_bus = parent_priv->mdio_bus;
+ priv->mdio_base = parent_priv->mdio_base;
+ }
+
+ priv->netcp_pktdma = &netcp_pktdma;
+
+ if (priv->has_mdio) {
+ priv->phydev = phy_connect(priv->mdio_bus, priv->phy_addr,
+ dev, priv->phy_if);
+ phy_config(priv->phydev);
+ }
+
+ return 0;
+}
+
+int ks2_eth_remove(struct udevice *dev)
+{
+ struct ks2_eth_priv *priv = dev_get_priv(dev);
+
+ cpsw_mdio_free(priv->mdio_bus);
+
+ return 0;
+}
+
+static const struct eth_ops ks2_eth_ops = {
+ .start = ks2_eth_start,
+ .send = ks2_eth_send,
+ .recv = ks2_eth_recv,
+ .free_pkt = ks2_eth_free_pkt,
+ .stop = ks2_eth_stop,
+ .read_rom_hwaddr = ks2_eth_read_rom_hwaddr,
+ .write_hwaddr = ks2_eth_write_hwaddr,
+};
+
+static int ks2_eth_bind_slaves(struct udevice *dev, int gbe, int *gbe_0)
+{
+ const void *fdt = gd->fdt_blob;
+ struct udevice *sl_dev;
+ int interfaces;
+ int sec_slave;
+ int slave;
+ int ret;
+ char *slave_name;
+
+ interfaces = fdt_subnode_offset(fdt, gbe, "interfaces");
+ fdt_for_each_subnode(slave, fdt, interfaces) {
+ int slave_no;
+
+ slave_no = fdtdec_get_int(fdt, slave, "slave-port", -ENOENT);
+ if (slave_no == -ENOENT)
+ continue;
+
+ if (slave_no == 0) {
+ /* This is the current eth device */
+ *gbe_0 = slave;
+ } else {
+ /* Slave devices to be registered */
+ slave_name = malloc(20);
+ snprintf(slave_name, 20, "netcp@slave-%d", slave_no);
+ ret = device_bind_driver_to_node(dev, "eth_ks2_sl",
+ slave_name, offset_to_ofnode(slave),
+ &sl_dev);
+ if (ret) {
+ pr_err("ks2_net - not able to bind slave interfaces\n");
+ return ret;
+ }
+ }
+ }
+
+ sec_slave = fdt_subnode_offset(fdt, gbe, "secondary-slave-ports");
+ fdt_for_each_subnode(slave, fdt, sec_slave) {
+ int slave_no;
+
+ slave_no = fdtdec_get_int(fdt, slave, "slave-port", -ENOENT);
+ if (slave_no == -ENOENT)
+ continue;
+
+ /* Slave devices to be registered */
+ slave_name = malloc(20);
+ snprintf(slave_name, 20, "netcp@slave-%d", slave_no);
+ ret = device_bind_driver_to_node(dev, "eth_ks2_sl", slave_name,
+ offset_to_ofnode(slave), &sl_dev);
+ if (ret) {
+ pr_err("ks2_net - not able to bind slave interfaces\n");
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
+static int ks2_eth_parse_slave_interface(int netcp, int slave,
+ struct ks2_eth_priv *priv,
+ struct eth_pdata *pdata)
+{
+ const void *fdt = gd->fdt_blob;
+ int mdio;
+ int phy;
+ int dma_count;
+ u32 dma_channel[8];
+
+ priv->slave_port = fdtdec_get_int(fdt, slave, "slave-port", -1);
+ priv->net_rx_buffs.rx_flow = priv->slave_port * 8;
+
+ /* U-Boot slave port number starts with 1 instead of 0 */
+ priv->slave_port += 1;
+
+ dma_count = fdtdec_get_int_array_count(fdt, netcp,
+ "ti,navigator-dmas",
+ dma_channel, 8);
+
+ if (dma_count > (2 * priv->slave_port)) {
+ int dma_idx;
+
+ dma_idx = priv->slave_port * 2 - 1;
+ priv->net_rx_buffs.rx_flow = dma_channel[dma_idx];
+ }
+
+ priv->link_type = fdtdec_get_int(fdt, slave, "link-interface", -1);
+
+ phy = fdtdec_lookup_phandle(fdt, slave, "phy-handle");
+ if (phy >= 0) {
+ priv->phy_addr = fdtdec_get_int(fdt, phy, "reg", -1);
+
+ mdio = fdt_parent_offset(fdt, phy);
+ if (mdio < 0) {
+ pr_err("mdio dt not found\n");
+ return -ENODEV;
+ }
+ priv->mdio_base = (void *)fdtdec_get_addr(fdt, mdio, "reg");
+ }
+
+ if (priv->link_type == LINK_TYPE_SGMII_MAC_TO_PHY_MODE) {
+ priv->phy_if = PHY_INTERFACE_MODE_SGMII;
+ pdata->phy_interface = priv->phy_if;
+ priv->sgmii_link_type = SGMII_LINK_MAC_PHY;
+ priv->has_mdio = true;
+ } else if (priv->link_type == LINK_TYPE_RGMII_LINK_MAC_PHY) {
+ priv->phy_if = PHY_INTERFACE_MODE_RGMII;
+ pdata->phy_interface = priv->phy_if;
+ priv->has_mdio = true;
+ }
+
+ return 0;
+}
+
+static int ks2_sl_eth_ofdata_to_platdata(struct udevice *dev)
+{
+ struct ks2_eth_priv *priv = dev_get_priv(dev);
+ struct eth_pdata *pdata = dev_get_platdata(dev);
+ const void *fdt = gd->fdt_blob;
+ int slave = dev_of_offset(dev);
+ int interfaces;
+ int gbe;
+ int netcp_devices;
+ int netcp;
+
+ interfaces = fdt_parent_offset(fdt, slave);
+ gbe = fdt_parent_offset(fdt, interfaces);
+ netcp_devices = fdt_parent_offset(fdt, gbe);
+ netcp = fdt_parent_offset(fdt, netcp_devices);
+
+ ks2_eth_parse_slave_interface(netcp, slave, priv, pdata);
+
+ pdata->iobase = fdtdec_get_addr(fdt, netcp, "reg");
+
+ return 0;
+}
+
+static int ks2_eth_ofdata_to_platdata(struct udevice *dev)
+{
+ struct ks2_eth_priv *priv = dev_get_priv(dev);
+ struct eth_pdata *pdata = dev_get_platdata(dev);
+ const void *fdt = gd->fdt_blob;
+ int gbe_0 = -ENODEV;
+ int netcp_devices;
+ int gbe;
+
+ netcp_devices = fdt_subnode_offset(fdt, dev_of_offset(dev),
+ "netcp-devices");
+ gbe = fdt_subnode_offset(fdt, netcp_devices, "gbe");
+
+ ks2_eth_bind_slaves(dev, gbe, &gbe_0);
+
+ ks2_eth_parse_slave_interface(dev_of_offset(dev), gbe_0, priv, pdata);
+
+ pdata->iobase = devfdt_get_addr(dev);
+
+ return 0;
+}
+
+static const struct udevice_id ks2_eth_ids[] = {
+ { .compatible = "ti,netcp-1.0" },
+ { }
+};
+
+U_BOOT_DRIVER(eth_ks2_slave) = {
+ .name = "eth_ks2_sl",
+ .id = UCLASS_ETH,
+ .ofdata_to_platdata = ks2_sl_eth_ofdata_to_platdata,
+ .probe = ks2_eth_probe,
+ .remove = ks2_eth_remove,
+ .ops = &ks2_eth_ops,
+ .priv_auto_alloc_size = sizeof(struct ks2_eth_priv),
+ .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+ .flags = DM_FLAG_ALLOC_PRIV_DMA,
+};
+
+U_BOOT_DRIVER(eth_ks2) = {
+ .name = "eth_ks2",
+ .id = UCLASS_ETH,
+ .of_match = ks2_eth_ids,
+ .ofdata_to_platdata = ks2_eth_ofdata_to_platdata,
+ .probe = ks2_eth_probe,
+ .remove = ks2_eth_remove,
+ .ops = &ks2_eth_ops,
+ .priv_auto_alloc_size = sizeof(struct ks2_eth_priv),
+ .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+ .flags = DM_FLAG_ALLOC_PRIV_DMA,
+};
PORT_GP_18(0, fn, sfx), \
PORT_GP_23(1, fn, sfx), \
PORT_GP_26(2, fn, sfx), \
- PORT_GP_12(3, fn, sfx), \
+ PORT_GP_CFG_12(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
PORT_GP_1(3, 12, fn, sfx), \
PORT_GP_1(3, 13, fn, sfx), \
PORT_GP_1(3, 14, fn, sfx), \
PORT_GP_1(3, 15, fn, sfx), \
- PORT_GP_11(4, fn, sfx), \
+ PORT_GP_CFG_11(4, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
PORT_GP_20(5, fn, sfx), \
PORT_GP_18(6, fn, sfx)
/*
{ },
};
+enum ioctrl_regs {
+ POCCTRL,
+};
+
+static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
+ [POCCTRL] = { 0xe6060380, },
+ { /* sentinel */ },
+};
+
+static int r8a77990_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
+{
+ int bit = -EINVAL;
+
+ *pocctrl = pinmux_ioctrl_regs[POCCTRL].reg;
+
+ if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
+ bit = pin & 0x1f;
+
+ if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 10))
+ bit = (pin & 0x1f) + 19;
+
+ return bit;
+}
+
+static const struct sh_pfc_soc_operations r8a77990_pinmux_ops = {
+ .pin_to_pocctrl = r8a77990_pin_to_pocctrl,
+};
+
const struct sh_pfc_soc_info r8a77990_pinmux_info = {
.name = "r8a77990_pfc",
+ .ops = &r8a77990_pinmux_ops,
.unlock_reg = 0xe6060000, /* PMMR */
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
.nr_functions = ARRAY_SIZE(pinmux_functions),
.cfg_regs = pinmux_config_regs,
+ .ioctrl_regs = pinmux_ioctrl_regs,
.pinmux_data = pinmux_data,
.pinmux_data_size = ARRAY_SIZE(pinmux_data),
strength = strength / step - 1;
val = sh_pfc_read_raw_reg(reg, 32);
- val &= ~GENMASK(offset + size - 1, offset);
+ val &= ~GENMASK(offset + 4 - 1, offset);
val |= strength << offset;
if (unlock_reg)
config DM_REGULATOR_GPIO
bool "Enable Driver Model for GPIO REGULATOR"
- depends on DM_REGULATOR
+ depends on DM_REGULATOR && DM_GPIO
---help---
This config enables implementation of driver-model regulator uclass
features for gpio regulators. The driver implements get/set for
voltage value.
+config SPL_DM_REGULATOR_GPIO
+ bool "Enable Driver Model for GPIO REGULATOR in SPL"
+ depends on DM_REGULATOR_GPIO && SPL_GPIO_SUPPORT
+ ---help---
+ This config enables implementation of driver-model regulator uclass
+ features for gpio regulators in SPL.
+
config REGULATOR_RK8XX
bool "Enable driver for RK8XX regulators"
depends on DM_REGULATOR && PMIC_RK8XX
ops->setconfig += gd->reloc_off;
#if CONFIG_POST & CONFIG_SYS_POST_UART
if (ops->loop)
- ops->loop += gd->reloc_off
+ ops->loop += gd->reloc_off;
#endif
#endif
/* Set the baud rate */
*/
#include <common.h>
+#include <hwconfig.h>
#include <fsl_errata.h>
#include<fsl_usb.h>
#if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3) || \
return false;
}
+bool has_erratum_a005275(void)
+{
+ u32 svr = get_svr();
+ u32 soc = SVR_SOC_VER(svr);
+
+ if (hwconfig("no_erratum_a005275"))
+ return false;
+
+ switch (soc) {
+#ifdef CONFIG_PPC
+ case SVR_P3041:
+ case SVR_P2041:
+ case SVR_P2040:
+ return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 1, 1);
+ case SVR_P5010:
+ case SVR_P5020:
+ case SVR_P5021:
+ return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
+ case SVR_P5040:
+ case SVR_P1010:
+ return IS_SVR_REV(svr, 1, 0);
+#endif
+ }
+
+ return false;
+}
+
bool has_erratum_a006261(void)
{
u32 svr = get_svr();
struct usb_ehci *ehci = NULL;
struct ehci_hccr *hccr;
struct ehci_hcor *hcor;
+ struct ehci_ctrl *ehci_ctrl = &priv->ehci;
/*
* Get the base address for EHCI controller from the device node
hcor = (struct ehci_hcor *)
((void *)hccr + HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
+ ehci_ctrl->has_fsl_erratum_a005275 = has_erratum_a005275();
+
if (ehci_fsl_init(priv, ehci, hccr, hcor) < 0)
return -ENXIO;
int ehci_hcd_init(int index, enum usb_init_type init,
struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
+ struct ehci_ctrl *ehci_ctrl = container_of(hccr,
+ struct ehci_ctrl, hccr);
struct usb_ehci *ehci = NULL;
switch (index) {
*hcor = (struct ehci_hcor *)((uint32_t) *hccr +
HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
+ ehci_ctrl->has_fsl_erratum_a005275 = has_erratum_a005275();
+
return ehci_fsl_init(index, ehci, *hccr, *hcor);
}
endpt = QH_ENDPT1_RL(8) | QH_ENDPT1_C(c) |
QH_ENDPT1_MAXPKTLEN(maxpacket) | QH_ENDPT1_H(0) |
QH_ENDPT1_DTC(QH_ENDPT1_DTC_DT_FROM_QTD) |
- QH_ENDPT1_EPS(ehci_encode_speed(dev->speed)) |
QH_ENDPT1_ENDPT(usb_pipeendpoint(pipe)) | QH_ENDPT1_I(0) |
QH_ENDPT1_DEVADDR(usb_pipedevice(pipe));
+
+ /* Force FS for fsl HS quirk */
+ if (!ctrl->has_fsl_erratum_a005275)
+ endpt |= QH_ENDPT1_EPS(ehci_encode_speed(dev->speed));
+ else
+ endpt |= QH_ENDPT1_EPS(ehci_encode_speed(QH_FULL_SPEED));
+
qh->qh_endpt1 = cpu_to_hc32(endpt);
endpt = QH_ENDPT2_MULT(1) | QH_ENDPT2_UFCMASK(0) | QH_ENDPT2_UFSMASK(0);
qh->qh_endpt2 = cpu_to_hc32(endpt);
} else {
int ret;
+ /* Disable chirp for HS erratum */
+ if (ctrl->has_fsl_erratum_a005275)
+ reg |= PORTSC_FSL_PFSC;
+
reg |= EHCI_PS_PR;
reg &= ~EHCI_PS_PE;
ehci_writel(status_reg, reg);
#ifndef USB_EHCI_H
#define USB_EHCI_H
+#include <stdbool.h>
#include <usb.h>
#include <generic-phy.h>
#define PORTSC_PSPD_FS 0x0
#define PORTSC_PSPD_LS 0x1
#define PORTSC_PSPD_HS 0x2
+#define PORTSC_FSL_PFSC BIT(24) /* PFSC bit to disable HS chirping */
+
uint32_t or_systune;
} __attribute__ ((packed, aligned(4)));
uint32_t *periodic_list;
int periodic_schedules;
int ntds;
+ bool has_fsl_erratum_a005275; /* Freescale HS silicon quirk */
struct ehci_ops ops;
void *priv; /* client's private data */
};
{
struct w1_device *w1;
- w1 = dev_get_platdata(dev);
+ w1 = dev_get_parent_platdata(dev);
w1->id = 0;
return 0;
}
struct udevice *dev;
for (ret = uclass_first_device(UCLASS_W1, &dev);
- !ret;
- uclass_next_device(&dev), i++) {
- if (ret) {
- debug("Cannot find w1 bus %d\n", busnum);
- return ret;
- }
+ dev && !ret;
+ ret = uclass_next_device(&dev), i++) {
if (i == busnum) {
*busp = dev;
return 0;
}
}
+
+ if (!ret) {
+ debug("Cannot find w1 bus %d\n", busnum);
+ ret = -ENODEV;
+ }
+
return ret;
}
{
struct ubifs_compressor *compr = ubifs_compressors[tfm->compressor];
int err;
+ size_t tmp_len = *dlen;
if (compr->compr_type == UBIFS_COMPR_NONE) {
memcpy(dst, src, slen);
return 0;
}
- err = compr->decompress(src, slen, dst, (size_t *)dlen);
+ err = compr->decompress(src, slen, dst, &tmp_len);
if (err)
ubifs_err(c, "cannot decompress %d bytes, compressor %s, "
"error %d", slen, compr->name, err);
+ *dlen = tmp_len;
return err;
return 0;
#define CONFIG_ENV_OFFSET_REDUND 0x100000
#define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */
#define CONFIG_BOOTCOMMAND "nand read " \
- "0x22000000 0x200000 0x300000; " \
- "bootm 0x22000000"
+ "0x22000000 0x200000 0x600000; " \
+ "nand read 0x21000000 0x180000 0x20000; " \
+ "bootz 0x22000000 - 0x21000000"
#elif defined(CONFIG_SPI_BOOT)
/* bootstrap + u-boot + env + linux in spi flash */
#define CONFIG_ENV_OFFSET 0x5000
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2018 Synopsys, Inc. All rights reserved.
- */
-
-#ifndef _CONFIG_EMDK_H_
-#define _CONFIG_EMDK_H_
-
-#include <linux/sizes.h>
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-
-#define CONFIG_SYS_SDRAM_BASE 0x10000000
-#define CONFIG_SYS_SDRAM_SIZE SZ_8M
-
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_1M)
-
-#define CONFIG_SYS_MALLOC_LEN SZ_64K
-#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE
-
-/* Required by DW MMC driver */
-#define CONFIG_BOUNCE_BUFFER
-
-/*
- * Environment
- */
-#define CONFIG_ENV_SIZE SZ_4K
-#define CONFIG_BOOTFILE "app.bin"
-#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "upgrade_image=u-boot.bin\0" \
- "upgrade=emdk rom unlock && " \
- "fatload mmc 0 ${loadaddr} ${upgrade_image} && " \
- "cp.b ${loadaddr} 0 ${filesize} && " \
- "dcache flush && " \
- "emdk rom lock\0"
-
-#endif /* _CONFIG_EMDK_H_ */
-
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018 Synopsys, Inc. All rights reserved.
+ */
+
+#ifndef _CONFIG_EMSDP_H_
+#define _CONFIG_EMSDP_H_
+
+#include <linux/sizes.h>
+
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SYS_SDRAM_BASE 0x10000000
+#define CONFIG_SYS_SDRAM_SIZE SZ_8M
+
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_1M)
+
+#define CONFIG_SYS_MALLOC_LEN SZ_64K
+#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE
+
+/* Required by DW MMC driver */
+#define CONFIG_BOUNCE_BUFFER
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_SIZE SZ_4K
+#define CONFIG_BOOTFILE "app.bin"
+#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "upgrade_image=u-boot.bin\0" \
+ "upgrade=emsdp rom unlock && " \
+ "fatload mmc 0 ${loadaddr} ${upgrade_image} && " \
+ "cp.b ${loadaddr} 0 ${filesize} && " \
+ "dcache flush && " \
+ "emsdp rom lock\0"
+
+#endif /* _CONFIG_EMSDP_H_ */
+
#define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000
#define CONFIG_SYS_INIT_RAM_SIZE 0x40000 /* 256KB */
#endif
+
+/*
+ * Some boards (e.g. socfpga_sr1500) use 8 bytes at the end of the internal
+ * SRAM as bootcounter storage. Make sure to not put the stack directly
+ * at this address to not overwrite the bootcounter by checking, if the
+ * bootcounter address is located in the internal SRAM.
+ */
+#if ((CONFIG_SYS_BOOTCOUNT_ADDR > CONFIG_SYS_INIT_RAM_ADDR) && \
+ (CONFIG_SYS_BOOTCOUNT_ADDR < (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_SIZE)))
+#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_BOOTCOUNT_ADDR
+#else
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)
+#endif
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_KSNAV_NETCP_PDMA_TX_SND_QUEUE KS2_NETCP_PDMA_TX_SND_QUEUE
/* Keystone net */
-#define CONFIG_DRIVER_TI_KEYSTONE_NET
#define CONFIG_KSNET_MAC_ID_BASE KS2_MAC_ID_BASE_ADDR
#define CONFIG_KSNET_NETCP_BASE KS2_NETCP_BASE
#define CONFIG_KSNET_SERDES_SGMII_BASE KS2_SGMII_SERDES_BASE
#define CONFIG_PMECC_CAP 4
#define CONFIG_PMECC_SECTOR_SIZE 512
-#define CONFIG_CMD_MTDPARTS
#define CONFIG_RBTREE
#define CONFIG_LZO
#define CONFIG_SPL_BSS_START_ADDR 0x100000
#define CONFIG_SPL_BSS_MAX_SIZE 0x100000
+#define CONFIG_SPL_LOAD_FIT_ADDRESS 0x10000000
+
#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
#endif /* __CONFIG_ZYNQ_COMMON_H */
#define DWMCI_INTMSK_DTO (1 << 3)
#define DWMCI_INTMSK_TXDR (1 << 4)
#define DWMCI_INTMSK_RXDR (1 << 5)
+#define DWMCI_INTMSK_RCRC (1 << 6)
#define DWMCI_INTMSK_DCRC (1 << 7)
#define DWMCI_INTMSK_RTO (1 << 8)
#define DWMCI_INTMSK_DRTO (1 << 9)
AVB_VERIFY_CHECK \
"part start mmc ${mmcdev} boot boot_start; " \
"part size mmc ${mmcdev} boot boot_size; " \
- "mmc read ${fdtaddr} ${fdt_start} ${fdt_size}; " \
"mmc read ${loadaddr} ${boot_start} ${boot_size}; " \
"bootm ${loadaddr}#${fdtfile};\0 "
/* USB Erratum Checking code */
#if defined(CONFIG_PPC) || defined(CONFIG_ARM)
bool has_dual_phy(void);
+bool has_erratum_a005275(void);
bool has_erratum_a006261(void);
bool has_erratum_a007075(void);
bool has_erratum_a007798(void);
*/
int init_cache_f_r(void);
-#if !CONFIG_IS_ENABLED(CPU)
-/**
- * print_cpuinfo() - Display information about the CPU
- *
- * Return: 0 if OK, -ve on error
- */
int print_cpuinfo(void);
-#endif
int timer_init(void);
int reserve_mmu(void);
int misc_init_f(void);
int fec_initialize (bd_t *bis);
int fecmxc_initialize(bd_t *bis);
int fecmxc_initialize_multi(bd_t *bis, int dev_id, int phy_id, uint32_t addr);
-int ftgmac100_initialize(bd_t *bits);
int ftmac100_initialize(bd_t *bits);
int ftmac110_initialize(bd_t *bits);
void gt6426x_eth_initialize(bd_t *bis);
CONFIG_FZOTG266HD0A_BASE
CONFIG_GATEWAYIP
CONFIG_GICV2
-CONFIG_GICV3
CONFIG_GLOBAL_DATA_NOT_REG10
CONFIG_GLOBAL_TIMER
CONFIG_GMII
CONFIG_SH_SDHI_FREQ
CONFIG_SH_SDRAM_OFFSET
CONFIG_SH_SPI_BASE
-CONFIG_SH_TMU_CLK_FREQ
CONFIG_SIEMENS_MACH_TYPE
CONFIG_SIMU
CONFIG_SKIP_LOCAL_MAC_RANDOMIZATION
return vers->gen_caps & TEE_GEN_CAP_GP;
}
-static int dm_test_tee(struct unit_test_state *uts)
+struct test_tee_vars {
+ struct tee_shm *reg_shm;
+ struct tee_shm *alloc_shm;
+};
+
+static int test_tee(struct unit_test_state *uts, struct test_tee_vars *vars)
{
struct tee_version_data vers;
struct udevice *dev;
u32 session = 0;
int rc;
u8 data[128];
- struct tee_shm *reg_shm;
- struct tee_shm *alloc_shm;
dev = tee_find_device(NULL, match, NULL, &vers);
ut_assert(dev);
ut_assert(!state->session);
ut_assert(!state->num_shms);
- rc = tee_shm_register(dev, data, sizeof(data), 0, ®_shm);
+ rc = tee_shm_register(dev, data, sizeof(data), 0, &vars->reg_shm);
ut_assert(!rc);
ut_assert(state->num_shms == 1);
- rc = tee_shm_alloc(dev, 256, 0, &alloc_shm);
+ rc = tee_shm_alloc(dev, 256, 0, &vars->alloc_shm);
ut_assert(!rc);
ut_assert(state->num_shms == 2);
- ut_assert(tee_shm_is_registered(reg_shm, dev));
- ut_assert(tee_shm_is_registered(alloc_shm, dev));
+ ut_assert(tee_shm_is_registered(vars->reg_shm, dev));
+ ut_assert(tee_shm_is_registered(vars->alloc_shm, dev));
- tee_shm_free(reg_shm);
- tee_shm_free(alloc_shm);
+ tee_shm_free(vars->reg_shm);
+ vars->reg_shm = NULL;
+ tee_shm_free(vars->alloc_shm);
+ vars->alloc_shm = NULL;
ut_assert(!state->num_shms);
return 0;
}
+static int dm_test_tee(struct unit_test_state *uts)
+{
+ struct test_tee_vars vars = { NULL, NULL };
+ int rc = test_tee(uts, &vars);
+
+ /* In case test_tee() asserts these may still remain allocated */
+ tee_shm_free(vars.reg_shm);
+ tee_shm_free(vars.alloc_shm);
+
+ return rc;
+}
+
DM_TEST(dm_test_tee, DM_TESTF_SCAN_FDT);
unsigned char *ptr;
uint8_t zeros[0x4000];
int size;
+ int ret;
if (align > 0x4000) {
fprintf(stderr, "Wrong alignment requested %d\n", align);
}
size = sbuf.st_size;
- lseek(ifd, offset, SEEK_SET);
+ ret = lseek(ifd, offset, SEEK_SET);
+ if (ret < 0) {
+ fprintf(stderr, "%s: lseek error %s\n",
+ __func__, strerror(errno));
+ exit(EXIT_FAILURE);
+ }
+
if (write(ifd, ptr, size) != size) {
fprintf(stderr, "Write error %s\n", strerror(errno));
exit(EXIT_FAILURE);
int tail;
int zero = 0;
uint8_t zeros[4096];
- int size;
+ int size, ret;
memset(zeros, 0, sizeof(zeros));
}
size = sbuf.st_size;
- lseek(ifd, offset, SEEK_SET);
+ ret = lseek(ifd, offset, SEEK_SET);
+ if (ret < 0) {
+ fprintf(stderr, "%s: lseek error %s\n",
+ __func__, strerror(errno));
+ exit(EXIT_FAILURE);
+ }
+
if (write(ifd, ptr, size) != size) {
fprintf(stderr, "Write error %s\n",
strerror(errno));
}
ret = fread(&header, sizeof(header), 1, fd);
- if (ret != 1)
+ if (ret != 1) {
printf("Failure Read header %d\n", ret);
+ exit(EXIT_FAILURE);
+ }
fclose(fd);
char *tmp_filename = NULL;
uint32_t size = 0;
uint32_t file_padding = 0;
+ int ret;
int container = -1;
int cont_img_count = 0; /* indexes to arrange the container */
case SCFW:
case DATA:
case MSG_BLOCK:
+ if (container < 0) {
+ fprintf(stderr, "No container found\n");
+ exit(EXIT_FAILURE);
+ }
check_file(&sbuf, img_sp->filename);
tmp_filename = img_sp->filename;
set_image_array_entry(&imx_header.fhdr[container],
break;
case SECO:
+ if (container < 0) {
+ fprintf(stderr, "No container found\n");
+ exit(EXIT_FAILURE);
+ }
check_file(&sbuf, img_sp->filename);
tmp_filename = img_sp->filename;
set_image_array_entry(&imx_header.fhdr[container],
} while (img_sp->option != NO_IMG);
/* Add padding or skip appended container */
- lseek(ofd, file_padding, SEEK_SET);
-
- /* Note: Image offset are not contained in the image */
- tmp = flatten_container_header(&imx_header, container + 1, &size,
- file_padding);
- /* Write image header */
- if (write(ofd, tmp, size) != size) {
- fprintf(stderr, "error writing image hdr\n");
+ ret = lseek(ofd, file_padding, SEEK_SET);
+ if (ret < 0) {
+ fprintf(stderr, "%s: lseek error %s\n",
+ __func__, strerror(errno));
exit(EXIT_FAILURE);
}
- /* Clean-up memory used by the headers */
- free(tmp);
+ if (container >= 0) {
+ /* Note: Image offset are not contained in the image */
+ tmp = flatten_container_header(&imx_header, container + 1,
+ &size, file_padding);
+ /* Write image header */
+ if (write(ofd, tmp, size) != size) {
+ fprintf(stderr, "error writing image hdr\n");
+ exit(EXIT_FAILURE);
+ }
+
+ /* Clean-up memory used by the headers */
+ free(tmp);
+ }
/*
* step through the image stack again this time copying
int main(int argc, char *argv[])
{
unsigned int i, j, i_rel_shdr, sh_type, sh_entsize, sh_entries;
- size_t rel_size, rel_actual_size, load_sz;
+ size_t rel_size, rel_actual_size;
const char *shstrtab, *sh_name, *rel_pfx;
int (*parse_fn)(const void *rel);
uint8_t *buf_start, *buf;
const Elf32_Ehdr *ehdr32;
const Elf64_Ehdr *ehdr64;
uintptr_t sh_offset;
- Elf32_Phdr *phdr32;
- Elf64_Phdr *phdr64;
Elf32_Shdr *shdr32;
Elf64_Shdr *shdr64;
struct stat st;
goto out_free_relocs;
}
- phdr32 = elf + ehdr_field(e_phoff);
- phdr64 = elf + ehdr_field(e_phoff);
shdr32 = elf + ehdr_field(e_shoff);
shdr64 = elf + ehdr_field(e_shoff);
shstrtab = elf + shdr_field(ehdr_field(e_shstrndx), sh_offset);
for (i = 0; i < ehdr_field(e_shnum); i++) {
sh_name = shstr(shdr_field(i, sh_name));
- if (!strcmp(sh_name, ".rel")) {
+ if (!strcmp(sh_name, ".data.reloc")) {
i_rel_shdr = i;
continue;
}
rel_size = shdr_field(i_rel_shdr, sh_size);
rel_actual_size = buf - buf_start;
if (rel_actual_size > rel_size) {
- fprintf(stderr, "Relocs overflowed .rel section\n");
- return -ENOMEM;
- }
-
- /* Update the .rel section's size */
- set_shdr_field(i_rel_shdr, sh_size, rel_actual_size);
-
- /* Shrink the PT_LOAD program header filesz (ie. shrink u-boot.bin) */
- for (i = 0; i < ehdr_field(e_phnum); i++) {
- if (phdr_field(i, p_type) != PT_LOAD)
- continue;
-
- load_sz = phdr_field(i, p_filesz);
- load_sz -= rel_size - rel_actual_size;
- set_phdr_field(i, p_filesz, load_sz);
- break;
+ fprintf(stderr, "Relocations overflow available space of 0x%lx (required 0x%lx)!\n",
+ rel_size, rel_actual_size);
+ fprintf(stderr, "Please adjust CONFIG_MIPS_RELOCATION_TABLE_SIZE to at least 0x%lx\n",
+ (rel_actual_size + 0x100) & ~0xFF);
+ err = -ENOMEM;
+ goto out_free_relocs;
}
/* Make sure data is written back to the file */
projects / oweals / u-boot.git / commitdiff