am335x: Enable CONFIG_OMAP_WATCHDOG support
authorTom Rini <trini@ti.com>
Tue, 1 Oct 2013 16:32:04 +0000 (12:32 -0400)
committerTom Rini <trini@ti.com>
Fri, 1 Nov 2013 19:55:59 +0000 (15:55 -0400)
There is a board-specific portion for calling watchdog enable itself, in
main U-Boot.

Signed-off-by: Tom Rini <trini@ti.com>
arch/arm/cpu/armv7/omap-common/boot-common.c
board/ti/am335x/board.c
include/configs/ti_am335x_common.h

index 0ffa03ac01a8edc430b2f3b4c7e9178efedbdaf9..69fff323d3602163784da3898b6c2e0c16ba0dc9 100644 (file)
@@ -14,6 +14,7 @@
 #include <asm/arch/omap.h>
 #include <asm/arch/mmc_host_def.h>
 #include <asm/arch/sys_proto.h>
+#include <watchdog.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -76,6 +77,9 @@ void spl_board_init(void)
 #if defined(CONFIG_AM33XX) && defined(CONFIG_SPL_MUSB_NEW_SUPPORT)
        arch_misc_init();
 #endif
+#if defined(CONFIG_HW_WATCHDOG)
+       hw_watchdog_init();
+#endif
 #ifdef CONFIG_AM33XX
        am33xx_spl_board_init();
 #endif
index c2fc5a613b20d5be82d9a86d3bab0f43088d3c5d..57fedab340af29e767245aec6768d316104867a3 100644 (file)
@@ -28,6 +28,8 @@
 #include <cpsw.h>
 #include <power/tps65217.h>
 #include <power/tps65910.h>
+#include <environment.h>
+#include <watchdog.h>
 #include "board.h"
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -485,6 +487,10 @@ int board_init(void)
                STNOR_GPMC_CONFIG5, STNOR_GPMC_CONFIG6, STNOR_GPMC_CONFIG7 };
 #endif
 
+#if defined(CONFIG_HW_WATCHDOG)
+       hw_watchdog_init();
+#endif
+
        gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 
        gpmc_init();
index 03726f257c715d9057cbeb29091c9c2f255b8c71..10fe47f4d63bb346c6662356127e1a2ee2662514 100644 (file)
 #define CONFIG_BOOTCOUNT_LIMIT
 #define CONFIG_SYS_BOOTCOUNT_ADDR      0x44E3E000
 
+/* Enable the HW watchdog, since we can use this with bootcount */
+#define CONFIG_HW_WATCHDOG
+#define CONFIG_OMAP_WATCHDOG
+
 /*
  * SPL related defines.  The Public RAM memory map the ROM defines the
  * area between 0x402F0400 and 0x4030B800 as a download area and
@@ -57,6 +61,9 @@
 #define CONFIG_SPL_TEXT_BASE           0x402F0400
 #define CONFIG_SPL_MAX_SIZE            (0x4030B800 - CONFIG_SPL_TEXT_BASE)
 
+/* Enable the watchdog inside of SPL */
+#define CONFIG_SPL_WATCHDOG_SUPPORT
+
 /*
  * Since SPL did pll and ddr initialization for us,
  * we don't need to do it twice.