arm: dts: k3-j721e: Add DT nodes for USB

J721e has two instances of Cadence USB3 controller. Add DT nodes for the
same. USB0 is configured to device mode and USB1 is configured to host
mode. For now only high speed mode is supported.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

diff --git a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
index 9291e57e258a7509339c3726b6c0b06d22e35a6f..9ca025c4c5176f35e7c4ceeb59eb92f833a6b5e1 100644 (file)
--- a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
@@ -282,6 +282,20 @@
        u-boot,dm-spl;
 };
 
+&main_usbss0_pins_default {
+       u-boot,dm-spl;
+};
+
+&usbss0 {
+       u-boot,dm-spl;
+       ti,usb2-only;
+};
+
+&usb0 {
+       dr_mode = "peripheral";
+       u-boot,dm-spl;
+};
+
 &mcu_cpsw {
        pinctrl-names = "default";
        pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;

diff --git a/arch/arm/dts/k3-j721e-common-proc-board.dts b/arch/arm/dts/k3-j721e-common-proc-board.dts
index c978cabd13350f8ccaff7f03f0fbbd5a5fb521bc..137da7e425a1ddd78357a6e5e9d4e1d2c915bdcf 100644 (file)
--- a/arch/arm/dts/k3-j721e-common-proc-board.dts
+++ b/arch/arm/dts/k3-j721e-common-proc-board.dts
@@ -77,3 +77,40 @@
        voltage-ranges = <1800 1800 3300 3300>;
        ti,driver-strength-ohm = <50>;
 };
+
+&main_pmx0 {
+       main_usbss0_pins_default: main_usbss0_pins_default {
+               pinctrl-single,pins = <
+                       J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */
+                       J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */
+               >;
+       };
+
+       main_usbss1_pins_default: main_usbss1_pins_default {
+               pinctrl-single,pins = <
+                       J721E_IOPAD(0x214, PIN_OUTPUT, 4) /* (V4) MCAN1_TX.USB1_DRVVBUS */
+               >;
+       };
+};
+
+&usbss0 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&main_usbss0_pins_default>;
+       ti,vbus-divider;
+};
+
+&usb0 {
+       dr_mode = "otg";
+       maximum-speed = "super-speed";
+};
+
+&usbss1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&main_usbss1_pins_default>;
+       ti,usb2-only;
+};
+
+&usb1 {
+       dr_mode = "host";
+       maximum-speed = "high-speed";
+};

diff --git a/arch/arm/dts/k3-j721e-main.dtsi b/arch/arm/dts/k3-j721e-main.dtsi
index 3a0763209fc2172b042abefd571253d412f7ec9f..5083a0c3aef05cff2d197db2e98e75f0a005f292 100644 (file)
--- a/arch/arm/dts/k3-j721e-main.dtsi
+++ b/arch/arm/dts/k3-j721e-main.dtsi
@@ -340,6 +340,76 @@
                resets = <&k3_reset 15 1>;
        };
 
+       usbss0: cdns_usb@4104000 {
+               compatible = "ti,j721e-usb";
+               reg = <0x00 0x4104000 0x00 0x100>;
+               dma-coherent;
+               power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>;
+               clocks = <&k3_clks 288 15>, <&k3_clks 288 3>;
+               clock-names = "usb2_refclk", "lpm_clk";
+               assigned-clocks = <&k3_clks 288 15>;    /* USB2_REFCLK */
+               assigned-clock-parents = <&k3_clks 288 16>; /* HFOSC0 */
+               #address-cells = <2>;
+               #size-cells = <2>;
+               ranges;
+
+               phy@4108000 {
+                       compatible = "ti,j721e-usb2-phy";
+                       reg = <0x00 0x4108000 0x00 0x400>;
+               };
+
+               usb0: usb@6000000 {
+                       compatible = "cdns,usb3";
+                       reg = <0x00 0x6000000 0x00 0x10000>,
+                             <0x00 0x6010000 0x00 0x10000>,
+                             <0x00 0x6020000 0x00 0x10000>;
+                       reg-names = "otg", "xhci", "dev";
+                       interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,  /* irq.0 */
+                                    <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */
+                                    <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */
+                       interrupt-names = "host",
+                                         "peripheral",
+                                         "otg";
+                       maximum-speed = "super-speed";
+                       dr_mode = "otg";
+               };
+       };
+
+       usbss1: cdns_usb@4114000 {
+               compatible = "ti,j721e-usb";
+               reg = <0x00 0x4114000 0x00 0x100>;
+               dma-coherent;
+               power-domains = <&k3_pds 289 TI_SCI_PD_EXCLUSIVE>;
+               clocks = <&k3_clks 289 15>, <&k3_clks 289 3>;
+               clock-names = "usb2_refclk", "lpm_clk";
+               assigned-clocks = <&k3_clks 289 15>;    /* USB2_REFCLK */
+               assigned-clock-parents = <&k3_clks 289 16>; /* HFOSC0 */
+               #address-cells = <2>;
+               #size-cells = <2>;
+               ranges;
+
+               phy@4118000 {
+                       compatible = "ti,j721e-usb2-phy";
+                       reg = <0x00 0x4118000 0x00 0x400>;
+               };
+
+               usb1: usb@6400000 {
+                       compatible = "cdns,usb3";
+                       reg = <0x00 0x6400000 0x00 0x10000>,
+                             <0x00 0x6410000 0x00 0x10000>,
+                             <0x00 0x6420000 0x00 0x10000>;
+                       reg-names = "otg", "xhci", "dev";
+                       interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
+                                    <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */
+                                    <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */
+                       interrupt-names = "host",
+                                         "peripheral",
+                                         "otg";
+                       maximum-speed = "super-speed";
+                       dr_mode = "otg";
+               };
+       };
+
        ufs_wrapper: ufs-wrapper@4e80000 {
                compatible = "ti,j721e-ufs";
                reg = <0x0 0x4e80000 0x0 0x100>;

diff --git a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
index 41af48214f6fc72ba1f9a3ab170efb70f4ec3f51..1a8e1078611010326112a337c6b35ccc2aca74bc 100644 (file)
--- a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
+++ b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
@@ -112,6 +112,13 @@
                        J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */
                >;
        };
+
+       main_usbss0_pins_default: main_usbss0_pins_default {
+               pinctrl-single,pins = <
+                       J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */
+                       J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */
+               >;
+       };
 };
 
 &wkup_uart0 {