bmips: allow disabling usb support
authorÁlvaro Fernández Rojas <noltari@gmail.com>
Sat, 4 Apr 2020 14:01:12 +0000 (16:01 +0200)
committerDaniel Schwierzeck <daniel.schwierzeck@gmail.com>
Mon, 27 Apr 2020 18:29:33 +0000 (20:29 +0200)
Currently, if usb is disabled the following error is produced:
  CC      drivers/usb/host/ohci-hcd.o
drivers/usb/host/ohci-hcd.c: In function ‘usb_lowlevel_init’:
drivers/usb/host/ohci-hcd.c:2057:35: error: ‘CONFIG_SYS_USB_OHCI_REGS_BASE’ undeclared (first use in this function); did you mean ‘CONFIG_SYS_MONITOR_BASE’?
  gohci.regs = (struct ohci_regs *)CONFIG_SYS_USB_OHCI_REGS_BASE;
                                   ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~
                                   CONFIG_SYS_MONITOR_BASE
drivers/usb/host/ohci-hcd.c:2057:35: note: each undeclared identifier is reported only once for each function it appears in
drivers/usb/host/ohci-hcd.c:2061:20: error: ‘CONFIG_SYS_USB_OHCI_SLOT_NAME’ undeclared (first use in this function); did you mean ‘CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS’?
  gohci.slot_name = CONFIG_SYS_USB_OHCI_SLOT_NAME;
                    ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~
                    CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
include/configs/bmips_bcm6318.h
include/configs/bmips_bcm63268.h
include/configs/bmips_bcm6328.h
include/configs/bmips_bcm6348.h
include/configs/bmips_bcm6358.h
include/configs/bmips_bcm6362.h
include/configs/bmips_bcm6368.h

index c7e7119aafd14b2438b76a4647a73120c8e1fa70..45eb931c257af38e729d3974cf49ea82eed7e4b7 100644 (file)
@@ -19,7 +19,9 @@
 #define CONFIG_EHCI_MMIO_BIG_ENDIAN
 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS
 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
 #define CONFIG_EHCI_MMIO_BIG_ENDIAN
 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS
 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
+#if defined(CONFIG_USB_OHCI_HCD)
 #define CONFIG_USB_OHCI_NEW
 #define CONFIG_USB_OHCI_NEW
+#endif /* CONFIG_USB_OHCI_HCD */
 
 /* U-Boot */
 #define CONFIG_SYS_LOAD_ADDR           CONFIG_SYS_SDRAM_BASE + SZ_1M
 
 /* U-Boot */
 #define CONFIG_SYS_LOAD_ADDR           CONFIG_SYS_SDRAM_BASE + SZ_1M
index 45f26bb309757609db1c05021e96a22e9c5c99d5..eed321eb6fc8aca0d43cb46829f6d2760a322cd9 100644 (file)
@@ -19,7 +19,9 @@
 #define CONFIG_EHCI_MMIO_BIG_ENDIAN
 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS
 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
 #define CONFIG_EHCI_MMIO_BIG_ENDIAN
 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS
 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
+#if defined(CONFIG_USB_OHCI_HCD)
 #define CONFIG_USB_OHCI_NEW
 #define CONFIG_USB_OHCI_NEW
+#endif /* CONFIG_USB_OHCI_HCD */
 
 /* U-Boot */
 #define CONFIG_SYS_LOAD_ADDR           CONFIG_SYS_SDRAM_BASE + SZ_1M
 
 /* U-Boot */
 #define CONFIG_SYS_LOAD_ADDR           CONFIG_SYS_SDRAM_BASE + SZ_1M
index 8d594387853f4d80a76d4174eaac32e0ffd4d64b..c78099a49dcd09e42f01ccbb8a6426236d6db650 100644 (file)
@@ -19,7 +19,9 @@
 #define CONFIG_EHCI_MMIO_BIG_ENDIAN
 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS
 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
 #define CONFIG_EHCI_MMIO_BIG_ENDIAN
 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS
 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
+#if defined(CONFIG_USB_OHCI_HCD)
 #define CONFIG_USB_OHCI_NEW
 #define CONFIG_USB_OHCI_NEW
+#endif /* CONFIG_USB_OHCI_HCD */
 
 /* U-Boot */
 #define CONFIG_SYS_LOAD_ADDR           CONFIG_SYS_SDRAM_BASE + SZ_1M
 
 /* U-Boot */
 #define CONFIG_SYS_LOAD_ADDR           CONFIG_SYS_SDRAM_BASE + SZ_1M
index 061d6b25b714850ed1f8c5497aec27a9a57897e5..547cf857ceb0a135deb257f12c4e76846bd518ae 100644 (file)
@@ -17,7 +17,9 @@
 /* USB */
 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS
 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
 /* USB */
 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS
 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
+#if defined(CONFIG_USB_OHCI_HCD)
 #define CONFIG_USB_OHCI_NEW
 #define CONFIG_USB_OHCI_NEW
+#endif /* CONFIG_USB_OHCI_HCD */
 
 /* U-Boot */
 #define CONFIG_SYS_LOAD_ADDR           CONFIG_SYS_SDRAM_BASE + SZ_1M
 
 /* U-Boot */
 #define CONFIG_SYS_LOAD_ADDR           CONFIG_SYS_SDRAM_BASE + SZ_1M
index 583217d26217b9de132cea173279e6aa769384a6..116e9705b6be7a8db1c405eef8f17795b0966d17 100644 (file)
@@ -19,7 +19,9 @@
 #define CONFIG_EHCI_MMIO_BIG_ENDIAN
 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS
 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
 #define CONFIG_EHCI_MMIO_BIG_ENDIAN
 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS
 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
+#if defined(CONFIG_USB_OHCI_HCD)
 #define CONFIG_USB_OHCI_NEW
 #define CONFIG_USB_OHCI_NEW
+#endif /* CONFIG_USB_OHCI_HCD */
 
 /* U-Boot */
 #define CONFIG_SYS_LOAD_ADDR           CONFIG_SYS_SDRAM_BASE + SZ_1M
 
 /* U-Boot */
 #define CONFIG_SYS_LOAD_ADDR           CONFIG_SYS_SDRAM_BASE + SZ_1M
index 570bc3b33d3dc6aa73207f9267150059b18e5340..e5e8b15e18723a8dc57e8a8f30eb55f92c0bc396 100644 (file)
@@ -19,7 +19,9 @@
 #define CONFIG_EHCI_MMIO_BIG_ENDIAN
 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS
 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
 #define CONFIG_EHCI_MMIO_BIG_ENDIAN
 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS
 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
+#if defined(CONFIG_USB_OHCI_HCD)
 #define CONFIG_USB_OHCI_NEW
 #define CONFIG_USB_OHCI_NEW
+#endif /* CONFIG_USB_OHCI_HCD */
 
 /* U-Boot */
 #define CONFIG_SYS_LOAD_ADDR           CONFIG_SYS_SDRAM_BASE + SZ_1M
 
 /* U-Boot */
 #define CONFIG_SYS_LOAD_ADDR           CONFIG_SYS_SDRAM_BASE + SZ_1M
index ab5bdac7268aef0a168b270816e328ab5fb35f3f..4d4403f8d218d333aa2bac0e0b68ec8a6bf5af4d 100644 (file)
@@ -19,7 +19,9 @@
 #define CONFIG_EHCI_MMIO_BIG_ENDIAN
 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS
 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
 #define CONFIG_EHCI_MMIO_BIG_ENDIAN
 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS
 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
+#if defined(CONFIG_USB_OHCI_HCD)
 #define CONFIG_USB_OHCI_NEW
 #define CONFIG_USB_OHCI_NEW
+#endif /* CONFIG_USB_OHCI_HCD */
 
 /* U-Boot */
 #define CONFIG_SYS_LOAD_ADDR           CONFIG_SYS_SDRAM_BASE + SZ_1M
 
 /* U-Boot */
 #define CONFIG_SYS_LOAD_ADDR           CONFIG_SYS_SDRAM_BASE + SZ_1M