consider that a completely unreadable NAND block is bad,
and thus should be skipped silently.
+ CONFIG_SPL_ABORT_ON_RAW_IMAGE
+ When defined, SPL will proceed to another boot method
+ if the image it has loaded does not have a signature.
+
CONFIG_SPL_RELOC_STACK
Adress of the start of the stack SPL will use after
relocation. If unspecified, this is equal to
PLL_ENET_MAIN_250M_CLK, PLL_AUDIO_MAIN_CLK}
},
{AHB_CLK_ROOT, CCM_AHB_CHANNEL,
- {OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_DRAM_MAIN_533M_CLK,
+ {OSC_24M_CLK, PLL_SYS_PFD2_270M_CLK, PLL_DRAM_MAIN_533M_CLK,
PLL_SYS_PFD0_392M_CLK, PLL_ENET_MAIN_125M_CLK, PLL_USB_MAIN_480M_CLK,
PLL_AUDIO_MAIN_CLK, PLL_VIDEO_MAIN_CLK}
},
{
switch (imxtype) {
case MXC_CPU_MX7S:
- return "7SOLO"; /* Single-core version of the mx7 */
+ return "7S"; /* Single-core version of the mx7 */
case MXC_CPU_MX7D:
return "7D"; /* Dual-core version of the mx7 */
case MXC_CPU_MX6QP:
MX6_PAD_SD1_DAT3__USDHC1_DAT3 = IOMUX_PAD(0x0548, 0x0240, 0, 0x0000, 0, 0),
MX6_PAD_SD1_DAT4__USDHC1_DAT4 = IOMUX_PAD(0x054C, 0x0244, 0, 0x0000, 0, 0),
MX6_PAD_SD1_DAT5__USDHC1_DAT5 = IOMUX_PAD(0x0550, 0x0248, 0, 0x0000, 0, 0),
+ MX6_PAD_SD1_DAT5__GPIO_5_9 = IOMUX_PAD(0x0550, 0x0248, 5, 0x0000, 0, 0),
MX6_PAD_SD1_DAT6__USDHC1_DAT6 = IOMUX_PAD(0x0554, 0x024C, 0, 0x0000, 0, 0),
MX6_PAD_SD1_DAT7__USDHC1_DAT7 = IOMUX_PAD(0x0558, 0x0250, 0, 0x0000, 0, 0),
MX6_PAD_KEY_ROW7__GPIO_4_7 = IOMUX_PAD(0x04B0, 0x01A8, 5, 0x0000, 0, 0),
MX7D_PAD_LCD_DATA23__GPIO3_IO28 = IOMUX_PAD(0x0394, 0x0124, 5, 0x0000, 0, 0),
MX7D_PAD_LCD_DATA23__I2C4_SDA = IOMUX_PAD(0x0394, 0x0124, IOMUX_CONFIG_SION | 6, 0x05F0, 1, 0),
- MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX = IOMUX_PAD(0x0398, 0x0128, 0, 0x0000, 0, 0),
+ MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX = IOMUX_PAD(0x0398, 0x0128, 0, 0x06F4, 0, 0),
MX7D_PAD_UART1_RX_DATA__UART1_DTE_TX = IOMUX_PAD(0x0398, 0x0128, 0, 0x0000, 0, 0),
MX7D_PAD_UART1_RX_DATA__I2C1_SCL = IOMUX_PAD(0x0398, 0x0128, IOMUX_CONFIG_SION | 1, 0x0000, 0, 0),
MX7D_PAD_UART1_TX_DATA__GPIO4_IO1 = IOMUX_PAD(0x039C, 0x012C, 5, 0x0000, 0, 0),
MX7D_PAD_UART1_TX_DATA__ENET1_MDC = IOMUX_PAD(0x039C, 0x012C, 6, 0x0000, 0, 0),
- MX7D_PAD_UART2_RX_DATA__UART2_DCE_RX = IOMUX_PAD(0x03A0, 0x0130, 0, 0x0000, 0, 0),
+ MX7D_PAD_UART2_RX_DATA__UART2_DCE_RX = IOMUX_PAD(0x03A0, 0x0130, 0, 0x06FC, 2, 0),
MX7D_PAD_UART2_RX_DATA__UART2_DTE_TX = IOMUX_PAD(0x03A0, 0x0130, 0, 0x0000, 0, 0),
MX7D_PAD_UART2_RX_DATA__I2C2_SCL = IOMUX_PAD(0x03A0, 0x0130, IOMUX_CONFIG_SION | 1, 0x0000, 0, 0),
MX7D_PAD_UART2_TX_DATA__UART2_DCE_TX = IOMUX_PAD(0x03A4, 0x0134, 0, 0x0000, 0, 0),
- MX7D_PAD_UART2_TX_DATA__UART2_DTE_RX = IOMUX_PAD(0x03A4, 0x0134, 0, 0x0000, 0, 0),
+ MX7D_PAD_UART2_TX_DATA__UART2_DTE_RX = IOMUX_PAD(0x03A4, 0x0134, 0, 0x06FC, 3, 0),
MX7D_PAD_UART2_TX_DATA__I2C2_SDA = IOMUX_PAD(0x03A4, 0x0134, IOMUX_CONFIG_SION | 1, 0x05E0, 0, 0),
MX7D_PAD_UART2_TX_DATA__SAI3_RX_DATA0 = IOMUX_PAD(0x03A4, 0x0134, 2, 0x06C8, 0, 0),
MX7D_PAD_UART2_TX_DATA__ECSPI1_RDY = IOMUX_PAD(0x03A4, 0x0134, 3, 0x0000, 0, 0),
MX7D_PAD_UART3_TX_DATA__GPIO4_IO5 = IOMUX_PAD(0x03AC, 0x013C, 5, 0x0000, 0, 0),
MX7D_PAD_UART3_TX_DATA__SD2_LCTL = IOMUX_PAD(0x03AC, 0x013C, 6, 0x0000, 0, 0),
- MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS = IOMUX_PAD(0x03B0, 0x0140, 0, 0x0000, 0, 0),
+ MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS = IOMUX_PAD(0x03B0, 0x0140, 0, 0x0700, 2, 0),
MX7D_PAD_UART3_RTS_B__UART3_DTE_CTS = IOMUX_PAD(0x03B0, 0x0140, 0, 0x0000, 0, 0),
MX7D_PAD_UART3_RTS_B__USB_OTG2_OC = IOMUX_PAD(0x03B0, 0x0140, 1, 0x0000, 0, 0),
#include <asm/types.h>
-typedef struct fsl_i2c {
+typedef struct fsl_i2c_base {
u8 adr; /* I2C slave address */
u8 res0[3];
#include <asm/types.h>
-typedef struct fsl_i2c {
+typedef struct fsl_i2c_base {
u8 adr; /* I2C slave address */
u8 res0[3];
u8 res6[0xE8];
} fsl_i2c_t;
+#ifdef CONFIG_DM_I2C
+struct fsl_i2c_dev {
+ struct fsl_i2c_base __iomem *base; /* register base */
+ u32 i2c_clk;
+ u32 index;
+ u8 slaveadd;
+ uint speed;
+};
+#endif
+
#endif /* _ASM_I2C_H_ */
/* I2C Registers */
typedef struct ccsr_i2c {
- struct fsl_i2c i2c[1];
- u8 res[4096 - 1 * sizeof(struct fsl_i2c)];
+ struct fsl_i2c_base i2c[1];
+ u8 res[4096 - 1 * sizeof(struct fsl_i2c_base)];
} ccsr_i2c_t;
#if defined(CONFIG_MPC8540) \
/* Daul I2C Registers(0x3000-0x4000) */
typedef struct ccsr_i2c {
- struct fsl_i2c i2c[2];
- u8 res[4096 - 2 * sizeof(struct fsl_i2c)];
+ struct fsl_i2c_base i2c[2];
+ u8 res[4096 - 2 * sizeof(struct fsl_i2c_base)];
} ccsr_i2c_t;
/* DUART Registers(0x4000-0x5000) */
static void i2c_write_start_seq(void)
{
- struct fsl_i2c *dev;
- dev = (struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C_OFFSET);
+ struct fsl_i2c_base *base;
+ base = (struct fsl_i2c_base *)(CONFIG_SYS_IMMR +
+ CONFIG_SYS_I2C_OFFSET);
udelay(DELAY_ABORT_SEQ);
- out_8(&dev->cr, (I2C_CR_MEN | I2C_CR_MSTA));
+ out_8(&base->cr, (I2C_CR_MEN | I2C_CR_MSTA));
udelay(DELAY_ABORT_SEQ);
- out_8(&dev->cr, (I2C_CR_MEN));
+ out_8(&base->cr, (I2C_CR_MEN));
}
int i2c_make_abort(void)
{
- struct fsl_i2c *dev;
- dev = (struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C_OFFSET);
+ struct fsl_i2c_base *base;
+ base = (struct fsl_i2c_base *)(CONFIG_SYS_IMMR +
+ CONFIG_SYS_I2C_OFFSET);
uchar last;
int nbr_read = 0;
int i = 0;
int ret = 0;
/* wait after each operation to finsh with a delay */
- out_8(&dev->cr, (I2C_CR_MSTA));
+ out_8(&base->cr, (I2C_CR_MSTA));
udelay(DELAY_ABORT_SEQ);
- out_8(&dev->cr, (I2C_CR_MEN | I2C_CR_MSTA));
+ out_8(&base->cr, (I2C_CR_MEN | I2C_CR_MSTA));
udelay(DELAY_ABORT_SEQ);
- in_8(&dev->dr);
+ in_8(&base->dr);
udelay(DELAY_ABORT_SEQ);
- last = in_8(&dev->dr);
+ last = in_8(&base->dr);
nbr_read++;
/*
while (((last & 0x01) != 0x01) &&
(nbr_read < CONFIG_SYS_IVM_EEPROM_MAX_LEN)) {
udelay(DELAY_ABORT_SEQ);
- last = in_8(&dev->dr);
+ last = in_8(&base->dr);
nbr_read++;
}
if ((last & 0x01) != 0x01)
printf("[INFO] i2c abort after %d bytes (0x%02x)\n",
nbr_read, last);
udelay(DELAY_ABORT_SEQ);
- out_8(&dev->cr, (I2C_CR_MEN));
+ out_8(&base->cr, (I2C_CR_MEN));
udelay(DELAY_ABORT_SEQ);
/* clear status reg */
- out_8(&dev->sr, 0);
+ out_8(&base->sr, 0);
for (i = 0; i < 5; i++)
i2c_write_start_seq();
spl_image.name = "U-Boot";
}
-void spl_parse_image_header(const struct image_header *header)
+int spl_parse_image_header(const struct image_header *header)
{
u32 header_size = sizeof(struct image_header);
* is bad, and thus should be skipped silently.
*/
panic("** no mkimage signature but raw image not supported");
+#elif defined(CONFIG_SPL_ABORT_ON_RAW_IMAGE)
+ /* Signature not found, proceed to other boot methods. */
+ return -EINVAL;
#else
/* Signature not found - assume u-boot.bin */
debug("mkimage signature not found - ih_magic = %x\n",
spl_set_header_raw_uboot();
#endif
}
+ return 0;
}
__weak void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
goto end;
}
- spl_parse_image_header(header);
+ err = spl_parse_image_header(header);
+ if (err < 0) {
+ puts("spl: ext4fs_read failed\n");
+ goto end;
+ }
err = ext4fs_read((char *)spl_image.load_addr, filelen, &actlen);
if (err <= 0)
goto end;
- spl_parse_image_header(header);
+ err = spl_parse_image_header(header);
+ if (err <= 0)
+ goto end;
err = file_fat_read(filename, (u8 *)spl_image.load_addr, 0);
{
u32 image_size_sectors;
unsigned long count;
+ int ret;
+
+ ret = spl_parse_image_header(header);
+ if (ret)
+ return ret;
- spl_parse_image_header(header);
/* convert size to sectors - round up */
image_size_sectors = (spl_image.size + mmc->read_bl_len - 1) /
mmc->read_bl_len;
if (err)
return err;
- spl_parse_image_header(header);
+ err = spl_parse_image_header(header);
+ if (err)
+ return err;
+
return nand_spl_load_image(offset, spl_image.size,
(void *)(unsigned long)spl_image.load_addr);
}
/* load linux */
nand_spl_load_image(CONFIG_SYS_NAND_SPL_KERNEL_OFFS,
sizeof(*header), (void *)header);
- spl_parse_image_header(header);
+ err = spl_parse_image_header(header);
+ if (err)
+ return err;
if (header->ih_os == IH_OS_LINUX) {
/* happy - was a linux */
err = nand_spl_load_image(
printf("Problem booting with BOOTP\n");
return rv;
}
- spl_parse_image_header((struct image_header *)load_addr);
-
- return 0;
+ return spl_parse_image_header((struct image_header *)load_addr);
}
int spl_nor_load_image(void)
{
+ int ret;
/*
* Loading of the payload to SDRAM is done with skipping of
* the mkimage header in this SPL NOR driver
if (image_get_os(header) == IH_OS_LINUX) {
/* happy - was a Linux */
- spl_parse_image_header(header);
+ ret = spl_parse_image_header(header);
+ if (ret)
+ return ret;
memcpy((void *)spl_image.load_addr,
(void *)(CONFIG_SYS_OS_BASE +
* Load real U-Boot from its location in NOR flash to its
* defined location in SDRAM
*/
- spl_parse_image_header(
+ ret = spl_parse_image_header(
(const struct image_header *)CONFIG_SYS_UBOOT_BASE);
+ if (ret)
+ return ret;
memcpy((void *)(unsigned long)spl_image.load_addr,
(void *)(CONFIG_SYS_UBOOT_BASE + sizeof(struct image_header)),
int spl_onenand_load_image(void)
{
struct image_header *header;
+ int ret;
debug("spl: onenand\n");
/* Load u-boot */
onenand_spl_load_image(CONFIG_SYS_ONENAND_U_BOOT_OFFS,
CONFIG_SYS_ONENAND_PAGE_SIZE, (void *)header);
- spl_parse_image_header(header);
+ ret = spl_parse_image_header(header);
+ if (ret)
+ return ret;
onenand_spl_load_image(CONFIG_SYS_ONENAND_U_BOOT_OFFS,
spl_image.size, (void *)spl_image.load_addr);
if (!ret) {
while ((res =
xyzModem_stream_read(buf, BUF_SIZE, &err)) > 0) {
- if (addr == 0)
- spl_parse_image_header((struct image_header *)buf);
+ if (addr == 0) {
+ ret = spl_parse_image_header((struct image_header *)buf);
+ if (ret)
+ return ret;
+ }
store_addr = addr + spl_image.load_addr;
size += res;
addr += res;
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_CLK=y
+CONFIG_SYS_I2C_DW=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_SYS_NS16550=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_CLK=y
+CONFIG_SYS_I2C_DW=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_SYS_NS16550=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DWAPB_GPIO=y
+CONFIG_SYS_I2C_DW=y
CONFIG_DM_MMC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DWAPB_GPIO=y
+CONFIG_SYS_I2C_DW=y
CONFIG_DM_MMC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_DWAPB_GPIO=y
+CONFIG_SYS_I2C_DW=y
CONFIG_DM_MMC=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_DWAPB_GPIO=y
+CONFIG_SYS_I2C_DW=y
CONFIG_DM_MMC=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DWAPB_GPIO=y
+CONFIG_SYS_I2C_DW=y
CONFIG_DM_MMC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DWAPB_GPIO=y
+CONFIG_SYS_I2C_DW=y
CONFIG_DM_MMC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DWAPB_GPIO=y
+CONFIG_SYS_I2C_DW=y
CONFIG_DM_MMC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_SYS_I2C_DW=y
CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_SYS_I2C_DW=y
CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_SYS_I2C_DW=y
CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_SYS_I2C_DW=y
CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_SYS_I2C_DW=y
CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_SYS_I2C_DW=y
CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_SYS_I2C_DW=y
CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_SYS_I2C_DW=y
CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_SYS_I2C_DW=y
CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_SYS_I2C_DW=y
CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_SYS_I2C_DW=y
CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_SYS_I2C_DW=y
CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_SYS_I2C_DW=y
CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_SYS_I2C_DW=y
CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_SYS_I2C_DW=y
CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_SYS_I2C_DW=y
CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_SYS_I2C_DW=y
CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_SYS_I2C_DW=y
CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_SYS_I2C_DW=y
CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_SYS_I2C_DW=y
CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_SYS_I2C_DW=y
CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_USE_TINY_PRINTF=y
bindings are supported.
Binding info: doc/device-tree-bindings/i2c/i2c-gpio.txt
+config SYS_I2C_FSL
+ bool "Freescale I2C bus driver"
+ depends on DM_I2C
+ help
+ Add support for Freescale I2C busses as used on MPC8240, MPC8245, and
+ MPC85xx processors.
+
config SYS_I2C_CADENCE
tristate "Cadence I2C Controller"
depends on DM_I2C && (ARCH_ZYNQ || ARM64)
Say yes here to select Cadence I2C Host Controller. This controller is
e.g. used by Xilinx Zynq.
+config SYS_I2C_DW
+ bool "Designware I2C Controller"
+ default n
+ help
+ Say yes here to select the Designware I2C Host Controller. This
+ controller is used in various SoCs, e.g. the ST SPEAr, Altera
+ SoCFPGA, Synopsys ARC700 and some Intel x86 SoCs.
+
+config SYS_I2C_DW_ENABLE_STATUS_UNSUPPORTED
+ bool "DW I2C Enable Status Register not supported"
+ depends on SYS_I2C_DW && (TARGET_SPEAR300 || TARGET_SPEAR310 || \
+ TARGET_SPEAR320 || TARGET_SPEAR600 || TARGET_X600)
+ default y
+ help
+ Some versions of the Designware I2C controller do not support the
+ enable status register. This config option can be enabled in such
+ cases.
+
config SYS_I2C_INTEL
bool "Intel I2C/SMBUS driver"
depends on DM_I2C
struct dw_scl_sda_cfg *scl_sda_cfg;
};
+#ifdef CONFIG_SYS_I2C_DW_ENABLE_STATUS_UNSUPPORTED
+static void dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
+{
+ u32 ena = enable ? IC_ENABLE_0B : 0;
+
+ writel(ena, &i2c_base->ic_enable);
+}
+#else
static void dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
{
u32 ena = enable ? IC_ENABLE_0B : 0;
printf("timeout in %sabling I2C adapter\n", enable ? "en" : "dis");
}
+#endif
/*
* i2c_set_bus_speed - Set the i2c speed
#include <i2c.h> /* Functional interface */
#include <asm/io.h>
#include <asm/fsl_i2c.h> /* HW definitions */
+#include <dm.h>
+#include <mapmem.h>
/* The maximum number of microseconds we will wait until another master has
* released the bus. If not defined in the board header file, then use a
DECLARE_GLOBAL_DATA_PTR;
-static const struct fsl_i2c *i2c_dev[4] = {
- (struct fsl_i2c *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C_OFFSET),
+#ifndef CONFIG_DM_I2C
+static const struct fsl_i2c_base *i2c_base[4] = {
+ (struct fsl_i2c_base *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C_OFFSET),
#ifdef CONFIG_SYS_FSL_I2C2_OFFSET
- (struct fsl_i2c *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C2_OFFSET),
+ (struct fsl_i2c_base *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C2_OFFSET),
#endif
#ifdef CONFIG_SYS_FSL_I2C3_OFFSET
- (struct fsl_i2c *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C3_OFFSET),
+ (struct fsl_i2c_base *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C3_OFFSET),
#endif
#ifdef CONFIG_SYS_FSL_I2C4_OFFSET
- (struct fsl_i2c *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C4_OFFSET)
+ (struct fsl_i2c_base *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C4_OFFSET)
#endif
};
+#endif
/* I2C speed map for a DFSR value of 1 */
/**
* Set the I2C bus speed for a given I2C device
*
- * @param dev: the I2C device
+ * @param base: the I2C device registers
* @i2c_clk: I2C bus clock frequency
* @speed: the desired speed of the bus
*
*
* The return value is the actual bus speed that is set.
*/
-static unsigned int set_i2c_bus_speed(const struct fsl_i2c *dev,
+static unsigned int set_i2c_bus_speed(const struct fsl_i2c_base *base,
unsigned int i2c_clk, unsigned int speed)
{
unsigned short divider = min(i2c_clk / speed, (unsigned int)USHRT_MAX);
debug("divider:%d, est_div:%ld, DFSR:%d\n", divider, est_div, dfsr);
debug("FDR:0x%.2x, speed:%d\n", fdr, speed);
#endif
- writeb(dfsr, &dev->dfsrr); /* set default filter */
- writeb(fdr, &dev->fdr); /* set bus speed */
+ writeb(dfsr, &base->dfsrr); /* set default filter */
+ writeb(fdr, &base->fdr); /* set bus speed */
#else
unsigned int i;
fdr = fsl_i2c_speed_map[i].fdr;
speed = i2c_clk / fsl_i2c_speed_map[i].divider;
- writeb(fdr, &dev->fdr); /* set bus speed */
+ writeb(fdr, &base->fdr); /* set bus speed */
break;
}
return speed;
}
+#ifndef CONFIG_DM_I2C
static unsigned int get_i2c_clock(int bus)
{
if (bus)
else
return gd->arch.i2c1_clk; /* I2C1 clock */
}
+#endif
-static int fsl_i2c_fixup(const struct fsl_i2c *dev)
+static int fsl_i2c_fixup(const struct fsl_i2c_base *base)
{
const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT);
unsigned long long timeval = 0;
flags = I2C_CR_BIT6;
#endif
- writeb(I2C_CR_MEN | I2C_CR_MSTA, &dev->cr);
+ writeb(I2C_CR_MEN | I2C_CR_MSTA, &base->cr);
timeval = get_ticks();
- while (!(readb(&dev->sr) & I2C_SR_MBB)) {
+ while (!(readb(&base->sr) & I2C_SR_MBB)) {
if ((get_ticks() - timeval) > timeout)
goto err;
}
- if (readb(&dev->sr) & I2C_SR_MAL) {
+ if (readb(&base->sr) & I2C_SR_MAL) {
/* SDA is stuck low */
- writeb(0, &dev->cr);
+ writeb(0, &base->cr);
udelay(100);
- writeb(I2C_CR_MSTA | flags, &dev->cr);
- writeb(I2C_CR_MEN | I2C_CR_MSTA | flags, &dev->cr);
+ writeb(I2C_CR_MSTA | flags, &base->cr);
+ writeb(I2C_CR_MEN | I2C_CR_MSTA | flags, &base->cr);
}
- readb(&dev->dr);
+ readb(&base->dr);
timeval = get_ticks();
- while (!(readb(&dev->sr) & I2C_SR_MIF)) {
+ while (!(readb(&base->sr) & I2C_SR_MIF)) {
if ((get_ticks() - timeval) > timeout)
goto err;
}
ret = 0;
err:
- writeb(I2C_CR_MEN | flags, &dev->cr);
- writeb(0, &dev->sr);
+ writeb(I2C_CR_MEN | flags, &base->cr);
+ writeb(0, &base->sr);
udelay(100);
return ret;
}
-static void fsl_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
+static void __i2c_init(const struct fsl_i2c_base *base, int speed, int
+ slaveadd, int i2c_clk, int busnum)
{
- const struct fsl_i2c *dev;
const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT);
unsigned long long timeval;
*/
i2c_init_board();
#endif
- dev = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
-
- writeb(0, &dev->cr); /* stop I2C controller */
+ writeb(0, &base->cr); /* stop I2C controller */
udelay(5); /* let it shutdown in peace */
- set_i2c_bus_speed(dev, get_i2c_clock(adap->hwadapnr), speed);
- writeb(slaveadd << 1, &dev->adr);/* write slave address */
- writeb(0x0, &dev->sr); /* clear status register */
- writeb(I2C_CR_MEN, &dev->cr); /* start I2C controller */
+ set_i2c_bus_speed(base, i2c_clk, speed);
+ writeb(slaveadd << 1, &base->adr);/* write slave address */
+ writeb(0x0, &base->sr); /* clear status register */
+ writeb(I2C_CR_MEN, &base->cr); /* start I2C controller */
timeval = get_ticks();
- while (readb(&dev->sr) & I2C_SR_MBB) {
+ while (readb(&base->sr) & I2C_SR_MBB) {
if ((get_ticks() - timeval) < timeout)
continue;
- if (fsl_i2c_fixup(dev))
+ if (fsl_i2c_fixup(base))
debug("i2c_init: BUS#%d failed to init\n",
- adap->hwadapnr);
+ busnum);
break;
}
}
static int
-i2c_wait4bus(struct i2c_adapter *adap)
+i2c_wait4bus(const struct fsl_i2c_base *base)
{
- struct fsl_i2c *dev = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
unsigned long long timeval = get_ticks();
const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT);
- while (readb(&dev->sr) & I2C_SR_MBB) {
+ while (readb(&base->sr) & I2C_SR_MBB) {
if ((get_ticks() - timeval) > timeout)
return -1;
}
return 0;
}
-static __inline__ int
-i2c_wait(struct i2c_adapter *adap, int write)
+static inline int
+i2c_wait(const struct fsl_i2c_base *base, int write)
{
u32 csr;
unsigned long long timeval = get_ticks();
const unsigned long long timeout = usec2ticks(CONFIG_I2C_TIMEOUT);
- struct fsl_i2c *dev = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
do {
- csr = readb(&dev->sr);
+ csr = readb(&base->sr);
if (!(csr & I2C_SR_MIF))
continue;
/* Read again to allow register to stabilise */
- csr = readb(&dev->sr);
+ csr = readb(&base->sr);
- writeb(0x0, &dev->sr);
+ writeb(0x0, &base->sr);
if (csr & I2C_SR_MAL) {
debug("i2c_wait: MAL\n");
return -1;
}
-static __inline__ int
-i2c_write_addr(struct i2c_adapter *adap, u8 dev, u8 dir, int rsta)
+static inline int
+i2c_write_addr(const struct fsl_i2c_base *base, u8 dev, u8 dir, int rsta)
{
- struct fsl_i2c *device = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
-
writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX
| (rsta ? I2C_CR_RSTA : 0),
- &device->cr);
+ &base->cr);
- writeb((dev << 1) | dir, &device->dr);
+ writeb((dev << 1) | dir, &base->dr);
- if (i2c_wait(adap, I2C_WRITE_BIT) < 0)
+ if (i2c_wait(base, I2C_WRITE_BIT) < 0)
return 0;
return 1;
}
-static __inline__ int
-__i2c_write(struct i2c_adapter *adap, u8 *data, int length)
+static inline int
+__i2c_write_data(const struct fsl_i2c_base *base, u8 *data, int length)
{
- struct fsl_i2c *dev = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
int i;
for (i = 0; i < length; i++) {
- writeb(data[i], &dev->dr);
+ writeb(data[i], &base->dr);
- if (i2c_wait(adap, I2C_WRITE_BIT) < 0)
+ if (i2c_wait(base, I2C_WRITE_BIT) < 0)
break;
}
return i;
}
-static __inline__ int
-__i2c_read(struct i2c_adapter *adap, u8 *data, int length)
+static inline int
+__i2c_read_data(const struct fsl_i2c_base *base, u8 *data, int length)
{
- struct fsl_i2c *dev = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
int i;
writeb(I2C_CR_MEN | I2C_CR_MSTA | ((length == 1) ? I2C_CR_TXAK : 0),
- &dev->cr);
+ &base->cr);
/* dummy read */
- readb(&dev->dr);
+ readb(&base->dr);
for (i = 0; i < length; i++) {
- if (i2c_wait(adap, I2C_READ_BIT) < 0)
+ if (i2c_wait(base, I2C_READ_BIT) < 0)
break;
/* Generate ack on last next to last byte */
if (i == length - 2)
writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_TXAK,
- &dev->cr);
+ &base->cr);
/* Do not generate stop on last byte */
if (i == length - 1)
writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX,
- &dev->cr);
+ &base->cr);
- data[i] = readb(&dev->dr);
+ data[i] = readb(&base->dr);
}
return i;
}
static int
-fsl_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr, int alen, u8 *data,
- int length)
+__i2c_read(const struct fsl_i2c_base *base, u8 chip_addr, u8 *offset, int olen,
+ u8 *data, int dlen)
{
- struct fsl_i2c *device = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
- int i = -1; /* signal error */
- u8 *a = (u8*)&addr;
- int len = alen * -1;
+ int ret = -1; /* signal error */
- if (i2c_wait4bus(adap) < 0)
+ if (i2c_wait4bus(base) < 0)
return -1;
- /* To handle the need of I2C devices that require to write few bytes
- * (more than 4 bytes of address as in the case of else part)
- * of data before reading, Negative equivalent of length(bytes to write)
- * is passed, but used the +ve part of len for writing data
+ /* Some drivers use offset lengths in excess of 4 bytes. These drivers
+ * adhere to the following convention:
+ * - the offset length is passed as negative (that is, the absolute
+ * value of olen is the actual offset length)
+ * - the offset itself is passed in data, which is overwritten by the
+ * subsequent read operation
*/
- if (alen < 0) {
- /* Generate a START and send the Address and
- * the Tx Bytes to the slave.
- * "START: Address: Write bytes data[len]"
- * IF part supports writing any number of bytes in contrast
- * to the else part, which supports writing address offset
- * of upto 4 bytes only.
- * bytes that need to be written are passed in
- * "data", which will eventually keep the data READ,
- * after writing the len bytes out of it
- */
- if (i2c_write_addr(adap, dev, I2C_WRITE_BIT, 0) != 0)
- i = __i2c_write(adap, data, len);
-
- if (i != len)
+ if (olen < 0) {
+ if (i2c_write_addr(base, chip_addr, I2C_WRITE_BIT, 0) != 0)
+ ret = __i2c_write_data(base, data, -olen);
+
+ if (ret != -olen)
return -1;
- if (length && i2c_write_addr(adap, dev, I2C_READ_BIT, 1) != 0)
- i = __i2c_read(adap, data, length);
+ if (dlen && i2c_write_addr(base, chip_addr,
+ I2C_READ_BIT, 1) != 0)
+ ret = __i2c_read_data(base, data, dlen);
} else {
- if ((!length || alen > 0) &&
- i2c_write_addr(adap, dev, I2C_WRITE_BIT, 0) != 0 &&
- __i2c_write(adap, &a[4 - alen], alen) == alen)
- i = 0; /* No error so far */
-
- if (length &&
- i2c_write_addr(adap, dev, I2C_READ_BIT, alen ? 1 : 0) != 0)
- i = __i2c_read(adap, data, length);
+ if ((!dlen || olen > 0) &&
+ i2c_write_addr(base, chip_addr, I2C_WRITE_BIT, 0) != 0 &&
+ __i2c_write_data(base, offset, olen) == olen)
+ ret = 0; /* No error so far */
+
+ if (dlen && i2c_write_addr(base, chip_addr, I2C_READ_BIT,
+ olen ? 1 : 0) != 0)
+ ret = __i2c_read_data(base, data, dlen);
}
- writeb(I2C_CR_MEN, &device->cr);
+ writeb(I2C_CR_MEN, &base->cr);
- if (i2c_wait4bus(adap)) /* Wait until STOP */
+ if (i2c_wait4bus(base)) /* Wait until STOP */
debug("i2c_read: wait4bus timed out\n");
- if (i == length)
- return 0;
+ if (ret == dlen)
+ return 0;
return -1;
}
static int
-fsl_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr, int alen,
- u8 *data, int length)
+__i2c_write(const struct fsl_i2c_base *base, u8 chip_addr, u8 *offset, int olen,
+ u8 *data, int dlen)
{
- struct fsl_i2c *device = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
- int i = -1; /* signal error */
- u8 *a = (u8*)&addr;
+ int ret = -1; /* signal error */
- if (i2c_wait4bus(adap) < 0)
+ if (i2c_wait4bus(base) < 0)
return -1;
- if (i2c_write_addr(adap, dev, I2C_WRITE_BIT, 0) != 0 &&
- __i2c_write(adap, &a[4 - alen], alen) == alen) {
- i = __i2c_write(adap, data, length);
+ if (i2c_write_addr(base, chip_addr, I2C_WRITE_BIT, 0) != 0 &&
+ __i2c_write_data(base, offset, olen) == olen) {
+ ret = __i2c_write_data(base, data, dlen);
}
- writeb(I2C_CR_MEN, &device->cr);
- if (i2c_wait4bus(adap)) /* Wait until STOP */
+ writeb(I2C_CR_MEN, &base->cr);
+ if (i2c_wait4bus(base)) /* Wait until STOP */
debug("i2c_write: wait4bus timed out\n");
- if (i == length)
- return 0;
+ if (ret == dlen)
+ return 0;
return -1;
}
static int
-fsl_i2c_probe(struct i2c_adapter *adap, uchar chip)
+__i2c_probe_chip(const struct fsl_i2c_base *base, uchar chip)
{
- struct fsl_i2c *dev = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
/* For unknow reason the controller will ACK when
* probing for a slave with the same address, so skip
* it.
*/
- if (chip == (readb(&dev->adr) >> 1))
+ if (chip == (readb(&base->adr) >> 1))
return -1;
- return fsl_i2c_read(adap, chip, 0, 0, NULL, 0);
+ return __i2c_read(base, chip, 0, 0, NULL, 0);
}
-static unsigned int fsl_i2c_set_bus_speed(struct i2c_adapter *adap,
- unsigned int speed)
+static unsigned int __i2c_set_bus_speed(const struct fsl_i2c_base *base,
+ unsigned int speed, int i2c_clk)
{
- struct fsl_i2c *dev = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
-
- writeb(0, &dev->cr); /* stop controller */
- set_i2c_bus_speed(dev, get_i2c_clock(adap->hwadapnr), speed);
- writeb(I2C_CR_MEN, &dev->cr); /* start controller */
+ writeb(0, &base->cr); /* stop controller */
+ set_i2c_bus_speed(base, i2c_clk, speed);
+ writeb(I2C_CR_MEN, &base->cr); /* start controller */
return 0;
}
+#ifndef CONFIG_DM_I2C
+static void fsl_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
+{
+ __i2c_init(i2c_base[adap->hwadapnr], speed, slaveadd,
+ get_i2c_clock(adap->hwadapnr), adap->hwadapnr);
+}
+
+static int
+fsl_i2c_probe_chip(struct i2c_adapter *adap, uchar chip)
+{
+ return __i2c_probe_chip(i2c_base[adap->hwadapnr], chip);
+}
+
+static int
+fsl_i2c_read(struct i2c_adapter *adap, u8 chip_addr, uint offset, int olen,
+ u8 *data, int dlen)
+{
+ u8 *o = (u8 *)&offset;
+ return __i2c_read(i2c_base[adap->hwadapnr], chip_addr, &o[4 - olen],
+ olen, data, dlen);
+}
+
+static int
+fsl_i2c_write(struct i2c_adapter *adap, u8 chip_addr, uint offset, int olen,
+ u8 *data, int dlen)
+{
+ u8 *o = (u8 *)&offset;
+ return __i2c_write(i2c_base[adap->hwadapnr], chip_addr, &o[4 - olen],
+ olen, data, dlen);
+}
+
+static unsigned int fsl_i2c_set_bus_speed(struct i2c_adapter *adap,
+ unsigned int speed)
+{
+ return __i2c_set_bus_speed(i2c_base[adap->hwadapnr], speed,
+ get_i2c_clock(adap->hwadapnr));
+}
+
/*
* Register fsl i2c adapters
*/
-U_BOOT_I2C_ADAP_COMPLETE(fsl_0, fsl_i2c_init, fsl_i2c_probe, fsl_i2c_read,
+U_BOOT_I2C_ADAP_COMPLETE(fsl_0, fsl_i2c_init, fsl_i2c_probe_chip, fsl_i2c_read,
fsl_i2c_write, fsl_i2c_set_bus_speed,
CONFIG_SYS_FSL_I2C_SPEED, CONFIG_SYS_FSL_I2C_SLAVE,
0)
#ifdef CONFIG_SYS_FSL_I2C2_OFFSET
-U_BOOT_I2C_ADAP_COMPLETE(fsl_1, fsl_i2c_init, fsl_i2c_probe, fsl_i2c_read,
+U_BOOT_I2C_ADAP_COMPLETE(fsl_1, fsl_i2c_init, fsl_i2c_probe_chip, fsl_i2c_read,
fsl_i2c_write, fsl_i2c_set_bus_speed,
CONFIG_SYS_FSL_I2C2_SPEED, CONFIG_SYS_FSL_I2C2_SLAVE,
1)
#endif
#ifdef CONFIG_SYS_FSL_I2C3_OFFSET
-U_BOOT_I2C_ADAP_COMPLETE(fsl_2, fsl_i2c_init, fsl_i2c_probe, fsl_i2c_read,
+U_BOOT_I2C_ADAP_COMPLETE(fsl_2, fsl_i2c_init, fsl_i2c_probe_chip, fsl_i2c_read,
fsl_i2c_write, fsl_i2c_set_bus_speed,
CONFIG_SYS_FSL_I2C3_SPEED, CONFIG_SYS_FSL_I2C3_SLAVE,
2)
#endif
#ifdef CONFIG_SYS_FSL_I2C4_OFFSET
-U_BOOT_I2C_ADAP_COMPLETE(fsl_3, fsl_i2c_init, fsl_i2c_probe, fsl_i2c_read,
+U_BOOT_I2C_ADAP_COMPLETE(fsl_3, fsl_i2c_init, fsl_i2c_probe_chip, fsl_i2c_read,
fsl_i2c_write, fsl_i2c_set_bus_speed,
CONFIG_SYS_FSL_I2C4_SPEED, CONFIG_SYS_FSL_I2C4_SLAVE,
3)
#endif
+#else /* CONFIG_DM_I2C */
+static int fsl_i2c_probe_chip(struct udevice *bus, u32 chip_addr,
+ u32 chip_flags)
+{
+ struct fsl_i2c_dev *dev = dev_get_priv(bus);
+ return __i2c_probe_chip(dev->base, chip_addr);
+}
+
+static int fsl_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
+{
+ struct fsl_i2c_dev *dev = dev_get_priv(bus);
+ return __i2c_set_bus_speed(dev->base, speed, dev->i2c_clk);
+}
+
+static int fsl_i2c_ofdata_to_platdata(struct udevice *bus)
+{
+ struct fsl_i2c_dev *dev = dev_get_priv(bus);
+ u64 reg;
+ u32 addr, size;
+
+ reg = fdtdec_get_addr(gd->fdt_blob, bus->of_offset, "reg");
+ addr = reg >> 32;
+ size = reg & 0xFFFFFFFF;
+
+ dev->base = map_sysmem(CONFIG_SYS_IMMR + addr, size);
+
+ if (!dev->base)
+ return -ENOMEM;
+
+ dev->index = fdtdec_get_int(gd->fdt_blob, bus->of_offset,
+ "cell-index", -1);
+ dev->slaveadd = fdtdec_get_int(gd->fdt_blob, bus->of_offset,
+ "u-boot,i2c-slave-addr", 0x7f);
+ dev->speed = fdtdec_get_int(gd->fdt_blob, bus->of_offset,
+ "clock-frequency", 400000);
+
+ dev->i2c_clk = dev->index ? gd->arch.i2c2_clk : gd->arch.i2c1_clk;
+
+ return 0;
+}
+
+static int fsl_i2c_probe(struct udevice *bus)
+{
+ struct fsl_i2c_dev *dev = dev_get_priv(bus);
+ __i2c_init(dev->base, dev->speed, dev->slaveadd, dev->i2c_clk,
+ dev->index);
+ return 0;
+}
+
+static int fsl_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
+{
+ struct fsl_i2c_dev *dev = dev_get_priv(bus);
+ struct i2c_msg *dmsg, *omsg, dummy;
+
+ memset(&dummy, 0, sizeof(struct i2c_msg));
+
+ /* We expect either two messages (one with an offset and one with the
+ * actucal data) or one message (just data) */
+ if (nmsgs > 2 || nmsgs == 0) {
+ debug("%s: Only one or two messages are supported.", __func__);
+ return -1;
+ }
+
+ omsg = nmsgs == 1 ? &dummy : msg;
+ dmsg = nmsgs == 1 ? msg : msg + 1;
+
+ if (dmsg->flags & I2C_M_RD)
+ return __i2c_read(dev->base, dmsg->addr, omsg->buf, omsg->len,
+ dmsg->buf, dmsg->len);
+ else
+ return __i2c_write(dev->base, dmsg->addr, omsg->buf, omsg->len,
+ dmsg->buf, dmsg->len);
+}
+
+static const struct dm_i2c_ops fsl_i2c_ops = {
+ .xfer = fsl_i2c_xfer,
+ .probe_chip = fsl_i2c_probe_chip,
+ .set_bus_speed = fsl_i2c_set_bus_speed,
+};
+
+static const struct udevice_id fsl_i2c_ids[] = {
+ { .compatible = "fsl-i2c", },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(i2c_fsl) = {
+ .name = "i2c_fsl",
+ .id = UCLASS_I2C,
+ .of_match = fsl_i2c_ids,
+ .probe = fsl_i2c_probe,
+ .ofdata_to_platdata = fsl_i2c_ofdata_to_platdata,
+ .priv_auto_alloc_size = sizeof(struct fsl_i2c_dev),
+ .ops = &fsl_i2c_ops,
+};
+
+#endif /* CONFIG_DM_I2C */
struct i2c_cdns_bus {
int id;
+ unsigned int input_freq;
struct cdns_i2c_regs __iomem *regs; /* register base */
};
-
-/** cdns_i2c_probe() - Probe method
- * @dev: udevice pointer
- *
- * DM callback called when device is probed
- */
-static int cdns_i2c_probe(struct udevice *dev)
-{
- struct i2c_cdns_bus *bus = dev_get_priv(dev);
-
- bus->regs = (struct cdns_i2c_regs *)dev_get_addr(dev);
- if (!bus->regs)
- return -ENOMEM;
-
- /* TODO: Calculate dividers based on CPU_CLK_1X */
- /* 111MHz / ( (3 * 17) * 22 ) = ~100KHz */
- writel((16 << CDNS_I2C_CONTROL_DIV_B_SHIFT) |
- (2 << CDNS_I2C_CONTROL_DIV_A_SHIFT), &bus->regs->control);
-
- /* Enable master mode, ack, and 7-bit addressing */
- setbits_le32(&bus->regs->control, CDNS_I2C_CONTROL_MS |
- CDNS_I2C_CONTROL_ACKEN | CDNS_I2C_CONTROL_NEA);
-
- debug("%s bus %d at %p\n", __func__, dev->seq, bus->regs);
-
- return 0;
-}
-
-static int cdns_i2c_remove(struct udevice *dev)
-{
- struct i2c_cdns_bus *bus = dev_get_priv(dev);
-
- debug("%s bus %d at %p\n", __func__, dev->seq, bus->regs);
-
- unmap_sysmem(bus->regs);
-
- return 0;
-}
-
/* Wait for an interrupt */
static u32 cdns_i2c_wait(struct cdns_i2c_regs *cdns_i2c, u32 mask)
{
return int_status & mask;
}
+#define CDNS_I2C_DIVA_MAX 4
+#define CDNS_I2C_DIVB_MAX 64
+
+static int cdns_i2c_calc_divs(unsigned long *f, unsigned long input_clk,
+ unsigned int *a, unsigned int *b)
+{
+ unsigned long fscl = *f, best_fscl = *f, actual_fscl, temp;
+ unsigned int div_a, div_b, calc_div_a = 0, calc_div_b = 0;
+ unsigned int last_error, current_error;
+
+ /* calculate (divisor_a+1) x (divisor_b+1) */
+ temp = input_clk / (22 * fscl);
+
+ /*
+ * If the calculated value is negative or 0CDNS_I2C_DIVA_MAX,
+ * the fscl input is out of range. Return error.
+ */
+ if (!temp || (temp > (CDNS_I2C_DIVA_MAX * CDNS_I2C_DIVB_MAX)))
+ return -EINVAL;
+
+ last_error = -1;
+ for (div_a = 0; div_a < CDNS_I2C_DIVA_MAX; div_a++) {
+ div_b = DIV_ROUND_UP(input_clk, 22 * fscl * (div_a + 1));
+
+ if ((div_b < 1) || (div_b > CDNS_I2C_DIVB_MAX))
+ continue;
+ div_b--;
+
+ actual_fscl = input_clk / (22 * (div_a + 1) * (div_b + 1));
+
+ if (actual_fscl > fscl)
+ continue;
+
+ current_error = ((actual_fscl > fscl) ? (actual_fscl - fscl) :
+ (fscl - actual_fscl));
+
+ if (last_error > current_error) {
+ calc_div_a = div_a;
+ calc_div_b = div_b;
+ best_fscl = actual_fscl;
+ last_error = current_error;
+ }
+ }
+
+ *a = calc_div_a;
+ *b = calc_div_b;
+ *f = best_fscl;
+
+ return 0;
+}
+
static int cdns_i2c_set_bus_speed(struct udevice *dev, unsigned int speed)
{
- if (speed != 100000) {
- printf("%s, failed to set clock speed to %u\n", __func__,
- speed);
+ struct i2c_cdns_bus *bus = dev_get_priv(dev);
+ u32 div_a = 0, div_b = 0;
+ unsigned long speed_p = speed;
+ int ret = 0;
+
+ if (speed > 400000) {
+ debug("%s, failed to set clock speed to %u\n", __func__,
+ speed);
return -EINVAL;
}
+ ret = cdns_i2c_calc_divs(&speed_p, bus->input_freq, &div_a, &div_b);
+ if (ret)
+ return ret;
+
+ debug("%s: div_a: %d, div_b: %d, input freq: %d, speed: %d/%ld\n",
+ __func__, div_a, div_b, bus->input_freq, speed, speed_p);
+
+ writel((div_b << CDNS_I2C_CONTROL_DIV_B_SHIFT) |
+ (div_a << CDNS_I2C_CONTROL_DIV_A_SHIFT), &bus->regs->control);
+
+ /* Enable master mode, ack, and 7-bit addressing */
+ setbits_le32(&bus->regs->control, CDNS_I2C_CONTROL_MS |
+ CDNS_I2C_CONTROL_ACKEN | CDNS_I2C_CONTROL_NEA);
+
return 0;
}
return 0;
}
+static int cdns_i2c_ofdata_to_platdata(struct udevice *dev)
+{
+ struct i2c_cdns_bus *i2c_bus = dev_get_priv(dev);
+
+ i2c_bus->regs = (struct cdns_i2c_regs *)dev_get_addr(dev);
+ if (!i2c_bus->regs)
+ return -ENOMEM;
+
+ i2c_bus->input_freq = 100000000; /* TODO hardcode input freq for now */
+
+ return 0;
+}
+
static const struct dm_i2c_ops cdns_i2c_ops = {
.xfer = cdns_i2c_xfer,
.probe_chip = cdns_i2c_probe_chip,
.name = "i2c-cdns",
.id = UCLASS_I2C,
.of_match = cdns_i2c_of_match,
- .probe = cdns_i2c_probe,
- .remove = cdns_i2c_remove,
+ .ofdata_to_platdata = cdns_i2c_ofdata_to_platdata,
.priv_auto_alloc_size = sizeof(struct i2c_cdns_bus),
.ops = &cdns_i2c_ops,
};
I2C multimaster arbitration scheme using GPIOs and a challenge &
response mechanism where masters have to claim the bus by asserting
a GPIO.
+
+config I2C_MUX_PCA954x
+ tristate "TI PCA954x I2C Mux/switches"
+ depends on I2C_MUX
+ help
+ If you say yes here you get support for the TI PCA954x
+ I2C mux/switch devices. It is x width I2C multiplexer which enables to
+ paritioning I2C bus and connect multiple devices with the same address
+ to the same I2C controller where driver handles proper routing to
+ target i2c device. PCA9544 and PCA9548 are supported.
#
obj-$(CONFIG_I2C_ARB_GPIO_CHALLENGE) += i2c-arb-gpio-challenge.o
obj-$(CONFIG_$(SPL_)I2C_MUX) += i2c-mux-uclass.o
+obj-$(CONFIG_I2C_MUX_PCA954x) += pca954x.o
--- /dev/null
+/*
+ * Copyright (C) 2015 - 2016 Xilinx, Inc.
+ * Written by Michal Simek
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <i2c.h>
+#include <asm/gpio.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct pca954x_priv {
+ u32 addr; /* I2C mux address */
+ u32 width; /* I2C mux width - number of busses */
+};
+
+static int pca954x_deselect(struct udevice *mux, struct udevice *bus,
+ uint channel)
+{
+ struct pca954x_priv *priv = dev_get_priv(mux);
+ uchar byte = 0;
+
+ return dm_i2c_write(mux, priv->addr, &byte, 1);
+}
+
+static int pca954x_select(struct udevice *mux, struct udevice *bus,
+ uint channel)
+{
+ struct pca954x_priv *priv = dev_get_priv(mux);
+ uchar byte = 1 << channel;
+
+ return dm_i2c_write(mux, priv->addr, &byte, 1);
+}
+
+static const struct i2c_mux_ops pca954x_ops = {
+ .select = pca954x_select,
+ .deselect = pca954x_deselect,
+};
+
+static const struct udevice_id pca954x_ids[] = {
+ { .compatible = "nxp,pca9548", .data = (ulong)8 },
+ { .compatible = "nxp,pca9544", .data = (ulong)4 },
+ { }
+};
+
+static int pca954x_ofdata_to_platdata(struct udevice *dev)
+{
+ struct pca954x_priv *priv = dev_get_priv(dev);
+
+ priv->addr = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "reg", 0);
+ if (!priv->addr) {
+ debug("MUX not found\n");
+ return -ENODEV;
+ }
+ priv->width = dev_get_driver_data(dev);
+
+ if (!priv->width) {
+ debug("No I2C MUX width specified\n");
+ return -EINVAL;
+ }
+
+ debug("Device %s at 0x%x with width %d\n",
+ dev->name, priv->addr, priv->width);
+
+ return 0;
+}
+
+U_BOOT_DRIVER(pca954x) = {
+ .name = "pca954x",
+ .id = UCLASS_I2C_MUX,
+ .of_match = pca954x_ids,
+ .ops = &pca954x_ops,
+ .ofdata_to_platdata = pca954x_ofdata_to_platdata,
+ .priv_auto_alloc_size = sizeof(struct pca954x_priv),
+};
MVTWSI_ERROR_TIMEOUT, control, status, expected_status);
}
-/*
- * These flags are ORed to any write to the control register
- * They allow global setting of TWSIEN and ACK.
- * By default none are set.
- * twsi_start() sets TWSIEN (in case the controller was disabled)
- * twsi_recv() sets ACK or resets it depending on expected status.
- */
-static u8 twsi_control_flags = MVTWSI_CONTROL_TWSIEN;
-
/*
* Assert the START condition, either in a single I2C transaction
* or inside back-to-back ones (repeated starts).
*/
-static int twsi_start(struct i2c_adapter *adap, int expected_status)
+static int twsi_start(struct i2c_adapter *adap, int expected_status, u8 *flags)
{
struct mvtwsi_registers *twsi = twsi_get_base(adap);
/* globally set TWSIEN in case it was not */
- twsi_control_flags |= MVTWSI_CONTROL_TWSIEN;
+ *flags |= MVTWSI_CONTROL_TWSIEN;
/* assert START */
- writel(twsi_control_flags | MVTWSI_CONTROL_START |
+ writel(*flags | MVTWSI_CONTROL_START |
MVTWSI_CONTROL_CLEAR_IFLG, &twsi->control);
/* wait for controller to process START */
return twsi_wait(adap, expected_status);
/*
* Send a byte (i2c address or data).
*/
-static int twsi_send(struct i2c_adapter *adap, u8 byte, int expected_status)
+static int twsi_send(struct i2c_adapter *adap, u8 byte, int expected_status,
+ u8 *flags)
{
struct mvtwsi_registers *twsi = twsi_get_base(adap);
/* put byte in data register for sending */
writel(byte, &twsi->data);
/* clear any pending interrupt -- that'll cause sending */
- writel(twsi_control_flags | MVTWSI_CONTROL_CLEAR_IFLG, &twsi->control);
+ writel(*flags | MVTWSI_CONTROL_CLEAR_IFLG, &twsi->control);
/* wait for controller to receive byte and check ACK */
return twsi_wait(adap, expected_status);
}
* Receive a byte.
* Global mvtwsi_control_flags variable says if we should ack or nak.
*/
-static int twsi_recv(struct i2c_adapter *adap, u8 *byte)
+static int twsi_recv(struct i2c_adapter *adap, u8 *byte, u8 *flags)
{
struct mvtwsi_registers *twsi = twsi_get_base(adap);
int expected_status, status;
/* compute expected status based on ACK bit in global control flags */
- if (twsi_control_flags & MVTWSI_CONTROL_ACK)
+ if (*flags & MVTWSI_CONTROL_ACK)
expected_status = MVTWSI_STATUS_DATA_R_ACK;
else
expected_status = MVTWSI_STATUS_DATA_R_NAK;
/* acknowledge *previous state* and launch receive */
- writel(twsi_control_flags | MVTWSI_CONTROL_CLEAR_IFLG, &twsi->control);
+ writel(*flags | MVTWSI_CONTROL_CLEAR_IFLG, &twsi->control);
/* wait for controller to receive byte and assert ACK or NAK */
status = twsi_wait(adap, expected_status);
/* if we did receive expected byte then store it */
static void twsi_reset(struct i2c_adapter *adap)
{
struct mvtwsi_registers *twsi = twsi_get_base(adap);
- /* ensure controller will be enabled by any twsi*() function */
- twsi_control_flags = MVTWSI_CONTROL_TWSIEN;
+
/* reset controller */
writel(0, &twsi->soft_reset);
/* wait 2 ms -- this is what the Marvell LSP does */
* Expected address status will derive from direction bit (bit 0) in addr.
*/
static int i2c_begin(struct i2c_adapter *adap, int expected_start_status,
- u8 addr)
+ u8 addr, u8 *flags)
{
int status, expected_addr_status;
else /* writing */
expected_addr_status = MVTWSI_STATUS_ADDR_W_ACK;
/* assert START */
- status = twsi_start(adap, expected_start_status);
+ status = twsi_start(adap, expected_start_status, flags);
/* send out the address if the start went well */
if (status == 0)
- status = twsi_send(adap, addr, expected_addr_status);
+ status = twsi_send(adap, addr, expected_addr_status,
+ flags);
/* return ok or status of first failure to caller */
return status;
}
static int twsi_i2c_probe(struct i2c_adapter *adap, uchar chip)
{
u8 dummy_byte;
+ u8 flags = 0;
int status;
/* begin i2c read */
- status = i2c_begin(adap, MVTWSI_STATUS_START, (chip << 1) | 1);
+ status = i2c_begin(adap, MVTWSI_STATUS_START, (chip << 1) | 1, &flags);
/* dummy read was accepted: receive byte but NAK it. */
if (status == 0)
- status = twsi_recv(adap, &dummy_byte);
+ status = twsi_recv(adap, &dummy_byte, &flags);
/* Stop transaction */
twsi_stop(adap, 0);
/* return 0 or status of first failure */
int alen, uchar *data, int length)
{
int status;
+ u8 flags = 0;
/* begin i2c write to send the address bytes */
- status = i2c_begin(adap, MVTWSI_STATUS_START, (chip << 1));
+ status = i2c_begin(adap, MVTWSI_STATUS_START, (chip << 1), &flags);
/* send addr bytes */
while ((status == 0) && alen--)
status = twsi_send(adap, addr >> (8*alen),
- MVTWSI_STATUS_DATA_W_ACK);
+ MVTWSI_STATUS_DATA_W_ACK, &flags);
/* begin i2c read to receive eeprom data bytes */
if (status == 0)
status = i2c_begin(adap, MVTWSI_STATUS_REPEATED_START,
- (chip << 1) | 1);
+ (chip << 1) | 1, &flags);
/* prepare ACK if at least one byte must be received */
if (length > 0)
- twsi_control_flags |= MVTWSI_CONTROL_ACK;
+ flags |= MVTWSI_CONTROL_ACK;
/* now receive actual bytes */
while ((status == 0) && length--) {
/* reset NAK if we if no more to read now */
if (length == 0)
- twsi_control_flags &= ~MVTWSI_CONTROL_ACK;
+ flags &= ~MVTWSI_CONTROL_ACK;
/* read current byte */
- status = twsi_recv(adap, data++);
+ status = twsi_recv(adap, data++, &flags);
}
/* Stop transaction */
status = twsi_stop(adap, status);
int alen, uchar *data, int length)
{
int status;
+ u8 flags = 0;
/* begin i2c write to send the eeprom adress bytes then data bytes */
- status = i2c_begin(adap, MVTWSI_STATUS_START, (chip << 1));
+ status = i2c_begin(adap, MVTWSI_STATUS_START, (chip << 1), &flags);
/* send addr bytes */
while ((status == 0) && alen--)
status = twsi_send(adap, addr >> (8*alen),
- MVTWSI_STATUS_DATA_W_ACK);
+ MVTWSI_STATUS_DATA_W_ACK, &flags);
/* send data bytes */
while ((status == 0) && (length-- > 0))
- status = twsi_send(adap, *(data++), MVTWSI_STATUS_DATA_W_ACK);
+ status = twsi_send(adap, *(data++), MVTWSI_STATUS_DATA_W_ACK,
+ &flags);
/* Stop transaction */
status = twsi_stop(adap, status);
/* return 0 or status of first failure */
static int spi_load_image_os(struct spi_flash *flash,
struct image_header *header)
{
+ int err;
+
/* Read for a header, parse or error out. */
spi_flash_read(flash, CONFIG_SYS_SPI_KERNEL_OFFS, 0x40,
(void *)header);
if (image_get_magic(header) != IH_MAGIC)
return -1;
- spl_parse_image_header(header);
+ err = spl_parse_image_header(header);
+ if (err)
+ return err;
spi_flash_read(flash, CONFIG_SYS_SPI_KERNEL_OFFS,
spl_image.size, (void *)spl_image.load_addr);
if (err)
return err;
- spl_parse_image_header(header);
+ err = spl_parse_image_header(header);
+ if (err)
+ return err;
err = spi_flash_read(flash, CONFIG_SYS_SPI_U_BOOT_OFFS,
spl_image.size, (void *)spl_image.load_addr);
}
*/
__raw_writel((div / 16) << 16, DI_BS_CLKGEN1(clk->id));
- clk->rate = (u64)(clk->parent->rate * 16) / div;
+ do_div(parent_rate, div);
+
+ clk->rate = parent_rate;
return 0;
}
* I2C configuration
*/
#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_DW
#define CONFIG_I2C_ENV_EEPROM_BUS 2
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_SYS_I2C_SPEED1 100000
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 800 /* 400 KB */
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SYS_MONITOR_LEN (CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS/2*1024)
+#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
+#define CONFIG_SPL_EXT_SUPPORT
#endif
/* SATA support */
#if defined(CONFIG_SPL_SATA_SUPPORT)
#define CONFIG_SPL_SATA_BOOT_DEVICE 0
#define CONFIG_SYS_SATA_FAT_BOOT_PARTITION 1
+#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
+#define CONFIG_SPL_EXT_SUPPORT
#endif
/* Define the payload for FAT/EXT support */
/* SPL */
#define CONFIG_SPL_FAT_SUPPORT
-#define CONFIG_SPL_EXT_SUPPORT
#define CONFIG_SPL_MMC_SUPPORT
#include "imx6_spl.h" /* common IMX6 SPL configuration */
#define CONFIG_USB_EHCI_MX6
#define CONFIG_USB_STORAGE
#define CONFIG_USB_KEYBOARD
+#define CONFIG_SYS_STDIO_DEREGISTER
#define CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP
#define CONFIG_USB_HOST_ETHER
#define CONFIG_USB_ETHER_ASIX
* I2C support
*/
#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_DW
#define CONFIG_SYS_I2C_BUS_MAX 4
#define CONFIG_SYS_I2C_BASE SOCFPGA_I2C0_ADDRESS
#define CONFIG_SYS_I2C_BASE1 SOCFPGA_I2C1_ADDRESS
/* I2C driver configuration */
#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_DW
#if defined(CONFIG_SPEAR600)
#define CONFIG_SYS_I2C_BASE 0xD0200000
#elif defined(CONFIG_SPEAR300)
#define CONFIG_SPL_MMC_SUPPORT
#define CONFIG_SPL_SPI_SUPPORT
#define CONFIG_SPL_FAT_SUPPORT
-#define CONFIG_SPL_EXT_SUPPORT
/* common IMX6 SPL configuration */
#include "imx6_spl.h"
/* I2C config options */
#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_DW
#define CONFIG_SYS_I2C_BASE 0xD0200000
#define CONFIG_SYS_I2C_SPEED 400000
#define CONFIG_SYS_I2C_SLAVE 0x02
u32 spl_boot_device(void);
u32 spl_boot_mode(void);
void spl_set_header_raw_uboot(void);
-void spl_parse_image_header(const struct image_header *header);
+int spl_parse_image_header(const struct image_header *header);
void spl_board_prepare_for_linux(void);
void __noreturn jump_to_image_linux(void *arg);
int spl_start_uboot(void);
d = d2;
d->write_dcd_command.tag = DCD_CHECK_DATA_COMMAND_TAG;
d->write_dcd_command.length = cpu_to_be16(4);
- d->write_dcd_command.param = DCD_CHECK_BITS_SET_PARAM;
+ d->write_dcd_command.param = DCD_CHECK_BITS_CLR_PARAM;
break;
default:
break;
projects / oweals / u-boot.git / commitdiff