arm: dts: sync dts for Action Semi S900

Synchronize device tree bindings with v5.5-rc6 tag with commit id
"b3a987b0264d".

Also, it removes older clock binding defined for S900 along with undocumented
compatible string "actions,s900-serial" from serial driver and adapts clock
driver to cater to new bindings.

Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 59a2713cb2da8b242cad31f3db7df503cee27874..ba96efaa1e6ccd8b0b0bcf026753d28d5231612c 100644 (file)
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -64,7 +64,7 @@ dtb-$(CONFIG_KIRKWOOD) += \
        kirkwood-pogo_e02.dtb \
        kirkwood-sheevaplug.dtb
 
-dtb-$(CONFIG_ARCH_OWL) += \
+dtb-$(CONFIG_MACH_S900) += \
        bubblegum_96.dtb
 
 dtb-$(CONFIG_ROCKCHIP_PX30) += \

diff --git a/arch/arm/dts/s900.dtsi b/arch/arm/dts/s900.dtsi
index 2bbb30a5a8657101b13e4ece22fe930f0cd5b542..eb35cf78ab73e54e2258db37c45910c77d6a31c2 100644 (file)
--- a/arch/arm/dts/s900.dtsi
+++ b/arch/arm/dts/s900.dtsi
@@ -1,17 +1,94 @@
-// SPDX-License-Identifier: GPL-2.0+
-//
-// Device Tree Source for Actions Semi S900 SoC
-//
-// Copyright (C) 2015 Actions Semi Co., Ltd.
-// Copyright (C) 2018 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2017 Andreas Färber
+ */
 
-/dts-v1/;
-#include <dt-bindings/clock/s900_cmu.h>
+#include <dt-bindings/clock/actions,s900-cmu.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/reset/actions,s900-reset.h>
 
 / {
        compatible = "actions,s900";
-       #address-cells = <0x2>;
-       #size-cells = <0x2>;
+       interrupt-parent = <&gic>;
+       #address-cells = <2>;
+       #size-cells = <2>;
+
+       cpus {
+               #address-cells = <2>;
+               #size-cells = <0>;
+
+               cpu0: cpu@0 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a53";
+                       reg = <0x0 0x0>;
+                       enable-method = "psci";
+               };
+
+               cpu1: cpu@1 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a53";
+                       reg = <0x0 0x1>;
+                       enable-method = "psci";
+               };
+
+               cpu2: cpu@2 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a53";
+                       reg = <0x0 0x2>;
+                       enable-method = "psci";
+               };
+
+               cpu3: cpu@3 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a53";
+                       reg = <0x0 0x3>;
+                       enable-method = "psci";
+               };
+       };
+
+       reserved-memory {
+               #address-cells = <2>;
+               #size-cells = <2>;
+               ranges;
+
+               secmon@1f000000 {
+                       reg = <0x0 0x1f000000 0x0 0x1000000>;
+                       no-map;
+               };
+       };
+
+       psci {
+               compatible = "arm,psci-0.2";
+               method = "smc";
+       };
+
+       arm-pmu {
+               compatible = "arm,cortex-a53-pmu";
+               interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+       };
+
+       timer {
+               compatible = "arm,armv8-timer";
+               interrupts = <GIC_PPI 13
+                       (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                            <GIC_PPI 14
+                       (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                            <GIC_PPI 11
+                       (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                            <GIC_PPI 10
+                       (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+       };
+
+       hosc: hosc {
+               compatible = "fixed-clock";
+               clock-frequency = <24000000>;
+               #clock-cells = <0>;
+       };
 
        losc: losc {
                compatible = "fixed-clock";
@@ -26,28 +103,231 @@
        };
 
        soc {
-               u-boot,dm-pre-reloc;
                compatible = "simple-bus";
-               #address-cells = <0x2>;
-               #size-cells = <0x2>;
+               #address-cells = <2>;
+               #size-cells = <2>;
                ranges;
 
+               gic: interrupt-controller@e00f1000 {
+                       compatible = "arm,gic-400";
+                       reg = <0x0 0xe00f1000 0x0 0x1000>,
+                             <0x0 0xe00f2000 0x0 0x2000>,
+                             <0x0 0xe00f4000 0x0 0x2000>,
+                             <0x0 0xe00f6000 0x0 0x2000>;
+                       interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+                       interrupt-controller;
+                       #interrupt-cells = <3>;
+               };
+
+               uart0: serial@e0120000 {
+                       compatible = "actions,s900-uart", "actions,owl-uart";
+                       reg = <0x0 0xe0120000 0x0 0x2000>;
+                       clocks = <&cmu CLK_UART0>;
+                       interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+                       status = "disabled";
+               };
+
+               uart1: serial@e0122000 {
+                       compatible = "actions,s900-uart", "actions,owl-uart";
+                       reg = <0x0 0xe0122000 0x0 0x2000>;
+                       clocks = <&cmu CLK_UART1>;
+                       interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+                       status = "disabled";
+               };
+
+               uart2: serial@e0124000 {
+                       compatible = "actions,s900-uart", "actions,owl-uart";
+                       reg = <0x0 0xe0124000 0x0 0x2000>;
+                       clocks = <&cmu CLK_UART2>;
+                       interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+                       status = "disabled";
+               };
+
+               uart3: serial@e0126000 {
+                       compatible = "actions,s900-uart", "actions,owl-uart";
+                       reg = <0x0 0xe0126000 0x0 0x2000>;
+                       clocks = <&cmu CLK_UART3>;
+                       interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+                       status = "disabled";
+               };
+
+               uart4: serial@e0128000 {
+                       compatible = "actions,s900-uart", "actions,owl-uart";
+                       reg = <0x0 0xe0128000 0x0 0x2000>;
+                       clocks = <&cmu CLK_UART4>;
+                       interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+                       status = "disabled";
+               };
+
                uart5: serial@e012a000 {
-                       u-boot,dm-pre-reloc;
-                       compatible = "actions,s900-serial";
-                       reg = <0x0 0xe012a000 0x0 0x1000>;
-                       clocks = <&cmu CLOCK_UART5>;
+                       compatible = "actions,s900-uart", "actions,owl-uart";
+                       reg = <0x0 0xe012a000 0x0 0x2000>;
+                       clocks = <&cmu CLK_UART5>;
+                       interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
                        status = "disabled";
                };
 
+               uart6: serial@e012c000 {
+                       compatible = "actions,s900-uart", "actions,owl-uart";
+                       reg = <0x0 0xe012c000 0x0 0x2000>;
+                       clocks = <&cmu CLK_UART6>;
+                       interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+                       status = "disabled";
+               };
+
+               sps: power-controller@e012e000 {
+                       compatible = "actions,s900-sps";
+                       reg = <0x0 0xe012e000 0x0 0x2000>;
+                       #power-domain-cells = <1>;
+               };
+
                cmu: clock-controller@e0160000 {
-                       u-boot,dm-pre-reloc;
                        compatible = "actions,s900-cmu";
                        reg = <0x0 0xe0160000 0x0 0x1000>;
-                       clocks = <&losc>, <&diff24M>;
-                       clock-names = "losc", "diff24M";
+                       clocks = <&hosc>, <&losc>;
                        #clock-cells = <1>;
+                       #reset-cells = <1>;
+               };
+
+               i2c0: i2c@e0170000 {
+                       compatible = "actions,s900-i2c";
+                       reg = <0 0xe0170000 0 0x1000>;
+                       clocks = <&cmu CLK_I2C0>;
+                       interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
+               i2c1: i2c@e0172000 {
+                       compatible = "actions,s900-i2c";
+                       reg = <0 0xe0172000 0 0x1000>;
+                       clocks = <&cmu CLK_I2C1>;
+                       interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
+               i2c2: i2c@e0174000 {
+                       compatible = "actions,s900-i2c";
+                       reg = <0 0xe0174000 0 0x1000>;
+                       clocks = <&cmu CLK_I2C2>;
+                       interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
+               i2c3: i2c@e0176000 {
+                       compatible = "actions,s900-i2c";
+                       reg = <0 0xe0176000 0 0x1000>;
+                       clocks = <&cmu CLK_I2C3>;
+                       interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
+               i2c4: i2c@e0178000 {
+                       compatible = "actions,s900-i2c";
+                       reg = <0 0xe0178000 0 0x1000>;
+                       clocks = <&cmu CLK_I2C4>;
+                       interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
+               i2c5: i2c@e017a000 {
+                       compatible = "actions,s900-i2c";
+                       reg = <0 0xe017a000 0 0x1000>;
+                       clocks = <&cmu CLK_I2C5>;
+                       interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
+               pinctrl: pinctrl@e01b0000 {
+                       compatible = "actions,s900-pinctrl";
+                       reg = <0x0 0xe01b0000 0x0 0x1000>;
+                       clocks = <&cmu CLK_GPIO>;
+                       gpio-controller;
+                       gpio-ranges = <&pinctrl 0 0 146>;
+                       #gpio-cells = <2>;
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+                       interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+               };
+
+               timer: timer@e0228000 {
+                       compatible = "actions,s900-timer";
+                       reg = <0x0 0xe0228000 0x0 0x8000>;
+                       interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "timer1";
+               };
+
+               dma: dma-controller@e0260000 {
+                       compatible = "actions,s900-dma";
+                       reg = <0x0 0xe0260000 0x0 0x1000>;
+                       interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+                       #dma-cells = <1>;
+                       dma-channels = <12>;
+                       dma-requests = <46>;
+                       clocks = <&cmu CLK_DMAC>;
+               };
+
+               mmc0: mmc@e0330000 {
+                       compatible = "actions,owl-mmc";
+                       reg = <0x0 0xe0330000 0x0 0x4000>;
+                       interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cmu CLK_SD0>;
+                       resets = <&cmu RESET_SD0>;
+                       dmas = <&dma 2>;
+                       dma-names = "mmc";
+                       status = "disabled";
+               };
+
+               mmc1: mmc@e0334000 {
+                       compatible = "actions,owl-mmc";
+                       reg = <0x0 0xe0334000 0x0 0x4000>;
+                       interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cmu CLK_SD1>;
+                       resets = <&cmu RESET_SD1>;
+                       dmas = <&dma 3>;
+                       dma-names = "mmc";
+                       status = "disabled";
+               };
+
+               mmc2: mmc@e0338000 {
+                       compatible = "actions,owl-mmc";
+                       reg = <0x0 0xe0338000 0x0 0x4000>;
+                       interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cmu CLK_SD2>;
+                       resets = <&cmu RESET_SD2>;
+                       dmas = <&dma 4>;
+                       dma-names = "mmc";
+                       status = "disabled";
+               };
+
+               mmc3: mmc@e033c000 {
+                       compatible = "actions,owl-mmc";
+                       reg = <0x0 0xe033c000 0x0 0x4000>;
+                       interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cmu CLK_SD3>;
+                       resets = <&cmu RESET_SD3>;
+                       dmas = <&dma 46>;
+                       dma-names = "mmc";
+                       status = "disabled";
                };
        };
 };
-

diff --git a/drivers/clk/owl/clk_s900.c b/drivers/clk/owl/clk_s900.c
index a7c15d2812e2f8f2bfa08f421de071f2204b2349..d60f199252a634809bb6a940d741a1c7f2ef3c35 100644 (file)
--- a/drivers/clk/owl/clk_s900.c
+++ b/drivers/clk/owl/clk_s900.c
@@ -12,7 +12,7 @@
 #include <asm/arch-owl/regs_s900.h>
 #include <asm/io.h>
 
-#include <dt-bindings/clock/s900_cmu.h>
+#include <dt-bindings/clock/actions,s900-cmu.h>
 
 void owl_clk_init(struct owl_clk_priv *priv)
 {
@@ -78,7 +78,7 @@ int owl_clk_enable(struct clk *clk)
        struct owl_clk_priv *priv = dev_get_priv(clk->dev);
 
        switch (clk->id) {
-       case CLOCK_UART5:
+       case CLK_UART5:
                owl_uart_clk_enable(priv);
                break;
        default:
@@ -93,7 +93,7 @@ int owl_clk_disable(struct clk *clk)
        struct owl_clk_priv *priv = dev_get_priv(clk->dev);
 
        switch (clk->id) {
-       case CLOCK_UART5:
+       case CLK_UART5:
                owl_uart_clk_disable(priv);
                break;
        default:

diff --git a/drivers/serial/serial_owl.c b/drivers/serial/serial_owl.c
index 539acdc92a5a88fa8338862430ba8602fc8d03ca..bb60ca2d9b81b03727ebe2c9d900961e447924e0 100644 (file)
--- a/drivers/serial/serial_owl.c
+++ b/drivers/serial/serial_owl.c
@@ -120,7 +120,6 @@ static const struct dm_serial_ops owl_serial_ops = {
 };
 
 static const struct udevice_id owl_serial_ids[] = {
-       { .compatible = "actions,s900-serial" },
        { .compatible = "actions,owl-uart" },
        { }
 };

diff --git a/include/dt-bindings/clock/actions,s900-cmu.h b/include/dt-bindings/clock/actions,s900-cmu.h
new file mode 100644 (file)
index 0000000..7c12515
--- /dev/null
+++ b/include/dt-bindings/clock/actions,s900-cmu.h
@@ -0,0 +1,129 @@
+// SPDX-License-Identifier: GPL-2.0+
+//
+// Device Tree binding constants for Actions Semi S900 Clock Management Unit
+//
+// Copyright (c) 2014 Actions Semi Inc.
+// Copyright (c) 2018 Linaro Ltd.
+
+#ifndef __DT_BINDINGS_CLOCK_S900_CMU_H
+#define __DT_BINDINGS_CLOCK_S900_CMU_H
+
+#define CLK_NONE                       0
+
+/* fixed rate clocks */
+#define CLK_LOSC                       1
+#define CLK_HOSC                       2
+
+/* pll clocks */
+#define CLK_CORE_PLL                   3
+#define CLK_DEV_PLL                    4
+#define CLK_DDR_PLL                    5
+#define CLK_NAND_PLL                   6
+#define CLK_DISPLAY_PLL                        7
+#define CLK_DSI_PLL                    8
+#define CLK_ASSIST_PLL                 9
+#define CLK_AUDIO_PLL                  10
+
+/* system clock */
+#define CLK_CPU                                15
+#define CLK_DEV                                16
+#define CLK_NOC                                17
+#define CLK_NOC_MUX                    18
+#define CLK_NOC_DIV                    19
+#define CLK_AHB                                20
+#define CLK_APB                                21
+#define CLK_DMAC                       22
+
+/* peripheral device clock */
+#define CLK_GPIO                       23
+
+#define CLK_BISP                       24
+#define CLK_CSI0                       25
+#define CLK_CSI1                       26
+
+#define CLK_DE0                                27
+#define CLK_DE1                                28
+#define CLK_DE2                                29
+#define CLK_DE3                                30
+#define CLK_DSI                                32
+
+#define CLK_GPU                                33
+#define CLK_GPU_CORE                   34
+#define CLK_GPU_MEM                    35
+#define CLK_GPU_SYS                    36
+
+#define CLK_HDE                                37
+#define CLK_I2C0                       38
+#define CLK_I2C1                       39
+#define CLK_I2C2                       40
+#define CLK_I2C3                       41
+#define CLK_I2C4                       42
+#define CLK_I2C5                       43
+#define CLK_I2SRX                      44
+#define CLK_I2STX                      45
+#define CLK_IMX                                46
+#define CLK_LCD                                47
+#define CLK_NAND0                      48
+#define CLK_NAND1                      49
+#define CLK_PWM0                       50
+#define CLK_PWM1                       51
+#define CLK_PWM2                       52
+#define CLK_PWM3                       53
+#define CLK_PWM4                       54
+#define CLK_PWM5                       55
+#define CLK_SD0                                56
+#define CLK_SD1                                57
+#define CLK_SD2                                58
+#define CLK_SD3                                59
+#define CLK_SENSOR                     60
+#define CLK_SPEED_SENSOR               61
+#define CLK_SPI0                       62
+#define CLK_SPI1                       63
+#define CLK_SPI2                       64
+#define CLK_SPI3                       65
+#define CLK_THERMAL_SENSOR             66
+#define CLK_UART0                      67
+#define CLK_UART1                      68
+#define CLK_UART2                      69
+#define CLK_UART3                      70
+#define CLK_UART4                      71
+#define CLK_UART5                      72
+#define CLK_UART6                      73
+#define CLK_VCE                                74
+#define CLK_VDE                                75
+
+#define CLK_USB3_480MPLL0              76
+#define CLK_USB3_480MPHY0              77
+#define CLK_USB3_5GPHY                 78
+#define CLK_USB3_CCE                   79
+#define CLK_USB3_MAC                   80
+
+#define CLK_TIMER                      83
+
+#define CLK_HDMI_AUDIO                 84
+
+#define CLK_24M                                85
+
+#define CLK_EDP                                86
+
+#define CLK_24M_EDP                    87
+#define CLK_EDP_PLL                    88
+#define CLK_EDP_LINK                   89
+
+#define CLK_USB2H0_PLLEN               90
+#define CLK_USB2H0_PHY                 91
+#define CLK_USB2H0_CCE                 92
+#define CLK_USB2H1_PLLEN               93
+#define CLK_USB2H1_PHY                 94
+#define CLK_USB2H1_CCE                 95
+
+#define CLK_DDR0                       96
+#define CLK_DDR1                       97
+#define CLK_DMM                                98
+
+#define CLK_ETH_MAC                    99
+#define CLK_RMII_REF                   100
+
+#define CLK_NR_CLKS                    (CLK_RMII_REF + 1)
+
+#endif /* __DT_BINDINGS_CLOCK_S900_CMU_H */

diff --git a/include/dt-bindings/clock/s900_cmu.h b/include/dt-bindings/clock/s900_cmu.h
deleted file mode 100644 (file)
index 2685a6d..0000000
--- a/include/dt-bindings/clock/s900_cmu.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2015 Actions Semi Co., Ltd.
- * Copyright (C) 2018 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
- *
- */
-
-#ifndef _DT_BINDINGS_CLOCK_S900_CMU_H_
-#define _DT_BINDINGS_CLOCK_S900_CMU_H_
-
-/* Module Clock ID */
-#define CLOCK_DDRCH1                           0
-#define CLOCK_DMAC                             1
-#define CLOCK_DDRCH0                           2
-#define CLOCK_BROM                             3
-#define CLOCK_NANDC0                           4
-#define CLOCK_SD0                              5
-#define CLOCK_SD1                              6
-#define CLOCK_SD2                              7
-#define CLOCK_DE                               8
-#define CLOCK_LVDS                             9
-#define CLOCK_EDP                              10
-#define CLOCK_NANDC1                           11
-#define CLOCK_DSI                              12
-#define CLOCK_CSI0                             13
-#define CLOCK_BISP                             14
-#define CLOCK_CSI1                             15
-#define CLOCK_SD3                              16
-#define CLOCK_I2C4                             17
-#define CLOCK_GPIO                             18
-#define CLOCK_DMM                              19
-#define CLOCK_I2STX                            20
-#define CLOCK_I2SRX                            21
-#define CLOCK_HDMIA                            22
-#define CLOCK_SPDIF                            23
-#define CLOCK_PCM0                             24
-#define CLOCK_VDE                              25
-#define CLOCK_VCE                              26
-#define CLOCK_HDE                              27
-#define CLOCK_SHARESRAM                                28
-#define CLOCK_CMU_DDR1                         29
-#define CLOCK_GPU3D                            30
-#define CLOCK_CMUDDR0                          31
-#define CLOCK_SPEED                            32
-#define CLOCK_I2C5                             33
-#define CLOCK_THERMAL                          34
-#define CLOCK_HDMI                             35
-#define CLOCK_PWM4                             36
-#define CLOCK_PWM5                             37
-#define CLOCK_UART0                            38
-#define CLOCK_UART1                            39
-#define CLOCK_UART2                            40
-#define CLOCK_IRC                              41
-#define CLOCK_SPI0                             42
-#define CLOCK_SPI1                             43
-#define CLOCK_SPI2                             44
-#define CLOCK_SPI3                             45
-#define CLOCK_I2C0                             46
-#define CLOCK_I2C1                             47
-#define CLOCK_PCM1                             48
-#define CLOCK_IMX                              49
-#define CLOCK_UART6                            50
-#define CLOCK_UART3                            51
-#define CLOCK_UART4                            52
-#define CLOCK_UART5                            53
-#define CLOCK_ETHERNET                         54
-#define CLOCK_PWM0                             55
-#define CLOCK_PWM1                             56
-#define CLOCK_PWM2                             57
-#define CLOCK_PWM3                             58
-#define CLOCK_TIMER                            59
-#define CLOCK_SE                               60
-#define CLOCK_HDCP2TX                          61
-#define CLOCK_I2C2                             62
-#define CLOCK_I2C3                             63
-
-#endif

diff --git a/include/dt-bindings/reset/actions,s900-reset.h b/include/dt-bindings/reset/actions,s900-reset.h
new file mode 100644 (file)
index 0000000..42c19d0
--- /dev/null
+++ b/include/dt-bindings/reset/actions,s900-reset.h
@@ -0,0 +1,65 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
+//
+// Device Tree binding constants for Actions Semi S900 Reset Management Unit
+//
+// Copyright (c) 2018 Linaro Ltd.
+
+#ifndef __DT_BINDINGS_ACTIONS_S900_RESET_H
+#define __DT_BINDINGS_ACTIONS_S900_RESET_H
+
+#define RESET_CHIPID                           0
+#define RESET_CPU_SCNT                         1
+#define RESET_SRAMI                            2
+#define RESET_DDR_CTL_PHY                      3
+#define RESET_DMAC                             4
+#define RESET_GPIO                             5
+#define RESET_BISP_AXI                         6
+#define RESET_CSI0                             7
+#define RESET_CSI1                             8
+#define RESET_DE                               9
+#define RESET_DSI                              10
+#define RESET_GPU3D_PA                         11
+#define RESET_GPU3D_PB                         12
+#define RESET_HDE                              13
+#define RESET_I2C0                             14
+#define RESET_I2C1                             15
+#define RESET_I2C2                             16
+#define RESET_I2C3                             17
+#define RESET_I2C4                             18
+#define RESET_I2C5                             19
+#define RESET_IMX                              20
+#define RESET_NANDC0                           21
+#define RESET_NANDC1                           22
+#define RESET_SD0                              23
+#define RESET_SD1                              24
+#define RESET_SD2                              25
+#define RESET_SD3                              26
+#define RESET_SPI0                             27
+#define RESET_SPI1                             28
+#define RESET_SPI2                             29
+#define RESET_SPI3                             30
+#define RESET_UART0                            31
+#define RESET_UART1                            32
+#define RESET_UART2                            33
+#define RESET_UART3                            34
+#define RESET_UART4                            35
+#define RESET_UART5                            36
+#define RESET_UART6                            37
+#define RESET_HDMI                             38
+#define RESET_LVDS                             39
+#define RESET_EDP                              40
+#define RESET_USB2HUB                          41
+#define RESET_USB2HSIC                         42
+#define RESET_USB3                             43
+#define RESET_PCM1                             44
+#define RESET_AUDIO                            45
+#define RESET_PCM0                             46
+#define RESET_SE                               47
+#define RESET_GIC                              48
+#define RESET_DDR_CTL_PHY_AXI                  49
+#define RESET_CMU_DDR                          50
+#define RESET_DMM                              51
+#define RESET_HDCP2TX                          52
+#define RESET_ETHERNET                         53
+
+#endif /* __DT_BINDINGS_ACTIONS_S900_RESET_H */