wait_bit: use wait_for_bit_le32 and remove wait_for_bit

wait_for_bit callers use the 32 bit LE version

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>

diff --git a/arch/arm/mach-imx/mx6/ddr.c b/arch/arm/mach-imx/mx6/ddr.c
index 52a9a259040075b24aacd704197d463feef4ad0b..f07f938c651e8959126c368485c43bfb9fd7f41c 100644 (file)
--- a/arch/arm/mach-imx/mx6/ddr.c
+++ b/arch/arm/mach-imx/mx6/ddr.c
@@ -21,10 +21,10 @@ static void reset_read_data_fifos(void)
 
        /* Reset data FIFOs twice. */
        setbits_le32(&mmdc0->mpdgctrl0, 1 << 31);
-       wait_for_bit("MMDC", &mmdc0->mpdgctrl0, 1 << 31, 0, 100, 0);
+       wait_for_bit_le32(&mmdc0->mpdgctrl0, 1 << 31, 0, 100, 0);
 
        setbits_le32(&mmdc0->mpdgctrl0, 1 << 31);
-       wait_for_bit("MMDC", &mmdc0->mpdgctrl0, 1 << 31, 0, 100, 0);
+       wait_for_bit_le32(&mmdc0->mpdgctrl0, 1 << 31, 0, 100, 0);
 }
 
 static void precharge_all(const bool cs0_enable, const bool cs1_enable)
@@ -39,12 +39,12 @@ static void precharge_all(const bool cs0_enable, const bool cs1_enable)
         */
        if (cs0_enable) { /* CS0 */
                writel(0x04008050, &mmdc0->mdscr);
-               wait_for_bit("MMDC", &mmdc0->mdscr, 1 << 14, 1, 100, 0);
+               wait_for_bit_le32(&mmdc0->mdscr, 1 << 14, 1, 100, 0);
        }
 
        if (cs1_enable) { /* CS1 */
                writel(0x04008058, &mmdc0->mdscr);
-               wait_for_bit("MMDC", &mmdc0->mdscr, 1 << 14, 1, 100, 0);
+               wait_for_bit_le32(&mmdc0->mdscr, 1 << 14, 1, 100, 0);
        }
 }
 
@@ -146,7 +146,7 @@ int mmdc_do_write_level_calibration(struct mx6_ddr_sysinfo const *sysinfo)
         * 7. Upon completion of this process the MMDC de-asserts
         * the MPWLGCR[HW_WL_EN]
         */
-       wait_for_bit("MMDC", &mmdc0->mpwlgcr, 1 << 0, 0, 100, 0);
+       wait_for_bit_le32(&mmdc0->mpwlgcr, 1 << 0, 0, 100, 0);
 
        /*
         * 8. check for any errors: check both PHYs for x64 configuration,
@@ -278,7 +278,7 @@ int mmdc_do_dqs_calibration(struct mx6_ddr_sysinfo const *sysinfo)
                writel(0x00008028, &mmdc0->mdscr);
 
        /* poll to make sure the con_ack bit was asserted */
-       wait_for_bit("MMDC", &mmdc0->mdscr, 1 << 14, 1, 100, 0);
+       wait_for_bit_le32(&mmdc0->mdscr, 1 << 14, 1, 100, 0);
 
        /*
         * Check MDMISC register CALIB_PER_CS to see which CS calibration
@@ -312,7 +312,7 @@ int mmdc_do_dqs_calibration(struct mx6_ddr_sysinfo const *sysinfo)
         * this bit until it clears to indicate completion of the write access.
         */
        setbits_le32(&mmdc0->mpswdar0, 1);
-       wait_for_bit("MMDC", &mmdc0->mpswdar0, 1 << 0, 0, 100, 0);
+       wait_for_bit_le32(&mmdc0->mpswdar0, 1 << 0, 0, 100, 0);
 
        /* Set the RD_DL_ABS# bits to their default values
         * (will be calibrated later in the read delay-line calibration).
@@ -359,7 +359,7 @@ int mmdc_do_dqs_calibration(struct mx6_ddr_sysinfo const *sysinfo)
        setbits_le32(&mmdc0->mpdgctrl0, 5 << 28);
 
        /* Poll for completion.  MPDGCTRL0[HW_DG_EN] should be 0 */
-       wait_for_bit("MMDC", &mmdc0->mpdgctrl0, 1 << 28, 0, 100, 0);
+       wait_for_bit_le32(&mmdc0->mpdgctrl0, 1 << 28, 0, 100, 0);
 
        /*
         * Check to see if any errors were encountered during calibration
@@ -423,7 +423,7 @@ int mmdc_do_dqs_calibration(struct mx6_ddr_sysinfo const *sysinfo)
         * setting MPRDDLHWCTL[HW_RD_DL_EN] = 0.   Also, ensure that
         * no error bits were set.
         */
-       wait_for_bit("MMDC", &mmdc0->mprddlhwctl, 1 << 4, 0, 100, 0);
+       wait_for_bit_le32(&mmdc0->mprddlhwctl, 1 << 4, 0, 100, 0);
 
        /* check both PHYs for x64 configuration, if x32, check only PHY0 */
        if (readl(&mmdc0->mprddlhwctl) & 0x0000000f)
@@ -477,7 +477,7 @@ int mmdc_do_dqs_calibration(struct mx6_ddr_sysinfo const *sysinfo)
         * by setting MPWRDLHWCTL[HW_WR_DL_EN] = 0.
         * Also, ensure that no error bits were set.
         */
-       wait_for_bit("MMDC", &mmdc0->mpwrdlhwctl, 1 << 4, 0, 100, 0);
+       wait_for_bit_le32(&mmdc0->mpwrdlhwctl, 1 << 4, 0, 100, 0);
 
        /* Check both PHYs for x64 configuration, if x32, check only PHY0 */
        if (readl(&mmdc0->mpwrdlhwctl) & 0x0000000f)
@@ -526,7 +526,7 @@ int mmdc_do_dqs_calibration(struct mx6_ddr_sysinfo const *sysinfo)
        writel(0x0, &mmdc0->mdscr);     /* CS0 */
 
        /* Poll to make sure the con_ack bit is clear */
-       wait_for_bit("MMDC", &mmdc0->mdscr, 1 << 14, 0, 100, 0);
+       wait_for_bit_le32(&mmdc0->mdscr, 1 << 14, 0, 100, 0);
 
        /*
         * Print out the registers that were updated as a result

diff --git a/arch/arm/mach-socfpga/clock_manager.c b/arch/arm/mach-socfpga/clock_manager.c
index cb6ae036961d690de910f4e7a1b5b8db62b0bbc6..c740c9f648d2165a0f96a02f4e577dac10ed41ca 100644 (file)
--- a/arch/arm/mach-socfpga/clock_manager.c
+++ b/arch/arm/mach-socfpga/clock_manager.c
@@ -37,8 +37,8 @@ void cm_wait_for_lock(u32 mask)
 /* function to poll in the fsm busy bit */
 int cm_wait_for_fsm(void)
 {
-       return wait_for_bit(__func__, (const u32 *)&clock_manager_base->stat,
-                           CLKMGR_STAT_BUSY, false, 20000, false);
+       return wait_for_bit_le32(&clock_manager_base->stat,
+                                CLKMGR_STAT_BUSY, false, 20000, false);
 }
 
 int set_cpu_clk_info(void)

diff --git a/arch/arm/mach-socfpga/clock_manager_gen5.c b/arch/arm/mach-socfpga/clock_manager_gen5.c
index 31fd51097a938732ca222a16c86a017a2a2f3fcb..a23f3fc5d01fec3f0f141d521ab19a7b932004e4 100644 (file)
--- a/arch/arm/mach-socfpga/clock_manager_gen5.c
+++ b/arch/arm/mach-socfpga/clock_manager_gen5.c
@@ -37,15 +37,13 @@ static int cm_write_with_phase(u32 value, u32 reg_address, u32 mask)
        int ret;
 
        /* poll until phase is zero */
-       ret = wait_for_bit(__func__, (const u32 *)reg_address, mask,
-                          false, 20000, false);
+       ret = wait_for_bit_le32(reg_address, mask, false, 20000, false);
        if (ret)
                return ret;
 
        writel(value, reg_address);
 
-       return wait_for_bit(__func__, (const u32 *)reg_address, mask,
-                           false, 20000, false);
+       return wait_for_bit_le32(reg_address, mask, false, 20000, false);
 }
 
 /*

diff --git a/arch/arm/mach-socfpga/reset_manager_arria10.c b/arch/arm/mach-socfpga/reset_manager_arria10.c
index ae16897494bdcb6429abd1085bac32a2b7c26af7..54f0ddb2558e23004b32dc68923b3befee128e96 100644 (file)
--- a/arch/arm/mach-socfpga/reset_manager_arria10.c
+++ b/arch/arm/mach-socfpga/reset_manager_arria10.c
@@ -222,8 +222,8 @@ int socfpga_reset_deassert_bridges_handoff(void)
        clrbits_le32(&reset_manager_base->brgmodrst, mask_rstmgr);
 
        /* Poll until all idleack to 0, timeout at 1000ms */
-       return wait_for_bit(__func__, &sysmgr_regs->noc_idleack, mask_noc,
-                           false, 1000, false);
+       return wait_for_bit_le32(&sysmgr_regs->noc_idleack, mask_noc,
+                                false, 1000, false);
 }
 
 void socfpga_reset_assert_fpga_connected_peripherals(void)
@@ -343,26 +343,26 @@ int socfpga_bridges_reset(void)
        writel(ALT_SYSMGR_NOC_TMO_EN_SET_MSK, &sysmgr_regs->noc_timeout);
 
        /* Poll until all idleack to 1 */
-       ret = wait_for_bit(__func__, &sysmgr_regs->noc_idleack,
-                    ALT_SYSMGR_NOC_H2F_SET_MSK |
-                    ALT_SYSMGR_NOC_LWH2F_SET_MSK |
-                    ALT_SYSMGR_NOC_F2H_SET_MSK |
-                    ALT_SYSMGR_NOC_F2SDR0_SET_MSK |
-                    ALT_SYSMGR_NOC_F2SDR1_SET_MSK |
-                    ALT_SYSMGR_NOC_F2SDR2_SET_MSK,
-                    true, 10000, false);
+       ret = wait_for_bit_le32(&sysmgr_regs->noc_idleack,
+                               ALT_SYSMGR_NOC_H2F_SET_MSK |
+                               ALT_SYSMGR_NOC_LWH2F_SET_MSK |
+                               ALT_SYSMGR_NOC_F2H_SET_MSK |
+                               ALT_SYSMGR_NOC_F2SDR0_SET_MSK |
+                               ALT_SYSMGR_NOC_F2SDR1_SET_MSK |
+                               ALT_SYSMGR_NOC_F2SDR2_SET_MSK,
+                               true, 10000, false);
        if (ret)
                return ret;
 
        /* Poll until all idlestatus to 1 */
-       ret = wait_for_bit(__func__, &sysmgr_regs->noc_idlestatus,
-                    ALT_SYSMGR_NOC_H2F_SET_MSK |
-                    ALT_SYSMGR_NOC_LWH2F_SET_MSK |
-                    ALT_SYSMGR_NOC_F2H_SET_MSK |
-                    ALT_SYSMGR_NOC_F2SDR0_SET_MSK |
-                    ALT_SYSMGR_NOC_F2SDR1_SET_MSK |
-                    ALT_SYSMGR_NOC_F2SDR2_SET_MSK,
-                    true, 10000, false);
+       ret = wait_for_bit_le32(&sysmgr_regs->noc_idlestatus,
+                               ALT_SYSMGR_NOC_H2F_SET_MSK |
+                               ALT_SYSMGR_NOC_LWH2F_SET_MSK |
+                               ALT_SYSMGR_NOC_F2H_SET_MSK |
+                               ALT_SYSMGR_NOC_F2SDR0_SET_MSK |
+                               ALT_SYSMGR_NOC_F2SDR1_SET_MSK |
+                               ALT_SYSMGR_NOC_F2SDR2_SET_MSK,
+                               true, 10000, false);
        if (ret)
                return ret;
 

diff --git a/arch/mips/mach-ath79/ar934x/clk.c b/arch/mips/mach-ath79/ar934x/clk.c
index 9b41d3de60b615bb3a88f823d8bca1f76052791c..ba2243c9be9c2a97e6919dee70c44ca38aed85e1 100644 (file)
--- a/arch/mips/mach-ath79/ar934x/clk.c
+++ b/arch/mips/mach-ath79/ar934x/clk.c
@@ -90,7 +90,7 @@ static void ar934x_srif_pll_cfg(void __iomem *pll_reg_base, const u32 srif_val)
                setbits_be32(pll_reg_base + 0x8, BIT(30));
                udelay(5);
 
-               wait_for_bit("clk", pll_reg_base + 0xc, BIT(3), 1, 10, 0);
+               wait_for_bit_le32(pll_reg_base + 0xc, BIT(3), 1, 10, 0);
 
                clrbits_be32(pll_reg_base + 0x8, BIT(30));
                udelay(5);

diff --git a/board/samtec/vining_2000/vining_2000.c b/board/samtec/vining_2000/vining_2000.c
index af1a3e75cb508c672c6d5d478948c94943327ffc..cced08b8b857a0b1ccd596f6739122988172c62b 100644 (file)
--- a/board/samtec/vining_2000/vining_2000.c
+++ b/board/samtec/vining_2000/vining_2000.c
@@ -378,7 +378,7 @@ static int read_adc(u32 *val)
 
        /* start auto calibration */
        setbits_le32(b + ADCx_GC, ADCx_GC_CAL);
-       ret = wait_for_bit("ADC", b + ADCx_GC, ADCx_GC_CAL, ADCx_GC_CAL, 10, 0);
+       ret = wait_for_bit_le32(b + ADCx_GC, ADCx_GC_CAL, ADCx_GC_CAL, 10, 0);
        if (ret)
                goto adc_exit;
 
@@ -386,7 +386,7 @@ static int read_adc(u32 *val)
        writel(0, b + ADCx_HC0);
 
        /* wait for conversion */
-       ret = wait_for_bit("ADC", b + ADCx_HS, ADCx_HS_C0, ADCx_HS_C0, 10, 0);
+       ret = wait_for_bit_le32(b + ADCx_HS, ADCx_HS_C0, ADCx_HS_C0, 10, 0);
        if (ret)
                goto adc_exit;
 

diff --git a/drivers/clk/clk_pic32.c b/drivers/clk/clk_pic32.c
index f6eef314ec312d0fb726c52426bb381018fe891a..177803943d9dc8537b64e7a02ef0f33386644bba 100644 (file)
--- a/drivers/clk/clk_pic32.c
+++ b/drivers/clk/clk_pic32.c
@@ -197,8 +197,8 @@ static ulong pic32_set_refclk(struct pic32_clk_priv *priv, int periph,
        writel(REFO_ON | REFO_OE, reg + _CLR_OFFSET);
 
        /* wait till previous src change is active */
-       wait_for_bit(__func__, reg, REFO_DIVSW_EN | REFO_ACTIVE,
-                    false, CONFIG_SYS_HZ, false);
+       wait_for_bit_le32(reg, REFO_DIVSW_EN | REFO_ACTIVE,
+                         false, CONFIG_SYS_HZ, false);
 
        /* parent_id */
        v = readl(reg);
@@ -223,8 +223,8 @@ static ulong pic32_set_refclk(struct pic32_clk_priv *priv, int periph,
        writel(REFO_DIVSW_EN, reg + _SET_OFFSET);
 
        /* wait for divider switching to complete */
-       return wait_for_bit(__func__, reg, REFO_DIVSW_EN, false,
-                           CONFIG_SYS_HZ, false);
+       return wait_for_bit_le32(reg, REFO_DIVSW_EN, false,
+                                CONFIG_SYS_HZ, false);
 }
 
 static ulong pic32_get_refclk(struct pic32_clk_priv *priv, int periph)
@@ -311,8 +311,8 @@ static int pic32_mpll_init(struct pic32_clk_priv *priv)
 
        /* Wait for ready */
        mask = MPLL_RDY | MPLL_VREG_RDY;
-       return wait_for_bit(__func__, priv->syscfg_base + CFGMPLL, mask,
-                           true, get_tbclk(), false);
+       return wait_for_bit_le32(priv->syscfg_base + CFGMPLL, mask,
+                                true, get_tbclk(), false);
 }
 
 static void pic32_clk_init(struct udevice *dev)

diff --git a/drivers/clk/renesas/clk-rcar-gen3.c b/drivers/clk/renesas/clk-rcar-gen3.c
index b26bbcc59fb7317e256638f1c8446117574fe5f9..22828fd4702bfed703060bedf0bb122789cacd0f 100644 (file)
--- a/drivers/clk/renesas/clk-rcar-gen3.c
+++ b/drivers/clk/renesas/clk-rcar-gen3.c
@@ -1046,8 +1046,8 @@ static int gen3_clk_endisable(struct clk *clk, bool enable)
                if (ret)
                        return ret;
                clrbits_le32(priv->base + SMSTPCR(reg), bitmask);
-               return wait_for_bit("MSTP", priv->base + MSTPSR(reg),
-                                   bitmask, 0, 100, 0);
+               return wait_for_bit_le32(priv->base + MSTPSR(reg),
+                                        bitmask, 0, 100, 0);
        } else {
                setbits_le32(priv->base + SMSTPCR(reg), bitmask);
                return 0;

diff --git a/drivers/ddr/microchip/ddr2.c b/drivers/ddr/microchip/ddr2.c
index 6056418588cdfd23d700fb4f0f3b390da75a9b74..a52427c3d6182845b4e509436e6e3efd3f89e52e 100644 (file)
--- a/drivers/ddr/microchip/ddr2.c
+++ b/drivers/ddr/microchip/ddr2.c
@@ -57,8 +57,8 @@ static int ddr2_phy_calib_start(void)
        writel(SCL_START | SCL_EN, &ddr2_phy->scl_start);
 
        /* Wait for SCL for data byte to pass */
-       return wait_for_bit(__func__, &ddr2_phy->scl_start, SCL_LUBPASS,
-                           true, CONFIG_SYS_HZ, false);
+       return wait_for_bit_le32(&ddr2_phy->scl_start, SCL_LUBPASS,
+                                true, CONFIG_SYS_HZ, false);
 }
 
 /* DDR2 Controller initialization */
@@ -256,8 +256,8 @@ void ddr2_ctrl_init(void)
        writel(INIT_START, &ctrl->memcon);
 
        /* wait for all host cmds to be transmitted */
-       wait_for_bit(__func__, &ctrl->cmdissue, CMD_VALID, false,
-                    CONFIG_SYS_HZ, false);
+       wait_for_bit_le32(&ctrl->cmdissue, CMD_VALID, false,
+                         CONFIG_SYS_HZ, false);
 
        /* inform all cmds issued, ready for normal operation */
        writel(INIT_START | INIT_DONE, &ctrl->memcon);

diff --git a/drivers/fpga/socfpga_arria10.c b/drivers/fpga/socfpga_arria10.c
index 5c1a68a00995c33054cdbaaa9d64c9a1c99346be..d5763965ddc2e12e835734b4e145a1c47174c177 100644 (file)
--- a/drivers/fpga/socfpga_arria10.c
+++ b/drivers/fpga/socfpga_arria10.c
@@ -62,8 +62,7 @@ int is_fpgamgr_user_mode(void)
 
 static int wait_for_user_mode(void)
 {
-       return wait_for_bit(__func__,
-               &fpga_manager_base->imgcfg_stat,
+       return wait_for_bit_le32(&fpga_manager_base->imgcfg_stat,
                ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK,
                1, FPGA_TIMEOUT_MSEC, false);
 }
@@ -115,19 +114,17 @@ static int wait_for_nconfig_pin_and_nstatus_pin(void)
        /* Poll until f2s_nconfig_pin and f2s_nstatus_pin; loop until de-asserted,
         * timeout at 1000ms
         */
-       return wait_for_bit(__func__,
-                           &fpga_manager_base->imgcfg_stat,
-                           mask,
-                           false, FPGA_TIMEOUT_MSEC, false);
+       return wait_for_bit_le32(&fpga_manager_base->imgcfg_stat,
+               mask,
+               false, FPGA_TIMEOUT_MSEC, false);
 }
 
 static int wait_for_f2s_nstatus_pin(unsigned long value)
 {
        /* Poll until f2s to specific value, timeout at 1000ms */
-       return wait_for_bit(__func__,
-                           &fpga_manager_base->imgcfg_stat,
-                           ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK,
-                           value, FPGA_TIMEOUT_MSEC, false);
+       return wait_for_bit_le32(&fpga_manager_base->imgcfg_stat,
+               ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK,
+               value, FPGA_TIMEOUT_MSEC, false);
 }
 
 /* set CD ratio */

diff --git a/drivers/mmc/msm_sdhci.c b/drivers/mmc/msm_sdhci.c
index 9117ab6bf9ca2528b1fa46db8c87828e06f9b238..f0661bd96c31a04bf041e2d4ee164bb5a31fbfa9 100644 (file)
--- a/drivers/mmc/msm_sdhci.c
+++ b/drivers/mmc/msm_sdhci.c
@@ -109,15 +109,15 @@ static int msm_sdc_probe(struct udevice *dev)
 
 
        /* Wait for reset to be written to register */
-       if (wait_for_bit(__func__, prv->base + SDCC_MCI_STATUS2,
-                        SDCC_MCI_STATUS2_MCI_ACT, false, 10, false)) {
+       if (wait_for_bit_le32(prv->base + SDCC_MCI_STATUS2,
+                             SDCC_MCI_STATUS2_MCI_ACT, false, 10, false)) {
                printf("msm_sdhci: reset request failed\n");
                return -EIO;
        }
 
        /* SW reset can take upto 10HCLK + 15MCLK cycles. (min 40us) */
-       if (wait_for_bit(__func__, prv->base + SDCC_MCI_POWER,
-                        SDCC_MCI_POWER_SW_RST, false, 2, false)) {
+       if (wait_for_bit_le32(prv->base + SDCC_MCI_POWER,
+                             SDCC_MCI_POWER_SW_RST, false, 2, false)) {
                printf("msm_sdhci: stuck in reset\n");
                return -ETIMEDOUT;
        }

diff --git a/drivers/mtd/pic32_flash.c b/drivers/mtd/pic32_flash.c
index e1a8d3bc4b407d2f8543b95ba52a76a8414fb548..8bbf2fa9a2b2b5dfaa26a37d4270c4043db2d38c 100644 (file)
--- a/drivers/mtd/pic32_flash.c
+++ b/drivers/mtd/pic32_flash.c
@@ -66,8 +66,8 @@ static inline void flash_initiate_operation(u32 nvmop)
 
 static int flash_wait_till_busy(const char *func, ulong timeout)
 {
-       int ret = wait_for_bit(__func__, &nvm_regs_p->ctrl.raw,
-                              NVM_WR, false, timeout, false);
+       int ret = wait_for_bit_le32(&nvm_regs_p->ctrl.raw,
+                                   NVM_WR, false, timeout, false);
 
        return ret ? ERR_TIMOUT : ERR_OK;
 }

diff --git a/drivers/net/ag7xxx.c b/drivers/net/ag7xxx.c
index 00e6806892ad2e418de6939a2db9180f6cd1777a..f28187058e88fa1dc0997c4d3ccc3e8c858ed977 100644 (file)
--- a/drivers/net/ag7xxx.c
+++ b/drivers/net/ag7xxx.c
@@ -164,8 +164,8 @@ static int ag7xxx_switch_read(struct mii_dev *bus, int addr, int reg, u16 *val)
        writel(AG7XXX_ETH_MII_MGMT_CMD_READ,
               regs + AG7XXX_ETH_MII_MGMT_CMD);
 
-       ret = wait_for_bit("ag7xxx", regs + AG7XXX_ETH_MII_MGMT_IND,
-                          AG7XXX_ETH_MII_MGMT_IND_BUSY, 0, 1000, 0);
+       ret = wait_for_bit_le32(regs + AG7XXX_ETH_MII_MGMT_IND,
+                               AG7XXX_ETH_MII_MGMT_IND_BUSY, 0, 1000, 0);
        if (ret)
                return ret;
 
@@ -185,8 +185,8 @@ static int ag7xxx_switch_write(struct mii_dev *bus, int addr, int reg, u16 val)
               regs + AG7XXX_ETH_MII_MGMT_ADDRESS);
        writel(val, regs + AG7XXX_ETH_MII_MGMT_CTRL);
 
-       ret = wait_for_bit("ag7xxx", regs + AG7XXX_ETH_MII_MGMT_IND,
-                          AG7XXX_ETH_MII_MGMT_IND_BUSY, 0, 1000, 0);
+       ret = wait_for_bit_le32(regs + AG7XXX_ETH_MII_MGMT_IND,
+                               AG7XXX_ETH_MII_MGMT_IND_BUSY, 0, 1000, 0);
 
        return ret;
 }
@@ -510,13 +510,13 @@ static void ag7xxx_eth_stop(struct udevice *dev)
 
        /* Stop the TX DMA. */
        writel(0, priv->regs + AG7XXX_ETH_DMA_TX_CTRL);
-       wait_for_bit("ag7xxx", priv->regs + AG7XXX_ETH_DMA_TX_CTRL, ~0, 0,
-                    1000, 0);
+       wait_for_bit_le32(priv->regs + AG7XXX_ETH_DMA_TX_CTRL, ~0, 0,
+                         1000, 0);
 
        /* Stop the RX DMA. */
        writel(0, priv->regs + AG7XXX_ETH_DMA_RX_CTRL);
-       wait_for_bit("ag7xxx", priv->regs + AG7XXX_ETH_DMA_RX_CTRL, ~0, 0,
-                    1000, 0);
+       wait_for_bit_le32(priv->regs + AG7XXX_ETH_DMA_RX_CTRL, ~0, 0,
+                         1000, 0);
 }
 
 /*

diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index 00076cffbed2869a96fa33cc85ae60ea38ac64bd..232e8034df935a09e432c6aeea2cbe12bdac935a 100644 (file)
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -361,8 +361,9 @@ static void eqos_flush_buffer(void *buf, size_t size)
 
 static int eqos_mdio_wait_idle(struct eqos_priv *eqos)
 {
-       return wait_for_bit(__func__, &eqos->mac_regs->mdio_address,
-                           EQOS_MAC_MDIO_ADDRESS_GB, false, 1000000, true);
+       return wait_for_bit_le32(&eqos->mac_regs->mdio_address,
+                                EQOS_MAC_MDIO_ADDRESS_GB, false,
+                                1000000, true);
 }
 
 static int eqos_mdio_read(struct mii_dev *bus, int mdio_addr, int mdio_devad,
@@ -588,15 +589,15 @@ static int eqos_calibrate_pads_tegra186(struct udevice *dev)
        setbits_le32(&eqos->tegra186_regs->auto_cal_config,
                     EQOS_AUTO_CAL_CONFIG_START | EQOS_AUTO_CAL_CONFIG_ENABLE);
 
-       ret = wait_for_bit(__func__, &eqos->tegra186_regs->auto_cal_status,
-                          EQOS_AUTO_CAL_STATUS_ACTIVE, true, 10, false);
+       ret = wait_for_bit_le32(&eqos->tegra186_regs->auto_cal_status,
+                               EQOS_AUTO_CAL_STATUS_ACTIVE, true, 10, false);
        if (ret) {
                pr_err("calibrate didn't start");
                goto failed;
        }
 
-       ret = wait_for_bit(__func__, &eqos->tegra186_regs->auto_cal_status,
-                          EQOS_AUTO_CAL_STATUS_ACTIVE, false, 10, false);
+       ret = wait_for_bit_le32(&eqos->tegra186_regs->auto_cal_status,
+                               EQOS_AUTO_CAL_STATUS_ACTIVE, false, 10, false);
        if (ret) {
                pr_err("calibrate didn't finish");
                goto failed;
@@ -862,8 +863,8 @@ static int eqos_start(struct udevice *dev)
 
        eqos->reg_access_ok = true;
 
-       ret = wait_for_bit(__func__, &eqos->dma_regs->mode,
-                          EQOS_DMA_MODE_SWR, false, 10, false);
+       ret = wait_for_bit_le32(&eqos->dma_regs->mode,
+                               EQOS_DMA_MODE_SWR, false, 10, false);
        if (ret) {
                pr_err("EQOS_DMA_MODE_SWR stuck");
                goto err_stop_resets;

diff --git a/drivers/net/ethoc.c b/drivers/net/ethoc.c
index a6df950081762a73184c1ef50ced2ddcd8878186..51a6c97550d0445bea0c94a83db0ed8fc644f936 100644 (file)
--- a/drivers/net/ethoc.c
+++ b/drivers/net/ethoc.c
@@ -548,8 +548,8 @@ static int ethoc_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
        ethoc_write(priv, MIIADDRESS, MIIADDRESS_ADDR(addr, reg));
        ethoc_write(priv, MIICOMMAND, MIICOMMAND_READ);
 
-       rc = wait_for_bit(__func__, ethoc_reg(priv, MIISTATUS),
-                         MIISTATUS_BUSY, false, CONFIG_SYS_HZ, false);
+       rc = wait_for_bit_le32(ethoc_reg(priv, MIISTATUS),
+                              MIISTATUS_BUSY, false, CONFIG_SYS_HZ, false);
 
        if (rc == 0) {
                u32 data = ethoc_read(priv, MIIRX_DATA);
@@ -571,8 +571,8 @@ static int ethoc_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
        ethoc_write(priv, MIITX_DATA, val);
        ethoc_write(priv, MIICOMMAND, MIICOMMAND_WRITE);
 
-       rc = wait_for_bit(__func__, ethoc_reg(priv, MIISTATUS),
-                         MIISTATUS_BUSY, false, CONFIG_SYS_HZ, false);
+       rc = wait_for_bit_le32(ethoc_reg(priv, MIISTATUS),
+                              MIISTATUS_BUSY, false, CONFIG_SYS_HZ, false);
 
        if (rc == 0) {
                /* reset MII command register */

diff --git a/drivers/net/pic32_eth.c b/drivers/net/pic32_eth.c
index 0b89911f04a2b13c433bd5a626c1a0e6fc823a71..7129372790ef29465fb0bd037be0e91227ddcc35 100644 (file)
--- a/drivers/net/pic32_eth.c
+++ b/drivers/net/pic32_eth.c
@@ -64,8 +64,8 @@ static int pic32_mii_init(struct pic32eth_dev *priv)
        writel(ETHCON_ON | ETHCON_TXRTS | ETHCON_RXEN, &ectl_p->con1.clr);
 
        /* wait till busy */
-       wait_for_bit(__func__, &ectl_p->stat.raw, ETHSTAT_BUSY, false,
-                    CONFIG_SYS_HZ, false);
+       wait_for_bit_le32(&ectl_p->stat.raw, ETHSTAT_BUSY, false,
+                         CONFIG_SYS_HZ, false);
 
        /* turn controller ON to access PHY over MII */
        writel(ETHCON_ON, &ectl_p->con1.set);
@@ -239,8 +239,8 @@ static void pic32_ctrl_reset(struct pic32eth_dev *priv)
        writel(ETHCON_ON | ETHCON_TXRTS | ETHCON_RXEN, &ectl_p->con1.clr);
 
        /* wait till busy */
-       wait_for_bit(__func__, &ectl_p->stat.raw, ETHSTAT_BUSY, false,
-                    CONFIG_SYS_HZ, false);
+       wait_for_bit_le32(&ectl_p->stat.raw, ETHSTAT_BUSY, false,
+                         CONFIG_SYS_HZ, false);
        /* decrement received buffcnt to zero. */
        while (readl(&ectl_p->stat.raw) & ETHSTAT_BUFCNT)
                writel(ETHCON_BUFCDEC, &ectl_p->con1.set);
@@ -375,8 +375,8 @@ static void pic32_eth_stop(struct udevice *dev)
        mdelay(10);
 
        /* wait until everything is down */
-       wait_for_bit(__func__, &ectl_p->stat.raw, ETHSTAT_BUSY, false,
-                    2 * CONFIG_SYS_HZ, false);
+       wait_for_bit_le32(&ectl_p->stat.raw, ETHSTAT_BUSY, false,
+                         2 * CONFIG_SYS_HZ, false);
 
        /* clear any existing interrupt event */
        writel(0xffffffff, &ectl_p->irq.clr);

diff --git a/drivers/net/pic32_mdio.c b/drivers/net/pic32_mdio.c
index 578fc969051e1e51e6aa96344dc24b31d565df2f..6ae5c40fa36af741b184a77b326968cbcdcc1984 100644 (file)
--- a/drivers/net/pic32_mdio.c
+++ b/drivers/net/pic32_mdio.c
@@ -22,8 +22,8 @@ static int pic32_mdio_write(struct mii_dev *bus,
        struct pic32_mii_regs *mii_regs = bus->priv;
 
        /* Wait for the previous operation to finish */
-       wait_for_bit(__func__, &mii_regs->mind.raw, MIIMIND_BUSY,
-                    false, CONFIG_SYS_HZ, true);
+       wait_for_bit_le32(&mii_regs->mind.raw, MIIMIND_BUSY,
+                         false, CONFIG_SYS_HZ, true);
 
        /* Put phyaddr and regaddr into MIIMADD */
        v = (addr << MIIMADD_PHYADDR_SHIFT) | (reg & MIIMADD_REGADDR);
@@ -36,8 +36,8 @@ static int pic32_mdio_write(struct mii_dev *bus,
        udelay(12);
 
        /* Wait for write to complete */
-       wait_for_bit(__func__, &mii_regs->mind.raw, MIIMIND_BUSY,
-                    false, CONFIG_SYS_HZ, true);
+       wait_for_bit_le32(&mii_regs->mind.raw, MIIMIND_BUSY,
+                         false, CONFIG_SYS_HZ, true);
 
        return 0;
 }
@@ -48,8 +48,8 @@ static int pic32_mdio_read(struct mii_dev *bus, int addr, int devaddr, int reg)
        struct pic32_mii_regs *mii_regs = bus->priv;
 
        /* Wait for the previous operation to finish */
-       wait_for_bit(__func__, &mii_regs->mind.raw, MIIMIND_BUSY,
-                    false, CONFIG_SYS_HZ, true);
+       wait_for_bit_le32(&mii_regs->mind.raw, MIIMIND_BUSY,
+                         false, CONFIG_SYS_HZ, true);
 
        /* Put phyaddr and regaddr into MIIMADD */
        v = (addr << MIIMADD_PHYADDR_SHIFT) | (reg & MIIMADD_REGADDR);
@@ -62,9 +62,9 @@ static int pic32_mdio_read(struct mii_dev *bus, int addr, int devaddr, int reg)
        udelay(12);
 
        /* Wait for read to complete */
-       wait_for_bit(__func__, &mii_regs->mind.raw,
-                    MIIMIND_NOTVALID | MIIMIND_BUSY,
-                    false, CONFIG_SYS_HZ, false);
+       wait_for_bit_le32(&mii_regs->mind.raw,
+                         MIIMIND_NOTVALID | MIIMIND_BUSY,
+                         false, CONFIG_SYS_HZ, false);
 
        /* Clear the command register */
        writel(0, &mii_regs->mcmd.raw);
@@ -82,22 +82,22 @@ static int pic32_mdio_reset(struct mii_dev *bus)
        writel(MIIMCFG_RSTMGMT, &mii_regs->mcfg.raw);
 
        /* Wait for the operation to finish */
-       wait_for_bit(__func__, &mii_regs->mind.raw, MIIMIND_BUSY,
+       wait_for_bit_le32(&mii_regs->mind.raw, MIIMIND_BUSY,
                     false, CONFIG_SYS_HZ, true);
 
        /* Clear reset bit */
        writel(0, &mii_regs->mcfg);
 
        /* Wait for the operation to finish */
-       wait_for_bit(__func__, &mii_regs->mind.raw, MIIMIND_BUSY,
-                    false, CONFIG_SYS_HZ, true);
+       wait_for_bit_le32(&mii_regs->mind.raw, MIIMIND_BUSY,
+                         false, CONFIG_SYS_HZ, true);
 
        /* Set the MII Management Clock (MDC) - no faster than 2.5 MHz */
        writel(MIIMCFG_CLKSEL_DIV40, &mii_regs->mcfg.raw);
 
        /* Wait for the operation to finish */
-       wait_for_bit(__func__, &mii_regs->mind.raw, MIIMIND_BUSY,
-                    false, CONFIG_SYS_HZ, true);
+       wait_for_bit_le32(&mii_regs->mind.raw, MIIMIND_BUSY,
+                         false, CONFIG_SYS_HZ, true);
        return 0;
 }
 

diff --git a/drivers/net/ravb.c b/drivers/net/ravb.c
index dc743e113dec6f41a69ae6490f17aa5ca41c7708..26bd91529193d8f34a2ff65ababd96dea79f64f8 100644 (file)
--- a/drivers/net/ravb.c
+++ b/drivers/net/ravb.c
@@ -222,8 +222,8 @@ static int ravb_reset(struct udevice *dev)
        writel(CCC_OPC_CONFIG, eth->iobase + RAVB_REG_CCC);
 
        /* Check the operating mode is changed to the config mode. */
-       return wait_for_bit(dev->name, (void *)eth->iobase + RAVB_REG_CSR,
-                           CSR_OPS_CONFIG, true, 100, true);
+       return wait_for_bit_le32(eth->iobase + RAVB_REG_CSR,
+                                CSR_OPS_CONFIG, true, 100, true);
 }
 
 static void ravb_base_desc_init(struct ravb_priv *eth)

diff --git a/drivers/net/xilinx_axi_emac.c b/drivers/net/xilinx_axi_emac.c
index 9a2a578ff9b641e5f9157fae6a2a67d07e6725f7..70a2e95a8ec179cbbf1e597a39b89bb3d2dc33c0 100644 (file)
--- a/drivers/net/xilinx_axi_emac.c
+++ b/drivers/net/xilinx_axi_emac.c
@@ -366,8 +366,8 @@ static int axi_ethernet_init(struct axidma_priv *priv)
         * processor mode and hence bypass in this mode
         */
        if (!priv->eth_hasnobuf) {
-               err = wait_for_bit(__func__, (const u32 *)&regs->is,
-                                  XAE_INT_MGTRDY_MASK, true, 200, false);
+               err = wait_for_bit_le32(&regs->is, XAE_INT_MGTRDY_MASK,
+                                       true, 200, false);
                if (err) {
                        printf("%s: Timeout\n", __func__);
                        return 1;

diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index 1dfd631e1a3c6448e4fd0cbb2e4b1d5640c4a211..2cc49bca922a1f0896a9e6368813df77313b0661 100644 (file)
--- a/drivers/net/zynq_gem.c
+++ b/drivers/net/zynq_gem.c
@@ -192,8 +192,8 @@ static u32 phy_setup_op(struct zynq_gem_priv *priv, u32 phy_addr, u32 regnum,
        struct zynq_gem_regs *regs = priv->iobase;
        int err;
 
-       err = wait_for_bit(__func__, &regs->nwsr, ZYNQ_GEM_NWSR_MDIOIDLE_MASK,
-                           true, 20000, false);
+       err = wait_for_bit_le32(&regs->nwsr, ZYNQ_GEM_NWSR_MDIOIDLE_MASK,
+                               true, 20000, false);
        if (err)
                return err;
 
@@ -205,8 +205,8 @@ static u32 phy_setup_op(struct zynq_gem_priv *priv, u32 phy_addr, u32 regnum,
        /* Write mgtcr and wait for completion */
        writel(mgtcr, &regs->phymntnc);
 
-       err = wait_for_bit(__func__, &regs->nwsr, ZYNQ_GEM_NWSR_MDIOIDLE_MASK,
-                           true, 20000, false);
+       err = wait_for_bit_le32(&regs->nwsr, ZYNQ_GEM_NWSR_MDIOIDLE_MASK,
+                               true, 20000, false);
        if (err)
                return err;
 
@@ -514,8 +514,8 @@ static int zynq_gem_send(struct udevice *dev, void *ptr, int len)
        if (priv->tx_bd->status & ZYNQ_GEM_TXBUF_EXHAUSTED)
                printf("TX buffers exhausted in mid frame\n");
 
-       return wait_for_bit(__func__, &regs->txsr, ZYNQ_GEM_TSR_DONE,
-                           true, 20000, true);
+       return wait_for_bit_le32(&regs->txsr, ZYNQ_GEM_TSR_DONE,
+                                true, 20000, true);
 }
 
 /* Do not check frame_recd flag in rx_status register 0x20 - just poll BD */

diff --git a/drivers/reset/sti-reset.c b/drivers/reset/sti-reset.c
index 17786f976a5f9574626a0ec73ed17ee440ee9edf..0fc5a288026f204086a9cd6d2b30ef1370990b67 100644 (file)
--- a/drivers/reset/sti-reset.c
+++ b/drivers/reset/sti-reset.c
@@ -266,8 +266,8 @@ static int sti_reset_program_hw(struct reset_ctl *reset_ctl, int assert)
                return 0;
 
        reg = (void __iomem *)base + ch->ack_offset;
-       if (wait_for_bit(__func__, reg, BIT(ch->ack_bit), ctrl_val,
-                        1000, false)) {
+       if (wait_for_bit_le32(reg, BIT(ch->ack_bit), ctrl_val,
+                             1000, false)) {
                pr_err("Stuck on waiting ack reset_ctl=%p dev=%p id=%lu\n",
                      reset_ctl, reset_ctl->dev, reset_ctl->id);
 

diff --git a/drivers/serial/serial_pic32.c b/drivers/serial/serial_pic32.c
index b0e01aa0e5c1064afe97a8d9f88d2e9751f37f11..0632d26211d6c8c4ff00e06c338970a52a410149 100644 (file)
--- a/drivers/serial/serial_pic32.c
+++ b/drivers/serial/serial_pic32.c
@@ -51,8 +51,8 @@ static int pic32_serial_init(void __iomem *base, ulong clk, u32 baudrate)
        u32 div = DIV_ROUND_CLOSEST(clk, baudrate * 16);
 
        /* wait for TX FIFO to empty */
-       wait_for_bit(__func__, base + U_STA, UART_TX_EMPTY,
-                    true, CONFIG_SYS_HZ, false);
+       wait_for_bit_le32(base + U_STA, UART_TX_EMPTY,
+                         true, CONFIG_SYS_HZ, false);
 
        /* send break */
        writel(UART_TX_BRK, base + U_STASET);

diff --git a/drivers/spi/atmel_spi.c b/drivers/spi/atmel_spi.c
index 228e714e093374a0494e8fd69cfe85330d92e5c4..8010ab434c082d3b5b5073365e34f298bfd3d5bb 100644 (file)
--- a/drivers/spi/atmel_spi.c
+++ b/drivers/spi/atmel_spi.c
@@ -394,8 +394,8 @@ out:
                 * Wait until the transfer is completely done before
                 * we deactivate CS.
                 */
-               wait_for_bit(__func__, &reg_base->sr,
-                            ATMEL_SPI_SR_TXEMPTY, true, 1000, false);
+               wait_for_bit_le32(&reg_base->sr,
+                                 ATMEL_SPI_SR_TXEMPTY, true, 1000, false);
 
                atmel_spi_cs_deactivate(dev);
        }

diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
index e02f2217f45f55c3c67da247d5b0a1332d026ff9..dca3fdfdeadbc6c95aa0bf41d231694dc8dacd91 100644 (file)
--- a/drivers/spi/cadence_qspi_apb.c
+++ b/drivers/spi/cadence_qspi_apb.c
@@ -675,8 +675,8 @@ int cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat,
        }
 
        /* Check indirect done status */
-       ret = wait_for_bit("QSPI", plat->regbase + CQSPI_REG_INDIRECTRD,
-                          CQSPI_REG_INDIRECTRD_DONE, 1, 10, 0);
+       ret = wait_for_bit_le32(plat->regbase + CQSPI_REG_INDIRECTRD,
+                               CQSPI_REG_INDIRECTRD_DONE, 1, 10, 0);
        if (ret) {
                printf("Indirect read completion error (%i)\n", ret);
                goto failrd;
@@ -762,9 +762,9 @@ int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat,
                                bb_txbuf + rounddown(write_bytes, 4),
                                write_bytes % 4);
 
-               ret = wait_for_bit("QSPI", plat->regbase + CQSPI_REG_SDRAMLEVEL,
-                                  CQSPI_REG_SDRAMLEVEL_WR_MASK <<
-                                  CQSPI_REG_SDRAMLEVEL_WR_LSB, 0, 10, 0);
+               ret = wait_for_bit_le32(plat->regbase + CQSPI_REG_SDRAMLEVEL,
+                                       CQSPI_REG_SDRAMLEVEL_WR_MASK <<
+                                       CQSPI_REG_SDRAMLEVEL_WR_LSB, 0, 10, 0);
                if (ret) {
                        printf("Indirect write timed out (%i)\n", ret);
                        goto failwr;
@@ -775,8 +775,8 @@ int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat,
        }
 
        /* Check indirect done status */
-       ret = wait_for_bit("QSPI", plat->regbase + CQSPI_REG_INDIRECTWR,
-                          CQSPI_REG_INDIRECTWR_DONE, 1, 10, 0);
+       ret = wait_for_bit_le32(plat->regbase + CQSPI_REG_INDIRECTWR,
+                               CQSPI_REG_INDIRECTWR_DONE, 1, 10, 0);
        if (ret) {
                printf("Indirect write completion error (%i)\n", ret);
                goto failwr;

diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
index 0f3f7d97f0137fa7b258358119f8a0459d313a33..eed52c15c8147677b10362d4e44411ce66700067 100644 (file)
--- a/drivers/spi/fsl_qspi.c
+++ b/drivers/spi/fsl_qspi.c
@@ -1011,11 +1011,11 @@ static int fsl_qspi_probe(struct udevice *bus)
        priv->num_chipselect = plat->num_chipselect;
 
        /* make sure controller is not busy anywhere */
-       ret = wait_for_bit(__func__, &priv->regs->sr,
-                          QSPI_SR_BUSY_MASK |
-                          QSPI_SR_AHB_ACC_MASK |
-                          QSPI_SR_IP_ACC_MASK,
-                          false, 100, false);
+       ret = wait_for_bit_le32(&priv->regs->sr,
+                               QSPI_SR_BUSY_MASK |
+                               QSPI_SR_AHB_ACC_MASK |
+                               QSPI_SR_IP_ACC_MASK,
+                               false, 100, false);
 
        if (ret) {
                debug("ERROR : The controller is busy\n");
@@ -1173,11 +1173,11 @@ static int fsl_qspi_claim_bus(struct udevice *dev)
        priv = dev_get_priv(bus);
 
        /* make sure controller is not busy anywhere */
-       ret = wait_for_bit(__func__, &priv->regs->sr,
-                          QSPI_SR_BUSY_MASK |
-                          QSPI_SR_AHB_ACC_MASK |
-                          QSPI_SR_IP_ACC_MASK,
-                          false, 100, false);
+       ret = wait_for_bit_le32(&priv->regs->sr,
+                               QSPI_SR_BUSY_MASK |
+                               QSPI_SR_AHB_ACC_MASK |
+                               QSPI_SR_IP_ACC_MASK,
+                               false, 100, false);
 
        if (ret) {
                debug("ERROR : The controller is busy\n");

diff --git a/drivers/spi/mvebu_a3700_spi.c b/drivers/spi/mvebu_a3700_spi.c
index ec4907391ca920a3f1ab45e78bd279d816008e4c..d1708a8d56c8a18564efaaff87905d9abd93218c 100644 (file)
--- a/drivers/spi/mvebu_a3700_spi.c
+++ b/drivers/spi/mvebu_a3700_spi.c
@@ -95,8 +95,9 @@ static int spi_legacy_shift_byte(struct spi_reg *reg, unsigned int bytelen,
        din_8 = din;
 
        while (bytelen) {
-               ret = wait_for_bit(__func__, &reg->ctrl,
-                                  MVEBU_SPI_A3700_XFER_RDY, true, 100, false);
+               ret = wait_for_bit_le32(&reg->ctrl,
+                                       MVEBU_SPI_A3700_XFER_RDY,
+                                       true,100, false);
                if (ret)
                        return ret;
 
@@ -109,9 +110,9 @@ static int spi_legacy_shift_byte(struct spi_reg *reg, unsigned int bytelen,
                writel(pending_dout, &reg->dout);
 
                if (din) {
-                       ret = wait_for_bit(__func__, &reg->ctrl,
-                                          MVEBU_SPI_A3700_XFER_RDY,
-                                          true, 100, false);
+                       ret = wait_for_bit_le32(&reg->ctrl,
+                                               MVEBU_SPI_A3700_XFER_RDY,
+                                               true, 100, false);
                        if (ret)
                                return ret;
 
@@ -160,8 +161,9 @@ static int mvebu_spi_xfer(struct udevice *dev, unsigned int bitlen,
 
        /* Deactivate CS */
        if (flags & SPI_XFER_END) {
-               ret = wait_for_bit(__func__, &reg->ctrl,
-                                  MVEBU_SPI_A3700_XFER_RDY, true, 100, false);
+               ret = wait_for_bit_le32(&reg->ctrl,
+                                       MVEBU_SPI_A3700_XFER_RDY,
+                                       true, 100, false);
                if (ret)
                        return ret;
 
@@ -231,8 +233,8 @@ static int mvebu_spi_probe(struct udevice *bus)
        /* Flush read/write FIFO */
        data = readl(&reg->cfg);
        writel(data | MVEBU_SPI_A3700_FIFO_FLUSH, &reg->cfg);
-       ret = wait_for_bit(__func__, &reg->cfg, MVEBU_SPI_A3700_FIFO_FLUSH,
-                          false, 1000, false);
+       ret = wait_for_bit_le32(&reg->cfg, MVEBU_SPI_A3700_FIFO_FLUSH,
+                               false, 1000, false);
        if (ret)
                return ret;
 

diff --git a/drivers/usb/host/dwc2.c b/drivers/usb/host/dwc2.c
index 1293e18f75e74da33ccdd3dea7bc8c779af02d21..540c016412b37cbbb1b1d0734cf721692f1085e2 100644 (file)
--- a/drivers/usb/host/dwc2.c
+++ b/drivers/usb/host/dwc2.c
@@ -108,8 +108,8 @@ static void dwc_otg_flush_tx_fifo(struct dwc2_core_regs *regs, const int num)
 
        writel(DWC2_GRSTCTL_TXFFLSH | (num << DWC2_GRSTCTL_TXFNUM_OFFSET),
               &regs->grstctl);
-       ret = wait_for_bit(__func__, &regs->grstctl, DWC2_GRSTCTL_TXFFLSH,
-                          false, 1000, false);
+       ret = wait_for_bit_le32(&regs->grstctl, DWC2_GRSTCTL_TXFFLSH,
+                               false, 1000, false);
        if (ret)
                printf("%s: Timeout!\n", __func__);
 
@@ -127,8 +127,8 @@ static void dwc_otg_flush_rx_fifo(struct dwc2_core_regs *regs)
        int ret;
 
        writel(DWC2_GRSTCTL_RXFFLSH, &regs->grstctl);
-       ret = wait_for_bit(__func__, &regs->grstctl, DWC2_GRSTCTL_RXFFLSH,
-                          false, 1000, false);
+       ret = wait_for_bit_le32(&regs->grstctl, DWC2_GRSTCTL_RXFFLSH,
+                               false, 1000, false);
        if (ret)
                printf("%s: Timeout!\n", __func__);
 
@@ -145,15 +145,15 @@ static void dwc_otg_core_reset(struct dwc2_core_regs *regs)
        int ret;
 
        /* Wait for AHB master IDLE state. */
-       ret = wait_for_bit(__func__, &regs->grstctl, DWC2_GRSTCTL_AHBIDLE,
-                          true, 1000, false);
+       ret = wait_for_bit_le32(&regs->grstctl, DWC2_GRSTCTL_AHBIDLE,
+                               true, 1000, false);
        if (ret)
                printf("%s: Timeout!\n", __func__);
 
        /* Core Soft Reset */
        writel(DWC2_GRSTCTL_CSFTRST, &regs->grstctl);
-       ret = wait_for_bit(__func__, &regs->grstctl, DWC2_GRSTCTL_CSFTRST,
-                          false, 1000, false);
+       ret = wait_for_bit_le32(&regs->grstctl, DWC2_GRSTCTL_CSFTRST,
+                               false, 1000, false);
        if (ret)
                printf("%s: Timeout!\n", __func__);
 
@@ -267,8 +267,8 @@ static void dwc_otg_core_host_init(struct udevice *dev,
                clrsetbits_le32(&regs->hc_regs[i].hcchar,
                                DWC2_HCCHAR_EPDIR,
                                DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS);
-               ret = wait_for_bit(__func__, &regs->hc_regs[i].hcchar,
-                                  DWC2_HCCHAR_CHEN, false, 1000, false);
+               ret = wait_for_bit_le32(&regs->hc_regs[i].hcchar,
+                                       DWC2_HCCHAR_CHEN, false, 1000, false);
                if (ret)
                        printf("%s: Timeout!\n", __func__);
        }
@@ -783,8 +783,8 @@ int wait_for_chhltd(struct dwc2_hc_regs *hc_regs, uint32_t *sub, u8 *toggle)
        int ret;
        uint32_t hcint, hctsiz;
 
-       ret = wait_for_bit(__func__, &hc_regs->hcint, DWC2_HCINT_CHHLTD, true,
-                          1000, false);
+       ret = wait_for_bit_le32(&hc_regs->hcint, DWC2_HCINT_CHHLTD, true,
+                               1000, false);
        if (ret)
                return ret;
 

diff --git a/drivers/usb/host/ehci-msm.c b/drivers/usb/host/ehci-msm.c
index 2c0c63322cb2576cc8d38f7d74dd9a1153a1568f..f5320ca2985dd4c3925d6654dab119ccb742115d 100644 (file)
--- a/drivers/usb/host/ehci-msm.c
+++ b/drivers/usb/host/ehci-msm.c
@@ -133,8 +133,7 @@ static int ehci_usb_remove(struct udevice *dev)
        setbits_le32(&ehci->usbcmd, CMD_RESET);
 
        /* Wait for reset */
-       if (wait_for_bit(__func__, &ehci->usbcmd, CMD_RESET, false, 30,
-                        false)) {
+       if (wait_for_bit_le32(&ehci->usbcmd, CMD_RESET, false, 30, false)) {
                printf("Stuck on USB reset.\n");
                return -ETIMEDOUT;
        }

diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c
index fe2627ea937c6e3bfc1b2313c4103167e16ef6c9..2c8fc3c4b150acc89244565dffecd726ce7abcc2 100644 (file)
--- a/drivers/usb/host/ehci-mx6.c
+++ b/drivers/usb/host/ehci-mx6.c
@@ -142,13 +142,12 @@ static int usb_phy_enable(int index, struct usb_ehci *ehci)
 
        /* Stop then Reset */
        clrbits_le32(usb_cmd, UCMD_RUN_STOP);
-       ret = wait_for_bit(__func__, usb_cmd, UCMD_RUN_STOP, false, 10000,
-                          false);
+       ret = wait_for_bit_le32(usb_cmd, UCMD_RUN_STOP, false, 10000, false);
        if (ret)
                return ret;
 
        setbits_le32(usb_cmd, UCMD_RESET);
-       ret = wait_for_bit(__func__, usb_cmd, UCMD_RESET, false, 10000, false);
+       ret = wait_for_bit_le32(usb_cmd, UCMD_RESET, false, 10000, false);
        if (ret)
                return ret;
 

diff --git a/drivers/usb/host/ohci-lpc32xx.c b/drivers/usb/host/ohci-lpc32xx.c
index 2f2b4b90def72b4407d6a3a1fea238d6802a6431..44a49807a417f0dbfa3eb873a8fb9ce785392cdf 100644 (file)
--- a/drivers/usb/host/ohci-lpc32xx.c
+++ b/drivers/usb/host/ohci-lpc32xx.c
@@ -143,8 +143,8 @@ static int usbpll_setup(void)
        setbits_le32(&clk_pwr->usb_ctrl, CLK_USBCTRL_POSTDIV_2POW(0x01));
        setbits_le32(&clk_pwr->usb_ctrl, CLK_USBCTRL_PLL_PWRUP);
 
-       ret = wait_for_bit(__func__, &clk_pwr->usb_ctrl, CLK_USBCTRL_PLL_STS,
-                          true, CONFIG_SYS_HZ, false);
+       ret = wait_for_bit_le32(&clk_pwr->usb_ctrl, CLK_USBCTRL_PLL_STS,
+                               true, CONFIG_SYS_HZ, false);
        if (ret)
                return ret;
 
@@ -178,8 +178,8 @@ int usb_cpu_init(void)
 
        /* enable I2C clock */
        writel(OTG_CLK_I2C_EN, &otg->otg_clk_ctrl);
-       ret = wait_for_bit(__func__, &otg->otg_clk_sts, OTG_CLK_I2C_EN, true,
-                          CONFIG_SYS_HZ, false);
+       ret = wait_for_bit_le32(&otg->otg_clk_sts, OTG_CLK_I2C_EN, true,
+                               CONFIG_SYS_HZ, false);
        if (ret)
                return ret;
 
@@ -199,8 +199,8 @@ int usb_cpu_init(void)
                         OTG_CLK_I2C_EN | OTG_CLK_HOST_EN;
        writel(mask, &otg->otg_clk_ctrl);
 
-       ret = wait_for_bit(__func__, &otg->otg_clk_sts, mask, true,
-                          CONFIG_SYS_HZ, false);
+       ret = wait_for_bit_le32(&otg->otg_clk_sts, mask, true,
+                               CONFIG_SYS_HZ, false);
        if (ret)
                return ret;
 

diff --git a/drivers/usb/host/xhci-rcar.c b/drivers/usb/host/xhci-rcar.c
index d47c99644d6944d382100c3534fb697e72983f26..71202d7b03890c71f71f5c3d6f1a90f0ec1a10bf 100644 (file)
--- a/drivers/usb/host/xhci-rcar.c
+++ b/drivers/usb/host/xhci-rcar.c
@@ -55,18 +55,18 @@ static int xhci_rcar_download_fw(struct rcar_xhci *ctx, const u32 *fw_data,
                setbits_le32(regs + RCAR_USB3_DL_CTRL,
                             RCAR_USB3_DL_CTRL_FW_SET_DATA0);
 
-               ret = wait_for_bit("xhci-rcar", regs + RCAR_USB3_DL_CTRL,
-                                  RCAR_USB3_DL_CTRL_FW_SET_DATA0, false,
-                                  10, false);
+               ret = wait_for_bit_le32(regs + RCAR_USB3_DL_CTRL,
+                                       RCAR_USB3_DL_CTRL_FW_SET_DATA0, false,
+                                       10, false);
                if (ret)
                        break;
        }
 
        clrbits_le32(regs + RCAR_USB3_DL_CTRL, RCAR_USB3_DL_CTRL_ENABLE);
 
-       ret = wait_for_bit("xhci-rcar", regs + RCAR_USB3_DL_CTRL,
-                          RCAR_USB3_DL_CTRL_FW_SUCCESS, true,
-                          10, false);
+       ret = wait_for_bit_le32(regs + RCAR_USB3_DL_CTRL,
+                               RCAR_USB3_DL_CTRL_FW_SUCCESS, true,
+                               10, false);
 
        return ret;
 }

diff --git a/drivers/video/atmel_hlcdfb.c b/drivers/video/atmel_hlcdfb.c
index f77da2ec9797eafb0336bdd2cf7856a2bffd2a03..c0dd689e7c1f943f8d7af5f529da152f013297a8 100644 (file)
--- a/drivers/video/atmel_hlcdfb.c
+++ b/drivers/video/atmel_hlcdfb.c
@@ -70,26 +70,26 @@ void lcd_ctrl_init(void *lcdbase)
 
        /* Disable DISP signal */
        writel(LCDC_LCDDIS_DISPDIS, &regs->lcdc_lcddis);
-       ret = wait_for_bit(__func__, &regs->lcdc_lcdsr, LCDC_LCDSR_DISPSTS,
-                          false, 1000, false);
+       ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_DISPSTS,
+                               false, 1000, false);
        if (ret)
                printf("%s: %d: Timeout!\n", __func__, __LINE__);
        /* Disable synchronization */
        writel(LCDC_LCDDIS_SYNCDIS, &regs->lcdc_lcddis);
-       ret = wait_for_bit(__func__, &regs->lcdc_lcdsr, LCDC_LCDSR_LCDSTS,
-                          false, 1000, false);
+       ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_LCDSTS,
+                               false, 1000, false);
        if (ret)
                printf("%s: %d: Timeout!\n", __func__, __LINE__);
        /* Disable pixel clock */
        writel(LCDC_LCDDIS_CLKDIS, &regs->lcdc_lcddis);
-       ret = wait_for_bit(__func__, &regs->lcdc_lcdsr, LCDC_LCDSR_CLKSTS,
-                          false, 1000, false);
+       ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_CLKSTS,
+                               false, 1000, false);
        if (ret)
                printf("%s: %d: Timeout!\n", __func__, __LINE__);
        /* Disable PWM */
        writel(LCDC_LCDDIS_PWMDIS, &regs->lcdc_lcddis);
-       ret = wait_for_bit(__func__, &regs->lcdc_lcdsr, LCDC_LCDSR_PWMSTS,
-                          false, 1000, false);
+       ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_PWMSTS,
+                               false, 1000, false);
        if (ret)
                printf("%s: %d: Timeout!\n", __func__, __LINE__);
 
@@ -215,26 +215,26 @@ void lcd_ctrl_init(void *lcdbase)
        /* Enable LCD */
        value = readl(&regs->lcdc_lcden);
        writel(value | LCDC_LCDEN_CLKEN, &regs->lcdc_lcden);
-       ret = wait_for_bit(__func__, &regs->lcdc_lcdsr, LCDC_LCDSR_CLKSTS,
-                          true, 1000, false);
+       ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_CLKSTS,
+                               true, 1000, false);
        if (ret)
                printf("%s: %d: Timeout!\n", __func__, __LINE__);
        value = readl(&regs->lcdc_lcden);
        writel(value | LCDC_LCDEN_SYNCEN, &regs->lcdc_lcden);
-       ret = wait_for_bit(__func__, &regs->lcdc_lcdsr, LCDC_LCDSR_LCDSTS,
-                          true, 1000, false);
+       ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_LCDSTS,
+                               true, 1000, false);
        if (ret)
                printf("%s: %d: Timeout!\n", __func__, __LINE__);
        value = readl(&regs->lcdc_lcden);
        writel(value | LCDC_LCDEN_DISPEN, &regs->lcdc_lcden);
-       ret = wait_for_bit(__func__, &regs->lcdc_lcdsr, LCDC_LCDSR_DISPSTS,
-                          true, 1000, false);
+       ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_DISPSTS,
+                               true, 1000, false);
        if (ret)
                printf("%s: %d: Timeout!\n", __func__, __LINE__);
        value = readl(&regs->lcdc_lcden);
        writel(value | LCDC_LCDEN_PWMEN, &regs->lcdc_lcden);
-       ret = wait_for_bit(__func__, &regs->lcdc_lcdsr, LCDC_LCDSR_PWMSTS,
-                          true, 1000, false);
+       ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_PWMSTS,
+                               true, 1000, false);
        if (ret)
                printf("%s: %d: Timeout!\n", __func__, __LINE__);
 
@@ -299,26 +299,26 @@ static void atmel_hlcdc_init(struct udevice *dev)
 
        /* Disable DISP signal */
        writel(LCDC_LCDDIS_DISPDIS, &regs->lcdc_lcddis);
-       ret = wait_for_bit(__func__, &regs->lcdc_lcdsr, LCDC_LCDSR_DISPSTS,
-                          false, 1000, false);
+       ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_DISPSTS,
+                               false, 1000, false);
        if (ret)
                printf("%s: %d: Timeout!\n", __func__, __LINE__);
        /* Disable synchronization */
        writel(LCDC_LCDDIS_SYNCDIS, &regs->lcdc_lcddis);
-       ret = wait_for_bit(__func__, &regs->lcdc_lcdsr, LCDC_LCDSR_LCDSTS,
-                          false, 1000, false);
+       ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_LCDSTS,
+                               false, 1000, false);
        if (ret)
                printf("%s: %d: Timeout!\n", __func__, __LINE__);
        /* Disable pixel clock */
        writel(LCDC_LCDDIS_CLKDIS, &regs->lcdc_lcddis);
-       ret = wait_for_bit(__func__, &regs->lcdc_lcdsr, LCDC_LCDSR_CLKSTS,
-                          false, 1000, false);
+       ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_CLKSTS,
+                               false, 1000, false);
        if (ret)
                printf("%s: %d: Timeout!\n", __func__, __LINE__);
        /* Disable PWM */
        writel(LCDC_LCDDIS_PWMDIS, &regs->lcdc_lcddis);
-       ret = wait_for_bit(__func__, &regs->lcdc_lcdsr, LCDC_LCDSR_PWMSTS,
-                          false, 1000, false);
+       ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_PWMSTS,
+                               false, 1000, false);
        if (ret)
                printf("%s: %d: Timeout!\n", __func__, __LINE__);
 
@@ -451,26 +451,26 @@ static void atmel_hlcdc_init(struct udevice *dev)
        /* Enable LCD */
        value = readl(&regs->lcdc_lcden);
        writel(value | LCDC_LCDEN_CLKEN, &regs->lcdc_lcden);
-       ret = wait_for_bit(__func__, &regs->lcdc_lcdsr, LCDC_LCDSR_CLKSTS,
-                          true, 1000, false);
+       ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_CLKSTS,
+                               true, 1000, false);
        if (ret)
                printf("%s: %d: Timeout!\n", __func__, __LINE__);
        value = readl(&regs->lcdc_lcden);
        writel(value | LCDC_LCDEN_SYNCEN, &regs->lcdc_lcden);
-       ret = wait_for_bit(__func__, &regs->lcdc_lcdsr, LCDC_LCDSR_LCDSTS,
-                          true, 1000, false);
+       ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_LCDSTS,
+                               true, 1000, false);
        if (ret)
                printf("%s: %d: Timeout!\n", __func__, __LINE__);
        value = readl(&regs->lcdc_lcden);
        writel(value | LCDC_LCDEN_DISPEN, &regs->lcdc_lcden);
-       ret = wait_for_bit(__func__, &regs->lcdc_lcdsr, LCDC_LCDSR_DISPSTS,
-                          true, 1000, false);
+       ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_DISPSTS,
+                               true, 1000, false);
        if (ret)
                printf("%s: %d: Timeout!\n", __func__, __LINE__);
        value = readl(&regs->lcdc_lcden);
        writel(value | LCDC_LCDEN_PWMEN, &regs->lcdc_lcden);
-       ret = wait_for_bit(__func__, &regs->lcdc_lcdsr, LCDC_LCDSR_PWMSTS,
-                          true, 1000, false);
+       ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_PWMSTS,
+                               true, 1000, false);
        if (ret)
                printf("%s: %d: Timeout!\n", __func__, __LINE__);
 }

diff --git a/include/wait_bit.h b/include/wait_bit.h
index e8acfa577666005301efba3b383fddc61c2c4c2d..bd021baa4841bd8f132dc19928903da2dbb4c844 100644 (file)
--- a/include/wait_bit.h
+++ b/include/wait_bit.h
@@ -15,60 +15,6 @@
 #include <linux/errno.h>
 #include <asm/io.h>
 
-/**
- * wait_for_bit()      waits for bit set/cleared in register
- *
- * Function polls register waiting for specific bit(s) change
- * (either 0->1 or 1->0). It can fail under two conditions:
- * - Timeout
- * - User interaction (CTRL-C)
- * Function succeeds only if all bits of masked register are set/cleared
- * (depending on set option).
- *
- * @param prefix       Prefix added to timeout messagge (message visible only
- *                     with debug enabled)
- * @param reg          Register that will be read (using readl())
- * @param mask         Bit(s) of register that must be active
- * @param set          Selects wait condition (bit set or clear)
- * @param timeout_ms   Timeout (in miliseconds)
- * @param breakable    Enables CTRL-C interruption
- * @return             0 on success, -ETIMEDOUT or -EINTR on failure
- */
-static inline int wait_for_bit(const char *prefix, const u32 *reg,
-                              const u32 mask, const bool set,
-                              const unsigned int timeout_ms,
-                              const bool breakable)
-{
-       u32 val;
-       unsigned long start = get_timer(0);
-
-       while (1) {
-               val = readl(reg);
-
-               if (!set)
-                       val = ~val;
-
-               if ((val & mask) == mask)
-                       return 0;
-
-               if (get_timer(start) > timeout_ms)
-                       break;
-
-               if (breakable && ctrlc()) {
-                       puts("Abort\n");
-                       return -EINTR;
-               }
-
-               udelay(1);
-               WATCHDOG_RESET();
-       }
-
-       debug("%s: Timeout (reg=%p mask=%08x wait_set=%i)\n", prefix, reg, mask,
-             set);
-
-       return -ETIMEDOUT;
-}
-
 /**
  * wait_for_bit_x()    waits for bit set/cleared in register
  *