riscv: ax25: Hide the ax25-specific Kconfig option

There is no need to expose RISCV_NDS to the Kconfig menu as it is
an ax25-specific option. Introduce a dedicated Kconfig option for
the cache ops of ax25 platform and use that to guard the cache ops.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Rick Chen <rick@andestech.com>

diff --git a/arch/riscv/cpu/ax25/Kconfig b/arch/riscv/cpu/ax25/Kconfig
index 6c7022f0f5cf75399ad7b24d65effd8e108f8251..e9dbca2faeadac5cf6a2adbae1762c48d377922c 100644 (file)
--- a/arch/riscv/cpu/ax25/Kconfig
+++ b/arch/riscv/cpu/ax25/Kconfig
@@ -1,7 +1,14 @@
 config RISCV_NDS
-       bool "AndeStar V5 ISA support"
-       default n
+       bool
        help
-               Say Y here if you plan to run U-Boot on AndeStar v5
-               platforms and use some specific features which are
-               provided by Andes Technology AndeStar V5 Families.
+         Run U-Boot on AndeStar V5 platforms and use some specific features
+         which are provided by Andes Technology AndeStar V5 families.
+
+if RISCV_NDS
+
+config RISCV_NDS_CACHE
+       bool "AndeStar V5 families specific cache support"
+       help
+         Provide Andes Technology AndeStar V5 families specific cache support.
+
+endif

diff --git a/arch/riscv/cpu/ax25/cache.c b/arch/riscv/cpu/ax25/cache.c
index 6600ac2fac138c84c1215a5bfd189cc5b49c3d86..8d6ae170b8c5a02463c14f6a0e7eacc28a40eab4 100644 (file)
--- a/arch/riscv/cpu/ax25/cache.c
+++ b/arch/riscv/cpu/ax25/cache.c
@@ -9,7 +9,7 @@
 void icache_enable(void)
 {
 #ifndef CONFIG_SYS_ICACHE_OFF
-#ifdef CONFIG_RISCV_NDS
+#ifdef CONFIG_RISCV_NDS_CACHE
        asm volatile (
                "csrr t1, mcache_ctl\n\t"
                "ori t0, t1, 0x1\n\t"
@@ -22,7 +22,7 @@ void icache_enable(void)
 void icache_disable(void)
 {
 #ifndef CONFIG_SYS_ICACHE_OFF
-#ifdef CONFIG_RISCV_NDS
+#ifdef CONFIG_RISCV_NDS_CACHE
        asm volatile (
                "fence.i\n\t"
                "csrr t1, mcache_ctl\n\t"
@@ -36,7 +36,7 @@ void icache_disable(void)
 void dcache_enable(void)
 {
 #ifndef CONFIG_SYS_DCACHE_OFF
-#ifdef CONFIG_RISCV_NDS
+#ifdef CONFIG_RISCV_NDS_CACHE
        asm volatile (
                "csrr t1, mcache_ctl\n\t"
                "ori t0, t1, 0x2\n\t"
@@ -49,7 +49,7 @@ void dcache_enable(void)
 void dcache_disable(void)
 {
 #ifndef CONFIG_SYS_DCACHE_OFF
-#ifdef CONFIG_RISCV_NDS
+#ifdef CONFIG_RISCV_NDS_CACHE
        asm volatile (
                "fence\n\t"
                "csrr t1, mcache_ctl\n\t"
@@ -64,7 +64,7 @@ int icache_status(void)
 {
        int ret = 0;
 
-#ifdef CONFIG_RISCV_NDS
+#ifdef CONFIG_RISCV_NDS_CACHE
        asm volatile (
                "csrr t1, mcache_ctl\n\t"
                "andi   %0, t1, 0x01\n\t"
@@ -81,7 +81,7 @@ int dcache_status(void)
 {
        int ret = 0;
 
-#ifdef CONFIG_RISCV_NDS
+#ifdef CONFIG_RISCV_NDS_CACHE
        asm volatile (
                "csrr t1, mcache_ctl\n\t"
                "andi   %0, t1, 0x02\n\t"

diff --git a/board/AndesTech/ax25-ae350/Kconfig b/board/AndesTech/ax25-ae350/Kconfig
index bb69ea348926315aef49305e3041afede311429f..44cb302f708cd15d3c6b0e8e45334f411de53fec 100644 (file)
--- a/board/AndesTech/ax25-ae350/Kconfig
+++ b/board/AndesTech/ax25-ae350/Kconfig
@@ -21,4 +21,8 @@ config ENV_SIZE
 config ENV_OFFSET
        default 0x140000 if ENV_IS_IN_SPI_FLASH
 
+config BOARD_SPECIFIC_OPTIONS # dummy
+       def_bool y
+       select RISCV_NDS
+
 endif