sun50i:
BUILDMAN: "sun50i"
arm_catch_all:
- BUILDMAN: "arm -x arm11,arm7,arm9,aarch64,at91,bcm,freescale,kirkwood,mvebu,siemens,tegra,uniphier,mx,samsung,sunxi,am33xx,omap,rockchip,toradex,socfpga,k2,k3,zynq"
+ BUILDMAN: "arm -x arm11,arm7,arm9,aarch64,at91,bcm,freescale,kirkwood,mvebu,siemens,tegra,uniphier,mx,samsung,sunxi,am33xx,omap,rk,toradex,socfpga,k2,k3,zynq"
sandbox_x86:
BUILDMAN: "sandbox x86"
technexion:
uniphier:
BUILDMAN: "uniphier"
aarch64_catch_all:
- BUILDMAN: "aarch64 -x bcm,k3,tegra,ls1,ls2,mvebu,uniphier,sunxi,samsung,rockchip,versal,zynq"
+ BUILDMAN: "aarch64 -x bcm,k3,tegra,ls1,ls2,lx216,mvebu,uniphier,sunxi,samsung,socfpga,rk,versal,zynq"
rockchip:
- BUILDMAN: "rockchip"
+ BUILDMAN: "rk"
sh:
BUILDMAN: "sh -x arm"
zynq:
- BUILDMAN="sun50i -x orangepi"
- name: "buildman catch-all ARM"
env:
- - BUILDMAN="arm -x arm11,arm7,arm9,aarch64,at91,bcm,freescale,kirkwood,mvebu,siemens,tegra,uniphier,mx,samsung,sunxi,am33xx,omap,rockchip,toradex,socfpga,k2,k3,zynq"
+ - BUILDMAN="arm -x arm11,arm7,arm9,aarch64,at91,bcm,freescale,kirkwood,mvebu,siemens,tegra,uniphier,mx,samsung,sunxi,am33xx,omap,rk,toradex,socfpga,k2,k3,zynq"
- name: "buildman sandbox x86"
env:
- BUILDMAN="sandbox x86"
- BUILDMAN="uniphier"
- name: "buildman catch-all AArch64"
env:
- - BUILDMAN="aarch64 -x bcm,k3,tegra,ls1,ls2,mvebu,uniphier,sunxi,samsung,rockchip,versal,zynq"
+ - BUILDMAN="aarch64 -x bcm,k3,tegra,ls1,ls2,lx216,mvebu,uniphier,sunxi,samsung,socfpga,rk,versal,zynq"
- name: "buildman rockchip"
env:
- - BUILDMAN="rockchip -x orangepi"
+ - BUILDMAN="rk -x orangepi"
- name: "buildman sh"
env:
- BUILDMAN="sh -x arm"
(grep -v '^#' | \
grep -v '^$$' | \
tr '\n' '\0' | \
- sed -e 's/\\\x0/\n/g' | \
+ sed -e 's/\\\x0\s*//g' | \
xxd -i ; echo ", 0x00" ; )
endef
select PL011_SERIAL
select SUPPORT_SPL
-config TARGET_WOODBURN
- bool "Support woodburn"
- select CPU_ARM1136
-
-config TARGET_WOODBURN_SD
- bool "Support woodburn_sd"
- select CPU_ARM1136
- select SUPPORT_SPL
-
config TARGET_FLEA3
bool "Support flea3"
select CPU_ARM1136
config ARCH_MEDIATEK
bool "MediaTek SoCs"
- select BINMAN
select DM
select OF_CONTROL
select SPL_DM if SPL
source "board/toradex/colibri_pxa270/Kconfig"
source "board/variscite/dart_6ul/Kconfig"
source "board/vscom/baltos/Kconfig"
-source "board/woodburn/Kconfig"
source "board/xilinx/Kconfig"
source "board/xilinx/zynq/Kconfig"
source "board/xilinx/zynqmp/Kconfig"
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright 2014 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
*/
#ifndef __DTS_IMX6SX_PINFUNC_H
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2018 NXP
- */
-
-&qspi2 {
- num-cs = <2>;
-
- flash0: n25q256a@0 {
- compatible = "jedec,spi-nor";
- };
-
- flash1: n25q256a@1 {
- compatible = "jedec,spi-nor";
- };
-};
-/*
- * Copyright (C) 2015 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright (C) 2015 Freescale Semiconductor, Inc.
#include "imx6sx-sdb.dtsi"
#size-cells = <1>;
compatible = "micron,n25q256a", "jedec,spi-nor";
spi-max-frequency = <29000000>;
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <4>;
reg = <0>;
};
- flash1: n25q256a@1 {
+ flash1: n25q256a@2 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "micron,n25q256a", "jedec,spi-nor";
spi-max-frequency = <29000000>;
- reg = <1>;
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <4>;
+ reg = <2>;
};
};
®_soc {
vin-supply = <&sw1a_reg>;
};
+
+®_vdd1p1 {
+ vin-supply = <&vgen6_reg>;
+};
+
+®_vdd2p5 {
+ vin-supply = <&vgen6_reg>;
+};
+
+®_can_stby {
+ /* Transceiver EN/STBY is active low on RevB board */
+ gpio = <&gpio4 27 GPIO_ACTIVE_LOW>;
+};
+
+&snvs_pwrkey {
+ status = "okay";
+};
-/*
- * Copyright (C) 2014 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright (C) 2014 Freescale Semiconductor, Inc.
/dts-v1/;
stdout-path = &uart1;
};
- memory {
+ memory@80000000 {
+ device_type = "memory";
reg = <0x80000000 0x40000000>;
};
- backlight {
+ backlight_display: backlight-display {
compatible = "pwm-backlight";
pwms = <&pwm3 0 5000000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
label = "Volume Up";
gpios = <&gpio1 18 GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEUP>;
+ wakeup-source;
};
volume-down {
label = "Volume Down";
gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEDOWN>;
+ wakeup-source;
};
};
- regulators {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
+ vcc_sd3: regulator-vcc-sd3 {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_vcc_sd3>;
+ regulator-name = "VCC_SD3";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
- vcc_sd3: regulator@0 {
- compatible = "regulator-fixed";
- reg = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_vcc_sd3>;
- regulator-name = "VCC_SD3";
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
+ reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb_otg1>;
+ regulator-name = "usb_otg1_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
- reg_usb_otg1_vbus: regulator@1 {
- compatible = "regulator-fixed";
- reg = <1>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb_otg1>;
- regulator-name = "usb_otg1_vbus";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
+ reg_usb_otg2_vbus: regulator-usb-otg2-vbus {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb_otg2>;
+ regulator-name = "usb_otg2_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
- reg_usb_otg2_vbus: regulator@2 {
- compatible = "regulator-fixed";
- reg = <2>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb_otg2>;
- regulator-name = "usb_otg2_vbus";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
- reg_psu_5v: regulator@3 {
- compatible = "regulator-fixed";
- reg = <3>;
- regulator-name = "PSU-5V0";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- };
-
- reg_lcd_3v3: regulator@4 {
- compatible = "regulator-fixed";
- reg = <4>;
- regulator-name = "lcd-3v3";
- gpio = <&gpio3 27 0>;
- enable-active-high;
- };
-
- reg_peri_3v3: regulator@5 {
- compatible = "regulator-fixed";
- reg = <5>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_peri_3v3>;
- regulator-name = "peri_3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- gpio = <&gpio4 16 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- regulator-always-on;
- };
-
- reg_enet_3v3: regulator@6 {
- compatible = "regulator-fixed";
- reg = <6>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_enet_3v3>;
- regulator-name = "enet_3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- gpios = <&gpio2 6 GPIO_ACTIVE_LOW>;
- };
+ reg_psu_5v: regulator-psu-5v {
+ compatible = "regulator-fixed";
+ regulator-name = "PSU-5V0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ reg_lcd_3v3: regulator-lcd-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "lcd-3v3";
+ gpio = <&gpio3 27 0>;
+ enable-active-high;
+ };
+
+ reg_peri_3v3: regulator-peri-3v3 {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_peri_3v3>;
+ regulator-name = "peri_3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio4 16 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+ };
+
+ reg_enet_3v3: regulator-enet-3v3 {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet_3v3>;
+ regulator-name = "enet_3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio2 6 GPIO_ACTIVE_LOW>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_pcie_gpio: regulator-pcie-gpio {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pcie_reg>;
+ regulator-name = "MPCIE_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio2 1 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_lcd_5v: regulator-lcd-5v {
+ compatible = "regulator-fixed";
+ regulator-name = "lcd-5v0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ reg_can_en: regulator-can-en {
+ compatible = "regulator-fixed";
+ regulator-name = "can-en";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ reg_can_stby: regulator-can-stby {
+ compatible = "regulator-fixed";
+ regulator-name = "can-stby";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
};
sound {
mux-int-port = <2>;
mux-ext-port = <6>;
};
+
+ panel {
+ compatible = "sii,43wvf1g";
+ backlight = <&backlight_display>;
+ dvdd-supply = <®_lcd_3v3>;
+ avdd-supply = <®_lcd_5v>;
+
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&display_out>;
+ };
+ };
+ };
};
&audmux {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet1>;
phy-supply = <®_enet_3v3>;
- phy-mode = "rgmii";
+ phy-mode = "rgmii-id";
phy-handle = <ðphy1>;
+ phy-reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>;
status = "okay";
mdio {
status = "okay";
};
+&flexcan1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan1>;
+ xceiver-supply = <®_can_stby>;
+ status = "okay";
+};
+
+&flexcan2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan2>;
+ xceiver-supply = <®_can_stby>;
+ status = "okay";
+};
+
&i2c3 {
clock-frequency = <100000>;
pinctrl-names = "default";
};
};
+&pcie {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pcie>;
+ reset-gpio = <&gpio2 0 GPIO_ACTIVE_LOW>;
+ vpcie-supply = <®_pcie_gpio>;
+ status = "okay";
+};
+
&lcdif1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcd>;
- lcd-supply = <®_lcd_3v3>;
- display = <&display0>;
status = "okay";
- display0: display0 {
- bits-per-pixel = <16>;
- bus-width = <24>;
-
- display-timings {
- native-mode = <&timing0>;
- timing0: timing0 {
- clock-frequency = <33500000>;
- hactive = <800>;
- vactive = <480>;
- hback-porch = <89>;
- hfront-porch = <164>;
- vback-porch = <23>;
- vfront-porch = <10>;
- hsync-len = <10>;
- vsync-len = <10>;
- hsync-active = <0>;
- vsync-active = <0>;
- de-active = <1>;
- pixelclk-active = <0>;
- };
+ port {
+ display_out: endpoint {
+ remote-endpoint = <&panel_in>;
};
};
};
MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x3081
MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x3081
MX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M 0x91
+ /* phy reset */
+ MX6SX_PAD_ENET2_CRS__GPIO2_IO_7 0x10b0
>;
};
>;
};
+ pinctrl_flexcan1: flexcan1grp {
+ fsl,pins = <
+ MX6SX_PAD_QSPI1B_DQS__CAN1_TX 0x1b020
+ MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX 0x1b020
+ >;
+ };
+
+ pinctrl_flexcan2: flexcan2grp {
+ fsl,pins = <
+ MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX 0x1b020
+ MX6SX_PAD_QSPI1A_DQS__CAN2_TX 0x1b020
+ >;
+ };
+
pinctrl_gpio_keys: gpio_keysgrp {
fsl,pins = <
MX6SX_PAD_CSI_DATA04__GPIO1_IO_18 0x17059
>;
};
+ pinctrl_pcie: pciegrp {
+ fsl,pins = <
+ MX6SX_PAD_ENET1_COL__GPIO2_IO_0 0x10b0
+ >;
+ };
+
+ pinctrl_pcie_reg: pciereggrp {
+ fsl,pins = <
+ MX6SX_PAD_ENET1_CRS__GPIO2_IO_1 0x10b0
+ >;
+ };
+
pinctrl_peri_3v3: peri3v3grp {
fsl,pins = <
MX6SX_PAD_QSPI1A_DATA0__GPIO4_IO_16 0x80000000
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright 2014 Freescale Semiconductor, Inc.
#include <dt-bindings/clock/imx6sx-clock.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "imx6sx-pinfunc.h"
-#include "skeleton.dtsi"
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ /*
+ * The decompressor and also some bootloaders rely on a
+ * pre-existing /chosen node to be available to insert the
+ * command line and merge other ATAGS info.
+ */
+ chosen {};
+
aliases {
can0 = &flexcan1;
can1 = &flexcan2;
serial3 = &uart4;
serial4 = &uart5;
serial5 = &uart6;
- spi0 = &qspi1;
- spi1 = &qspi2;
- spi2 = &ecspi1;
- spi3 = &ecspi2;
- spi4 = &ecspi3;
- spi5 = &ecspi4;
- spi6 = &ecspi5;
+ spi0 = &ecspi1;
+ spi1 = &ecspi2;
+ spi2 = &ecspi3;
+ spi3 = &ecspi4;
+ spi4 = &ecspi5;
usbphy0 = &usbphy1;
usbphy1 = &usbphy2;
};
198000 1175000
>;
clock-latency = <61036>; /* two CLK32 periods */
+ #cooling-cells = <2>;
clocks = <&clks IMX6SX_CLK_ARM>,
<&clks IMX6SX_CLK_PLL2_PFD2>,
<&clks IMX6SX_CLK_STEP>,
};
};
- intc: interrupt-controller@00a01000 {
- compatible = "arm,cortex-a9-gic";
- #interrupt-cells = <3>;
- interrupt-controller;
- reg = <0x00a01000 0x1000>,
- <0x00a00100 0x100>;
- interrupt-parent = <&intc>;
+ ckil: clock-ckil {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "ckil";
};
- clocks {
- #address-cells = <1>;
- #size-cells = <0>;
+ osc: clock-osc {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ clock-output-names = "osc";
+ };
- ckil: clock@0 {
- compatible = "fixed-clock";
- reg = <0>;
- #clock-cells = <0>;
- clock-frequency = <32768>;
- clock-output-names = "ckil";
- };
+ ipp_di0: clock-ipp-di0 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ clock-output-names = "ipp_di0";
+ };
- osc: clock@1 {
- compatible = "fixed-clock";
- reg = <1>;
- #clock-cells = <0>;
- clock-frequency = <24000000>;
- clock-output-names = "osc";
- };
+ ipp_di1: clock-ipp-di1 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ clock-output-names = "ipp_di1";
+ };
- ipp_di0: clock@2 {
- compatible = "fixed-clock";
- reg = <2>;
- #clock-cells = <0>;
- clock-frequency = <0>;
- clock-output-names = "ipp_di0";
- };
+ anaclk1: clock-anaclk1 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ clock-output-names = "anaclk1";
+ };
- ipp_di1: clock@3 {
- compatible = "fixed-clock";
- reg = <3>;
- #clock-cells = <0>;
- clock-frequency = <0>;
- clock-output-names = "ipp_di1";
- };
+ anaclk2: clock-anaclk2 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ clock-output-names = "anaclk2";
+ };
+
+ tempmon: tempmon {
+ compatible = "fsl,imx6sx-tempmon", "fsl,imx6q-tempmon";
+ interrupt-parent = <&gpc>;
+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+ fsl,tempmon = <&anatop>;
+ nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
+ nvmem-cell-names = "calib", "temp_grade";
+ clocks = <&clks IMX6SX_CLK_PLL3_USB_OTG>;
+ };
+
+ pmu {
+ compatible = "arm,cortex-a9-pmu";
+ interrupt-parent = <&gpc>;
+ interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ usbphynop1: usbphynop1 {
+ compatible = "usb-nop-xceiv";
+ #phy-cells = <0>;
};
soc {
interrupt-parent = <&gpc>;
ranges;
- pmu {
- compatible = "arm,cortex-a9-pmu";
- interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+ ocram_s: sram@8f8000 {
+ compatible = "mmio-sram";
+ reg = <0x008f8000 0x4000>;
+ clocks = <&clks IMX6SX_CLK_OCRAM_S>;
};
- ocram: sram@00900000 {
+ ocram: sram@900000 {
compatible = "mmio-sram";
reg = <0x00900000 0x20000>;
clocks = <&clks IMX6SX_CLK_OCRAM>;
};
- L2: l2-cache@00a02000 {
+ intc: interrupt-controller@a01000 {
+ compatible = "arm,cortex-a9-gic";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x00a01000 0x1000>,
+ <0x00a00100 0x100>;
+ interrupt-parent = <&intc>;
+ };
+
+ L2: l2-cache@a02000 {
compatible = "arm,pl310-cache";
reg = <0x00a02000 0x1000>;
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
arm,data-latency = <4 2 3>;
};
- gpu: gpu@01800000 {
+ gpu: gpu@1800000 {
compatible = "vivante,gc";
reg = <0x01800000 0x4000>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
<&clks IMX6SX_CLK_GPU>,
<&clks IMX6SX_CLK_GPU>;
clock-names = "bus", "core", "shader";
+ power-domains = <&pd_pu>;
};
- dma_apbh: dma-apbh@01804000 {
+ dma_apbh: dma-apbh@1804000 {
compatible = "fsl,imx6sx-dma-apbh", "fsl,imx28-dma-apbh";
reg = <0x01804000 0x2000>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
clocks = <&clks IMX6SX_CLK_APBH_DMA>;
};
- gpmi: gpmi-nand@01806000{
+ gpmi: gpmi-nand@1806000{
compatible = "fsl,imx6sx-gpmi-nand";
#address-cells = <1>;
#size-cells = <1>;
status = "disabled";
};
- aips1: aips-bus@02000000 {
+ aips1: aips-bus@2000000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x02000000 0x100000>;
ranges;
- spba-bus@02000000 {
+ spba-bus@2000000 {
compatible = "fsl,spba-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x02000000 0x40000>;
ranges;
- spdif: spdif@02004000 {
+ spdif: spdif@2004000 {
compatible = "fsl,imx6sx-spdif", "fsl,imx35-spdif";
reg = <0x02004000 0x4000>;
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
- ecspi1: ecspi@02008000 {
+ ecspi1: spi@2008000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
status = "disabled";
};
- ecspi2: ecspi@0200c000 {
+ ecspi2: spi@200c000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
status = "disabled";
};
- ecspi3: ecspi@02010000 {
+ ecspi3: spi@2010000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
status = "disabled";
};
- ecspi4: ecspi@02014000 {
+ ecspi4: spi@2014000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
status = "disabled";
};
- uart1: serial@02020000 {
- compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
+ uart1: serial@2020000 {
+ compatible = "fsl,imx6sx-uart",
+ "fsl,imx6q-uart", "fsl,imx21-uart";
reg = <0x02020000 0x4000>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SX_CLK_UART_IPG>,
status = "disabled";
};
- esai: esai@02024000 {
+ esai: esai@2024000 {
reg = <0x02024000 0x4000>;
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SX_CLK_ESAI_IPG>,
status = "disabled";
};
- ssi1: ssi@02028000 {
+ ssi1: ssi@2028000 {
#sound-dai-cells = <0>;
compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
reg = <0x02028000 0x4000>;
status = "disabled";
};
- ssi2: ssi@0202c000 {
+ ssi2: ssi@202c000 {
#sound-dai-cells = <0>;
compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
reg = <0x0202c000 0x4000>;
status = "disabled";
};
- ssi3: ssi@02030000 {
+ ssi3: ssi@2030000 {
#sound-dai-cells = <0>;
compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
reg = <0x02030000 0x4000>;
status = "disabled";
};
- asrc: asrc@02034000 {
+ asrc: asrc@2034000 {
reg = <0x02034000 0x4000>;
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SX_CLK_ASRC_MEM>,
};
};
- pwm1: pwm@02080000 {
+ pwm1: pwm@2080000 {
compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
reg = <0x02080000 0x4000>;
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
#pwm-cells = <2>;
};
- pwm2: pwm@02084000 {
+ pwm2: pwm@2084000 {
compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
reg = <0x02084000 0x4000>;
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
#pwm-cells = <2>;
};
- pwm3: pwm@02088000 {
+ pwm3: pwm@2088000 {
compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
reg = <0x02088000 0x4000>;
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
#pwm-cells = <2>;
};
- pwm4: pwm@0208c000 {
+ pwm4: pwm@208c000 {
compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
reg = <0x0208c000 0x4000>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
#pwm-cells = <2>;
};
- flexcan1: can@02090000 {
+ flexcan1: can@2090000 {
compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan";
reg = <0x02090000 0x4000>;
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SX_CLK_CAN1_IPG>,
<&clks IMX6SX_CLK_CAN1_SERIAL>;
clock-names = "ipg", "per";
+ fsl,stop-mode = <&gpr 0x10 1 0x10 17>;
status = "disabled";
};
- flexcan2: can@02094000 {
+ flexcan2: can@2094000 {
compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan";
reg = <0x02094000 0x4000>;
interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SX_CLK_CAN2_IPG>,
<&clks IMX6SX_CLK_CAN2_SERIAL>;
clock-names = "ipg", "per";
+ fsl,stop-mode = <&gpr 0x10 2 0x10 18>;
status = "disabled";
};
- gpt: gpt@02098000 {
- compatible = "fsl,imx6sx-gpt", "fsl,imx31-gpt";
+ gpt: gpt@2098000 {
+ compatible = "fsl,imx6sx-gpt", "fsl,imx6dl-gpt";
reg = <0x02098000 0x4000>;
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SX_CLK_GPT_BUS>,
clock-names = "ipg", "per";
};
- gpio1: gpio@0209c000 {
+ gpio1: gpio@209c000 {
compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
reg = <0x0209c000 0x4000>;
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
gpio-ranges = <&iomuxc 0 5 26>;
};
- gpio2: gpio@020a0000 {
+ gpio2: gpio@20a0000 {
compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
reg = <0x020a0000 0x4000>;
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
gpio-ranges = <&iomuxc 0 31 20>;
};
- gpio3: gpio@020a4000 {
+ gpio3: gpio@20a4000 {
compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
reg = <0x020a4000 0x4000>;
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
gpio-ranges = <&iomuxc 0 51 29>;
};
- gpio4: gpio@020a8000 {
+ gpio4: gpio@20a8000 {
compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
reg = <0x020a8000 0x4000>;
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
gpio-ranges = <&iomuxc 0 80 32>;
};
- gpio5: gpio@020ac000 {
+ gpio5: gpio@20ac000 {
compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
reg = <0x020ac000 0x4000>;
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
gpio-ranges = <&iomuxc 0 112 24>;
};
- gpio6: gpio@020b0000 {
+ gpio6: gpio@20b0000 {
compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
reg = <0x020b0000 0x4000>;
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
gpio-ranges = <&iomuxc 0 136 12>, <&iomuxc 12 158 11>;
};
- gpio7: gpio@020b4000 {
+ gpio7: gpio@20b4000 {
compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
reg = <0x020b4000 0x4000>;
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
gpio-ranges = <&iomuxc 0 148 10>, <&iomuxc 10 169 2>;
};
- kpp: kpp@020b8000 {
+ kpp: kpp@20b8000 {
compatible = "fsl,imx6sx-kpp", "fsl,imx21-kpp";
reg = <0x020b8000 0x4000>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX6SX_CLK_DUMMY>;
+ clocks = <&clks IMX6SX_CLK_IPG>;
status = "disabled";
};
- wdog1: wdog@020bc000 {
+ wdog1: wdog@20bc000 {
compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
reg = <0x020bc000 0x4000>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX6SX_CLK_DUMMY>;
+ clocks = <&clks IMX6SX_CLK_IPG>;
};
- wdog2: wdog@020c0000 {
+ wdog2: wdog@20c0000 {
compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
reg = <0x020c0000 0x4000>;
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX6SX_CLK_DUMMY>;
+ clocks = <&clks IMX6SX_CLK_IPG>;
status = "disabled";
};
- clks: ccm@020c4000 {
+ clks: ccm@20c4000 {
compatible = "fsl,imx6sx-ccm";
reg = <0x020c4000 0x4000>;
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
#clock-cells = <1>;
- clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
- clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
+ clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>, <&anaclk1>, <&anaclk2>;
+ clock-names = "ckil", "osc", "ipp_di0", "ipp_di1", "anaclk1", "anaclk2";
};
- anatop: anatop@020c8000 {
+ anatop: anatop@20c8000 {
compatible = "fsl,imx6sx-anatop", "fsl,imx6q-anatop",
"syscon", "simple-bus";
reg = <0x020c8000 0x1000>;
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
- regulator-1p1 {
+ reg_vdd1p1: regulator-1p1 {
compatible = "fsl,anatop-regulator";
regulator-name = "vdd1p1";
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <1375000>;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1200000>;
regulator-always-on;
anatop-reg-offset = <0x110>;
anatop-vol-bit-shift = <8>;
anatop-min-bit-val = <4>;
anatop-min-voltage = <800000>;
anatop-max-voltage = <1375000>;
+ anatop-enable-bit = <0>;
};
- regulator-3p0 {
+ reg_vdd3p0: regulator-3p0 {
compatible = "fsl,anatop-regulator";
regulator-name = "vdd3p0";
regulator-min-microvolt = <2800000>;
anatop-min-bit-val = <0>;
anatop-min-voltage = <2625000>;
anatop-max-voltage = <3400000>;
+ anatop-enable-bit = <0>;
};
- regulator-2p5 {
+ reg_vdd2p5: regulator-2p5 {
compatible = "fsl,anatop-regulator";
regulator-name = "vdd2p5";
- regulator-min-microvolt = <2100000>;
- regulator-max-microvolt = <2875000>;
+ regulator-min-microvolt = <2250000>;
+ regulator-max-microvolt = <2750000>;
regulator-always-on;
anatop-reg-offset = <0x130>;
anatop-vol-bit-shift = <8>;
anatop-min-bit-val = <0>;
anatop-min-voltage = <2100000>;
anatop-max-voltage = <2875000>;
+ anatop-enable-bit = <0>;
};
reg_arm: regulator-vddcore {
};
};
- tempmon: tempmon {
- compatible = "fsl,imx6sx-tempmon", "fsl,imx6q-tempmon";
- interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
- fsl,tempmon = <&anatop>;
- fsl,tempmon-data = <&ocotp>;
- clocks = <&clks IMX6SX_CLK_PLL3_USB_OTG>;
- };
-
- usbphy1: usbphy@020c9000 {
+ usbphy1: usbphy@20c9000 {
compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy";
reg = <0x020c9000 0x1000>;
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
fsl,anatop = <&anatop>;
};
- usbphy2: usbphy@020ca000 {
+ usbphy2: usbphy@20ca000 {
compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy";
reg = <0x020ca000 0x1000>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
fsl,anatop = <&anatop>;
};
- snvs: snvs@020cc000 {
+ snvs: snvs@20cc000 {
compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
reg = <0x020cc000 0x4000>;
compatible = "syscon-poweroff";
regmap = <&snvs>;
offset = <0x38>;
+ value = <0x60>;
mask = <0x60>;
status = "disabled";
};
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
linux,keycode = <KEY_POWER>;
wakeup-source;
+ status = "disabled";
};
};
- epit1: epit@020d0000 {
+ epit1: epit@20d0000 {
reg = <0x020d0000 0x4000>;
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
};
- epit2: epit@020d4000 {
+ epit2: epit@20d4000 {
reg = <0x020d4000 0x4000>;
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
};
- src: src@020d8000 {
+ src: src@20d8000 {
compatible = "fsl,imx6sx-src", "fsl,imx51-src";
reg = <0x020d8000 0x4000>;
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
#reset-cells = <1>;
};
- gpc: gpc@020dc000 {
+ gpc: gpc@20dc000 {
compatible = "fsl,imx6sx-gpc", "fsl,imx6q-gpc";
reg = <0x020dc000 0x4000>;
interrupt-controller;
#interrupt-cells = <3>;
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&intc>;
+ clocks = <&clks IMX6SX_CLK_IPG>;
+ clock-names = "ipg";
+
+ pgc {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ power-domain@0 {
+ reg = <0>;
+ #power-domain-cells = <0>;
+ };
+
+ pd_pu: power-domain@1 {
+ reg = <1>;
+ #power-domain-cells = <0>;
+ power-supply = <®_soc>;
+ clocks = <&clks IMX6SX_CLK_GPU>;
+ };
+
+ pd_disp: power-domain@2 {
+ reg = <2>;
+ #power-domain-cells = <0>;
+ clocks = <&clks IMX6SX_CLK_PXP_AXI>,
+ <&clks IMX6SX_CLK_DISPLAY_AXI>,
+ <&clks IMX6SX_CLK_LCDIF1_PIX>,
+ <&clks IMX6SX_CLK_LCDIF_APB>,
+ <&clks IMX6SX_CLK_LCDIF2_PIX>,
+ <&clks IMX6SX_CLK_CSI>,
+ <&clks IMX6SX_CLK_VADC>;
+ };
+
+ pd_pci: power-domain@3 {
+ reg = <3>;
+ #power-domain-cells = <0>;
+ power-supply = <®_pcie>;
+ };
+ };
};
- iomuxc: iomuxc@020e0000 {
+ iomuxc: iomuxc@20e0000 {
compatible = "fsl,imx6sx-iomuxc";
reg = <0x020e0000 0x4000>;
};
- gpr: iomuxc-gpr@020e4000 {
+ gpr: iomuxc-gpr@20e4000 {
compatible = "fsl,imx6sx-iomuxc-gpr",
"fsl,imx6q-iomuxc-gpr", "syscon";
reg = <0x020e4000 0x4000>;
};
- sdma: sdma@020ec000 {
+ sdma: sdma@20ec000 {
compatible = "fsl,imx6sx-sdma", "fsl,imx6q-sdma";
reg = <0x020ec000 0x4000>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX6SX_CLK_SDMA>,
+ clocks = <&clks IMX6SX_CLK_IPG>,
<&clks IMX6SX_CLK_SDMA>;
clock-names = "ipg", "ahb";
#dma-cells = <3>;
};
};
- aips2: aips-bus@02100000 {
+ aips2: aips-bus@2100000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
crypto: caam@2100000 {
compatible = "fsl,sec-v4.0";
- fsl,sec-era = <4>;
#address-cells = <1>;
#size-cells = <1>;
reg = <0x2100000 0x10000>;
};
};
- usbotg1: usb@02184000 {
+ usbotg1: usb@2184000 {
compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
reg = <0x02184000 0x200>;
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
- usbotg2: usb@02184200 {
+ usbotg2: usb@2184200 {
compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
reg = <0x02184200 0x200>;
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
- usbh: usb@02184400 {
+ usbh: usb@2184400 {
compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
reg = <0x02184400 0x200>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SX_CLK_USBOH3>;
+ fsl,usbphy = <&usbphynop1>;
fsl,usbmisc = <&usbmisc 2>;
phy_type = "hsic";
fsl,anatop = <&anatop>;
status = "disabled";
};
- usbmisc: usbmisc@02184800 {
+ usbmisc: usbmisc@2184800 {
#index-cells = <1>;
compatible = "fsl,imx6sx-usbmisc", "fsl,imx6q-usbmisc";
reg = <0x02184800 0x200>;
clocks = <&clks IMX6SX_CLK_USBOH3>;
};
- fec1: ethernet@02188000 {
+ fec1: ethernet@2188000 {
compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec";
reg = <0x02188000 0x4000>;
+ interrupt-names = "int0", "pps";
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SX_CLK_ENET>,
<&clks IMX6SX_CLK_ENET_PTP>;
clock-names = "ipg", "ahb", "ptp",
"enet_clk_ref", "enet_out";
- fsl,num-tx-queues=<3>;
- fsl,num-rx-queues=<3>;
+ fsl,num-tx-queues = <3>;
+ fsl,num-rx-queues = <3>;
status = "disabled";
- };
+ };
- mlb: mlb@0218c000 {
+ mlb: mlb@218c000 {
reg = <0x0218c000 0x4000>;
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
status = "disabled";
};
- usdhc1: usdhc@02190000 {
+ usdhc1: usdhc@2190000 {
compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
reg = <0x02190000 0x4000>;
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
- usdhc2: usdhc@02194000 {
+ usdhc2: usdhc@2194000 {
compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
reg = <0x02194000 0x4000>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
- usdhc3: usdhc@02198000 {
+ usdhc3: usdhc@2198000 {
compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
reg = <0x02198000 0x4000>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
- usdhc4: usdhc@0219c000 {
+ usdhc4: usdhc@219c000 {
compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
reg = <0x0219c000 0x4000>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
- i2c1: i2c@021a0000 {
+ i2c1: i2c@21a0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
status = "disabled";
};
- i2c2: i2c@021a4000 {
+ i2c2: i2c@21a4000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
status = "disabled";
};
- i2c3: i2c@021a8000 {
+ i2c3: i2c@21a8000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
status = "disabled";
};
- mmdc: mmdc@021b0000 {
+ memory-controller@21b0000 {
compatible = "fsl,imx6sx-mmdc", "fsl,imx6q-mmdc";
reg = <0x021b0000 0x4000>;
+ clocks = <&clks IMX6SX_CLK_MMDC_P0_IPG>;
};
- fec2: ethernet@021b4000 {
+ fec2: ethernet@21b4000 {
compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec";
reg = <0x021b4000 0x4000>;
+ interrupt-names = "int0", "pps";
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SX_CLK_ENET>,
status = "disabled";
};
- weim: weim@021b8000 {
+ weim: weim@21b8000 {
+ #address-cells = <2>;
+ #size-cells = <1>;
compatible = "fsl,imx6sx-weim", "fsl,imx6q-weim";
reg = <0x021b8000 0x4000>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SX_CLK_EIM_SLOW>;
+ fsl,weim-cs-gpr = <&gpr>;
+ status = "disabled";
};
- ocotp: ocotp@021bc000 {
+ ocotp: ocotp@21bc000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
compatible = "fsl,imx6sx-ocotp", "syscon";
reg = <0x021bc000 0x4000>;
clocks = <&clks IMX6SX_CLK_OCOTP>;
+
+ tempmon_calib: calib@38 {
+ reg = <0x38 4>;
+ };
+
+ tempmon_temp_grade: temp-grade@20 {
+ reg = <0x20 4>;
+ };
};
- sai1: sai@021d4000 {
+ sai1: sai@21d4000 {
compatible = "fsl,imx6sx-sai";
reg = <0x021d4000 0x4000>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
- audmux: audmux@021d8000 {
+ audmux: audmux@21d8000 {
compatible = "fsl,imx6sx-audmux", "fsl,imx31-audmux";
reg = <0x021d8000 0x4000>;
status = "disabled";
};
- sai2: sai@021dc000 {
+ sai2: sai@21dc000 {
compatible = "fsl,imx6sx-sai";
reg = <0x021dc000 0x4000>;
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
- qspi1: qspi@021e0000 {
+ qspi1: spi@21e0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6sx-qspi";
status = "disabled";
};
- qspi2: qspi@021e4000 {
+ qspi2: spi@21e4000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6sx-qspi";
status = "disabled";
};
- uart2: serial@021e8000 {
- compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
+ uart2: serial@21e8000 {
+ compatible = "fsl,imx6sx-uart",
+ "fsl,imx6q-uart", "fsl,imx21-uart";
reg = <0x021e8000 0x4000>;
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SX_CLK_UART_IPG>,
status = "disabled";
};
- uart3: serial@021ec000 {
- compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
+ uart3: serial@21ec000 {
+ compatible = "fsl,imx6sx-uart",
+ "fsl,imx6q-uart", "fsl,imx21-uart";
reg = <0x021ec000 0x4000>;
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SX_CLK_UART_IPG>,
status = "disabled";
};
- uart4: serial@021f0000 {
- compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
+ uart4: serial@21f0000 {
+ compatible = "fsl,imx6sx-uart",
+ "fsl,imx6q-uart", "fsl,imx21-uart";
reg = <0x021f0000 0x4000>;
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SX_CLK_UART_IPG>,
status = "disabled";
};
- uart5: serial@021f4000 {
- compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
+ uart5: serial@21f4000 {
+ compatible = "fsl,imx6sx-uart",
+ "fsl,imx6q-uart", "fsl,imx21-uart";
reg = <0x021f4000 0x4000>;
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SX_CLK_UART_IPG>,
status = "disabled";
};
- i2c4: i2c@021f8000 {
+ i2c4: i2c@21f8000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
};
};
- aips3: aips-bus@02200000 {
+ aips3: aips-bus@2200000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x02200000 0x100000>;
ranges;
- spba-bus@02200000 {
+ spba-bus@2240000 {
compatible = "fsl,spba-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x02240000 0x40000>;
ranges;
- csi1: csi@02214000 {
+ csi1: csi@2214000 {
reg = <0x02214000 0x4000>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>,
status = "disabled";
};
- pxp: pxp@02218000 {
+ pxp: pxp@2218000 {
+ compatible = "fsl,imx6sx-pxp", "fsl,imx6ull-pxp";
reg = <0x02218000 0x4000>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX6SX_CLK_PXP_AXI>,
- <&clks IMX6SX_CLK_DISPLAY_AXI>;
- clock-names = "pxp-axi", "disp-axi";
+ clocks = <&clks IMX6SX_CLK_PXP_AXI>;
+ clock-names = "axi";
+ power-domains = <&pd_disp>;
status = "disabled";
};
- csi2: csi@0221c000 {
+ csi2: csi@221c000 {
reg = <0x0221c000 0x4000>;
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>,
status = "disabled";
};
- lcdif1: lcdif@02220000 {
+ lcdif1: lcdif@2220000 {
compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
reg = <0x02220000 0x4000>;
- interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 5 IRQ_TYPE_EDGE_RISING>;
clocks = <&clks IMX6SX_CLK_LCDIF1_PIX>,
<&clks IMX6SX_CLK_LCDIF_APB>,
<&clks IMX6SX_CLK_DISPLAY_AXI>;
clock-names = "pix", "axi", "disp_axi";
+ power-domains = <&pd_disp>;
status = "disabled";
};
- lcdif2: lcdif@02224000 {
+ lcdif2: lcdif@2224000 {
compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
reg = <0x02224000 0x4000>;
- interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 6 IRQ_TYPE_EDGE_RISING>;
clocks = <&clks IMX6SX_CLK_LCDIF2_PIX>,
<&clks IMX6SX_CLK_LCDIF_APB>,
<&clks IMX6SX_CLK_DISPLAY_AXI>;
clock-names = "pix", "axi", "disp_axi";
+ power-domains = <&pd_disp>;
status = "disabled";
};
- vadc: vadc@02228000 {
+ vadc: vadc@2228000 {
reg = <0x02228000 0x4000>, <0x0222c000 0x4000>;
reg-names = "vadc-vafe", "vadc-vdec";
clocks = <&clks IMX6SX_CLK_VADC>,
<&clks IMX6SX_CLK_CSI>;
clock-names = "vadc", "csi";
+ power-domains = <&pd_disp>;
status = "disabled";
};
};
- adc1: adc@02280000 {
+ adc1: adc@2280000 {
compatible = "fsl,imx6sx-adc", "fsl,vf610-adc";
reg = <0x02280000 0x4000>;
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
fsl,adck-max-frequency = <30000000>, <40000000>,
<20000000>;
status = "disabled";
- };
+ };
- adc2: adc@02284000 {
+ adc2: adc@2284000 {
compatible = "fsl,imx6sx-adc", "fsl,vf610-adc";
reg = <0x02284000 0x4000>;
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
fsl,adck-max-frequency = <30000000>, <40000000>,
<20000000>;
status = "disabled";
- };
+ };
- wdog3: wdog@02288000 {
+ wdog3: wdog@2288000 {
compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
reg = <0x02288000 0x4000>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX6SX_CLK_DUMMY>;
+ clocks = <&clks IMX6SX_CLK_IPG>;
status = "disabled";
};
- ecspi5: ecspi@0228c000 {
+ ecspi5: spi@228c000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
status = "disabled";
};
- uart6: serial@022a0000 {
- compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
+ uart6: serial@22a0000 {
+ compatible = "fsl,imx6sx-uart",
+ "fsl,imx6q-uart", "fsl,imx21-uart";
reg = <0x022a0000 0x4000>;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SX_CLK_UART_IPG>,
status = "disabled";
};
- pwm5: pwm@022a4000 {
+ pwm5: pwm@22a4000 {
compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
reg = <0x022a4000 0x4000>;
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
#pwm-cells = <2>;
};
- pwm6: pwm@022a8000 {
+ pwm6: pwm@22a8000 {
compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
reg = <0x022a8000 0x4000>;
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
#pwm-cells = <2>;
};
- pwm7: pwm@022ac000 {
+ pwm7: pwm@22ac000 {
compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
reg = <0x022ac000 0x4000>;
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
#pwm-cells = <2>;
};
- pwm8: pwm@0022b0000 {
+ pwm8: pwm@22b0000 {
compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
reg = <0x0022b0000 0x4000>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
};
};
- pcie: pcie@0x08000000 {
+ pcie: pcie@8ffc000 {
compatible = "fsl,imx6sx-pcie", "snps,dw-pcie";
- reg = <0x08ffc000 0x4000>; /* DBI */
+ reg = <0x08ffc000 0x04000>, <0x08f00000 0x80000>;
+ reg-names = "dbi", "config";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
- /* configuration space */
- ranges = <0x00000800 0 0x08f00000 0x08f00000 0 0x00080000
- /* downstream I/O */
- 0x81000000 0 0 0x08f80000 0 0x00010000
- /* non-prefetchable memory */
- 0x82000000 0 0x08000000 0x08000000 0 0x00f00000>;
+ bus-range = <0x00 0xff>;
+ ranges = <0x81000000 0 0 0x08f80000 0 0x00010000 /* downstream I/O */
+ 0x82000000 0 0x08000000 0x08000000 0 0x00f00000>; /* non-prefetchable memory */
num-lanes = <1>;
- interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX6SX_CLK_PCIE_REF_125M>,
- <&clks IMX6SX_CLK_PCIE_AXI>,
+ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SX_CLK_PCIE_AXI>,
<&clks IMX6SX_CLK_LVDS1_OUT>,
+ <&clks IMX6SX_CLK_PCIE_REF_125M>,
<&clks IMX6SX_CLK_DISPLAY_AXI>;
- clock-names = "pcie_ref_125m", "pcie_axi",
- "lvds_gate", "display_axi";
+ clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_inbound_axi";
+ power-domains = <&pd_disp>, <&pd_pci>;
+ power-domain-names = "pcie", "pcie_phy";
status = "disabled";
};
};
-
- gpu-subsystem {
- compatible = "fsl,imx-gpu-subsystem";
- cores = <&gpu>;
- };
};
u-boot,dm-pre-reloc;
display0: display@0 {
- bits-per-pixel = <16>;
+ bits-per-pixel = <24>;
bus-width = <24>;
display-timings {
u-boot,dm-spl;
};
+&pinctrl_usdhc1 {
+ u-boot,dm-spl;
+};
+
&pinctrl_usdhc2 {
u-boot,dm-spl;
};
&fec1 {
fsl,magic-packet;
- fsl,rgmii_rxc_dly;
- fsl,rgmii_txc_dly;
phy-handle = <ðphy0>;
phy-mode = "rgmii";
phy-supply = <®_ethphy>;
pinctrl-0 = <&pinctrl_fec1>;
phy-mode = "rgmii-id";
phy-handle = <ðphy0>;
+ phy-reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
+ phy-reset-duration = <10>;
fsl,magic-packet;
status = "okay";
obj-y += cpu.o iomux.o misc.o lowlevel_init.o
obj-$(CONFIG_OF_SYSTEM_SETUP) += fdt.o
+obj-$(CONFIG_AHAB_BOOT) += ahab.o
ifdef CONFIG_SPL_BUILD
obj-$(CONFIG_SPL_LOAD_IMX_CONTAINER) += image.o parse-container.o
};
#elif defined(CONFIG_IMX8MM) || defined(CONFIG_IMX8MN)
static struct clk_root_map root_array[] = {
+ {ARM_A53_CLK_ROOT, CORE_CLOCK_SLICE, 0,
+ {OSC_24M_CLK, ARM_PLL_CLK, SYSTEM_PLL2_500M_CLK,
+ SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL1_400M_CLK, AUDIO_PLL1_CLK, SYSTEM_PLL3_CLK}
+ },
{NAND_USDHC_BUS_CLK_ROOT, BUS_CLOCK_SLICE, 2,
{OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_133M_CLK,
bool "MediaTek MT7629 SoC"
select CPU_V7A
select SPL
+ select BINMAN
help
The MediaTek MT7629 is a ARM-based SoC with a dual-core Cortex-A7
including DDR3, crypto engine, 3x3 11n/ac Wi-Fi, Gigabit Ethernet,
return cpu_intel_get_info(info, INTEL_BCLK_MHZ);
}
-static int apl_get_count(struct udevice *dev)
-{
- return 4;
-}
-
static const struct cpu_ops cpu_x86_apl_ops = {
.get_desc = cpu_x86_get_desc,
.get_info = apl_get_info,
- .get_count = apl_get_count,
+ .get_count = cpu_x86_get_count,
.get_vendor = cpu_x86_get_vendor,
};
return 0;
}
-static int cpu_x86_get_count(struct udevice *dev)
+int cpu_x86_get_count(struct udevice *dev)
{
int node, cpu;
int num = 0;
struct p2sb_platdata {
#if CONFIG_IS_ENABLED(OF_PLATDATA)
- struct dtd_intel_apl_p2sb dtplat;
+ struct dtd_intel_p2sb dtplat;
#endif
ulong mmio_base;
pci_dev_t bdf;
#define P2SB_HPTC_ADDRESS_SELECT_3 (3 << 0)
/*
- * apl_p2sb_early_init() - Enable decoding for HPET range
+ * p2sb_early_init() - Enable decoding for HPET range
*
* This is needed by FSP-M which uses the High Precision Event Timer.
*
* @dev: P2SB device
* @return 0 if OK, -ve on error
*/
-static int apl_p2sb_early_init(struct udevice *dev)
+static int p2sb_early_init(struct udevice *dev)
{
struct p2sb_platdata *plat = dev_get_platdata(dev);
pci_dev_t pdev = plat->bdf;
return 0;
}
-static int apl_p2sb_spl_init(struct udevice *dev)
+static int p2sb_spl_init(struct udevice *dev)
{
/* Enable decoding for HPET. Needed for FSP global pointer storage */
dm_pci_write_config(dev, P2SB_HPTC, P2SB_HPTC_ADDRESS_SELECT_0 |
return 0;
}
-int apl_p2sb_ofdata_to_platdata(struct udevice *dev)
+int p2sb_ofdata_to_platdata(struct udevice *dev)
{
struct p2sb_uc_priv *upriv = dev_get_uclass_priv(dev);
struct p2sb_platdata *plat = dev_get_platdata(dev);
return 0;
}
-static int apl_p2sb_probe(struct udevice *dev)
+static int p2sb_probe(struct udevice *dev)
{
if (spl_phase() == PHASE_TPL) {
- return apl_p2sb_early_init(dev);
+ return p2sb_early_init(dev);
} else {
struct p2sb_platdata *plat = dev_get_platdata(dev);
return -EINVAL;
if (spl_phase() == PHASE_SPL)
- return apl_p2sb_spl_init(dev);
+ return p2sb_spl_init(dev);
}
return 0;
return 0;
}
-static const struct udevice_id apl_p2sb_ids[] = {
- { .compatible = "intel,apl-p2sb" },
+static const struct udevice_id p2sb_ids[] = {
+ { .compatible = "intel,p2sb" },
{ }
};
-U_BOOT_DRIVER(apl_p2sb_drv) = {
- .name = "intel_apl_p2sb",
+U_BOOT_DRIVER(p2sb_drv) = {
+ .name = "intel_p2sb",
.id = UCLASS_P2SB,
- .of_match = apl_p2sb_ids,
- .probe = apl_p2sb_probe,
- .ofdata_to_platdata = apl_p2sb_ofdata_to_platdata,
+ .of_match = p2sb_ids,
+ .probe = p2sb_probe,
+ .ofdata_to_platdata = p2sb_ofdata_to_platdata,
.platdata_auto_alloc_size = sizeof(struct p2sb_platdata),
.per_child_platdata_auto_alloc_size =
sizeof(struct p2sb_child_platdata),
movl %cr0, %eax
orl $(X86_CR0_NW | X86_CR0_CD), %eax
movl %eax, %cr0
- invd
+ wbinvd
/*
* Zero the BIST (Built-In Self Test) value since we don't have it.
movl %cr0, %eax
orl $(X86_CR0_NW | X86_CR0_CD), %eax
movl %eax, %cr0
- invd
+ wbinvd
/* load the temporary Global Descriptor Table */
data32 cs lidt idt_ptr
p2sb: p2sb@d,0 {
u-boot,dm-pre-reloc;
reg = <0x02006810 0 0 0 0>;
- compatible = "intel,apl-p2sb";
+ compatible = "intel,p2sb";
early-regs = <IOMAP_P2SB_BAR 0x100000>;
n {
*/
int cpu_x86_get_desc(struct udevice *dev, char *buf, int size);
+/**
+ * cpu_x86_get_count() - Get the number of cores for an x86 CPU
+ *
+ * This function is suitable to use as the get_count() method for
+ * the CPU uclass.
+ *
+ * @dev: Device to check (UCLASS_CPU)
+ * @return: Number of cores if successful,
+ * -ENOENT if not "/cpus" entry is found in the device tree
+ */
+int cpu_x86_get_count(struct udevice *dev);
+
/**
* cpu_x86_get_vendor() - Get a vendor string for an x86 CPU
*
* memory map cannot be read.
*/
ret = uclass_find_first_device(UCLASS_SPI_FLASH, &dev);
+ if (!ret && !dev)
+ ret = -ENODEV;
if (ret)
return log_msg_ret("Cannot find SPI flash\n", ret);
ret = dm_spi_get_mmap(dev, &map_base, &map_size, &offset);
#include <miiphy.h>
#include <lcd.h>
#include <led.h>
+#include <power/pmic.h>
+#include <power/regulator.h>
+#include <power/da9063_pmic.h>
#include <splash.h>
#include <video_fb.h>
}
}
+#if defined(CONFIG_DM_PMIC_DA9063)
+/*
+ * On the aristainetos2c boards the PMIC needs to be initialized,
+ * because the Ethernet PHY uses a different regulator that is not
+ * setup per hardware default. This does not influence the other versions
+ * as this regulator isn't used there at all.
+ *
+ * Unfortunately we have not yet a interface to setup all
+ * values we need.
+ */
+static int setup_pmic_voltages(void)
+{
+ struct udevice *dev;
+ int off;
+ int ret;
+
+ off = fdt_path_offset(gd->fdt_blob, "pmic0");
+ if (off < 0) {
+ printf("%s: No pmic path offset\n", __func__);
+ return off;
+ }
+
+ ret = uclass_get_device_by_of_offset(UCLASS_PMIC, off, &dev);
+ if (ret) {
+ printf("%s: Could not find PMIC\n", __func__);
+ return ret;
+ }
+
+ pmic_reg_write(dev, DA9063_REG_PAGE_CON, 0x01);
+ pmic_reg_write(dev, DA9063_REG_BPRO_CFG, 0xc1);
+ ret = pmic_reg_read(dev, DA9063_REG_BUCK_ILIM_B);
+ if (ret < 0) {
+ printf("%s: error %d get register\n", __func__, ret);
+ return ret;
+ }
+ ret &= 0xf0;
+ ret |= 0x09;
+ pmic_reg_write(dev, DA9063_REG_BUCK_ILIM_B, ret);
+ pmic_reg_write(dev, DA9063_REG_VBPRO_A, 0x43);
+ pmic_reg_write(dev, DA9063_REG_VBPRO_B, 0xc3);
+
+ return 0;
+}
+#else
+static int setup_pmic_voltages(void)
+{
+ return 0;
+}
+#endif
+
int board_late_init(void)
{
int x, y;
else
env_set("board_type", ARI_BT_7);
+ if (setup_pmic_voltages())
+ printf("Error setup PMIC\n");
+
return 0;
}
}
#ifdef CONFIG_FEC_MXC
-#define FEC_RST_PAD IMX_GPIO_NR(1, 9)
-static iomux_v3_cfg_t const fec1_rst_pads[] = {
- IMX8MQ_PAD_GPIO1_IO09__GPIO1_IO9 | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-static void setup_iomux_fec(void)
-{
- imx_iomux_v3_setup_multiple_pads(fec1_rst_pads,
- ARRAY_SIZE(fec1_rst_pads));
-
- gpio_request(IMX_GPIO_NR(1, 9), "fec1_rst");
- gpio_direction_output(IMX_GPIO_NR(1, 9), 0);
- udelay(500);
- gpio_direction_output(IMX_GPIO_NR(1, 9), 1);
-}
-
static int setup_fec(void)
{
struct iomuxc_gpr_base_regs *gpr =
(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
- setup_iomux_fec();
-
/* Use 125M anatop REF_CLK1 for ENET1, not from external */
clrsetbits_le32(&gpr->gpr[1], BIT(13) | BIT(17), 0);
return set_clk_enet(ENET_125MHZ);
i.MX8QXP MEK BOARD
M: Peng Fan <peng.fan@nxp.com>
+M: Fabio Estevam <festevam@gmail.com>
S: Maintained
F: board/freescale/imx8qxp_mek/
F: include/configs/imx8qxp_mek.h
#include <mmc.h>
#include <fsl_esdhc_imx.h>
#include <miiphy.h>
-#include <netdev.h>
#include <asm/arch/sys_proto.h>
#include <i2c.h>
#include <input.h>
IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
};
-static iomux_v3_cfg_t const enet_pads[] = {
- IOMUX_PADS(PAD_KEY_COL1__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_KEY_COL2__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
-};
/* I2C2 PMIC, iPod, Tuner, Codec, Touch, HDMI EDID, MIPI CSI2 card */
static struct i2c_pads_info mx6q_i2c_pad_info1 = {
}
#endif
-static void setup_iomux_enet(void)
-{
- SETUP_IOMUX_PADS(enet_pads);
-}
static iomux_v3_cfg_t const usdhc3_pads[] = {
IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
}
#endif
-static void setup_fec(void)
-{
- if (is_mx6dqp()) {
- /*
- * select ENET MAC0 TX clock from PLL
- */
- imx_iomux_set_gpr_register(5, 9, 1, 1);
- enable_fec_anatop_clock(0, ENET_125MHZ);
- }
-
- setup_iomux_enet();
-}
-
-int board_eth_init(bd_t *bis)
-{
- setup_fec();
-
- return cpu_eth_init(bis);
-}
-
u32 get_board_rev(void)
{
int rev = nxp_board_rev();
#include <mmc.h>
#include <fsl_esdhc_imx.h>
#include <miiphy.h>
-#include <netdev.h>
#include <asm/arch/mxc_hdmi.h>
#include <asm/arch/crm_regs.h>
#include <asm/io.h>
PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
- PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
-
#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
};
-static iomux_v3_cfg_t const enet_pads[] = {
- IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- /* AR8031 PHY Reset */
- IOMUX_PADS(PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)),
-};
-
-static void setup_iomux_enet(void)
-{
- SETUP_IOMUX_PADS(enet_pads);
-}
-
static iomux_v3_cfg_t const usdhc2_pads[] = {
IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
return 1;
}
-int board_eth_init(bd_t *bis)
-{
- setup_iomux_enet();
-
- return cpu_eth_init(bis);
-}
-
#ifdef CONFIG_USB_EHCI_MX6
static void setup_usb(void)
{
#include <fsl_esdhc_imx.h>
#include <i2c.h>
#include <mmc.h>
-#include <netdev.h>
#include <power/pmic.h>
#include <power/pfuze100_pmic.h>
#include "../common/pfuze.h"
};
#endif
-static iomux_v3_cfg_t const fec_pads[] = {
- MX6_PAD_FEC_MDC__FEC_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_FEC_MDIO__FEC_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_FEC_CRS_DV__FEC_RX_DV | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_FEC_RXD0__FEC_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_FEC_RXD1__FEC_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_FEC_TX_EN__FEC_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_FEC_TXD0__FEC_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_FEC_TXD1__FEC_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_FEC_REF_CLK__FEC_REF_OUT | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_FEC_RX_ER__GPIO_4_19 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_FEC_TX_CLK__GPIO_4_21 | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
static void setup_iomux_uart(void)
{
imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
}
-static void setup_iomux_fec(void)
-{
- imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
-
- /* Power up LAN8720 PHY */
- gpio_request(ETH_PHY_POWER, "eth_pwr");
- gpio_direction_output(ETH_PHY_POWER , 1);
- udelay(15000);
-}
-
int board_mmc_get_env_dev(int devno)
{
return devno;
#endif
#ifdef CONFIG_FEC_MXC
-int board_eth_init(bd_t *bis)
-{
- setup_iomux_fec();
-
- return cpu_eth_init(bis);
-}
static int setup_fec(void)
{
MX7DSABRESD BOARD
M: Adrian Alonso <adrian.alonso@nxp.com>
+M: Fabio Estevam <festevam@gmail.com>
S: Maintained
F: board/freescale/mx7dsabresd
F: include/configs/mx7dsabresd.h
F: arch/arm/dts/fsl-imx8-apalis-u-boot.dtsi
F: board/toradex/apalis-imx8/
F: configs/apalis-imx8qm_defconfig
+F: doc/board/toradex/apalix-imx8.rst
F: include/configs/apalis-imx8.h
+++ /dev/null
-U-Boot for the Toradex Apalis iMX8QM V1.0B Module
-
-Quick Start
-===========
-
-- Build the ARM trusted firmware binary
-- Get scfw_tcm.bin and ahab-container.img
-- Build U-Boot
-- Load U-Boot binary using uuu
-- Flash U-Boot binary into the eMMC
-- Boot
-
-Get and Build the ARM Trusted Firmware
-======================================
-
-$ git clone -b imx_4.14.78_1.0.0_ga https://source.codeaurora.org/external/imx/imx-atf
-$ cd imx-atf/
-$ make PLAT=imx8qm bl31
-
-Get scfw_tcm.bin and ahab-container.img
-=======================================
-
-$ wget https://github.com/toradex/meta-fsl-bsp-release/blob/toradex-sumo-4.14.78-1.0.0_ga-bringup/imx/meta-bsp/recipes-bsp/imx-sc-firmware/files/mx8qm-apalis-scfw-tcm.bin?raw=true
-$ mv mx8qm-apalis-scfw-tcm.bin\?raw\=true mx8qm-apalis-scfw-tcm.bin
-$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.0.bin
-$ chmod +x firmware-imx-8.0.bin
-$ ./firmware-imx-8.0.bin
-
-Copy the following binaries to the U-Boot folder:
-
-$ cp imx-atf/build/imx8qm/release/bl31.bin .
-$ cp u-boot/u-boot.bin .
-
-Copy the following firmware to the U-Boot folder:
-
-$ cp firmware-imx-8.0/firmware/seco/ahab-container.img .
-
-Build U-Boot
-============
-
-$ make apalis-imx8qm_defconfig
-$ make u-boot-dtb.imx
-
-Load the U-Boot Binary Using UUU
-================================
-
-Get the latest version of the universal update utility (uuu) aka mfgtools 3.0:
-
-https://community.nxp.com/external-link.jspa?url=https%3A%2F%2Fgithub.com%2FNXPmicro%2Fmfgtools%2Freleases
-
-Put the module into USB recovery aka serial downloader mode, connect USB device
-to your host and execute uuu:
-
-sudo ./uuu u-boot/u-boot-dtb.imx
-
-Flash the U-Boot Binary into the eMMC
-=====================================
-
-Burn the u-boot-dtb.imx binary to the primary eMMC hardware boot area partition:
-
-load mmc 1:1 $loadaddr u-boot-dtb.imx
-setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt ${blkcnt} / 0x200
-mmc dev 0 1
-mmc write ${loadaddr} 0x0 ${blkcnt}
-
-Boot
F: arch/arm/dts/fsl-imx8x-colibri-u-boot.dtsi
F: board/toradex/colibri-imx8x/
F: configs/colibri-imx8qxp_defconfig
+F: doc/board/toradex/colibri-imx8x.rst
F: include/configs/colibri-imx8x.h
+++ /dev/null
-U-Boot for the Toradex Colibri iMX8QXP V1.0B Module
-
-Quick Start
-===========
-
-- Build the ARM trusted firmware binary
-- Get scfw_tcm.bin and ahab-container.img
-- Build U-Boot
-- Load U-Boot binary using uuu
-- Flash U-Boot binary into the eMMC
-- Boot
-
-Get and Build the ARM Trusted Firmware
-======================================
-
-$ git clone -b imx_4.14.78_1.0.0_ga https://source.codeaurora.org/external/imx/imx-atf
-$ cd imx-atf/
-$ make PLAT=imx8qxp bl31
-
-Get scfw_tcm.bin and ahab-container.img
-=======================================
-
-$ wget https://github.com/toradex/meta-fsl-bsp-release/blob/toradex-sumo-4.14.78-1.0.0_ga-bringup/imx/meta-bsp/recipes-bsp/imx-sc-firmware/files/mx8qx-colibri-scfw-tcm.bin?raw=true
-$ mv mx8qx-colibri-scfw-tcm.bin\?raw\=true mx8qx-colibri-scfw-tcm.bin
-$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.0.bin
-$ chmod +x firmware-imx-8.0.bin
-$ ./firmware-imx-8.0.bin
-
-Copy the following binaries to the U-Boot folder:
-
-$ cp imx-atf/build/imx8qxp/release/bl31.bin .
-$ cp u-boot/u-boot.bin .
-
-Copy the following firmware to the U-Boot folder:
-
-$ cp firmware-imx-8.0/firmware/seco/ahab-container.img .
-
-Build U-Boot
-============
-
-$ make colibri-imx8qxp_defconfig
-$ make u-boot-dtb.imx
-
-Load the U-Boot Binary Using UUU
-================================
-
-Get the latest version of the universal update utility (uuu) aka mfgtools 3.0:
-
-https://community.nxp.com/external-link.jspa?url=https%3A%2F%2Fgithub.com%2FNXPmicro%2Fmfgtools%2Freleases
-
-Put the module into USB recovery aka serial downloader mode, connect USB device
-to your host and execute uuu:
-
-sudo ./uuu u-boot/u-boot-dtb.imx
-
-Flash the U-Boot Binary into the eMMC
-=====================================
-
-Burn the u-boot-dtb.imx binary to the primary eMMC hardware boot area partition:
-
-load mmc 1:1 $loadaddr u-boot-dtb.imx
-setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt ${blkcnt} / 0x200
-mmc dev 0 1
-mmc write ${loadaddr} 0x0 ${blkcnt}
-
-Boot
W: https://www.toradex.com/community
S: Maintained
F: board/toradex/colibri_imx7/
+F: doc/board/toradex/colibri_imx7.rst
F: include/configs/colibri_imx7.h
F: configs/colibri_imx7_defconfig
F: configs/colibri_imx7_emmc_defconfig
F: arch/arm/dts/imx8mm-verdin-u-boot.dtsi
F: board/toradex/verdin-imx8mm/
F: configs/verdin-imx8mm_defconfig
+F: doc/board/toradex/verdin-imx8mm.rst
F: include/configs/verdin-imx8mm.h
+++ /dev/null
-U-Boot for the Toradex Verdin iMX8M Mini Module
-
-Quick Start
-===========
-
-- Build the ARM trusted firmware binary
-- Get the DDR firmware
-- Build U-Boot
-- Flash to eMMC
-- Boot
-
-Get and Build the ARM Trusted Firmware (Trusted Firmware A)
-===========================================================
-
-$ echo "Downloading and building TF-A..."
-$ git clone -b imx_4.14.98_2.3.0 https://source.codeaurora.org/external/imx/imx-atf
-$ cd imx-atf
-
-Please edit `plat/imx/imx8mm/include/platform_def.h` so it contains proper
-values for UART configuration and BL31 base address (correct values listed
-below):
-#define BL31_BASE 0x910000
-#define IMX_BOOT_UART_BASE 0x30860000
-#define DEBUG_CONSOLE 1
-
-Then build ATF (TF-A):
-$ make PLAT=imx8mm bl31
-
-Get the DDR Firmware
-====================
-
-$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.4.1.bin
-$ chmod +x firmware-imx-8.4.1.bin
-$ ./firmware-imx-8.4.1.bin
-$ cp firmware-imx-8.4.1/firmware/ddr/synopsys/lpddr4*.bin ./
-
-Build U-Boot
-============
-
-$ export CROSS_COMPILE=aarch64-linux-gnu-
-$ make verdin-imx8mm_defconfig
-$ make flash.bin
-
-Flash to eMMC
-=============
-
-> tftpboot ${loadaddr} flash.bin
-> setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt ${blkcnt} / 0x200
-> mmc dev 0 1 && mmc write ${loadaddr} 0x2 ${blkcnt}
-
-As a convenience, instead of the last two commands one may also use the update
-U-Boot wrapper:
-> run update_uboot
-
-Boot
-====
-
-ATF, U-boot proper and u-boot.dtb images are packed into FIT image,
-which is loaded and parsed by SPL.
-
-Boot sequence is:
-SPL ---> ATF (TF-A) ---> U-boot proper
-
-Output:
-U-Boot SPL 2020.01-00187-gd411d164e5 (Jan 26 2020 - 04:47:26 +0100)
-Normal Boot
-Trying to boot from MMC1
-NOTICE: Configuring TZASC380
-NOTICE: RDC off
-NOTICE: BL31: v2.0(release):rel_imx_4.14.98_2.3.0-0-g09c5cc994-dirty
-NOTICE: BL31: Built : 01:11:41, Jan 25 2020
-NOTICE: sip svc init
-
-
-U-Boot 2020.01-00187-gd411d164e5 (Jan 26 2020 - 04:47:26 +0100)
-
-CPU: Freescale i.MX8MMQ rev1.0 at 0 MHz
-Reset cause: POR
-DRAM: 2 GiB
-MMC: FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2
-Loading Environment from MMC... OK
-In: serial
-Out: serial
-Err: serial
-Model: Toradex Verdin iMX8M Mini Quad 2GB Wi-Fi / BT IT V1.0A, Serial# 06535149
-Net: eth0: ethernet@30be0000
-Hit any key to stop autoboot: 0
-Verdin iMX8MM #
+++ /dev/null
-if TARGET_WOODBURN
-
-config SYS_BOARD
- default "woodburn"
-
-config SYS_SOC
- default "mx35"
-
-config SYS_CONFIG_NAME
- default "woodburn"
-
-endif
-
-if TARGET_WOODBURN_SD
-
-config SYS_BOARD
- default "woodburn"
-
-config SYS_SOC
- default "mx35"
-
-config SYS_CONFIG_NAME
- default "woodburn_sd"
-
-endif
+++ /dev/null
-WOODBURN BOARD
-M: Stefano Babic <sbabic@denx.de>
-S: Maintained
-F: board/woodburn/
-F: include/configs/woodburn.h
-F: configs/woodburn_defconfig
-
-WOODBURN_SD BOARD
-#M: -
-S: Maintained
-F: include/configs/woodburn_sd.h
-F: configs/woodburn_sd_defconfig
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
-#
-# (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
-
-obj-y := woodburn.o
-obj-y += lowlevel_init.o
+++ /dev/null
-BOOT_FROM sd
-
-/* DDR2 init */
-DATA 4 0xB8001010 0x00000304
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
- *
- * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
- *
- * Copyright (C) 2011, Stefano Babic <sbabic@denx.de>
- */
-
-#include <config.h>
-#include <asm/arch/lowlevel_macro.S>
-
-.globl lowlevel_init
-lowlevel_init:
-
- core_init
-
- init_aips
-
- init_max
-
- init_m3if
-
- mov pc, lr
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2012, Stefano Babic <sbabic@denx.de>
- *
- * Based on flea3.c and mx35pdk.c
- */
-
-#include <common.h>
-#include <init.h>
-#include <asm/io.h>
-#include <linux/errno.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/crm_regs.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/iomux-mx35.h>
-#include <i2c.h>
-#include <power/pmic.h>
-#include <fsl_pmic.h>
-#include <mc13892.h>
-#include <mmc.h>
-#include <fsl_esdhc_imx.h>
-#include <linux/types.h>
-#include <asm/gpio.h>
-#include <asm/arch/sys_proto.h>
-#include <netdev.h>
-#include <spl.h>
-
-#define CCM_CCMR_CONFIG 0x003F4208
-
-#define ESDCTL_DDR2_CONFIG 0x007FFC3F
-
-/* For MMC */
-#define GPIO_MMC_CD 7
-#define GPIO_MMC_WP 8
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int dram_init(void)
-{
- gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1,
- PHYS_SDRAM_1_SIZE);
-
- return 0;
-}
-
-static void board_setup_sdram(void)
-{
- struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR;
-
- /* Initialize with default values both CSD0/1 */
- writel(0x2000, &esdc->esdctl0);
- writel(0x2000, &esdc->esdctl1);
-
- mx3_setup_sdram_bank(CSD0_BASE_ADDR, ESDCTL_DDR2_CONFIG,
- 13, 10, 2, 0x8080);
-}
-
-static void setup_iomux_fec(void)
-{
- static const iomux_v3_cfg_t fec_pads[] = {
- MX35_PAD_FEC_TX_CLK__FEC_TX_CLK,
- MX35_PAD_FEC_RX_CLK__FEC_RX_CLK,
- MX35_PAD_FEC_RX_DV__FEC_RX_DV,
- MX35_PAD_FEC_COL__FEC_COL,
- MX35_PAD_FEC_RDATA0__FEC_RDATA_0,
- MX35_PAD_FEC_TDATA0__FEC_TDATA_0,
- MX35_PAD_FEC_TX_EN__FEC_TX_EN,
- MX35_PAD_FEC_MDC__FEC_MDC,
- MX35_PAD_FEC_MDIO__FEC_MDIO,
- MX35_PAD_FEC_TX_ERR__FEC_TX_ERR,
- MX35_PAD_FEC_RX_ERR__FEC_RX_ERR,
- MX35_PAD_FEC_CRS__FEC_CRS,
- MX35_PAD_FEC_RDATA1__FEC_RDATA_1,
- MX35_PAD_FEC_TDATA1__FEC_TDATA_1,
- MX35_PAD_FEC_RDATA2__FEC_RDATA_2,
- MX35_PAD_FEC_TDATA2__FEC_TDATA_2,
- MX35_PAD_FEC_RDATA3__FEC_RDATA_3,
- MX35_PAD_FEC_TDATA3__FEC_TDATA_3,
- };
-
- /* setup pins for FEC */
- imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
-}
-
-int woodburn_init(void)
-{
- struct ccm_regs *ccm =
- (struct ccm_regs *)IMX_CCM_BASE;
-
- /* initialize PLL and clock configuration */
- writel(CCM_CCMR_CONFIG, &ccm->ccmr);
-
- /* Set-up RAM */
- board_setup_sdram();
-
- /* enable clocks */
- writel(readl(&ccm->cgr0) |
- MXC_CCM_CGR0_EMI_MASK |
- MXC_CCM_CGR0_EDIO_MASK |
- MXC_CCM_CGR0_EPIT1_MASK,
- &ccm->cgr0);
-
- writel(readl(&ccm->cgr1) |
- MXC_CCM_CGR1_FEC_MASK |
- MXC_CCM_CGR1_GPIO1_MASK |
- MXC_CCM_CGR1_GPIO2_MASK |
- MXC_CCM_CGR1_GPIO3_MASK |
- MXC_CCM_CGR1_I2C1_MASK |
- MXC_CCM_CGR1_I2C2_MASK |
- MXC_CCM_CGR1_I2C3_MASK,
- &ccm->cgr1);
-
- /* Set-up NAND */
- __raw_writel(readl(&ccm->rcsr) | MXC_CCM_RCSR_NFC_FMS, &ccm->rcsr);
-
- /* Set pinmux for the required peripherals */
- setup_iomux_fec();
-
- /* setup GPIO1_4 FEC_ENABLE signal */
- imx_iomux_v3_setup_pad(MX35_PAD_SCKR__GPIO1_4);
- gpio_direction_output(4, 1);
- imx_iomux_v3_setup_pad(MX35_PAD_HCKT__GPIO1_9);
- gpio_direction_output(9, 1);
-
- return 0;
-}
-
-#if defined(CONFIG_SPL_BUILD)
-void board_init_f(ulong dummy)
-{
- /* Set the stack pointer. */
- asm volatile("mov sp, %0\n" : : "r"(CONFIG_SPL_STACK));
-
- /* Initialize MUX and SDRAM */
- woodburn_init();
-
- /* Clear the BSS. */
- memset(__bss_start, 0, __bss_end - __bss_start);
-
- preloader_console_init();
- timer_init();
-
- board_init_r(NULL, 0);
-}
-
-void spl_board_init(void)
-{
-}
-
-#endif
-
-
-/* Booting from NOR in external mode */
-int board_early_init_f(void)
-{
- return woodburn_init();
-}
-
-
-int board_init(void)
-{
- struct pmic *p;
- u32 val;
- int ret;
-
- /* address of boot parameters */
- gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
-
- ret = pmic_init(I2C_PMIC);
- if (ret)
- return ret;
-
- p = pmic_get("FSL_PMIC");
-
- /*
- * Set switchers in Auto in NORMAL mode & STANDBY mode
- * Setup the switcher mode for SW1 & SW2
- */
- pmic_reg_read(p, REG_SW_4, &val);
- val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) |
- (SWMODE_MASK << SWMODE2_SHIFT)));
- val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) |
- (SWMODE_AUTO_AUTO << SWMODE2_SHIFT);
- /* Set SWILIMB */
- val |= (1 << 22);
- pmic_reg_write(p, REG_SW_4, val);
-
- /* Setup the switcher mode for SW3 & SW4 */
- pmic_reg_read(p, REG_SW_5, &val);
- val &= ~((SWMODE_MASK << SWMODE4_SHIFT) |
- (SWMODE_MASK << SWMODE3_SHIFT));
- val |= (SWMODE_AUTO_AUTO << SWMODE4_SHIFT) |
- (SWMODE_AUTO_AUTO << SWMODE3_SHIFT);
- pmic_reg_write(p, REG_SW_5, val);
-
- /* Set VGEN1 to 3.15V */
- pmic_reg_read(p, REG_SETTING_0, &val);
- val &= ~(VGEN1_MASK);
- val |= VGEN1_3_15;
- pmic_reg_write(p, REG_SETTING_0, val);
-
- pmic_reg_read(p, REG_MODE_0, &val);
- val |= VGEN1EN;
- pmic_reg_write(p, REG_MODE_0, val);
- udelay(2000);
-
- return 0;
-}
-
-#if defined(CONFIG_FSL_ESDHC_IMX)
-struct fsl_esdhc_cfg esdhc_cfg = {MMC_SDHC1_BASE_ADDR};
-
-int board_mmc_init(bd_t *bis)
-{
- static const iomux_v3_cfg_t sdhc1_pads[] = {
- MX35_PAD_SD1_CMD__ESDHC1_CMD,
- MX35_PAD_SD1_CLK__ESDHC1_CLK,
- MX35_PAD_SD1_DATA0__ESDHC1_DAT0,
- MX35_PAD_SD1_DATA1__ESDHC1_DAT1,
- MX35_PAD_SD1_DATA2__ESDHC1_DAT2,
- MX35_PAD_SD1_DATA3__ESDHC1_DAT3,
- };
-
- /* configure pins for SDHC1 only */
- imx_iomux_v3_setup_multiple_pads(sdhc1_pads, ARRAY_SIZE(sdhc1_pads));
-
- /* MMC Card Detect on GPIO1_7 */
- imx_iomux_v3_setup_pad(MX35_PAD_SCKT__GPIO1_7);
- gpio_direction_input(GPIO_MMC_CD);
-
- /* MMC Write Protection on GPIO1_8 */
- imx_iomux_v3_setup_pad(MX35_PAD_FST__GPIO1_8);
- gpio_direction_input(GPIO_MMC_WP);
-
- esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
-
- return fsl_esdhc_initialize(bis, &esdhc_cfg);
-}
-
-int board_mmc_getcd(struct mmc *mmc)
-{
- return !gpio_get_value(GPIO_MMC_CD);
-}
-#endif
-
-u32 get_board_rev(void)
-{
- int rev = 0;
-
- return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
-}
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_DM_PMIC=y
+# CONFIG_SPL_PMIC_CHILDREN is not set
+CONFIG_DM_PMIC_DA9063=y
CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_DA9063=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_PWM=y
CONFIG_PWM_IMX=y
CONFIG_ARM=y
-CONFIG_SYS_ICACHE_OFF=y
-CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_IMXRT=y
CONFIG_SYS_TEXT_BASE=0x80002000
CONFIG_SPL_GPIO_SUPPORT=y
# CONFIG_VIDEO_BPP32 is not set
CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_VIDEO_IPUV3=y
+CONFIG_FEC_MXC=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
+CONFIG_RGMII=y
CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
+CONFIG_FEC_MXC=y
+CONFIG_RGMII=y
CONFIG_MII=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_USB_STORAGE=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
+CONFIG_DM_ETH=y
+CONFIG_FEC_MXC=y
+CONFIG_PHY_SMSC=y
CONFIG_PHYLIB=y
CONFIG_MII=y
CONFIG_PCI=y
+CONFIG_DM_PCI=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_DM_PMIC=y
CONFIG_DM_GPIO=y
CONFIG_TARGET_MX7DSABRESD=y
CONFIG_NR_DRAM_BANKS=1
-CONFIG_ARMV7_BOOT_SEC_DEFAULT=y
# CONFIG_ARMV7_VIRT is not set
CONFIG_IMX_RDC=y
CONFIG_IMX_BOOTAUX=y
CONFIG_DM_GPIO=y
CONFIG_TARGET_MX7DSABRESD=y
CONFIG_NR_DRAM_BANKS=1
-CONFIG_ARMV7_BOOT_SEC_DEFAULT=y
# CONFIG_ARMV7_VIRT is not set
CONFIG_IMX_RDC=y
CONFIG_IMX_BOOTAUX=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,768k(uboot)ro,256K(env_redundant),256k(env),512k(dtb),6M(kernel)ro,-(rootfs) rootfstype=ubifs ubi.mtd=6 root=ubi0:rootfs"
# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_SYS_DCACHE_OFF=y
-CONFIG_TARGET_WOODBURN=y
-CONFIG_SYS_TEXT_BASE=0xA0000000
-CONFIG_ENV_SIZE=0x20000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_BOOTDELAY=3
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PROMPT="woodburn U-Boot > "
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SPI=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_DATE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nand0=mxc_nand,nor0=physmap-flash.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=mxc_nand:50m(root1),32m(rootfb),64m(pcache),64m(app1),10m(app2),-(spool);physmap-flash.0:512k(u-boot),64k(env1),64k(env2),3776k(kernel1),3776k(kernel2)"
-CONFIG_EFI_PARTITION=y
-# CONFIG_PARTITION_UUIDS is not set
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
-CONFIG_ENV_ADDR=0xA0080000
-CONFIG_ENV_ADDR_REDUND=0xA00A0000
-CONFIG_MXC_GPIO=y
-CONFIG_FSL_ESDHC_IMX=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_PROTECTION=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_NAND_MXC=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_MICREL=y
-CONFIG_PHY_MICREL_KSZ8XXX=y
-CONFIG_MII=y
-CONFIG_SPI=y
-CONFIG_MXC_SPI=y
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_SYS_DCACHE_OFF=y
-CONFIG_TARGET_WOODBURN_SD=y
-CONFIG_SYS_TEXT_BASE=0x82000000
-CONFIG_SPL_GPIO_SUPPORT=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x20000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_SPL=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
-CONFIG_SPL_TEXT_BASE=0x10002300
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/woodburn/imximage.cfg"
-CONFIG_BOOTDELAY=3
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL_BOARD_INIT=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x100
-CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PROMPT="woodburn U-Boot > "
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SPI=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_DATE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nand0=mxc_nand,nor0=physmap-flash.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=mxc_nand:50m(root1),32m(rootfb),64m(pcache),64m(app1),10m(app2),-(spool);physmap-flash.0:512k(u-boot),64k(env1),64k(env2),3776k(kernel1),3776k(kernel2)"
-CONFIG_EFI_PARTITION=y
-# CONFIG_PARTITION_UUIDS is not set
-# CONFIG_SPL_PARTITION_UUIDS is not set
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
-CONFIG_ENV_ADDR=0xA0080000
-CONFIG_ENV_ADDR_REDUND=0xA00A0000
-CONFIG_MXC_GPIO=y
-CONFIG_FSL_ESDHC_IMX=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_PROTECTION=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_NAND_MXC=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_MICREL=y
-CONFIG_PHY_MICREL_KSZ8XXX=y
-CONFIG_MII=y
-CONFIG_SPI=y
-CONFIG_MXC_SPI=y
+++ /dev/null
-!!! WARNING !!!
-
-This guide describes to the old way of doing things. No new Ethernet drivers
-should be implemented this way. All new drivers should be written against the
-U-Boot core driver model. See doc/driver-model/README.txt
-
------------------------
- Ethernet Driver Guide
------------------------
-
-The networking stack in Das U-Boot is designed for multiple network devices
-to be easily added and controlled at runtime. This guide is meant for people
-who wish to review the net driver stack with an eye towards implementing your
-own ethernet device driver. Here we will describe a new pseudo 'APE' driver.
-
-------------------
- Driver Functions
-------------------
-
-All functions you will be implementing in this document have the return value
-meaning of 0 for success and non-zero for failure.
-
- ----------
- Register
- ----------
-
-When U-Boot initializes, it will call the common function eth_initialize().
-This will in turn call the board-specific board_eth_init() (or if that fails,
-the cpu-specific cpu_eth_init()). These board-specific functions can do random
-system handling, but ultimately they will call the driver-specific register
-function which in turn takes care of initializing that particular instance.
-
-Keep in mind that you should code the driver to avoid storing state in global
-data as someone might want to hook up two of the same devices to one board.
-Any such information that is specific to an interface should be stored in a
-private, driver-defined data structure and pointed to by eth->priv (see below).
-
-So the call graph at this stage would look something like:
-board_init()
- eth_initialize()
- board_eth_init() / cpu_eth_init()
- driver_register()
- initialize eth_device
- eth_register()
-
-At this point in time, the only thing you need to worry about is the driver's
-register function. The pseudo code would look something like:
-int ape_register(bd_t *bis, int iobase)
-{
- struct ape_priv *priv;
- struct eth_device *dev;
- struct mii_dev *bus;
-
- priv = malloc(sizeof(*priv));
- if (priv == NULL)
- return -ENOMEM;
-
- dev = malloc(sizeof(*dev));
- if (dev == NULL) {
- free(priv);
- return -ENOMEM;
- }
-
- /* setup whatever private state you need */
-
- memset(dev, 0, sizeof(*dev));
- sprintf(dev->name, "APE");
-
- /*
- * if your device has dedicated hardware storage for the
- * MAC, read it and initialize dev->enetaddr with it
- */
- ape_mac_read(dev->enetaddr);
-
- dev->iobase = iobase;
- dev->priv = priv;
- dev->init = ape_init;
- dev->halt = ape_halt;
- dev->send = ape_send;
- dev->recv = ape_recv;
- dev->write_hwaddr = ape_write_hwaddr;
-
- eth_register(dev);
-
-#ifdef CONFIG_PHYLIB
- bus = mdio_alloc();
- if (!bus) {
- free(priv);
- free(dev);
- return -ENOMEM;
- }
-
- bus->read = ape_mii_read;
- bus->write = ape_mii_write;
- mdio_register(bus);
-#endif
-
- return 1;
-}
-
-The exact arguments needed to initialize your device are up to you. If you
-need to pass more/less arguments, that's fine. You should also add the
-prototype for your new register function to include/netdev.h.
-
-The return value for this function should be as follows:
-< 0 - failure (hardware failure, not probe failure)
->=0 - number of interfaces detected
-
-You might notice that many drivers seem to use xxx_initialize() rather than
-xxx_register(). This is the old naming convention and should be avoided as it
-causes confusion with the driver-specific init function.
-
-Other than locating the MAC address in dedicated hardware storage, you should
-not touch the hardware in anyway. That step is handled in the driver-specific
-init function. Remember that we are only registering the device here, we are
-not checking its state or doing random probing.
-
- -----------
- Callbacks
- -----------
-
-Now that we've registered with the ethernet layer, we can start getting some
-real work done. You will need five functions:
- int ape_init(struct eth_device *dev, bd_t *bis);
- int ape_send(struct eth_device *dev, volatile void *packet, int length);
- int ape_recv(struct eth_device *dev);
- int ape_halt(struct eth_device *dev);
- int ape_write_hwaddr(struct eth_device *dev);
-
-The init function checks the hardware (probing/identifying) and gets it ready
-for send/recv operations. You often do things here such as resetting the MAC
-and/or PHY, and waiting for the link to autonegotiate. You should also take
-the opportunity to program the device's MAC address with the dev->enetaddr
-member. This allows the rest of U-Boot to dynamically change the MAC address
-and have the new settings be respected.
-
-The send function does what you think -- transmit the specified packet whose
-size is specified by length (in bytes). You should not return until the
-transmission is complete, and you should leave the state such that the send
-function can be called multiple times in a row.
-
-The recv function should process packets as long as the hardware has them
-readily available before returning. i.e. you should drain the hardware fifo.
-For each packet you receive, you should call the net_process_received_packet() function on it
-along with the packet length. The common code sets up packet buffers for you
-already in the .bss (net_rx_packets), so there should be no need to allocate your
-own. This doesn't mean you must use the net_rx_packets array however; you're
-free to call the net_process_received_packet() function with any buffer you wish. So the pseudo
-code here would look something like:
-int ape_recv(struct eth_device *dev)
-{
- int length, i = 0;
- ...
- while (packets_are_available()) {
- ...
- length = ape_get_packet(&net_rx_packets[i]);
- ...
- net_process_received_packet(&net_rx_packets[i], length);
- ...
- if (++i >= PKTBUFSRX)
- i = 0;
- ...
- }
- ...
- return 0;
-}
-
-The halt function should turn off / disable the hardware and place it back in
-its reset state. It can be called at any time (before any call to the related
-init function), so make sure it can handle this sort of thing.
-
-The write_hwaddr function should program the MAC address stored in dev->enetaddr
-into the Ethernet controller.
-
-So the call graph at this stage would look something like:
-some net operation (ping / tftp / whatever...)
- eth_init()
- dev->init()
- eth_send()
- dev->send()
- eth_rx()
- dev->recv()
- eth_halt()
- dev->halt()
-
---------------------------------
- CONFIG_PHYLIB / CONFIG_CMD_MII
---------------------------------
-
-If your device supports banging arbitrary values on the MII bus (pretty much
-every device does), you should add support for the mii command. Doing so is
-fairly trivial and makes debugging mii issues a lot easier at runtime.
-
-After you have called eth_register() in your driver's register function, add
-a call to mdio_alloc() and mdio_register() like so:
- bus = mdio_alloc();
- if (!bus) {
- free(priv);
- free(dev);
- return -ENOMEM;
- }
-
- bus->read = ape_mii_read;
- bus->write = ape_mii_write;
- mdio_register(bus);
-
-And then define the mii_read and mii_write functions if you haven't already.
-Their syntax is straightforward:
- int mii_read(struct mii_dev *bus, int addr, int devad, int reg);
- int mii_write(struct mii_dev *bus, int addr, int devad, int reg,
- u16 val);
-
-The read function should read the register 'reg' from the phy at address 'addr'
-and return the result to its caller. The implementation for the write function
-should logically follow.
ffffffff Top of ROM (and last byte of 32-bit address space)
ffff8000 TPL loaded here (from IFWI)
ff000000 Bottom of ROM
- fefc000 Top of CAR region
+ fefc0000 Top of CAR region
fef96000 Stack for FSP-M
fef40000 59000 FSP-M
fef11000 SPL loaded here
rockchip/index
sifive/index
st/index
+ toradex/index
xilinx/index
--- /dev/null
+.. SPDX-License-Identifier: GPL-2.0+
+
+Apalis iMX8QM V1.0B Module
+==========================
+
+Quick Start
+-----------
+
+- Build the ARM trusted firmware binary
+- Get scfw_tcm.bin and ahab-container.img
+- Build U-Boot
+- Load U-Boot binary using uuu
+- Flash U-Boot binary into the eMMC
+- Boot
+
+Get and Build the ARM Trusted Firmware
+--------------------------------------
+
+.. code-block:: bash
+
+ $ git clone -b imx_4.14.78_1.0.0_ga https://source.codeaurora.org/external/imx/imx-atf
+ $ cd imx-atf/
+ $ make PLAT=imx8qm bl31
+
+Get scfw_tcm.bin and ahab-container.img
+---------------------------------------
+
+.. code-block:: bash
+
+ $ wget https://github.com/toradex/meta-fsl-bsp-release/blob/toradex-sumo-4.14.78-1.0.0_ga-bringup/imx/meta-bsp/recipes-
+ bsp/imx-sc-firmware/files/mx8qm-apalis-scfw-tcm.bin?raw=true
+ $ mv mx8qm-apalis-scfw-tcm.bin\?raw\=true mx8qm-apalis-scfw-tcm.bin
+ $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.0.bin
+ $ chmod +x firmware-imx-8.0.bin
+ $ ./firmware-imx-8.0.bin
+
+Copy the following binaries to the U-Boot folder:
+
+.. code-block:: bash
+
+ $ cp imx-atf/build/imx8qm/release/bl31.bin .
+ $ cp u-boot/u-boot.bin .
+
+Copy the following firmware to the U-Boot folder:
+
+.. code-block:: bash
+
+ $ cp firmware-imx-8.0/firmware/seco/ahab-container.img .
+
+Build U-Boot
+------------
+.. code-block:: bash
+
+ $ make apalis-imx8qm_defconfig
+ $ make u-boot-dtb.imx
+
+Load the U-Boot Binary Using UUU
+--------------------------------
+
+Get the latest version of the universal update utility (uuu) aka ``mfgtools 3.0``:
+
+https://community.nxp.com/external-link.jspa?url=https%3A%2F%2Fgithub.com%2FNXPmicro%2Fmfgtools%2Freleases
+
+Put the module into USB recovery aka serial downloader mode, connect USB device
+to your host and execute uuu:
+
+.. code-block:: bash
+
+ sudo ./uuu u-boot/u-boot-dtb.imx
+
+Flash the U-Boot Binary into the eMMC
+-------------------------------------
+
+Burn the ``u-boot-dtb.imx`` binary to the primary eMMC hardware boot area
+partition and boot:
+
+.. code-block:: bash
+
+ load mmc 1:1 $loadaddr u-boot-dtb.imx
+ setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt ${blkcnt} / 0x200
+ mmc dev 0 1
+ mmc write ${loadaddr} 0x0 ${blkcnt}
--- /dev/null
+.. SPDX-License-Identifier: GPL-2.0+
+
+Colibri iMX8QXP V1.0B Module
+============================
+
+Quick Start
+-----------
+
+- Build the ARM trusted firmware binary
+- Get scfw_tcm.bin and ahab-container.img
+- Build U-Boot
+- Load U-Boot binary using uuu
+- Flash U-Boot binary into the eMMC
+- Boot
+
+Get and Build the ARM Trusted Firmware
+--------------------------------------
+
+.. code-block:: bash
+
+ $ git clone -b imx_4.14.78_1.0.0_ga https://source.codeaurora.org/external/imx/imx-atf
+ $ cd imx-atf/
+ $ make PLAT=imx8qxp bl31
+
+Get scfw_tcm.bin and ahab-container.img
+---------------------------------------
+.. code-block:: bash
+
+ $ wget https://github.com/toradex/meta-fsl-bsp-release/blob/
+ toradex-sumo-4.14.78-1.0.0_ga-bringup/imx/meta-bsp/recipes-
+ bsp/imx-sc-firmware/files/mx8qx-colibri-scfw-tcm.bin?raw=true
+ $ mv mx8qx-colibri-scfw-tcm.bin\?raw\=true mx8qx-colibri-scfw-tcm.bin
+ $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.0.bin
+ $ chmod +x firmware-imx-8.0.bin
+ $ ./firmware-imx-8.0.bin
+
+Copy the following binaries to the U-Boot folder:
+
+.. code-block:: bash
+
+ $ cp imx-atf/build/imx8qxp/release/bl31.bin .
+ $ cp u-boot/u-boot.bin .
+
+Copy the following firmware to the U-Boot folder:
+
+.. code-block:: bash
+
+ $ cp firmware-imx-8.0/firmware/seco/ahab-container.img .
+
+Build U-Boot
+------------
+
+.. code-block:: bash
+
+ $ make colibri-imx8qxp_defconfig
+ $ make u-boot-dtb.imx
+
+Load the U-Boot Binary Using UUU
+--------------------------------
+
+Get the latest version of the universal update utility (uuu) aka ``mfgtools 3.0``:
+
+https://community.nxp.com/external-link.jspa?url=https%3A%2F%2Fgithub.com%2FNXPmicro%2Fmfgtools%2Freleases
+
+Put the module into USB recovery aka serial downloader mode, connect USB device
+to your host and execute ``uuu``:
+
+.. code-block:: bash
+
+ sudo ./uuu u-boot/u-boot-dtb.imx
+
+Flash the U-Boot Binary into the eMMC
+-------------------------------------
+
+Burn the ``u-boot-dtb.imx`` binary to the primary eMMC hardware boot area partition:
+
+.. code-block:: bash
+
+ load mmc 1:1 $loadaddr u-boot-dtb.imx
+ setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt ${blkcnt} / 0x200
+ mmc dev 0 1
+ mmc write ${loadaddr} 0x0 ${blkcnt}
--- /dev/null
+.. SPDX-License-Identifier: GPL-2.0+
+
+Colibri iMX7
+============
+
+Quick Start
+-----------
+
+- Build U-Boot
+- NAND IMX image adjustments before flashing
+- Flashing manually U-Boot to eMMC
+- Flashing manually U-Boot to NAND
+- Using ``update_uboot`` script
+
+Build U-Boot
+------------
+
+.. code-block:: bash
+
+ $ export CROSS_COMPILE=arm-linux-gnueabi-
+ $ export ARCH=arm
+ $ make colibri_imx7_emmc_defconfig # For NAND: colibri_imx7_defconfig
+ $ make
+
+After build succeeds, you will obtain final ``u-boot-dtb.imx`` IMX specific
+image, ready for flashing (but check next section for additional
+adjustments).
+
+Final IMX program image includes (section ``6.6.7`` from `IMX7DRM
+<https://www.nxp.com/webapp/Download?colCode=IMX7DRM>`_):
+
+* **Image vector table** (IVT) for BootROM
+* **Boot data** -indicates the program image location, program image size
+ in bytes, and the plugin flag.
+* **Device configuration data**
+* **User image**: U-Boot image (``u-boot-dtb.bin``)
+
+
+IMX image adjustments prior to flashing
+---------------------------------------
+
+1. U-Boot for both Colibri iMX7 NAND and eMMC versions
+is built with HABv4 support (`AN4581.pdf
+<https://www.nxp.com/docs/en/application-note/AN4581.pdf>`_)
+enabled by default, which requires to generate a proper
+Command Sequence File (CSF) by srktool from NXP (not included in the
+U-Boot tree, check additional details in introduction_habv4.txt)
+and concatenate it to the final ``u-boot-dtb.imx``.
+
+2. In case if you don't want to generate a proper ``CSF`` (for any reason),
+you still need to pad the IMX image so i has the same size as specified in
+in **Boot Data** section of IMX image.
+To obtain this value, run:
+
+.. code-block:: bash
+
+ $ od -X -N 0x30 u-boot-dtb.imx
+ 0000000 402000d1 87800000 00000000 877ff42c
+ 0000020 877ff420 877ff400 878a5000 00000000
+ ^^^^^^^^
+ 0000040 877ff000 000a8060 00000000 40b401d2
+ ^^^^^^^^ ^^^^^^^^
+
+Where:
+
+* ``877ff400`` - IVT self address
+* ``877ff000`` - Program image address
+* ``000a8060`` - Program image size
+
+To calculate the padding:
+
+* IVT offset = ``0x877ff400`` - ``0x877ff000`` = ``0x400``
+* Program image size = ``0xa8060`` - ``0x400`` = ``0xa7c60``
+
+and then pad the image:
+
+.. code-block:: bash
+
+ $ objcopy -I binary -O binary --pad-to 0xa7c60 --gap-fill=0x00 \
+ u-boot-dtb.imx u-boot-dtb.imx.zero-padded
+
+3. Also, according to requirement from ``6.6.7.1``, the final image
+should have ``0x400`` offset for initial IVT table.
+
+For eMMC setup we handle this by flashing it to ``0x400``, howewer
+for NAND setup we adjust the image prior to flashing, adding padding in the
+beginning of the image.
+
+.. code-block:: bash
+
+ $ dd if=u-boot-dtb.imx.zero-padded of=u-boot-dtb.imx.ready bs=1024 seek=1
+
+Flash U-Boot IMX image to eMMC
+------------------------------
+
+Flash the ``u-boot-dtb.imx.zero-padded`` binary to the primary eMMC hardware
+boot area partition:
+
+.. code-block:: bash
+
+
+ => load mmc 1:1 $loadaddr u-boot-dtb.imx.zero-padded
+ => setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt ${blkcnt} / 0x200
+ => mmc dev 0 1
+ => mmc write ${loadaddr} 0x2 ${blkcnt}
+
+Flash U-Boot IMX image to NAND
+------------------------------
+
+.. code-block:: bash
+
+ => load mmc 1:1 $loadaddr u-boot-dtb.imx.ready
+ => nand erase.part u-boot1
+ => nand write ${loadaddr} u-boot1 ${filesize}
+ => nand erase.part u-boot2
+ => nand write ${loadaddr} u-boot2 ${filesize}
+
+Using update_uboot script
+-------------------------
+
+You can also usb U-Boot env update_uboot script,
+which wraps all eMMC/NAND specific command invocation:
+
+.. code-block:: bash
+
+ => load mmc 1:1 $loadaddr u-boot-dtb.imx.ready
+ => run update_uboot
--- /dev/null
+.. SPDX-License-Identifier: GPL-2.0+
+
+Toradex
+=======
+
+.. toctree::
+ :maxdepth: 2
+
+ apalix-imx8
+ colibri_imx7
+ colibri-imx8x
+ verdin-imx8mm
--- /dev/null
+.. SPDX-License-Identifier: GPL-2.0+
+
+Verdin iMX8M Mini Module
+========================
+
+Quick Start
+-----------
+
+- Build the ARM trusted firmware binary
+- Get the DDR firmware
+- Build U-Boot
+- Flash to eMMC
+- Boot
+
+Get and Build the ARM Trusted Firmware (Trusted Firmware A)
+-----------------------------------------------------------
+
+.. code-block:: bash
+
+ $ echo "Downloading and building TF-A..."
+ $ git clone -b imx_4.14.98_2.3.0 \
+ https://source.codeaurora.org/external/imx/imx-atf
+ $ cd imx-atf
+
+Please edit ``plat/imx/imx8mm/include/platform_def.h`` so it contains proper
+values for UART configuration and BL31 base address (correct values listed
+below):
+
+.. code-block:: bash
+
+ #define BL31_BASE 0x910000
+ #define IMX_BOOT_UART_BASE 0x30860000
+ #define DEBUG_CONSOLE 1
+
+Then build ATF (TF-A):
+
+.. code-block:: bash
+
+ $ make PLAT=imx8mm bl31
+
+Get the DDR Firmware
+--------------------
+
+.. code-block:: bash
+
+ $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.4.1.bin
+ $ chmod +x firmware-imx-8.4.1.bin
+ $ ./firmware-imx-8.4.1.bin
+ $ cp firmware-imx-8.4.1/firmware/ddr/synopsys/lpddr4*.bin ./
+
+Build U-Boot
+------------
+.. code-block:: bash
+
+ $ export CROSS_COMPILE=aarch64-linux-gnu-
+ $ make verdin-imx8mm_defconfig
+ $ make flash.bin
+
+Flash to eMMC
+-------------
+
+.. code-block:: bash
+
+ > tftpboot ${loadaddr} flash.bin
+ > setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt ${blkcnt} / 0x200
+ > mmc dev 0 1 && mmc write ${loadaddr} 0x2 ${blkcnt}
+
+As a convenience, instead of the last two commands one may also use the update
+U-Boot wrapper:
+
+.. code-block:: bash
+
+ > run update_uboot
+
+Boot
+----
+
+ATF, U-Boot proper and u-boot.dtb images are packed into FIT image,
+which is loaded and parsed by SPL.
+
+Boot sequence is:
+
+* SPL ---> ATF (TF-A) ---> U-Boot proper
+
+Output:
+
+.. code-block:: bash
+
+ U-Boot SPL 2020.01-00187-gd411d164e5 (Jan 26 2020 - 04:47:26 +0100)
+ Normal Boot
+ Trying to boot from MMC1
+ NOTICE: Configuring TZASC380
+ NOTICE: RDC off
+ NOTICE: BL31: v2.0(release):rel_imx_4.14.98_2.3.0-0-g09c5cc994-dirty
+ NOTICE: BL31: Built : 01:11:41, Jan 25 2020
+ NOTICE: sip svc init
+
+
+ U-Boot 2020.01-00187-gd411d164e5 (Jan 26 2020 - 04:47:26 +0100)
+
+ CPU: Freescale i.MX8MMQ rev1.0 at 0 MHz
+ Reset cause: POR
+ DRAM: 2 GiB
+ MMC: FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2
+ Loading Environment from MMC... OK
+ In: serial
+ Out: serial
+ Err: serial
+ Model: Toradex Verdin iMX8M Mini Quad 2GB Wi-Fi / BT IT V1.0A, Serial:
+ Net: eth0: ethernet@30be0000
+ Hit any key to stop autoboot: 0
+ Verdin iMX8MM #
{
p2sb: p2sb@d,0 {
reg = <0x02006810 0 0 0 0>;
- compatible = "intel,apl-p2sb";
+ compatible = "intel,p2sb";
early-regs = <IOMAP_P2SB_BAR 0x100000>;
north {
+++ /dev/null
-* Texas Instruments - dp83867 Giga bit ethernet phy
-
-Required properties:
- - reg - The ID number for the phy, usually a small integer
- - ti,rx-internal-delay - RGMII Recieve Clock Delay - see dt-bindings/net/ti-dp83867.h
- for applicable values
- - ti,tx-internal-delay - RGMII Transmit Clock Delay - see dt-bindings/net/ti-dp83867.h
- for applicable values
- - ti,fifo-depth - Transmitt FIFO depth- see dt-bindings/net/ti-dp83867.h
- for applicable values
- - enet-phy-lane-swap - Indicates that PHY will swap the TX/RX lanes to
- compensate for the board being designed with the lanes swapped.
- - enet-phy-no-lane-swap - Indicates that PHY will disable swap of the
- TX/RX lanes.
- - ti,clk-output-sel - Muxing option for CLK_OUT pin. See dt-bindings/net/ti-dp83867.h
- for applicable values. The CLK_OUT pin can also
- be disabled by this property. When omitted, the
- PHY's default will be left as is.
-
-Default child nodes are standard Ethernet PHY device
-nodes as described in doc/devicetree/bindings/net/ethernet.txt
-
-Example:
-
- ethernet-phy@0 {
- reg = <0>;
- ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
- ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
- ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
- enet-phy-lane-no-swap;
- ti,clk-output-sel = <DP83867_CLK_O_SEL_CHN_A_TCLK>;
- };
-
-Datasheet can be found:
-http://www.ti.com/product/DP83867IR/datasheet
{
p2sb: p2sb@d,0 {
reg = <0x02006810 0 0 0 0>;
- compatible = "intel,apl-p2sb";
+ compatible = "intel,p2sb";
early-regs = <IOMAP_P2SB_BAR 0x100000>;
n {
--- /dev/null
+Ethernet Driver Guide
+=======================
+
+The networking stack in Das U-Boot is designed for multiple network devices
+to be easily added and controlled at runtime. This guide is meant for people
+who wish to review the net driver stack with an eye towards implementing your
+own ethernet device driver. Here we will describe a new pseudo 'APE' driver.
+
+Most existing drivers do already - and new network driver MUST - use the
+U-Boot core driver model. Generic information about this can be found in
+doc/driver-model/design.rst, this document will thus focus on the network
+specific code parts.
+Some drivers are still using the old Ethernet interface, differences between
+the two and hints about porting will be handled at the end.
+
+Driver framework
+------------------
+
+A network driver following the driver model must declare itself using
+the UCLASS_ETH .id field in the U-Boot driver struct:
+
+.. code-block:: c
+
+ U_BOOT_DRIVER(eth_ape) = {
+ .name = "eth_ape",
+ .id = UCLASS_ETH,
+ .of_match = eth_ape_ids,
+ .ofdata_to_platdata = eth_ape_ofdata_to_platdata,
+ .probe = eth_ape_probe,
+ .ops = ð_ape_ops,
+ .priv_auto_alloc_size = sizeof(struct eth_ape_priv),
+ .platdata_auto_alloc_size = sizeof(struct eth_ape_pdata),
+ .flags = DM_FLAG_ALLOC_PRIV_DMA,
+ };
+
+struct eth_ape_priv contains runtime per-instance data, like buffers, pointers
+to current descriptors, current speed settings, pointers to PHY related data
+(like struct mii_dev) and so on. Declaring its size in .priv_auto_alloc_size
+will let the driver framework allocate it at the right time.
+It can be retrieved using a dev_get_priv(dev) call.
+
+struct eth_ape_pdata contains static platform data, like the MMIO base address,
+a hardware variant, the MAC address. ``struct eth_pdata eth_pdata``
+as the first member of this struct helps to avoid duplicated code.
+If you don't need any more platform data beside the standard member,
+just use sizeof(struct eth_pdata) for the platdata_auto_alloc_size.
+
+PCI devices add a line pointing to supported vendor/device ID pairs:
+
+.. code-block:: c
+
+ static struct pci_device_id supported[] = {
+ { PCI_DEVICE(PCI_VENDOR_ID_APE, 0x4223) },
+ {}
+ };
+
+ U_BOOT_PCI_DEVICE(eth_ape, supported);
+
+It is also possible to declare support for a whole class of PCI devices::
+
+ { PCI_DEVICE_CLASS(PCI_CLASS_SYSTEM_SDHCI << 8, 0xffff00) },
+
+Device probing and instantiation will be handled by the driver model framework,
+so follow the guidelines there. The probe() function would initialise the
+platform specific parts of the hardware, like clocks, resets, GPIOs, the MDIO
+bus. Also it would take care of any special PHY setup (power rails, enable
+bits for internal PHYs, etc.).
+
+Driver methods
+----------------
+
+The real work will be done in the driver method functions the driver provides
+by defining the members of struct eth_ops:
+
+.. code-block:: c
+
+ struct eth_ops {
+ int (*start)(struct udevice *dev);
+ int (*send)(struct udevice *dev, void *packet, int length);
+ int (*recv)(struct udevice *dev, int flags, uchar **packetp);
+ int (*free_pkt)(struct udevice *dev, uchar *packet, int length);
+ void (*stop)(struct udevice *dev);
+ int (*mcast)(struct udevice *dev, const u8 *enetaddr, int join);
+ int (*write_hwaddr)(struct udevice *dev);
+ int (*read_rom_hwaddr)(struct udevice *dev);
+ };
+
+An up-to-date version of this struct together with more information can be
+found in include/net.h.
+
+Only start, stop, send and recv are required, the rest are optional and are
+handled by generic code or ignored if not provided.
+
+The **start** function initialises the hardware and gets it ready for send/recv
+operations. You often do things here such as resetting the MAC
+and/or PHY, and waiting for the link to autonegotiate. You should also take
+the opportunity to program the device's MAC address with the enetaddr member
+of the generic struct eth_pdata (which would be the first member of your
+own platdata struct). This allows the rest of U-Boot to dynamically change
+the MAC address and have the new settings be respected.
+
+The **send** function does what you think -- transmit the specified packet
+whose size is specified by length (in bytes). The packet buffer can (and
+will!) be reused for subsequent calls to send(), so it must be no longer
+used when the send() function returns. The easiest way to achieve this is
+to wait until the transmission is complete. Alternatively, if supported by
+the hardware, just waiting for the buffer to be consumed (by some DMA engine)
+might be an option as well.
+Another way of consuming the buffer could be to copy the data to be send,
+then just queue the copied packet (for instance handing it over to a DMA
+engine), and return immediately afterwards.
+In any case you should leave the state such that the send function can be
+called multiple times in a row.
+
+The **recv** function polls for availability of a new packet. If none is
+available, it must return with -EAGAIN.
+If a packet has been received, make sure it is accessible to the CPU
+(invalidate caches if needed), then write its address to the packetp pointer,
+and return the length. If there is an error (receive error, too short or too
+long packet), return 0 if you require the packet to be cleaned up normally,
+or a negative error code otherwise (cleanup not necessary or already done).
+The U-Boot network stack will then process the packet.
+
+If **free_pkt** is defined, U-Boot will call it after a received packet has
+been processed, so the packet buffer can be freed or recycled. Typically you
+would hand it back to the hardware to acquire another packet. free_pkt() will
+be called after recv(), for the same packet, so you don't necessarily need
+to infer the buffer to free from the ``packet`` pointer, but can rely on that
+being the last packet that recv() handled.
+The common code sets up packet buffers for you already in the .bss
+(net_rx_packets), so there should be no need to allocate your own. This doesn't
+mean you must use the net_rx_packets array however; you're free to use any
+buffer you wish.
+
+The **stop** function should turn off / disable the hardware and place it back
+in its reset state. It can be called at any time (before any call to the
+related start() function), so make sure it can handle this sort of thing.
+
+The (optional) **write_hwaddr** function should program the MAC address stored
+in pdata->enetaddr into the Ethernet controller.
+
+So the call graph at this stage would look something like:
+
+.. code-block:: c
+
+ (some net operation (ping / tftp / whatever...))
+ eth_init()
+ ops->start()
+ eth_send()
+ ops->send()
+ eth_rx()
+ ops->recv()
+ (process packet)
+ if (ops->free_pkt)
+ ops->free_pkt()
+ eth_halt()
+ ops->stop()
+
+
+CONFIG_PHYLIB / CONFIG_CMD_MII
+--------------------------------
+
+If your device supports banging arbitrary values on the MII bus (pretty much
+every device does), you should add support for the mii command. Doing so is
+fairly trivial and makes debugging mii issues a lot easier at runtime.
+
+In your driver's ``probe()`` function, add a call to mdio_alloc() and
+mdio_register() like so:
+
+.. code-block:: c
+
+ bus = mdio_alloc();
+ if (!bus) {
+ ...
+ return -ENOMEM;
+ }
+
+ bus->read = ape_mii_read;
+ bus->write = ape_mii_write;
+ mdio_register(bus);
+
+And then define the mii_read and mii_write functions if you haven't already.
+Their syntax is straightforward::
+
+ int mii_read(struct mii_dev *bus, int addr, int devad, int reg);
+ int mii_write(struct mii_dev *bus, int addr, int devad, int reg,
+ u16 val);
+
+The read function should read the register 'reg' from the phy at address 'addr'
+and return the result to its caller. The implementation for the write function
+should logically follow.
+
+................................................................
+
+Legacy network drivers
+------------------------
+
+!!! WARNING !!!
+
+This section below describes the old way of doing things. No new Ethernet
+drivers should be implemented this way. All new drivers should be written
+against the U-Boot core driver model, as described above.
+
+The actual callback functions are fairly similar, the differences are:
+
+- ``start()`` is called ``init()``
+- ``stop()`` is called ``halt()``
+- The ``recv()`` function must loop until all packets have been received, for
+ each packet it must call the net_process_received_packet() function,
+ handing it over the pointer and the length. Afterwards it should free
+ the packet, before checking for new data.
+
+For porting an old driver to the new driver model, split the existing recv()
+function into the actual new recv() function, just fetching **one** packet,
+remove the call to net_process_received_packet(), then move the packet
+cleanup into the ``free_pkt()`` function.
+
+Registering the driver and probing a device is handled very differently,
+follow the recommendations in the driver model design documentation for
+instructions on how to port this over. For the records, the old way of
+initialising a network driver is as follows:
+
+Old network driver registration
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+When U-Boot initializes, it will call the common function eth_initialize().
+This will in turn call the board-specific board_eth_init() (or if that fails,
+the cpu-specific cpu_eth_init()). These board-specific functions can do random
+system handling, but ultimately they will call the driver-specific register
+function which in turn takes care of initializing that particular instance.
+
+Keep in mind that you should code the driver to avoid storing state in global
+data as someone might want to hook up two of the same devices to one board.
+Any such information that is specific to an interface should be stored in a
+private, driver-defined data structure and pointed to by eth->priv (see below).
+
+So the call graph at this stage would look something like:
+
+.. code-block:: c
+
+ board_init()
+ eth_initialize()
+ board_eth_init() / cpu_eth_init()
+ driver_register()
+ initialize eth_device
+ eth_register()
+
+At this point in time, the only thing you need to worry about is the driver's
+register function. The pseudo code would look something like:
+
+.. code-block:: c
+
+ int ape_register(bd_t *bis, int iobase)
+ {
+ struct ape_priv *priv;
+ struct eth_device *dev;
+ struct mii_dev *bus;
+
+ priv = malloc(sizeof(*priv));
+ if (priv == NULL)
+ return -ENOMEM;
+
+ dev = malloc(sizeof(*dev));
+ if (dev == NULL) {
+ free(priv);
+ return -ENOMEM;
+ }
+
+ /* setup whatever private state you need */
+
+ memset(dev, 0, sizeof(*dev));
+ sprintf(dev->name, "APE");
+
+ /*
+ * if your device has dedicated hardware storage for the
+ * MAC, read it and initialize dev->enetaddr with it
+ */
+ ape_mac_read(dev->enetaddr);
+
+ dev->iobase = iobase;
+ dev->priv = priv;
+ dev->init = ape_init;
+ dev->halt = ape_halt;
+ dev->send = ape_send;
+ dev->recv = ape_recv;
+ dev->write_hwaddr = ape_write_hwaddr;
+
+ eth_register(dev);
+
+ #ifdef CONFIG_PHYLIB
+ bus = mdio_alloc();
+ if (!bus) {
+ free(priv);
+ free(dev);
+ return -ENOMEM;
+ }
+
+ bus->read = ape_mii_read;
+ bus->write = ape_mii_write;
+ mdio_register(bus);
+ #endif
+
+ return 1;
+ }
+
+The exact arguments needed to initialize your device are up to you. If you
+need to pass more/less arguments, that's fine. You should also add the
+prototype for your new register function to include/netdev.h.
+
+The return value for this function should be as follows:
+< 0 - failure (hardware failure, not probe failure)
+>=0 - number of interfaces detected
+
+You might notice that many drivers seem to use xxx_initialize() rather than
+xxx_register(). This is the old naming convention and should be avoided as it
+causes confusion with the driver-specific init function.
+
+Other than locating the MAC address in dedicated hardware storage, you should
+not touch the hardware in anyway. That step is handled in the driver-specific
+init function. Remember that we are only registering the device here, we are
+not checking its state or doing random probing.
debugging
design
+ ethernet
fdt-fixup
fs_firmware_loader
i2c-howto
static ulong intel_clk_get_rate(struct clk *clk)
{
- ulong rate;
-
switch (clk->id) {
case CLK_I2C:
/* Hard-coded to 133MHz on current platforms */
default:
return -ENODEV;
}
-
- return rate;
}
static struct clk_ops intel_clk_ops = {
on, the link is always up with fixed speed and fixed duplex-setting.
More information: doc/device-tree-bindings/net/fixed-link.txt
+config PHY_NCSI
+ bool "NC-SI based PHY"
+ depends on DM_ETH
+
endif #PHYLIB
obj-$(CONFIG_PHY_VITESSE) += vitesse.o
obj-$(CONFIG_PHY_MSCC) += mscc.o
obj-$(CONFIG_PHY_FIXED) += fixed.o
+obj-$(CONFIG_PHY_NCSI) += ncsi.o
AQUANTIA_VND1_GSTART_RATE_1G},
[PHY_INTERFACE_MODE_SGMII_2500] = {0x144, AQUANTIA_VND1_GSYSCFG_2_5G,
AQUANTIA_VND1_GSTART_RATE_2_5G},
- [PHY_INTERFACE_MODE_XGMII] = {0x100, AQUANTIA_VND1_GSYSCFG_10G,
- AQUANTIA_VND1_GSTART_RATE_10G},
[PHY_INTERFACE_MODE_XFI] = {0x100, AQUANTIA_VND1_GSYSCFG_10G,
AQUANTIA_VND1_GSTART_RATE_10G},
[PHY_INTERFACE_MODE_USXGMII] = {0x080, AQUANTIA_VND1_GSYSCFG_10G,
AQUANTIA_VND1_GSTART_RATE_10G},
};
-static int aquantia_set_proto(struct phy_device *phydev)
+static int aquantia_set_proto(struct phy_device *phydev,
+ phy_interface_t interface)
{
int i;
- if (!aquantia_syscfg[phydev->interface].cnt)
+ if (!aquantia_syscfg[interface].cnt)
return 0;
/* set the default rate to enable the SI link */
phy_write(phydev, MDIO_MMD_VEND1, AQUANTIA_VND1_GSTART_RATE,
- aquantia_syscfg[phydev->interface].start_rate);
+ aquantia_syscfg[interface].start_rate);
/* set selected protocol for all relevant line side link speeds */
- for (i = 0; i <= aquantia_syscfg[phydev->interface].cnt; i++)
+ for (i = 0; i <= aquantia_syscfg[interface].cnt; i++)
phy_write(phydev, MDIO_MMD_VEND1,
AQUANTIA_VND1_GSYSCFG_BASE + i,
- aquantia_syscfg[phydev->interface].syscfg);
+ aquantia_syscfg[interface].syscfg);
return 0;
}
fault = phy_read(phydev, MDIO_MMD_VEND1, GLOBAL_FAULT);
if (id != 0)
- printf("%s running firmware version %X.%X.%X\n",
- phydev->dev->name, (id >> 8), id & 0xff,
- (rstatus >> 4) & 0xf);
+ debug("%s running firmware version %X.%X.%X\n",
+ phydev->dev->name, (id >> 8), id & 0xff,
+ (rstatus >> 4) & 0xf);
if (fault != 0)
printf("%s fault 0x%04x detected\n", phydev->dev->name, fault);
* on FW config
*/
if (interface == PHY_INTERFACE_MODE_XGMII) {
+ debug("use XFI or USXGMII SI protos, XGMII is not valid\n");
+
reg_val1 = phy_read(phydev, MDIO_MMD_PHYXS,
AQUANTIA_SYSTEM_INTERFACE_SR);
if ((reg_val1 & AQUANTIA_SI_IN_USE_MASK) == AQUANTIA_SI_USXGMII)
mdelay(10);
/* configure protocol based on phydev->interface */
- aquantia_set_proto(phydev);
+ aquantia_set_proto(phydev, interface);
/* apply custom configuration based on DT */
aquantia_dts_config(phydev);
if (usx_an) {
reg_val1 |= AQUANTIA_USX_AUTONEG_CONTROL_ENA;
- printf("%s: system interface USXGMII\n",
- phydev->dev->name);
+ debug("%s: system interface USXGMII\n",
+ phydev->dev->name);
} else {
reg_val1 &= ~AQUANTIA_USX_AUTONEG_CONTROL_ENA;
- printf("%s: system interface XFI\n",
- phydev->dev->name);
+ debug("%s: system interface XFI\n",
+ phydev->dev->name);
}
phy_write(phydev, MDIO_MMD_PHYXS,
val = phy_read(phydev, MDIO_MMD_VEND1, AQUANTIA_RESERVED_STATUS);
reg_val1 = phy_read(phydev, MDIO_MMD_VEND1, AQUANTIA_FIRMWARE_ID);
- printf("%s: %s Firmware Version %x.%x.%x\n", phydev->dev->name,
- phydev->drv->name,
- (reg_val1 & AQUANTIA_FIRMWARE_MAJOR_MASK) >> 8,
- reg_val1 & AQUANTIA_FIRMWARE_MINOR_MASK,
- (val & AQUANTIA_FIRMWARE_BUILD_MASK) >> 4);
+ debug("%s: %s Firmware Version %x.%x.%x\n", phydev->dev->name,
+ phydev->drv->name,
+ (reg_val1 & AQUANTIA_FIRMWARE_MAJOR_MASK) >> 8,
+ reg_val1 & AQUANTIA_FIRMWARE_MINOR_MASK,
+ (val & AQUANTIA_FIRMWARE_BUILD_MASK) >> 4);
return 0;
}
#define DP83867_STRAP_STS2 0x006f
#define DP83867_RGMIIDCTL 0x0086
#define DP83867_IO_MUX_CFG 0x0170
+#define DP83867_SGMIICTL 0x00D3
#define DP83867_SW_RESET BIT(15)
#define DP83867_SW_RESTART BIT(14)
/* CFG4 bits */
#define DP83867_CFG4_PORT_MIRROR_EN BIT(0)
+/* SGMIICTL bits */
+#define DP83867_SGMII_TYPE BIT(14)
+
enum {
DP83867_PORT_MIRRORING_KEEP,
DP83867_PORT_MIRRORING_EN,
int port_mirroring;
bool set_clk_output;
unsigned int clk_output_sel;
+ bool sgmii_ref_clk_en;
};
static int dp83867_config_port_mirroring(struct phy_device *phydev)
if (ofnode_read_bool(node, "enet-phy-lane-no-swap"))
dp83867->port_mirroring = DP83867_PORT_MIRRORING_DIS;
+ if (ofnode_read_bool(node, "ti,sgmii-ref-clock-output-enable"))
+ dp83867->sgmii_ref_clk_en = true;
+
return 0;
}
#else
}
if (phy_interface_is_sgmii(phydev)) {
+ if (dp83867->sgmii_ref_clk_en)
+ phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIICTL,
+ DP83867_SGMII_TYPE);
+
phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR,
(BMCR_ANENABLE | BMCR_FULLDPLX | BMCR_SPEED1000));
}
/**
- * m88e1518_phy_writebits - write bits to a register
+ * m88e151x_phy_writebits - write bits to a register
*/
-void m88e1518_phy_writebits(struct phy_device *phydev,
+void m88e151x_phy_writebits(struct phy_device *phydev,
u8 reg_num, u16 offset, u16 len, u16 data)
{
u16 reg, mask;
phy_write(phydev, MDIO_DEVAD_NONE, reg_num, reg);
}
-static int m88e1518_config(struct phy_device *phydev)
+static int m88e151x_config(struct phy_device *phydev)
{
u16 reg;
phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 18);
/* In reg 20, write MODE[2:0] = 0x1 (SGMII to Copper) */
- m88e1518_phy_writebits(phydev, MIIM_88E151x_GENERAL_CTRL,
+ m88e151x_phy_writebits(phydev, MIIM_88E151x_GENERAL_CTRL,
0, 3, MIIM_88E151x_MODE_SGMII);
/* PHY reset is necessary after changing MODE[2:0] */
- m88e1518_phy_writebits(phydev, MIIM_88E151x_GENERAL_CTRL,
+ m88e151x_phy_writebits(phydev, MIIM_88E151x_GENERAL_CTRL,
MIIM_88E151x_RESET_OFFS, 1, 1);
/* Reset page selection */
return 0;
}
-/* Marvell 88E1510 */
-static int m88e1510_config(struct phy_device *phydev)
-{
- /* Select page 3 */
- phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE,
- MIIM_88E1118_PHY_LED_PAGE);
-
- /* Enable INTn output on LED[2] */
- m88e1518_phy_writebits(phydev, MIIM_88E151x_LED_TIMER_CTRL,
- MIIM_88E151x_INT_EN_OFFS, 1, 1);
-
- /* Configure LEDs */
- /* LED[0]:0011 (ACT) */
- m88e1518_phy_writebits(phydev, MIIM_88E151x_LED_FUNC_CTRL,
- MIIM_88E151x_LED0_OFFS, MIIM_88E151x_LED_FLD_SZ,
- MIIM_88E151x_LED0_ACT);
- /* LED[1]:0110 (LINK 100/1000 Mbps) */
- m88e1518_phy_writebits(phydev, MIIM_88E151x_LED_FUNC_CTRL,
- MIIM_88E151x_LED1_OFFS, MIIM_88E151x_LED_FLD_SZ,
- MIIM_88E151x_LED1_100_1000_LINK);
-
- /* Reset page selection */
- phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0);
-
- return m88e1518_config(phydev);
-}
-
/* Marvell 88E1118 */
static int m88e1118_config(struct phy_device *phydev)
{
.shutdown = &genphy_shutdown,
};
-static struct phy_driver M88E1510_driver = {
- .name = "Marvell 88E1510",
- .uid = 0x1410dd0,
- .mask = 0xfffffff,
- .features = PHY_GBIT_FEATURES,
- .config = &m88e1510_config,
- .startup = &m88e1011s_startup,
- .shutdown = &genphy_shutdown,
- .readext = &m88e1xxx_phy_extread,
- .writeext = &m88e1xxx_phy_extwrite,
-};
-
-/*
- * This supports:
- * 88E1518, uid 0x1410dd1
- * 88E1512, uid 0x1410dd4
- */
-static struct phy_driver M88E1518_driver = {
- .name = "Marvell 88E1518",
+static struct phy_driver M88E151x_driver = {
+ .name = "Marvell 88E151x",
.uid = 0x1410dd0,
- .mask = 0xffffffa,
+ .mask = 0xffffff0,
.features = PHY_GBIT_FEATURES,
- .config = &m88e1518_config,
+ .config = &m88e151x_config,
.startup = &m88e1011s_startup,
.shutdown = &genphy_shutdown,
.readext = &m88e1xxx_phy_extread,
phy_register(&M88E1118R_driver);
phy_register(&M88E1111S_driver);
phy_register(&M88E1011S_driver);
- phy_register(&M88E1510_driver);
- phy_register(&M88E1518_driver);
+ phy_register(&M88E151x_driver);
phy_register(&M88E1680_driver);
return 0;
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * NC-SI protocol configuration
+ *
+ * Copyright (C) 2019, IBM Corporation.
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <phy.h>
+#include <net/ncsi.h>
+#include <net/ncsi-pkt.h>
+#include <asm/unaligned.h>
+
+#define NCSI_PACKAGE_MAX 8
+#define NCSI_CHANNEL_MAX 31
+
+#define NCSI_PACKAGE_SHIFT 5
+#define NCSI_PACKAGE_INDEX(c) (((c) >> NCSI_PACKAGE_SHIFT) & 0x7)
+#define NCSI_RESERVED_CHANNEL 0x1f
+#define NCSI_CHANNEL_INDEX(c) ((c) & ((1 << NCSI_PACKAGE_SHIFT) - 1))
+#define NCSI_TO_CHANNEL(p, c) (((p) << NCSI_PACKAGE_SHIFT) | (c))
+
+#define NCSI_PKT_REVISION 0x01
+
+#define NCSI_CAP_GENERIC_MASK 0x7f
+#define NCSI_CAP_BC_MASK 0x0f
+#define NCSI_CAP_MC_MASK 0x3f
+#define NCSI_CAP_AEN_MASK 0x07
+#define NCSI_CAP_VLAN_MASK 0x07
+
+static void ncsi_send_ebf(unsigned int np, unsigned int nc);
+static void ncsi_send_ae(unsigned int np, unsigned int nc);
+static void ncsi_send_gls(unsigned int np, unsigned int nc);
+static int ncsi_send_command(unsigned int np, unsigned int nc, unsigned int cmd,
+ uchar *payload, int len, bool wait);
+
+struct ncsi_channel {
+ unsigned int id;
+ bool has_link;
+
+ /* capabilities */
+ u32 cap_generic;
+ u32 cap_bc;
+ u32 cap_mc;
+ u32 cap_buffer;
+ u32 cap_aen;
+ u32 cap_vlan;
+
+ /* version information */
+ struct {
+ u32 version; /* Supported BCD encoded NCSI version */
+ u32 alpha2; /* Supported BCD encoded NCSI version */
+ u8 fw_name[12]; /* Firmware name string */
+ u32 fw_version; /* Firmware version */
+ u16 pci_ids[4]; /* PCI identification */
+ u32 mf_id; /* Manufacture ID */
+ } version;
+
+};
+
+struct ncsi_package {
+ unsigned int id;
+ unsigned int n_channels;
+ struct ncsi_channel *channels;
+};
+
+struct ncsi {
+ enum {
+ NCSI_PROBE_PACKAGE_SP,
+ NCSI_PROBE_PACKAGE_DP,
+ NCSI_PROBE_CHANNEL_SP,
+ NCSI_PROBE_CHANNEL,
+ NCSI_CONFIG,
+ } state;
+
+ unsigned int pending_requests;
+ unsigned int requests[256];
+ unsigned int last_request;
+
+ unsigned int current_package;
+ unsigned int current_channel;
+
+ unsigned int n_packages;
+ struct ncsi_package *packages;
+};
+
+struct ncsi *ncsi_priv;
+
+bool ncsi_active(void)
+{
+ unsigned int np, nc;
+
+ if (!ncsi_priv)
+ return false;
+
+ np = ncsi_priv->current_package;
+ nc = ncsi_priv->current_channel;
+
+ if (ncsi_priv->state != NCSI_CONFIG)
+ return false;
+
+ return np < NCSI_PACKAGE_MAX && nc < NCSI_CHANNEL_MAX &&
+ ncsi_priv->packages[np].channels[nc].has_link;
+}
+
+static unsigned int cmd_payload(int cmd)
+{
+ switch (cmd) {
+ case NCSI_PKT_CMD_CIS:
+ return 0;
+ case NCSI_PKT_CMD_SP:
+ return 4;
+ case NCSI_PKT_CMD_DP:
+ return 0;
+ case NCSI_PKT_CMD_EC:
+ return 0;
+ case NCSI_PKT_CMD_DC:
+ return 4;
+ case NCSI_PKT_CMD_RC:
+ return 4;
+ case NCSI_PKT_CMD_ECNT:
+ return 0;
+ case NCSI_PKT_CMD_DCNT:
+ return 0;
+ case NCSI_PKT_CMD_AE:
+ return 8;
+ case NCSI_PKT_CMD_SL:
+ return 8;
+ case NCSI_PKT_CMD_GLS:
+ return 0;
+ case NCSI_PKT_CMD_SVF:
+ return 8;
+ case NCSI_PKT_CMD_EV:
+ return 4;
+ case NCSI_PKT_CMD_DV:
+ return 0;
+ case NCSI_PKT_CMD_SMA:
+ return 8;
+ case NCSI_PKT_CMD_EBF:
+ return 4;
+ case NCSI_PKT_CMD_DBF:
+ return 0;
+ case NCSI_PKT_CMD_EGMF:
+ return 4;
+ case NCSI_PKT_CMD_DGMF:
+ return 0;
+ case NCSI_PKT_CMD_SNFC:
+ return 4;
+ case NCSI_PKT_CMD_GVI:
+ return 0;
+ case NCSI_PKT_CMD_GC:
+ return 0;
+ case NCSI_PKT_CMD_GP:
+ return 0;
+ case NCSI_PKT_CMD_GCPS:
+ return 0;
+ case NCSI_PKT_CMD_GNS:
+ return 0;
+ case NCSI_PKT_CMD_GNPTS:
+ return 0;
+ case NCSI_PKT_CMD_GPS:
+ return 0;
+ default:
+ printf("NCSI: Unknown command 0x%02x\n", cmd);
+ return 0;
+ }
+}
+
+static u32 ncsi_calculate_checksum(unsigned char *data, int len)
+{
+ u32 checksum = 0;
+ int i;
+
+ for (i = 0; i < len; i += 2)
+ checksum += (((u32)data[i] << 8) | data[i + 1]);
+
+ checksum = (~checksum + 1);
+ return checksum;
+}
+
+static int ncsi_validate_rsp(struct ncsi_rsp_pkt *pkt, int payload)
+{
+ struct ncsi_rsp_pkt_hdr *hdr = &pkt->rsp;
+ u32 checksum, c_offset;
+ __be32 pchecksum;
+
+ if (hdr->common.revision != 1) {
+ printf("NCSI: 0x%02x response has unsupported revision 0x%x\n",
+ hdr->common.type, hdr->common.revision);
+ return -1;
+ }
+
+ if (hdr->code != 0) {
+ printf("NCSI: 0x%02x response returns error %d\n",
+ hdr->common.type, __be16_to_cpu(hdr->code));
+ if (ntohs(hdr->reason) == 0x05)
+ printf("(Invalid command length)\n");
+ return -1;
+ }
+
+ if (ntohs(hdr->common.length) != payload) {
+ printf("NCSI: 0x%02x response has incorrect length %d\n",
+ hdr->common.type, hdr->common.length);
+ return -1;
+ }
+
+ c_offset = sizeof(struct ncsi_rsp_pkt_hdr) + payload - sizeof(checksum);
+ pchecksum = get_unaligned_be32((void *)hdr + c_offset);
+ if (pchecksum != 0) {
+ checksum = ncsi_calculate_checksum((unsigned char *)hdr,
+ c_offset);
+ if (pchecksum != checksum) {
+ printf("NCSI: 0x%02x response has invalid checksum\n",
+ hdr->common.type);
+ return -1;
+ }
+ }
+
+ return 0;
+}
+
+static void ncsi_rsp_ec(struct ncsi_rsp_pkt *pkt)
+{
+ struct ncsi_rsp_pkt_hdr *rsp = (struct ncsi_rsp_pkt_hdr *)&pkt->rsp;
+ unsigned int np, nc;
+
+ np = NCSI_PACKAGE_INDEX(rsp->common.channel);
+ nc = NCSI_CHANNEL_INDEX(rsp->common.channel);
+
+ if (ncsi_priv->packages[np].channels[nc].cap_aen != 0)
+ ncsi_send_ae(np, nc);
+ /* else, done */
+}
+
+static void ncsi_rsp_ecnt(struct ncsi_rsp_pkt *pkt)
+{
+ struct ncsi_rsp_pkt_hdr *rsp = (struct ncsi_rsp_pkt_hdr *)&pkt->rsp;
+ unsigned int np, nc;
+
+ np = NCSI_PACKAGE_INDEX(rsp->common.channel);
+ nc = NCSI_CHANNEL_INDEX(rsp->common.channel);
+
+ ncsi_send_command(np, nc, NCSI_PKT_CMD_EC, NULL, 0, true);
+}
+
+static void ncsi_rsp_ebf(struct ncsi_rsp_pkt *pkt)
+{
+ struct ncsi_rsp_pkt_hdr *rsp = (struct ncsi_rsp_pkt_hdr *)&pkt->rsp;
+ unsigned int np, nc;
+
+ np = NCSI_PACKAGE_INDEX(rsp->common.channel);
+ nc = NCSI_CHANNEL_INDEX(rsp->common.channel);
+
+ ncsi_send_command(np, nc, NCSI_PKT_CMD_ECNT, NULL, 0, true);
+}
+
+static void ncsi_rsp_sma(struct ncsi_rsp_pkt *pkt)
+{
+ struct ncsi_rsp_pkt_hdr *rsp = (struct ncsi_rsp_pkt_hdr *)&pkt->rsp;
+ unsigned int np, nc;
+
+ np = NCSI_PACKAGE_INDEX(rsp->common.channel);
+ nc = NCSI_CHANNEL_INDEX(rsp->common.channel);
+
+ ncsi_send_ebf(np, nc);
+}
+
+static void ncsi_rsp_gc(struct ncsi_rsp_pkt *pkt)
+{
+ struct ncsi_rsp_gc_pkt *gc = (struct ncsi_rsp_gc_pkt *)pkt;
+ struct ncsi_rsp_pkt_hdr *rsp = (struct ncsi_rsp_pkt_hdr *)&gc->rsp;
+ struct ncsi_channel *c;
+ unsigned int np, nc;
+
+ np = NCSI_PACKAGE_INDEX(rsp->common.channel);
+ nc = NCSI_CHANNEL_INDEX(rsp->common.channel);
+
+ if (np >= ncsi_priv->n_packages ||
+ nc >= ncsi_priv->packages[np].n_channels) {
+ printf("NCSI: Invalid package / channel (0x%02x, 0x%02x)\n",
+ np, nc);
+ return;
+ }
+
+ c = &ncsi_priv->packages[np].channels[nc];
+ c->cap_generic = ntohl(gc->cap) & NCSI_CAP_GENERIC_MASK;
+ c->cap_bc = ntohl(gc->bc_cap) & NCSI_CAP_BC_MASK;
+ c->cap_mc = ntohl(gc->mc_cap) & NCSI_CAP_MC_MASK;
+ c->cap_aen = ntohl(gc->aen_cap) & NCSI_CAP_AEN_MASK;
+ c->cap_vlan = ntohl(gc->vlan_mode) & NCSI_CAP_VLAN_MASK;
+
+ /* End of probe for this channel */
+}
+
+static void ncsi_rsp_gvi(struct ncsi_rsp_pkt *pkt)
+{
+ struct ncsi_rsp_gvi_pkt *gvi = (struct ncsi_rsp_gvi_pkt *)pkt;
+ struct ncsi_rsp_pkt_hdr *rsp = (struct ncsi_rsp_pkt_hdr *)&gvi->rsp;
+ struct ncsi_channel *c;
+ unsigned int np, nc, i;
+
+ np = NCSI_PACKAGE_INDEX(rsp->common.channel);
+ nc = NCSI_CHANNEL_INDEX(rsp->common.channel);
+
+ if (np >= ncsi_priv->n_packages ||
+ nc >= ncsi_priv->packages[np].n_channels) {
+ printf("NCSI: Invalid package / channel (0x%02x, 0x%02x)\n",
+ np, nc);
+ return;
+ }
+
+ c = &ncsi_priv->packages[np].channels[nc];
+ c->version.version = get_unaligned_be32(&gvi->ncsi_version);
+ c->version.alpha2 = gvi->alpha2;
+ memcpy(c->version.fw_name, gvi->fw_name, sizeof(c->version.fw_name));
+ c->version.fw_version = get_unaligned_be32(&gvi->fw_version);
+ for (i = 0; i < ARRAY_SIZE(c->version.pci_ids); i++)
+ c->version.pci_ids[i] = get_unaligned_be16(gvi->pci_ids + i);
+ c->version.mf_id = get_unaligned_be32(&gvi->mf_id);
+
+ if (ncsi_priv->state == NCSI_PROBE_CHANNEL)
+ ncsi_send_command(np, nc, NCSI_PKT_CMD_GC, NULL, 0, true);
+}
+
+static void ncsi_rsp_gls(struct ncsi_rsp_pkt *pkt)
+{
+ struct ncsi_rsp_gls_pkt *gls = (struct ncsi_rsp_gls_pkt *)pkt;
+ struct ncsi_rsp_pkt_hdr *rsp = (struct ncsi_rsp_pkt_hdr *)&gls->rsp;
+ unsigned int np, nc;
+
+ np = NCSI_PACKAGE_INDEX(rsp->common.channel);
+ nc = NCSI_CHANNEL_INDEX(rsp->common.channel);
+
+ if (np >= ncsi_priv->n_packages ||
+ nc >= ncsi_priv->packages[np].n_channels) {
+ printf("NCSI: Invalid package / channel (0x%02x, 0x%02x)\n",
+ np, nc);
+ return;
+ }
+
+ ncsi_priv->packages[np].channels[nc].has_link =
+ !!(get_unaligned_be32(&gls->status));
+
+ if (ncsi_priv->state == NCSI_PROBE_CHANNEL)
+ ncsi_send_command(np, nc, NCSI_PKT_CMD_GVI, NULL, 0, true);
+}
+
+static void ncsi_rsp_cis(struct ncsi_rsp_pkt *pkt)
+{
+ struct ncsi_rsp_pkt_hdr *rsp = (struct ncsi_rsp_pkt_hdr *)pkt;
+ struct ncsi_package *package;
+ unsigned int np, nc;
+
+ np = NCSI_PACKAGE_INDEX(rsp->common.channel);
+ nc = NCSI_CHANNEL_INDEX(rsp->common.channel);
+
+ if (np >= ncsi_priv->n_packages) {
+ printf("NCSI: Mystery package 0x%02x from CIS\n", np);
+ return;
+ }
+
+ package = &ncsi_priv->packages[np];
+
+ if (nc < package->n_channels) {
+ /*
+ * This is fine in general but in the current design we
+ * don't send CIS commands to known channels.
+ */
+ debug("NCSI: Duplicate channel 0x%02x\n", nc);
+ return;
+ }
+
+ package->channels = realloc(package->channels,
+ sizeof(struct ncsi_channel) *
+ (package->n_channels + 1));
+ if (!package->channels) {
+ printf("NCSI: Could not allocate memory for new channel\n");
+ return;
+ }
+
+ debug("NCSI: New channel 0x%02x\n", nc);
+
+ package->channels[nc].id = nc;
+ package->channels[nc].has_link = false;
+ package->n_channels++;
+
+ ncsi_send_gls(np, nc);
+}
+
+static void ncsi_rsp_dp(struct ncsi_rsp_pkt *pkt)
+{
+ struct ncsi_rsp_pkt_hdr *rsp = (struct ncsi_rsp_pkt_hdr *)pkt;
+ unsigned int np;
+
+ /* No action needed */
+
+ np = NCSI_PACKAGE_INDEX(rsp->common.channel);
+ if (np >= ncsi_priv->n_packages)
+ debug("NCSI: DP response from unknown package %d\n", np);
+}
+
+static void ncsi_rsp_sp(struct ncsi_rsp_pkt *pkt)
+{
+ struct ncsi_rsp_pkt_hdr *rsp = (struct ncsi_rsp_pkt_hdr *)pkt;
+ unsigned int np;
+
+ np = NCSI_PACKAGE_INDEX(rsp->common.channel);
+
+ if (np < ncsi_priv->n_packages) {
+ /* Already know about this package */
+ debug("NCSI: package 0x%02x selected\n", np);
+ return;
+ }
+
+ debug("NCSI: adding new package %d\n", np);
+
+ ncsi_priv->packages = realloc(ncsi_priv->packages,
+ sizeof(struct ncsi_package) *
+ (ncsi_priv->n_packages + 1));
+ if (!ncsi_priv->packages) {
+ printf("NCSI: could not allocate memory for new package\n");
+ return;
+ }
+
+ ncsi_priv->packages[np].id = np;
+ ncsi_priv->packages[np].n_channels = 0;
+ ncsi_priv->packages[np].channels = NULL;
+ ncsi_priv->n_packages++;
+}
+
+static void ncsi_update_state(struct ncsi_rsp_pkt_hdr *nh)
+{
+ bool timeout = !nh;
+ int np, nc;
+
+ switch (ncsi_priv->state) {
+ case NCSI_PROBE_PACKAGE_SP:
+ if (!timeout &&
+ ncsi_priv->current_package + 1 < NCSI_PACKAGE_MAX) {
+ ncsi_priv->current_package++;
+ } else {
+ ncsi_priv->state = NCSI_PROBE_PACKAGE_DP;
+ ncsi_priv->current_package = 0;
+ }
+ return ncsi_probe_packages();
+ case NCSI_PROBE_PACKAGE_DP:
+ if (ncsi_priv->current_package + 1 < ncsi_priv->n_packages &&
+ !timeout) {
+ ncsi_priv->current_package++;
+ } else {
+ if (!ncsi_priv->n_packages) {
+ printf("NCSI: no packages found\n");
+ net_set_state(NETLOOP_FAIL);
+ return;
+ }
+ printf("NCSI: probing channels\n");
+ ncsi_priv->state = NCSI_PROBE_CHANNEL_SP;
+ ncsi_priv->current_package = 0;
+ ncsi_priv->current_channel = 0;
+ }
+ return ncsi_probe_packages();
+ case NCSI_PROBE_CHANNEL_SP:
+ if (!timeout && nh->common.type == NCSI_PKT_RSP_SP) {
+ ncsi_priv->state = NCSI_PROBE_CHANNEL;
+ return ncsi_probe_packages();
+ }
+ printf("NCSI: failed to select package 0x%0x2 or timeout\n",
+ ncsi_priv->current_package);
+ net_set_state(NETLOOP_FAIL);
+ break;
+ case NCSI_PROBE_CHANNEL:
+ // TODO only does package 0 for now
+ if (ncsi_priv->pending_requests == 0) {
+ np = ncsi_priv->current_package;
+ nc = ncsi_priv->current_channel;
+
+ /* Configure first channel that has link */
+ if (ncsi_priv->packages[np].channels[nc].has_link) {
+ ncsi_priv->state = NCSI_CONFIG;
+ } else if (ncsi_priv->current_channel + 1 <
+ NCSI_CHANNEL_MAX) {
+ ncsi_priv->current_channel++;
+ } else {
+ // XXX As above only package 0
+ printf("NCSI: no channel found with link\n");
+ net_set_state(NETLOOP_FAIL);
+ return;
+ }
+ return ncsi_probe_packages();
+ }
+ break;
+ case NCSI_CONFIG:
+ if (ncsi_priv->pending_requests == 0) {
+ printf("NCSI: configuration done!\n");
+ net_set_state(NETLOOP_SUCCESS);
+ } else if (timeout) {
+ printf("NCSI: timeout during configure\n");
+ net_set_state(NETLOOP_FAIL);
+ }
+ break;
+ default:
+ printf("NCSI: something went very wrong, nevermind\n");
+ net_set_state(NETLOOP_FAIL);
+ break;
+ }
+}
+
+static void ncsi_timeout_handler(void)
+{
+ if (ncsi_priv->pending_requests)
+ ncsi_priv->pending_requests--;
+
+ ncsi_update_state(NULL);
+}
+
+static int ncsi_send_command(unsigned int np, unsigned int nc, unsigned int cmd,
+ uchar *payload, int len, bool wait)
+{
+ struct ncsi_pkt_hdr *hdr;
+ __be32 *pchecksum;
+ int eth_hdr_size;
+ u32 checksum;
+ uchar *pkt, *start;
+ int final_len;
+
+ pkt = calloc(1, PKTSIZE_ALIGN + PKTALIGN);
+ if (!pkt)
+ return -ENOMEM;
+ start = pkt;
+
+ eth_hdr_size = net_set_ether(pkt, net_bcast_ethaddr, PROT_NCSI);
+ pkt += eth_hdr_size;
+
+ /* Set NCSI command header fields */
+ hdr = (struct ncsi_pkt_hdr *)pkt;
+ hdr->mc_id = 0;
+ hdr->revision = NCSI_PKT_REVISION;
+ hdr->id = ++ncsi_priv->last_request;
+ ncsi_priv->requests[ncsi_priv->last_request] = 1;
+ hdr->type = cmd;
+ hdr->channel = NCSI_TO_CHANNEL(np, nc);
+ hdr->length = htons(len);
+
+ if (payload && len)
+ memcpy(pkt + sizeof(struct ncsi_pkt_hdr), payload, len);
+
+ /* Calculate checksum */
+ checksum = ncsi_calculate_checksum((unsigned char *)hdr,
+ sizeof(*hdr) + len);
+ pchecksum = (__be32 *)((void *)(hdr + 1) + len);
+ put_unaligned_be32(htonl(checksum), pchecksum);
+
+ if (wait) {
+ net_set_timeout_handler(1000UL, ncsi_timeout_handler);
+ ncsi_priv->pending_requests++;
+ }
+
+ if (len < 26)
+ len = 26;
+ /* frame header, packet header, payload, checksum */
+ final_len = eth_hdr_size + sizeof(struct ncsi_cmd_pkt_hdr) + len + 4;
+
+ net_send_packet(start, final_len);
+ free(start);
+ return 0;
+}
+
+static void ncsi_handle_aen(struct ip_udp_hdr *ip, unsigned int len)
+{
+ struct ncsi_aen_pkt_hdr *hdr = (struct ncsi_aen_pkt_hdr *)ip;
+ int payload, i;
+ __be32 pchecksum;
+ u32 checksum;
+
+ switch (hdr->type) {
+ case NCSI_PKT_AEN_LSC:
+ printf("NCSI: link state changed\n");
+ payload = 12;
+ break;
+ case NCSI_PKT_AEN_CR:
+ printf("NCSI: re-configuration required\n");
+ payload = 4;
+ break;
+ case NCSI_PKT_AEN_HNCDSC:
+ /* Host notifcation - N/A but weird */
+ debug("NCSI: HNCDSC AEN received\n");
+ return;
+ default:
+ printf("%s: Invalid type 0x%02x\n", __func__, hdr->type);
+ return;
+ }
+
+ /* Validate packet */
+ if (hdr->common.revision != 1) {
+ printf("NCSI: 0x%02x response has unsupported revision 0x%x\n",
+ hdr->common.type, hdr->common.revision);
+ return;
+ }
+
+ if (ntohs(hdr->common.length) != payload) {
+ printf("NCSI: 0x%02x response has incorrect length %d\n",
+ hdr->common.type, hdr->common.length);
+ return;
+ }
+
+ pchecksum = get_unaligned_be32((void *)(hdr + 1) + payload - 4);
+ if (pchecksum != 0) {
+ checksum = ncsi_calculate_checksum((unsigned char *)hdr,
+ sizeof(*hdr) + payload - 4);
+ if (pchecksum != checksum) {
+ printf("NCSI: 0x%02x response has invalid checksum\n",
+ hdr->common.type);
+ return;
+ }
+ }
+
+ /* Link or configuration lost - just redo the discovery process */
+ ncsi_priv->state = NCSI_PROBE_PACKAGE_SP;
+ for (i = 0; i < ncsi_priv->n_packages; i++)
+ free(ncsi_priv->packages[i].channels);
+ free(ncsi_priv->packages);
+ ncsi_priv->n_packages = 0;
+
+ ncsi_priv->current_package = NCSI_PACKAGE_MAX;
+ ncsi_priv->current_channel = NCSI_CHANNEL_MAX;
+
+ ncsi_probe_packages();
+}
+
+void ncsi_receive(struct ethernet_hdr *et, struct ip_udp_hdr *ip,
+ unsigned int len)
+{
+ struct ncsi_rsp_pkt *pkt = (struct ncsi_rsp_pkt *)ip;
+ struct ncsi_rsp_pkt_hdr *nh = (struct ncsi_rsp_pkt_hdr *)&pkt->rsp;
+ void (*handler)(struct ncsi_rsp_pkt *pkt) = NULL;
+ unsigned short payload;
+
+ if (ncsi_priv->pending_requests)
+ ncsi_priv->pending_requests--;
+
+ if (len < sizeof(struct ncsi_rsp_pkt_hdr)) {
+ printf("NCSI: undersized packet: %u bytes\n", len);
+ goto out;
+ }
+
+ if (nh->common.type == NCSI_PKT_AEN)
+ return ncsi_handle_aen(ip, len);
+
+ switch (nh->common.type) {
+ case NCSI_PKT_RSP_SP:
+ payload = 4;
+ handler = ncsi_rsp_sp;
+ break;
+ case NCSI_PKT_RSP_DP:
+ payload = 4;
+ handler = ncsi_rsp_dp;
+ break;
+ case NCSI_PKT_RSP_CIS:
+ payload = 4;
+ handler = ncsi_rsp_cis;
+ break;
+ case NCSI_PKT_RSP_GLS:
+ payload = 16;
+ handler = ncsi_rsp_gls;
+ break;
+ case NCSI_PKT_RSP_GVI:
+ payload = 40;
+ handler = ncsi_rsp_gvi;
+ break;
+ case NCSI_PKT_RSP_GC:
+ payload = 32;
+ handler = ncsi_rsp_gc;
+ break;
+ case NCSI_PKT_RSP_SMA:
+ payload = 4;
+ handler = ncsi_rsp_sma;
+ break;
+ case NCSI_PKT_RSP_EBF:
+ payload = 4;
+ handler = ncsi_rsp_ebf;
+ break;
+ case NCSI_PKT_RSP_ECNT:
+ payload = 4;
+ handler = ncsi_rsp_ecnt;
+ break;
+ case NCSI_PKT_RSP_EC:
+ payload = 4;
+ handler = ncsi_rsp_ec;
+ break;
+ case NCSI_PKT_RSP_AE:
+ payload = 4;
+ handler = NULL;
+ break;
+ default:
+ printf("NCSI: unsupported packet type 0x%02x\n",
+ nh->common.type);
+ goto out;
+ }
+
+ if (ncsi_validate_rsp(pkt, payload) != 0) {
+ printf("NCSI: discarding invalid packet of type 0x%02x\n",
+ nh->common.type);
+ goto out;
+ }
+
+ if (handler)
+ handler(pkt);
+out:
+ ncsi_update_state(nh);
+}
+
+static void ncsi_send_sp(unsigned int np)
+{
+ uchar payload[4] = {0};
+
+ ncsi_send_command(np, NCSI_RESERVED_CHANNEL, NCSI_PKT_CMD_SP,
+ (unsigned char *)&payload,
+ cmd_payload(NCSI_PKT_CMD_SP), true);
+}
+
+static void ncsi_send_dp(unsigned int np)
+{
+ ncsi_send_command(np, NCSI_RESERVED_CHANNEL, NCSI_PKT_CMD_DP, NULL, 0,
+ true);
+}
+
+static void ncsi_send_gls(unsigned int np, unsigned int nc)
+{
+ ncsi_send_command(np, nc, NCSI_PKT_CMD_GLS, NULL, 0, true);
+}
+
+static void ncsi_send_cis(unsigned int np, unsigned int nc)
+{
+ ncsi_send_command(np, nc, NCSI_PKT_CMD_CIS, NULL, 0, true);
+}
+
+static void ncsi_send_ae(unsigned int np, unsigned int nc)
+{
+ struct ncsi_cmd_ae_pkt cmd;
+
+ memset(&cmd, 0, sizeof(cmd));
+ cmd.mode = htonl(ncsi_priv->packages[np].channels[nc].cap_aen);
+
+ ncsi_send_command(np, nc, NCSI_PKT_CMD_AE,
+ ((unsigned char *)&cmd)
+ + sizeof(struct ncsi_cmd_pkt_hdr),
+ cmd_payload(NCSI_PKT_CMD_AE), true);
+}
+
+static void ncsi_send_ebf(unsigned int np, unsigned int nc)
+{
+ struct ncsi_cmd_ebf_pkt cmd;
+
+ memset(&cmd, 0, sizeof(cmd));
+ cmd.mode = htonl(ncsi_priv->packages[np].channels[nc].cap_bc);
+
+ ncsi_send_command(np, nc, NCSI_PKT_CMD_EBF,
+ ((unsigned char *)&cmd)
+ + sizeof(struct ncsi_cmd_pkt_hdr),
+ cmd_payload(NCSI_PKT_CMD_EBF), true);
+}
+
+static void ncsi_send_sma(unsigned int np, unsigned int nc)
+{
+ struct ncsi_cmd_sma_pkt cmd;
+ unsigned char *addr, i;
+
+ addr = eth_get_ethaddr();
+ if (!addr) {
+ printf("NCSI: no MAC address configured\n");
+ return;
+ }
+
+ memset(&cmd, 0, sizeof(cmd));
+ for (i = 0; i < ARP_HLEN; i++)
+ cmd.mac[i] = addr[i];
+ cmd.index = 1;
+ cmd.at_e = 1;
+
+ ncsi_send_command(np, nc, NCSI_PKT_CMD_SMA,
+ ((unsigned char *)&cmd)
+ + sizeof(struct ncsi_cmd_pkt_hdr),
+ cmd_payload(NCSI_PKT_CMD_SMA), true);
+}
+
+void ncsi_probe_packages(void)
+{
+ struct ncsi_package *package;
+ unsigned int np, nc;
+
+ switch (ncsi_priv->state) {
+ case NCSI_PROBE_PACKAGE_SP:
+ if (ncsi_priv->current_package == NCSI_PACKAGE_MAX)
+ ncsi_priv->current_package = 0;
+ ncsi_send_sp(ncsi_priv->current_package);
+ break;
+ case NCSI_PROBE_PACKAGE_DP:
+ ncsi_send_dp(ncsi_priv->current_package);
+ break;
+ case NCSI_PROBE_CHANNEL_SP:
+ if (ncsi_priv->n_packages > 0)
+ ncsi_send_sp(ncsi_priv->current_package);
+ else
+ printf("NCSI: no packages discovered, configuration not possible\n");
+ break;
+ case NCSI_PROBE_CHANNEL:
+ /* Kicks off chain of channel discovery */
+ ncsi_send_cis(ncsi_priv->current_package,
+ ncsi_priv->current_channel);
+ break;
+ case NCSI_CONFIG:
+ for (np = 0; np < ncsi_priv->n_packages; np++) {
+ package = &ncsi_priv->packages[np];
+ for (nc = 0; nc < package->n_channels; nc++)
+ if (package->channels[nc].has_link)
+ break;
+ if (nc < package->n_channels)
+ break;
+ }
+ if (np == ncsi_priv->n_packages) {
+ printf("NCSI: no link available\n");
+ return;
+ }
+
+ printf("NCSI: configuring channel %d\n", nc);
+ ncsi_priv->current_package = np;
+ ncsi_priv->current_channel = nc;
+ /* Kicks off rest of configure chain */
+ ncsi_send_sma(np, nc);
+ break;
+ default:
+ printf("NCSI: unknown state 0x%x\n", ncsi_priv->state);
+ }
+}
+
+int ncsi_probe(struct phy_device *phydev)
+{
+ if (!phydev->priv) {
+ phydev->priv = malloc(sizeof(struct ncsi));
+ if (!phydev->priv)
+ return -ENOMEM;
+ memset(phydev->priv, 0, sizeof(struct ncsi));
+ }
+
+ ncsi_priv = phydev->priv;
+
+ return 0;
+}
+
+int ncsi_startup(struct phy_device *phydev)
+{
+ /* Set phydev parameters */
+ phydev->speed = SPEED_100;
+ phydev->duplex = DUPLEX_FULL;
+ /* Normal phy reset is N/A */
+ phydev->flags |= PHY_FLAG_BROKEN_RESET;
+
+ /* Set initial probe state */
+ ncsi_priv->state = NCSI_PROBE_PACKAGE_SP;
+
+ /* No active package/channel yet */
+ ncsi_priv->current_package = NCSI_PACKAGE_MAX;
+ ncsi_priv->current_channel = NCSI_CHANNEL_MAX;
+
+ /* Pretend link works so the MAC driver sets final bits up */
+ phydev->link = true;
+
+ /* Set ncsi_priv so we can use it when called from net_loop() */
+ ncsi_priv = phydev->priv;
+
+ return 0;
+}
+
+int ncsi_shutdown(struct phy_device *phydev)
+{
+ printf("NCSI: Disabling package %d\n", ncsi_priv->current_package);
+ ncsi_send_dp(ncsi_priv->current_package);
+ return 0;
+}
+
+static struct phy_driver ncsi_driver = {
+ .uid = PHY_NCSI_ID,
+ .mask = 0xffffffff,
+ .name = "NC-SI",
+ .features = PHY_100BT_FEATURES | PHY_DEFAULT_FEATURES |
+ SUPPORTED_100baseT_Full | SUPPORTED_MII,
+ .probe = ncsi_probe,
+ .startup = ncsi_startup,
+ .shutdown = ncsi_shutdown,
+};
+
+int phy_ncsi_init(void)
+{
+ phy_register(&ncsi_driver);
+ return 0;
+}
/*
* Timeout reached ?
*/
- if (i > PHY_ANEG_TIMEOUT) {
+ if (i > (PHY_ANEG_TIMEOUT / 50)) {
printf(" TIMEOUT !\n");
phydev->link = 0;
return -ETIMEDOUT;
#ifdef CONFIG_PHY_FIXED
phy_fixed_init();
#endif
+#ifdef CONFIG_PHY_NCSI
+ phy_ncsi_init();
+#endif
#ifdef CONFIG_PHY_XILINX_GMII2RGMII
phy_xilinx_gmii2rgmii_init();
#endif
#ifdef CONFIG_PHY_FIXED
phydev = phy_connect_fixed(bus, dev, interface);
#endif
+
+#ifdef CONFIG_PHY_NCSI
+ if (!phydev)
+ phydev = phy_device_create(bus, 0, PHY_NCSI_ID, false, interface);
+#endif
+
#ifdef CONFIG_PHY_XILINX_GMII2RGMII
if (!phydev)
phydev = phy_connect_gmii2rgmii(bus, dev, interface);
ret = power_domain_off(&pd);
}
+ /*
+ * For platforms with parent and child power-domain devices
+ * we may not run device_remove() on the power-domain parent
+ * because it will result in removing its children and switching
+ * off their power-domain parent. So we will get here again and
+ * again and will be stuck in an endless loop.
+ */
+ if (!on && dev_get_parent(dev) == pd.dev &&
+ device_get_uclass_id(dev) == UCLASS_POWER_DOMAIN)
+ return ret;
+
/*
* power_domain_get() bound the device, thus
* we must remove it again to prevent unbinding
return 0;
}
+#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
+static int ns1655_serial_set_base_addr(struct udevice *dev)
+{
+ fdt_addr_t addr;
+ struct ns16550_platdata *plat;
+
+ plat = dev_get_platdata(dev);
+
+ addr = dev_read_addr_pci(dev);
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+#ifdef CONFIG_SYS_NS16550_PORT_MAPPED
+ plat->base = addr;
+#else
+ plat->base = (unsigned long)map_physmem(addr, 0, MAP_NOCACHE);
+#endif
+
+ return 0;
+}
+#endif
+
int ns16550_serial_probe(struct udevice *dev)
{
struct NS16550 *const com_port = dev_get_priv(dev);
struct reset_ctl_bulk reset_bulk;
int ret;
+#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
+ ret = ns1655_serial_set_base_addr(dev);
+ if (ret)
+ return ret;
+#endif
+
ret = reset_get_bulk(dev, &reset_bulk);
if (!ret)
reset_deassert_bulk(&reset_bulk);
{
struct ns16550_platdata *plat = dev->platdata;
const u32 port_type = dev_get_driver_data(dev);
- fdt_addr_t addr;
struct clk clk;
int err;
- /* try Processor Local Bus device first */
- addr = dev_read_addr_pci(dev);
- if (addr == FDT_ADDR_T_NONE)
- return -EINVAL;
-
-#ifdef CONFIG_SYS_NS16550_PORT_MAPPED
- plat->base = addr;
-#else
- plat->base = (unsigned long)map_physmem(addr, 0, MAP_NOCACHE);
-#endif
-
plat->reg_offset = dev_read_u32_default(dev, "reg-offset", 0);
plat->reg_shift = dev_read_u32_default(dev, "reg-shift", 0);
plat->reg_width = dev_read_u32_default(dev, "reg-io-width", 1);
return ret;
}
} else {
- dev_warn(dev, "Failed to get per clk: %d\n", ret);
+ debug("%s: Failed to get per clk: %d\n", __func__, ret);
}
#endif
int ret;
int dev = mmc_get_env_dev();
const char *errmsg;
+ env_t *ep = NULL;
mmc = find_mmc_device(dev);
}
ret = env_import(buf, 1);
+ if (!ret) {
+ ep = (env_t *)buf;
+ gd->env_addr = (ulong)&ep->data;
+ }
fini:
fini_mmc_for_env(mmc);
#undef CONFIG_BOOTM_NETBSD
#define CONFIG_FSL_USDHC
+#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#define USDHC1_BASE_ADDR 0x5B010000
+#define USDHC2_BASE_ADDR 0x5B020000
+#define USDHC3_BASE_ADDR 0x5B030000
+
#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
#define CONFIG_ENV_OVERWRITE
"panel=NULL\0" \
"console=ttyLP0\0" \
"fdt_addr=0x83000000\0" \
- "fdt_high=0xffffffffffffffff\0" \
"boot_fdt=try\0" \
"fdt_file=imx8qm-rom7720-a1.dtb\0" \
"initrd_addr=0x83800000\0" \
- "initrd_high=0xffffffffffffffff\0" \
"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
"script=boot.scr\0" \
"image=Image\0" \
"panel=NULL\0" \
- "console=ttyLP0,${baudrate} earlycon\0" \
+ "console=ttyLP0\0" \
"fdt_addr=0x83000000\0" \
"fdt_high=0xffffffffffffffff\0" \
"boot_fdt=try\0" \
"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
"mmcautodetect=yes\0" \
- "mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 " \
+ "mmcargs=setenv bootargs console=${console},${baudrate} root=${mmcroot}\0 " \
"loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
"bootscript=echo Running bootscript from mmc ...; " \
"source\0" \
"echo wait for boot; " \
"fi;" \
"fi;\0" \
- "netargs=setenv bootargs console=${console} " \
+ "netargs=setenv bootargs console=${console},${baudrate} " \
"root=/dev/nfs " \
"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
"netboot=echo Booting from net ...; " \
"ramdisk_addr_r=0x13000000\0" \
"ramdiskaddr=0x13000000\0" \
"initrd_high=0xffffffff\0" \
- "fdt_high=0xffffffff\0" \
"ip_dyn=yes\0" \
"console=" CONSOLE_DEV ",115200\0" \
"bootm_size=0x10000000\0" \
#define CONFIG_POWER_PFUZE100
#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
-#define CONFIG_FEC_MXC
-#define IMX_FEC_BASE ENET_BASE_ADDR
-#define CONFIG_FEC_XCV_TYPE RGMII
-#define CONFIG_ETHPRIME "FEC"
-#define CONFIG_FEC_MXC_PHYADDR 1
-
-#define CONFIG_PHY_ATHEROS
-
#endif /* __MX6SABREAUTO_CONFIG_H */
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 /* Enabled USB controller number */
#endif
-#define CONFIG_FEC_MXC
-#define IMX_FEC_BASE ENET_BASE_ADDR
-#define CONFIG_FEC_XCV_TYPE RGMII
-#define CONFIG_ETHPRIME "FEC"
-#define CONFIG_FEC_MXC_PHYADDR 1
-
-#define CONFIG_PHY_ATHEROS
-
-
#endif /* __MX6SABRESD_CONFIG_H */
#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
#define CONFIG_SYS_I2C_SPEED 100000
-#define CONFIG_FEC_MXC
-#define IMX_FEC_BASE ENET_BASE_ADDR
-#define CONFIG_FEC_XCV_TYPE RMII
-#define CONFIG_FEC_MXC_PHYADDR 0
-
-#define CONFIG_PHY_SMSC
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"script=boot.scr\0" \
"image=zImage\0" \
#ifndef __CONFIG_H
#define __CONFIG_H
+#include <linux/sizes.h>
#include "at91-sama5_common.h"
/*
#define CONFIG_SYS_SPL_MALLOC_START 0x20080000
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
-#define CONFIG_SYS_MONITOR_LEN (512 << 10)
+/* size of u-boot.bin to load */
+#define CONFIG_SYS_MONITOR_LEN (2 * SZ_512K)
#ifdef CONFIG_SD_BOOT
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2011, Stefano Babic <sbabic@denx.de>
- *
- * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
- *
- * Configuration for the woodburn board.
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <asm/arch/imx-regs.h>
-#include "woodburn_common.h"
-
-/* Set TEXT at the beginning of the NOR flash */
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2011, Stefano Babic <sbabic@denx.de>
- *
- * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
- *
- * Configuration for the woodburn board.
- */
-
-#ifndef __WOODBURN_COMMON_CONFIG_H
-#define __WOODBURN_COMMON_CONFIG_H
-
-#include <asm/arch/imx-regs.h>
-
- /* High Level Configuration Options */
-#define CONFIG_MX35
-#define CONFIG_MX35_HCLK_FREQ 24000000
-#define CONFIG_SYS_FSL_CLK
-
-#define CONFIG_MACH_TYPE MACH_TYPE_FLEA3
-
-/* This is required to setup the ESDC controller */
-
-#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
-#define CONFIG_REVISION_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024)
-
-/*
- * Hardware drivers
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_MXC
-#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
-#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
-#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
-#define CONFIG_SYS_SPD_BUS_NUM 0
-
-/* PMIC Controller */
-#define CONFIG_POWER
-#define CONFIG_POWER_I2C
-#define CONFIG_POWER_FSL
-#define CONFIG_POWER_FSL_MC13892
-#define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x8
-#define CONFIG_RTC_MC13XXX
-
-/* mmc driver */
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
-#define CONFIG_SYS_FSL_ESDHC_NUM 1
-
-/*
- * UART (console)
- */
-#define CONFIG_MXC_UART
-#define CONFIG_MXC_UART_BASE UART1_BASE
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-/*
- * Command definition
- */
-
-#define CONFIG_NET_RETRY_COUNT 100
-
-
-#define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */
-
-/*
- * Ethernet on SOC (FEC)
- */
-#define CONFIG_FEC_MXC
-#define IMX_FEC_BASE FEC_BASE_ADDR
-#define CONFIG_FEC_MXC_PHYADDR 0x1
-
-#define CONFIG_DISCOVER_PHY
-
-#define CONFIG_ARP_TIMEOUT 200UL
-
-/*
- * Miscellaneous configurable options
- */
-
-#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x10000
-
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-
-/*
- * Physical Memory Map
- */
-#define PHYS_SDRAM_1 CSD0_BASE_ADDR
-#define PHYS_SDRAM_1_SIZE (256 * 1024 * 1024)
-
-#define CONFIG_SYS_SDRAM_BASE CSD0_BASE_ADDR
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (LOW_LEVEL_SRAM_STACK - \
- IRAM_BASE_ADDR - \
- GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_ADDR (IRAM_BASE_ADDR + \
- CONFIG_SYS_GBL_DATA_OFFSET)
-
-/*
- * MTD Command for mtdparts
- */
-
-/*
- * FLASH and environment organization
- */
-#define CONFIG_SYS_FLASH_BASE CS0_BASE_ADDR
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
-/* Monitor at beginning of flash */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
-
-/* Address and size of Redundant Environment Sector */
-
-/*
- * CFI FLASH driver setup
- */
-
-/* A non-standard buffered write algorithm */
-
-/*
- * NAND FLASH driver setup
- */
-#define CONFIG_NAND_MXC_V1_1
-#define CONFIG_MXC_NAND_REGS_BASE (NFC_BASE_ADDR)
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_BASE (NFC_BASE_ADDR)
-#define CONFIG_MXC_NAND_HWECC
-#define CONFIG_SYS_NAND_LARGEPAGE
-
-#define CONFIG_SYS_NAND_ONFI_DETECTION
-
-/*
- * Default environment and default scripts
- * to update uboot and load kernel
- */
-
-#define CONFIG_HOSTNAME "woodburn"
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=${serverip}:${rootpath}\0" \
- "ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip_sta=setenv bootargs ${bootargs} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
- ":${hostname}:${netdev}:off panic=1\0" \
- "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \
- "addip=if test -n ${ipdyn};then run addip_dyn;" \
- "else run addip_sta;fi\0" \
- "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
- "addtty=setenv bootargs ${bootargs}" \
- " console=ttymxc0,${baudrate}\0" \
- "addmisc=setenv bootargs ${bootargs} ${misc}\0" \
- "loadaddr=80800000\0" \
- "kernel_addr_r=80800000\0" \
- "hostname=" CONFIG_HOSTNAME "\0" \
- "bootfile=" CONFIG_HOSTNAME "/uImage\0" \
- "ramdisk_file=" CONFIG_HOSTNAME "/uRamdisk\0" \
- "flash_self=run ramargs addip addtty addmtd addmisc;" \
- "bootm ${kernel_addr} ${ramdisk_addr}\0" \
- "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \
- "bootm ${kernel_addr}\0" \
- "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
- "run nfsargs addip addtty addmtd addmisc;" \
- "bootm ${kernel_addr_r}\0" \
- "net_self_load=tftp ${kernel_addr_r} ${bootfile};" \
- "tftp ${ramdisk_addr_r} ${ramdisk_file};\0" \
- "net_self=if run net_self_load;then " \
- "run ramargs addip addtty addmtd addmisc;" \
- "bootm ${kernel_addr_r} ${ramdisk_addr_r};" \
- "else echo Images not loades;fi\0" \
- "u-boot=" CONFIG_HOSTNAME "/u-boot.bin\0" \
- "load=tftp ${loadaddr} ${u-boot}\0" \
- "uboot_addr=" __stringify(CONFIG_SYS_MONITOR_BASE) "\0" \
- "update=protect off ${uboot_addr} +80000;" \
- "erase ${uboot_addr} +80000;" \
- "cp.b ${loadaddr} ${uboot_addr} ${filesize}\0" \
- "upd=if run load;then echo Updating u-boot;if run update;" \
- "then echo U-Boot updated;" \
- "else echo Error updating u-boot !;" \
- "echo Board without bootloader !!;" \
- "fi;" \
- "else echo U-Boot not downloaded..exiting;fi\0" \
- "bootcmd=run net_nfs\0"
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2011, Stefano Babic <sbabic@denx.de>
- *
- * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
- *
- * Configuration for the woodburn board.
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <asm/arch/imx-regs.h>
-#include "woodburn_common.h"
-
-/* Set TEXT in RAM */
-
-/*
- * SPL
- */
-
-#define CONFIG_SPL_MAX_SIZE (64 * 1024) /* 8 KB for stack */
-#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
-
-#define CONFIG_SYS_SPL_MALLOC_START 0x8f000000
-#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
-#define CONFIG_SPL_BSS_START_ADDR 0x8f080000 /* end of RAM */
-#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
-
-#endif /* __CONFIG_H */
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (C) 2014 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
*/
#ifndef __DT_BINDINGS_CLOCK_IMX6SX_H
#define IMX6SX_PLL6_BYPASS 262
#define IMX6SX_PLL7_BYPASS 263
#define IMX6SX_CLK_SPDIF_GCLK 264
-#define IMX6SX_CLK_CLK_END 265
+#define IMX6SX_CLK_LVDS2_SEL 265
+#define IMX6SX_CLK_LVDS2_OUT 266
+#define IMX6SX_CLK_LVDS2_IN 267
+#define IMX6SX_CLK_ANACLK2 268
+#define IMX6SX_CLK_MMDC_P1_IPG 269
+#define IMX6SX_CLK_CLK_END 270
#endif /* __DT_BINDINGS_CLOCK_IMX6SX_H */
#define PROT_VLAN 0x8100 /* IEEE 802.1q protocol */
#define PROT_IPV6 0x86dd /* IPv6 over bluebook */
#define PROT_PPP_SES 0x8864 /* PPPoE session messages */
+#define PROT_NCSI 0x88f8 /* NC-SI control packets */
#define IPPROTO_ICMP 1 /* Internet Control Message Protocol */
#define IPPROTO_UDP 17 /* User Datagram Protocol */
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright Gavin Shan, IBM Corporation 2016.
+ */
+
+#ifndef __NCSI_PKT_H__
+#define __NCSI_PKT_H__
+
+struct ncsi_pkt_hdr {
+ unsigned char mc_id; /* Management controller ID */
+ unsigned char revision; /* NCSI version - 0x01 */
+ unsigned char reserved; /* Reserved */
+ unsigned char id; /* Packet sequence number */
+ unsigned char type; /* Packet type */
+ unsigned char channel; /* Network controller ID */
+ __be16 length; /* Payload length */
+ __be32 reserved1[2]; /* Reserved */
+};
+
+struct ncsi_cmd_pkt_hdr {
+ struct ncsi_pkt_hdr common; /* Common NCSI packet header */
+};
+
+struct ncsi_rsp_pkt_hdr {
+ struct ncsi_pkt_hdr common; /* Common NCSI packet header */
+ __be16 code; /* Response code */
+ __be16 reason; /* Response reason */
+};
+
+struct ncsi_aen_pkt_hdr {
+ struct ncsi_pkt_hdr common; /* Common NCSI packet header */
+ unsigned char reserved2[3]; /* Reserved */
+ unsigned char type; /* AEN packet type */
+};
+
+/* NCSI common command packet */
+struct ncsi_cmd_pkt {
+ struct ncsi_cmd_pkt_hdr cmd; /* Command header */
+ __be32 checksum; /* Checksum */
+ unsigned char pad[26];
+};
+
+struct ncsi_rsp_pkt {
+ struct ncsi_rsp_pkt_hdr rsp; /* Response header */
+ __be32 checksum; /* Checksum */
+ unsigned char pad[22];
+};
+
+/* Select Package */
+struct ncsi_cmd_sp_pkt {
+ struct ncsi_cmd_pkt_hdr cmd; /* Command header */
+ unsigned char reserved[3]; /* Reserved */
+ unsigned char hw_arbitration; /* HW arbitration */
+ __be32 checksum; /* Checksum */
+ unsigned char pad[22];
+};
+
+/* Disable Channel */
+struct ncsi_cmd_dc_pkt {
+ struct ncsi_cmd_pkt_hdr cmd; /* Command header */
+ unsigned char reserved[3]; /* Reserved */
+ unsigned char ald; /* Allow link down */
+ __be32 checksum; /* Checksum */
+ unsigned char pad[22];
+};
+
+/* Reset Channel */
+struct ncsi_cmd_rc_pkt {
+ struct ncsi_cmd_pkt_hdr cmd; /* Command header */
+ __be32 reserved; /* Reserved */
+ __be32 checksum; /* Checksum */
+ unsigned char pad[22];
+};
+
+/* AEN Enable */
+struct ncsi_cmd_ae_pkt {
+ struct ncsi_cmd_pkt_hdr cmd; /* Command header */
+ unsigned char reserved[3]; /* Reserved */
+ unsigned char mc_id; /* MC ID */
+ __be32 mode; /* AEN working mode */
+ __be32 checksum; /* Checksum */
+ unsigned char pad[18];
+};
+
+/* Set Link */
+struct ncsi_cmd_sl_pkt {
+ struct ncsi_cmd_pkt_hdr cmd; /* Command header */
+ __be32 mode; /* Link working mode */
+ __be32 oem_mode; /* OEM link mode */
+ __be32 checksum; /* Checksum */
+ unsigned char pad[18];
+};
+
+/* Set VLAN Filter */
+struct ncsi_cmd_svf_pkt {
+ struct ncsi_cmd_pkt_hdr cmd; /* Command header */
+ __be16 reserved; /* Reserved */
+ __be16 vlan; /* VLAN ID */
+ __be16 reserved1; /* Reserved */
+ unsigned char index; /* VLAN table index */
+ unsigned char enable; /* Enable or disable */
+ __be32 checksum; /* Checksum */
+ unsigned char pad[18];
+};
+
+/* Enable VLAN */
+struct ncsi_cmd_ev_pkt {
+ struct ncsi_cmd_pkt_hdr cmd; /* Command header */
+ unsigned char reserved[3]; /* Reserved */
+ unsigned char mode; /* VLAN filter mode */
+ __be32 checksum; /* Checksum */
+ unsigned char pad[22];
+};
+
+/* Set MAC Address */
+struct ncsi_cmd_sma_pkt {
+ struct ncsi_cmd_pkt_hdr cmd; /* Command header */
+ unsigned char mac[6]; /* MAC address */
+ unsigned char index; /* MAC table index */
+ unsigned char at_e; /* Addr type and operation */
+ __be32 checksum; /* Checksum */
+ unsigned char pad[18];
+};
+
+/* Enable Broadcast Filter */
+struct ncsi_cmd_ebf_pkt {
+ struct ncsi_cmd_pkt_hdr cmd; /* Command header */
+ __be32 mode; /* Filter mode */
+ __be32 checksum; /* Checksum */
+ unsigned char pad[22];
+};
+
+/* Enable Global Multicast Filter */
+struct ncsi_cmd_egmf_pkt {
+ struct ncsi_cmd_pkt_hdr cmd; /* Command header */
+ __be32 mode; /* Global MC mode */
+ __be32 checksum; /* Checksum */
+ unsigned char pad[22];
+};
+
+/* Set NCSI Flow Control */
+struct ncsi_cmd_snfc_pkt {
+ struct ncsi_cmd_pkt_hdr cmd; /* Command header */
+ unsigned char reserved[3]; /* Reserved */
+ unsigned char mode; /* Flow control mode */
+ __be32 checksum; /* Checksum */
+ unsigned char pad[22];
+};
+
+/* OEM Request Command as per NCSI Specification */
+struct ncsi_cmd_oem_pkt {
+ struct ncsi_cmd_pkt_hdr cmd; /* Command header */
+ __be32 mfr_id; /* Manufacture ID */
+ unsigned char data[]; /* OEM Payload Data */
+};
+
+/* OEM Response Packet as per NCSI Specification */
+struct ncsi_rsp_oem_pkt {
+ struct ncsi_rsp_pkt_hdr rsp; /* Command header */
+ __be32 mfr_id; /* Manufacture ID */
+ unsigned char data[]; /* Payload data */
+};
+
+/* Mellanox Response Data */
+struct ncsi_rsp_oem_mlx_pkt {
+ unsigned char cmd_rev; /* Command Revision */
+ unsigned char cmd; /* Command ID */
+ unsigned char param; /* Parameter */
+ unsigned char optional; /* Optional data */
+ unsigned char data[]; /* Data */
+};
+
+/* Broadcom Response Data */
+struct ncsi_rsp_oem_bcm_pkt {
+ unsigned char ver; /* Payload Version */
+ unsigned char type; /* OEM Command type */
+ __be16 len; /* Payload Length */
+ unsigned char data[]; /* Cmd specific Data */
+};
+
+/* Get Link Status */
+struct ncsi_rsp_gls_pkt {
+ struct ncsi_rsp_pkt_hdr rsp; /* Response header */
+ __be32 status; /* Link status */
+ __be32 other; /* Other indications */
+ __be32 oem_status; /* OEM link status */
+ __be32 checksum;
+ unsigned char pad[10];
+};
+
+/* Get Version ID */
+struct ncsi_rsp_gvi_pkt {
+ struct ncsi_rsp_pkt_hdr rsp; /* Response header */
+ __be32 ncsi_version; /* NCSI version */
+ unsigned char reserved[3]; /* Reserved */
+ unsigned char alpha2; /* NCSI version */
+ unsigned char fw_name[12]; /* f/w name string */
+ __be32 fw_version; /* f/w version */
+ __be16 pci_ids[4]; /* PCI IDs */
+ __be32 mf_id; /* Manufacture ID */
+ __be32 checksum;
+};
+
+/* Get Capabilities */
+struct ncsi_rsp_gc_pkt {
+ struct ncsi_rsp_pkt_hdr rsp; /* Response header */
+ __be32 cap; /* Capabilities */
+ __be32 bc_cap; /* Broadcast cap */
+ __be32 mc_cap; /* Multicast cap */
+ __be32 buf_cap; /* Buffering cap */
+ __be32 aen_cap; /* AEN cap */
+ unsigned char vlan_cnt; /* VLAN filter count */
+ unsigned char mixed_cnt; /* Mix filter count */
+ unsigned char mc_cnt; /* MC filter count */
+ unsigned char uc_cnt; /* UC filter count */
+ unsigned char reserved[2]; /* Reserved */
+ unsigned char vlan_mode; /* VLAN mode */
+ unsigned char channel_cnt; /* Channel count */
+ __be32 checksum; /* Checksum */
+};
+
+/* Get Parameters */
+struct ncsi_rsp_gp_pkt {
+ struct ncsi_rsp_pkt_hdr rsp; /* Response header */
+ unsigned char mac_cnt; /* Number of MAC addr */
+ unsigned char reserved[2]; /* Reserved */
+ unsigned char mac_enable; /* MAC addr enable flags */
+ unsigned char vlan_cnt; /* VLAN tag count */
+ unsigned char reserved1; /* Reserved */
+ __be16 vlan_enable; /* VLAN tag enable flags */
+ __be32 link_mode; /* Link setting */
+ __be32 bc_mode; /* BC filter mode */
+ __be32 valid_modes; /* Valid mode parameters */
+ unsigned char vlan_mode; /* VLAN mode */
+ unsigned char fc_mode; /* Flow control mode */
+ unsigned char reserved2[2]; /* Reserved */
+ __be32 aen_mode; /* AEN mode */
+ unsigned char mac[6]; /* Supported MAC addr */
+ __be16 vlan; /* Supported VLAN tags */
+ __be32 checksum; /* Checksum */
+};
+
+/* Get Controller Packet Statistics */
+struct ncsi_rsp_gcps_pkt {
+ struct ncsi_rsp_pkt_hdr rsp; /* Response header */
+ __be32 cnt_hi; /* Counter cleared */
+ __be32 cnt_lo; /* Counter cleared */
+ __be32 rx_bytes; /* Rx bytes */
+ __be32 tx_bytes; /* Tx bytes */
+ __be32 rx_uc_pkts; /* Rx UC packets */
+ __be32 rx_mc_pkts; /* Rx MC packets */
+ __be32 rx_bc_pkts; /* Rx BC packets */
+ __be32 tx_uc_pkts; /* Tx UC packets */
+ __be32 tx_mc_pkts; /* Tx MC packets */
+ __be32 tx_bc_pkts; /* Tx BC packets */
+ __be32 fcs_err; /* FCS errors */
+ __be32 align_err; /* Alignment errors */
+ __be32 false_carrier; /* False carrier detection */
+ __be32 runt_pkts; /* Rx runt packets */
+ __be32 jabber_pkts; /* Rx jabber packets */
+ __be32 rx_pause_xon; /* Rx pause XON frames */
+ __be32 rx_pause_xoff; /* Rx XOFF frames */
+ __be32 tx_pause_xon; /* Tx XON frames */
+ __be32 tx_pause_xoff; /* Tx XOFF frames */
+ __be32 tx_s_collision; /* Single collision frames */
+ __be32 tx_m_collision; /* Multiple collision frames */
+ __be32 l_collision; /* Late collision frames */
+ __be32 e_collision; /* Excessive collision frames */
+ __be32 rx_ctl_frames; /* Rx control frames */
+ __be32 rx_64_frames; /* Rx 64-bytes frames */
+ __be32 rx_127_frames; /* Rx 65-127 bytes frames */
+ __be32 rx_255_frames; /* Rx 128-255 bytes frames */
+ __be32 rx_511_frames; /* Rx 256-511 bytes frames */
+ __be32 rx_1023_frames; /* Rx 512-1023 bytes frames */
+ __be32 rx_1522_frames; /* Rx 1024-1522 bytes frames */
+ __be32 rx_9022_frames; /* Rx 1523-9022 bytes frames */
+ __be32 tx_64_frames; /* Tx 64-bytes frames */
+ __be32 tx_127_frames; /* Tx 65-127 bytes frames */
+ __be32 tx_255_frames; /* Tx 128-255 bytes frames */
+ __be32 tx_511_frames; /* Tx 256-511 bytes frames */
+ __be32 tx_1023_frames; /* Tx 512-1023 bytes frames */
+ __be32 tx_1522_frames; /* Tx 1024-1522 bytes frames */
+ __be32 tx_9022_frames; /* Tx 1523-9022 bytes frames */
+ __be32 rx_valid_bytes; /* Rx valid bytes */
+ __be32 rx_runt_pkts; /* Rx error runt packets */
+ __be32 rx_jabber_pkts; /* Rx error jabber packets */
+ __be32 checksum; /* Checksum */
+};
+
+/* Get NCSI Statistics */
+struct ncsi_rsp_gns_pkt {
+ struct ncsi_rsp_pkt_hdr rsp; /* Response header */
+ __be32 rx_cmds; /* Rx NCSI commands */
+ __be32 dropped_cmds; /* Dropped commands */
+ __be32 cmd_type_errs; /* Command type errors */
+ __be32 cmd_csum_errs; /* Command checksum errors */
+ __be32 rx_pkts; /* Rx NCSI packets */
+ __be32 tx_pkts; /* Tx NCSI packets */
+ __be32 tx_aen_pkts; /* Tx AEN packets */
+ __be32 checksum; /* Checksum */
+};
+
+/* Get NCSI Pass-through Statistics */
+struct ncsi_rsp_gnpts_pkt {
+ struct ncsi_rsp_pkt_hdr rsp; /* Response header */
+ __be32 tx_pkts; /* Tx packets */
+ __be32 tx_dropped; /* Tx dropped packets */
+ __be32 tx_channel_err; /* Tx channel errors */
+ __be32 tx_us_err; /* Tx undersize errors */
+ __be32 rx_pkts; /* Rx packets */
+ __be32 rx_dropped; /* Rx dropped packets */
+ __be32 rx_channel_err; /* Rx channel errors */
+ __be32 rx_us_err; /* Rx undersize errors */
+ __be32 rx_os_err; /* Rx oversize errors */
+ __be32 checksum; /* Checksum */
+};
+
+/* Get package status */
+struct ncsi_rsp_gps_pkt {
+ struct ncsi_rsp_pkt_hdr rsp; /* Response header */
+ __be32 status; /* Hardware arbitration status */
+ __be32 checksum;
+};
+
+/* Get package UUID */
+struct ncsi_rsp_gpuuid_pkt {
+ struct ncsi_rsp_pkt_hdr rsp; /* Response header */
+ unsigned char uuid[16]; /* UUID */
+ __be32 checksum;
+};
+
+/* AEN: Link State Change */
+struct ncsi_aen_lsc_pkt {
+ struct ncsi_aen_pkt_hdr aen; /* AEN header */
+ __be32 status; /* Link status */
+ __be32 oem_status; /* OEM link status */
+ __be32 checksum; /* Checksum */
+ unsigned char pad[14];
+};
+
+/* AEN: Configuration Required */
+struct ncsi_aen_cr_pkt {
+ struct ncsi_aen_pkt_hdr aen; /* AEN header */
+ __be32 checksum; /* Checksum */
+ unsigned char pad[22];
+};
+
+/* AEN: Host Network Controller Driver Status Change */
+struct ncsi_aen_hncdsc_pkt {
+ struct ncsi_aen_pkt_hdr aen; /* AEN header */
+ __be32 status; /* Status */
+ __be32 checksum; /* Checksum */
+ unsigned char pad[18];
+};
+
+/* NCSI packet revision */
+#define NCSI_PKT_REVISION 0x01
+
+/* NCSI packet commands */
+#define NCSI_PKT_CMD_CIS 0x00 /* Clear Initial State */
+#define NCSI_PKT_CMD_SP 0x01 /* Select Package */
+#define NCSI_PKT_CMD_DP 0x02 /* Deselect Package */
+#define NCSI_PKT_CMD_EC 0x03 /* Enable Channel */
+#define NCSI_PKT_CMD_DC 0x04 /* Disable Channel */
+#define NCSI_PKT_CMD_RC 0x05 /* Reset Channel */
+#define NCSI_PKT_CMD_ECNT 0x06 /* Enable Channel Network Tx */
+#define NCSI_PKT_CMD_DCNT 0x07 /* Disable Channel Network Tx */
+#define NCSI_PKT_CMD_AE 0x08 /* AEN Enable */
+#define NCSI_PKT_CMD_SL 0x09 /* Set Link */
+#define NCSI_PKT_CMD_GLS 0x0a /* Get Link */
+#define NCSI_PKT_CMD_SVF 0x0b /* Set VLAN Filter */
+#define NCSI_PKT_CMD_EV 0x0c /* Enable VLAN */
+#define NCSI_PKT_CMD_DV 0x0d /* Disable VLAN */
+#define NCSI_PKT_CMD_SMA 0x0e /* Set MAC address */
+#define NCSI_PKT_CMD_EBF 0x10 /* Enable Broadcast Filter */
+#define NCSI_PKT_CMD_DBF 0x11 /* Disable Broadcast Filter */
+#define NCSI_PKT_CMD_EGMF 0x12 /* Enable Global Multicast Filter */
+#define NCSI_PKT_CMD_DGMF 0x13 /* Disable Global Multicast Filter */
+#define NCSI_PKT_CMD_SNFC 0x14 /* Set NCSI Flow Control */
+#define NCSI_PKT_CMD_GVI 0x15 /* Get Version ID */
+#define NCSI_PKT_CMD_GC 0x16 /* Get Capabilities */
+#define NCSI_PKT_CMD_GP 0x17 /* Get Parameters */
+#define NCSI_PKT_CMD_GCPS 0x18 /* Get Controller Packet Statistics */
+#define NCSI_PKT_CMD_GNS 0x19 /* Get NCSI Statistics */
+#define NCSI_PKT_CMD_GNPTS 0x1a /* Get NCSI Pass-throu Statistics */
+#define NCSI_PKT_CMD_GPS 0x1b /* Get package status */
+#define NCSI_PKT_CMD_OEM 0x50 /* OEM */
+#define NCSI_PKT_CMD_PLDM 0x51 /* PLDM request over NCSI over RBT */
+#define NCSI_PKT_CMD_GPUUID 0x52 /* Get package UUID */
+
+/* NCSI packet responses */
+#define NCSI_PKT_RSP_CIS (NCSI_PKT_CMD_CIS + 0x80)
+#define NCSI_PKT_RSP_SP (NCSI_PKT_CMD_SP + 0x80)
+#define NCSI_PKT_RSP_DP (NCSI_PKT_CMD_DP + 0x80)
+#define NCSI_PKT_RSP_EC (NCSI_PKT_CMD_EC + 0x80)
+#define NCSI_PKT_RSP_DC (NCSI_PKT_CMD_DC + 0x80)
+#define NCSI_PKT_RSP_RC (NCSI_PKT_CMD_RC + 0x80)
+#define NCSI_PKT_RSP_ECNT (NCSI_PKT_CMD_ECNT + 0x80)
+#define NCSI_PKT_RSP_DCNT (NCSI_PKT_CMD_DCNT + 0x80)
+#define NCSI_PKT_RSP_AE (NCSI_PKT_CMD_AE + 0x80)
+#define NCSI_PKT_RSP_SL (NCSI_PKT_CMD_SL + 0x80)
+#define NCSI_PKT_RSP_GLS (NCSI_PKT_CMD_GLS + 0x80)
+#define NCSI_PKT_RSP_SVF (NCSI_PKT_CMD_SVF + 0x80)
+#define NCSI_PKT_RSP_EV (NCSI_PKT_CMD_EV + 0x80)
+#define NCSI_PKT_RSP_DV (NCSI_PKT_CMD_DV + 0x80)
+#define NCSI_PKT_RSP_SMA (NCSI_PKT_CMD_SMA + 0x80)
+#define NCSI_PKT_RSP_EBF (NCSI_PKT_CMD_EBF + 0x80)
+#define NCSI_PKT_RSP_DBF (NCSI_PKT_CMD_DBF + 0x80)
+#define NCSI_PKT_RSP_EGMF (NCSI_PKT_CMD_EGMF + 0x80)
+#define NCSI_PKT_RSP_DGMF (NCSI_PKT_CMD_DGMF + 0x80)
+#define NCSI_PKT_RSP_SNFC (NCSI_PKT_CMD_SNFC + 0x80)
+#define NCSI_PKT_RSP_GVI (NCSI_PKT_CMD_GVI + 0x80)
+#define NCSI_PKT_RSP_GC (NCSI_PKT_CMD_GC + 0x80)
+#define NCSI_PKT_RSP_GP (NCSI_PKT_CMD_GP + 0x80)
+#define NCSI_PKT_RSP_GCPS (NCSI_PKT_CMD_GCPS + 0x80)
+#define NCSI_PKT_RSP_GNS (NCSI_PKT_CMD_GNS + 0x80)
+#define NCSI_PKT_RSP_GNPTS (NCSI_PKT_CMD_GNPTS + 0x80)
+#define NCSI_PKT_RSP_GPS (NCSI_PKT_CMD_GPS + 0x80)
+#define NCSI_PKT_RSP_OEM (NCSI_PKT_CMD_OEM + 0x80)
+#define NCSI_PKT_RSP_PLDM (NCSI_PKT_CMD_PLDM + 0x80)
+#define NCSI_PKT_RSP_GPUUID (NCSI_PKT_CMD_GPUUID + 0x80)
+
+/* NCSI response code/reason */
+#define NCSI_PKT_RSP_C_COMPLETED 0x0000 /* Command Completed */
+#define NCSI_PKT_RSP_C_FAILED 0x0001 /* Command Failed */
+#define NCSI_PKT_RSP_C_UNAVAILABLE 0x0002 /* Command Unavailable */
+#define NCSI_PKT_RSP_C_UNSUPPORTED 0x0003 /* Command Unsupported */
+#define NCSI_PKT_RSP_R_NO_ERROR 0x0000 /* No Error */
+#define NCSI_PKT_RSP_R_INTERFACE 0x0001 /* Interface not ready */
+#define NCSI_PKT_RSP_R_PARAM 0x0002 /* Invalid Parameter */
+#define NCSI_PKT_RSP_R_CHANNEL 0x0003 /* Channel not Ready */
+#define NCSI_PKT_RSP_R_PACKAGE 0x0004 /* Package not Ready */
+#define NCSI_PKT_RSP_R_LENGTH 0x0005 /* Invalid payload length */
+#define NCSI_PKT_RSP_R_UNKNOWN 0x7fff /* Command type unsupported */
+
+/* NCSI AEN packet type */
+#define NCSI_PKT_AEN 0xFF /* AEN Packet */
+#define NCSI_PKT_AEN_LSC 0x00 /* Link status change */
+#define NCSI_PKT_AEN_CR 0x01 /* Configuration required */
+#define NCSI_PKT_AEN_HNCDSC 0x02 /* HNC driver status change */
+
+#endif /* __NCSI_PKT_H__ */
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * NC-SI PHY
+ *
+ * Copyright (C) 2019, IBM Corporation.
+ */
+
+#include <common.h>
+#include <phy.h>
+
+bool ncsi_active(void);
+void ncsi_receive(struct ethernet_hdr *et, struct ip_udp_hdr *ip,
+ unsigned int len);
+void ncsi_probe_packages(void);
#include <linux/mii.h>
#include <linux/ethtool.h>
#include <linux/mdio.h>
+#include <log.h>
#include <phy_interface.h>
#define PHY_FIXED_ID 0xa5a55a5a
+#define PHY_NCSI_ID 0xbeefcafe
+
/*
* There is no actual id for this.
* This is just a dummy id for gmii2rgmmi converter.
{
struct mii_dev *bus = phydev->bus;
+ if (!bus || !bus->read) {
+ debug("%s: No bus configured\n", __func__);
+ return -1;
+ }
+
return bus->read(bus, phydev->addr, devad, regnum);
}
{
struct mii_dev *bus = phydev->bus;
+ if (!bus || !bus->read) {
+ debug("%s: No bus configured\n", __func__);
+ return -1;
+ }
+
return bus->write(bus, phydev->addr, devad, regnum, val);
}
#ifdef CONFIG_PHYLIB_10G
extern struct phy_driver gen10g_driver;
-/* For now, XGMII is the only 10G interface */
+/*
+ * List all 10G interfaces here, the assumption being that PHYs on these
+ * interfaces are C45
+ */
static inline int is_10g_interface(phy_interface_t interface)
{
- return interface == PHY_INTERFACE_MODE_XGMII;
+ return interface == PHY_INTERFACE_MODE_XGMII ||
+ interface == PHY_INTERFACE_MODE_USXGMII ||
+ interface == PHY_INTERFACE_MODE_XFI;
}
#endif
int phy_xilinx_init(void);
int phy_mscc_init(void);
int phy_fixed_init(void);
+int phy_ncsi_init(void);
int phy_xilinx_gmii2rgmii_init(void);
int board_phy_config(struct phy_device *phydev);
PHY_INTERFACE_MODE_XLAUI,
PHY_INTERFACE_MODE_CAUI2,
PHY_INTERFACE_MODE_CAUI4,
+ PHY_INTERFACE_MODE_NCSI,
PHY_INTERFACE_MODE_XFI,
PHY_INTERFACE_MODE_USXGMII,
PHY_INTERFACE_MODE_NONE, /* Must be last */
[PHY_INTERFACE_MODE_XLAUI] = "xlaui4",
[PHY_INTERFACE_MODE_CAUI2] = "caui2",
[PHY_INTERFACE_MODE_CAUI4] = "caui4",
+ [PHY_INTERFACE_MODE_NCSI] = "NC-SI",
[PHY_INTERFACE_MODE_XFI] = "xfi",
[PHY_INTERFACE_MODE_USXGMII] = "usxgmii",
[PHY_INTERFACE_MODE_NONE] = "",
tosend = min(net_boot_file_size - offset, tosend);
(void)memcpy(dst, (void *)(image_save_addr + offset), tosend);
- debug("%s: block=%d, offset=%ld, len=%d, tosend=%ld\n", __func__,
+ debug("%s: block=%u, offset=%lu, len=%u, tosend=%lu\n", __func__,
block, offset, len, tosend);
return tosend;
}
projects / oweals / u-boot.git / commitdiff