mach-omap2: add AM335x Display PLL register definition
authorHannes Schmelzer <oe5hpm@oevsv.at>
Tue, 9 Jan 2018 18:01:31 +0000 (19:01 +0100)
committerAnatolij Gustschin <agust@denx.de>
Thu, 11 Jan 2018 14:16:34 +0000 (15:16 +0100)
Adds the register definition of the Display DPLL

Signed-off-by: Hannes Schmelzer <oe5hpm@oevsv.at>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
arch/arm/include/asm/arch-am33xx/clock.h
arch/arm/mach-omap2/am33xx/clock_am33xx.c

index 5399bb81f0bbed6988be3b00d101ea128ad60500..9dbcd3a4075c2210d35c65808c622051d2b4602c 100644 (file)
@@ -104,6 +104,7 @@ extern const struct dpll_regs dpll_mpu_regs;
 extern const struct dpll_regs dpll_core_regs;
 extern const struct dpll_regs dpll_per_regs;
 extern const struct dpll_regs dpll_ddr_regs;
+extern const struct dpll_regs dpll_disp_regs;
 extern const struct dpll_params dpll_mpu_opp[NUM_CRYSTAL_FREQ][NUM_OPPS];
 extern const struct dpll_params dpll_core_1000MHz[NUM_CRYSTAL_FREQ];
 extern const struct dpll_params dpll_per_192MHz[NUM_CRYSTAL_FREQ];
index 1780bbdb6fb6fa16fb9ec0fef17a447f141f6e99..9ab4d250d275320486adac898b2e0a81a8d02414 100644 (file)
@@ -52,6 +52,13 @@ const struct dpll_regs dpll_ddr_regs = {
        .cm_div_m2_dpll         = CM_WKUP + 0xA0,
 };
 
+const struct dpll_regs dpll_disp_regs = {
+       .cm_clkmode_dpll        = CM_WKUP + 0x98,
+       .cm_idlest_dpll         = CM_WKUP + 0x48,
+       .cm_clksel_dpll         = CM_WKUP + 0x54,
+       .cm_div_m2_dpll         = CM_WKUP + 0xA4,
+};
+
 struct dpll_params dpll_mpu_opp100 = {
                CONFIG_SYS_MPUCLK, OSC-1, 1, -1, -1, -1, -1};
 const struct dpll_params dpll_core_opp100 = {