Tegra114: Add arch-tegra114 include files
authorTom Warren <twarren.nvidia@gmail.com>
Mon, 28 Jan 2013 13:32:07 +0000 (13:32 +0000)
committerTom Warren <twarren@nvidia.com>
Mon, 11 Feb 2013 17:35:25 +0000 (10:35 -0700)
Common Tegra files are in arch-tegra, shared between T20/T30/T114.
Tegra114-specific headers are in arch-tegra114. Note that some of
these will be filled in as more T114 support is added (drivers,
WB/LP0 support, etc.).

Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
15 files changed:
arch/arm/include/asm/arch-tegra/clk_rst.h
arch/arm/include/asm/arch-tegra/gp_padctrl.h
arch/arm/include/asm/arch-tegra/pmc.h
arch/arm/include/asm/arch-tegra/tegra.h
arch/arm/include/asm/arch-tegra114/clock-tables.h [new file with mode: 0644]
arch/arm/include/asm/arch-tegra114/clock.h [new file with mode: 0644]
arch/arm/include/asm/arch-tegra114/flow.h [new file with mode: 0644]
arch/arm/include/asm/arch-tegra114/funcmux.h [new file with mode: 0644]
arch/arm/include/asm/arch-tegra114/gp_padctrl.h [new file with mode: 0644]
arch/arm/include/asm/arch-tegra114/gpio.h [new file with mode: 0644]
arch/arm/include/asm/arch-tegra114/hardware.h [new file with mode: 0644]
arch/arm/include/asm/arch-tegra114/pinmux.h [new file with mode: 0644]
arch/arm/include/asm/arch-tegra114/pmu.h [new file with mode: 0644]
arch/arm/include/asm/arch-tegra114/spl.h [new file with mode: 0644]
arch/arm/include/asm/arch-tegra114/tegra.h [new file with mode: 0644]

index b64aa7d6cfd1860dadd45f018e50aba6d0452b89..c754ec753b0196ac49da8ce48fa5f14cae0fed96 100644 (file)
@@ -121,16 +121,43 @@ struct clk_rst_ctlr {
        uint crc_clk_cpug_cmplx;        /* _CLK_CPUG_CMPLX_0,       0x378 */
        uint crc_clk_cpulp_cmplx;       /* _CLK_CPULP_CMPLX_0,      0x37C */
        uint crc_cpu_softrst_ctrl;      /* _CPU_SOFTRST_CTRL_0,     0x380 */
-       uint crc_reserved33[11];        /* _reserved_33,        0x384-3ac */
+       uint crc_cpu_softrst_ctrl1;     /* _CPU_SOFTRST_CTR1L_0,    0x384 */
+       uint crc_cpu_softrst_ctrl2;     /* _CPU_SOFTRST_CTRL2_0,    0x388 */
+       uint crc_reserved33[9];         /* _reserved_33,        0x38c-3ac */
        uint crc_clk_src_vw[TEGRA_CLK_SOURCES_VW]; /* _G3D2_0..., 0x3b0-0x42c */
        /* _RST_DEV_V/W_SET_0 0x430 ~ 0x43c */
        struct clk_set_clr crc_rst_dev_ex_vw[TEGRA_CLK_REGS_VW];
        /* _CLK_ENB_V/W_CLR_0 0x440 ~ 0x44c */
        struct clk_set_clr crc_clk_enb_ex_vw[TEGRA_CLK_REGS_VW];
-       uint crc_reserved40[12];        /* _reserved_40,        0x450-47C */
-       uint crc_pll_cfg0;              /* _PLL_CFG0_0,         0x480 */
-       uint crc_pll_cfg1;              /* _PLL_CFG1_0,         0x484 */
-       uint crc_pll_cfg2;              /* _PLL_CFG2_0,         0x488 */
+       /* Additional (T114) registers */
+       uint crc_rst_cpug_cmplx_set;    /* _RST_CPUG_CMPLX_SET_0,  0x450 */
+       uint crc_rst_cpug_cmplx_clr;    /* _RST_CPUG_CMPLX_CLR_0,  0x454 */
+       uint crc_rst_cpulp_cmplx_set;   /* _RST_CPULP_CMPLX_SET_0, 0x458 */
+       uint crc_rst_cpulp_cmplx_clr;   /* _RST_CPULP_CMPLX_CLR_0, 0x45C */
+       uint crc_clk_cpug_cmplx_set;    /* _CLK_CPUG_CMPLX_SET_0,  0x460 */
+       uint crc_clk_cpug_cmplx_clr;    /* _CLK_CPUG_CMPLX_CLR_0,  0x464 */
+       uint crc_clk_cpulp_cmplx_set;   /* _CLK_CPULP_CMPLX_SET_0, 0x468 */
+       uint crc_clk_cpulp_cmplx_clr;   /* _CLK_CPULP_CMPLX_CLR_0, 0x46C */
+       uint crc_cpu_cmplx_status;      /* _CPU_CMPLX_STATUS_0,    0x470 */
+       uint crc_reserved40[1];         /* _reserved_40,        0x474 */
+       uint crc_intstatus;             /* __INTSTATUS_0,       0x478 */
+       uint crc_intmask;               /* __INTMASK_0,         0x47C */
+       uint crc_utmip_pll_cfg0;        /* _UTMIP_PLL_CFG0_0,   0x480 */
+       uint crc_utmip_pll_cfg1;        /* _UTMIP_PLL_CFG1_0,   0x484 */
+       uint crc_utmip_pll_cfg2;        /* _UTMIP_PLL_CFG2_0,   0x488 */
+
+       uint crc_plle_aux;              /* _PLLE_AUX_0,         0x48C */
+       uint crc_sata_pll_cfg0;         /* _SATA_PLL_CFG0_0,    0x490 */
+       uint crc_sata_pll_cfg1;         /* _SATA_PLL_CFG1_0,    0x494 */
+       uint crc_pcie_pll_cfg0;         /* _PCIE_PLL_CFG0_0,    0x498 */
+
+       uint crc_prog_audio_dly_clk;    /* _PROG_AUDIO_DLY_CLK_0, 0x49C */
+       uint crc_audio_sync_clk_i2s0;   /* _AUDIO_SYNC_CLK_I2S0_0, 0x4A0 */
+       uint crc_audio_sync_clk_i2s1;   /* _AUDIO_SYNC_CLK_I2S1_0, 0x4A4 */
+       uint crc_audio_sync_clk_i2s2;   /* _AUDIO_SYNC_CLK_I2S2_0, 0x4A8 */
+       uint crc_audio_sync_clk_i2s3;   /* _AUDIO_SYNC_CLK_I2S3_0, 0x4AC */
+       uint crc_audio_sync_clk_i2s4;   /* _AUDIO_SYNC_CLK_I2S4_0, 0x4B0 */
+       uint crc_audio_sync_clk_spdif;  /* _AUDIO_SYNC_CLK_SPDIF_0, 0x4B4 */
 };
 
 /* CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0 */
@@ -279,4 +306,23 @@ enum {
 #define CLK_SYS_RATE_APB_RATE_SHIFT     0
 #define CLK_SYS_RATE_APB_RATE_MASK      (3 << CLK_SYS_RATE_AHB_RATE_SHIFT)
 
+/* CLK_RST_CONTROLLER_RST_CPUxx_CMPLX_CLR */
+#define CLR_CPURESET0   (1 << 0)
+#define CLR_CPURESET1   (1 << 1)
+#define CLR_CPURESET2   (1 << 2)
+#define CLR_CPURESET3   (1 << 3)
+#define CLR_DBGRESET0   (1 << 12)
+#define CLR_DBGRESET1   (1 << 13)
+#define CLR_DBGRESET2   (1 << 14)
+#define CLR_DBGRESET3   (1 << 15)
+#define CLR_CORERESET0  (1 << 16)
+#define CLR_CORERESET1  (1 << 17)
+#define CLR_CORERESET2  (1 << 18)
+#define CLR_CORERESET3  (1 << 19)
+#define CLR_CXRESET0    (1 << 20)
+#define CLR_CXRESET1    (1 << 21)
+#define CLR_CXRESET2    (1 << 22)
+#define CLR_CXRESET3    (1 << 23)
+#define CLR_NONCPURESET (1 << 29)
+
 #endif /* _TEGRA_CLK_RST_H_ */
index e6085a052480feedfc3d332714693b5afead0538..209abf160a3cb78e1c861c2b1f75c231a0aa317e 100644 (file)
@@ -35,5 +35,6 @@
 /* CHIPID field returned from APB_MISC_GP_HIDREV register */
 #define CHIPID_TEGRA20                 0x20
 #define CHIPID_TEGRA30                 0x30
+#define CHIPID_TEGRA114                        0x35
 
 #endif /* _TEGRA_GP_PADCTRL_H_ */
index b1d47cd2e3ef24949ce9f475bd2618a992056e99..1bcdcf8eec7257efa7ab7839f9ecaa8bf7f29bb8 100644 (file)
@@ -128,5 +128,13 @@ struct pmc_ctlr {
 #define START_CP       (1 << 8)
 
 #define CPUPWRREQ_OE   (1 << 16)
+#define CPUPWRREQ_POL  (1 << 15)
+
+#define CRAILID                (0)
+#define CE0ID          (14)
+#define C0NCID         (15)
+#define CRAIL          (1 << CRAILID)
+#define CE0            (1 << CE0ID)
+#define C0NC           (1 << C0NCID)
 
 #endif /* PMC_H */
index 5273fa1125c64d789439138f3a2472e8b12fb65b..bf7229d8ace9fbc09461342d916dd04498a018b8 100644 (file)
@@ -79,6 +79,7 @@ enum {
        SKU_ID_AP25E            = 0x1b,
        SKU_ID_T25E             = 0x1c,
        SKU_ID_T30              = 0x81, /* Cardhu value */
+       SKU_ID_T114_ENG         = 0x00, /* Dalmore value, unfused */
 };
 
 /*
@@ -91,6 +92,7 @@ enum {
        TEGRA_SOC_T20,
        TEGRA_SOC_T25,
        TEGRA_SOC_T30,
+       TEGRA_SOC_T114,
 
        TEGRA_SOC_CNT,
        TEGRA_SOC_UNKNOWN       = -1,
diff --git a/arch/arm/include/asm/arch-tegra114/clock-tables.h b/arch/arm/include/asm/arch-tegra114/clock-tables.h
new file mode 100644 (file)
index 0000000..d8fa0e1
--- /dev/null
@@ -0,0 +1,402 @@
+/*
+ * Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* Tegra114 clock PLL tables */
+
+#ifndef _TEGRA114_CLOCK_TABLES_H_
+#define _TEGRA114_CLOCK_TABLES_H_
+
+/* The PLLs supported by the hardware */
+enum clock_id {
+       CLOCK_ID_FIRST,
+       CLOCK_ID_CGENERAL = CLOCK_ID_FIRST,
+       CLOCK_ID_MEMORY,
+       CLOCK_ID_PERIPH,
+       CLOCK_ID_AUDIO,
+       CLOCK_ID_USB,
+       CLOCK_ID_DISPLAY,
+
+       /* now the simple ones */
+       CLOCK_ID_FIRST_SIMPLE,
+       CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE,
+       CLOCK_ID_EPCI,
+       CLOCK_ID_SFROM32KHZ,
+
+       /* These are the base clocks (inputs to the Tegra SOC) */
+       CLOCK_ID_32KHZ,
+       CLOCK_ID_OSC,
+
+       CLOCK_ID_COUNT, /* number of PLLs */
+       CLOCK_ID_DISPLAY2,      /* placeholder */
+       CLOCK_ID_NONE = -1,
+};
+
+/* The clocks supported by the hardware */
+enum periph_id {
+       PERIPH_ID_FIRST,
+
+       /* Low word: 31:0 (DEVICES_L) */
+       PERIPH_ID_CPU = PERIPH_ID_FIRST,
+       PERIPH_ID_COP,
+       PERIPH_ID_TRIGSYS,
+       PERIPH_ID_RESERVED3,
+       PERIPH_ID_RTC,
+       PERIPH_ID_TMR,
+       PERIPH_ID_UART1,
+       PERIPH_ID_UART2,
+
+       /* 8 */
+       PERIPH_ID_GPIO,
+       PERIPH_ID_SDMMC2,
+       PERIPH_ID_SPDIF,
+       PERIPH_ID_I2S1,
+       PERIPH_ID_I2C1,
+       PERIPH_ID_NDFLASH,
+       PERIPH_ID_SDMMC1,
+       PERIPH_ID_SDMMC4,
+
+       /* 16 */
+       PERIPH_ID_RESERVED16,
+       PERIPH_ID_PWM,
+       PERIPH_ID_I2S2,
+       PERIPH_ID_EPP,
+       PERIPH_ID_VI,
+       PERIPH_ID_2D,
+       PERIPH_ID_USBD,
+       PERIPH_ID_ISP,
+
+       /* 24 */
+       PERIPH_ID_3D,
+       PERIPH_ID_RESERVED24,
+       PERIPH_ID_DISP2,
+       PERIPH_ID_DISP1,
+       PERIPH_ID_HOST1X,
+       PERIPH_ID_VCP,
+       PERIPH_ID_I2S0,
+       PERIPH_ID_CACHE2,
+
+       /* Middle word: 63:32 (DEVICES_H) */
+       PERIPH_ID_MEM,
+       PERIPH_ID_AHBDMA,
+       PERIPH_ID_APBDMA,
+       PERIPH_ID_RESERVED35,
+       PERIPH_ID_KBC,
+       PERIPH_ID_STAT_MON,
+       PERIPH_ID_PMC,
+       PERIPH_ID_FUSE,
+
+       /* 40 */
+       PERIPH_ID_KFUSE,
+       PERIPH_ID_SBC1,
+       PERIPH_ID_SNOR,
+       PERIPH_ID_RESERVED43,
+       PERIPH_ID_SBC2,
+       PERIPH_ID_RESERVED45,
+       PERIPH_ID_SBC3,
+       PERIPH_ID_I2C5,
+
+       /* 48 */
+       PERIPH_ID_DSI,
+       PERIPH_ID_TVO,
+       PERIPH_ID_MIPI,
+       PERIPH_ID_HDMI,
+       PERIPH_ID_CSI,
+       PERIPH_ID_TVDAC,
+       PERIPH_ID_I2C2,
+       PERIPH_ID_UART3,
+
+       /* 56 */
+       PERIPH_ID_RESERVED56,
+       PERIPH_ID_EMC,
+       PERIPH_ID_USB2,
+       PERIPH_ID_USB3,
+       PERIPH_ID_MPE,
+       PERIPH_ID_VDE,
+       PERIPH_ID_BSEA,
+       PERIPH_ID_BSEV,
+
+       /* Upper word 95:64 (DEVICES_U) */
+       PERIPH_ID_SPEEDO,
+       PERIPH_ID_UART4,
+       PERIPH_ID_UART5,
+       PERIPH_ID_I2C3,
+       PERIPH_ID_SBC4,
+       PERIPH_ID_SDMMC3,
+       PERIPH_ID_PCIE,
+       PERIPH_ID_OWR,
+
+       /* 72 */
+       PERIPH_ID_AFI,
+       PERIPH_ID_CORESIGHT,
+       PERIPH_ID_PCIEXCLK,
+       PERIPH_ID_AVPUCQ,
+       PERIPH_ID_RESERVED76,
+       PERIPH_ID_RESERVED77,
+       PERIPH_ID_RESERVED78,
+       PERIPH_ID_DTV,
+
+       /* 80 */
+       PERIPH_ID_NANDSPEED,
+       PERIPH_ID_I2CSLOW,
+       PERIPH_ID_DSIB,
+       PERIPH_ID_RESERVED83,
+       PERIPH_ID_IRAMA,
+       PERIPH_ID_IRAMB,
+       PERIPH_ID_IRAMC,
+       PERIPH_ID_IRAMD,
+
+       /* 88 */
+       PERIPH_ID_CRAM2,
+       PERIPH_ID_RESERVED89,
+       PERIPH_ID_MDOUBLER,
+       PERIPH_ID_RESERVED91,
+       PERIPH_ID_SUSOUT,
+       PERIPH_ID_RESERVED93,
+       PERIPH_ID_RESERVED94,
+       PERIPH_ID_RESERVED95,
+
+       PERIPH_ID_VW_FIRST,
+       /* V word: 31:0 */
+       PERIPH_ID_CPUG = PERIPH_ID_VW_FIRST,
+       PERIPH_ID_CPULP,
+       PERIPH_ID_3D2,
+       PERIPH_ID_MSELECT,
+       PERIPH_ID_TSENSOR,
+       PERIPH_ID_I2S3,
+       PERIPH_ID_I2S4,
+       PERIPH_ID_I2C4,
+
+       /* 104 */
+       PERIPH_ID_SBC5,
+       PERIPH_ID_SBC6,
+       PERIPH_ID_AUDIO,
+       PERIPH_ID_APBIF,
+       PERIPH_ID_DAM0,
+       PERIPH_ID_DAM1,
+       PERIPH_ID_DAM2,
+       PERIPH_ID_HDA2CODEC2X,
+
+       /* 112 */
+       PERIPH_ID_ATOMICS,
+       PERIPH_ID_EX_RESERVED17,
+       PERIPH_ID_EX_RESERVED18,
+       PERIPH_ID_EX_RESERVED19,
+       PERIPH_ID_EX_RESERVED20,
+       PERIPH_ID_EX_RESERVED21,
+       PERIPH_ID_EX_RESERVED22,
+       PERIPH_ID_ACTMON,
+
+       /* 120 */
+       PERIPH_ID_EX_RESERVED24,
+       PERIPH_ID_EX_RESERVED25,
+       PERIPH_ID_EX_RESERVED26,
+       PERIPH_ID_EX_RESERVED27,
+       PERIPH_ID_SATA,
+       PERIPH_ID_HDA,
+       PERIPH_ID_EX_RESERVED30,
+       PERIPH_ID_EX_RESERVED31,
+
+       /* W word: 31:0 */
+       PERIPH_ID_HDA2HDMICODEC,
+       PERIPH_ID_RESERVED1_SATACOLD,
+       PERIPH_ID_RESERVED2_PCIERX0,
+       PERIPH_ID_RESERVED3_PCIERX1,
+       PERIPH_ID_RESERVED4_PCIERX2,
+       PERIPH_ID_RESERVED5_PCIERX3,
+       PERIPH_ID_RESERVED6_PCIERX4,
+       PERIPH_ID_RESERVED7_PCIERX5,
+
+       /* 136 */
+       PERIPH_ID_CEC,
+       PERIPH_ID_PCIE2_IOBIST,
+       PERIPH_ID_EMC_IOBIST,
+       PERIPH_ID_HDMI_IOBIST,
+       PERIPH_ID_SATA_IOBIST,
+       PERIPH_ID_MIPI_IOBIST,
+       PERIPH_ID_EMC1_IOBIST,
+       PERIPH_ID_XUSB,
+
+       /* 144 */
+       PERIPH_ID_CILAB,
+       PERIPH_ID_CILCD,
+       PERIPH_ID_CILE,
+       PERIPH_ID_DSIA_LP,
+       PERIPH_ID_DSIB_LP,
+       PERIPH_ID_RESERVED21_ENTROPY,
+       PERIPH_ID_RESERVED22_W,
+       PERIPH_ID_RESERVED23_W,
+
+       /* 152 */
+       PERIPH_ID_RESERVED24_W,
+       PERIPH_ID_AMX0,
+       PERIPH_ID_ADX0,
+       PERIPH_ID_DVFS,
+       PERIPH_ID_XUSB_SS,
+       PERIPH_ID_EMC_DLL,
+       PERIPH_ID_MC1,
+       PERIPH_ID_EMC1,
+
+       PERIPH_ID_COUNT,
+       PERIPH_ID_NONE = -1,
+};
+
+enum pll_out_id {
+       PLL_OUT1,
+       PLL_OUT2,
+       PLL_OUT3,
+       PLL_OUT4
+};
+
+/*
+ * Clock peripheral IDs which sadly don't match up with PERIPH_ID. we want
+ * callers to use the PERIPH_ID for all access to peripheral clocks to avoid
+ * confusion bewteen PERIPH_ID_... and PERIPHC_...
+ *
+ * We don't call this CLOCK_PERIPH_ID or PERIPH_CLOCK_ID as it would just be
+ * confusing.
+ */
+enum periphc_internal_id {
+       /* 0x00 */
+       PERIPHC_I2S1,
+       PERIPHC_I2S2,
+       PERIPHC_SPDIF_OUT,
+       PERIPHC_SPDIF_IN,
+       PERIPHC_PWM,
+       PERIPHC_05h,
+       PERIPHC_SBC2,
+       PERIPHC_SBC3,
+
+       /* 0x08 */
+       PERIPHC_08h,
+       PERIPHC_I2C1,
+       PERIPHC_I2C5,
+       PERIPHC_0bh,
+       PERIPHC_0ch,
+       PERIPHC_SBC1,
+       PERIPHC_DISP1,
+       PERIPHC_DISP2,
+
+       /* 0x10 */
+       PERIPHC_CVE,
+       PERIPHC_11h,
+       PERIPHC_VI,
+       PERIPHC_13h,
+       PERIPHC_SDMMC1,
+       PERIPHC_SDMMC2,
+       PERIPHC_G3D,
+       PERIPHC_G2D,
+
+       /* 0x18 */
+       PERIPHC_NDFLASH,
+       PERIPHC_SDMMC4,
+       PERIPHC_VFIR,
+       PERIPHC_EPP,
+       PERIPHC_MPE,
+       PERIPHC_MIPI,
+       PERIPHC_UART1,
+       PERIPHC_UART2,
+
+       /* 0x20 */
+       PERIPHC_HOST1X,
+       PERIPHC_21h,
+       PERIPHC_TVO,
+       PERIPHC_HDMI,
+       PERIPHC_24h,
+       PERIPHC_TVDAC,
+       PERIPHC_I2C2,
+       PERIPHC_EMC,
+
+       /* 0x28 */
+       PERIPHC_UART3,
+       PERIPHC_29h,
+       PERIPHC_VI_SENSOR,
+       PERIPHC_2bh,
+       PERIPHC_2ch,
+       PERIPHC_SBC4,
+       PERIPHC_I2C3,
+       PERIPHC_SDMMC3,
+
+       /* 0x30 */
+       PERIPHC_UART4,
+       PERIPHC_UART5,
+       PERIPHC_VDE,
+       PERIPHC_OWR,
+       PERIPHC_NOR,
+       PERIPHC_CSITE,
+       PERIPHC_I2S0,
+       PERIPHC_37h,
+
+       PERIPHC_VW_FIRST,
+       /* 0x38 */
+       PERIPHC_G3D2 = PERIPHC_VW_FIRST,
+       PERIPHC_MSELECT,
+       PERIPHC_TSENSOR,
+       PERIPHC_I2S3,
+       PERIPHC_I2S4,
+       PERIPHC_I2C4,
+       PERIPHC_SBC5,
+       PERIPHC_SBC6,
+
+       /* 0x40 */
+       PERIPHC_AUDIO,
+       PERIPHC_41h,
+       PERIPHC_DAM0,
+       PERIPHC_DAM1,
+       PERIPHC_DAM2,
+       PERIPHC_HDA2CODEC2X,
+       PERIPHC_ACTMON,
+       PERIPHC_EXTPERIPH1,
+
+       /* 0x48 */
+       PERIPHC_EXTPERIPH2,
+       PERIPHC_EXTPERIPH3,
+       PERIPHC_NANDSPEED,
+       PERIPHC_I2CSLOW,
+       PERIPHC_SYS,
+       PERIPHC_SPEEDO,
+       PERIPHC_4eh,
+       PERIPHC_4fh,
+
+       /* 0x50 */
+       PERIPHC_50h,
+       PERIPHC_51h,
+       PERIPHC_52h,
+       PERIPHC_53h,
+       PERIPHC_SATAOOB,
+       PERIPHC_SATA,
+       PERIPHC_HDA,
+
+       PERIPHC_COUNT,
+
+       PERIPHC_NONE = -1,
+};
+
+/* Converts a clock number to a clock register: 0=L, 1=H, 2=U, 0=V, 1=W */
+#define PERIPH_REG(id) \
+       (id < PERIPH_ID_VW_FIRST) ? \
+               ((id) >> 5) : ((id - PERIPH_ID_VW_FIRST) >> 5)
+
+/* Mask value for a clock (within PERIPH_REG(id)) */
+#define PERIPH_MASK(id) (1 << ((id) & 0x1f))
+
+/* return 1 if a PLL ID is in range */
+#define clock_id_is_pll(id) ((id) >= CLOCK_ID_FIRST && (id) < CLOCK_ID_COUNT)
+
+/* return 1 if a peripheral ID is in range */
+#define clock_periph_id_isvalid(id) ((id) >= PERIPH_ID_FIRST && \
+               (id) < PERIPH_ID_COUNT)
+
+#endif /* _TEGRA114_CLOCK_TABLES_H_ */
diff --git a/arch/arm/include/asm/arch-tegra114/clock.h b/arch/arm/include/asm/arch-tegra114/clock.h
new file mode 100644 (file)
index 0000000..abbefcd
--- /dev/null
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* Tegra114 clock control functions */
+
+#ifndef _TEGRA114_CLOCK_H_
+#define _TEGRA114_CLOCK_H_
+
+#include <asm/arch-tegra/clock.h>
+
+/* CLK_RST_CONTROLLER_OSC_CTRL_0 */
+#define OSC_FREQ_SHIFT          28
+#define OSC_FREQ_MASK           (0xF << OSC_FREQ_SHIFT)
+
+#endif /* _TEGRA114_CLOCK_H_ */
diff --git a/arch/arm/include/asm/arch-tegra114/flow.h b/arch/arm/include/asm/arch-tegra114/flow.h
new file mode 100644 (file)
index 0000000..c7eb051
--- /dev/null
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _TEGRA114_FLOW_H_
+#define _TEGRA114_FLOW_H_
+
+struct flow_ctlr {
+       u32 halt_cpu_events;
+       u32 halt_cop_events;
+       u32 cpu_csr;
+       u32 cop_csr;
+       u32 xrq_events;
+       u32 halt_cpu1_events;
+       u32 cpu1_csr;
+       u32 halt_cpu2_events;
+       u32 cpu2_csr;
+       u32 halt_cpu3_events;
+       u32 cpu3_csr;
+       u32 cluster_control;
+};
+
+#endif /* _TEGRA114_FLOW_H_ */
diff --git a/arch/arm/include/asm/arch-tegra114/funcmux.h b/arch/arm/include/asm/arch-tegra114/funcmux.h
new file mode 100644 (file)
index 0000000..7f48f25
--- /dev/null
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* Tegra114 high-level function multiplexing */
+
+#ifndef _TEGRA114_FUNCMUX_H_
+#define _TEGRA114_FUNCMUX_H_
+
+#include <asm/arch-tegra/funcmux.h>
+
+/* Configs supported by the func mux */
+enum {
+       FUNCMUX_DEFAULT = 0,    /* default config */
+
+       /* UART configs */
+       FUNCMUX_UART4_GMI = 0,
+};
+#endif /* _TEGRA114_FUNCMUX_H_ */
diff --git a/arch/arm/include/asm/arch-tegra114/gp_padctrl.h b/arch/arm/include/asm/arch-tegra114/gp_padctrl.h
new file mode 100644 (file)
index 0000000..c538bdd
--- /dev/null
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _TEGRA114_GP_PADCTRL_H_
+#define _TEGRA114_GP_PADCTRL_H_
+
+#include <asm/arch-tegra/gp_padctrl.h>
+
+/* APB_MISC_GP and padctrl registers */
+struct apb_misc_gp_ctlr {
+       u32     modereg;        /* 0x00: APB_MISC_GP_MODEREG */
+       u32     hidrev;         /* 0x04: APB_MISC_GP_HIDREV */
+       u32     reserved0[22];  /* 0x08 - 0x5C: */
+       u32     emu_revid;      /* 0x60: APB_MISC_GP_EMU_REVID */
+       u32     xactor_scratch; /* 0x64: APB_MISC_GP_XACTOR_SCRATCH */
+       u32     aocfg1;         /* 0x68: APB_MISC_GP_AOCFG1PADCTRL */
+       u32     aocfg2;         /* 0x6c: APB_MISC_GP_AOCFG2PADCTRL */
+       u32     atcfg1;         /* 0x70: APB_MISC_GP_ATCFG1PADCTRL */
+       u32     atcfg2;         /* 0x74: APB_MISC_GP_ATCFG2PADCTRL */
+       u32     atcfg3;         /* 0x78: APB_MISC_GP_ATCFG3PADCTRL */
+       u32     atcfg4;         /* 0x7C: APB_MISC_GP_ATCFG4PADCTRL */
+       u32     atcfg5;         /* 0x80: APB_MISC_GP_ATCFG5PADCTRL */
+       u32     cdev1cfg;       /* 0x84: APB_MISC_GP_CDEV1CFGPADCTRL */
+       u32     cdev2cfg;       /* 0x88: APB_MISC_GP_CDEV2CFGPADCTRL */
+       u32     csuscfg;        /* 0x8C: APB_MISC_GP_CSUSCFGPADCTRL */
+       u32     dap1cfg;        /* 0x90: APB_MISC_GP_DAP1CFGPADCTRL */
+       u32     dap2cfg;        /* 0x94: APB_MISC_GP_DAP2CFGPADCTRL */
+       u32     dap3cfg;        /* 0x98: APB_MISC_GP_DAP3CFGPADCTRL */
+       u32     dap4cfg;        /* 0x9C: APB_MISC_GP_DAP4CFGPADCTRL */
+       u32     dbgcfg;         /* 0xA0: APB_MISC_GP_DBGCFGPADCTRL */
+       u32     lcdcfg1;        /* 0xA4: APB_MISC_GP_LCDCFG1PADCTRL */
+       u32     lcdcfg2;        /* 0xA8: APB_MISC_GP_LCDCFG2PADCTRL */
+       u32     sdio2cfg;       /* 0xAC: APB_MISC_GP_SDIO2CFGPADCTRL */
+       u32     sdio3cfg;       /* 0xB0: APB_MISC_GP_SDIO3CFGPADCTRL */
+       u32     spicfg;         /* 0xB4: APB_MISC_GP_SPICFGPADCTRL */
+       u32     uaacfg;         /* 0xB8: APB_MISC_GP_UAACFGPADCTRL */
+       u32     uabcfg;         /* 0xBC: APB_MISC_GP_UABCFGPADCTRL */
+       u32     uart2cfg;       /* 0xC0: APB_MISC_GP_UART2CFGPADCTRL */
+       u32     uart3cfg;       /* 0xC4: APB_MISC_GP_UART3CFGPADCTRL */
+       u32     vicfg1;         /* 0xC8: APB_MISC_GP_VICFG1PADCTRL */
+       u32     vivttgen;       /* 0xCC: APB_MISC_GP_VIVTTGENPADCTRL */
+       u32     reserved1[7];   /* 0xD0-0xE8: */
+       u32     sdio1cfg;       /* 0xEC: APB_MISC_GP_SDIO1CFGPADCTRL */
+};
+
+#endif /* _TEGRA114_GP_PADCTRL_H_ */
diff --git a/arch/arm/include/asm/arch-tegra114/gpio.h b/arch/arm/include/asm/arch-tegra114/gpio.h
new file mode 100644 (file)
index 0000000..21853b6
--- /dev/null
@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _TEGRA114_GPIO_H_
+#define _TEGRA114_GPIO_H_
+
+/*
+ * The Tegra114 GPIO controller has 246 GPIOS in 8 banks of 4 ports,
+ * each with 8 GPIOs.
+ */
+#define TEGRA_GPIO_PORTS       4       /* number of ports per bank */
+#define TEGRA_GPIO_BANKS       8       /* number of banks */
+
+#include <asm/arch-tegra/gpio.h>
+#include <asm/arch-tegra30/gpio.h>
+
+#endif /* _TEGRA114_GPIO_H_ */
diff --git a/arch/arm/include/asm/arch-tegra114/hardware.h b/arch/arm/include/asm/arch-tegra114/hardware.h
new file mode 100644 (file)
index 0000000..c21fbb6
--- /dev/null
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _TEGRA114_HARDWARE_H_
+#define _TEGRA114_HARDWARE_H_
+
+/* include tegra specific hardware definitions */
+
+#endif /* _TEGRA114_HARDWARE_H_ */
diff --git a/arch/arm/include/asm/arch-tegra114/pinmux.h b/arch/arm/include/asm/arch-tegra114/pinmux.h
new file mode 100644 (file)
index 0000000..fd22930
--- /dev/null
@@ -0,0 +1,618 @@
+/*
+ * Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _TEGRA114_PINMUX_H_
+#define _TEGRA114_PINMUX_H_
+
+/*
+ * Pin groups which we adjust. There are three basic attributes of each pin
+ * group which use this enum:
+ *
+ *     - function
+ *     - pullup / pulldown
+ *     - tristate or normal
+ */
+enum pmux_pingrp {
+       PINGRP_ULPI_DATA0 = 0,  /* offset 0x3000 */
+       PINGRP_ULPI_DATA1,
+       PINGRP_ULPI_DATA2,
+       PINGRP_ULPI_DATA3,
+       PINGRP_ULPI_DATA4,
+       PINGRP_ULPI_DATA5,
+       PINGRP_ULPI_DATA6,
+       PINGRP_ULPI_DATA7,
+       PINGRP_ULPI_CLK,
+       PINGRP_ULPI_DIR,
+       PINGRP_ULPI_NXT,
+       PINGRP_ULPI_STP,
+       PINGRP_DAP3_FS,
+       PINGRP_DAP3_DIN,
+       PINGRP_DAP3_DOUT,
+       PINGRP_DAP3_SCLK,
+       PINGRP_GPIO_PV0,
+       PINGRP_GPIO_PV1,
+       PINGRP_SDMMC1_CLK,
+       PINGRP_SDMMC1_CMD,
+       PINGRP_SDMMC1_DAT3,
+       PINGRP_SDMMC1_DAT2,
+       PINGRP_SDMMC1_DAT1,
+       PINGRP_SDMMC1_DAT0,
+       PINGRP_GPIO_PV2,
+       PINGRP_GPIO_PV3,
+       PINGRP_CLK2_OUT,
+       PINGRP_CLK2_REQ,
+       PINGRP_LCD_PWR1,
+       PINGRP_LCD_PWR2,
+       PINGRP_LCD_SDIN,
+       PINGRP_LCD_SDOUT,
+       PINGRP_LCD_WR_N,
+       PINGRP_LCD_CS0_N,
+       PINGRP_LCD_DC0,
+       PINGRP_LCD_SCK,
+       PINGRP_LCD_PWR0,
+       PINGRP_LCD_PCLK,
+       PINGRP_LCD_DE,
+       PINGRP_LCD_HSYNC,
+       PINGRP_LCD_VSYNC,
+       PINGRP_LCD_D0,
+       PINGRP_LCD_D1,
+       PINGRP_LCD_D2,
+       PINGRP_LCD_D3,
+       PINGRP_LCD_D4,
+       PINGRP_LCD_D5,
+       PINGRP_LCD_D6,
+       PINGRP_LCD_D7,
+       PINGRP_LCD_D8,
+       PINGRP_LCD_D9,
+       PINGRP_LCD_D10,
+       PINGRP_LCD_D11,
+       PINGRP_LCD_D12,
+       PINGRP_LCD_D13,
+       PINGRP_LCD_D14,
+       PINGRP_LCD_D15,
+       PINGRP_LCD_D16,
+       PINGRP_LCD_D17,
+       PINGRP_LCD_D18,
+       PINGRP_LCD_D19,
+       PINGRP_LCD_D20,
+       PINGRP_LCD_D21,
+       PINGRP_LCD_D22,
+       PINGRP_LCD_D23,
+       PINGRP_LCD_CS1_N,
+       PINGRP_LCD_M1,
+       PINGRP_LCD_DC1,
+       PINGRP_HDMI_INT,
+       PINGRP_DDC_SCL,
+       PINGRP_DDC_SDA,
+       PINGRP_CRT_HSYNC,
+       PINGRP_CRT_VSYNC,
+       PINGRP_VI_D0,
+       PINGRP_VI_D1,
+       PINGRP_VI_D2,
+       PINGRP_VI_D3,
+       PINGRP_VI_D4,
+       PINGRP_VI_D5,
+       PINGRP_VI_D6,
+       PINGRP_VI_D7,
+       PINGRP_VI_D8,
+       PINGRP_VI_D9,
+       PINGRP_VI_D10,
+       PINGRP_VI_D11,
+       PINGRP_VI_PCLK,
+       PINGRP_VI_MCLK,
+       PINGRP_VI_VSYNC,
+       PINGRP_VI_HSYNC,
+       PINGRP_UART2_RXD,
+       PINGRP_UART2_TXD,
+       PINGRP_UART2_RTS_N,
+       PINGRP_UART2_CTS_N,
+       PINGRP_UART3_TXD,
+       PINGRP_UART3_RXD,
+       PINGRP_UART3_CTS_N,
+       PINGRP_UART3_RTS_N,
+       PINGRP_GPIO_PU0,
+       PINGRP_GPIO_PU1,
+       PINGRP_GPIO_PU2,
+       PINGRP_GPIO_PU3,
+       PINGRP_GPIO_PU4,
+       PINGRP_GPIO_PU5,
+       PINGRP_GPIO_PU6,
+       PINGRP_GEN1_I2C_SDA,
+       PINGRP_GEN1_I2C_SCL,
+       PINGRP_DAP4_FS,
+       PINGRP_DAP4_DIN,
+       PINGRP_DAP4_DOUT,
+       PINGRP_DAP4_SCLK,
+       PINGRP_CLK3_OUT,
+       PINGRP_CLK3_REQ,
+       PINGRP_GMI_WP_N,
+       PINGRP_GMI_IORDY,
+       PINGRP_GMI_WAIT,
+       PINGRP_GMI_ADV_N,
+       PINGRP_GMI_CLK,
+       PINGRP_GMI_CS0_N,
+       PINGRP_GMI_CS1_N,
+       PINGRP_GMI_CS2_N,
+       PINGRP_GMI_CS3_N,
+       PINGRP_GMI_CS4_N,
+       PINGRP_GMI_CS6_N,
+       PINGRP_GMI_CS7_N,
+       PINGRP_GMI_AD0,
+       PINGRP_GMI_AD1,
+       PINGRP_GMI_AD2,
+       PINGRP_GMI_AD3,
+       PINGRP_GMI_AD4,
+       PINGRP_GMI_AD5,
+       PINGRP_GMI_AD6,
+       PINGRP_GMI_AD7,
+       PINGRP_GMI_AD8,
+       PINGRP_GMI_AD9,
+       PINGRP_GMI_AD10,
+       PINGRP_GMI_AD11,
+       PINGRP_GMI_AD12,
+       PINGRP_GMI_AD13,
+       PINGRP_GMI_AD14,
+       PINGRP_GMI_AD15,
+       PINGRP_GMI_A16,
+       PINGRP_GMI_A17,
+       PINGRP_GMI_A18,
+       PINGRP_GMI_A19,
+       PINGRP_GMI_WR_N,
+       PINGRP_GMI_OE_N,
+       PINGRP_GMI_DQS,
+       PINGRP_GMI_RST_N,
+       PINGRP_GEN2_I2C_SCL,
+       PINGRP_GEN2_I2C_SDA,
+       PINGRP_SDMMC4_CLK,
+       PINGRP_SDMMC4_CMD,
+       PINGRP_SDMMC4_DAT0,
+       PINGRP_SDMMC4_DAT1,
+       PINGRP_SDMMC4_DAT2,
+       PINGRP_SDMMC4_DAT3,
+       PINGRP_SDMMC4_DAT4,
+       PINGRP_SDMMC4_DAT5,
+       PINGRP_SDMMC4_DAT6,
+       PINGRP_SDMMC4_DAT7,
+       PINGRP_SDMMC4_RST_N,
+       PINGRP_CAM_MCLK,
+       PINGRP_GPIO_PCC1,
+       PINGRP_GPIO_PBB0,
+       PINGRP_CAM_I2C_SCL,
+       PINGRP_CAM_I2C_SDA,
+       PINGRP_GPIO_PBB3,
+       PINGRP_GPIO_PBB4,
+       PINGRP_GPIO_PBB5,
+       PINGRP_GPIO_PBB6,
+       PINGRP_GPIO_PBB7,
+       PINGRP_GPIO_PCC2,
+       PINGRP_JTAG_RTCK,
+       PINGRP_PWR_I2C_SCL,
+       PINGRP_PWR_I2C_SDA,
+       PINGRP_KB_ROW0,
+       PINGRP_KB_ROW1,
+       PINGRP_KB_ROW2,
+       PINGRP_KB_ROW3,
+       PINGRP_KB_ROW4,
+       PINGRP_KB_ROW5,
+       PINGRP_KB_ROW6,
+       PINGRP_KB_ROW7,
+       PINGRP_KB_ROW8,
+       PINGRP_KB_ROW9,
+       PINGRP_KB_ROW10,
+       PINGRP_KB_ROW11,
+       PINGRP_KB_ROW12,
+       PINGRP_KB_ROW13,
+       PINGRP_KB_ROW14,
+       PINGRP_KB_ROW15,
+       PINGRP_KB_COL0,
+       PINGRP_KB_COL1,
+       PINGRP_KB_COL2,
+       PINGRP_KB_COL3,
+       PINGRP_KB_COL4,
+       PINGRP_KB_COL5,
+       PINGRP_KB_COL6,
+       PINGRP_KB_COL7,
+       PINGRP_CLK_32K_OUT,
+       PINGRP_SYS_CLK_REQ,
+       PINGRP_CORE_PWR_REQ,
+       PINGRP_CPU_PWR_REQ,
+       PINGRP_PWR_INT_N,
+       PINGRP_CLK_32K_IN,
+       PINGRP_OWR,
+       PINGRP_DAP1_FS,
+       PINGRP_DAP1_DIN,
+       PINGRP_DAP1_DOUT,
+       PINGRP_DAP1_SCLK,
+       PINGRP_CLK1_REQ,
+       PINGRP_CLK1_OUT,
+       PINGRP_SPDIF_IN,
+       PINGRP_SPDIF_OUT,
+       PINGRP_DAP2_FS,
+       PINGRP_DAP2_DIN,
+       PINGRP_DAP2_DOUT,
+       PINGRP_DAP2_SCLK,
+       PINGRP_SPI2_MOSI,
+       PINGRP_SPI2_MISO,
+       PINGRP_SPI2_CS0_N,
+       PINGRP_SPI2_SCK,
+       PINGRP_SPI1_MOSI,
+       PINGRP_SPI1_SCK,
+       PINGRP_SPI1_CS0_N,
+       PINGRP_SPI1_MISO,
+       PINGRP_SPI2_CS1_N,
+       PINGRP_SPI2_CS2_N,
+       PINGRP_SDMMC3_CLK,
+       PINGRP_SDMMC3_CMD,
+       PINGRP_SDMMC3_DAT0,
+       PINGRP_SDMMC3_DAT1,
+       PINGRP_SDMMC3_DAT2,
+       PINGRP_SDMMC3_DAT3,
+       PINGRP_SDMMC3_DAT4,
+       PINGRP_SDMMC3_DAT5,
+       PINGRP_SDMMC3_DAT6,
+       PINGRP_SDMMC3_DAT7,
+       PINGRP_PEX_L0_PRSNT_N,
+       PINGRP_PEX_L0_RST_N,
+       PINGRP_PEX_L0_CLKREQ_N,
+       PINGRP_PEX_WAKE_N,
+       PINGRP_PEX_L1_PRSNT_N,
+       PINGRP_PEX_L1_RST_N,
+       PINGRP_PEX_L1_CLKREQ_N,
+       PINGRP_PEX_L2_PRSNT_N,
+       PINGRP_PEX_L2_RST_N,
+       PINGRP_PEX_L2_CLKREQ_N,
+       PINGRP_HDMI_CEC,        /* offset 0x33e0 */
+       PINGRP_SDMMC1_WP_N,
+       PINGRP_SDMMC3_CD_N,
+       PINGRP_SPI1_CS1_N,
+       PINGRP_SPI1_CS2_N,
+       PINGRP_USB_VBUS_EN0,    /* offset 0x33f4 */
+       PINGRP_USB_VBUS_EN1,
+       PINGRP_SDMMC3_CLK_LB_IN,
+       PINGRP_SDMMC3_CLK_LB_OUT,
+       PINGRP_NAND_GMI_CLK_LB,
+       PINGRP_RESET_OUT_N,
+       PINGRP_COUNT,
+};
+
+enum pdrive_pingrp {
+       PDRIVE_PINGROUP_AO1 = 0, /* offset 0x868 */
+       PDRIVE_PINGROUP_AO2,
+       PDRIVE_PINGROUP_AT1,
+       PDRIVE_PINGROUP_AT2,
+       PDRIVE_PINGROUP_AT3,
+       PDRIVE_PINGROUP_AT4,
+       PDRIVE_PINGROUP_AT5,
+       PDRIVE_PINGROUP_CDEV1,
+       PDRIVE_PINGROUP_CDEV2,
+       PDRIVE_PINGROUP_CSUS,
+       PDRIVE_PINGROUP_DAP1,
+       PDRIVE_PINGROUP_DAP2,
+       PDRIVE_PINGROUP_DAP3,
+       PDRIVE_PINGROUP_DAP4,
+       PDRIVE_PINGROUP_DBG,
+       PDRIVE_PINGROUP_LCD1,
+       PDRIVE_PINGROUP_LCD2,
+       PDRIVE_PINGROUP_SDIO2,
+       PDRIVE_PINGROUP_SDIO3,
+       PDRIVE_PINGROUP_SPI,
+       PDRIVE_PINGROUP_UAA,
+       PDRIVE_PINGROUP_UAB,
+       PDRIVE_PINGROUP_UART2,
+       PDRIVE_PINGROUP_UART3,
+       PDRIVE_PINGROUP_VI1 = 24,       /* offset 0x8c8 */
+       PDRIVE_PINGROUP_SDIO1 = 33,     /* offset 0x8ec */
+       PDRIVE_PINGROUP_CRT = 36,       /* offset 0x8f8 */
+       PDRIVE_PINGROUP_DDC,
+       PDRIVE_PINGROUP_GMA,
+       PDRIVE_PINGROUP_GMB,
+       PDRIVE_PINGROUP_GMC,
+       PDRIVE_PINGROUP_GMD,
+       PDRIVE_PINGROUP_GME,
+       PDRIVE_PINGROUP_GMF,
+       PDRIVE_PINGROUP_GMG,
+       PDRIVE_PINGROUP_GMH,
+       PDRIVE_PINGROUP_OWR,
+       PDRIVE_PINGROUP_UAD,
+       PDRIVE_PINGROUP_GPV,
+       PDRIVE_PINGROUP_DEV3 = 49,      /* offset 0x92c */
+       PDRIVE_PINGROUP_CEC = 52,       /* offset 0x938 */
+       PDRIVE_PINGROUP_AT6,
+       PDRIVE_PINGROUP_DAP5,
+       PDRIVE_PINGROUP_VBUS,
+       PDRIVE_PINGROUP_COUNT,
+};
+
+/*
+ * Functions which can be assigned to each of the pin groups. The values here
+ * bear no relation to the values programmed into pinmux registers and are
+ * purely a convenience. The translation is done through a table search.
+ */
+enum pmux_func {
+       PMUX_FUNC_AHB_CLK,
+       PMUX_FUNC_APB_CLK,
+       PMUX_FUNC_AUDIO_SYNC,
+       PMUX_FUNC_CRT,
+       PMUX_FUNC_DAP1,
+       PMUX_FUNC_DAP2,
+       PMUX_FUNC_DAP3,
+       PMUX_FUNC_DAP4,
+       PMUX_FUNC_DAP5,
+       PMUX_FUNC_DISPA,
+       PMUX_FUNC_DISPB,
+       PMUX_FUNC_EMC_TEST0_DLL,
+       PMUX_FUNC_EMC_TEST1_DLL,
+       PMUX_FUNC_GMI,
+       PMUX_FUNC_GMI_INT,
+       PMUX_FUNC_HDMI,
+       PMUX_FUNC_I2C1,
+       PMUX_FUNC_I2C2,
+       PMUX_FUNC_I2C3,
+       PMUX_FUNC_IDE,
+       PMUX_FUNC_KBC,
+       PMUX_FUNC_MIO,
+       PMUX_FUNC_MIPI_HS,
+       PMUX_FUNC_NAND,
+       PMUX_FUNC_OSC,
+       PMUX_FUNC_OWR,
+       PMUX_FUNC_PCIE,
+       PMUX_FUNC_PLLA_OUT,
+       PMUX_FUNC_PLLC_OUT1,
+       PMUX_FUNC_PLLM_OUT1,
+       PMUX_FUNC_PLLP_OUT2,
+       PMUX_FUNC_PLLP_OUT3,
+       PMUX_FUNC_PLLP_OUT4,
+       PMUX_FUNC_PWM,
+       PMUX_FUNC_PWR_INTR,
+       PMUX_FUNC_PWR_ON,
+       PMUX_FUNC_RTCK,
+       PMUX_FUNC_SDMMC1,
+       PMUX_FUNC_SDMMC2,
+       PMUX_FUNC_SDMMC3,
+       PMUX_FUNC_SDMMC4,
+       PMUX_FUNC_SFLASH,
+       PMUX_FUNC_SPDIF,
+       PMUX_FUNC_SPI1,
+       PMUX_FUNC_SPI2,
+       PMUX_FUNC_SPI2_ALT,
+       PMUX_FUNC_SPI3,
+       PMUX_FUNC_SPI4,
+       PMUX_FUNC_TRACE,
+       PMUX_FUNC_TWC,
+       PMUX_FUNC_UARTA,
+       PMUX_FUNC_UARTB,
+       PMUX_FUNC_UARTC,
+       PMUX_FUNC_UARTD,
+       PMUX_FUNC_UARTE,
+       PMUX_FUNC_ULPI,
+       PMUX_FUNC_VI,
+       PMUX_FUNC_VI_SENSOR_CLK,
+       PMUX_FUNC_XIO,
+       PMUX_FUNC_BLINK,
+       PMUX_FUNC_CEC,
+       PMUX_FUNC_CLK12,
+       PMUX_FUNC_DAP,
+       PMUX_FUNC_DAPSDMMC2,
+       PMUX_FUNC_DDR,
+       PMUX_FUNC_DEV3,
+       PMUX_FUNC_DTV,
+       PMUX_FUNC_VI_ALT1,
+       PMUX_FUNC_VI_ALT2,
+       PMUX_FUNC_VI_ALT3,
+       PMUX_FUNC_EMC_DLL,
+       PMUX_FUNC_EXTPERIPH1,
+       PMUX_FUNC_EXTPERIPH2,
+       PMUX_FUNC_EXTPERIPH3,
+       PMUX_FUNC_GMI_ALT,
+       PMUX_FUNC_HDA,
+       PMUX_FUNC_HSI,
+       PMUX_FUNC_I2C4,
+       PMUX_FUNC_I2C5,
+       PMUX_FUNC_I2CPWR,
+       PMUX_FUNC_I2S0,
+       PMUX_FUNC_I2S1,
+       PMUX_FUNC_I2S2,
+       PMUX_FUNC_I2S3,
+       PMUX_FUNC_I2S4,
+       PMUX_FUNC_NAND_ALT,
+       PMUX_FUNC_POPSDIO4,
+       PMUX_FUNC_POPSDMMC4,
+       PMUX_FUNC_PWM0,
+       PMUX_FUNC_PWM1,
+       PMUX_FUNC_PWM2,
+       PMUX_FUNC_PWM3,
+       PMUX_FUNC_SATA,
+       PMUX_FUNC_SPI5,
+       PMUX_FUNC_SPI6,
+       PMUX_FUNC_SYSCLK,
+       PMUX_FUNC_VGP1,
+       PMUX_FUNC_VGP2,
+       PMUX_FUNC_VGP3,
+       PMUX_FUNC_VGP4,
+       PMUX_FUNC_VGP5,
+       PMUX_FUNC_VGP6,
+
+       PMUX_FUNC_USB,
+       PMUX_FUNC_SOC,
+       PMUX_FUNC_CPU,
+       PMUX_FUNC_CLK,
+       PMUX_FUNC_PWRON,
+       PMUX_FUNC_PMI,
+       PMUX_FUNC_CLDVFS,
+       PMUX_FUNC_RESET_OUT_N,
+
+       PMUX_FUNC_SAFE,
+       PMUX_FUNC_MAX,
+
+       PMUX_FUNC_RSVD1 = 0x8000,
+       PMUX_FUNC_RSVD2 = 0x8001,
+       PMUX_FUNC_RSVD3 = 0x8002,
+       PMUX_FUNC_RSVD4 = 0x8003,
+};
+
+/* return 1 if a pmux_func is in range */
+#define pmux_func_isvalid(func) ((((func) >= 0) && ((func) < PMUX_FUNC_MAX)) \
+       || (((func) >= PMUX_FUNC_RSVD1) && ((func) <= PMUX_FUNC_RSVD4)))
+
+/* return 1 if a pingrp is in range */
+#define pmux_pingrp_isvalid(pin) (((pin) >= 0) && ((pin) < PINGRP_COUNT))
+
+/* The pullup/pulldown state of a pin group */
+enum pmux_pull {
+       PMUX_PULL_NORMAL = 0,
+       PMUX_PULL_DOWN,
+       PMUX_PULL_UP,
+};
+/* return 1 if a pin_pupd_is in range */
+#define pmux_pin_pupd_isvalid(pupd) (((pupd) >= PMUX_PULL_NORMAL) && \
+                               ((pupd) <= PMUX_PULL_UP))
+
+/* Defines whether a pin group is tristated or in normal operation */
+enum pmux_tristate {
+       PMUX_TRI_NORMAL = 0,
+       PMUX_TRI_TRISTATE = 1,
+};
+/* return 1 if a pin_tristate_is in range */
+#define pmux_pin_tristate_isvalid(tristate) (((tristate) >= PMUX_TRI_NORMAL) \
+                               && ((tristate) <= PMUX_TRI_TRISTATE))
+
+enum pmux_pin_io {
+       PMUX_PIN_OUTPUT = 0,
+       PMUX_PIN_INPUT = 1,
+};
+/* return 1 if a pin_io_is in range */
+#define pmux_pin_io_isvalid(io) (((io) >= PMUX_PIN_OUTPUT) && \
+                               ((io) <= PMUX_PIN_INPUT))
+
+enum pmux_pin_lock {
+       PMUX_PIN_LOCK_DEFAULT = 0,
+       PMUX_PIN_LOCK_DISABLE,
+       PMUX_PIN_LOCK_ENABLE,
+};
+/* return 1 if a pin_lock is in range */
+#define pmux_pin_lock_isvalid(lock) (((lock) >= PMUX_PIN_LOCK_DEFAULT) && \
+                               ((lock) <= PMUX_PIN_LOCK_ENABLE))
+
+enum pmux_pin_od {
+       PMUX_PIN_OD_DEFAULT = 0,
+       PMUX_PIN_OD_DISABLE,
+       PMUX_PIN_OD_ENABLE,
+};
+/* return 1 if a pin_od is in range */
+#define pmux_pin_od_isvalid(od) (((od) >= PMUX_PIN_OD_DEFAULT) && \
+                               ((od) <= PMUX_PIN_OD_ENABLE))
+
+enum pmux_pin_ioreset {
+       PMUX_PIN_IO_RESET_DEFAULT = 0,
+       PMUX_PIN_IO_RESET_DISABLE,
+       PMUX_PIN_IO_RESET_ENABLE,
+};
+/* return 1 if a pin_ioreset_is in range */
+#define pmux_pin_ioreset_isvalid(ioreset) \
+                               (((ioreset) >= PMUX_PIN_IO_RESET_DEFAULT) && \
+                               ((ioreset) <= PMUX_PIN_IO_RESET_ENABLE))
+
+/* Available power domains used by pin groups */
+enum pmux_vddio {
+       PMUX_VDDIO_BB = 0,
+       PMUX_VDDIO_LCD,
+       PMUX_VDDIO_VI,
+       PMUX_VDDIO_UART,
+       PMUX_VDDIO_DDR,
+       PMUX_VDDIO_NAND,
+       PMUX_VDDIO_SYS,
+       PMUX_VDDIO_AUDIO,
+       PMUX_VDDIO_SD,
+       PMUX_VDDIO_CAM,
+       PMUX_VDDIO_GMI,
+       PMUX_VDDIO_PEXCTL,
+       PMUX_VDDIO_SDMMC1,
+       PMUX_VDDIO_SDMMC3,
+       PMUX_VDDIO_SDMMC4,
+
+       PMUX_VDDIO_NONE
+};
+
+/* T114 pin drive group and pin mux registers */
+#define PDRIVE_PINGROUP_OFFSET  (0x868 >> 2)
+#define PMUX_OFFSET     ((0x3000 >> 2) - PDRIVE_PINGROUP_OFFSET - \
+                       PDRIVE_PINGROUP_COUNT)
+struct pmux_tri_ctlr {
+       uint pmt_reserved0;             /* ABP_MISC_PP_ reserved offset 00 */
+       uint pmt_reserved1;             /* ABP_MISC_PP_ reserved offset 04 */
+       uint pmt_strap_opt_a;           /* _STRAPPING_OPT_A_0, offset 08   */
+       uint pmt_reserved2;             /* ABP_MISC_PP_ reserved offset 0C */
+       uint pmt_reserved3;             /* ABP_MISC_PP_ reserved offset 10 */
+       uint pmt_reserved4[4];          /* _TRI_STATE_REG_A/B/C/D in t20 */
+       uint pmt_cfg_ctl;               /* _CONFIG_CTL_0, offset 24        */
+
+       uint pmt_reserved[528];         /* ABP_MISC_PP_ reserved offs 28-864 */
+
+       uint pmt_drive[PDRIVE_PINGROUP_COUNT];  /* pin drive grps offs 868 */
+       uint pmt_reserved5[PMUX_OFFSET];
+       uint pmt_ctl[PINGRP_COUNT];     /* mux/pupd/tri regs, offset 0x3000 */
+};
+
+/*
+ * This defines the configuration for a pin, including the function assigned,
+ * pull up/down settings and tristate settings. Having set up one of these
+ * you can call pinmux_config_pingroup() to configure a pin in one step. Also
+ * available is pinmux_config_table() to configure a list of pins.
+ */
+struct pingroup_config {
+       enum pmux_pingrp pingroup;      /* pin group PINGRP_...             */
+       enum pmux_func func;            /* function to assign FUNC_...      */
+       enum pmux_pull pull;            /* pull up/down/normal PMUX_PULL_...*/
+       enum pmux_tristate tristate;    /* tristate or normal PMUX_TRI_...  */
+       enum pmux_pin_io io;            /* input or output PMUX_PIN_...  */
+       enum pmux_pin_lock lock;        /* lock enable/disable PMUX_PIN...  */
+       enum pmux_pin_od od;            /* open-drain or push-pull driver  */
+       enum pmux_pin_ioreset ioreset;  /* input/output reset PMUX_PIN...  */
+};
+
+/* Set a pin group to tristate */
+void pinmux_tristate_enable(enum pmux_pingrp pin);
+
+/* Set a pin group to normal (non tristate) */
+void pinmux_tristate_disable(enum pmux_pingrp pin);
+
+/* Set the pull up/down feature for a pin group */
+void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd);
+
+/* Set the mux function for a pin group */
+void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func);
+
+/* Set the complete configuration for a pin group */
+void pinmux_config_pingroup(struct pingroup_config *config);
+
+/* Set a pin group to tristate or normal */
+void pinmux_set_tristate(enum pmux_pingrp pin, int enable);
+
+/* Set a pin group as input or output */
+void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io);
+
+/**
+ * Configure a list of pin groups
+ *
+ * @param config       List of config items
+ * @param len          Number of config items in list
+ */
+void pinmux_config_table(struct pingroup_config *config, int len);
+
+/* Set a group of pins from a table */
+void pinmux_init(void);
+
+#endif  /* _TEGRA114_PINMUX_H_ */
diff --git a/arch/arm/include/asm/arch-tegra114/pmu.h b/arch/arm/include/asm/arch-tegra114/pmu.h
new file mode 100644 (file)
index 0000000..c6e2381
--- /dev/null
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _TEGRA114_PMU_H_
+#define _TEGRA114_PMU_H_
+
+/* Set core and CPU voltages to nominal levels */
+int pmu_set_nominal(void);
+
+#endif /* _TEGRA114_PMU_H_ */
diff --git a/arch/arm/include/asm/arch-tegra114/spl.h b/arch/arm/include/asm/arch-tegra114/spl.h
new file mode 100644 (file)
index 0000000..ebb16fe
--- /dev/null
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef        _ASM_ARCH_SPL_H_
+#define        _ASM_ARCH_SPL_H_
+
+#define BOOT_DEVICE_RAM         1
+
+#endif
diff --git a/arch/arm/include/asm/arch-tegra114/tegra.h b/arch/arm/include/asm/arch-tegra114/tegra.h
new file mode 100644 (file)
index 0000000..a3d12d6
--- /dev/null
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _TEGRA114_H_
+#define _TEGRA114_H_
+
+#define NV_PA_SDRAM_BASE       0x80000000      /* 0x80000000 for real T114 */
+
+#include <asm/arch-tegra/tegra.h>
+
+#define BCT_ODMDATA_OFFSET     1752    /* offset to ODMDATA word */
+
+#undef NVBOOTINFOTABLE_BCTSIZE
+#undef NVBOOTINFOTABLE_BCTPTR
+#define NVBOOTINFOTABLE_BCTSIZE        0x48    /* BCT size in BIT in IRAM */
+#define NVBOOTINFOTABLE_BCTPTR 0x4C    /* BCT pointer in BIT in IRAM */
+
+#define MAX_NUM_CPU            4
+
+#endif /* TEGRA114_H */