ARM: display5: Remove common.c file (after DM/DTS U-Boot proper conversion)
authorLukasz Majewski <lukma@denx.de>
Tue, 3 Sep 2019 14:38:46 +0000 (16:38 +0200)
committerStefano Babic <sbabic@denx.de>
Tue, 8 Oct 2019 14:35:59 +0000 (16:35 +0200)
The common.c file content can be safely moved to spl.c file after
performing the DM/DTS conversion for the U-Boot proper.

It contains the non DM/DTS setup code, which now is only used by SPL.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
board/liebherr/display5/Makefile
board/liebherr/display5/common.c [deleted file]
board/liebherr/display5/common.h
board/liebherr/display5/spl.c

index f934672428ab1e72012afaa2e53cb596c041f892..ee503add75d3a9dfc87a32097332518d4d480ee1 100644 (file)
@@ -5,7 +5,7 @@
 # SPDX-License-Identifier:    GPL-2.0+
 #
 ifdef CONFIG_SPL_BUILD
-obj-y = common.o spl.o
+obj-y = spl.o
 else
-obj-y := common.o display5.o
+obj-y := display5.o
 endif
diff --git a/board/liebherr/display5/common.c b/board/liebherr/display5/common.c
deleted file mode 100644 (file)
index 5e71407..0000000
+++ /dev/null
@@ -1,83 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2017 DENX Software Engineering
- * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
- */
-
-#include <asm/mach-imx/iomux-v3.h>
-#include <asm/arch/mx6-pins.h>
-#include "common.h"
-
-iomux_v3_cfg_t const uart_console_pads[] = {
-       /* UART5 */
-       MX6_PAD_CSI0_DAT14__UART5_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
-       MX6_PAD_CSI0_DAT15__UART5_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
-       MX6_PAD_CSI0_DAT18__UART5_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
-       MX6_PAD_CSI0_DAT19__UART5_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
-void displ5_set_iomux_uart_spl(void)
-{
-       SETUP_IOMUX_PADS(uart_console_pads);
-}
-
-iomux_v3_cfg_t const misc_pads_spl[] = {
-       /* Emergency recovery pin */
-       MX6_PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-void displ5_set_iomux_misc_spl(void)
-{
-       SETUP_IOMUX_PADS(misc_pads_spl);
-}
-
-#ifdef CONFIG_MXC_SPI
-iomux_v3_cfg_t const ecspi2_pads[] = {
-       /* SPI2, NOR Flash nWP, CS0 */
-       MX6_PAD_CSI0_DAT10__ECSPI2_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
-       MX6_PAD_CSI0_DAT9__ECSPI2_MOSI  | MUX_PAD_CTRL(SPI_PAD_CTRL),
-       MX6_PAD_CSI0_DAT8__ECSPI2_SCLK  | MUX_PAD_CTRL(SPI_PAD_CTRL),
-       MX6_PAD_CSI0_DAT11__GPIO5_IO29  | MUX_PAD_CTRL(NO_PAD_CTRL),
-       MX6_PAD_SD3_DAT5__GPIO7_IO00    | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-int board_spi_cs_gpio(unsigned int bus, unsigned int cs)
-{
-       if (bus != 1 || cs != 0)
-               return -EINVAL;
-
-       return IMX_GPIO_NR(5, 29);
-}
-
-void displ5_set_iomux_ecspi_spl(void)
-{
-       SETUP_IOMUX_PADS(ecspi2_pads);
-}
-
-#else
-void displ5_set_iomux_ecspi_spl(void) {}
-#endif
-
-#ifdef CONFIG_FSL_ESDHC_IMX
-iomux_v3_cfg_t const usdhc4_pads[] = {
-       MX6_PAD_SD4_CLK__SD4_CLK        | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-       MX6_PAD_SD4_CMD__SD4_CMD        | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-       MX6_PAD_SD4_DAT0__SD4_DATA0     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-       MX6_PAD_SD4_DAT1__SD4_DATA1     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-       MX6_PAD_SD4_DAT2__SD4_DATA2     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-       MX6_PAD_SD4_DAT3__SD4_DATA3     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-       MX6_PAD_SD4_DAT4__SD4_DATA4     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-       MX6_PAD_SD4_DAT5__SD4_DATA5     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-       MX6_PAD_SD4_DAT6__SD4_DATA6     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-       MX6_PAD_SD4_DAT7__SD4_DATA7     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-       MX6_PAD_NANDF_ALE__SD4_RESET    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-};
-
-void displ5_set_iomux_usdhc_spl(void)
-{
-       SETUP_IOMUX_PADS(usdhc4_pads);
-}
-
-#else
-void displ5_set_iomux_usdhc_spl(void) {}
-#endif
index 4eb70dc42fb69614561123c070a21eb8529561af..44c7470074ce6c7bd3b540508ec47c2444c91b0d 100644 (file)
@@ -31,9 +31,4 @@
 #define ENET_PAD_CTRL_CLK  ((PAD_CTL_PUS_100K_UP & ~PAD_CTL_PKE) | \
        PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
 
-void displ5_set_iomux_uart_spl(void);
-void displ5_set_iomux_ecspi_spl(void);
-void displ5_set_iomux_usdhc_spl(void);
-void displ5_set_iomux_misc_spl(void);
-
 #endif /* __DISPL5_COMMON_H_ */
index 354b63e431f687d862b646bbf44fdb5e79559d36..311edaf939cc691f17cc9627fc16e0e5606f6943 100644 (file)
@@ -104,6 +104,80 @@ static const struct mx6_ddr3_cfg mt41k128m16jt_125 = {
        .trasmin = 3500,
 };
 
+iomux_v3_cfg_t const uart_console_pads[] = {
+       /* UART5 */
+       MX6_PAD_CSI0_DAT14__UART5_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+       MX6_PAD_CSI0_DAT15__UART5_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+       MX6_PAD_CSI0_DAT18__UART5_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
+       MX6_PAD_CSI0_DAT19__UART5_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+void displ5_set_iomux_uart_spl(void)
+{
+       SETUP_IOMUX_PADS(uart_console_pads);
+}
+
+iomux_v3_cfg_t const misc_pads_spl[] = {
+       /* Emergency recovery pin */
+       MX6_PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+void displ5_set_iomux_misc_spl(void)
+{
+       SETUP_IOMUX_PADS(misc_pads_spl);
+}
+
+#ifdef CONFIG_MXC_SPI
+iomux_v3_cfg_t const ecspi2_pads[] = {
+       /* SPI2, NOR Flash nWP, CS0 */
+       MX6_PAD_CSI0_DAT10__ECSPI2_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
+       MX6_PAD_CSI0_DAT9__ECSPI2_MOSI  | MUX_PAD_CTRL(SPI_PAD_CTRL),
+       MX6_PAD_CSI0_DAT8__ECSPI2_SCLK  | MUX_PAD_CTRL(SPI_PAD_CTRL),
+       MX6_PAD_CSI0_DAT11__GPIO5_IO29  | MUX_PAD_CTRL(NO_PAD_CTRL),
+       MX6_PAD_SD3_DAT5__GPIO7_IO00    | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+int board_spi_cs_gpio(unsigned int bus, unsigned int cs)
+{
+       if (bus != 1 || cs != 0)
+               return -EINVAL;
+
+       return IMX_GPIO_NR(5, 29);
+}
+
+void displ5_set_iomux_ecspi_spl(void)
+{
+       SETUP_IOMUX_PADS(ecspi2_pads);
+}
+
+#else
+void displ5_set_iomux_ecspi_spl(void) {}
+#endif
+
+#ifdef CONFIG_FSL_ESDHC_IMX
+iomux_v3_cfg_t const usdhc4_pads[] = {
+       MX6_PAD_SD4_CLK__SD4_CLK        | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6_PAD_SD4_CMD__SD4_CMD        | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6_PAD_SD4_DAT0__SD4_DATA0     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6_PAD_SD4_DAT1__SD4_DATA1     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6_PAD_SD4_DAT2__SD4_DATA2     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6_PAD_SD4_DAT3__SD4_DATA3     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6_PAD_SD4_DAT4__SD4_DATA4     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6_PAD_SD4_DAT5__SD4_DATA5     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6_PAD_SD4_DAT6__SD4_DATA6     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6_PAD_SD4_DAT7__SD4_DATA7     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6_PAD_NANDF_ALE__SD4_RESET    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+void displ5_set_iomux_usdhc_spl(void)
+{
+       SETUP_IOMUX_PADS(usdhc4_pads);
+}
+
+#else
+void displ5_set_iomux_usdhc_spl(void) {}
+#endif
+
 static void ccgr_init(void)
 {
        struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;