- BUILDMAN="arm11 arm7 arm920t arm946es"
- env:
- JOB="arm926ejs"
- BUILDMAN="arm926ejs -x mx,siemens,atmel"
+ BUILDMAN="arm926ejs -x mx,siemens,atmel,kirkwood"
- env:
- BUILDMAN="atmel"
- env:
- BUILDMAN="sandbox x86"
TOOLCHAIN="x86_64"
- env:
- - BUILDMAN="kirkwood"
+ - BUILDMAN="kirkwood -x openrd"
- env:
- BUILDMAN="mvebu"
- env:
config DISTRO_DEFAULTS
bool "Select defaults suitable for booting general purpose Linux distributions"
- imply USE_BOOTCOMMAND
- select CMD_BOOTZ if ARM && !ARM64
+ select AUTO_COMPLETE
+ select CMDLINE_EDITING
select CMD_BOOTI if ARM64
+ select CMD_BOOTZ if ARM && !ARM64
select CMD_DHCP if CMD_NET
- select CMD_PING if CMD_NET
- select CMD_PXE if NET
select CMD_ENV_EXISTS
select CMD_EXT2
select CMD_EXT4
select CMD_FAT
select CMD_FS_GENERIC
- imply CMD_MII if NET
select CMD_PART if PARTITIONS
+ select CMD_PING if CMD_NET
+ select CMD_PXE if NET
+ select ENV_VARS_UBOOT_CONFIG
select HUSH_PARSER
- select CMDLINE_EDITING
- select AUTO_COMPLETE
- select SYS_LONGHELP
select SUPPORT_RAW_INITRD
- select ENV_VARS_UBOOT_CONFIG
+ select SYS_LONGHELP
+ imply CMD_MII if NET
+ imply USE_BOOTCOMMAND
help
Select this to enable various options and commands which are suitable
for building u-boot for booting general purpose Linux distributions.
config FIT_ENABLE_SHA256_SUPPORT
bool "Support SHA256 checksum of FIT image contents"
- select SHA256
default y
+ select SHA256
help
Enable this to support SHA256 checksum of FIT image contents. A
SHA256 checksum is a 256-bit (32-byte) hash value used to check that
config FIT_SIGNATURE
bool "Enable signature verification of FIT uImages"
depends on DM
- select RSA
select HASH
+ select RSA
help
This option enables signature verification of FIT uImages,
using a hash signed and verified using RSA. If
F: include/efi*
F: include/pe.h
F: include/asm-generic/pe.h
+F: lib/charset.c
F: lib/efi*/
F: test/py/tests/test_efi*
F: cmd/bootefi.c
# SPDX-License-Identifier: GPL-2.0+
VERSION = 2018
-PATCHLEVEL = 07
+PATCHLEVEL = 09
SUBLEVEL =
-EXTRAVERSION =
+EXTRAVERSION = -rc1
NAME =
# *DOCUMENTATION*
u-boot.dis: u-boot
$(OBJDUMP) -d $< > $@
-ifdef CONFIG_TPL
-SPL_PAYLOAD := tpl/u-boot-with-tpl.bin
+ifneq ($(CONFIG_SPL_PAYLOAD),)
+SPL_PAYLOAD := $(CONFIG_SPL_PAYLOAD:"%"=%)
else
SPL_PAYLOAD := u-boot.bin
endif
config ARC
bool "ARC architecture"
- select HAVE_PRIVATE_LIBGCC
- select SUPPORT_OF_CONTROL
select ARCH_EARLY_INIT_R
+ select ARC_TIMER
select CLK
+ select HAVE_PRIVATE_LIBGCC
+ select SUPPORT_OF_CONTROL
select TIMER
- select ARC_TIMER
config ARM
bool "ARM architecture"
config NIOS2
bool "Nios II architecture"
- select SUPPORT_OF_CONTROL
- select OF_CONTROL
- select DM
select CPU
+ select DM
+ select OF_CONTROL
+ select SUPPORT_OF_CONTROL
+ imply CMD_DM
config PPC
bool "PowerPC architecture"
config SANDBOX
bool "Sandbox"
select BOARD_LATE_INIT
- select SUPPORT_OF_CONTROL
select DM
+ select DM_GPIO
+ select DM_I2C
select DM_KEYBOARD
- select DM_SPI_FLASH
+ select DM_MMC
select DM_SERIAL
- select DM_I2C
select DM_SPI
- select DM_GPIO
- select DM_MMC
+ select DM_SPI_FLASH
select HAVE_BLOCK_DEVICE
- select SPI
select LZO
+ select SPI
+ select SUPPORT_OF_CONTROL
+ imply CMD_DM
imply CMD_GETTIME
imply CMD_HASH
imply CMD_IO
imply CMD_IOTRACE
imply CMD_LZMADEC
+ imply CMD_SATA
+ imply CMD_SF_TEST
imply CRC32_VERIFY
imply FAT_WRITE
imply HASH_VERIFY
imply LZMA
imply SCSI
- imply CMD_SATA
- imply CMD_SF_TEST
config SH
bool "SuperH architecture"
config X86
bool "x86 architecture"
select CREATE_ARCH_SYMLINK
- select HAVE_PRIVATE_LIBGCC
- select USE_PRIVATE_LIBGCC
- select SUPPORT_OF_CONTROL
- select OF_CONTROL
select DM
select DM_PCI
+ select HAVE_PRIVATE_LIBGCC
+ select OF_CONTROL
select PCI
+ select SUPPORT_OF_CONTROL
select TIMER
+ select USE_PRIVATE_LIBGCC
select X86_TSC_TIMER
imply BLK
+ imply CMD_DM
+ imply CMD_FPGA_LOADMK
+ imply CMD_GETTIME
+ imply CMD_IO
+ imply CMD_IRQ
+ imply CMD_PCI
+ imply CMD_SF_TEST
+ imply CMD_ZBOOT
imply DM_ETH
imply DM_GPIO
imply DM_KEYBOARD
imply DM_MMC
imply DM_RTC
- imply DM_SERIAL
imply DM_SCSI
+ imply DM_SERIAL
imply DM_SPI
imply DM_SPI_FLASH
imply DM_USB
imply DM_VIDEO
imply SYSRESET
imply SYSRESET_X86
- imply CMD_FPGA_LOADMK
- imply CMD_GETTIME
- imply CMD_IO
- imply CMD_IRQ
- imply CMD_PCI
- imply CMD_SF_TEST
- imply CMD_ZBOOT
- imply USB_HOST_ETHER
imply USB_ETHER_ASIX
imply USB_ETHER_SMSC95XX
+ imply USB_HOST_ETHER
config XTENSA
bool "Xtensa architecture"
config CPU_ARC750D
bool "ARC 750D"
- select ARC_MMU_V2
depends on ISA_ARCOMPACT
+ select ARC_MMU_V2
help
Choose this option to build an U-Boot for ARC750D CPU.
config CPU_ARC770D
bool "ARC 770D"
- select ARC_MMU_V3
depends on ISA_ARCOMPACT
+ select ARC_MMU_V3
help
Choose this option to build an U-Boot for ARC770D CPU.
config CPU_ARCEM6
bool "ARC EM6"
- select ARC_MMU_ABSENT
depends on ISA_ARCV2
+ select ARC_MMU_ABSENT
help
Next Generation ARC Core based on ISA-v2 ISA without MMU.
config CPU_ARCHS36
bool "ARC HS36"
- select ARC_MMU_ABSENT
depends on ISA_ARCV2
+ select ARC_MMU_ABSENT
help
Next Generation ARC Core based on ISA-v2 ISA without MMU.
config CPU_ARCHS38
bool "ARC HS38"
- select ARC_MMU_V4
depends on ISA_ARCV2
+ select ARC_MMU_V4
help
Next Generation ARC Core based on ISA-v2 ISA with MMU.
bool
config ARM_ERRATA_845369
- bool
+ bool
config ARM_ERRATA_852421
bool
config CPU_V7A
bool
- select HAS_VBAR
select HAS_THUMB2
+ select HAS_VBAR
select SYS_CACHE_SHIFT_6
imply SYS_ARM_MMU
config CPU_V7M
bool
select HAS_THUMB2
- select THUMB2_KERNEL
- select SYS_CACHE_SHIFT_5
select SYS_ARM_MPU
+ select SYS_CACHE_SHIFT_5
select SYS_THUMB_BUILD
+ select THUMB2_KERNEL
config CPU_V7R
bool
select HAS_THUMB2
- select SYS_CACHE_SHIFT_6
- select SYS_ARM_MPU
select SYS_ARM_CACHE_CP15
+ select SYS_ARM_MPU
+ select SYS_CACHE_SHIFT_6
config CPU_PXA
bool
config KIRKWOOD
bool "Marvell Kirkwood"
- select CPU_ARM926EJS
- select BOARD_EARLY_INIT_F
select ARCH_MISC_INIT
+ select BOARD_EARLY_INIT_F
+ select CPU_ARM926EJS
config ARCH_MVEBU
bool "Marvell MVEBU family (Armada XP/375/38x/3700/7K/8K)"
- select OF_CONTROL
- select OF_SEPARATE
select DM
select DM_ETH
select DM_SERIAL
select DM_SPI
select DM_SPI_FLASH
+ select OF_CONTROL
+ select OF_SEPARATE
select SPI
+ imply CMD_DM
config TARGET_DEVKIT3250
bool "Support devkit3250"
config TARGET_SPEAR300
bool "Support spear300"
- select CPU_ARM926EJS
select BOARD_EARLY_INIT_F
- imply CMD_SAVES
+ select CPU_ARM926EJS
select PL011_SERIAL
+ imply CMD_SAVES
config TARGET_SPEAR310
bool "Support spear310"
- select CPU_ARM926EJS
select BOARD_EARLY_INIT_F
- imply CMD_SAVES
+ select CPU_ARM926EJS
select PL011_SERIAL
+ imply CMD_SAVES
config TARGET_SPEAR320
bool "Support spear320"
- select CPU_ARM926EJS
select BOARD_EARLY_INIT_F
- imply CMD_SAVES
+ select CPU_ARM926EJS
select PL011_SERIAL
+ imply CMD_SAVES
config TARGET_SPEAR600
bool "Support spear600"
- select CPU_ARM926EJS
select BOARD_EARLY_INIT_F
- imply CMD_SAVES
+ select CPU_ARM926EJS
select PL011_SERIAL
+ imply CMD_SAVES
config TARGET_STV0991
bool "Support stv0991"
select DM_SERIAL
select DM_SPI
select DM_SPI_FLASH
+ select PL01X_SERIAL
select SPI
select SPI_FLASH
- select PL01X_SERIAL
+ imply CMD_DM
config TARGET_X600
bool "Support x600"
select BOARD_LATE_INIT
select CPU_ARM926EJS
- select SUPPORT_SPL
select PL011_SERIAL
+ select SUPPORT_SPL
config TARGET_WOODBURN
bool "Support woodburn"
config ARCH_BCM283X
bool "Broadcom BCM283X family"
select DM
- select DM_SERIAL
select DM_GPIO
+ select DM_SERIAL
select OF_CONTROL
select PL01X_SERIAL
select SERIAL_SEARCH_ALL
+ imply CMD_DM
imply FAT_WRITE
config TARGET_VEXPRESS_CA15_TC2
select DM
select OF_CONTROL
select OF_PRIOR_STAGE
+ imply CMD_DM
help
This enables support for Broadcom ARM-based set-top box
chipsets, including the 7445 family of chips.
config TARGET_BCMCYGNUS
bool "Support bcmcygnus"
select CPU_V7A
- imply CRC32_VERIFY
+ imply BCM_SF2_ETH
+ imply BCM_SF2_ETH_GMAC
imply CMD_HASH
+ imply CRC32_VERIFY
imply FAT_WRITE
imply HASH_VERIFY
imply NETDEVICES
- imply BCM_SF2_ETH
- imply BCM_SF2_ETH_GMAC
config TARGET_BCMNSP
bool "Support bcmnsp"
config ARCH_EXYNOS
bool "Samsung EXYNOS"
select DM
+ select DM_GPIO
select DM_I2C
- select DM_SPI_FLASH
+ select DM_KEYBOARD
select DM_SERIAL
select DM_SPI
- select DM_GPIO
- select DM_KEYBOARD
+ select DM_SPI_FLASH
select SPI
+ imply CMD_DM
imply FAT_WRITE
config ARCH_S5PC1XX
bool "Samsung S5PC1XX"
select CPU_V7A
select DM
- select DM_SERIAL
select DM_GPIO
select DM_I2C
+ select DM_SERIAL
+ imply CMD_DM
config ARCH_HIGHBANK
bool "Calxeda Highbank"
select DM
select DM_SERIAL
select PL01X_SERIAL
+ imply CMD_DM
config ARCH_KEYSTONE
bool "TI Keystone"
+ select CMD_POWEROFF
select CPU_V7A
select SUPPORT_SPL
- select SYS_THUMB_BUILD
- select CMD_POWEROFF
select SYS_ARCH_TIMER
+ select SYS_THUMB_BUILD
imply CMD_MTDPARTS
- imply FIT
imply CMD_SAVES
+ imply FIT
config ARCH_OMAP2PLUS
bool "TI OMAP2+"
select ARM64
select DM
select SUPPORT_SPL
+ imply CMD_DM
config ARCH_MX23
bool "NXP i.MX23 family"
select CPU_ARM1136
config ARCH_MX7ULP
- bool "NXP MX7ULP"
+ bool "NXP MX7ULP"
select CPU_V7A
select ROM_UNIFIED_SECTIONS
imply MXC_GPIO
config ARCH_MX7
bool "Freescale MX7"
+ select ARCH_MISC_INIT
+ select BOARD_EARLY_INIT_F
select CPU_V7A
select SYS_FSL_HAS_SEC if SECURE_BOOT
select SYS_FSL_SEC_COMPAT_4
select SYS_FSL_SEC_LE
- select BOARD_EARLY_INIT_F
- select ARCH_MISC_INIT
imply MXC_GPIO
config ARCH_MX6
if ARCH_MX6
config SPL_LDSCRIPT
- default "arch/arm/mach-omap2/u-boot-spl.lds"
+ default "arch/arm/mach-omap2/u-boot-spl.lds"
endif
config ARCH_MX5
bool "Freescale MX5"
- select CPU_V7A
select BOARD_EARLY_INIT_F
+ select CPU_V7A
imply MXC_GPIO
config ARCH_OWL
select DM
select DM_SERIAL
select OF_CONTROL
+ imply CMD_DM
config ARCH_QEMU
bool "QEMU Virtual Platform"
select DM_SERIAL
select OF_CONTROL
select PL01X_SERIAL
+ imply CMD_DM
config ARCH_RMOBILE
bool "Renesas ARM SoCs"
+ select BOARD_EARLY_INIT_F
select DM
select DM_SERIAL
- select BOARD_EARLY_INIT_F
+ imply CMD_DM
imply FAT_WRITE
imply SYS_THUMB_BUILD
select DM
select DM_GPIO
select DM_SERIAL
- select SPMI
+ select MSM_SMEM
select OF_CONTROL
select OF_SEPARATE
select SMEM
- select MSM_SMEM
+ select SPMI
+ imply CMD_DM
config ARCH_SOCFPGA
bool "Altera SOCFPGA family"
select ARCH_EARLY_INIT_R
select ARCH_MISC_INIT
+ select ARM64 if TARGET_SOCFPGA_STRATIX10
select CPU_V7A if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
select DM
select DM_SERIAL
select ENABLE_ARM_SOC_BOOT0_HOOK if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
select OF_CONTROL
select SPL_DM_RESET if DM_RESET
+ select SPL_DM_SERIAL
select SPL_LIBCOMMON_SUPPORT
select SPL_LIBDISK_SUPPORT
select SPL_LIBGENERIC_SUPPORT
select SPL_MMC_SUPPORT if DM_MMC
select SPL_NAND_SUPPORT if SPL_NAND_DENALI
select SPL_OF_CONTROL
+ select SPL_SEPARATE_BSS if TARGET_SOCFPGA_STRATIX10
select SPL_SERIAL_SUPPORT
- select SPL_DM_SERIAL
select SPL_SPI_FLASH_SUPPORT if SPL_SPI_SUPPORT
select SPL_SPI_SUPPORT if DM_SPI
select SPL_WATCHDOG_SUPPORT
select SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE
select SYS_NS16550
select SYS_THUMB_BUILD if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
- select ARM64 if TARGET_SOCFPGA_STRATIX10
+ imply CMD_DM
imply CMD_MTDPARTS
imply CRC32_VERIFY
imply DM_SPI
imply DM_SPI_FLASH
imply FAT_WRITE
imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
- select SPL_SEPARATE_BSS if TARGET_SOCFPGA_STRATIX10
config ARCH_SUNXI
bool "Support sunxi (Allwinner) SoCs"
select SPECIFY_CONSOLE_INDEX
select SPL_STACK_R if SPL
select SPL_SYS_MALLOC_SIMPLE if SPL
- select SYS_NS16550
select SPL_SYS_THUMB_BUILD if !ARM64
+ select SYS_NS16550
select SYS_THUMB_BUILD if !ARM64
select USB if DISTRO_DEFAULTS
- select USB_STORAGE if DISTRO_DEFAULTS
select USB_KEYBOARD if DISTRO_DEFAULTS
+ select USB_STORAGE if DISTRO_DEFAULTS
select USE_TINY_PRINTF
+ imply CMD_DM
imply CMD_GPT
imply DISTRO_DEFAULTS
imply FAT_WRITE
config ARCH_ZYNQ
bool "Xilinx Zynq based platform"
+ select BOARD_EARLY_INIT_F if WDT
select BOARD_LATE_INIT
+ select CLK
+ select CLK_ZYNQ
select CPU_V7A
- select SUPPORT_SPL
- select OF_CONTROL
- select SPL_BOARD_INIT if SPL
- select BOARD_EARLY_INIT_F if WDT
- select SPL_OF_CONTROL if SPL
select DM
select DM_ETH if NET
- select SPL_DM if SPL
select DM_MMC if MMC
- select DM_SPI
select DM_SERIAL
+ select DM_SPI
select DM_SPI_FLASH
- select SPL_SEPARATE_BSS if SPL
select DM_USB if USB
- select CLK
- select SPL_CLK if SPL
- select CLK_ZYNQ
+ select OF_CONTROL
select SPI
+ select SPL_BOARD_INIT if SPL
+ select SPL_CLK if SPL
+ select SPL_DM if SPL
+ select SPL_OF_CONTROL if SPL
+ select SPL_SEPARATE_BSS if SPL
+ select SUPPORT_SPL
+ imply ARCH_EARLY_INIT_R
imply CMD_CLK
- imply FAT_WRITE
+ imply CMD_DM
imply CMD_SPL
- imply ARCH_EARLY_INIT_R
+ imply FAT_WRITE
config ARCH_ZYNQMP_R5
bool "Xilinx ZynqMP R5 based platform"
+ select CLK
select CPU_V7R
- select OF_CONTROL
select DM
select DM_SERIAL
- select CLK
+ select OF_CONTROL
+ imply CMD_DM
config ARCH_ZYNQMP
bool "Xilinx ZynqMP based platform"
select ARM64
select BOARD_LATE_INIT
+ select CLK
select DM
- select OF_CONTROL
select DM_SERIAL
- select SUPPORT_SPL
- select CLK
+ select DM_USB if USB
+ select OF_CONTROL
select SPL_BOARD_INIT if SPL
select SPL_CLK if SPL
- select DM_USB if USB
+ select SUPPORT_SPL
+ imply CMD_DM
imply FAT_WRITE
config TEGRA
config TARGET_VEXPRESS64_BASE_FVP
bool "Support Versatile Express ARMv8a FVP BASE model"
select ARM64
- select SEMIHOSTING
select PL01X_SERIAL
+ select SEMIHOSTING
config TARGET_VEXPRESS64_BASE_FVP_DRAM
bool "Support Versatile Express ARMv8a FVP BASE model booting from DRAM"
config TARGET_LS2080A_EMU
bool "Support ls2080a_emu"
select ARCH_LS2080A
+ select ARCH_MISC_INIT
select ARM64
select ARMV8_MULTIENTRY
- select ARCH_MISC_INIT
help
Support for Freescale LS2080A_EMU platform
The LS2080A Development System (EMULATOR) is a pre silicon
config TARGET_LS2080A_SIMU
bool "Support ls2080a_simu"
select ARCH_LS2080A
+ select ARCH_MISC_INIT
select ARM64
select ARMV8_MULTIENTRY
- select ARCH_MISC_INIT
help
Support for Freescale LS2080A_SIMU platform
The LS2080A Development System (QDS) is a pre silicon
config TARGET_LS1088AQDS
bool "Support ls1088aqds"
select ARCH_LS1088A
+ select ARCH_MISC_INIT
select ARM64
select ARMV8_MULTIENTRY
- select ARCH_MISC_INIT
select BOARD_LATE_INIT
select SUPPORT_SPL
help
config TARGET_LS2080AQDS
bool "Support ls2080aqds"
select ARCH_LS2080A
+ select ARCH_MISC_INIT
select ARM64
select ARMV8_MULTIENTRY
select BOARD_LATE_INIT
select SUPPORT_SPL
- select ARCH_MISC_INIT
imply SCSI
imply SCSI_AHCI
help
config TARGET_LS2080ARDB
bool "Support ls2080ardb"
select ARCH_LS2080A
+ select ARCH_MISC_INIT
select ARM64
select ARMV8_MULTIENTRY
select BOARD_LATE_INIT
select SUPPORT_SPL
- select ARCH_MISC_INIT
imply SCSI
imply SCSI_AHCI
help
config TARGET_LS2081ARDB
bool "Support ls2081ardb"
select ARCH_LS2080A
+ select ARCH_MISC_INIT
select ARM64
select ARMV8_MULTIENTRY
select BOARD_LATE_INIT
select SUPPORT_SPL
- select ARCH_MISC_INIT
help
Support for Freescale LS2081ARDB platform.
The LS2081A Reference design board (RDB) is a high-performance
select OF_CONTROL
select PL01X_SERIAL
select SPECIFY_CONSOLE_INDEX
+ imply CMD_DM
help
Support for HiKey 96boards platform. It features a HI6220
SoC, with 8xA53 CPU, mali450 gpu, and 1GB RAM.
bool "Support Poplar 96boards Enterprise Edition Platform"
select ARM64
select DM
- select OF_CONTROL
select DM_SERIAL
select DM_USB
+ select OF_CONTROL
select PL01X_SERIAL
+ imply CMD_DM
help
Support for Poplar 96boards EE platform. It features a HI3798cv200
SoC, with 4xA53 CPU, 1GB RAM and the high performance Mali T720 GPU
config TARGET_LS1012AFRWY
bool "Support ls1012afrwy"
select ARCH_LS1012A
- select BOARD_LATE_INIT
select ARM64
+ select BOARD_LATE_INIT
imply SCSI
imply SCSI_AHCI
help
config TARGET_LS1088ARDB
bool "Support ls1088ardb"
select ARCH_LS1088A
+ select ARCH_MISC_INIT
select ARM64
select ARMV8_MULTIENTRY
- select ARCH_MISC_INIT
select BOARD_LATE_INIT
select SUPPORT_SPL
help
config TARGET_LS1021AQDS
bool "Support ls1021aqds"
+ select ARCH_LS1021A
+ select ARCH_SUPPORT_PSCI
+ select BOARD_EARLY_INIT_F
select BOARD_LATE_INIT
select CPU_V7A
select CPU_V7_HAS_NONSEC
select CPU_V7_HAS_VIRT
- select SUPPORT_SPL
- select ARCH_LS1021A
- select ARCH_SUPPORT_PSCI
select LS1_DEEP_SLEEP
+ select SUPPORT_SPL
select SYS_FSL_DDR
- select BOARD_EARLY_INIT_F
imply SCSI
config TARGET_LS1021ATWR
bool "Support ls1021atwr"
+ select ARCH_LS1021A
+ select ARCH_SUPPORT_PSCI
+ select BOARD_EARLY_INIT_F
select BOARD_LATE_INIT
select CPU_V7A
select CPU_V7_HAS_NONSEC
select CPU_V7_HAS_VIRT
- select SUPPORT_SPL
- select ARCH_LS1021A
- select ARCH_SUPPORT_PSCI
select LS1_DEEP_SLEEP
- select BOARD_EARLY_INIT_F
+ select SUPPORT_SPL
imply SCSI
config TARGET_LS1021AIOT
bool "Support ls1021aiot"
+ select ARCH_LS1021A
+ select ARCH_SUPPORT_PSCI
select BOARD_LATE_INIT
select CPU_V7A
select CPU_V7_HAS_NONSEC
select CPU_V7_HAS_VIRT
select SUPPORT_SPL
- select ARCH_LS1021A
- select ARCH_SUPPORT_PSCI
imply SCSI
help
Support for Freescale LS1021AIOT platform.
select ARCH_LS1043A
select ARM64
select ARMV8_MULTIENTRY
+ select BOARD_EARLY_INIT_F
select BOARD_LATE_INIT
select SUPPORT_SPL
- select BOARD_EARLY_INIT_F
imply SCSI
help
Support for Freescale LS1043AQDS platform.
select ARCH_LS1043A
select ARM64
select ARMV8_MULTIENTRY
+ select BOARD_EARLY_INIT_F
select BOARD_LATE_INIT
select SUPPORT_SPL
- select BOARD_EARLY_INIT_F
imply SCSI
help
Support for Freescale LS1043ARDB platform.
select ARCH_LS1046A
select ARM64
select ARMV8_MULTIENTRY
+ select BOARD_EARLY_INIT_F
select BOARD_LATE_INIT
- select SUPPORT_SPL
select DM_SPI_FLASH if DM_SPI
- select BOARD_EARLY_INIT_F
+ select SUPPORT_SPL
imply SCSI
help
Support for Freescale LS1046AQDS platform.
select ARCH_LS1046A
select ARM64
select ARMV8_MULTIENTRY
+ select BOARD_EARLY_INIT_F
select BOARD_LATE_INIT
- select SUPPORT_SPL
select DM_SPI_FLASH if DM_SPI
select POWER_MC34VR500
- select BOARD_EARLY_INIT_F
+ select SUPPORT_SPL
imply SCSI
help
Support for Freescale LS1046ARDB platform.
select SPL_OF_CONTROL if SPL
select SPL_PINCTRL if SPL
select SUPPORT_SPL
+ imply CMD_DM
imply DISTRO_DEFAULTS
imply FAT_WRITE
help
select DM
select DM_SERIAL
select SYS_THUMB_BUILD
+ imply CMD_DM
config ARCH_STI
bool "Support STMicrolectronics SoCs"
+ select BLK
select CPU_V7A
select DM
- select DM_SERIAL
- select BLK
select DM_MMC
select DM_RESET
+ select DM_SERIAL
+ imply CMD_DM
help
Support for STMicroelectronics STiH407/10 SoC family.
This SoC is used on Linaro 96Board STiH410-B2260
select DM_GPIO
select DM_RESET
select DM_SERIAL
+ select MISC
select OF_CONTROL
select OF_LIBFDT
- select MISC
select PINCTRL
select REGMAP
select SUPPORT_SPL
select SYSCON
select SYSRESET
select SYS_THUMB_BUILD
+ imply CMD_DM
help
Support for STM32MP SoC family developed by STMicroelectronics,
MPUs based on ARM cortex A core
config ARCH_ROCKCHIP
bool "Support Rockchip SoCs"
- select OF_CONTROL
select BLK
select DM
- select SPL_DM if SPL
- select SYS_MALLOC_F
- select SYS_THUMB_BUILD if !ARM64
- select SPL_SYS_MALLOC_SIMPLE if SPL
select DM_GPIO
select DM_I2C
select DM_MMC
+ select DM_PWM
+ select DM_REGULATOR
select DM_SERIAL
select DM_SPI
select DM_SPI_FLASH
select DM_USB if USB
- select DM_PWM
- select DM_REGULATOR
select ENABLE_ARM_SOC_BOOT0_HOOK
+ select OF_CONTROL
select SPI
+ select SPL_DM if SPL
+ select SPL_SYS_MALLOC_SIMPLE if SPL
+ select SYS_MALLOC_F
+ select SYS_THUMB_BUILD if !ARM64
+ imply ADC
+ imply CMD_DM
imply DISTRO_DEFAULTS
imply FAT_WRITE
- imply USB_FUNCTION_FASTBOOT
- imply SPL_SYSRESET
- imply TPL_SYSRESET
- imply ADC
imply SARADC_ROCKCHIP
+ imply SPL_SYSRESET
imply SYS_NS16550
+ imply TPL_SYSRESET
+ imply USB_FUNCTION_FASTBOOT
config TARGET_THUNDERX_88XX
bool "Support ThunderX 88xx"
select ARM64
select OF_CONTROL
- select SYS_CACHE_SHIFT_7
select PL01X_SERIAL
+ select SYS_CACHE_SHIFT_7
config ARCH_ASPEED
bool "Support Aspeed SoCs"
- select OF_CONTROL
select DM
+ select OF_CONTROL
+ imply CMD_DM
endchoice
endmenu
config SPL_LDSCRIPT
- default "arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds" if (ARCH_MX23 || ARCH_MX28) && !SPL_FRAMEWORK
- default "arch/arm/cpu/arm1136/u-boot-spl.lds" if CPU_ARM1136
+ default "arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds" if (ARCH_MX23 || ARCH_MX28) && !SPL_FRAMEWORK
+ default "arch/arm/cpu/arm1136/u-boot-spl.lds" if CPU_ARM1136
default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARM64
ifdef CONFIG_ARM64
OBJCOPYFLAGS += -j .text -j .secure_text -j .secure_data -j .rodata -j .data \
-j .u_boot_list -j .rela.dyn -j .got -j .got.plt \
- -j .binman_sym_table
+ -j .binman_sym_table -j .text_rest
else
OBJCOPYFLAGS += -j .text -j .secure_text -j .secure_data -j .rodata -j .hash \
-j .data -j .got -j .got.plt -j .u_boot_list -j .rel.dyn \
- -j .binman_sym_table
+ -j .binman_sym_table -j .text_rest
endif
# if a dtb section exists we always have to include it
config ARMV7_LPAE
bool "Use LPAE page table format" if EXPERT
depends on CPU_V7A
- default n
+ default y if ARMV7_VIRT
---help---
Say Y here to use the long descriptor page table format. This is
required if U-Boot runs in HYP mode.
config ARCH_LS1021A
bool
+ select SYS_FSL_DDR_BE if SYS_FSL_DDR
+ select SYS_FSL_DDR_VER_50 if SYS_FSL_DDR
select SYS_FSL_ERRATUM_A008378
select SYS_FSL_ERRATUM_A008407
select SYS_FSL_ERRATUM_A008997
select SYS_FSL_ERRATUM_A009942
select SYS_FSL_ERRATUM_A010315
select SYS_FSL_HAS_CCI400
- select SYS_FSL_SRDS_1
- select SYS_HAS_SERDES
- select SYS_FSL_DDR_BE if SYS_FSL_DDR
- select SYS_FSL_DDR_VER_50 if SYS_FSL_DDR
select SYS_FSL_HAS_DDR3 if SYS_FSL_DDR
select SYS_FSL_HAS_DDR4 if SYS_FSL_DDR
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_COMPAT_5
select SYS_FSL_SEC_LE
+ select SYS_FSL_SRDS_1
+ select SYS_HAS_SERDES
+ imply CMD_PCI
imply SCSI
imply SCSI_AHCI
- imply CMD_PCI
menu "LS102xA architecture"
depends on ARCH_LS1021A
#ifdef CONFIG_ARMV7_VIRT
orreq r5, r5, #0x100 @ allow HVC instruction
moveq r6, #HYP_MODE @ Enter the kernel as HYP
+ mrseq r3, sp_svc
+ msreq sp_hyp, r3 @ migrate SP
#endif
mcr p15, 0, r5, c1, c1, 0 @ write SCR (with NS bit set)
menu "ARMv8 secure monitor firmware"
config ARMV8_SEC_FIRMWARE_SUPPORT
bool "Enable ARMv8 secure monitor firmware framework support"
- select OF_LIBFDT
select FIT
+ select OF_LIBFDT
help
This framework is aimed at making secure monitor firmware load
process brief.
config SPL_ARMV8_SEC_FIRMWARE_SUPPORT
bool "Enable ARMv8 secure monitor firmware framework support for SPL"
- select SPL_OF_LIBFDT
select SPL_FIT
+ select SPL_OF_LIBFDT
help
Say Y here to support this framework in SPL phase.
#include <asm/io.h>
#include <linux/errno.h>
#include <asm/system.h>
+#include <fm_eth.h>
#include <asm/armv8/mmu.h>
#include <asm/io.h>
#include <asm/arch/fsl_serdes.h>
#include <fsl_immap.h>
#include <asm/arch/mp.h>
#include <efi_loader.h>
-#include <fm_eth.h>
#include <fsl-mc/fsl_mc.h>
#ifdef CONFIG_FSL_ESDHC
#include <fsl_esdhc.h>
The "loadables" is not optional. It tells SPL which images to load into memory.
+Falcon mode with QSPI boot
+--------------------------
+To use falcon mode with QSPI boot, SPL needs to be enabled. Similar to SD or
+NAND boot, a RAM version full feature U-Boot is needed. Unlike SD or NAND boot,
+SPL with QSPI doesn't need to combine SPL image with RAM version image. Two
+separated images are used, u-boot-spl.pbl and u-boot.img. The former is SPL
+image with RCW and PBI commands to load the SPL payload into On-Chip RAM. The
+latter is RAM version U-Boot in FIT format (or legacy format if FIT is not
+used).
+
Other things to consider
-----------------------
Falcon boot skips a lot of initialization in U-Boot. If Linux expects the
#include <common.h>
#include <fsl_immap.h>
#include <fsl_ifc.h>
-#include <ahci.h>
-#include <scsi.h>
#include <asm/arch/fsl_serdes.h>
#include <asm/arch/soc.h>
#include <asm/io.h>
#endif
}
-#ifdef CONFIG_SCSI_AHCI_PLAT
-int sata_init(void)
-{
- struct ccsr_ahci __iomem *ccsr_ahci;
-
-#ifdef CONFIG_SYS_SATA2
- ccsr_ahci = (void *)CONFIG_SYS_SATA2;
- out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
- out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY2_CFG);
- out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY3_CFG);
- out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
- out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG);
-#endif
-
-#ifdef CONFIG_SYS_SATA1
- ccsr_ahci = (void *)CONFIG_SYS_SATA1;
- out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
- out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY2_CFG);
- out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY3_CFG);
- out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
- out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG);
-
- ahci_init((void __iomem *)CONFIG_SYS_SATA1);
- scsi_scan(false);
-#endif
-
- return 0;
-}
-#endif
-
/* Get VDD in the unit mV from voltage ID */
int get_core_volt_from_fuse(void)
{
}
#elif defined(CONFIG_FSL_LSCH2)
-#ifdef CONFIG_SCSI_AHCI_PLAT
-int sata_init(void)
-{
- struct ccsr_ahci __iomem *ccsr_ahci = (void *)CONFIG_SYS_SATA;
-
- /* Disable SATA ECC */
- out_le32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + 0x520, 0x80000000);
- out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
- out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY2_CFG);
- out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY3_CFG);
- out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
- out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG);
-
- ahci_init((void __iomem *)CONFIG_SYS_SATA);
- scsi_scan(false);
-
- return 0;
-}
-#endif
static void erratum_a009929(void)
{
#ifdef CONFIG_BOARD_LATE_INIT
int board_late_init(void)
{
-#ifdef CONFIG_SCSI_AHCI_PLAT
- sata_init();
-#endif
#ifdef CONFIG_CHAIN_OF_TRUST
fsl_setenv_chain_of_trust();
#endif
#include <fsl_csu.h>
#include <asm/arch/fdt.h>
#include <asm/arch/ppa.h>
+#include <asm/arch/soc.h>
DECLARE_GLOBAL_DATA_PTR;
#endif
#ifdef CONFIG_SPL_NAND_SUPPORT
return BOOT_DEVICE_NAND;
+#endif
+#ifdef CONFIG_QSPI_BOOT
+ return BOOT_DEVICE_NOR;
#endif
return 0;
}
void board_init_f(ulong dummy)
{
+ icache_enable();
/* Clear global data */
memset((void *)gd, 0, sizeof(gd_t));
board_early_init_f();
gd->arch.tlb_addr = (gd->ram_top - gd->arch.tlb_size) & ~(0x10000 - 1);
gd->arch.tlb_allocated = gd->arch.tlb_addr;
#endif /* CONFIG_SPL_FSL_LS_PPA */
+#if defined(CONFIG_QSPI_AHB_INIT) && defined(CONFIG_QSPI_BOOT)
+ qspi_ahb_init();
+#endif
}
#ifdef CONFIG_SPL_OS_BOOT
{
*(.__image_copy_start)
CPUDIR/start.o (.text*)
+ }
+
+ /* This needs to come before *(.text*) */
+ .efi_runtime : {
+ __efi_runtime_start = .;
+ *(.text.efi_runtime*)
+ *(.rodata.efi_runtime*)
+ *(.data.efi_runtime*)
+ __efi_runtime_stop = .;
+ }
+
+ .text_rest :
+ {
*(.text*)
}
. = ALIGN(8);
- .efi_runtime : {
- __efi_runtime_start = .;
- *(efi_runtime_text)
- *(efi_runtime_data)
- __efi_runtime_stop = .;
- }
-
.efi_runtime_rel : {
__efi_runtime_rel_start = .;
- *(.relaefi_runtime_text)
- *(.relaefi_runtime_data)
+ *(.rel*.efi_runtime)
+ *(.rel*.efi_runtime.*)
__efi_runtime_rel_stop = .;
}
*(.__image_copy_start)
*(.vectors)
CPUDIR/start.o (.text*)
+ }
+
+ /* This needs to come before *(.text*) */
+ .__efi_runtime_start : {
+ *(.__efi_runtime_start)
+ }
+
+ .efi_runtime : {
+ *(.text.efi_runtime*)
+ *(.rodata.efi_runtime*)
+ *(.data.efi_runtime*)
+ }
+
+ .__efi_runtime_stop : {
+ *(.__efi_runtime_stop)
+ }
+
+ .text_rest :
+ {
*(.text*)
}
. = ALIGN(4);
- .__efi_runtime_start : {
- *(.__efi_runtime_start)
- }
-
- .efi_runtime : {
- *(efi_runtime_text)
- *(efi_runtime_data)
- }
-
- .__efi_runtime_stop : {
- *(.__efi_runtime_stop)
- }
-
.efi_runtime_rel_start :
{
*(.__efi_runtime_rel_start)
}
.efi_runtime_rel : {
- *(.relefi_runtime_text)
- *(.relefi_runtime_data)
+ *(.rel*.efi_runtime)
+ *(.rel*.efi_runtime.*)
}
.efi_runtime_rel_stop :
&duart0 {
status = "okay";
};
+
+&sata {
+ status = "okay";
+};
status = "okay";
phy_type = "ulpi";
};
+
+&sata {
+ status = "okay";
+};
&duart0 {
status = "okay";
};
+
+&sata {
+ status = "okay";
+};
0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
};
+ sata: sata@3200000 {
+ compatible = "fsl,ls1012a-ahci";
+ reg = <0x0 0x3200000 0x0 0x10000>;
+ interrupts = <0 69 4>;
+ clocks = <&clockgen 4 0>;
+ status = "disabled";
+ };
+
usb0: usb2@8600000 {
compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
reg = <0x0 0x8600000 0x0 0x1000>;
vccio-supply = <&sys_3v3_reg>;
regulators {
- #address-cells = <1>;
- #size-cells = <0>;
-
/* SW1: +V1.35_VDDIO_DDR */
vdd1_reg: vdd1 {
regulator-name = "vddio_ddr_1v35";
vccio-supply = <&vdd_5v_in_reg>;
regulators {
- #address-cells = <1>;
- #size-cells = <0>;
-
vdd1_reg: vdd1 {
regulator-name = "vddio_ddr_1v2";
regulator-min-microvolt = <1200000>;
#define SVR_DEV(svr) ((svr) >> 8)
#define IS_SVR_DEV(svr, dev) (((svr) >> 16) == (dev))
-/* ahci port register default value */
-#define AHCI_PORT_PHY_1_CFG 0xa003fffe
-#define AHCI_PORT_PHY2_CFG 0x28184d1f
-#define AHCI_PORT_PHY3_CFG 0x0e081509
-#define AHCI_PORT_TRANS_CFG 0x08000029
-#define AHCI_PORT_AXICC_CFG 0x3fffffff
-
#ifndef __ASSEMBLY__
-/* AHCI (sata) register map */
-struct ccsr_ahci {
- u32 res1[0xa4/4]; /* 0x0 - 0xa4 */
- u32 pcfg; /* port config */
- u32 ppcfg; /* port phy1 config */
- u32 pp2c; /* port phy2 config */
- u32 pp3c; /* port phy3 config */
- u32 pp4c; /* port phy4 config */
- u32 pp5c; /* port phy5 config */
- u32 axicc; /* AXI cache control */
- u32 paxic; /* port AXI config */
- u32 axipc; /* AXI PROT control */
- u32 ptc; /* port Trans Config */
- u32 pts; /* port Trans Status */
- u32 plc; /* port link config */
- u32 plc1; /* port link config1 */
- u32 plc2; /* port link config2 */
- u32 pls; /* port link status */
- u32 pls1; /* port link status1 */
- u32 pcmdc; /* port CMD config */
- u32 ppcs; /* port phy control status */
- u32 pberr; /* port 0/1 BIST error */
- u32 cmds; /* port 0/1 CMD status error */
-};
-
#ifdef CONFIG_FSL_LSCH3
void fsl_lsch3_early_init_f(void);
int get_core_volt_from_fuse(void);
void init_pfe_scfg_dcfg_regs(void);
#endif
#endif
+#ifdef CONFIG_QSPI_AHB_INIT
+int qspi_ahb_init(void);
+#endif
void cpu_name(char *name);
#ifdef CONFIG_SYS_FSL_ERRATUM_A009635
u32 flow_dbg_cnt0; /* offset 0x48 */
u32 flow_dbg_cnt1; /* offset 0x4c */
u32 flow_dbg_qual; /* offset 0x50 */
- u32 flow_ctlr_spare; /* offset 0x54 */
+ u32 flow_ctrl_spare; /* offset 0x54 */
u32 ram_repair_cluster1;/* offset 0x58 */
};
#define CSR_WAIT_WFI_SHIFT 8
#define CSR_PWR_OFF_STS (1 << 16)
-/* RAM_REPAIR, 0x40, 0x58 */
-enum {
- RAM_REPAIR_REQ = 0x1 << 0,
- RAM_REPAIR_STS = 0x1 << 1,
-};
+#define RAM_REPAIR_REQ BIT(0)
+#define RAM_REPAIR_STS BIT(1)
+#define RAM_REPAIR_BYPASS_EN BIT(2)
#endif /* _TEGRA124_FLOW_H_ */
#define FIQ_MODE 0x11
#define IRQ_MODE 0x12
#define SVC_MODE 0x13
+#define MON_MODE 0x16
#define ABT_MODE 0x17
#define HYP_MODE 0x1a
#define UND_MODE 0x1b
psci_ver = sec_firmware_support_psci_version();
#elif defined(CONFIG_ARMV7_PSCI_1_0) || defined(CONFIG_ARMV8_PSCI)
psci_ver = ARM_PSCI_VER_1_0;
+#elif defined(CONFIG_ARMV7_PSCI_0_2)
+ psci_ver = ARM_PSCI_VER_0_2;
#endif
if (psci_ver >= ARM_PSCI_VER_1_0) {
tmp = fdt_setprop_string(fdt, nodeoff,
if (tmp)
return tmp;
+ tmp = fdt_setprop_string(fdt, nodeoff, "status", "okay");
+ if (tmp)
+ return tmp;
+
#endif
return 0;
}
bool "Support snapper9260"
select AT91SAM9260
select DM
- select DM_SERIAL
select DM_GPIO
+ select DM_SERIAL
+ imply CMD_DM
config TARGET_GURNARD
bool "Support gurnard"
select AT91SAM9G45
select BOARD_LATE_INIT
select DM
+ select DM_ETH
+ select DM_GPIO
select DM_SERIAL
select DM_SPI
- select DM_GPIO
- select DM_ETH
select SPI
+ imply CMD_DM
config TARGET_AT91SAM9261EK
bool "Atmel at91sam9261 reference board"
config TARGET_AT91SAM9M10G45EK
bool "Atmel AT91SAM9M10G45-EK board"
select AT91SAM9M10G45
- select SUPPORT_SPL
select BOARD_EARLY_INIT_F
+ select SUPPORT_SPL
config TARGET_PM9G45
bool "Ronetix pm9g45 board"
config TARGET_AT91SAM9N12EK
bool "Atmel AT91SAM9N12-EK board"
select AT91SAM9N12
- select SUPPORT_SPL
select BOARD_EARLY_INIT_F
+ select SUPPORT_SPL
config TARGET_AT91SAM9RLEK
bool "Atmel at91sam9rl reference board"
config TARGET_AT91SAM9X5EK
bool "Atmel AT91SAM9X5-EK board"
select AT91SAM9X5
- select SUPPORT_SPL
select BOARD_EARLY_INIT_F
select BOARD_LATE_INIT
+ select SUPPORT_SPL
config TARGET_SAMA5D2_PTC_EK
bool "SAMA5D2 PTC EK board"
- select SAMA5D2
select BOARD_EARLY_INIT_F
+ select SAMA5D2
config TARGET_SAMA5D2_XPLAINED
bool "SAMA5D2 Xplained board"
- select SAMA5D2
- select SUPPORT_SPL
select BOARD_EARLY_INIT_F
select BOARD_LATE_INIT
+ select SAMA5D2
+ select SUPPORT_SPL
config TARGET_SAMA5D27_SOM1_EK
bool "SAMA5D27 SOM1 EK board"
- select CPU_V7A
- select SUPPORT_SPL
select BOARD_EARLY_INIT_F
select BOARD_LATE_INIT
+ select CPU_V7A
+ select SUPPORT_SPL
help
The SAMA5D27 SOM1 embeds SAMA5D2 SiP(System in Package),
a 64Mbit QSPI flash, KSZ8081 Phy and a Mac-address EEPROM
config TARGET_SAMA5D3_XPLAINED
bool "SAMA5D3 Xplained board"
+ select BOARD_EARLY_INIT_F
select SAMA5D3
select SUPPORT_SPL
- select BOARD_EARLY_INIT_F
config TARGET_SAMA5D3XEK
bool "SAMA5D3X-EK board"
- select SAMA5D3
+ select BOARD_EARLY_INIT_F
select BOARD_LATE_INIT
+ select SAMA5D3
select SUPPORT_SPL
- select BOARD_EARLY_INIT_F
config TARGET_SAMA5D4_XPLAINED
bool "SAMA5D4 Xplained board"
- select SAMA5D4
- select SUPPORT_SPL
select BOARD_EARLY_INIT_F
select BOARD_LATE_INIT
+ select SAMA5D4
+ select SUPPORT_SPL
config TARGET_SAMA5D4EK
bool "SAMA5D4 Evaluation Kit"
- select SAMA5D4
- select SUPPORT_SPL
select BOARD_EARLY_INIT_F
select BOARD_LATE_INIT
+ select SAMA5D4
+ select SUPPORT_SPL
config TARGET_MEESC
bool "Support meesc"
config TARGET_CORVUS
bool "Support corvus"
select AT91SAM9M10G45
- select SUPPORT_SPL
select DM
- select DM_SERIAL
- select DM_GPIO
select DM_ETH
+ select DM_GPIO
+ select DM_SERIAL
+ select SUPPORT_SPL
+ imply CMD_DM
config TARGET_TAURUS
bool "Support taurus"
select AT91SAM9G20
- select SUPPORT_SPL
select DM
+ select DM_ETH
+ select DM_GPIO
select DM_SERIAL
select DM_SPI
- select DM_GPIO
- select DM_ETH
select SPI
+ select SUPPORT_SPL
+ imply CMD_DM
config TARGET_SMARTWEB
bool "Support smartweb"
select AT91SAM9260
- select SUPPORT_SPL
select DM
- select DM_SERIAL
- select DM_GPIO
select DM_ETH
+ select DM_GPIO
+ select DM_SERIAL
+ select SUPPORT_SPL
+ imply CMD_DM
config TARGET_VINCO
bool "Support VINCO"
- select SAMA5D4
- select SUPPORT_SPL
select DM
select DM_SPI
+ select SAMA5D4
select SPI
+ select SUPPORT_SPL
+ imply CMD_DM
config TARGET_WB45N
bool "Support Laird WB45N"
config TARGET_WB50N
bool "Support Laird WB50N"
+ select BOARD_EARLY_INIT_F
select BOARD_LATE_INIT
select CPU_V7A
select SUPPORT_SPL
- select BOARD_EARLY_INIT_F
endchoice
config TARGET_EA20
bool "EA20 board"
+ select BOARD_LATE_INIT
select MACH_DAVINCI_DA850_EVM
select SOC_DA850
- select BOARD_LATE_INIT
config TARGET_OMAPL138_LCDK
bool "OMAPL138 LCDK"
config SOC_DA8XX
bool
- select SYS_DA850_PLL_INIT if SUPPORT_SPL || DA850_LOWLEVEL
select SYS_DA850_DDR_INIT if SUPPORT_SPL || DA850_LOWLEVEL
+ select SYS_DA850_PLL_INIT if SUPPORT_SPL || DA850_LOWLEVEL
config MACH_DAVINCI_DA850_EVM
bool
config ARCH_EXYNOS4
bool "Exynos4 SoC family"
- select CPU_V7A
select BOARD_EARLY_INIT_F
+ select CPU_V7A
help
Samsung Exynos4 SoC family are based on ARM Cortex-A9 CPU. There
are multiple SoCs in this family including Exynos4210, Exynos4412,
config ARCH_EXYNOS5
bool "Exynos5 SoC family"
- select CPU_V7A
select BOARD_EARLY_INIT_F
+ select CPU_V7A
select SHA_HW_ACCEL
- imply CRC32_VERIFY
imply CMD_HASH
+ imply CRC32_VERIFY
imply HASH_VERIFY
- imply USB_ETHER_RTL8152
imply USB_ETHER_ASIX
+ imply USB_ETHER_RTL8152
imply USB_ETHER_SMSC95XX
help
Samsung Exynos5 SoC family are based on ARM Cortex-A15 CPU (and
prompt "EXYNOS4 board select"
config TARGET_SMDKV310
- select SUPPORT_SPL
bool "Exynos4210 SMDKV310 board"
select OF_CONTROL
+ select SUPPORT_SPL
config TARGET_TRATS
bool "Exynos4210 Trats board"
select ARM_ERRATA_774769
select CPU_V7_HAS_NONSEC
select CPU_V7_HAS_VIRT
- select SUPPORT_SPL
select OF_CONTROL
+ select SUPPORT_SPL
config TARGET_SMDK5250
bool "SMDK5250 board"
- select SUPPORT_SPL
select OF_CONTROL
+ select SUPPORT_SPL
config TARGET_SNOW
bool "Snow board"
- select SUPPORT_SPL
select OF_CONTROL
+ select SUPPORT_SPL
config TARGET_SPRING
bool "Spring board"
- select SUPPORT_SPL
select OF_CONTROL
select SPL_DISABLE_OF_CONTROL
+ select SUPPORT_SPL
config TARGET_SMDK5420
bool "SMDK5420 board"
- select SUPPORT_SPL
select OF_CONTROL
+ select SUPPORT_SPL
config TARGET_PEACH_PI
bool "Peach Pi board"
- select SUPPORT_SPL
select OF_CONTROL
+ select SUPPORT_SPL
config TARGET_PEACH_PIT
bool "Peach Pit board"
- select SUPPORT_SPL
select OF_CONTROL
+ select SUPPORT_SPL
endchoice
endif
bool "ESPRESSO7420 board"
select ARM64
select ARMV8_MULTIENTRY
- select SUPPORT_SPL
+ select CLK_EXYNOS
select OF_CONTROL
- select SPL_DISABLE_OF_CONTROL
select PINCTRL
select PINCTRL_EXYNOS7420
- select CLK_EXYNOS
+ select SPL_DISABLE_OF_CONTROL
+ select SUPPORT_SPL
endchoice
endif
config TARGET_MX31PDK
bool "Support the i.MX31 PDK board from Freescale/NXP"
+ select BOARD_EARLY_INIT_F
select BOARD_LATE_INIT
select SUPPORT_SPL
- select BOARD_EARLY_INIT_F
endchoice
if ARCH_MX5
config MX5
- select GPT_TIMER
bool
default y
+ select GPT_TIMER
config MX51
bool
- select SYS_FSL_ERRATUM_ESDHC_A001
select ARM_CORTEX_A8_CVE_2017_5715
+ select SYS_FSL_ERRATUM_ESDHC_A001
config MX53
bool
config TARGET_KP_IMX53
bool "Support K+P imx53 board"
select BOARD_LATE_INIT
- select MX53
select DM
- select DM_SERIAL
select DM_ETH
- select DM_I2C
select DM_GPIO
+ select DM_I2C
select DM_PMIC
+ select DM_SERIAL
+ select MX53
+ imply CMD_DM
config TARGET_MX51EVK
bool "Support mx51evk"
config TARGET_MX53CX9020
bool "Support CX9020"
select BOARD_LATE_INIT
- select MX53
select DM
select DM_SERIAL
+ select MX53
+ imply CMD_DM
config TARGET_MX53EVK
bool "Support mx53evk"
if ARCH_MX6
config MX6_SMP
+ bool
select ARM_ERRATA_751472
select ARM_ERRATA_761320
select ARM_ERRATA_794072
select ARM_ERRATA_845369
select MP
- bool
config MX6
- select ARM_ERRATA_743622 if !MX6UL && !MX6ULL
- select GPT_TIMER if !MX6UL && !MX6ULL
bool
default y
+ select ARM_ERRATA_743622 if !MX6UL && !MX6ULL
+ select GPT_TIMER if !MX6UL && !MX6ULL
imply CMD_FUSE
config MX6D
+ bool
select HAS_CAAM
select MX6_SMP
- bool
config MX6DL
+ bool
select HAS_CAAM
select MX6_SMP
- bool
config MX6Q
+ bool
select HAS_CAAM
select MX6_SMP
- bool
config MX6QDL
+ bool
select HAS_CAAM
select MX6_SMP
- bool
config MX6S
- select HAS_CAAM
bool
+ select HAS_CAAM
config MX6SL
bool
config MX6SX
+ bool
select HAS_CAAM
select ROM_UNIFIED_SECTIONS
- bool
config MX6SLL
- select ROM_UNIFIED_SECTIONS
bool
+ select ROM_UNIFIED_SECTIONS
config MX6UL
+ bool
select HAS_CAAM
- select SYS_L2CACHE_OFF
select ROM_UNIFIED_SECTIONS
select SYSCOUNTER_TIMER
- bool
+ select SYS_L2CACHE_OFF
config MX6UL_LITESOM
bool
- select MX6UL
select DM
select DM_THERMAL
+ select MX6UL
select SUPPORT_SPL
+ imply CMD_DM
config MX6UL_OPOS6UL
bool
- select MX6UL
select BOARD_LATE_INIT
select DM
select DM_GPIO
select DM_MMC
select DM_THERMAL
- select SUPPORT_SPL
+ select MX6UL
select SPL_DM if SPL
select SPL_OF_CONTROL if SPL
- select SPL_SEPARATE_BSS if SPL
select SPL_PINCTRL if SPL
+ select SPL_SEPARATE_BSS if SPL
+ select SUPPORT_SPL
+ imply CMD_DM
config MX6ULL
- select SYS_L2CACHE_OFF
+ bool
select ROM_UNIFIED_SECTIONS
select SYSCOUNTER_TIMER
- bool
+ select SYS_L2CACHE_OFF
config MX6_DDRCAL
bool "Include dynamic DDR calibration routines"
config TARGET_APALIS_IMX6
bool "Toradex Apalis iMX6 board"
select BOARD_LATE_INIT
- select SUPPORT_SPL
select DM
select DM_SERIAL
select DM_THERMAL
+ select SUPPORT_SPL
+ imply CMD_DM
imply CMD_SATA
config TARGET_ARISTAINETOS
config TARGET_CGTQMX6EVAL
bool "cgtqmx6eval"
- select MX6QDL
select BOARD_LATE_INIT
- select SUPPORT_SPL
select DM
select DM_THERMAL
+ select MX6QDL
+ select SUPPORT_SPL
+ imply CMD_DM
config TARGET_CM_FX6
bool "CM-FX6"
- select SUPPORT_SPL
- select MX6QDL
select BOARD_LATE_INIT
select DM
- select DM_SERIAL
select DM_GPIO
+ select DM_SERIAL
+ select MX6QDL
+ select SUPPORT_SPL
+ imply CMD_DM
config TARGET_COLIBRI_IMX6
bool "Toradex Colibri iMX6 board"
select BOARD_LATE_INIT
- select SUPPORT_SPL
select DM
select DM_SERIAL
select DM_THERMAL
+ select SUPPORT_SPL
+ imply CMD_DM
config TARGET_COLIBRI_IMX6ULL
bool "Toradex Colibri iMX6ULL"
config TARGET_DHCOMIMX6
bool "dh_imx6"
- select MX6QDL
- select BOARD_LATE_INIT
select BOARD_EARLY_INIT_F
- select SUPPORT_SPL
+ select BOARD_LATE_INIT
select DM
select DM_THERMAL
+ select MX6QDL
+ select SUPPORT_SPL
+ imply CMD_DM
imply CMD_SPL
config TARGET_DISPLAY5
bool "LWN DISPLAY5 board"
- select SUPPORT_SPL
select DM
select DM_SERIAL
+ select SUPPORT_SPL
+ imply CMD_DM
config TARGET_EMBESTMX6BOARDS
bool "embestmx6boards"
config TARGET_MX6CUBOXI
bool "Solid-run mx6 boards"
- select MX6QDL
select BOARD_LATE_INIT
+ select MX6QDL
select SUPPORT_SPL
config TARGET_MX6LOGICPD
select DM_MMC
select DM_PMIC
select OF_CONTROL
+ imply CMD_DM
config TARGET_MX6MEMCAL
bool "mx6memcal"
config TARGET_MX6DL_MAMOJ
bool "Support BTicino Mamoj"
- select MX6QDL
- select OF_CONTROL
- select PINCTRL
select DM
select DM_ETH
select DM_GPIO
select DM_PMIC
select DM_PMIC_PFUZE100
select DM_THERMAL
+ select MX6QDL
+ select OF_CONTROL
+ select PINCTRL
select SPL
- select SUPPORT_SPL
select SPL_DM if SPL
- select SPL_OF_LIBFDT if SPL
- select SPL_OF_CONTROL if SPL
- select SPL_PINCTRL if SPL
- select SPL_SEPARATE_BSS if SPL
select SPL_GPIO_SUPPORT if SPL
select SPL_LIBCOMMON_SUPPORT if SPL
select SPL_LIBDISK_SUPPORT if SPL
select SPL_LIBGENERIC_SUPPORT if SPL
select SPL_MMC_SUPPORT if SPL
+ select SPL_OF_CONTROL if SPL
+ select SPL_OF_LIBFDT if SPL
+ select SPL_PINCTRL if SPL
+ select SPL_SEPARATE_BSS if SPL
select SPL_SERIAL_SUPPORT if SPL
- select SPL_USB_HOST_SUPPORT if SPL
select SPL_USB_GADGET_SUPPORT if SPL
+ select SPL_USB_HOST_SUPPORT if SPL
select SPL_USB_SDP_SUPPORT if SPL
select SPL_WATCHDOG_SUPPORT if SPL
+ select SUPPORT_SPL
+ imply CMD_DM
config TARGET_MX6Q_ENGICAM
bool "Support Engicam i.Core(RQS)"
select BOARD_LATE_INIT
- select MX6QDL
- select OF_CONTROL
- select SPL_OF_LIBFDT
select DM
select DM_ETH
select DM_GPIO
select DM_I2C
select DM_MMC
select DM_THERMAL
- select SUPPORT_SPL
+ select MX6QDL
+ select OF_CONTROL
select SPL_DM if SPL
select SPL_OF_CONTROL if SPL
- select SPL_SEPARATE_BSS if SPL
+ select SPL_OF_LIBFDT
select SPL_PINCTRL if SPL
+ select SPL_SEPARATE_BSS if SPL
+ select SUPPORT_SPL
+ imply CMD_DM
config TARGET_MX6SABREAUTO
bool "mx6sabreauto"
- select MX6QDL
+ select BOARD_EARLY_INIT_F
select BOARD_LATE_INIT
- select SUPPORT_SPL
select DM
select DM_THERMAL
- select BOARD_EARLY_INIT_F
+ select MX6QDL
+ select SUPPORT_SPL
+ imply CMD_DM
config TARGET_MX6SABRESD
bool "mx6sabresd"
- select MX6QDL
+ select BOARD_EARLY_INIT_F
select BOARD_LATE_INIT
- select SUPPORT_SPL
select DM
select DM_THERMAL
- select BOARD_EARLY_INIT_F
+ select MX6QDL
+ select SUPPORT_SPL
+ imply CMD_DM
config TARGET_MX6SLEVK
bool "mx6slevk"
select SUPPORT_SPL
config TARGET_MX6SLLEVK
- bool "mx6sll evk"
+ bool "mx6sll evk"
select BOARD_LATE_INIT
- select MX6SLL
- select DM
- select DM_THERMAL
+ select DM
+ select DM_THERMAL
+ select MX6SLL
+ imply CMD_DM
config TARGET_MX6SXSABRESD
bool "mx6sxsabresd"
+ select BOARD_EARLY_INIT_F
select BOARD_LATE_INIT
- select MX6SX
- select SUPPORT_SPL
select DM
select DM_THERMAL
- select BOARD_EARLY_INIT_F
+ select MX6SX
+ select SUPPORT_SPL
config TARGET_MX6SXSABREAUTO
- bool "mx6sxsabreauto"
+ bool "mx6sxsabreauto"
+ select BOARD_EARLY_INIT_F
select BOARD_LATE_INIT
+ select DM
+ select DM_THERMAL
select MX6SX
- select DM
- select DM_THERMAL
- select BOARD_EARLY_INIT_F
+ imply CMD_DM
config TARGET_MX6UL_9X9_EVK
bool "mx6ul_9x9_evk"
select BOARD_LATE_INIT
- select MX6UL
select DM
select DM_THERMAL
+ select MX6UL
select SUPPORT_SPL
+ imply CMD_DM
config TARGET_MX6UL_14X14_EVK
- select BOARD_LATE_INIT
bool "mx6ul_14x14_evk"
- select MX6UL
+ select BOARD_LATE_INIT
select DM
select DM_THERMAL
+ select MX6UL
select SUPPORT_SPL
+ imply CMD_DM
config TARGET_MX6UL_ENGICAM
bool "Support Engicam GEAM6UL/Is.IoT"
select BOARD_LATE_INIT
- select MX6UL
- select OF_CONTROL
select DM
select DM_ETH
select DM_GPIO
select DM_I2C
select DM_MMC
select DM_THERMAL
- select SUPPORT_SPL
+ select MX6UL
+ select OF_CONTROL
select SPL_DM if SPL
select SPL_OF_CONTROL if SPL
- select SPL_SEPARATE_BSS if SPL
select SPL_PINCTRL if SPL
+ select SPL_SEPARATE_BSS if SPL
+ select SUPPORT_SPL
+ imply CMD_DM
config TARGET_MX6ULL_14X14_EVK
bool "Support mx6ull_14x14_evk"
select BOARD_LATE_INIT
- select MX6ULL
select DM
select DM_THERMAL
+ select MX6ULL
+ imply CMD_DM
config TARGET_NITROGEN6X
bool "nitrogen6x"
- imply USB_HOST_ETHER
imply USB_ETHER_ASIX
- imply USB_ETHER_SMSC95XX
imply USB_ETHER_MCS7830
+ imply USB_ETHER_SMSC95XX
+ imply USB_HOST_ETHER
config TARGET_OPOS6ULDEV
bool "Armadeus OPOS6ULDev board"
config TARGET_PFLA02
bool "Phytec PFLA02 (PhyFlex) i.MX6 Quad"
- select MX6QDL
select BOARD_LATE_INIT
+ select MX6QDL
select SUPPORT_SPL
config TARGET_SECOMX6
config TARGET_KP_IMX6Q_TPC
bool "K+P KP_IMX6Q_TPC i.MX6 Quad"
- select MX6QDL
- select BOARD_LATE_INIT
select BOARD_EARLY_INIT_F
- select SUPPORT_SPL
+ select BOARD_LATE_INIT
select DM
select DM_THERMAL
+ select MX6QDL
+ select SUPPORT_SPL
+ imply CMD_DM
imply CMD_SPL
config TARGET_TQMA6
config TARGET_UDOO
bool "udoo"
- select MX6QDL
select BOARD_LATE_INIT
+ select MX6QDL
select SUPPORT_SPL
config TARGET_UDOO_NEO
bool "UDOO Neo"
select BOARD_LATE_INIT
- select SUPPORT_SPL
- select MX6SX
select DM
select DM_THERMAL
+ select MX6SX
+ select SUPPORT_SPL
+ imply CMD_DM
config TARGET_SAMTEC_VINING_2000
bool "samtec VIN|ING 2000"
select BOARD_LATE_INIT
- select MX6SX
select DM
select DM_THERMAL
+ select MX6SX
+ imply CMD_DM
config TARGET_WANDBOARD
bool "wandboard"
- select MX6QDL
select BOARD_LATE_INIT
+ select MX6QDL
select SUPPORT_SPL
config TARGET_WARP
bool "WaRP"
- select MX6SL
select BOARD_LATE_INIT
+ select MX6SL
config TARGET_XPRESS
bool "CCV xPress"
select BOARD_LATE_INIT
- select MX6UL
select DM
select DM_THERMAL
+ select MX6UL
select SUPPORT_SPL
+ imply CMD_DM
config TARGET_ZC5202
bool "zc5202"
select BOARD_LATE_INIT
- select SUPPORT_SPL
select DM
select DM_THERMAL
+ select SUPPORT_SPL
+ imply CMD_DM
config TARGET_ZC5601
bool "zc5601"
select BOARD_LATE_INIT
- select SUPPORT_SPL
select DM
select DM_THERMAL
+ select SUPPORT_SPL
+ imply CMD_DM
endchoice
config MX7
bool
+ default y
+ select ARCH_SUPPORT_PSCI
+ select CPU_V7_HAS_NONSEC
+ select CPU_V7_HAS_VIRT
select ROM_UNIFIED_SECTIONS
select SYSCOUNTER_TIMER
- select CPU_V7_HAS_VIRT
- select CPU_V7_HAS_NONSEC
- select ARCH_SUPPORT_PSCI
imply CMD_FUSE
- default y
config MX7D
+ bool
select HAS_CAAM
select ROM_UNIFIED_SECTIONS
imply CMD_FUSE
- bool
choice
prompt "MX7 board select"
config TARGET_CL_SOM_IMX7
bool "CL-SOM-iMX7"
- select MX7D
select DM
select DM_THERMAL
+ select MX7D
select SUPPORT_SPL
+ imply CMD_DM
config TARGET_MX7DSABRESD
bool "mx7dsabresd"
select BOARD_LATE_INIT
- select MX7D
select DM
select DM_THERMAL
+ select MX7D
+ imply CMD_DM
config TARGET_PICO_IMX7D
bool "pico-imx7d"
select BOARD_LATE_INIT
- select MX7D
select DM
select DM_THERMAL
+ select MX7D
select SUPPORT_SPL
+ imply CMD_DM
config TARGET_WARP7
bool "warp7"
select BOARD_LATE_INIT
- select MX7D
select DM
select DM_THERMAL
+ select MX7D
+ imply CMD_DM
config TARGET_COLIBRI_IMX7
bool "Support Colibri iMX7S/iMX7D modules"
select DM
select DM_SERIAL
select DM_THERMAL
+ imply CMD_DM
endchoice
select CLK
select DM
select DM_SERIAL
+ imply CMD_DM
help
The Amlogic Meson GXBaby (S905) is an ARM SoC with a
quad-core Cortex-A53 CPU and a Mali-450 GPU.
select CLK
select DM
select DM_SERIAL
+ imply CMD_DM
help
The Amlogic Meson GXL (S905X and S905D) is an ARM SoC with a
quad-core Cortex-A53 CPU and a Mali-450 GPU.
config ARMADA_32BIT
bool
+ select ARCH_MISC_INIT
+ select BOARD_EARLY_INIT_F
select CPU_V7A
- select SUPPORT_SPL
select SPL_DM
select SPL_DM_SEQ_ALIAS
select SPL_OF_CONTROL
select SPL_SIMPLE_BUS
- select BOARD_EARLY_INIT_F
- select ARCH_MISC_INIT
+ select SUPPORT_SPL
config ARMADA_64BIT
bool
config OMAP34XX
bool "OMAP34XX SoC"
+ select ARM_CORTEX_A8_CVE_2017_5715
select ARM_ERRATA_430973
select ARM_ERRATA_454179
select ARM_ERRATA_621766
select ARM_ERRATA_725233
- select ARM_CORTEX_A8_CVE_2017_5715
select USE_TINY_PRINTF
imply NAND_OMAP_GPMC
imply SPL_EXT_SUPPORT
config OMAP54XX
bool "OMAP54XX SoC"
+ select ARM_CORTEX_A15_CVE_2017_5715
select ARM_ERRATA_798870
select SYS_THUMB_BUILD
- select ARM_CORTEX_A15_CVE_2017_5715
imply NAND_OMAP_ELM
imply NAND_OMAP_GPMC
imply SPL_DISPLAY_PRINT
config AM33XX
bool "AM33XX SoC"
- select SPECIFY_CONSOLE_INDEX
select ARM_CORTEX_A8_CVE_2017_5715
+ select SPECIFY_CONSOLE_INDEX
imply NAND_OMAP_ELM
imply NAND_OMAP_GPMC
imply SPL_NAND_AM33XX_BCH
bool "Support am335x_evm"
select BOARD_LATE_INIT
select DM
- select DM_SERIAL
select DM_GPIO
+ select DM_SERIAL
select TI_I2C_BOARD_DETECT
+ imply CMD_DM
+ imply SPL_DM
+ imply SPL_DM_SEQ_ALIAS
imply SPL_ENV_SUPPORT
imply SPL_EXT_SUPPORT
imply SPL_FAT_SUPPORT
imply SPL_LIBGENERIC_SUPPORT
imply SPL_MMC_SUPPORT
imply SPL_NAND_SUPPORT
+ imply SPL_OF_LIBFDT
imply SPL_POWER_SUPPORT
+ imply SPL_SEPARATE_BSS
imply SPL_SERIAL_SUPPORT
+ imply SPL_SYS_MALLOC_SIMPLE
imply SPL_WATCHDOG_SUPPORT
imply SPL_YMODEM_SUPPORT
- imply SPL_SYS_MALLOC_SIMPLE
- imply SPL_SEPARATE_BSS
- imply SPL_DM
- imply SPL_DM_SEQ_ALIAS
- imply SPL_OF_LIBFDT
help
This option specifies support for the AM335x
GP and HS EVM development platforms. The AM335x
bool "Support am335x_baltos"
select BOARD_LATE_INIT
select DM
- select DM_SERIAL
select DM_GPIO
+ select DM_SERIAL
+ imply CMD_DM
config TARGET_AM335X_IGEP003X
bool "Support am335x_igep003x"
select BOARD_LATE_INIT
select DM
- select DM_SERIAL
select DM_GPIO
+ select DM_SERIAL
+ imply CMD_DM
config TARGET_AM335X_SHC
bool "Support am335x based shc board from bosch"
select BOARD_LATE_INIT
select DM
- select DM_SERIAL
select DM_GPIO
+ select DM_SERIAL
+ imply CMD_DM
imply CMD_SPL
config TARGET_AM335X_SL50
bool "Support am335x_sl50"
select BOARD_LATE_INIT
select DM
- select DM_SERIAL
select DM_GPIO
+ select DM_SERIAL
+ imply CMD_DM
config TARGET_BAV335X
bool "Support bav335x"
select BOARD_LATE_INIT
select DM
select DM_SERIAL
+ imply CMD_DM
help
The BAV335x OEM Network Processor integrates all the functions of an
embedded network computer in a small, easy to use SODIMM module which
select BOARD_LATE_INIT
select DM
select DM_SERIAL
+ imply CMD_DM
config TARGET_CM_T335
bool "Support cm_t335"
select DM
- select DM_SERIAL
select DM_GPIO
+ select DM_SERIAL
+ imply CMD_DM
config TARGET_DRACO
bool "Support draco"
select BOARD_LATE_INIT
select DM
- select DM_SERIAL
select DM_GPIO
+ select DM_SERIAL
+ imply CMD_DM
config TARGET_ETAMIN
bool "Support etamin"
select BOARD_LATE_INIT
select DM
- select DM_SERIAL
select DM_GPIO
+ select DM_SERIAL
+ imply CMD_DM
config TARGET_PCM051
bool "Support pcm051"
select DM
- select DM_SERIAL
select DM_GPIO
+ select DM_SERIAL
+ imply CMD_DM
config TARGET_PENGWYN
bool "Support pengwyn"
select DM
- select DM_SERIAL
select DM_GPIO
+ select DM_SERIAL
+ imply CMD_DM
config TARGET_PEPPER
bool "Support pepper"
select DM
- select DM_SERIAL
select DM_GPIO
+ select DM_SERIAL
+ imply CMD_DM
config TARGET_PXM2
bool "Support pxm2"
select BOARD_LATE_INIT
select DM
- select DM_SERIAL
select DM_GPIO
+ select DM_SERIAL
+ imply CMD_DM
config TARGET_RASTABAN
bool "Support rastaban"
select BOARD_LATE_INIT
select DM
- select DM_SERIAL
select DM_GPIO
+ select DM_SERIAL
+ imply CMD_DM
config TARGET_RUT
bool "Support rut"
select BOARD_LATE_INIT
select DM
- select DM_SERIAL
select DM_GPIO
+ select DM_SERIAL
+ imply CMD_DM
config TARGET_THUBAN
bool "Support thuban"
select BOARD_LATE_INIT
select DM
- select DM_SERIAL
select DM_GPIO
+ select DM_SERIAL
+ imply CMD_DM
config TARGET_PDU001
bool "Support PDU001"
select DM
select DM_SERIAL
+ imply CMD_DM
help
Support for PDU001 platform developed by EETS GmbH.
The PDU001 is a processor and display unit developed around
if AM43XX || AM33XX
config ISW_ENTRY_ADDR
hex "Address in memory or XIP flash of bootloader entry point"
+ default 0x402F4000 if AM43XX
+ default 0x402F0400 if AM33XX
help
After any reset, the boot ROM on the AM43XX SOC
searches the boot media for a valid boot image.
point address depending on the device type
(secure/non-secure), boot media (xip/non-xip) and
image headers.
- default 0x402F4000 if AM43XX
- default 0x402F0400 if AM33XX
config PUB_ROM_DATA_SIZE
hex "Size in bytes of the L3 SRAM reserved by ROM to store data"
+ default 0x8400
help
During the device boot, the public ROM uses the top of
the public L3 OCMC RAM to store r/w data like stack,
boot image. Once the ROM transfers control to the boot
image, this area is no longer used, and can be reclaimed
for run time use by the boot image.
- default 0x8400
endif
config TARGET_AM3517_EVM
bool "AM3517 EVM"
select DM
- select DM_SERIAL
select DM_GPIO
select DM_I2C
select DM_MMC
+ select DM_SERIAL
+ imply CMD_DM
config TARGET_MT_VENTOUX
bool "TeeJet Mt.Ventoux"
config TARGET_OMAP3_BEAGLE
bool "TI OMAP3 BeagleBoard"
select DM
- select DM_SERIAL
select DM_GPIO
+ select DM_SERIAL
select OMAP3_GPIO_5
select OMAP3_GPIO_6
+ imply CMD_DM
config TARGET_CM_T35
bool "CompuLab CM-T3530 and CM-T3730 boards"
config TARGET_DEVKIT8000
bool "TimLL OMAP3 Devkit8000"
select DM
- select DM_SERIAL
select DM_GPIO
+ select DM_SERIAL
+ imply CMD_DM
config TARGET_OMAP3_EVM
bool "TI OMAP3 EVM"
select DM
- select DM_SERIAL
select DM_GPIO
+ select DM_SERIAL
select OMAP3_GPIO_3
+ imply CMD_DM
config TARGET_OMAP3_IGEP00X0
bool "IGEP"
select DM
- select DM_SERIAL
select DM_GPIO
+ select DM_SERIAL
select OMAP3_GPIO_3
select OMAP3_GPIO_5
select OMAP3_GPIO_6
+ imply CMD_DM
config TARGET_OMAP3_OVERO
bool "OMAP35xx Gumstix Overo"
select DM
- select DM_SERIAL
select DM_GPIO
+ select DM_SERIAL
select OMAP3_GPIO_2
select OMAP3_GPIO_3
select OMAP3_GPIO_4
select OMAP3_GPIO_5
select OMAP3_GPIO_6
+ imply CMD_DM
config TARGET_OMAP3_ZOOM1
bool "TI Zoom1"
select DM
- select DM_SERIAL
select DM_GPIO
+ select DM_SERIAL
+ imply CMD_DM
config TARGET_AM3517_CRANE
bool "am3517_crane"
bool "OMAP3 Logic"
select BOARD_LATE_INIT
select DM
- select DM_SERIAL
select DM_GPIO
+ select DM_SERIAL
select OMAP3_GPIO_3
select OMAP3_GPIO_4
select OMAP3_GPIO_6
+ imply CMD_DM
config TARGET_NOKIA_RX51
bool "Nokia RX51"
config TARGET_OMAP3_CAIRO
bool "QUIPOS CAIRO"
select DM
- select DM_SERIAL
select DM_GPIO
+ select DM_SERIAL
+ imply CMD_DM
config TARGET_SNIPER
bool "LG Optimus Black"
select DM
- select DM_SERIAL
select DM_GPIO
+ select DM_SERIAL
select OMAP3_GPIO_2
select OMAP3_GPIO_3
select OMAP3_GPIO_4
select OMAP3_GPIO_5
select OMAP3_GPIO_6
+ imply CMD_DM
endchoice
bool "TI DRA7XX"
select BOARD_LATE_INIT
select DRA7XX
- select TI_I2C_BOARD_DETECT
select PHYS_64BIT
- imply SCSI
+ select TI_I2C_BOARD_DETECT
imply DM_PMIC
- imply PMIC_LP87565
imply DM_REGULATOR
imply DM_REGULATOR_LP87565
- imply SPL_THERMAL
imply DM_THERMAL
+ imply PMIC_LP87565
+ imply SCSI
+ imply SPL_THERMAL
imply TI_DRA7_THERMAL
config TARGET_AM57XX_EVM
bool "AM57XX"
select BOARD_LATE_INIT
+ select CMD_DDR3
select DRA7XX
select TI_I2C_BOARD_DETECT
- select CMD_DDR3
+ imply DM_THERMAL
imply SCSI
imply SPL_THERMAL
- imply DM_THERMAL
imply TI_DRA7_THERMAL
endchoice
config TARGET_QEMU_ARM_32BIT
bool "Support qemu_arm"
depends on ARCH_QEMU
- select CPU_V7A
select ARCH_SUPPORT_PSCI
+ select CPU_V7A
select SYS_ARCH_TIMER
config TARGET_QEMU_ARM_64BIT
select DM
select DM_SERIAL
select USE_TINY_PRINTF
+ imply CMD_DM
config TARGET_GOSE
bool "Gose board"
select DM
select DM_SERIAL
+ select SPL_TINY_MEMSET
select SUPPORT_SPL
select USE_TINY_PRINTF
- select SPL_TINY_MEMSET
+ imply CMD_DM
config TARGET_KOELSCH
bool "Koelsch board"
select DM
select DM_SERIAL
+ select SPL_TINY_MEMSET
select SUPPORT_SPL
select USE_TINY_PRINTF
- select SPL_TINY_MEMSET
+ imply CMD_DM
config TARGET_LAGER
bool "Lager board"
select DM
select DM_SERIAL
+ select SPL_TINY_MEMSET
select SUPPORT_SPL
select USE_TINY_PRINTF
- select SPL_TINY_MEMSET
+ imply CMD_DM
config TARGET_KZM9G
bool "KZM9D board"
bool "Alt board"
select DM
select DM_SERIAL
+ select SPL_TINY_MEMSET
select SUPPORT_SPL
select USE_TINY_PRINTF
- select SPL_TINY_MEMSET
+ imply CMD_DM
config TARGET_SILK
bool "Silk board"
select DM
select DM_SERIAL
+ select SPL_TINY_MEMSET
select SUPPORT_SPL
select USE_TINY_PRINTF
- select SPL_TINY_MEMSET
+ imply CMD_DM
config TARGET_PORTER
bool "Porter board"
select DM
select DM_SERIAL
+ select SPL_TINY_MEMSET
select SUPPORT_SPL
select USE_TINY_PRINTF
- select SPL_TINY_MEMSET
+ imply CMD_DM
config TARGET_STOUT
bool "Stout board"
select DM
select DM_SERIAL
+ select SPL_TINY_MEMSET
select SUPPORT_SPL
select USE_TINY_PRINTF
- select SPL_TINY_MEMSET
+ imply CMD_DM
endchoice
config TARGET_VYASA_RK3288
bool "Vyasa-RK3288"
select BOARD_LATE_INIT
- select TPL
+ select ROCKCHIP_BROM_HELPER
select SUPPORT_TPL
- select TPL_DM
- select TPL_REGMAP
- select TPL_SYSCON
- select TPL_CLK
- select TPL_RAM
- select TPL_OF_PLATDATA
- select TPL_OF_CONTROL
+ select TPL
select TPL_BOOTROM_SUPPORT
- select TPL_NEEDS_SEPARATE_TEXT_BASE if SPL
- select ROCKCHIP_BROM_HELPER
+ select TPL_CLK
+ select TPL_DM
select TPL_DRIVERS_MISC_SUPPORT
select TPL_LIBCOMMON_SUPPORT
select TPL_LIBGENERIC_SUPPORT
+ select TPL_NEEDS_SEPARATE_TEXT_BASE if SPL
+ select TPL_OF_CONTROL
+ select TPL_OF_PLATDATA
+ select TPL_RAM
+ select TPL_REGMAP
select TPL_SERIAL_SUPPORT
+ select TPL_SYSCON
help
Vyasa is a RK3288-based development board with 2 USB ports,
HDMI, VGA, micro-SD card, audio, WiFi and Gigabit Ethernet, It
config TARGET_SOCFPGA_ARRIA10
bool
- select SPL_BOARD_INIT if SPL
select ALTERA_SDRAM
+ select SPL_BOARD_INIT if SPL
config TARGET_SOCFPGA_CYCLONE5
bool
config TARGET_SOCFPGA_STRATIX10
bool
select ARMV8_MULTIENTRY
- select ARMV8_SPIN_TABLE
select ARMV8_SET_SMPEN
+ select ARMV8_SPIN_TABLE
choice
prompt "Altera SOCFPGA board select"
select PINCTRL
select PINCTRL_STM32
select RAM
- select STM32_SDRAM
select STM32_RCC
select STM32_RESET
+ select STM32_SDRAM
select STM32_SERIAL
select STM32_TIMER
select TIMER
select PINCTRL
select PINCTRL_STM32
select RAM
- select STM32_SDRAM
- select STM32_RCC
- select STM32_RESET
- select STM32_SERIAL
- select STM32_TIMER
- select TIMER
- select SUPPORT_SPL
select SPL
select SPL_BOARD_INIT
select SPL_CLK
select SPL_OF_CONTROL
select SPL_OF_LIBFDT
select SPL_OF_TRANSLATE
- imply SPL_OS_BOOT
select SPL_PINCTRL
select SPL_RAM
select SPL_SERIAL_SUPPORT
select SPL_SYS_MALLOC_SIMPLE
select SPL_TIMER
select SPL_XIP_SUPPORT
+ select STM32_RCC
+ select STM32_RESET
+ select STM32_SDRAM
+ select STM32_SERIAL
+ select STM32_TIMER
+ select SUPPORT_SPL
+ select TIMER
+ imply SPL_OS_BOOT
config STM32H7
bool "stm32h7 family"
select PINCTRL_STM32
select RAM
select REGMAP
- select STM32_SDRAM
select STM32_RCC
select STM32_RESET
+ select STM32_SDRAM
select STM32_SERIAL
select STM32_TIMER
select SYSCON
config TEGRA_COMMON
bool "Tegra common options"
+ select BINMAN
+ select BOARD_EARLY_INIT_F
select CLK
select DM
select DM_ETH
select DM_SPI
select DM_SPI_FLASH
select MISC
- select SPI
select OF_CONTROL
+ select SPI
select VIDCONSOLE_AS_LCD if DM_VIDEO
- select BOARD_EARLY_INIT_F
- select BINMAN
+ imply CMD_DM
imply CRC32_VERIFY
config TEGRA_NO_BPMP
config TEGRA210
bool "Tegra210 family"
- select TEGRA_GPIO
select TEGRA_ARMV8_COMMON
+ select TEGRA_GPIO
select TEGRA_NO_BPMP
config TEGRA186
{
#ifdef CONFIG_ARM64
return SZ_512M;
+#elif defined(CONFIG_ARMV7_SECURE_RESERVE_SIZE)
+ // BASE+SIZE might not == 4GB. If so, we want the carveout to cover
+ // from BASE to 4GB, not BASE to BASE+SIZE.
+ return (0 - CONFIG_ARMV7_SECURE_BASE);
#else
return 0;
#endif
#include <asm/io.h>
#include <asm/types.h>
-#include <asm/arch/flow.h>
+
#include <asm/arch/powergate.h>
#include <asm/arch/tegra.h>
return 0;
}
-static void tegra_powergate_ram_repair(void)
-{
-#ifdef CONFIG_TEGRA124
- struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE;
-
- /* Request RAM repair for cluster 0 and wait until complete */
- setbits_le32(&flow->ram_repair, RAM_REPAIR_REQ);
- while (!(readl(&flow->ram_repair) & RAM_REPAIR_STS))
- ;
-
- /* Same for cluster 1 */
- setbits_le32(&flow->ram_repair_cluster1, RAM_REPAIR_REQ);
- while (!(readl(&flow->ram_repair_cluster1) & RAM_REPAIR_STS))
- ;
-#endif
-}
-
int tegra_powergate_sequence_power_up(enum tegra_powergate id,
enum periph_id periph)
{
int err;
- tegra_powergate_ram_repair();
reset_set_enable(periph, 1);
err = tegra_powergate_power_on(id);
config TARGET_APALIS_TK1
bool "Toradex Apalis TK1 module"
+ select ARCH_SUPPORT_PSCI
select CPU_V7_HAS_NONSEC
select CPU_V7_HAS_VIRT
- select ARCH_SUPPORT_PSCI
config TARGET_JETSON_TK1
bool "NVIDIA Tegra124 Jetson TK1 board"
+ select ARCH_SUPPORT_PSCI
select BOARD_LATE_INIT
select CPU_V7_HAS_NONSEC
select CPU_V7_HAS_VIRT
- select ARCH_SUPPORT_PSCI
config TARGET_CEI_TK1_SOM
bool "Colorado Engineering Inc Tegra124 TK1-som board"
writel(reg, &clkrst->crc_rst_cpug_cmplx_clr);
}
+static void tegra124_ram_repair(void)
+{
+ struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE;
+ u32 ram_repair_timeout; /*usec*/
+ u32 val;
+
+ /*
+ * Request the Flow Controller perform RAM repair whenever it turns on
+ * a power rail that requires RAM repair.
+ */
+ clrbits_le32(&flow->ram_repair, RAM_REPAIR_BYPASS_EN);
+
+ /* Request SW trigerred RAM repair by setting req bit */
+ /* cluster 0 */
+ setbits_le32(&flow->ram_repair, RAM_REPAIR_REQ);
+ /* Wait for completion (status == 0) */
+ ram_repair_timeout = 500;
+ do {
+ udelay(1);
+ val = readl(&flow->ram_repair);
+ } while (!(val & RAM_REPAIR_STS) && ram_repair_timeout--);
+ if (!ram_repair_timeout)
+ debug("Ram Repair cluster0 failed\n");
+
+ /* cluster 1 */
+ setbits_le32(&flow->ram_repair_cluster1, RAM_REPAIR_REQ);
+ /* Wait for completion (status == 0) */
+ ram_repair_timeout = 500;
+ do {
+ udelay(1);
+ val = readl(&flow->ram_repair_cluster1);
+ } while (!(val & RAM_REPAIR_STS) && ram_repair_timeout--);
+
+ if (!ram_repair_timeout)
+ debug("Ram Repair cluster1 failed\n");
+}
+
/**
* Tegra124 requires some special clock initialization, including setting up
* the DVC I2C, turning on MSELECT and selecting the G CPU cluster
&pmc->pmc_pwrgate_timer_mult);
enable_cpu_power_rail();
+ powerup_cpus();
+ tegra124_ram_repair();
enable_cpu_clocks();
clock_enable_coresight(1);
- remove_cpu_resets();
writel(reset_vector, EXCEP_VECTOR_CPU_RESET_VECTOR);
- powerup_cpus();
+ remove_cpu_resets();
debug("%s exit, should continue @ reset_vector\n", __func__);
}
config ARCH_UNIPHIER_32BIT
bool
+ select ARCH_SUPPORT_PSCI
+ select ARMV7_NONSEC
select CPU_V7A
select CPU_V7_HAS_NONSEC
- select ARMV7_NONSEC
- select ARCH_SUPPORT_PSCI
choice
prompt "UniPhier SoC select"
bool "Enable UniPhier LD20 SoC support"
depends on ARCH_UNIPHIER_V8_MULTI
default y
+ select OF_BOARD_SETUP
config ARCH_UNIPHIER_PXS3
bool "Enable UniPhier PXs3 SoC support"
config CACHE_UNIPHIER
bool "Enable the UniPhier L2 cache controller"
depends on ARCH_UNIPHIER_32BIT
- select SYS_CACHE_SHIFT_7
default y
+ select SYS_CACHE_SHIFT_7
help
This option allows to use the UniPhier System Cache as L2 cache.
*(.__image_copy_start)
*(.vectors)
CPUDIR/start.o (.text*)
+ }
+
+ /* This needs to come before *(.text*) */
+ .__efi_runtime_start : {
+ *(.__efi_runtime_start)
+ }
+
+ .efi_runtime : {
+ *(.text.efi_runtime*)
+ *(.rodata.efi_runtime*)
+ *(.data.efi_runtime*)
+ }
+
+ .__efi_runtime_stop : {
+ *(.__efi_runtime_stop)
+ }
+
+ .text_rest :
+ {
*(.text*)
}
. = ALIGN(4);
- .__efi_runtime_start : {
- *(.__efi_runtime_start)
- }
-
- .efi_runtime : {
- *(efi_runtime_text)
- *(efi_runtime_data)
- }
-
- .__efi_runtime_stop : {
- *(.__efi_runtime_stop)
- }
-
.efi_runtime_rel_start :
{
*(.__efi_runtime_rel_start)
}
.efi_runtime_rel : {
- *(.relefi_runtime_text)
- *(.relefi_runtime_data)
+ *(.rel*.efi_runtime)
+ *(.rel*.efi_runtime.*)
}
.efi_runtime_rel_stop :
config TARGET_MICROBLAZE_GENERIC
bool "Support microblaze-generic"
select BOARD_LATE_INIT
- select SUPPORT_SPL
- select OF_CONTROL
select DM
select DM_SERIAL
+ select OF_CONTROL
+ select SUPPORT_SPL
select SYSRESET
+ imply CMD_DM
endchoice
config TARGET_QEMU_MIPS
bool "Support qemu-mips"
+ select ROM_EXCEPTION_VECTORS
select SUPPORTS_BIG_ENDIAN
- select SUPPORTS_LITTLE_ENDIAN
select SUPPORTS_CPU_MIPS32_R1
select SUPPORTS_CPU_MIPS32_R2
select SUPPORTS_CPU_MIPS64_R1
select SUPPORTS_CPU_MIPS64_R2
- select ROM_EXCEPTION_VECTORS
+ select SUPPORTS_LITTLE_ENDIAN
config TARGET_MALTA
bool "Support malta"
select DM_SERIAL
select DYNAMIC_IO_PORT_BASE
select MIPS_CM
+ select MIPS_L1_CACHE_SHIFT_6
select MIPS_L2_CACHE
select OF_CONTROL
select OF_ISA_BUS
+ select ROM_EXCEPTION_VECTORS
select SUPPORTS_BIG_ENDIAN
- select SUPPORTS_LITTLE_ENDIAN
select SUPPORTS_CPU_MIPS32_R1
select SUPPORTS_CPU_MIPS32_R2
select SUPPORTS_CPU_MIPS32_R6
select SUPPORTS_CPU_MIPS64_R1
select SUPPORTS_CPU_MIPS64_R2
select SUPPORTS_CPU_MIPS64_R6
+ select SUPPORTS_LITTLE_ENDIAN
select SWAP_IO_SPACE
- select MIPS_L1_CACHE_SHIFT_6
- select ROM_EXCEPTION_VECTORS
+ imply CMD_DM
config TARGET_VCT
bool "Support vct"
+ select ROM_EXCEPTION_VECTORS
select SUPPORTS_BIG_ENDIAN
select SUPPORTS_CPU_MIPS32_R1
select SUPPORTS_CPU_MIPS32_R2
select SYS_MIPS_CACHE_INIT_RAM_LOAD
- select ROM_EXCEPTION_VECTORS
config TARGET_DBAU1X00
bool "Support dbau1x00"
+ select MIPS_TUNE_4KC
+ select ROM_EXCEPTION_VECTORS
select SUPPORTS_BIG_ENDIAN
- select SUPPORTS_LITTLE_ENDIAN
select SUPPORTS_CPU_MIPS32_R1
select SUPPORTS_CPU_MIPS32_R2
+ select SUPPORTS_LITTLE_ENDIAN
select SYS_MIPS_CACHE_INIT_RAM_LOAD
- select ROM_EXCEPTION_VECTORS
- select MIPS_TUNE_4KC
config TARGET_PB1X00
bool "Support pb1x00"
- select SUPPORTS_LITTLE_ENDIAN
+ select MIPS_TUNE_4KC
+ select ROM_EXCEPTION_VECTORS
select SUPPORTS_CPU_MIPS32_R1
select SUPPORTS_CPU_MIPS32_R2
+ select SUPPORTS_LITTLE_ENDIAN
select SYS_MIPS_CACHE_INIT_RAM_LOAD
- select ROM_EXCEPTION_VECTORS
- select MIPS_TUNE_4KC
config ARCH_ATH79
bool "Support QCA/Atheros ath79"
- select OF_CONTROL
select DM
+ select OF_CONTROL
+ imply CMD_DM
config ARCH_BMIPS
bool "Support BMIPS SoCs"
- select OF_CONTROL
- select DM
select CLK
select CPU
+ select DM
+ select OF_CONTROL
select RAM
select SYSRESET
+ imply CMD_DM
config MACH_PIC32
bool "Support Microchip PIC32"
- select OF_CONTROL
select DM
+ select OF_CONTROL
+ imply CMD_DM
config TARGET_BOSTON
bool "Support Boston"
select DM
select DM_SERIAL
- select OF_CONTROL
select MIPS_CM
select MIPS_L1_CACHE_SHIFT_6
select MIPS_L2_CACHE
select OF_BOARD_SETUP
+ select OF_CONTROL
+ select ROM_EXCEPTION_VECTORS
select SUPPORTS_BIG_ENDIAN
- select SUPPORTS_LITTLE_ENDIAN
select SUPPORTS_CPU_MIPS32_R1
select SUPPORTS_CPU_MIPS32_R2
select SUPPORTS_CPU_MIPS32_R6
select SUPPORTS_CPU_MIPS64_R1
select SUPPORTS_CPU_MIPS64_R2
select SUPPORTS_CPU_MIPS64_R6
- select ROM_EXCEPTION_VECTORS
+ select SUPPORTS_LITTLE_ENDIAN
+ imply CMD_DM
config TARGET_XILFPGA
bool "Support Imagination Xilfpga"
- select OF_CONTROL
select DM
- select DM_SERIAL
- select DM_GPIO
select DM_ETH
- select SUPPORTS_LITTLE_ENDIAN
- select SUPPORTS_CPU_MIPS32_R1
- select SUPPORTS_CPU_MIPS32_R2
+ select DM_GPIO
+ select DM_SERIAL
select MIPS_L1_CACHE_SHIFT_4
+ select OF_CONTROL
select ROM_EXCEPTION_VECTORS
+ select SUPPORTS_CPU_MIPS32_R1
+ select SUPPORTS_CPU_MIPS32_R2
+ select SUPPORTS_LITTLE_ENDIAN
+ imply CMD_DM
help
This supports IMGTEC MIPSfpga platform
config SOC_AR933X
bool
+ select MIPS_TUNE_24KC
+ select ROM_EXCEPTION_VECTORS
select SUPPORTS_BIG_ENDIAN
select SUPPORTS_CPU_MIPS32_R1
select SUPPORTS_CPU_MIPS32_R2
- select ROM_EXCEPTION_VECTORS
- select MIPS_TUNE_24KC
help
This supports QCA/Atheros ar933x family SOCs.
config SOC_AR934X
bool
+ select MIPS_TUNE_74KC
select SUPPORTS_BIG_ENDIAN
select SUPPORTS_CPU_MIPS32_R1
select SUPPORTS_CPU_MIPS32_R2
- select MIPS_TUNE_74KC
help
This supports QCA/Atheros ar934x family SOCs.
config SOC_QCA953X
bool
+ select MIPS_TUNE_24KC
+ select ROM_EXCEPTION_VECTORS
select SUPPORTS_BIG_ENDIAN
select SUPPORTS_CPU_MIPS32_R1
select SUPPORTS_CPU_MIPS32_R2
- select ROM_EXCEPTION_VECTORS
- select MIPS_TUNE_24KC
help
This supports QCA/Atheros qca953x family SOCs.
config SOC_BMIPS_BCM3380
bool "BMIPS BCM3380 family"
+ select MIPS_L1_CACHE_SHIFT_4
+ select MIPS_TUNE_4KC
select SUPPORTS_BIG_ENDIAN
select SUPPORTS_CPU_MIPS32_R1
- select MIPS_TUNE_4KC
- select MIPS_L1_CACHE_SHIFT_4
select SWAP_IO_SPACE
select SYSRESET_WATCHDOG
help
config SOC_BMIPS_BCM6318
bool "BMIPS BCM6318 family"
+ select MIPS_L1_CACHE_SHIFT_4
+ select MIPS_TUNE_4KC
select SUPPORTS_BIG_ENDIAN
select SUPPORTS_CPU_MIPS32_R1
- select MIPS_TUNE_4KC
- select MIPS_L1_CACHE_SHIFT_4
select SWAP_IO_SPACE
select SYSRESET_SYSCON
help
config SOC_BMIPS_BCM6328
bool "BMIPS BCM6328 family"
+ select MIPS_L1_CACHE_SHIFT_4
+ select MIPS_TUNE_4KC
select SUPPORTS_BIG_ENDIAN
select SUPPORTS_CPU_MIPS32_R1
- select MIPS_TUNE_4KC
- select MIPS_L1_CACHE_SHIFT_4
select SWAP_IO_SPACE
select SYSRESET_SYSCON
help
config SOC_BMIPS_BCM6338
bool "BMIPS BCM6338 family"
+ select MIPS_L1_CACHE_SHIFT_4
+ select MIPS_TUNE_4KC
select SUPPORTS_BIG_ENDIAN
select SUPPORTS_CPU_MIPS32_R1
- select MIPS_TUNE_4KC
- select MIPS_L1_CACHE_SHIFT_4
select SWAP_IO_SPACE
select SYSRESET_SYSCON
help
config SOC_BMIPS_BCM6348
bool "BMIPS BCM6348 family"
+ select MIPS_L1_CACHE_SHIFT_4
+ select MIPS_TUNE_4KC
select SUPPORTS_BIG_ENDIAN
select SUPPORTS_CPU_MIPS32_R1
- select MIPS_TUNE_4KC
- select MIPS_L1_CACHE_SHIFT_4
select SWAP_IO_SPACE
select SYSRESET_WATCHDOG
help
config SOC_BMIPS_BCM6358
bool "BMIPS BCM6358 family"
+ select MIPS_L1_CACHE_SHIFT_4
+ select MIPS_TUNE_4KC
select SUPPORTS_BIG_ENDIAN
select SUPPORTS_CPU_MIPS32_R1
- select MIPS_TUNE_4KC
- select MIPS_L1_CACHE_SHIFT_4
select SWAP_IO_SPACE
select SYSRESET_SYSCON
help
config SOC_BMIPS_BCM6368
bool "BMIPS BCM6368 family"
+ select MIPS_L1_CACHE_SHIFT_4
+ select MIPS_TUNE_4KC
select SUPPORTS_BIG_ENDIAN
select SUPPORTS_CPU_MIPS32_R1
- select MIPS_TUNE_4KC
- select MIPS_L1_CACHE_SHIFT_4
select SWAP_IO_SPACE
select SYSRESET_SYSCON
help
config SOC_BMIPS_BCM6362
bool "BMIPS BCM6362 family"
+ select MIPS_L1_CACHE_SHIFT_4
+ select MIPS_TUNE_4KC
select SUPPORTS_BIG_ENDIAN
select SUPPORTS_CPU_MIPS32_R1
- select MIPS_TUNE_4KC
- select MIPS_L1_CACHE_SHIFT_4
select SWAP_IO_SPACE
select SYSRESET_SYSCON
help
config SOC_BMIPS_BCM63268
bool "BMIPS BCM63268 family"
+ select MIPS_L1_CACHE_SHIFT_4
+ select MIPS_TUNE_4KC
select SUPPORTS_BIG_ENDIAN
select SUPPORTS_CPU_MIPS32_R1
- select MIPS_TUNE_4KC
- select MIPS_L1_CACHE_SHIFT_4
select SWAP_IO_SPACE
select SYSRESET_SYSCON
help
config SOC_PIC32MZDA
bool "Microchip PIC32MZ[DA] family"
- select SUPPORTS_LITTLE_ENDIAN
+ select MIPS_L1_CACHE_SHIFT_4
+ select ROM_EXCEPTION_VECTORS
select SUPPORTS_CPU_MIPS32_R1
select SUPPORTS_CPU_MIPS32_R2
- select MIPS_L1_CACHE_SHIFT_4
+ select SUPPORTS_LITTLE_ENDIAN
select SYS_MIPS_CACHE_INIT_RAM_LOAD
- select ROM_EXCEPTION_VECTORS
help
This supports Microchip PIC32MZ[DA] family of microcontrollers.
select CREATE_ARCH_SYMLINK
select SYS_FSL_DDR
select SYS_FSL_DDR_BE
- imply USB_EHCI_HCD if USB
imply CMD_HASH
imply CMD_IRQ
+ imply USB_EHCI_HCD if USB
config MPC86xx
bool "MPC86xx"
config TARGET_MPC8313ERDB
bool "Support MPC8313ERDB"
- select SUPPORT_SPL
select BOARD_EARLY_INIT_F
+ select SUPPORT_SPL
config TARGET_MPC8315ERDB
bool "Support MPC8315ERDB"
config TARGET_MPC8349EMDS
bool "Support MPC8349EMDS"
+ select BOARD_EARLY_INIT_F
select SYS_FSL_DDR
- select SYS_FSL_HAS_DDR2
select SYS_FSL_DDR_BE
- select BOARD_EARLY_INIT_F
+ select SYS_FSL_HAS_DDR2
config TARGET_MPC8349ITX
bool "Support MPC8349ITX"
config TARGET_IDS8313
bool "Support ids8313"
select DM
+ imply CMD_DM
config TARGET_KM8360
bool "Support km8360"
.text :
{
arch/riscv/cpu/ax25/start.o (.text)
- *(.text)
+ }
+
+ /* This needs to come before *(.text*) */
+ .efi_runtime : {
+ __efi_runtime_start = .;
+ *(.text.efi_runtime*)
+ *(.rodata.efi_runtime*)
+ *(.data.efi_runtime*)
+ __efi_runtime_stop = .;
+ }
+
+ .text_rest :
+ {
+ *(.text*)
}
. = ALIGN(4);
. = ALIGN(4);
- .efi_runtime : {
- __efi_runtime_start = .;
- *(efi_runtime_text)
- *(efi_runtime_data)
- __efi_runtime_stop = .;
- }
-
.efi_runtime_rel : {
__efi_runtime_rel_start = .;
- *(.relaefi_runtime_text)
- *(.relaefi_runtime_data)
+ *(.rel*.efi_runtime)
+ *(.rel*.efi_runtime.*)
__efi_runtime_rel_stop = .;
}
PLATFORM_CPPFLAGS += -DCONFIG_ARCH_MAP_SYSMEM
PLATFORM_LIBS += -lrt
+LDFLAGS_FINAL += --gc-sections
+PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections
+
# Define this to avoid linking with SDL, which requires SDL libraries
# This can solve 'sdl-config: Command not found' errors
ifneq ($(NO_SDL),)
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (c) 2015 National Instruments
- *
- * (C) Copyright 2015
- * Joe Hershberger <joe.hershberger@ni.com>
+ * Copyright (c) 2015-2018 National Instruments
+ * Copyright (c) 2015-2018 Joe Hershberger <joe.hershberger@ni.com>
*/
#include <asm/eth-raw-os.h>
#include <linux/if_ether.h>
#include <linux/if_packet.h>
-static int _raw_packet_start(const char *ifname, unsigned char *ethmac,
- struct eth_sandbox_raw_priv *priv)
+struct sandbox_eth_raw_if_nameindex *sandbox_eth_raw_if_nameindex(void)
+{
+ return (struct sandbox_eth_raw_if_nameindex *)if_nameindex();
+}
+
+void sandbox_eth_raw_if_freenameindex(struct sandbox_eth_raw_if_nameindex *ptr)
+{
+ if_freenameindex((struct if_nameindex *)ptr);
+}
+
+int sandbox_eth_raw_os_is_local(const char *ifname)
+{
+ int fd = socket(AF_INET, SOCK_DGRAM, 0);
+ struct ifreq ifr;
+ int ret = 0;
+
+ if (fd < 0)
+ return -errno;
+ memset(&ifr, 0, sizeof(ifr));
+ strncpy(ifr.ifr_name, ifname, IFNAMSIZ);
+ ret = ioctl(fd, SIOCGIFFLAGS, &ifr);
+ if (ret < 0) {
+ ret = -errno;
+ goto out;
+ }
+ ret = !!(ifr.ifr_flags & IFF_LOOPBACK);
+out:
+ close(fd);
+ return ret;
+}
+
+int sandbox_eth_raw_os_idx_to_name(struct eth_sandbox_raw_priv *priv)
+{
+ if (!if_indextoname(priv->host_ifindex, priv->host_ifname))
+ return -errno;
+ return 0;
+}
+
+static int _raw_packet_start(struct eth_sandbox_raw_priv *priv,
+ unsigned char *ethmac)
{
struct sockaddr_ll *device;
struct packet_mreq mr;
int flags;
/* Prepare device struct */
+ priv->local_bind_sd = -1;
priv->device = malloc(sizeof(struct sockaddr_ll));
if (priv->device == NULL)
return -ENOMEM;
device = priv->device;
memset(device, 0, sizeof(struct sockaddr_ll));
- device->sll_ifindex = if_nametoindex(ifname);
+ device->sll_ifindex = if_nametoindex(priv->host_ifname);
+ priv->host_ifindex = device->sll_ifindex;
device->sll_family = AF_PACKET;
memcpy(device->sll_addr, ethmac, 6);
device->sll_halen = htons(6);
return -errno;
}
/* Bind to the specified interface */
- ret = setsockopt(priv->sd, SOL_SOCKET, SO_BINDTODEVICE, ifname,
- strlen(ifname) + 1);
+ ret = setsockopt(priv->sd, SOL_SOCKET, SO_BINDTODEVICE,
+ priv->host_ifname, strlen(priv->host_ifname) + 1);
if (ret < 0) {
- printf("Failed to bind to '%s': %d %s\n", ifname, errno,
- strerror(errno));
+ printf("Failed to bind to '%s': %d %s\n", priv->host_ifname,
+ errno, strerror(errno));
return -errno;
}
printf("Failed to set promiscuous mode: %d %s\n"
"Falling back to the old \"flags\" way...\n",
errno, strerror(errno));
- if (strlen(ifname) >= IFNAMSIZ) {
- printf("Interface name %s is too long.\n", ifname);
+ if (strlen(priv->host_ifname) >= IFNAMSIZ) {
+ printf("Interface name %s is too long.\n",
+ priv->host_ifname);
return -EINVAL;
}
- strncpy(ifr.ifr_name, ifname, IFNAMSIZ);
+ strncpy(ifr.ifr_name, priv->host_ifname, IFNAMSIZ);
if (ioctl(priv->sd, SIOCGIFFLAGS, &ifr) < 0) {
printf("Failed to read flags: %d %s\n", errno,
strerror(errno));
int one = 1;
/* Prepare device struct */
+ priv->local_bind_sd = -1;
+ priv->local_bind_udp_port = 0;
priv->device = malloc(sizeof(struct sockaddr_in));
if (priv->device == NULL)
return -ENOMEM;
strerror(errno));
return -errno;
}
- priv->local_bind_sd = -1;
- priv->local_bind_udp_port = 0;
return 0;
}
-int sandbox_eth_raw_os_start(const char *ifname, unsigned char *ethmac,
- struct eth_sandbox_raw_priv *priv)
+int sandbox_eth_raw_os_start(struct eth_sandbox_raw_priv *priv,
+ unsigned char *ethmac)
{
if (priv->local)
return _local_inet_start(priv);
else
- return _raw_packet_start(ifname, ethmac, priv);
+ return _raw_packet_start(priv, ethmac);
}
int sandbox_eth_raw_os_send(void *packet, int length,
int retval;
struct udphdr *udph = packet + sizeof(struct iphdr);
- if (!priv->sd || !priv->device)
+ if (priv->sd < 0 || !priv->device)
return -EINVAL;
/*
int retval;
int saddr_size;
- if (!priv->sd || !priv->device)
+ if (priv->sd < 0 || !priv->device)
return -EINVAL;
saddr_size = sizeof(struct sockaddr);
retval = recvfrom(priv->sd, packet, 1536, 0,
}
.efi_runtime : {
- *(efi_runtime_text)
- *(efi_runtime_data)
+ *(.text.efi_runtime*)
+ *(.rodata.efi_runtime*)
+ *(.data.efi_runtime*)
}
.__efi_runtime_stop : {
}
.efi_runtime_rel : {
- *(.relefi_runtime_text)
- *(.relefi_runtime_data)
+ *(.rel*.efi_runtime)
+ *(.rel*.efi_runtime.*)
}
.efi_runtime_rel_stop :
model = "sandbox";
aliases {
- eth5 = "/eth@90000000";
i2c0 = &i2c_0;
pci0 = &pci;
rtc0 = &rtc_0;
};
};
+ ethrawbus {
+ compatible = "sandbox,eth-raw-bus";
+ skip-localhost = <0>;
+ };
+
eth@10002000 {
compatible = "sandbox,eth";
reg = <0x10002000 0x1000>;
fake-host-hwaddr = [00 00 66 44 22 00];
};
- eth@80000000 {
- compatible = "sandbox,eth-raw";
- reg = <0x80000000 0x1000>;
- host-raw-interface = "eth0";
- };
-
- eth@90000000 {
- compatible = "sandbox,eth-raw";
- reg = <0x90000000 0x1000>;
- host-raw-interface = "lo";
- };
-
gpio_a: gpios@0 {
gpio-controller;
compatible = "sandbox,gpio";
model = "sandbox";
aliases {
- eth5 = "/eth@90000000";
i2c0 = &i2c_0;
pci0 = &pci;
rtc0 = &rtc_0;
};
};
+ ethrawbus {
+ compatible = "sandbox,eth-raw-bus";
+ skip-localhost = <1>;
+ };
+
eth@10002000 {
compatible = "sandbox,eth";
reg = <0x0 0x10002000 0x0 0x1000>;
fake-host-hwaddr = [00 00 66 44 22 00];
};
- eth@80000000 {
- compatible = "sandbox,eth-raw";
- reg = <0x0 0x80000000 0x0 0x1000>;
- host-raw-interface = "eth0";
- };
-
- eth@90000000 {
- compatible = "sandbox,eth-raw";
- reg = <0x0 0x90000000 0x0 0x1000>;
- host-raw-interface = "lo";
- };
-
gpio_a: gpios@0 {
gpio-controller;
compatible = "sandbox,gpio";
eth@10002000 {
compatible = "sandbox,eth";
reg = <0x10002000 0x1000>;
- fake-host-hwaddr = <0x00 0x00 0x66 0x44 0x22 0x00>;
+ fake-host-hwaddr = [00 00 66 44 22 00];
};
eth_5: eth@10003000 {
compatible = "sandbox,eth";
reg = <0x10003000 0x1000>;
- fake-host-hwaddr = <0x00 0x00 0x66 0x44 0x22 0x11>;
+ fake-host-hwaddr = [00 00 66 44 22 11];
};
eth_3: sbe5 {
compatible = "sandbox,eth";
reg = <0x10005000 0x1000>;
- fake-host-hwaddr = <0x00 0x00 0x66 0x44 0x22 0x33>;
+ fake-host-hwaddr = [00 00 66 44 22 33];
};
eth@10004000 {
compatible = "sandbox,eth";
reg = <0x10004000 0x1000>;
- fake-host-hwaddr = <0x00 0x00 0x66 0x44 0x22 0x22>;
+ fake-host-hwaddr = [00 00 66 44 22 22];
};
gpio_a: base-gpios {
#ifndef __ETH_RAW_OS_H
#define __ETH_RAW_OS_H
+#define IFNAMSIZ 16
+
/**
* struct eth_sandbox_raw_priv - raw socket session
*
* sd: socket descriptor - the open socket during a session
+ * host_ifname: interface name on the host to use for sending our packets
+ * host_ifindex: interface index number on the host
* device: struct sockaddr_ll - the host interface packets move to/from
* local: 1 or 0 to select the local interface ('lo') or not
* local_bindsd: socket descriptor to prevent the kernel from sending
*/
struct eth_sandbox_raw_priv {
int sd;
+ char host_ifname[IFNAMSIZ];
+ unsigned int host_ifindex;
void *device;
int local;
int local_bind_sd;
unsigned short local_bind_udp_port;
};
-int sandbox_eth_raw_os_start(const char *ifname, unsigned char *ethmac,
- struct eth_sandbox_raw_priv *priv);
+/* A struct to mimic if_nameindex but that does not depend on Linux headers */
+struct sandbox_eth_raw_if_nameindex {
+ unsigned int if_index; /* Index of interface (1, 2, ...) */
+ char *if_name; /* Null-terminated name ("eth0", etc.) */
+};
+
+/* Enumerate host network interfaces */
+struct sandbox_eth_raw_if_nameindex *sandbox_eth_raw_if_nameindex(void);
+/* Free the data structure of enumerated network interfaces */
+void sandbox_eth_raw_if_freenameindex(struct sandbox_eth_raw_if_nameindex *ptr);
+
+/*
+ * Check if the interface named "ifname" is a localhost interface or not.
+ * ifname - the interface name on the host to check
+ *
+ * returns - 0 if real interface, 1 if local, negative if error
+ */
+int sandbox_eth_raw_os_is_local(const char *ifname);
+
+/*
+ * Look up the name of the interface based on the ifindex populated in priv.
+ *
+ * Overwrite the host_ifname member in priv based on looking up host_ifindex
+ *
+ * returns - 0 if success, negative if error
+ */
+int sandbox_eth_raw_os_idx_to_name(struct eth_sandbox_raw_priv *priv);
+
+int sandbox_eth_raw_os_start(struct eth_sandbox_raw_priv *priv,
+ unsigned char *ethmac);
int sandbox_eth_raw_os_send(void *packet, int length,
struct eth_sandbox_raw_priv *priv);
int sandbox_eth_raw_os_recv(void *packet, int *length,
ifeq ($(IS_32BIT),y)
PLATFORM_CPPFLAGS += -march=i386 -m32
+# TODO: These break on x86_64; need to debug further
+PLATFORM_RELFLAGS += -fdata-sections
else
PLATFORM_CPPFLAGS += $(if $(CONFIG_SPL_BUILD),,-fpic) -fno-common -m64
endif
#include <generated/generic-asm-offsets.h>
#include <generated/asm-offsets.h>
-.section .text
+.section .text.start
.code32
.globl _start
.type _start, @function
#include <config.h>
-.section .text
+.section .text.start
.code64
.globl _start
.type _start, @function
. = CONFIG_SYS_TEXT_BASE; /* Location of bootcode in flash */
__text_start = .;
+
+ .text.start : { *(.text.start); }
+
+ .__efi_runtime_start : {
+ *(.__efi_runtime_start)
+ }
+
+ .efi_runtime : {
+ *(.text.efi_runtime*)
+ *(.rodata.efi_runtime*)
+ *(.data.efi_runtime*)
+ }
+
+ .__efi_runtime_stop : {
+ *(.__efi_runtime_stop)
+ }
+
.text : { *(.text*); }
. = ALIGN(4);
}
. = ALIGN(4);
- .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+ .rodata : {
+ *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+ KEEP(*(.rodata.efi.init));
+ }
. = ALIGN(4);
.data : { *(.data*) }
. = ALIGN(4);
.got : { *(.got*) }
+ .efi_runtime_rel_start :
+ {
+ *(.__efi_runtime_rel_start)
+ }
+
+ .efi_runtime_rel : {
+ *(.rel*.efi_runtime)
+ *(.rel*.efi_runtime.*)
+ }
+
+ .efi_runtime_rel_stop :
+ {
+ *(.__efi_runtime_rel_stop)
+ }
+
. = ALIGN(4);
__data_end = .;
__init_end = .;
. = CONFIG_SYS_TEXT_BASE; /* Location of bootcode in flash */
__text_start = .;
+
+ .text.start : { *(.text.start); }
+
+ .__efi_runtime_start : {
+ *(.__efi_runtime_start)
+ }
+
+ .efi_runtime : {
+ *(.text.efi_runtime*)
+ *(.rodata.efi_runtime*)
+ *(.data.efi_runtime*)
+ }
+
+ .__efi_runtime_stop : {
+ *(.__efi_runtime_stop)
+ }
+
.text : { *(.text*); }
. = ALIGN(4);
. = ALIGN(4);
- .__efi_runtime_start : {
- *(.__efi_runtime_start)
- }
-
- .efi_runtime : {
- *(efi_runtime_text)
- *(efi_runtime_data)
- }
-
- .__efi_runtime_stop : {
- *(.__efi_runtime_stop)
- }
-
.efi_runtime_rel_start :
{
*(.__efi_runtime_rel_start)
}
.efi_runtime_rel : {
- *(.relefi_runtime_text)
- *(.relefi_runtime_data)
+ *(.rel*.efi_runtime)
+ *(.rel*.efi_runtime.*)
}
.efi_runtime_rel_stop :
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Brought in from Linux 4.1, removed things not useful to U-Boot.
- * The definitions perhaps came from the GNU Library which is GPL.
- */
-
-#ifndef _ASM_X86_ELF_H
-#define _ASM_X86_ELF_H
-
-/* ELF register definitions */
-#define R_386_NONE 0
-#define R_386_32 1
-#define R_386_PC32 2
-#define R_386_GOT32 3
-#define R_386_PLT32 4
-#define R_386_COPY 5
-#define R_386_GLOB_DAT 6
-#define R_386_JMP_SLOT 7
-#define R_386_RELATIVE 8
-#define R_386_GOTOFF 9
-#define R_386_GOTPC 10
-#define R_386_NUM 11
-
-/* x86-64 relocation types */
-#define R_X86_64_NONE 0 /* No reloc */
-#define R_X86_64_64 1 /* Direct 64 bit */
-#define R_X86_64_PC32 2 /* PC relative 32 bit signed */
-#define R_X86_64_GOT32 3 /* 32 bit GOT entry */
-#define R_X86_64_PLT32 4 /* 32 bit PLT address */
-#define R_X86_64_COPY 5 /* Copy symbol at runtime */
-#define R_X86_64_GLOB_DAT 6 /* Create GOT entry */
-#define R_X86_64_JUMP_SLOT 7 /* Create PLT entry */
-#define R_X86_64_RELATIVE 8 /* Adjust by program base */
-/* 32 bit signed pc relative offset to GOT */
-#define R_X86_64_GOTPCREL 9
-#define R_X86_64_32 10 /* Direct 32 bit zero extended */
-#define R_X86_64_32S 11 /* Direct 32 bit sign extended */
-#define R_X86_64_16 12 /* Direct 16 bit zero extended */
-#define R_X86_64_PC16 13 /* 16 bit sign extended pc relative */
-#define R_X86_64_8 14 /* Direct 8 bit sign extended */
-#define R_X86_64_PC8 15 /* 8 bit sign extended pc relative */
-
-#define R_X86_64_NUM 16
-
-#endif
#include <common.h>
#include <efi.h>
#include <elf.h>
-#include <asm/elf.h>
efi_status_t EFIAPI _relocate(long ldbase, Elf32_Dyn *dyn)
{
#include <common.h>
#include <efi.h>
#include <elf.h>
-#include <asm/elf.h>
efi_status_t EFIAPI _relocate(long ldbase, Elf64_Dyn *dyn)
{
-OPENRD BOARD
-
M: Albert ARIBAUD <albert-u-boot@aribaud.net>
-S: Maintained
+OPENRD / OPENRD_CLIENT BOARD
+
#M: Albert ARIBAUD <albert-u-boot@aribaud.net>
+S: Orphaned (Since 2018-09)
F: board/Marvell/openrd/
F: include/configs/openrd.h
F: configs/openrd_base_defconfig
-
-OPENRD_CLIENT BOARD
-M: Albert ARIBAUD <albert-u-boot@aribaud.net>
-S: Maintained
F: configs/openrd_client_defconfig
F: configs/openrd_ultimate_defconfig
F: board/freescale/ls1046ardb/ls1046ardb.c
F: include/configs/ls1046ardb.h
F: configs/ls1046ardb_qspi_defconfig
+F: configs/ls1046ardb_qspi_spl_defconfig
F: configs/ls1046ardb_sdcard_defconfig
F: configs/ls1046ardb_emmc_defconfig
--- /dev/null
+#QSPI clk
+0957015c 40100000
+#Configure Scratch register
+09570600 00000000
+09570604 10000000
+#Disable CCI barrier tranaction
+09570178 0000e010
+09180000 00000008
+#USB PHY frequency sel
+09570418 0000009e
+0957041c 0000009e
+09570420 0000009e
+#Serdes SATA
+09eb1300 80104e20
+09eb08dc 00502880
+#PEX gen3 link
+09570158 00000300
+89400890 01048000
+89500890 01048000
+89600890 01048000
+#Alt base register
+09570158 00001000
+#flush PBI data
+096100c0 000fffff
+#Change endianness
+09550000 000f400c
--- /dev/null
+#PBL preamble and RCW header
+aa55aa55 01ee0100
+# RCW
+0c150010 0e000000 00000000 00000000
+11335559 40005012 40025000 c1000000
+00000000 00000000 00000000 00238800
+20124000 00003101 00000096 00000001
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2017 NXP Semiconductors
* Copyright 2015 Freescale Semiconductor
+ * Copyright 2017 NXP
*/
#include <common.h>
#include <malloc.h>
*(.__image_copy_start)
board/qualcomm/dragonboard410c/head.o (.text*)
CPUDIR/start.o (.text*)
+ }
+
+ /* This needs to come before *(.text*) */
+ .efi_runtime : {
+ __efi_runtime_start = .;
+ *(.text.efi_runtime*)
+ *(.rodata.efi_runtime*)
+ *(.data.efi_runtime*)
+ __efi_runtime_stop = .;
+ }
+
+ .text_rest :
+ {
*(.text*)
}
.efi_runtime_rel : {
__efi_runtime_rel_start = .;
- *(.relaefi_runtime_text)
- *(.relaefi_runtime_data)
+ *(.rel*.efi_runtime)
+ *(.rel*.efi_runtime.*)
__efi_runtime_rel_stop = .;
}
*(.__image_copy_start)
board/qualcomm/dragonboard820c/head.o (.text*)
CPUDIR/start.o (.text*)
+ }
+
+ /* This needs to come before *(.text*) */
+ .efi_runtime : {
+ __efi_runtime_start = .;
+ *(.text.efi_runtime*)
+ *(.rodata.efi_runtime*)
+ *(.data.efi_runtime*)
+ __efi_runtime_stop = .;
+ }
+
+ .text_rest :
+ {
*(.text*)
}
. = ALIGN(8);
- .efi_runtime : {
- __efi_runtime_start = .;
- *(efi_runtime_text)
- *(efi_runtime_data)
- __efi_runtime_stop = .;
- }
-
.efi_runtime_rel : {
__efi_runtime_rel_start = .;
- *(.relaefi_runtime_text)
- *(.relaefi_runtime_data)
+ *(.rel*.efi_runtime)
+ *(.rel*.efi_runtime.*)
__efi_runtime_rel_stop = .;
}
F: board/technexion/pico-imx7d/
F: include/configs/pico-imx7d.h
F: configs/pico-imx7d_defconfig
+
+Technexion PICO-PI-IMX7
+M: Otavio Salvador <otavio@ossystems.com.br>
+S: Maintained
+F: configs/pico-pi-imx7d_defconfig
*(.vectors)
CPUDIR/start.o (.text*)
board/ti/am335x/built-in.o (.text*)
+ }
+
+ /* This needs to come before *(.text*) */
+ .__efi_runtime_start : {
+ *(.__efi_runtime_start)
+ }
+
+ .efi_runtime : {
+ *(.text.efi_runtime*)
+ *(.rodata.efi_runtime*)
+ *(.data.efi_runtime*)
+ }
+
+ .__efi_runtime_stop : {
+ *(.__efi_runtime_stop)
+ }
+
+ .text_rest :
+ {
*(.text*)
}
. = ALIGN(4);
- .__efi_runtime_start : {
- *(.__efi_runtime_start)
- }
-
- .efi_runtime : {
- *(efi_runtime_text)
- *(efi_runtime_data)
- }
-
- .__efi_runtime_stop : {
- *(.__efi_runtime_stop)
- }
-
.efi_runtime_rel_start :
{
*(.__efi_runtime_rel_start)
}
.efi_runtime_rel : {
- *(.relefi_runtime_text)
- *(.relefi_runtime_data)
+ *(.rel*.efi_runtime)
+ *(.rel*.efi_runtime.*)
}
.efi_runtime_rel_stop :
config CMD_CONFIG
bool "config"
- select BUILD_BIN2C
default SANDBOX
+ select BUILD_BIN2C
help
Print ".config" contents.
config CMD_CRC32
bool "crc32"
- select HASH
default y
+ select HASH
help
Compute CRC32.
config CMD_DM
bool "dm - Access to driver model information"
depends on DM
- default y
help
Provides access to driver model data structures and information,
such as a list of devices, list of uclasses and the state of each
config CMD_GPT
bool "GPT (GUID Partition Table) command"
- select PARTITION_UUIDS
select EFI_PARTITION
select HAVE_BLOCK_DEVICE
+ select PARTITION_UUIDS
imply RANDOM_UUID
help
Enable the 'gpt' command to ready and write GPT style partition
config CMD_PART
bool "part"
- select PARTITION_UUIDS
select HAVE_BLOCK_DEVICE
+ select PARTITION_UUIDS
help
Read and display information about the partition table on
various media.
help
Enables the command "sdp" which is used to have U-Boot emulating the
Serial Download Protocol (SDP) via USB.
+
config CMD_ROCKUSB
bool "rockusb"
depends on USB_FUNCTION_ROCKUSB
help
- Rockusb protocol is widely used by Rockchip SoC based devices. It can
+ Rockusb protocol is widely used by Rockchip SoC based devices. It can
read/write info, image to/from devices. This enable rockusb command
support to communication with rockusb device. for more detail about
this command, please read doc/README.rockusb.
the original data.
Sub-commands:
- blob enc - encapsulating data as a cryptgraphic blob
+ blob enc - encapsulating data as a cryptgraphic blob
blob dec - decapsulating cryptgraphic blob to get the data
Syntax:
config CMD_TPM_V2
bool
+ select CMD_LOG
config CMD_TPM
bool "Enable the 'tpm' command"
config CMD_UBI
tristate "Enable UBI - Unsorted block images commands"
+ default y if NAND_SUNXI
+ select CMD_MTDPARTS
select CRC32
select MTD_UBI
- select CMD_MTDPARTS
- default y if NAND_SUNXI
help
UBI is a software layer above MTD layer which admits use of LVM-like
logical volumes on top of MTD devices, hides some complexities of
config CMD_UBIFS
tristate "Enable UBIFS - Unsorted block images filesystem commands"
depends on CMD_UBI
+ default y if CMD_UBI
select CRC32
select LZO
- default y if CMD_UBI
help
UBIFS is a file system for flash devices which works on top of UBI.
#include <errno.h>
#include <linux/libfdt.h>
#include <linux/libfdt_env.h>
+#include <mapmem.h>
#include <memalign.h>
#include <asm/global_data.h>
#include <asm-generic/sections.h>
#include <asm-generic/unaligned.h>
#include <linux/linkage.h>
+#ifdef CONFIG_ARMV7_NONSEC
+#include <asm/armv7.h>
+#include <asm/secure.h>
+#endif
+
DECLARE_GLOBAL_DATA_PTR;
#define OBJ_LIST_NOT_INITIALIZED 1
if (efi_obj_list_initialized != OBJ_LIST_NOT_INITIALIZED)
return efi_obj_list_initialized;
+ /* Initialize system table */
+ ret = efi_initialize_system_table();
+ if (ret != EFI_SUCCESS)
+ goto out;
+
/* Initialize EFI driver uclass */
ret = efi_driver_init();
if (ret != EFI_SUCCESS)
ret = efi_reset_system_init();
if (ret != EFI_SUCCESS)
goto out;
- ret = efi_get_time_init();
- if (ret != EFI_SUCCESS)
- goto out;
out:
efi_obj_list_initialized = ret;
fdt_ram_start = ram_start;
}
- /* Give us at least 4kb breathing room */
- fdt_size = ALIGN(fdt_size + 4096, EFI_PAGE_SIZE);
+ /*
+ * Give us at least 4KB of breathing room in case the device tree needs
+ * to be expanded later. Round up to the nearest EFI page boundary.
+ */
+ fdt_size += 4096;
+ fdt_size = ALIGN(fdt_size + EFI_PAGE_SIZE - 1, EFI_PAGE_SIZE);
fdt_pages = fdt_size >> EFI_PAGE_SHIFT;
/* Safe fdt location is at 128MB */
}
#endif
-/* Carve out DT reserved memory ranges */
-static efi_status_t efi_carve_out_dt_rsv(void *fdt)
+#ifdef CONFIG_ARMV7_NONSEC
+static bool is_nonsec;
+
+static efi_status_t efi_run_in_hyp(EFIAPI efi_status_t (*entry)(
+ efi_handle_t image_handle, struct efi_system_table *st),
+ efi_handle_t image_handle, struct efi_system_table *st)
+{
+ /* Enable caches again */
+ dcache_enable();
+
+ is_nonsec = true;
+
+ return efi_do_enter(image_handle, st, entry);
+}
+#endif
+
+/*
+ * efi_carve_out_dt_rsv() - Carve out DT reserved memory ranges
+ *
+ * The mem_rsv entries of the FDT are added to the memory map. Any failures are
+ * ignored because this is not critical and we would rather continue to try to
+ * boot.
+ *
+ * @fdt: Pointer to device tree
+ */
+static void efi_carve_out_dt_rsv(void *fdt)
{
int nr_rsv, i;
uint64_t addr, size, pages;
continue;
pages = ALIGN(size, EFI_PAGE_SIZE) >> EFI_PAGE_SHIFT;
- efi_add_memory_map(addr, pages, EFI_RESERVED_MEMORY_TYPE,
- false);
+ if (!efi_add_memory_map(addr, pages, EFI_RESERVED_MEMORY_TYPE,
+ false))
+ printf("FDT memrsv map %d: Failed to add to map\n", i);
}
-
- return EFI_SUCCESS;
}
static efi_status_t efi_install_fdt(void *fdt)
return EFI_LOAD_ERROR;
}
- if (efi_carve_out_dt_rsv(fdt) != EFI_SUCCESS) {
- printf("ERROR: failed to carve out memory\n");
- return EFI_LOAD_ERROR;
- }
+ efi_carve_out_dt_rsv(fdt);
/* Link to it in the efi tables */
ret = efi_install_configuration_table(&efi_guid_fdt, fdt);
}
#endif
+#ifdef CONFIG_ARMV7_NONSEC
+ if (armv7_boot_nonsec() && !is_nonsec) {
+ dcache_disable(); /* flush cache before switch to HYP */
+
+ armv7_init_nonsec();
+ secure_ram_addr(_do_nonsec_entry)(
+ efi_run_in_hyp,
+ (uintptr_t)entry,
+ (uintptr_t)loaded_image_info_obj.handle,
+ (uintptr_t)&systab);
+
+ /* Should never reach here, efi exits with longjmp */
+ while (1) { }
+ }
+#endif
+
ret = efi_do_enter(loaded_image_info_obj.handle, &systab, entry);
exit:
unsigned long addr;
char *saddr;
efi_status_t r;
- void *fdt_addr;
+ unsigned long fdt_addr;
+ void *fdt;
/* Allow unaligned memory access */
allow_unaligned();
return CMD_RET_USAGE;
if (argc > 2) {
- fdt_addr = (void *)simple_strtoul(argv[2], NULL, 16);
+ fdt_addr = simple_strtoul(argv[2], NULL, 16);
if (!fdt_addr && *argv[2] != '0')
return CMD_RET_USAGE;
/* Install device tree */
- r = efi_install_fdt(fdt_addr);
+ fdt = map_sysmem(fdt_addr, 0);
+ r = efi_install_fdt(fdt);
if (r != EFI_SUCCESS) {
printf("ERROR: failed to install device tree\n");
return CMD_RET_FAILURE;
addr = simple_strtoul(saddr, NULL, 16);
else
addr = CONFIG_SYS_LOAD_ADDR;
- memcpy((char *)addr, __efi_helloworld_begin, size);
+ memcpy(map_sysmem(addr, size), __efi_helloworld_begin, size);
} else
#endif
#ifdef CONFIG_CMD_BOOTEFI_SELFTEST
}
printf("## Starting EFI application at %08lx ...\n", addr);
- r = do_bootefi_exec((void *)addr, bootefi_device_path,
+ r = do_bootefi_exec(map_sysmem(addr, 0), bootefi_device_path,
bootefi_image_path);
printf("## Application terminated, r = %lu\n",
r & ~EFI_ERROR_MASK);
switch (argc) {
case 1:
+ /* refresh bootfile name from env */
+ copy_filename(net_boot_file_name, env_get("bootfile"),
+ sizeof(net_boot_file_name));
break;
case 2: /*
addr = simple_strtoul(argv[1], &end, 16);
if (end == (argv[1] + strlen(argv[1]))) {
load_addr = addr;
+ /* refresh bootfile name from env */
+ copy_filename(net_boot_file_name, env_get("bootfile"),
+ sizeof(net_boot_file_name));
} else {
net_boot_file_name_explicit = true;
copy_filename(net_boot_file_name, argv[1],
int do_tpm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
cmd_tbl_t *tpm_commands, *cmd;
+ struct tpm_chip_priv *priv;
+ struct udevice *dev;
unsigned int size;
+ int ret;
if (argc < 2)
return CMD_RET_USAGE;
- tpm_commands = get_tpm_commands(&size);
+ ret = get_tpm(&dev);
+ if (ret)
+ return ret;
+
+ priv = dev_get_uclass_priv(dev);
+
+ /* Below getters return NULL if the desired stack is not built */
+ switch (priv->version) {
+ case TPM_V1:
+ tpm_commands = get_tpm1_commands(&size);
+ break;
+ case TPM_V2:
+ tpm_commands = get_tpm2_commands(&size);
+ break;
+ default:
+ tpm_commands = NULL;
+ }
+
+ if (!tpm_commands)
+ return CMD_RET_USAGE;
cmd = find_cmd_tbl(argv[1], tpm_commands, size);
if (!cmd)
#endif /* CONFIG_TPM_LIST_RESOURCES */
};
-cmd_tbl_t *get_tpm_commands(unsigned int *size)
+cmd_tbl_t *get_tpm1_commands(unsigned int *size)
{
*size = ARRAY_SIZE(tpm1_commands);
do_tpm_pcr_setauthvalue, "", ""),
};
-cmd_tbl_t *get_tpm_commands(unsigned int *size)
+cmd_tbl_t *get_tpm2_commands(unsigned int *size)
{
*size = ARRAY_SIZE(tpm2_commands);
return tpm2_commands;
}
-U_BOOT_CMD(tpm, CONFIG_SYS_MAXARGS, 1, do_tpm, "Issue a TPMv2.x command",
+U_BOOT_CMD(tpm2, CONFIG_SYS_MAXARGS, 1, do_tpm, "Issue a TPMv2.x command",
"<command> [<arguments>]\n"
"\n"
"info\n"
config LOG
bool "Enable logging support"
- select DM
+ depends on DM
help
This enables support for logging of status and debug messages. These
can be displayed on the console, recorded in a memory buffer, or
{
int i, ret;
struct stdio_dev *dev;
+ int prev;
- disable_ctrlc(1);
+ prev = disable_ctrlc(1);
for (i = 0; i < cd_count[file]; i++) {
dev = console_devices[file][i];
if (dev->tstc != NULL) {
ret = dev->tstc(dev);
if (ret > 0) {
tstcdev = dev;
- disable_ctrlc(0);
+ disable_ctrlc(prev);
return ret;
}
}
}
- disable_ctrlc(0);
+ disable_ctrlc(prev);
return 0;
}
static int ctrlc_was_pressed = 0;
int ctrlc(void)
{
-#ifndef CONFIG_SANDBOX
if (!ctrlc_disabled && gd->have_console) {
if (tstc()) {
switch (getc()) {
}
}
}
-#endif
return 0;
}
return p - (char *)buf;
}
-#ifdef CONFIG_NR_DRAM_BANKS
-#define MEMORY_BANKS_MAX CONFIG_NR_DRAM_BANKS
-#else
#define MEMORY_BANKS_MAX 4
-#endif
int fdt_fixup_memory_banks(void *blob, u64 start[], u64 size[], int banks)
{
int err, nodeoffset;
endif # SPL_OS_BOOT
+config SPL_PAYLOAD
+ string "SPL payload"
+ default "tpl/u-boot-with-tpl.bin" if TPL
+ default "u-boot.bin"
+ help
+ Payload for SPL boot. For backward compability, default to
+ u-boot.bin, i.e. RAW image without any header. In case of
+ TPL, tpl/u-boot-with-tpl.bin. For new boards, suggest to
+ use u-boot.img.
+
config SPL_PCI_SUPPORT
bool "Support PCI drivers"
help
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
-# CONFIG_BLK is not set
+CONFIG_BLK=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_FSL_PFE=y
CONFIG_DM_ETH=y
CONFIG_SYS_NS16550=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
+CONFIG_DM_SCSI=y
+CONFIG_SATA_CEVA=y
+CONFIG_SCSI=y
+CONFIG_AHCI=y
# CONFIG_MMC is not set
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_FSL_PFE=y
CONFIG_DM_ETH=y
CONFIG_E1000=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SCSI_AHCI=y
-# CONFIG_BLK is not set
+CONFIG_BLK=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_FSL_PFE=y
CONFIG_DM_ETH=y
CONFIG_E1000=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
+CONFIG_DM_SCSI=y
+CONFIG_SATA_CEVA=y
+CONFIG_SCSI_AHCI=y
+CONFIG_SCSI=y
+CONFIG_AHCI=y
CONFIG_OF_CONTROL=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
-# CONFIG_BLK is not set
+CONFIG_BLK=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_PCI=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
CONFIG_RSA_SOFTWARE_EXP=y
+CONFIG_DM_SCSI=y
+CONFIG_SATA_CEVA=y
+CONFIG_SCSI_AHCI=y
+CONFIG_SCSI=y
+CONFIG_AHCI=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
-# CONFIG_BLK is not set
+CONFIG_BLK=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_FSL_PFE=y
CONFIG_DM_ETH=y
CONFIG_E1000=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
+CONFIG_DM_SCSI=y
+CONFIG_SATA_CEVA=y
+CONFIG_SCSI_AHCI=y
+CONFIG_SCSI=y
+CONFIG_AHCI=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_FSL_LS_PPA=y
-CONFIG_SPL_FSL_LS_PPA=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_FSL_CAAM=y
CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_ARM=y
CONFIG_TARGET_LS1046AQDS=y
CONFIG_SYS_TEXT_BASE=0x82000000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_FSL_LS_PPA=y
+CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_ARM=y
CONFIG_TARGET_LS1046AQDS=y
CONFIG_SYS_TEXT_BASE=0x82000000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_FSL_LS_PPA=y
+CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMINFO=y
CONFIG_FSL_CAAM=y
CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_ARM=y
CONFIG_TARGET_LS1046ARDB=y
CONFIG_SYS_TEXT_BASE=0x82000000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_FSL_LS_PPA=y
+CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_DM=y
CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_FSL_CAAM=y
CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_TARGET_LS1046ARDB=y
+CONFIG_SYS_TEXT_BASE=0x82000000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_FSL_LS_PPA=y
+CONFIG_SPL_FSL_LS_PPA=y
+CONFIG_QSPI_AHB_INIT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb"
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_QSPI_BOOT=y
+CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.quadspi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_SPL_NOR_SUPPORT=y
+CONFIG_SPL_OS_BOOT=y
+CONFIG_SYS_OS_BASE=0x40980000
+CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_CMD_SPL=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_CACHE=y
+CONFIG_MP=y
+CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.quadspi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_SPL_ENV_IS_NOWHERE=y
+CONFIG_DM=y
+CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
+CONFIG_SPI_FLASH=y
+CONFIG_PHYLIB=y
+CONFIG_NETDEVICES=y
+CONFIG_PHY_GIGE=y
+CONFIG_E1000=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_QSPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_STORAGE=y
+CONFIG_SPL_GZIP=y
CONFIG_ARM=y
CONFIG_TARGET_LS1046ARDB=y
CONFIG_SYS_TEXT_BASE=0x82000000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SECURE_BOOT=y
CONFIG_FSL_LS_PPA=y
+CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.quadspi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_SPL_CRYPTO_SUPPORT=y
CONFIG_SPL_HASH_SUPPORT=y
CONFIG_CMD_GPT=y
CONFIG_ARM=y
CONFIG_TARGET_LS1046ARDB=y
CONFIG_SYS_TEXT_BASE=0x82000000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_FSL_LS_PPA=y
+CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_PCI=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_PCI=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_PCI=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_PCI=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_PCI=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_PCI=y
CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_PHYLIB=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_PHYLIB=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_SPL_OF_PLATDATA=y
# CONFIG_ENV_IS_IN_FAT is not set
CONFIG_ENV_IS_IN_NAND=y
-# CONFIG_BLK is not set
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x82000000
CONFIG_DM_I2C=y
CONFIG_USB_MUSB_GADGET=y
CONFIG_USB_MUSB_OMAP2PLUS=y
CONFIG_TWL4030_USB=y
-CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="TI"
CONFIG_USB_GADGET_VENDOR_NUM=0x0451
CONFIG_TIMER_EARLY=y
CONFIG_SANDBOX_TIMER=y
CONFIG_TPM_TIS_SANDBOX=y
+CONFIG_TPM2_TIS_SANDBOX=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EMUL=y
CONFIG_FS_CRAMFS=y
CONFIG_CMD_DHRYSTONE=y
CONFIG_TPM=y
+CONFIG_TPM_V1=y
+CONFIG_TPM_V2=y
CONFIG_LZ4=y
CONFIG_ERRNO_STR=y
CONFIG_OF_LIBFDT_OVERLAY=y
* persistence
* runtime support
-* support bootefi booting ARMv7 in non-secure mode (CONFIG_ARMV7_NONSEC=y)
-
## Links
* [1](http://uefi.org/specifications)
allocate it yourself in ofdata_to_platdata(). Note that it is preferable
to do all the device tree decoding in ofdata_to_platdata() rather than
in probe(). (Apart from the ugliness of mixing configuration and run-time
- data, one day it is possible that U-Boot will cache platformat data for
+ data, one day it is possible that U-Boot will cache platform data for
devices which are regularly de/activated).
h. The device's probe() method is called. This should do anything that
alias angelo_ts Angelo Dureghello <angelo@sysam.it>
alias bmeng Bin Meng <bmeng.cn@gmail.com>
alias danielschwierzeck Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
-alias dinh Dinh Nguyen <dinguyen@kernel.org>
+alias dinh Dinh Nguyen <dinguyen@kernel.org>
alias hs Heiko Schocher <hs@denx.de>
alias iwamatsu Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
alias jaehoon Jaehoon Chung <jh80.chung@samsung.com>
alias mariosix Mario Six <mario.six@gdsys.cc>
alias masahiro Masahiro Yamada <yamada.masahiro@socionext.com>
alias mateusz Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
-alias maxime Maxime Ripard <maxime.ripard@free-electrons.com>
+alias maxime Maxime Ripard <maxime.ripard@free-electrons.com>
alias monstr Michal Simek <monstr@monstr.eu>
alias prafulla Prafulla Wadaskar <prafulla@marvell.com>
alias prom Minkyu Kang <mk7.kang@samsung.com>
#include <dm.h>
#include <ahci.h>
#include <scsi.h>
-#include <asm/arch/hardware.h>
-
#include <asm/io.h>
/* Vendor Specific Register Offsets */
#define AHCI_VEND_PP3C 0xB0
#define AHCI_VEND_PP4C 0xB4
#define AHCI_VEND_PP5C 0xB8
+#define AHCI_VEND_AXICC 0xBc
#define AHCI_VEND_PAXIC 0xC0
#define AHCI_VEND_PTC 0xC8
#define DRV_NAME "ahci-ceva"
#define CEVA_FLAG_BROKEN_GEN2 1
+/* flag bit definition */
+#define FLAG_COHERENT 1
+
+/* register config value */
+#define CEVA_PHY1_CFG 0xa003fffe
+#define CEVA_PHY2_CFG 0x28184d1f
+#define CEVA_PHY3_CFG 0x0e081509
+#define CEVA_TRANS_CFG 0x08000029
+#define CEVA_AXICC_CFG 0x3fffffff
+
+/* ecc addr-val pair */
+#define ECC_DIS_ADDR_CH2 0x80000000
+#define ECC_DIS_VAL_CH2 0x20140520
+
+enum ceva_soc {
+ CEVA_1V84,
+ CEVA_LS1012A,
+};
+
struct ceva_sata_priv {
ulong base;
+ enum ceva_soc soc;
+ ulong flag;
};
-static int ceva_init_sata(ulong mmio)
+static int ceva_init_sata(struct ceva_sata_priv *priv)
{
+ ulong base = priv->base;
ulong tmp;
- int i;
-
- /*
- * AXI Data bus width to 64
- * Set Mem Addr Read, Write ID for data transfers
- * Transfer limit to 72 DWord
- */
- tmp = PAXIC_ADBW_BW64 | PAXIC_MAWIDD | PAXIC_MARIDD | PAXIC_OTL;
- writel(tmp, mmio + AHCI_VEND_PAXIC);
-
- /* Set AHCI Enable */
- tmp = readl(mmio + HOST_CTL);
- tmp |= HOST_AHCI_EN;
- writel(tmp, mmio + HOST_CTL);
-
- for (i = 0; i < NR_PORTS; i++) {
- /* TPSS TPRS scalars, CISE and Port Addr */
- tmp = PCFG_TPSS_VAL | PCFG_TPRS_VAL | (PCFG_PAD_VAL + i);
- writel(tmp, mmio + AHCI_VEND_PCFG);
-
- /* Port Phy Cfg register enables */
- tmp = PPCFG_TTA | PPCFG_PSS_EN | PPCFG_ESDF_EN;
- writel(tmp, mmio + AHCI_VEND_PPCFG);
- /* Rx Watermark setting */
+ switch (priv->soc) {
+ case CEVA_1V84:
+ tmp = PAXIC_ADBW_BW64 | PAXIC_MAWIDD | PAXIC_MARIDD | PAXIC_OTL;
+ writel(tmp, base + AHCI_VEND_PAXIC);
+ tmp = PCFG_TPSS_VAL | PCFG_TPRS_VAL | PCFG_PAD_VAL;
+ writel(tmp, base + AHCI_VEND_PCFG);
+ tmp = PPCFG_TTA | PPCFG_PSS_EN | PPCFG_ESDF_EN;
+ writel(tmp, base + AHCI_VEND_PPCFG);
tmp = PTC_RX_WM_VAL | PTC_RSVD;
- writel(tmp, mmio + AHCI_VEND_PTC);
-
- /* Default to Gen 2 Speed and Gen 1 if Gen2 is broken */
- tmp = PORT_SCTL_SPD_GEN3 | PORT_SCTL_IPM;
- writel(tmp, mmio + PORT_SCR_CTL + PORT_BASE + PORT_OFFSET * i);
+ writel(tmp, base + AHCI_VEND_PTC);
+ break;
+
+ case CEVA_LS1012A:
+ writel(ECC_DIS_ADDR_CH2, ECC_DIS_VAL_CH2);
+ writel(CEVA_PHY1_CFG, base + AHCI_VEND_PPCFG);
+ writel(CEVA_TRANS_CFG, base + AHCI_VEND_PTC);
+ if (priv->flag & FLAG_COHERENT)
+ writel(CEVA_AXICC_CFG, base + AHCI_VEND_AXICC);
+ break;
}
+
return 0;
}
{
struct ceva_sata_priv *priv = dev_get_priv(dev);
- ceva_init_sata(priv->base);
+ ceva_init_sata(priv);
return ahci_probe_scsi(dev, priv->base);
}
static const struct udevice_id sata_ceva_ids[] = {
- { .compatible = "ceva,ahci-1v84" },
+ { .compatible = "ceva,ahci-1v84", .data = CEVA_1V84 },
+ { .compatible = "fsl,ls1012a-ahci", .data = CEVA_LS1012A },
{ }
};
{
struct ceva_sata_priv *priv = dev_get_priv(dev);
- priv->base = devfdt_get_addr(dev);
+ if (dev_read_bool(dev, "dma-coherent"))
+ priv->flag |= FLAG_COHERENT;
+
+ priv->base = dev_read_addr(dev);
if (priv->base == FDT_ADDR_T_NONE)
return -EINVAL;
+ priv->soc = dev_get_driver_data(dev);
+
return 0;
}
unsigned int ctrl_num)
{
unsigned int i;
- char buffer[HWCONFIG_BUFFER_SIZE];
- char *buf = NULL;
+ char buf[HWCONFIG_BUFFER_SIZE];
#if defined(CONFIG_SYS_FSL_DDR3) || \
defined(CONFIG_SYS_FSL_DDR2) || \
defined(CONFIG_SYS_FSL_DDR4)
* Extract hwconfig from environment since we have not properly setup
* the environment but need it for ddr config params
*/
- if (env_get_f("hwconfig", buffer, sizeof(buffer)) > 0)
- buf = buffer;
+ if (env_get_f("hwconfig", buf, sizeof(buf)) < 0)
+ buf[0] = '\0';
#if defined(CONFIG_SYS_FSL_DDR3) || \
defined(CONFIG_SYS_FSL_DDR2) || \
int use_spd = 0;
#ifdef CONFIG_DDR_SPD
- char buffer[HWCONFIG_BUFFER_SIZE];
- char *buf = NULL;
+ char buf[HWCONFIG_BUFFER_SIZE];
/*
* Extract hwconfig from environment since we have not properly setup
* the environment but need it for ddr config params
*/
- if (env_get_f("hwconfig", buffer, sizeof(buffer)) > 0)
- buf = buffer;
+ if (env_get_f("hwconfig", buf, sizeof(buf)) < 0)
+ buf[0] = '\0';
/* if hwconfig is not enabled, or "sdram" is not defined, use spd */
if (hwconfig_sub_f("fsl_ddr", "sdram", buf)) {
help
Enable driver model for Ethernet.
- The eth_*() interface will be implemented by the UC_ETH class
- This is currently implemented in net/eth.c
+ The eth_*() interface will be implemented by the UCLASS_ETH class
+ This is currently implemented in net/eth-uclass.c
Look in include/net.h for details.
config DRIVER_TI_CPSW
config MVGBE
bool "Marvell Orion5x/Kirkwood network interface support"
depends on KIRKWOOD || ORION5X
+ select PHYLIB if DM_ETH
help
This driver supports the network interface units in the
Marvell Orion5x and Kirkwood SoCs
obj-$(CONFIG_RTL8169) += rtl8169.o
obj-$(CONFIG_ETH_SANDBOX) += sandbox.o
obj-$(CONFIG_ETH_SANDBOX_RAW) += sandbox-raw.o
+obj-$(CONFIG_ETH_SANDBOX_RAW) += sandbox-raw-bus.o
obj-$(CONFIG_SH_ETHER) += sh_eth.o
obj-$(CONFIG_RENESAS_RAVB) += ravb.o
obj-$(CONFIG_SMC91111) += smc91111.o
#ifdef CONFIG_DM_ETH
if (slave->data->phy_of_handle)
- dev_set_of_offset(phydev->dev, slave->data->phy_of_handle);
+ phydev->node = offset_to_ofnode(slave->data->phy_of_handle);
#endif
priv->phydev = phydev;
*/
#include <common.h>
+#include <dm.h>
#include <net.h>
#include <malloc.h>
#include <miiphy.h>
return 0;
}
-/*
- * smi_reg_read - miiphy_read callback function.
- *
- * Returns 16bit phy register value, or -EFAULT on error
- */
-static int smi_reg_read(struct mii_dev *bus, int phy_adr, int devad,
- int reg_ofs)
+static int __mvgbe_mdio_read(struct mvgbe_device *dmvgbe, int phy_adr,
+ int devad, int reg_ofs)
{
- u16 data = 0;
- struct eth_device *dev = eth_get_dev_by_name(bus->name);
- struct mvgbe_device *dmvgbe = to_mvgbe(dev);
struct mvgbe_registers *regs = dmvgbe->regs;
u32 smi_reg;
u32 timeout;
+ u16 data = 0;
/* Phyadr read request */
if (phy_adr == MV_PHY_ADR_REQUEST &&
}
/*
- * smi_reg_write - miiphy_write callback function.
+ * smi_reg_read - miiphy_read callback function.
*
- * Returns 0 if write succeed, -EFAULT on error
+ * Returns 16bit phy register value, or -EFAULT on error
*/
-static int smi_reg_write(struct mii_dev *bus, int phy_adr, int devad,
- int reg_ofs, u16 data)
+static int smi_reg_read(struct mii_dev *bus, int phy_adr, int devad,
+ int reg_ofs)
{
+#ifdef CONFIG_DM_ETH
+ struct mvgbe_device *dmvgbe = bus->priv;
+#else
struct eth_device *dev = eth_get_dev_by_name(bus->name);
struct mvgbe_device *dmvgbe = to_mvgbe(dev);
+#endif
+
+ return __mvgbe_mdio_read(dmvgbe, phy_adr, devad, reg_ofs);
+}
+
+static int __mvgbe_mdio_write(struct mvgbe_device *dmvgbe, int phy_adr,
+ int devad, int reg_ofs, u16 data)
+{
struct mvgbe_registers *regs = dmvgbe->regs;
u32 smi_reg;
return 0;
}
+
+/*
+ * smi_reg_write - miiphy_write callback function.
+ *
+ * Returns 0 if write succeed, -EFAULT on error
+ */
+static int smi_reg_write(struct mii_dev *bus, int phy_adr, int devad,
+ int reg_ofs, u16 data)
+{
+#ifdef CONFIG_DM_ETH
+ struct mvgbe_device *dmvgbe = bus->priv;
+#else
+ struct eth_device *dev = eth_get_dev_by_name(bus->name);
+ struct mvgbe_device *dmvgbe = to_mvgbe(dev);
+#endif
+
+ return __mvgbe_mdio_write(dmvgbe, phy_adr, devad, reg_ofs, data);
+}
#endif
/* Stop and checks all queues */
/*
* port_uc_addr_set - This function Set the port Unicast address.
*/
-static void port_uc_addr_set(struct mvgbe_registers *regs, u8 * p_addr)
+static void port_uc_addr_set(struct mvgbe_device *dmvgbe, u8 *p_addr)
{
+ struct mvgbe_registers *regs = dmvgbe->regs;
u32 mac_h;
u32 mac_l;
dmvgbe->p_rxdesc_curr = dmvgbe->p_rxdesc;
}
-static int mvgbe_init(struct eth_device *dev)
+static int __mvgbe_init(struct mvgbe_device *dmvgbe, u8 *enetaddr,
+ const char *name)
{
- struct mvgbe_device *dmvgbe = to_mvgbe(dev);
struct mvgbe_registers *regs = dmvgbe->regs;
#if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) && \
!defined(CONFIG_PHYLIB) && \
+ !defined(CONFIG_DM_ETH) && \
defined(CONFIG_SYS_FAULT_ECHO_LINK_DOWN)
int i;
#endif
set_dram_access(regs);
port_init_mac_tables(regs);
- port_uc_addr_set(regs, dmvgbe->dev.enetaddr);
+ port_uc_addr_set(dmvgbe, enetaddr);
/* Assign port configuration and command. */
MVGBE_REG_WR(regs->pxc, PRT_CFG_VAL);
#if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) && \
!defined(CONFIG_PHYLIB) && \
+ !defined(CONFIG_DM_ETH) && \
defined(CONFIG_SYS_FAULT_ECHO_LINK_DOWN)
/* Wait up to 5s for the link status */
for (i = 0; i < 5; i++) {
u16 phyadr;
- miiphy_read(dev->name, MV_PHY_ADR_REQUEST,
+ miiphy_read(name, MV_PHY_ADR_REQUEST,
MV_PHY_ADR_REQUEST, &phyadr);
/* Return if we get link up */
- if (miiphy_link(dev->name, phyadr))
+ if (miiphy_link(name, phyadr))
return 0;
udelay(1000000);
}
- printf("No link on %s\n", dev->name);
+ printf("No link on %s\n", name);
return -1;
#endif
return 0;
}
-static int mvgbe_halt(struct eth_device *dev)
+#ifndef CONFIG_DM_ETH
+static int mvgbe_init(struct eth_device *dev)
{
struct mvgbe_device *dmvgbe = to_mvgbe(dev);
+
+ return __mvgbe_init(dmvgbe, dmvgbe->dev.enetaddr, dmvgbe->dev.name);
+}
+#endif
+
+static void __mvgbe_halt(struct mvgbe_device *dmvgbe)
+{
struct mvgbe_registers *regs = dmvgbe->regs;
/* Disable all gigE address decoder */
MVGBE_REG_WR(regs->ice, 0);
MVGBE_REG_WR(regs->pim, 0);
MVGBE_REG_WR(regs->peim, 0);
+}
+
+#ifndef CONFIG_DM_ETH
+static int mvgbe_halt(struct eth_device *dev)
+{
+ struct mvgbe_device *dmvgbe = to_mvgbe(dev);
+
+ __mvgbe_halt(dmvgbe);
return 0;
}
+#endif
+
+#ifdef CONFIG_DM_ETH
+static int mvgbe_write_hwaddr(struct udevice *dev)
+{
+ struct eth_pdata *pdata = dev_get_platdata(dev);
+ port_uc_addr_set(dev_get_priv(dev), pdata->enetaddr);
+
+ return 0;
+}
+#else
static int mvgbe_write_hwaddr(struct eth_device *dev)
{
struct mvgbe_device *dmvgbe = to_mvgbe(dev);
- struct mvgbe_registers *regs = dmvgbe->regs;
/* Programs net device MAC address after initialization */
- port_uc_addr_set(regs, dmvgbe->dev.enetaddr);
+ port_uc_addr_set(dmvgbe, dmvgbe->dev.enetaddr);
return 0;
}
+#endif
-static int mvgbe_send(struct eth_device *dev, void *dataptr, int datasize)
+static int __mvgbe_send(struct mvgbe_device *dmvgbe, void *dataptr,
+ int datasize)
{
- struct mvgbe_device *dmvgbe = to_mvgbe(dev);
struct mvgbe_registers *regs = dmvgbe->regs;
struct mvgbe_txdesc *p_txdesc = dmvgbe->p_txdesc;
void *p = (void *)dataptr;
return 0;
}
-static int mvgbe_recv(struct eth_device *dev)
+#ifndef CONFIG_DM_ETH
+static int mvgbe_send(struct eth_device *dev, void *dataptr, int datasize)
{
struct mvgbe_device *dmvgbe = to_mvgbe(dev);
+
+ return __mvgbe_send(dmvgbe, dataptr, datasize);
+}
+#endif
+
+static int __mvgbe_recv(struct mvgbe_device *dmvgbe, uchar **packetp)
+{
struct mvgbe_rxdesc *p_rxdesc_curr = dmvgbe->p_rxdesc_curr;
u32 cmd_sts;
u32 timeout = 0;
u32 rxdesc_curr_addr;
+ unsigned char *data;
+ int rx_bytes = 0;
+
+ *packetp = NULL;
/* wait untill rx packet available or timeout */
do {
" upper layer (net_process_received_packet)\n",
__func__);
- /* let the upper layer handle the packet */
- net_process_received_packet((p_rxdesc_curr->buf_ptr +
- RX_BUF_OFFSET),
- (int)(p_rxdesc_curr->byte_cnt -
- RX_BUF_OFFSET));
+ data = (p_rxdesc_curr->buf_ptr + RX_BUF_OFFSET);
+ rx_bytes = (int)(p_rxdesc_curr->byte_cnt -
+ RX_BUF_OFFSET);
+
+ *packetp = data;
}
/*
* free these descriptors and point next in the ring
rxdesc_curr_addr = (u32)&dmvgbe->p_rxdesc_curr;
writel((unsigned)p_rxdesc_curr->nxtdesc_p, rxdesc_curr_addr);
+ return rx_bytes;
+}
+
+#ifndef CONFIG_DM_ETH
+static int mvgbe_recv(struct eth_device *dev)
+{
+ struct mvgbe_device *dmvgbe = to_mvgbe(dev);
+ uchar *packet;
+ int ret;
+
+ ret = __mvgbe_recv(dmvgbe, &packet);
+ if (ret < 0)
+ return ret;
+
+ net_process_received_packet(packet, ret);
+
return 0;
}
+#endif
-#if defined(CONFIG_PHYLIB)
+#if defined(CONFIG_PHYLIB) || defined(CONFIG_DM_ETH)
+#if defined(CONFIG_DM_ETH)
+static struct phy_device *__mvgbe_phy_init(struct udevice *dev,
+ struct mii_dev *bus,
+ phy_interface_t phy_interface,
+ int phyid)
+#else
+static struct phy_device *__mvgbe_phy_init(struct eth_device *dev,
+ struct mii_dev *bus,
+ phy_interface_t phy_interface,
+ int phyid)
+#endif
+{
+ struct phy_device *phydev;
+
+ /* Set phy address of the port */
+ miiphy_write(dev->name, MV_PHY_ADR_REQUEST, MV_PHY_ADR_REQUEST,
+ phyid);
+
+ phydev = phy_connect(bus, phyid, dev, phy_interface);
+ if (!phydev) {
+ printf("phy_connect failed\n");
+ return NULL;
+ }
+
+ phy_config(phydev);
+ phy_startup(phydev);
+
+ return phydev;
+}
+#endif /* CONFIG_PHYLIB || CONFIG_DM_ETH */
+
+#if defined(CONFIG_PHYLIB) && !defined(CONFIG_DM_ETH)
int mvgbe_phylib_init(struct eth_device *dev, int phyid)
{
struct mii_dev *bus;
return -ENOMEM;
}
- /* Set phy address of the port */
- smi_reg_write(bus, MV_PHY_ADR_REQUEST, 0, MV_PHY_ADR_REQUEST, phyid);
-
- phydev = phy_connect(bus, phyid, dev, PHY_INTERFACE_MODE_RGMII);
- if (!phydev) {
- printf("phy_connect failed\n");
+ phydev = __mvgbe_phy_init(dev, bus, PHY_INTERFACE_MODE_RGMII, phyid);
+ if (!phydev)
return -ENODEV;
- }
-
- phy_config(phydev);
- phy_startup(phydev);
return 0;
}
#endif
+static int mvgbe_alloc_buffers(struct mvgbe_device *dmvgbe)
+{
+ dmvgbe->p_rxdesc = memalign(PKTALIGN,
+ MV_RXQ_DESC_ALIGNED_SIZE * RINGSZ + 1);
+ if (!dmvgbe->p_rxdesc)
+ goto error1;
+
+ dmvgbe->p_rxbuf = memalign(PKTALIGN,
+ RINGSZ * PKTSIZE_ALIGN + 1);
+ if (!dmvgbe->p_rxbuf)
+ goto error2;
+
+ dmvgbe->p_aligned_txbuf = memalign(8, PKTSIZE_ALIGN);
+ if (!dmvgbe->p_aligned_txbuf)
+ goto error3;
+
+ dmvgbe->p_txdesc = memalign(PKTALIGN, sizeof(struct mvgbe_txdesc) + 1);
+ if (!dmvgbe->p_txdesc)
+ goto error4;
+
+ return 0;
+
+error4:
+ free(dmvgbe->p_aligned_txbuf);
+error3:
+ free(dmvgbe->p_rxbuf);
+error2:
+ free(dmvgbe->p_rxdesc);
+error1:
+ return -ENOMEM;
+}
+
+#ifndef CONFIG_DM_ETH
int mvgbe_initialize(bd_t *bis)
{
struct mvgbe_device *dmvgbe;
struct eth_device *dev;
int devnum;
+ int ret;
u8 used_ports[MAX_MVGBE_DEVS] = CONFIG_MVGBE_PORTS;
for (devnum = 0; devnum < MAX_MVGBE_DEVS; devnum++) {
continue;
dmvgbe = malloc(sizeof(struct mvgbe_device));
-
if (!dmvgbe)
- goto error1;
+ return -ENOMEM;
memset(dmvgbe, 0, sizeof(struct mvgbe_device));
-
- dmvgbe->p_rxdesc =
- (struct mvgbe_rxdesc *)memalign(PKTALIGN,
- MV_RXQ_DESC_ALIGNED_SIZE*RINGSZ + 1);
-
- if (!dmvgbe->p_rxdesc)
- goto error2;
-
- dmvgbe->p_rxbuf = (u8 *) memalign(PKTALIGN,
- RINGSZ*PKTSIZE_ALIGN + 1);
-
- if (!dmvgbe->p_rxbuf)
- goto error3;
-
- dmvgbe->p_aligned_txbuf = memalign(8, PKTSIZE_ALIGN);
-
- if (!dmvgbe->p_aligned_txbuf)
- goto error4;
-
- dmvgbe->p_txdesc = (struct mvgbe_txdesc *) memalign(
- PKTALIGN, sizeof(struct mvgbe_txdesc) + 1);
-
- if (!dmvgbe->p_txdesc) {
- free(dmvgbe->p_aligned_txbuf);
-error4:
- free(dmvgbe->p_rxbuf);
-error3:
- free(dmvgbe->p_rxdesc);
-error2:
- free(dmvgbe);
-error1:
+ ret = mvgbe_alloc_buffers(dmvgbe);
+ if (ret) {
printf("Err.. %s Failed to allocate memory\n",
__func__);
- return -1;
+ free(dmvgbe);
+ return ret;
}
dev = &dmvgbe->dev;
}
return 0;
}
+#endif
+
+#ifdef CONFIG_DM_ETH
+static int mvgbe_port_is_fixed_link(struct mvgbe_device *dmvgbe)
+{
+ return dmvgbe->phyaddr > PHY_MAX_ADDR;
+}
+
+static int mvgbe_start(struct udevice *dev)
+{
+ struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct mvgbe_device *dmvgbe = dev_get_priv(dev);
+ int ret;
+
+ ret = __mvgbe_init(dmvgbe, pdata->enetaddr, dev->name);
+ if (ret)
+ return ret;
+
+ if (!mvgbe_port_is_fixed_link(dmvgbe)) {
+ dmvgbe->phydev = __mvgbe_phy_init(dev, dmvgbe->bus,
+ dmvgbe->phy_interface,
+ dmvgbe->phyaddr);
+ if (!dmvgbe->phydev)
+ return -ENODEV;
+ }
+
+ return 0;
+}
+
+static int mvgbe_send(struct udevice *dev, void *packet, int length)
+{
+ struct mvgbe_device *dmvgbe = dev_get_priv(dev);
+
+ return __mvgbe_send(dmvgbe, packet, length);
+}
+
+static int mvgbe_recv(struct udevice *dev, int flags, uchar **packetp)
+{
+ struct mvgbe_device *dmvgbe = dev_get_priv(dev);
+
+ return __mvgbe_recv(dmvgbe, packetp);
+}
+
+static void mvgbe_stop(struct udevice *dev)
+{
+ struct mvgbe_device *dmvgbe = dev_get_priv(dev);
+
+ __mvgbe_halt(dmvgbe);
+}
+
+static int mvgbe_probe(struct udevice *dev)
+{
+ struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct mvgbe_device *dmvgbe = dev_get_priv(dev);
+ struct mii_dev *bus;
+ int ret;
+
+ ret = mvgbe_alloc_buffers(dmvgbe);
+ if (ret)
+ return ret;
+
+ dmvgbe->regs = (void __iomem *)pdata->iobase;
+
+ bus = mdio_alloc();
+ if (!bus) {
+ printf("Failed to allocate MDIO bus\n");
+ return -ENOMEM;
+ }
+
+ bus->read = smi_reg_read;
+ bus->write = smi_reg_write;
+ snprintf(bus->name, sizeof(bus->name), dev->name);
+ bus->priv = dmvgbe;
+ dmvgbe->bus = bus;
+
+ ret = mdio_register(bus);
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+
+static const struct eth_ops mvgbe_ops = {
+ .start = mvgbe_start,
+ .send = mvgbe_send,
+ .recv = mvgbe_recv,
+ .stop = mvgbe_stop,
+ .write_hwaddr = mvgbe_write_hwaddr,
+};
+
+static int mvgbe_ofdata_to_platdata(struct udevice *dev)
+{
+ struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct mvgbe_device *dmvgbe = dev_get_priv(dev);
+ void *blob = (void *)gd->fdt_blob;
+ int node = dev_of_offset(dev);
+ const char *phy_mode;
+ int fl_node;
+ int pnode;
+ unsigned long addr;
+
+ pdata->iobase = devfdt_get_addr(dev);
+ pdata->phy_interface = -1;
+
+ pnode = fdt_node_offset_by_compatible(blob, node,
+ "marvell,kirkwood-eth-port");
+
+ /* Get phy-mode / phy_interface from DT */
+ phy_mode = fdt_getprop(gd->fdt_blob, pnode, "phy-mode", NULL);
+ if (phy_mode)
+ pdata->phy_interface = phy_get_interface_by_name(phy_mode);
+ if (pdata->phy_interface == -1) {
+ debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
+ return -EINVAL;
+ }
+
+ dmvgbe->phy_interface = pdata->phy_interface;
+
+ /* fetch 'fixed-link' property */
+ fl_node = fdt_subnode_offset(blob, pnode, "fixed-link");
+ if (fl_node != -FDT_ERR_NOTFOUND) {
+ /* set phy_addr to invalid value for fixed link */
+ dmvgbe->phyaddr = PHY_MAX_ADDR + 1;
+ dmvgbe->duplex = fdtdec_get_bool(blob, fl_node, "full-duplex");
+ dmvgbe->speed = fdtdec_get_int(blob, fl_node, "speed", 0);
+ } else {
+ /* Now read phyaddr from DT */
+ addr = fdtdec_lookup_phandle(blob, pnode, "phy-handle");
+ if (addr > 0)
+ dmvgbe->phyaddr = fdtdec_get_int(blob, addr, "reg", 0);
+ }
+
+ return 0;
+}
+
+static const struct udevice_id mvgbe_ids[] = {
+ { .compatible = "marvell,kirkwood-eth" },
+ { }
+};
+
+U_BOOT_DRIVER(mvgbe) = {
+ .name = "mvgbe",
+ .id = UCLASS_ETH,
+ .of_match = mvgbe_ids,
+ .ofdata_to_platdata = mvgbe_ofdata_to_platdata,
+ .probe = mvgbe_probe,
+ .ops = &mvgbe_ops,
+ .priv_auto_alloc_size = sizeof(struct mvgbe_device),
+ .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+};
+#endif /* CONFIG_DM_ETH */
#define RXUQ 0 /* Used Rx queue */
#define TXUQ 0 /* Used Rx queue */
+#ifndef CONFIG_DM_ETH
#define to_mvgbe(_d) container_of(_d, struct mvgbe_device, dev)
+#endif
#define MVGBE_REG_WR(adr, val) writel(val, &adr)
#define MVGBE_REG_RD(adr) readl(&adr)
#define MVGBE_REG_BITS_RESET(adr, val) writel(readl(&adr) & ~(val), &adr)
/* port device data struct */
struct mvgbe_device {
+#ifndef CONFIG_DM_ETH
struct eth_device dev;
+#endif
struct mvgbe_registers *regs;
struct mvgbe_txdesc *p_txdesc;
struct mvgbe_rxdesc *p_rxdesc;
struct mvgbe_rxdesc *p_rxdesc_curr;
u8 *p_rxbuf;
u8 *p_aligned_txbuf;
+
+#ifdef CONFIG_DM_ETH
+ phy_interface_t phy_interface;
+ unsigned int link;
+ unsigned int duplex;
+ unsigned int speed;
+
+ int init;
+ int phyaddr;
+ struct phy_device *phydev;
+ struct mii_dev *bus;
+#endif
};
#endif /* __MVGBE_H__ */
* Copyright 2011, 2013 Freescale Semiconductor, Inc.
* author Andy Fleming
*/
+#include <common.h>
#include <phy.h>
#define AR803x_PHY_DEBUG_ADDR_REG 0x1d
* Copyright 2010-2011 Freescale Semiconductor, Inc.
* author Andy Fleming
*/
-#include <config.h>
#include <common.h>
#include <phy.h>
* Copyright 2010-2011 Freescale Semiconductor, Inc.
* author Andy Fleming
*/
+#include <common.h>
#include <phy.h>
#define MIIM_DM9161_SCR 0x10
*
* Based loosely off of Linux's PHY Lib
*/
-
-#include <config.h>
#include <common.h>
#include <miiphy.h>
#include <phy.h>
* Copyright 2010-2011 Freescale Semiconductor, Inc.
* author Andy Fleming
*/
+#include <common.h>
#include <phy.h>
/* LXT971 Status 2 registers */
* Copyright 2010-2011 Freescale Semiconductor, Inc.
* author Andy Fleming
*/
-#include <config.h>
#include <common.h>
#include <errno.h>
#include <phy.h>
* author Andy Fleming
* (C) 2012 NetModule AG, David Andrey, added KSZ9031
*/
-#include <config.h>
#include <common.h>
#include <dm.h>
#include <errno.h>
* (C) Copyright 2017 Adaptrum, Inc.
* Written by Alexandru Gagniuc <alex.g@adaptrum.com> for Adaptrum, Inc.
*/
-
-#include <config.h>
#include <common.h>
#include <dm.h>
#include <errno.h>
* Copyright 2010-2011 Freescale Semiconductor, Inc.
* author Andy Fleming
*/
+#include <common.h>
#include <phy.h>
/* NatSemi DP83630 */
*
* Based loosely off of Linux's PHY Lib
*/
-
-#include <config.h>
#include <common.h>
#include <console.h>
#include <dm.h>
dev->link = 0;
dev->interface = interface;
+#ifdef CONFIG_DM_ETH
+ dev->node = ofnode_null();
+#endif
+
dev->autoneg = AUTONEG_ENABLE;
dev->addr = addr;
* author Andy Fleming
* Copyright 2016 Karsten Merker <merker@debian.org>
*/
-#include <config.h>
#include <common.h>
#include <linux/bitops.h>
#include <phy.h>
* Some code copied from linux kernel
* Copyright (c) 2006 Herbert Valerio Riedel <hvr@gnu.org>
*/
+#include <common.h>
#include <miiphy.h>
/* This code does not check the partner abilities. */
* Copyright 2010-2011 Freescale Semiconductor, Inc.
* author Andy Fleming
*/
-#include <config.h>
#include <common.h>
#include <phy.h>
#include <linux/compat.h>
#include <malloc.h>
-#include <fdtdec.h>
#include <dm.h>
#include <dt-bindings/net/ti-dp83867.h>
-DECLARE_GLOBAL_DATA_PTR;
/* TI DP83867 */
#define DP83867_DEVADDR 0x1f
#define DP83867_CTRL 0x1f
/* Extended Registers */
+#define DP83867_CFG4 0x0031
#define DP83867_RGMIICTL 0x0032
#define DP83867_RGMIIDCTL 0x0086
#define DP83867_IO_MUX_CFG 0x0170
int tx_id_delay;
int fifo_depth;
int io_impedance;
+ bool rxctrl_strap_quirk;
};
/**
static int dp83867_of_init(struct phy_device *phydev)
{
struct dp83867_private *dp83867 = phydev->priv;
- struct udevice *dev = phydev->dev;
- int node = dev_of_offset(dev);
- const void *fdt = gd->fdt_blob;
+ ofnode node;
- if (fdtdec_get_bool(fdt, node, "ti,max-output-impedance"))
+ node = phy_get_ofnode(phydev);
+ if (!ofnode_valid(node))
+ return -EINVAL;
+
+ if (ofnode_read_bool(node, "ti,max-output-impedance"))
dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX;
- else if (fdtdec_get_bool(fdt, node, "ti,min-output-impedance"))
+ else if (ofnode_read_bool(node, "ti,min-output-impedance"))
dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN;
else
dp83867->io_impedance = -EINVAL;
- dp83867->rx_id_delay = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
- "ti,rx-internal-delay", -1);
+ if (ofnode_read_bool(node, "ti,dp83867-rxctrl-strap-quirk"))
+ dp83867->rxctrl_strap_quirk = true;
+ dp83867->rx_id_delay = ofnode_read_u32_default(node,
+ "ti,rx-internal-delay",
+ -1);
- dp83867->tx_id_delay = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
- "ti,tx-internal-delay", -1);
+ dp83867->tx_id_delay = ofnode_read_u32_default(node,
+ "ti,tx-internal-delay",
+ -1);
- dp83867->fifo_depth = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
- "ti,fifo-depth", -1);
+ dp83867->fifo_depth = ofnode_read_u32_default(node, "ti,fifo-depth",
+ -1);
return 0;
}
phy_write(phydev, MDIO_DEVAD_NONE, DP83867_CTRL,
val | DP83867_SW_RESTART);
+ /* Mode 1 or 2 workaround */
+ if (dp83867->rxctrl_strap_quirk) {
+ val = phy_read_mmd_indirect(phydev, DP83867_CFG4,
+ DP83867_DEVADDR, phydev->addr);
+ val &= ~BIT(7);
+ phy_write_mmd_indirect(phydev, DP83867_CFG4,
+ DP83867_DEVADDR, phydev->addr, val);
+ }
+
if (phy_interface_is_rgmii(phydev)) {
ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL,
(DP83867_MDI_CROSSOVER_AUTO << DP83867_MDI_CROSSOVER) |
* Original Author: Andy Fleming
* Add vsc8662 phy support - Priyanka Jain
*/
+#include <common.h>
#include <miiphy.h>
/* Cicada Auxiliary Control/Status Register */
#include <phy.h>
#include <dm.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#define MII_PHY_STATUS_SPD_MASK 0x0C00
#define MII_PHY_STATUS_FULLDUPLEX 0x1000
#define MII_PHY_STATUS_1000 0x0800
static int xilinxphy_of_init(struct phy_device *phydev)
{
u32 phytype;
+ ofnode node;
debug("%s\n", __func__);
- phytype = fdtdec_get_int(gd->fdt_blob, dev_of_offset(phydev->dev),
- "xlnx,phy-type", -1);
+ node = phy_get_ofnode(phydev);
+ if (!ofnode_valid(node))
+ return -EINVAL;
+
+ phytype = ofnode_read_u32_default(node, "xlnx,phy-type", -1);
if (phytype == XAE_PHY_TYPE_1000BASE_X)
phydev->flags |= XAE_PHY_TYPE_1000BASE_X;
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2018 National Instruments
+ * Copyright (c) 2018 Joe Hershberger <joe.hershberger@ni.com>
+ */
+
+#include <common.h>
+#include <asm/eth-raw-os.h>
+#include <dm.h>
+#include <errno.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
+
+static int eth_raw_bus_post_bind(struct udevice *dev)
+{
+ struct sandbox_eth_raw_if_nameindex *ni, *i;
+ struct udevice *child;
+ struct eth_sandbox_raw_priv *priv;
+ char *ub_ifname;
+ static const char ub_ifname_pfx[] = "host_";
+ u32 skip_localhost = 0;
+
+ ni = sandbox_eth_raw_if_nameindex();
+ if (!ni)
+ return -EINVAL;
+
+ dev_read_u32(dev, "skip-localhost", &skip_localhost);
+ for (i = ni; !(i->if_index == 0 && !i->if_name); i++) {
+ int local = sandbox_eth_raw_os_is_local(i->if_name);
+
+ if (local < 0)
+ continue;
+ if (skip_localhost && local)
+ continue;
+
+ ub_ifname = calloc(IFNAMSIZ + sizeof(ub_ifname_pfx), 1);
+ strcpy(ub_ifname, ub_ifname_pfx);
+ strncat(ub_ifname, i->if_name, IFNAMSIZ);
+ device_bind_driver(dev, "eth_sandbox_raw", ub_ifname, &child);
+
+ device_set_name_alloced(child);
+ device_probe(child);
+ priv = dev_get_priv(child);
+ if (priv) {
+ memcpy(priv->host_ifname, i->if_name, IFNAMSIZ);
+ priv->host_ifindex = i->if_index;
+ priv->local = local;
+ }
+ }
+
+ sandbox_eth_raw_if_freenameindex(ni);
+
+ return 0;
+}
+
+static const struct udevice_id sandbox_eth_raw_bus_ids[] = {
+ { .compatible = "sandbox,eth-raw-bus" },
+ { }
+};
+
+U_BOOT_DRIVER(sandbox_eth_raw_bus) = {
+ .name = "sb_eth_raw_bus",
+ .id = UCLASS_SIMPLE_BUS,
+ .of_match = sandbox_eth_raw_bus_ids,
+ .bind = eth_raw_bus_post_bind,
+};
{
struct eth_sandbox_raw_priv *priv = dev_get_priv(dev);
struct eth_pdata *pdata = dev_get_platdata(dev);
- const char *interface;
+ int ret;
debug("eth_sandbox_raw: Start\n");
- interface = fdt_getprop(gd->fdt_blob, dev_of_offset(dev),
- "host-raw-interface", NULL);
- if (interface == NULL)
- return -EINVAL;
-
- if (strcmp(interface, "lo") == 0) {
- priv->local = 1;
+ ret = sandbox_eth_raw_os_start(priv, pdata->enetaddr);
+ if (priv->local) {
env_set("ipaddr", "127.0.0.1");
env_set("serverip", "127.0.0.1");
+ net_ip = string_to_ip("127.0.0.1");
+ net_server_ip = net_ip;
}
- return sandbox_eth_raw_os_start(interface, pdata->enetaddr, priv);
+ return ret;
}
static int sb_eth_raw_send(struct udevice *dev, void *packet, int length)
sandbox_eth_raw_os_stop(priv);
}
+static int sb_eth_raw_read_rom_hwaddr(struct udevice *dev)
+{
+ struct eth_pdata *pdata = dev_get_platdata(dev);
+
+ net_random_ethaddr(pdata->enetaddr);
+
+ return 0;
+}
+
static const struct eth_ops sb_eth_raw_ops = {
.start = sb_eth_raw_start,
.send = sb_eth_raw_send,
.recv = sb_eth_raw_recv,
.stop = sb_eth_raw_stop,
+ .read_rom_hwaddr = sb_eth_raw_read_rom_hwaddr,
};
static int sb_eth_raw_ofdata_to_platdata(struct udevice *dev)
{
struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_sandbox_raw_priv *priv = dev_get_priv(dev);
+ const char *ifname;
+ u32 local;
+ int ret;
+
+ pdata->iobase = dev_read_addr(dev);
+
+ ifname = dev_read_string(dev, "host-raw-interface");
+ if (ifname) {
+ strncpy(priv->host_ifname, ifname, IFNAMSIZ);
+ printf(": Using %s from DT\n", priv->host_ifname);
+ }
+ if (dev_read_u32(dev, "host-raw-interface-idx",
+ &priv->host_ifindex) < 0) {
+ priv->host_ifindex = 0;
+ } else {
+ ret = sandbox_eth_raw_os_idx_to_name(priv);
+ if (ret < 0)
+ return ret;
+ printf(": Using interface index %d from DT (%s)\n",
+ priv->host_ifindex, priv->host_ifname);
+ }
+
+ local = sandbox_eth_raw_os_is_local(priv->host_ifname);
+ if (local < 0)
+ return local;
+ priv->local = local;
- pdata->iobase = devfdt_get_addr(dev);
return 0;
}
debug("eth_sandbox: Start\n");
- fdtdec_get_byte_array(gd->fdt_blob, dev_of_offset(dev),
- "fake-host-hwaddr", priv->fake_host_hwaddr,
- ARP_HLEN);
priv->recv_packet_buffer = net_rx_packets[0];
+
return 0;
}
static int sb_eth_ofdata_to_platdata(struct udevice *dev)
{
struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_sandbox_priv *priv = dev_get_priv(dev);
+ const u8 *mac;
+
+ pdata->iobase = dev_read_addr(dev);
+
+ mac = dev_read_u8_array_ptr(dev, "fake-host-hwaddr", ARP_HLEN);
+ if (!mac) {
+ printf("'fake-host-hwaddr' is missing from the DT\n");
+ return -EINVAL;
+ }
+ memcpy(priv->fake_host_hwaddr, mac, ARP_HLEN);
- pdata->iobase = devfdt_get_addr(dev);
return 0;
}
struct zynq_gem_regs *iobase;
phy_interface_t interface;
struct phy_device *phydev;
- int phy_of_handle;
+ ofnode phy_of_node;
struct mii_dev *bus;
struct clk clk;
u32 max_speed;
}
priv->phydev->advertising = priv->phydev->supported;
-
- if (priv->phy_of_handle > 0)
- dev_set_of_offset(priv->phydev->dev, priv->phy_of_handle);
+ priv->phydev->node = priv->phy_of_node;
return phy_config(priv->phydev);
}
{
struct eth_pdata *pdata = dev_get_platdata(dev);
struct zynq_gem_priv *priv = dev_get_priv(dev);
- int node = dev_of_offset(dev);
+ struct ofnode_phandle_args phandle_args;
const char *phy_mode;
- pdata->iobase = (phys_addr_t)devfdt_get_addr(dev);
+ pdata->iobase = (phys_addr_t)dev_read_addr(dev);
priv->iobase = (struct zynq_gem_regs *)pdata->iobase;
/* Hardcode for now */
priv->phyaddr = -1;
- priv->phy_of_handle = fdtdec_lookup_phandle(gd->fdt_blob, node,
- "phy-handle");
- if (priv->phy_of_handle > 0)
- priv->phyaddr = fdtdec_get_int(gd->fdt_blob,
- priv->phy_of_handle, "reg", -1);
+ if (dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
+ &phandle_args)) {
+ debug("phy-handle does not exist %s\n", dev->name);
+ return -ENOENT;
+ }
- phy_mode = fdt_getprop(gd->fdt_blob, node, "phy-mode", NULL);
+ priv->phyaddr = ofnode_read_u32_default(phandle_args.node, "reg", -1);
+ priv->phy_of_node = phandle_args.node;
+ phy_mode = dev_read_prop(dev, "phy-mode", NULL);
if (phy_mode)
pdata->phy_interface = phy_get_interface_by_name(phy_mode);
if (pdata->phy_interface == -1) {
}
priv->interface = pdata->phy_interface;
- priv->max_speed = fdtdec_get_uint(gd->fdt_blob, priv->phy_of_handle,
- "max-speed", SPEED_1000);
- priv->int_pcs = fdtdec_get_bool(gd->fdt_blob, node,
- "is-internal-pcspma");
+ priv->max_speed = dev_read_u32_default(dev, "max-speed", SPEED_1000);
+ priv->int_pcs = dev_read_bool(dev, "is-internal-pcspma");
printf("ZYNQ GEM: %lx, phyaddr %x, interface %s\n", (ulong)priv->iobase,
priv->phyaddr, phy_string_for_interface(priv->interface));
Binding info: doc/device-tree-bindings/pmic/s2mps11.txt
config DM_PMIC_SANDBOX
- bool "Enable Driver Model for emulated Sandbox PMIC "
+ bool "Enable Driver Model for emulated Sandbox PMIC"
depends on DM_PMIC
---help---
Enable the driver for Sandbox PMIC emulation. The emulated PMIC device
#include <asm/arch/at91_rtt.h>
#include <asm/arch/at91_gpbr.h>
-#if defined(CONFIG_CMD_DATE)
-
int rtc_get (struct rtc_time *tmp)
{
at91_rtt_t *rtt = (at91_rtt_t *) ATMEL_BASE_RTT;
while (readl(&rtt->vr) != 0)
;
}
-
-#endif
#include <asm/io.h>
#include <asm/davinci_rtc.h>
-#if defined(CONFIG_CMD_DATE)
int rtc_get(struct rtc_time *tmp)
{
struct davinci_rtc *rtc = (struct davinci_rtc *)DAVINCI_RTC_BASE;
/* run RTC counter */
writel(0x01, &rtc->ctrl);
}
-#endif
#include <command.h>
#include <rtc.h>
-#if defined(CONFIG_CMD_DATE)
-
/* GPP Pins */
#define DATA 0x200
#define SCLK 0x400
return 0;
}
-
-#endif
#include <rtc.h>
#include <spi.h>
-#if defined(CONFIG_CMD_DATE)
-
#define RTC_SECONDS 0x00
#define RTC_MINUTES 0x01
#define RTC_HOURS 0x02
}
#endif /* end of code exclusion (see #ifdef CONFIG_SXNI855T above) */
-
-#endif
#ifndef CONFIG_DM_RTC
-#if defined(CONFIG_CMD_DATE)
-
/*---------------------------------------------------------------------*/
#undef DEBUG_RTC
i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val);
}
-#endif /* CONFIG_CMD_DATE*/
-
#endif /* !CONFIG_DM_RTC */
#ifdef CONFIG_DM_RTC
#include <rtc.h>
#include <i2c.h>
-#if defined(CONFIG_CMD_DATE)
-
/*
* RTC register addresses
*/
{
i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val);
}
-
-#endif
#include <rtc.h>
#include <i2c.h>
-#if defined(CONFIG_CMD_DATE)
-
/*---------------------------------------------------------------------*/
#undef DEBUG_RTC
#define DEBUG_RTC
{
i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val);
}
-#endif
#include <rtc.h>
-#if defined(CONFIG_CMD_DATE)
-
static uchar rtc_read(unsigned int addr );
static void rtc_write(unsigned int addr, uchar val);
#endif
*(volatile unsigned char*)(addr) = val;
}
-
-#endif
#include <command.h>
#include <rtc.h>
-#if defined(CONFIG_CMD_DATE)
-
static uchar rtc_read( unsigned int addr );
static void rtc_write( unsigned int addr, uchar val);
#endif
out8( addr, val );
}
-
-#endif
#include <rtc.h>
#include <i2c.h>
-#if defined(CONFIG_CMD_DATE)
-
/*
* RTC register addresses
*/
{
i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val);
}
-
-#endif
#include <linux/compat.h>
#include <rtc.h>
-#if defined(CONFIG_CMD_DATE)
-
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
{
di_init();
}
-
-#endif
#endif
*/
-#if defined(CONFIG_SYS_I2C_RTC_ADDR) && defined(CONFIG_CMD_DATE)
-
/* ------------------------------------------------------------------------- */
/*
these are simple defines for the chip local to here so they aren't too
val = val & 0x3F;/*turn off freq test keep calibration*/
i2c_write(CONFIG_SYS_I2C_RTC_ADDR, RTC_CONTROL_ADDR, 1, &val, 1);
}
-#endif
#include <rtc.h>
#include <i2c.h>
-#if defined(CONFIG_SYS_I2C_RTC_ADDR) && defined(CONFIG_CMD_DATE)
-
/*
* Convert between century and "century bits" (CB1 and CB0). These routines
* assume years are in the range 1900 - 2299.
}
rtc_dump("end reset");
}
-#endif /* CONFIG_RTC_M41T60 && CONFIG_SYS_I2C_RTC_ADDR && CONFIG_CMD_DATE */
#include <rtc.h>
#include <i2c.h>
-#if defined(CONFIG_CMD_DATE)
-
#define M41T62_REG_SSEC 0
#define M41T62_REG_SEC 1
#define M41T62_REG_MIN 2
val &= ~M41T80_ALHOUR_HT;
i2c_write(CONFIG_SYS_I2C_RTC_ADDR, M41T62_REG_ALARM_HOUR, 1, &val, 1);
}
-
-#endif
#include <rtc.h>
#include <config.h>
-#if defined(CONFIG_CMD_DATE)
-
static uchar rtc_read (uchar reg);
static void rtc_write (uchar reg, uchar val);
*(unsigned char *)
((CONFIG_SYS_NVRAM_BASE_ADDR + CONFIG_SYS_NVRAM_SIZE - 8) + reg) = val;
}
-
-#endif
#include <rtc.h>
#include <i2c.h>
-#if defined(CONFIG_CMD_DATE)
-
#ifndef CONFIG_SYS_I2C_RTC_ADDR
#define CONFIG_SYS_I2C_RTC_ADDR 0x50
#endif
void rtc_reset (void)
{
}
-
-#endif
#define out8(p, v) outb(v, p)
#endif
-#if defined(CONFIG_CMD_DATE)
-
/* Set this to 1 to clear the CMOS RAM */
#define CLEAR_CMOS 0
mc146818_write8(RTC_YEAR, bin2bcd(tmp->tm_year % 100));
mc146818_write8(RTC_MONTH, bin2bcd(tmp->tm_mon));
- mc146818_write8(RTC_DAY_OF_WEEK, bin2bcd(tmp->tm_wday));
+ /* Sunday = 1, Saturday = 7 */
+ mc146818_write8(RTC_DAY_OF_WEEK, bin2bcd(tmp->tm_wday + 1));
mc146818_write8(RTC_DATE_OF_MONTH, bin2bcd(tmp->tm_mday));
mc146818_write8(RTC_HOURS, bin2bcd(tmp->tm_hour));
mc146818_write8(RTC_MINUTES, bin2bcd(tmp->tm_min));
/* Clear any pending interrupts */
mc146818_read8(RTC_CONFIG_C);
}
-#endif /* CONFIG_CMD_DATE */
#ifdef CONFIG_DM_RTC
#include <common.h>
-#if defined(CONFIG_CMD_DATE)
-
#include <command.h>
#include <rtc.h>
#include <asm/immap.h>
rtc->cr |= RTC_CR_SWR;
}
-
-#endif /* CONFIG_MCFRTC && CONFIG_CMD_DATE */
rtc_write(d++, *s++);
}
-#if defined(CONFIG_CMD_DATE)
-
/* ------------------------------------------------------------------------- */
int rtc_get (struct rtc_time *tmp)
wd_value = RTC_WDS | ((multi & 0x1F) << 2) | (res & 0x3);
rtc_write(RTC_WATCHDOG, wd_value);
}
-
-#endif
#include <rtc.h>
#include <i2c.h>
-#if defined(CONFIG_CMD_DATE)
-
static uchar rtc_read (uchar reg);
static void rtc_write (uchar reg, uchar val);
{
i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val);
}
-
-#endif
#include <rtc.h>
#include <i2c.h>
-#if defined(CONFIG_CMD_DATE)
/*
* Reads are always done starting with register 15, which requires some
* jumping-through-hoops to access the data correctly.
if (!setup_done)
rs5c372_enable();
}
-
-#endif
#include <rtc.h>
#include <i2c.h>
-#if defined(CONFIG_CMD_DATE)
-
/*---------------------------------------------------------------------*/
#undef DEBUG_RTC
printf("Error writing to RTC\n");
}
-
-#endif /* CONFIG_RTC_RX8025 && CONFIG_CMD_DATE */
#include <common.h>
#include <command.h>
-#if (defined(CONFIG_CMD_DATE))
-
#include <asm/arch/s3c24x0_cpu.h>
#include <rtc.h>
writeb((readb(&rtc->rtccon) & ~0x06) | 0x08, &rtc->rtccon);
writeb(readb(&rtc->rtccon) & ~(0x08 | 0x01), &rtc->rtccon);
}
-
-#endif
#include <rtc.h>
#include <i2c.h>
-#if defined(CONFIG_CMD_DATE)
-
#define CCR_SEC 0
#define CCR_MIN 1
#define CCR_HOUR 2
* Nothing to do
*/
}
-
-#endif
*/
#include <common.h>
+#include <console.h>
#include <dm.h>
#include <fdtdec.h>
#include <lcd.h>
os_tty_raw(0, state->term_raw == STATE_TERM_RAW_WITH_SIGS);
priv->start_of_line = 0;
+ if (state->term_raw != STATE_TERM_RAW)
+ disable_ctrlc(1);
+
return 0;
}
menu "TPM support"
-comment "Please select only one TPM revision"
- depends on TPM_V1 && TPM_V2
-
config TPM_V1
bool "TPMv1.x support"
depends on TPM
Major TPM versions are not compatible at all, choose either
one or the other. This option enables TPMv1.x drivers/commands.
-if TPM_V1 && !TPM_V2
+if TPM_V1
config TPM_TIS_SANDBOX
bool "Enable sandbox TPM driver"
depends on TPM_V1 && SANDBOX
+ default y
help
This driver emulates a TPMv1.x, providing access to base functions
such as reading and writing TPM private data. This is enough to
config TPM_TIS_LPC
bool "Enable support for Infineon SLB9635/45 TPMs on LPC"
depends on TPM_V1 && X86
- select TPM_DRIVER_SELECTED
help
This driver supports Infineon TPM devices connected on the LPC bus.
The usual tpm operations and the 'tpm' command can be used to talk
config TPM_V2
bool "TPMv2.x support"
depends on TPM
+ default y
help
Major TPM versions are not compatible at all, choose either
one or the other. This option enables TPMv2.x drivers/commands.
-if TPM_V2 && !TPM_V1
+if TPM_V2
config TPM2_TIS_SANDBOX
bool "Enable sandbox TPMv2.x driver"
depends on TPM_V2 && SANDBOX
- select TPM_DRIVER_SELECTED
+ default y
help
This driver emulates a TPMv2.x, providing access to base functions
such as basic configuration, PCR extension and PCR read. Extended
config TPM2_TIS_SPI
bool "Enable support for TPMv2.x SPI chips"
depends on TPM_V2 && DM_SPI
- select TPM_DRIVER_SELECTED
help
This driver supports TPMv2.x devices connected on the SPI bus.
The usual TPM operations and the 'tpm' command can be used to talk
#include <common.h>
#include <dm.h>
#include <linux/unaligned/be_byteshift.h>
-#if defined(CONFIG_TPM_V1)
#include <tpm-v1.h>
-#elif defined(CONFIG_TPM_V2)
#include <tpm-v2.h>
-#endif
#include "tpm_internal.h"
int tpm_open(struct udevice *dev)
*recv += sizeof(rc);
/* Add trailing \0 */
- *recv = '\0';
+ *recv = NULL;
return 0;
}
struct sandbox_tpm2 *tpm = dev_get_priv(dev);
struct tpm_chip_priv *priv = dev_get_uclass_priv(dev);
+ /* Use the TPM v2 stack */
+ priv->version = TPM_V2;
+
memset(tpm, 0, sizeof(*tpm));
priv->pcr_count = 32;
static int tpm_tis_spi_open(struct udevice *dev)
{
struct tpm_chip *chip = dev_get_priv(dev);
+ struct tpm_chip_priv *priv = dev_get_uclass_priv(dev);
if (chip->is_open)
return -EBUSY;
struct tpm_chip *chip = dev_get_priv(dev);
int ret;
+ /* Use the TPM v2 stack */
+ priv->version = TPM_V2;
+
if (IS_ENABLED(CONFIG_DM_GPIO)) {
struct gpio_desc reset_gpio;
endchoice
choice
- prompt "Location of uncompressed DTBs "
+ prompt "Location of uncompressed DTBs"
depends on (SPL_MULTI_DTB_FIT_GZIP || SPL_MULTI_DTB_FIT_LZO)
default SPL_MULTI_DTB_FIT_DYN_ALLOC if SYS_MALLOC_F
*/
__weak enum env_location env_get_location(enum env_operation op, int prio)
{
- switch (op) {
- case ENVOP_GET_CHAR:
- case ENVOP_INIT:
- case ENVOP_LOAD:
- if (prio >= ARRAY_SIZE(env_locations))
- return ENVL_UNKNOWN;
-
- gd->env_load_location = env_locations[prio];
- return gd->env_load_location;
-
- case ENVOP_SAVE:
- return gd->env_load_location;
- }
+ if (prio >= ARRAY_SIZE(env_locations))
+ return ENVL_UNKNOWN;
+
+ gd->env_load_prio = prio;
- return ENVL_UNKNOWN;
+ return env_locations[prio];
}
return 0;
}
+ /*
+ * In case of invalid environment, we set the 'default' env location
+ * to the highest priority. In this way, next calls to env_save()
+ * will restore the environment at the right place.
+ */
+ env_get_location(ENVOP_LOAD, 0);
+
return -ENODEV;
}
int env_save(void)
{
struct env_driver *drv;
- int prio;
- for (prio = 0; (drv = env_driver_lookup(ENVOP_SAVE, prio)); prio++) {
+ drv = env_driver_lookup(ENVOP_SAVE, gd->env_load_prio);
+ if (drv) {
int ret;
if (!drv->save)
- continue;
+ return -ENODEV;
if (!env_has_inited(drv->location))
- continue;
+ return -ENODEV;
printf("Saving Environment to %s... ", drv->name);
ret = drv->save();
volume_info volinfo;
fsdata datablock;
fsdata *mydata = &datablock;
- int cursect;
+ int cursect, i;
int ret = -1, name_len;
char l_filename[VFAT_MAXLEN_BYTES];
+ char bad[2] = " ";
+ const char illegal[] = "<>:\"/\\|?*";
*actwrite = size;
dir_curclust = 0;
}
dentptr = (dir_entry *) do_fat_read_at_block;
+ /* Strip leading (back-)slashes */
+ while ISDIRDELIM(*filename)
+ ++filename;
+ /* Check that the filename is valid */
+ for (i = 0; i < strlen(illegal); ++i) {
+ *bad = illegal[i];
+ if (strstr(filename, bad)) {
+ printf("FAT: illegal filename (%s)\n", filename);
+ return -1;
+ }
+ }
+
name_len = strlen(filename);
if (name_len >= VFAT_MAXLEN_BYTES)
name_len = VFAT_MAXLEN_BYTES - 1;
unsigned long env_addr; /* Address of Environment struct */
unsigned long env_valid; /* Environment valid? enum env_valid */
unsigned long env_has_init; /* Bitmask of boolean of struct env_location offsets */
- int env_load_location;
+ int env_load_prio; /* Priority of the loaded environment */
unsigned long ram_base; /* Base address of RAM used by U-Boot */
unsigned long ram_top; /* Top address of RAM used by U-Boot */
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
#else
#define CONFIG_SPL_FLUSH_IMAGE
-#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
#define CONFIG_SPL_PAD_TO 0x40000
#define CONFIG_SPL_MAX_SIZE 0x28000
#ifdef CONFIG_RAMBOOT_PBL
#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xqds/t1024_pbi.cfg
#define CONFIG_SPL_FLUSH_IMAGE
-#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
#define CONFIG_SPL_PAD_TO 0x40000
#define CONFIG_SPL_MAX_SIZE 0x28000
#ifdef CONFIG_RAMBOOT_PBL
#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xrdb/t1024_pbi.cfg
#define CONFIG_SPL_FLUSH_IMAGE
-#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
#define CONFIG_SPL_PAD_TO 0x40000
#define CONFIG_SPL_MAX_SIZE 0x28000
#endif
#define CONFIG_SPL_FLUSH_IMAGE
-#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
#define CONFIG_SPL_PAD_TO 0x40000
#define CONFIG_SPL_MAX_SIZE 0x28000
#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xqds/t208x_pbi.cfg
#define CONFIG_SPL_FLUSH_IMAGE
-#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
#define CONFIG_SPL_PAD_TO 0x40000
#define CONFIG_SPL_MAX_SIZE 0x28000
#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xrdb/t2080_pbi.cfg
#define CONFIG_SPL_FLUSH_IMAGE
-#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
#define CONFIG_SPL_PAD_TO 0x40000
#define CONFIG_SPL_MAX_SIZE 0x28000
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
#else
#define CONFIG_SPL_FLUSH_IMAGE
-#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
#define CONFIG_SPL_PAD_TO 0x40000
#define CONFIG_SPL_MAX_SIZE 0x28000
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
#else
#define CONFIG_SPL_FLUSH_IMAGE
-#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
#define CONFIG_SPL_PAD_TO 0x40000
#define CONFIG_SPL_MAX_SIZE 0x28000
/* SD boot SPL */
#ifdef CONFIG_SD_BOOT
-#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
#define CONFIG_SPL_TEXT_BASE 0x10000000
#define CONFIG_SPL_MAX_SIZE 0x17000
/* NAND SPL */
#ifdef CONFIG_NAND_BOOT
#define CONFIG_SPL_PBL_PAD
-#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
#define CONFIG_SPL_TEXT_BASE 0x10000000
#define CONFIG_SPL_MAX_SIZE 0x1a000
#define CONFIG_SPL_STACK 0x1001d000
#define SPL_NO_USB
#define SPL_NO_SATA
#endif
-#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_NAND_BOOT))
+#if defined(CONFIG_SPL_BUILD) && \
+ (defined(CONFIG_NAND_BOOT) || defined(CONFIG_QSPI_BOOT))
#define SPL_NO_MMC
#endif
-#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SD_BOOT))
+#if defined(CONFIG_SPL_BUILD) && \
+ !defined(CONFIG_SPL_FSL_LS_PPA)
#define SPL_NO_IFC
#endif
/* SD boot SPL */
#ifdef CONFIG_SD_BOOT
-#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_ENV_SUPPORT
-#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
-#define CONFIG_SPL_WATCHDOG_SUPPORT
-#define CONFIG_SPL_I2C_SUPPORT
-#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
-
-#define CONFIG_SPL_MMC_SUPPORT
#define CONFIG_SPL_TEXT_BASE 0x10000000
#define CONFIG_SPL_MAX_SIZE 0x1f000 /* 124 KiB */
#define CONFIG_SPL_STACK 0x10020000
#endif /* ifdef CONFIG_SECURE_BOOT */
#endif
+#if defined(CONFIG_QSPI_BOOT) && defined(CONFIG_SPL)
+#define CONFIG_SPL_TARGET "spl/u-boot-spl.pbl"
+#define CONFIG_SPL_TEXT_BASE 0x10000000
+#define CONFIG_SPL_MAX_SIZE 0x1f000
+#define CONFIG_SPL_STACK 0x10020000
+#define CONFIG_SPL_PAD_TO 0x20000
+#define CONFIG_SPL_BSS_START_ADDR 0x8f000000
+#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
+#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
+ CONFIG_SPL_BSS_MAX_SIZE)
+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
+#define CONFIG_SYS_MONITOR_LEN 0x100000
+#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
+#endif
+
/* NAND SPL */
#ifdef CONFIG_NAND_BOOT
#define CONFIG_SPL_PBL_PAD
-#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_ENV_SUPPORT
#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
#endif
-#ifdef CONFIG_RAMBOOT_PBL
-#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1046ardb/ls1046ardb_pbi.cfg
-#endif
-
#ifdef CONFIG_SD_BOOT
+#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1046ardb/ls1046ardb_pbi.cfg
#ifdef CONFIG_EMMC_BOOT
#define CONFIG_SYS_FSL_PBL_RCW \
board/freescale/ls1046ardb/ls1046ardb_rcw_emmc.cfg
#else
#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1046ardb/ls1046ardb_rcw_sd.cfg
#endif
+#elif defined(CONFIG_QSPI_BOOT)
+#define CONFIG_SYS_FSL_PBL_RCW \
+ board/freescale/ls1046ardb/ls1046ardb_rcw_qspi.cfg
+#define CONFIG_SYS_FSL_PBL_PBI \
+ board/freescale/ls1046ardb/ls1046ardb_qspi_pbi.cfg
+#define CONFIG_SYS_UBOOT_BASE 0x40100000
+#define CONFIG_SYS_SPL_ARGS_ADDR 0x90000000
#endif
#ifndef SPL_NO_IFC
#if defined(CONFIG_QSPI_BOOT)
#define CONFIG_BOOTCOMMAND "sf probe 0:0;" \
- "sf read 0x80200000 0xd00000 0x100000;"\
- " fsl_mc apply dpl 0x80200000 &&" \
+ "sf read 0x80001000 0xd00000 0x100000;"\
+ " fsl_mc lazyapply dpl 0x80001000 &&" \
" sf read $kernel_load $kernel_start" \
" $kernel_size && bootm $kernel_load"
#elif defined(CONFIG_SD_BOOT)
-#define CONFIG_BOOTCOMMAND "mmcinfo;mmc read 0x80200000 0x6800 0x800;"\
- " fsl_mc apply dpl 0x80200000 &&" \
+#define CONFIG_BOOTCOMMAND "mmcinfo;mmc read 0x80001000 0x6800 0x800;"\
+ " fsl_mc lazyapply dpl 0x80001000 &&" \
" mmc read $kernel_load $kernel_start" \
" $kernel_size && bootm $kernel_load"
#else /* NOR BOOT*/
-#define CONFIG_BOOTCOMMAND "fsl_mc apply dpl 0x580d00000 &&" \
+#define CONFIG_BOOTCOMMAND "fsl_mc lazyapply dpl 0x580d00000 &&" \
" cp.b $kernel_start $kernel_load" \
" $kernel_size && bootm $kernel_load"
#endif
#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
#define CONFIG_SPL_MAX_SIZE 0x16000
#define CONFIG_SPL_STACK (CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0)
-#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
#define CONFIG_SPL_TEXT_BASE 0x1800a000
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000
"installer=load mmc 0:2 $load_addr " \
"/flex_installer_arm64.itb; " \
"env exists mcinitcmd && run mcinitcmd && " \
- "mmc read 0x80200000 0x6800 0x800;" \
- "fsl_mc apply dpl 0x80200000;" \
+ "mmc read 0x80001000 0x6800 0x800;" \
+ "fsl_mc lazyapply dpl 0x80001000;" \
"bootm $load_addr#ls1088ardb\0" \
"qspi_bootcmd=echo Trying load from qspi..;" \
"sf probe && sf read $load_addr " \
#if defined(CONFIG_QSPI_BOOT)
/* Try to boot an on-QSPI kernel first, then do normal distro boot */
#define CONFIG_BOOTCOMMAND \
- "sf read 0x80200000 0xd00000 0x100000;" \
+ "sf read 0x80001000 0xd00000 0x100000;" \
"env exists mcinitcmd && env exists secureboot " \
" && sf read 0x80780000 0x780000 0x100000 " \
"&& esbc_validate 0x80780000;env exists mcinitcmd " \
- "&& fsl_mc apply dpl 0x80200000;" \
+ "&& fsl_mc lazyapply dpl 0x80001000;" \
"run distro_bootcmd;run qspi_bootcmd;" \
"env exists secureboot && esbc_halt;"
#elif defined(CONFIG_SD_BOOT)
#define CONFIG_BOOTCOMMAND \
"env exists mcinitcmd && mmcinfo; " \
- "mmc read 0x80200000 0x6800 0x800; " \
+ "mmc read 0x80001000 0x6800 0x800; " \
"env exists mcinitcmd && env exists secureboot " \
- " && mmc read 0x80780000 0x3800 0x10 " \
+ " && mmc read 0x80780000 0x3C00 0x10 " \
"&& esbc_validate 0x80780000;env exists mcinitcmd " \
- "&& fsl_mc apply dpl 0x80200000;" \
+ "&& fsl_mc lazyapply dpl 0x80001000;" \
"run distro_bootcmd;run sd_bootcmd;" \
"env exists secureboot && esbc_halt;"
#endif
#define CONFIG_SPL_BSS_MAX_SIZE 0x00100000
#define CONFIG_SPL_MAX_SIZE 0x16000
#define CONFIG_SPL_STACK (CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0)
-#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
#define CONFIG_SPL_TEXT_BASE 0x1800a000
#ifdef CONFIG_NAND_BOOT
/* SPI */
#if defined(CONFIG_FSL_QSPI) || defined(CONFIG_FSL_DSPI)
-#define CONFIG_SPI_FLASH
#ifdef CONFIG_FSL_DSPI
#define CONFIG_SPI_FLASH_STMICRO
#endif
-#ifdef CONFIG_FSL_QSPI
-#define CONFIG_SPI_FLASH_SPANSION
-#endif
#define FSL_QSPI_FLASH_SIZE SZ_64M /* 64MB */
#define FSL_QSPI_FLASH_NUM 2
#endif
#define CONFIG_SYS_NS16550_COM1 MV_UART_CONSOLE_BASE
#endif
-/*
- * Serial Port configuration
- * The following definitions let you select what serial you want to use
- * for your console driver.
- */
-
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \
- 115200,230400, 460800, 921600 }
/* auto boot */
#define CONFIG_PREBOOT
CONFIG_MTDPARTS_DEFAULT " rw ubi.mtd=2,2048\0" \
"x_bootcmd_kernel=nand read 0x6400000 0x100000 0x300000\0" \
"x_bootcmd_usb=usb start\0" \
- "x_bootargs_root=root=ubi0:rootfs rootfstype=ubifs\0" \
- "mtdids="CONFIG_MTDIDS_DEFAULT"\0" \
- "mtdparts="CONFIG_MTDPARTS_DEFAULT"\0"
+ "x_bootargs_root=root=ubi0:rootfs rootfstype=ubifs\0"
/*
* Ethernet Driver configuration
*/
#ifdef __x86_64__
#define EFIAPI __attribute__((ms_abi))
+#define efi_va_list __builtin_ms_va_list
+#define efi_va_start __builtin_ms_va_start
+#define efi_va_arg __builtin_va_arg
+#define efi_va_end __builtin_ms_va_end
#else
#define EFIAPI asmlinkage
+#define efi_va_list va_list
+#define efi_va_start va_start
+#define efi_va_arg va_arg
+#define efi_va_end va_end
#endif /* __x86_64__ */
struct efi_device_path;
#include <asm/setjmp.h>
#endif
+/* UEFI spec version 2.7 */
+#define EFI_SPECIFICATION_VERSION (2 << 16 | 70)
+
/* Types and defines for EFI CreateEvent */
enum efi_timer_delay {
EFI_TIMER_STOP = 0,
struct efi_event;
/* EFI Boot Services table */
+#define EFI_BOOT_SERVICES_SIGNATURE 0x56524553544f4f42
struct efi_boot_services {
struct efi_table_hdr hdr;
efi_status_t (EFIAPI *raise_tpl)(efi_uintn_t new_tpl);
void **handle, ...);
efi_status_t (EFIAPI *uninstall_multiple_protocol_interfaces)(
void *handle, ...);
- efi_status_t (EFIAPI *calculate_crc32)(void *data,
- unsigned long data_size, uint32_t *crc32);
+ efi_status_t (EFIAPI *calculate_crc32)(const void *data,
+ efi_uintn_t data_size,
+ u32 *crc32);
void (EFIAPI *copy_mem)(void *destination, const void *source,
size_t length);
void (EFIAPI *set_mem)(void *buffer, size_t size, uint8_t value);
};
/* EFI Runtime Services table */
-#define EFI_RUNTIME_SERVICES_SIGNATURE 0x5652453544e5552ULL
-#define EFI_RUNTIME_SERVICES_REVISION 0x00010000
+#define EFI_RUNTIME_SERVICES_SIGNATURE 0x56524553544e5552ULL
#define CAPSULE_FLAGS_PERSIST_ACROSS_RESET 0x00010000
#define CAPSULE_FLAGS_POPULATE_SYSTEM_TABLE 0x00020000
struct efi_system_table {
struct efi_table_hdr hdr;
- unsigned long fw_vendor; /* physical addr of wchar_t vendor string */
+ u16 *fw_vendor; /* physical addr of wchar_t vendor string */
u32 fw_revision;
efi_handle_t con_in_handle;
struct efi_simple_input_interface *con_in;
EFI_GUID(0x5b1b31a1, 0x9562, 0x11d2, \
0x8e, 0x3f, 0x00, 0xa0, 0xc9, 0x69, 0x72, 0x3b)
+#define EFI_LOADED_IMAGE_PROTOCOL_REVISION 0x1000
+
struct efi_loaded_image {
u32 revision;
void *parent_handle;
#include <linux/list.h>
+/* Maximum number of configuration tables */
+#define EFI_MAX_CONFIGURATION_TABLES 16
+
int __efi_entry_check(void);
int __efi_exit_check(void);
const char *__efi_nesting(void);
#define EFI_CACHELINE_SIZE 128
#endif
+/* Key identifying current memory map */
+extern efi_uintn_t efi_memory_map_key;
+
extern struct efi_runtime_services efi_runtime_services;
extern struct efi_system_table systab;
/* List of all events */
extern struct list_head efi_events;
+/* Called by bootefi to initialize runtime */
+efi_status_t efi_initialize_system_table(void);
/* Called by bootefi to make console interface available */
int efi_console_register(void);
/* Called by bootefi to make all disk storage accessible as EFI objects */
* Use these to indicate that your code / data should go into the EFI runtime
* section and thus still be available when the OS is running
*/
-#define __efi_runtime_data __attribute__ ((section ("efi_runtime_data")))
-#define __efi_runtime __attribute__ ((section ("efi_runtime_text")))
+#define __efi_runtime_data __attribute__ ((section (".data.efi_runtime")))
+#define __efi_runtime __attribute__ ((section (".text.efi_runtime")))
/* Call this with mmio_ptr as the _pointer_ to a pointer to an MMIO region
* to make it available at runtime */
efi_status_t __efi_runtime EFIAPI efi_get_time(
struct efi_time *time,
struct efi_time_cap *capabilities);
-efi_status_t efi_get_time_init(void);
#ifdef CONFIG_CMD_BOOTEFI_SELFTEST
/*
#endif /* __ASSEMBLER */
+/* ELF register definitions */
+#define R_386_NONE 0
+#define R_386_32 1
+#define R_386_PC32 2
+#define R_386_GOT32 3
+#define R_386_PLT32 4
+#define R_386_COPY 5
+#define R_386_GLOB_DAT 6
+#define R_386_JMP_SLOT 7
+#define R_386_RELATIVE 8
+#define R_386_GOTOFF 9
+#define R_386_GOTPC 10
+#define R_386_NUM 11
+
+/* x86-64 relocation types */
+#define R_X86_64_NONE 0 /* No reloc */
+#define R_X86_64_64 1 /* Direct 64 bit */
+#define R_X86_64_PC32 2 /* PC relative 32 bit signed */
+#define R_X86_64_GOT32 3 /* 32 bit GOT entry */
+#define R_X86_64_PLT32 4 /* 32 bit PLT address */
+#define R_X86_64_COPY 5 /* Copy symbol at runtime */
+#define R_X86_64_GLOB_DAT 6 /* Create GOT entry */
+#define R_X86_64_JUMP_SLOT 7 /* Create PLT entry */
+#define R_X86_64_RELATIVE 8 /* Adjust by program base */
+/* 32 bit signed pc relative offset to GOT */
+#define R_X86_64_GOTPCREL 9
+#define R_X86_64_32 10 /* Direct 32 bit zero extended */
+#define R_X86_64_32S 11 /* Direct 32 bit sign extended */
+#define R_X86_64_16 12 /* Direct 16 bit zero extended */
+#define R_X86_64_PC16 13 /* 16 bit sign extended pc relative */
+#define R_X86_64_8 14 /* Direct 8 bit sign extended */
+#define R_X86_64_PC8 15 /* 8 bit sign extended pc relative */
+
+#define R_X86_64_NUM 16
+
/*
* XXX - PowerPC defines really don't belong in here,
* but we'll put them in for simplicity.
#ifndef __ASSEMBLY__
#ifdef CONFIG_PHY_AQUANTIA
-#include <miiphy.h>
-#include <phy.h>
+#include <phy_interface.h>
#endif
struct spi_slave;
/* copy a filename (allow for "..." notation, limit length) */
void copy_filename(char *dst, const char *src, int size);
+/* check if serverip is specified in filename from the command line */
+int is_serverip_in_cmd(void);
+
+/**
+ * net_parse_bootfile - Parse the bootfile env var / cmd line param
+ *
+ * @param ipaddr - a pointer to the ipaddr to populate if included in bootfile
+ * @param filename - a pointer to the string to save the filename part
+ * @param max_len - The longest - 1 that the filename part can be
+ *
+ * return 1 if parsed, 0 if bootfile is empty
+ */
+int net_parse_bootfile(struct in_addr *ipaddr, char *filename, int max_len);
+
/* get a random source port */
unsigned int random_port(void);
#ifndef _PHY_H
#define _PHY_H
+#include <dm.h>
#include <linux/list.h>
#include <linux/mii.h>
#include <linux/ethtool.h>
#include <linux/mdio.h>
+#include <phy_interface.h>
#define PHY_FIXED_ID 0xa5a55a5a
#endif
-typedef enum {
- PHY_INTERFACE_MODE_MII,
- PHY_INTERFACE_MODE_GMII,
- PHY_INTERFACE_MODE_SGMII,
- PHY_INTERFACE_MODE_SGMII_2500,
- PHY_INTERFACE_MODE_QSGMII,
- PHY_INTERFACE_MODE_TBI,
- PHY_INTERFACE_MODE_RMII,
- PHY_INTERFACE_MODE_RGMII,
- PHY_INTERFACE_MODE_RGMII_ID,
- PHY_INTERFACE_MODE_RGMII_RXID,
- PHY_INTERFACE_MODE_RGMII_TXID,
- PHY_INTERFACE_MODE_RTBI,
- PHY_INTERFACE_MODE_XGMII,
- PHY_INTERFACE_MODE_XAUI,
- PHY_INTERFACE_MODE_RXAUI,
- PHY_INTERFACE_MODE_SFI,
- PHY_INTERFACE_MODE_INTERNAL,
- PHY_INTERFACE_MODE_NONE, /* Must be last */
-
- PHY_INTERFACE_MODE_COUNT,
-} phy_interface_t;
-
-static const char *phy_interface_strings[] = {
- [PHY_INTERFACE_MODE_MII] = "mii",
- [PHY_INTERFACE_MODE_GMII] = "gmii",
- [PHY_INTERFACE_MODE_SGMII] = "sgmii",
- [PHY_INTERFACE_MODE_SGMII_2500] = "sgmii-2500",
- [PHY_INTERFACE_MODE_QSGMII] = "qsgmii",
- [PHY_INTERFACE_MODE_TBI] = "tbi",
- [PHY_INTERFACE_MODE_RMII] = "rmii",
- [PHY_INTERFACE_MODE_RGMII] = "rgmii",
- [PHY_INTERFACE_MODE_RGMII_ID] = "rgmii-id",
- [PHY_INTERFACE_MODE_RGMII_RXID] = "rgmii-rxid",
- [PHY_INTERFACE_MODE_RGMII_TXID] = "rgmii-txid",
- [PHY_INTERFACE_MODE_RTBI] = "rtbi",
- [PHY_INTERFACE_MODE_XGMII] = "xgmii",
- [PHY_INTERFACE_MODE_XAUI] = "xaui",
- [PHY_INTERFACE_MODE_RXAUI] = "rxaui",
- [PHY_INTERFACE_MODE_SFI] = "sfi",
- [PHY_INTERFACE_MODE_INTERNAL] = "internal",
- [PHY_INTERFACE_MODE_NONE] = "",
-};
-
-static inline const char *phy_string_for_interface(phy_interface_t i)
-{
- /* Default to unknown */
- if (i > PHY_INTERFACE_MODE_NONE)
- i = PHY_INTERFACE_MODE_NONE;
-
- return phy_interface_strings[i];
-}
-
-
struct phy_device;
#define MDIO_NAME_LEN 32
#ifdef CONFIG_DM_ETH
struct udevice *dev;
+ ofnode node;
#else
struct eth_device *dev;
#endif
struct phy_device *phy_connect(struct mii_dev *bus, int addr,
struct udevice *dev,
phy_interface_t interface);
+static inline ofnode phy_get_ofnode(struct phy_device *phydev)
+{
+ if (ofnode_valid(phydev->node))
+ return phydev->node;
+ else
+ return dev_ofnode(phydev->dev);
+}
#else
void phy_connect_dev(struct phy_device *phydev, struct eth_device *dev);
struct phy_device *phy_connect(struct mii_dev *bus, int addr,
struct eth_device *dev,
phy_interface_t interface);
+static inline ofnode phy_get_ofnode(struct phy_device *phydev)
+{
+ return ofnode_null();
+}
#endif
int phy_startup(struct phy_device *phydev);
int phy_config(struct phy_device *phydev);
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ * Andy Fleming <afleming@gmail.com>
+ *
+ * This file pretty much stolen from Linux's mii.h/ethtool.h/phy.h
+ */
+
+#ifndef _PHY_INTERFACE_H
+#define _PHY_INTERFACE_H
+
+typedef enum {
+ PHY_INTERFACE_MODE_MII,
+ PHY_INTERFACE_MODE_GMII,
+ PHY_INTERFACE_MODE_SGMII,
+ PHY_INTERFACE_MODE_SGMII_2500,
+ PHY_INTERFACE_MODE_QSGMII,
+ PHY_INTERFACE_MODE_TBI,
+ PHY_INTERFACE_MODE_RMII,
+ PHY_INTERFACE_MODE_RGMII,
+ PHY_INTERFACE_MODE_RGMII_ID,
+ PHY_INTERFACE_MODE_RGMII_RXID,
+ PHY_INTERFACE_MODE_RGMII_TXID,
+ PHY_INTERFACE_MODE_RTBI,
+ PHY_INTERFACE_MODE_XGMII,
+ PHY_INTERFACE_MODE_XAUI,
+ PHY_INTERFACE_MODE_RXAUI,
+ PHY_INTERFACE_MODE_SFI,
+ PHY_INTERFACE_MODE_INTERNAL,
+ PHY_INTERFACE_MODE_NONE, /* Must be last */
+
+ PHY_INTERFACE_MODE_COUNT,
+} phy_interface_t;
+
+static const char * const phy_interface_strings[] = {
+ [PHY_INTERFACE_MODE_MII] = "mii",
+ [PHY_INTERFACE_MODE_GMII] = "gmii",
+ [PHY_INTERFACE_MODE_SGMII] = "sgmii",
+ [PHY_INTERFACE_MODE_SGMII_2500] = "sgmii-2500",
+ [PHY_INTERFACE_MODE_QSGMII] = "qsgmii",
+ [PHY_INTERFACE_MODE_TBI] = "tbi",
+ [PHY_INTERFACE_MODE_RMII] = "rmii",
+ [PHY_INTERFACE_MODE_RGMII] = "rgmii",
+ [PHY_INTERFACE_MODE_RGMII_ID] = "rgmii-id",
+ [PHY_INTERFACE_MODE_RGMII_RXID] = "rgmii-rxid",
+ [PHY_INTERFACE_MODE_RGMII_TXID] = "rgmii-txid",
+ [PHY_INTERFACE_MODE_RTBI] = "rtbi",
+ [PHY_INTERFACE_MODE_XGMII] = "xgmii",
+ [PHY_INTERFACE_MODE_XAUI] = "xaui",
+ [PHY_INTERFACE_MODE_RXAUI] = "rxaui",
+ [PHY_INTERFACE_MODE_SFI] = "sfi",
+ [PHY_INTERFACE_MODE_INTERNAL] = "internal",
+ [PHY_INTERFACE_MODE_NONE] = "",
+};
+
+static inline const char *phy_string_for_interface(phy_interface_t i)
+{
+ /* Default to unknown */
+ if (i > PHY_INTERFACE_MODE_NONE)
+ i = PHY_INTERFACE_MODE_NONE;
+
+ return phy_interface_strings[i];
+}
+
+#endif /* _PHY_INTERFACE_H */
/* Max buffer size supported by our tpm */
#define TPM_DEV_BUFSIZE 1260
+/**
+ * enum tpm_version - The version of the TPM stack to be used
+ * @TPM_V1: Use TPM v1.x stack
+ * @TPM_V2: Use TPM v2.x stack
+ */
+enum tpm_version {
+ TPM_V1 = 0,
+ TPM_V2,
+};
+
/**
* struct tpm_chip_priv - Information about a TPM, stored by the uclass
*
* communcation is attempted. If the device has an xfer() method, this is
* not needed. There is no need to set up @buf.
*
+ * @version: TPM stack to be used
* @duration_ms: Length of each duration type in milliseconds
* @retry_time_ms: Time to wait before retrying receive
+ * @buf: Buffer used during the exchanges with the chip
* @pcr_count: Number of PCR per bank
* @pcr_select_min: Minimum size in bytes of the pcrSelect array
- * @buf: Buffer used during the exchanges with the chip
*/
struct tpm_chip_priv {
+ enum tpm_version version;
+
uint duration_ms[TPM_DURATION_COUNT];
uint retry_time_ms;
-#if defined(CONFIG_TPM_V2)
+ u8 buf[TPM_DEV_BUFSIZE + sizeof(u8)]; /* Max buffer size + addr */
+
+ /* TPM v2 specific data */
uint pcr_count;
uint pcr_select_min;
-#endif
- u8 buf[TPM_DEV_BUFSIZE + sizeof(u8)]; /* Max buffer size + addr */
};
/**
* After all commands have been completed the caller should call
* close().
*
- * @dev: Device to close
+ * @dev: Device to open
* @return 0 ok OK, -ve on error
*/
int (*open)(struct udevice *dev);
int tpm_init(void);
/**
- * Retrieve the array containing all the commands.
+ * Retrieve the array containing all the v1 (resp. v2) commands.
*
* @return a cmd_tbl_t array.
*/
-cmd_tbl_t *get_tpm_commands(unsigned int *size);
+#if defined(CONFIG_TPM_V1)
+cmd_tbl_t *get_tpm1_commands(unsigned int *size);
+#else
+static inline cmd_tbl_t *get_tpm1_commands(unsigned int *size)
+{
+ return NULL;
+}
+#endif
+#if defined(CONFIG_TPM_V2)
+cmd_tbl_t *get_tpm2_commands(unsigned int *size);
+#else
+static inline cmd_tbl_t *get_tpm2_commands(unsigned int *size)
+{
+ return NULL;
+}
+#endif
#endif /* __TPM_COMMON_H */
config FDT_FIXUP_PARTITIONS
bool "overwrite MTD partitions in DTS through defined in 'mtdparts'"
depends on OF_LIBFDT
- default n
+ depends on CMD_MTDPARTS
help
Allow overwriting defined partitions in the device tree blob
using partition info defined in the 'mtdparts' environment
return ret;
if (!bdev)
return -ENOENT;
+ /* Set the DM_FLAG_NAME_ALLOCED flag to avoid a memory leak */
+ device_set_name_alloced(bdev);
/* Allocate priv */
ret = device_probe(bdev);
if (ret)
config EFI_LOADER
bool "Support running EFI Applications in U-Boot"
depends on (ARM || X86 || RISCV) && OF_LIBFDT
- # We do not support bootefi booting ARMv7 in non-secure mode
- depends on !ARMV7_NONSEC
# We need EFI_STUB_64BIT to be set on x86_64 with EFI_STUB
depends on !EFI_STUB || !X86_64 || EFI_STUB_64BIT
# We need EFI_STUB_32BIT to be set on x86_32 with EFI_STUB
# This file only gets included with CONFIG_EFI_LOADER set, so all
# object inclusion implicitly depends on it
+CFLAGS_efi_boottime.o += \
+ -DFW_VERSION="0x$(VERSION)" \
+ -DFW_PATCHLEVEL="0x$(PATCHLEVEL)"
CFLAGS_helloworld.o := $(CFLAGS_EFI) -Os -ffreestanding
CFLAGS_REMOVE_helloworld.o := $(CFLAGS_NON_EFI) -Os
*/
static bool efi_is_direct_boot = true;
-/*
- * EFI can pass arbitrary additional "tables" containing vendor specific
- * information to the payload. One such table is the FDT table which contains
- * a pointer to a flattened device tree blob.
- *
- * In most cases we want to pass an FDT to the payload, so reserve one slot of
- * config table space for it. The pointer gets populated by do_bootefi_exec().
- */
-static struct efi_configuration_table __efi_runtime_data efi_conf_table[16];
-
#ifdef CONFIG_ARM
/*
* The "gd" pointer lives in a register on ARM and AArch64 that we declare
return indent_string(--nesting_level);
}
+/**
+ * efi_update_table_header_crc32() - Update CRC32 in table header
+ *
+ * @table: EFI table
+ */
+static void efi_update_table_header_crc32(struct efi_table_hdr *table)
+{
+ table->crc32 = 0;
+ table->crc32 = crc32(0, (const unsigned char *)table,
+ table->headersize);
+}
+
/**
* efi_queue_event() - queue an EFI event
* @event: event to signal
event->is_queued = false;
}
+/**
+ * is_valid_tpl() - check if the task priority level is valid
+ *
+ * @tpl: TPL level to check
+ * ReturnValue: status code
+ */
+efi_status_t is_valid_tpl(efi_uintn_t tpl)
+{
+ switch (tpl) {
+ case TPL_APPLICATION:
+ case TPL_CALLBACK:
+ case TPL_NOTIFY:
+ case TPL_HIGH_LEVEL:
+ return EFI_SUCCESS;
+ default:
+ return EFI_INVALID_PARAMETER;
+ }
+}
+
/**
* efi_signal_event() - signal an EFI event
* @event: event to signal
if (event == NULL)
return EFI_INVALID_PARAMETER;
- if ((type & EVT_NOTIFY_SIGNAL) && (type & EVT_NOTIFY_WAIT))
+ switch (type) {
+ case 0:
+ case EVT_TIMER:
+ case EVT_NOTIFY_SIGNAL:
+ case EVT_TIMER | EVT_NOTIFY_SIGNAL:
+ case EVT_NOTIFY_WAIT:
+ case EVT_TIMER | EVT_NOTIFY_WAIT:
+ case EVT_SIGNAL_EXIT_BOOT_SERVICES:
+ case EVT_SIGNAL_VIRTUAL_ADDRESS_CHANGE:
+ break;
+ default:
return EFI_INVALID_PARAMETER;
+ }
- if ((type & (EVT_NOTIFY_SIGNAL | EVT_NOTIFY_WAIT)) &&
- notify_function == NULL)
+ if (is_valid_tpl(notify_tpl) != EFI_SUCCESS)
return EFI_INVALID_PARAMETER;
evt = calloc(1, sizeof(struct efi_event));
*/
static void efi_remove_configuration_table(int i)
{
- struct efi_configuration_table *this = &efi_conf_table[i];
- struct efi_configuration_table *next = &efi_conf_table[i + 1];
- struct efi_configuration_table *end = &efi_conf_table[systab.nr_tables];
+ struct efi_configuration_table *this = &systab.tables[i];
+ struct efi_configuration_table *next = &systab.tables[i + 1];
+ struct efi_configuration_table *end = &systab.tables[systab.nr_tables];
memmove(this, next, (ulong)end - (ulong)next);
systab.nr_tables--;
/* Check for guid override */
for (i = 0; i < systab.nr_tables; i++) {
- if (!guidcmp(guid, &efi_conf_table[i].guid)) {
+ if (!guidcmp(guid, &systab.tables[i].guid)) {
if (table)
- efi_conf_table[i].table = table;
+ systab.tables[i].table = table;
else
efi_remove_configuration_table(i);
goto out;
return EFI_NOT_FOUND;
/* No override, check for overflow */
- if (i >= ARRAY_SIZE(efi_conf_table))
+ if (i >= EFI_MAX_CONFIGURATION_TABLES)
return EFI_OUT_OF_RESOURCES;
/* Add a new entry */
- memcpy(&efi_conf_table[i].guid, guid, sizeof(*guid));
- efi_conf_table[i].table = table;
+ memcpy(&systab.tables[i].guid, guid, sizeof(*guid));
+ systab.tables[i].table = table;
systab.nr_tables = i + 1;
out:
+ /* systab.nr_tables may have changed. So we need to update the crc32 */
+ efi_update_table_header_crc32(&systab.hdr);
+
/* Notify that the configuration table was changed */
list_for_each_entry(evt, &efi_events, link) {
if (evt->group && !guidcmp(evt->group, guid)) {
/* efi_exit() assumes that the handle points to the info */
obj->handle = info;
+ info->revision = EFI_LOADED_IMAGE_PROTOCOL_REVISION;
info->file_path = file_path;
if (device_path) {
EFI_ENTRY("%p, %ld", image_handle, map_key);
+ /* Check that the caller has read the current memory map */
+ if (map_key != efi_memory_map_key)
+ return EFI_INVALID_PARAMETER;
+
/* Make sure that notification functions are not called anymore */
efi_tpl = TPL_HIGH_LEVEL;
systab.boottime = NULL;
/* Recalculate CRC32 */
- systab.hdr.crc32 = 0;
- systab.hdr.crc32 = crc32(0, (const unsigned char *)&systab,
- sizeof(struct efi_system_table));
+ efi_update_table_header_crc32(&systab.hdr);
/* Give the payload some time to boot */
efi_set_watchdog(0);
{
EFI_ENTRY("%p", handle);
- va_list argptr;
+ efi_va_list argptr;
const efi_guid_t *protocol;
void *protocol_interface;
efi_status_t r = EFI_SUCCESS;
if (!handle)
return EFI_EXIT(EFI_INVALID_PARAMETER);
- va_start(argptr, handle);
+ efi_va_start(argptr, handle);
for (;;) {
- protocol = va_arg(argptr, efi_guid_t*);
+ protocol = efi_va_arg(argptr, efi_guid_t*);
if (!protocol)
break;
- protocol_interface = va_arg(argptr, void*);
+ protocol_interface = efi_va_arg(argptr, void*);
r = EFI_CALL(efi_install_protocol_interface(
handle, protocol,
EFI_NATIVE_INTERFACE,
break;
i++;
}
- va_end(argptr);
+ efi_va_end(argptr);
if (r == EFI_SUCCESS)
return EFI_EXIT(r);
/* If an error occurred undo all changes. */
- va_start(argptr, handle);
+ efi_va_start(argptr, handle);
for (; i; --i) {
- protocol = va_arg(argptr, efi_guid_t*);
- protocol_interface = va_arg(argptr, void*);
+ protocol = efi_va_arg(argptr, efi_guid_t*);
+ protocol_interface = efi_va_arg(argptr, void*);
EFI_CALL(efi_uninstall_protocol_interface(handle, protocol,
protocol_interface));
}
- va_end(argptr);
+ efi_va_end(argptr);
return EFI_EXIT(r);
}
{
EFI_ENTRY("%p", handle);
- va_list argptr;
+ efi_va_list argptr;
const efi_guid_t *protocol;
void *protocol_interface;
efi_status_t r = EFI_SUCCESS;
if (!handle)
return EFI_EXIT(EFI_INVALID_PARAMETER);
- va_start(argptr, handle);
+ efi_va_start(argptr, handle);
for (;;) {
- protocol = va_arg(argptr, efi_guid_t*);
+ protocol = efi_va_arg(argptr, efi_guid_t*);
if (!protocol)
break;
- protocol_interface = va_arg(argptr, void*);
+ protocol_interface = efi_va_arg(argptr, void*);
r = EFI_CALL(efi_uninstall_protocol_interface(
handle, protocol,
protocol_interface));
break;
i++;
}
- va_end(argptr);
+ efi_va_end(argptr);
if (r == EFI_SUCCESS)
return EFI_EXIT(r);
/* If an error occurred undo all changes. */
- va_start(argptr, handle);
+ efi_va_start(argptr, handle);
for (; i; --i) {
- protocol = va_arg(argptr, efi_guid_t*);
- protocol_interface = va_arg(argptr, void*);
+ protocol = efi_va_arg(argptr, efi_guid_t*);
+ protocol_interface = efi_va_arg(argptr, void*);
EFI_CALL(efi_install_protocol_interface(&handle, protocol,
EFI_NATIVE_INTERFACE,
protocol_interface));
}
- va_end(argptr);
+ efi_va_end(argptr);
return EFI_EXIT(r);
}
*
* Return: status code
*/
-static efi_status_t EFIAPI efi_calculate_crc32(void *data,
- unsigned long data_size,
- uint32_t *crc32_p)
+static efi_status_t EFIAPI efi_calculate_crc32(const void *data,
+ efi_uintn_t data_size,
+ u32 *crc32_p)
{
- EFI_ENTRY("%p, %ld", data, data_size);
+ EFI_ENTRY("%p, %zu", data, data_size);
*crc32_p = crc32(0, data, data_size);
return EFI_EXIT(EFI_SUCCESS);
}
return EFI_EXIT(r);
}
-static const struct efi_boot_services efi_boot_services = {
+static struct efi_boot_services efi_boot_services = {
.hdr = {
- .headersize = sizeof(struct efi_table_hdr),
+ .signature = EFI_BOOT_SERVICES_SIGNATURE,
+ .revision = EFI_SPECIFICATION_VERSION,
+ .headersize = sizeof(struct efi_boot_services),
},
.raise_tpl = efi_raise_tpl,
.restore_tpl = efi_restore_tpl,
.create_event_ex = efi_create_event_ex,
};
-static uint16_t __efi_runtime_data firmware_vendor[] = L"Das U-Boot";
+static u16 __efi_runtime_data firmware_vendor[] = L"Das U-Boot";
struct efi_system_table __efi_runtime_data systab = {
.hdr = {
.signature = EFI_SYSTEM_TABLE_SIGNATURE,
- .revision = 2 << 16 | 70, /* 2.7 */
- .headersize = sizeof(struct efi_table_hdr),
+ .revision = EFI_SPECIFICATION_VERSION,
+ .headersize = sizeof(struct efi_system_table),
},
- .fw_vendor = (long)firmware_vendor,
+ .fw_vendor = firmware_vendor,
+ .fw_revision = FW_VERSION << 16 | FW_PATCHLEVEL << 8,
.con_in = (void *)&efi_con_in,
.con_out = (void *)&efi_con_out,
.std_err = (void *)&efi_con_out,
.runtime = (void *)&efi_runtime_services,
.boottime = (void *)&efi_boot_services,
.nr_tables = 0,
- .tables = (void *)efi_conf_table,
+ .tables = NULL,
};
+
+/**
+ * efi_initialize_system_table() - Initialize system table
+ *
+ * Return Value: status code
+ */
+efi_status_t efi_initialize_system_table(void)
+{
+ efi_status_t ret;
+
+ /* Allocate configuration table array */
+ ret = efi_allocate_pool(EFI_RUNTIME_SERVICES_DATA,
+ EFI_MAX_CONFIGURATION_TABLES *
+ sizeof(struct efi_configuration_table),
+ (void **)&systab.tables);
+
+ /* Set crc32 field in table headers */
+ efi_update_table_header_crc32(&systab.hdr);
+ efi_update_table_header_crc32(&efi_runtime_services.hdr);
+ efi_update_table_header_crc32(&efi_boot_services.hdr);
+
+ return ret;
+}
EFI_ENTRY("%p", this);
printf(ESC"[2J");
+ efi_con_mode.cursor_column = 0;
+ efi_con_mode.cursor_row = 0;
return EFI_EXIT(EFI_SUCCESS);
}
bool extended_verification)
{
EFI_ENTRY("%p, %d", this, extended_verification);
- return EFI_EXIT(EFI_UNSUPPORTED);
+
+ /* Empty input buffer */
+ while (tstc())
+ getc();
+
+ return EFI_EXIT(EFI_SUCCESS);
}
/*
const efi_guid_t efi_file_info_guid = EFI_FILE_INFO_GUID;
static int machines[] = {
-#if defined(CONFIG_ARM64)
+#if defined(__aarch64__)
IMAGE_FILE_MACHINE_ARM64,
-#elif defined(CONFIG_ARM)
+#elif defined(__arm__)
IMAGE_FILE_MACHINE_ARM,
IMAGE_FILE_MACHINE_THUMB,
IMAGE_FILE_MACHINE_ARMNT,
#endif
-#if defined(CONFIG_X86_64)
+#if defined(__x86_64__)
IMAGE_FILE_MACHINE_AMD64,
-#elif defined(CONFIG_X86)
+#elif defined(__i386__)
IMAGE_FILE_MACHINE_I386,
#endif
-#if defined(CONFIG_CPU_RISCV_32)
+#if defined(__riscv) && (__riscv_xlen == 32)
IMAGE_FILE_MACHINE_RISCV32,
#endif
-#if defined(CONFIG_CPU_RISCV_64)
+#if defined(__riscv) && (__riscv_xlen == 64)
IMAGE_FILE_MACHINE_RISCV64,
#endif
0 };
#include <efi_loader.h>
#include <inttypes.h>
#include <malloc.h>
+#include <mapmem.h>
#include <watchdog.h>
#include <linux/list_sort.h>
DECLARE_GLOBAL_DATA_PTR;
+efi_uintn_t efi_memory_map_key;
+
struct efi_mem_list {
struct list_head link;
struct efi_mem_desc desc;
debug("%s: 0x%" PRIx64 " 0x%" PRIx64 " %d %s\n", __func__,
start, pages, memory_type, overlap_only_ram ? "yes" : "no");
+ if (memory_type >= EFI_MAX_MEMORY_TYPE)
+ return EFI_INVALID_PARAMETER;
+
if (!pages)
return start;
+ ++efi_memory_map_key;
newlist = calloc(1, sizeof(*newlist));
newlist->desc.type = memory_type;
newlist->desc.physical_start = start;
efi_status_t r = EFI_SUCCESS;
uint64_t addr;
+ if (!memory)
+ return EFI_INVALID_PARAMETER;
+
switch (type) {
case EFI_ALLOCATE_ANY_PAGES:
/* Any page */
- addr = efi_find_free_memory(len, gd->start_addr_sp);
+ addr = efi_find_free_memory(len, -1ULL);
if (!addr) {
r = EFI_NOT_FOUND;
break;
/* Reserve that map in our memory maps */
ret = efi_add_memory_map(addr, pages, memory_type, true);
if (ret == addr) {
- *memory = addr;
+ *memory = (uintptr_t)map_sysmem(addr, len);
} else {
/* Map would overlap, bail out */
r = EFI_OUT_OF_RESOURCES;
efi_status_t efi_free_pages(uint64_t memory, efi_uintn_t pages)
{
uint64_t r = 0;
+ uint64_t addr = map_to_sysmem((void *)(uintptr_t)memory);
- r = efi_add_memory_map(memory, pages, EFI_CONVENTIONAL_MEMORY, false);
+ r = efi_add_memory_map(addr, pages, EFI_CONVENTIONAL_MEMORY, false);
/* Merging of adjacent free regions is missing */
- if (r == memory)
+ if (r == addr)
return EFI_SUCCESS;
return EFI_NOT_FOUND;
efi_status_t efi_allocate_pool(int pool_type, efi_uintn_t size, void **buffer)
{
efi_status_t r;
- efi_physical_addr_t t;
+ struct efi_pool_allocation *alloc;
u64 num_pages = (size + sizeof(struct efi_pool_allocation) +
EFI_PAGE_MASK) >> EFI_PAGE_SHIFT;
+ if (!buffer)
+ return EFI_INVALID_PARAMETER;
+
if (size == 0) {
*buffer = NULL;
return EFI_SUCCESS;
}
r = efi_allocate_pages(EFI_ALLOCATE_ANY_PAGES, pool_type, num_pages,
- &t);
+ (uint64_t *)&alloc);
if (r == EFI_SUCCESS) {
- struct efi_pool_allocation *alloc = (void *)(uintptr_t)t;
alloc->num_pages = num_pages;
*buffer = alloc->data;
}
struct list_head *lhandle;
efi_uintn_t provided_map_size = *memory_map_size;
+ if (!memory_map_size)
+ return EFI_INVALID_PARAMETER;
+
list_for_each(lhandle, &efi_mem)
map_entries++;
if (provided_map_size < map_size)
return EFI_BUFFER_TOO_SMALL;
+ if (!memory_map)
+ return EFI_INVALID_PARAMETER;
+
if (descriptor_size)
*descriptor_size = sizeof(struct efi_mem_desc);
*descriptor_version = EFI_MEMORY_DESCRIPTOR_VERSION;
/* Copy list into array */
- if (memory_map) {
- /* Return the list in ascending order */
- memory_map = &memory_map[map_entries - 1];
- list_for_each(lhandle, &efi_mem) {
- struct efi_mem_list *lmem;
+ /* Return the list in ascending order */
+ memory_map = &memory_map[map_entries - 1];
+ list_for_each(lhandle, &efi_mem) {
+ struct efi_mem_list *lmem;
- lmem = list_entry(lhandle, struct efi_mem_list, link);
- *memory_map = lmem->desc;
- memory_map--;
- }
+ lmem = list_entry(lhandle, struct efi_mem_list, link);
+ *memory_map = lmem->desc;
+ memory_map--;
}
- *map_key = 0;
+ if (map_key)
+ *map_key = efi_memory_map_key;
return EFI_SUCCESS;
}
}
}
-int efi_memory_init(void)
+/* Add memory regions for U-Boot's memory and for the runtime services code */
+static void add_u_boot_and_runtime(void)
{
unsigned long runtime_start, runtime_end, runtime_pages;
unsigned long uboot_start, uboot_pages;
unsigned long uboot_stack_size = 16 * 1024 * 1024;
- efi_add_known_memory();
-
/* Add U-Boot */
uboot_start = (gd->start_addr_sp - uboot_stack_size) & ~EFI_PAGE_MASK;
uboot_pages = (gd->ram_top - uboot_start) >> EFI_PAGE_SHIFT;
runtime_pages = (runtime_end - runtime_start) >> EFI_PAGE_SHIFT;
efi_add_memory_map(runtime_start, runtime_pages,
EFI_RUNTIME_SERVICES_CODE, false);
+}
+
+int efi_memory_init(void)
+{
+ efi_add_known_memory();
+
+ if (!IS_ENABLED(CONFIG_SANDBOX))
+ add_u_boot_and_runtime();
#ifdef CONFIG_EFI_LOADER_BOUNCE_BUFFER
/* Request a 32bit 64MB bounce buffer region */
memcpy(netobj->net_mode.current_address.mac_addr, eth_get_ethaddr(), 6);
netobj->net_mode.hwaddr_size = ARP_HLEN;
netobj->net_mode.max_packet_size = PKTSIZE;
+ netobj->net_mode.if_type = ARP_ETHER;
netobj->pxe.mode = &netobj->pxe_mode;
if (dhcp_ack)
#include <common.h>
#include <command.h>
#include <dm.h>
+#include <elf.h>
#include <efi_loader.h>
#include <rtc.h>
* TODO(sjg@chromium.org): These defines and structs should come from the elf
* header for each arch (or a generic header) rather than being repeated here.
*/
-#if defined(CONFIG_ARM64)
-#define R_RELATIVE 1027
+#if defined(__aarch64__)
+#define R_RELATIVE R_AARCH64_RELATIVE
#define R_MASK 0xffffffffULL
#define IS_RELA 1
-#elif defined(CONFIG_ARM)
-#define R_RELATIVE 23
+#elif defined(__arm__)
+#define R_RELATIVE R_ARM_RELATIVE
#define R_MASK 0xffULL
-#elif defined(CONFIG_X86)
-#include <asm/elf.h>
+#elif defined(__x86_64__) || defined(__i386__)
#define R_RELATIVE R_386_RELATIVE
#define R_MASK 0xffULL
-#elif defined(CONFIG_RISCV)
-#include <elf.h>
+#elif defined(__riscv)
#define R_RELATIVE R_RISCV_RELATIVE
#define R_MASK 0xffULL
#define IS_RELA 1
u32 foo2;
u32 foo3;
};
-#ifdef CONFIG_CPU_RISCV_32
+#if (__riscv_xlen == 32)
#define R_ABSOLUTE R_RISCV_32
#define SYM_INDEX 8
-#else
+#elif (__riscv_xlen == 64)
#define R_ABSOLUTE R_RISCV_64
#define SYM_INDEX 32
+#else
+#error unknown riscv target
#endif
#else
#error Need to add relocation awareness
while (1) { }
}
+/**
+ * efi_get_time_boottime - get current time
+ *
+ * This function implements the GetTime runtime service.
+ * See the Unified Extensible Firmware Interface (UEFI) specification
+ * for details.
+ *
+ * @time: pointer to structure to receive current time
+ * @capabilities: pointer to structure to receive RTC properties
+ * Return Value: status code
+ */
static efi_status_t EFIAPI efi_get_time_boottime(
struct efi_time *time,
struct efi_time_cap *capabilities)
{
-#if defined(CONFIG_CMD_DATE) && defined(CONFIG_DM_RTC)
- struct rtc_time tm;
+#ifdef CONFIG_DM_RTC
+ efi_status_t ret = EFI_SUCCESS;
int r;
+ struct rtc_time tm;
struct udevice *dev;
EFI_ENTRY("%p %p", time, capabilities);
- r = uclass_get_device(UCLASS_RTC, 0, &dev);
- if (r)
- return EFI_EXIT(EFI_DEVICE_ERROR);
+ if (!time) {
+ ret = EFI_INVALID_PARAMETER;
+ goto out;
+ }
- r = dm_rtc_get(dev, &tm);
- if (r)
- return EFI_EXIT(EFI_DEVICE_ERROR);
+ r = uclass_get_device(UCLASS_RTC, 0, &dev);
+ if (!r)
+ r = dm_rtc_get(dev, &tm);
+ if (r) {
+ ret = EFI_DEVICE_ERROR;
+ goto out;
+ }
memset(time, 0, sizeof(*time));
time->year = tm.tm_year;
time->day = tm.tm_mday;
time->hour = tm.tm_hour;
time->minute = tm.tm_min;
- time->daylight = tm.tm_isdst;
-
- return EFI_EXIT(EFI_SUCCESS);
+ time->second = tm.tm_sec;
+ time->daylight = EFI_TIME_ADJUST_DAYLIGHT;
+ if (tm.tm_isdst > 0)
+ time->daylight |= EFI_TIME_IN_DAYLIGHT;
+ time->timezone = EFI_UNSPECIFIED_TIMEZONE;
+
+ if (capabilities) {
+ /* Set reasonable dummy values */
+ capabilities->resolution = 1; /* 1 Hz */
+ capabilities->accuracy = 100000000; /* 100 ppm */
+ capabilities->sets_to_zero = false;
+ }
+out:
+ return EFI_EXIT(ret);
#else
- return EFI_DEVICE_ERROR;
+ EFI_ENTRY("%p %p", time, capabilities);
+ return EFI_EXIT(EFI_DEVICE_ERROR);
#endif
}
return EFI_DEVICE_ERROR;
}
-efi_status_t __weak efi_get_time_init(void)
-{
- return EFI_SUCCESS;
-}
-
struct efi_runtime_detach_list_struct {
void *ptr;
void *patchto;
struct efi_runtime_services __efi_runtime_data efi_runtime_services = {
.hdr = {
.signature = EFI_RUNTIME_SERVICES_SIGNATURE,
- .revision = EFI_RUNTIME_SERVICES_REVISION,
- .headersize = sizeof(struct efi_table_hdr),
+ .revision = EFI_SPECIFICATION_VERSION,
+ .headersize = sizeof(struct efi_runtime_services),
},
.get_time = &efi_get_time_boottime,
.set_time = (void *)&efi_device_error,
/* Reserve 4kiB page for SMBIOS */
ret = efi_allocate_pages(EFI_ALLOCATE_MAX_ADDRESS,
EFI_RUNTIME_SERVICES_DATA, 1, &dmi);
- if (ret != EFI_SUCCESS)
- return ret;
+
+ if (ret != EFI_SUCCESS) {
+ /* Could not find space in lowmem, use highmem instead */
+ ret = efi_allocate_pages(EFI_ALLOCATE_ANY_PAGES,
+ EFI_RUNTIME_SERVICES_DATA, 1, &dmi);
+
+ if (ret != EFI_SUCCESS)
+ return ret;
+ }
/*
* Generate SMBIOS tables - we know that efi_allocate_pages() returns
-efi_miniapp_file_image.h
+efi_miniapp_file_image_exit.h
+efi_miniapp_file_image_return.h
*.efi
+*.so
obj-$(CONFIG_CMD_BOOTEFI_SELFTEST) += \
efi_selftest.o \
efi_selftest_bitblt.o \
+efi_selftest_config_table.o \
efi_selftest_controllers.o \
efi_selftest_console.o \
+efi_selftest_crc32.o \
efi_selftest_devicepath.o \
efi_selftest_devicepath_util.o \
efi_selftest_events.o \
efi_selftest_fdt.o \
efi_selftest_gop.o \
efi_selftest_manageprotocols.o \
+efi_selftest_rtc.o \
efi_selftest_snp.o \
efi_selftest_textinput.o \
efi_selftest_textoutput.o \
# TODO: As of v2018.01 the relocation code for the EFI application cannot
# be built on x86_64.
-ifeq ($(CONFIG_X86_64),)
+ifeq ($(CONFIG_X86_64)$(CONFIG_SANDBOX),)
ifneq ($(CONFIG_CMD_BOOTEFI_SELFTEST),)
#include <efi_selftest.h>
#include <vsprintf.h>
-/*
- * Constants for test step bitmap
- */
+/* Constants for test step bitmap */
#define EFI_ST_SETUP 1
#define EFI_ST_EXECUTE 2
#define EFI_ST_TEARDOWN 4
*
* The size of the memory map is determined.
* Pool memory is allocated to copy the memory map.
- * The memory amp is copied and the map key is obtained.
+ * The memory map is copied and the map key is obtained.
* The map key is used to exit the boot services.
*/
void efi_st_exit_boot_services(void)
* Check that a test exists.
*
* @testname: name of the test
- * @return: test
+ * @return: test, or NULL if not found
*/
static struct efi_unit_test *find_test(const u16 *testname)
{
*
* @testname name of a single selected test or NULL
* @phase test phase
- * @steps steps to execute
+ * @steps steps to execute (mask with bits from EFI_ST_...)
* failures returns EFI_ST_SUCCESS if all test steps succeeded
*/
void efi_st_do_tests(const u16 *testname, unsigned int phase,
efi_st_printc(EFI_WHITE, "\nSummary: %u failures\n\n", failures);
/* Reset system */
- efi_st_printf("Preparing for reset. Press any key.\n");
+ efi_st_printf("Preparing for reset. Press any key...\n");
efi_st_get_key();
runtime->reset_system(EFI_RESET_WARM, EFI_NOT_READY,
sizeof(reset_message), reset_message);
efi_st_printf("\n");
- efi_st_error("Reset failed.\n");
+ efi_st_error("Reset failed\n");
return EFI_UNSUPPORTED;
}
efi_uintn_t buf_size;
char buf[16] __aligned(ARCH_DMA_MINALIGN);
+ /* Connect controller to virtual disk */
ret = boottime->connect_controller(disk_handle, NULL, NULL, 1);
if (ret != EFI_SUCCESS) {
efi_st_error("Failed to connect controller\n");
return EFI_ST_FAILURE;
}
+
+ /* Get the handle for the partition */
ret = boottime->locate_handle_buffer(
BY_PROTOCOL, &guid_device_path, NULL,
&no_handles, &handles);
efi_st_error("Partition handle not found\n");
return EFI_ST_FAILURE;
}
+
+ /* Open the simple file system protocol */
ret = boottime->open_protocol(handle_partition,
&guid_simple_file_system_protocol,
(void **)&file_system, NULL, NULL,
efi_st_error("Failed to open simple file system protocol\n");
return EFI_ST_FAILURE;
}
+
+ /* Open volume */
ret = file_system->open_volume(file_system, &root);
if (ret != EFI_SUCCESS) {
efi_st_error("Failed to open volume\n");
"Wrong volume label '%ps', expected 'U-BOOT TEST'\n",
system_info.info.volume_label);
}
+
+ /* Read file */
ret = root->open(root, &file, (s16 *)L"hello.txt", EFI_FILE_MODE_READ,
0);
if (ret != EFI_SUCCESS) {
efi_st_error("Failed to read file\n");
return EFI_ST_FAILURE;
}
+ if (buf_size != 13) {
+ efi_st_error("Wrong number of bytes read: %u\n",
+ (unsigned int)buf_size);
+ return EFI_ST_FAILURE;
+ }
if (efi_st_memcmp(buf, "Hello world!", 12)) {
efi_st_error("Unexpected file content\n");
return EFI_ST_FAILURE;
efi_st_error("Failed to close file\n");
return EFI_ST_FAILURE;
}
+
+#ifdef CONFIG_FAT_WRITE
+ /* Write file */
+ ret = root->open(root, &file, (s16 *)L"u-boot.txt",
+ EFI_FILE_MODE_WRITE | EFI_FILE_MODE_CREATE, 0);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Failed to open file\n");
+ return EFI_ST_FAILURE;
+ }
+ buf_size = 7;
+ boottime->set_mem(buf, sizeof(buf), 0);
+ boottime->copy_mem(buf, "U-Boot", buf_size);
+ ret = file->write(file, &buf_size, buf);
+ if (ret != EFI_SUCCESS || buf_size != 7) {
+ efi_st_error("Failed to write file\n");
+ return EFI_ST_FAILURE;
+ }
+ ret = file->close(file);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Failed to close file\n");
+ return EFI_ST_FAILURE;
+ }
+
+ /* Verify file */
+ boottime->set_mem(buf, sizeof(buf), 0);
+ ret = root->open(root, &file, (s16 *)L"u-boot.txt", EFI_FILE_MODE_READ,
+ 0);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Failed to open file\n");
+ return EFI_ST_FAILURE;
+ }
+ buf_size = sizeof(buf) - 1;
+ ret = file->read(file, &buf_size, buf);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Failed to read file\n");
+ return EFI_ST_FAILURE;
+ }
+ if (buf_size != 7) {
+ efi_st_error("Wrong number of bytes read: %u\n",
+ (unsigned int)buf_size);
+ return EFI_ST_FAILURE;
+ }
+ if (efi_st_memcmp(buf, "U-Boot", 7)) {
+ efi_st_error("Unexpected file content %s\n", buf);
+ return EFI_ST_FAILURE;
+ }
+ ret = file->close(file);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Failed to close file\n");
+ return EFI_ST_FAILURE;
+ }
+#else
+ efi_st_todo("CONFIG_FAT_WRITE is not set\n");
+#endif /* CONFIG_FAT_WRITE */
+
+ /* Close volume */
ret = root->close(root);
if (ret != EFI_SUCCESS) {
efi_st_error("Failed to close volume\n");
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * efi_selftest_config_tables
+ *
+ * Copyright (c) 2018 Heinrich Schuchardt <xypron.glpk@gmx.de>
+ *
+ * This test checks the following service:
+ * InstallConfigurationTable.
+ */
+
+#include <efi_selftest.h>
+
+static const struct efi_system_table *sys_table;
+static struct efi_boot_services *boottime;
+
+static efi_guid_t table_guid =
+ EFI_GUID(0xff1c3f9e, 0x795b, 0x1529, 0xf1, 0x55,
+ 0x17, 0x2e, 0x51, 0x6b, 0x49, 0x75);
+
+/*
+ * Notification function, increments the notfication count if parameter
+ * context is provided.
+ *
+ * @event notified event
+ * @context pointer to the notification count
+ */
+static void EFIAPI notify(struct efi_event *event, void *context)
+{
+ unsigned int *count = context;
+
+ if (count)
+ ++*count;
+}
+
+/*
+ * Check crc32 of a table.
+ */
+static int check_table(const void *table)
+{
+ efi_status_t ret;
+ u32 crc32, res;
+ /* Casting from const to not const */
+ struct efi_table_hdr *hdr = (struct efi_table_hdr *)table;
+
+ crc32 = hdr->crc32;
+ /*
+ * Setting the crc32 of the 'const' table to zero is easier than
+ * copying
+ */
+ hdr->crc32 = 0;
+ ret = boottime->calculate_crc32(table, hdr->headersize, &res);
+ /* Reset table crc32 so it stays constant */
+ hdr->crc32 = crc32;
+ if (ret != EFI_ST_SUCCESS) {
+ efi_st_error("CalculateCrc32 failed\n");
+ return EFI_ST_FAILURE;
+ }
+ if (res != crc32) {
+ efi_st_error("Incorrect CRC32\n");
+ return EFI_ST_FAILURE;
+ }
+ return EFI_ST_SUCCESS;
+}
+
+/*
+ * Setup unit test.
+ *
+ * @handle: handle of the loaded image
+ * @systable: system table
+ * @return: EFI_ST_SUCCESS for success
+ */
+static int setup(const efi_handle_t handle,
+ const struct efi_system_table *systable)
+{
+ sys_table = systable;
+ boottime = systable->boottime;
+
+ return EFI_ST_SUCCESS;
+}
+
+/*
+ * Execute unit test.
+ *
+ * A table is installed, updated, removed. The table entry and the
+ * triggering of events is checked.
+ *
+ * @return: EFI_ST_SUCCESS for success
+ */
+static int execute(void)
+{
+ efi_status_t ret;
+ unsigned int counter = 0;
+ struct efi_event *event;
+ void *table;
+ const unsigned int tables[2];
+ efi_uintn_t i;
+ efi_uintn_t tabcnt;
+ efi_uintn_t table_count = sys_table->nr_tables;
+
+ ret = boottime->create_event_ex(0, TPL_NOTIFY,
+ notify, (void *)&counter,
+ &table_guid, &event);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Failed to create event\n");
+ return EFI_ST_FAILURE;
+ }
+
+ /* Try to delete non-existent table */
+ ret = boottime->install_configuration_table(&table_guid, NULL);
+ if (ret != EFI_NOT_FOUND) {
+ efi_st_error("Failed to detect missing table\n");
+ return EFI_ST_FAILURE;
+ }
+ if (counter) {
+ efi_st_error("Notification function was called.\n");
+ return EFI_ST_FAILURE;
+ }
+ /* Check if the event was signaled */
+ ret = boottime->check_event(event);
+ if (ret == EFI_SUCCESS) {
+ efi_st_error("Event was signaled on EFI_NOT_FOUND\n");
+ return EFI_ST_FAILURE;
+ }
+ if (counter != 1) {
+ efi_st_error("Notification function was not called.\n");
+ return EFI_ST_FAILURE;
+ }
+ if (table_count != sys_table->nr_tables) {
+ efi_st_error("Incorrect table count %u, expected %u\n",
+ (unsigned int)sys_table->nr_tables,
+ (unsigned int)table_count);
+ return EFI_ST_FAILURE;
+ }
+
+ /* Install table */
+ ret = boottime->install_configuration_table(&table_guid,
+ (void *)&tables[0]);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Failed to install table\n");
+ return EFI_ST_FAILURE;
+ }
+ /* Check signaled state */
+ ret = boottime->check_event(event);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Event was not signaled on insert\n");
+ return EFI_ST_FAILURE;
+ }
+ if (++table_count != sys_table->nr_tables) {
+ efi_st_error("Incorrect table count %u, expected %u\n",
+ (unsigned int)sys_table->nr_tables,
+ (unsigned int)table_count);
+ return EFI_ST_FAILURE;
+ }
+ table = NULL;
+ for (i = 0; i < sys_table->nr_tables; ++i) {
+ if (!efi_st_memcmp(&sys_table->tables[i].guid, &table_guid,
+ sizeof(efi_guid_t)))
+ table = sys_table->tables[i].table;
+ }
+ if (!table) {
+ efi_st_error("Installed table not found\n");
+ return EFI_ST_FAILURE;
+ }
+ if (table != &tables[0]) {
+ efi_st_error("Incorrect table address\n");
+ return EFI_ST_FAILURE;
+ }
+ if (check_table(sys_table) != EFI_ST_SUCCESS) {
+ efi_st_error("Checking system table\n");
+ return EFI_ST_FAILURE;
+ }
+
+ /* Update table */
+ ret = boottime->install_configuration_table(&table_guid,
+ (void *)&tables[1]);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Failed to update table\n");
+ return EFI_ST_FAILURE;
+ }
+ /* Check signaled state */
+ ret = boottime->check_event(event);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Event was not signaled on update\n");
+ return EFI_ST_FAILURE;
+ }
+ if (table_count != sys_table->nr_tables) {
+ efi_st_error("Incorrect table count %u, expected %u\n",
+ (unsigned int)sys_table->nr_tables,
+ (unsigned int)table_count);
+ return EFI_ST_FAILURE;
+ }
+ table = NULL;
+ tabcnt = 0;
+ for (i = 0; i < sys_table->nr_tables; ++i) {
+ if (!efi_st_memcmp(&sys_table->tables[i].guid, &table_guid,
+ sizeof(efi_guid_t))) {
+ table = sys_table->tables[i].table;
+ ++tabcnt;
+ }
+ }
+ if (!table) {
+ efi_st_error("Installed table not found\n");
+ return EFI_ST_FAILURE;
+ }
+ if (tabcnt > 1) {
+ efi_st_error("Duplicate table guid\n");
+ return EFI_ST_FAILURE;
+ }
+ if (table != &tables[1]) {
+ efi_st_error("Incorrect table address\n");
+ return EFI_ST_FAILURE;
+ }
+ if (check_table(sys_table) != EFI_ST_SUCCESS) {
+ efi_st_error("Checking system table\n");
+ return EFI_ST_FAILURE;
+ }
+
+ /* Delete table */
+ ret = boottime->install_configuration_table(&table_guid, NULL);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Failed to delete table\n");
+ return EFI_ST_FAILURE;
+ }
+ /* Check signaled state */
+ ret = boottime->check_event(event);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Event was not signaled on delete\n");
+ return EFI_ST_FAILURE;
+ }
+ if (--table_count != sys_table->nr_tables) {
+ efi_st_error("Incorrect table count %u, expected %u\n",
+ (unsigned int)sys_table->nr_tables,
+ (unsigned int)table_count);
+ return EFI_ST_FAILURE;
+ }
+ table = NULL;
+ for (i = 0; i < sys_table->nr_tables; ++i) {
+ if (!efi_st_memcmp(&sys_table->tables[i].guid, &table_guid,
+ sizeof(efi_guid_t))) {
+ table = sys_table->tables[i].table;
+ }
+ }
+ if (table) {
+ efi_st_error("Wrong table deleted\n");
+ return EFI_ST_FAILURE;
+ }
+
+ ret = boottime->close_event(event);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Failed to close event\n");
+ return EFI_ST_FAILURE;
+ }
+ if (check_table(sys_table) != EFI_ST_SUCCESS) {
+ efi_st_error("Checking system table\n");
+ return EFI_ST_FAILURE;
+ }
+
+ return EFI_ST_SUCCESS;
+}
+
+EFI_UNIT_TEST(configtables) = {
+ .name = "configuration tables",
+ .phase = EFI_EXECUTE_BEFORE_BOOTTIME_EXIT,
+ .setup = setup,
+ .execute = execute,
+};
/*
* Print an unsigned 32bit value as decimal number to an u16 string
*
- * @value: value to be printed
- * @buf: pointer to buffer address
- * on return position of terminating zero word
+ * @value: value to be printed
+ * @prec: minimum number of digits to display
+ * @buf: pointer to buffer address
+ * on return position of terminating zero word
*/
-static void uint2dec(u32 value, u16 **buf)
+static void uint2dec(u32 value, int prec, u16 **buf)
{
u16 *pos = *buf;
int i;
for (i = 0; i < 10; ++i) {
/* Write current digit */
c = f >> 60;
- if (c || pos != *buf)
+ if (c || pos != *buf || 10 - i <= prec)
*pos++ = c + '0';
/* Eliminate current digit */
f &= 0xfffffffffffffff;
/*
* Print a signed 32bit value as decimal number to an u16 string
*
- * @value: value to be printed
- * @buf: pointer to buffer address
+ * @value: value to be printed
+ * @prec: minimum number of digits to display
+ * @buf: pointer to buffer address
* on return position of terminating zero word
*/
-static void int2dec(s32 value, u16 **buf)
+static void int2dec(s32 value, int prec, u16 **buf)
{
u32 u;
u16 *pos = *buf;
} else {
u = value;
}
- uint2dec(u, &pos);
+ uint2dec(u, prec, &pos);
*buf = pos;
}
u16 *pos = buf;
const char *s;
u16 *u;
+ int prec;
va_start(args, fmt);
break;
case '%':
++c;
+ /* Parse precision */
+ if (*c == '.') {
+ ++c;
+ prec = *c - '0';
+ ++c;
+ } else {
+ prec = 0;
+ }
switch (*c) {
case '\0':
--c;
break;
case 'd':
- int2dec(va_arg(args, s32), &pos);
+ int2dec(va_arg(args, s32), prec, &pos);
break;
case 'p':
++c;
*pos++ = *s;
break;
case 'u':
- uint2dec(va_arg(args, u32), &pos);
+ uint2dec(va_arg(args, u32), prec, &pos);
break;
default:
break;
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * efi_selftest_crc32
+ *
+ * Copyright (c) 2018 Heinrich Schuchardt <xypron.glpk@gmx.de>
+ *
+ * This unit test checks the CalculateCrc32 bootservice and checks the
+ * headers of the system table, the boot services tablle, and the runtime
+ * services table before and after ExitBootServices().
+ */
+
+#include <efi_selftest.h>
+
+const struct efi_system_table *st;
+efi_status_t (EFIAPI *bs_crc32)(const void *data, efi_uintn_t data_size,
+ u32 *crc32);
+
+static int check_table(const void *table)
+{
+ efi_status_t ret;
+ u32 crc32, res;
+ /* Casting from const to not const */
+ struct efi_table_hdr *hdr = (struct efi_table_hdr *)table;
+
+ if (!hdr->signature) {
+ efi_st_error("Missing header signature\n");
+ return EFI_ST_FAILURE;
+ }
+ if (!hdr->revision) {
+ efi_st_error("Missing header revision\n");
+ return EFI_ST_FAILURE;
+ }
+ if (hdr->headersize <= sizeof(struct efi_table_hdr)) {
+ efi_st_error("Incorrect headersize value\n");
+ return EFI_ST_FAILURE;
+ }
+ if (hdr->reserved) {
+ efi_st_error("Reserved header field is not zero\n");
+ return EFI_ST_FAILURE;
+ }
+
+ crc32 = hdr->crc32;
+ /*
+ * Setting the crc32 of the 'const' table to zero is easier than
+ * copying
+ */
+ hdr->crc32 = 0;
+ ret = bs_crc32(table, hdr->headersize, &res);
+ /* Reset table crc32 so it stays constant */
+ hdr->crc32 = crc32;
+ if (ret != EFI_ST_SUCCESS) {
+ efi_st_error("CalculateCrc32 failed\n");
+ return EFI_ST_FAILURE;
+ }
+ if (res != crc32) {
+ efi_st_error("Incorrect CRC32\n");
+ // return EFI_ST_FAILURE;
+ }
+ return EFI_ST_SUCCESS;
+}
+
+/*
+ * Setup unit test.
+ *
+ * Check that CalculateCrc32 is working correctly.
+ * Check tables before ExitBootServices().
+ *
+ * @handle: handle of the loaded image
+ * @systable: system table
+ * @return: EFI_ST_SUCCESS for success
+ */
+static int setup(const efi_handle_t handle,
+ const struct efi_system_table *systable)
+{
+ efi_status_t ret;
+ u32 res;
+
+ st = systable;
+ bs_crc32 = systable->boottime->calculate_crc32;
+
+ /* Check that CalculateCrc32 is working */
+ ret = bs_crc32("U-Boot", 6, &res);
+ if (ret != EFI_ST_SUCCESS) {
+ efi_st_error("CalculateCrc32 failed\n");
+ return EFI_ST_FAILURE;
+ }
+ if (res != 0x134b0db4) {
+ efi_st_error("Incorrect CRC32\n");
+ return EFI_ST_FAILURE;
+ }
+
+ /* Check tables before ExitBootServices() */
+ if (check_table(st) != EFI_ST_SUCCESS) {
+ efi_st_error("Checking system table\n");
+ return EFI_ST_FAILURE;
+ }
+ if (check_table(st->boottime) != EFI_ST_SUCCESS) {
+ efi_st_error("Checking boottime table\n");
+ return EFI_ST_FAILURE;
+ }
+ if (check_table(st->runtime) != EFI_ST_SUCCESS) {
+ efi_st_error("Checking runtime table\n");
+ return EFI_ST_FAILURE;
+ }
+
+ return EFI_ST_SUCCESS;
+}
+
+/*
+ * Execute unit test
+ *
+ * Check tables after ExitBootServices()
+ *
+ * @return: EFI_ST_SUCCESS for success
+ */
+static int execute(void)
+{
+ if (check_table(st) != EFI_ST_SUCCESS) {
+ efi_st_error("Checking system table\n");
+ return EFI_ST_FAILURE;
+ }
+ if (check_table(st->runtime) != EFI_ST_SUCCESS) {
+ efi_st_error("Checking runtime table\n");
+ return EFI_ST_FAILURE;
+ }
+
+ /*
+ * We cannot call SetVirtualAddressMap() and recheck the runtime
+ * table afterwards because this would invalidate the addresses of the
+ * unit tests.
+ */
+
+ return EFI_ST_SUCCESS;
+}
+
+EFI_UNIT_TEST(crc32) = {
+ .name = "crc32",
+ .phase = EFI_SETUP_BEFORE_BOOTTIME_EXIT,
+ .setup = setup,
+ .execute = execute,
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * efi_selftest_rtc
+ *
+ * Copyright (c) 2018 Heinrich Schuchardt <xypron.glpk@gmx.de>
+ *
+ * Test the real time clock runtime services.
+ */
+
+#include <efi_selftest.h>
+
+#define EFI_ST_NO_RTC "Could not read real time clock\n"
+
+static struct efi_runtime_services *runtime;
+
+/*
+ * Setup unit test.
+ *
+ * @handle: handle of the loaded image
+ * @systable: system table
+ * @return: EFI_ST_SUCCESS for success
+ */
+static int setup(const efi_handle_t handle,
+ const struct efi_system_table *systable)
+{
+ runtime = systable->runtime;
+ return EFI_ST_SUCCESS;
+}
+
+/*
+ * Execute unit test.
+ *
+ * Display current time.
+ *
+ * @return: EFI_ST_SUCCESS for success
+ */
+static int execute(void)
+{
+ efi_status_t ret;
+ struct efi_time tm;
+
+ /* Display current time */
+ ret = runtime->get_time(&tm, NULL);
+ if (ret != EFI_SUCCESS) {
+#ifdef CONFIG_CMD_DATE
+ efi_st_error(EFI_ST_NO_RTC);
+ return EFI_ST_FAILURE;
+#else
+ efi_st_todo(EFI_ST_NO_RTC);
+ return EFI_ST_SUCCESS;
+#endif
+ } else {
+ efi_st_printf("Time according to real time clock: "
+ "%.4u-%.2u-%.2u %.2u:%.2u:%.2u\n",
+ tm.year, tm.month, tm.day,
+ tm.hour, tm.minute, tm.second);
+ }
+
+ return EFI_ST_SUCCESS;
+}
+
+EFI_UNIT_TEST(rtc) = {
+ .name = "real time clock",
+ .phase = EFI_EXECUTE_BEFORE_BOOTTIME_EXIT,
+ .setup = setup,
+ .execute = execute,
+};
}
#if defined(CONFIG_NR_DRAM_BANKS)
+
+static int get_next_memory_node(const void *blob, int startoffset)
+{
+ int mem = -1;
+
+ do {
+ mem = fdt_node_offset_by_prop_value(gd->fdt_blob, mem,
+ "device_type", "memory", 7);
+ } while (!fdtdec_get_is_enabled(blob, mem));
+
+ return mem;
+}
+
int fdtdec_setup_memory_banksize(void)
{
int bank, ret, mem, reg = 0;
struct fdt_resource res;
- mem = fdt_node_offset_by_prop_value(gd->fdt_blob, -1, "device_type",
- "memory", 7);
+ mem = get_next_memory_node(gd->fdt_blob, -1);
if (mem < 0) {
debug("%s: Missing /memory node\n", __func__);
return -EINVAL;
ret = fdt_get_resource(gd->fdt_blob, mem, "reg", reg++, &res);
if (ret == -FDT_ERR_NOTFOUND) {
reg = 0;
- mem = fdt_node_offset_by_prop_value(gd->fdt_blob, mem,
- "device_type",
- "memory", 7);
+ mem = get_next_memory_node(gd->fdt_blob, mem);
if (mem == -FDT_ERR_NOTFOUND)
break;
break;
}
- uuid_bin_to_str(addr, uuid, str_format);
+ if (addr)
+ uuid_bin_to_str(addr, uuid, str_format);
+ else
+ strcpy(uuid, "<NULL>");
return string(buf, end, uuid, field_width, precision, flags);
}
struct eth_device_priv *priv;
current = eth_get_dev();
- if (!current || !device_active(current))
+ if (!current || !eth_is_active(current))
return;
eth_get_ops(current)->stop(current);
/**********************************************************************/
-static int on_bootfile(const char *name, const char *value, enum env_op op,
- int flags)
-{
- if (flags & H_PROGRAMMATIC)
- return 0;
-
- switch (op) {
- case env_op_create:
- case env_op_overwrite:
- copy_filename(net_boot_file_name, value,
- sizeof(net_boot_file_name));
- break;
- default:
- break;
- }
-
- return 0;
-}
-U_BOOT_ENV_CALLBACK(bootfile, on_bootfile);
-
static int on_ipaddr(const char *name, const char *value, enum env_op op,
int flags)
{
const char *s = env_get("autoload");
if (s != NULL && strcmp(s, "NFS") == 0) {
+ if (net_check_prereq(NFS)) {
+/* We aren't expecting to get a serverip, so just accept the assigned IP */
+#ifdef CONFIG_BOOTP_SERVERIP
+ net_set_state(NETLOOP_SUCCESS);
+#else
+ printf("Cannot autoload with NFS\n");
+ net_set_state(NETLOOP_FAIL);
+#endif
+ return;
+ }
/*
* Use NFS to load the bootfile.
*/
net_set_state(NETLOOP_SUCCESS);
return;
}
+ if (net_check_prereq(TFTPGET)) {
+/* We aren't expecting to get a serverip, so just accept the assigned IP */
+#ifdef CONFIG_BOOTP_SERVERIP
+ net_set_state(NETLOOP_SUCCESS);
+#else
+ printf("Cannot autoload with TFTPGET\n");
+ net_set_state(NETLOOP_FAIL);
+#endif
+ return;
+ }
tftp_start(TFTPGET);
}
/* Fall through */
case TFTPGET:
case TFTPPUT:
- if (net_server_ip.s_addr == 0) {
+ if (net_server_ip.s_addr == 0 && !is_serverip_in_cmd()) {
puts("*** ERROR: `serverip' not set\n");
return 1;
}
void copy_filename(char *dst, const char *src, int size)
{
- if (*src && (*src == '"')) {
+ if (src && *src && (*src == '"')) {
++src;
--size;
}
- while ((--size > 0) && *src && (*src != '"'))
+ while ((--size > 0) && src && *src && (*src != '"'))
*dst++ = *src++;
*dst = '\0';
}
+int is_serverip_in_cmd(void)
+{
+ return !!strchr(net_boot_file_name, ':');
+}
+
+int net_parse_bootfile(struct in_addr *ipaddr, char *filename, int max_len)
+{
+ char *colon;
+
+ if (net_boot_file_name[0] == '\0')
+ return 0;
+
+ colon = strchr(net_boot_file_name, ':');
+ if (colon) {
+ if (ipaddr)
+ *ipaddr = string_to_ip(net_boot_file_name);
+ strncpy(filename, colon + 1, max_len);
+ } else {
+ strncpy(filename, net_boot_file_name, max_len);
+ }
+ filename[max_len - 1] = '\0';
+
+ return 1;
+}
+
#if defined(CONFIG_CMD_NFS) || \
defined(CONFIG_CMD_SNTP) || \
defined(CONFIG_CMD_DNS)
switch (ntohl(rpc_pkt.u.reply.data[0])) {
/* Minimal supported NFS version */
case 3:
- debug("*** Waring: NFS version not supported: Requested: V%d, accepted: min V%d - max V%d\n",
+ debug("*** Warning: NFS version not supported: Requested: V%d, accepted: min V%d - max V%d\n",
(supported_nfs_versions & NFSV2_FLAG) ?
2 : 3,
ntohl(rpc_pkt.u.reply.data[0]),
if (nfs_path == NULL) {
net_set_state(NETLOOP_FAIL);
- debug("*** ERROR: Fail allocate memory\n");
+ printf("*** ERROR: Fail allocate memory\n");
return;
}
- if (net_boot_file_name[0] == '\0') {
+ if (!net_parse_bootfile(&nfs_server_ip, nfs_path,
+ sizeof(nfs_path_buff))) {
sprintf(nfs_path, "/nfsroot/%02X%02X%02X%02X.img",
net_ip.s_addr & 0xFF,
(net_ip.s_addr >> 8) & 0xFF,
(net_ip.s_addr >> 16) & 0xFF,
(net_ip.s_addr >> 24) & 0xFF);
- debug("*** Warning: no boot file name; using '%s'\n",
- nfs_path);
- } else {
- char *p = net_boot_file_name;
-
- p = strchr(p, ':');
-
- if (p != NULL) {
- nfs_server_ip = string_to_ip(net_boot_file_name);
- ++p;
- strcpy(nfs_path, p);
- } else {
- strcpy(nfs_path, net_boot_file_name);
- }
+ printf("*** Warning: no boot file name; using '%s'\n",
+ nfs_path);
}
nfs_filename = basename(nfs_path);
nfs_path = dirname(nfs_path);
- debug("Using %s device\n", eth_get_name());
+ printf("Using %s device\n", eth_get_name());
- debug("File transfer via NFS from server %pI4; our IP address is %pI4",
- &nfs_server_ip, &net_ip);
+ printf("File transfer via NFS from server %pI4; our IP address is %pI4",
+ &nfs_server_ip, &net_ip);
/* Check if we need to send across this subnet */
if (net_gateway.s_addr && net_netmask.s_addr) {
struct in_addr server_net;
our_net.s_addr = net_ip.s_addr & net_netmask.s_addr;
- server_net.s_addr = net_server_ip.s_addr & net_netmask.s_addr;
+ server_net.s_addr = nfs_server_ip.s_addr & net_netmask.s_addr;
if (our_net.s_addr != server_net.s_addr)
- debug("; sending through gateway %pI4",
- &net_gateway);
+ printf("; sending through gateway %pI4",
+ &net_gateway);
}
- debug("\nFilename '%s/%s'.", nfs_path, nfs_filename);
+ printf("\nFilename '%s/%s'.", nfs_path, nfs_filename);
if (net_boot_file_expected_size_in_blocks) {
- debug(" Size is 0x%x Bytes = ",
- net_boot_file_expected_size_in_blocks << 9);
+ printf(" Size is 0x%x Bytes = ",
+ net_boot_file_expected_size_in_blocks << 9);
print_size(net_boot_file_expected_size_in_blocks << 9, "");
}
- debug("\nLoad address: 0x%lx\nLoading: *\b", load_addr);
+ printf("\nLoad address: 0x%lx\nLoading: *\b", load_addr);
net_set_timeout_handler(nfs_timeout, nfs_timeout_handler);
net_set_udp_handler(nfs_handler);
* case, most NFS servers are optimized for a power of 2.
*/
#define NFS_READ_SIZE 1024 /* biggest power of two that fits Ether frame */
+#define NFS_MAX_ATTRS 26
/* Values for Accept State flag on RPC answers (See: rfc1831) */
enum rpc_accept_stat {
struct rpc_t {
union {
- uint8_t data[2048];
+ uint8_t data[NFS_READ_SIZE + (6 + NFS_MAX_ATTRS) *
+ sizeof(uint32_t)];
struct {
uint32_t id;
uint32_t type;
uint32_t verifier;
uint32_t v2;
uint32_t astatus;
- uint32_t data[NFS_READ_SIZE];
+ uint32_t data[NFS_READ_SIZE / sizeof(uint32_t) +
+ NFS_MAX_ATTRS];
} reply;
} u;
} __attribute__((packed));
tftp_block_size_option, timeout_ms);
tftp_remote_ip = net_server_ip;
- if (net_boot_file_name[0] == '\0') {
+ if (!net_parse_bootfile(&tftp_remote_ip, tftp_filename, MAX_LEN)) {
sprintf(default_filename, "%02X%02X%02X%02X.img",
net_ip.s_addr & 0xFF,
(net_ip.s_addr >> 8) & 0xFF,
printf("*** Warning: no boot file name; using '%s'\n",
tftp_filename);
- } else {
- char *p = strchr(net_boot_file_name, ':');
-
- if (p == NULL) {
- strncpy(tftp_filename, net_boot_file_name, MAX_LEN);
- tftp_filename[MAX_LEN - 1] = 0;
- } else {
- tftp_remote_ip = string_to_ip(net_boot_file_name);
- strncpy(tftp_filename, p + 1, MAX_LEN);
- tftp_filename[MAX_LEN - 1] = 0;
- }
}
printf("Using %s device\n", eth_get_name());
CONFIG_ARMADA100_FEC
CONFIG_ARMADA168
CONFIG_ARMADA_39X
+CONFIG_ARMV7_PSCI_0_2
CONFIG_ARMV7_PSCI_1_0
CONFIG_ARMV7_SECURE_BASE
CONFIG_ARMV7_SECURE_MAX_SIZE
# fs-test.fs.ext4.out: Summary: PASS: 24 FAIL: 0
# FAT16 tests:
# fs-test.sb.fat16.out: Summary: PASS: 24 FAIL: 0
-# fs-test.fat16.out: Summary: PASS: 21 FAIL: 3
-# fs-test.fs.fat16.out: Summary: PASS: 21 FAIL: 3
+# fs-test.fat16.out: Summary: PASS: 20 FAIL: 4
+# fs-test.fs.fat16.out: Summary: PASS: 20 FAIL: 4
# FAT32 tests:
# fs-test.sb.fat32.out: Summary: PASS: 24 FAIL: 0
-# fs-test.fat32.out: Summary: PASS: 21 FAIL: 3
-# fs-test.fs.fat32.out: Summary: PASS: 21 FAIL: 3
-# Total Summary: TOTAL PASS: 204 TOTAL FAIL: 12
+# fs-test.fat32.out: Summary: PASS: 20 FAIL: 4
+# fs-test.fs.fat32.out: Summary: PASS: 20 FAIL: 4
+# Total Summary: TOTAL PASS: 200 TOTAL FAIL: 16
# pre-requisite binaries list.
PREREQ_BINS="md5sum mkfs mount umount dd fallocate mkdir"
twice will spawn an error used to detect that the TPM was not reset and no
initialization code should be run.
"""
- output = u_boot_console.run_command('tpm init')
+ output = u_boot_console.run_command('tpm2 init')
if force or not 'Error' in output:
u_boot_console.run_command('echo --- start of init ---')
- u_boot_console.run_command('tpm startup TPM2_SU_CLEAR')
- u_boot_console.run_command('tpm self_test full')
- u_boot_console.run_command('tpm clear TPM2_RH_LOCKOUT')
+ u_boot_console.run_command('tpm2 startup TPM2_SU_CLEAR')
+ u_boot_console.run_command('tpm2 self_test full')
+ u_boot_console.run_command('tpm2 clear TPM2_RH_LOCKOUT')
output = u_boot_console.run_command('echo $?')
if not output.endswith('0'):
- u_boot_console.run_command('tpm clear TPM2_RH_PLATFORM')
+ u_boot_console.run_command('tpm2 clear TPM2_RH_PLATFORM')
u_boot_console.run_command('echo --- end of init ---')
@pytest.mark.buildconfigspec('cmd_tpm_v2')
def test_tpm2_init(u_boot_console):
"""Init the software stack to use TPMv2 commands."""
- u_boot_console.run_command('tpm init')
+ u_boot_console.run_command('tpm2 init')
output = u_boot_console.run_command('echo $?')
assert output.endswith('0')
Initiate the TPM internal state machine.
"""
- u_boot_console.run_command('tpm startup TPM2_SU_CLEAR')
+ u_boot_console.run_command('tpm2 startup TPM2_SU_CLEAR')
output = u_boot_console.run_command('echo $?')
assert output.endswith('0')
Ask the TPM to perform all self tests to also enable full capabilities.
"""
- u_boot_console.run_command('tpm self_test full')
+ u_boot_console.run_command('tpm2 self_test full')
output = u_boot_console.run_command('echo $?')
assert output.endswith('0')
to enter a fully operational state.
"""
- u_boot_console.run_command('tpm self_test continue')
+ u_boot_console.run_command('tpm2 self_test continue')
output = u_boot_console.run_command('echo $?')
assert output.endswith('0')
PLATFORM hierarchies are also available.
"""
- u_boot_console.run_command('tpm clear TPM2_RH_LOCKOUT')
+ u_boot_console.run_command('tpm2 clear TPM2_RH_LOCKOUT')
output = u_boot_console.run_command('echo $?')
assert output.endswith('0')
- u_boot_console.run_command('tpm clear TPM2_RH_PLATFORM')
+ u_boot_console.run_command('tpm2 clear TPM2_RH_PLATFORM')
output = u_boot_console.run_command('echo $?')
assert output.endswith('0')
force_init(u_boot_console)
- u_boot_console.run_command('tpm change_auth TPM2_RH_LOCKOUT unicorn')
+ u_boot_console.run_command('tpm2 change_auth TPM2_RH_LOCKOUT unicorn')
output = u_boot_console.run_command('echo $?')
assert output.endswith('0')
- u_boot_console.run_command('tpm clear TPM2_RH_LOCKOUT unicorn')
+ u_boot_console.run_command('tpm2 clear TPM2_RH_LOCKOUT unicorn')
output = u_boot_console.run_command('echo $?')
- u_boot_console.run_command('tpm clear TPM2_RH_PLATFORM')
+ u_boot_console.run_command('tpm2 clear TPM2_RH_PLATFORM')
assert output.endswith('0')
@pytest.mark.buildconfigspec('cmd_tpm_v2')
force_init(u_boot_console)
ram = u_boot_utils.find_ram_base(u_boot_console)
- read_cap = u_boot_console.run_command('tpm get_capability 0x6 0x20e 0x200 1') #0x%x 1' % ram)
+ read_cap = u_boot_console.run_command('tpm2 get_capability 0x6 0x20e 0x200 1') #0x%x 1' % ram)
output = u_boot_console.run_command('echo $?')
assert output.endswith('0')
assert 'Property 0x0000020e: 0x00000000' in read_cap
ram = u_boot_utils.find_ram_base(u_boot_console)
# Set the DAM parameters to known values
- u_boot_console.run_command('tpm dam_parameters 3 10 0')
+ u_boot_console.run_command('tpm2 dam_parameters 3 10 0')
output = u_boot_console.run_command('echo $?')
assert output.endswith('0')
# Check the values have been saved
- read_cap = u_boot_console.run_command('tpm get_capability 0x6 0x20f 0x%x 3' % ram)
+ read_cap = u_boot_console.run_command('tpm2 get_capability 0x6 0x20f 0x%x 3' % ram)
output = u_boot_console.run_command('echo $?')
assert output.endswith('0')
assert 'Property 0x0000020f: 0x00000003' in read_cap
force_init(u_boot_console)
ram = u_boot_utils.find_ram_base(u_boot_console)
- read_pcr = u_boot_console.run_command('tpm pcr_read 0 0x%x' % ram)
+ read_pcr = u_boot_console.run_command('tpm2 pcr_read 0 0x%x' % ram)
output = u_boot_console.run_command('echo $?')
assert output.endswith('0')
force_init(u_boot_console)
ram = u_boot_utils.find_ram_base(u_boot_console)
- u_boot_console.run_command('tpm pcr_extend 0 0x%x' % ram)
+ u_boot_console.run_command('tpm2 pcr_extend 0 0x%x' % ram)
output = u_boot_console.run_command('echo $?')
assert output.endswith('0')
- read_pcr = u_boot_console.run_command('tpm pcr_read 0 0x%x' % ram)
+ read_pcr = u_boot_console.run_command('tpm2 pcr_read 0 0x%x' % ram)
output = u_boot_console.run_command('echo $?')
assert output.endswith('0')
assert 'f5 a5 fd 42 d1 6a 20 30 27 98 ef 6e d3 09 97 9b' in read_pcr
import tempfile
import time
-sys.path.append(os.path.join(os.path.dirname(__file__), 'buildman'))
+sys.path.insert(1, os.path.join(os.path.dirname(__file__), 'buildman'))
import kconfiglib
### constant variables ###
line = line.strip()
if not line or line.startswith('#'):
continue
- words = line.split(' ', 2)
+ words = line.split(None, 2)
if len(words) < 3 or words[0] != 'alias':
if not bad_line:
bad_line = "%s:%d:Invalid line '%s'" % (fname, linenum,
projects / oweals / u-boot.git / commitdiff