clk: imx8qm: fix usdhc2 clocks
authorMarcel Ziswiler <marcel@ziswiler.com>
Fri, 31 May 2019 16:00:17 +0000 (19:00 +0300)
committerStefano Babic <sbabic@denx.de>
Tue, 11 Jun 2019 08:42:48 +0000 (10:42 +0200)
Trying to bring up uSDHC2 the following error message was observed:

MMC:   imx8_clk_set_rate(Invalid clk ID #60)
imx8_clk_set_rate(Invalid clk ID #60)
usdhc@5b030000 - probe failed: -22

This commit fixes this by properly setting resp. clocks.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Max Krummenacher <max.krummenacher@toradex.com>
drivers/clk/imx/clk-imx8qm.c

index 6b5561e1786afe63e153372d17a8fd079dcad663..a6b09d2109503bce18d26a01c3028f6318339ca5 100644 (file)
@@ -80,6 +80,12 @@ ulong imx8_clk_get_rate(struct clk *clk)
                resource = SC_R_SDHC_1;
                pm_clk = SC_PM_CLK_PER;
                break;
+       case IMX8QM_SDHC2_IPG_CLK:
+       case IMX8QM_SDHC2_CLK:
+       case IMX8QM_SDHC2_DIV:
+               resource = SC_R_SDHC_2;
+               pm_clk = SC_PM_CLK_PER;
+               break;
        case IMX8QM_UART0_IPG_CLK:
        case IMX8QM_UART0_CLK:
                resource = SC_R_UART_0;
@@ -185,6 +191,12 @@ ulong imx8_clk_set_rate(struct clk *clk, unsigned long rate)
                resource = SC_R_SDHC_1;
                pm_clk = SC_PM_CLK_PER;
                break;
+       case IMX8QM_SDHC2_IPG_CLK:
+       case IMX8QM_SDHC2_CLK:
+       case IMX8QM_SDHC2_DIV:
+               resource = SC_R_SDHC_2;
+               pm_clk = SC_PM_CLK_PER;
+               break;
        case IMX8QM_ENET0_IPG_CLK:
        case IMX8QM_ENET0_AHB_CLK:
        case IMX8QM_ENET0_REF_DIV:
@@ -273,6 +285,12 @@ int __imx8_clk_enable(struct clk *clk, bool enable)
                resource = SC_R_SDHC_1;
                pm_clk = SC_PM_CLK_PER;
                break;
+       case IMX8QM_SDHC2_IPG_CLK:
+       case IMX8QM_SDHC2_CLK:
+       case IMX8QM_SDHC2_DIV:
+               resource = SC_R_SDHC_2;
+               pm_clk = SC_PM_CLK_PER;
+               break;
        case IMX8QM_ENET0_IPG_CLK:
        case IMX8QM_ENET0_AHB_CLK:
        case IMX8QM_ENET0_REF_DIV: