imx8mq: Enable eMMC HS400 and SD UHS mode on EVK

iMX8MQ EVK board has a eMMC5.0 chip and supports SD3.0, so enable the UHS
and HS400 configs to enhance the eMMC/SD access.

The change also needs to set usdhc clock to 400Mhz, and add the
off-on-delay-us to SD reset pin, otherwise some SD cards will
fail to select UHS mode in re-initialization.

Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>

diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mq.c b/arch/arm/mach-imx/imx8m/clock_imx8mq.c
index aad9cf13ef230443be61a2096278ac52cdf6e9f7..76104e4f92b8a52dc42592392cfd0fae12698d12 100644 (file)
--- a/arch/arm/mach-imx/imx8m/clock_imx8mq.c
+++ b/arch/arm/mach-imx/imx8m/clock_imx8mq.c
@@ -428,15 +428,13 @@ void init_clk_usdhc(u32 index)
        case 0:
                clock_enable(CCGR_USDHC1, 0);
                clock_set_target_val(USDHC1_CLK_ROOT, CLK_ROOT_ON |
-                                    CLK_ROOT_SOURCE_SEL(1) |
-                                    CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2));
+                                    CLK_ROOT_SOURCE_SEL(1));
                clock_enable(CCGR_USDHC1, 1);
                return;
        case 1:
                clock_enable(CCGR_USDHC2, 0);
                clock_set_target_val(USDHC2_CLK_ROOT, CLK_ROOT_ON |
-                                    CLK_ROOT_SOURCE_SEL(1) |
-                                    CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2));
+                                    CLK_ROOT_SOURCE_SEL(1));
                clock_enable(CCGR_USDHC2, 1);
                return;
        default: