Add PCI Express support on MPC8568MDS
authorHaiying Wang <Haiying.Wang@freescale.com>
Wed, 14 Nov 2007 20:52:06 +0000 (15:52 -0500)
committerKumar Gala <galak@kernel.crashing.org>
Wed, 12 Dec 2007 04:34:19 +0000 (22:34 -0600)
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
board/mpc8568mds/Makefile
board/mpc8568mds/ft_board.c [deleted file]
board/mpc8568mds/init.S
board/mpc8568mds/mpc8568mds.c
include/configs/MPC8568MDS.h

index a799aa4cc58ec08b4f1b9aad51f6039040210575..643fbc041ddab62505223853c3a6984670fd51a5 100644 (file)
@@ -29,9 +29,7 @@ endif
 
 LIB    = $(obj)lib$(BOARD).a
 
-COBJS  := $(BOARD).o \
-       bcsr.o \
-       ft_board.o
+COBJS  := $(BOARD).o bcsr.o
 
 SOBJS  := init.o
 
diff --git a/board/mpc8568mds/ft_board.c b/board/mpc8568mds/ft_board.c
deleted file mode 100644 (file)
index 36815cc..0000000
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * Copyright 2004-2007 Freescale Semiconductor.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-
-#include <ft_build.h>
-
-extern void ft_cpu_setup(void *blob, bd_t *bd);
-
-#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
-void
-ft_board_setup(void *blob, bd_t *bd)
-{
-       u32 *p;
-       int len;
-#ifdef CONFIG_PCI
-       ft_pci_setup(blob, bd);
-#endif
-       ft_cpu_setup(blob, bd);
-       p = ft_get_prop(blob, "/memory/reg", &len);
-       if (p != NULL) {
-               *p++ = cpu_to_be32(bd->bi_memstart);
-               *p = cpu_to_be32(bd->bi_memsize);
-       }
-}
-#endif /* CONFIG_OF_FLAT_TREE && CONFIG_OF_BOARD_SETUP */
index 972a7d429906e25547b4b79343af52432cae1a02..38ba9c773d747665f5cb8ebc9bd0128f829227bc 100644 (file)
 #include <config.h>
 #include <mpc85xx.h>
 
+#define LAWAR_TRGT_PCI1         0x00000000
+#define LAWAR_TRGT_PCIE1       0x00200000
+#define LAWAR_TRGT_RIO          0x00c00000
+#define LAWAR_TRGT_LBC          0x00400000
+#define LAWAR_TRGT_DDR          0x00f00000
 
 /*
  * TLB0 and TLB1 Entries
@@ -211,27 +216,27 @@ tlb1_entry:
  */
 
 #define LAWBAR0 0
-#define LAWAR0  ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
+#define LAWAR0  ((LAWAR_TRGT_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
 
 #define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff)
-#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M))
+#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M))
 
-#define LAWBAR2 ((CFG_PEX_MEM_BASE>>12) & 0xfffff)
-#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PEX | (LAWAR_SIZE & LAWAR_SIZE_512M))
+#define LAWBAR2 ((CFG_PCIE1_MEM_BASE>>12) & 0xfffff)
+#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_512M))
 
 #define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff)
-#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_8M))
+#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_8M))
 
-#define LAWBAR4 ((CFG_PEX_IO_PHYS>>12) & 0xfffff)
-#define LAWAR4  (LAWAR_EN | LAWAR_TRGT_IF_PEX | (LAWAR_SIZE & LAWAR_SIZE_8M))
+#define LAWBAR4 ((CFG_PCIE1_IO_PHYS>>12) & 0xfffff)
+#define LAWAR4  (LAWAR_EN | LAWAR_TRGT_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_8M))
 
 
 #define LAWBAR5 ((CFG_SRIO_MEM_BASE>>12) & 0xfffff)
-#define LAWAR5 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M))
+#define LAWAR5 (LAWAR_EN | LAWAR_TRGT_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M))
 
 /* LBC window - maps 256M.  That's SDRAM, BCSR, PIBs, and Flash */
 #define LAWBAR6 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
-#define LAWAR6 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M))
+#define LAWAR6 (LAWAR_EN | LAWAR_TRGT_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M))
 
        .section .bootpg, "ax"
        .globl  law_entry
index 2a68185bb9ec634679c597ccbacf339f368666d1..ab5b67d9e58a695c2da13bf5c62439d89ecbf37f 100644 (file)
 #include <pci.h>
 #include <asm/processor.h>
 #include <asm/immap_85xx.h>
+#include <asm/immap_fsl_pci.h>
 #include <spd.h>
 #include <i2c.h>
 #include <ioports.h>
 
+#if defined(CONFIG_OF_FLAT_TREE)
+#include <ft_build.h>
+#endif
+
 #include "bcsr.h"
 
 const qe_iop_conf_t qe_iop_conf_tab[] = {
@@ -336,16 +341,19 @@ static struct pci_config_table pci_mpc8568mds_config_table[] = {
 };
 #endif
 
-static struct pci_controller hose[] = {
-       {
+static struct pci_controller pci1_hose = {
 #ifndef CONFIG_PCI_PNP
        config_table: pci_mpc8568mds_config_table,
 #endif
-       }
 };
-
 #endif /* CONFIG_PCI */
 
+#ifdef CONFIG_PCIE1
+static struct pci_controller pcie1_hose;
+#endif  /* CONFIG_PCIE1 */
+
+int first_free_busno = 0;
+
 /*
  * pib_init() -- Initialize the PCA9555 IO expander on the PIB board
  */
@@ -388,11 +396,170 @@ pib_init(void)
        asm("eieio");
 }
 
+#ifdef CONFIG_PCI
 void
 pci_init_board(void)
 {
-#ifdef CONFIG_PCI
+       volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+       uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
+       uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
+
+#ifdef CONFIG_PCI1
+{
        pib_init();
-       pci_mpc85xx_init(hose);
+
+       volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR;
+       extern void fsl_pci_init(struct pci_controller *hose);
+       struct pci_controller *hose = &pci1_hose;
+
+       uint pci_32 = 1;      /* PORDEVSR[15] */
+       uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;       /* PORDEVSR[14] */
+       uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;   /* PORPLLSR[16] */
+
+       uint pci_agent = (host_agent == 3) || (host_agent == 4 ) || (host_agent == 6);
+
+       uint pci_speed = 66666000;
+
+       if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) {
+               printf ("    PCI: %d bit, %s MHz, %s, %s, %s\n",
+                       (pci_32) ? 32 : 64,
+                       (pci_speed == 33333000) ? "33" :
+                       (pci_speed == 66666000) ? "66" : "unknown",
+                       pci_clk_sel ? "sync" : "async",
+                       pci_agent ? "agent" : "host",
+                       pci_arb ? "arbiter" : "external-arbiter"
+                       );
+
+               /* inbound */
+               pci_set_region(hose->regions + 0,
+                               CFG_PCI_MEMORY_BUS,
+                               CFG_PCI_MEMORY_PHYS,
+                               CFG_PCI_MEMORY_SIZE,
+                               PCI_REGION_MEM | PCI_REGION_MEMORY);
+
+               /* outbound memory */
+               pci_set_region(hose->regions + 1,
+                               CFG_PCI1_MEM_BASE,
+                               CFG_PCI1_MEM_PHYS,
+                               CFG_PCI1_MEM_SIZE,
+                               PCI_REGION_MEM);
+
+               /* outbound io */
+               pci_set_region(hose->regions + 2,
+                               CFG_PCI1_IO_BASE,
+                               CFG_PCI1_IO_PHYS,
+                               CFG_PCI1_IO_SIZE,
+                               PCI_REGION_IO);
+
+               hose->region_count = 3;
+
+               hose->first_busno = first_free_busno;
+               pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
+
+               fsl_pci_init(hose);
+               first_free_busno = hose->last_busno+1;
+               printf ("PCI on bus %02x - %02x\n",hose->first_busno,hose->last_busno);
+       } else {
+       printf ("    PCI: disabled\n");
+       }
+}
+#else
+       gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
+#endif
+
+#ifdef CONFIG_PCIE1
+{
+       volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR;
+       extern void fsl_pci_init(struct pci_controller *hose);
+       struct pci_controller *hose = &pcie1_hose;
+       int pcie_ep =  (host_agent == 0) || (host_agent == 2 ) || (host_agent == 3);
+
+       int pcie_configured  = io_sel >= 1;
+
+       if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){
+               printf ("\n    PCIE connected to slot as %s (base address %x)",
+                       pcie_ep ? "End Point" : "Root Complex",
+                       (uint)pci);
+
+               if (pci->pme_msg_det) {
+                       pci->pme_msg_det = 0xffffffff;
+                       debug (" with errors.  Clearing.  Now 0x%08x",pci->pme_msg_det);
+               }
+               printf ("\n");
+
+               /* inbound */
+               pci_set_region(hose->regions + 0,
+                               CFG_PCI_MEMORY_BUS,
+                               CFG_PCI_MEMORY_PHYS,
+                               CFG_PCI_MEMORY_SIZE,
+                               PCI_REGION_MEM | PCI_REGION_MEMORY);
+
+               /* outbound memory */
+               pci_set_region(hose->regions + 1,
+                               CFG_PCIE1_MEM_BASE,
+                               CFG_PCIE1_MEM_PHYS,
+                               CFG_PCIE1_MEM_SIZE,
+                               PCI_REGION_MEM);
+
+               /* outbound io */
+               pci_set_region(hose->regions + 2,
+                               CFG_PCIE1_IO_BASE,
+                               CFG_PCIE1_IO_PHYS,
+                               CFG_PCIE1_IO_SIZE,
+                               PCI_REGION_IO);
+
+               hose->region_count = 3;
+
+               hose->first_busno=first_free_busno;
+               pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
+
+               fsl_pci_init(hose);
+               printf ("PCIE on bus %02x - %02x\n",hose->first_busno,hose->last_busno);
+
+               first_free_busno=hose->last_busno+1;
+
+       } else {
+               printf ("    PCIE: disabled\n");
+       }
+}
+#else
+       gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
 #endif
 }
+#endif /* CONFIG_PCI */
+
+#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
+void
+ft_board_setup(void *blob, bd_t *bd)
+{
+       u32 *p;
+       int len;
+
+       ft_cpu_setup(blob, bd);
+       p = ft_get_prop(blob, "/memory/reg", &len);
+       if (p != NULL) {
+               *p++ = cpu_to_be32(bd->bi_memstart);
+               *p = cpu_to_be32(bd->bi_memsize);
+       }
+
+#ifdef CONFIG_PCI1
+       p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8000/bus-range", &len);
+       if (p != NULL) {
+               p[0] = 0;
+               p[1] = pci1_hose.last_busno - pci1_hose.first_busno;
+               debug("PCI@8000 first_busno=%d last_busno=%d\n",p[0],p[1]);
+       }
+#endif
+
+#ifdef CONFIG_PCIE1
+       p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@a000/bus-range", &len);
+       if (p != NULL) {
+               p[0] = 0;
+               p[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
+               debug("PCI@a000 first_busno=%d last_busno=%d\n",p[0],p[1]);
+       }
+#endif
+}
+#endif
+
+
index b9366cc99476dc70d2d1df7f025715c495cc0461..cf79257bd72b0b0c58a10830181afc14a69553f1 100644 (file)
 #define CONFIG_MPC8568         1       /* MPC8568 specific */
 #define CONFIG_MPC8568MDS      1       /* MPC8568MDS board specific */
 
-#define CONFIG_PCI
+#define CONFIG_PCI             1       /* Enable PCI/PCIE */
+#define CONFIG_PCI1            1       /* PCI controller */
+#define CONFIG_PCIE1           1       /* PCIE controller */
+#define CONFIG_FSL_PCI_INIT    1       /* use common fsl pci init code */
 #define CONFIG_TSEC_ENET               /* tsec ethernet support */
 #define CONFIG_QE                      /* Enable QE */
 #define CONFIG_ENV_OVERWRITE
@@ -87,6 +90,9 @@ extern unsigned long get_clock_freq(void);
 #define CFG_CCSRBAR            0xe0000000      /* relocated CCSRBAR */
 #define CFG_IMMR               CFG_CCSRBAR     /* PQII uses CFG_IMMR */
 
+#define CFG_PCI1_ADDR           (CFG_CCSRBAR+0x8000)
+#define CFG_PCIE1_ADDR          (CFG_CCSRBAR+0xa000)
+
 /*
  * DDR Setup
  */
@@ -325,12 +331,12 @@ extern unsigned long get_clock_freq(void);
 #define CFG_PCI1_IO_PHYS       0xe2000000
 #define CFG_PCI1_IO_SIZE       0x00800000      /* 8M */
 
-#define CFG_PEX_MEM_BASE       0xa0000000
-#define CFG_PEX_MEM_PHYS       CFG_PEX_MEM_BASE
-#define CFG_PEX_MEM_SIZE       0x10000000      /* 256M */
-#define CFG_PEX_IO_BASE                0x00000000
-#define CFG_PEX_IO_PHYS                0xe2800000
-#define CFG_PEX_IO_SIZE                0x00800000      /* 8M */
+#define CFG_PCIE1_MEM_BASE     0xa0000000
+#define CFG_PCIE1_MEM_PHYS     CFG_PCIE1_MEM_BASE
+#define CFG_PCIE1_MEM_SIZE     0x20000000      /* 512M */
+#define CFG_PCIE1_IO_BASE      0x00000000
+#define CFG_PCIE1_IO_PHYS      0xe2800000
+#define CFG_PCIE1_IO_SIZE      0x00800000      /* 8M */
 
 #define CFG_SRIO_MEM_BASE      0xc0000000
 
@@ -383,6 +389,11 @@ extern unsigned long get_clock_freq(void);
 #undef CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 #define CFG_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
 
+/* PCI view of System Memory */
+#define CFG_PCI_MEMORY_BUS      0x00000000
+#define CFG_PCI_MEMORY_PHYS     0x00000000
+#define CFG_PCI_MEMORY_SIZE     0x80000000
+
 #endif /* CONFIG_PCI */
 
 #ifndef CONFIG_NET_MULTI