Merge tag 'efi-2019-04-rc4-2' of https://github.com/xypron2/u-boot

Pull request for UEFI system for v2019.04-rc4

Fix an error with the serial communication on boards with a very small
UART buffer which leads to a stalled system.

Provide an X86 reset driver for the UEFI runtime.

diff --git a/arch/arm/dts/r8a7790-lager-u-boot.dts b/arch/arm/dts/r8a7790-lager-u-boot.dts
index 8a37cb9d9a82fd6cfd92edb21f6bca327451f1b0..fecf7e77aee3aefafc175033e7af9f59aaa60126 100644 (file)
--- a/arch/arm/dts/r8a7790-lager-u-boot.dts
+++ b/arch/arm/dts/r8a7790-lager-u-boot.dts
@@ -11,3 +11,10 @@
 &scif0 {
        u-boot,dm-pre-reloc;
 };
+
+&qspi {
+       flash@0 {
+               spi-tx-bus-width = <1>;
+               spi-rx-bus-width = <1>;
+       };
+};

diff --git a/arch/arm/dts/r8a7790-stout-u-boot.dts b/arch/arm/dts/r8a7790-stout-u-boot.dts
index 47982652e8b211e5f21aef2b93cc9bef3fc0e0d2..1396764d32d82fff7ddea07489431651a6280bc1 100644 (file)
--- a/arch/arm/dts/r8a7790-stout-u-boot.dts
+++ b/arch/arm/dts/r8a7790-stout-u-boot.dts
@@ -11,3 +11,10 @@
 &scifa0 {
        u-boot,dm-pre-reloc;
 };
+
+&qspi {
+       flash@0 {
+               spi-tx-bus-width = <1>;
+               spi-rx-bus-width = <1>;
+       };
+};

diff --git a/arch/arm/dts/r8a7791-koelsch-u-boot.dts b/arch/arm/dts/r8a7791-koelsch-u-boot.dts
index 85a5290079f26068d175de49aee320342439d450..4a98528099d30df1d21f5713e4ee401ac86b6569 100644 (file)
--- a/arch/arm/dts/r8a7791-koelsch-u-boot.dts
+++ b/arch/arm/dts/r8a7791-koelsch-u-boot.dts
@@ -11,3 +11,10 @@
 &scif0 {
        u-boot,dm-pre-reloc;
 };
+
+&qspi {
+       flash@0 {
+               spi-tx-bus-width = <1>;
+               spi-rx-bus-width = <1>;
+       };
+};

diff --git a/arch/arm/dts/r8a7791-porter-u-boot.dts b/arch/arm/dts/r8a7791-porter-u-boot.dts
index 275f6b437554aa66605dd6b3fddfc659e5856809..82051be824a1f95aa62b46d39473da75ee83170a 100644 (file)
--- a/arch/arm/dts/r8a7791-porter-u-boot.dts
+++ b/arch/arm/dts/r8a7791-porter-u-boot.dts
@@ -16,3 +16,10 @@
        status = "okay";
        clock-frequency = <400000>;
 };
+
+&qspi {
+       flash@0 {
+               spi-tx-bus-width = <1>;
+               spi-rx-bus-width = <1>;
+       };
+};

diff --git a/arch/arm/dts/r8a7793-gose-u-boot.dts b/arch/arm/dts/r8a7793-gose-u-boot.dts
index d8e072c36be21244d2f38f4890c322396f432adf..a35d35c3357534c0c002cab1247720bf726240c7 100644 (file)
--- a/arch/arm/dts/r8a7793-gose-u-boot.dts
+++ b/arch/arm/dts/r8a7793-gose-u-boot.dts
@@ -11,3 +11,10 @@
 &scif0 {
        u-boot,dm-pre-reloc;
 };
+
+&qspi {
+       flash@0 {
+               spi-tx-bus-width = <1>;
+               spi-rx-bus-width = <1>;
+       };
+};

diff --git a/arch/arm/dts/r8a7794-alt-u-boot.dts b/arch/arm/dts/r8a7794-alt-u-boot.dts
index e6ef23dda3185ba99f6980bbd8a12c2c8b2a504a..593a418c3b120a004f1bc27086cd0b628f7bddb5 100644 (file)
--- a/arch/arm/dts/r8a7794-alt-u-boot.dts
+++ b/arch/arm/dts/r8a7794-alt-u-boot.dts
@@ -11,3 +11,10 @@
 &scif2 {
        u-boot,dm-pre-reloc;
 };
+
+&qspi {
+       flash@0 {
+               spi-tx-bus-width = <1>;
+               spi-rx-bus-width = <1>;
+       };
+};

diff --git a/arch/arm/dts/r8a7794-silk-u-boot.dts b/arch/arm/dts/r8a7794-silk-u-boot.dts
index 0e104aa13937e831fee93fa3dfd785c634537755..179753d7cf543b78923bc07ef4c502369e66a057 100644 (file)
--- a/arch/arm/dts/r8a7794-silk-u-boot.dts
+++ b/arch/arm/dts/r8a7794-silk-u-boot.dts
@@ -11,3 +11,10 @@
 &scif2 {
        u-boot,dm-pre-reloc;
 };
+
+&qspi {
+       flash@0 {
+               spi-tx-bus-width = <1>;
+               spi-rx-bus-width = <1>;
+       };
+};

diff --git a/arch/arm/dts/r8a77965-u-boot.dtsi b/arch/arm/dts/r8a77965-u-boot.dtsi
index cbd29b3aed682bcbfd1b8905e8ce0eb82c998f32..ca80ef8f29ee98265b7f2c4b0565e196c24c9b20 100644 (file)
--- a/arch/arm/dts/r8a77965-u-boot.dtsi
+++ b/arch/arm/dts/r8a77965-u-boot.dtsi
@@ -19,103 +19,4 @@
                bank-width = <2>;
                status = "disabled";
        };
-
-       sdhi0: sd@ee100000 {
-               compatible = "renesas,sdhi-r8a77965";
-               reg = <0 0xee100000 0 0x2000>;
-               interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
-               clocks = <&cpg CPG_MOD 314>;
-               max-frequency = <200000000>;
-               power-domains = <&sysc 32>;
-               resets = <&cpg 314>;
-               status = "disabled";
-       };
-
-       sdhi1: sd@ee120000 {
-               compatible = "renesas,sdhi-r8a77965";
-               reg = <0 0xee120000 0 0x2000>;
-               interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
-               clocks = <&cpg CPG_MOD 313>;
-               max-frequency = <200000000>;
-               power-domains = <&sysc 32>;
-               resets = <&cpg 313>;
-               status = "disabled";
-       };
-
-       sdhi2: sd@ee140000 {
-               compatible = "renesas,sdhi-r8a77965";
-               reg = <0 0xee140000 0 0x2000>;
-               interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
-               clocks = <&cpg CPG_MOD 312>;
-               max-frequency = <200000000>;
-               power-domains = <&sysc 32>;
-               resets = <&cpg 312>;
-               status = "disabled";
-       };
-
-       sdhi3: sd@ee160000 {
-               compatible = "renesas,sdhi-r8a77965";
-               reg = <0 0xee160000 0 0x2000>;
-               interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
-               clocks = <&cpg CPG_MOD 311>;
-               max-frequency = <200000000>;
-               power-domains = <&sysc 32>;
-               resets = <&cpg 311>;
-               status = "disabled";
-       };
-
-       ehci0: usb@ee080100 {
-               compatible = "generic-ehci";
-               reg = <0 0xee080100 0 0x100>;
-               interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
-               clocks = <&cpg CPG_MOD 703>;
-               phys = <&usb2_phy0>;
-               phy-names = "usb";
-               companion= <&ohci0>;
-               power-domains = <&sysc 32>;
-               resets = <&cpg 703>;
-       };
-
-       usb2_phy0: usb-phy@ee080200 {
-               compatible = "renesas,usb2-phy-r8a77965",
-                            "renesas,rcar-gen3-usb2-phy";
-               reg = <0 0xee080200 0 0x700>;
-               interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
-               clocks = <&cpg CPG_MOD 703>;
-               power-domains = <&sysc 32>;
-               resets = <&cpg 703>;
-               #phy-cells = <0>;
-       };
-
-       ehci1: usb@ee0a0100 {
-               compatible = "generic-ehci";
-               reg = <0 0xee0a0100 0 0x100>;
-               interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
-               clocks = <&cpg CPG_MOD 702>;
-               phys = <&usb2_phy1>;
-               phy-names = "usb";
-               companion= <&ohci1>;
-               power-domains = <&sysc 32>;
-               resets = <&cpg 702>;
-       };
-
-       usb2_phy1: usb-phy@ee0a0200 {
-               compatible = "renesas,usb2-phy-r8a77965",
-                            "renesas,rcar-gen3-usb2-phy";
-               reg = <0 0xee0a0200 0 0x700>;
-               clocks = <&cpg CPG_MOD 702>;
-               power-domains = <&sysc 32>;
-               resets = <&cpg 702>;
-               #phy-cells = <0>;
-       };
-
-       xhci0: usb@ee000000 {
-               compatible = "renesas,xhci-r8a77965",
-                            "renesas,rcar-gen3-xhci";
-               reg = <0 0xee000000 0 0xc00>;
-               interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
-               clocks = <&cpg CPG_MOD 328>;
-               power-domains = <&sysc 32>;
-               resets = <&cpg 328>;
-       };
 };

diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index fcf211d62bd628e3a7b10f58ea66e05c7460f3dd..ec8339e04574462af171b97f0f35cdb9ef74d6c0 100644 (file)
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -62,8 +62,8 @@ void v7_outer_cache_enable(void)
        /* Disable the L2 cache */
        clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
 
-       writel(0x111, &pl310->pl310_tag_latency_ctrl);
-       writel(0x121, &pl310->pl310_data_latency_ctrl);
+       writel(0x0, &pl310->pl310_tag_latency_ctrl);
+       writel(0x10, &pl310->pl310_data_latency_ctrl);
 
        /* enable BRESP, instruction and data prefetch, full line of zeroes */
        setbits_le32(&pl310->pl310_aux_ctrl,

diff --git a/arch/arm/mach-socfpga/spl_a10.c b/arch/arm/mach-socfpga/spl_a10.c
index c97eacb424f23f5fecf18f88ec2d97f62c3dbc06..c8e73d47c0b40c3ac11e42f5b07059b255448ba7 100644 (file)
--- a/arch/arm/mach-socfpga/spl_a10.c
+++ b/arch/arm/mach-socfpga/spl_a10.c
@@ -77,6 +77,8 @@ void spl_board_init(void)
 
 void board_init_f(ulong dummy)
 {
+       dcache_disable();
+
        socfpga_init_security_policies();
        socfpga_sdram_remap_zero();
 

diff --git a/arch/x86/dts/coreboot.dts b/arch/x86/dts/coreboot.dts
index e212f3dc7dbe12f19ef49ef99bc4d2565c8b8679..a88da6eafd68f472008046a5cd0015fae9fbcd47 100644 (file)
--- a/arch/x86/dts/coreboot.dts
+++ b/arch/x86/dts/coreboot.dts
@@ -10,6 +10,7 @@
 /include/ "skeleton.dtsi"
 /include/ "serial.dtsi"
 /include/ "keyboard.dtsi"
+/include/ "pcspkr.dtsi"
 /include/ "reset.dtsi"
 /include/ "rtc.dtsi"
 /include/ "tsc_timer.dtsi"

diff --git a/arch/x86/dts/crownbay.dts b/arch/x86/dts/crownbay.dts
index 2ffcc5f27eceaec5bb24bc9e1917cb6f34ab68b3..8938a94e7707c2c503cce2d533d7877ff4b47df1 100644 (file)
--- a/arch/x86/dts/crownbay.dts
+++ b/arch/x86/dts/crownbay.dts
@@ -10,6 +10,7 @@
 /include/ "skeleton.dtsi"
 /include/ "serial.dtsi"
 /include/ "keyboard.dtsi"
+/include/ "pcspkr.dtsi"
 /include/ "reset.dtsi"
 /include/ "rtc.dtsi"
 /include/ "tsc_timer.dtsi"

diff --git a/arch/x86/dts/edison.dts b/arch/x86/dts/edison.dts
index ca8dfb42872386929e39017d7728e7a6977d8509..e8564bbb8a92efca5679d48bbb2261886b1274c5 100644 (file)
--- a/arch/x86/dts/edison.dts
+++ b/arch/x86/dts/edison.dts
@@ -18,10 +18,12 @@
 
        aliases {
                serial0 = &serial0;
+               serial1 = &serial1;
+               serial2 = &serial2;
        };
 
        chosen {
-               stdout-path = &serial0;
+               stdout-path = &serial2;
        };
 
        cpus {
@@ -53,7 +55,23 @@
                          0x01000000 0x0 0x2000 0x2000 0 0xe000>;
        };
 
-       serial0: serial@ff010180 {
+       serial0: serial@ff010080 {
+               compatible = "intel,mid-uart";
+               reg = <0xff010080 0x100>;
+               reg-shift = <0>;
+               clock-frequency = <29491200>;
+               current-speed = <115200>;
+       };
+
+       serial1: serial@ff010100 {
+               compatible = "intel,mid-uart";
+               reg = <0xff010100 0x100>;
+               reg-shift = <0>;
+               clock-frequency = <29491200>;
+               current-speed = <115200>;
+       };
+
+       serial2: serial@ff010180 {
                compatible = "intel,mid-uart";
                reg = <0xff010180 0x100>;
                reg-shift = <0>;

diff --git a/arch/x86/dts/pcspkr.dtsi b/arch/x86/dts/pcspkr.dtsi
new file mode 100644 (file)
index 0000000..934ab10
--- /dev/null
+++ b/arch/x86/dts/pcspkr.dtsi
@@ -0,0 +1,5 @@
+/ {
+       pcspkr {
+               compatible = "i8254,beeper";
+       };
+};

diff --git a/arch/x86/include/asm/arch-tangier/acpi/southcluster.asl b/arch/x86/include/asm/arch-tangier/acpi/southcluster.asl
index baad98b1c7ef50f722f03aaa1b5b7e940a8d8e2b..8b5b709045bd6c75b2a9ac18004a1329988affdd 100644 (file)
--- a/arch/x86/include/asm/arch-tangier/acpi/southcluster.asl
+++ b/arch/x86/include/asm/arch-tangier/acpi/southcluster.asl
@@ -179,6 +179,9 @@ Device (PCI0)
                 "\\_SB.PCI0.GPIO", 0, ResourceConsumer, , ) { 112 }
             GpioIo(Exclusive, PullUp, 0, 0, IoRestrictionOutputOnly,
                 "\\_SB.PCI0.GPIO", 0, ResourceConsumer, , ) { 113 }
+
+            FixedDMA(0x000d, 0x0002, Width32bit, )
+            FixedDMA(0x000c, 0x0003, Width32bit, )
         })
 
         Method (_CRS, 0, NotSerialized)
@@ -219,6 +222,17 @@ Device (PCI0)
         {
             Return (STA_VISIBLE)
         }
+
+        Name (RBUF, ResourceTemplate()
+        {
+            FixedDMA(0x0009, 0x0000, Width32bit, )
+            FixedDMA(0x0008, 0x0001, Width32bit, )
+        })
+
+        Method (_CRS, 0, NotSerialized)
+        {
+            Return (RBUF)
+        }
     }
 
     Device (I2C6)

diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c
index 04058a60d75eb59c20dce160cf751cb11f9b8ad9..270274f6b3b7fa71d2c3586a2e57614013ee7be9 100644 (file)
--- a/arch/x86/lib/acpi_table.c
+++ b/arch/x86/lib/acpi_table.c
@@ -347,7 +347,7 @@ static void acpi_create_spcr(struct acpi_spcr *spcr)
        uint serial_width;
        int access_size;
        int space_id;
-       int ret;
+       int ret = -ENODEV;
 
        /* Fill out header fields */
        acpi_fill_header(header, "SPCR");
@@ -355,8 +355,8 @@ static void acpi_create_spcr(struct acpi_spcr *spcr)
        header->revision = 2;
 
        /* Read the device once, here. It is reused below */
-       ret = uclass_first_device_err(UCLASS_SERIAL, &dev);
-       if (!ret)
+       dev = gd->cur_serial_dev;
+       if (dev)
                ret = serial_getinfo(dev, &serial_info);
        if (ret)
                serial_info.type = SERIAL_CHIP_UNKNOWN;

diff --git a/arch/x86/lib/i8254.c b/arch/x86/lib/i8254.c
index d0227954b16f3ef82e438c9c1c6065e1da2a4593..0f975389103df0d3846056c8a9df640345a45cf5 100644 (file)
--- a/arch/x86/lib/i8254.c
+++ b/arch/x86/lib/i8254.c
@@ -51,6 +51,10 @@ int i8254_enable_beep(uint frequency_hz)
        if (!frequency_hz)
                return -EINVAL;
 
+       /* make sure i8254 is setup correctly before generating beeps */
+       outb(PIT_CMD_CTR2 | PIT_CMD_BOTH | PIT_CMD_MODE3,
+            PIT_BASE + PIT_COMMAND);
+
        i8254_set_beep_freq(frequency_hz);
        setio_8(SYSCTL_PORTB, PORTB_BEEP_ENABLE);
 

diff --git a/board/altera/arria10-socdk/Kconfig b/board/altera/arria10-socdk/Kconfig
index b80cc6d6f93521193beb2cb10aed1371cb56f36f..621dc97024a233033cb214b9aeff7906a038d32d 100644 (file)
--- a/board/altera/arria10-socdk/Kconfig
+++ b/board/altera/arria10-socdk/Kconfig
@@ -1,4 +1,4 @@
-if TARGET_SOCFPGA_ARRIA10
+if TARGET_SOCFPGA_ARRIA10_SOCDK
 
 config SYS_CPU
        default "armv7"

diff --git a/configs/crownbay_defconfig b/configs/crownbay_defconfig
index 34c2eb323ef6513d76979ca13016dbdb840380b1..e0c98247a70d465aec243f042f4e755861e9a62a 100644 (file)
--- a/configs/crownbay_defconfig
+++ b/configs/crownbay_defconfig
@@ -28,6 +28,7 @@ CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
+CONFIG_CMD_SOUND=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
@@ -41,6 +42,8 @@ CONFIG_REGMAP=y
 CONFIG_SYSCON=y
 CONFIG_CPU=y
 CONFIG_E1000=y
+CONFIG_SOUND=y
+CONFIG_SOUND_I8254=y
 CONFIG_SPI=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_KEYBOARD=y

diff --git a/configs/porter_defconfig b/configs/porter_defconfig
index ce309b6d86e02b8e040e180ec8c9b61ac0f63d1b..826f78bb42c43ababf49d0eaa9fbb6bf6865ca2d 100644 (file)
--- a/configs/porter_defconfig
+++ b/configs/porter_defconfig
@@ -62,6 +62,7 @@ CONFIG_DM_MMC=y
 CONFIG_RENESAS_SDHI=y
 CONFIG_MTD=y
 CONFIG_MTD_DEVICE=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_MTD=y
@@ -79,6 +80,7 @@ CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
 CONFIG_SCIF_CONSOLE=y
 CONFIG_SPI=y
+CONFIG_DM_SPI=y
 CONFIG_SH_QSPI=y
 CONFIG_USB=y
 CONFIG_DM_USB=y

diff --git a/configs/silk_defconfig b/configs/silk_defconfig
index 0291a7c98151c887637879fc4aadeae73a30ecc2..09196d7bb8e570e1f5d488f8b785dd9501e36a0c 100644 (file)
--- a/configs/silk_defconfig
+++ b/configs/silk_defconfig
@@ -64,6 +64,7 @@ CONFIG_SH_MMCIF=y
 CONFIG_RENESAS_SDHI=y
 CONFIG_MTD=y
 CONFIG_MTD_DEVICE=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_MTD=y
@@ -81,6 +82,7 @@ CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
 CONFIG_SCIF_CONSOLE=y
 CONFIG_SPI=y
+CONFIG_DM_SPI=y
 CONFIG_SH_QSPI=y
 CONFIG_USB=y
 CONFIG_DM_USB=y

diff --git a/configs/stout_defconfig b/configs/stout_defconfig
index 1c92cb6117a2424d663895cfab5b201f35683eec..552cf55df5d5a0ac2d4266643319583e6638f25d 100644 (file)
--- a/configs/stout_defconfig
+++ b/configs/stout_defconfig
@@ -62,6 +62,7 @@ CONFIG_DM_MMC=y
 CONFIG_RENESAS_SDHI=y
 CONFIG_MTD=y
 CONFIG_MTD_DEVICE=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_MTD=y
@@ -79,6 +80,7 @@ CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
 CONFIG_SCIF_CONSOLE=y
 CONFIG_SPI=y
+CONFIG_DM_SPI=y
 CONFIG_SH_QSPI=y
 CONFIG_USB=y
 CONFIG_DM_USB=y

diff --git a/drivers/clk/sunxi/clk_a10.c b/drivers/clk/sunxi/clk_a10.c
index b8b57e2b3127b2dbfbb2475d72f47f671a3f0732..15ffe5ecb358b3028c4ee33729add821581cbbda 100644 (file)
--- a/drivers/clk/sunxi/clk_a10.c
+++ b/drivers/clk/sunxi/clk_a10.c
@@ -22,6 +22,7 @@ static struct ccu_clk_gate a10_gates[] = {
        [CLK_AHB_MMC1]          = GATE(0x060, BIT(9)),
        [CLK_AHB_MMC2]          = GATE(0x060, BIT(10)),
        [CLK_AHB_MMC3]          = GATE(0x060, BIT(11)),
+       [CLK_AHB_EMAC]          = GATE(0x060, BIT(17)),
        [CLK_AHB_SPI0]          = GATE(0x060, BIT(20)),
        [CLK_AHB_SPI1]          = GATE(0x060, BIT(21)),
        [CLK_AHB_SPI2]          = GATE(0x060, BIT(22)),

diff --git a/drivers/clk/sunxi/clk_a10s.c b/drivers/clk/sunxi/clk_a10s.c
index c6fcede82290866fe309f80812f5d98362180141..33d41d47b0f2c299c8cabe9bc805b42435716f80 100644 (file)
--- a/drivers/clk/sunxi/clk_a10s.c
+++ b/drivers/clk/sunxi/clk_a10s.c
@@ -19,6 +19,7 @@ static struct ccu_clk_gate a10s_gates[] = {
        [CLK_AHB_MMC0]          = GATE(0x060, BIT(8)),
        [CLK_AHB_MMC1]          = GATE(0x060, BIT(9)),
        [CLK_AHB_MMC2]          = GATE(0x060, BIT(10)),
+       [CLK_AHB_EMAC]          = GATE(0x060, BIT(17)),
        [CLK_AHB_SPI0]          = GATE(0x060, BIT(20)),
        [CLK_AHB_SPI1]          = GATE(0x060, BIT(21)),
        [CLK_AHB_SPI2]          = GATE(0x060, BIT(22)),

diff --git a/drivers/clk/sunxi/clk_a31.c b/drivers/clk/sunxi/clk_a31.c
index fa6e3eeef0e2f5b15e6da953147f44e5ae98761c..4ec3c2ae8929c5449e990a6d7c14b9e7355409f1 100644 (file)
--- a/drivers/clk/sunxi/clk_a31.c
+++ b/drivers/clk/sunxi/clk_a31.c
@@ -17,6 +17,7 @@ static struct ccu_clk_gate a31_gates[] = {
        [CLK_AHB1_MMC1]         = GATE(0x060, BIT(9)),
        [CLK_AHB1_MMC2]         = GATE(0x060, BIT(10)),
        [CLK_AHB1_MMC3]         = GATE(0x060, BIT(11)),
+       [CLK_AHB1_EMAC]         = GATE(0x060, BIT(17)),
        [CLK_AHB1_SPI0]         = GATE(0x060, BIT(20)),
        [CLK_AHB1_SPI1]         = GATE(0x060, BIT(21)),
        [CLK_AHB1_SPI2]         = GATE(0x060, BIT(22)),
@@ -57,6 +58,7 @@ static struct ccu_reset a31_resets[] = {
        [RST_AHB1_MMC1]         = RESET(0x2c0, BIT(9)),
        [RST_AHB1_MMC2]         = RESET(0x2c0, BIT(10)),
        [RST_AHB1_MMC3]         = RESET(0x2c0, BIT(11)),
+       [RST_AHB1_EMAC]         = RESET(0x2c0, BIT(17)),
        [RST_AHB1_SPI0]         = RESET(0x2c0, BIT(20)),
        [RST_AHB1_SPI1]         = RESET(0x2c0, BIT(21)),
        [RST_AHB1_SPI2]         = RESET(0x2c0, BIT(22)),

diff --git a/drivers/clk/sunxi/clk_a64.c b/drivers/clk/sunxi/clk_a64.c
index 322d6cd55794cc809ed1c1ad481751a2850c44f5..f94e8aa754a528627aca1264d93b70b08c088a57 100644 (file)
--- a/drivers/clk/sunxi/clk_a64.c
+++ b/drivers/clk/sunxi/clk_a64.c
@@ -16,6 +16,7 @@ static const struct ccu_clk_gate a64_gates[] = {
        [CLK_BUS_MMC0]          = GATE(0x060, BIT(8)),
        [CLK_BUS_MMC1]          = GATE(0x060, BIT(9)),
        [CLK_BUS_MMC2]          = GATE(0x060, BIT(10)),
+       [CLK_BUS_EMAC]          = GATE(0x060, BIT(17)),
        [CLK_BUS_SPI0]          = GATE(0x060, BIT(20)),
        [CLK_BUS_SPI1]          = GATE(0x060, BIT(21)),
        [CLK_BUS_OTG]           = GATE(0x060, BIT(23)),
@@ -49,6 +50,7 @@ static const struct ccu_reset a64_resets[] = {
        [RST_BUS_MMC0]          = RESET(0x2c0, BIT(8)),
        [RST_BUS_MMC1]          = RESET(0x2c0, BIT(9)),
        [RST_BUS_MMC2]          = RESET(0x2c0, BIT(10)),
+       [RST_BUS_EMAC]          = RESET(0x2c0, BIT(17)),
        [RST_BUS_SPI0]          = RESET(0x2c0, BIT(20)),
        [RST_BUS_SPI1]          = RESET(0x2c0, BIT(21)),
        [RST_BUS_OTG]           = RESET(0x2c0, BIT(23)),

diff --git a/drivers/clk/sunxi/clk_a83t.c b/drivers/clk/sunxi/clk_a83t.c
index 36f7e14c45c3e061ac535f5b9c6d1b0da8ae874e..2be87a31fd5301f7c6b9e8dd8cabaff3edaa4b56 100644 (file)
--- a/drivers/clk/sunxi/clk_a83t.c
+++ b/drivers/clk/sunxi/clk_a83t.c
@@ -16,6 +16,7 @@ static struct ccu_clk_gate a83t_gates[] = {
        [CLK_BUS_MMC0]          = GATE(0x060, BIT(8)),
        [CLK_BUS_MMC1]          = GATE(0x060, BIT(9)),
        [CLK_BUS_MMC2]          = GATE(0x060, BIT(10)),
+       [CLK_BUS_EMAC]          = GATE(0x060, BIT(17)),
        [CLK_BUS_SPI0]          = GATE(0x060, BIT(20)),
        [CLK_BUS_SPI1]          = GATE(0x060, BIT(21)),
        [CLK_BUS_OTG]           = GATE(0x060, BIT(24)),
@@ -47,6 +48,7 @@ static struct ccu_reset a83t_resets[] = {
        [RST_BUS_MMC0]          = RESET(0x2c0, BIT(8)),
        [RST_BUS_MMC1]          = RESET(0x2c0, BIT(9)),
        [RST_BUS_MMC2]          = RESET(0x2c0, BIT(10)),
+       [RST_BUS_EMAC]          = RESET(0x2c0, BIT(17)),
        [RST_BUS_SPI0]          = RESET(0x2c0, BIT(20)),
        [RST_BUS_SPI1]          = RESET(0x2c0, BIT(21)),
        [RST_BUS_OTG]           = RESET(0x2c0, BIT(24)),

diff --git a/drivers/clk/sunxi/clk_h3.c b/drivers/clk/sunxi/clk_h3.c
index 5f99ef7342fe3b56586c5834fd937eefb68d0125..6111a13f1c176a53519a1c0ffb5fbe3d74e45c0b 100644 (file)
--- a/drivers/clk/sunxi/clk_h3.c
+++ b/drivers/clk/sunxi/clk_h3.c
@@ -16,6 +16,7 @@ static struct ccu_clk_gate h3_gates[] = {
        [CLK_BUS_MMC0]          = GATE(0x060, BIT(8)),
        [CLK_BUS_MMC1]          = GATE(0x060, BIT(9)),
        [CLK_BUS_MMC2]          = GATE(0x060, BIT(10)),
+       [CLK_BUS_EMAC]          = GATE(0x060, BIT(17)),
        [CLK_BUS_SPI0]          = GATE(0x060, BIT(20)),
        [CLK_BUS_SPI1]          = GATE(0x060, BIT(21)),
        [CLK_BUS_OTG]           = GATE(0x060, BIT(23)),
@@ -33,6 +34,8 @@ static struct ccu_clk_gate h3_gates[] = {
        [CLK_BUS_UART2]         = GATE(0x06c, BIT(18)),
        [CLK_BUS_UART3]         = GATE(0x06c, BIT(19)),
 
+       [CLK_BUS_EPHY]          = GATE(0x070, BIT(0)),
+
        [CLK_SPI0]              = GATE(0x0a0, BIT(31)),
        [CLK_SPI1]              = GATE(0x0a4, BIT(31)),
 
@@ -55,6 +58,7 @@ static struct ccu_reset h3_resets[] = {
        [RST_BUS_MMC0]          = RESET(0x2c0, BIT(8)),
        [RST_BUS_MMC1]          = RESET(0x2c0, BIT(9)),
        [RST_BUS_MMC2]          = RESET(0x2c0, BIT(10)),
+       [RST_BUS_EMAC]          = RESET(0x2c0, BIT(17)),
        [RST_BUS_SPI0]          = RESET(0x2c0, BIT(20)),
        [RST_BUS_SPI1]          = RESET(0x2c0, BIT(21)),
        [RST_BUS_OTG]           = RESET(0x2c0, BIT(23)),
@@ -67,6 +71,8 @@ static struct ccu_reset h3_resets[] = {
        [RST_BUS_OHCI2]         = RESET(0x2c0, BIT(30)),
        [RST_BUS_OHCI3]         = RESET(0x2c0, BIT(31)),
 
+       [RST_BUS_EPHY]          = RESET(0x2c8, BIT(2)),
+
        [RST_BUS_UART0]         = RESET(0x2d8, BIT(16)),
        [RST_BUS_UART1]         = RESET(0x2d8, BIT(17)),
        [RST_BUS_UART2]         = RESET(0x2d8, BIT(18)),

diff --git a/drivers/clk/sunxi/clk_h6.c b/drivers/clk/sunxi/clk_h6.c
index 71f0c78656c0facf2f84061d3c26615c0b2f9b10..0bb00f449aca1bc498ebaf33e9bc8079af204489 100644 (file)
--- a/drivers/clk/sunxi/clk_h6.c
+++ b/drivers/clk/sunxi/clk_h6.c
@@ -26,6 +26,8 @@ static struct ccu_clk_gate h6_gates[] = {
 
        [CLK_BUS_SPI0]          = GATE(0x96c, BIT(0)),
        [CLK_BUS_SPI1]          = GATE(0x96c, BIT(1)),
+
+       [CLK_BUS_EMAC]          = GATE(0x97c, BIT(0)),
 };
 
 static struct ccu_reset h6_resets[] = {
@@ -39,6 +41,8 @@ static struct ccu_reset h6_resets[] = {
 
        [RST_BUS_SPI0]          = RESET(0x96c, BIT(16)),
        [RST_BUS_SPI1]          = RESET(0x96c, BIT(17)),
+
+       [RST_BUS_EMAC]          = RESET(0x97c, BIT(16)),
 };
 
 static const struct ccu_desc h6_ccu_desc = {

diff --git a/drivers/clk/sunxi/clk_r40.c b/drivers/clk/sunxi/clk_r40.c
index 92907281f1ad746f3ede9f3b5a44859e449d3077..30beac98bb88eb998ed03e65b61027c6fbfea786 100644 (file)
--- a/drivers/clk/sunxi/clk_r40.c
+++ b/drivers/clk/sunxi/clk_r40.c
@@ -29,6 +29,8 @@ static struct ccu_clk_gate r40_gates[] = {
        [CLK_BUS_OHCI1]         = GATE(0x060, BIT(30)),
        [CLK_BUS_OHCI2]         = GATE(0x060, BIT(31)),
 
+       [CLK_BUS_GMAC]          = GATE(0x064, BIT(17)),
+
        [CLK_BUS_UART0]         = GATE(0x06c, BIT(16)),
        [CLK_BUS_UART1]         = GATE(0x06c, BIT(17)),
        [CLK_BUS_UART2]         = GATE(0x06c, BIT(18)),
@@ -60,6 +62,7 @@ static struct ccu_reset r40_resets[] = {
        [RST_BUS_MMC1]          = RESET(0x2c0, BIT(9)),
        [RST_BUS_MMC2]          = RESET(0x2c0, BIT(10)),
        [RST_BUS_MMC3]          = RESET(0x2c0, BIT(11)),
+       [RST_BUS_GMAC]          = RESET(0x2c0, BIT(17)),
        [RST_BUS_SPI0]          = RESET(0x2c0, BIT(20)),
        [RST_BUS_SPI1]          = RESET(0x2c0, BIT(21)),
        [RST_BUS_SPI2]          = RESET(0x2c0, BIT(22)),

diff --git a/drivers/ddr/altera/sdram_arria10.c b/drivers/ddr/altera/sdram_arria10.c
index 29ea7492f30299acc8a282ecfd044d068b052c56..1777e7e1a50e8caf6ebbda79d28a547f9ff17e0e 100644 (file)
--- a/drivers/ddr/altera/sdram_arria10.c
+++ b/drivers/ddr/altera/sdram_arria10.c
@@ -31,7 +31,6 @@ static u64 sdram_size_calc(void);
 #define DDR_REG_CORE2SEQ        0xFFD05078
 #define DDR_READ_LATENCY_DELAY 40
 #define DDR_SIZE_2GB_HEX       0x80000000
-#define DDR_MAX_TRIES          0x00100000
 
 #define IO48_MMR_DRAMSTS       0xFFCFA0EC
 #define IO48_MMR_NIOS2_RESERVE0        0xFFCFA110
@@ -103,52 +102,18 @@ static int match_ddr_conf(u32 ddr_conf)
        return 0;
 }
 
-/* Check whether SDRAM is successfully Calibrated */
-static int is_sdram_cal_success(void)
-{
-       return readl(&socfpga_ecc_hmc_base->ddrcalstat);
-}
-
-static unsigned char ddr_get_bit(u32 ereg, unsigned char bit)
-{
-       u32 reg = readl(ereg);
-
-       return (reg & BIT(bit)) ? 1 : 0;
-}
-
-static unsigned char ddr_wait_bit(u32 ereg, u32 bit,
-                          u32 expected, u32 timeout_usec)
-{
-       u32 tmr;
-
-       for (tmr = 0; tmr < timeout_usec; tmr += 100) {
-               udelay(100);
-               WATCHDOG_RESET();
-               if (ddr_get_bit(ereg, bit) == expected)
-                       return 0;
-       }
-
-       return 1;
-}
-
 static int emif_clear(void)
 {
-       u32 i = DDR_MAX_TRIES;
-       u8 ret = 0;
-
        writel(0, DDR_REG_CORE2SEQ);
 
-       do {
-               ret = !wait_for_bit_le32((u32 *)DDR_REG_SEQ2CORE,
-                                  SEQ2CORE_MASK, 1, 50, 0);
-       } while (ret && (--i > 0));
-
-       return !i;
+       return wait_for_bit_le32((u32 *)DDR_REG_SEQ2CORE,
+                               SEQ2CORE_MASK, 0, 1000, 0);
 }
 
 static int emif_reset(void)
 {
        u32 c2s, s2c;
+       int ret;
 
        c2s = readl(DDR_REG_CORE2SEQ);
        s2c = readl(DDR_REG_SEQ2CORE);
@@ -159,21 +124,28 @@ static int emif_reset(void)
             readl(IO48_MMR_NIOS2_RESERVE2),
             readl(IO48_MMR_DRAMSTS));
 
-       if ((s2c & SEQ2CORE_MASK) && emif_clear()) {
-               debug("failed emif_clear()\n");
-               return -EPERM;
+       if (s2c & SEQ2CORE_MASK) {
+               ret = emif_clear();
+               if (ret) {
+                       debug("failed emif_clear()\n");
+                       return -EPERM;
+               }
        }
 
        writel(CORE2SEQ_INT_REQ, DDR_REG_CORE2SEQ);
 
-       if (ddr_wait_bit(DDR_REG_SEQ2CORE, SEQ2CORE_INT_RESP_BIT, 0, 1000000)) {
+       ret = wait_for_bit_le32((u32 *)DDR_REG_SEQ2CORE,
+                               SEQ2CORE_INT_RESP_BIT, false, 1000, false);
+       if (ret) {
                debug("emif_reset failed to see interrupt acknowledge\n");
-               return -EPERM;
-       } else {
-               debug("emif_reset interrupt acknowledged\n");
+               emif_clear();
+               return ret;
        }
 
-       if (emif_clear()) {
+       mdelay(1);
+
+       ret = emif_clear();
+       if (ret) {
                debug("emif_clear() failed\n");
                return -EPERM;
        }
@@ -189,30 +161,23 @@ static int emif_reset(void)
 
 static int ddr_setup(void)
 {
-       int i, j, ddr_setup_complete = 0;
-
-       /* Try 3 times to do a calibration */
-       for (i = 0; (i < 3) && !ddr_setup_complete; i++) {
-               WATCHDOG_RESET();
-
-               /* A delay to wait for calibration bit to set */
-               for (j = 0; (j < 10) && !ddr_setup_complete; j++) {
-                       mdelay(500);
-                       ddr_setup_complete = is_sdram_cal_success();
-               }
-
-               if (!ddr_setup_complete)
-                       if (emif_reset())
-                               puts("Error: Failed to reset EMIF\n");
-       }
+       int i, ret;
+
+       /* Try 32 times to do a calibration */
+       for (i = 0; i < 32; i++) {
+               mdelay(500);
+               ret = wait_for_bit_le32(&socfpga_ecc_hmc_base->ddrcalstat,
+                                       BIT(0), true, 500, false);
+               if (!ret)
+                       return 0;
 
-       /* After 3 times trying calibration */
-       if (!ddr_setup_complete) {
-               puts("Error: Could Not Calibrate SDRAM\n");
-               return -EPERM;
+               ret = emif_reset();
+               if (ret)
+                       puts("Error: Failed to reset EMIF\n");
        }
 
-       return 0;
+       puts("Error: Could Not Calibrate SDRAM\n");
+       return -EPERM;
 }
 
 static int sdram_is_ecc_enabled(void)
@@ -270,7 +235,7 @@ static u64 sdram_size_calc(void)
        size *= (2 << (readl(&socfpga_ecc_hmc_base->ddrioctrl) &
                       ALT_ECC_HMC_OCP_DDRIOCTRL_IO_SIZE_MSK));
 
-       debug("SDRAM size=%llu", size);
+       debug("SDRAM size=%llu\n", size);
 
        return size;
 }
@@ -304,7 +269,7 @@ static void sdram_mmr_init(void)
         *      bit[9:6] = Minor Release #
         *      bit[14:10] = Major Release #
         */
-       if ((socfpga_io48_mmr_base->niosreserve1 >> 6) & 0x1FF) {
+       if ((readl(&socfpga_io48_mmr_base->niosreserve1) >> 6) & 0x1FF) {
                update_value = readl(&socfpga_io48_mmr_base->niosreserve0);
                writel(((update_value & 0xFF) >> 5),
                       &socfpga_ecc_hmc_base->ddrioctrl);
@@ -394,7 +359,7 @@ static void sdram_mmr_init(void)
                        caltim0_cfg_act_to_rdwr -
                        (ctrlcfg0_cfg_ctrl_burst_len >> 2));
 
-       io48_value = ((((socfpga_io48_mmr_base->dramtiming0 &
+       io48_value = ((((readl(&socfpga_io48_mmr_base->dramtiming0) &
                      ALT_IO48_DRAMTIME_MEM_READ_LATENCY_MASK) + 2 + 15 +
                      (ctrlcfg0_cfg_ctrl_burst_len >> 1)) >> 1) -
                      /* Up to here was in memory cycles so divide by 2 */
@@ -424,7 +389,7 @@ static void sdram_mmr_init(void)
                &socfpga_noc_ddr_scheduler_base->ddr_t_main_scheduler_ddrmode);
 
        /* Configure the read latency [0xFFD12414] */
-       writel(((socfpga_io48_mmr_base->dramtiming0 &
+       writel(((readl(&socfpga_io48_mmr_base->dramtiming0) &
                ALT_IO48_DRAMTIME_MEM_READ_LATENCY_MASK) >> 1) +
                DDR_READ_LATENCY_DELAY,
                &socfpga_noc_ddr_scheduler_base->

diff --git a/drivers/power/axp818.c b/drivers/power/axp818.c
index c737da1180fb53c0348a101114a26ffbb9dd9836..834919ddd4c189af7d16d5e956eb1903315153d4 100644 (file)
--- a/drivers/power/axp818.c
+++ b/drivers/power/axp818.c
@@ -161,7 +161,7 @@ int axp_set_dldo(int dldo_num, unsigned int mvolt)
        cfg = axp818_mvolt_to_cfg(mvolt, 700, 3300, 100);
        if (dldo_num == 2 && mvolt > 3300)
                cfg += 1 + axp818_mvolt_to_cfg(mvolt, 3400, 4200, 200);
-       ret = pmic_bus_write(AXP818_ELDO1_CTRL + (dldo_num - 1), cfg);
+       ret = pmic_bus_write(AXP818_DLDO1_CTRL + (dldo_num - 1), cfg);
        if (ret)
                return ret;
 

diff --git a/include/configs/rcar-gen2-common.h b/include/configs/rcar-gen2-common.h
index d606da8b0ec4bff262d415e0b47b5cfe16af3d3c..9213d33e217f44e33eea9a4e62e32a3ba377e1c6 100644 (file)
--- a/include/configs/rcar-gen2-common.h
+++ b/include/configs/rcar-gen2-common.h
@@ -53,6 +53,8 @@
 /* SF MTD */
 #if defined(CONFIG_SPI_FLASH_MTD) && !defined(CONFIG_SPL_BUILD)
 #else
+#undef CONFIG_DM_SPI
+#undef CONFIG_DM_SPI_FLASH
 #undef CONFIG_SPI_FLASH_MTD
 #endif
 

diff --git a/include/configs/rcar-gen3-common.h b/include/configs/rcar-gen3-common.h
index 06d5d3219ca65425bbcf0233453ab6f76e24f756..20f982165dd5c381d641381b0adb749e68dcb9f4 100644 (file)
--- a/include/configs/rcar-gen3-common.h
+++ b/include/configs/rcar-gen3-common.h
@@ -48,7 +48,6 @@
 #define CONFIG_SYS_MONITOR_BASE                0x00000000
 #define CONFIG_SYS_MONITOR_LEN         (256 * 1024)
 #define CONFIG_SYS_MALLOC_LEN          (1 * 1024 * 1024)
-#define CONFIG_SYS_BOOTMAPSZ           (8 * 1024 * 1024)
 #define CONFIG_SYS_BOOTM_LEN           (64 << 20)
 
 /* ENV setting */

diff --git a/include/configs/socfpga_arria10_socdk.h b/include/configs/socfpga_arria10_socdk.h
index 58e446b60a90042adae850355ce86885d2ee8a6f..0f116fbf2d981d2cfa4779ba34cfd852c95c6373 100644 (file)
--- a/include/configs/socfpga_arria10_socdk.h
+++ b/include/configs/socfpga_arria10_socdk.h
@@ -15,8 +15,6 @@
 /*
  * U-Boot general configurations
  */
-/* Cache options */
-#define CONFIG_SYS_DCACHE_OFF
 
 /* Memory configurations  */
 #define PHYS_SDRAM_1_SIZE              0x40000000

diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index c9cbf8f5e37247367203953f13e3ceca5039638b..181af9b646a385857f3d5f2e5a544ca443ddc077 100644 (file)
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -275,13 +275,20 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
 
 /* SPL QSPI boot support */
 #ifdef CONFIG_SPL_SPI_SUPPORT
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 #define CONFIG_SYS_SPI_U_BOOT_OFFS     0x40000
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#define CONFIG_SYS_SPI_U_BOOT_OFFS     0x100000
+#endif
 #endif
 
 /* SPL NAND boot support */
 #ifdef CONFIG_SPL_NAND_SUPPORT
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS  0
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 #define CONFIG_SYS_NAND_U_BOOT_OFFS    0x40000
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#define CONFIG_SYS_NAND_U_BOOT_OFFS    0x100000
+#endif
 #endif
 
 /*