arm: dts: mediatek: move u-boot properties to -u-boot.dtsi file

This patch move u-boot properties to -u-boot.dtsi file.

Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>

diff --git a/arch/arm/dts/mt7623-u-boot.dtsi b/arch/arm/dts/mt7623-u-boot.dtsi
new file mode 100644 (file)
index 0000000..832c16d
--- /dev/null
+++ b/arch/arm/dts/mt7623-u-boot.dtsi
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ * Author: Sam Shih <sam.shih@mediatek.com>
+ */
+
+&topckgen {
+       u-boot,dm-pre-reloc;
+};
+
+&topckgen {
+       u-boot,dm-pre-reloc;
+};
+
+&pericfg {
+       u-boot,dm-pre-reloc;
+};
+
+&timer0 {
+       u-boot,dm-pre-reloc;
+};
+
+&apmixedsys {
+       u-boot,dm-pre-reloc;
+};
+
+&uart2 {
+       u-boot,dm-pre-reloc;
+};

diff --git a/arch/arm/dts/mt7623.dtsi b/arch/arm/dts/mt7623.dtsi
index 1135b1e1ae02657c19583079a4b98363c4846d55..1f45dea575bb07eb72aa54d0ff13b9460ca97851 100644 (file)
--- a/arch/arm/dts/mt7623.dtsi
+++ b/arch/arm/dts/mt7623.dtsi
@@ -101,21 +101,18 @@
                compatible = "mediatek,mt7623-topckgen";
                reg = <0x10000000 0x1000>;
                #clock-cells = <1>;
-               u-boot,dm-pre-reloc;
        };
 
        infracfg: syscon@10001000 {
                compatible = "mediatek,mt7623-infracfg", "syscon";
                reg = <0x10001000 0x1000>;
                #clock-cells = <1>;
-               u-boot,dm-pre-reloc;
        };
 
        pericfg: syscon@10003000 {
                compatible = "mediatek,mt7623-pericfg", "syscon";
                reg = <0x10003000 0x1000>;
                #clock-cells = <1>;
-               u-boot,dm-pre-reloc;
        };
 
        pinctrl: pinctrl@10005000 {
@@ -155,7 +152,6 @@
                interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>;
                clocks = <&system_clk>;
                clock-names = "system-clk";
-               u-boot,dm-pre-reloc;
        };
 
        sysirq: interrupt-controller@10200100 {
@@ -170,7 +166,6 @@
                compatible = "mediatek,mt7623-apmixedsys";
                reg = <0x10209000 0x1000>;
                #clock-cells = <1>;
-               u-boot,dm-pre-reloc;
        };
 
        gic: interrupt-controller@10211000 {
@@ -215,7 +210,6 @@
                         <&pericfg CLK_PERI_UART2>;
                clock-names = "baud", "bus";
                status = "disabled";
-               u-boot,dm-pre-reloc;
        };
 
        uart3: serial@11005000 {

diff --git a/arch/arm/dts/mt7623n-bananapi-bpi-r2.dts b/arch/arm/dts/mt7623n-bananapi-bpi-r2.dts
index b0c86219b6cba8f9c2e9b9520c6d6dda50f6433c..bcedcf20f133a3a8fe85b3a1af459c0106c04aa3 100644 (file)
--- a/arch/arm/dts/mt7623n-bananapi-bpi-r2.dts
+++ b/arch/arm/dts/mt7623n-bananapi-bpi-r2.dts
@@ -7,6 +7,7 @@
 
 /dts-v1/;
 #include "mt7623.dtsi"
+#include "mt7623-u-boot.dtsi"
 
 / {
        model = "Bananapi BPI-R2";

diff --git a/arch/arm/dts/mt7629-rfb-u-boot.dtsi b/arch/arm/dts/mt7629-rfb-u-boot.dtsi
index 1ef55685189e43966e3e56e347f6349d49e8ebec..164afd633b6dc28f533f0a998cd90b4d16581a04 100644 (file)
--- a/arch/arm/dts/mt7629-rfb-u-boot.dtsi
+++ b/arch/arm/dts/mt7629-rfb-u-boot.dtsi
@@ -22,3 +22,39 @@
 #endif
        };
 };
+
+&infracfg {
+       u-boot,dm-pre-reloc;
+};
+
+&pericfg {
+       u-boot,dm-pre-reloc;
+};
+
+&timer0 {
+       u-boot,dm-pre-reloc;
+};
+
+&mcucfg {
+       u-boot,dm-pre-reloc;
+};
+
+&dramc {
+       u-boot,dm-pre-reloc;
+};
+
+&apmixedsys {
+       u-boot,dm-pre-reloc;
+};
+
+&topckgen {
+       u-boot,dm-pre-reloc;
+};
+
+&uart0 {
+       u-boot,dm-pre-reloc;
+};
+
+&snfi {
+       u-boot,dm-pre-reloc;
+};

diff --git a/arch/arm/dts/mt7629-rfb.dts b/arch/arm/dts/mt7629-rfb.dts
index 0981f9b3b1e0eff9aff8a10b690036f08c28d4f1..687fe1c02971a99001d7db94b378c3af8e1a1650 100644 (file)
--- a/arch/arm/dts/mt7629-rfb.dts
+++ b/arch/arm/dts/mt7629-rfb.dts
@@ -7,6 +7,7 @@
 
 /dts-v1/;
 #include "mt7629.dtsi"
+#include "mt7629-rfb-u-boot.dtsi"
 
 / {
        model = "MediaTek MT7629 RFB";

diff --git a/arch/arm/dts/mt7629.dtsi b/arch/arm/dts/mt7629.dtsi
index b0c843bafdeadbc8f23910862cf11ceb522323c3..a33a74a5568477a808af0a8478849e71878230eb 100644 (file)
--- a/arch/arm/dts/mt7629.dtsi
+++ b/arch/arm/dts/mt7629.dtsi
@@ -68,14 +68,12 @@
                compatible = "mediatek,mt7629-infracfg", "syscon";
                reg = <0x10000000 0x1000>;
                #clock-cells = <1>;
-               u-boot,dm-pre-reloc;
        };
 
        pericfg: syscon@10002000 {
                compatible = "mediatek,mt7629-pericfg", "syscon";
                reg = <0x10002000 0x1000>;
                #clock-cells = <1>;
-               u-boot,dm-pre-reloc;
        };
 
        timer0: timer@10004000 {
@@ -85,7 +83,6 @@
                clocks = <&topckgen CLK_TOP_CLKXTAL_D4>,
                         <&topckgen CLK_TOP_10M_SEL>;
                clock-names = "mux", "src";
-               u-boot,dm-pre-reloc;
        };
 
        scpsys: scpsys@10006000 {
@@ -103,7 +100,6 @@
                compatible = "mediatek,mt7629-mcucfg", "syscon";
                reg = <0x10200000 0x1000>;
                #clock-cells = <1>;
-               u-boot,dm-pre-reloc;
        };
 
        sysirq: interrupt-controller@10200a80 {
@@ -124,21 +120,18 @@
                         <&topckgen CLK_TOP_MEM_SEL>,
                         <&topckgen CLK_TOP_DMPLL>;
                clock-names = "phy", "phy_mux", "mem", "mem_mux";
-               u-boot,dm-pre-reloc;
        };
 
        apmixedsys: clock-controller@10209000 {
                compatible = "mediatek,mt7629-apmixedsys";
                reg = <0x10209000 0x1000>;
                #clock-cells = <1>;
-               u-boot,dm-pre-reloc;
        };
 
        topckgen: clock-controller@10210000 {
                compatible = "mediatek,mt7629-topckgen";
                reg = <0x10210000 0x1000>;
                #clock-cells = <1>;
-               u-boot,dm-pre-reloc;
        };
 
        watchdog: watchdog@10212000 {
@@ -186,7 +179,6 @@
                status = "disabled";
                assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>;
                assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>;
-               u-boot,dm-pre-reloc;
        };
 
        uart1: serial@11003000 {
@@ -228,7 +220,6 @@
                status = "disabled";
                #address-cells = <1>;
                #size-cells = <0>;
-               u-boot,dm-pre-reloc;
        };
 
        ethsys: syscon@1b000000 {