string
option env="UBOOTVERSION"
-config KCONFIG_OBJDIR
- string
- option env="KCONFIG_OBJDIR"
+# Allow defaults in arch-specific code to override any given here
+source "arch/Kconfig"
menu "General setup"
config LOCALVERSION
string "Local version - append to U-Boot release"
- depends on !SPL_BUILD
help
Append an extra string to the end of your U-Boot version.
This will show up on your boot log, for example.
config LOCALVERSION_AUTO
bool "Automatically append version information to the version string"
- depends on !SPL_BUILD
default y
help
This will try to automatically determine if the current tree is a
config CC_OPTIMIZE_FOR_SIZE
bool "Optimize for size"
- depends on !SPL_BUILD
default y
help
Enabling this option will pass "-Os" instead of "-O2" to gcc
menu "Boot images"
-config SPL_BUILD
- bool
- depends on $KCONFIG_OBJDIR="spl" || $KCONFIG_OBJDIR="tpl"
- default y
-
-config TPL_BUILD
- bool
- depends on $KCONFIG_OBJDIR="tpl"
- default y
-
config SUPPORT_SPL
bool
config SPL
bool
depends on SUPPORT_SPL
- prompt "Enable SPL" if !SPL_BUILD
- default y if SPL_BUILD
+ prompt "Enable SPL"
help
If you want to build SPL as well as the normal image, say Y.
config TPL
bool
depends on SPL && SUPPORT_TPL
- prompt "Enable TPL" if !SPL_BUILD
- default y if TPL_BUILD
- default n
+ prompt "Enable TPL"
help
If you want to build TPL as well as the normal image and SPL, say Y.
config FIT
bool "Support Flattened Image Tree"
- depends on !SPL_BUILD
help
This option allows to boot the new uImage structrure,
Flattened Image Tree. FIT is formally a FDT, which can include
select RSA
help
This option enables signature verification of FIT uImages,
- using a hash signed and verified using RSA.
+ using a hash signed and verified using RSA. If
+ CONFIG_SHA_PROG_HW_ACCEL is defined, i.e support for progressive
+ hashing is available using hardware, RSA library will use it.
See doc/uImage.FIT/signature.txt for more details.
config SYS_EXTRA_OPTIONS
string "Extra Options (DEPRECATED)"
- depends on !SPL_BUILD
help
The old configuration infrastructure (= mkconfig + boards.cfg)
provided the extra options field. If you have something like
endmenu # Boot images
-source "arch/Kconfig"
-
source "common/Kconfig"
source "dts/Kconfig"
S: Maintained
T: git git://git.denx.de/u-boot-dfu.git
F: drivers/dfu/
+F: drivers/usb/gadget/
DRIVER MODEL
M: Simon Glass <sjg@chromium.org>
Enable the hash verify command (hash -v). This adds to code
size a little.
- CONFIG_SHA1 - support SHA1 hashing
- CONFIG_SHA256 - support SHA256 hashing
+ CONFIG_SHA1 - This option enables support of hashing using SHA1
+ algorithm. The hash is calculated in software.
+ CONFIG_SHA256 - This option enables support of hashing using
+ SHA256 algorithm. The hash is calculated in software.
+ CONFIG_SHA_HW_ACCEL - This option enables hardware acceleration
+ for SHA1/SHA256 hashing.
+ This affects the 'hash' command and also the
+ hash_lookup_algo() function.
+ CONFIG_SHA_PROG_HW_ACCEL - This option enables
+ hardware-acceleration for SHA1/SHA256 progressive hashing.
+ Data can be streamed in a block at a time and the hashing
+ is performed in hardware.
Note: There is also a sha1sum command, which should perhaps
be deprecated in favour of 'hash sha1'.
CONFIG_FIT_SIGNATURE
This option enables signature verification of FIT uImages,
- using a hash signed and verified using RSA. See
- doc/uImage.FIT/signature.txt for more details.
+ using a hash signed and verified using RSA. If
+ CONFIG_SHA_PROG_HW_ACCEL is defined, i.e support for progressive
+ hashing is available using hardware, RSA library will use it.
+ See doc/uImage.FIT/signature.txt for more details.
WARNING: When relying on signed FIT images with required
signature check the legacy image format is default
- CONFIG_FSL_DDR_INTERACTIVE
Enable interactive DDR debugging. See doc/README.fsl-ddr.
+- CONFIG_FSL_DDR_SYNC_REFRESH
+ Enable sync of refresh for multiple controllers.
+
- CONFIG_SYS_83XX_DDR_USES_CS0
Only for 83xx systems. If specified, then DDR should
be configured using CS0 and CS1 instead of CS2 and CS3.
bool "Support integratorcp_cm920t"
select CPU_ARM920T
-config TARGET_A320EVB
- bool "Support a320evb"
- select CPU_ARM920T
-
config ARCH_AT91
bool "Atmel AT91"
bool "Support scb9328"
select CPU_ARM920T
-config TARGET_CM4008
- bool "Support cm4008"
- select CPU_ARM920T
-
-config TARGET_CM41XX
- bool "Support cm41xx"
- select CPU_ARM920T
-
config TARGET_VCMA9
bool "Support VCMA9"
select CPU_ARM920T
bool "Support devkit3250"
select CPU_ARM926EJS
-config TARGET_JADECPU
- bool "Support jadecpu"
- select CPU_ARM926EJS
-
config TARGET_MX25PDK
bool "Support mx25pdk"
select CPU_ARM926EJS
bool "Marvell Orion"
select CPU_ARM926EJS
-config TARGET_DKB
- bool "Support dkb"
- select CPU_ARM926EJS
-
config TARGET_SPEAR300
bool "Support spear300"
select CPU_ARM926EJS
bool "Support rpi_2"
select CPU_V7
-config TARGET_TNETV107X_EVM
- bool "Support tnetv107x_evm"
- select CPU_ARM1176
-
config TARGET_INTEGRATORAP_CM946ES
bool "Support integratorap_cm946es"
select CPU_ARM946ES
bool "NVIDIA Tegra"
select SUPPORT_SPL
select SPL
- select OF_CONTROL if !SPL_BUILD
- select CPU_ARM720T if SPL_BUILD
- select CPU_V7 if !SPL_BUILD
+ select OF_CONTROL
+ select CPU_V7
config TARGET_VEXPRESS64_AEMV8A
bool "Support vexpress_aemv8a"
select CPU_V7
select SUPPORT_SPL
select SPL
- select OF_CONTROL if !SPL_BUILD
+ select OF_CONTROL
endchoice
source "board/CarMediaLab/flea3/Kconfig"
source "board/Marvell/aspenite/Kconfig"
source "board/Marvell/db-mv784mp-gp/Kconfig"
-source "board/Marvell/dkb/Kconfig"
source "board/Marvell/gplugd/Kconfig"
source "board/altera/socfpga/Kconfig"
source "board/armadeus/apf27/Kconfig"
source "board/broadcom/bcmcygnus/Kconfig"
source "board/broadcom/bcmnsp/Kconfig"
source "board/cirrus/edb93xx/Kconfig"
-source "board/cm4008/Kconfig"
-source "board/cm41xx/Kconfig"
source "board/compulab/cm_t335/Kconfig"
source "board/compulab/cm_fx6/Kconfig"
source "board/congatec/cgtqmx6eval/Kconfig"
source "board/denx/m53evk/Kconfig"
source "board/embest/mx6boards/Kconfig"
source "board/esg/ima3-mx53/Kconfig"
-source "board/faraday/a320evb/Kconfig"
source "board/freescale/ls2085a/Kconfig"
source "board/freescale/ls1021aqds/Kconfig"
source "board/freescale/ls1021atwr/Kconfig"
source "board/st-ericsson/u8500/Kconfig"
source "board/st/stv0991/Kconfig"
source "board/sunxi/Kconfig"
-source "board/syteco/jadecpu/Kconfig"
source "board/syteco/zmx25/Kconfig"
source "board/tbs/tbs2910/Kconfig"
source "board/ti/am335x/Kconfig"
source "board/ti/am43xx/Kconfig"
source "board/ti/ti814x/Kconfig"
source "board/ti/ti816x/Kconfig"
-source "board/ti/tnetv107xevm/Kconfig"
source "board/timll/devkit3250/Kconfig"
source "board/toradex/colibri_pxa270/Kconfig"
source "board/tqc/tqma6/Kconfig"
obj-y = cpu.o
obj-$(CONFIG_BCM2835) += bcm2835/
-obj-$(CONFIG_TNETV107X) += tnetv107x/
if TARGET_RPI || TARGET_RPI_2
config DM
- default y if !SPL_BUILD
+ default y
config DM_SERIAL
- default y if !SPL_BUILD
+ default y
config DM_GPIO
- default y if !SPL_BUILD
+ default y
endif
mov pc, r2
mmu_disable_phys:
-#ifdef CONFIG_DISABLE_TCM
- /*
- * Disable the TCMs
- */
- mrc p15, 0, r0, c0, c0, 2 /* Return TCM details */
- cmp r0, #0
- beq skip_tcmdisable
- mov r1, #0
- mov r2, #1
- tst r0, r2
- mcrne p15, 0, r1, c9, c1, 1 /* Disable Instruction TCM if present*/
- tst r0, r2, LSL #16
- mcrne p15, 0, r1, c9, c1, 0 /* Disable Data TCM if present*/
-skip_tcmdisable:
-#endif
-#endif
-
-#ifdef CONFIG_PERIPORT_REMAP
- /* Peri port setup */
- ldr r0, =CONFIG_PERIPORT_BASE
- orr r0, r0, #CONFIG_PERIPORT_SIZE
- mcr p15,0,r0,c15,c2,4
#endif
/*
+++ /dev/null
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += aemif.o clock.o init.o mux.o timer.o
-obj-y += lowlevel_init.o
+++ /dev/null
-/*
- * TNETV107X: Asynchronous EMIF Configuration
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/mux.h>
-
-#define ASYNC_EMIF_BASE TNETV107X_ASYNC_EMIF_CNTRL_BASE
-#define ASYNC_EMIF_CONFIG(cs) (ASYNC_EMIF_BASE+0x10+(cs)*4)
-#define ASYNC_EMIF_ONENAND_CONTROL (ASYNC_EMIF_BASE+0x5c)
-#define ASYNC_EMIF_NAND_CONTROL (ASYNC_EMIF_BASE+0x60)
-#define ASYNC_EMIF_WAITCYCLE_CONFIG (ASYNC_EMIF_BASE+0x4)
-
-#define CONFIG_SELECT_STROBE(v) ((v) ? 1 << 31 : 0)
-#define CONFIG_EXTEND_WAIT(v) ((v) ? 1 << 30 : 0)
-#define CONFIG_WR_SETUP(v) (((v) & 0x0f) << 26)
-#define CONFIG_WR_STROBE(v) (((v) & 0x3f) << 20)
-#define CONFIG_WR_HOLD(v) (((v) & 0x07) << 17)
-#define CONFIG_RD_SETUP(v) (((v) & 0x0f) << 13)
-#define CONFIG_RD_STROBE(v) (((v) & 0x3f) << 7)
-#define CONFIG_RD_HOLD(v) (((v) & 0x07) << 4)
-#define CONFIG_TURN_AROUND(v) (((v) & 0x03) << 2)
-#define CONFIG_WIDTH(v) (((v) & 0x03) << 0)
-
-#define NUM_CS 4
-
-#define set_config_field(reg, field, val) \
- do { \
- if (val != -1) { \
- reg &= ~CONFIG_##field(0xffffffff); \
- reg |= CONFIG_##field(val); \
- } \
- } while (0)
-
-void configure_async_emif(int cs, struct async_emif_config *cfg)
-{
- unsigned long tmp;
-
- if (cfg->mode == ASYNC_EMIF_MODE_NAND) {
- tmp = __raw_readl(ASYNC_EMIF_NAND_CONTROL);
- tmp |= (1 << cs);
- __raw_writel(tmp, ASYNC_EMIF_NAND_CONTROL);
-
- } else if (cfg->mode == ASYNC_EMIF_MODE_ONENAND) {
- tmp = __raw_readl(ASYNC_EMIF_ONENAND_CONTROL);
- tmp |= (1 << cs);
- __raw_writel(tmp, ASYNC_EMIF_ONENAND_CONTROL);
- }
-
- tmp = __raw_readl(ASYNC_EMIF_CONFIG(cs));
-
- set_config_field(tmp, SELECT_STROBE, cfg->select_strobe);
- set_config_field(tmp, EXTEND_WAIT, cfg->extend_wait);
- set_config_field(tmp, WR_SETUP, cfg->wr_setup);
- set_config_field(tmp, WR_STROBE, cfg->wr_strobe);
- set_config_field(tmp, WR_HOLD, cfg->wr_hold);
- set_config_field(tmp, RD_SETUP, cfg->rd_setup);
- set_config_field(tmp, RD_STROBE, cfg->rd_strobe);
- set_config_field(tmp, RD_HOLD, cfg->rd_hold);
- set_config_field(tmp, TURN_AROUND, cfg->turn_around);
- set_config_field(tmp, WIDTH, cfg->width);
-
- __raw_writel(tmp, ASYNC_EMIF_CONFIG(cs));
-}
-
-void init_async_emif(int num_cs, struct async_emif_config *config)
-{
- int cs;
-
- clk_enable(TNETV107X_LPSC_AEMIF);
-
- for (cs = 0; cs < num_cs; cs++)
- configure_async_emif(cs, config + cs);
-}
+++ /dev/null
-/*
- * TNETV107X: Clock management APIs
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm-generic/errno.h>
-#include <asm/io.h>
-#include <asm/processor.h>
-#include <asm/arch/clock.h>
-
-#define CLOCK_BASE TNETV107X_CLOCK_CONTROL_BASE
-#define PSC_BASE TNETV107X_PSC_BASE
-
-#define BIT(x) (1 << (x))
-
-#define MAX_PREDIV 64
-#define MAX_POSTDIV 8UL
-#define MAX_MULT 512
-#define MAX_DIV (MAX_PREDIV * MAX_POSTDIV)
-
-/* LPSC registers */
-#define PSC_PTCMD 0x120
-#define PSC_PTSTAT 0x128
-#define PSC_MDSTAT(n) (0x800 + (n) * 4)
-#define PSC_MDCTL(n) (0xA00 + (n) * 4)
-
-#define PSC_MDCTL_LRSTZ BIT(8)
-
-#define psc_reg_read(reg) __raw_readl((u32 *)(PSC_BASE + (reg)))
-#define psc_reg_write(reg, val) __raw_writel(val, (u32 *)(PSC_BASE + (reg)))
-
-/* SSPLL registers */
-struct sspll_regs {
- u32 modes;
- u32 postdiv;
- u32 prediv;
- u32 mult_factor;
- u32 divider_range;
- u32 bw_divider;
- u32 spr_amount;
- u32 spr_rate_div;
- u32 diag;
-};
-
-/* SSPLL base addresses */
-static struct sspll_regs *sspll_regs[] = {
- (struct sspll_regs *)(CLOCK_BASE + 0x040),
- (struct sspll_regs *)(CLOCK_BASE + 0x080),
- (struct sspll_regs *)(CLOCK_BASE + 0x0c0),
-};
-
-#define sspll_reg(pll, reg) (&(sspll_regs[pll]->reg))
-#define sspll_reg_read(pll, reg) __raw_readl(sspll_reg(pll, reg))
-#define sspll_reg_write(pll, reg, val) __raw_writel(val, sspll_reg(pll, reg))
-
-
-/* PLL Control Registers */
-struct pllctl_regs {
- u32 ctl; /* 00 */
- u32 ocsel; /* 04 */
- u32 secctl; /* 08 */
- u32 __pad0;
- u32 mult; /* 10 */
- u32 prediv; /* 14 */
- u32 div1; /* 18 */
- u32 div2; /* 1c */
- u32 div3; /* 20 */
- u32 oscdiv1; /* 24 */
- u32 postdiv; /* 28 */
- u32 bpdiv; /* 2c */
- u32 wakeup; /* 30 */
- u32 __pad1;
- u32 cmd; /* 38 */
- u32 stat; /* 3c */
- u32 alnctl; /* 40 */
- u32 dchange; /* 44 */
- u32 cken; /* 48 */
- u32 ckstat; /* 4c */
- u32 systat; /* 50 */
- u32 ckctl; /* 54 */
- u32 __pad2[2];
- u32 div4; /* 60 */
- u32 div5; /* 64 */
- u32 div6; /* 68 */
- u32 div7; /* 6c */
- u32 div8; /* 70 */
-};
-
-struct lpsc_map {
- int pll, div;
-};
-
-static struct pllctl_regs *pllctl_regs[] = {
- (struct pllctl_regs *)(CLOCK_BASE + 0x700),
- (struct pllctl_regs *)(CLOCK_BASE + 0x300),
- (struct pllctl_regs *)(CLOCK_BASE + 0x500),
-};
-
-#define pllctl_reg(pll, reg) (&(pllctl_regs[pll]->reg))
-#define pllctl_reg_read(pll, reg) __raw_readl(pllctl_reg(pll, reg))
-#define pllctl_reg_write(pll, reg, val) __raw_writel(val, pllctl_reg(pll, reg))
-
-#define pllctl_reg_rmw(pll, reg, mask, val) \
- pllctl_reg_write(pll, reg, \
- (pllctl_reg_read(pll, reg) & ~(mask)) | val)
-
-#define pllctl_reg_setbits(pll, reg, mask) \
- pllctl_reg_rmw(pll, reg, 0, mask)
-
-#define pllctl_reg_clrbits(pll, reg, mask) \
- pllctl_reg_rmw(pll, reg, mask, 0)
-
-/* PLLCTL Bits */
-#define PLLCTL_CLKMODE BIT(8)
-#define PLLCTL_PLLSELB BIT(7)
-#define PLLCTL_PLLENSRC BIT(5)
-#define PLLCTL_PLLDIS BIT(4)
-#define PLLCTL_PLLRST BIT(3)
-#define PLLCTL_PLLPWRDN BIT(1)
-#define PLLCTL_PLLEN BIT(0)
-
-#define PLLDIV_ENABLE BIT(15)
-
-static int pll_div_offset[] = {
-#define div_offset(reg) offsetof(struct pllctl_regs, reg)
- div_offset(div1), div_offset(div2), div_offset(div3),
- div_offset(div4), div_offset(div5), div_offset(div6),
- div_offset(div7), div_offset(div8),
-};
-
-static unsigned long pll_bypass_mask[] = { 1, 4, 2 };
-static unsigned long pll_div_mask[] = { 0x01ff, 0x00ff, 0x00ff };
-
-/* Mappings from PLL+DIV to subsystem clocks */
-#define sys_arm1176_clk {SYS_PLL, 0}
-#define sys_dsp_clk {SYS_PLL, 1}
-#define sys_ddr_clk {SYS_PLL, 2}
-#define sys_full_clk {SYS_PLL, 3}
-#define sys_lcd_clk {SYS_PLL, 4}
-#define sys_vlynq_ref_clk {SYS_PLL, 5}
-#define sys_tsc_clk {SYS_PLL, 6}
-#define sys_half_clk {SYS_PLL, 7}
-
-#define eth_clk_5 {ETH_PLL, 0}
-#define eth_clk_50 {ETH_PLL, 1}
-#define eth_clk_125 {ETH_PLL, 2}
-#define eth_clk_250 {ETH_PLL, 3}
-#define eth_clk_25 {ETH_PLL, 4}
-
-#define tdm_clk {TDM_PLL, 0}
-#define tdm_extra_clk {TDM_PLL, 1}
-#define tdm1_clk {TDM_PLL, 2}
-
-static const struct lpsc_map lpsc_clk_map[] = {
- [TNETV107X_LPSC_ARM] = sys_arm1176_clk,
- [TNETV107X_LPSC_GEM] = sys_dsp_clk,
- [TNETV107X_LPSC_DDR2_PHY] = sys_ddr_clk,
- [TNETV107X_LPSC_TPCC] = sys_full_clk,
- [TNETV107X_LPSC_TPTC0] = sys_full_clk,
- [TNETV107X_LPSC_TPTC1] = sys_full_clk,
- [TNETV107X_LPSC_RAM] = sys_full_clk,
- [TNETV107X_LPSC_MBX_LITE] = sys_arm1176_clk,
- [TNETV107X_LPSC_LCD] = sys_lcd_clk,
- [TNETV107X_LPSC_ETHSS] = eth_clk_125,
- [TNETV107X_LPSC_AEMIF] = sys_full_clk,
- [TNETV107X_LPSC_CHIP_CFG] = sys_half_clk,
- [TNETV107X_LPSC_TSC] = sys_tsc_clk,
- [TNETV107X_LPSC_ROM] = sys_half_clk,
- [TNETV107X_LPSC_UART2] = sys_half_clk,
- [TNETV107X_LPSC_PKTSEC] = sys_half_clk,
- [TNETV107X_LPSC_SECCTL] = sys_half_clk,
- [TNETV107X_LPSC_KEYMGR] = sys_half_clk,
- [TNETV107X_LPSC_KEYPAD] = sys_half_clk,
- [TNETV107X_LPSC_GPIO] = sys_half_clk,
- [TNETV107X_LPSC_MDIO] = sys_half_clk,
- [TNETV107X_LPSC_SDIO0] = sys_half_clk,
- [TNETV107X_LPSC_UART0] = sys_half_clk,
- [TNETV107X_LPSC_UART1] = sys_half_clk,
- [TNETV107X_LPSC_TIMER0] = sys_half_clk,
- [TNETV107X_LPSC_TIMER1] = sys_half_clk,
- [TNETV107X_LPSC_WDT_ARM] = sys_half_clk,
- [TNETV107X_LPSC_WDT_DSP] = sys_half_clk,
- [TNETV107X_LPSC_SSP] = sys_half_clk,
- [TNETV107X_LPSC_TDM0] = tdm_clk,
- [TNETV107X_LPSC_VLYNQ] = sys_vlynq_ref_clk,
- [TNETV107X_LPSC_MCDMA] = sys_half_clk,
- [TNETV107X_LPSC_USB0] = sys_half_clk,
- [TNETV107X_LPSC_TDM1] = tdm1_clk,
- [TNETV107X_LPSC_DEBUGSS] = sys_half_clk,
- [TNETV107X_LPSC_ETHSS_RGMII] = eth_clk_250,
- [TNETV107X_LPSC_SYSTEM] = sys_half_clk,
- [TNETV107X_LPSC_IMCOP] = sys_dsp_clk,
- [TNETV107X_LPSC_SPARE] = sys_half_clk,
- [TNETV107X_LPSC_SDIO1] = sys_half_clk,
- [TNETV107X_LPSC_USB1] = sys_half_clk,
- [TNETV107X_LPSC_USBSS] = sys_half_clk,
- [TNETV107X_LPSC_DDR2_EMIF1_VRST] = sys_ddr_clk,
- [TNETV107X_LPSC_DDR2_EMIF2_VCTL_RST] = sys_ddr_clk,
-};
-
-static const unsigned long pll_ext_freq[] = {
- [SYS_PLL] = CONFIG_PLL_SYS_EXT_FREQ,
- [ETH_PLL] = CONFIG_PLL_ETH_EXT_FREQ,
- [TDM_PLL] = CONFIG_PLL_TDM_EXT_FREQ,
-};
-
-static unsigned long pll_freq_get(int pll)
-{
- unsigned long mult = 1, prediv = 1, postdiv = 1;
- unsigned long ref = CONFIG_SYS_INT_OSC_FREQ;
- unsigned long ret;
- u32 bypass;
-
- bypass = __raw_readl((u32 *)(CLOCK_BASE));
- if (!(bypass & pll_bypass_mask[pll])) {
- mult = sspll_reg_read(pll, mult_factor);
- prediv = sspll_reg_read(pll, prediv) + 1;
- postdiv = sspll_reg_read(pll, postdiv) + 1;
- }
-
- if (pllctl_reg_read(pll, ctl) & PLLCTL_CLKMODE)
- ref = pll_ext_freq[pll];
-
- if (!(pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN))
- return ref;
-
- ret = (unsigned long)(ref + ((unsigned long long)ref * mult) / 256);
- ret /= (prediv * postdiv);
-
- return ret;
-}
-
-static unsigned long __pll_div_freq_get(int pll, unsigned int fpll,
- int div)
-{
- int divider = 1;
- unsigned long divreg;
-
- divreg = __raw_readl((void *)pllctl_regs[pll] + pll_div_offset[div]);
-
- if (divreg & PLLDIV_ENABLE)
- divider = (divreg & pll_div_mask[pll]) + 1;
-
- return fpll / divider;
-}
-
-static unsigned long pll_div_freq_get(int pll, int div)
-{
- unsigned int fpll = pll_freq_get(pll);
-
- return __pll_div_freq_get(pll, fpll, div);
-}
-
-static void __pll_div_freq_set(int pll, unsigned int fpll, int div,
- unsigned long hz)
-{
- int divider = (fpll / hz - 1);
-
- divider &= pll_div_mask[pll];
- divider |= PLLDIV_ENABLE;
-
- __raw_writel(divider, (void *)pllctl_regs[pll] + pll_div_offset[div]);
- pllctl_reg_setbits(pll, alnctl, (1 << div));
- pllctl_reg_setbits(pll, dchange, (1 << div));
-}
-
-static unsigned long pll_div_freq_set(int pll, int div, unsigned long hz)
-{
- unsigned int fpll = pll_freq_get(pll);
-
- __pll_div_freq_set(pll, fpll, div, hz);
-
- pllctl_reg_write(pll, cmd, 1);
-
- /* Wait until new divider takes effect */
- while (pllctl_reg_read(pll, stat) & 0x01);
-
- return __pll_div_freq_get(pll, fpll, div);
-}
-
-unsigned long clk_get_rate(unsigned int clk)
-{
- return pll_div_freq_get(lpsc_clk_map[clk].pll, lpsc_clk_map[clk].div);
-}
-
-unsigned long clk_round_rate(unsigned int clk, unsigned long hz)
-{
- unsigned long fpll, divider, pll;
-
- pll = lpsc_clk_map[clk].pll;
- fpll = pll_freq_get(pll);
- divider = (fpll / hz - 1);
- divider &= pll_div_mask[pll];
-
- return fpll / (divider + 1);
-}
-
-int clk_set_rate(unsigned int clk, unsigned long _hz)
-{
- unsigned long hz;
-
- hz = clk_round_rate(clk, _hz);
- if (hz != _hz)
- return -EINVAL; /* Cannot set to target freq */
-
- pll_div_freq_set(lpsc_clk_map[clk].pll, lpsc_clk_map[clk].div, hz);
- return 0;
-}
-
-void lpsc_control(int mod, unsigned long state, int lrstz)
-{
- u32 mdctl;
-
- mdctl = psc_reg_read(PSC_MDCTL(mod));
- mdctl &= ~0x1f;
- mdctl |= state;
-
- if (lrstz == 0)
- mdctl &= ~PSC_MDCTL_LRSTZ;
- else if (lrstz == 1)
- mdctl |= PSC_MDCTL_LRSTZ;
-
- psc_reg_write(PSC_MDCTL(mod), mdctl);
-
- psc_reg_write(PSC_PTCMD, 1);
-
- /* wait for power domain transition to end */
- while (psc_reg_read(PSC_PTSTAT) & 1);
-
- /* Wait for module state change */
- while ((psc_reg_read(PSC_MDSTAT(mod)) & 0x1f) != state);
-}
-
-int lpsc_status(unsigned int id)
-{
- return psc_reg_read(PSC_MDSTAT(id)) & 0x1f;
-}
-
-static void init_pll(const struct pll_init_data *data)
-{
- unsigned long fpll;
- unsigned long best_pre = 0, best_post = 0, best_mult = 0;
- unsigned long div, prediv, postdiv, mult;
- unsigned long delta, actual;
- long best_delta = -1;
- int i;
- u32 tmp;
-
- if (data->pll == SYS_PLL)
- return; /* cannot reconfigure system pll on the fly */
-
- tmp = pllctl_reg_read(data->pll, ctl);
- if (data->internal_osc) {
- tmp &= ~PLLCTL_CLKMODE;
- fpll = CONFIG_SYS_INT_OSC_FREQ;
- } else {
- tmp |= PLLCTL_CLKMODE;
- fpll = pll_ext_freq[data->pll];
- }
- pllctl_reg_write(data->pll, ctl, tmp);
-
- mult = data->pll_freq / fpll;
- for (mult = max(mult, 1UL); mult <= MAX_MULT; mult++) {
- div = (fpll * mult) / data->pll_freq;
- if (div < 1 || div > MAX_DIV)
- continue;
-
- for (postdiv = 1; postdiv <= min(div, MAX_POSTDIV); postdiv++) {
- prediv = div / postdiv;
- if (prediv < 1 || prediv > MAX_PREDIV)
- continue;
-
- actual = (fpll / prediv) * (mult / postdiv);
- delta = (actual - data->pll_freq);
- if (delta < 0)
- delta = -delta;
- if ((delta < best_delta) || (best_delta == -1)) {
- best_delta = delta;
- best_mult = mult;
- best_pre = prediv;
- best_post = postdiv;
- if (delta == 0)
- goto done;
- }
- }
- }
-done:
-
- if (best_delta == -1) {
- printf("pll cannot derive %lu from %lu\n",
- data->pll_freq, fpll);
- return;
- }
-
- fpll = fpll * best_mult;
- fpll /= best_pre * best_post;
-
- pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLENSRC);
- pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLEN);
-
- pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLRST);
-
- pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLPWRDN);
- pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLDIS);
-
- sspll_reg_write(data->pll, mult_factor, (best_mult - 1) << 8);
- sspll_reg_write(data->pll, prediv, best_pre - 1);
- sspll_reg_write(data->pll, postdiv, best_post - 1);
-
- for (i = 0; i < 10; i++)
- if (data->div_freq[i])
- __pll_div_freq_set(data->pll, fpll, i,
- data->div_freq[i]);
-
- pllctl_reg_write(data->pll, cmd, 1);
-
- /* Wait until pll "go" operation completes */
- while (pllctl_reg_read(data->pll, stat) & 0x01);
-
- pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLRST);
- pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLEN);
-}
-
-void init_plls(int num_pll, struct pll_init_data *config)
-{
- int i;
-
- for (i = 0; i < num_pll; i++)
- init_pll(&config[i]);
-}
+++ /dev/null
-/*
- * TNETV107X: Architecture initialization
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-
-void chip_configuration_unlock(void)
-{
- __raw_writel(TNETV107X_KICK0_MAGIC, TNETV107X_KICK0);
- __raw_writel(TNETV107X_KICK1_MAGIC, TNETV107X_KICK1);
-}
-
-int arch_cpu_init(void)
-{
- icache_enable();
- chip_configuration_unlock();
-
- return 0;
-}
+++ /dev/null
-/*
- * TNETV107X: Low-level pre-relocation initialization
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-.globl lowlevel_init
-lowlevel_init:
- /* nothing for now, maybe needed for more exotic boot modes */
- mov pc, lr
+++ /dev/null
-/*
- * TNETV107X: Pinmux configuration
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/mux.h>
-
-#define MUX_MODE_1 0x00
-#define MUX_MODE_2 0x04
-#define MUX_MODE_3 0x0c
-#define MUX_MODE_4 0x1c
-
-#define MUX_DEBUG 0
-
-static const struct pin_config pin_table[] = {
- /* reg shift mode */
- TNETV107X_MUX_CFG(0, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(0, 0, MUX_MODE_2),
- TNETV107X_MUX_CFG(0, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(0, 5, MUX_MODE_2),
- TNETV107X_MUX_CFG(0, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(0, 10, MUX_MODE_2),
- TNETV107X_MUX_CFG(0, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(0, 15, MUX_MODE_2),
- TNETV107X_MUX_CFG(0, 20, MUX_MODE_1),
- TNETV107X_MUX_CFG(0, 20, MUX_MODE_2),
- TNETV107X_MUX_CFG(0, 25, MUX_MODE_1),
- TNETV107X_MUX_CFG(0, 25, MUX_MODE_2),
- TNETV107X_MUX_CFG(1, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(1, 0, MUX_MODE_2),
- TNETV107X_MUX_CFG(1, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(1, 5, MUX_MODE_2),
- TNETV107X_MUX_CFG(1, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(1, 10, MUX_MODE_2),
- TNETV107X_MUX_CFG(1, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(1, 15, MUX_MODE_2),
- TNETV107X_MUX_CFG(1, 20, MUX_MODE_1),
- TNETV107X_MUX_CFG(1, 20, MUX_MODE_2),
- TNETV107X_MUX_CFG(1, 25, MUX_MODE_1),
- TNETV107X_MUX_CFG(1, 25, MUX_MODE_2),
- TNETV107X_MUX_CFG(2, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(2, 0, MUX_MODE_2),
- TNETV107X_MUX_CFG(2, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(2, 5, MUX_MODE_2),
- TNETV107X_MUX_CFG(2, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(2, 10, MUX_MODE_2),
- TNETV107X_MUX_CFG(2, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(2, 15, MUX_MODE_2),
- TNETV107X_MUX_CFG(2, 20, MUX_MODE_1),
- TNETV107X_MUX_CFG(2, 20, MUX_MODE_2),
- TNETV107X_MUX_CFG(2, 25, MUX_MODE_1),
- TNETV107X_MUX_CFG(2, 25, MUX_MODE_2),
- TNETV107X_MUX_CFG(3, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(3, 0, MUX_MODE_2),
- TNETV107X_MUX_CFG(3, 0, MUX_MODE_4),
- TNETV107X_MUX_CFG(3, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(3, 5, MUX_MODE_2),
- TNETV107X_MUX_CFG(3, 5, MUX_MODE_4),
- TNETV107X_MUX_CFG(3, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(3, 10, MUX_MODE_2),
- TNETV107X_MUX_CFG(3, 10, MUX_MODE_4),
- TNETV107X_MUX_CFG(3, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(3, 15, MUX_MODE_2),
- TNETV107X_MUX_CFG(3, 15, MUX_MODE_4),
- TNETV107X_MUX_CFG(3, 20, MUX_MODE_1),
- TNETV107X_MUX_CFG(3, 20, MUX_MODE_2),
- TNETV107X_MUX_CFG(3, 20, MUX_MODE_4),
- TNETV107X_MUX_CFG(3, 25, MUX_MODE_1),
- TNETV107X_MUX_CFG(3, 25, MUX_MODE_2),
- TNETV107X_MUX_CFG(3, 25, MUX_MODE_4),
- TNETV107X_MUX_CFG(4, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(4, 0, MUX_MODE_2),
- TNETV107X_MUX_CFG(4, 0, MUX_MODE_4),
- TNETV107X_MUX_CFG(4, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(4, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(4, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(4, 15, MUX_MODE_4),
- TNETV107X_MUX_CFG(4, 20, MUX_MODE_1),
- TNETV107X_MUX_CFG(4, 20, MUX_MODE_3),
- TNETV107X_MUX_CFG(4, 25, MUX_MODE_1),
- TNETV107X_MUX_CFG(4, 25, MUX_MODE_4),
- TNETV107X_MUX_CFG(5, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(5, 0, MUX_MODE_4),
- TNETV107X_MUX_CFG(5, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(5, 5, MUX_MODE_4),
- TNETV107X_MUX_CFG(5, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(5, 10, MUX_MODE_4),
- TNETV107X_MUX_CFG(5, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(5, 15, MUX_MODE_4),
- TNETV107X_MUX_CFG(5, 20, MUX_MODE_1),
- TNETV107X_MUX_CFG(5, 20, MUX_MODE_4),
- TNETV107X_MUX_CFG(5, 25, MUX_MODE_1),
- TNETV107X_MUX_CFG(5, 25, MUX_MODE_4),
- TNETV107X_MUX_CFG(6, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(6, 0, MUX_MODE_4),
- TNETV107X_MUX_CFG(6, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(6, 5, MUX_MODE_4),
- TNETV107X_MUX_CFG(6, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(6, 10, MUX_MODE_4),
- TNETV107X_MUX_CFG(6, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(6, 15, MUX_MODE_4),
- TNETV107X_MUX_CFG(6, 20, MUX_MODE_1),
- TNETV107X_MUX_CFG(6, 20, MUX_MODE_4),
- TNETV107X_MUX_CFG(6, 25, MUX_MODE_1),
- TNETV107X_MUX_CFG(6, 25, MUX_MODE_4),
- TNETV107X_MUX_CFG(7, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(7, 0, MUX_MODE_4),
- TNETV107X_MUX_CFG(7, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(7, 5, MUX_MODE_4),
- TNETV107X_MUX_CFG(7, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(7, 10, MUX_MODE_4),
- TNETV107X_MUX_CFG(7, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(7, 15, MUX_MODE_2),
- TNETV107X_MUX_CFG(7, 20, MUX_MODE_1),
- TNETV107X_MUX_CFG(7, 20, MUX_MODE_2),
- TNETV107X_MUX_CFG(7, 25, MUX_MODE_1),
- TNETV107X_MUX_CFG(7, 25, MUX_MODE_2),
- TNETV107X_MUX_CFG(8, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(8, 0, MUX_MODE_2),
- TNETV107X_MUX_CFG(8, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(8, 5, MUX_MODE_2),
- TNETV107X_MUX_CFG(8, 5, MUX_MODE_4),
- TNETV107X_MUX_CFG(8, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(8, 10, MUX_MODE_2),
- TNETV107X_MUX_CFG(9, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(9, 0, MUX_MODE_2),
- TNETV107X_MUX_CFG(9, 0, MUX_MODE_4),
- TNETV107X_MUX_CFG(9, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(9, 5, MUX_MODE_2),
- TNETV107X_MUX_CFG(9, 5, MUX_MODE_4),
- TNETV107X_MUX_CFG(9, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(9, 10, MUX_MODE_2),
- TNETV107X_MUX_CFG(9, 10, MUX_MODE_4),
- TNETV107X_MUX_CFG(9, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(9, 15, MUX_MODE_2),
- TNETV107X_MUX_CFG(9, 15, MUX_MODE_4),
- TNETV107X_MUX_CFG(9, 20, MUX_MODE_1),
- TNETV107X_MUX_CFG(9, 20, MUX_MODE_2),
- TNETV107X_MUX_CFG(9, 20, MUX_MODE_4),
- TNETV107X_MUX_CFG(10, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(10, 0, MUX_MODE_2),
- TNETV107X_MUX_CFG(10, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(10, 5, MUX_MODE_2),
- TNETV107X_MUX_CFG(10, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(10, 10, MUX_MODE_2),
- TNETV107X_MUX_CFG(10, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(10, 15, MUX_MODE_2),
- TNETV107X_MUX_CFG(10, 20, MUX_MODE_1),
- TNETV107X_MUX_CFG(10, 20, MUX_MODE_2),
- TNETV107X_MUX_CFG(10, 25, MUX_MODE_1),
- TNETV107X_MUX_CFG(10, 25, MUX_MODE_2),
- TNETV107X_MUX_CFG(11, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(11, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(12, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(12, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(12, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(12, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(12, 20, MUX_MODE_1),
- TNETV107X_MUX_CFG(12, 25, MUX_MODE_1),
- TNETV107X_MUX_CFG(13, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(13, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(13, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(13, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(14, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(14, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(14, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(14, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(14, 20, MUX_MODE_1),
- TNETV107X_MUX_CFG(14, 25, MUX_MODE_1),
- TNETV107X_MUX_CFG(15, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(15, 0, MUX_MODE_2),
- TNETV107X_MUX_CFG(15, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(15, 5, MUX_MODE_2),
- TNETV107X_MUX_CFG(15, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(15, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(15, 20, MUX_MODE_1),
- TNETV107X_MUX_CFG(15, 25, MUX_MODE_1),
- TNETV107X_MUX_CFG(16, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(16, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(16, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(16, 10, MUX_MODE_2),
- TNETV107X_MUX_CFG(16, 10, MUX_MODE_3),
- TNETV107X_MUX_CFG(16, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(16, 15, MUX_MODE_2),
- TNETV107X_MUX_CFG(17, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(17, 0, MUX_MODE_2),
- TNETV107X_MUX_CFG(17, 0, MUX_MODE_3),
- TNETV107X_MUX_CFG(17, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(17, 5, MUX_MODE_2),
- TNETV107X_MUX_CFG(17, 5, MUX_MODE_3),
- TNETV107X_MUX_CFG(17, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(17, 10, MUX_MODE_2),
- TNETV107X_MUX_CFG(17, 10, MUX_MODE_3),
- TNETV107X_MUX_CFG(17, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(17, 15, MUX_MODE_2),
- TNETV107X_MUX_CFG(17, 15, MUX_MODE_3),
- TNETV107X_MUX_CFG(18, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(18, 0, MUX_MODE_2),
- TNETV107X_MUX_CFG(18, 0, MUX_MODE_3),
- TNETV107X_MUX_CFG(18, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(18, 5, MUX_MODE_2),
- TNETV107X_MUX_CFG(18, 5, MUX_MODE_3),
- TNETV107X_MUX_CFG(18, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(18, 10, MUX_MODE_2),
- TNETV107X_MUX_CFG(18, 10, MUX_MODE_3),
- TNETV107X_MUX_CFG(18, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(18, 15, MUX_MODE_2),
- TNETV107X_MUX_CFG(18, 15, MUX_MODE_3),
- TNETV107X_MUX_CFG(19, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(19, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(19, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(19, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(19, 20, MUX_MODE_1),
- TNETV107X_MUX_CFG(19, 25, MUX_MODE_1),
- TNETV107X_MUX_CFG(20, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(20, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(20, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(20, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(20, 15, MUX_MODE_3),
- TNETV107X_MUX_CFG(20, 20, MUX_MODE_1),
- TNETV107X_MUX_CFG(20, 25, MUX_MODE_1),
- TNETV107X_MUX_CFG(21, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(21, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(21, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(21, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(21, 20, MUX_MODE_1),
- TNETV107X_MUX_CFG(21, 25, MUX_MODE_1),
- TNETV107X_MUX_CFG(22, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(22, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(22, 5, MUX_MODE_3),
- TNETV107X_MUX_CFG(22, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(22, 10, MUX_MODE_3),
- TNETV107X_MUX_CFG(22, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(22, 15, MUX_MODE_2),
- TNETV107X_MUX_CFG(22, 15, MUX_MODE_3),
- TNETV107X_MUX_CFG(22, 20, MUX_MODE_1),
- TNETV107X_MUX_CFG(22, 20, MUX_MODE_3),
- TNETV107X_MUX_CFG(22, 25, MUX_MODE_1),
- TNETV107X_MUX_CFG(22, 25, MUX_MODE_3),
- TNETV107X_MUX_CFG(23, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(23, 0, MUX_MODE_3),
- TNETV107X_MUX_CFG(23, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(23, 5, MUX_MODE_3),
- TNETV107X_MUX_CFG(23, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(23, 10, MUX_MODE_3),
- TNETV107X_MUX_CFG(24, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(24, 0, MUX_MODE_2),
- TNETV107X_MUX_CFG(24, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(24, 5, MUX_MODE_2),
- TNETV107X_MUX_CFG(24, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(24, 10, MUX_MODE_2),
- TNETV107X_MUX_CFG(24, 10, MUX_MODE_3),
- TNETV107X_MUX_CFG(24, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(24, 15, MUX_MODE_2),
- TNETV107X_MUX_CFG(24, 15, MUX_MODE_3),
- TNETV107X_MUX_CFG(24, 20, MUX_MODE_1),
- TNETV107X_MUX_CFG(24, 20, MUX_MODE_2),
- TNETV107X_MUX_CFG(24, 25, MUX_MODE_1),
- TNETV107X_MUX_CFG(24, 25, MUX_MODE_2),
- TNETV107X_MUX_CFG(25, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(25, 0, MUX_MODE_2),
- TNETV107X_MUX_CFG(25, 0, MUX_MODE_3),
- TNETV107X_MUX_CFG(25, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(25, 5, MUX_MODE_2),
- TNETV107X_MUX_CFG(25, 5, MUX_MODE_3),
- TNETV107X_MUX_CFG(25, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(25, 10, MUX_MODE_2),
- TNETV107X_MUX_CFG(25, 10, MUX_MODE_3),
- TNETV107X_MUX_CFG(25, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(25, 15, MUX_MODE_2),
- TNETV107X_MUX_CFG(25, 15, MUX_MODE_3),
- TNETV107X_MUX_CFG(25, 15, MUX_MODE_4),
- TNETV107X_MUX_CFG(26, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(26, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(26, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(26, 10, MUX_MODE_2),
- TNETV107X_MUX_CFG(26, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(26, 15, MUX_MODE_2),
- TNETV107X_MUX_CFG(26, 20, MUX_MODE_1),
- TNETV107X_MUX_CFG(26, 20, MUX_MODE_2),
- TNETV107X_MUX_CFG(26, 25, MUX_MODE_1),
- TNETV107X_MUX_CFG(26, 25, MUX_MODE_2),
-};
-
-const int pin_table_size = sizeof(pin_table) / sizeof(pin_table[0]);
-
-int mux_select_pin(short index)
-{
- const struct pin_config *cfg;
- unsigned long mask, mode, reg;
-
- if (index >= pin_table_size)
- return 0;
-
- cfg = &pin_table[index];
-
- mask = 0x1f << cfg->mask_offset;
- mode = cfg->mode << cfg->mask_offset;
-
- reg = __raw_readl(TNETV107X_PINMUX(cfg->reg_index));
- reg = (reg & ~mask) | mode;
- __raw_writel(reg, TNETV107X_PINMUX(cfg->reg_index));
-
- return 1;
-}
-
-int mux_select_pins(const short *pins)
-{
- int i, ret = 1;
-
- for (i = 0; pins[i] >= 0; i++)
- ret &= mux_select_pin(pins[i]);
-
- return ret;
-}
+++ /dev/null
-/*
- * TNETV107X: Timer implementation
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-
-struct timer_regs {
- u_int32_t pid12;
- u_int32_t pad[3];
- u_int32_t tim12;
- u_int32_t tim34;
- u_int32_t prd12;
- u_int32_t prd34;
- u_int32_t tcr;
- u_int32_t tgcr;
- u_int32_t wdtcr;
-};
-
-#define regs ((struct timer_regs *)CONFIG_SYS_TIMERBASE)
-
-#define TIMER_LOAD_VAL (CONFIG_SYS_HZ_CLOCK / CONFIG_SYS_HZ)
-#define TIM_CLK_DIV 16
-
-static ulong timestamp;
-static ulong lastinc;
-
-int timer_init(void)
-{
- clk_enable(TNETV107X_LPSC_TIMER0);
-
- lastinc = timestamp = 0;
-
- /* We are using timer34 in unchained 32-bit mode, full speed */
- __raw_writel(0x0, ®s->tcr);
- __raw_writel(0x0, ®s->tgcr);
- __raw_writel(0x06 | ((TIM_CLK_DIV - 1) << 8), ®s->tgcr);
- __raw_writel(0x0, ®s->tim34);
- __raw_writel(TIMER_LOAD_VAL, ®s->prd34);
- __raw_writel(2 << 22, ®s->tcr);
-
- return 0;
-}
-
-static ulong get_timer_raw(void)
-{
- ulong now = __raw_readl(®s->tim34);
-
- if (now >= lastinc)
- timestamp += now - lastinc;
- else
- timestamp += now + TIMER_LOAD_VAL - lastinc;
-
- lastinc = now;
-
- return timestamp;
-}
-
-ulong get_timer(ulong base)
-{
- return (get_timer_raw() / (TIMER_LOAD_VAL / TIM_CLK_DIV)) - base;
-}
-
-unsigned long long get_ticks(void)
-{
- return get_timer(0);
-}
-
-void __udelay(unsigned long usec)
-{
- ulong tmo;
- ulong endtime;
- signed long diff;
-
- tmo = CONFIG_SYS_HZ_CLOCK / 1000;
- tmo *= usec;
- tmo /= (1000 * TIM_CLK_DIV);
-
- endtime = get_timer_raw() + tmo;
-
- do {
- ulong now = get_timer_raw();
- diff = endtime - now;
- } while (diff >= 0);
-}
-
-ulong get_tbclk(void)
-{
- return CONFIG_SYS_HZ;
-}
obj-y += cpu.o
obj-$(CONFIG_USE_IRQ) += interrupts.o
-obj-$(if $(filter a320,$(SOC)),y) += a320/
obj-$(CONFIG_EP93XX) += ep93xx/
obj-$(CONFIG_IMX) += imx/
-obj-$(CONFIG_KS8695) += ks8695/
obj-$(CONFIG_S3C24X0) += s3c24x0/
+++ /dev/null
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += reset.o
-obj-y += timer.o
+++ /dev/null
-/*
- * (C) Copyright 2009 Faraday Technology
- * Po-Yu Chuang <ratbert@faraday-tech.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-.global reset_cpu
-reset_cpu:
- b reset_cpu
+++ /dev/null
-/*
- * (C) Copyright 2009 Faraday Technology
- * Po-Yu Chuang <ratbert@faraday-tech.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <div64.h>
-#include <asm/io.h>
-#include <faraday/ftpmu010.h>
-#include <faraday/fttmr010.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define TIMER_CLOCK 32768
-#define TIMER_LOAD_VAL 0xffffffff
-
-static inline unsigned long long tick_to_time(unsigned long long tick)
-{
- tick *= CONFIG_SYS_HZ;
- do_div(tick, gd->arch.timer_rate_hz);
-
- return tick;
-}
-
-static inline unsigned long long usec_to_tick(unsigned long long usec)
-{
- usec *= gd->arch.timer_rate_hz;
- do_div(usec, 1000000);
-
- return usec;
-}
-
-int timer_init(void)
-{
- struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
- unsigned int cr;
-
- debug("%s()\n", __func__);
-
- /* disable timers */
- writel(0, &tmr->cr);
-
- /* use 32768Hz oscillator for RTC, WDT, TIMER */
- ftpmu010_32768osc_enable();
-
- /* setup timer */
- writel(TIMER_LOAD_VAL, &tmr->timer3_load);
- writel(TIMER_LOAD_VAL, &tmr->timer3_counter);
- writel(0, &tmr->timer3_match1);
- writel(0, &tmr->timer3_match2);
-
- /* we don't want timer to issue interrupts */
- writel(FTTMR010_TM3_MATCH1 |
- FTTMR010_TM3_MATCH2 |
- FTTMR010_TM3_OVERFLOW,
- &tmr->interrupt_mask);
-
- cr = readl(&tmr->cr);
- cr |= FTTMR010_TM3_CLOCK; /* use external clock */
- cr |= FTTMR010_TM3_ENABLE;
- writel(cr, &tmr->cr);
-
- gd->arch.timer_rate_hz = TIMER_CLOCK;
- gd->arch.tbu = gd->arch.tbl = 0;
-
- return 0;
-}
-
-/*
- * Get the current 64 bit timer tick count
- */
-unsigned long long get_ticks(void)
-{
- struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
- ulong now = TIMER_LOAD_VAL - readl(&tmr->timer3_counter);
-
- /* increment tbu if tbl has rolled over */
- if (now < gd->arch.tbl)
- gd->arch.tbu++;
- gd->arch.tbl = now;
- return (((unsigned long long)gd->arch.tbu) << 32) | gd->arch.tbl;
-}
-
-void __udelay(unsigned long usec)
-{
- unsigned long long start;
- ulong tmo;
-
- start = get_ticks(); /* get current timestamp */
- tmo = usec_to_tick(usec); /* convert usecs to ticks */
- while ((get_ticks() - start) < tmo)
- ; /* loop till time has passed */
-}
-
-/*
- * get_timer(base) can be used to check for timeouts or
- * to measure elasped time relative to an event:
- *
- * ulong start_time = get_timer(0) sets start_time to the current
- * time value.
- * get_timer(start_time) returns the time elapsed since then.
- *
- * The time is used in CONFIG_SYS_HZ units!
- */
-ulong get_timer(ulong base)
-{
- return tick_to_time(get_ticks()) - base;
-}
-
-/*
- * Return the number of timer ticks per second.
- */
-ulong get_tbclk(void)
-{
- return gd->arch.timer_rate_hz;
-}
+++ /dev/null
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = lowlevel_init.o
-obj-y += timer.o
+++ /dev/null
-/*
- * lowlevel_init.S - basic hardware initialization for the KS8695 CPU
- *
- * Copyright (c) 2004-2005, Greg Ungerer <greg.ungerer@opengear.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/platform.h>
-
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
-
-/*
- *************************************************************************
- *
- * Handy dandy macros
- *
- *************************************************************************
- */
-
-/* Delay a bit */
-.macro DELAY_FOR cycles, reg0
- ldr \reg0, =\cycles
- subs \reg0, \reg0, #1
- subne pc, pc, #0xc
-.endm
-
-/*
- *************************************************************************
- *
- * Some local storage.
- *
- *************************************************************************
- */
-
-/* Should we boot with an interactive console or not */
-.globl serial_console
-
-/*
- *************************************************************************
- *
- * Raw hardware initialization code. The important thing is to get
- * SDRAM setup and running. We do some other basic things here too,
- * like getting the PLL set for high speed, and init the LEDs.
- *
- *************************************************************************
- */
-
-.globl lowlevel_init
-lowlevel_init:
-
-#if DEBUG
- /*
- * enable UART for early debug trace
- */
- ldr r1, =(KS8695_IO_BASE+KS8695_UART_DIVISOR)
- mov r2, #((25000000+CONFIG_BAUDRATE/2) / CONFIG_BAUDRATE)
- str r2, [r1]
- ldr r1, =(KS8695_IO_BASE+KS8695_UART_LINE_CTRL)
- mov r2, #KS8695_UART_LINEC_WLEN8
- str r2, [r1] /* 8 data bits, no parity, 1 stop */
- ldr r1, =(KS8695_IO_BASE+KS8695_UART_TX_HOLDING)
- mov r2, #0x41
- str r2, [r1] /* write 'A' */
-#endif
-#if DEBUG
- ldr r1, =(KS8695_IO_BASE+KS8695_UART_TX_HOLDING)
- mov r2, #0x42
- str r2, [r1]
-#endif
-
- /*
- * remap the memory and flash regions. we want to end up with
- * ram from address 0, and flash at 32MB.
- */
- ldr r1, =(KS8695_IO_BASE+KS8695_MEM_CTRL0)
- ldr r2, =0xbfc00040
- str r2, [r1] /* large flash map */
- ldr pc, =(highflash+0x02000000-0x00f00000) /* jump to high flash address */
-highflash:
- ldr r2, =0x8fe00040
- str r2, [r1] /* remap flash range */
-
- /*
- * remap the second select region to the 4MB immediately after
- * the first region. This way if you have a larger flash (say 8Mb)
- * then you can have it all mapped nicely. Has no effect if you
- * only have a 4Mb or smaller flash.
- */
- ldr r1, =(KS8695_IO_BASE+KS8695_MEM_CTRL1)
- ldr r2, =0x9fe40040
- str r2, [r1] /* remap flash2 region, contiguous */
- ldr r1, =(KS8695_IO_BASE+KS8695_MEM_GENERAL)
- ldr r2, =0x30000005
- str r2, [r1] /* enable both flash selects */
-
-#ifdef CONFIG_CM41xx
- /*
- * map the second flash chip, using the external IO lines.
- */
- ldr r1, =(KS8695_IO_BASE+KS8695_IO_CTRL0)
- ldr r2, =0xafe80b6d
- str r2, [r1] /* remap io0 region, contiguous */
- ldr r1, =(KS8695_IO_BASE+KS8695_IO_CTRL1)
- ldr r2, =0xbfec0b6d
- str r2, [r1] /* remap io1 region, contiguous */
- ldr r1, =(KS8695_IO_BASE+KS8695_MEM_GENERAL)
- ldr r2, =0x30050005
- str r2, [r1] /* enable second flash */
-#endif
-
- /*
- * before relocating, we have to setup RAM timing
- */
- ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_CTRL0)
-#if (PHYS_SDRAM_1_SIZE == 0x02000000)
- ldr r2, =0x7fc0000e /* 32MB */
-#else
- ldr r2, =0x3fc0000e /* 16MB */
-#endif
- str r2, [r1] /* configure sdram bank0 setup */
- ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_CTRL1)
- mov r2, #0
- str r2, [r1] /* configure sdram bank1 setup */
-
- ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_GENERAL)
- ldr r2, =0x0000000a
- str r2, [r1] /* set RAS/CAS timing */
-
- ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_BUFFER)
- ldr r2, =0x00030000
- str r2, [r1] /* send NOP command */
- DELAY_FOR 0x100, r0
- ldr r2, =0x00010000
- str r2, [r1] /* send PRECHARGE-ALL */
- DELAY_FOR 0x100, r0
-
- ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_REFRESH)
- ldr r2, =0x00000020
- str r2, [r1] /* set for fast refresh */
- DELAY_FOR 0x100, r0
- ldr r2, =0x00000190
- str r2, [r1] /* set normal refresh timing */
-
- ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_BUFFER)
- ldr r2, =0x00020033
- str r2, [r1] /* send mode command */
- DELAY_FOR 0x100, r0
- ldr r2, =0x01f00000
- str r2, [r1] /* enable sdram fifos */
-
- /*
- * set pll to top speed
- */
- ldr r1, =(KS8695_IO_BASE+KS8695_SYSTEN_BUS_CLOCK)
- mov r2, #0
- str r2, [r1] /* set pll clock to 166MHz */
-
- ldr r1, =(KS8695_IO_BASE+KS8695_SWITCH_CTRL0)
- ldr r2, [r1] /* Get switch ctrl0 register */
- and r2, r2, #0x0fc00000 /* Mask out LED control bits */
- orr r2, r2, #0x01800000 /* Set Link/activity/speed actions */
- str r2, [r1]
-
-#ifdef CONFIG_CM4008
- ldr r1, =(KS8695_IO_BASE+KS8695_GPIO_MODE)
- ldr r2, =0x0000fe30
- str r2, [r1] /* enable LED's as outputs */
- ldr r1, =(KS8695_IO_BASE+KS8695_GPIO_DATA)
- ldr r2, =0x0000fe20
- str r2, [r1] /* turn on power LED */
-#endif
-#if defined(CONFIG_CM4008) || defined(CONFIG_CM41xx)
- ldr r2, [r1] /* get current GPIO input data */
- tst r2, #0x8 /* check if "erase" depressed */
- beq nobutton
- mov r2, #0 /* be quiet on boot, no console */
- ldr r1, =serial_console
- str r2, [r1]
-nobutton:
-#endif
-
- add lr, lr, #0x02000000 /* flash is now mapped high */
- add ip, ip, #0x02000000 /* this is a hack */
- mov pc, lr /* all done, return */
-
-#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
+++ /dev/null
-/*
- * (C) Copyright 2004-2005, Greg Ungerer <greg.ungerer@opengear.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/platform.h>
-
-/*
- * Initial timer set constants. Nothing complicated, just set for a 1ms
- * tick.
- */
-#define TIMER_INTERVAL (TICKS_PER_uSEC * mSEC_1)
-#define TIMER_COUNT (TIMER_INTERVAL / 2)
-#define TIMER_PULSE TIMER_COUNT
-
-/*
- * Handy KS8695 register access functions.
- */
-#define ks8695_read(a) *((volatile ulong *) (KS8695_IO_BASE + (a)))
-#define ks8695_write(a,v) *((volatile ulong *) (KS8695_IO_BASE + (a))) = (v)
-
-ulong timer_ticks;
-
-int timer_init (void)
-{
- /* Set the hadware timer for 1ms */
- ks8695_write(KS8695_TIMER1, TIMER_COUNT);
- ks8695_write(KS8695_TIMER1_PCOUNT, TIMER_PULSE);
- ks8695_write(KS8695_TIMER_CTRL, 0x2);
- timer_ticks = 0;
-
- return 0;
-}
-
-ulong get_timer_masked(void)
-{
- /* Check for timer wrap */
- if (ks8695_read(KS8695_INT_STATUS) & KS8695_INTMASK_TIMERINT1) {
- /* Clear interrupt condition */
- ks8695_write(KS8695_INT_STATUS, KS8695_INTMASK_TIMERINT1);
- timer_ticks++;
- }
- return timer_ticks;
-}
-
-ulong get_timer(ulong base)
-{
- return (get_timer_masked() - base);
-}
-
-void __udelay(ulong usec)
-{
- ulong start = get_timer_masked();
- ulong end;
-
- /* Only 1ms resolution :-( */
- end = usec / 1000;
- while (get_timer(start) < end)
- ;
-}
-
-void reset_cpu (ulong ignored)
-{
- ulong tc;
-
- /* Set timer0 to watchdog, and let it timeout */
- tc = ks8695_read(KS8695_TIMER_CTRL) & 0x2;
- ks8695_write(KS8695_TIMER_CTRL, tc);
- ks8695_write(KS8695_TIMER0, ((10 << 8) | 0xff));
- ks8695_write(KS8695_TIMER_CTRL, (tc | 0x1));
-
- /* Should only wait here till watchdog resets */
- for (;;)
- ;
-}
obj-$(CONFIG_ARMADA100) += armada100/
obj-$(if $(filter lpc32xx,$(SOC)),y) += lpc32xx/
-obj-$(CONFIG_MB86R0x) += mb86r0x/
obj-$(CONFIG_MX25) += mx25/
obj-$(CONFIG_MX27) += mx27/
obj-$(if $(filter mxs,$(SOC)),y) += mxs/
-obj-$(CONFIG_PANTHEON) += pantheon/
obj-$(if $(filter spear,$(SOC)),y) += spear/
+++ /dev/null
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = clock.o reset.o timer.o
+++ /dev/null
-/*
- * (C) Copyright 2010
- * Matthias Weisser <weisserm@arcor.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-
-/*
- * Get the peripheral bus frequency depending on pll pin settings
- */
-ulong get_bus_freq(ulong dummy)
-{
- struct mb86r0x_crg * crg = (struct mb86r0x_crg *)
- MB86R0x_CRG_BASE;
- uint32_t pllmode;
-
- pllmode = readl(&crg->crpr) & MB86R0x_CRG_CRPR_PLLMODE;
-
- if (pllmode == MB86R0x_CRG_CRPR_PLLMODE_X20)
- return 40000000;
-
- return 41164767;
-}
+++ /dev/null
-/*
- * (C) Copyright 2010
- * Matthias Weisser <weisserm@arcor.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-
-/*
- * Reset the cpu by setting software reset request bit
- */
-void reset_cpu(ulong ignored)
-{
- struct mb86r0x_crg * crg = (struct mb86r0x_crg *)
- MB86R0x_CRG_BASE;
-
- writel(MB86R0x_CRSR_SWRSTREQ, &crg->crsr);
- while (1)
- /* NOP */;
- /* Never reached */
-}
+++ /dev/null
-/*
- * (C) Copyright 2007-2008
- * Stelian Pop <stelian@popies.net>
- * Lead Tech Design <www.leadtechdesign.com>
- *
- * (C) Copyright 2010
- * Matthias Weisser, Graf-Syteco <weisserm@arcor.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <div64.h>
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-
-#define TIMER_LOAD_VAL 0xffffffff
-#define TIMER_FREQ (CONFIG_MB86R0x_IOCLK / 256)
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define timestamp gd->arch.tbl
-#define lastdec gd->arch.lastinc
-
-static inline unsigned long long tick_to_time(unsigned long long tick)
-{
- tick *= CONFIG_SYS_HZ;
- do_div(tick, TIMER_FREQ);
-
- return tick;
-}
-
-static inline unsigned long long usec_to_tick(unsigned long long usec)
-{
- usec *= TIMER_FREQ;
- do_div(usec, 1000000);
-
- return usec;
-}
-
-/* nothing really to do with interrupts, just starts up a counter. */
-int timer_init(void)
-{
- struct mb86r0x_timer * timer = (struct mb86r0x_timer *)
- MB86R0x_TIMER_BASE;
- ulong ctrl = readl(&timer->control);
-
- writel(TIMER_LOAD_VAL, &timer->load);
-
- ctrl |= MB86R0x_TIMER_ENABLE | MB86R0x_TIMER_PRS_8S |
- MB86R0x_TIMER_SIZE_32;
-
- writel(ctrl, &timer->control);
-
- /* capture current value time */
- lastdec = readl(&timer->value);
- timestamp = 0; /* start "advancing" time stamp from 0 */
-
- return 0;
-}
-
-/*
- * timer without interrupts
- */
-unsigned long long get_ticks(void)
-{
- struct mb86r0x_timer * timer = (struct mb86r0x_timer *)
- MB86R0x_TIMER_BASE;
- ulong now = readl(&timer->value);
-
- if (now <= lastdec) {
- /* normal mode (non roll) */
- /* move stamp forward with absolut diff ticks */
- timestamp += lastdec - now;
- } else {
- /* we have rollover of incrementer */
- timestamp += lastdec + TIMER_LOAD_VAL - now;
- }
- lastdec = now;
- return timestamp;
-}
-
-ulong get_timer_masked(void)
-{
- return tick_to_time(get_ticks());
-}
-
-void __udelay(unsigned long usec)
-{
- unsigned long long tmp;
- ulong tmo;
-
- tmo = usec_to_tick(usec);
- tmp = get_ticks(); /* get current timestamp */
-
- while ((get_ticks() - tmp) < tmo) /* loop till event */
- /*NOP*/;
-}
-
-ulong get_timer(ulong base)
-{
- return get_timer_masked() - base;
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk(void)
-{
- ulong tbclk;
-
- tbclk = TIMER_FREQ;
- return tbclk;
-}
+++ /dev/null
-#
-# (C) Copyright 2011
-# Marvell Semiconductor <www.marvell.com>
-# Written-by: Lei Wen <leiwen@marvell.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = cpu.o timer.o dram.o
+++ /dev/null
-/*
- * (C) Copyright 2011
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Lei Wen <leiwen@marvell.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/pantheon.h>
-
-#define UARTCLK14745KHZ (APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(1))
-#define SET_MRVL_ID (1<<8)
-#define L2C_RAM_SEL (1<<4)
-
-int arch_cpu_init(void)
-{
- u32 val;
- struct panthcpu_registers *cpuregs =
- (struct panthcpu_registers*) PANTHEON_CPU_BASE;
-
- struct panthapb_registers *apbclkres =
- (struct panthapb_registers*) PANTHEON_APBC_BASE;
-
- struct panthmpmu_registers *mpmu =
- (struct panthmpmu_registers*) PANTHEON_MPMU_BASE;
-
- struct panthapmu_registers *apmu =
- (struct panthapmu_registers *) PANTHEON_APMU_BASE;
-
- /* set SEL_MRVL_ID bit in PANTHEON_CPU_CONF register */
- val = readl(&cpuregs->cpu_conf);
- val = val | SET_MRVL_ID;
- writel(val, &cpuregs->cpu_conf);
-
- /* Turn on clock gating (PMUM_CCGR) */
- writel(0xFFFFFFFF, &mpmu->ccgr);
-
- /* Turn on clock gating (PMUM_ACGR) */
- writel(0xFFFFFFFF, &mpmu->acgr);
-
- /* Turn on uart2 clock */
- writel(UARTCLK14745KHZ, &apbclkres->uart0);
-
- /* Enable GPIO clock */
- writel(APBC_APBCLK, &apbclkres->gpio);
-
-#ifdef CONFIG_I2C_MV
- /* Enable I2C clock */
- writel(APBC_RST | APBC_FNCLK | APBC_APBCLK, &apbclkres->twsi);
- writel(APBC_FNCLK | APBC_APBCLK, &apbclkres->twsi);
-#endif
-
-#ifdef CONFIG_MV_SDHCI
- /* Enable mmc clock */
- writel(APMU_PERI_CLK | APMU_AXI_CLK | APMU_PERI_RST | APMU_AXI_RST,
- &apmu->sd1);
- writel(APMU_PERI_CLK | APMU_AXI_CLK | APMU_PERI_RST | APMU_AXI_RST,
- &apmu->sd3);
-#endif
-
- icache_enable();
-
- return 0;
-}
-
-#if defined(CONFIG_DISPLAY_CPUINFO)
-int print_cpuinfo(void)
-{
- u32 id;
- struct panthcpu_registers *cpuregs =
- (struct panthcpu_registers*) PANTHEON_CPU_BASE;
-
- id = readl(&cpuregs->chip_id);
- printf("SoC: PANTHEON 88AP%X-%X\n", (id & 0xFFF), (id >> 0x10));
- return 0;
-}
-#endif
-
-#ifdef CONFIG_I2C_MV
-void i2c_clk_enable(void)
-{
-}
-#endif
+++ /dev/null
-/*
- * (C) Copyright 2011
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Lei Wen <leiwen@marvell.com>,
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/pantheon.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * Pantheon DRAM controller supports upto 8 banks
- * for chip select 0 and 1
- */
-
-/*
- * DDR Memory Control Registers
- * Refer Datasheet 4.4
- */
-struct panthddr_map_registers {
- u32 cs; /* Memory Address Map Register -CS */
- u32 pad[3];
-};
-
-struct panthddr_registers {
- u8 pad[0x100 - 0x000];
- struct panthddr_map_registers mmap[2];
-};
-
-/*
- * panth_sdram_base - reads SDRAM Base Address Register
- */
-u32 panth_sdram_base(int chip_sel)
-{
- struct panthddr_registers *ddr_regs =
- (struct panthddr_registers *)PANTHEON_DRAM_BASE;
- u32 result = 0;
- u32 CS_valid = 0x01 & readl(&ddr_regs->mmap[chip_sel].cs);
-
- if (!CS_valid)
- return 0;
-
- result = readl(&ddr_regs->mmap[chip_sel].cs) & 0xFF800000;
- return result;
-}
-
-/*
- * panth_sdram_size - reads SDRAM size
- */
-u32 panth_sdram_size(int chip_sel)
-{
- struct panthddr_registers *ddr_regs =
- (struct panthddr_registers *)PANTHEON_DRAM_BASE;
- u32 result = 0;
- u32 CS_valid = 0x01 & readl(&ddr_regs->mmap[chip_sel].cs);
-
- if (!CS_valid)
- return 0;
-
- result = readl(&ddr_regs->mmap[chip_sel].cs);
- result = (result >> 16) & 0xF;
- if (result < 0x7) {
- printf("Unknown DRAM Size\n");
- return -1;
- } else {
- return ((0x8 << (result - 0x7)) * 1024 * 1024);
- }
-}
-
-#ifndef CONFIG_SYS_BOARD_DRAM_INIT
-int dram_init(void)
-{
- int i;
-
- gd->ram_size = 0;
- for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
- gd->bd->bi_dram[i].start = panth_sdram_base(i);
- gd->bd->bi_dram[i].size = panth_sdram_size(i);
- /*
- * It is assumed that all memory banks are consecutive
- * and without gaps.
- * If the gap is found, ram_size will be reported for
- * consecutive memory only
- */
- if (gd->bd->bi_dram[i].start != gd->ram_size)
- break;
-
- gd->ram_size += gd->bd->bi_dram[i].size;
-
- }
-
- for (; i < CONFIG_NR_DRAM_BANKS; i++) {
- /*
- * If above loop terminated prematurely, we need to set
- * remaining banks' start address & size as 0. Otherwise other
- * u-boot functions and Linux kernel gets wrong values which
- * could result in crash
- */
- gd->bd->bi_dram[i].start = 0;
- gd->bd->bi_dram[i].size = 0;
- }
- return 0;
-}
-
-/*
- * If this function is not defined here,
- * board.c alters dram bank zero configuration defined above.
- */
-void dram_init_banksize(void)
-{
- dram_init();
-}
-#endif /* CONFIG_SYS_BOARD_DRAM_INIT */
+++ /dev/null
-/*
- * (C) Copyright 2011
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Lei Wen <leiwen@marvell.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/pantheon.h>
-
-/*
- * Timer registers
- * Refer 6.2.9 in Datasheet
- */
-struct panthtmr_registers {
- u32 clk_ctrl; /* Timer clk control reg */
- u32 match[9]; /* Timer match registers */
- u32 count[3]; /* Timer count registers */
- u32 status[3];
- u32 ie[3];
- u32 preload[3]; /* Timer preload value */
- u32 preload_ctrl[3];
- u32 wdt_match_en;
- u32 wdt_match_r;
- u32 wdt_val;
- u32 wdt_sts;
- u32 icr[3];
- u32 wdt_icr;
- u32 cer; /* Timer count enable reg */
- u32 cmr;
- u32 ilr[3];
- u32 wcr;
- u32 wfar;
- u32 wsar;
- u32 cvwr[3];
-};
-
-#define TIMER 0 /* Use TIMER 0 */
-/* Each timer has 3 match registers */
-#define MATCH_CMP(x) ((3 * TIMER) + x)
-#define TIMER_LOAD_VAL 0xffffffff
-#define COUNT_RD_REQ 0x1
-
-DECLARE_GLOBAL_DATA_PTR;
-/* Using gd->arch.tbu from timestamp and gd->arch.tbl for lastdec */
-
-/*
- * For preventing risk of instability in reading counter value,
- * first set read request to register cvwr and then read same
- * register after it captures counter value.
- */
-ulong read_timer(void)
-{
- struct panthtmr_registers *panthtimers =
- (struct panthtmr_registers *) PANTHEON_TIMER_BASE;
- volatile int loop=100;
- ulong val;
-
- writel(COUNT_RD_REQ, &panthtimers->cvwr);
- while (loop--)
- val = readl(&panthtimers->cvwr);
-
- /*
- * This stop gcc complain and prevent loop mistake init to 0
- */
- val = readl(&panthtimers->cvwr);
-
- return val;
-}
-
-ulong get_timer_masked(void)
-{
- ulong now = read_timer();
-
- if (now >= gd->arch.tbl) {
- /* normal mode */
- gd->arch.tbu += now - gd->arch.tbl;
- } else {
- /* we have an overflow ... */
- gd->arch.tbu += now + TIMER_LOAD_VAL - gd->arch.tbl;
- }
- gd->arch.tbl = now;
-
- return gd->arch.tbu;
-}
-
-ulong get_timer(ulong base)
-{
- return ((get_timer_masked() / (CONFIG_SYS_HZ_CLOCK / 1000)) -
- base);
-}
-
-void __udelay(unsigned long usec)
-{
- ulong delayticks;
- ulong endtime;
-
- delayticks = (usec * (CONFIG_SYS_HZ_CLOCK / 1000000));
- endtime = get_timer_masked() + delayticks;
-
- while (get_timer_masked() < endtime)
- ;
-}
-
-/*
- * init the Timer
- */
-int timer_init(void)
-{
- struct panthapb_registers *apb1clkres =
- (struct panthapb_registers *) PANTHEON_APBC_BASE;
- struct panthtmr_registers *panthtimers =
- (struct panthtmr_registers *) PANTHEON_TIMER_BASE;
-
- /* Enable Timer clock at 3.25 MHZ */
- writel(APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3), &apb1clkres->timers);
-
- /* load value into timer */
- writel(0x0, &panthtimers->clk_ctrl);
- /* Use Timer 0 Match Resiger 0 */
- writel(TIMER_LOAD_VAL, &panthtimers->match[MATCH_CMP(0)]);
- /* Preload value is 0 */
- writel(0x0, &panthtimers->preload[TIMER]);
- /* Enable match comparator 0 for Timer 0 */
- writel(0x1, &panthtimers->preload_ctrl[TIMER]);
-
- /* Enable timer 0 */
- writel(0x1, &panthtimers->cer);
- /* init the gd->arch.tbu and gd->arch.tbl value */
- gd->arch.tbl = read_timer();
- gd->arch.tbu = 0;
-
- return 0;
-}
-
-#define MPMU_APRR_WDTR (1<<4)
-#define TMR_WFAR 0xbaba /* WDT Register First key */
-#define TMP_WSAR 0xeb10 /* WDT Register Second key */
-
-/*
- * This function uses internal Watchdog Timer
- * based reset mechanism.
- * Steps to write watchdog registers (protected access)
- * 1. Write key value to TMR_WFAR reg.
- * 2. Write key value to TMP_WSAR reg.
- * 3. Perform write operation.
- */
-void reset_cpu (unsigned long ignored)
-{
- struct panthmpmu_registers *mpmu =
- (struct panthmpmu_registers *) PANTHEON_MPMU_BASE;
- struct panthtmr_registers *panthtimers =
- (struct panthtmr_registers *) PANTHEON_WD_TIMER_BASE;
- u32 val;
-
- /* negate hardware reset to the WDT after system reset */
- val = readl(&mpmu->aprr);
- val = val | MPMU_APRR_WDTR;
- writel(val, &mpmu->aprr);
-
- /* reset/enable WDT clock */
- writel(APBC_APBCLK, &mpmu->wdtpcr);
-
- /* clear previous WDT status */
- writel(TMR_WFAR, &panthtimers->wfar);
- writel(TMP_WSAR, &panthtimers->wsar);
- writel(0, &panthtimers->wdt_sts);
-
- /* set match counter */
- writel(TMR_WFAR, &panthtimers->wfar);
- writel(TMP_WSAR, &panthtimers->wsar);
- writel(0xf, &panthtimers->wdt_match_r);
-
- /* enable WDT reset */
- writel(TMR_WFAR, &panthtimers->wfar);
- writel(TMP_WSAR, &panthtimers->wsar);
- writel(0x3, &panthtimers->wdt_match_en);
-
- /*enable functional WDT clock */
- writel(APBC_APBCLK | APBC_FNCLK, &mpmu->wdtpcr);
-}
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On ARM it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
- return get_timer(0);
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk (void)
-{
- return (ulong)CONFIG_SYS_HZ;
-}
config TARGET_SMDKV310
select SUPPORT_SPL
bool "Exynos4210 SMDKV310 board"
- select OF_CONTROL if !SPL_BUILD
+ select OF_CONTROL
config TARGET_TRATS
bool "Exynos4210 Trats board"
select CPU_V7_HAS_NONSEC
select CPU_V7_HAS_VIRT
select SUPPORT_SPL
- select OF_CONTROL if !SPL_BUILD
+ select OF_CONTROL
config TARGET_SMDK5250
bool "SMDK5250 board"
select SUPPORT_SPL
- select OF_CONTROL if !SPL_BUILD
+ select OF_CONTROL
config TARGET_SNOW
bool "Snow board"
select SUPPORT_SPL
- select OF_CONTROL if !SPL_BUILD
+ select OF_CONTROL
config TARGET_SMDK5420
bool "SMDK5420 board"
select SUPPORT_SPL
- select OF_CONTROL if !SPL_BUILD
+ select OF_CONTROL
config TARGET_PEACH_PI
bool "Peach Pi board"
select SUPPORT_SPL
- select OF_CONTROL if !SPL_BUILD
+ select OF_CONTROL
config TARGET_PEACH_PIT
bool "Peach Pit board"
select SUPPORT_SPL
- select OF_CONTROL if !SPL_BUILD
+ select OF_CONTROL
endchoice
default "exynos"
config DM
- default y if !SPL_BUILD
+ default y
config DM_SERIAL
- default y if !SPL_BUILD
+ default y
config DM_SPI
- default y if !SPL_BUILD
+ default y
config DM_SPI_FLASH
- default y if !SPL_BUILD
+ default y
config DM_GPIO
- default y if !SPL_BUILD
+ default y
config SYS_MALLOC_F
- default y if !SPL_BUILD
+ default y
config SYS_MALLOC_F_LEN
- default 0x400 if !SPL_BUILD
+ default 0x400
source "board/samsung/smdkv310/Kconfig"
source "board/samsung/trats/Kconfig"
#include <asm/arch/clock.h>
#include <asm/io.h>
#include <asm/arch/immap_ls102xa.h>
+#include <asm/cache.h>
+#include <asm/system.h>
#include <tsec.h>
#include <netdev.h>
#include <fsl_esdhc.h>
#include "fsl_epu.h"
+#define DCSR_RCPM2_BLOCK_OFFSET 0x223000
+#define DCSR_RCPM2_CPMFSMCR0 0x400
+#define DCSR_RCPM2_CPMFSMSR0 0x404
+#define DCSR_RCPM2_CPMFSMCR1 0x414
+#define DCSR_RCPM2_CPMFSMSR1 0x418
+#define CPMFSMSR_FSM_STATE_MASK 0x7f
+
DECLARE_GLOBAL_DATA_PTR;
+#ifndef CONFIG_SYS_DCACHE_OFF
+
+/*
+ * Bit[1] of the descriptor indicates the descriptor type,
+ * and bit[0] indicates whether the descriptor is valid.
+ */
+#define PMD_TYPE_TABLE 0x3
+#define PMD_TYPE_SECT 0x1
+
+/* AttrIndx[2:0] */
+#define PMD_ATTRINDX(t) ((t) << 2)
+
+/* Section */
+#define PMD_SECT_AF (1 << 10)
+
+#define BLOCK_SIZE_L1 (1UL << 30)
+#define BLOCK_SIZE_L2 (1UL << 21)
+
+/* TTBCR flags */
+#define TTBCR_EAE (1 << 31)
+#define TTBCR_T0SZ(x) ((x) << 0)
+#define TTBCR_T1SZ(x) ((x) << 16)
+#define TTBCR_USING_TTBR0 (TTBCR_T0SZ(0) | TTBCR_T1SZ(0))
+#define TTBCR_IRGN0_NC (0 << 8)
+#define TTBCR_IRGN0_WBWA (1 << 8)
+#define TTBCR_IRGN0_WT (2 << 8)
+#define TTBCR_IRGN0_WBNWA (3 << 8)
+#define TTBCR_IRGN0_MASK (3 << 8)
+#define TTBCR_ORGN0_NC (0 << 10)
+#define TTBCR_ORGN0_WBWA (1 << 10)
+#define TTBCR_ORGN0_WT (2 << 10)
+#define TTBCR_ORGN0_WBNWA (3 << 10)
+#define TTBCR_ORGN0_MASK (3 << 10)
+#define TTBCR_SHARED_NON (0 << 12)
+#define TTBCR_SHARED_OUTER (2 << 12)
+#define TTBCR_SHARED_INNER (3 << 12)
+#define TTBCR_EPD0 (0 << 7)
+#define TTBCR (TTBCR_SHARED_NON | \
+ TTBCR_ORGN0_NC | \
+ TTBCR_IRGN0_NC | \
+ TTBCR_USING_TTBR0 | \
+ TTBCR_EAE)
+
+/*
+ * Memory region attributes for LPAE (defined in pgtable):
+ *
+ * n = AttrIndx[2:0]
+ *
+ * n MAIR
+ * UNCACHED 000 00000000
+ * BUFFERABLE 001 01000100
+ * DEV_WC 001 01000100
+ * WRITETHROUGH 010 10101010
+ * WRITEBACK 011 11101110
+ * DEV_CACHED 011 11101110
+ * DEV_SHARED 100 00000100
+ * DEV_NONSHARED 100 00000100
+ * unused 101
+ * unused 110
+ * WRITEALLOC 111 11111111
+ */
+#define MT_MAIR0 0xeeaa4400
+#define MT_MAIR1 0xff000004
+#define MT_STRONLY_ORDER 0
+#define MT_NORMAL_NC 1
+#define MT_DEVICE_MEM 4
+#define MT_NORMAL 7
+
+/* The phy_addr must be aligned to 4KB */
+static inline void set_pgtable(u32 *page_table, u32 index, u32 phy_addr)
+{
+ u32 value = phy_addr | PMD_TYPE_TABLE;
+
+ page_table[2 * index] = value;
+ page_table[2 * index + 1] = 0;
+}
+
+/* The phy_addr must be aligned to 4KB */
+static inline void set_pgsection(u32 *page_table, u32 index, u64 phy_addr,
+ u32 memory_type)
+{
+ u64 value;
+
+ value = phy_addr | PMD_TYPE_SECT | PMD_SECT_AF;
+ value |= PMD_ATTRINDX(memory_type);
+ page_table[2 * index] = value & 0xFFFFFFFF;
+ page_table[2 * index + 1] = (value >> 32) & 0xFFFFFFFF;
+}
+
+/*
+ * Start MMU after DDR is available, we create MMU table in DRAM.
+ * The base address of TTLB is gd->arch.tlb_addr. We use two
+ * levels of translation tables here to cover 40-bit address space.
+ *
+ * The TTLBs are located at PHY 2G~4G.
+ *
+ * VA mapping:
+ *
+ * ------- <---- 0GB
+ * | |
+ * | |
+ * |-------| <---- 0x24000000
+ * |///////| ===> 192MB VA map for PCIe1 with offset 0x40_0000_0000
+ * |-------| <---- 0x300000000
+ * | |
+ * |-------| <---- 0x34000000
+ * |///////| ===> 192MB VA map for PCIe2 with offset 0x48_0000_0000
+ * |-------| <---- 0x40000000
+ * | |
+ * |-------| <---- 0x80000000 DDR0 space start
+ * |\\\\\\\|
+ *.|\\\\\\\| ===> 2GB VA map for 2GB DDR0 Memory space
+ * |\\\\\\\|
+ * ------- <---- 4GB DDR0 space end
+ */
+static void mmu_setup(void)
+{
+ u32 *level0_table = (u32 *)gd->arch.tlb_addr;
+ u32 *level1_table = (u32 *)(gd->arch.tlb_addr + 0x1000);
+ u64 va_start = 0;
+ u32 reg;
+ int i;
+
+ /* Level 0 Table 2-3 are used to map DDR */
+ set_pgsection(level0_table, 3, 3 * BLOCK_SIZE_L1, MT_NORMAL);
+ set_pgsection(level0_table, 2, 2 * BLOCK_SIZE_L1, MT_NORMAL);
+ /* Level 0 Table 1 is used to map device */
+ set_pgsection(level0_table, 1, 1 * BLOCK_SIZE_L1, MT_DEVICE_MEM);
+ /* Level 0 Table 0 is used to map device including PCIe MEM */
+ set_pgtable(level0_table, 0, (u32)level1_table);
+
+ /* Level 1 has 512 entries */
+ for (i = 0; i < 512; i++) {
+ /* Mapping for PCIe 1 */
+ if (va_start >= CONFIG_SYS_PCIE1_VIRT_ADDR &&
+ va_start < (CONFIG_SYS_PCIE1_VIRT_ADDR +
+ CONFIG_SYS_PCIE_MMAP_SIZE))
+ set_pgsection(level1_table, i,
+ CONFIG_SYS_PCIE1_PHYS_BASE + va_start,
+ MT_DEVICE_MEM);
+ /* Mapping for PCIe 2 */
+ else if (va_start >= CONFIG_SYS_PCIE2_VIRT_ADDR &&
+ va_start < (CONFIG_SYS_PCIE2_VIRT_ADDR +
+ CONFIG_SYS_PCIE_MMAP_SIZE))
+ set_pgsection(level1_table, i,
+ CONFIG_SYS_PCIE2_PHYS_BASE + va_start,
+ MT_DEVICE_MEM);
+ else
+ set_pgsection(level1_table, i,
+ va_start,
+ MT_DEVICE_MEM);
+ va_start += BLOCK_SIZE_L2;
+ }
+
+ asm volatile("dsb sy;isb");
+ asm volatile("mcr p15, 0, %0, c2, c0, 2" /* Write RT to TTBCR */
+ : : "r" (TTBCR) : "memory");
+ asm volatile("mcrr p15, 0, %0, %1, c2" /* TTBR 0 */
+ : : "r" ((u32)level0_table), "r" (0) : "memory");
+ asm volatile("mcr p15, 0, %0, c10, c2, 0" /* write MAIR 0 */
+ : : "r" (MT_MAIR0) : "memory");
+ asm volatile("mcr p15, 0, %0, c10, c2, 1" /* write MAIR 1 */
+ : : "r" (MT_MAIR1) : "memory");
+
+ /* Set the access control to all-supervisor */
+ asm volatile("mcr p15, 0, %0, c3, c0, 0"
+ : : "r" (~0));
+
+ /* Enable the mmu */
+ reg = get_cr();
+ set_cr(reg | CR_M);
+}
+
+/*
+ * This function is called from lib/board.c. It recreates MMU
+ * table in main memory. MMU and i/d-cache are enabled here.
+ */
+void enable_caches(void)
+{
+ /* Invalidate all TLB */
+ mmu_page_table_flush(gd->arch.tlb_addr,
+ gd->arch.tlb_addr + gd->arch.tlb_size);
+ /* Set up and enable mmu */
+ mmu_setup();
+
+ /* Invalidate & Enable d-cache */
+ invalidate_dcache_all();
+ set_cr(get_cr() | CR_C);
+}
+#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
+
#if defined(CONFIG_DISPLAY_CPUINFO)
int print_cpuinfo(void)
{
}
#endif
-void enable_caches(void)
-{
-#ifndef CONFIG_SYS_ICACHE_OFF
- icache_enable();
-#endif
-#ifndef CONFIG_SYS_DCACHE_OFF
- dcache_enable();
-#endif
-}
-
#ifdef CONFIG_FSL_ESDHC
int cpu_mmc_init(bd_t *bis)
{
int arch_cpu_init(void)
{
void *epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
+ void *rcpm2_base =
+ (void *)(CONFIG_SYS_DCSRBAR + DCSR_RCPM2_BLOCK_OFFSET);
+ u32 state;
+
+ /*
+ * The RCPM FSM state may not be reset after power-on.
+ * So, reset them.
+ */
+ state = in_be32(rcpm2_base + DCSR_RCPM2_CPMFSMSR0) &
+ CPMFSMSR_FSM_STATE_MASK;
+ if (state != 0) {
+ out_be32(rcpm2_base + DCSR_RCPM2_CPMFSMCR0, 0x80);
+ out_be32(rcpm2_base + DCSR_RCPM2_CPMFSMCR0, 0x0);
+ }
+
+ state = in_be32(rcpm2_base + DCSR_RCPM2_CPMFSMSR1) &
+ CPMFSMSR_FSM_STATE_MASK;
+ if (state != 0) {
+ out_be32(rcpm2_base + DCSR_RCPM2_CPMFSMCR1, 0x80);
+ out_be32(rcpm2_base + DCSR_RCPM2_CPMFSMCR1, 0x0);
+ }
/*
* After wakeup from deep sleep, Clear EPU registers
endchoice
config DM
- default y if !SPL_BUILD
+ default y
config DM_GPIO
- default y if DM && !SPL_BUILD
+ default y if DM
config DM_SERIAL
- default y if DM && !SPL_BUILD
+ default y if DM
config SYS_MALLOC_F
- default y if DM && !SPL_BUILD
+ default y if DM
config SYS_MALLOC_F_LEN
- default 0x400 if DM && !SPL_BUILD
+ default 0x400 if DM
config SYS_SOC
default "omap3"
config TARGET_S5P_GONI
bool "S5P Goni board"
- select OF_CONTROL if !SPL_BUILD
+ select OF_CONTROL
config TARGET_SMDKC100
bool "Support smdkc100 board"
- select OF_CONTROL if !SPL_BUILD
+ select OF_CONTROL
endchoice
default y
config SYS_MALLOC_F_LEN
- default 0x2000
+ default 0x400
config CMD_PINMON
bool "Enable boot mode pins monitor command"
config CMD_DDRPHY_DUMP
bool "Enable dump command of DDR PHY parameters"
- depends on !SPL_BUILD
help
The command "ddrphy" shows the resulting parameters of DDR PHY
training; it is useful for the evaluation of DDR PHY training.
choice
prompt "DDR3 Frequency select"
- depends on SPL_BUILD
config DDR_FREQ_1600
bool "DDR3 1600"
isb sy
ret
ENDPROC(__asm_invalidate_icache_all)
+
+ENTRY(__asm_flush_l3_cache)
+ mov x0, #0 /* return status as success */
+ ret
+ENDPROC(__asm_flush_l3_cache)
+ .weak __asm_flush_l3_cache
__asm_invalidate_dcache_all();
}
-void __weak flush_l3_cache(void)
-{
-}
-
/*
- * Performs a clean & invalidation of the entire data cache at all levels
+ * Performs a clean & invalidation of the entire data cache at all levels.
+ * This function needs to be inline to avoid using stack.
+ * __asm_flush_l3_cache return status of timeout
*/
-void flush_dcache_all(void)
+inline void flush_dcache_all(void)
{
+ int ret;
+
__asm_flush_dcache_all();
- flush_l3_cache();
+ ret = __asm_flush_l3_cache();
+ if (ret)
+ debug("flushing dcache returns 0x%x\n", ret);
+ else
+ debug("flushing dcache successfully.\n");
}
/*
#include <asm/armv8/mmu.h>
#include <asm/io.h>
#include <asm/arch-fsl-lsch3/immap_lsch3.h>
+#include <fsl-mc/fsl_mc.h>
#include "cpu.h"
#include "mp.h"
#include "speed.h"
-#include <fsl_mc.h>
DECLARE_GLOBAL_DATA_PTR;
* set level 2 table 0 to cache-inhibit, covering 0 to 1GB
*/
section_l1t0 = 0;
- section_l1t1 = BLOCK_SIZE_L0;
+ section_l1t1 = BLOCK_SIZE_L0 | PMD_SECT_OUTER_SHARE;
section_l2 = 0;
for (i = 0; i < 512; i++) {
set_pgtable_section(level1_table_0, i, section_l1t0,
(u64)level2_table_0 | PMD_TYPE_TABLE;
level1_table_0[2] =
0x80000000 | PMD_SECT_AF | PMD_TYPE_SECT |
- PMD_ATTRINDX(MT_NORMAL);
+ PMD_SECT_OUTER_SHARE | PMD_ATTRINDX(MT_NORMAL);
level1_table_0[3] =
0xc0000000 | PMD_SECT_AF | PMD_TYPE_SECT |
- PMD_ATTRINDX(MT_NORMAL);
+ PMD_SECT_OUTER_SHARE | PMD_ATTRINDX(MT_NORMAL);
/* Rewrite table to enable cache */
set_pgtable_section(level2_table_0,
return 0;
}
-/*
- * flush_l3_cache
- * Dickens L3 cache can be flushed by transitioning from FAM to SFONLY power
- * state, by writing to HP-F P-state request register.
- * Fixme: This function should moved to a common file if other SoCs also use
- * the same Dickens.
- */
-#define HNF0_PSTATE_REQ 0x04200010
-#define HNF1_PSTATE_REQ 0x04210010
-#define HNF2_PSTATE_REQ 0x04220010
-#define HNF3_PSTATE_REQ 0x04230010
-#define HNF4_PSTATE_REQ 0x04240010
-#define HNF5_PSTATE_REQ 0x04250010
-#define HNF6_PSTATE_REQ 0x04260010
-#define HNF7_PSTATE_REQ 0x04270010
-#define HNFPSTAT_MASK (0xFFFFFFFFFFFFFFFC)
-#define HNFPSTAT_FAM 0x3
-#define HNFPSTAT_SFONLY 0x01
-
-static void hnf_pstate_req(u64 *ptr, u64 state)
-{
- int timeout = 1000;
- out_le64(ptr, (in_le64(ptr) & HNFPSTAT_MASK) | (state & 0x3));
- ptr++;
- /* checking if the transition is completed */
- while (timeout > 0) {
- if (((in_le64(ptr) & 0x0c) >> 2) == (state & 0x3))
- break;
- udelay(100);
- timeout--;
- }
-}
-
-void flush_l3_cache(void)
-{
- hnf_pstate_req((u64 *)HNF0_PSTATE_REQ, HNFPSTAT_SFONLY);
- hnf_pstate_req((u64 *)HNF1_PSTATE_REQ, HNFPSTAT_SFONLY);
- hnf_pstate_req((u64 *)HNF2_PSTATE_REQ, HNFPSTAT_SFONLY);
- hnf_pstate_req((u64 *)HNF3_PSTATE_REQ, HNFPSTAT_SFONLY);
- hnf_pstate_req((u64 *)HNF4_PSTATE_REQ, HNFPSTAT_SFONLY);
- hnf_pstate_req((u64 *)HNF5_PSTATE_REQ, HNFPSTAT_SFONLY);
- hnf_pstate_req((u64 *)HNF6_PSTATE_REQ, HNFPSTAT_SFONLY);
- hnf_pstate_req((u64 *)HNF7_PSTATE_REQ, HNFPSTAT_SFONLY);
- hnf_pstate_req((u64 *)HNF0_PSTATE_REQ, HNFPSTAT_FAM);
- hnf_pstate_req((u64 *)HNF1_PSTATE_REQ, HNFPSTAT_FAM);
- hnf_pstate_req((u64 *)HNF2_PSTATE_REQ, HNFPSTAT_FAM);
- hnf_pstate_req((u64 *)HNF3_PSTATE_REQ, HNFPSTAT_FAM);
- hnf_pstate_req((u64 *)HNF4_PSTATE_REQ, HNFPSTAT_FAM);
- hnf_pstate_req((u64 *)HNF5_PSTATE_REQ, HNFPSTAT_FAM);
- hnf_pstate_req((u64 *)HNF6_PSTATE_REQ, HNFPSTAT_FAM);
- hnf_pstate_req((u64 *)HNF7_PSTATE_REQ, HNFPSTAT_FAM);
-}
-
/*
* This function is called from lib/board.c.
* It recreates MMU table in main memory. MMU and d-cache are enabled earlier.
printf("\n Bus: %-4s MHz ",
strmhz(buf, sysinfo.freq_systembus));
printf("DDR: %-4s MHz", strmhz(buf, sysinfo.freq_ddrbus));
+ printf(" DP-DDR: %-4s MHz", strmhz(buf, sysinfo.freq_ddrbus2));
puts("\n");
return 0;
__maybe_unused u64 spin_tbl_addr = (u64)get_spin_tbl_addr();
fdt32_t *reg;
int addr_cells;
- u64 val;
+ u64 val, core_id;
size_t *boot_code_size = &(__secondary_boot_code_size);
off = fdt_path_offset(blob, "/cpus");
off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
while (off != -FDT_ERR_NOTFOUND) {
reg = (fdt32_t *)fdt_getprop(blob, off, "reg", 0);
+ core_id = of_read_number(reg, addr_cells);
if (reg) {
- val = spin_tbl_addr;
- val += id_to_core(of_read_number(reg, addr_cells))
- * SPIN_TABLE_ELEM_SIZE;
- val = cpu_to_fdt64(val);
- fdt_setprop_string(blob, off, "enable-method",
- "spin-table");
- fdt_setprop(blob, off, "cpu-release-addr",
- &val, sizeof(val));
+ if (core_id == 0 || (is_core_online(core_id))) {
+ val = spin_tbl_addr;
+ val += id_to_core(core_id) *
+ SPIN_TABLE_ELEM_SIZE;
+ val = cpu_to_fdt64(val);
+ fdt_setprop_string(blob, off, "enable-method",
+ "spin-table");
+ fdt_setprop(blob, off, "cpu-release-addr",
+ &val, sizeof(val));
+ } else {
+ debug("skipping offline core\n");
+ }
} else {
puts("Warning: found cpu node without reg property\n");
}
#ifdef CONFIG_MP
ft_fixup_cpu(blob);
#endif
+
+#ifdef CONFIG_SYS_NS16550
+ do_fixup_by_compat_u32(blob, "ns16550",
+ "clock-frequency", CONFIG_SYS_NS16550_CLK, 1);
+#endif
}
ldr x0, =secondary_boot_func
blr x0
2:
+
+#ifdef CONFIG_FSL_TZPC_BP147
+ /* Set Non Secure access for all devices protected via TZPC */
+ ldr x1, =TZPCDECPROT_0_SET_BASE /* Decode Protection-0 Set Reg */
+ orr w0, w0, #1 << 3 /* DCFG_RESET is accessible from NS world */
+ str w0, [x1]
+
+ isb
+ dsb sy
+#endif
+
+#ifdef CONFIG_FSL_TZASC_400
+ /* Set TZASC so that:
+ * a. We use only Region0 whose global secure write/read is EN
+ * b. We use only Region0 whose NSAID write/read is EN
+ *
+ * NOTE: As per the CCSR map doc, TZASC 3 and TZASC 4 are just
+ * placeholders.
+ */
+ ldr x1, =TZASC_GATE_KEEPER(0)
+ ldr x0, [x1] /* Filter 0 Gate Keeper Register */
+ orr x0, x0, #1 << 0 /* Set open_request for Filter 0 */
+ str x0, [x1]
+
+ ldr x1, =TZASC_GATE_KEEPER(1)
+ ldr x0, [x1] /* Filter 0 Gate Keeper Register */
+ orr x0, x0, #1 << 0 /* Set open_request for Filter 0 */
+ str x0, [x1]
+
+ ldr x1, =TZASC_REGION_ATTRIBUTES_0(0)
+ ldr x0, [x1] /* Region-0 Attributes Register */
+ orr x0, x0, #1 << 31 /* Set Sec global write en, Bit[31] */
+ orr x0, x0, #1 << 30 /* Set Sec global read en, Bit[30] */
+ str x0, [x1]
+
+ ldr x1, =TZASC_REGION_ATTRIBUTES_0(1)
+ ldr x0, [x1] /* Region-1 Attributes Register */
+ orr x0, x0, #1 << 31 /* Set Sec global write en, Bit[31] */
+ orr x0, x0, #1 << 30 /* Set Sec global read en, Bit[30] */
+ str x0, [x1]
+
+ ldr x1, =TZASC_REGION_ID_ACCESS_0(0)
+ ldr w0, [x1] /* Region-0 Access Register */
+ mov w0, #0xFFFFFFFF /* Set nsaid_wr_en and nsaid_rd_en */
+ str w0, [x1]
+
+ ldr x1, =TZASC_REGION_ID_ACCESS_0(1)
+ ldr w0, [x1] /* Region-1 Attributes Register */
+ mov w0, #0xFFFFFFFF /* Set nsaid_wr_en and nsaid_rd_en */
+ str w0, [x1]
+
+ isb
+ dsb sy
+#endif
mov lr, x29 /* Restore LR */
ret
ENDPROC(lowlevel_init)
+hnf_pstate_poll:
+ /* x0 has the desired status, return 0 for success, 1 for timeout
+ * clobber x1, x2, x3, x4, x6, x7
+ */
+ mov x1, x0
+ mov x7, #0 /* flag for timeout */
+ mrs x3, cntpct_el0 /* read timer */
+ add x3, x3, #1200 /* timeout after 100 microseconds */
+ mov x0, #0x18
+ movk x0, #0x420, lsl #16 /* HNF0_PSTATE_STATUS */
+ mov w6, #8 /* HN-F node count */
+1:
+ ldr x2, [x0]
+ cmp x2, x1 /* check status */
+ b.eq 2f
+ mrs x4, cntpct_el0
+ cmp x4, x3
+ b.ls 1b
+ mov x7, #1 /* timeout */
+ b 3f
+2:
+ add x0, x0, #0x10000 /* move to next node */
+ subs w6, w6, #1
+ cbnz w6, 1b
+3:
+ mov x0, x7
+ ret
+
+hnf_set_pstate:
+ /* x0 has the desired state, clobber x1, x2, x6 */
+ mov x1, x0
+ /* power state to SFONLY */
+ mov w6, #8 /* HN-F node count */
+ mov x0, #0x10
+ movk x0, #0x420, lsl #16 /* HNF0_PSTATE_REQ */
+1: /* set pstate to sfonly */
+ ldr x2, [x0]
+ and x2, x2, #0xfffffffffffffffc /* & HNFPSTAT_MASK */
+ orr x2, x2, x1
+ str x2, [x0]
+ add x0, x0, #0x10000 /* move to next node */
+ subs w6, w6, #1
+ cbnz w6, 1b
+
+ ret
+
+ENTRY(__asm_flush_l3_cache)
+ /*
+ * Return status in x0
+ * success 0
+ * tmeout 1 for setting SFONLY, 2 for FAM, 3 for both
+ */
+ mov x29, lr
+ mov x8, #0
+
+ dsb sy
+ mov x0, #0x1 /* HNFPSTAT_SFONLY */
+ bl hnf_set_pstate
+
+ mov x0, #0x4 /* SFONLY status */
+ bl hnf_pstate_poll
+ cbz x0, 1f
+ mov x8, #1 /* timeout */
+1:
+ dsb sy
+ mov x0, #0x3 /* HNFPSTAT_FAM */
+ bl hnf_set_pstate
+
+ mov x0, #0xc /* FAM status */
+ bl hnf_pstate_poll
+ cbz x0, 1f
+ add x8, x8, #0x2
+1:
+ mov x0, x8
+ mov lr, x29
+ ret
+ENDPROC(__asm_flush_l3_cache)
+
/* Keep literals not used by the secondary boot code outside it */
.ltorg
return !!((1 << core) & cpu_mask());
}
+int is_core_online(u64 cpu_id)
+{
+ u64 *table;
+ int pos = id_to_core(cpu_id);
+ table = (u64 *)get_spin_tbl_addr() + pos * WORDS_PER_SPIN_TABLE_ENTRY;
+ return table[SPIN_TABLE_ELEM_STATUS_IDX] == 1;
+}
+
int cpu_reset(int nr)
{
puts("Feature is not implemented.\n");
void *get_spin_tbl_addr(void);
phys_addr_t determine_mp_bootpg(void);
void secondary_boot_func(void);
+int is_core_online(u64 cpu_id);
#endif
#endif /* _FSL_CH3_MP_H */
sys_info->freq_systembus = sysclk;
#ifdef CONFIG_DDR_CLK_FREQ
sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
+ sys_info->freq_ddrbus2 = CONFIG_DDR_CLK_FREQ;
#else
sys_info->freq_ddrbus = sysclk;
+ sys_info->freq_ddrbus2 = sysclk;
#endif
sys_info->freq_systembus *= (in_le32(&gur->rcwsr[0]) >>
sys_info->freq_ddrbus *= (in_le32(&gur->rcwsr[0]) >>
FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT) &
FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK;
+ sys_info->freq_ddrbus2 *= (in_le32(&gur->rcwsr[0]) >>
+ FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_SHIFT) &
+ FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_MASK;
for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) {
/*
gd->cpu_clk = sys_info.freq_processor[0];
gd->bus_clk = sys_info.freq_systembus;
gd->mem_clk = sys_info.freq_ddrbus;
-
+ gd->arch.mem2_clk = sys_info.freq_ddrbus2;
#if defined(CONFIG_FSL_ESDHC)
gd->arch.sdhc_clk = gd->bus_clk / 2;
#endif /* defined(CONFIG_FSL_ESDHC) */
* get_ddr_freq
* return ddr bus freq in Hz
*********************************************/
-ulong get_ddr_freq(ulong dummy)
+ulong get_ddr_freq(ulong ctrl_num)
{
if (!gd->mem_clk)
get_clocks();
+ /*
+ * DDR controller 0 & 1 are on memory complex 0
+ * DDR controler 2 is on memory complext 1
+ */
+ if (ctrl_num >= 2)
+ return gd->arch.mem2_clk;
+
return gd->mem_clk;
}
+++ /dev/null
-/*
- * (C) Copyright 2009 Faraday Technology
- * Po-Yu Chuang <ratbert@faraday-tech.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __A320_H
-#define __A320_H
-
-/*
- * Hardware register bases
- */
-#define CONFIG_FTSMC020_BASE 0x90200000 /* Static Memory Controller */
-#define CONFIG_DEBUG_LED 0x902ffffc /* Debug LED */
-#define CONFIG_FTSDMC020_BASE 0x90300000 /* SDRAM Controller */
-#define CONFIG_FTMAC100_BASE 0x90900000 /* Ethernet */
-#define CONFIG_FTPMU010_BASE 0x98100000 /* Power Management Unit */
-#define CONFIG_FTTMR010_BASE 0x98400000 /* Timer */
-#define CONFIG_FTRTC010_BASE 0x98600000 /* Real Time Clock*/
-
-#endif /* __A320_H */
#define CONFIG_SYS_FSL_PMU_CLTBENR (CONFIG_SYS_FSL_PMU_ADDR + \
0x18A0)
+#define CONFIG_SYS_FSL_DCSR_DDR_ADDR 0x70012c000ULL
+#define CONFIG_SYS_FSL_DCSR_DDR2_ADDR 0x70012d000ULL
+#define CONFIG_SYS_FSL_DCSR_DDR3_ADDR 0x700132000ULL
+#define CONFIG_SYS_FSL_DCSR_DDR4_ADDR 0x700133000ULL
+
#define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01000000)
#define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01010000)
#define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x01020000)
#define I2C4_BASE_ADDR (CONFIG_SYS_IMMR + 0x01030000)
+/* TZ Protection Controller Definitions */
+#define TZPC_BASE 0x02200000
+#define TZPCR0SIZE_BASE (TZPC_BASE)
+#define TZPCDECPROT_0_STAT_BASE (TZPC_BASE + 0x800)
+#define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804)
+#define TZPCDECPROT_0_CLR_BASE (TZPC_BASE + 0x808)
+#define TZPCDECPROT_1_STAT_BASE (TZPC_BASE + 0x80C)
+#define TZPCDECPROT_1_SET_BASE (TZPC_BASE + 0x810)
+#define TZPCDECPROT_1_CLR_BASE (TZPC_BASE + 0x814)
+#define TZPCDECPROT_2_STAT_BASE (TZPC_BASE + 0x818)
+#define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C)
+#define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820)
+
+/* TZ Address Space Controller Definitions */
+#define TZASC1_BASE 0x01100000 /* as per CCSR map. */
+#define TZASC2_BASE 0x01110000 /* as per CCSR map. */
+#define TZASC3_BASE 0x01120000 /* as per CCSR map. */
+#define TZASC4_BASE 0x01130000 /* as per CCSR map. */
+#define TZASC_BUILD_CONFIG_REG(x) ((TZASC1_BASE + (x * 0x10000)))
+#define TZASC_ACTION_REG(x) ((TZASC1_BASE + (x * 0x10000)) + 0x004)
+#define TZASC_GATE_KEEPER(x) ((TZASC1_BASE + (x * 0x10000)) + 0x008)
+#define TZASC_REGION_BASE_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x100)
+#define TZASC_REGION_BASE_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x104)
+#define TZASC_REGION_TOP_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x108)
+#define TZASC_REGION_TOP_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x10C)
+#define TZASC_REGION_ATTRIBUTES_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x110)
+#define TZASC_REGION_ID_ACCESS_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x114)
+
/* Generic Interrupt Controller Definitions */
#define GICD_BASE 0x06000000
#define GICR_BASE 0x06100000
#error SoC not defined
#endif
+#ifdef CONFIG_LS2085A
+#define CONFIG_SYS_FSL_ERRATUM_A008336
+#define CONFIG_SYS_FSL_ERRATUM_A008514
+#endif
+
#endif /* _ASM_ARMV8_FSL_LSCH3_CONFIG_ */
unsigned long freq_processor[CONFIG_MAX_CPUS];
unsigned long freq_systembus;
unsigned long freq_ddrbus;
+ unsigned long freq_ddrbus2;
unsigned long freq_localbus;
unsigned long freq_qe;
#ifdef CONFIG_SYS_DPAA_FMAN
#define FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_MASK 0x1f
#define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT 10
#define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK 0x3f
+#define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_SHIFT 18
+#define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_MASK 0x3f
u8 res_180[0x200-0x180];
u32 scratchrw[32]; /* Scratch Read/Write */
u8 res_280[0x300-0x280];
+++ /dev/null
-/*
- * SPDX-License-Identifier: GPL-2.0+
- */
-#ifndef __address_h
-#define __address_h 1
-
-#define KS8695_SDRAM_START 0x00000000
-#define KS8695_SDRAM_SIZE 0x01000000
-#define KS8695_MEM_SIZE KS8695_SDRAM_SIZE
-#define KS8695_MEM_START KS8695_SDRAM_START
-
-#define KS8695_PCMCIA_IO_BASE 0x03800000
-#define KS8695_PCMCIA_IO_SIZE 0x00040000
-
-#define KS8695_IO_BASE 0x03FF0000
-#define KS8695_IO_SIZE 0x00010000
-
-#define KS8695_SYSTEN_CONFIG 0x00
-#define KS8695_SYSTEN_BUS_CLOCK 0x04
-
-#define KS8695_FLASH_START 0x02800000
-#define KS8695_FLASH_SIZE 0x00400000
-
-/*i/o control registers offset difinitions*/
-#define KS8695_IO_CTRL0 0x4000
-#define KS8695_IO_CTRL1 0x4004
-#define KS8695_IO_CTRL2 0x4008
-#define KS8695_IO_CTRL3 0x400C
-
-/*memory control registers offset difinitions*/
-#define KS8695_MEM_CTRL0 0x4010
-#define KS8695_MEM_CTRL1 0x4014
-#define KS8695_MEM_CTRL2 0x4018
-#define KS8695_MEM_CTRL3 0x401C
-#define KS8695_MEM_GENERAL 0x4020
-#define KS8695_SDRAM_CTRL0 0x4030
-#define KS8695_SDRAM_CTRL1 0x4034
-#define KS8695_SDRAM_GENERAL 0x4038
-#define KS8695_SDRAM_BUFFER 0x403C
-#define KS8695_SDRAM_REFRESH 0x4040
-
-/*WAN control registers offset difinitions*/
-#define KS8695_WAN_DMA_TX 0x6000
-#define KS8695_WAN_DMA_RX 0x6004
-#define KS8695_WAN_DMA_TX_START 0x6008
-#define KS8695_WAN_DMA_RX_START 0x600C
-#define KS8695_WAN_TX_LIST 0x6010
-#define KS8695_WAN_RX_LIST 0x6014
-#define KS8695_WAN_MAC_LOW 0x6018
-#define KS8695_WAN_MAC_HIGH 0x601C
-#define KS8695_WAN_MAC_ELOW 0x6080
-#define KS8695_WAN_MAC_EHIGH 0x6084
-
-/*LAN control registers offset difinitions*/
-#define KS8695_LAN_DMA_TX 0x8000
-#define KS8695_LAN_DMA_RX 0x8004
-#define KS8695_LAN_DMA_TX_START 0x8008
-#define KS8695_LAN_DMA_RX_START 0x800C
-#define KS8695_LAN_TX_LIST 0x8010
-#define KS8695_LAN_RX_LIST 0x8014
-#define KS8695_LAN_MAC_LOW 0x8018
-#define KS8695_LAN_MAC_HIGH 0x801C
-#define KS8695_LAN_MAC_ELOW 0X8080
-#define KS8695_LAN_MAC_EHIGH 0X8084
-
-/*HPNA control registers offset difinitions*/
-#define KS8695_HPNA_DMA_TX 0xA000
-#define KS8695_HPNA_DMA_RX 0xA004
-#define KS8695_HPNA_DMA_TX_START 0xA008
-#define KS8695_HPNA_DMA_RX_START 0xA00C
-#define KS8695_HPNA_TX_LIST 0xA010
-#define KS8695_HPNA_RX_LIST 0xA014
-#define KS8695_HPNA_MAC_LOW 0xA018
-#define KS8695_HPNA_MAC_HIGH 0xA01C
-#define KS8695_HPNA_MAC_ELOW 0xA080
-#define KS8695_HPNA_MAC_EHIGH 0xA084
-
-/*UART control registers offset difinitions*/
-#define KS8695_UART_RX_BUFFER 0xE000
-#define KS8695_UART_TX_HOLDING 0xE004
-
-#define KS8695_UART_FIFO_CTRL 0xE008
-#define KS8695_UART_FIFO_TRIG01 0x00
-#define KS8695_UART_FIFO_TRIG04 0x80
-#define KS8695_UART_FIFO_TXRST 0x03
-#define KS8695_UART_FIFO_RXRST 0x02
-#define KS8695_UART_FIFO_FEN 0x01
-
-#define KS8695_UART_LINE_CTRL 0xE00C
-#define KS8695_UART_LINEC_BRK 0x40
-#define KS8695_UART_LINEC_EPS 0x10
-#define KS8695_UART_LINEC_PEN 0x08
-#define KS8695_UART_LINEC_STP2 0x04
-#define KS8695_UART_LINEC_WLEN8 0x03
-#define KS8695_UART_LINEC_WLEN7 0x02
-#define KS8695_UART_LINEC_WLEN6 0x01
-#define KS8695_UART_LINEC_WLEN5 0x00
-
-#define KS8695_UART_MODEM_CTRL 0xE010
-#define KS8695_UART_MODEMC_RTS 0x02
-#define KS8695_UART_MODEMC_DTR 0x01
-
-#define KS8695_UART_LINE_STATUS 0xE014
-#define KS8695_UART_LINES_TXFE 0x20
-#define KS8695_UART_LINES_BE 0x10
-#define KS8695_UART_LINES_FE 0x08
-#define KS8695_UART_LINES_PE 0x04
-#define KS8695_UART_LINES_OE 0x02
-#define KS8695_UART_LINES_RXFE 0x01
-#define KS8695_UART_LINES_ANY (KS8695_UART_LINES_OE|KS8695_UART_LINES_BE|KS8695_UART_LINES_PE|KS8695_UART_LINES_FE)
-
-#define KS8695_UART_MODEM_STATUS 0xE018
-#define KS8695_UART_MODEM_DCD 0x80
-#define KS8695_UART_MODEM_DSR 0x20
-#define KS8695_UART_MODEM_CTS 0x10
-#define KS8695_UART_MODEM_DDCD 0x08
-#define KS8695_UART_MODEM_DDSR 0x02
-#define KS8695_UART_MODEM_DCTS 0x01
-#define UART8695_MODEM_ANY 0xFF
-
-#define KS8695_UART_DIVISOR 0xE01C
-#define KS8695_UART_STATUS 0xE020
-
-/*Interrupt controlller registers offset difinitions*/
-#define KS8695_INT_CONTL 0xE200
-#define KS8695_INT_ENABLE 0xE204
-#define KS8695_INT_ENABLE_MODEM 0x0800
-#define KS8695_INT_ENABLE_ERR 0x0400
-#define KS8695_INT_ENABLE_RX 0x0200
-#define KS8695_INT_ENABLE_TX 0x0100
-
-#define KS8695_INT_STATUS 0xE208
-#define KS8695_INT_WAN_PRIORITY 0xE20C
-#define KS8695_INT_HPNA_PRIORITY 0xE210
-#define KS8695_INT_LAN_PRIORITY 0xE214
-#define KS8695_INT_TIMER_PRIORITY 0xE218
-#define KS8695_INT_UART_PRIORITY 0xE21C
-#define KS8695_INT_EXT_PRIORITY 0xE220
-#define KS8695_INT_CHAN_PRIORITY 0xE224
-#define KS8695_INT_BUSERROR_PRO 0xE228
-#define KS8695_INT_MASK_STATUS 0xE22C
-#define KS8695_FIQ_PEND_PRIORITY 0xE230
-#define KS8695_IRQ_PEND_PRIORITY 0xE234
-
-/*timer registers offset difinitions*/
-#define KS8695_TIMER_CTRL 0xE400
-#define KS8695_TIMER1 0xE404
-#define KS8695_TIMER0 0xE408
-#define KS8695_TIMER1_PCOUNT 0xE40C
-#define KS8695_TIMER0_PCOUNT 0xE410
-
-/*GPIO registers offset difinitions*/
-#define KS8695_GPIO_MODE 0xE600
-#define KS8695_GPIO_CTRL 0xE604
-#define KS8695_GPIO_DATA 0xE608
-
-/*SWITCH registers offset difinitions*/
-#define KS8695_SWITCH_CTRL0 0xE800
-#define KS8695_SWITCH_CTRL1 0xE804
-#define KS8695_SWITCH_PORT1 0xE808
-#define KS8695_SWITCH_PORT2 0xE80C
-#define KS8695_SWITCH_PORT3 0xE810
-#define KS8695_SWITCH_PORT4 0xE814
-#define KS8695_SWITCH_PORT5 0xE818
-#define KS8695_SWITCH_AUTO0 0xE81C
-#define KS8695_SWITCH_AUTO1 0xE820
-#define KS8695_SWITCH_LUE_CTRL 0xE824
-#define KS8695_SWITCH_LUE_HIGH 0xE828
-#define KS8695_SWITCH_LUE_LOW 0xE82C
-#define KS8695_SWITCH_ADVANCED 0xE830
-
-#define KS8695_SWITCH_LPPM12 0xE874
-#define KS8695_SWITCH_LPPM34 0xE878
-
-/*host communication registers difinitions*/
-#define KS8695_DSCP_HIGH 0xE834
-#define KS8695_DSCP_LOW 0xE838
-#define KS8695_SWITCH_MAC_HIGH 0xE83C
-#define KS8695_SWITCH_MAC_LOW 0xE840
-
-/*miscellaneours registers difinitions*/
-#define KS8695_MANAGE_COUNTER 0xE844
-#define KS8695_MANAGE_DATA 0xE848
-#define KS8695_LAN12_POWERMAGR 0xE84C
-#define KS8695_LAN34_POWERMAGR 0xE850
-
-#define KS8695_DEVICE_ID 0xEA00
-#define KS8695_REVISION_ID 0xEA04
-
-#define KS8695_MISC_CONTROL 0xEA08
-#define KS8695_WAN_CONTROL 0xEA0C
-#define KS8695_WAN_POWERMAGR 0xEA10
-#define KS8695_WAN_PHY_CONTROL 0xEA14
-#define KS8695_WAN_PHY_STATUS 0xEA18
-
-/* bus clock definitions*/
-#define KS8695_BUS_CLOCK_125MHZ 0x0
-#define KS8695_BUS_CLOCK_100MHZ 0x1
-#define KS8695_BUS_CLOCK_62MHZ 0x2
-#define KS8695_BUS_CLOCK_50MHZ 0x3
-#define KS8695_BUS_CLOCK_41MHZ 0x4
-#define KS8695_BUS_CLOCK_33MHZ 0x5
-#define KS8695_BUS_CLOCK_31MHZ 0x6
-#define KS8695_BUS_CLOCK_25MHZ 0x7
-
-/* -------------------------------------------------------------------------------
- * definations for IRQ
- * -------------------------------------------------------------------------------*/
-
-#define KS8695_INT_EXT_INT0 2
-#define KS8695_INT_EXT_INT1 3
-#define KS8695_INT_EXT_INT2 4
-#define KS8695_INT_EXT_INT3 5
-#define KS8695_INT_TIMERINT0 6
-#define KS8695_INT_TIMERINT1 7
-#define KS8695_INT_UART_TX 8
-#define KS8695_INT_UART_RX 9
-#define KS8695_INT_UART_LINE_ERR 10
-#define KS8695_INT_UART_MODEMS 11
-#define KS8695_INT_LAN_STOP_RX 12
-#define KS8695_INT_LAN_STOP_TX 13
-#define KS8695_INT_LAN_BUF_RX_STATUS 14
-#define KS8695_INT_LAN_BUF_TX_STATUS 15
-#define KS8695_INT_LAN_RX_STATUS 16
-#define KS8695_INT_LAN_TX_STATUS 17
-#define KS8695_INT_HPAN_STOP_RX 18
-#define KS8695_INT_HPNA_STOP_TX 19
-#define KS8695_INT_HPNA_BUF_RX_STATUS 20
-#define KS8695_INT_HPNA_BUF_TX_STATUS 21
-#define KS8695_INT_HPNA_RX_STATUS 22
-#define KS8695_INT_HPNA_TX_STATUS 23
-#define KS8695_INT_BUS_ERROR 24
-#define KS8695_INT_WAN_STOP_RX 25
-#define KS8695_INT_WAN_STOP_TX 26
-#define KS8695_INT_WAN_BUF_RX_STATUS 27
-#define KS8695_INT_WAN_BUF_TX_STATUS 28
-#define KS8695_INT_WAN_RX_STATUS 29
-#define KS8695_INT_WAN_TX_STATUS 30
-
-#define KS8695_INT_UART KS8695_INT_UART_TX
-
-/* -------------------------------------------------------------------------------
- * Interrupt bit positions
- *
- * -------------------------------------------------------------------------------
- */
-
-#define KS8695_INTMASK_EXT_INT0 ( 1 << KS8695_INT_EXT_INT0 )
-#define KS8695_INTMASK_EXT_INT1 ( 1 << KS8695_INT_EXT_INT1 )
-#define KS8695_INTMASK_EXT_INT2 ( 1 << KS8695_INT_EXT_INT2 )
-#define KS8695_INTMASK_EXT_INT3 ( 1 << KS8695_INT_EXT_INT3 )
-#define KS8695_INTMASK_TIMERINT0 ( 1 << KS8695_INT_TIMERINT0 )
-#define KS8695_INTMASK_TIMERINT1 ( 1 << KS8695_INT_TIMERINT1 )
-#define KS8695_INTMASK_UART_TX ( 1 << KS8695_INT_UART_TX )
-#define KS8695_INTMASK_UART_RX ( 1 << KS8695_INT_UART_RX )
-#define KS8695_INTMASK_UART_LINE_ERR ( 1 << KS8695_INT_UART_LINE_ERR )
-#define KS8695_INTMASK_UART_MODEMS ( 1 << KS8695_INT_UART_MODEMS )
-#define KS8695_INTMASK_LAN_STOP_RX ( 1 << KS8695_INT_LAN_STOP_RX )
-#define KS8695_INTMASK_LAN_STOP_TX ( 1 << KS8695_INT_LAN_STOP_TX )
-#define KS8695_INTMASK_LAN_BUF_RX_STATUS ( 1 << KS8695_INT_LAN_BUF_RX_STATUS )
-#define KS8695_INTMASK_LAN_BUF_TX_STATUS ( 1 << KS8695_INT_LAN_BUF_TX_STATUS )
-#define KS8695_INTMASK_LAN_RX_STATUS ( 1 << KS8695_INT_LAN_RX_STATUS )
-#define KS8695_INTMASK_LAN_TX_STATUS ( 1 << KS8695_INT_LAN_RX_STATUS )
-#define KS8695_INTMASK_HPAN_STOP_RX ( 1 << KS8695_INT_HPAN_STOP_RX )
-#define KS8695_INTMASK_HPNA_STOP_TX ( 1 << KS8695_INT_HPNA_STOP_TX )
-#define KS8695_INTMASK_HPNA_BUF_RX_STATUS ( 1 << KS8695_INT_HPNA_BUF_RX_STATUS )
-#define KS8695_INTMAKS_HPNA_BUF_TX_STATUS ( 1 << KS8695_INT_HPNA_BUF_TX_STATUS
-#define KS8695_INTMASK_HPNA_RX_STATUS ( 1 << KS8695_INT_HPNA_RX_STATUS )
-#define KS8695_INTMASK_HPNA_TX_STATUS ( 1 << KS8695_INT_HPNA_TX_STATUS )
-#define KS8695_INTMASK_BUS_ERROR ( 1 << KS8695_INT_BUS_ERROR )
-#define KS8695_INTMASK_WAN_STOP_RX ( 1 << KS8695_INT_WAN_STOP_RX )
-#define KS8695_INTMASK_WAN_STOP_TX ( 1 << KS8695_INT_WAN_STOP_TX )
-#define KS8695_INTMASK_WAN_BUF_RX_STATUS ( 1 << KS8695_INT_WAN_BUF_RX_STATUS )
-#define KS8695_INTMASK_WAN_BUF_TX_STATUS ( 1 << KS8695_INT_WAN_BUF_TX_STATUS )
-#define KS8695_INTMASK_WAN_RX_STATUS ( 1 << KS8695_INT_WAN_RX_STATUS )
-#define KS8695_INTMASK_WAN_TX_STATUS ( 1 << KS8695_INT_WAN_TX_STATUS )
-
-#define KS8695_SC_VALID_INT 0xFFFFFFFF
-#define MAXIRQNUM 31
-
-/*
- * Timer definitions
- *
- * Use timer 1 & 2
- * (both run at 25MHz).
- *
- */
-#define TICKS_PER_uSEC 25
-#define mSEC_1 1000
-#define mSEC_10 (mSEC_1 * 10)
-
-#endif
-
-/* END */
#define CONFIG_SYS_LS102XA_USB1_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_LS102XA_USB1_OFFSET)
+#define CONFIG_SYS_FSL_SEC_OFFSET 0x00700000
#define CONFIG_SYS_LS102XA_USB1_OFFSET 0x07600000
#define CONFIG_SYS_TSEC1_OFFSET 0x01d10000
#define CONFIG_SYS_TSEC2_OFFSET 0x01d50000
#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000)
#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000)
+#define CONFIG_SYS_PCIE1_PHYS_BASE 0x4000000000ULL
+#define CONFIG_SYS_PCIE2_PHYS_BASE 0x4800000000ULL
+#define CONFIG_SYS_PCIE1_VIRT_ADDR 0x24000000UL
+#define CONFIG_SYS_PCIE2_VIRT_ADDR 0x34000000UL
+#define CONFIG_SYS_PCIE_MMAP_SIZE (192 * 1024 * 1024) /* 192M */
+/*
+ * TLB will map VIRT_ADDR to (PHYS_BASE + VIRT_ADDR)
+ * So 40bit PCIe PHY addr can directly be converted to a 32bit virtual addr.
+ */
+#define CONFIG_SYS_PCIE1_PHYS_ADDR (CONFIG_SYS_PCIE1_PHYS_BASE + \
+ CONFIG_SYS_PCIE1_VIRT_ADDR)
+#define CONFIG_SYS_PCIE2_PHYS_ADDR (CONFIG_SYS_PCIE2_PHYS_BASE + \
+ CONFIG_SYS_PCIE2_VIRT_ADDR)
+
#ifdef CONFIG_DDR_SPD
#define CONFIG_SYS_FSL_DDR_BE
#define CONFIG_VERY_BIG_RAM
#define DCFG_DCSR_PORCR1 0
+/*
+ * Define default values for some CCSR macros to make header files cleaner
+ *
+ * To completely disable CCSR relocation in a board header file, define
+ * CONFIG_SYS_CCSR_DO_NOT_RELOCATE. This will force CONFIG_SYS_CCSRBAR_PHYS
+ * to a value that is the same as CONFIG_SYS_CCSRBAR.
+ */
+
+#ifdef CONFIG_SYS_CCSRBAR_PHYS
+#error "Do not define CONFIG_SYS_CCSRBAR_PHYS directly."
+#endif
+
+#ifdef CONFIG_SYS_CCSR_DO_NOT_RELOCATE
+#undef CONFIG_SYS_CCSRBAR_PHYS_HIGH
+#undef CONFIG_SYS_CCSRBAR_PHYS_LOW
+#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0
+#endif
+
+#ifndef CONFIG_SYS_CCSRBAR
+#define CONFIG_SYS_CCSRBAR CONFIG_SYS_IMMR
+#endif
+
+#ifndef CONFIG_SYS_CCSRBAR_PHYS_HIGH
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0xf
+#else
+#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0
+#endif
+#endif
+
+#ifndef CONFIG_SYS_CCSRBAR_PHYS_LOW
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_IMMR
+#endif
+
+#define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \
+ CONFIG_SYS_CCSRBAR_PHYS_LOW)
+
struct sys_info {
unsigned long freq_processor[CONFIG_MAX_CPUS];
unsigned long freq_systembus;
u32 pex1rdmmsgrqsr;
u32 pex2rdmmsgrqsr;
u32 spimsiclrcr;
- u32 pex1mscportsr;
- u32 pex2mscportsr;
+ u32 pexmscportsr[2];
u32 pex2pmwrcr;
u32 resv5[24];
u32 mac1_streamid;
#ifndef __FSL_LS102XA_STREAM_ID_H_
#define __FSL_LS102XA_STREAM_ID_H_
+#include <fsl_sec.h>
+
+#define SET_LIODN_ENTRY_1(name, idA, off, compatoff) \
+ { .compat = name, \
+ .id = { idA }, .num_ids = 1, \
+ .reg_offset = off + CONFIG_SYS_IMMR, \
+ .compat_offset = compatoff + CONFIG_SYS_CCSRBAR_PHYS, \
+ }
+
+#define SET_LIODN_ENTRY_2(name, idA, idB, off, compatoff) \
+ { .compat = name, \
+ .id = { idA, idB }, .num_ids = 2, \
+ .reg_offset = off + CONFIG_SYS_IMMR, \
+ .compat_offset = compatoff + CONFIG_SYS_CCSRBAR_PHYS, \
+ }
+
+/*
+ * handle both old and new versioned SEC properties:
+ * "fsl,secX.Y" became "fsl,sec-vX.Y" during development
+ */
+#define SET_SEC_JR_LIODN_ENTRY(jrnum, liodnA, liodnB) \
+ SET_LIODN_ENTRY_2("fsl,sec4.0-job-ring", liodnA, liodnB, \
+ offsetof(ccsr_sec_t, jrliodnr[jrnum].ls) + \
+ CONFIG_SYS_FSL_SEC_OFFSET, \
+ CONFIG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrnum), \
+ SET_LIODN_ENTRY_2("fsl,sec-v4.0-job-ring", liodnA, liodnB,\
+ offsetof(ccsr_sec_t, jrliodnr[jrnum].ls) + \
+ CONFIG_SYS_FSL_SEC_OFFSET, \
+ CONFIG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrnum)
+
+/* This is a bit evil since we treat rtic param as both a string & hex value */
+#define SET_SEC_RTIC_LIODN_ENTRY(rtic, liodnA) \
+ SET_LIODN_ENTRY_1("fsl,sec4.0-rtic-memory", \
+ liodnA, \
+ offsetof(ccsr_sec_t, rticliodnr[0x##rtic-0xa].ls) + \
+ CONFIG_SYS_FSL_SEC_OFFSET, \
+ CONFIG_SYS_FSL_SEC_OFFSET + 0x6100 + 0x20 * (0x##rtic-0xa)), \
+ SET_LIODN_ENTRY_1("fsl,sec-v4.0-rtic-memory", \
+ liodnA, \
+ offsetof(ccsr_sec_t, rticliodnr[0x##rtic-0xa].ls) + \
+ CONFIG_SYS_FSL_SEC_OFFSET, \
+ CONFIG_SYS_FSL_SEC_OFFSET + 0x6100 + 0x20 * (0x##rtic-0xa))
+
+#define SET_SEC_DECO_LIODN_ENTRY(num, liodnA, liodnB) \
+ SET_LIODN_ENTRY_2(NULL, liodnA, liodnB, \
+ offsetof(ccsr_sec_t, decoliodnr[num].ls) + \
+ CONFIG_SYS_FSL_SEC_OFFSET, 0)
+
+struct liodn_id_table {
+ const char *compat;
+ u32 id[2];
+ u8 num_ids;
+ phys_addr_t compat_offset;
+ unsigned long reg_offset;
+};
+
struct smmu_stream_id {
uint16_t offset;
uint16_t stream_id;
char dev_name[32];
};
+void ls1021x_config_caam_stream_id(struct liodn_id_table *tbl, int size);
void ls102xa_config_smmu_stream_id(struct smmu_stream_id *id, uint32_t num);
#endif
+++ /dev/null
-/*
- * (C) Copyright 2007
- *
- * Author : Carsten Schneider, mycable GmbH
- * <cs@mycable.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H
-
-#include <linux/sizes.h>
-#include <asm/arch/mb86r0x.h>
-
-#endif
+++ /dev/null
-/*
- * (C) Copyright 2007
- *
- * mb86r0x definitions
- *
- * Author : Carsten Schneider, mycable GmbH
- * <cs@mycable.de>
- *
- * (C) Copyright 2010
- * Matthias Weisser <weisserm@arcor.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef MB86R0X_H
-#define MB86R0X_H
-
-#ifndef __ASSEMBLY__
-
-/* GPIO registers */
-struct mb86r0x_gpio {
- uint32_t gpdr0;
- uint32_t gpdr1;
- uint32_t gpdr2;
- uint32_t res;
- uint32_t gpddr0;
- uint32_t gpddr1;
- uint32_t gpddr2;
-};
-
-/* PWM registers */
-struct mb86r0x_pwm {
- uint32_t bcr;
- uint32_t tpr;
- uint32_t pr;
- uint32_t dr;
- uint32_t cr;
- uint32_t sr;
- uint32_t ccr;
- uint32_t ir;
-};
-
-/* The mb86r0x chip control (CCNT) register set. */
-struct mb86r0x_ccnt {
- uint32_t ccid;
- uint32_t csrst;
- uint32_t pad0[2];
- uint32_t cist;
- uint32_t cistm;
- uint32_t cgpio_ist;
- uint32_t cgpio_istm;
- uint32_t cgpio_ip;
- uint32_t cgpio_im;
- uint32_t caxi_bw;
- uint32_t caxi_ps;
- uint32_t cmux_md;
- uint32_t cex_pin_st;
- uint32_t cmlb;
- uint32_t pad1[1];
- uint32_t cusb;
- uint32_t pad2[41];
- uint32_t cbsc;
- uint32_t cdcrc;
- uint32_t cmsr0;
- uint32_t cmsr1;
- uint32_t pad3[2];
-};
-
-/* The mb86r0x clock reset generator */
-struct mb86r0x_crg {
- uint32_t crpr;
- uint32_t pad0;
- uint32_t crwr;
- uint32_t crsr;
- uint32_t crda;
- uint32_t crdb;
- uint32_t crha;
- uint32_t crpa;
- uint32_t crpb;
- uint32_t crhb;
- uint32_t cram;
-};
-
-/* The mb86r0x timer */
-struct mb86r0x_timer {
- uint32_t load;
- uint32_t value;
- uint32_t control;
- uint32_t intclr;
- uint32_t ris;
- uint32_t mis;
- uint32_t bgload;
-};
-
-/* mb86r0x gdc display controller */
-struct mb86r0x_gdc_dsp {
- /* Display settings */
- uint32_t dcm0;
- uint16_t pad00;
- uint16_t htp;
- uint16_t hdp;
- uint16_t hdb;
- uint16_t hsp;
- uint8_t hsw;
- uint8_t vsw;
- uint16_t pad01;
- uint16_t vtr;
- uint16_t vsp;
- uint16_t vdp;
- uint16_t wx;
- uint16_t wy;
- uint16_t ww;
- uint16_t wh;
-
- /* Layer 0 */
- uint32_t l0m;
- uint32_t l0oa;
- uint32_t l0da;
- uint16_t l0dx;
- uint16_t l0dy;
-
- /* Layer 1 */
- uint32_t l1m;
- uint32_t cbda0;
- uint32_t cbda1;
- uint32_t pad02;
-
- /* Layer 2 */
- uint32_t l2m;
- uint32_t l2oa0;
- uint32_t l2da0;
- uint32_t l2oa1;
- uint32_t l2da1;
- uint16_t l2dx;
- uint16_t l2dy;
-
- /* Layer 3 */
- uint32_t l3m;
- uint32_t l3oa0;
- uint32_t l3da0;
- uint32_t l3oa1;
- uint32_t l3da1;
- uint16_t l3dx;
- uint16_t l3dy;
-
- /* Layer 4 */
- uint32_t l4m;
- uint32_t l4oa0;
- uint32_t l4da0;
- uint32_t l4oa1;
- uint32_t l4da1;
- uint16_t l4dx;
- uint16_t l4dy;
-
- /* Layer 5 */
- uint32_t l5m;
- uint32_t l5oa0;
- uint32_t l5da0;
- uint32_t l5oa1;
- uint32_t l5da1;
- uint16_t l5dx;
- uint16_t l5dy;
-
- /* Cursor */
- uint16_t cutc;
- uint8_t cpm;
- uint8_t csize;
- uint32_t cuoa0;
- uint16_t cux0;
- uint16_t cuy0;
- uint32_t cuoa1;
- uint16_t cux1;
- uint16_t cuy1;
-
- /* Layer blending */
- uint32_t l0bld;
- uint32_t pad03;
- uint32_t l0tc;
- uint16_t l3tc;
- uint16_t l2tc;
- uint32_t pad04[15];
-
- /* Display settings */
- uint32_t dcm1;
- uint32_t dcm2;
- uint32_t dcm3;
- uint32_t pad05;
-
- /* Layer 0 extended */
- uint32_t l0em;
- uint16_t l0wx;
- uint16_t l0wy;
- uint16_t l0ww;
- uint16_t l0wh;
- uint32_t pad06;
-
- /* Layer 1 extended */
- uint32_t l1em;
- uint16_t l1wx;
- uint16_t l1wy;
- uint16_t l1ww;
- uint16_t l1wh;
- uint32_t pad07;
-
- /* Layer 2 extended */
- uint32_t l2em;
- uint16_t l2wx;
- uint16_t l2wy;
- uint16_t l2ww;
- uint16_t l2wh;
- uint32_t pad08;
-
- /* Layer 3 extended */
- uint32_t l3em;
- uint16_t l3wx;
- uint16_t l3wy;
- uint16_t l3ww;
- uint16_t l3wh;
- uint32_t pad09;
-
- /* Layer 4 extended */
- uint32_t l4em;
- uint16_t l4wx;
- uint16_t l4wy;
- uint16_t l4ww;
- uint16_t l4wh;
- uint32_t pad10;
-
- /* Layer 5 extended */
- uint32_t l5em;
- uint16_t l5wx;
- uint16_t l5wy;
- uint16_t l5ww;
- uint16_t l5wh;
- uint32_t pad11;
-
- /* Multi screen control */
- uint32_t msc;
- uint32_t pad12[3];
- uint32_t dls;
- uint32_t dbgc;
-
- /* Layer blending */
- uint32_t l1bld;
- uint32_t l2bld;
- uint32_t l3bld;
- uint32_t l4bld;
- uint32_t l5bld;
- uint32_t pad13;
-
- /* Extended transparency control */
- uint32_t l0etc;
- uint32_t l1etc;
- uint32_t l2etc;
- uint32_t l3etc;
- uint32_t l4etc;
- uint32_t l5etc;
- uint32_t pad14[10];
-
- /* YUV coefficients */
- uint32_t l1ycr0;
- uint32_t l1ycr1;
- uint32_t l1ycg0;
- uint32_t l1ycg1;
- uint32_t l1ycb0;
- uint32_t l1ycb1;
- uint32_t pad15[130];
-
- /* Layer palletes */
- uint32_t l0pal[256];
- uint32_t l1pal[256];
- uint32_t pad16[256];
- uint32_t l2pal[256];
- uint32_t l3pal[256];
- uint32_t pad17[256];
-
- /* PWM settings */
- uint32_t vpwmm;
- uint16_t vpwms;
- uint16_t vpwme;
- uint32_t vpwmc;
- uint32_t pad18[253];
-};
-
-/* mb86r0x gdc capture controller */
-struct mb86r0x_gdc_cap {
- uint32_t vcm;
- uint32_t csc;
- uint32_t vcs;
- uint32_t pad01;
-
- uint32_t cbm;
- uint32_t cboa;
- uint32_t cbla;
- uint16_t cihstr;
- uint16_t civstr;
- uint16_t cihend;
- uint16_t civend;
- uint32_t pad02;
-
- uint32_t chp;
- uint32_t cvp;
- uint32_t pad03[4];
-
- uint32_t clpf;
- uint32_t pad04;
- uint32_t cmss;
- uint32_t cmds;
- uint32_t pad05[12];
-
- uint32_t rgbhc;
- uint32_t rgbhen;
- uint32_t rgbven;
- uint32_t pad06;
- uint32_t rgbs;
- uint32_t pad07[11];
-
- uint32_t rgbcmy;
- uint32_t rgbcmcb;
- uint32_t rgbcmcr;
- uint32_t rgbcmb;
- uint32_t pad08[12 + 1984];
-};
-
-/* mb86r0x gdc draw */
-struct mb86r0x_gdc_draw {
- uint32_t ys;
- uint32_t xs;
- uint32_t dxdy;
- uint32_t xus;
- uint32_t dxudy;
- uint32_t xls;
- uint32_t dxldy;
- uint32_t usn;
- uint32_t lsn;
- uint32_t pad01[7];
- uint32_t rs;
- uint32_t drdx;
- uint32_t drdy;
- uint32_t gs;
- uint32_t dgdx;
- uint32_t dgdy;
- uint32_t bs;
- uint32_t dbdx;
- uint32_t dbdy;
- uint32_t pad02[7];
- uint32_t zs;
- uint32_t dzdx;
- uint32_t dzdy;
- uint32_t pad03[13];
- uint32_t ss;
- uint32_t dsdx;
- uint32_t dsdy;
- uint32_t ts;
- uint32_t dtdx;
- uint32_t dtdy;
- uint32_t qs;
- uint32_t dqdx;
- uint32_t dqdy;
- uint32_t pad04[23];
- uint32_t lpn;
- uint32_t lxs;
- uint32_t lxde;
- uint32_t lys;
- uint32_t lyde;
- uint32_t lzs;
- uint32_t lzde;
- uint32_t pad05[13];
- uint32_t pxdc;
- uint32_t pydc;
- uint32_t pzdc;
- uint32_t pad06[25];
- uint32_t rxs;
- uint32_t rys;
- uint32_t rsizex;
- uint32_t rsizey;
- uint32_t pad07[12];
- uint32_t saddr;
- uint32_t sstride;
- uint32_t srx;
- uint32_t sry;
- uint32_t daddr;
- uint32_t dstride;
- uint32_t drx;
- uint32_t dry;
- uint32_t brsizex;
- uint32_t brsizey;
- uint32_t tcolor;
- uint32_t pad08[93];
- uint32_t blpo;
- uint32_t pad09[7];
- uint32_t ctr;
- uint32_t ifsr;
- uint32_t ifcnt;
- uint32_t sst;
- uint32_t ds;
- uint32_t pst;
- uint32_t est;
- uint32_t pad10;
- uint32_t mdr0;
- uint32_t mdr1;
- uint32_t mdr2;
- uint32_t mdr3;
- uint32_t mdr4;
- uint32_t pad14[2];
- uint32_t mdr7;
- uint32_t fbr;
- uint32_t xres;
- uint32_t zbr;
- uint32_t tbr;
- uint32_t pfbr;
- uint32_t cxmin;
- uint32_t cxmax;
- uint32_t cymin;
- uint32_t cymax;
- uint32_t txs;
- uint32_t tis;
- uint32_t toa;
- uint32_t sho;
- uint32_t abr;
- uint32_t pad15[2];
- uint32_t fc;
- uint32_t bc;
- uint32_t alf;
- uint32_t blp;
- uint32_t pad16;
- uint32_t tbc;
- uint32_t pad11[42];
- uint32_t lx0dc;
- uint32_t ly0dc;
- uint32_t lx1dc;
- uint32_t ly1dc;
- uint32_t pad12[12];
- uint32_t x0dc;
- uint32_t y0dc;
- uint32_t x1dc;
- uint32_t y1dc;
- uint32_t x2dc;
- uint32_t y2dc;
- uint32_t pad13[666];
-};
-
-/* mb86r0x gdc geometry engine */
-struct mb86r0x_gdc_geom {
- uint32_t gctr;
- uint32_t pad00[15];
- uint32_t gmdr0;
- uint32_t gmdr1;
- uint32_t gmdr2;
- uint32_t pad01[237];
- uint32_t dfifog;
- uint32_t pad02[767];
-};
-
-/* mb86r0x gdc */
-struct mb86r0x_gdc {
- uint32_t pad00[2];
- uint32_t lts;
- uint32_t pad01;
- uint32_t lsta;
- uint32_t pad02[3];
- uint32_t ist;
- uint32_t imask;
- uint32_t pad03[6];
- uint32_t lsa;
- uint32_t lco;
- uint32_t lreq;
-
- uint32_t pad04[16*1024 - 19];
- struct mb86r0x_gdc_dsp dsp0;
- struct mb86r0x_gdc_dsp dsp1;
- uint32_t pad05[4*1024 - 2];
- uint32_t vccc;
- uint32_t vcsr;
- struct mb86r0x_gdc_cap cap0;
- struct mb86r0x_gdc_cap cap1;
- uint32_t pad06[4*1024];
- uint32_t texture_base[16*1024];
- struct mb86r0x_gdc_draw draw;
- uint32_t pad07[7*1024];
- struct mb86r0x_gdc_geom geom;
- uint32_t pad08[7*1024];
-};
-
-/* mb86r0x ddr2c */
-struct mb86r0x_ddr2c {
- uint16_t dric;
- uint16_t dric1;
- uint16_t dric2;
- uint16_t drca;
- uint16_t drcm;
- uint16_t drcst1;
- uint16_t drcst2;
- uint16_t drcr;
- uint16_t pad00[8];
- uint16_t drcf;
- uint16_t pad01[7];
- uint16_t drasr;
- uint16_t pad02[15];
- uint16_t drims;
- uint16_t pad03[7];
- uint16_t dros;
- uint16_t pad04;
- uint16_t dribsodt1;
- uint16_t dribsocd;
- uint16_t dribsocd2;
- uint16_t pad05[3];
- uint16_t droaba;
- uint16_t pad06[9];
- uint16_t drobs;
- uint16_t pad07[5];
- uint16_t drimr1;
- uint16_t drimr2;
- uint16_t drimr3;
- uint16_t drimr4;
- uint16_t droisr1;
- uint16_t droisr2;
-};
-
-/* mb86r0x memc */
-struct mb86r0x_memc {
- uint32_t mcfmode[8];
- uint32_t mcftim[8];
- uint32_t mcfarea[8];
-};
-
-#endif /* __ASSEMBLY__ */
-
-/*
- * Physical Address Defines
- */
-#define MB86R0x_DDR2_BASE 0xf3000000
-#define MB86R0x_GDC_BASE 0xf1fc0000
-#define MB86R0x_CCNT_BASE 0xfff42000
-#define MB86R0x_CAN0_BASE 0xfff54000
-#define MB86R0x_CAN1_BASE 0xfff55000
-#define MB86R0x_I2C0_BASE 0xfff56000
-#define MB86R0x_I2C1_BASE 0xfff57000
-#define MB86R0x_EHCI_BASE 0xfff80000
-#define MB86R0x_OHCI_BASE 0xfff81000
-#define MB86R0x_IRC1_BASE 0xfffb0000
-#define MB86R0x_MEMC_BASE 0xfffc0000
-#define MB86R0x_TIMER_BASE 0xfffe0000
-#define MB86R0x_UART0_BASE 0xfffe1000
-#define MB86R0x_UART1_BASE 0xfffe2000
-#define MB86R0x_IRCE_BASE 0xfffe4000
-#define MB86R0x_CRG_BASE 0xfffe7000
-#define MB86R0x_IRC0_BASE 0xfffe8000
-#define MB86R0x_GPIO_BASE 0xfffe9000
-#define MB86R0x_PWM0_BASE 0xfff41000
-#define MB86R0x_PWM1_BASE 0xfff41100
-
-#define MB86R0x_CRSR_SWRSTREQ (1 << 1)
-
-/*
- * Timer register bits
- */
-#define MB86R0x_TIMER_ENABLE (1 << 7)
-#define MB86R0x_TIMER_MODE_MSK (1 << 6)
-#define MB86R0x_TIMER_MODE_FR (0 << 6)
-#define MB86R0x_TIMER_MODE_PD (1 << 6)
-
-#define MB86R0x_TIMER_INT_EN (1 << 5)
-#define MB86R0x_TIMER_PRS_MSK (3 << 2)
-#define MB86R0x_TIMER_PRS_4S (1 << 2)
-#define MB86R0x_TIMER_PRS_8S (1 << 3)
-#define MB86R0x_TIMER_SIZE_32 (1 << 1)
-#define MB86R0x_TIMER_ONE_SHT (1 << 0)
-
-/*
- * Clock reset generator bits
- */
-#define MB86R0x_CRG_CRPR_PLLRDY (1 << 8)
-#define MB86R0x_CRG_CRPR_PLLMODE (0x1f << 0)
-#define MB86R0x_CRG_CRPR_PLLMODE_X49 (0 << 0)
-#define MB86R0x_CRG_CRPR_PLLMODE_X46 (1 << 0)
-#define MB86R0x_CRG_CRPR_PLLMODE_X37 (2 << 0)
-#define MB86R0x_CRG_CRPR_PLLMODE_X20 (3 << 0)
-#define MB86R0x_CRG_CRPR_PLLMODE_X47 (4 << 0)
-#define MB86R0x_CRG_CRPR_PLLMODE_X44 (5 << 0)
-#define MB86R0x_CRG_CRPR_PLLMODE_X36 (6 << 0)
-#define MB86R0x_CRG_CRPR_PLLMODE_X19 (7 << 0)
-#define MB86R0x_CRG_CRPR_PLLMODE_X39 (8 << 0)
-#define MB86R0x_CRG_CRPR_PLLMODE_X38 (9 << 0)
-#define MB86R0x_CRG_CRPR_PLLMODE_X30 (10 << 0)
-#define MB86R0x_CRG_CRPR_PLLMODE_X15 (11 << 0)
-/*
- * DDR2 controller bits
- */
-#define MB86R0x_DDR2_DRCI_DRINI (1 << 15)
-#define MB86R0x_DDR2_DRCI_CKEN (1 << 14)
-#define MB86R0x_DDR2_DRCI_DRCMD (1 << 0)
-#define MB86R0x_DDR2_DRCI_CMD (MB86R0x_DDR2_DRCI_DRINI | \
- MB86R0x_DDR2_DRCI_CKEN | \
- MB86R0x_DDR2_DRCI_DRCMD)
-#define MB86R0x_DDR2_DRCI_INIT (MB86R0x_DDR2_DRCI_DRINI | \
- MB86R0x_DDR2_DRCI_CKEN)
-#define MB86R0x_DDR2_DRCI_NORMAL MB86R0x_DDR2_DRCI_CKEN
-#endif /* MB86R0X_H */
+++ /dev/null
-/*
- * (C) Copyright 2011
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Lei Wen <leiwen@marvell.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _PANTHEON_CONFIG_H
-#define _PANTHEON_CONFIG_H
-
-#include <asm/arch/pantheon.h>
-
-/* default Dcache Line length for pantheon */
-#define CONFIG_SYS_CACHELINE_SIZE 32
-
-#define CONFIG_SYS_TCLK (14745600) /* NS16550 clk config */
-#define CONFIG_SYS_HZ_CLOCK (3250000) /* Timer Freq. 3.25MHZ */
-#define CONFIG_MARVELL_MFP /* Enable mvmfp driver */
-#define MV_MFPR_BASE PANTHEON_MFPR_BASE
-#define MV_UART_CONSOLE_BASE PANTHEON_UART1_BASE
-#define CONFIG_SYS_NS16550_IER (1 << 6) /* Bit 6 in UART_IER register
- represents UART Unit Enable */
-/*
- * I2C definition
- */
-#ifdef CONFIG_CMD_I2C
-#define CONFIG_I2C_MV 1
-#define CONFIG_MV_I2C_REG 0xd4011000
-#define CONFIG_HARD_I2C 1
-#define CONFIG_SYS_I2C_SPEED 0
-#define CONFIG_SYS_I2C_SLAVE 0xfe
-#endif
-
-/*
- * MMC definition
- */
-#ifdef CONFIG_CMD_MMC
-#define CONFIG_CMD_FAT 1
-#define CONFIG_MMC 1
-#define CONFIG_GENERIC_MMC 1
-#define CONFIG_SDHCI 1
-#define CONFIG_MMC_SDHCI_IO_ACCESSORS 1
-#define CONFIG_SYS_MMC_MAX_BLK_COUNT 0x1000
-#define CONFIG_MMC_SDMA 1
-#define CONFIG_MV_SDHCI 1
-#define CONFIG_DOS_PARTITION 1
-#define CONFIG_EFI_PARTITION 1
-#define CONFIG_SYS_MMC_NUM 2
-#define CONFIG_SYS_MMC_BASE {0xD4280000, 0xd4281000}
-#endif
-
-#endif /* _PANTHEON_CONFIG_H */
+++ /dev/null
-/*
- * (C) Copyright 2011
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Lei Wen <leiwen@marvell.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _PANTHEON_CPU_H
-#define _PANTHEON_CPU_H
-
-#include <asm/io.h>
-#include <asm/system.h>
-
-/*
- * Main Power Management (MPMU) Registers
- * Refer Register Datasheet 9.1
- */
-struct panthmpmu_registers {
- u8 pad0[0x0024];
- u32 ccgr; /*0x0024*/
- u8 pad1[0x0200 - 0x024 - 4];
- u32 wdtpcr; /*0x0200*/
- u8 pad2[0x1020 - 0x200 - 4];
- u32 aprr; /*0x1020*/
- u32 acgr; /*0x1024*/
-};
-
-/*
- * Application Power Management (APMU) Registers
- * Refer Register Datasheet 9.2
- */
-struct panthapmu_registers {
- u8 pad0[0x0054];
- u32 sd1; /*0x0054*/
- u8 pad1[0x00e0 - 0x054 - 4];
- u32 sd3; /*0x00e0*/
-};
-
-/*
- * APB Clock Reset/Control Registers
- * Refer Register Datasheet 6.14
- */
-struct panthapb_registers {
- u32 uart0; /*0x000*/
- u32 uart1; /*0x004*/
- u32 gpio; /*0x008*/
- u8 pad0[0x02c - 0x08 - 4];
- u32 twsi; /*0x02c*/
- u8 pad1[0x034 - 0x2c - 4];
- u32 timers; /*0x034*/
-};
-
-/*
- * CPU Interface Registers
- * Refer Register Datasheet 4.3
- */
-struct panthcpu_registers {
- u32 chip_id; /* Chip Id Reg */
- u32 pad;
- u32 cpu_conf; /* CPU Conf Reg */
- u32 pad1;
- u32 cpu_sram_spd; /* CPU SRAM Speed Reg */
- u32 pad2;
- u32 cpu_l2c_spd; /* CPU L2cache Speed Conf */
- u32 mcb_conf; /* MCB Conf Reg */
- u32 sys_boot_ctl; /* Sytem Boot Control */
-};
-
-/*
- * Functions
- */
-u32 panth_sdram_base(int);
-u32 panth_sdram_size(int);
-int mv_sdh_init(u32 regbase, u32 max_clk, u32 min_clk, u32 quirks);
-
-#endif /* _PANTHEON_CPU_H */
+++ /dev/null
-/*
- * Based on arch/arm/include/asm/arch-armada100/mfp.h
- * (C) Copyright 2011
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Lei Wen <leiwen@marvell.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __PANTHEON_MFP_H
-#define __PANTHEON_MFP_H
-
-/*
- * Frequently used MFP Configuration macros for all PANTHEON family of SoCs
- *
- * offset, pull,pF, drv,dF, edge,eF ,afn,aF
- */
-/* UART2 */
-#define MFP47_UART2_RXD (MFP_REG(0x198) | MFP_AF6 | MFP_DRIVE_MEDIUM)
-#define MFP48_UART2_TXD (MFP_REG(0x19c) | MFP_AF6 | MFP_DRIVE_MEDIUM)
-#define MFP53_CI2C_SCL (MFP_REG(0x1b0) | MFP_AF2 | MFP_DRIVE_MEDIUM)
-#define MFP54_CI2C_SDA (MFP_REG(0x1b4) | MFP_AF2 | MFP_DRIVE_MEDIUM)
-
-/* More macros can be defined here... */
-#define MFP_MMC1_DAT7 (MFP_REG(0x84) | MFP_AF0 | MFP_DRIVE_MEDIUM)
-#define MFP_MMC1_DAT6 (MFP_REG(0x88) | MFP_AF0 | MFP_DRIVE_MEDIUM)
-#define MFP_MMC1_DAT5 (MFP_REG(0x8c) | MFP_AF0 | MFP_DRIVE_MEDIUM)
-#define MFP_MMC1_DAT4 (MFP_REG(0x90) | MFP_AF0 | MFP_DRIVE_MEDIUM)
-#define MFP_MMC1_DAT3 (MFP_REG(0x94) | MFP_AF0 | MFP_DRIVE_FAST)
-#define MFP_MMC1_DAT2 (MFP_REG(0x98) | MFP_AF0 | MFP_DRIVE_FAST)
-#define MFP_MMC1_DAT1 (MFP_REG(0x9c) | MFP_AF0 | MFP_DRIVE_FAST)
-#define MFP_MMC1_DAT0 (MFP_REG(0xa0) | MFP_AF0 | MFP_DRIVE_FAST)
-#define MFP_MMC1_CMD (MFP_REG(0xa4) | MFP_AF0 | MFP_DRIVE_FAST)
-#define MFP_MMC1_CLK (MFP_REG(0xa8) | MFP_AF0 | MFP_DRIVE_FAST)
-#define MFP_MMC1_CD (MFP_REG(0xac) | MFP_AF0 | MFP_DRIVE_MEDIUM)
-#define MFP_MMC1_WP (MFP_REG(0xb0) | MFP_AF0 | MFP_DRIVE_MEDIUM)
-
-#define MFP_PIN_MAX 117
-#endif
+++ /dev/null
-/*
- * (C) Copyright 2011
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Lei Wen <leiwen@marvell.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _PANTHEON_H
-#define _PANTHEON_H
-
-/* Common APB clock register bit definitions */
-#define APBC_APBCLK (1<<0) /* APB Bus Clock Enable */
-#define APBC_FNCLK (1<<1) /* Functional Clock Enable */
-#define APBC_RST (1<<2) /* Reset Generation */
-/* Functional Clock Selection Mask */
-#define APBC_FNCLKSEL(x) (((x) & 0xf) << 4)
-
-/* Common APMU register bit definitions */
-#define APMU_PERI_CLK (1<<4) /* Peripheral Clock Enable */
-#define APMU_AXI_CLK (1<<3) /* AXI Clock Enable*/
-#define APMU_PERI_RST (1<<1) /* Peripheral Reset */
-#define APMU_AXI_RST (1<<0) /* AXI Reset */
-
-/* Register Base Addresses */
-#define PANTHEON_DRAM_BASE 0xB0000000
-#define PANTHEON_TIMER_BASE 0xD4014000
-#define PANTHEON_WD_TIMER_BASE 0xD4080000
-#define PANTHEON_APBC_BASE 0xD4015000
-#define PANTHEON_UART1_BASE 0xD4017000
-#define PANTHEON_UART2_BASE 0xD4018000
-#define PANTHEON_GPIO_BASE 0xD4019000
-#define PANTHEON_MFPR_BASE 0xD401E000
-#define PANTHEON_MPMU_BASE 0xD4050000
-#define PANTHEON_APMU_BASE 0xD4282800
-#define PANTHEON_CPU_BASE 0xD4282C00
-
-#endif /* _PANTHEON_H */
+++ /dev/null
-/*
- * TNETV107X: Clock APIs
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __ASM_ARCH_CLOCK_H
-#define __ASM_ARCH_CLOCK_H
-
-#define PSC_MDCTL_NEXT_SWRSTDISABLE 0x0
-#define PSC_MDCTL_NEXT_SYNCRST 0x1
-#define PSC_MDCTL_NEXT_DISABLE 0x2
-#define PSC_MDCTL_NEXT_ENABLE 0x3
-
-#define CONFIG_SYS_INT_OSC_FREQ 24000000
-
-#ifndef __ASSEMBLY__
-
-/* PLL identifiers */
-enum pll_type_e {
- SYS_PLL,
- TDM_PLL,
- ETH_PLL
-};
-
-/* PLL configuration data */
-struct pll_init_data {
- int pll;
- int internal_osc;
- unsigned long pll_freq;
- unsigned long div_freq[10];
-};
-
-void init_plls(int num_pll, struct pll_init_data *config);
-int lpsc_status(unsigned int mod);
-void lpsc_control(int mod, unsigned long state, int lrstz);
-unsigned long clk_get_rate(unsigned int clk);
-unsigned long clk_round_rate(unsigned int clk, unsigned long hz);
-int clk_set_rate(unsigned int clk, unsigned long hz);
-
-static inline void clk_enable(unsigned int mod)
-{
- lpsc_control(mod, PSC_MDCTL_NEXT_ENABLE, -1);
-}
-
-static inline void clk_disable(unsigned int mod)
-{
- lpsc_control(mod, PSC_MDCTL_NEXT_DISABLE, -1);
-}
-
-#endif
-
-#endif
+++ /dev/null
-/*
- * TNETV107X: Hardware information
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H
-
-#ifndef __ASSEMBLY__
-
-#include <linux/sizes.h>
-
-#define ASYNC_EMIF_NUM_CS 4
-#define ASYNC_EMIF_MODE_NOR 0
-#define ASYNC_EMIF_MODE_NAND 1
-#define ASYNC_EMIF_MODE_ONENAND 2
-#define ASYNC_EMIF_PRESERVE -1
-
-struct async_emif_config {
- unsigned mode;
- unsigned select_strobe;
- unsigned extend_wait;
- unsigned wr_setup;
- unsigned wr_strobe;
- unsigned wr_hold;
- unsigned rd_setup;
- unsigned rd_strobe;
- unsigned rd_hold;
- unsigned turn_around;
- enum {
- ASYNC_EMIF_8 = 0,
- ASYNC_EMIF_16 = 1,
- ASYNC_EMIF_32 = 2,
- } width;
-};
-
-void init_async_emif(int num_cs, struct async_emif_config *config);
-
-int wdt_start(unsigned long msecs);
-int wdt_stop(void);
-int wdt_kick(void);
-
-#endif
-
-/* Chip configuration unlock codes and registers */
-#define TNETV107X_KICK0 (TNETV107X_CHIP_CONFIG_SYS_BASE+0x38)
-#define TNETV107X_KICK1 (TNETV107X_CHIP_CONFIG_SYS_BASE+0x3c)
-#define TNETV107X_PINMUX(n) (TNETV107X_CHIP_CONFIG_SYS_BASE+0x150+(n)*4)
-#define TNETV107X_KICK0_MAGIC 0x83e70b13
-#define TNETV107X_KICK1_MAGIC 0x95a4f1e0
-
-/* Module base addresses */
-#define TNETV107X_TPCC_BASE 0x01C00000
-#define TNETV107X_TPTC0_BASE 0x01C10000
-#define TNETV107X_TPTC1_BASE 0x01C10400
-#define TNETV107X_INTC_BASE 0x03000000
-#define TNETV107X_LCD_CONTROLLER_BASE 0x08030000
-#define TNETV107X_INTD_BASE 0x08038000
-#define TNETV107X_INTD_IPC_BASE 0x08038000
-#define TNETV107X_INTD_FAST_BASE 0x08039000
-#define TNETV107X_INTD_ASYNC_BASE 0x0803A000
-#define TNETV107X_INTD_SLOW_BASE 0x0803B000
-#define TNETV107X_PKA_BASE 0x08040000
-#define TNETV107X_RNG_BASE 0x08044000
-#define TNETV107X_TIMER0_BASE 0x08086500
-#define TNETV107X_TIMER1_BASE 0x08086600
-#define TNETV107X_WDT0_ARM_BASE 0x08086700
-#define TNETV107X_WDT1_DSP_BASE 0x08086800
-#define TNETV107X_CHIP_CONFIG_SYS_BASE 0x08087000
-#define TNETV107X_GPIO_BASE 0x08088000
-#define TNETV107X_UART1_BASE 0x08088400
-#define TNETV107X_TOUCHSCREEN_BASE 0x08088500
-#define TNETV107X_SDIO0_BASE 0x08088700
-#define TNETV107X_SDIO1_BASE 0x08088800
-#define TNETV107X_MDIO_BASE 0x08088900
-#define TNETV107X_KEYPAD_BASE 0x08088A00
-#define TNETV107X_SSP_BASE 0x08088C00
-#define TNETV107X_CLOCK_CONTROL_BASE 0x0808A000
-#define TNETV107X_PSC_BASE 0x0808B000
-#define TNETV107X_TDM0_BASE 0x08100000
-#define TNETV107X_TDM1_BASE 0x08100100
-#define TNETV107X_MCDMA_BASE 0x08108000
-#define TNETV107X_UART0_DMA_BASE 0x08108200
-#define TNETV107X_USBSS_BASE 0x08120000
-#define TNETV107X_VLYNQ_CONTROL_BASE 0x0810D000
-#define TNETV107X_ASYNC_EMIF_CNTRL_BASE 0x08200000
-#define TNETV107X_VLYNQ_MEM_MAP_BASE 0x0C000000
-#define TNETV107X_IMCOP_BASE 0x01CC0000
-#define TNETV107X_MBX_LITE_BASE 0x07000000
-#define TNETV107X_ETHSS_BASE 0x0803C000
-#define TNETV107X_CPSW_BASE 0x0803C000
-#define TNETV107X_SPF_BASE 0x0803C800
-#define TNETV107X_IOPU_ETHSS_BASE 0x0803D000
-#define TNETV107X_VTP_CNTRL_0 0x0803D800
-#define TNETV107X_VTP_CNTRL_1 0x0803D900
-#define TNETV107X_UART2_DMA_BASE 0x08108400
-#define TNETV107X_INTERNAL_MEMORY 0x20000000
-#define TNETV107X_ASYNC_EMIF_DATA_CE0_BASE 0x30000000
-#define TNETV107X_ASYNC_EMIF_DATA_CE1_BASE 0x40000000
-#define TNETV107X_ASYNC_EMIF_DATA_CE2_BASE 0x44000000
-#define TNETV107X_ASYNC_EMIF_DATA_CE3_BASE 0x48000000
-#define TNETV107X_DDR_EMIF_DATA_BASE 0x80000000
-#define TNETV107X_DDR_EMIF_CONTROL_BASE 0x90000000
-
-/* LPSC module definitions */
-#define TNETV107X_LPSC_ARM 0
-#define TNETV107X_LPSC_GEM 1
-#define TNETV107X_LPSC_DDR2_PHY 2
-#define TNETV107X_LPSC_TPCC 3
-#define TNETV107X_LPSC_TPTC0 4
-#define TNETV107X_LPSC_TPTC1 5
-#define TNETV107X_LPSC_RAM 6
-#define TNETV107X_LPSC_MBX_LITE 7
-#define TNETV107X_LPSC_LCD 8
-#define TNETV107X_LPSC_ETHSS 9
-#define TNETV107X_LPSC_AEMIF 10
-#define TNETV107X_LPSC_CHIP_CFG 11
-#define TNETV107X_LPSC_TSC 12
-#define TNETV107X_LPSC_ROM 13
-#define TNETV107X_LPSC_UART2 14
-#define TNETV107X_LPSC_PKTSEC 15
-#define TNETV107X_LPSC_SECCTL 16
-#define TNETV107X_LPSC_KEYMGR 17
-#define TNETV107X_LPSC_KEYPAD 18
-#define TNETV107X_LPSC_GPIO 19
-#define TNETV107X_LPSC_MDIO 20
-#define TNETV107X_LPSC_SDIO0 21
-#define TNETV107X_LPSC_UART0 22
-#define TNETV107X_LPSC_UART1 23
-#define TNETV107X_LPSC_TIMER0 24
-#define TNETV107X_LPSC_TIMER1 25
-#define TNETV107X_LPSC_WDT_ARM 26
-#define TNETV107X_LPSC_WDT_DSP 27
-#define TNETV107X_LPSC_SSP 28
-#define TNETV107X_LPSC_TDM0 29
-#define TNETV107X_LPSC_VLYNQ 30
-#define TNETV107X_LPSC_MCDMA 31
-#define TNETV107X_LPSC_USB0 32
-#define TNETV107X_LPSC_TDM1 33
-#define TNETV107X_LPSC_DEBUGSS 34
-#define TNETV107X_LPSC_ETHSS_RGMII 35
-#define TNETV107X_LPSC_SYSTEM 36
-#define TNETV107X_LPSC_IMCOP 37
-#define TNETV107X_LPSC_SPARE 38
-#define TNETV107X_LPSC_SDIO1 39
-#define TNETV107X_LPSC_USB1 40
-#define TNETV107X_LPSC_USBSS 41
-#define TNETV107X_LPSC_DDR2_EMIF1_VRST 42
-#define TNETV107X_LPSC_DDR2_EMIF2_VCTL_RST 43
-#define TNETV107X_LPSC_MAX 44
-
-/* Interrupt controller */
-#define INTC_GLB_EN (TNETV107X_INTC_BASE + 0x10)
-#define INTC_HINT_EN (TNETV107X_INTC_BASE + 0x1500)
-#define INTC_EN_CLR0 (TNETV107X_INTC_BASE + 0x380)
-
-#define DAVINCI_ASYNC_EMIF_CNTRL_BASE TNETV107X_ASYNC_EMIF_CNTRL_BASE
-
-#endif /* __ASM_ARCH_HARDWARE_H */
+++ /dev/null
-/*
- * TNETV107X: Pinmux APIs
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __ASM_ARCH_MUX_H
-#define __ASM_ARCH_MUX_H
-
-struct pin_config {
- unsigned char reg_index;
- unsigned char mask_offset;
- unsigned char mode;
-};
-
-#define TNETV107X_MUX_CFG(reg, offset, mux_mode) \
- { reg, offset, mux_mode }
-
-int mux_select_pin(short index);
-int mux_select_pins(const short *pins);
-
-enum tnetv107x_pin_mux_index {
- TNETV107X_PIN_ASR_A00,
- TNETV107X_PIN_GPIO32,
- TNETV107X_PIN_ASR_A01,
- TNETV107X_PIN_GPIO33,
- TNETV107X_PIN_ASR_A02,
- TNETV107X_PIN_GPIO34,
- TNETV107X_PIN_ASR_A03,
- TNETV107X_PIN_GPIO35,
- TNETV107X_PIN_ASR_A04,
- TNETV107X_PIN_GPIO36,
- TNETV107X_PIN_ASR_A05,
- TNETV107X_PIN_GPIO37,
- TNETV107X_PIN_ASR_A06,
- TNETV107X_PIN_GPIO38,
- TNETV107X_PIN_ASR_A07,
- TNETV107X_PIN_GPIO39,
- TNETV107X_PIN_ASR_A08,
- TNETV107X_PIN_GPIO40,
- TNETV107X_PIN_ASR_A09,
- TNETV107X_PIN_GPIO41,
- TNETV107X_PIN_ASR_A10,
- TNETV107X_PIN_GPIO42,
- TNETV107X_PIN_ASR_A11,
- TNETV107X_PIN_BOOT_STRP_0,
- TNETV107X_PIN_ASR_A12,
- TNETV107X_PIN_BOOT_STRP_1,
- TNETV107X_PIN_ASR_A13,
- TNETV107X_PIN_GPIO43,
- TNETV107X_PIN_ASR_A14,
- TNETV107X_PIN_GPIO44,
- TNETV107X_PIN_ASR_A15,
- TNETV107X_PIN_GPIO45,
- TNETV107X_PIN_ASR_A16,
- TNETV107X_PIN_GPIO46,
- TNETV107X_PIN_ASR_A17,
- TNETV107X_PIN_GPIO47,
- TNETV107X_PIN_ASR_A18,
- TNETV107X_PIN_GPIO48,
- TNETV107X_PIN_SDIO1_DATA3_0,
- TNETV107X_PIN_ASR_A19,
- TNETV107X_PIN_GPIO49,
- TNETV107X_PIN_SDIO1_DATA2_0,
- TNETV107X_PIN_ASR_A20,
- TNETV107X_PIN_GPIO50,
- TNETV107X_PIN_SDIO1_DATA1_0,
- TNETV107X_PIN_ASR_A21,
- TNETV107X_PIN_GPIO51,
- TNETV107X_PIN_SDIO1_DATA0_0,
- TNETV107X_PIN_ASR_A22,
- TNETV107X_PIN_GPIO52,
- TNETV107X_PIN_SDIO1_CMD_0,
- TNETV107X_PIN_ASR_A23,
- TNETV107X_PIN_GPIO53,
- TNETV107X_PIN_SDIO1_CLK_0,
- TNETV107X_PIN_ASR_BA_1,
- TNETV107X_PIN_GPIO54,
- TNETV107X_PIN_SYS_PLL_CLK,
- TNETV107X_PIN_ASR_CS0,
- TNETV107X_PIN_ASR_CS1,
- TNETV107X_PIN_ASR_CS2,
- TNETV107X_PIN_TDM_PLL_CLK,
- TNETV107X_PIN_ASR_CS3,
- TNETV107X_PIN_ETH_PHY_CLK,
- TNETV107X_PIN_ASR_D00,
- TNETV107X_PIN_GPIO55,
- TNETV107X_PIN_ASR_D01,
- TNETV107X_PIN_GPIO56,
- TNETV107X_PIN_ASR_D02,
- TNETV107X_PIN_GPIO57,
- TNETV107X_PIN_ASR_D03,
- TNETV107X_PIN_GPIO58,
- TNETV107X_PIN_ASR_D04,
- TNETV107X_PIN_GPIO59_0,
- TNETV107X_PIN_ASR_D05,
- TNETV107X_PIN_GPIO60_0,
- TNETV107X_PIN_ASR_D06,
- TNETV107X_PIN_GPIO61_0,
- TNETV107X_PIN_ASR_D07,
- TNETV107X_PIN_GPIO62_0,
- TNETV107X_PIN_ASR_D08,
- TNETV107X_PIN_GPIO63_0,
- TNETV107X_PIN_ASR_D09,
- TNETV107X_PIN_GPIO64_0,
- TNETV107X_PIN_ASR_D10,
- TNETV107X_PIN_SDIO1_DATA3_1,
- TNETV107X_PIN_ASR_D11,
- TNETV107X_PIN_SDIO1_DATA2_1,
- TNETV107X_PIN_ASR_D12,
- TNETV107X_PIN_SDIO1_DATA1_1,
- TNETV107X_PIN_ASR_D13,
- TNETV107X_PIN_SDIO1_DATA0_1,
- TNETV107X_PIN_ASR_D14,
- TNETV107X_PIN_SDIO1_CMD_1,
- TNETV107X_PIN_ASR_D15,
- TNETV107X_PIN_SDIO1_CLK_1,
- TNETV107X_PIN_ASR_OE,
- TNETV107X_PIN_BOOT_STRP_2,
- TNETV107X_PIN_ASR_RNW,
- TNETV107X_PIN_GPIO29_0,
- TNETV107X_PIN_ASR_WAIT,
- TNETV107X_PIN_GPIO30_0,
- TNETV107X_PIN_ASR_WE,
- TNETV107X_PIN_BOOT_STRP_3,
- TNETV107X_PIN_ASR_WE_DQM0,
- TNETV107X_PIN_GPIO31,
- TNETV107X_PIN_LCD_PD17_0,
- TNETV107X_PIN_ASR_WE_DQM1,
- TNETV107X_PIN_ASR_BA0_0,
- TNETV107X_PIN_VLYNQ_CLK,
- TNETV107X_PIN_GPIO14,
- TNETV107X_PIN_LCD_PD19_0,
- TNETV107X_PIN_VLYNQ_RXD0,
- TNETV107X_PIN_GPIO15,
- TNETV107X_PIN_LCD_PD20_0,
- TNETV107X_PIN_VLYNQ_RXD1,
- TNETV107X_PIN_GPIO16,
- TNETV107X_PIN_LCD_PD21_0,
- TNETV107X_PIN_VLYNQ_TXD0,
- TNETV107X_PIN_GPIO17,
- TNETV107X_PIN_LCD_PD22_0,
- TNETV107X_PIN_VLYNQ_TXD1,
- TNETV107X_PIN_GPIO18,
- TNETV107X_PIN_LCD_PD23_0,
- TNETV107X_PIN_SDIO0_CLK,
- TNETV107X_PIN_GPIO19,
- TNETV107X_PIN_SDIO0_CMD,
- TNETV107X_PIN_GPIO20,
- TNETV107X_PIN_SDIO0_DATA0,
- TNETV107X_PIN_GPIO21,
- TNETV107X_PIN_SDIO0_DATA1,
- TNETV107X_PIN_GPIO22,
- TNETV107X_PIN_SDIO0_DATA2,
- TNETV107X_PIN_GPIO23,
- TNETV107X_PIN_SDIO0_DATA3,
- TNETV107X_PIN_GPIO24,
- TNETV107X_PIN_EMU0,
- TNETV107X_PIN_EMU1,
- TNETV107X_PIN_RTCK,
- TNETV107X_PIN_TRST_N,
- TNETV107X_PIN_TCK,
- TNETV107X_PIN_TDI,
- TNETV107X_PIN_TDO,
- TNETV107X_PIN_TMS,
- TNETV107X_PIN_TDM1_CLK,
- TNETV107X_PIN_TDM1_RX,
- TNETV107X_PIN_TDM1_TX,
- TNETV107X_PIN_TDM1_FS,
- TNETV107X_PIN_KEYPAD_R0,
- TNETV107X_PIN_KEYPAD_R1,
- TNETV107X_PIN_KEYPAD_R2,
- TNETV107X_PIN_KEYPAD_R3,
- TNETV107X_PIN_KEYPAD_R4,
- TNETV107X_PIN_KEYPAD_R5,
- TNETV107X_PIN_KEYPAD_R6,
- TNETV107X_PIN_GPIO12,
- TNETV107X_PIN_KEYPAD_R7,
- TNETV107X_PIN_GPIO10,
- TNETV107X_PIN_KEYPAD_C0,
- TNETV107X_PIN_KEYPAD_C1,
- TNETV107X_PIN_KEYPAD_C2,
- TNETV107X_PIN_KEYPAD_C3,
- TNETV107X_PIN_KEYPAD_C4,
- TNETV107X_PIN_KEYPAD_C5,
- TNETV107X_PIN_KEYPAD_C6,
- TNETV107X_PIN_GPIO13,
- TNETV107X_PIN_TEST_CLK_IN,
- TNETV107X_PIN_KEYPAD_C7,
- TNETV107X_PIN_GPIO11,
- TNETV107X_PIN_SSP0_0,
- TNETV107X_PIN_SCC_DCLK,
- TNETV107X_PIN_LCD_PD20_1,
- TNETV107X_PIN_SSP0_1,
- TNETV107X_PIN_SCC_CS_N,
- TNETV107X_PIN_LCD_PD21_1,
- TNETV107X_PIN_SSP0_2,
- TNETV107X_PIN_SCC_D,
- TNETV107X_PIN_LCD_PD22_1,
- TNETV107X_PIN_SSP0_3,
- TNETV107X_PIN_SCC_RESETN,
- TNETV107X_PIN_LCD_PD23_1,
- TNETV107X_PIN_SSP1_0,
- TNETV107X_PIN_GPIO25,
- TNETV107X_PIN_UART2_CTS,
- TNETV107X_PIN_SSP1_1,
- TNETV107X_PIN_GPIO26,
- TNETV107X_PIN_UART2_RD,
- TNETV107X_PIN_SSP1_2,
- TNETV107X_PIN_GPIO27,
- TNETV107X_PIN_UART2_RTS,
- TNETV107X_PIN_SSP1_3,
- TNETV107X_PIN_GPIO28,
- TNETV107X_PIN_UART2_TD,
- TNETV107X_PIN_UART0_CTS,
- TNETV107X_PIN_UART0_RD,
- TNETV107X_PIN_UART0_RTS,
- TNETV107X_PIN_UART0_TD,
- TNETV107X_PIN_UART1_RD,
- TNETV107X_PIN_UART1_TD,
- TNETV107X_PIN_LCD_AC_NCS,
- TNETV107X_PIN_LCD_HSYNC_RNW,
- TNETV107X_PIN_LCD_VSYNC_A0,
- TNETV107X_PIN_LCD_MCLK,
- TNETV107X_PIN_LCD_PD16_0,
- TNETV107X_PIN_LCD_PCLK_E,
- TNETV107X_PIN_LCD_PD00,
- TNETV107X_PIN_LCD_PD01,
- TNETV107X_PIN_LCD_PD02,
- TNETV107X_PIN_LCD_PD03,
- TNETV107X_PIN_LCD_PD04,
- TNETV107X_PIN_LCD_PD05,
- TNETV107X_PIN_LCD_PD06,
- TNETV107X_PIN_LCD_PD07,
- TNETV107X_PIN_LCD_PD08,
- TNETV107X_PIN_GPIO59_1,
- TNETV107X_PIN_LCD_PD09,
- TNETV107X_PIN_GPIO60_1,
- TNETV107X_PIN_LCD_PD10,
- TNETV107X_PIN_ASR_BA0_1,
- TNETV107X_PIN_GPIO61_1,
- TNETV107X_PIN_LCD_PD11,
- TNETV107X_PIN_GPIO62_1,
- TNETV107X_PIN_LCD_PD12,
- TNETV107X_PIN_GPIO63_1,
- TNETV107X_PIN_LCD_PD13,
- TNETV107X_PIN_GPIO64_1,
- TNETV107X_PIN_LCD_PD14,
- TNETV107X_PIN_GPIO29_1,
- TNETV107X_PIN_LCD_PD15,
- TNETV107X_PIN_GPIO30_1,
- TNETV107X_PIN_EINT0,
- TNETV107X_PIN_GPIO08,
- TNETV107X_PIN_EINT1,
- TNETV107X_PIN_GPIO09,
- TNETV107X_PIN_GPIO00,
- TNETV107X_PIN_LCD_PD20_2,
- TNETV107X_PIN_TDM_CLK_IN_2,
- TNETV107X_PIN_GPIO01,
- TNETV107X_PIN_LCD_PD21_2,
- TNETV107X_PIN_24M_CLK_OUT_1,
- TNETV107X_PIN_GPIO02,
- TNETV107X_PIN_LCD_PD22_2,
- TNETV107X_PIN_GPIO03,
- TNETV107X_PIN_LCD_PD23_2,
- TNETV107X_PIN_GPIO04,
- TNETV107X_PIN_LCD_PD16_1,
- TNETV107X_PIN_USB0_RXERR,
- TNETV107X_PIN_GPIO05,
- TNETV107X_PIN_LCD_PD17_1,
- TNETV107X_PIN_TDM_CLK_IN_1,
- TNETV107X_PIN_GPIO06,
- TNETV107X_PIN_LCD_PD18,
- TNETV107X_PIN_24M_CLK_OUT_2,
- TNETV107X_PIN_GPIO07,
- TNETV107X_PIN_LCD_PD19_1,
- TNETV107X_PIN_USB1_RXERR,
- TNETV107X_PIN_ETH_PLL_CLK,
- TNETV107X_PIN_MDIO,
- TNETV107X_PIN_MDC,
- TNETV107X_PIN_AIC_MUTE_STAT_N,
- TNETV107X_PIN_TDM0_CLK,
- TNETV107X_PIN_AIC_HNS_EN_N,
- TNETV107X_PIN_TDM0_FS,
- TNETV107X_PIN_AIC_HDS_EN_STAT_N,
- TNETV107X_PIN_TDM0_TX,
- TNETV107X_PIN_AIC_HNF_EN_STAT_N,
- TNETV107X_PIN_TDM0_RX,
-};
-
-#endif
/*
* Section
*/
-#define PMD_SECT_S (3 << 8)
+#define PMD_SECT_OUTER_SHARE (2 << 8)
+#define PMD_SECT_INNER_SHARE (3 << 8)
#define PMD_SECT_AF (1 << 10)
#define PMD_SECT_NG (1 << 11)
#define PMD_SECT_PXN (UL(1) << 53)
#ifdef CONFIG_OMAP
struct omap_boot_parameters omap_boot_params;
#endif
+#ifdef CONFIG_FSL_LSCH3
+ unsigned long mem2_clk;
+#endif
};
#include <asm-generic/global_data.h>
void __asm_flush_dcache_range(u64 start, u64 end);
void __asm_invalidate_tlb_all(void);
void __asm_invalidate_icache_all(void);
+int __asm_flush_l3_cache(void);
void armv8_switch_to_el2(void);
void armv8_switch_to_el1(void);
#include <common.h>
#include <linux/kbuild.h>
-#if defined(CONFIG_MB86R0x)
-#include <asm/arch/mb86r0x.h>
-#endif
#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX35) \
|| defined(CONFIG_MX51) || defined(CONFIG_MX53)
#include <asm/arch/imx-regs.h>
{
/*
* TODO : Check if each entry in this file is really necessary.
- * - struct mb86r0x_ddr2
- * - struct mb86r0x_memc
* - struct esdramc_regs
* - struct max_regs
* - struct aips_regs
* code. Is it better to define the macros directly in headers?
*/
-#if defined(CONFIG_MB86R0x)
- /* ddr2 controller */
- DEFINE(DDR2_DRIC, offsetof(struct mb86r0x_ddr2c, dric));
- DEFINE(DDR2_DRIC1, offsetof(struct mb86r0x_ddr2c, dric1));
- DEFINE(DDR2_DRIC2, offsetof(struct mb86r0x_ddr2c, dric2));
- DEFINE(DDR2_DRCA, offsetof(struct mb86r0x_ddr2c, drca));
- DEFINE(DDR2_DRCM, offsetof(struct mb86r0x_ddr2c, drcm));
- DEFINE(DDR2_DRCST1, offsetof(struct mb86r0x_ddr2c, drcst1));
- DEFINE(DDR2_DRCST2, offsetof(struct mb86r0x_ddr2c, drcst2));
- DEFINE(DDR2_DRCR, offsetof(struct mb86r0x_ddr2c, drcr));
- DEFINE(DDR2_DRCF, offsetof(struct mb86r0x_ddr2c, drcf));
- DEFINE(DDR2_DRASR, offsetof(struct mb86r0x_ddr2c, drasr));
- DEFINE(DDR2_DRIMS, offsetof(struct mb86r0x_ddr2c, drims));
- DEFINE(DDR2_DROS, offsetof(struct mb86r0x_ddr2c, dros));
- DEFINE(DDR2_DRIBSODT1, offsetof(struct mb86r0x_ddr2c, dribsodt1));
- DEFINE(DDR2_DROABA, offsetof(struct mb86r0x_ddr2c, droaba));
- DEFINE(DDR2_DROBS, offsetof(struct mb86r0x_ddr2c, drobs));
-
- /* clock reset generator */
- DEFINE(CRG_CRPR, offsetof(struct mb86r0x_crg, crpr));
- DEFINE(CRG_CRHA, offsetof(struct mb86r0x_crg, crha));
- DEFINE(CRG_CRPA, offsetof(struct mb86r0x_crg, crpa));
- DEFINE(CRG_CRPB, offsetof(struct mb86r0x_crg, crpb));
- DEFINE(CRG_CRHB, offsetof(struct mb86r0x_crg, crhb));
- DEFINE(CRG_CRAM, offsetof(struct mb86r0x_crg, cram));
-
- /* chip control module */
- DEFINE(CCNT_CDCRC, offsetof(struct mb86r0x_ccnt, cdcrc));
-
- /* external bus interface */
- DEFINE(MEMC_MCFMODE0, offsetof(struct mb86r0x_memc, mcfmode[0]));
- DEFINE(MEMC_MCFMODE2, offsetof(struct mb86r0x_memc, mcfmode[2]));
- DEFINE(MEMC_MCFMODE4, offsetof(struct mb86r0x_memc, mcfmode[4]));
- DEFINE(MEMC_MCFTIM0, offsetof(struct mb86r0x_memc, mcftim[0]));
- DEFINE(MEMC_MCFTIM2, offsetof(struct mb86r0x_memc, mcftim[2]));
- DEFINE(MEMC_MCFTIM4, offsetof(struct mb86r0x_memc, mcftim[4]));
- DEFINE(MEMC_MCFAREA0, offsetof(struct mb86r0x_memc, mcfarea[0]));
- DEFINE(MEMC_MCFAREA2, offsetof(struct mb86r0x_memc, mcfarea[2]));
- DEFINE(MEMC_MCFAREA4, offsetof(struct mb86r0x_memc, mcfarea[4]));
-#endif
-
#if defined(CONFIG_MX25)
/* Clock Control Module */
DEFINE(CCM_CCTL, offsetof(struct ccm_regs, cctl));
static void do_nonsec_virt_switch(void)
{
smp_kick_all_cpus();
- flush_dcache_all(); /* flush cache before swtiching to EL2 */
+ dcache_disable(); /* flush cache before swtiching to EL2 */
armv8_switch_to_el2();
#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
armv8_switch_to_el1();
bool "CAM ENC 4xx board"
select SUPPORT_SPL
-config TARGET_HAWKBOARD
- bool "Hawkboard"
- select SUPPORT_SPL
-
config TARGET_DAVINCI_DM355EVM
bool "DM355 EVM board"
default 0x1800
config USE_PRIVATE_LIBGCC
- default y if SPL_BUILD
+ default y
config DM
- default y if !SPL_BUILD
+ default y
config DM_SERIAL
- default y if !SPL_BUILD
+ default y
config DM_SPI
- default y if !SPL_BUILD
+ default y
config DM_SPI_FLASH
- default y if !SPL_BUILD
+ default y
config DM_I2C
- default y if !SPL_BUILD
+ default y
config DM_GPIO
- default y if !SPL_BUILD
+ default y
source "arch/arm/mach-tegra/tegra20/Kconfig"
source "arch/arm/mach-tegra/tegra30/Kconfig"
+++ /dev/null
-if TARGET_DKB
-
-config SYS_BOARD
- default "dkb"
-
-config SYS_VENDOR
- default "Marvell"
-
-config SYS_SOC
- default "pantheon"
-
-config SYS_CONFIG_NAME
- default "dkb"
-
-endif
+++ /dev/null
-DKB BOARD
-M: Lei Wen <leiwen@marvell.com>
-S: Maintained
-F: board/Marvell/dkb/
-F: include/configs/dkb.h
-F: configs/dkb_defconfig
+++ /dev/null
-#
-# (C) Copyright 2011
-# Marvell Semiconductor <www.marvell.com>
-# Written-by: Lei Wen <leiwen@marvell.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := dkb.o
+++ /dev/null
-/*
- * (C) Copyright 2011
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Lei Wen <leiwen@marvell.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <mvmfp.h>
-#include <i2c.h>
-#include <asm/arch/mfp.h>
-#include <asm/arch/cpu.h>
-#ifdef CONFIG_GENERIC_MMC
-#include <sdhci.h>
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_early_init_f(void)
-{
- u32 mfp_cfg[] = {
- /* Enable Console on UART2 */
- MFP47_UART2_RXD,
- MFP48_UART2_TXD,
-
- /* I2C */
- MFP53_CI2C_SCL,
- MFP54_CI2C_SDA,
-
- /* MMC1 */
- MFP_MMC1_DAT7,
- MFP_MMC1_DAT6,
- MFP_MMC1_DAT5,
- MFP_MMC1_DAT4,
- MFP_MMC1_DAT3,
- MFP_MMC1_DAT2,
- MFP_MMC1_DAT1,
- MFP_MMC1_DAT0,
- MFP_MMC1_CMD,
- MFP_MMC1_CLK,
- MFP_MMC1_CD,
- MFP_MMC1_WP,
-
- MFP_EOC /*End of configureation*/
- };
- /* configure MFP's */
- mfp_config(mfp_cfg);
-
- return 0;
-}
-
-int board_init(void)
-{
- /* arch number of Board */
- gd->bd->bi_arch_number = MACH_TYPE_TTC_DKB;
- /* adress of boot parameters */
- gd->bd->bi_boot_params = panth_sdram_base(0) + 0x100;
- return 0;
-}
-
-#ifdef CONFIG_GENERIC_MMC
-#define I2C_SLAVE_ADDR 0x34
-#define LDO13_REG 0x28
-#define LDO_V30 0x6
-#define LDO_VOLTAGE(x) ((x & 0x7) << 1)
-#define LDO_EN 0x1
-int board_mmc_init(bd_t *bd)
-{
- ulong mmc_base_address[CONFIG_SYS_MMC_NUM] = CONFIG_SYS_MMC_BASE;
- u8 i, data;
-
- /* set LDO 13 to 3.0v */
- data = LDO_VOLTAGE(LDO_V30) | LDO_EN;
- i2c_write(I2C_SLAVE_ADDR, LDO13_REG, 1, &data, 1);
-
- for (i = 0; i < CONFIG_SYS_MMC_NUM; i++) {
- if (mv_sdh_init(mmc_base_address[i], 0, 0,
- SDHCI_QUIRK_32BIT_DMA_ADDR))
- return 1;
- }
-
- return 0;
-}
-#endif
+++ /dev/null
-if TARGET_CM4008
-
-config SYS_BOARD
- default "cm4008"
-
-config SYS_SOC
- default "ks8695"
-
-config SYS_CONFIG_NAME
- default "cm4008"
-
-endif
+++ /dev/null
-CM4008 BOARD
-M: Greg Ungerer <greg.ungerer@opengear.com>
-S: Maintained
-F: board/cm4008/
-F: include/configs/cm4008.h
-F: configs/cm4008_defconfig
+++ /dev/null
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := cm4008.o flash.o
+++ /dev/null
-/*
- * (C) Copyright 2005
- * Greg Ungerer, OpenGear Inc, <greg.ungerer@opengear.com>
- *
- * (C) Copyright 2002
- * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/platform.h>
-#include <netdev.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* ------------------------------------------------------------------------- */
-
-#define ks8695_read(a) *((volatile unsigned int *) (KS8695_IO_BASE+(a)))
-#define ks8695_write(a,b) *((volatile unsigned int *) (KS8695_IO_BASE+(a))) = (b)
-
-/* ------------------------------------------------------------------------- */
-
-
-/*
- * Miscelaneous platform dependent initialisations
- */
-int env_flash_cmdline (void)
-{
- char *sp = (char *) 0x0201c020;
- char *ep;
- int len;
-
- /* Check if "erase" push button is depressed */
- if ((ks8695_read(KS8695_GPIO_DATA) & 0x8) == 0) {
- printf("### Entering network recovery mode...\n");
- setenv("bootargs", "console=ttyAM0,115200 mem=16M initrd=0x400000,6M root=/dev/ram0");
- setenv("bootcmd", "bootp 0x400000; gofsk 0x400000");
- setenv("bootdelay", "2");
- return 0;
- }
-
- /* Check for flash based kernel boot args to use as default */
- for (ep = sp, len = 0; ((len < 1024) && (*ep != 0)); ep++, len++)
- ;
-
- if ((len > 0) && (len <1024))
- setenv("bootargs", sp);
-
- return 0;
-}
-
-int board_late_init (void)
-{
- return 0;
-}
-
-int board_eth_init(bd_t *bis)
-{
- return ks8695_eth_initialize();
-}
-
-int board_init (void)
-{
- /* arch number of CM4008 */
- gd->bd->bi_arch_number = 624;
-
- /* adress of boot parameters */
- gd->bd->bi_boot_params = 0x00000100;
-
- /* power down all but port 0 on the switch */
- ks8695_write(KS8695_SWITCH_LPPM12, 0x00000005);
- ks8695_write(KS8695_SWITCH_LPPM34, 0x00050005);
-
- return 0;
-}
-
-int dram_init (void)
-{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-
- return (0);
-}
+++ /dev/null
-CONFIG_SYS_TEXT_BASE = 0x00f00000
+++ /dev/null
-/*
- * (C) Copyright 2005
- * Greg Ungerer, OpenGear Inc, greg.ungerer@opengear.com
- *
- * (C) Copyright 2001
- * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
- *
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <linux/byteorder/swab.h>
-#include <asm/sections.h>
-
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-#define mb() __asm__ __volatile__ ("" : : : "memory")
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size (unsigned char * addr, flash_info_t * info);
-static int write_data (flash_info_t * info, ulong dest, unsigned char data);
-static void flash_get_offsets (ulong base, flash_info_t * info);
-void inline spin_wheel (void);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
- int i;
- ulong size = 0;
-
- for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
- switch (i) {
- case 0:
- flash_get_size ((unsigned char *) PHYS_FLASH_1, &flash_info[i]);
- flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);
- break;
- case 1:
- /* ignore for now */
- flash_info[i].flash_id = FLASH_UNKNOWN;
- break;
- default:
- panic ("configured too many flash banks!\n");
- break;
- }
- size += flash_info[i].size;
- }
-
- /* Protect monitor and environment sectors
- */
- flash_protect (FLAG_PROTECT_SET,
- CONFIG_SYS_FLASH_BASE,
- CONFIG_SYS_FLASH_BASE + (__bss_end - __bss_start),
- &flash_info[0]);
-
- return size;
-}
-
-/*-----------------------------------------------------------------------
- */
-static void flash_get_offsets (ulong base, flash_info_t * info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN)
- return;
-
- if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
- for (i = 0; i < info->sector_count; i++) {
- info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE);
- info->protect[i] = 0;
- }
- }
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t * info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_INTEL:
- printf ("INTEL ");
- break;
- default:
- printf ("Unknown Vendor ");
- break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_28F128J3A:
- printf ("28F128J3A\n");
- break;
- default:
- printf ("Unknown Chip Type\n");
- break;
- }
-
- printf (" Size: %ld MB in %d Sectors\n",
- info->size >> 20, info->sector_count);
-
- printf (" Sector Start Addresses:");
- for (i = 0; i < info->sector_count; ++i) {
- if ((i % 5) == 0)
- printf ("\n ");
- printf (" %08lX%s",
- info->start[i], info->protect[i] ? " (RO)" : " ");
- }
- printf ("\n");
- return;
-}
-
-/*
- * The following code cannot be run from FLASH!
- */
-static ulong flash_get_size (unsigned char * addr, flash_info_t * info)
-{
- volatile unsigned char value;
-
- /* Write auto select command: read Manufacturer ID */
- addr[0x5555] = 0xAA;
- addr[0x2AAA] = 0x55;
- addr[0x5555] = 0x90;
-
- mb ();
- value = addr[0];
-
- switch (value) {
-
- case (unsigned char)INTEL_MANUFACT:
- info->flash_id = FLASH_MAN_INTEL;
- break;
-
- default:
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- addr[0] = 0xFF; /* restore read mode */
- return (0); /* no or unknown flash */
- }
-
- mb ();
- value = addr[2]; /* device ID */
-
- switch (value) {
-
- case (unsigned char)INTEL_ID_28F640J3A:
- info->flash_id += FLASH_28F640J3A;
- info->sector_count = 64;
- info->size = 0x00800000;
- break; /* => 8 MB */
-
- case (unsigned char)INTEL_ID_28F128J3A:
- info->flash_id += FLASH_28F128J3A;
- info->sector_count = 128;
- info->size = 0x01000000;
- break; /* => 16 MB */
-
- default:
- info->flash_id = FLASH_UNKNOWN;
- break;
- }
-
- if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
- printf ("** ERROR: sector count %d > max (%d) **\n",
- info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
- info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
- }
-
- addr[0] = 0xFF; /* restore read mode */
-
- return (info->size);
-}
-
-
-/*-----------------------------------------------------------------------
- */
-
-int flash_erase (flash_info_t * info, int s_first, int s_last)
-{
- int prot, sect;
- ulong type;
- int rcode = 0;
- ulong start;
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
- return 1;
- }
-
- type = (info->flash_id & FLASH_VENDMASK);
- if ((type != FLASH_MAN_INTEL)) {
- printf ("Can't erase unknown flash type %08lx - aborted\n",
- info->flash_id);
- return 1;
- }
-
- prot = 0;
- for (sect = s_first; sect <= s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot)
- printf ("- Warning: %d protected sectors will not be erased!\n", prot);
- else
- printf ("\n");
-
- /* Disable interrupts which might cause a timeout here */
- disable_interrupts();
-
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect <= s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- volatile unsigned char *addr;
- unsigned char status;
-
- printf ("Erasing sector %2d ... ", sect);
-
- /* arm simple, non interrupt dependent timer */
- start = get_timer(0);
-
- addr = (volatile unsigned char *) (info->start[sect]);
- *addr = 0x50; /* clear status register */
- *addr = 0x20; /* erase setup */
- *addr = 0xD0; /* erase confirm */
-
- while (((status = *addr) & 0x80) != 0x80) {
- if (get_timer(start) >
- CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
- *addr = 0xB0; /* suspend erase */
- *addr = 0xFF; /* reset to read mode */
- rcode = 1;
- break;
- }
- }
-
- *addr = 0x50; /* clear status register cmd */
- *addr = 0xFF; /* resest to read mode */
-
- printf (" done\n");
- }
- }
- return rcode;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- * 4 - Flash not identified
- */
-
-int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
-{
- ulong cp, wp;
- unsigned char data;
- int count, i, l, rc, port_width;
-
- if (info->flash_id == FLASH_UNKNOWN)
- return 4;
-
- wp = addr;
- port_width = 1;
-
- /*
- * handle unaligned start bytes
- */
- if ((l = addr - wp) != 0) {
- data = 0;
- for (i = 0, cp = wp; i < l; ++i, ++cp) {
- data = (data << 8) | (*(uchar *) cp);
- }
- for (; i < port_width && cnt > 0; ++i) {
- data = (data << 8) | *src++;
- --cnt;
- ++cp;
- }
- for (; cnt == 0 && i < port_width; ++i, ++cp) {
- data = (data << 8) | (*(uchar *) cp);
- }
-
- if ((rc = write_data (info, wp, data)) != 0) {
- return (rc);
- }
- wp += port_width;
- }
-
- /*
- * handle word aligned part
- */
- count = 0;
- while (cnt >= port_width) {
- data = 0;
- for (i = 0; i < port_width; ++i) {
- data = (data << 8) | *src++;
- }
- if ((rc = write_data (info, wp, data)) != 0) {
- return (rc);
- }
- wp += port_width;
- cnt -= port_width;
- if (count++ > 0x800) {
- spin_wheel ();
- count = 0;
- }
- }
-
- if (cnt == 0) {
- return (0);
- }
-
- /*
- * handle unaligned tail bytes
- */
- data = 0;
- for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
- data = (data << 8) | *src++;
- --cnt;
- }
- for (; i < port_width; ++i, ++cp) {
- data = (data << 8) | (*(uchar *) cp);
- }
-
- return (write_data (info, wp, data));
-}
-
-/*-----------------------------------------------------------------------
- * Write a word or halfword to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_data (flash_info_t * info, ulong dest, unsigned char data)
-{
- volatile unsigned char *addr = (volatile unsigned char *) dest;
- ulong status;
- ulong start;
-
- /* Check if Flash is (sufficiently) erased */
- if ((*addr & data) != data) {
- printf ("not erased at %08lx (%lx)\n", (ulong) addr,
- (ulong) * addr);
- return (2);
- }
- /* Disable interrupts which might cause a timeout here */
- disable_interrupts();
-
- *addr = 0x40; /* write setup */
- *addr = data;
-
- /* arm simple, non interrupt dependent timer */
- start = get_timer(0);
-
- /* wait while polling the status register */
- while (((status = *addr) & 0x80) != 0x80) {
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- *addr = 0xFF; /* restore read mode */
- return (1);
- }
- }
-
- *addr = 0xFF; /* restore read mode */
-
- return (0);
-}
-
-void inline spin_wheel (void)
-{
- static int p = 0;
- static char w[] = "\\/-";
-
- printf ("\010%c", w[p]);
- (++p == 3) ? (p = 0) : 0;
-}
+++ /dev/null
-if TARGET_CM41XX
-
-config SYS_BOARD
- default "cm41xx"
-
-config SYS_SOC
- default "ks8695"
-
-config SYS_CONFIG_NAME
- default "cm41xx"
-
-endif
+++ /dev/null
-CM41XX BOARD
-#M: -
-S: Maintained
-F: board/cm41xx/
-F: include/configs/cm41xx.h
-F: configs/cm41xx_defconfig
+++ /dev/null
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := cm41xx.o flash.o
+++ /dev/null
-/*
- * (C) Copyright 2005
- * Greg Ungerer, OpenGear Inc, <greg.ungerer@opengear.com>
- *
- * (C) Copyright 2002
- * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/platform.h>
-#include <netdev.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* ------------------------------------------------------------------------- */
-
-#define ks8695_read(a) *((volatile unsigned int *) (KS8695_IO_BASE+(a)))
-#define ks8695_write(a,b) *((volatile unsigned int *) (KS8695_IO_BASE+(a))) = (b)
-
-/* ------------------------------------------------------------------------- */
-
-
-/*
- * Miscelaneous platform dependent initialisations
- */
-int env_flash_cmdline (void)
-{
- char *sp = (char *) 0x0201c020;
- char *ep;
- int len;
-
- /* Check if "erase" push button is depressed */
- if ((ks8695_read(KS8695_GPIO_DATA) & 0x8) == 0) {
- printf("### Entering network recovery mode...\n");
- setenv("bootargs", "console=ttyAM0,115200 mem=32M initrd=0x400000,8M root=/dev/ram0");
- setenv("bootcmd", "bootp 0x400000; gofsk 0x400000");
- setenv("bootdelay", "2");
- return 0;
- }
-
- /* Check for flash based kernel boot args to use as default */
- for (ep = sp, len = 0; ((len < 1024) && (*ep != 0)); ep++, len++)
- ;
-
- if ((len > 0) && (len <1024))
- setenv("bootargs", sp);
-
- return 0;
-}
-
-int board_late_init (void)
-{
- return 0;
-}
-
-int board_eth_init(bd_t *bis)
-{
- return ks8695_eth_initialize();
-}
-
-int board_init (void)
-{
- /* arch number of CM41xx */
- gd->bd->bi_arch_number = 672;
-
- /* adress of boot parameters */
- gd->bd->bi_boot_params = 0x00000100;
-
- /* power down all but port 0 on the switch */
- ks8695_write(KS8695_SWITCH_LPPM12, 0x00000005);
- ks8695_write(KS8695_SWITCH_LPPM34, 0x00050005);
-
- return 0;
-}
-
-int dram_init (void)
-{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-
- return (0);
-}
+++ /dev/null
-CONFIG_SYS_TEXT_BASE = 0x00f00000
+++ /dev/null
-/*
- * (C) Copyright 2005
- * Greg Ungerer, OpenGear Inc, greg.ungerer@opengear.com
- *
- * (C) Copyright 2001
- * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
- *
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <linux/byteorder/swab.h>
-#include <asm/sections.h>
-
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-#define mb() __asm__ __volatile__ ("" : : : "memory")
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size (unsigned char * addr, flash_info_t * info);
-static int write_data (flash_info_t * info, ulong dest, unsigned char data);
-static void flash_get_offsets (ulong base, flash_info_t * info);
-void inline spin_wheel (void);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
- int i;
- ulong size = 0;
-
- for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
- switch (i) {
- case 0:
- flash_get_size ((unsigned char *) PHYS_FLASH_1, &flash_info[i]);
- flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);
- break;
- case 1:
- /* ignore for now */
- flash_info[i].flash_id = FLASH_UNKNOWN;
- break;
- default:
- panic ("configured too many flash banks!\n");
- break;
- }
- size += flash_info[i].size;
- }
-
- /* Protect monitor and environment sectors
- */
- flash_protect (FLAG_PROTECT_SET,
- CONFIG_SYS_FLASH_BASE,
- CONFIG_SYS_FLASH_BASE + (__bss_end - __bss_start),
- &flash_info[0]);
-
- return size;
-}
-
-/*-----------------------------------------------------------------------
- */
-static void flash_get_offsets (ulong base, flash_info_t * info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN)
- return;
-
- if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
- for (i = 0; i < info->sector_count; i++) {
- info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE);
- info->protect[i] = 0;
- }
- }
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t * info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_INTEL:
- printf ("INTEL ");
- break;
- default:
- printf ("Unknown Vendor ");
- break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_28F128J3A:
- printf ("28F128J3A\n");
- break;
- default:
- printf ("Unknown Chip Type\n");
- break;
- }
-
- printf (" Size: %ld MB in %d Sectors\n",
- info->size >> 20, info->sector_count);
-
- printf (" Sector Start Addresses:");
- for (i = 0; i < info->sector_count; ++i) {
- if ((i % 5) == 0)
- printf ("\n ");
- printf (" %08lX%s",
- info->start[i], info->protect[i] ? " (RO)" : " ");
- }
- printf ("\n");
- return;
-}
-
-/*
- * The following code cannot be run from FLASH!
- */
-static ulong flash_get_size (unsigned char * addr, flash_info_t * info)
-{
- volatile unsigned char value;
-
- /* Write auto select command: read Manufacturer ID */
- addr[0x5555] = 0xAA;
- addr[0x2AAA] = 0x55;
- addr[0x5555] = 0x90;
-
- mb ();
- value = addr[0];
-
- switch (value) {
-
- case (unsigned char)INTEL_MANUFACT:
- info->flash_id = FLASH_MAN_INTEL;
- break;
-
- default:
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- addr[0] = 0xFF; /* restore read mode */
- return (0); /* no or unknown flash */
- }
-
- mb ();
- value = addr[2]; /* device ID */
-
- switch (value) {
-
- case (unsigned char)INTEL_ID_28F640J3A:
- info->flash_id += FLASH_28F640J3A;
- info->sector_count = 64;
- info->size = 0x00800000;
- break; /* => 8 MB */
-
- case (unsigned char)INTEL_ID_28F128J3A:
- info->flash_id += FLASH_28F128J3A;
- info->sector_count = 128;
- info->size = 0x01000000;
- break; /* => 16 MB */
-
- default:
- info->flash_id = FLASH_UNKNOWN;
- break;
- }
-
- if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
- printf ("** ERROR: sector count %d > max (%d) **\n",
- info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
- info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
- }
-
- addr[0] = 0xFF; /* restore read mode */
-
- return (info->size);
-}
-
-
-/*-----------------------------------------------------------------------
- */
-
-int flash_erase (flash_info_t * info, int s_first, int s_last)
-{
- int prot, sect;
- ulong type;
- int rcode = 0;
- ulong start;
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
- return 1;
- }
-
- type = (info->flash_id & FLASH_VENDMASK);
- if ((type != FLASH_MAN_INTEL)) {
- printf ("Can't erase unknown flash type %08lx - aborted\n",
- info->flash_id);
- return 1;
- }
-
- prot = 0;
- for (sect = s_first; sect <= s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot)
- printf ("- Warning: %d protected sectors will not be erased!\n", prot);
- else
- printf ("\n");
-
- /* Disable interrupts which might cause a timeout here */
- disable_interrupts();
-
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect <= s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- volatile unsigned char *addr;
- unsigned char status;
-
- printf ("Erasing sector %2d ... ", sect);
-
- /* arm simple, non interrupt dependent timer */
- start = get_timer(0);
-
- addr = (volatile unsigned char *) (info->start[sect]);
- *addr = 0x50; /* clear status register */
- *addr = 0x20; /* erase setup */
- *addr = 0xD0; /* erase confirm */
-
- while (((status = *addr) & 0x80) != 0x80) {
- if (get_timer(start) >
- CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
- *addr = 0xB0; /* suspend erase */
- *addr = 0xFF; /* reset to read mode */
- rcode = 1;
- break;
- }
- }
-
- *addr = 0x50; /* clear status register cmd */
- *addr = 0xFF; /* resest to read mode */
-
- printf (" done\n");
- }
- }
- return rcode;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- * 4 - Flash not identified
- */
-
-int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
-{
- ulong cp, wp;
- unsigned char data;
- int count, i, l, rc, port_width;
-
- if (info->flash_id == FLASH_UNKNOWN)
- return 4;
-
- wp = addr;
- port_width = 1;
-
- /*
- * handle unaligned start bytes
- */
- if ((l = addr - wp) != 0) {
- data = 0;
- for (i = 0, cp = wp; i < l; ++i, ++cp) {
- data = (data << 8) | (*(uchar *) cp);
- }
- for (; i < port_width && cnt > 0; ++i) {
- data = (data << 8) | *src++;
- --cnt;
- ++cp;
- }
- for (; cnt == 0 && i < port_width; ++i, ++cp) {
- data = (data << 8) | (*(uchar *) cp);
- }
-
- if ((rc = write_data (info, wp, data)) != 0) {
- return (rc);
- }
- wp += port_width;
- }
-
- /*
- * handle word aligned part
- */
- count = 0;
- while (cnt >= port_width) {
- data = 0;
- for (i = 0; i < port_width; ++i) {
- data = (data << 8) | *src++;
- }
- if ((rc = write_data (info, wp, data)) != 0) {
- return (rc);
- }
- wp += port_width;
- cnt -= port_width;
- if (count++ > 0x800) {
- spin_wheel ();
- count = 0;
- }
- }
-
- if (cnt == 0) {
- return (0);
- }
-
- /*
- * handle unaligned tail bytes
- */
- data = 0;
- for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
- data = (data << 8) | *src++;
- --cnt;
- }
- for (; i < port_width; ++i, ++cp) {
- data = (data << 8) | (*(uchar *) cp);
- }
-
- return (write_data (info, wp, data));
-}
-
-/*-----------------------------------------------------------------------
- * Write a word or halfword to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_data (flash_info_t * info, ulong dest, unsigned char data)
-{
- volatile unsigned char *addr = (volatile unsigned char *) dest;
- ulong status;
- ulong start;
-
- /* Check if Flash is (sufficiently) erased */
- if ((*addr & data) != data) {
- printf ("not erased at %08lx (%lx)\n", (ulong) addr,
- (ulong) * addr);
- return (2);
- }
- /* Disable interrupts which might cause a timeout here */
- disable_interrupts();
-
- *addr = 0x40; /* write setup */
- *addr = data;
-
- /* arm simple, non interrupt dependent timer */
- start = get_timer(0);
-
- /* wait while polling the status register */
- while (((status = *addr) & 0x80) != 0x80) {
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- *addr = 0xFF; /* restore read mode */
- return (1);
- }
- }
-
- *addr = 0xFF; /* restore read mode */
-
- return (0);
-}
-
-void inline spin_wheel (void)
-{
- static int p = 0;
- static char w[] = "\\/-";
-
- printf ("\010%c", w[p]);
- (++p == 3) ? (p = 0) : 0;
-}
default "cm_t335"
config DM
- default y if !SPL_BUILD
+ default y
config DM_GPIO
- default y if !SPL_BUILD
+ default y
config DM_SERIAL
- default y if !SPL_BUILD
+ default y
endif
default "da850evm"
endif
-
-if TARGET_HAWKBOARD
-
-config SYS_BOARD
- default "da8xxevm"
-
-config SYS_VENDOR
- default "davinci"
-
-config SYS_CONFIG_NAME
- default "hawkboard"
-
-endif
F: configs/da850_am18xxevm_defconfig
F: configs/da850evm_defconfig
F: configs/da850evm_direct_nor_defconfig
-
-HAWKBOARD BOARD
-M: Syed Mohammed Khasim <sm.khasim@gmail.com>
-M: Sughosh Ganu <urwithsughosh@gmail.com>
-S: Maintained
-F: include/configs/hawkboard.h
-F: configs/hawkboard_defconfig
-F: configs/hawkboard_uart_defconfig
obj-$(CONFIG_MACH_DAVINCI_DA830_EVM) += da830evm.o
obj-$(CONFIG_MACH_DAVINCI_DA850_EVM) += da850evm.o
-obj-$(CONFIG_MACH_DAVINCI_HAWK) += hawkboard.o
+++ /dev/null
-Summary
-=======
-The README is for the boot procedure used for TI's OMAP-L138 based
-hawkboard. The hawkboard comes with a 128MiB Nand flash and a 128MiB
-DDR SDRAM along with a host of other controllers.
-
-The hawkboard is booted in three stages. The initial bootloader which
-executes upon reset is the Rom Boot Loader(RBL) which sits in the
-internal ROM of the omap. The RBL initialises the memory and the nand
-controller, and copies the image stored at a predefined location(block
-1) of the nand flash. The image loaded by the RBL to the memory is the
-AIS signed spl image. This, in turns copies the u-boot binary from the
-nand flash to the memory and jumps to the u-boot entry point.
-
-AIS is an image format defined by TI for the images that are to be
-loaded to memory by the RBL. The image is divided into a series of
-sections and the image's entry point is specified. Each section comes
-with meta data like the target address the section is to be copied to
-and the size of the section, which is used by the RBL to load the
-image. At the end of the image the RBL jumps to the image entry
-point.
-
-The secondary stage bootloader(spl) which is loaded by the RBL then
-loads the u-boot from a predefined location in the nand to the memory
-and jumps to the u-boot entry point.
-
-The reason a secondary stage bootloader is used is because the ECC
-layout expected by the RBL is not the same as that used by
-u-boot/linux. This also implies that for flashing the spl image,we
-need to use the u-boot which uses the ECC layout expected by the
-RBL[1]. Booting u-boot over UART(UART boot) is explained here[2].
-
-
-Compilation
-===========
-Three images might be needed
-
-* spl - This is the secondary bootloader which boots the u-boot
- binary.
-
-* u-boot binary - This is the image flashed to the nand and copied to
- the memory by the spl.
-
- Both the images get compiled with hawkboard_config, with the TOPDIR
- containing the u-boot images, and the spl image under the spl
- directory.
-
- The spl image needs to be processed with the AISGen tool for
- generating the AIS signed image to be flashed. Steps for generating
- the AIS image are explained here[3].
-
-* u-boot for uart boot - This is same as the u-boot binary generated
- above, with the sole difference of the CONFIG_SYS_TEXT_BASE being
- 0xc1080000, as expected by the RBL.
-
- hawkboard_uart_config
-
-
-Flashing the images to Nand
-===========================
-The spl AIS image needs to be flashed to the block 1 of the Nand
-flash, as that is the location the RBL expects the image[4]. For
-flashing the spl, boot over the u-boot specified in [1], and flash the
-image
-
-=> tftpboot 0xc0700000 <nand_spl_ais.bin>
-=> nand erase 0x20000 0x20000
-=> nand write.e 0xc0700000 0x20000 <nand_spl_size>
-
-The u-boot binary is flashed at location 0xe0000(block 6) of the nand
-flash. The spl loader expects the u-boot at this location. For
-flashing the u-boot binary
-
-=> tftpboot 0xc0700000 u-boot.bin
-=> nand erase 0xe0000 0x40000
-=> nand write.e 0xc0700000 0xe0000 <u-boot-size>
-
-
-Links
-=====
-
-[1]
- http://code.google.com/p/hawkboard/downloads/detail?name=u-boot_uart_ais_v1.bin
-
-[2]
- http://elinux.org/Hawkboard#Booting_u-boot_over_UART
-
-[3]
- http://elinux.org/Hawkboard#Signing_u-boot_for_UART_boot
-
-[4]
- http://processors.wiki.ti.com/index.php/RBL_UBL_and_host_program#RBL_booting_from_NAND_and_ECC.2FBad_blocks
+++ /dev/null
-# PLL0CFG0 PLL0CFG1
-PLL0 0x00180001 0x00000205
-# PLL1CFG0 PLL1CFG1 DRPYC1R SDCR SDTIMR1 SDTIMR2 SDRCR CLK2XSRC
-DDR2 0x15010001 0x00000002 0x00000043 0x00134632 0x26492a09 0x7d13c722 0x00000249 0x00000000
+++ /dev/null
-/*
- * Modified for Hawkboard - Syed Mohammed Khasim <khasim@beagleboard.org>
- *
- * Copyright (C) 2008 Sekhar Nori, Texas Instruments, Inc. <nsekhar@ti.com>
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- * Copyright (C) 2004 Texas Instruments.
- * Copyright (C) 2012 Sughosh Ganu <urwithsughosh@gmail.com>.
- *
- * ----------------------------------------------------------------------------
- * SPDX-License-Identifier: GPL-2.0+
- * ----------------------------------------------------------------------------
- */
-
-#include <common.h>
-#include <asm/errno.h>
-#include <asm/arch/hardware.h>
-#include <asm/io.h>
-#include <asm/arch/davinci_misc.h>
-#include <asm/arch/pinmux_defs.h>
-#include <asm/arch/da8xx-usb.h>
-#include <ns16550.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-const struct pinmux_resource pinmuxes[] = {
- PINMUX_ITEM(emac_pins_mii),
- PINMUX_ITEM(emac_pins_mdio),
- PINMUX_ITEM(emifa_pins_cs3),
- PINMUX_ITEM(emifa_pins_cs4),
- PINMUX_ITEM(emifa_pins_nand),
- PINMUX_ITEM(uart2_pins_txrx),
- PINMUX_ITEM(uart2_pins_rtscts),
-};
-
-const int pinmuxes_size = ARRAY_SIZE(pinmuxes);
-
-const struct lpsc_resource lpsc[] = {
- { DAVINCI_LPSC_AEMIF }, /* NAND, NOR */
- { DAVINCI_LPSC_SPI1 }, /* Serial Flash */
- { DAVINCI_LPSC_EMAC }, /* image download */
- { DAVINCI_LPSC_UART2 }, /* console */
- { DAVINCI_LPSC_GPIO },
-};
-
-const int lpsc_size = ARRAY_SIZE(lpsc);
-
-int board_init(void)
-{
- /* arch number of the board */
- gd->bd->bi_arch_number = MACH_TYPE_OMAPL138_HAWKBOARD;
-
- /* address of boot parameters */
- gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
-
- return 0;
-}
-
-int board_early_init_f(void)
-{
- /*
- * Kick Registers need to be set to allow access to Pin Mux registers
- */
- writel(DV_SYSCFG_KICK0_UNLOCK, &davinci_syscfg_regs->kick0);
- writel(DV_SYSCFG_KICK1_UNLOCK, &davinci_syscfg_regs->kick1);
-
- /* set cfgchip3 to select mii */
- writel(readl(&davinci_syscfg_regs->cfgchip3) &
- ~(1 << 8), &davinci_syscfg_regs->cfgchip3);
-
- return 0;
-}
-
-int misc_init_r(void)
-{
- char buf[32];
-
- printf("ARM Clock : %s MHz\n",
- strmhz(buf, clk_get(DAVINCI_ARM_CLKID)));
-
- return 0;
-}
-
-int usb_phy_on(void)
-{
- u32 timeout;
- u32 cfgchip2;
-
- cfgchip2 = readl(&davinci_syscfg_regs->cfgchip2);
-
- cfgchip2 &= ~(CFGCHIP2_RESET | CFGCHIP2_PHYPWRDN | CFGCHIP2_OTGPWRDN |
- CFGCHIP2_OTGMODE | CFGCHIP2_REFFREQ |
- CFGCHIP2_USB1PHYCLKMUX);
- cfgchip2 |= CFGCHIP2_SESENDEN | CFGCHIP2_VBDTCTEN | CFGCHIP2_PHY_PLLON |
- CFGCHIP2_REFFREQ_24MHZ | CFGCHIP2_USB2PHYCLKMUX |
- CFGCHIP2_USB1SUSPENDM;
-
- writel(cfgchip2, &davinci_syscfg_regs->cfgchip2);
-
- /* wait until the usb phy pll locks */
- timeout = DA8XX_USB_OTG_TIMEOUT;
- while (timeout--)
- if (readl(&davinci_syscfg_regs->cfgchip2) & CFGCHIP2_PHYCLKGD)
- return 1;
-
- /* USB phy was not turned on */
- return 0;
-}
-
-void usb_phy_off(void)
-{
- u32 cfgchip2;
-
- /*
- * Power down the on-chip PHY.
- */
- cfgchip2 = readl(&davinci_syscfg_regs->cfgchip2);
- cfgchip2 &= ~(CFGCHIP2_PHY_PLLON | CFGCHIP2_USB1SUSPENDM);
- cfgchip2 |= CFGCHIP2_PHYPWRDN | CFGCHIP2_OTGPWRDN | CFGCHIP2_RESET;
- writel(cfgchip2, &davinci_syscfg_regs->cfgchip2);
-}
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * (C) Copyright 2008
- * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
- . = 0xc1080000;
-
- . = ALIGN(4);
- .text :
- {
- *(.vectors)
- arch/arm/cpu/arm926ejs/start.o (.text*)
- arch/arm/cpu/arm926ejs/built-in.o (.text*)
- drivers/mtd/nand/built-in.o (.text*)
-
- *(.text*)
- }
-
- . = ALIGN(4);
- .rodata : { *(.rodata*) }
-
- . = ALIGN(4);
- .data : {
- *(.data)
- __datarel_start = .;
- *(.data.rel)
- __datarelrolocal_start = .;
- *(.data.rel.ro.local)
- __datarellocal_start = .;
- *(.data.rel.local)
- __datarelro_start = .;
- *(.data.rel.ro)
- }
-
- . = ALIGN(4);
- __image_copy_end = .;
- __rel_dyn_start = .;
- __rel_dyn_end = .;
-
- __got_start = .;
- . = ALIGN(4);
- .got : { *(.got) }
-
- __got_end = .;
-
- .bss :
- {
- . = ALIGN(4);
- __bss_start = .;
- *(.bss*)
- . = ALIGN(4);
- __bss_end = .;
- }
-
- .end :
- {
- *(.__end)
- }
-}
+++ /dev/null
-if TARGET_A320EVB
-
-config SYS_BOARD
- default "a320evb"
-
-config SYS_VENDOR
- default "faraday"
-
-config SYS_SOC
- default "a320"
-
-config SYS_CONFIG_NAME
- default "a320evb"
-
-endif
+++ /dev/null
-A320EVB BOARD
-M: Po-Yu Chuang <ratbert@faraday-tech.com>
-S: Maintained
-F: board/faraday/a320evb/
-F: include/configs/a320evb.h
-F: configs/a320evb_defconfig
+++ /dev/null
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := a320evb.o
-obj-y += lowlevel_init.o
+++ /dev/null
-/*
- * (C) Copyright 2009 Faraday Technology
- * Po-Yu Chuang <ratbert@faraday-tech.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <netdev.h>
-#include <asm/io.h>
-
-#include <faraday/ftsmc020.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * Miscellaneous platform dependent initialisations
- */
-
-int board_init(void)
-{
- gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
-
- ftsmc020_init(); /* initialize Flash */
- return 0;
-}
-
-int dram_init(void)
-{
- unsigned long sdram_base = PHYS_SDRAM_1;
- unsigned long expected_size = PHYS_SDRAM_1_SIZE;
- unsigned long actual_size;
-
- actual_size = get_ram_size((void *)sdram_base, expected_size);
-
- gd->ram_size = actual_size;
-
- if (expected_size != actual_size)
- printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
- actual_size >> 20, expected_size >> 20);
-
- return 0;
-}
-
-int board_eth_init(bd_t *bd)
-{
- return ftmac100_initialize(bd);
-}
-
-ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
-{
- if (banknum == 0) { /* non-CFI boot flash */
- info->portwidth = FLASH_CFI_8BIT;
- info->chipwidth = FLASH_CFI_BY8;
- info->interface = FLASH_CFI_X8;
- return 1;
- } else
- return 0;
-}
+++ /dev/null
-/*
- * (C) Copyright 2009 Faraday Technology
- * Po-Yu Chuang <ratbert@faraday-tech.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <config.h>
-#include <version.h>
-
-#include <asm/macro.h>
-#include <faraday/ftsdmc020.h>
-
-/*
- * parameters for the SDRAM controller
- */
-#define TP0_A (CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_TP0)
-#define TP1_A (CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_TP1)
-#define CR_A (CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_CR)
-#define B0_BSR_A (CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_BANK0_BSR)
-#define ACR_A (CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_ACR)
-
-#define TP0_D CONFIG_SYS_FTSDMC020_TP0
-#define TP1_D CONFIG_SYS_FTSDMC020_TP1
-#define CR_D1 FTSDMC020_CR_IPREC
-#define CR_D2 FTSDMC020_CR_ISMR
-#define CR_D3 FTSDMC020_CR_IREF
-
-#define B0_BSR_D (CONFIG_SYS_FTSDMC020_BANK0_BSR | \
- FTSDMC020_BANK_BASE(PHYS_SDRAM_1))
-#define ACR_D FTSDMC020_ACR_TOC(0x18)
-
-/*
- * numeric 7 segment display
- */
-.macro led, num
- write32 CONFIG_DEBUG_LED, \num
-.endm
-
-/*
- * Waiting for SDRAM to set up
- */
-.macro wait_sdram
- ldr r0, =CONFIG_FTSDMC020_BASE
-1:
- ldr r1, [r0, #FTSDMC020_OFFSET_CR]
- cmp r1, #0
- bne 1b
-.endm
-
-.globl lowlevel_init
-lowlevel_init:
- mov r11, lr
-
- led 0x0
-
- bl init_sdmc
-
- led 0x1
-
- /* everything is fine now */
- mov lr, r11
- mov pc, lr
-
-/*
- * memory initialization
- */
-init_sdmc:
- led 0x10
-
- /* set SDRAM register */
-
- write32 TP0_A, TP0_D
- led 0x11
-
- write32 TP1_A, TP1_D
- led 0x12
-
- /* set to precharge */
- write32 CR_A, CR_D1
- led 0x13
-
- wait_sdram
- led 0x14
-
- /* set mode register */
- write32 CR_A, CR_D2
- led 0x15
-
- wait_sdram
- led 0x16
-
- /* set to refresh */
- write32 CR_A, CR_D3
- led 0x17
-
- wait_sdram
- led 0x18
-
- write32 B0_BSR_A, B0_BSR_D
- led 0x19
-
- write32 ACR_A, ACR_D
- led 0x1a
-
- mov pc, lr
for (i = 0; i < num; i++)
out_be32(scfg + id[i].offset, id[i].stream_id);
}
+
+void ls1021x_config_caam_stream_id(struct liodn_id_table *tbl, int size)
+{
+ int i;
+ u32 liodn;
+
+ for (i = 0; i < size; i++) {
+ if (tbl[i].num_ids == 2)
+ liodn = (tbl[i].id[0] << 16) | tbl[i].id[1];
+ else
+ liodn = tbl[i].id[0];
+
+ out_le32((uint32_t *)(tbl[i].reg_offset), liodn);
+ }
+}
};
#endif
+struct liodn_id_table sec_liodn_tbl[] = {
+ SET_SEC_JR_LIODN_ENTRY(0, 0x10, 0x10),
+ SET_SEC_JR_LIODN_ENTRY(1, 0x10, 0x10),
+ SET_SEC_JR_LIODN_ENTRY(2, 0x10, 0x10),
+ SET_SEC_JR_LIODN_ENTRY(3, 0x10, 0x10),
+ SET_SEC_RTIC_LIODN_ENTRY(a, 0x10),
+ SET_SEC_RTIC_LIODN_ENTRY(b, 0x10),
+ SET_SEC_RTIC_LIODN_ENTRY(c, 0x10),
+ SET_SEC_RTIC_LIODN_ENTRY(d, 0x10),
+ SET_SEC_DECO_LIODN_ENTRY(0, 0x10, 0x10),
+ SET_SEC_DECO_LIODN_ENTRY(1, 0x10, 0x10),
+ SET_SEC_DECO_LIODN_ENTRY(2, 0x10, 0x10),
+ SET_SEC_DECO_LIODN_ENTRY(3, 0x10, 0x10),
+ SET_SEC_DECO_LIODN_ENTRY(4, 0x10, 0x10),
+ SET_SEC_DECO_LIODN_ENTRY(5, 0x10, 0x10),
+ SET_SEC_DECO_LIODN_ENTRY(6, 0x10, 0x10),
+ SET_SEC_DECO_LIODN_ENTRY(7, 0x10, 0x10),
+};
+
struct smmu_stream_id dev_stream_id[] = {
{ 0x100, 0x01, "ETSEC MAC1" },
{ 0x104, 0x02, "ETSEC MAC2" },
config_serdes_mux();
#endif
+ ls1021x_config_caam_stream_id(sec_liodn_tbl,
+ ARRAY_SIZE(sec_liodn_tbl));
ls102xa_config_smmu_stream_id(dev_stream_id,
ARRAY_SIZE(dev_stream_id));
};
#endif
+struct liodn_id_table sec_liodn_tbl[] = {
+ SET_SEC_JR_LIODN_ENTRY(0, 0x10, 0x10),
+ SET_SEC_JR_LIODN_ENTRY(1, 0x10, 0x10),
+ SET_SEC_JR_LIODN_ENTRY(2, 0x10, 0x10),
+ SET_SEC_JR_LIODN_ENTRY(3, 0x10, 0x10),
+ SET_SEC_RTIC_LIODN_ENTRY(a, 0x10),
+ SET_SEC_RTIC_LIODN_ENTRY(b, 0x10),
+ SET_SEC_RTIC_LIODN_ENTRY(c, 0x10),
+ SET_SEC_RTIC_LIODN_ENTRY(d, 0x10),
+ SET_SEC_DECO_LIODN_ENTRY(0, 0x10, 0x10),
+ SET_SEC_DECO_LIODN_ENTRY(1, 0x10, 0x10),
+ SET_SEC_DECO_LIODN_ENTRY(2, 0x10, 0x10),
+ SET_SEC_DECO_LIODN_ENTRY(3, 0x10, 0x10),
+ SET_SEC_DECO_LIODN_ENTRY(4, 0x10, 0x10),
+ SET_SEC_DECO_LIODN_ENTRY(5, 0x10, 0x10),
+ SET_SEC_DECO_LIODN_ENTRY(6, 0x10, 0x10),
+ SET_SEC_DECO_LIODN_ENTRY(7, 0x10, 0x10),
+};
+
struct smmu_stream_id dev_stream_id[] = {
{ 0x100, 0x01, "ETSEC MAC1" },
{ 0x104, 0x02, "ETSEC MAC2" },
#endif
#endif
+ ls1021x_config_caam_stream_id(sec_liodn_tbl,
+ ARRAY_SIZE(sec_liodn_tbl));
ls102xa_config_smmu_stream_id(dev_stream_id,
ARRAY_SIZE(dev_stream_id));
popts->data_bus_width = 1;
popts->otf_burst_chop_en = 0;
popts->burst_length = DDR_BL8;
+ popts->bstopre = 0; /* enable auto precharge */
}
/*
* Factors to consider for half-strength driver enable:
#include <asm/io.h>
#include <fdt_support.h>
#include <libfdt.h>
-#include <fsl_mc.h>
+#include <fsl-mc/fsl_mc.h>
#include <environment.h>
DECLARE_GLOBAL_DATA_PTR;
u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR;
u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR;
- out_le32(cltbenr, 0x1); /* enable cluster0 timebase */
- out_le32(cntcr, 0x1); /* enable clock for timer */
+ /* Enable timebase for all clusters.
+ * It is safe to do so even some clusters are not enabled.
+ */
+ out_le32(cltbenr, 0xf);
+
+ /* Enable clock for timer
+ * This is a global setting.
+ */
+ out_le32(cntcr, 0x1);
return 0;
}
{
int offset;
- offset = fdt_path_offset(fdt, "/fsl,dprc@0");
+ offset = fdt_path_offset(fdt, "/fsl-mc");
+
+ /*
+ * TODO: Remove this when backward compatibility
+ * with old DT node (fsl,dprc@0) is no longer needed.
+ */
+ if (offset < 0)
+ offset = fdt_path_offset(fdt, "/fsl,dprc@0");
+
+ if (offset < 0) {
+ printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
+ __func__, offset);
+ return;
+ }
+
if (get_mc_boot_status() == 0)
fdt_status_okay(fdt, offset);
else
default "pepper"
config DM
- default y if !SPL_BUILD
+ default y
config DM_GPIO
- default y if !SPL_BUILD
+ default y
config DM_SERIAL
- default y if !SPL_BUILD
+ default y
endif
default "am335x_igep0033"
config DM
- default y if !SPL_BUILD
+ default y
config DM_GPIO
- default y if !SPL_BUILD
+ default y
config DM_SERIAL
- default y if !SPL_BUILD
+ default y
endif
default "pcm051"
config DM
- default y if !SPL_BUILD
+ default y
config DM_GPIO
- default y if !SPL_BUILD
+ default y
config DM_SERIAL
- default y if !SPL_BUILD
+ default y
endif
default "s5p_goni"
config DM
- default y if !SPL_BUILD
+ default y
config DM_GPIO
- default y if !SPL_BUILD
+ default y
config DM_SERIAL
- default y if !SPL_BUILD
+ default y
endif
default "smdkc100"
config DM
- default y if !SPL_BUILD
+ default y
config DM_GPIO
- default y if !SPL_BUILD
+ default y
config DM_SERIAL
- default y if !SPL_BUILD
+ default y
endif
default "pengwyn"
config DM
- default y if !SPL_BUILD
+ default y
config DM_GPIO
- default y if !SPL_BUILD
+ default y
config DM_SERIAL
- default y if !SPL_BUILD
+ default y
endif
+++ /dev/null
-if TARGET_JADECPU
-
-config SYS_BOARD
- default "jadecpu"
-
-config SYS_VENDOR
- default "syteco"
-
-config SYS_SOC
- default "mb86r0x"
-
-config SYS_CONFIG_NAME
- default "jadecpu"
-
-endif
+++ /dev/null
-JADECPU BOARD
-M: Matthias Weisser <weisserm@arcor.de>
-S: Maintained
-F: board/syteco/jadecpu/
-F: include/configs/jadecpu.h
-F: configs/jadecpu_defconfig
+++ /dev/null
-#
-# (C) Copyright 2003-2008
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2008
-# Stelian Pop <stelian@popies.net>
-# Lead Tech Design <www.leadtechdesign.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += jadecpu.o
-obj-y += lowlevel_init.o
+++ /dev/null
-/*
- * (c) 2010 Graf-Syteco, Matthias Weisser
- * <weisserm@arcor.de>
- *
- * (C) Copyright 2007, mycable GmbH
- * Carsten Schneider <cs@mycable.de>, Alexander Bigga <ab@mycable.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <netdev.h>
-#include <asm/io.h>
-#include <asm/arch/mb86r0x.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * Miscellaneous platform dependent initialisations
- */
-int board_init(void)
-{
- struct mb86r0x_ccnt * ccnt = (struct mb86r0x_ccnt *)
- MB86R0x_CCNT_BASE;
-
- /* We select mode 0 for group 2 and mode 1 for group 4 */
- writel(0x00000010, &ccnt->cmux_md);
-
- gd->flags = 0;
- gd->bd->bi_boot_params = PHYS_SDRAM + PHYS_SDRAM_SIZE - 0x10000;
-
- icache_enable();
- dcache_enable();
-
- return 0;
-}
-
-static void setup_display_power(uint32_t pwr_bit, char *pwm_opts,
- unsigned long pwm_base)
-{
- struct mb86r0x_gpio *gpio = (struct mb86r0x_gpio *)
- MB86R0x_GPIO_BASE;
- struct mb86r0x_pwm *pwm = (struct mb86r0x_pwm *) pwm_base;
- const char *e;
-
- writel(readl(&gpio->gpdr2) | pwr_bit, &gpio->gpdr2);
-
- e = getenv(pwm_opts);
- if (e != NULL) {
- const char *s;
- uint32_t freq, init;
-
- freq = 0;
- init = 0;
-
- s = strchr(e, 'f');
- if (s != NULL)
- freq = simple_strtol(s + 2, NULL, 0);
-
- s = strchr(e, 'i');
- if (s != NULL)
- init = simple_strtol(s + 2, NULL, 0);
-
- if (freq > 0) {
- writel(CONFIG_MB86R0x_IOCLK / 1000 / freq,
- &pwm->bcr);
- writel(1002, &pwm->tpr);
- writel(1, &pwm->pr);
- writel(init * 10 + 1, &pwm->dr);
- writel(1, &pwm->cr);
- writel(1, &pwm->sr);
- }
- }
-}
-
-int board_late_init(void)
-{
- struct mb86r0x_gpio *gpio = (struct mb86r0x_gpio *)
- MB86R0x_GPIO_BASE;
- uint32_t in_word;
-
-#ifdef CONFIG_VIDEO_MB86R0xGDC
- /* Check if we have valid display settings and turn on power if so */
- /* Display 0 */
- if (getenv("gs_dsp_0_param") || getenv("videomode"))
- setup_display_power((1 << 3), "gs_dsp_0_pwm",
- MB86R0x_PWM0_BASE);
-
- /* The corresponding GPIO is always an output */
- writel(readl(&gpio->gpddr2) | (1 << 3), &gpio->gpddr2);
-
- /* Display 1 */
- if (getenv("gs_dsp_1_param") || getenv("videomode1"))
- setup_display_power((1 << 4), "gs_dsp_1_pwm",
- MB86R0x_PWM1_BASE);
-
- /* The corresponding GPIO is always an output */
- writel(readl(&gpio->gpddr2) | (1 << 4), &gpio->gpddr2);
-#endif /* CONFIG_VIDEO_MB86R0xGDC */
-
- /* 5V enable */
- writel(readl(&gpio->gpdr1) & ~(1 << 5), &gpio->gpdr1);
- writel(readl(&gpio->gpddr1) | (1 << 5), &gpio->gpddr1);
-
- /* We have special boot options if told by GPIOs */
- in_word = readl(&gpio->gpdr1);
-
- if ((in_word & 0xC0) == 0xC0) {
- setenv("stdin", "serial");
- setenv("stdout", "serial");
- setenv("stderr", "serial");
- setenv("preboot", "run gs_slow_boot");
- } else if ((in_word & 0xC0) != 0) {
- setenv("stdout", "vga");
- setenv("preboot", "run gs_slow_boot");
- } else {
- setenv("stdin", "serial");
- setenv("stdout", "serial");
- setenv("stderr", "serial");
- if (getenv("gs_devel")) {
- setenv("preboot", "run gs_slow_boot");
- } else {
- setenv("preboot", "run gs_fast_boot");
- }
- }
-
- return 0;
-}
-
-int misc_init_r(void)
-{
- return 0;
-}
-
-/*
- * DRAM configuration
- */
-int dram_init(void)
-{
- /* dram_init must store complete ramsize in gd->ram_size */
- gd->ram_size = get_ram_size((void *)PHYS_SDRAM,
- PHYS_SDRAM_SIZE);
-
- return 0;
-}
-
-void dram_init_banksize(void)
-{
- gd->bd->bi_dram[0].start = PHYS_SDRAM;
- gd->bd->bi_dram[0].size = gd->ram_size;
-}
-
-int board_eth_init(bd_t *bis)
-{
- int rc = 0;
-#ifdef CONFIG_SMC911X
- rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
-#endif
- return rc;
-}
+++ /dev/null
-/*
- * Board specific setup info
- *
- * (C) Copyright 2007, mycable GmbH
- * Carsten Schneider <cs@mycable.de>, Alexander Bigga <ab@mycable.de>
- *
- * (C) Copyright 2003, ARM Ltd.
- * Philippe Robin, <philippe.robin@arm.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/macro.h>
-#include <asm/arch/mb86r0x.h>
-#include <generated/asm-offsets.h>
-
-/* Set up the platform, once the cpu has been initialized */
-.globl lowlevel_init
-lowlevel_init:
-/*
- * Initialize Clock Reset Generator (CRG)
- */
-
- ldr r0, =MB86R0x_CRG_BASE
-
- /* Not change the initial value that is set by external pin.*/
-WAIT_PLL:
- ldr r2, [r0, #CRG_CRPR] /* Wait for PLLREADY */
- tst r2, #MB86R0x_CRG_CRPR_PLLRDY
- beq WAIT_PLL
-
- /* Set clock gate control */
- ldr r1, =CONFIG_SYS_CRG_CRHA_INIT
- str r1, [r0, #CRG_CRHA]
- ldr r1, =CONFIG_SYS_CRG_CRPA_INIT
- str r1, [r0, #CRG_CRPA]
- ldr r1, =CONFIG_SYS_CRG_CRPB_INIT
- str r1, [r0, #CRG_CRPB]
- ldr r1, =CONFIG_SYS_CRG_CRHB_INIT
- str r1, [r0, #CRG_CRHB]
- ldr r1, =CONFIG_SYS_CRG_CRAM_INIT
- str r1, [r0, #CRG_CRAM]
-
-/*
- * Initialize External Bus Interface
- */
- ldr r0, =MB86R0x_MEMC_BASE
-
- ldr r1, =CONFIG_SYS_MEMC_MCFMODE0_INIT
- str r1, [r0, #MEMC_MCFMODE0]
- ldr r1, =CONFIG_SYS_MEMC_MCFMODE2_INIT
- str r1, [r0, #MEMC_MCFMODE2]
- ldr r1, =CONFIG_SYS_MEMC_MCFMODE4_INIT
- str r1, [r0, #MEMC_MCFMODE4]
-
- ldr r1, =CONFIG_SYS_MEMC_MCFTIM0_INIT
- str r1, [r0, #MEMC_MCFTIM0]
- ldr r1, =CONFIG_SYS_MEMC_MCFTIM2_INIT
- str r1, [r0, #MEMC_MCFTIM2]
- ldr r1, =CONFIG_SYS_MEMC_MCFTIM4_INIT
- str r1, [r0, #MEMC_MCFTIM4]
-
- ldr r1, =CONFIG_SYS_MEMC_MCFAREA0_INIT
- str r1, [r0, #MEMC_MCFAREA0]
- ldr r1, =CONFIG_SYS_MEMC_MCFAREA2_INIT
- str r1, [r0, #MEMC_MCFAREA2]
- ldr r1, =CONFIG_SYS_MEMC_MCFAREA4_INIT
- str r1, [r0, #MEMC_MCFAREA4]
-
-/*
- * Initialize DDR2 Controller
- */
-
- /* Wait for PLL LOCK up time or more */
- wait_timer 20
-
- /*
- * (2) Initialize DDRIF
- */
- ldr r0, =MB86R0x_DDR2_BASE
- ldr r1, =CONFIG_SYS_DDR2_DRIMS_INIT
- strh r1, [r0, #DDR2_DRIMS]
-
- /*
- * (3) Wait for 20MCKPs(120nsec) or more
- */
- wait_timer 20
-
- /*
- * (4) IRESET/IUSRRST release
- */
- ldr r0, =MB86R0x_CCNT_BASE
- ldr r1, =CONFIG_SYS_CCNT_CDCRC_INIT_1
- str r1, [r0, #CCNT_CDCRC]
-
- /*
- * (5) Wait for 20MCKPs(120nsec) or more
- */
- wait_timer 20
-
- /*
- * (6) IDLLRST release
- */
- ldr r0, =MB86R0x_CCNT_BASE
- ldr r1, =CONFIG_SYS_CCNT_CDCRC_INIT_2
- str r1, [r0, #CCNT_CDCRC]
-
- /*
- * (7+8) Wait for 200us(=200000ns) or more (DDR2 Spec)
- */
- wait_timer 33536
-
- /*
- * (9) MCKE ON
- */
- ldr r0, =MB86R0x_DDR2_BASE
- ldr r1, =CONFIG_SYS_DDR2_DRIC1_INIT
- strh r1, [r0, #DDR2_DRIC1]
- ldr r1, =CONFIG_SYS_DDR2_DRIC2_INIT
- strh r1, [r0, #DDR2_DRIC2]
- ldr r1, =CONFIG_SYS_DDR2_DRCA_INIT
- strh r1, [r0, #DDR2_DRCA]
- ldr r1, =MB86R0x_DDR2_DRCI_INIT
- strh r1, [r0, #DDR2_DRIC]
-
- /*
- * (10) Initialize SDRAM
- */
-
- ldr r1, =MB86R0x_DDR2_DRCI_CMD
- strh r1, [r0, #DDR2_DRIC]
-
- wait_timer 67 /* 400ns wait */
-
- ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_1
- strh r1, [r0, #DDR2_DRIC1]
- ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_1
- strh r1, [r0, #DDR2_DRIC2]
- ldr r1, =MB86R0x_DDR2_DRCI_CMD
- strh r1, [r0, #DDR2_DRIC]
-
- ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_2
- strh r1, [r0, #DDR2_DRIC1]
- ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_2
- strh r1, [r0, #DDR2_DRIC2]
- ldr r1, =MB86R0x_DDR2_DRCI_CMD
- strh r1, [r0, #DDR2_DRIC]
-
- ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_3
- strh r1, [r0, #DDR2_DRIC1]
- ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_3
- strh r1, [r0, #DDR2_DRIC2]
- ldr r1, =MB86R0x_DDR2_DRCI_CMD
- strh r1, [r0, #DDR2_DRIC]
-
- ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_4
- strh r1, [r0, #DDR2_DRIC1]
- ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_4
- strh r1, [r0, #DDR2_DRIC2]
- ldr r1, =MB86R0x_DDR2_DRCI_CMD
- strh r1, [r0, #DDR2_DRIC]
-
- ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_5
- strh r1, [r0, #DDR2_DRIC1]
- ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_5
- strh r1, [r0, #DDR2_DRIC2]
- ldr r1, =MB86R0x_DDR2_DRCI_CMD
- strh r1, [r0, #DDR2_DRIC]
-
- wait_timer 200
-
- ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_6
- strh r1, [r0, #DDR2_DRIC1]
- ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_6
- strh r1, [r0, #DDR2_DRIC2]
- ldr r1, =MB86R0x_DDR2_DRCI_CMD
- strh r1, [r0, #DDR2_DRIC]
-
- ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_7
- strh r1, [r0, #DDR2_DRIC1]
- ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_7
- strh r1, [r0, #DDR2_DRIC2]
- ldr r1, =MB86R0x_DDR2_DRCI_CMD
- strh r1, [r0, #DDR2_DRIC]
-
- wait_timer 18 /* 105ns wait */
-
- ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_8
- strh r1, [r0, #DDR2_DRIC1]
- ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_8
- strh r1, [r0, #DDR2_DRIC2]
- ldr r1, =MB86R0x_DDR2_DRCI_CMD
- strh r1, [r0, #DDR2_DRIC]
-
- wait_timer 200 /* MRS to OCD: 200clock */
-
- ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_9
- strh r1, [r0, #DDR2_DRIC1]
- ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_9
- strh r1, [r0, #DDR2_DRIC2]
- ldr r1, =MB86R0x_DDR2_DRCI_CMD
- strh r1, [r0, #DDR2_DRIC]
-
- ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_10
- strh r1, [r0, #DDR2_DRIC1]
- ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_10
- strh r1, [r0, #DDR2_DRIC2]
- ldr r1, =MB86R0x_DDR2_DRCI_CMD
- strh r1, [r0, #DDR2_DRIC]
-
- ldr r1, =CONFIG_SYS_DDR2_DRCM_INIT
- strh r1, [r0, #DDR2_DRCM]
-
- ldr r1, =CONFIG_SYS_DDR2_DRCST1_INIT
- strh r1, [r0, #DDR2_DRCST1]
-
- ldr r1, =CONFIG_SYS_DDR2_DRCST2_INIT
- strh r1, [r0, #DDR2_DRCST2]
-
- ldr r1, =CONFIG_SYS_DDR2_DRCR_INIT
- strh r1, [r0, #DDR2_DRCR]
-
- ldr r1, =CONFIG_SYS_DDR2_DRCF_INIT
- strh r1, [r0, #DDR2_DRCF]
-
- ldr r1, =CONFIG_SYS_DDR2_DRASR_INIT
- strh r1, [r0, #DDR2_DRASR]
-
- /*
- * (11) ODT setting
- */
- ldr r1, =CONFIG_SYS_DDR2_DROBS_INIT
- strh r1, [r0, #DDR2_DROBS]
- ldr r1, =CONFIG_SYS_DDR2_DROABA_INIT
- strh r1, [r0, #DDR2_DROABA]
- ldr r1, =CONFIG_SYS_DDR2_DRIBSODT1_INIT
- strh r1, [r0, #DDR2_DRIBSODT1]
-
- /*
- * (12) Shift to ODTCONT ON (SDRAM side) and DDR2 usual operation mode
- */
- ldr r1, =CONFIG_SYS_DDR2_DROS_INIT
- strh r1, [r0, #DDR2_DROS]
- ldr r1, =MB86R0x_DDR2_DRCI_NORMAL
- strh r1, [r0, #DDR2_DRIC]
-
- mov pc, lr
NOR for environment.
config DM
- default y if !SPL_BUILD
+ default y
config DM_GPIO
- default y if DM && !SPL_BUILD
+ default y if DM
config DM_SERIAL
- default y if DM && !SPL_BUILD
+ default y if DM
config SYS_MALLOC_F
- default y if DM && !SPL_BUILD
+ default y if DM
config SYS_MALLOC_F_LEN
- default 0x400 if DM && !SPL_BUILD
+ default 0x400 if DM
endif
+++ /dev/null
-if TARGET_TNETV107X_EVM
-
-config SYS_BOARD
- default "tnetv107xevm"
-
-config SYS_VENDOR
- default "ti"
-
-config SYS_SOC
- default "tnetv107x"
-
-config SYS_CONFIG_NAME
- default "tnetv107x_evm"
-
-endif
+++ /dev/null
-TNETV107XEVM BOARD
-#M: Chan-Taek Park <c-park@ti.com>
-S: Orphan (since 2014-06)
-F: board/ti/tnetv107xevm/
-F: include/configs/tnetv107x_evm.h
-F: configs/tnetv107x_evm_defconfig
+++ /dev/null
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += sdb_board.o
+++ /dev/null
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-CONFIG_SYS_TEXT_BASE = 0x83FC0000
+++ /dev/null
-/*
- * TNETV107X-EVM: Board initialization
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <miiphy.h>
-#include <linux/mtd/nand.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/clock.h>
-#include <asm/io.h>
-#include <asm/mach-types.h>
-#include <asm/ti-common/davinci_nand.h>
-#include <asm/arch/mux.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static struct async_emif_config async_emif_config[ASYNC_EMIF_NUM_CS] = {
- { /* CS0 */
- .mode = ASYNC_EMIF_MODE_NAND,
- .wr_setup = 5,
- .wr_strobe = 5,
- .wr_hold = 2,
- .rd_setup = 5,
- .rd_strobe = 5,
- .rd_hold = 2,
- .turn_around = 5,
- .width = ASYNC_EMIF_8,
- },
- { /* CS1 */
- .mode = ASYNC_EMIF_MODE_NOR,
- .wr_setup = 2,
- .wr_strobe = 27,
- .wr_hold = 4,
- .rd_setup = 2,
- .rd_strobe = 27,
- .rd_hold = 4,
- .turn_around = 2,
- .width = ASYNC_EMIF_PRESERVE,
- },
- { /* CS2 */
- .mode = ASYNC_EMIF_MODE_NOR,
- .wr_setup = 2,
- .wr_strobe = 27,
- .wr_hold = 4,
- .rd_setup = 2,
- .rd_strobe = 27,
- .rd_hold = 4,
- .turn_around = 2,
- .width = ASYNC_EMIF_PRESERVE,
- },
- { /* CS3 */
- .mode = ASYNC_EMIF_MODE_NOR,
- .wr_setup = 1,
- .wr_strobe = 90,
- .wr_hold = 3,
- .rd_setup = 1,
- .rd_strobe = 26,
- .rd_hold = 3,
- .turn_around = 1,
- .width = ASYNC_EMIF_8,
- },
-};
-
-static struct pll_init_data pll_config[] = {
- {
- .pll = ETH_PLL,
- .internal_osc = 1,
- .pll_freq = 500000000,
- .div_freq = {
- 5000000, 50000000, 125000000, 250000000, 25000000,
- },
- },
-};
-
-static const short sdio1_pins[] = {
- TNETV107X_PIN_SDIO1_CLK_1, TNETV107X_PIN_SDIO1_CMD_1,
- TNETV107X_PIN_SDIO1_DATA0_1, TNETV107X_PIN_SDIO1_DATA1_1,
- TNETV107X_PIN_SDIO1_DATA2_1, TNETV107X_PIN_SDIO1_DATA3_1,
- -1
-};
-
-static const short uart1_pins[] = {
- TNETV107X_PIN_UART1_RD, TNETV107X_PIN_UART1_TD, -1
-};
-
-static const short ssp_pins[] = {
- TNETV107X_PIN_SSP0_0, TNETV107X_PIN_SSP0_1, TNETV107X_PIN_SSP0_2,
- TNETV107X_PIN_SSP1_0, TNETV107X_PIN_SSP1_1, TNETV107X_PIN_SSP1_2,
- TNETV107X_PIN_SSP1_3, -1
-};
-
-int board_init(void)
-{
-#ifndef CONFIG_USE_IRQ
- __raw_writel(0, INTC_GLB_EN); /* Global disable */
- __raw_writel(0, INTC_HINT_EN); /* Disable host ints */
- __raw_writel(0, INTC_EN_CLR0 + 0); /* Clear enable */
- __raw_writel(0, INTC_EN_CLR0 + 4); /* Clear enable */
- __raw_writel(0, INTC_EN_CLR0 + 8); /* Clear enable */
-#endif
-
- gd->bd->bi_arch_number = MACH_TYPE_TNETV107X;
- gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
-
- init_plls(ARRAY_SIZE(pll_config), pll_config);
-
- init_async_emif(ARRAY_SIZE(async_emif_config), async_emif_config);
-
- mux_select_pin(TNETV107X_PIN_ASR_CS3);
- mux_select_pins(sdio1_pins);
- mux_select_pins(uart1_pins);
- mux_select_pins(ssp_pins);
-
- return 0;
-}
-
-int dram_init(void)
-{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-
- return 0;
-}
-
-#ifdef CONFIG_NAND_DAVINCI
-int board_nand_init(struct nand_chip *nand)
-{
- davinci_nand_init(nand);
-
- return 0;
-}
-#endif
menu "Command line interface"
- depends on !SPL_BUILD
config HUSH_PARSER
bool "Use hush shell"
"enc src dst len km - Encapsulate and create blob of data\n"
" $len bytes long at address $src and\n"
" store the result at address $dst.\n"
- " $km is the 16 byte key modifier\n"
- " is also required for generation/use as\n"
- " key for cryptographic operation. Key\n"
- " modifier should be 16 byte long.\n"
+ " $km is the address where the key\n"
+ " modifier is stored.\n"
+ " The modifier is required for generation\n"
+ " /use as key for cryptographic operation.\n"
+ " Key modifier should be 16 byte long.\n"
"blob dec src dst len km - Decapsulate the blob of data at address\n"
" $src and store result of $len byte at\n"
" addr $dst.\n"
- " $km is the 16 byte key modifier\n"
- " is also required for generation/use as\n"
- " key for cryptographic operation. Key\n"
- " modifier should be 16 byte long.\n";
+ " $km is the address where the key\n"
+ " modifier is stored.\n"
+ " The modifier is required for generation\n"
+ " /use as key for cryptographic operation.\n"
+ " Key modifier should be 16 byte long.\n";
U_BOOT_CMD(
blob, 6, 1, do_blob,
SHA1_SUM_LEN,
hw_sha1,
CHUNKSZ_SHA1,
+#ifdef CONFIG_SHA_PROG_HW_ACCEL
+ hw_sha_init,
+ hw_sha_update,
+ hw_sha_finish,
+#endif
}, {
"sha256",
SHA256_SUM_LEN,
hw_sha256,
CHUNKSZ_SHA256,
+#ifdef CONFIG_SHA_PROG_HW_ACCEL
+ hw_sha_init,
+ hw_sha_update,
+ hw_sha_finish,
+#endif
},
#endif
#ifdef CONFIG_SHA1
ARCH := $(CONFIG_SYS_ARCH:"%"=%)
CPU := $(CONFIG_SYS_CPU:"%"=%)
+ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_TEGRA
+CPU := arm720t
+endif
+endif
BOARD := $(CONFIG_SYS_BOARD:"%"=%)
ifneq ($(CONFIG_SYS_VENDOR),)
VENDOR := $(CONFIG_SYS_VENDOR:"%"=%)
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_TARGET_A320EVB=y
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_TARGET_CM4008=y
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_TARGET_CM41XX=y
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_TARGET_DKB=y
+++ /dev/null
-CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_DAVINCI=y
-+S:CONFIG_TARGET_HAWKBOARD=y
+++ /dev/null
-CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="UART_U_BOOT"
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_DAVINCI=y
-+S:CONFIG_TARGET_HAWKBOARD=y
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_TARGET_JADECPU=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
-S:CONFIG_SPL_NAND_DENALI=y
+CONFIG_SPL_NAND_DENALI=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
-S:CONFIG_SPL_NAND_DENALI=y
+CONFIG_SPL_NAND_DENALI=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
-S:CONFIG_SPL_NAND_DENALI=y
+CONFIG_SPL_NAND_DENALI=y
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_TARGET_TNETV107X_EVM=y
--- /dev/null
+Freescale ARM64 SoCs like LS2085A have ARM TrustZone components like
+TZPC-BP147 (TrustZone Protection Controller) and TZASC-400 (TrustZone
+Address Space Controller).
+
+While most of the configuration related programming of these peripherals
+is left to a root-of-trust security software layer (running in EL3
+privilege mode), but still some configurations of these peripherals
+might be required while the bootloader is executing in EL3 privilege
+mode. The following sections define how to turn on these features for
+LS2085A like SoCs.
+
+TZPC-BP147 (TrustZone Protection Controller)
+============================================
+- Depends on CONFIG_FSL_TZPC_BP147 configuration flag.
+- Separates Secure World and Normal World on-chip RAM (OCRAM) spaces.
+- Provides a programming model to set access control policy via the TZPC
+ TZDECPROT Registers.
+
+TZASC-400 (TrustZone Address Space Controller)
+==============================================
+- Depends on CONFIG_FSL_TZASC_400 configuration flag.
+- Separates Secure World and Normal World external memory spaces for bus masters
+ such as processors and DMA-equipped peripherals.
+- Supports 8 fully programmable address regions, initially inactive at reset,
+ and one base region, always active, that covers the remaining address space.
Difference from Linux's Kconfig
-------------------------------
-The biggest difference between Linux Kernel and U-Boot in terms of the
-configuration is that U-Boot has to configure multiple boot images per board:
-Normal, SPL, TPL.
-Kconfig functions need to be expanded for U-Boot to handle multiple images.
-The files scripts/kconfig/* were imported from Linux Kernel and adjusted
-for that purpose.
+Here are some worth-mentioning configuration targets.
-See below for how each configuration target works in U-Boot:
+- silentoldconfig
-- config, nconfig, menuconfig, xconfig, gconfig
+ This target updates .config, include/generated/autoconf.h and
+ include/configs/* as in Linux. In U-Boot, it also does the followings
+ for the compatibility with the old configuration system:
- These targets are used to configure Normal and create (or modify) the
- .config file. For SPL configuration, the configutation targets are prefixed
- with "spl/", for example "make spl/config", "make spl/menuconfig", etc.
- Those targets create or modify the spl/.config file. Likewise, run
- "make tpl/config", "make tpl/menuconfig", etc. for TPL.
+ * create a symbolic link "arch/${ARCH}/include/asm/arch" pointing to
+ the SoC/CPU specific header directory
+ * create include/config.h
+ * create include/autoconf.mk
+ * create spl/include/autoconf.mk (SPL and TPL only)
+ * create tpl/include/autoconf.mk (TPL only)
-- silentoldconfig
+ If we could completely switch to Kconfig in a long run
+ (i.e. remove all the include/configs/*.h), those additional processings
+ above would be removed.
- This target updates .config, include/generated/autoconf.h and
- include/configs/*. In U-Boot, the same thing is done for SPL, TPL,
- if supported by the target board. Depending on whether CONFIG_SPL and
- CONFIG_TPL are defined, "make silentoldconfig" iterates three times at most
- changing the work directory.
-
- To sum up, "make silentoldconfig" possibly updates:
- - .config, include/generated/autoconf.h, include/config/*
- - spl/.config, spl/include/generated/autoconf.h, spl/include/config/*
- (in case CONFIG_SPL=y)
- - tpl/.config, tpl/include/generated/autoconf.h, tpl/include/config/*
- (in case CONFIG_TPL=y)
-
-- defconfig, <board>_defconfig
-
- The target "<board>_defconfig" is used to create the .config based on the
- file configs/<board>_defconfig. The "defconfig" target is the same
- except it checks for a file specified with KBUILD_DEFCONFIG environment.
-
- Note:
- The defconfig files are placed under the "configs" directory,
- not "arch/$(ARCH)/configs". This is because "ARCH" is not necessarily
- given from the command line for the U-Boot configuration and build.
-
- The defconfig file format in U-Boot has the special syntax; each line has
- "<condition>:" prefix to show which image(s) the line is valid for.
- For example,
-
- CONFIG_FOO=100
- S:CONFIG_FOO=200
- T:CONFIG_FOO=300
- ST:CONFIG_BAR=y
- +S:CONFIG_BAZ=y
- +T:CONFIG_QUX=y
- +ST:CONFIG_QUUX=y
-
- Here, the "<condition>:" prefix is one of:
- None - the line is valid only for Normal image
- S: - the line is valid only for SPL image
- T: - the line is valid only for TPL image
- ST: - the line is valid for SPL and TPL images
- +S: - the line is valid for Normal and SPL images
- +T: - the line is valid for Normal and TPL images
- +ST: - the line is valid for Normal, SPL and TPL images
-
- So, if neither CONFIG_SPL nor CONFIG_TPL is defined, the defconfig file
- has no "<condition>:" part and therefore has the same form as in Linux.
- From the example defconfig shown above, three separete configuration sets
- are generated and used for creating .config, spl/.config and tpl/.config.
-
- - Input for the default configuration of Normal
- CONFIG_FOO=100
- CONFIG_BAZ=y
- CONFIG_QUX=y
- CONFIG_QUUX=y
-
- - Input for the default configuration of SPL
- CONFIG_FOO=200
- CONFIG_BAR=y
- CONFIG_BAZ=y
- CONFIG_QUUX=y
-
- - Input for the default configuration of TPL
- CONFIG_FOO=300
- CONFIG_BAR=y
- CONFIG_QUX=y
- CONFIG_QUUX=y
-
-- savedefconfig
-
- This is the reverse operation of "make defconfig". If neither CONFIG_SPL
- nor CONFIG_TPL is defined in the .config file, it works like "savedefconfig"
- in Linux Kernel: creates the minimal set of config based on the .config
- and saves it into the "defconfig" file. If CONFIG_SPL (and CONFIG_TPL) is
- defined, the common lines among .config, spl/.config (and tpl/.config) are
- coalesced together with "<condition:>" prefix for each line as shown above.
- This file can be used as an input of "defconfig" target.
+- defconfig
+
+ In U-Boot, "make defconfig" is a shorthand of "make sandbox_defconfig"
+
+- <board>_defconfig
+
+ Now it works as in Linux.
+ The prefixes such as "+S:" in *_defconfig are deprecated.
+ You can simply remove the prefixes. Do not add them for new boards.
- <board>_config
This does not exist in Linux's Kconfig.
+ "make <board>_config" works the same as "make <board>_defconfig".
Prior to Kconfig, in U-Boot, "make <board>_config" was used for the
- configuration. It is still supported for backward compatibility and
- its behavior is the same as "make <board>_defconfig".
+ configuration. It is still supported for backward compatibility, so
+ we do not need to update the distro recipes.
+
+
+The other configuration targets work as in Linux Kernel.
Migration steps to Kconfig
Configuration files for use in C sources
- include/generated/autoconf.h (generated by Kconfig for Normal)
- - spl/include/generated/autoconf.h (generated by Kconfig for SPL)
- - tpl/include/generated/autoconf.h (generated by Kconfig for TPL)
- include/configs/<board>.h (exists for all boards)
Configuration file for use in makefiles
- - include/config/auto.conf (generated by Kconfig for Normal)
- - spl/include/config/auto.conf (generated by Kconfig for SPL)
- - tpl/include/config/auto.conf (generated by Kconfig for TPL)
+ - include/config/auto.conf (generated by Kconfig)
- include/autoconf.mk (generated by the old config for Normal)
- spl/include/autoconfig.mk (generated by the old config for SPL)
- tpl/include/autoconfig.mk (generated by the old config for TPL)
CONFIG_SYS_EXTRA_OPTIONS should not be used for new boards.
- In the pre-Kconfig, a single board had multiple entries in the boards.cfg
- file with differences in the option fields. The correspoing defconfig files
- were auto-generated when switching to Kconfig. Now we have too many
+ file with differences in the option fields. The corresponding defconfig
+ files were auto-generated when switching to Kconfig. Now we have too many
defconfig files compared with the number of the supported boards. It is
recommended to have only one defconfig per board and allow users to select
the config options.
Board Arch CPU Commit Removed Last known maintainer/contact
=================================================================================================
-icecube_5200 powerpc mpc5xxx - - Wolfgang Denk <wd@denx.de>
-Lite5200 powerpc mpc5xxx - -
-cpci5200 powerpc mpc5xxx - - Reinhard Arlt <reinhard.arlt@esd-electronics.com>
-mecp5200 powerpc mpc5xxx - - Reinhard Arlt <reinhard.arlt@esd-electronics.com>
-pf5200 powerpc mpc5xxx - - Reinhard Arlt <reinhard.arlt@esd-electronics.com>
-PM520 powerpc mpc5xxx - - Josef Wagner <Wagner@Microsys.de>
-Total5200 powerpc mpc5xxx - -
-CATcenter powerpc ppc4xx - -
-PPChameleonEVB powerpc ppc4xx - - Andrea "llandre" Marson <andrea.marson@dave-tech.it>
-P2020DS powerpc mpc85xx - -
-P2020COME powerpc mpc85xx - - Ira W. Snyder <iws@ovro.caltech.edu>
-P2020RDB powerpc mpc85xx - - Poonam Aggrwal <poonam.aggrwal@freescale.com>
-P2010RDB powerpc mpc85xx - -
-P1020RDB powerpc mpc85xx - -
-P1011RDB powerpc mpc85xx - -
-MPC8360EMDS powerpc mpc83xx - - Dave Liu <daveliu@freescale.com>
-MPC8360ERDK powerpc mpc83xx - - Anton Vorontsov <avorontsov@ru.mvista.com>
+hawkboard arm arm926ejs - - Syed Mohammed Khasim <sm.khasim@gmail.com>:Sughosh Ganu <urwithsughosh@gmail.com>
+tnetv107x arm arm1176 - - Chan-Taek Park <c-park@ti.com>
+a320evb arm arm920t - - Po-Yu Chuang <ratbert@faraday-tech.com>
+cm4008 arm arm920t - - Greg Ungerer <greg.ungerer@opengear.com>
+cm41xx arm arm920t - -
+dkb arm arm926ejs - - Lei Wen <leiwen@marvell.com>
+jadecpu arm arm926ejs - - Matthias Weisser <weisserm@arcor.de>
+icecube_5200 powerpc mpc5xxx 37b608a5 2015-01-23 Wolfgang Denk <wd@denx.de>
+Lite5200 powerpc mpc5xxx 37b608a5 2015-01-23
+cpci5200 powerpc mpc5xxx 37b608a5 2015-01-23 Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+mecp5200 powerpc mpc5xxx 37b608a5 2015-01-23 Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+pf5200 powerpc mpc5xxx 37b608a5 2015-01-23 Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+PM520 powerpc mpc5xxx a258e732 2015-01-23 Josef Wagner <Wagner@Microsys.de>
+Total5200 powerpc mpc5xxx ad734f7d 2015-01-23
+CATcenter powerpc ppc4xx 5344cc1a 2015-01-23
+PPChameleonEVB powerpc ppc4xx 5344cc1a 2015-01-23 Andrea "llandre" Marson <andrea.marson@dave-tech.it>
+P2020DS powerpc mpc85xx 168dcc6c 2015-01-23
+P2020COME powerpc mpc85xx 89123536 2015-01-23 Ira W. Snyder <iws@ovro.caltech.edu>
+P2020RDB powerpc mpc85xx 743d4815 2015-01-23 Poonam Aggrwal <poonam.aggrwal@freescale.com>
+P2010RDB powerpc mpc85xx 743d4815 2015-01-23
+P1020RDB powerpc mpc85xx 743d4815 2015-01-23
+P1011RDB powerpc mpc85xx 743d4815 2015-01-23
+MPC8360EMDS powerpc mpc83xx 8d1e3cb1 2015-01-23 Dave Liu <daveliu@freescale.com>
+MPC8360ERDK powerpc mpc83xx 8d1e3cb1 2015-01-23 Anton Vorontsov <avorontsov@ru.mvista.com>
P3G4 powerpc 74xx_7xx d928664f 2015-01-16 Wolfgang Denk <wd@denx.de>
ZUMA powerpc 74xx_7xx d928664f 2015-01-16 Nye Liu <nyet@zumanetworks.com>
ppmc7xx powerpc 74xx_7xx d928664f 2015-01-16
config DM
bool "Enable Driver Model"
- depends on !SPL_BUILD
help
This config option enables Driver Model. This brings in the core
support, including scanning of platform data on start-up. If
config DM_WARN
bool "Enable warnings in driver model"
+ depends on DM
+ default y
help
The dm_warn() function can use up quite a bit of space for its
strings. By default this is disabled for SPL builds to save space.
This will cause dm_warn() to be compiled out - it will do nothing
when called.
- depends on DM
- default y if !SPL_BUILD
- default n if SPL_BUILD
config DM_DEVICE_REMOVE
bool "Support device removal"
+ depends on DM
+ default y
help
We can save some code space by dropping support for removing a
device. This is not normally required in SPL, so by default this
option is disabled for SPL.
- depends on DM
- default y if !SPL_BUILD
- default n if SPL_BUILD
config DM_STDIO
bool "Support stdio registration"
+ depends on DM
+ default y
help
Normally serial drivers register with stdio so that they can be used
as normal output devices. In SPL we don't normally use stdio, so
we can omit this feature.
- depends on DM
- default y if !SPL_BUILD
- default n if SPL_BUILD
#include "desc.h"
#include "jr.h"
-int blob_decrypt(u8 *key_mod, u8 *src, u8 *dst, u8 len)
+int blob_decap(u8 *key_mod, u8 *src, u8 *dst, u32 len)
{
int ret, i = 0;
u32 *desc;
return ret;
}
-int blob_encrypt(u8 *key_mod, u8 *src, u8 *dst, u8 len)
+int blob_encap(u8 *key_mod, u8 *src, u8 *dst, u32 len)
{
int ret, i = 0;
u32 *desc;
#include "jobdesc.h"
#include "desc.h"
#include "jr.h"
+#include "fsl_hash.h"
+#include <hw_sha.h>
+#include <asm-generic/errno.h>
#define CRYPTO_MAX_ALG_NAME 80
#define SHA1_DIGEST_SIZE 20
},
};
+static enum caam_hash_algos get_hash_type(struct hash_algo *algo)
+{
+ if (!strcmp(algo->name, driver_hash[SHA1].name))
+ return SHA1;
+ else
+ return SHA256;
+}
+
+/* Create the context for progressive hashing using h/w acceleration.
+ *
+ * @ctxp: Pointer to the pointer of the context for hashing
+ * @caam_algo: Enum for SHA1 or SHA256
+ * @return 0 if ok, -ENOMEM on error
+ */
+static int caam_hash_init(void **ctxp, enum caam_hash_algos caam_algo)
+{
+ *ctxp = calloc(1, sizeof(struct sha_ctx));
+ if (*ctxp == NULL) {
+ debug("Cannot allocate memory for context\n");
+ return -ENOMEM;
+ }
+ return 0;
+}
+
+/*
+ * Update sg table for progressive hashing using h/w acceleration
+ *
+ * The context is freed by this function if an error occurs.
+ * We support at most 32 Scatter/Gather Entries.
+ *
+ * @hash_ctx: Pointer to the context for hashing
+ * @buf: Pointer to the buffer being hashed
+ * @size: Size of the buffer being hashed
+ * @is_last: 1 if this is the last update; 0 otherwise
+ * @caam_algo: Enum for SHA1 or SHA256
+ * @return 0 if ok, -EINVAL on error
+ */
+static int caam_hash_update(void *hash_ctx, const void *buf,
+ unsigned int size, int is_last,
+ enum caam_hash_algos caam_algo)
+{
+ uint32_t final = 0;
+ dma_addr_t addr = virt_to_phys((void *)buf);
+ struct sha_ctx *ctx = hash_ctx;
+
+ if (ctx->sg_num >= MAX_SG_32) {
+ free(ctx);
+ return -EINVAL;
+ }
+
+#ifdef CONFIG_PHYS_64BIT
+ ctx->sg_tbl[ctx->sg_num].addr_hi = addr >> 32;
+#else
+ ctx->sg_tbl[ctx->sg_num].addr_hi = 0x0;
+#endif
+ ctx->sg_tbl[ctx->sg_num].addr_lo = addr;
+
+ sec_out32(&ctx->sg_tbl[ctx->sg_num].len_flag,
+ (size & SG_ENTRY_LENGTH_MASK));
+
+ ctx->sg_num++;
+
+ if (is_last) {
+ final = sec_in32(&ctx->sg_tbl[ctx->sg_num - 1].len_flag) |
+ SG_ENTRY_FINAL_BIT;
+ sec_out32(&ctx->sg_tbl[ctx->sg_num - 1].len_flag, final);
+ }
+
+ return 0;
+}
+
+/*
+ * Perform progressive hashing on the given buffer and copy hash at
+ * destination buffer
+ *
+ * The context is freed after completion of hash operation.
+ *
+ * @hash_ctx: Pointer to the context for hashing
+ * @dest_buf: Pointer to the destination buffer where hash is to be copied
+ * @size: Size of the buffer being hashed
+ * @caam_algo: Enum for SHA1 or SHA256
+ * @return 0 if ok, -EINVAL on error
+ */
+static int caam_hash_finish(void *hash_ctx, void *dest_buf,
+ int size, enum caam_hash_algos caam_algo)
+{
+ uint32_t len = 0;
+ struct sha_ctx *ctx = hash_ctx;
+ int i = 0, ret = 0;
+
+ if (size < driver_hash[caam_algo].digestsize) {
+ free(ctx);
+ return -EINVAL;
+ }
+
+ for (i = 0; i < ctx->sg_num; i++)
+ len += (sec_in32(&ctx->sg_tbl[i].len_flag) &
+ SG_ENTRY_LENGTH_MASK);
+
+ inline_cnstr_jobdesc_hash(ctx->sha_desc, (uint8_t *)ctx->sg_tbl, len,
+ ctx->hash,
+ driver_hash[caam_algo].alg_type,
+ driver_hash[caam_algo].digestsize,
+ 1);
+
+ ret = run_descriptor_jr(ctx->sha_desc);
+
+ if (ret)
+ debug("Error %x\n", ret);
+ else
+ memcpy(dest_buf, ctx->hash, sizeof(ctx->hash));
+
+ free(ctx);
+ return ret;
+}
+
int caam_hash(const unsigned char *pbuf, unsigned int buf_len,
unsigned char *pout, enum caam_hash_algos algo)
{
desc = malloc(sizeof(int) * MAX_CAAM_DESCSIZE);
if (!desc) {
debug("Not enough memory for descriptor allocation\n");
- return -1;
+ return -ENOMEM;
}
inline_cnstr_jobdesc_hash(desc, pbuf, buf_len, pout,
if (caam_hash(pbuf, buf_len, pout, SHA1))
printf("CAAM was not setup properly or it is faulty\n");
}
+
+int hw_sha_init(struct hash_algo *algo, void **ctxp)
+{
+ return caam_hash_init(ctxp, get_hash_type(algo));
+}
+
+int hw_sha_update(struct hash_algo *algo, void *ctx, const void *buf,
+ unsigned int size, int is_last)
+{
+ return caam_hash_update(ctx, buf, size, is_last, get_hash_type(algo));
+}
+
+int hw_sha_finish(struct hash_algo *algo, void *ctx, void *dest_buf,
+ int size)
+{
+ return caam_hash_finish(ctx, dest_buf, size, get_hash_type(algo));
+}
--- /dev/null
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ */
+
+#ifndef _SHA_H
+#define _SHA_H
+
+#include <fsl_sec.h>
+#include <hash.h>
+#include "jr.h"
+
+/* We support at most 32 Scatter/Gather Entries.*/
+#define MAX_SG_32 32
+
+/*
+ * Hash context contains the following fields
+ * @sha_desc: Sha Descriptor
+ * @sg_num: number of entries in sg table
+ * @len: total length of buffer
+ * @sg_tbl: sg entry table
+ * @hash: index to the hash calculated
+ */
+struct sha_ctx {
+ uint32_t sha_desc[64];
+ uint32_t sg_num;
+ uint32_t len;
+ struct sg_entry sg_tbl[MAX_SG_32];
+ u8 hash[HASH_MAX_DIGEST_SIZE];
+};
+
+#endif
bus_width = 3 - ((ddr_in32(&ddr->sdram_cfg) & SDRAM_CFG_DBW_MASK)
>> SDRAM_CFG_DBW_SHIFT);
timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 /
- (get_ddr_freq(0) >> 20)) << 1;
+ (get_ddr_freq(ctrl_num) >> 20)) << 1;
total_gb_size_per_controller >>= 4; /* shift down to gb size */
debug("total %d GB\n", total_gb_size_per_controller);
debug("Need to wait up to %d * 10ms\n", timeout);
#include <fsl_immap.h>
#include <asm/io.h>
-unsigned int picos_to_mclk(unsigned int picos);
-
/*
* Determine Rtt value.
*
* 16 for <= 2933MT/s
* 18 for higher
*/
-static inline unsigned int compute_cas_write_latency(void)
+static inline unsigned int compute_cas_write_latency(
+ const unsigned int ctrl_num)
{
unsigned int cwl;
- const unsigned int mclk_ps = get_memory_clk_period_ps();
+ const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
if (mclk_ps >= 1250)
cwl = 9;
else if (mclk_ps >= 1070)
* 11 if 0.935ns > tCK >= 0.833ns
* 12 if 0.833ns > tCK >= 0.75ns
*/
-static inline unsigned int compute_cas_write_latency(void)
+static inline unsigned int compute_cas_write_latency(
+ const unsigned int ctrl_num)
{
unsigned int cwl;
- const unsigned int mclk_ps = get_memory_clk_period_ps();
+ const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
if (mclk_ps >= 2500)
cwl = 5;
* Avoid writing for DDR I. The new PQ38 DDR controller
* dreams up non-zero default values to be backwards compatible.
*/
-static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr,
+static void set_timing_cfg_0(const unsigned int ctrl_num,
+ fsl_ddr_cfg_regs_t *ddr,
const memctl_options_t *popts,
const dimm_params_t *dimm_params)
{
/* Mode register set cycle time (tMRD). */
unsigned char tmrd_mclk;
#if defined(CONFIG_SYS_FSL_DDR4) || defined(CONFIG_SYS_FSL_DDR3)
- const unsigned int mclk_ps = get_memory_clk_period_ps();
+ const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
#endif
#ifdef CONFIG_SYS_FSL_DDR4
int txp = max((int)mclk_ps * 4, 6000); /* unit=ps */
trwt_mclk = 2;
twrt_mclk = 1;
- act_pd_exit_mclk = picos_to_mclk(txp);
+ act_pd_exit_mclk = picos_to_mclk(ctrl_num, txp);
pre_pd_exit_mclk = act_pd_exit_mclk;
/*
* MRS_CYC = max(tMRD, tMOD)
* tMRD = 8nCK, tMOD = max(24nCK, 15ns)
*/
- tmrd_mclk = max(24U, picos_to_mclk(15000));
+ tmrd_mclk = max(24U, picos_to_mclk(ctrl_num, 15000));
#elif defined(CONFIG_SYS_FSL_DDR3)
- unsigned int data_rate = get_ddr_freq(0);
+ unsigned int data_rate = get_ddr_freq(ctrl_num);
int txp;
unsigned int ip_rev;
int odt_overlap;
* tMRD = 4nCK (8nCK for RDIMM)
* tMOD = max(12nCK, 15ns)
*/
- tmrd_mclk = max((unsigned int)12, picos_to_mclk(15000));
+ tmrd_mclk = max((unsigned int)12,
+ picos_to_mclk(ctrl_num, 15000));
} else {
/*
* MRS_CYC = tMRD
taxpd_mclk = 1;
} else {
/* act_pd_exit_mclk = tXARD, see above */
- act_pd_exit_mclk = picos_to_mclk(txp);
+ act_pd_exit_mclk = picos_to_mclk(ctrl_num, txp);
/* Mode register MR0[A12] is '1' - fast exit */
pre_pd_exit_mclk = act_pd_exit_mclk;
taxpd_mclk = 1;
#endif /* !defined(CONFIG_SYS_FSL_DDR1) */
/* DDR SDRAM Timing Configuration 3 (TIMING_CFG_3) */
-static void set_timing_cfg_3(fsl_ddr_cfg_regs_t *ddr,
- const memctl_options_t *popts,
- const common_timing_params_t *common_dimm,
- unsigned int cas_latency,
- unsigned int additive_latency)
+static void set_timing_cfg_3(const unsigned int ctrl_num,
+ fsl_ddr_cfg_regs_t *ddr,
+ const memctl_options_t *popts,
+ const common_timing_params_t *common_dimm,
+ unsigned int cas_latency,
+ unsigned int additive_latency)
{
/* Extended precharge to activate interval (tRP) */
unsigned int ext_pretoact = 0;
/* Control Adjust */
unsigned int cntl_adj = 0;
- ext_pretoact = picos_to_mclk(common_dimm->trp_ps) >> 4;
- ext_acttopre = picos_to_mclk(common_dimm->tras_ps) >> 4;
- ext_acttorw = picos_to_mclk(common_dimm->trcd_ps) >> 4;
+ ext_pretoact = picos_to_mclk(ctrl_num, common_dimm->trp_ps) >> 4;
+ ext_acttopre = picos_to_mclk(ctrl_num, common_dimm->tras_ps) >> 4;
+ ext_acttorw = picos_to_mclk(ctrl_num, common_dimm->trcd_ps) >> 4;
ext_caslat = (2 * cas_latency - 1) >> 4;
ext_add_lat = additive_latency >> 4;
#ifdef CONFIG_SYS_FSL_DDR4
- ext_refrec = (picos_to_mclk(common_dimm->trfc1_ps) - 8) >> 4;
+ ext_refrec = (picos_to_mclk(ctrl_num, common_dimm->trfc1_ps) - 8) >> 4;
#else
- ext_refrec = (picos_to_mclk(common_dimm->trfc_ps) - 8) >> 4;
+ ext_refrec = (picos_to_mclk(ctrl_num, common_dimm->trfc_ps) - 8) >> 4;
/* ext_wrrec only deals with 16 clock and above, or 14 with OTF */
#endif
- ext_wrrec = (picos_to_mclk(common_dimm->twr_ps) +
+ ext_wrrec = (picos_to_mclk(ctrl_num, common_dimm->twr_ps) +
(popts->otf_burst_chop_en ? 2 : 0)) >> 4;
ddr->timing_cfg_3 = (0
}
/* DDR SDRAM Timing Configuration 1 (TIMING_CFG_1) */
-static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr,
- const memctl_options_t *popts,
- const common_timing_params_t *common_dimm,
- unsigned int cas_latency)
+static void set_timing_cfg_1(const unsigned int ctrl_num,
+ fsl_ddr_cfg_regs_t *ddr,
+ const memctl_options_t *popts,
+ const common_timing_params_t *common_dimm,
+ unsigned int cas_latency)
{
/* Precharge-to-activate interval (tRP) */
unsigned char pretoact_mclk;
1, 2, 3, 4, 5, 6, 7, 8, 10, 10, 12, 12, 14, 14, 0, 0};
#endif
- pretoact_mclk = picos_to_mclk(common_dimm->trp_ps);
- acttopre_mclk = picos_to_mclk(common_dimm->tras_ps);
- acttorw_mclk = picos_to_mclk(common_dimm->trcd_ps);
+ pretoact_mclk = picos_to_mclk(ctrl_num, common_dimm->trp_ps);
+ acttopre_mclk = picos_to_mclk(ctrl_num, common_dimm->tras_ps);
+ acttorw_mclk = picos_to_mclk(ctrl_num, common_dimm->trcd_ps);
/*
* Translate CAS Latency to a DDR controller field value:
#endif
#ifdef CONFIG_SYS_FSL_DDR4
- refrec_ctrl = picos_to_mclk(common_dimm->trfc1_ps) - 8;
- wrrec_mclk = picos_to_mclk(common_dimm->twr_ps);
- acttoact_mclk = max(picos_to_mclk(common_dimm->trrds_ps), 4U);
- wrtord_mclk = max(2U, picos_to_mclk(2500));
+ refrec_ctrl = picos_to_mclk(ctrl_num, common_dimm->trfc1_ps) - 8;
+ wrrec_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
+ acttoact_mclk = max(picos_to_mclk(ctrl_num, common_dimm->trrds_ps), 4U);
+ wrtord_mclk = max(2U, picos_to_mclk(ctrl_num, 2500));
if ((wrrec_mclk < 1) || (wrrec_mclk > 24))
printf("Error: WRREC doesn't support %d clocks\n", wrrec_mclk);
else
wrrec_mclk = wrrec_table[wrrec_mclk - 1];
#else
- refrec_ctrl = picos_to_mclk(common_dimm->trfc_ps) - 8;
- wrrec_mclk = picos_to_mclk(common_dimm->twr_ps);
- acttoact_mclk = picos_to_mclk(common_dimm->trrd_ps);
- wrtord_mclk = picos_to_mclk(common_dimm->twtr_ps);
+ refrec_ctrl = picos_to_mclk(ctrl_num, common_dimm->trfc_ps) - 8;
+ wrrec_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
+ acttoact_mclk = picos_to_mclk(ctrl_num, common_dimm->trrd_ps);
+ wrtord_mclk = picos_to_mclk(ctrl_num, common_dimm->twtr_ps);
if ((wrrec_mclk < 1) || (wrrec_mclk > 16))
printf("Error: WRREC doesn't support %d clocks\n", wrrec_mclk);
else
}
/* DDR SDRAM Timing Configuration 2 (TIMING_CFG_2) */
-static void set_timing_cfg_2(fsl_ddr_cfg_regs_t *ddr,
- const memctl_options_t *popts,
- const common_timing_params_t *common_dimm,
- unsigned int cas_latency,
- unsigned int additive_latency)
+static void set_timing_cfg_2(const unsigned int ctrl_num,
+ fsl_ddr_cfg_regs_t *ddr,
+ const memctl_options_t *popts,
+ const common_timing_params_t *common_dimm,
+ unsigned int cas_latency,
+ unsigned int additive_latency)
{
/* Additive latency */
unsigned char add_lat_mclk;
/* Window for four activates (tFAW) */
unsigned short four_act;
#ifdef CONFIG_SYS_FSL_DDR3
- const unsigned int mclk_ps = get_memory_clk_period_ps();
+ const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
#endif
/* FIXME add check that this must be less than acttorw_mclk */
#elif defined(CONFIG_SYS_FSL_DDR2)
wr_lat = cas_latency - 1;
#else
- wr_lat = compute_cas_write_latency();
+ wr_lat = compute_cas_write_latency(ctrl_num);
#endif
#ifdef CONFIG_SYS_FSL_DDR4
- rd_to_pre = picos_to_mclk(7500);
+ rd_to_pre = picos_to_mclk(ctrl_num, 7500);
#else
- rd_to_pre = picos_to_mclk(common_dimm->trtp_ps);
+ rd_to_pre = picos_to_mclk(ctrl_num, common_dimm->trtp_ps);
#endif
/*
* JEDEC has some min requirements for tRTP
wr_data_delay = popts->write_data_delay;
#ifdef CONFIG_SYS_FSL_DDR4
cpo = 0;
- cke_pls = max(3U, picos_to_mclk(5000));
+ cke_pls = max(3U, picos_to_mclk(ctrl_num, 5000));
#elif defined(CONFIG_SYS_FSL_DDR3)
/*
* cke pulse = max(3nCK, 7.5ns) for DDR3-800
* max(3nCK, 5.625ns) for DDR3-1066, 1333
* max(3nCK, 5ns) for DDR3-1600, 1866, 2133
*/
- cke_pls = max(3U, picos_to_mclk(mclk_ps > 1870 ? 7500 :
- (mclk_ps > 1245 ? 5625 : 5000)));
+ cke_pls = max(3U, picos_to_mclk(ctrl_num, mclk_ps > 1870 ? 7500 :
+ (mclk_ps > 1245 ? 5625 : 5000)));
#else
cke_pls = FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR;
#endif
- four_act = picos_to_mclk(popts->tfaw_window_four_activates_ps);
+ four_act = picos_to_mclk(ctrl_num,
+ popts->tfaw_window_four_activates_ps);
ddr->timing_cfg_2 = (0
| ((add_lat_mclk & 0xf) << 28)
}
/* DDR SDRAM control configuration 2 (DDR_SDRAM_CFG_2) */
-static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr,
+static void set_ddr_sdram_cfg_2(const unsigned int ctrl_num,
+ fsl_ddr_cfg_regs_t *ddr,
const memctl_options_t *popts,
const unsigned int unq_mrs_en)
{
#endif
#if (CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7)
- slow = get_ddr_freq(0) < 1249000000;
+ slow = get_ddr_freq(ctrl_num) < 1249000000;
#endif
if (popts->registered_dimm_en) {
#ifdef CONFIG_SYS_FSL_DDR4
/* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
-static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr,
+static void set_ddr_sdram_mode_2(const unsigned int ctrl_num,
+ fsl_ddr_cfg_regs_t *ddr,
const memctl_options_t *popts,
const common_timing_params_t *common_dimm,
const unsigned int unq_mrs_en)
unsigned int wr_crc = 0; /* Disable */
unsigned int rtt_wr = 0; /* Rtt_WR - dynamic ODT off */
unsigned int srt = 0; /* self-refresh temerature, normal range */
- unsigned int cwl = compute_cas_write_latency() - 9;
+ unsigned int cwl = compute_cas_write_latency(ctrl_num) - 9;
unsigned int mpr = 0; /* serial */
unsigned int wc_lat;
- const unsigned int mclk_ps = get_memory_clk_period_ps();
+ const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
if (popts->rtt_override)
rtt_wr = popts->rtt_wr_override_value;
}
#elif defined(CONFIG_SYS_FSL_DDR3)
/* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
-static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr,
+static void set_ddr_sdram_mode_2(const unsigned int ctrl_num,
+ fsl_ddr_cfg_regs_t *ddr,
const memctl_options_t *popts,
const common_timing_params_t *common_dimm,
const unsigned int unq_mrs_en)
unsigned int rtt_wr = 0; /* Rtt_WR - dynamic ODT off */
unsigned int srt = 0; /* self-refresh temerature, normal range */
unsigned int asr = 0; /* auto self-refresh disable */
- unsigned int cwl = compute_cas_write_latency() - 5;
+ unsigned int cwl = compute_cas_write_latency(ctrl_num) - 5;
unsigned int pasr = 0; /* partial array self refresh disable */
if (popts->rtt_override)
#else /* for DDR2 and DDR1 */
/* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
-static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr,
+static void set_ddr_sdram_mode_2(const unsigned int ctrl_num,
+ fsl_ddr_cfg_regs_t *ddr,
const memctl_options_t *popts,
const common_timing_params_t *common_dimm,
const unsigned int unq_mrs_en)
}
/* DDR SDRAM Mode configuration 10 (DDR_SDRAM_MODE_10) */
-static void set_ddr_sdram_mode_10(fsl_ddr_cfg_regs_t *ddr,
+static void set_ddr_sdram_mode_10(const unsigned int ctrl_num,
+ fsl_ddr_cfg_regs_t *ddr,
const memctl_options_t *popts,
const common_timing_params_t *common_dimm,
const unsigned int unq_mrs_en)
int i;
unsigned short esdmode6 = 0; /* Extended SDRAM mode 6 */
unsigned short esdmode7 = 0; /* Extended SDRAM mode 7 */
- unsigned int tccdl_min = picos_to_mclk(common_dimm->tccdl_ps);
+ unsigned int tccdl_min = picos_to_mclk(ctrl_num, common_dimm->tccdl_ps);
esdmode6 = ((tccdl_min - 4) & 0x7) << 10;
#endif
/* DDR SDRAM Interval Configuration (DDR_SDRAM_INTERVAL) */
-static void set_ddr_sdram_interval(fsl_ddr_cfg_regs_t *ddr,
- const memctl_options_t *popts,
- const common_timing_params_t *common_dimm)
+static void set_ddr_sdram_interval(const unsigned int ctrl_num,
+ fsl_ddr_cfg_regs_t *ddr,
+ const memctl_options_t *popts,
+ const common_timing_params_t *common_dimm)
{
unsigned int refint; /* Refresh interval */
unsigned int bstopre; /* Precharge interval */
- refint = picos_to_mclk(common_dimm->refresh_rate_ps);
+ refint = picos_to_mclk(ctrl_num, common_dimm->refresh_rate_ps);
bstopre = popts->bstopre;
#ifdef CONFIG_SYS_FSL_DDR4
/* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
-static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
+static void set_ddr_sdram_mode(const unsigned int ctrl_num,
+ fsl_ddr_cfg_regs_t *ddr,
const memctl_options_t *popts,
const common_timing_params_t *common_dimm,
unsigned int cas_latency,
* 1=fast exit DLL on (tXP)
*/
- wr_mclk = picos_to_mclk(common_dimm->twr_ps);
+ wr_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
if (wr_mclk <= 24) {
wr = wr_table[wr_mclk - 10];
} else {
#elif defined(CONFIG_SYS_FSL_DDR3)
/* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
-static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
+static void set_ddr_sdram_mode(const unsigned int ctrl_num,
+ fsl_ddr_cfg_regs_t *ddr,
const memctl_options_t *popts,
const common_timing_params_t *common_dimm,
unsigned int cas_latency,
*/
dll_on = 1;
- wr_mclk = picos_to_mclk(common_dimm->twr_ps);
+ wr_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
if (wr_mclk <= 16) {
wr = wr_table[wr_mclk - 5];
} else {
#else /* !CONFIG_SYS_FSL_DDR3 */
/* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
-static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
+static void set_ddr_sdram_mode(const unsigned int ctrl_num,
+ fsl_ddr_cfg_regs_t *ddr,
const memctl_options_t *popts,
const common_timing_params_t *common_dimm,
unsigned int cas_latency,
#if defined(CONFIG_SYS_FSL_DDR1)
wr = 0; /* Historical */
#elif defined(CONFIG_SYS_FSL_DDR2)
- wr = picos_to_mclk(common_dimm->twr_ps);
+ wr = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
#endif
dll_res = 0;
mode = 0;
debug("FSLDDR: timing_cfg_6 = 0x%08x\n", ddr->timing_cfg_6);
}
-static void set_timing_cfg_7(fsl_ddr_cfg_regs_t *ddr,
- const common_timing_params_t *common_dimm)
+static void set_timing_cfg_7(const unsigned int ctrl_num,
+ fsl_ddr_cfg_regs_t *ddr,
+ const common_timing_params_t *common_dimm)
{
unsigned int txpr, tcksre, tcksrx;
unsigned int cke_rst, cksre, cksrx, par_lat, cs_to_cmd;
- txpr = max(5U, picos_to_mclk(common_dimm->trfc1_ps + 10000));
- tcksre = max(5U, picos_to_mclk(10000));
- tcksrx = max(5U, picos_to_mclk(10000));
+ txpr = max(5U, picos_to_mclk(ctrl_num, common_dimm->trfc1_ps + 10000));
+ tcksre = max(5U, picos_to_mclk(ctrl_num, 10000));
+ tcksrx = max(5U, picos_to_mclk(ctrl_num, 10000));
par_lat = 0;
cs_to_cmd = 0;
debug("FSLDDR: timing_cfg_7 = 0x%08x\n", ddr->timing_cfg_7);
}
-static void set_timing_cfg_8(fsl_ddr_cfg_regs_t *ddr,
+static void set_timing_cfg_8(const unsigned int ctrl_num,
+ fsl_ddr_cfg_regs_t *ddr,
const memctl_options_t *popts,
const common_timing_params_t *common_dimm,
unsigned int cas_latency)
{
unsigned int rwt_bg, wrt_bg, rrt_bg, wwt_bg;
unsigned int acttoact_bg, wrtord_bg, pre_all_rec;
- unsigned int tccdl = picos_to_mclk(common_dimm->tccdl_ps);
+ unsigned int tccdl = picos_to_mclk(ctrl_num, common_dimm->tccdl_ps);
unsigned int wr_lat = ((ddr->timing_cfg_2 & 0x00780000) >> 19) +
((ddr->timing_cfg_2 & 0x00040000) >> 14);
wwt_bg = tccdl - 4;
} else {
rrt_bg = tccdl - 2;
- wwt_bg = tccdl - 4;
+ wwt_bg = tccdl - 2;
}
- acttoact_bg = picos_to_mclk(common_dimm->trrdl_ps);
- wrtord_bg = max(4U, picos_to_mclk(7500));
+ acttoact_bg = picos_to_mclk(ctrl_num, common_dimm->trrdl_ps);
+ wrtord_bg = max(4U, picos_to_mclk(ctrl_num, 7500));
if (popts->otf_burst_chop_en)
wrtord_bg += 2;
}
unsigned int
-compute_fsl_memctl_config_regs(const memctl_options_t *popts,
+compute_fsl_memctl_config_regs(const unsigned int ctrl_num,
+ const memctl_options_t *popts,
fsl_ddr_cfg_regs_t *ddr,
const common_timing_params_t *common_dimm,
const dimm_params_t *dimm_params,
set_ddr_eor(ddr, popts);
#if !defined(CONFIG_SYS_FSL_DDR1)
- set_timing_cfg_0(ddr, popts, dimm_params);
+ set_timing_cfg_0(ctrl_num, ddr, popts, dimm_params);
#endif
- set_timing_cfg_3(ddr, popts, common_dimm, cas_latency,
+ set_timing_cfg_3(ctrl_num, ddr, popts, common_dimm, cas_latency,
additive_latency);
- set_timing_cfg_1(ddr, popts, common_dimm, cas_latency);
- set_timing_cfg_2(ddr, popts, common_dimm,
- cas_latency, additive_latency);
+ set_timing_cfg_1(ctrl_num, ddr, popts, common_dimm, cas_latency);
+ set_timing_cfg_2(ctrl_num, ddr, popts, common_dimm,
+ cas_latency, additive_latency);
set_ddr_cdr1(ddr, popts);
set_ddr_cdr2(ddr, popts);
if ((ip_rev > 0x40700) && (popts->cswl_override != 0))
ddr->debug[18] = popts->cswl_override;
- set_ddr_sdram_cfg_2(ddr, popts, unq_mrs_en);
- set_ddr_sdram_mode(ddr, popts, common_dimm,
- cas_latency, additive_latency, unq_mrs_en);
- set_ddr_sdram_mode_2(ddr, popts, common_dimm, unq_mrs_en);
+ set_ddr_sdram_cfg_2(ctrl_num, ddr, popts, unq_mrs_en);
+ set_ddr_sdram_mode(ctrl_num, ddr, popts, common_dimm,
+ cas_latency, additive_latency, unq_mrs_en);
+ set_ddr_sdram_mode_2(ctrl_num, ddr, popts, common_dimm, unq_mrs_en);
#ifdef CONFIG_SYS_FSL_DDR4
set_ddr_sdram_mode_9(ddr, popts, common_dimm, unq_mrs_en);
- set_ddr_sdram_mode_10(ddr, popts, common_dimm, unq_mrs_en);
+ set_ddr_sdram_mode_10(ctrl_num, ddr, popts, common_dimm, unq_mrs_en);
#endif
- set_ddr_sdram_interval(ddr, popts, common_dimm);
+ set_ddr_sdram_interval(ctrl_num, ddr, popts, common_dimm);
set_ddr_data_init(ddr);
set_ddr_sdram_clk_cntl(ddr, popts);
set_ddr_init_addr(ddr);
#ifdef CONFIG_SYS_FSL_DDR4
set_ddr_sdram_cfg_3(ddr, popts);
set_timing_cfg_6(ddr);
- set_timing_cfg_7(ddr, common_dimm);
- set_timing_cfg_8(ddr, popts, common_dimm, cas_latency);
+ set_timing_cfg_7(ctrl_num, ddr, common_dimm);
+ set_timing_cfg_8(ctrl_num, ddr, popts, common_dimm, cas_latency);
set_timing_cfg_9(ddr);
set_ddr_dq_mapping(ddr, dimm_params);
#endif
#ifdef CONFIG_SYS_FSL_DDR_EMU
/* disble DDR training for emulator */
ddr->debug[2] = 0x00000400;
- ddr->debug[4] = 0xff800000;
+ ddr->debug[4] = 0xff800800;
+ ddr->debug[5] = 0x08000800;
+ ddr->debug[6] = 0x08000800;
+ ddr->debug[7] = 0x08000800;
+ ddr->debug[8] = 0x08000800;
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A004508
if ((ip_rev >= 0x40000) && (ip_rev < 0x40400))
*
* FIXME: use #define for the retvals
*/
-unsigned int
-ddr_compute_dimm_parameters(const ddr1_spd_eeprom_t *spd,
- dimm_params_t *pdimm,
- unsigned int dimm_number)
+unsigned int ddr_compute_dimm_parameters(const unsigned int ctrl_num,
+ const ddr1_spd_eeprom_t *spd,
+ dimm_params_t *pdimm,
+ unsigned int dimm_number)
{
unsigned int retval;
& ~(1 << pdimm->caslat_x_minus_1));
/* Compute CAS latencies below that defined by SPD */
- pdimm->caslat_lowest_derated
- = compute_derated_DDR1_CAS_latency(get_memory_clk_period_ps());
+ pdimm->caslat_lowest_derated = compute_derated_DDR1_CAS_latency(
+ get_memory_clk_period_ps(ctrl_num));
/* Compute timing parameters */
pdimm->trcd_ps = spd->trcd * 250;
pdimm->trp_ps = spd->trp * 250;
pdimm->tras_ps = spd->tras * 1000;
- pdimm->twr_ps = mclk_to_picos(3);
- pdimm->twtr_ps = mclk_to_picos(1);
+ pdimm->twr_ps = mclk_to_picos(ctrl_num, 3);
+ pdimm->twtr_ps = mclk_to_picos(ctrl_num, 1);
pdimm->trfc_ps = compute_trfc_ps_from_spd(0, spd->trfc);
pdimm->trrd_ps = spd->trrd * 250;
pdimm->tdh_ps
= convert_bcd_hundredths_to_cycle_time_ps(spd->data_hold);
- pdimm->trtp_ps = mclk_to_picos(2); /* By the book. */
+ pdimm->trtp_ps = mclk_to_picos(ctrl_num, 2); /* By the book. */
pdimm->tdqsq_max_ps = spd->tdqsq * 10;
pdimm->tqhs_ps = spd->tqhs * 10;
*
* FIXME: use #define for the retvals
*/
-unsigned int
-ddr_compute_dimm_parameters(const ddr2_spd_eeprom_t *spd,
- dimm_params_t *pdimm,
- unsigned int dimm_number)
+unsigned int ddr_compute_dimm_parameters(const unsigned int ctrl_num,
+ const ddr2_spd_eeprom_t *spd,
+ dimm_params_t *pdimm,
+ unsigned int dimm_number)
{
unsigned int retval;
& ~(1 << pdimm->caslat_x_minus_1));
/* Compute CAS latencies below that defined by SPD */
- pdimm->caslat_lowest_derated
- = compute_derated_DDR2_CAS_latency(get_memory_clk_period_ps());
+ pdimm->caslat_lowest_derated = compute_derated_DDR2_CAS_latency(
+ get_memory_clk_period_ps(ctrl_num));
/* Compute timing parameters */
pdimm->trcd_ps = spd->trcd * 250;
* Writes the results to the dimm_params_t structure pointed by pdimm.
*
*/
-unsigned int
-ddr_compute_dimm_parameters(const ddr3_spd_eeprom_t *spd,
- dimm_params_t *pdimm,
- unsigned int dimm_number)
+unsigned int ddr_compute_dimm_parameters(const unsigned int ctrl_num,
+ const ddr3_spd_eeprom_t *spd,
+ dimm_params_t *pdimm,
+ unsigned int dimm_number)
{
unsigned int retval;
unsigned int mtb_ps;
* Writes the results to the dimm_params_t structure pointed by pdimm.
*
*/
-unsigned int
-ddr_compute_dimm_parameters(const generic_spd_eeprom_t *spd,
- dimm_params_t *pdimm,
- unsigned int dimm_number)
+unsigned int ddr_compute_dimm_parameters(const unsigned int ctrl_num,
+ const generic_spd_eeprom_t *spd,
+ dimm_params_t *pdimm,
+ unsigned int dimm_number)
{
unsigned int retval;
int i;
u32 temp_sdram_cfg;
u32 total_gb_size_per_controller;
int timeout;
+#if defined(CONFIG_SYS_FSL_ERRATUM_A008336) || \
+ defined(CONFIG_SYS_FSL_ERRATUM_A008514)
+ u32 *eddrtqcr1;
+#endif
switch (ctrl_num) {
case 0:
ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
+#if defined(CONFIG_SYS_FSL_ERRATUM_A008336) || \
+ defined(CONFIG_SYS_FSL_ERRATUM_A008514)
+ eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR_ADDR + 0x800;
+#endif
break;
#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
case 1:
ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
+#if defined(CONFIG_SYS_FSL_ERRATUM_A008336) || \
+ defined(CONFIG_SYS_FSL_ERRATUM_A008514)
+ eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR2_ADDR + 0x800;
+#endif
break;
#endif
#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
case 2:
ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
+#if defined(CONFIG_SYS_FSL_ERRATUM_A008336) || \
+ defined(CONFIG_SYS_FSL_ERRATUM_A008514)
+ eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR3_ADDR + 0x800;
+#endif
break;
#endif
#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
case 3:
ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
+#if defined(CONFIG_SYS_FSL_ERRATUM_A008336) || \
+ defined(CONFIG_SYS_FSL_ERRATUM_A008514)
+ eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR4_ADDR + 0x800;
+#endif
break;
#endif
default:
if (step == 2)
goto step2;
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008336
+#ifdef CONFIG_LS2085A
+ /* A008336 only applies to general DDR controllers */
+ if ((ctrl_num == 0) || (ctrl_num == 1))
+#endif
+ ddr_out32(eddrtqcr1, 0x63b30002);
+#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008514
+#ifdef CONFIG_LS2085A
+ /* A008514 only applies to DP-DDR controler */
+ if (ctrl_num == 2)
+#endif
+ ddr_out32(eddrtqcr1, 0x63b20002);
+#endif
if (regs->ddr_eor)
ddr_out32(&ddr->eor, regs->ddr_eor);
bus_width = 3 - ((ddr_in32(&ddr->sdram_cfg) & SDRAM_CFG_DBW_MASK)
>> SDRAM_CFG_DBW_SHIFT);
timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 /
- (get_ddr_freq(0) >> 20)) << 2;
+ (get_ddr_freq(ctrl_num) >> 20)) << 2;
total_gb_size_per_controller >>= 4; /* shift down to gb size */
debug("total %d GB\n", total_gb_size_per_controller);
debug("Need to wait up to %d * 10ms\n", timeout);
#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
static unsigned int
-compute_cas_latency(const dimm_params_t *dimm_params,
+compute_cas_latency(const unsigned int ctrl_num,
+ const dimm_params_t *dimm_params,
common_timing_params_t *outpdimm,
unsigned int number_of_dimms)
{
unsigned int caslat_actual;
unsigned int retry = 16;
unsigned int tmp;
- const unsigned int mclk_ps = get_memory_clk_period_ps();
+ const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
#ifdef CONFIG_SYS_FSL_DDR3
const unsigned int taamax = 20000;
#else
}
#else /* for DDR1 and DDR2 */
static unsigned int
-compute_cas_latency(const dimm_params_t *dimm_params,
+compute_cas_latency(const unsigned int ctrl_num,
+ const dimm_params_t *dimm_params,
common_timing_params_t *outpdimm,
unsigned int number_of_dimms)
{
int i;
- const unsigned int mclk_ps = get_memory_clk_period_ps();
+ const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
unsigned int lowest_good_caslat;
unsigned int not_ok;
unsigned int temp1, temp2;
* by dimm_params.
*/
unsigned int
-compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params,
+compute_lowest_common_dimm_parameters(const unsigned int ctrl_num,
+ const dimm_params_t *dimm_params,
common_timing_params_t *outpdimm,
const unsigned int number_of_dimms)
{
printf("ERROR: Mix different RDIMM detected!\n");
/* calculate cas latency for all DDR types */
- if (compute_cas_latency(dimm_params, outpdimm, number_of_dimms))
+ if (compute_cas_latency(ctrl_num, dimm_params,
+ outpdimm, number_of_dimms))
return 1;
/* Determine if all DIMMs ECC capable. */
#if defined(CONFIG_SYS_FSL_DDR2)
if ((outpdimm->lowest_common_spd_caslat < 4) &&
- (picos_to_mclk(trcd_ps) > outpdimm->lowest_common_spd_caslat)) {
- additive_latency = picos_to_mclk(trcd_ps) -
+ (picos_to_mclk(ctrl_num, trcd_ps) >
+ outpdimm->lowest_common_spd_caslat)) {
+ additive_latency = picos_to_mclk(ctrl_num, trcd_ps) -
outpdimm->lowest_common_spd_caslat;
- if (mclk_to_picos(additive_latency) > trcd_ps) {
- additive_latency = picos_to_mclk(trcd_ps);
+ if (mclk_to_picos(ctrl_num, additive_latency) > trcd_ps) {
+ additive_latency = picos_to_mclk(ctrl_num, trcd_ps);
debug("setting additive_latency to %u because it was "
" greater than tRCD_ps\n", additive_latency);
}
*
* AL <= tRCD(min)
*/
- if (mclk_to_picos(additive_latency) > trcd_ps) {
+ if (mclk_to_picos(ctrl_num, additive_latency) > trcd_ps) {
printf("Error: invalid additive latency exceeds tRCD(min).\n");
return 1;
}
&(pinfo->spd_installed_dimms[i][j]);
dimm_params_t *pdimm =
&(pinfo->dimm_params[i][j]);
- retval = compute_dimm_parameters(spd, pdimm, i);
+ retval = compute_dimm_parameters(
+ i, spd, pdimm, j);
#ifdef CONFIG_SYS_DDR_RAW_TIMING
if (!i && !j && retval) {
printf("SPD error on controller %d! "
for (i = first_ctrl; i <= last_ctrl; i++) {
debug("Computing lowest common DIMM"
" parameters for memctl=%u\n", i);
- compute_lowest_common_dimm_parameters(
- pinfo->dimm_params[i],
- &timing_params[i],
- CONFIG_DIMM_SLOTS_PER_CTLR);
+ compute_lowest_common_dimm_parameters
+ (i,
+ pinfo->dimm_params[i],
+ &timing_params[i],
+ CONFIG_DIMM_SLOTS_PER_CTLR);
}
case STEP_GATHER_OPTS:
continue;
}
- compute_fsl_memctl_config_regs(
- &pinfo->memctl_opts[i],
- &ddr_reg[i], &timing_params[i],
- pinfo->dimm_params[i],
- dbw_capacity_adjust[i],
- size_only);
+ compute_fsl_memctl_config_regs
+ (i,
+ &pinfo->memctl_opts[i],
+ &ddr_reg[i], &timing_params[i],
+ pinfo->dimm_params[i],
+ dbw_capacity_adjust[i],
+ size_only);
}
default:
}
}
+#ifdef CONFIG_FSL_DDR_SYNC_REFRESH
+ fsl_ddr_sync_memctl_refresh(first_ctrl, last_ctrl);
+#endif
+
#ifdef CONFIG_PPC
/* program LAWs */
for (i = first_ctrl; i <= last_ctrl; i++) {
bus_width = 3 - ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK)
>> SDRAM_CFG_DBW_SHIFT);
timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 /
- (get_ddr_freq(0) >> 20)) << 1;
+ (get_ddr_freq(ctrl_num) >> 20)) << 1;
#ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
timeout_save = timeout;
#endif
case 1:
out_be32(&ddr->cs1_bnds, regs->cs[csn].bnds);
break;
+#if CONFIG_CHIP_SELECTS_PER_CTRL > 2
case 2:
out_be32(&ddr->cs2_bnds, regs->cs[csn].bnds);
break;
case 3:
out_be32(&ddr->cs3_bnds, regs->cs[csn].bnds);
break;
+#endif
}
clrbits_be32(&ddr->sdram_cfg, 0x2);
}
#endif
/* Global Timing Parameters. */
- debug("mclk_ps = %u ps\n", get_memory_clk_period_ps());
+ debug("mclk_ps = %u ps\n", get_memory_clk_period_ps(ctrl_num));
/* Pick a caslat override. */
popts->cas_latency_override = 0;
* FIXME: width, was considering looking at pdimm->primary_sdram_width
*/
#if defined(CONFIG_SYS_FSL_DDR1)
- popts->tfaw_window_four_activates_ps = mclk_to_picos(1);
+ popts->tfaw_window_four_activates_ps = mclk_to_picos(ctrl_num, 1);
#elif defined(CONFIG_SYS_FSL_DDR2)
/*
if (pdimm[0].n_ranks == 4)
popts->quad_rank_present = 1;
- ddr_freq = get_ddr_freq(0) / 1000000;
+ ddr_freq = get_ddr_freq(ctrl_num) / 1000000;
if (popts->registered_dimm_en) {
popts->rcw_override = 1;
popts->rcw_1 = 0x000a5a00;
* propagation, compute a suitably rounded mclk_ps to compute
* a working memory controller configuration.
*/
-unsigned int get_memory_clk_period_ps(void)
+unsigned int get_memory_clk_period_ps(const unsigned int ctrl_num)
{
- unsigned int data_rate = get_ddr_freq(0);
+ unsigned int data_rate = get_ddr_freq(ctrl_num);
unsigned int result;
/* Round to nearest 10ps, being careful about 64-bit multiply/divide */
}
/* Convert picoseconds into DRAM clock cycles (rounding up if needed). */
-unsigned int picos_to_mclk(unsigned int picos)
+unsigned int picos_to_mclk(const unsigned int ctrl_num, unsigned int picos)
{
unsigned long long clks, clks_rem;
- unsigned long data_rate = get_ddr_freq(0);
+ unsigned long data_rate = get_ddr_freq(ctrl_num);
/* Short circuit for zero picos */
if (!picos)
return (unsigned int) clks;
}
-unsigned int mclk_to_picos(unsigned int mclk)
+unsigned int mclk_to_picos(const unsigned int ctrl_num, unsigned int mclk)
{
- return get_memory_clk_period_ps() * mclk;
+ return get_memory_clk_period_ps(ctrl_num) * mclk;
}
#ifdef CONFIG_PPC
{
detail_board_ddr_info();
}
+
+#ifdef CONFIG_FSL_DDR_SYNC_REFRESH
+#define DDRC_DEBUG20_INIT_DONE 0x80000000
+#define DDRC_DEBUG2_RF 0x00000040
+void fsl_ddr_sync_memctl_refresh(unsigned int first_ctrl,
+ unsigned int last_ctrl)
+{
+ unsigned int i;
+ u32 ddrc_debug20;
+ u32 ddrc_debug2[CONFIG_NUM_DDR_CONTROLLERS] = {};
+ u32 *ddrc_debug2_p[CONFIG_NUM_DDR_CONTROLLERS] = {};
+ struct ccsr_ddr __iomem *ddr;
+
+ for (i = first_ctrl; i <= last_ctrl; i++) {
+ switch (i) {
+ case 0:
+ ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
+ break;
+#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
+ case 1:
+ ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
+ break;
+#endif
+#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
+ case 2:
+ ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
+ break;
+#endif
+#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
+ case 3:
+ ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
+ break;
+#endif
+ default:
+ printf("%s unexpected ctrl = %u\n", __func__, i);
+ return;
+ }
+ ddrc_debug20 = ddr_in32(&ddr->debug[19]);
+ ddrc_debug2_p[i] = &ddr->debug[1];
+ while (!(ddrc_debug20 & DDRC_DEBUG20_INIT_DONE)) {
+ /* keep polling until DDRC init is done */
+ udelay(100);
+ ddrc_debug20 = ddr_in32(&ddr->debug[19]);
+ }
+ ddrc_debug2[i] = ddr_in32(&ddr->debug[1]) | DDRC_DEBUG2_RF;
+ }
+ /*
+ * Sync refresh
+ * This is put together to make sure the refresh reqeusts are sent
+ * closely to each other.
+ */
+ for (i = first_ctrl; i <= last_ctrl; i++)
+ ddr_out32(ddrc_debug2_p[i], ddrc_debug2[i]);
+}
+#endif /* CONFIG_FSL_DDR_SYNC_REFRESH */
esdhc_write32(®s->cmdarg, cmd->cmdarg);
#if defined(CONFIG_FSL_USDHC)
esdhc_write32(®s->mixctrl,
- (esdhc_read32(®s->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F));
+ (esdhc_read32(®s->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F)
+ | (mmc->ddr_mode ? XFERTYP_DDREN : 0));
esdhc_write32(®s->xfertyp, xfertyp & 0xFFFF0000);
#else
esdhc_write32(®s->xfertyp, xfertyp);
if ((sdhc_clk / (div * pre_div)) <= clock)
break;
- pre_div >>= 1;
+ pre_div >>= mmc->ddr_mode ? 2 : 1;
div -= 1;
clk = (pre_div << 8) | (div << 4);
}
cfg->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT | MMC_MODE_HC;
+#ifdef CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
+ cfg->cfg.host_caps |= MMC_MODE_DDR_52MHz;
+#endif
if (cfg->max_bus_width > 0) {
if (cfg->max_bus_width < 8)
This option, if enabled, provides more flexible and linux-like
NAND initialization process.
-if !SPL_BUILD
-
config NAND_DENALI
bool "Support Denali NAND controller"
select SYS_NAND_SELF_INIT
of OOB area before last ECC sector data starts. This is potentially
used to preserve the bad block marker in the OOB area.
-endif
-
-if SPL_BUILD
+if SPL
config SPL_NAND_DENALI
bool "Support Denali NAND controller for SPL"
obj-$(CONFIG_FTMAC100) += ftmac100.o
obj-$(CONFIG_GRETH) += greth.o
obj-$(CONFIG_DRIVER_TI_KEYSTONE_NET) += keystone_net.o
-obj-$(CONFIG_DRIVER_KS8695ETH) += ks8695eth.o
obj-$(CONFIG_KS8851_MLL) += ks8851_mll.o
obj-$(CONFIG_LAN91C96) += lan91c96.o
obj-$(CONFIG_MACB) += macb.o
obj-$(CONFIG_XILINX_LL_TEMAC) += xilinx_ll_temac.o xilinx_ll_temac_mdio.o \
xilinx_ll_temac_fifo.o xilinx_ll_temac_sdma.o
obj-$(CONFIG_ZYNQ_GEM) += zynq_gem.o
-obj-$(CONFIG_FSL_MC_ENET) += fsl_mc/
+obj-$(CONFIG_FSL_MC_ENET) += fsl-mc/
obj-$(CONFIG_VSC9953) += vsc9953.o
--- /dev/null
+#
+# Copyright 2014 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+# Layerscape MC driver
+obj-y += mc.o \
+ mc_sys.o \
+ dpmng.o
--- /dev/null
+/* Copyright 2014 Freescale Semiconductor Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <fsl-mc/fsl_mc_sys.h>
+#include <fsl-mc/fsl_mc_cmd.h>
+#include <fsl-mc/fsl_dpmng.h>
+#include "fsl_dpmng_cmd.h"
+
+int mc_get_version(struct fsl_mc_io *mc_io, struct mc_version *mc_ver_info)
+{
+ struct mc_command cmd = { 0 };
+ int err;
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPMNG_CMDID_GET_VERSION,
+ MC_CMD_PRI_LOW, 0);
+
+ /* send command to mc*/
+ err = mc_send_command(mc_io, &cmd);
+ if (err)
+ return err;
+
+ /* retrieve response parameters */
+ DPMNG_RSP_GET_VERSION(cmd, mc_ver_info);
+
+ return 0;
+}
+
+int dpmng_reset_aiop(struct fsl_mc_io *mc_io, int container_id,
+ int aiop_tile_id)
+{
+ struct mc_command cmd = { 0 };
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPMNG_CMDID_RESET_AIOP,
+ MC_CMD_PRI_LOW, 0);
+ DPMNG_CMD_RESET_AIOP(cmd, container_id, aiop_tile_id);
+
+ /* send command to mc*/
+ return mc_send_command(mc_io, &cmd);
+}
+
+int dpmng_load_aiop(struct fsl_mc_io *mc_io,
+ int container_id,
+ int aiop_tile_id,
+ uint64_t img_iova,
+ uint32_t img_size)
+{
+ struct mc_command cmd = { 0 };
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPMNG_CMDID_LOAD_AIOP,
+ MC_CMD_PRI_LOW,
+ 0);
+ DPMNG_CMD_LOAD_AIOP(cmd, container_id, aiop_tile_id, img_size,
+ img_iova);
+
+ /* send command to mc*/
+ return mc_send_command(mc_io, &cmd);
+}
+
+int dpmng_run_aiop(struct fsl_mc_io *mc_io,
+ int container_id,
+ int aiop_tile_id,
+ const struct dpmng_aiop_run_cfg *cfg)
+{
+ struct mc_command cmd = { 0 };
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPMNG_CMDID_RUN_AIOP,
+ MC_CMD_PRI_LOW,
+ 0);
+ DPMNG_CMD_RUN_AIOP(cmd, container_id, aiop_tile_id, cfg);
+
+ /* send command to mc*/
+ return mc_send_command(mc_io, &cmd);
+}
+
+int dpmng_reset_mc_portal(struct fsl_mc_io *mc_io)
+{
+ struct mc_command cmd = { 0 };
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPMNG_CMDID_RESET_MC_PORTAL,
+ MC_CMD_PRI_LOW,
+ 0);
+
+ /* send command to mc*/
+ return mc_send_command(mc_io, &cmd);
+}
--- /dev/null
+/* Copyright 2014 Freescale Semiconductor Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef __FSL_DPMNG_CMD_H
+#define __FSL_DPMNG_CMD_H
+
+/* Command IDs */
+#define DPMNG_CMDID_GET_VERSION 0x831
+#define DPMNG_CMDID_RESET_AIOP 0x832
+#define DPMNG_CMDID_LOAD_AIOP 0x833
+#define DPMNG_CMDID_RUN_AIOP 0x834
+#define DPMNG_CMDID_RESET_MC_PORTAL 0x835
+
+/* cmd, param, offset, width, type, arg_name */
+#define DPMNG_RSP_GET_VERSION(cmd, mc_ver_info) \
+do { \
+ MC_RSP_OP(cmd, 0, 0, 32, uint32_t, mc_ver_info->revision); \
+ MC_RSP_OP(cmd, 0, 32, 32, uint32_t, mc_ver_info->major); \
+ MC_RSP_OP(cmd, 1, 0, 32, uint32_t, mc_ver_info->minor); \
+} while (0)
+
+/* cmd, param, offset, width, type, arg_name */
+#define DPMNG_CMD_RESET_AIOP(cmd, container_id, aiop_tile_id) \
+do { \
+ MC_CMD_OP(cmd, 0, 0, 32, int, aiop_tile_id); \
+ MC_CMD_OP(cmd, 0, 32, 32, int, container_id); \
+} while (0)
+
+/* cmd, param, offset, width, type, arg_name */
+#define DPMNG_CMD_LOAD_AIOP(cmd, container_id, aiop_tile_id, img_size, \
+ img_iova) \
+do { \
+ MC_CMD_OP(cmd, 0, 0, 32, int, aiop_tile_id); \
+ MC_CMD_OP(cmd, 0, 32, 32, int, container_id); \
+ MC_CMD_OP(cmd, 1, 0, 32, uint32_t, img_size); \
+ MC_CMD_OP(cmd, 2, 0, 64, uint64_t, img_iova); \
+} while (0)
+
+/* cmd, param, offset, width, type, arg_name */
+#define DPMNG_CMD_RUN_AIOP(cmd, container_id, aiop_tile_id, cfg) \
+do { \
+ MC_CMD_OP(cmd, 0, 0, 32, int, aiop_tile_id); \
+ MC_CMD_OP(cmd, 0, 32, 32, int, container_id); \
+ MC_CMD_OP(cmd, 1, 0, 32, uint32_t, cfg->cores_mask); \
+ MC_CMD_OP(cmd, 2, 0, 64, uint64_t, cfg->options); \
+} while (0)
+
+#endif /* __FSL_DPMNG_CMD_H */
--- /dev/null
+/*
+ * Copyright (C) 2014 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <errno.h>
+#include <asm/io.h>
+#include <fsl-mc/fsl_mc.h>
+#include <fsl-mc/fsl_mc_sys.h>
+#include <fsl-mc/fsl_dpmng.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+static int mc_boot_status;
+
+/**
+ * Copying MC firmware or DPL image to DDR
+ */
+static int mc_copy_image(const char *title,
+ u64 image_addr, u32 image_size, u64 mc_ram_addr)
+{
+ debug("%s copied to address %p\n", title, (void *)mc_ram_addr);
+ memcpy((void *)mc_ram_addr, (void *)image_addr, image_size);
+ return 0;
+}
+
+/**
+ * MC firmware FIT image parser checks if the image is in FIT
+ * format, verifies integrity of the image and calculates
+ * raw image address and size values.
+ * Returns 0 on success and a negative errno on error.
+ * task fail.
+ **/
+int parse_mc_firmware_fit_image(const void **raw_image_addr,
+ size_t *raw_image_size)
+{
+ int format;
+ void *fit_hdr;
+ int node_offset;
+ const void *data;
+ size_t size;
+ const char *uname = "firmware";
+
+ /* Check if the image is in NOR flash */
+#ifdef CONFIG_SYS_LS_MC_FW_IN_NOR
+ fit_hdr = (void *)CONFIG_SYS_LS_MC_FW_ADDR;
+#else
+#error "No CONFIG_SYS_LS_MC_FW_IN_xxx defined"
+#endif
+
+ /* Check if Image is in FIT format */
+ format = genimg_get_format(fit_hdr);
+
+ if (format != IMAGE_FORMAT_FIT) {
+ printf("fsl-mc: ERROR: Bad firmware image (not a FIT image)\n");
+ return -EINVAL;
+ }
+
+ if (!fit_check_format(fit_hdr)) {
+ printf("fsl-mc: ERROR: Bad firmware image (bad FIT header)\n");
+ return -EINVAL;
+ }
+
+ node_offset = fit_image_get_node(fit_hdr, uname);
+
+ if (node_offset < 0) {
+ printf("fsl-mc: ERROR: Bad firmware image (missing subimage)\n");
+ return -ENOENT;
+ }
+
+ /* Verify MC firmware image */
+ if (!(fit_image_verify(fit_hdr, node_offset))) {
+ printf("fsl-mc: ERROR: Bad firmware image (bad CRC)\n");
+ return -EINVAL;
+ }
+
+ /* Get address and size of raw image */
+ fit_image_get_data(fit_hdr, node_offset, &data, &size);
+
+ *raw_image_addr = data;
+ *raw_image_size = size;
+
+ return 0;
+}
+
+int mc_init(bd_t *bis)
+{
+ int error = 0;
+ int timeout = 200000;
+ struct mc_ccsr_registers __iomem *mc_ccsr_regs = MC_CCSR_BASE_ADDR;
+ u64 mc_ram_addr;
+ u64 mc_dpl_offset;
+ u32 reg_gsr;
+ u32 mc_fw_boot_status;
+ void *dpl_fdt_hdr;
+ int dpl_size;
+ const void *raw_image_addr;
+ size_t raw_image_size = 0;
+ struct fsl_mc_io mc_io;
+ int portal_id;
+ struct mc_version mc_ver_info;
+
+ /*
+ * The MC private DRAM block was already carved at the end of DRAM
+ * by board_init_f() using CONFIG_SYS_MEM_TOP_HIDE:
+ */
+ if (gd->bd->bi_dram[1].start) {
+ mc_ram_addr =
+ gd->bd->bi_dram[1].start + gd->bd->bi_dram[1].size;
+ } else {
+ mc_ram_addr =
+ gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size;
+ }
+
+ /*
+ * Management Complex cores should be held at reset out of POR.
+ * U-boot should be the first software to touch MC. To be safe,
+ * we reset all cores again by setting GCR1 to 0. It doesn't do
+ * anything if they are held at reset. After we setup the firmware
+ * we kick off MC by deasserting the reset bit for core 0, and
+ * deasserting the reset bits for Command Portal Managers.
+ * The stop bits are not touched here. They are used to stop the
+ * cores when they are active. Setting stop bits doesn't stop the
+ * cores from fetching instructions when they are released from
+ * reset.
+ */
+ out_le32(&mc_ccsr_regs->reg_gcr1, 0);
+ dmb();
+
+ error = parse_mc_firmware_fit_image(&raw_image_addr, &raw_image_size);
+ if (error != 0)
+ goto out;
+ /*
+ * Load the MC FW at the beginning of the MC private DRAM block:
+ */
+ mc_copy_image("MC Firmware",
+ (u64)raw_image_addr, raw_image_size, mc_ram_addr);
+
+ /*
+ * Get address and size of the DPL blob stored in flash:
+ */
+#ifdef CONFIG_SYS_LS_MC_DPL_IN_NOR
+ dpl_fdt_hdr = (void *)CONFIG_SYS_LS_MC_DPL_ADDR;
+#else
+#error "No CONFIG_SYS_LS_MC_DPL_IN_xxx defined"
+#endif
+
+ error = fdt_check_header(dpl_fdt_hdr);
+ if (error != 0) {
+ printf("fsl-mc: ERROR: Bad DPL image (bad header)\n");
+ goto out;
+ }
+
+ dpl_size = fdt_totalsize(dpl_fdt_hdr);
+ if (dpl_size > CONFIG_SYS_LS_MC_DPL_MAX_LENGTH) {
+ printf("fsl-mc: ERROR: Bad DPL image (too large: %d)\n",
+ dpl_size);
+ error = -EINVAL;
+ goto out;
+ }
+
+ /*
+ * Calculate offset in the MC private DRAM block at which the MC DPL
+ * blob is to be placed:
+ */
+#ifdef CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET
+ BUILD_BUG_ON((CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET & 0x3) != 0 ||
+ CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET > 0xffffffff);
+
+ mc_dpl_offset = CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET;
+#else
+ mc_dpl_offset = mc_get_dram_block_size() -
+ roundup(CONFIG_SYS_LS_MC_DPL_MAX_LENGTH, 4096);
+
+ if ((mc_dpl_offset & 0x3) != 0 || mc_dpl_offset > 0xffffffff) {
+ printf("%s: Invalid MC DPL offset: %llu\n",
+ __func__, mc_dpl_offset);
+ error = -EINVAL;
+ goto out;
+ }
+#endif
+
+ /*
+ * Load the MC DPL blob at the far end of the MC private DRAM block:
+ *
+ * TODO: Should we place the DPL at a different location to match
+ * assumptions of MC firmware about its memory layout?
+ */
+ mc_copy_image("MC DPL blob",
+ (u64)dpl_fdt_hdr, dpl_size, mc_ram_addr + mc_dpl_offset);
+
+ debug("mc_ccsr_regs %p\n", mc_ccsr_regs);
+
+ /*
+ * Tell MC where the MC Firmware image was loaded in DDR:
+ */
+ out_le32(&mc_ccsr_regs->reg_mcfbalr, (u32)mc_ram_addr);
+ out_le32(&mc_ccsr_regs->reg_mcfbahr, (u32)((u64)mc_ram_addr >> 32));
+ out_le32(&mc_ccsr_regs->reg_mcfapr, MCFAPR_BYPASS_ICID_MASK);
+
+ /*
+ * Tell MC where the DPL blob was loaded in DDR, by indicating
+ * its offset relative to the beginning of the DDR block
+ * allocated to the MC firmware. The MC firmware is responsible
+ * for checking that there is no overlap between the DPL blob
+ * and the runtime heap and stack of the MC firmware itself.
+ *
+ * NOTE: bits [31:2] of this offset need to be stored in bits [29:0] of
+ * the GSR MC CCSR register. So, this offset is assumed to be 4-byte
+ * aligned.
+ * Care must be taken not to write 1s into bits 31 and 30 of the GSR in
+ * this case as the SoC COP or PIC will be signaled.
+ */
+ out_le32(&mc_ccsr_regs->reg_gsr, (u32)(mc_dpl_offset >> 2));
+
+ printf("\nfsl-mc: Booting Management Complex ...\n");
+
+ /*
+ * Deassert reset and release MC core 0 to run
+ */
+ out_le32(&mc_ccsr_regs->reg_gcr1, GCR1_P1_DE_RST | GCR1_M_ALL_DE_RST);
+ dmb();
+ debug("Polling mc_ccsr_regs->reg_gsr ...\n");
+
+ for (;;) {
+ reg_gsr = in_le32(&mc_ccsr_regs->reg_gsr);
+ mc_fw_boot_status = (reg_gsr & GSR_FS_MASK);
+ if (mc_fw_boot_status & 0x1)
+ break;
+
+ udelay(1000); /* throttle polling */
+ if (timeout-- <= 0)
+ break;
+ }
+
+ if (timeout <= 0) {
+ printf("fsl-mc: timeout booting management complex firmware\n");
+
+ /* TODO: Get an error status from an MC CCSR register */
+ error = -ETIMEDOUT;
+ goto out;
+ }
+
+ if (mc_fw_boot_status != 0x1) {
+ /*
+ * TODO: Identify critical errors from the GSR register's FS
+ * field and for those errors, set error to -ENODEV or other
+ * appropriate errno, so that the status property is set to
+ * failure in the fsl,dprc device tree node.
+ */
+ printf("fsl-mc: WARNING: Firmware booted with error (GSR: %#x)\n",
+ reg_gsr);
+ }
+
+ /*
+ * TODO: need to obtain the portal_id for the root container from the
+ * DPL
+ */
+ portal_id = 0;
+
+ /*
+ * Check that the MC firmware is responding portal commands:
+ */
+ mc_io.mmio_regs = SOC_MC_PORTAL_ADDR(portal_id);
+ debug("Checking access to MC portal of root DPRC container (portal_id %d, portal physical addr %p)\n",
+ portal_id, mc_io.mmio_regs);
+
+ error = mc_get_version(&mc_io, &mc_ver_info);
+ if (error != 0) {
+ printf("fsl-mc: ERROR: Firmware version check failed (error: %d)\n",
+ error);
+ goto out;
+ }
+
+ if (MC_VER_MAJOR != mc_ver_info.major)
+ printf("fsl-mc: ERROR: Firmware major version mismatch (found: %d, expected: %d)\n",
+ mc_ver_info.major, MC_VER_MAJOR);
+
+ if (MC_VER_MINOR != mc_ver_info.minor)
+ printf("fsl-mc: WARNING: Firmware minor version mismatch (found: %d, expected: %d)\n",
+ mc_ver_info.minor, MC_VER_MINOR);
+
+ printf("fsl-mc: Management Complex booted (version: %d.%d.%d, boot status: %#x)\n",
+ mc_ver_info.major, mc_ver_info.minor, mc_ver_info.revision,
+ mc_fw_boot_status);
+out:
+ if (error != 0)
+ mc_boot_status = -error;
+ else
+ mc_boot_status = 0;
+
+ return error;
+}
+
+int get_mc_boot_status(void)
+{
+ return mc_boot_status;
+}
+
+/**
+ * Return the actual size of the MC private DRAM block.
+ *
+ * NOTE: For now this function always returns the minimum required size,
+ * However, in the future, the actual size may be obtained from an environment
+ * variable.
+ */
+unsigned long mc_get_dram_block_size(void)
+{
+ return CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE;
+}
--- /dev/null
+/*
+ * Freescale Layerscape MC I/O wrapper
+ *
+ * Copyright (C) 2014 Freescale Semiconductor, Inc.
+ * Author: German Rivera <German.Rivera@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <fsl-mc/fsl_mc_sys.h>
+#include <fsl-mc/fsl_mc_cmd.h>
+#include <common.h>
+#include <errno.h>
+#include <asm/io.h>
+
+#define MC_CMD_HDR_READ_CMDID(_hdr) \
+ ((uint16_t)u64_dec((_hdr), MC_CMD_HDR_CMDID_O, MC_CMD_HDR_CMDID_S))
+
+/**
+ * mc_send_command - Send MC command and wait for response
+ *
+ * @mc_io: Pointer to MC I/O object to be used
+ * @cmd: MC command buffer. On input, it contains the command to send to the MC.
+ * On output, it contains the response from the MC if any.
+ *
+ * Depending on the sharing option specified when creating the MC portal
+ * wrapper, this function will use a spinlock or mutex to ensure exclusive
+ * access to the MC portal from the point when the command is sent until a
+ * response is received from the MC.
+ */
+int mc_send_command(struct fsl_mc_io *mc_io,
+ struct mc_command *cmd)
+{
+ enum mc_cmd_status status;
+ int timeout = 2000;
+
+ mc_write_command(mc_io->mmio_regs, cmd);
+
+ for ( ; ; ) {
+ status = mc_read_response(mc_io->mmio_regs, cmd);
+ if (status != MC_CMD_STATUS_READY)
+ break;
+
+ if (--timeout == 0) {
+ printf("Error: Timeout waiting for MC response\n");
+ return -ETIMEDOUT;
+ }
+
+ udelay(500);
+ }
+
+ if (status != MC_CMD_STATUS_OK) {
+ printf("Error: MC command failed (portal: %p, obj handle: %#x, command: %#x, status: %#x)\n",
+ mc_io->mmio_regs,
+ (unsigned int)MC_CMD_HDR_READ_AUTHID(cmd->header),
+ (unsigned int)MC_CMD_HDR_READ_CMDID(cmd->header),
+ (unsigned int)status);
+
+ return -EIO;
+ }
+
+ return 0;
+}
+++ /dev/null
-#
-# Copyright 2014 Freescale Semiconductor, Inc.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-# Layerscape MC driver
-obj-y += mc.o
+++ /dev/null
-/*
- * Copyright (C) 2014 Freescale Semiconductor
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <errno.h>
-#include <asm/io.h>
-#include <fsl_mc.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-static int mc_boot_status;
-
-/**
- * Copying MC firmware or DPL image to DDR
- */
-static int mc_copy_image(const char *title,
- u64 image_addr, u32 image_size, u64 mc_ram_addr)
-{
- debug("%s copied to address %p\n", title, (void *)mc_ram_addr);
- memcpy((void *)mc_ram_addr, (void *)image_addr, image_size);
- return 0;
-}
-
-/**
- * MC firmware FIT image parser checks if the image is in FIT
- * format, verifies integrity of the image and calculates
- * raw image address and size values.
- * Returns 0 if success and 1 if any of the above mentioned
- * task fail.
- **/
-
-int parse_mc_firmware_fit_image(const void **raw_image_addr,
- size_t *raw_image_size)
-{
- int format;
- void *fit_hdr;
- int node_offset;
- const void *data;
- size_t size;
- const char *uname = "firmware";
-
- /* Check if the image is in NOR flash*/
-#ifdef CONFIG_SYS_LS_MC_FW_IN_NOR
- fit_hdr = (void *)CONFIG_SYS_LS_MC_FW_ADDR;
-#else
-#error "No CONFIG_SYS_LS_MC_FW_IN_xxx defined"
-#endif
-
- /* Check if Image is in FIT format */
- format = genimg_get_format(fit_hdr);
-
- if (format != IMAGE_FORMAT_FIT) {
- debug("Not a FIT image\n");
- return 1;
- }
-
- if (!fit_check_format(fit_hdr)) {
- debug("Bad FIT image format\n");
- return 1;
- }
-
- node_offset = fit_image_get_node(fit_hdr, uname);
-
- if (node_offset < 0) {
- debug("Can not find %s subimage\n", uname);
- return 1;
- }
-
- /* Verify MC firmware image */
- if (!(fit_image_verify(fit_hdr, node_offset))) {
- debug("Bad MC firmware hash");
- return 1;
- }
-
- /* Get address and size of raw image */
- fit_image_get_data(fit_hdr, node_offset, &data, &size);
-
- *raw_image_addr = data;
- *raw_image_size = size;
-
- return 0;
-}
-
-int mc_init(bd_t *bis)
-{
- int error = 0;
- int timeout = 200000;
- struct mc_ccsr_registers __iomem *mc_ccsr_regs = MC_CCSR_BASE_ADDR;
- u64 mc_ram_addr;
- u64 mc_dpl_offset;
- u32 reg_gsr;
- u32 mc_fw_boot_status;
- void *fdt_hdr;
- int dpl_size;
- const void *raw_image_addr;
- size_t raw_image_size = 0;
-
- BUILD_BUG_ON(CONFIG_SYS_LS_MC_FW_LENGTH % 4 != 0);
-
- /*
- * The MC private DRAM block was already carved at the end of DRAM
- * by board_init_f() using CONFIG_SYS_MEM_TOP_HIDE:
- */
- if (gd->bd->bi_dram[1].start) {
- mc_ram_addr =
- gd->bd->bi_dram[1].start + gd->bd->bi_dram[1].size;
- } else {
- mc_ram_addr =
- gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size;
- }
-
- /*
- * Management Complex cores should be held at reset out of POR.
- * U-boot should be the first software to touch MC. To be safe,
- * we reset all cores again by setting GCR1 to 0. It doesn't do
- * anything if they are held at reset. After we setup the firmware
- * we kick off MC by deasserting the reset bit for core 0, and
- * deasserting the reset bits for Command Portal Managers.
- * The stop bits are not touched here. They are used to stop the
- * cores when they are active. Setting stop bits doesn't stop the
- * cores from fetching instructions when they are released from
- * reset.
- */
- out_le32(&mc_ccsr_regs->reg_gcr1, 0);
- dmb();
-
- error = parse_mc_firmware_fit_image(&raw_image_addr, &raw_image_size);
- if (error != 0)
- goto out;
- /*
- * Load the MC FW at the beginning of the MC private DRAM block:
- */
- mc_copy_image(
- "MC Firmware",
- (u64)raw_image_addr,
- raw_image_size,
- mc_ram_addr);
-
- /*
- * Calculate offset in the MC private DRAM block at which the MC DPL
- * blob is to be placed:
- */
-#ifdef CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET
- BUILD_BUG_ON(
- (CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET & 0x3) != 0 ||
- CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET > 0xffffffff);
-
- mc_dpl_offset = CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET;
-#else
- mc_dpl_offset = mc_get_dram_block_size() -
- roundup(CONFIG_SYS_LS_MC_DPL_LENGTH, 4096);
-
- if ((mc_dpl_offset & 0x3) != 0 || mc_dpl_offset > 0xffffffff) {
- printf("%s: Invalid MC DPL offset: %llu\n",
- __func__, mc_dpl_offset);
- error = -EINVAL;
- goto out;
- }
-#endif
-
- /* Check if DPL image is in NOR flash */
-#ifdef CONFIG_SYS_LS_MC_DPL_IN_NOR
- fdt_hdr = (void *)CONFIG_SYS_LS_MC_DPL_ADDR;
-#else
-#error "No CONFIG_SYS_LS_MC_DPL_IN_xxx defined"
-#endif
-
- dpl_size = fdt_totalsize(fdt_hdr);
-
- /*
- * Load the MC DPL blob at the far end of the MC private DRAM block:
- */
- mc_copy_image(
- "MC DPL blob",
- (u64)fdt_hdr,
- dpl_size,
- mc_ram_addr + mc_dpl_offset);
-
- debug("mc_ccsr_regs %p\n", mc_ccsr_regs);
-
- /*
- * Tell MC where the MC Firmware image was loaded in DDR:
- */
- out_le32(&mc_ccsr_regs->reg_mcfbalr, (u32)mc_ram_addr);
- out_le32(&mc_ccsr_regs->reg_mcfbahr, (u32)((u64)mc_ram_addr >> 32));
- out_le32(&mc_ccsr_regs->reg_mcfapr, MCFAPR_BYPASS_ICID_MASK);
-
- /*
- * Tell MC where the DPL blob was loaded in DDR, by indicating
- * its offset relative to the beginning of the DDR block
- * allocated to the MC firmware. The MC firmware is responsible
- * for checking that there is no overlap between the DPL blob
- * and the runtime heap and stack of the MC firmware itself.
- *
- * NOTE: bits [31:2] of this offset need to be stored in bits [29:0] of
- * the GSR MC CCSR register. So, this offset is assumed to be 4-byte
- * aligned.
- * Care must be taken not to write 1s into bits 31 and 30 of the GSR in
- * this case as the SoC COP or PIC will be signaled.
- */
- out_le32(&mc_ccsr_regs->reg_gsr, (u32)(mc_dpl_offset >> 2));
-
- /*
- * Deassert reset and release MC core 0 to run
- */
- out_le32(&mc_ccsr_regs->reg_gcr1, GCR1_P1_DE_RST | GCR1_M_ALL_DE_RST);
- dmb();
- debug("Polling mc_ccsr_regs->reg_gsr ...\n");
-
- for (;;) {
- reg_gsr = in_le32(&mc_ccsr_regs->reg_gsr);
- mc_fw_boot_status = (reg_gsr & GSR_FS_MASK);
- if (mc_fw_boot_status & 0x1)
- break;
-
- udelay(1000); /* throttle polling */
- if (timeout-- <= 0)
- break;
- }
-
- if (timeout <= 0) {
- printf("%s: timeout booting management complex firmware\n",
- __func__);
-
- /* TODO: Get an error status from an MC CCSR register */
- error = -ETIMEDOUT;
- goto out;
- }
-
- printf("Management complex booted (boot status: %#x)\n",
- mc_fw_boot_status);
-
- if (mc_fw_boot_status != 0x1) {
- /*
- * TODO: Identify critical errors from the GSR register's FS
- * field and for those errors, set error to -ENODEV or other
- * appropriate errno, so that the status property is set to
- * failure in the fsl,dprc device tree node.
- */
- }
-
-out:
- if (error != 0)
- mc_boot_status = -error;
- else
- mc_boot_status = 0;
-
- return error;
-}
-
-int get_mc_boot_status(void)
-{
- return mc_boot_status;
-}
-
-/**
- * Return the actual size of the MC private DRAM block.
- *
- * NOTE: For now this function always returns the minimum required size,
- * However, in the future, the actual size may be obtained from an environment
- * variable.
- */
-unsigned long mc_get_dram_block_size(void)
-{
- return CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE;
-}
+++ /dev/null
-/*
- * ks8695eth.c -- KS8695 ethernet driver
- *
- * (C) Copyright 2004-2005, Greg Ungerer <greg.ungerer@opengear.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/****************************************************************************/
-
-#include <common.h>
-#include <malloc.h>
-#include <net.h>
-#include <asm/io.h>
-#include <asm/arch/platform.h>
-
-/****************************************************************************/
-
-/*
- * Hardware register access to the KS8695 LAN ethernet port
- * (well, it is the 4 port switch really).
- */
-#define ks8695_read(a) *((volatile unsigned long *) (KS8695_IO_BASE + (a)))
-#define ks8695_write(a,v) *((volatile unsigned long *) (KS8695_IO_BASE + (a))) = (v)
-
-/****************************************************************************/
-
-/*
- * Define the descriptor in-memory data structures.
- */
-struct ks8695_txdesc {
- uint32_t owner;
- uint32_t ctrl;
- uint32_t addr;
- uint32_t next;
-};
-
-struct ks8695_rxdesc {
- uint32_t status;
- uint32_t ctrl;
- uint32_t addr;
- uint32_t next;
-};
-
-/****************************************************************************/
-
-/*
- * Allocate local data structures to use for receiving and sending
- * packets. Just to keep it all nice and simple.
- */
-
-#define TXDESCS 4
-#define RXDESCS 4
-#define BUFSIZE 2048
-
-volatile struct ks8695_txdesc ks8695_tx[TXDESCS] __attribute__((aligned(256)));
-volatile struct ks8695_rxdesc ks8695_rx[RXDESCS] __attribute__((aligned(256)));
-volatile uint8_t ks8695_bufs[BUFSIZE*(TXDESCS+RXDESCS)] __attribute__((aligned(2048)));;
-
-/****************************************************************************/
-
-/*
- * Ideally we want to use the MAC address stored in flash.
- * But we do some sanity checks in case they are not present
- * first.
- */
-unsigned char eth_mac[] = {
- 0x00, 0x13, 0xc6, 0x00, 0x00, 0x00
-};
-
-void ks8695_getmac(void)
-{
- unsigned char *fp;
- int i;
-
- /* Check if flash MAC is valid */
- fp = (unsigned char *) 0x0201c000;
- for (i = 0; (i < 6); i++) {
- if ((fp[i] != 0) && (fp[i] != 0xff))
- break;
- }
-
- /* If we found a valid looking MAC address then use it */
- if (i < 6)
- memcpy(ð_mac[0], fp, 6);
-}
-
-/****************************************************************************/
-
-static int ks8695_eth_init(struct eth_device *dev, bd_t *bd)
-{
- int i;
-
- debug ("%s(%d): eth_reset()\n", __FILE__, __LINE__);
-
- /* Reset the ethernet engines first */
- ks8695_write(KS8695_LAN_DMA_TX, 0x80000000);
- ks8695_write(KS8695_LAN_DMA_RX, 0x80000000);
-
- ks8695_getmac();
-
- /* Set MAC address */
- ks8695_write(KS8695_LAN_MAC_LOW, (eth_mac[5] | (eth_mac[4] << 8) |
- (eth_mac[3] << 16) | (eth_mac[2] << 24)));
- ks8695_write(KS8695_LAN_MAC_HIGH, (eth_mac[1] | (eth_mac[0] << 8)));
-
- /* Turn the 4 port switch on */
- i = ks8695_read(KS8695_SWITCH_CTRL0);
- ks8695_write(KS8695_SWITCH_CTRL0, (i | 0x1));
- /* ks8695_write(KS8695_WAN_CONTROL, 0x3f000066); */
-
- /* Initialize descriptor rings */
- for (i = 0; (i < TXDESCS); i++) {
- ks8695_tx[i].owner = 0;
- ks8695_tx[i].ctrl = 0;
- ks8695_tx[i].addr = (uint32_t) &ks8695_bufs[i*BUFSIZE];
- ks8695_tx[i].next = (uint32_t) &ks8695_tx[i+1];
- }
- ks8695_tx[TXDESCS-1].ctrl = 0x02000000;
- ks8695_tx[TXDESCS-1].next = (uint32_t) &ks8695_tx[0];
-
- for (i = 0; (i < RXDESCS); i++) {
- ks8695_rx[i].status = 0x80000000;
- ks8695_rx[i].ctrl = BUFSIZE - 4;
- ks8695_rx[i].addr = (uint32_t) &ks8695_bufs[(i+TXDESCS)*BUFSIZE];
- ks8695_rx[i].next = (uint32_t) &ks8695_rx[i+1];
- }
- ks8695_rx[RXDESCS-1].ctrl |= 0x00080000;
- ks8695_rx[RXDESCS-1].next = (uint32_t) &ks8695_rx[0];
-
- /* The KS8695 is pretty slow reseting the ethernets... */
- udelay(2000000);
-
- /* Enable the ethernet engine */
- ks8695_write(KS8695_LAN_TX_LIST, (uint32_t) &ks8695_tx[0]);
- ks8695_write(KS8695_LAN_RX_LIST, (uint32_t) &ks8695_rx[0]);
- ks8695_write(KS8695_LAN_DMA_TX, 0x3);
- ks8695_write(KS8695_LAN_DMA_RX, 0x71);
- ks8695_write(KS8695_LAN_DMA_RX_START, 0x1);
-
- printf("KS8695 ETHERNET: %pM\n", eth_mac);
- return 0;
-}
-
-/****************************************************************************/
-
-static void ks8695_eth_halt(struct eth_device *dev)
-{
- debug ("%s(%d): eth_halt()\n", __FILE__, __LINE__);
-
- /* Reset the ethernet engines */
- ks8695_write(KS8695_LAN_DMA_TX, 0x80000000);
- ks8695_write(KS8695_LAN_DMA_RX, 0x80000000);
-}
-
-/****************************************************************************/
-
-static int ks8695_eth_recv(struct eth_device *dev)
-{
- volatile struct ks8695_rxdesc *dp;
- int i, len = 0;
-
- debug ("%s(%d): eth_rx()\n", __FILE__, __LINE__);
-
- for (i = 0; (i < RXDESCS); i++) {
- dp= &ks8695_rx[i];
- if ((dp->status & 0x80000000) == 0) {
- len = (dp->status & 0x7ff) - 4;
- NetReceive((void *) dp->addr, len);
- dp->status = 0x80000000;
- ks8695_write(KS8695_LAN_DMA_RX_START, 0x1);
- break;
- }
- }
-
- return len;
-}
-
-/****************************************************************************/
-
-static int ks8695_eth_send(struct eth_device *dev, void *packet, int len)
-{
- volatile struct ks8695_txdesc *dp;
- static int next = 0;
-
- debug ("%s(%d): eth_send(packet=%p,len=%d)\n", __FILE__, __LINE__,
- packet, len);
-
- dp = &ks8695_tx[next];
- memcpy((void *) dp->addr, (void *) packet, len);
-
- if (len < 64) {
- memset((void *) (dp->addr + len), 0, 64-len);
- len = 64;
- }
-
- dp->ctrl = len | 0xe0000000;
- dp->owner = 0x80000000;
-
- ks8695_write(KS8695_LAN_DMA_TX, 0x3);
- ks8695_write(KS8695_LAN_DMA_TX_START, 0x1);
-
- if (++next >= TXDESCS)
- next = 0;
-
- return 0;
-}
-
-/****************************************************************************/
-
-int ks8695_eth_initialize(void)
-{
- struct eth_device *dev;
-
- dev = malloc(sizeof(*dev));
- if (dev == NULL)
- return -1;
- memset(dev, 0, sizeof(*dev));
-
- dev->iobase = KS8695_IO_BASE + KS8695_LAN_DMA_TX;
- dev->init = ks8695_eth_init;
- dev->halt = ks8695_eth_halt;
- dev->send = ks8695_eth_send;
- dev->recv = ks8695_eth_recv;
- strcpy(dev->name, "ks8695eth");
-
- eth_register(dev);
- return 0;
-}
/*
- * Copyright 2014 Freescale Semiconductor, Inc.
+ * Copyright 2014-2015 Freescale Semiconductor, Inc.
* Layerscape PCIe driver
*
* SPDX-License-Identifier: GPL-2.0+
#include <asm/arch/fsl_serdes.h>
#include <pci.h>
#include <asm/io.h>
+#include <errno.h>
+#include <malloc.h>
#include <asm/pcie_layerscape.h>
+#ifndef CONFIG_SYS_PCI_MEMORY_BUS
+#define CONFIG_SYS_PCI_MEMORY_BUS CONFIG_SYS_SDRAM_BASE
+#endif
+
+#ifndef CONFIG_SYS_PCI_MEMORY_PHYS
+#define CONFIG_SYS_PCI_MEMORY_PHYS CONFIG_SYS_SDRAM_BASE
+#endif
+
+#ifndef CONFIG_SYS_PCI_MEMORY_SIZE
+#define CONFIG_SYS_PCI_MEMORY_SIZE (2 * 1024 * 1024 * 1024UL) /* 2G */
+#endif
+
+/* iATU registers */
+#define PCIE_ATU_VIEWPORT 0x900
+#define PCIE_ATU_REGION_INBOUND (0x1 << 31)
+#define PCIE_ATU_REGION_OUTBOUND (0x0 << 31)
+#define PCIE_ATU_REGION_INDEX0 (0x0 << 0)
+#define PCIE_ATU_REGION_INDEX1 (0x1 << 0)
+#define PCIE_ATU_REGION_INDEX2 (0x2 << 0)
+#define PCIE_ATU_REGION_INDEX3 (0x3 << 0)
+#define PCIE_ATU_CR1 0x904
+#define PCIE_ATU_TYPE_MEM (0x0 << 0)
+#define PCIE_ATU_TYPE_IO (0x2 << 0)
+#define PCIE_ATU_TYPE_CFG0 (0x4 << 0)
+#define PCIE_ATU_TYPE_CFG1 (0x5 << 0)
+#define PCIE_ATU_CR2 0x908
+#define PCIE_ATU_ENABLE (0x1 << 31)
+#define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30)
+#define PCIE_ATU_LOWER_BASE 0x90C
+#define PCIE_ATU_UPPER_BASE 0x910
+#define PCIE_ATU_LIMIT 0x914
+#define PCIE_ATU_LOWER_TARGET 0x918
+#define PCIE_ATU_BUS(x) (((x) & 0xff) << 24)
+#define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19)
+#define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
+#define PCIE_ATU_UPPER_TARGET 0x91C
+
+#define PCIE_LINK_CAP 0x7c
+#define PCIE_LINK_SPEED_MASK 0xf
+#define PCIE_LINK_STA 0x82
+
+#define PCIE_DBI_SIZE (4 * 1024) /* 4K */
+
+struct ls_pcie {
+ int idx;
+ void __iomem *dbi;
+ void __iomem *va_cfg0;
+ void __iomem *va_cfg1;
+ struct pci_controller hose;
+};
+
+struct ls_pcie_info {
+ unsigned long regs;
+ int pci_num;
+ u64 cfg0_phys;
+ u64 cfg0_size;
+ u64 cfg1_phys;
+ u64 cfg1_size;
+ u64 mem_bus;
+ u64 mem_phys;
+ u64 mem_size;
+ u64 io_bus;
+ u64 io_phys;
+ u64 io_size;
+};
+
+#define SET_LS_PCIE_INFO(x, num) \
+{ \
+ x.regs = CONFIG_SYS_PCIE##num##_ADDR; \
+ x.cfg0_phys = CONFIG_SYS_PCIE_CFG0_PHYS_OFF + \
+ CONFIG_SYS_PCIE##num##_PHYS_ADDR; \
+ x.cfg0_size = CONFIG_SYS_PCIE_CFG0_SIZE; \
+ x.cfg1_phys = CONFIG_SYS_PCIE_CFG1_PHYS_OFF + \
+ CONFIG_SYS_PCIE##num##_PHYS_ADDR; \
+ x.cfg1_size = CONFIG_SYS_PCIE_CFG1_SIZE; \
+ x.mem_bus = CONFIG_SYS_PCIE_MEM_BUS; \
+ x.mem_phys = CONFIG_SYS_PCIE_MEM_PHYS_OFF + \
+ CONFIG_SYS_PCIE##num##_PHYS_ADDR; \
+ x.mem_size = CONFIG_SYS_PCIE_MEM_SIZE; \
+ x.io_bus = CONFIG_SYS_PCIE_IO_BUS; \
+ x.io_phys = CONFIG_SYS_PCIE_IO_PHYS_OFF + \
+ CONFIG_SYS_PCIE##num##_PHYS_ADDR; \
+ x.io_size = CONFIG_SYS_PCIE_IO_SIZE; \
+ x.pci_num = num; \
+}
+
+#ifdef CONFIG_LS102XA
+#include <asm/arch/immap_ls102xa.h>
+
+/* PEX1/2 Misc Ports Status Register */
+#define LTSSM_STATE_SHIFT 20
+#define LTSSM_STATE_MASK 0x3f
+#define LTSSM_PCIE_L0 0x11 /* L0 state */
+
+static int ls_pcie_link_state(struct ls_pcie *pcie)
+{
+ u32 state;
+ struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+
+ state = in_be32(&scfg->pexmscportsr[pcie->idx]);
+ state = (state >> LTSSM_STATE_SHIFT) & LTSSM_STATE_MASK;
+ if (state < LTSSM_PCIE_L0) {
+ debug("....PCIe link error. LTSSM=0x%02x.\n", state);
+ return 0;
+ }
+
+ return 1;
+}
+#else
+#define PCIE_LDBG 0x7FC
+
+static int ls_pcie_link_state(struct ls_pcie *pcie)
+{
+ u32 state;
+
+ state = readl(pcie->dbi + PCIE_LDBG);
+ if (state)
+ return 1;
+
+ debug("....PCIe link error.\n");
+ return 0;
+}
+#endif
+
+static int ls_pcie_link_up(struct ls_pcie *pcie)
+{
+ int state;
+ u32 cap;
+
+ state = ls_pcie_link_state(pcie);
+ if (state)
+ return state;
+
+ /* Try to download speed to gen1 */
+ cap = readl(pcie->dbi + PCIE_LINK_CAP);
+ writel((cap & (~PCIE_LINK_SPEED_MASK)) | 1, pcie->dbi + PCIE_LINK_CAP);
+ udelay(2000);
+ state = ls_pcie_link_state(pcie);
+ if (state)
+ return state;
+
+ writel(cap, pcie->dbi + PCIE_LINK_CAP);
+
+ return 0;
+}
+
+static void ls_pcie_cfg0_set_busdev(struct ls_pcie *pcie, u32 busdev)
+{
+ writel(PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0,
+ pcie->dbi + PCIE_ATU_VIEWPORT);
+ writel(busdev, pcie->dbi + PCIE_ATU_LOWER_TARGET);
+}
+
+static void ls_pcie_cfg1_set_busdev(struct ls_pcie *pcie, u32 busdev)
+{
+ writel(PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1,
+ pcie->dbi + PCIE_ATU_VIEWPORT);
+ writel(busdev, pcie->dbi + PCIE_ATU_LOWER_TARGET);
+}
+
+static void ls_pcie_iatu_outbound_set(struct ls_pcie *pcie, int idx, int type,
+ u64 phys, u64 bus_addr, pci_size_t size)
+{
+ writel(PCIE_ATU_REGION_OUTBOUND | idx, pcie->dbi + PCIE_ATU_VIEWPORT);
+ writel((u32)phys, pcie->dbi + PCIE_ATU_LOWER_BASE);
+ writel(phys >> 32, pcie->dbi + PCIE_ATU_UPPER_BASE);
+ writel(phys + size - 1, pcie->dbi + PCIE_ATU_LIMIT);
+ writel((u32)bus_addr, pcie->dbi + PCIE_ATU_LOWER_TARGET);
+ writel(bus_addr >> 32, pcie->dbi + PCIE_ATU_UPPER_TARGET);
+ writel(type, pcie->dbi + PCIE_ATU_CR1);
+ writel(PCIE_ATU_ENABLE, pcie->dbi + PCIE_ATU_CR2);
+}
+
+static void ls_pcie_setup_atu(struct ls_pcie *pcie, struct ls_pcie_info *info)
+{
+#ifdef DEBUG
+ int i;
+#endif
+
+ /* ATU 0 : OUTBOUND : CFG0 */
+ ls_pcie_iatu_outbound_set(pcie, PCIE_ATU_REGION_INDEX0,
+ PCIE_ATU_TYPE_CFG0,
+ info->cfg0_phys,
+ 0,
+ info->cfg0_size);
+ /* ATU 1 : OUTBOUND : CFG1 */
+ ls_pcie_iatu_outbound_set(pcie, PCIE_ATU_REGION_INDEX1,
+ PCIE_ATU_TYPE_CFG1,
+ info->cfg1_phys,
+ 0,
+ info->cfg1_size);
+ /* ATU 2 : OUTBOUND : MEM */
+ ls_pcie_iatu_outbound_set(pcie, PCIE_ATU_REGION_INDEX2,
+ PCIE_ATU_TYPE_MEM,
+ info->mem_phys,
+ info->mem_bus,
+ info->mem_size);
+ /* ATU 3 : OUTBOUND : IO */
+ ls_pcie_iatu_outbound_set(pcie, PCIE_ATU_REGION_INDEX3,
+ PCIE_ATU_TYPE_IO,
+ info->io_phys,
+ info->io_bus,
+ info->io_size);
+
+#ifdef DEBUG
+ for (i = 0; i <= PCIE_ATU_REGION_INDEX3; i++) {
+ writel(PCIE_ATU_REGION_OUTBOUND | i,
+ pcie->dbi + PCIE_ATU_VIEWPORT);
+ debug("iATU%d:\n", i);
+ debug("\tLOWER PHYS 0x%08x\n",
+ readl(pcie->dbi + PCIE_ATU_LOWER_BASE));
+ debug("\tUPPER PHYS 0x%08x\n",
+ readl(pcie->dbi + PCIE_ATU_UPPER_BASE));
+ debug("\tLOWER BUS 0x%08x\n",
+ readl(pcie->dbi + PCIE_ATU_LOWER_TARGET));
+ debug("\tUPPER BUS 0x%08x\n",
+ readl(pcie->dbi + PCIE_ATU_UPPER_TARGET));
+ debug("\tLIMIT 0x%08x\n",
+ readl(pcie->dbi + PCIE_ATU_LIMIT));
+ debug("\tCR1 0x%08x\n",
+ readl(pcie->dbi + PCIE_ATU_CR1));
+ debug("\tCR2 0x%08x\n",
+ readl(pcie->dbi + PCIE_ATU_CR2));
+ }
+#endif
+}
+
+int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev)
+{
+ /* Do not skip controller */
+ return 0;
+}
+
+static int ls_pcie_addr_valid(struct pci_controller *hose, pci_dev_t d)
+{
+ if (PCI_DEV(d) > 0)
+ return -EINVAL;
+
+ return 0;
+}
+
+static int ls_pcie_read_config(struct pci_controller *hose, pci_dev_t d,
+ int where, u32 *val)
+{
+ struct ls_pcie *pcie = hose->priv_data;
+ u32 busdev, *addr;
+
+ if (ls_pcie_addr_valid(hose, d)) {
+ *val = 0xffffffff;
+ return -EINVAL;
+ }
+
+ if (PCI_BUS(d) == hose->first_busno) {
+ addr = pcie->dbi + (where & ~0x3);
+ } else {
+ busdev = PCIE_ATU_BUS(PCI_BUS(d)) |
+ PCIE_ATU_DEV(PCI_DEV(d)) |
+ PCIE_ATU_FUNC(PCI_FUNC(d));
+
+ if (PCI_BUS(d) == hose->first_busno + 1) {
+ ls_pcie_cfg0_set_busdev(pcie, busdev);
+ addr = pcie->va_cfg0 + (where & ~0x3);
+ } else {
+ ls_pcie_cfg1_set_busdev(pcie, busdev);
+ addr = pcie->va_cfg1 + (where & ~0x3);
+ }
+ }
+
+ *val = readl(addr);
+
+ return 0;
+}
+
+static int ls_pcie_write_config(struct pci_controller *hose, pci_dev_t d,
+ int where, u32 val)
+{
+ struct ls_pcie *pcie = hose->priv_data;
+ u32 busdev, *addr;
+
+ if (ls_pcie_addr_valid(hose, d))
+ return -EINVAL;
+
+ if (PCI_BUS(d) == hose->first_busno) {
+ addr = pcie->dbi + (where & ~0x3);
+ } else {
+ busdev = PCIE_ATU_BUS(PCI_BUS(d)) |
+ PCIE_ATU_DEV(PCI_DEV(d)) |
+ PCIE_ATU_FUNC(PCI_FUNC(d));
+
+ if (PCI_BUS(d) == hose->first_busno + 1) {
+ ls_pcie_cfg0_set_busdev(pcie, busdev);
+ addr = pcie->va_cfg0 + (where & ~0x3);
+ } else {
+ ls_pcie_cfg1_set_busdev(pcie, busdev);
+ addr = pcie->va_cfg1 + (where & ~0x3);
+ }
+ }
+
+ writel(val, addr);
+
+ return 0;
+}
+
+static void ls_pcie_setup_ctrl(struct ls_pcie *pcie,
+ struct ls_pcie_info *info)
+{
+ struct pci_controller *hose = &pcie->hose;
+ pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0);
+
+ ls_pcie_setup_atu(pcie, info);
+
+ pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0);
+
+ /* program correct class for RC */
+ pci_hose_write_config_word(hose, dev, PCI_CLASS_DEVICE,
+ PCI_CLASS_BRIDGE_PCI);
+}
+
+int ls_pcie_init_ctrl(int busno, enum srds_prtcl dev, struct ls_pcie_info *info)
+{
+ struct ls_pcie *pcie;
+ struct pci_controller *hose;
+ int num = dev - PCIE1;
+ pci_dev_t pdev = PCI_BDF(busno, 0, 0);
+ int i, linkup, ep_mode;
+ u8 header_type;
+ u16 temp16;
+
+ if (!is_serdes_configured(dev)) {
+ printf("PCIe%d: disabled\n", num + 1);
+ return busno;
+ }
+
+ pcie = malloc(sizeof(*pcie));
+ if (!pcie)
+ return busno;
+ memset(pcie, 0, sizeof(*pcie));
+
+ hose = &pcie->hose;
+ hose->priv_data = pcie;
+ hose->first_busno = busno;
+ pcie->idx = num;
+ pcie->dbi = map_physmem(info->regs, PCIE_DBI_SIZE, MAP_NOCACHE);
+ pcie->va_cfg0 = map_physmem(info->cfg0_phys,
+ info->cfg0_size,
+ MAP_NOCACHE);
+ pcie->va_cfg1 = map_physmem(info->cfg1_phys,
+ info->cfg1_size,
+ MAP_NOCACHE);
+
+ /* outbound memory */
+ pci_set_region(&hose->regions[0],
+ (pci_size_t)info->mem_bus,
+ (phys_size_t)info->mem_phys,
+ (pci_size_t)info->mem_size,
+ PCI_REGION_MEM);
+
+ /* outbound io */
+ pci_set_region(&hose->regions[1],
+ (pci_size_t)info->io_bus,
+ (phys_size_t)info->io_phys,
+ (pci_size_t)info->io_size,
+ PCI_REGION_IO);
+
+ /* System memory space */
+ pci_set_region(&hose->regions[2],
+ CONFIG_SYS_PCI_MEMORY_BUS,
+ CONFIG_SYS_PCI_MEMORY_PHYS,
+ CONFIG_SYS_PCI_MEMORY_SIZE,
+ PCI_REGION_SYS_MEMORY);
+
+ hose->region_count = 3;
+
+ for (i = 0; i < hose->region_count; i++)
+ debug("PCI reg:%d %016llx:%016llx %016llx %08lx\n",
+ i,
+ (u64)hose->regions[i].phys_start,
+ (u64)hose->regions[i].bus_start,
+ (u64)hose->regions[i].size,
+ hose->regions[i].flags);
+
+ pci_set_ops(hose,
+ pci_hose_read_config_byte_via_dword,
+ pci_hose_read_config_word_via_dword,
+ ls_pcie_read_config,
+ pci_hose_write_config_byte_via_dword,
+ pci_hose_write_config_word_via_dword,
+ ls_pcie_write_config);
+
+ pci_hose_read_config_byte(hose, pdev, PCI_HEADER_TYPE, &header_type);
+ ep_mode = (header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL;
+ printf("PCIe%u: %s ", info->pci_num,
+ ep_mode ? "Endpoint" : "Root Complex");
+
+ linkup = ls_pcie_link_up(pcie);
+
+ if (!linkup) {
+ /* Let the user know there's no PCIe link */
+ printf("no link, regs @ 0x%lx\n", info->regs);
+ hose->last_busno = hose->first_busno;
+ return busno;
+ }
+
+ /* Print the negotiated PCIe link width */
+ pci_hose_read_config_word(hose, dev, PCIE_LINK_STA, &temp16);
+ printf("x%d gen%d, regs @ 0x%lx\n", (temp16 & 0x3f0) >> 4,
+ (temp16 & 0xf), info->regs);
+
+ if (ep_mode)
+ return busno;
+
+ ls_pcie_setup_ctrl(pcie, info);
+
+ pci_register_hose(hose);
+
+ hose->last_busno = pci_hose_scan(hose);
+
+ printf("PCIe%x: Bus %02x - %02x\n",
+ info->pci_num, hose->first_busno, hose->last_busno);
+
+ return hose->last_busno + 1;
+}
+
+int ls_pcie_init_board(int busno)
+{
+ struct ls_pcie_info info;
+
+#ifdef CONFIG_PCIE1
+ SET_LS_PCIE_INFO(info, 1);
+ busno = ls_pcie_init_ctrl(busno, PCIE1, &info);
+#endif
+
+#ifdef CONFIG_PCIE2
+ SET_LS_PCIE_INFO(info, 2);
+ busno = ls_pcie_init_ctrl(busno, PCIE2, &info);
+#endif
+
+#ifdef CONFIG_PCIE3
+ SET_LS_PCIE_INFO(info, 3);
+ busno = ls_pcie_init_ctrl(busno, PCIE3, &info);
+#endif
+
+#ifdef CONFIG_PCIE4
+ SET_LS_PCIE_INFO(info, 4);
+ busno = ls_pcie_init_ctrl(busno, PCIE4, &info);
+#endif
+
+ return busno;
+}
+
+void pci_init_board(void)
+{
+ ls_pcie_init_board(0);
+}
+
#ifdef CONFIG_OF_BOARD_SETUP
#include <libfdt.h>
#include <fdt_support.h>
#ifdef CONFIG_PCIE2
ft_pcie_ls_setup(blob, FSL_PCIE_COMPAT, CONFIG_SYS_PCIE2_ADDR, PCIE2);
#endif
+
+ #ifdef CONFIG_PCIE3
+ ft_pcie_ls_setup(blob, FSL_PCIE_COMPAT, CONFIG_SYS_PCIE3_ADDR, PCIE3);
+ #endif
+
+ #ifdef CONFIG_PCIE4
+ ft_pcie_ls_setup(blob, FSL_PCIE_COMPAT, CONFIG_SYS_PCIE4_ADDR, PCIE4);
+ #endif
}
#else
{
}
#endif
-
-void pci_init_board(void)
-{
-}
obj-$(CONFIG_SYS_NS16550) += ns16550.o
obj-$(CONFIG_S5P) += serial_s5p.o
obj-$(CONFIG_IMX_SERIAL) += serial_imx.o
-obj-$(CONFIG_KS8695_SERIAL) += serial_ks8695.o
obj-$(CONFIG_MAX3100_SERIAL) += serial_max3100.o
obj-$(CONFIG_MXC_UART) += serial_mxc.o
obj-$(CONFIG_PXA_SERIAL) += serial_pxa.o
serial_initfunc(imx_serial_initialize);
serial_initfunc(iop480_serial_initialize);
serial_initfunc(jz_serial_initialize);
-serial_initfunc(ks8695_serial_initialize);
serial_initfunc(leon2_serial_initialize);
serial_initfunc(leon3_serial_initialize);
serial_initfunc(lh7a40x_serial_initialize);
imx_serial_initialize();
iop480_serial_initialize();
jz_serial_initialize();
- ks8695_serial_initialize();
leon2_serial_initialize();
leon3_serial_initialize();
lh7a40x_serial_initialize();
+++ /dev/null
-/*
- * serial.c -- KS8695 serial driver
- *
- * (C) Copyright 2004, Greg Ungerer <greg.ungerer@opengear.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/platform.h>
-#include <serial.h>
-#include <linux/compiler.h>
-
-#ifndef CONFIG_SERIAL1
-#error "Bad: you didn't configure serial ..."
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * Define the UART hardware register access structure.
- */
-struct ks8695uart {
- unsigned int RX; /* 0x00 - Receive data (r) */
- unsigned int TX; /* 0x04 - Transmit data (w) */
- unsigned int FCR; /* 0x08 - Fifo Control (r/w) */
- unsigned int LCR; /* 0x0c - Line Control (r/w) */
- unsigned int MCR; /* 0x10 - Modem Control (r/w) */
- unsigned int LSR; /* 0x14 - Line Status (r/w) */
- unsigned int MSR; /* 0x18 - Modem Status (r/w) */
- unsigned int BD; /* 0x1c - Baud Rate (r/w) */
- unsigned int SR; /* 0x20 - Status (r/w) */
-};
-
-#define KS8695_UART_ADDR ((void *) (KS8695_IO_BASE + KS8695_UART_RX_BUFFER))
-#define KS8695_UART_CLK 25000000
-
-
-/*
- * Under some circumstances we want to be "quiet" and not issue any
- * serial output - though we want u-boot to otherwise work and behave
- * the same. By default be noisy.
- */
-int serial_console = 1;
-
-
-static void ks8695_serial_setbrg(void)
-{
- volatile struct ks8695uart *uartp = KS8695_UART_ADDR;
-
- /* Set to global baud rate and 8 data bits, no parity, 1 stop bit*/
- uartp->BD = KS8695_UART_CLK / gd->baudrate;
- uartp->LCR = KS8695_UART_LINEC_WLEN8;
-}
-
-static int ks8695_serial_init(void)
-{
- serial_console = 1;
- serial_setbrg();
- return 0;
-}
-
-static void ks8695_serial_raw_putc(const char c)
-{
- volatile struct ks8695uart *uartp = KS8695_UART_ADDR;
- int i;
-
- for (i = 0; (i < 0x100000); i++) {
- if (uartp->LSR & KS8695_UART_LINES_TXFE)
- break;
- }
-
- uartp->TX = c;
-}
-
-static void ks8695_serial_putc(const char c)
-{
- if (serial_console) {
- ks8695_serial_raw_putc(c);
- if (c == '\n')
- ks8695_serial_raw_putc('\r');
- }
-}
-
-static int ks8695_serial_tstc(void)
-{
- volatile struct ks8695uart *uartp = KS8695_UART_ADDR;
- if (serial_console)
- return ((uartp->LSR & KS8695_UART_LINES_RXFE) ? 1 : 0);
- return 0;
-}
-
-static int ks8695_serial_getc(void)
-{
- volatile struct ks8695uart *uartp = KS8695_UART_ADDR;
-
- while ((uartp->LSR & KS8695_UART_LINES_RXFE) == 0)
- ;
- return (uartp->RX);
-}
-
-static struct serial_device ks8695_serial_drv = {
- .name = "ks8695_serial",
- .start = ks8695_serial_init,
- .stop = NULL,
- .setbrg = ks8695_serial_setbrg,
- .putc = ks8695_serial_putc,
- .puts = default_serial_puts,
- .getc = ks8695_serial_getc,
- .tstc = ks8695_serial_tstc,
-};
-
-void ks8695_serial_initialize(void)
-{
- serial_register(&ks8695_serial_drv);
-}
-
-__weak struct serial_device *default_serial_console(void)
-{
- return &ks8695_serial_drv;
-}
obj-$(CONFIG_VIDEO_LCD_HITACHI_TX18D42VM) += hitachi_tx18d42vm_lcd.o
obj-$(CONFIG_VIDEO_LCD_SSD2828) += ssd2828.o
obj-$(CONFIG_VIDEO_MB862xx) += mb862xx.o videomodes.o
-obj-$(CONFIG_VIDEO_MB86R0xGDC) += mb86r0xgdc.o videomodes.o
obj-$(CONFIG_VIDEO_MX3) += mx3fb.o videomodes.o
obj-$(CONFIG_VIDEO_IPUV3) += mxc_ipuv3_fb.o ipu_common.o ipu_disp.o
obj-$(CONFIG_VIDEO_MXS) += mxsfb.o videomodes.o
+++ /dev/null
-/*
- * (C) Copyright 2010
- * Matthias Weisser <weisserm@arcor.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * mb86r0xgdc.c - Graphic interface for Fujitsu MB86R0x integrated graphic
- * controller.
- */
-
-#include <common.h>
-
-#include <malloc.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-#include <video_fb.h>
-#include "videomodes.h"
-
-/*
- * 4MB (at the end of system RAM)
- */
-#define VIDEO_MEM_SIZE 0x400000
-
-#define FB_SYNC_CLK_INV (1<<16) /* pixel clock inverted */
-
-/*
- * Graphic Device
- */
-static GraphicDevice mb86r0x;
-
-static void dsp_init(struct mb86r0x_gdc_dsp *dsp, char *modestr,
- u32 *videomem)
-{
- struct ctfb_res_modes var_mode;
- u32 dcm1, dcm2, dcm3;
- u16 htp, hdp, hdb, hsp, vtr, vsp, vdp;
- u8 hsw, vsw;
- u32 l2m, l2em, l2oa0, l2da0, l2oa1, l2da1;
- u16 l2dx, l2dy, l2wx, l2wy, l2ww, l2wh;
- unsigned long div;
- int bpp;
-
- bpp = video_get_params(&var_mode, modestr);
-
- if (bpp == 0) {
- var_mode.xres = 640;
- var_mode.yres = 480;
- var_mode.pixclock = 39721; /* 25MHz */
- var_mode.left_margin = 48;
- var_mode.right_margin = 16;
- var_mode.upper_margin = 33;
- var_mode.lower_margin = 10;
- var_mode.hsync_len = 96;
- var_mode.vsync_len = 2;
- var_mode.sync = 0;
- var_mode.vmode = 0;
- bpp = 15;
- }
-
- /* Fill memory with white */
- memset(videomem, 0xFF, var_mode.xres * var_mode.yres * 2);
-
- mb86r0x.winSizeX = var_mode.xres;
- mb86r0x.winSizeY = var_mode.yres;
-
- /* LCD base clock is ~ 660MHZ. We do calculations in kHz */
- div = 660000 / (1000000000L / var_mode.pixclock);
- if (div > 64)
- div = 64;
- if (0 == div)
- div = 1;
-
- dcm1 = (div - 1) << 8;
- dcm2 = 0x00000000;
- if (var_mode.sync & FB_SYNC_CLK_INV)
- dcm3 = 0x00000100;
- else
- dcm3 = 0x00000000;
-
- htp = var_mode.left_margin + var_mode.xres +
- var_mode.hsync_len + var_mode.right_margin;
- hdp = var_mode.xres;
- hdb = var_mode.xres;
- hsp = var_mode.xres + var_mode.right_margin;
- hsw = var_mode.hsync_len;
-
- vsw = var_mode.vsync_len;
- vtr = var_mode.upper_margin + var_mode.yres +
- var_mode.vsync_len + var_mode.lower_margin;
- vsp = var_mode.yres + var_mode.lower_margin;
- vdp = var_mode.yres;
-
- l2m = ((var_mode.yres - 1) << (0)) |
- (((var_mode.xres * 2) / 64) << (16)) |
- ((1) << (31));
-
- l2em = (1 << 0) | (1 << 1);
-
- l2oa0 = mb86r0x.frameAdrs;
- l2da0 = mb86r0x.frameAdrs;
- l2oa1 = mb86r0x.frameAdrs;
- l2da1 = mb86r0x.frameAdrs;
- l2dx = 0;
- l2dy = 0;
- l2wx = 0;
- l2wy = 0;
- l2ww = var_mode.xres;
- l2wh = var_mode.yres - 1;
-
- writel(dcm1, &dsp->dcm1);
- writel(dcm2, &dsp->dcm2);
- writel(dcm3, &dsp->dcm3);
-
- writew(htp, &dsp->htp);
- writew(hdp, &dsp->hdp);
- writew(hdb, &dsp->hdb);
- writew(hsp, &dsp->hsp);
- writeb(hsw, &dsp->hsw);
-
- writeb(vsw, &dsp->vsw);
- writew(vtr, &dsp->vtr);
- writew(vsp, &dsp->vsp);
- writew(vdp, &dsp->vdp);
-
- writel(l2m, &dsp->l2m);
- writel(l2em, &dsp->l2em);
- writel(l2oa0, &dsp->l2oa0);
- writel(l2da0, &dsp->l2da0);
- writel(l2oa1, &dsp->l2oa1);
- writel(l2da1, &dsp->l2da1);
- writew(l2dx, &dsp->l2dx);
- writew(l2dy, &dsp->l2dy);
- writew(l2wx, &dsp->l2wx);
- writew(l2wy, &dsp->l2wy);
- writew(l2ww, &dsp->l2ww);
- writew(l2wh, &dsp->l2wh);
-
- writel(dcm1 | (1 << 18) | (1 << 31), &dsp->dcm1);
-}
-
-void *video_hw_init(void)
-{
- struct mb86r0x_gdc *gdc = (struct mb86r0x_gdc *) MB86R0x_GDC_BASE;
- GraphicDevice *pGD = &mb86r0x;
- char *s;
- u32 *vid;
-
- memset(pGD, 0, sizeof(GraphicDevice));
-
- pGD->gdfIndex = GDF_15BIT_555RGB;
- pGD->gdfBytesPP = 2;
- pGD->memSize = VIDEO_MEM_SIZE;
- pGD->frameAdrs = PHYS_SDRAM + PHYS_SDRAM_SIZE - VIDEO_MEM_SIZE;
-
- vid = (u32 *)pGD->frameAdrs;
-
- s = getenv("videomode");
- if (s != NULL)
- dsp_init(&gdc->dsp0, s, vid);
-
- s = getenv("videomode1");
- if (s != NULL)
- dsp_init(&gdc->dsp1, s, vid);
-
- return pGD;
-}
ifneq (,$(filter $(SOC), mx31 mx35 mx5 mx6 vf610 ls102xa))
obj-y += imx_watchdog.o
endif
-obj-$(CONFIG_TNETV107X_WATCHDOG) += tnetv107x_wdt.o
obj-$(CONFIG_S5P) += s5p_wdt.o
obj-$(CONFIG_XILINX_TB_WATCHDOG) += xilinx_tb_wdt.o
obj-$(CONFIG_BFIN_WATCHDOG) += bfin_wdt.o
+++ /dev/null
-/*
- * TNETV107X: Watchdog timer implementation (for reset)
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-
-#define MAX_DIV 0xFFFE0001
-
-struct wdt_regs {
- u32 kick_lock;
-#define KICK_LOCK_1 0x5555
-#define KICK_LOCK_2 0xaaaa
- u32 kick;
-
- u32 change_lock;
-#define CHANGE_LOCK_1 0x6666
-#define CHANGE_LOCK_2 0xbbbb
- u32 change;
-
- u32 disable_lock;
-#define DISABLE_LOCK_1 0x7777
-#define DISABLE_LOCK_2 0xcccc
-#define DISABLE_LOCK_3 0xdddd
- u32 disable;
-
- u32 prescale_lock;
-#define PRESCALE_LOCK_1 0x5a5a
-#define PRESCALE_LOCK_2 0xa5a5
- u32 prescale;
-};
-
-static struct wdt_regs* regs = (struct wdt_regs *)TNETV107X_WDT0_ARM_BASE;
-
-#define wdt_reg_read(reg) __raw_readl(®s->reg)
-#define wdt_reg_write(reg, val) __raw_writel((val), ®s->reg)
-
-static int write_prescale_reg(unsigned long prescale_value)
-{
- wdt_reg_write(prescale_lock, PRESCALE_LOCK_1);
- if ((wdt_reg_read(prescale_lock) & 0x3) != 0x1)
- return -1;
-
- wdt_reg_write(prescale_lock, PRESCALE_LOCK_2);
- if ((wdt_reg_read(prescale_lock) & 0x3) != 0x3)
- return -1;
-
- wdt_reg_write(prescale, prescale_value);
-
- return 0;
-}
-
-static int write_change_reg(unsigned long initial_timer_value)
-{
- wdt_reg_write(change_lock, CHANGE_LOCK_1);
- if ((wdt_reg_read(change_lock) & 0x3) != 0x1)
- return -1;
-
- wdt_reg_write(change_lock, CHANGE_LOCK_2);
- if ((wdt_reg_read(change_lock) & 0x3) != 0x3)
- return -1;
-
- wdt_reg_write(change, initial_timer_value);
-
- return 0;
-}
-
-static int wdt_control(unsigned long disable_value)
-{
- wdt_reg_write(disable_lock, DISABLE_LOCK_1);
- if ((wdt_reg_read(disable_lock) & 0x3) != 0x1)
- return -1;
-
- wdt_reg_write(disable_lock, DISABLE_LOCK_2);
- if ((wdt_reg_read(disable_lock) & 0x3) != 0x2)
- return -1;
-
- wdt_reg_write(disable_lock, DISABLE_LOCK_3);
- if ((wdt_reg_read(disable_lock) & 0x3) != 0x3)
- return -1;
-
- wdt_reg_write(disable, disable_value);
- return 0;
-}
-
-static int wdt_set_period(unsigned long msec)
-{
- unsigned long change_value, count_value;
- unsigned long prescale_value = 1;
- unsigned long refclk_khz, maxdiv;
- int ret;
-
- refclk_khz = clk_get_rate(TNETV107X_LPSC_WDT_ARM);
- maxdiv = (MAX_DIV / refclk_khz);
-
- if ((!msec) || (msec > maxdiv))
- return -1;
-
- count_value = refclk_khz * msec;
- if (count_value > 0xffff) {
- change_value = count_value / 0xffff + 1;
- prescale_value = count_value / change_value;
- } else {
- change_value = count_value;
- }
-
- ret = write_prescale_reg(prescale_value - 1);
- if (ret)
- return ret;
-
- ret = write_change_reg(change_value);
- if (ret)
- return ret;
-
- return 0;
-}
-
-unsigned long last_wdt = -1;
-
-int wdt_start(unsigned long msecs)
-{
- int ret;
- ret = wdt_control(0);
- if (ret)
- return ret;
- ret = wdt_set_period(msecs);
- if (ret)
- return ret;
- ret = wdt_control(1);
- if (ret)
- return ret;
- ret = wdt_kick();
- last_wdt = msecs;
- return ret;
-}
-
-int wdt_stop(void)
-{
- last_wdt = -1;
- return wdt_control(0);
-}
-
-int wdt_kick(void)
-{
- wdt_reg_write(kick_lock, KICK_LOCK_1);
- if ((wdt_reg_read(kick_lock) & 0x3) != 0x1)
- return -1;
-
- wdt_reg_write(kick_lock, KICK_LOCK_2);
- if ((wdt_reg_read(kick_lock) & 0x3) != 0x3)
- return -1;
-
- wdt_reg_write(kick, 1);
- return 0;
-}
-
-void reset_cpu(ulong addr)
-{
- clk_enable(TNETV107X_LPSC_WDT_ARM);
- wdt_start(1);
- wdt_kick();
-}
bool
menu "Device Tree Control"
- depends on !SPL_BUILD
depends on SUPPORT_OF_CONTROL
config OF_CONTROL
#undef CONFIG_CMD_SNTP
#undef CONFIG_CMD_TFTPPUT
#undef CONFIG_CMD_TFTPSRV
+#undef CONFIG_OF_CONTROL
+
+#ifndef CONFIG_SPL_DM
+#undef CONFIG_DM_SERIAL
+#undef CONFIG_DM_GPIO
+#undef CONFIG_DM_I2C
+#undef CONFIG_DM_SPI
+#endif
+
+#undef CONFIG_DM_WARN
+#undef CONFIG_DM_DEVICE_REMOVE
+#undef CONFIG_DM_STDIO
+
#endif /* CONFIG_SPL_BUILD */
#endif /* __CONFIG_UNCMD_SPL_H__ */
+++ /dev/null
-/*
- * (C) Copyright 2009 Faraday Technology
- * Po-Yu Chuang <ratbert@faraday-tech.com>
- *
- * Configuation settings for the Faraday A320 board.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <asm/arch/a320.h>
-
-/*
- * mach-type definition
- */
-#define MACH_TYPE_FARADAY 758
-#define CONFIG_MACH_TYPE MACH_TYPE_FARADAY
-
-/*
- * Linux kernel tagged list
- */
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-
-/*
- * CPU and Board Configuration Options
- */
-#undef CONFIG_SKIP_LOWLEVEL_INIT
-
-/*
- * Power Management Unit
- */
-#define CONFIG_FTPMU010_POWER
-
-/*
- * Timer
- */
-
-/*
- * Real Time Clock
- */
-#define CONFIG_RTC_FTRTC010
-
-/*
- * Serial console configuration
- */
-
-/* FTUART is a high speed NS 16C550A compatible UART */
-#define CONFIG_BAUDRATE 38400
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_COM1 0x98200000
-#define CONFIG_SYS_NS16550_REG_SIZE -4
-#define CONFIG_SYS_NS16550_CLK 18432000
-
-/*
- * Ethernet
- */
-#define CONFIG_FTMAC100
-
-#define CONFIG_BOOTDELAY 3
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_PING
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "A320 # " /* Monitor Command Prompt */
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE \
- (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-
-/* max number of command args */
-#define CONFIG_SYS_MAXARGS 16
-
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
-
-/*
- * SDRAM controller configuration
- */
-#define CONFIG_SYS_FTSDMC020_TP0 (FTSDMC020_TP0_TRAS(2) | \
- FTSDMC020_TP0_TRP(1) | \
- FTSDMC020_TP0_TRCD(1) | \
- FTSDMC020_TP0_TRF(3) | \
- FTSDMC020_TP0_TWR(1) | \
- FTSDMC020_TP0_TCL(2))
-
-#define CONFIG_SYS_FTSDMC020_TP1 (FTSDMC020_TP1_INI_PREC(4) | \
- FTSDMC020_TP1_INI_REFT(8) | \
- FTSDMC020_TP1_REF_INTV(0x180))
-
-#define CONFIG_SYS_FTSDMC020_BANK0_BSR (FTSDMC020_BANK_ENABLE | \
- FTSDMC020_BANK_DDW_X16 | \
- FTSDMC020_BANK_DSZ_256M | \
- FTSDMC020_BANK_MBW_32 | \
- FTSDMC020_BANK_SIZE_64M)
-
-/*
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
-#define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
-
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
- GENERATED_GBL_DATA_SIZE)
-
-/*
- * Load address and memory test area should agree with
- * board/faraday/a320/config.mk. Be careful not to overwrite U-boot itself.
- */
-#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x2000000)
-
-/* memtest works on 63 MB in DRAM */
-#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1
-#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x3F00000)
-
-#define CONFIG_SYS_TEXT_BASE 0
-
-/*
- * Static memory controller configuration
- */
-
-#define CONFIG_FTSMC020
-#include <faraday/ftsmc020.h>
-
-#define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_ENABLE | \
- FTSMC020_BANK_BASE(PHYS_FLASH_1) | \
- FTSMC020_BANK_SIZE_1M | \
- FTSMC020_BANK_MBW_8)
-
-#define FTSMC020_BANK0_TIMING (FTSMC020_TPR_RBE | \
- FTSMC020_TPR_AST(3) | \
- FTSMC020_TPR_CTW(3) | \
- FTSMC020_TPR_ATI(0xf) | \
- FTSMC020_TPR_AT2(3) | \
- FTSMC020_TPR_WTC(3) | \
- FTSMC020_TPR_AHT(3) | \
- FTSMC020_TPR_TRNA(0xf))
-
-#define FTSMC020_BANK1_CONFIG (FTSMC020_BANK_ENABLE | \
- FTSMC020_BANK_BASE(PHYS_FLASH_2) | \
- FTSMC020_BANK_SIZE_32M | \
- FTSMC020_BANK_MBW_32)
-
-#define FTSMC020_BANK1_TIMING (FTSMC020_TPR_AST(3) | \
- FTSMC020_TPR_CTW(3) | \
- FTSMC020_TPR_ATI(0xf) | \
- FTSMC020_TPR_AT2(3) | \
- FTSMC020_TPR_WTC(3) | \
- FTSMC020_TPR_AHT(3) | \
- FTSMC020_TPR_TRNA(0xf))
-
-#define CONFIG_SYS_FTSMC020_CONFIGS { \
- { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \
- { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \
-}
-
-/*
- * FLASH and environment organization
- */
-
-/* use CFI framework */
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_FLASH_CFI_DRIVER
-
-/* support JEDEC */
-#define CONFIG_FLASH_CFI_LEGACY
-#define CONFIG_SYS_FLASH_LEGACY_512Kx8
-
-#define PHYS_FLASH_1 0x00000000
-#define PHYS_FLASH_2 0x00400000
-#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
-#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2, }
-
-#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
-
-/* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_BANKS 2
-
-/* max number of sectors on one chip */
-#define CONFIG_SYS_MAX_FLASH_SECT 512
-
-#undef CONFIG_SYS_FLASH_EMPTY_INFO
-
-/* environments */
-#define CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x60000)
-#define CONFIG_ENV_SIZE 0x20000
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * (C) Copyright 2004
- * Greg Ungerer <greg.ungerer@opengear.com>.
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_KS8695 1 /* it is a KS8695 CPU */
-#define CONFIG_CM4008 1 /* it is an OpenGear CM4008 boad */
-
-#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS 1
-#define CONFIG_INITRD_TAG 1
-
-#define CONFIG_DRIVER_KS8695ETH /* use KS8695 ethernet driver */
-
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
-
-/*
- * Hardware drivers
- */
-
-/*
- * select serial console configuration
- */
-#define CONFIG_ENV_IS_NOWHERE
-#define CONFIG_KS8695_SERIAL
-#define CONFIG_SERIAL1
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_BAUDRATE 115200
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#undef CONFIG_CMD_SAVEENV
-
-
-#define CONFIG_BOOTDELAY 0
-#define CONFIG_BOOTARGS "mem=16M console=ttyAM0,115200"
-#define CONFIG_BOOTCOMMAND "gofsk 0x02200000"
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "boot > " /* Monitor Command Prompt */
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x00800000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x01000000 /* 16 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x00008000 /* default load address */
-
-/*-----------------------------------------------------------------------
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
-#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE 0x01000000 /* 16 MB */
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-
-#define CONFIG_SYS_INIT_SP_ADDR 0x00020000 /* lowest 128k of RAM */
-
-#define PHYS_FLASH_1 0x02000000 /* Flash Bank #1 */
-#define PHYS_FLASH_SECT_SIZE 0x00020000 /* 128 KB sectors (x1) */
-#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */
-#define CONFIG_SYS_MAX_FLASH_SECT (128) /* max number of sectors on one chip */
-
-/* timeout values are in ticks */
-#define CONFIG_SYS_FLASH_ERASE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
-#define CONFIG_SYS_FLASH_WRITE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Write */
-
-#define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment */
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * (C) Copyright 2005
- * Greg Ungerer <greg.ungerer@opengear.com>.
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_KS8695 1 /* it is a KS8695 CPU */
-#define CONFIG_CM41xx 1 /* it is an OpenGear CM41xx boad */
-
-#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS 1
-#define CONFIG_INITRD_TAG 1
-
-#define CONFIG_DRIVER_KS8695ETH /* use KS8695 ethernet driver */
-
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
-
-/*
- * Hardware drivers
- */
-
-/*
- * select serial console configuration
- */
-#define CONFIG_ENV_IS_NOWHERE
-#define CONFIG_KS8695_SERIAL
-#define CONFIG_SERIAL1
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_BAUDRATE 115200
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#undef CONFIG_CMD_SAVEENV
-
-
-#define CONFIG_BOOTDELAY 0
-#define CONFIG_BOOTARGS "mem=32M console=ttyAM0,115200"
-#define CONFIG_BOOTCOMMAND "gofsk 0x02200000"
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "boot > " /* Monitor Command Prompt */
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x00800000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x01000000 /* 16 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x00008000 /* default load address */
-
-/*-----------------------------------------------------------------------
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
-#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-
-#define CONFIG_SYS_INIT_SP_ADDR 0x00020000 /* lowest 128k of RAM */
-
-#define PHYS_FLASH_1 0x02000000 /* Flash Bank #1 */
-#define PHYS_FLASH_SECT_SIZE 0x00020000 /* 128 KB sectors (x1) */
-#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */
-#define CONFIG_SYS_MAX_FLASH_SECT (128) /* max number of sectors on one chip */
-
-/* timeout values are in ticks */
-#define CONFIG_SYS_FLASH_ERASE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
-#define CONFIG_SYS_FLASH_WRITE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Write */
-
-#define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment */
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * (C) Copyright 2011
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Lei Wen <leiwen@marvell.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_DKB_H
-#define __CONFIG_DKB_H
-
-/*
- * Version number information
- */
-#define CONFIG_IDENT_STRING "\nMarvell-TTC DKB"
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_SHEEVA_88SV331xV5 1 /* CPU Core subversion */
-#define CONFIG_PANTHEON 1 /* SOC Family Name */
-#define CONFIG_MACH_TTC_DKB 1 /* Machine type */
-#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
-
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE - 0x00200000)
-#define CONFIG_NR_DRAM_BANKS_MAX 2
-
-/*
- * Commands configuration
- */
-#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
-#include <config_cmd_default.h>
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_MMC
-#undef CONFIG_CMD_NET
-#undef CONFIG_CMD_NFS
-/*
- * mv-common.h should be defined after CMD configs since it used them
- * to enable certain macros
- */
-#include "mv-common.h"
-
-#undef CONFIG_ARCH_MISC_INIT
-
-/*
- * Environment variables configurations
- */
-#define CONFIG_ENV_IS_NOWHERE 1 /* if env in SDRAM */
-#define CONFIG_ENV_SIZE 0x20000 /* 64k */
-
-#endif /* __CONFIG_DKB_H */
+++ /dev/null
-/*
- * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
- *
- * Based on davinci_dvevm.h. Original Copyrights follow:
- *
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * Board
- */
-#define CONFIG_SYS_USE_NAND 1
-
-/*
- * SoC Configuration
- */
-#define CONFIG_MACH_DAVINCI_HAWK
-#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */
-#define CONFIG_SOC_DA850 /* TI DA850 SoC */
-#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
-#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
-#define CONFIG_SYS_OSCIN_FREQ 24000000
-#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
-#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
-#define CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_AIS_CONFIG_FILE "board/$(BOARDDIR)/hawkboard-ais-nand.cfg"
-
-#define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \
- DAVINCI_SYSCFG_SUSPSRC_EMAC | \
- DAVINCI_SYSCFG_SUSPSRC_I2C | \
- DAVINCI_SYSCFG_SUSPSRC_SPI1 | \
- DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \
- DAVINCI_SYSCFG_SUSPSRC_UART2)
-
-#if defined(CONFIG_UART_U_BOOT)
-#define CONFIG_SYS_TEXT_BASE 0xc1080000
-#elif !defined(CONFIG_SPL_BUILD)
-#define CONFIG_SYS_TEXT_BASE 0xc1180000
-#endif
-
-/* Spl */
-#define CONFIG_SPL_FRAMEWORK
-#define CONFIG_SPL_BOARD_INIT
-#define CONFIG_SPL_NAND_SUPPORT
-#define CONFIG_SPL_NAND_BASE
-#define CONFIG_SPL_NAND_DRIVERS
-#define CONFIG_SPL_NAND_ECC
-#define CONFIG_SPL_NAND_SIMPLE
-#define CONFIG_SPL_LIBGENERIC_SUPPORT /* for udelay and __div64_32 for NAND */
-#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_LDSCRIPT "board/$(BOARDDIR)/u-boot-spl-hawk.lds"
-#define CONFIG_SPL_TEXT_BASE 0xc1080000
-#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
-
-/*
- * Memory Info
- */
-#define CONFIG_SYS_MALLOC_LEN (1*1024*1024) /* malloc() len */
-#define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE
-#define PHYS_SDRAM_1_SIZE (128 << 20) /* SDRAM size 128MB */
-#define CONFIG_SYS_SDRAM_BASE 0xc0000000
-#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20)
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 -\
- GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_MONITOR_LEN 0x60000
-
-/* memtest start addr */
-#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1)
-
-/* memtest will be run on 16MB */
-#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 16*1024*1024)
-
-#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
-
-/*
- * Serial Driver info
- */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE -4
-#define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE
-#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_BAUDRATE 115200
-
-/*
- * Network & Ethernet Configuration
- */
-#define CONFIG_DRIVER_TI_EMAC
-#define CONFIG_MII
-#define CONFIG_BOOTP_DNS
-#define CONFIG_BOOTP_DNS2
-#define CONFIG_BOOTP_SEND_HOSTNAME
-#define CONFIG_NET_RETRY_COUNT 10
-
-/*
- * Nand Flash
- */
-#ifdef CONFIG_SYS_USE_NAND
-#define CONFIG_SYS_NO_FLASH
-#define CONFIG_ENV_IS_IN_NAND
-#define CONFIG_ENV_SIZE (128 << 10)
-#define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
-#define CONFIG_CLE_MASK 0x10
-#define CONFIG_ALE_MASK 0x8
-#define CONFIG_SYS_NAND_USE_FLASH_BBT
-#define CONFIG_NAND_DAVINCI
-#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
-#define CONFIG_SYS_NAND_HW_ECC_OOBFIRST /* SPL nand driver configuration */
-#define CFG_DAVINCI_STD_NAND_LAYOUT
-#define CONFIG_SYS_NAND_CS 3
-#define CONFIG_SYS_NAND_PAGE_2K
-/* Max number of NAND devices */
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_BASE_LIST { 0x62000000, }
-/* Block 0--not used by bootcode */
-#define CONFIG_ENV_OFFSET 0x0
-
-#define CONFIG_SYS_NAND_PAGE_SIZE (2 << 10)
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10)
-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0xe0000
-#define CONFIG_SYS_NAND_U_BOOT_DST 0xc1180000
-#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
-#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \
- CONFIG_SYS_NAND_U_BOOT_SIZE - \
- CONFIG_SYS_MALLOC_LEN - \
- GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_NAND_ECCPOS { \
- 24, 25, 26, 27, 28, \
- 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, \
- 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, \
- 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, \
- 59, 60, 61, 62, 63 }
-#define CONFIG_SYS_NAND_PAGE_COUNT 64
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
-#define CONFIG_SYS_NAND_ECCSIZE 512
-#define CONFIG_SYS_NAND_ECCBYTES 10
-#define CONFIG_SYS_NAND_OOBSIZE 64
-
-#endif /* CONFIG_SYS_USE_NAND */
-
-/* USB Configs */
-#define CONFIG_SYS_USB_OHCI_CPU_INIT
-#define CONFIG_USB_OHCI_NEW
-#define CONFIG_USB_OHCI_DA8XX
-#define CONFIG_USB_STORAGE
-#define CONFIG_DOS_PARTITION
-#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x01E25000
-#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
-#define CONFIG_SYS_USB_OHCI_SLOT_NAME "hawkboard"
-
-/*
- * U-Boot general configuration
- */
-#define CONFIG_MISC_INIT_R
-#define CONFIG_BOOTFILE "uImage" /* Boot file name */
-#define CONFIG_SYS_PROMPT "hawkboard > " /* Command Prompt */
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
-#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000)
-#define CONFIG_VERSION_VARIABLE
-#define CONFIG_AUTO_COMPLETE
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_CMDLINE_EDITING
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_CRC32_VERIFY
-#define CONFIG_MX_CYCLIC
-
-/*
- * Linux Information
- */
-#define LINUX_BOOT_PARAM_ADDR (CONFIG_SYS_MEMTEST_START + 0x100)
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_BOOTARGS \
- "mem=128M console=ttyS2,115200n8 root=/dev/ram0 rw initrd=0xc1180000,"\
- "4M ip=static"
-#define CONFIG_BOOTDELAY 3
-
-/*
- * U-Boot commands
- */
-#include <config_cmd_default.h>
-#define CONFIG_CMD_ENV
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_SAVES
-#define CONFIG_CMD_MEMORY
-#define CONFIG_CMD_USB
-#define CONFIG_CMD_EXT2
-
-#ifdef CONFIG_CMD_BDI
-#define CONFIG_CLOCKS
-#endif
-
-#ifdef CONFIG_SYS_USE_NAND
-#undef CONFIG_CMD_FLASH
-#undef CONFIG_CMD_IMLS
-#define CONFIG_CMD_NAND
-#endif
-
-#ifndef CONFIG_DRIVER_TI_EMAC
-#undef CONFIG_CMD_NET
-#undef CONFIG_CMD_DHCP
-#undef CONFIG_CMD_MII
-#undef CONFIG_CMD_PING
-#endif
-
-#endif /* __CONFIG_H */
#define CONFIG_MX31 /* This is a mx31 */
#define CONFIG_MX31_CLK32 32000
+#define CONFIG_SYS_GENERIC_BOARD
+
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
+++ /dev/null
-/*
- * (C) Copyright 2010
- * Matthias Weisser <weisserm@arcor.de>
- *
- * Configuation settings for the jadecpu board
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_MB86R0x
-#define CONFIG_MB86R0x_IOCLK get_bus_freq(0)
-#define CONFIG_SYS_TEXT_BASE 0x10000000
-
-
-#define CONFIG_USE_ARCH_MEMCPY
-#define CONFIG_USE_ARCH_MEMSET
-
-#define MACH_TYPE_JADECPU 2636
-
-#define CONFIG_MACH_TYPE MACH_TYPE_JADECPU
-
-/*
- * Environment settings
- */
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "gs_fast_boot=setenv bootdelay 5\0" \
- "gs_slow_boot=setenv bootdelay 10\0" \
- "bootcmd=dcache off; mw.l 0x40000000 0 1024; usb start;" \
- "fatls usb 0; fatload usb 0 0x40000000 jadecpu-init.bin;" \
- "bootelf 0x40000000\0" \
- ""
-
-#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS 1
-#define CONFIG_INITRD_TAG 1
-#define CONFIG_BOARD_LATE_INIT
-
-/*
- * Compressions
- */
-#define CONFIG_LZO
-
-/*
- * Hardware drivers
- */
-
-/*
- * Serial
- */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE (-4)
-#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
-#define CONFIG_SYS_NS16550_COM1 0xfffe1000 /* UART 0 */
-#define CONFIG_SYS_NS16550_COM2 0xfff50000 /* UART 2 */
-#define CONFIG_SYS_NS16550_COM3 0xfff51000 /* UART 3 */
-#define CONFIG_SYS_NS16550_COM4 0xfff43000 /* UART 4 */
-
-#define CONFIG_CONS_INDEX 4
-
-/*
- * Ethernet
- */
-#define CONFIG_SMC911X
-#define CONFIG_SMC911X_BASE 0x02000000
-#define CONFIG_SMC911X_16_BIT
-
-/*
- * Video
- */
-#define CONFIG_VIDEO
-#define CONFIG_VIDEO_MB86R0xGDC
-#define CONFIG_SYS_WHITE_ON_BLACK
-#define CONFIG_CFB_CONSOLE
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE
-#define CONFIG_VIDEO_LOGO
-#define CONFIG_SPLASH_SCREEN
-#define CONFIG_SPLASH_SCREEN_ALIGN
-#define CONFIG_VIDEO_BMP_LOGO
-#define CONFIG_VIDEO_BMP_GZIP
-#define CONFIG_VIDEO_BMP_RLE8
-#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (800*480 + 256*4 + 10*1024)
-#define VIDEO_FB_16BPP_WORD_SWAP
-#define VIDEO_KBD_INIT_FCT 0
-#define VIDEO_TSTC_FCT serial_stub_tstc
-#define VIDEO_GETC_FCT serial_stub_getc
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE 1
-#define CONFIG_BOOTP_BOOTPATH 1
-#define CONFIG_BOOTP_GATEWAY 1
-#define CONFIG_BOOTP_HOSTNAME 1
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-#undef CONFIG_CMD_BDI
-#undef CONFIG_CMD_FPGA
-#undef CONFIG_CMD_IMLS
-#undef CONFIG_CMD_LOADS
-#undef CONFIG_CMD_SOURCE
-#undef CONFIG_CMD_NFS
-#undef CONFIG_CMD_XIMG
-
-#define CONFIG_CMD_BMP
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_USB
-#define CONFIG_CMD_CACHE
-
-#define CONFIG_SYS_HUSH_PARSER
-
-/* USB */
-#define CONFIG_USB_OHCI_NEW
-#define CONFIG_SYS_USB_OHCI_REGS_BASE 0xFFF81000
-#define CONFIG_SYS_USB_OHCI_SLOT_NAME "mb86r0x"
-#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1
-#define CONFIG_USB_STORAGE
-#define CONFIG_DOS_PARTITION
-
-/* SDRAM */
-#define CONFIG_NR_DRAM_BANKS 1
-#define PHYS_SDRAM 0x40000000 /* Start address of DDRRAM */
-#define PHYS_SDRAM_SIZE 0x08000000 /* 128 megs */
-
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_SP_ADDR 0x01008000
-
-/*
- * FLASH and environment organization
- */
-#define CONFIG_SYS_FLASH_BASE 0x10000000
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_SYS_MAX_FLASH_SECT 256
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000)
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_SECT_SIZE (128 * 1024)
-#define CONFIG_ENV_SIZE (128 * 1024)
-
-/*
- * CFI FLASH driver setup
- */
-#define CONFIG_SYS_FLASH_CFI 1
-#define CONFIG_FLASH_CFI_DRIVER 1
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* ~10x faster */
-
-#define CONFIG_SYS_LOAD_ADDR 0x40000000 /* load address */
-
-#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM + (512*1024))
-#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM + PHYS_SDRAM_SIZE)
-
-#define CONFIG_BAUDRATE 115200
-
-#define CONFIG_SYS_PROMPT "jade> "
-#define CONFIG_SYS_CBSIZE 256
-#define CONFIG_SYS_MAXARGS 16
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
- sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_LONGHELP 1
-#define CONFIG_CMDLINE_EDITING 1
-
-#define CONFIG_PREBOOT ""
-
-#define CONFIG_BOOTDELAY 5
-#define CONFIG_AUTOBOOT_KEYED
-#define CONFIG_AUTOBOOT_PROMPT "boot in %d s\n", bootdelay
-#define CONFIG_AUTOBOOT_DELAY_STR "delaygs"
-#define CONFIG_AUTOBOOT_STOP_STR "stopgs"
-
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN (10 << 20)
-#define CONFIG_SYS_MEM_TOP_HIDE (4 << 20)
-
-/*
- * Clock reset generator init
- */
-#define CONFIG_SYS_CRG_CRHA_INIT 0xffff
-#define CONFIG_SYS_CRG_CRPA_INIT 0xffff
-#define CONFIG_SYS_CRG_CRPB_INIT 0xfffe
-#define CONFIG_SYS_CRG_CRHB_INIT 0xffff
-#define CONFIG_SYS_CRG_CRAM_INIT 0xffef
-
-/*
- * Memory controller settings
- */
-#define CONFIG_SYS_MEMC_MCFMODE0_INIT 0x00000001 /* 16bit */
-#define CONFIG_SYS_MEMC_MCFMODE2_INIT 0x00000001 /* 16bit */
-#define CONFIG_SYS_MEMC_MCFMODE4_INIT 0x00000021 /* 16bit, Page*/
-#define CONFIG_SYS_MEMC_MCFTIM0_INIT 0x16191008
-#define CONFIG_SYS_MEMC_MCFTIM2_INIT 0x03061008
-#define CONFIG_SYS_MEMC_MCFTIM4_INIT 0x03061804
-#define CONFIG_SYS_MEMC_MCFAREA0_INIT 0x000000c0 /* 0x0c000000 1MB */
-#define CONFIG_SYS_MEMC_MCFAREA2_INIT 0x00000020 /* 0x02000000 1MB */
-#define CONFIG_SYS_MEMC_MCFAREA4_INIT 0x001f0000 /* 0x10000000 32 MB */
-
-/*
- * DDR2 controller init settings
- */
-#define CONFIG_SYS_DDR2_DRIMS_INIT 0x5555
-#define CONFIG_SYS_CCNT_CDCRC_INIT_1 0x00000002
-#define CONFIG_SYS_CCNT_CDCRC_INIT_2 0x00000003
-#define CONFIG_SYS_DDR2_DRIC1_INIT 0x003f
-#define CONFIG_SYS_DDR2_DRIC2_INIT 0x0000
-#define CONFIG_SYS_DDR2_DRCA_INIT 0xc124 /* 512Mbit DDR2SDRAM x 2 */
-#define CONFIG_SYS_DDR2_DRCM_INIT 0x0032
-#define CONFIG_SYS_DDR2_DRCST1_INIT 0x3418
-#define CONFIG_SYS_DDR2_DRCST2_INIT 0x6e32
-#define CONFIG_SYS_DDR2_DRCR_INIT 0x0141
-#define CONFIG_SYS_DDR2_DRCF_INIT 0x0002
-#define CONFIG_SYS_DDR2_DRASR_INIT 0x0001
-#define CONFIG_SYS_DDR2_DROBS_INIT 0x0001
-#define CONFIG_SYS_DDR2_DROABA_INIT 0x0103
-#define CONFIG_SYS_DDR2_DRIBSODT1_INIT 0x003F
-#define CONFIG_SYS_DDR2_DROS_INIT 0x0001
-
-/*
- * DRAM init sequence
- */
-
-/* PALL Command */
-#define CONFIG_SYS_DDR2_INIT_DRIC1_1 0x0017
-#define CONFIG_SYS_DDR2_INIT_DRIC2_1 0x0400
-
-/* EMR(2) command */
-#define CONFIG_SYS_DDR2_INIT_DRIC1_2 0x0006
-#define CONFIG_SYS_DDR2_INIT_DRIC2_2 0x0000
-
-/* EMR(3) command */
-#define CONFIG_SYS_DDR2_INIT_DRIC1_3 0x0007
-#define CONFIG_SYS_DDR2_INIT_DRIC2_3 0x0000
-
-/* EMR(1) command */
-#define CONFIG_SYS_DDR2_INIT_DRIC1_4 0x0005
-#define CONFIG_SYS_DDR2_INIT_DRIC2_4 0x0000
-
-/* MRS command */
-#define CONFIG_SYS_DDR2_INIT_DRIC1_5 0x0004
-#define CONFIG_SYS_DDR2_INIT_DRIC2_5 0x0532
-
-/* PALL command */
-#define CONFIG_SYS_DDR2_INIT_DRIC1_6 0x0017
-#define CONFIG_SYS_DDR2_INIT_DRIC2_6 0x0400
-
-/* REF command 1 */
-#define CONFIG_SYS_DDR2_INIT_DRIC1_7 0x000f
-#define CONFIG_SYS_DDR2_INIT_DRIC2_7 0x0000
-
-/* MRS command */
-#define CONFIG_SYS_DDR2_INIT_DRIC1_8 0x0004
-#define CONFIG_SYS_DDR2_INIT_DRIC2_8 0x0432
-
-/* EMR(1) command */
-#define CONFIG_SYS_DDR2_INIT_DRIC1_9 0x0005
-#define CONFIG_SYS_DDR2_INIT_DRIC2_9 0x0380
-
-/* EMR(1) command */
-#define CONFIG_SYS_DDR2_INIT_DRIC1_10 0x0005
-#define CONFIG_SYS_DDR2_INIT_DRIC2_10 0x0002
-
-#endif /* __CONFIG_H */
#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
#define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"
+#define CONFIG_SYS_PCI_64BIT
+
+#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000
+#define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */
+#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000
+#define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */
+
+#define CONFIG_SYS_PCIE_IO_BUS 0x00000000
+#define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000
+#define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */
+
+#define CONFIG_SYS_PCIE_MEM_BUS 0x08000000
+#define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000
+#define CONFIG_SYS_PCIE_MEM_SIZE 0x08000000 /* 128M */
+
+#ifdef CONFIG_PCI
+#define CONFIG_NET_MULTI
+#define CONFIG_PCI_PNP
+#define CONFIG_E1000
+#define CONFIG_PCI_SCAN_SHOW
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_NET
+#endif
+
#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_MII
#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
#define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"
+#define CONFIG_SYS_PCI_64BIT
+
+#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000
+#define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */
+#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000
+#define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */
+
+#define CONFIG_SYS_PCIE_IO_BUS 0x00000000
+#define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000
+#define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */
+
+#define CONFIG_SYS_PCIE_MEM_BUS 0x08000000
+#define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000
+#define CONFIG_SYS_PCIE_MEM_SIZE 0x08000000 /* 128M */
+
+#ifdef CONFIG_PCI
+#define CONFIG_NET_MULTI
+#define CONFIG_PCI_PNP
+#define CONFIG_E1000
+#define CONFIG_PCI_SCAN_SHOW
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_NET
+#endif
+
#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_MII
#define CONFIG_FSL_LSCH3
#define CONFIG_LS2085A
#define CONFIG_GICV3
+#define CONFIG_FSL_TZPC_BP147
/* Link Definitions */
#define CONFIG_SYS_TEXT_BASE 0x30001000
#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_BOARD_EARLY_INIT_F 1
-#define CONFIG_IDENT_STRING " LS2085A-EMU"
-#define CONFIG_BOOTP_VCI_STRING "U-boot.LS2085A-EMU"
-
/* Flat Device Tree Definitions */
#define CONFIG_OF_LIBFDT
#define CONFIG_OF_BOARD_SETUP
#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (512UL * 1024 * 1024)
#define CONFIG_SYS_LS_MC_FW_IN_NOR
#define CONFIG_SYS_LS_MC_FW_ADDR 0x580200000ULL
-/* TODO Actual FW length needs to be determined at runtime from FW header */
-#define CONFIG_SYS_LS_MC_FW_LENGTH (4U * 1024 * 1024)
#define CONFIG_SYS_LS_MC_DPL_IN_NOR
#define CONFIG_SYS_LS_MC_DPL_ADDR 0x5806C0000ULL
/* TODO Actual DPL max length needs to be confirmed with the MC FW team */
-#define CONFIG_SYS_LS_MC_DPL_LENGTH 4096
+#define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH (256 * 1024)
#define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0xe00000
/* Carve the MC private DRAM block from the end of DRAM */
/* Physical Memory Map */
/* fixme: these need to be checked against the board */
#define CONFIG_CHIP_SELECTS_PER_CTRL 4
-#define CONFIG_SYS_CLK_FREQ 133333333
+#define CONFIG_SYS_CLK_FREQ 100000000
+#define CONFIG_DDR_CLK_FREQ 133333333
#define CONFIG_NR_DRAM_BANKS 3
"fdt_high=0xffffffffffffffff\0" \
"initrd_high=0xffffffffffffffff\0" \
"kernel_start=0x581200000\0" \
- "kernel_load=0x806f0000\0" \
+ "kernel_load=0xa0000000\0" \
"kernel_size=0x1000000\0" \
"console=ttyAMA0,38400n8\0"
-#define CONFIG_BOOTARGS "console=ttyS1,115200 root=/dev/ram0 " \
- "earlyprintk=uart8250-8bit,0x21c0600"
+#define CONFIG_BOOTARGS "console=ttyS1,115200 root=/dev/ram0 " \
+ "earlycon=uart8250,mmio,0x21c0600,115200 " \
+ "default_hugepagesz=2m hugepagesz=2m " \
+ "hugepages=16"
#define CONFIG_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \
"$kernel_size && bootm $kernel_load"
#define CONFIG_BOOTDELAY 1
#include "ls2085a_common.h"
+#define CONFIG_IDENT_STRING " LS2085A-EMU"
+#define CONFIG_BOOTP_VCI_STRING "U-boot.LS2085A-EMU"
+
#define CONFIG_DDR_SPD
#define CONFIG_SYS_FSL_DDR_EMU /* Support emulator */
#define SPD_EEPROM_ADDRESS1 0x51
#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
#define CONFIG_SYS_SPD_BUS_NUM 1 /* SPD on I2C bus 1 */
+#define CONFIG_FSL_DDR_SYNC_REFRESH
#endif /* __LS2_EMU_H */
#include "ls2085a_common.h"
+#define CONFIG_IDENT_STRING " LS2085A-SIMU"
+#define CONFIG_BOOTP_VCI_STRING "U-boot.LS2085A-SIMU"
+
/* SMSC 91C111 ethernet configuration */
#define CONFIG_SMC91111
#define CONFIG_SMC91111_BASE (0x2210000)
/* High Level Configuration Options */
#define CONFIG_MX31 1 /* This is a mx31 */
+#define CONFIG_SYS_GENERIC_BOARD
+
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_SYS_PL310_BASE L2_PL310_BASE
#endif
+#define CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
+
#define CONFIG_MP
#define CONFIG_MXC_GPT_HCLK
+++ /dev/null
-/*
- * Copyright (C) 2008 Texas Instruments, Inc <www.ti.com>
- *
- * Based on davinci_dvevm.h. Original Copyrights follow:
- *
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <linux/sizes.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/clock.h>
-
-/* Architecture, CPU, etc */
-#define CONFIG_TNETV107X
-#define CONFIG_TNETV107X_EVM
-#define CONFIG_TNETV107X_WATCHDOG
-#define CONFIG_ARCH_CPU_INIT
-#define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_DISABLE_TCM
-#define CONFIG_PERIPORT_REMAP
-#define CONFIG_PERIPORT_BASE 0x2000000
-#define CONFIG_PERIPORT_SIZE 0x10
-#define CONFIG_SYS_CLK_FREQ clk_get_rate(TNETV107X_LPSC_ARM)
-
-#define CONFIG_SYS_TIMERBASE TNETV107X_TIMER0_BASE
-#define CONFIG_SYS_HZ_CLOCK clk_get_rate(TNETV107X_LPSC_TIMER0)
-
-#define CONFIG_PLL_SYS_EXT_FREQ 25000000
-#define CONFIG_PLL_TDM_EXT_FREQ 19200000
-#define CONFIG_PLL_ETH_EXT_FREQ 25000000
-
-/* Memory Info */
-#define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024)
-#define PHYS_SDRAM_1 TNETV107X_DDR_EMIF_DATA_BASE
-#define PHYS_SDRAM_1_SIZE 0x04000000
-#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1
-#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 16*1024*1024)
-#define CONFIG_NR_DRAM_BANKS 1
-
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \
- CONFIG_SYS_INIT_RAM_SIZE - \
- GENERATED_GBL_DATA_SIZE)
-
-/* Serial Driver Info */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE -4
-#define CONFIG_SYS_NS16550_COM1 TNETV107X_UART1_BASE
-#define CONFIG_SYS_NS16550_CLK clk_get_rate(TNETV107X_LPSC_UART1)
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_BAUDRATE 115200
-
-/* Flash and environment info */
-#define CONFIG_SYS_NO_FLASH
-#define CONFIG_ENV_IS_IN_NAND
-#define CONFIG_NAND_DAVINCI
-#define CONFIG_ENV_SIZE (SZ_128K)
-#define CONFIG_SYS_NAND_HW_ECC
-#define CONFIG_SYS_NAND_1BIT_ECC
-#define CONFIG_SYS_NAND_CS 2
-#define CONFIG_SYS_NAND_USE_FLASH_BBT
-#define CONFIG_SYS_NAND_BASE TNETV107X_ASYNC_EMIF_DATA_CE0_BASE
-#define CONFIG_SYS_NAND_MASK_CLE 0x10
-#define CONFIG_SYS_NAND_MASK_ALE 0x8
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_MTD_PARTITIONS
-#define CONFIG_CMD_MTDPARTS
-#define CONFIG_MTD_DEVICE
-#define CONFIG_JFFS2_NAND
-#define CONFIG_ENV_OFFSET 0x180000
-
-/*
- * davinci_nand is a bit of a misnomer since this particular EMIF block is
- * commonly used across multiple TI devices. Unfortunately, this misnomer
- * (amongst others) carries forward into the kernel too. Consequently, if we
- * use a different device name here, the mtdparts variable won't be usable as
- * a kernel command-line argument.
- */
-#define MTDIDS_DEFAULT "nand0=davinci_nand.0"
-#define MTDPARTS_DEFAULT "mtdparts=davinci_nand.0:" \
- "1536k(uboot)ro," \
- "128k(params)ro," \
- "4m(kernel)," \
- "-(filesystem)"
-
-/* General U-Boot configuration */
-#define CONFIG_BOOTFILE "uImage"
-#define CONFIG_SYS_PROMPT "U-Boot > "
-#define CONFIG_SYS_CBSIZE 1024
-#define CONFIG_SYS_MAXARGS 64
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-#define CONFIG_VERSION_VARIABLE
-#define CONFIG_AUTO_COMPLETE
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_CMDLINE_EDITING
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_CRC32_VERIFY
-#define CONFIG_MX_CYCLIC
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
- sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_MEMTEST_START + \
- 0x700000)
-#define LINUX_BOOT_PARAM_ADDR (CONFIG_SYS_MEMTEST_START + 0x100)
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_BOOTARGS "mem=32M console=ttyS1,115200n8 " \
- "root=/dev/mmcblk0p1 rw noinitrd"
-#define CONFIG_BOOTCOMMAND ""
-#define CONFIG_BOOTDELAY 1
-
-#define CONFIG_CMD_BDI
-#define CONFIG_CMD_BOOTD
-#define CONFIG_CMD_CONSOLE
-#define CONFIG_CMD_ECHO
-#define CONFIG_CMD_EDITENV
-#define CONFIG_CMD_IMI
-#define CONFIG_CMD_ITEST
-#define CONFIG_CMD_LOADB
-#define CONFIG_CMD_LOADS
-#define CONFIG_CMD_MEMORY
-#define CONFIG_CMD_MISC
-#define CONFIG_CMD_RUN
-#define CONFIG_CMD_SAVEENV
-#define CONFIG_CMD_SOURCE
-#define CONFIG_CMD_ENV
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_SAVES
-#define CONFIG_CMD_MEMORY
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_JFFS2
-
-#endif /* __CONFIG_H */
#define CONFIG_MX25
#define CONFIG_SYS_TEXT_BASE 0xA0000000
+#define CONFIG_SYS_GENERIC_BOARD
+
#define CONFIG_SYS_TIMER_RATE 32768
#define CONFIG_SYS_TIMER_COUNTER \
(&((struct gpt_regs *)IMX_GPT1_BASE)->counter)
--- /dev/null
+/* Copyright 2014 Freescale Semiconductor Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+/*!
+ * @file fsl_dpmng.h
+ * @brief Management Complex General API
+ */
+
+#ifndef __FSL_DPMNG_H
+#define __FSL_DPMNG_H
+
+/*!
+ * @Group grp_dpmng Management Complex General API
+ *
+ * @brief Contains general API for the Management Complex firmware
+ * @{
+ */
+
+struct fsl_mc_io;
+
+/**
+ * @brief Management Complex firmware version information
+ */
+#define MC_VER_MAJOR 4
+#define MC_VER_MINOR 0
+
+struct mc_version {
+ uint32_t major;
+ /*!< Major version number: incremented on API compatibility changes */
+ uint32_t minor;
+ /*!< Minor version number: incremented on API additions (that are
+ * backward compatible); reset when major version is incremented
+ */
+ uint32_t revision;
+ /*!< Internal revision number: incremented on implementation changes
+ * and/or bug fixes that have no impact on API
+ */
+};
+
+/**
+ * @brief Retrieves the Management Complex firmware version information
+ *
+ * @param[in] mc_io Pointer to opaque I/O object
+ * @param[out] mc_ver_info Pointer to version information structure
+ *
+ * @returns '0' on Success; Error code otherwise.
+ */
+int mc_get_version(struct fsl_mc_io *mc_io, struct mc_version *mc_ver_info);
+
+/**
+ * @brief Resets an AIOP tile
+ *
+ * @param[in] mc_io Pointer to opaque I/O object
+ * @param[in] container_id AIOP container ID
+ * @param[in] aiop_tile_id AIOP tile ID to reset
+ *
+ * @returns '0' on Success; Error code otherwise.
+ */
+int dpmng_reset_aiop(struct fsl_mc_io *mc_io,
+ int container_id,
+ int aiop_tile_id);
+
+/**
+ * @brief Loads an image to AIOP tile
+ *
+ * @param[in] mc_io Pointer to opaque I/O object
+ * @param[in] container_id AIOP container ID
+ * @param[in] aiop_tile_id AIOP tile ID to reset
+ * @param[in] img_iova I/O virtual address of AIOP ELF image
+ * @param[in] img_size Size of AIOP ELF image in memory (in bytes)
+ *
+ * @returns '0' on Success; Error code otherwise.
+ */
+int dpmng_load_aiop(struct fsl_mc_io *mc_io,
+ int container_id,
+ int aiop_tile_id,
+ uint64_t img_iova,
+ uint32_t img_size);
+
+/**
+ * @brief AIOP run configuration
+ */
+struct dpmng_aiop_run_cfg {
+ uint32_t cores_mask;
+ /*!< Mask of AIOP cores to run (core 0 in most significant bit) */
+ uint64_t options;
+ /*!< Execution options (currently none defined) */
+};
+
+/**
+ * @brief Starts AIOP tile execution
+ *
+ * @param[in] mc_io Pointer to MC portal's I/O object
+ * @param[in] container_id AIOP container ID
+ * @param[in] aiop_tile_id AIOP tile ID to reset
+ * @param[in] cfg AIOP run configuration
+ *
+ * @returns '0' on Success; Error code otherwise.
+ */
+int dpmng_run_aiop(struct fsl_mc_io *mc_io,
+ int container_id,
+ int aiop_tile_id,
+ const struct dpmng_aiop_run_cfg *cfg);
+
+/**
+ * @brief Resets MC portal
+ *
+ * This function closes all object handles (tokens) that are currently
+ * open in the MC portal on which the command is submitted. This allows
+ * cleanup of stale handles that belong to non-functional user processes.
+ *
+ * @param[in] mc_io Pointer to MC portal's I/O object
+ *
+ * @returns '0' on Success; Error code otherwise.
+ */
+int dpmng_reset_mc_portal(struct fsl_mc_io *mc_io);
+
+/** @} */
+
+#endif /* __FSL_DPMNG_H */
--- /dev/null
+/*
+ * Copyright (C) 2014 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __FSL_MC_H__
+#define __FSL_MC_H__
+
+#include <common.h>
+
+#define MC_CCSR_BASE_ADDR \
+ ((struct mc_ccsr_registers __iomem *)0x8340000)
+
+#define BIT(x) (1 << (x))
+#define GCR1_P1_STOP BIT(31)
+#define GCR1_P2_STOP BIT(30)
+#define GCR1_P1_DE_RST BIT(23)
+#define GCR1_P2_DE_RST BIT(22)
+#define GCR1_M1_DE_RST BIT(15)
+#define GCR1_M2_DE_RST BIT(14)
+#define GCR1_M_ALL_DE_RST (GCR1_M1_DE_RST | GCR1_M2_DE_RST)
+#define GSR_FS_MASK 0x3fffffff
+#define MCFAPR_PL_MASK (0x1 << 18)
+#define MCFAPR_BMT_MASK (0x1 << 17)
+#define MCFAPR_BYPASS_ICID_MASK \
+ (MCFAPR_PL_MASK | MCFAPR_BMT_MASK)
+
+#define SOC_MC_PORTALS_BASE_ADDR ((void __iomem *)0x00080C000000)
+#define SOC_MC_PORTAL_STRIDE 0x10000
+
+#define SOC_MC_PORTAL_ADDR(_portal_id) \
+ ((void __iomem *)((uintptr_t)SOC_MC_PORTALS_BASE_ADDR + \
+ (_portal_id) * SOC_MC_PORTAL_STRIDE))
+
+struct mc_ccsr_registers {
+ u32 reg_gcr1;
+ u32 reserved1;
+ u32 reg_gsr;
+ u32 reserved2;
+ u32 reg_sicbalr;
+ u32 reg_sicbahr;
+ u32 reg_sicapr;
+ u32 reserved3;
+ u32 reg_mcfbalr;
+ u32 reg_mcfbahr;
+ u32 reg_mcfapr;
+ u32 reserved4[0x2f1];
+ u32 reg_psr;
+ u32 reserved5;
+ u32 reg_brr[2];
+ u32 reserved6[0x80];
+ u32 reg_error[];
+};
+
+int mc_init(bd_t *bis);
+
+int get_mc_boot_status(void);
+#endif
--- /dev/null
+/* Copyright 2014 Freescale Semiconductor Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef __FSL_MC_CMD_H
+#define __FSL_MC_CMD_H
+
+#define MC_CMD_NUM_OF_PARAMS 7
+
+#define MAKE_UMASK64(_width) \
+ ((uint64_t)((_width) < 64 ? ((uint64_t)1 << (_width)) - 1 : -1))
+
+static inline uint64_t u64_enc(int lsoffset, int width, uint64_t val)
+{
+ return (uint64_t)(((uint64_t)val & MAKE_UMASK64(width)) << lsoffset);
+}
+static inline uint64_t u64_dec(uint64_t val, int lsoffset, int width)
+{
+ return (uint64_t)((val >> lsoffset) & MAKE_UMASK64(width));
+}
+
+struct mc_command {
+ uint64_t header;
+ uint64_t params[MC_CMD_NUM_OF_PARAMS];
+};
+
+enum mc_cmd_status {
+ MC_CMD_STATUS_OK = 0x0, /*!< Completed successfully */
+ MC_CMD_STATUS_READY = 0x1, /*!< Ready to be processed */
+ MC_CMD_STATUS_AUTH_ERR = 0x3, /*!< Authentication error */
+ MC_CMD_STATUS_NO_PRIVILEGE = 0x4, /*!< No privilege */
+ MC_CMD_STATUS_DMA_ERR = 0x5, /*!< DMA or I/O error */
+ MC_CMD_STATUS_CONFIG_ERR = 0x6, /*!< Configuration error */
+ MC_CMD_STATUS_TIMEOUT = 0x7, /*!< Operation timed out */
+ MC_CMD_STATUS_NO_RESOURCE = 0x8, /*!< No resources */
+ MC_CMD_STATUS_NO_MEMORY = 0x9, /*!< No memory available */
+ MC_CMD_STATUS_BUSY = 0xA, /*!< Device is busy */
+ MC_CMD_STATUS_UNSUPPORTED_OP = 0xB, /*!< Unsupported operation */
+ MC_CMD_STATUS_INVALID_STATE = 0xC /*!< Invalid state */
+};
+
+#define MC_CMD_HDR_CMDID_O 52 /* Command ID field offset */
+#define MC_CMD_HDR_CMDID_S 12 /* Command ID field size */
+#define MC_CMD_HDR_AUTHID_O 38 /* Authentication ID field offset */
+#define MC_CMD_HDR_AUTHID_S 10 /* Authentication ID field size */
+#define MC_CMD_HDR_STATUS_O 16 /* Status field offset */
+#define MC_CMD_HDR_STATUS_S 8 /* Status field size*/
+#define MC_CMD_HDR_PRI_O 15 /* Priority field offset */
+#define MC_CMD_HDR_PRI_S 1 /* Priority field size */
+
+#define MC_CMD_HDR_READ_STATUS(_hdr) \
+ ((enum mc_cmd_status)u64_dec((_hdr), \
+ MC_CMD_HDR_STATUS_O, MC_CMD_HDR_STATUS_S))
+
+#define MC_CMD_HDR_READ_AUTHID(_hdr) \
+ ((uint16_t)u64_dec((_hdr), MC_CMD_HDR_AUTHID_O, MC_CMD_HDR_AUTHID_S))
+
+#define MC_CMD_PRI_LOW 0 /*!< Low Priority command indication */
+#define MC_CMD_PRI_HIGH 1 /*!< High Priority command indication */
+
+#define MC_CMD_OP(_cmd, _param, _offset, _width, _type, _arg) \
+ ((_cmd).params[_param] |= u64_enc((_offset), (_width), _arg))
+
+#define MC_RSP_OP(_cmd, _param, _offset, _width, _type, _arg) \
+ (_arg = (_type)u64_dec(_cmd.params[_param], (_offset), (_width)))
+
+static inline uint64_t mc_encode_cmd_header(uint16_t cmd_id,
+ uint8_t priority,
+ uint16_t auth_id)
+{
+ uint64_t hdr;
+
+ hdr = u64_enc(MC_CMD_HDR_CMDID_O, MC_CMD_HDR_CMDID_S, cmd_id);
+ hdr |= u64_enc(MC_CMD_HDR_AUTHID_O, MC_CMD_HDR_AUTHID_S, auth_id);
+ hdr |= u64_enc(MC_CMD_HDR_PRI_O, MC_CMD_HDR_PRI_S, priority);
+ hdr |= u64_enc(MC_CMD_HDR_STATUS_O, MC_CMD_HDR_STATUS_S,
+ MC_CMD_STATUS_READY);
+
+ return hdr;
+}
+
+/**
+ * mc_write_command - writes a command to a Management Complex (MC) portal
+ *
+ * @portal: pointer to an MC portal
+ * @cmd: pointer to a filled command
+ */
+static inline void mc_write_command(struct mc_command __iomem *portal,
+ struct mc_command *cmd)
+{
+ int i;
+
+ /* copy command parameters into the portal */
+ for (i = 0; i < MC_CMD_NUM_OF_PARAMS; i++)
+ writeq(cmd->params[i], &portal->params[i]);
+
+ /* submit the command by writing the header */
+ writeq(cmd->header, &portal->header);
+}
+
+/**
+ * mc_read_response - reads the response for the last MC command from a
+ * Management Complex (MC) portal
+ *
+ * @portal: pointer to an MC portal
+ * @resp: pointer to command response buffer
+ *
+ * Returns MC_CMD_STATUS_OK on Success; Error code otherwise.
+ */
+static inline enum mc_cmd_status mc_read_response(
+ struct mc_command __iomem *portal,
+ struct mc_command *resp)
+{
+ int i;
+ enum mc_cmd_status status;
+
+ /* Copy command response header from MC portal: */
+ resp->header = readq(&portal->header);
+ status = MC_CMD_HDR_READ_STATUS(resp->header);
+ if (status != MC_CMD_STATUS_OK)
+ return status;
+
+ /* Copy command response data from MC portal: */
+ for (i = 0; i < MC_CMD_NUM_OF_PARAMS; i++)
+ resp->params[i] = readq(&portal->params[i]);
+
+ return status;
+}
+
+int mc_send_command(struct fsl_mc_io *mc_io, struct mc_command *cmd);
+
+#endif /* __FSL_MC_CMD_H */
--- /dev/null
+/*
+ * Freescale Layerscape Management Complex (MC) Environment-specific code
+ *
+ * Copyright (C) 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _FSL_MC_SYS_H
+#define _FSL_MC_SYS_H
+
+#include <asm/io.h>
+
+struct mc_command;
+
+/*
+ * struct mc_portal_wrapper - MC command portal wrapper object
+ */
+struct fsl_mc_io {
+ struct mc_command __iomem *mmio_regs;
+};
+
+int mc_send_command(struct fsl_mc_io *mc_io,
+ struct mc_command *cmd);
+
+#endif /* _FSL_MC_SYS_H */
* to this specific DDR technology.
*/
static __inline__ int
-compute_dimm_parameters(const generic_spd_eeprom_t *spd,
+compute_dimm_parameters(const unsigned int ctrl_num,
+ const generic_spd_eeprom_t *spd,
dimm_params_t *pdimm,
unsigned int dimm_number)
{
- return ddr_compute_dimm_parameters(spd, pdimm, dimm_number);
+ return ddr_compute_dimm_parameters(ctrl_num, spd, pdimm, dimm_number);
}
#endif
unsigned int size_only);
const char *step_to_string(unsigned int step);
-unsigned int compute_fsl_memctl_config_regs(const memctl_options_t *popts,
+unsigned int compute_fsl_memctl_config_regs(const unsigned int ctrl_num,
+ const memctl_options_t *popts,
fsl_ddr_cfg_regs_t *ddr,
const common_timing_params_t *common_dimm,
const dimm_params_t *dimm_parameters,
unsigned int dbw_capacity_adjust,
unsigned int size_only);
unsigned int compute_lowest_common_dimm_parameters(
+ const unsigned int ctrl_num,
const dimm_params_t *dimm_params,
common_timing_params_t *outpdimm,
unsigned int number_of_dimms);
unsigned int ctrl_num);
void check_interleaving_options(fsl_ddr_info_t *pinfo);
-unsigned int mclk_to_picos(unsigned int mclk);
-unsigned int get_memory_clk_period_ps(void);
-unsigned int picos_to_mclk(unsigned int picos);
+unsigned int mclk_to_picos(const unsigned int ctrl_num, unsigned int mclk);
+unsigned int get_memory_clk_period_ps(const unsigned int ctrl_num);
+unsigned int picos_to_mclk(const unsigned int ctrl_num, unsigned int picos);
void fsl_ddr_set_lawbar(
const common_timing_params_t *memctl_common_params,
unsigned int memctl_interleaved,
unsigned int ctrl_num);
+void fsl_ddr_sync_memctl_refresh(unsigned int first_ctrl,
+ unsigned int last_ctrl);
int fsl_ddr_interactive_env_var_exists(void);
unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo, int var_is_set);
#endif
} dimm_params_t;
-extern unsigned int ddr_compute_dimm_parameters(
+unsigned int ddr_compute_dimm_parameters(const unsigned int ctrl_num,
const generic_spd_eeprom_t *spd,
dimm_params_t *pdimm,
unsigned int dimm_number);
#define XFERTYP_RSPTYP_48_BUSY 0x00030000
#define XFERTYP_MSBSEL 0x00000020
#define XFERTYP_DTDSEL 0x00000010
+#define XFERTYP_DDREN 0x00000008
#define XFERTYP_AC12EN 0x00000004
#define XFERTYP_BCEN 0x00000002
#define XFERTYP_DMAEN 0x00000001
+++ /dev/null
-/*
- * Copyright (C) 2014 Freescale Semiconductor
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __FSL_MC_H__
-#define __FSL_MC_H__
-
-#include <common.h>
-
-#define MC_CCSR_BASE_ADDR \
- ((struct mc_ccsr_registers __iomem *)0x8340000)
-
-#define BIT(x) (1 << (x))
-#define GCR1_P1_STOP BIT(31)
-#define GCR1_P2_STOP BIT(30)
-#define GCR1_P1_DE_RST BIT(23)
-#define GCR1_P2_DE_RST BIT(22)
-#define GCR1_M1_DE_RST BIT(15)
-#define GCR1_M2_DE_RST BIT(14)
-#define GCR1_M_ALL_DE_RST (GCR1_M1_DE_RST | GCR1_M2_DE_RST)
-#define GSR_FS_MASK 0x3fffffff
-#define MCFAPR_PL_MASK (0x1 << 18)
-#define MCFAPR_BMT_MASK (0x1 << 17)
-#define MCFAPR_BYPASS_ICID_MASK \
- (MCFAPR_PL_MASK | MCFAPR_BMT_MASK)
-
-#define SOC_MC_PORTALS_BASE_ADDR ((void __iomem *)0x00080C000000)
-#define SOC_MC_PORTAL_STRIDE 0x10000
-
-#define SOC_MC_PORTAL_ADDR(_portal_id) \
- ((void __iomem *)((uintptr_t)SOC_MC_PORTALS_BASE_ADDR + \
- (_portal_id) * SOC_MC_PORTAL_STRIDE))
-
-struct mc_ccsr_registers {
- u32 reg_gcr1;
- u32 reserved1;
- u32 reg_gsr;
- u32 reserved2;
- u32 reg_sicbalr;
- u32 reg_sicbahr;
- u32 reg_sicapr;
- u32 reserved3;
- u32 reg_mcfbalr;
- u32 reg_mcfbahr;
- u32 reg_mcfapr;
- u32 reserved4[0x2f1];
- u32 reg_psr;
- u32 reserved5;
- u32 reg_brr[2];
- u32 reserved6[0x80];
- u32 reg_error[];
-};
-
-int mc_init(bd_t *bis);
-
-int get_mc_boot_status(void);
-#endif
u32 jrcr;
};
+/*
+ * Scatter Gather Entry - Specifies the the Scatter Gather Format
+ * related information
+ */
+struct sg_entry {
+#ifdef CONFIG_SYS_FSL_SEC_LE
+ uint32_t addr_lo; /* Memory Address - lo */
+ uint16_t addr_hi; /* Memory Address of start of buffer - hi */
+ uint16_t reserved_zero;
+#else
+ uint16_t reserved_zero;
+ uint16_t addr_hi; /* Memory Address of start of buffer - hi */
+ uint32_t addr_lo; /* Memory Address - lo */
+#endif
+
+ uint32_t len_flag; /* Length of the data in the frame */
+#define SG_ENTRY_LENGTH_MASK 0x3FFFFFFF
+#define SG_ENTRY_EXTENSION_BIT 0x80000000
+#define SG_ENTRY_FINAL_BIT 0x40000000
+ uint32_t bpid_offset;
+#define SG_ENTRY_BPID_MASK 0x00FF0000
+#define SG_ENTRY_BPID_SHIFT 16
+#define SG_ENTRY_OFFSET_MASK 0x00001FFF
+#define SG_ENTRY_OFFSET_SHIFT 0
+};
+
int sec_init(void);
#endif
*/
#ifndef __HW_SHA_H
#define __HW_SHA_H
-
+#include <hash.h>
/**
* Computes hash value of input pbuf using h/w acceleration
*/
void hw_sha1(const uchar * in_addr, uint buflen,
uchar * out_addr, uint chunk_size);
+
+/*
+ * Create the context for sha progressive hashing using h/w acceleration
+ *
+ * @algo: Pointer to the hash_algo struct
+ * @ctxp: Pointer to the pointer of the context for hashing
+ * @return 0 if ok, -ve on error
+ */
+int hw_sha_init(struct hash_algo *algo, void **ctxp);
+
+/*
+ * Update buffer for sha progressive hashing using h/w acceleration
+ *
+ * The context is freed by this function if an error occurs.
+ *
+ * @algo: Pointer to the hash_algo struct
+ * @ctx: Pointer to the context for hashing
+ * @buf: Pointer to the buffer being hashed
+ * @size: Size of the buffer being hashed
+ * @is_last: 1 if this is the last update; 0 otherwise
+ * @return 0 if ok, -ve on error
+ */
+int hw_sha_update(struct hash_algo *algo, void *ctx, const void *buf,
+ unsigned int size, int is_last);
+
+/*
+ * Copy sha hash result at destination location
+ *
+ * The context is freed after completion of hash operation or after an error.
+ *
+ * @algo: Pointer to the hash_algo struct
+ * @ctx: Pointer to the context for hashing
+ * @dest_buf: Pointer to the destination buffer where hash is to be copied
+ * @size: Size of the buffer being hashed
+ * @return 0 if ok, -ve on error
+ */
+int hw_sha_finish(struct hash_algo *algo, void *ctx, void *dest_buf,
+ int size);
+
#endif
int ftmac110_initialize(bd_t *bits);
int greth_initialize(bd_t *bis);
void gt6426x_eth_initialize(bd_t *bis);
-int ks8695_eth_initialize(void);
int ks8851_mll_initialize(u8 dev_num, int base_addr);
int lan91c96_initialize(u8 dev_num, int base_addr);
int macb_eth_initialize(int id, void *regs, unsigned int phy_addr);
#if defined(CONFIG_405GP) || \
defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
defined(CONFIG_405EX) || defined(CONFIG_440) || \
- defined(CONFIG_MB86R0x) || defined(CONFIG_MPC5xxx) || \
+ defined(CONFIG_MPC5xxx) || \
defined(CONFIG_MPC83xx) || defined(CONFIG_MPC85xx) || \
defined(CONFIG_MPC86xx) || defined(CONFIG_SYS_SC520) || \
defined(CONFIG_TEGRA) || defined(CONFIG_SYS_COREBOOT) || \
void imx_serial_initialize(void);
void iop480_serial_initialize(void);
void jz_serial_initialize(void);
-void ks8695_serial_initialize(void);
void leon2_serial_initialize(void);
void leon3_serial_initialize(void);
void lh7a40x_serial_initialize(void);
source lib/rsa/Kconfig
+menu "Hashing Support"
+
+config SHA1
+ bool "Enable SHA1 support"
+ help
+ This option enables support of hashing using SHA1 algorithm.
+ The hash is calculated in software.
+ The SHA1 algorithm produces a 160-bit (20-byte) hash value
+ (digest).
+
+config SHA256
+ bool "Enable SHA256 support"
+ help
+ This option enables support of hashing using SHA256 algorithm.
+ The hash is calculated in software.
+ The SHA256 algorithm produces a 256-bit (32-byte) hash value
+ (digest).
+
+config SHA_HW_ACCEL
+ bool "Enable hashing using hardware"
+ help
+ This option enables hardware acceleration
+ for SHA1/SHA256 hashing.
+ This affects the 'hash' command and also the
+ hash_lookup_algo() function.
+
+config SHA_PROG_HW_ACCEL
+ bool "Enable Progressive hashing support using hardware"
+ depends on SHA_HW_ACCEL
+ help
+ This option enables hardware-acceleration for
+ SHA1/SHA256 progressive hashing.
+ Data can be streamed in a block at a time and the hashing
+ is performed in hardware.
+endmenu
+
endmenu
# (= When we move all CONFIGs from header files to Kconfig)
# this makefile can be deleted.
-# obj is "include" or "spl/include" or "tpl/include"
-# for non-SPL, SPL, TPL, respectively
-include $(obj)/config/auto.conf
+__all: include/autoconf.mk include/autoconf.mk.dep
+
+ifeq ($(shell grep -q '^CONFIG_SPL=y' include/config/auto.conf 2>/dev/null && echo y),y)
+__all: spl/include/autoconf.mk
+endif
+
+ifeq ($(shell grep -q '^CONFIG_TPL=y' include/config/auto.conf 2>/dev/null && echo y),y)
+__all: tpl/include/autoconf.mk
+endif
+
+include include/config/auto.conf
include scripts/Kbuild.include
include config.mk
UBOOTINCLUDE := \
- -I$(obj) \
-Iinclude \
$(if $(KBUILD_SRC), -I$(srctree)/include) \
-I$(srctree)/arch/$(ARCH)/include \
# same CONFIG macros
quiet_cmd_autoconf = GEN $@
cmd_autoconf = \
- $(CPP) $(c_flags) -DDO_DEPS_ONLY -dM $(srctree)/include/common.h > $@.tmp && { \
+ $(CPP) $(c_flags) $2 -DDO_DEPS_ONLY -dM $(srctree)/include/common.h > $@.tmp && { \
sed -n -f $(srctree)/tools/scripts/define2mk.sed $@.tmp | \
while read line; do \
- if ! grep -q "$${line%=*}=" $(obj)/config/auto.conf; then \
+ if ! grep -q "$${line%=*}=" include/config/auto.conf; then \
echo "$$line"; \
fi \
done > $@; \
rm $@.tmp; false; \
}
-$(obj)/autoconf.mk: FORCE
+include/autoconf.mk: FORCE
$(call cmd,autoconf)
-include/autoconf.mk include/autoconf.mk.dep: include/config.h
+spl/include/autoconf.mk: FORCE
+ $(Q)mkdir -p $(dir $@)
+ $(call cmd,autoconf,-DCONFIG_SPL_BUILD)
+
+tpl/include/autoconf.mk: FORCE
+ $(Q)mkdir -p $(dir $@)
+ $(call cmd,autoconf,-DCONFIG_SPL_BUILD -DCONFIG_TPL_BUILD)
+
+include/autoconf.mk include/autoconf.mk.dep \
+ spl/include/autoconf.mk tpl/include/autoconf.mk: include/config.h
# include/config.h
# Prior to Kconfig, it was generated by mkconfig. Now it is created here.
done; \
echo \#define CONFIG_BOARDDIR board/$(if $(VENDOR),$(VENDOR)/)$(BOARD);\
echo \#include \<config_defaults.h\>; \
+ echo \#include \<config_uncmd_spl.h\>; \
echo \#include \<configs/$(CONFIG_SYS_CONFIG_NAME).h\>; \
echo \#include \<asm/config.h\>; \
- echo \#include \<config_fallbacks.h\>; \
- echo \#include \<config_uncmd_spl.h\>; )
+ echo \#include \<config_fallbacks.h\>;)
endef
include/config.h: scripts/Makefile.autoconf create_symlink FORCE
# Read auto.conf if it exists, otherwise ignore
# Modified for U-Boot
--include $(prefix)/include/config/auto.conf
+-include include/config/auto.conf
-include $(prefix)/include/autoconf.mk
+include scripts/Makefile.uncmd_spl
include scripts/Kbuild.include
include $(srctree)/scripts/Kbuild.include
-UBOOTINCLUDE := -I$(obj)/include $(UBOOTINCLUDE)
-
--include $(obj)/include/config/auto.conf
+-include include/config/auto.conf
-include $(obj)/include/autoconf.mk
+KBUILD_CPPFLAGS += -DCONFIG_SPL_BUILD
+ifeq ($(CONFIG_TPL_BUILD),y)
+KBUILD_CPPFLAGS += -DCONFIG_TPL_BUILD
+endif
+
ifeq ($(CONFIG_TPL_BUILD),y)
-export CONFIG_TPL_BUILD
SPL_BIN := u-boot-tpl
else
SPL_BIN := u-boot-spl
--- /dev/null
+# Makefile version of include/config_uncmd_spl.h
+#
+# TODO: Invent a better way
+
+ifdef CONFIG_SPL_BUILD
+CONFIG_OF_CONTROL=
+
+ifndef CONFIG_SPL_DM
+CONFIG_DM_SERIAL=
+CONFIG_DM_GPIO=
+CONIFG_DM_I2C=
+CONFIG_DM_SPI=
+CONFIG_DM_SPI_FLASH=
+endif
+
+CONFIG_DM_DEVICE_REMOVE=
+
+endif
#
# A wrapper script to adjust Kconfig for U-Boot
#
-# Instead of touching various parts under the scripts/kconfig/ directory,
-# pushing necessary adjustments into this single script would be better
-# for code maintainance. All the make targets related to the configuration
-# (make %config) should be invoked via this script.
-# See doc/README.kconfig for further information of Kconfig.
+# This file will be removed after cleaning up defconfig files
#
# Copyright (C) 2014, Masahiro Yamada <yamada.m@jp.panasonic.com>
#
set -e
-# Set "DEBUG" enavironment variable to show debug messages
-debug () {
- if [ $DEBUG ]; then
- echo "$@"
- fi
-}
-
-# Useful shorthands
-build () {
- debug $progname: $MAKE -f $srctree/scripts/Makefile.build obj="$@"
- $MAKE -f $srctree/scripts/Makefile.build obj="$@"
-}
-
-autoconf () {
- debug $progname: $MAKE -f $srctree/scripts/Makefile.autoconf obj="$@"
- $MAKE -f $srctree/scripts/Makefile.autoconf obj="$@"
-}
-
# Make a configuration target
# Usage:
# run_make_config <target> <objdir>
# <target>: Make target such as "config", "menuconfig", "defconfig", etc.
-# <objdir>: Target directory where the make command is run.
-# Typically "", "spl", "tpl" for Normal, SPL, TPL, respectively.
run_make_config () {
- target=$1
- objdir=$2
-
# Linux expects defconfig files in arch/$(SRCARCH)/configs/ directory,
# but U-Boot has them in configs/ directory.
# Give SRCARCH=.. to fake scripts/kconfig/Makefile.
- options="SRCARCH=.. KCONFIG_OBJDIR=$objdir"
- if [ "$objdir" ]; then
- options="$options KCONFIG_CONFIG=$objdir/$KCONFIG_CONFIG"
- mkdir -p $objdir
- fi
-
- build scripts/kconfig $options $target
-}
-
-# Parse .config file to detect if CONFIG_SPL, CONFIG_TPL is enabled
-# and returns:
-# "" if neither CONFIG_SPL nor CONFIG_TPL is defined
-# "spl" if CONFIG_SPL is defined but CONFIG_TPL is not
-# "spl tpl" if both CONFIG_SPL and CONFIG_TPL are defined
-get_enabled_subimages() {
- if [ ! -r "$KCONFIG_CONFIG" ]; then
- # This should never happen
- echo "$progname: $KCONFIG_CONFIG not found" >&2
- exit 1
- fi
-
- # CONFIG_SPL=y -> spl
- # CONFIG_TPL=y -> tpl
- sed -n -e 's/^CONFIG_SPL=y$/spl/p' -e 's/^CONFIG_TPL=y$/tpl/p' \
- $KCONFIG_CONFIG
+ $MAKE -f $srctree/scripts/Makefile.build obj=scripts/kconfig SRCARCH=.. $1
}
do_silentoldconfig () {
run_make_config silentoldconfig
- subimages=$(get_enabled_subimages)
-
- for obj in $subimages
- do
- mkdir -p $obj/include/config $obj/include/generated
- run_make_config silentoldconfig $obj
- done
# If the following part fails, include/config/auto.conf should be
# deleted so "make silentoldconfig" will be re-run on the next build.
- autoconf include include/autoconf.mk include/autoconf.mk.dep || {
+ $MAKE -f $srctree/scripts/Makefile.autoconf || {
rm -f include/config/auto.conf
exit 1
}
# than include/config.h.
# Otherwise, 'make silentoldconfig' would be invoked twice.
touch include/config/auto.conf
-
- for obj in $subimages
- do
- autoconf $obj/include $obj/include/autoconf.mk || {
- rm -f include/config/auto.conf
- exit 1
- }
- done
}
cleanup_after_defconfig () {
# do_board_defconfig <board>_defconfig
do_board_defconfig () {
defconfig_path=$srctree/configs/$1
- tmp_defconfig_path=configs/.tmp_defconfig
if [ ! -r $defconfig_path ]; then
echo >&2 "***"
fi
mkdir -p arch configs
- # defconfig for Normal:
- # pick lines without prefixes and lines starting '+' prefix
- # and rip the prefixes off.
- sed -n -e '/^[+A-Z]*:/!p' -e 's/^+[A-Z]*://p' $defconfig_path \
- > configs/.tmp_defconfig
+ # prefix "*:" is deprecated. Drop it simply.
+ sed -e 's/^[+A-Z]*://' $defconfig_path > configs/.tmp_defconfig
run_make_config .tmp_defconfig || {
cleanup_after_defconfig
exit 1
}
- for img in $(get_enabled_subimages)
- do
- symbol=$(echo $img | cut -c 1 | tr '[a-z]' '[A-Z]')
- # defconfig for SPL, TPL:
- # pick lines with 'S', 'T' prefix and rip the prefixes off
- sed -n -e 's/^[+A-Z]*'$symbol'[A-Z]*://p' $defconfig_path \
- > configs/.tmp_defconfig
- run_make_config .tmp_defconfig $img || {
- cleanup_after_defconfig
- exit 1
- }
- done
-
cleanup_after_defconfig
}
-do_defconfig () {
- if [ "$KBUILD_DEFCONFIG" ]; then
- do_board_defconfig $KBUILD_DEFCONFIG
- echo "*** Default configuration is based on '$KBUILD_DEFCONFIG'"
- else
- run_make_config defconfig
- fi
-}
-
do_board_felconfig () {
do_board_defconfig ${1%%_felconfig}_defconfig
if ! grep -q CONFIG_ARCH_SUNXI=y .config || ! grep -q CONFIG_SPL=y .config ; then
exit 1
fi
sed -i -e 's/\# CONFIG_SPL_FEL is not set/CONFIG_SPL_FEL=y\nCONFIG_UART0_PORT_F=n/g' \
- .config spl/.config
+ .config
}
-do_savedefconfig () {
- if [ -r "$KCONFIG_CONFIG" ]; then
- subimages=$(get_enabled_subimages)
- else
- subimages=
- fi
-
- run_make_config savedefconfig
-
- output_lines=
-
- # -r option is necessay because some string-type configs may include
- # backslashes as an escape character
- while read -r line
- do
- output_lines="$output_lines%$line"
- done < defconfig
-
- for img in $subimages
- do
- run_make_config savedefconfig $img
-
- symbol=$(echo $img | cut -c 1 | tr '[a-z]' '[A-Z]')
- unmatched=
-
- while read -r line
- do
- tmp=
- match=
-
- # "# CONFIG_FOO is not set" should not be divided.
- # Use "%" as a separator, instead of a whitespace.
- # "%" is unlikely to appear in defconfig context.
- save_IFS=$IFS
- IFS=%
- # coalesce common lines together
- for i in $output_lines
- do
- case "$i" in
- [+A-Z]*:$line)
- tmp="$tmp%$unmatched"
- i=$(echo "$i" | \
- sed -e "s/^\([^:]*\)/\1$symbol/")
- tmp="$tmp%$i"
- match=1
- ;;
- $line)
- tmp="$tmp%$unmatched"
- tmp="$tmp%+$symbol:$i"
- match=1
- ;;
- *)
- tmp="$tmp%$i"
- ;;
- esac
- done
-
- # Restore the default separator for the outer for loop.
- IFS=$save_IFS
-
- if [ "$match" ]; then
- output_lines="$tmp"
- unmatched=
- else
- unmatched="$unmatched%$symbol:$line"
- fi
- done < defconfig
-
- output_lines="$output_lines%$unmatched"
- done
-
- rm -f defconfig
- touch defconfig
-
- save_IFS=$IFS
- IFS=%
-
- for line in $output_lines
- do
- case "$line" in
- "")
- # do not output blank lines
- ;;
- *)
- echo $line >> defconfig
- ;;
- esac
- done
-
- IFS=$save_IFS
-}
-
-# Some sanity checks before running "make <objdir>/<target>",
-# where <objdir> should be either "spl" or "tpl".
-# Doing "make spl/menuconfig" etc. on a non-SPL board makes no sense.
-# It should be allowed only when ".config" exists and "CONFIG_SPL" is enabled.
-#
-# Usage:
-# check_enabled_sumbimage <objdir>/<target> <objdir>
-check_enabled_subimage () {
-
- case $2 in
- spl|tpl) ;;
- *)
- echo >&2 "***"
- echo >&2 "*** \"make $1\" is not supported."
- echo >&2 "***"
- exit 1
- ;;
- esac
- test -r "$KCONFIG_CONFIG" && get_enabled_subimages | grep -q $2 || {
- config=CONFIG_$(echo $2 | tr '[a-z]' '[A-Z]')
-
- echo >&2 "***"
- echo >&2 "*** Create \"$KCONFIG_CONFIG\" with \"$config\" enabled"
- echo >&2 "*** before \"make $1\"."
- echo >&2 "***"
- exit 1
- }
-}
-
-# Usage:
-# do_others <objdir>/<target>
-# The field "<objdir>/" is typically empy, "spl/", "tpl/" for Normal, SPL, TPL,
-# respectively.
-# The field "<target>" is a configuration target such as "config",
-# "menuconfig", etc.
do_others () {
- target=${1##*/}
-
- if [ "$target" = "$1" ]; then
- objdir=
- else
- objdir=${1%/*}
- check_enabled_subimage $1 $objdir
-
- if [ -f "$objdir/$KCONFIG_CONFIG" ]; then
- timestamp_before=$(stat --printf="%Y" \
- $objdir/$KCONFIG_CONFIG)
- fi
- fi
-
- run_make_config $target $objdir
-
- if [ "$timestamp_before" -a -f "$objdir/$KCONFIG_CONFIG" ]; then
- timestamp_after=$(stat --printf="%Y" $objdir/$KCONFIG_CONFIG)
-
- if [ "$timestamp_after" -gt "$timestamp_before" ]; then
- # $objdir/.config has been updated.
- # touch .config to invoke "make silentoldconfig"
- touch $KCONFIG_CONFIG
- fi
- fi
+ run_make_config $1
}
progname=$(basename $0)
do_board_defconfig ${target%_config}_defconfig;;
silentoldconfig)
do_silentoldconfig;;
-defconfig)
- do_defconfig;;
-savedefconfig)
- do_savedefconfig;;
*)
do_others $target;;
esac
projects / oweals / u-boot.git / commitdiff