3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
13 * The Serial Management Controllers (SMC) and the Serial Communication
14 * Controllers (SCC) listed in ctlr_list array below are tested in
15 * the loopback UART mode.
16 * The controllers are configured accordingly and several characters
17 * are transmitted. The configurable test parameters are:
18 * MIN_PACKET_LENGTH - minimum size of packet to transmit
19 * MAX_PACKET_LENGTH - maximum size of packet to transmit
20 * TEST_NUM - number of tests
24 #if CONFIG_POST & CONFIG_SYS_POST_UART
25 #if defined(CONFIG_8xx)
27 #elif defined(CONFIG_MPC8260)
28 #include <asm/cpm_8260.h>
30 #error "Apparently a bad configuration, please fix."
35 DECLARE_GLOBAL_DATA_PTR;
40 /* The list of controllers to test */
41 #if defined(CONFIG_MPC823)
42 static int ctlr_list[][2] =
43 { {CTLR_SMC, 0}, {CTLR_SMC, 1}, {CTLR_SCC, 1} };
45 static int ctlr_list[][2] = { };
49 void (*init) (int index);
50 void (*halt) (int index);
51 void (*putc) (int index, const char c);
52 int (*getc) (int index);
55 static char *ctlr_name[2] = { "SMC", "SCC" };
57 static int proff_smc[] = { PROFF_SMC1, PROFF_SMC2 };
58 static int proff_scc[] =
59 { PROFF_SCC1, PROFF_SCC2, PROFF_SCC3, PROFF_SCC4 };
65 static void smc_init (int smc_index)
67 static int cpm_cr_ch[] = { CPM_CR_CH_SMC1, CPM_CR_CH_SMC2 };
69 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
71 volatile smc_uart_t *up;
72 volatile cbd_t *tbdf, *rbdf;
73 volatile cpm8xx_t *cp = &(im->im_cpm);
76 /* initialize pointers to SMC */
78 sp = (smc_t *) & (cp->cp_smc[smc_index]);
79 up = (smc_uart_t *) & cp->cp_dparam[proff_smc[smc_index]];
81 /* Disable transmitter/receiver.
83 sp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
87 im->im_siu_conf.sc_sdcr = 1;
89 /* clear error conditions */
90 #ifdef CONFIG_SYS_SDSR
91 im->im_sdma.sdma_sdsr = CONFIG_SYS_SDSR;
93 im->im_sdma.sdma_sdsr = 0x83;
96 /* clear SDMA interrupt mask */
97 #ifdef CONFIG_SYS_SDMR
98 im->im_sdma.sdma_sdmr = CONFIG_SYS_SDMR;
100 im->im_sdma.sdma_sdmr = 0x00;
103 /* Set the physical address of the host memory buffers in
104 * the buffer descriptors.
106 dpaddr = CPM_POST_BASE;
108 /* Allocate space for two buffer descriptors in the DP ram.
109 * For now, this address seems OK, but it may have to
110 * change with newer versions of the firmware.
111 * damm: allocating space after the two buffers for rx/tx data
114 rbdf = (cbd_t *) & cp->cp_dpmem[dpaddr];
115 rbdf->cbd_bufaddr = (uint) (rbdf + 2);
118 tbdf->cbd_bufaddr = ((uint) (rbdf + 2)) + 1;
121 /* Set up the uart parameters in the parameter ram.
123 up->smc_rbase = dpaddr;
124 up->smc_tbase = dpaddr + sizeof (cbd_t);
125 up->smc_rfcr = SMC_EB;
126 up->smc_tfcr = SMC_EB;
128 /* Set UART mode, 8 bit, no parity, one stop.
129 * Enable receive and transmit.
130 * Set local loopback mode.
132 sp->smc_smcmr = smcr_mk_clen (9) | SMCMR_SM_UART | (ushort) 0x0004;
134 /* Mask all interrupts and remove anything pending.
139 /* Set up the baud rate generator.
141 cp->cp_simode = 0x00000000;
144 (((gd->cpu_clk / 16 / gd->baudrate) -
145 1) << 1) | CPM_BRG_EN;
147 /* Make the first buffer the only buffer.
149 tbdf->cbd_sc |= BD_SC_WRAP;
150 rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
152 /* Single character receive.
157 /* Initialize Tx/Rx parameters.
160 while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
164 mk_cr_cmd (cpm_cr_ch[smc_index], CPM_CR_INIT_TRX) | CPM_CR_FLG;
166 while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
169 /* Enable transmitter/receiver.
171 sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN;
174 static void smc_halt(int smc_index)
178 static void smc_putc (int smc_index, const char c)
180 volatile cbd_t *tbdf;
182 volatile smc_uart_t *up;
183 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
184 volatile cpm8xx_t *cpmp = &(im->im_cpm);
186 up = (smc_uart_t *) & cpmp->cp_dparam[proff_smc[smc_index]];
188 tbdf = (cbd_t *) & cpmp->cp_dpmem[up->smc_tbase];
190 /* Wait for last character to go.
193 buf = (char *) tbdf->cbd_bufaddr;
196 while (tbdf->cbd_sc & BD_SC_READY)
201 tbdf->cbd_datlen = 1;
202 tbdf->cbd_sc |= BD_SC_READY;
205 while (tbdf->cbd_sc & BD_SC_READY)
210 static int smc_getc (int smc_index)
212 volatile cbd_t *rbdf;
213 volatile unsigned char *buf;
214 volatile smc_uart_t *up;
215 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
216 volatile cpm8xx_t *cpmp = &(im->im_cpm);
220 up = (smc_uart_t *) & cpmp->cp_dparam[proff_smc[smc_index]];
222 rbdf = (cbd_t *) & cpmp->cp_dpmem[up->smc_rbase];
224 /* Wait for character to show up.
226 buf = (unsigned char *) rbdf->cbd_bufaddr;
228 while (rbdf->cbd_sc & BD_SC_EMPTY);
230 for (i = 100; i > 0; i--) {
231 if (!(rbdf->cbd_sc & BD_SC_EMPTY))
240 rbdf->cbd_sc |= BD_SC_EMPTY;
249 static void scc_init (int scc_index)
251 static int cpm_cr_ch[] = {
258 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
260 volatile scc_uart_t *up;
261 volatile cbd_t *tbdf, *rbdf;
262 volatile cpm8xx_t *cp = &(im->im_cpm);
265 /* initialize pointers to SCC */
267 sp = (scc_t *) & (cp->cp_scc[scc_index]);
268 up = (scc_uart_t *) & cp->cp_dparam[proff_scc[scc_index]];
270 /* Disable transmitter/receiver.
272 sp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
274 dpaddr = CPM_POST_BASE;
278 im->im_siu_conf.sc_sdcr = 0x0001;
280 /* Set the physical address of the host memory buffers in
281 * the buffer descriptors.
284 rbdf = (cbd_t *) & cp->cp_dpmem[dpaddr];
285 rbdf->cbd_bufaddr = (uint) (rbdf + 2);
288 tbdf->cbd_bufaddr = ((uint) (rbdf + 2)) + 1;
291 /* Set up the baud rate generator.
293 cp->cp_sicr &= ~(0x000000FF << (8 * scc_index));
294 /* no |= needed, since BRG1 is 000 */
297 (((gd->cpu_clk / 16 / gd->baudrate) -
298 1) << 1) | CPM_BRG_EN;
300 /* Set up the uart parameters in the parameter ram.
302 up->scc_genscc.scc_rbase = dpaddr;
303 up->scc_genscc.scc_tbase = dpaddr + sizeof (cbd_t);
305 /* Initialize Tx/Rx parameters.
307 while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
310 mk_cr_cmd (cpm_cr_ch[scc_index], CPM_CR_INIT_TRX) | CPM_CR_FLG;
312 while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
315 up->scc_genscc.scc_rfcr = SCC_EB | 0x05;
316 up->scc_genscc.scc_tfcr = SCC_EB | 0x05;
318 up->scc_genscc.scc_mrblr = 1; /* Single character receive */
319 up->scc_maxidl = 0; /* disable max idle */
320 up->scc_brkcr = 1; /* send one break character on stop TX */
328 up->scc_char1 = 0x8000;
329 up->scc_char2 = 0x8000;
330 up->scc_char3 = 0x8000;
331 up->scc_char4 = 0x8000;
332 up->scc_char5 = 0x8000;
333 up->scc_char6 = 0x8000;
334 up->scc_char7 = 0x8000;
335 up->scc_char8 = 0x8000;
336 up->scc_rccm = 0xc0ff;
338 /* Set low latency / small fifo.
340 sp->scc_gsmrh = SCC_GSMRH_RFW;
344 sp->scc_gsmrl &= ~0xF;
345 sp->scc_gsmrl |= SCC_GSMRL_MODE_UART;
347 /* Set local loopback mode.
349 sp->scc_gsmrl &= ~SCC_GSMRL_DIAG_LE;
350 sp->scc_gsmrl |= SCC_GSMRL_DIAG_LOOP;
352 /* Set clock divider 16 on Tx and Rx
354 sp->scc_gsmrl |= (SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16);
356 sp->scc_psmr |= SCU_PSMR_CL;
358 /* Mask all interrupts and remove anything pending.
361 sp->scc_scce = 0xffff;
362 sp->scc_dsr = 0x7e7e;
363 sp->scc_psmr = 0x3000;
365 /* Make the first buffer the only buffer.
367 tbdf->cbd_sc |= BD_SC_WRAP;
368 rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
370 /* Enable transmitter/receiver.
372 sp->scc_gsmrl |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT);
375 static void scc_halt(int scc_index)
377 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
378 volatile cpm8xx_t *cp = &(im->im_cpm);
379 volatile scc_t *sp = (scc_t *) & (cp->cp_scc[scc_index]);
381 sp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT | SCC_GSMRL_DIAG_LE);
384 static void scc_putc (int scc_index, const char c)
386 volatile cbd_t *tbdf;
388 volatile scc_uart_t *up;
389 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
390 volatile cpm8xx_t *cpmp = &(im->im_cpm);
392 up = (scc_uart_t *) & cpmp->cp_dparam[proff_scc[scc_index]];
394 tbdf = (cbd_t *) & cpmp->cp_dpmem[up->scc_genscc.scc_tbase];
396 /* Wait for last character to go.
399 buf = (char *) tbdf->cbd_bufaddr;
402 while (tbdf->cbd_sc & BD_SC_READY)
407 tbdf->cbd_datlen = 1;
408 tbdf->cbd_sc |= BD_SC_READY;
411 while (tbdf->cbd_sc & BD_SC_READY)
416 static int scc_getc (int scc_index)
418 volatile cbd_t *rbdf;
419 volatile unsigned char *buf;
420 volatile scc_uart_t *up;
421 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
422 volatile cpm8xx_t *cpmp = &(im->im_cpm);
426 up = (scc_uart_t *) & cpmp->cp_dparam[proff_scc[scc_index]];
428 rbdf = (cbd_t *) & cpmp->cp_dpmem[up->scc_genscc.scc_rbase];
430 /* Wait for character to show up.
432 buf = (unsigned char *) rbdf->cbd_bufaddr;
434 while (rbdf->cbd_sc & BD_SC_EMPTY);
436 for (i = 100; i > 0; i--) {
437 if (!(rbdf->cbd_sc & BD_SC_EMPTY))
446 rbdf->cbd_sc |= BD_SC_EMPTY;
455 static int test_ctlr (int ctlr, int index)
458 char test_str[] = "*** UART Test String ***\r\n";
461 ctlr_proc[ctlr].init (index);
463 for (i = 0; i < sizeof (test_str) - 1; i++) {
464 ctlr_proc[ctlr].putc (index, test_str[i]);
465 if (ctlr_proc[ctlr].getc (index) != test_str[i])
472 ctlr_proc[ctlr].halt (index);
475 post_log ("uart %s%d test failed\n",
476 ctlr_name[ctlr], index + 1);
482 int uart_post_test (int flags)
487 ctlr_proc[CTLR_SMC].init = smc_init;
488 ctlr_proc[CTLR_SMC].halt = smc_halt;
489 ctlr_proc[CTLR_SMC].putc = smc_putc;
490 ctlr_proc[CTLR_SMC].getc = smc_getc;
492 ctlr_proc[CTLR_SCC].init = scc_init;
493 ctlr_proc[CTLR_SCC].halt = scc_halt;
494 ctlr_proc[CTLR_SCC].putc = scc_putc;
495 ctlr_proc[CTLR_SCC].getc = scc_getc;
497 for (i = 0; i < ARRAY_SIZE(ctlr_list); i++) {
498 if (test_ctlr (ctlr_list[i][0], ctlr_list[i][1]) != 0) {
503 #if !defined(CONFIG_8xx_CONS_NONE)
504 serial_reinit_all ();
510 #endif /* CONFIG_POST & CONFIG_SYS_POST_UART */