post/cpu/mpc8xx/spr.c

   1 /*
   2  * (C) Copyright 2002
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9
  10 /*
  11  * SPR test
  12  *
  13  * The test checks the contents of Special Purpose Registers (SPR) listed
  14  * in the spr_test_list array below.
  15  * Each SPR value is read using mfspr instruction, some bits are masked
  16  * according to the table and the resulting value is compared to the
  17  * corresponding table value.
  18  */
  19
  20 #include <post.h>
  21
  22 #if CONFIG_POST & CONFIG_SYS_POST_SPR
  23
  24 static struct
  25 {
  26     int number;
  27     char * name;
  28     unsigned long mask;
  29     unsigned long value;
  30 } spr_test_list [] = {
  31         /* Standard Special-Purpose Registers */
  32
  33         {1,     "XER",          0x00000000,     0x00000000},
  34         {8,     "LR",           0x00000000,     0x00000000},
  35         {9,     "CTR",          0x00000000,     0x00000000},
  36         {18,    "DSISR",        0x00000000,     0x00000000},
  37         {19,    "DAR",          0x00000000,     0x00000000},
  38         {22,    "DEC",          0x00000000,     0x00000000},
  39         {26,    "SRR0",         0x00000000,     0x00000000},
  40         {27,    "SRR1",         0x00000000,     0x00000000},
  41         {272,   "SPRG0",        0x00000000,     0x00000000},
  42         {273,   "SPRG1",        0x00000000,     0x00000000},
  43         {274,   "SPRG2",        0x00000000,     0x00000000},
  44         {275,   "SPRG3",        0x00000000,     0x00000000},
  45         {287,   "PVR",          0xFFFF0000,     0x00500000},
  46
  47         /* Additional Special-Purpose Registers */
  48
  49         {144,   "CMPA",         0x00000000,     0x00000000},
  50         {145,   "CMPB",         0x00000000,     0x00000000},
  51         {146,   "CMPC",         0x00000000,     0x00000000},
  52         {147,   "CMPD",         0x00000000,     0x00000000},
  53         {148,   "ICR",          0xFFFFFFFF,     0x00000000},
  54         {149,   "DER",          0x00000000,     0x00000000},
  55         {150,   "COUNTA",       0xFFFFFFFF,     0x00000000},
  56         {151,   "COUNTB",       0xFFFFFFFF,     0x00000000},
  57         {152,   "CMPE",         0x00000000,     0x00000000},
  58         {153,   "CMPF",         0x00000000,     0x00000000},
  59         {154,   "CMPG",         0x00000000,     0x00000000},
  60         {155,   "CMPH",         0x00000000,     0x00000000},
  61         {156,   "LCTRL1",       0xFFFFFFFF,     0x00000000},
  62         {157,   "LCTRL2",       0xFFFFFFFF,     0x00000000},
  63         {158,   "ICTRL",        0xFFFFFFFF,     0x00000007},
  64         {159,   "BAR",          0x00000000,     0x00000000},
  65         {630,   "DPDR",         0x00000000,     0x00000000},
  66         {631,   "DPIR",         0x00000000,     0x00000000},
  67         {638,   "IMMR",         0xFFFF0000,     CONFIG_SYS_IMMR  },
  68         {560,   "IC_CST",       0x8E380000,     0x00000000},
  69         {561,   "IC_ADR",       0x00000000,     0x00000000},
  70         {562,   "IC_DAT",       0x00000000,     0x00000000},
  71         {568,   "DC_CST",       0xEF380000,     0x00000000},
  72         {569,   "DC_ADR",       0x00000000,     0x00000000},
  73         {570,   "DC_DAT",       0x00000000,     0x00000000},
  74         {784,   "MI_CTR",       0xFFFFFFFF,     0x00000000},
  75         {786,   "MI_AP",        0x00000000,     0x00000000},
  76         {787,   "MI_EPN",       0x00000000,     0x00000000},
  77         {789,   "MI_TWC",       0xFFFFFE02,     0x00000000},
  78         {790,   "MI_RPN",       0x00000000,     0x00000000},
  79         {816,   "MI_DBCAM",     0x00000000,     0x00000000},
  80         {817,   "MI_DBRAM0",    0x00000000,     0x00000000},
  81         {818,   "MI_DBRAM1",    0x00000000,     0x00000000},
  82         {792,   "MD_CTR",       0xFFFFFFFF,     0x04000000},
  83         {793,   "M_CASID",      0xFFFFFFF0,     0x00000000},
  84         {794,   "MD_AP",        0x00000000,     0x00000000},
  85         {795,   "MD_EPN",       0x00000000,     0x00000000},
  86         {796,   "M_TWB",        0x00000003,     0x00000000},
  87         {797,   "MD_TWC",       0x00000003,     0x00000000},
  88         {798,   "MD_RPN",       0x00000000,     0x00000000},
  89         {799,   "M_TW",         0x00000000,     0x00000000},
  90         {824,   "MD_DBCAM",     0x00000000,     0x00000000},
  91         {825,   "MD_DBRAM0",    0x00000000,     0x00000000},
  92         {826,   "MD_DBRAM1",    0x00000000,     0x00000000},
  93 };
  94
  95 static int spr_test_list_size = ARRAY_SIZE(spr_test_list);
  96
  97 int spr_post_test (int flags)
  98 {
  99         int ret = 0;
 100         int ic = icache_status ();
 101         int i;
 102
 103         unsigned long code[] = {
 104                 0x7c6002a6,                             /* mfspr r3,SPR */
 105                 0x4e800020                              /* blr          */
 106         };
 107         unsigned long (*get_spr) (void) = (void *) code;
 108
 109         if (ic)
 110                 icache_disable ();
 111
 112         for (i = 0; i < spr_test_list_size; i++) {
 113                 int num = spr_test_list[i].number;
 114
 115                 /* mfspr r3,num */
 116                 code[0] = 0x7c6002a6 | ((num & 0x1F) << 16) | ((num & 0x3E0) << 6);
 117
 118                 if ((get_spr () & spr_test_list[i].mask) !=
 119                         (spr_test_list[i].value & spr_test_list[i].mask)) {
 120                         post_log ("The value of %s special register "
 121                                   "is incorrect: 0x%08X\n",
 122                                         spr_test_list[i].name, get_spr ());
 123                         ret = -1;
 124                 }
 125         }
 126
 127         if (ic)
 128                 icache_enable ();
 129
 130         return ret;
 131 }
 132 #endif /* CONFIG_POST & CONFIG_SYS_POST_SPR */