include/dt-bindings/clock/mt7628-clk.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Copyright (C) 2019 MediaTek Inc.
   4  *
   5  * Author:  Weijie Gao <weijie.gao@mediatek.com>
   6  */
   7
   8 #ifndef _DT_BINDINGS_MT7628_CLK_H_
   9 #define _DT_BINDINGS_MT7628_CLK_H_
  10
  11 /* Base clocks */
  12 #define CLK_SYS                         34
  13 #define CLK_CPU                         33
  14 #define CLK_XTAL                        32
  15
  16 /* Peripheral clocks */
  17 #define CLK_PWM                         31
  18 #define CLK_SDXC                        30
  19 #define CLK_CRYPTO                      29
  20 #define CLK_MIPS_CNT                    28
  21 #define CLK_PCIE                        26
  22 #define CLK_UPHY                        25
  23 #define CLK_ETH                         23
  24 #define CLK_UART2                       20
  25 #define CLK_UART1                       19
  26 #define CLK_SPI                         18
  27 #define CLK_I2S                         17
  28 #define CLK_I2C                         16
  29 #define CLK_GDMA                        14
  30 #define CLK_PIO                         13
  31 #define CLK_UART0                       12
  32 #define CLK_PCM                         11
  33 #define CLK_MC                          10
  34 #define CLK_INTC                        9
  35 #define CLK_TIMER                       8
  36
  37 #endif /* _DT_BINDINGS_MT7628_CLK_H_ */