include/configs/x600.h

   1 /*
   2  * (C) Copyright 2009
   3  * Vipin Kumar, STMicroelectronics, <vipin.kumar@st.com>
   4  *
   5  * Copyright (C) 2012, 2015 Stefan Roese <sr@denx.de>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #ifndef __CONFIG_H
  11 #define __CONFIG_H
  12
  13 /*
  14  * High Level Configuration Options
  15  * (easy to change)
  16  */
  17 #define CONFIG_SPEAR600                         /* SPEAr600 SoC */
  18 #define CONFIG_X600                             /* on X600 board */
  19
  20 #include <asm/arch/hardware.h>
  21
  22 /* Timer, HZ specific defines */
  23 #define CONFIG_SYS_HZ_CLOCK                     8300000
  24
  25 #define CONFIG_SYS_TEXT_BASE                    0x00800040
  26 #define CONFIG_SYS_FLASH_BASE                   0xf8000000
  27 /* Reserve 8KiB for SPL */
  28 #define CONFIG_SPL_PAD_TO                       8192    /* decimal for 'dd' */
  29 #define CONFIG_SYS_SPL_LEN                      CONFIG_SPL_PAD_TO
  30 #define CONFIG_SYS_UBOOT_BASE                   (CONFIG_SYS_FLASH_BASE + \
  31                                                  CONFIG_SYS_SPL_LEN)
  32 #define CONFIG_SYS_UBOOT_START                  CONFIG_SYS_TEXT_BASE
  33 #define CONFIG_SYS_MONITOR_BASE                 CONFIG_SYS_FLASH_BASE
  34 #define CONFIG_SYS_MONITOR_LEN                  0x60000
  35
  36 #define CONFIG_ENV_IS_IN_FLASH
  37
  38 /* Serial Configuration (PL011) */
  39 #define CONFIG_SYS_SERIAL0                      0xD0000000
  40 #define CONFIG_SYS_SERIAL1                      0xD0080000
  41 #define CONFIG_PL01x_PORTS                      { (void *)CONFIG_SYS_SERIAL0, \
  42                                                 (void *)CONFIG_SYS_SERIAL1 }
  43 #define CONFIG_PL011_SERIAL
  44 #define CONFIG_PL011_CLOCK                      (48 * 1000 * 1000)
  45 #define CONFIG_CONS_INDEX                       0
  46 #define CONFIG_BAUDRATE                         115200
  47 #define CONFIG_SYS_BAUDRATE_TABLE               { 9600, 19200, 38400, \
  48                                                   57600, 115200 }
  49 #define CONFIG_SYS_LOADS_BAUD_CHANGE
  50
  51 /* NOR FLASH config options */
  52 #define CONFIG_ST_SMI
  53 #define CONFIG_SYS_MAX_FLASH_BANKS              1
  54 #define CONFIG_SYS_FLASH_BANK_SIZE              0x01000000
  55 #define CONFIG_SYS_FLASH_ADDR_BASE              { CONFIG_SYS_FLASH_BASE }
  56 #define CONFIG_SYS_MAX_FLASH_SECT               128
  57 #define CONFIG_SYS_FLASH_EMPTY_INFO
  58 #define CONFIG_SYS_FLASH_ERASE_TOUT             (3 * CONFIG_SYS_HZ)
  59 #define CONFIG_SYS_FLASH_WRITE_TOUT             (3 * CONFIG_SYS_HZ)
  60
  61 /* NAND FLASH config options */
  62 #define CONFIG_NAND_FSMC
  63 #define CONFIG_SYS_NAND_SELF_INIT
  64 #define CONFIG_SYS_MAX_NAND_DEVICE              1
  65 #define CONFIG_SYS_NAND_BASE                    CONFIG_FSMC_NAND_BASE
  66 #define CONFIG_MTD_ECC_SOFT
  67 #define CONFIG_SYS_FSMC_NAND_8BIT
  68 #define CONFIG_SYS_NAND_ONFI_DETECTION
  69 #define CONFIG_NAND_ECC_BCH
  70 #define CONFIG_BCH
  71
  72 /* UBI/UBI config options */
  73 #define CONFIG_MTD_DEVICE
  74 #define CONFIG_MTD_PARTITIONS
  75 #define CONFIG_RBTREE
  76
  77 /* Ethernet config options */
  78 #define CONFIG_MII
  79 #define CONFIG_PHY_RESET_DELAY                  10000           /* in usec */
  80 #define CONFIG_PHY_ADDR         0       /* PHY address */
  81 #define CONFIG_PHY_GIGE                 /* Include GbE speed/duplex detection */
  82 #define CONFIG_PHY_MICREL
  83 #define CONFIG_PHY_MICREL_KSZ9031
  84
  85 #define CONFIG_SPEAR_GPIO
  86
  87 /* I2C config options */
  88 #define CONFIG_SYS_I2C
  89 #define CONFIG_SYS_I2C_BASE                     0xD0200000
  90 #define CONFIG_SYS_I2C_SPEED                    400000
  91 #define CONFIG_SYS_I2C_SLAVE                    0x02
  92 #define CONFIG_I2C_CHIPADDRESS                  0x50
  93
  94 #define CONFIG_RTC_M41T62       1
  95 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
  96
  97 /* FPGA config options */
  98 #define CONFIG_FPGA
  99 #define CONFIG_FPGA_XILINX
 100 #define CONFIG_FPGA_SPARTAN3
 101 #define CONFIG_FPGA_COUNT       1
 102
 103 /* USB EHCI options */
 104 #define CONFIG_USB_EHCI
 105 #define CONFIG_USB_EHCI_SPEAR
 106 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
 107
 108 /*
 109  * Command support defines
 110  */
 111 #define CONFIG_CMD_DATE
 112 #define CONFIG_CMD_ENV
 113 #define CONFIG_CMD_FPGA_LOADMK
 114 #define CONFIG_CMD_MTDPARTS
 115 #define CONFIG_CMD_NAND
 116 #define CONFIG_CMD_SAVES
 117 #define CONFIG_CMD_UBIFS
 118 #define CONFIG_LZO
 119
 120 /* Filesystem support (for USB key) */
 121 #define CONFIG_SUPPORT_VFAT
 122
 123
 124 /*
 125  * U-Boot Environment placing definitions.
 126  */
 127 #define CONFIG_ENV_SECT_SIZE                    0x00010000
 128 #define CONFIG_ENV_ADDR                         (CONFIG_SYS_MONITOR_BASE + \
 129                                                  CONFIG_SYS_MONITOR_LEN)
 130 #define CONFIG_ENV_SIZE                         0x02000
 131 #define CONFIG_ENV_ADDR_REDUND                  (CONFIG_ENV_ADDR + \
 132                                                  CONFIG_ENV_SECT_SIZE)
 133 #define CONFIG_ENV_SIZE_REDUND                  (CONFIG_ENV_SIZE)
 134
 135 /* Miscellaneous configurable options */
 136 #define CONFIG_ARCH_CPU_INIT
 137 #define CONFIG_BOOT_PARAMS_ADDR                 0x00000100
 138 #define CONFIG_CMDLINE_TAG
 139 #define CONFIG_SETUP_MEMORY_TAGS
 140 #define CONFIG_MISC_INIT_R
 141 #define CONFIG_MX_CYCLIC                /* enable mdc/mwc commands      */
 142
 143 #define CONFIG_SYS_MEMTEST_START                0x00800000
 144 #define CONFIG_SYS_MEMTEST_END                  0x04000000
 145 #define CONFIG_SYS_MALLOC_LEN                   (8 << 20)
 146 #define CONFIG_SYS_LONGHELP
 147 #define CONFIG_CMDLINE_EDITING
 148 #define CONFIG_AUTO_COMPLETE
 149 #define CONFIG_SYS_CBSIZE                       256
 150 #define CONFIG_SYS_PBSIZE                       (CONFIG_SYS_CBSIZE + \
 151                                                  sizeof(CONFIG_SYS_PROMPT) + 16)
 152 #define CONFIG_SYS_MAXARGS                      16
 153 #define CONFIG_SYS_BARGSIZE                     CONFIG_SYS_CBSIZE
 154 #define CONFIG_SYS_LOAD_ADDR                    0x00800000
 155
 156 /* Use last 2 lwords in internal SRAM for bootcounter */
 157 #define CONFIG_BOOTCOUNT_LIMIT
 158 #define CONFIG_SYS_BOOTCOUNT_ADDR               (CONFIG_SRAM_BASE + \
 159                                                  CONFIG_SRAM_SIZE)
 160
 161 #define CONFIG_HOSTNAME                         x600
 162 #define CONFIG_UBI_PART                         ubi0
 163 #define CONFIG_UBIFS_VOLUME                     rootfs
 164
 165 #define MTDIDS_DEFAULT          "nand0=nand"
 166 #define MTDPARTS_DEFAULT        "mtdparts=nand:64M(ubi0),64M(ubi1)"
 167
 168 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 169         "u-boot_addr=1000000\0"                                         \
 170         "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.spr\0"          \
 171         "load=tftp ${u-boot_addr} ${u-boot}\0"                          \
 172         "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE)      \
 173                 " +${filesize};"                                        \
 174                 "erase " __stringify(CONFIG_SYS_MONITOR_BASE) " +${filesize};" \
 175                 "cp.b ${u-boot_addr} " __stringify(CONFIG_SYS_MONITOR_BASE) \
 176                 " ${filesize};"                                         \
 177                 "protect on " __stringify(CONFIG_SYS_MONITOR_BASE)      \
 178                 " +${filesize}\0"                                       \
 179         "upd=run load update\0"                                         \
 180         "ubifs=" __stringify(CONFIG_HOSTNAME) "/ubifs.img\0"            \
 181         "part=" __stringify(CONFIG_UBI_PART) "\0"                       \
 182         "vol=" __stringify(CONFIG_UBIFS_VOLUME) "\0"                    \
 183         "load_ubifs=tftp ${kernel_addr} ${ubifs}\0"                     \
 184         "update_ubifs=ubi part ${part};ubi write ${kernel_addr} ${vol}" \
 185                 " ${filesize}\0"                                        \
 186         "upd_ubifs=run load_ubifs update_ubifs\0"                       \
 187         "init_ubifs=nand erase.part ubi0;ubi part ${part};"             \
 188                 "ubi create ${vol} 4000000\0"                           \
 189         "netdev=eth0\0"                                                 \
 190         "rootpath=/opt/eldk-4.2/arm\0"                                  \
 191         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 192                 "nfsroot=${serverip}:${rootpath}\0"                     \
 193         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 194         "boot_part=0\0"                                                 \
 195         "altbootcmd=if test $boot_part -eq 0;then "                     \
 196                         "echo Switching to partition 1!;"               \
 197                         "setenv boot_part 1;"                           \
 198                 "else; "                                                \
 199                         "echo Switching to partition 0!;"               \
 200                         "setenv boot_part 0;"                           \
 201                 "fi;"                                                   \
 202                 "saveenv;boot\0"                                        \
 203         "ubifsargs=set bootargs ubi.mtd=ubi${boot_part} "               \
 204                 "root=ubi0:rootfs rootfstype=ubifs\0"                   \
 205         "kernel=" __stringify(CONFIG_HOSTNAME) "/uImage\0"              \
 206         "kernel_fs=/boot/uImage \0"                                     \
 207         "kernel_addr=1000000\0"                                         \
 208         "dtb=" __stringify(CONFIG_HOSTNAME) "/"                         \
 209                 __stringify(CONFIG_HOSTNAME) ".dtb\0"                   \
 210         "dtb_fs=/boot/" __stringify(CONFIG_HOSTNAME) ".dtb\0"           \
 211         "dtb_addr=1800000\0"                                            \
 212         "load_kernel=tftp ${kernel_addr} ${kernel}\0"                   \
 213         "load_dtb=tftp ${dtb_addr} ${dtb}\0"                            \
 214         "addip=setenv bootargs ${bootargs} "                            \
 215                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 216                 ":${hostname}:${netdev}:off panic=1\0"                  \
 217         "addcon=setenv bootargs ${bootargs} console=ttyAMA0,"           \
 218                 "${baudrate}\0"                                         \
 219         "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"              \
 220         "net_nfs=run load_dtb load_kernel; "                            \
 221                 "run nfsargs addip addcon addmtd addmisc;"              \
 222                 "bootm ${kernel_addr} - ${dtb_addr}\0"                  \
 223         "mtdids=" MTDIDS_DEFAULT "\0"                                   \
 224         "mtdparts=" MTDPARTS_DEFAULT "\0"                               \
 225         "nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip"         \
 226                 " addcon addmisc addmtd;"                               \
 227                 "bootm ${kernel_addr} - ${dtb_addr}\0"                  \
 228         "ubifs_mount=ubi part ubi${boot_part};ubifsmount ubi:rootfs\0"  \
 229         "ubifs_load=ubifsload ${kernel_addr} ${kernel_fs};"             \
 230                 "ubifsload ${dtb_addr} ${dtb_fs};\0"                    \
 231         "nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip addcon " \
 232                 "addmtd addmisc;bootm ${kernel_addr} - ${dtb_addr}\0"   \
 233         "bootcmd=run nand_ubifs\0"                                      \
 234         "\0"
 235
 236 /* Physical Memory Map */
 237 #define CONFIG_NR_DRAM_BANKS                    1
 238 #define PHYS_SDRAM_1                            0x00000000
 239 #define PHYS_SDRAM_1_MAXSIZE                    0x40000000
 240
 241 #define CONFIG_SYS_SDRAM_BASE                   PHYS_SDRAM_1
 242 #define CONFIG_SRAM_BASE                        0xd2800000
 243 /* Preserve the last 2 lwords for the boot-counter */
 244 #define CONFIG_SRAM_SIZE                        ((8 << 10) - 0x8)
 245 #define CONFIG_SYS_INIT_RAM_ADDR                CONFIG_SRAM_BASE
 246 #define CONFIG_SYS_INIT_RAM_SIZE                CONFIG_SRAM_SIZE
 247
 248 #define CONFIG_SYS_INIT_SP_OFFSET               \
 249         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 250
 251 #define CONFIG_SYS_INIT_SP_ADDR                 \
 252         (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
 253
 254 /*
 255  * SPL related defines
 256  */
 257 #define CONFIG_SPL_TEXT_BASE            0xd2800b00
 258 #define CONFIG_SPL_MAX_SIZE             (CONFIG_SRAM_SIZE - 0xb00)
 259 #define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/spear"
 260 #define CONFIG_SPL_LDSCRIPT     "arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds"
 261
 262 #define CONFIG_SPL_FRAMEWORK
 263
 264 /*
 265  * Please select/define only one of the following
 266  * Each definition corresponds to a supported DDR chip.
 267  * DDR configuration is based on the following selection
 268  */
 269 #define CONFIG_DDR_MT47H64M16           1
 270 #define CONFIG_DDR_MT47H32M16           0
 271 #define CONFIG_DDR_MT47H128M8           0
 272
 273 /*
 274  * Synchronous/Asynchronous operation of DDR
 275  *
 276  * Select CONFIG_DDR_2HCLK for DDR clk = 333MHz, synchronous operation
 277  * Select CONFIG_DDR_HCLK for DDR clk = 166MHz, synchronous operation
 278  * Select CONFIG_DDR_PLL2 for DDR clk = PLL2, asynchronous operation
 279  */
 280 #define CONFIG_DDR_2HCLK                1
 281 #define CONFIG_DDR_HCLK                 0
 282 #define CONFIG_DDR_PLL2                 0
 283
 284 /*
 285  * xxx_BOOT_SUPPORTED macro defines whether a booting type is supported
 286  * or not. Modify/Add to only these macros to define new boot types
 287  */
 288 #define USB_BOOT_SUPPORTED              0
 289 #define PCIE_BOOT_SUPPORTED             0
 290 #define SNOR_BOOT_SUPPORTED             1
 291 #define NAND_BOOT_SUPPORTED             1
 292 #define PNOR_BOOT_SUPPORTED             0
 293 #define TFTP_BOOT_SUPPORTED             0
 294 #define UART_BOOT_SUPPORTED             0
 295 #define SPI_BOOT_SUPPORTED              0
 296 #define I2C_BOOT_SUPPORTED              0
 297 #define MMC_BOOT_SUPPORTED              0
 298
 299 #endif  /* __CONFIG_H */