include/configs/ts4800.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2015, Savoir-faire Linux Inc.
   4  *
   5  * Derived from MX51EVK code by
   6  *   Guennadi Liakhovetski <lg@denx.de>
   7  *   Freescale Semiconductor, Inc.
   8  *
   9  * Configuration settings for the TS4800 Board
  10  */
  11
  12 #ifndef __CONFIG_H
  13 #define __CONFIG_H
  14
  15 /* High Level Configuration Options */
  16
  17 #define CONFIG_SKIP_LOWLEVEL_INIT       /* U-Boot is a 2nd stage bootloader */
  18
  19 #define CONFIG_HW_WATCHDOG
  20
  21 #define CONFIG_MACH_TYPE        MACH_TYPE_TS48XX
  22
  23 /* text base address used when linking */
  24
  25 #include <asm/arch/imx-regs.h>
  26
  27 /* enable passing of ATAGs */
  28 #define CONFIG_CMDLINE_TAG
  29 #define CONFIG_SETUP_MEMORY_TAGS
  30 #define CONFIG_INITRD_TAG
  31 #define CONFIG_REVISION_TAG
  32
  33 /*
  34  * Size of malloc() pool
  35  */
  36 #define CONFIG_SYS_MALLOC_LEN           (10 * 1024 * 1024)
  37
  38 /*
  39  * Hardware drivers
  40  */
  41
  42 #define CONFIG_MXC_UART
  43 #define CONFIG_MXC_UART_BASE    UART1_BASE
  44
  45 /*
  46  * MMC Configs
  47  * */
  48 #define CONFIG_SYS_FSL_ESDHC_ADDR       MMC_SDHC1_BASE_ADDR
  49
  50 /*
  51  * Eth Configs
  52  */
  53
  54 #define CONFIG_FEC_MXC
  55 #define IMX_FEC_BASE            FEC_BASE_ADDR
  56 #define CONFIG_ETHPRIME         "FEC"
  57 #define CONFIG_FEC_MXC_PHYADDR  0
  58
  59 /* allow to overwrite serial and ethaddr */
  60 #define CONFIG_ENV_OVERWRITE            /* disable vendor parameters protection (serial#, ethaddr) */
  61
  62 /***********************************************************
  63  * Command definition
  64  ***********************************************************/
  65
  66 /* Environment variables */
  67
  68
  69 #define CONFIG_LOADADDR         0x91000000      /* loadaddr env var */
  70
  71 #define CONFIG_EXTRA_ENV_SETTINGS \
  72         "script=boot.scr\0" \
  73         "image=zImage\0" \
  74         "fdt_file=imx51-ts4800.dtb\0" \
  75         "fdt_addr=0x90fe0000\0" \
  76         "mmcdev=0\0" \
  77         "mmcpart=2\0" \
  78         "mmcroot=/dev/mmcblk0p3 rootwait rw\0" \
  79         "mmcargs=setenv bootargs root=${mmcroot}\0" \
  80         "addtty=setenv bootargs ${bootargs} console=ttymxc0,${baudrate}\0" \
  81         "loadbootscript=" \
  82                 "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
  83         "bootscript=echo Running bootscript from mmc ...; " \
  84                 "source\0" \
  85         "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image};\0" \
  86         "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
  87         "mmcboot=echo Booting from mmc ...; " \
  88                 "run mmcargs addtty; " \
  89                 "if run loadfdt; then " \
  90                         "bootz ${loadaddr} - ${fdt_addr}; " \
  91                 "else " \
  92                         "echo ERR: cannot load FDT; " \
  93                 "fi; "
  94
  95
  96 #define CONFIG_BOOTCOMMAND \
  97         "mmc dev ${mmcdev}; if mmc rescan; then " \
  98                 "if run loadbootscript; then " \
  99                         "run bootscript; " \
 100                 "else " \
 101                         "if run loadimage; then " \
 102                                 "run mmcboot; " \
 103                         "fi; " \
 104                 "fi; " \
 105         "fi; "
 106
 107 /*
 108  * Miscellaneous configurable options
 109  */
 110
 111 #define CONFIG_SYS_LOAD_ADDR            CONFIG_LOADADDR
 112
 113 /*-----------------------------------------------------------------------
 114  * Physical Memory Map
 115  */
 116 #define PHYS_SDRAM_1            CSD0_BASE_ADDR
 117 #define PHYS_SDRAM_1_SIZE       (256 * 1024 * 1024)
 118
 119 #define CONFIG_SYS_SDRAM_BASE           (PHYS_SDRAM_1)
 120 #define CONFIG_SYS_INIT_RAM_ADDR        (IRAM_BASE_ADDR)
 121 #define CONFIG_SYS_INIT_RAM_SIZE        (IRAM_SIZE)
 122
 123 #define CONFIG_SYS_INIT_SP_OFFSET \
 124         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 125 #define CONFIG_SYS_INIT_SP_ADDR \
 126         (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
 127
 128 /* Low level init */
 129 #define CONFIG_SYS_DDR_CLKSEL   0
 130 #define CONFIG_SYS_CLKTL_CBCDR  0x59E35100
 131 #define CONFIG_SYS_MAIN_PWR_ON
 132
 133 /*-----------------------------------------------------------------------
 134  * Environment organization
 135  */
 136
 137 #define CONFIG_SYS_MMC_ENV_DEV 0
 138
 139 #endif