1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2012 Altera Corporation <www.altera.com>
5 #ifndef __CONFIG_SOCFPGA_COMMON_H__
6 #define __CONFIG_SOCFPGA_COMMON_H__
9 * High level configuration
13 #define CONFIG_SYS_BOOTMAPSZ (64 * 1024 * 1024)
15 #define CONFIG_TIMESTAMP /* Print image info with timestamp */
17 /* add target to build it automatically upon "make" */
18 #define CONFIG_BUILD_TARGET "u-boot-with-spl.sfp"
21 * Memory configurations
23 #define PHYS_SDRAM_1 0x0
24 #define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024)
25 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1
26 #define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE
27 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
28 #define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000
29 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000
30 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
31 #define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000
32 #define CONFIG_SYS_INIT_RAM_SIZE 0x40000 /* 256KB */
34 #define CONFIG_SYS_INIT_SP_ADDR \
35 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)
37 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
40 * U-Boot general configurations
42 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */
43 /* Print buffer size */
44 #define CONFIG_SYS_MAXARGS 32 /* Max number of command args */
45 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
46 /* Boot argument buffer size */
48 #ifndef CONFIG_SYS_HOSTNAME
49 #define CONFIG_SYS_HOSTNAME CONFIG_SYS_BOARD
55 #define CONFIG_SYS_L2_PL310
56 #define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS
59 * EPCS/EPCQx1 Serial Flash Controller
61 #ifdef CONFIG_ALTERA_SPI
62 #define CONFIG_SF_DEFAULT_SPEED 30000000
64 * The base address is configurable in QSys, each board must specify the
65 * base address based on it's particular FPGA configuration. Please note
66 * that the address here is incremented by 0x400 from the Base address
67 * selected in QSys, since the SPI registers are at offset +0x400.
68 * #define CONFIG_SYS_SPI_BASE 0xff240400
73 * Ethernet on SoC (EMAC)
76 #define CONFIG_DW_ALTDESCRIPTOR
82 #ifdef CONFIG_CMD_FPGA
83 #define CONFIG_FPGA_COUNT 1
89 /* This timer uses eosc1, whose clock frequency is fixed at any condition. */
90 #define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS
91 #define CONFIG_SYS_TIMER_COUNTS_DOWN
92 #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4)
93 #define CONFIG_SYS_TIMER_RATE 25000000
98 #ifdef CONFIG_HW_WATCHDOG
99 #define CONFIG_DESIGNWARE_WATCHDOG
100 #define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS
101 #define CONFIG_DW_WDT_CLOCK_KHZ 25000
102 #define CONFIG_WATCHDOG_TIMEOUT_MSECS 30000
108 #ifdef CONFIG_CMD_MMC
109 #define CONFIG_BOUNCE_BUFFER
111 /* using smaller max blk cnt to avoid flooding the limited stack we have */
112 #define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 /* FIXME -- SPL only? */
118 #ifdef CONFIG_NAND_DENALI
119 #define CONFIG_SYS_MAX_NAND_DEVICE 1
120 #define CONFIG_SYS_NAND_ONFI_DETECTION
121 #define CONFIG_SYS_NAND_REGS_BASE SOCFPGA_NANDREGS_ADDRESS
122 #define CONFIG_SYS_NAND_DATA_BASE SOCFPGA_NANDDATA_ADDRESS
128 #ifndef CONFIG_DM_I2C
129 #define CONFIG_SYS_I2C
130 #define CONFIG_SYS_I2C_BASE SOCFPGA_I2C0_ADDRESS
131 #define CONFIG_SYS_I2C_BASE1 SOCFPGA_I2C1_ADDRESS
132 #define CONFIG_SYS_I2C_BASE2 SOCFPGA_I2C2_ADDRESS
133 #define CONFIG_SYS_I2C_BASE3 SOCFPGA_I2C3_ADDRESS
134 /* Using standard mode which the speed up to 100Kb/s */
135 #define CONFIG_SYS_I2C_SPEED 100000
136 #define CONFIG_SYS_I2C_SPEED1 100000
137 #define CONFIG_SYS_I2C_SPEED2 100000
138 #define CONFIG_SYS_I2C_SPEED3 100000
139 /* Address of device when used as slave */
140 #define CONFIG_SYS_I2C_SLAVE 0x02
141 #define CONFIG_SYS_I2C_SLAVE1 0x02
142 #define CONFIG_SYS_I2C_SLAVE2 0x02
143 #define CONFIG_SYS_I2C_SLAVE3 0x02
145 /* Clock supplied to I2C controller in unit of MHz */
146 unsigned int cm_get_l4_sp_clk_hz(void);
147 #define IC_CLK (cm_get_l4_sp_clk_hz() / 1000000)
149 #endif /* CONFIG_DM_I2C */
154 /* Enable multiple SPI NOR flash manufacturers */
155 #ifndef CONFIG_SPL_BUILD
156 #define CONFIG_SPI_FLASH_MTD
158 /* QSPI reference clock */
160 unsigned int cm_get_qspi_controller_clk_hz(void);
161 #define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz()
165 * Designware SPI support
171 #define CONFIG_SYS_NS16550_SERIAL
178 * USB Gadget (DFU, UMS)
180 #if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE)
181 #define CONFIG_SYS_DFU_DATA_BUF_SIZE (16 * 1024 * 1024)
182 #define DFU_DEFAULT_POLL_TIMEOUT 300
185 #define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525
186 #define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5
192 #if !defined(CONFIG_ENV_SIZE)
193 #define CONFIG_ENV_SIZE (8 * 1024)
196 /* Environment for SDMMC boot */
197 #if defined(CONFIG_ENV_IS_IN_MMC) && !defined(CONFIG_ENV_OFFSET)
198 #define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */
199 #define CONFIG_ENV_OFFSET (34 * 512) /* just after the GPT */
202 /* Environment for QSPI boot */
203 #if defined(CONFIG_ENV_IS_IN_SPI_FLASH) && !defined(CONFIG_ENV_OFFSET)
204 #define CONFIG_ENV_OFFSET 0x00100000
205 #define CONFIG_ENV_SECT_SIZE (64 * 1024)
209 * mtd partitioning for serial NOR flash
211 * device nor0 <ff705000.spi.0>, # parts = 6
212 * #: name size offset mask_flags
213 * 0: u-boot 0x00100000 0x00000000 0
214 * 1: env1 0x00040000 0x00100000 0
215 * 2: env2 0x00040000 0x00140000 0
216 * 3: UBI 0x03e80000 0x00180000 0
217 * 4: boot 0x00e80000 0x00180000 0
218 * 5: rootfs 0x01000000 0x01000000 0
225 * SRAM Memory layout for gen 5:
227 * 0xFFFF_0000 ...... Start of SRAM
228 * 0xFFFF_xxxx ...... Top of stack (grows down)
229 * 0xFFFF_yyyy ...... Malloc area
230 * 0xFFFF_zzzz ...... Global Data
231 * 0xFFFF_FF00 ...... End of SRAM
233 * SRAM Memory layout for Arria 10:
234 * 0xFFE0_0000 ...... Start of SRAM (bottom)
235 * 0xFFEx_xxxx ...... Top of stack (grows down to bottom)
236 * 0xFFEy_yyyy ...... Global Data
237 * 0xFFEz_zzzz ...... Malloc area (grows up to top)
238 * 0xFFE3_FFFF ...... End of SRAM (top)
240 #define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR
241 #define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE
243 #if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
244 /* SPL memory allocation configuration, this is for FAT implementation */
245 #ifndef CONFIG_SYS_SPL_MALLOC_START
246 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x00010000
247 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_INIT_RAM_SIZE - \
248 CONFIG_SYS_SPL_MALLOC_SIZE + \
249 CONFIG_SYS_INIT_RAM_ADDR)
253 /* SPL SDMMC boot support */
254 #ifdef CONFIG_SPL_MMC_SUPPORT
255 #if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT)
256 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.img"
257 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
260 #ifndef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION
261 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 1
265 /* SPL QSPI boot support */
266 #ifdef CONFIG_SPL_SPI_SUPPORT
267 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000
270 /* SPL NAND boot support */
271 #ifdef CONFIG_SPL_NAND_SUPPORT
272 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
273 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
279 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
280 #define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
281 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
282 #define CONFIG_SPL_STACK CONFIG_SYS_SPL_MALLOC_START
285 /* Extra Environment */
286 #ifndef CONFIG_SPL_BUILD
288 #ifdef CONFIG_CMD_DHCP
289 #define BOOT_TARGET_DEVICES_DHCP(func) func(DHCP, dhcp, na)
291 #define BOOT_TARGET_DEVICES_DHCP(func)
294 #if defined(CONFIG_CMD_PXE) && defined(CONFIG_CMD_DHCP)
295 #define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na)
297 #define BOOT_TARGET_DEVICES_PXE(func)
300 #ifdef CONFIG_CMD_MMC
301 #define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0)
303 #define BOOT_TARGET_DEVICES_MMC(func)
306 #define BOOT_TARGET_DEVICES(func) \
307 BOOT_TARGET_DEVICES_MMC(func) \
308 BOOT_TARGET_DEVICES_PXE(func) \
309 BOOT_TARGET_DEVICES_DHCP(func)
311 #include <config_distro_bootcmd.h>
313 #ifndef CONFIG_EXTRA_ENV_SETTINGS
314 #define CONFIG_EXTRA_ENV_SETTINGS \
315 "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
316 "bootm_size=0xa000000\0" \
317 "kernel_addr_r="__stringify(CONFIG_SYS_LOAD_ADDR)"\0" \
318 "fdt_addr_r=0x02000000\0" \
319 "scriptaddr=0x02100000\0" \
320 "pxefile_addr_r=0x02200000\0" \
321 "ramdisk_addr_r=0x02300000\0" \
327 #endif /* __CONFIG_SOCFPGA_COMMON_H__ */