1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2017 NXP Semiconductors
5 * Configuration settings for the i.MX7D Pico board.
8 #ifndef __PICO_IMX7D_CONFIG_H
9 #define __PICO_IMX7D_CONFIG_H
11 #include "mx7_common.h"
13 #define PHYS_SDRAM_SIZE SZ_1G
15 /* Size of malloc() pool */
16 #define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M)
18 #define CONFIG_MXC_UART_BASE UART5_IPS_BASE_ADDR
21 #define CONFIG_FEC_MXC
23 #define CONFIG_FEC_XCV_TYPE RGMII
24 #define CONFIG_ETHPRIME "FEC"
25 #define CONFIG_FEC_MXC_PHYADDR 1
27 #define CONFIG_PHY_ATHEROS
30 #define IMX_FEC_BASE ENET_IPS_BASE_ADDR
33 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
35 #define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
36 #define CONFIG_SYS_MMC_IMG_LOAD_PART 1
38 #define CONFIG_EXTRA_ENV_SETTINGS \
42 "fdt_high=0xffffffff\0" \
43 "initrd_high=0xffffffff\0" \
44 "fdtfile=imx7d-pico-pi.dtb\0" \
45 "fdt_addr=0x83000000\0" \
46 "fdt_addr_r=0x83000000\0" \
47 "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
48 "pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
49 "ramdisk_addr_r=0x83000000\0" \
50 "ramdiskaddr=0x83000000\0" \
51 "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \
52 "finduuid=part uuid mmc 0:1 uuid\0" \
54 "uuid_disk=${uuid_gpt_disk};" \
55 "name=rootfs,size=0,uuid=${uuid_gpt_rootfs}\0" \
56 "setup_emmc=mmc dev 0; gpt write mmc 0 $partitions; reset;\0" \
59 #define BOOT_TARGET_DEVICES(func) \
63 #include <config_distro_bootcmd.h>
65 #define CONFIG_SYS_MEMTEST_START 0x80000000
66 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x20000000)
68 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
69 #define CONFIG_SYS_HZ 1000
71 /* Physical Memory Map */
72 #define CONFIG_NR_DRAM_BANKS 1
73 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
75 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
76 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
77 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
79 #define CONFIG_SYS_INIT_SP_OFFSET \
80 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
81 #define CONFIG_SYS_INIT_SP_ADDR \
82 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
85 #define CONFIG_SYS_I2C
86 #define CONFIG_SYS_I2C_MXC
87 #define CONFIG_SYS_I2C_MXC_I2C1
88 #define CONFIG_SYS_I2C_MXC_I2C2
89 #define CONFIG_SYS_I2C_MXC_I2C3
90 #define CONFIG_SYS_I2C_MXC_I2C4
91 #define CONFIG_SYS_I2C_SPEED 100000
95 #define CONFIG_POWER_I2C
96 #define CONFIG_POWER_PFUZE3000
97 #define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08
99 /* FLASH and environment organization */
100 #define CONFIG_ENV_SIZE SZ_8K
102 #define CONFIG_ENV_OFFSET (8 * SZ_64K)
103 #define CONFIG_SYS_FSL_USDHC_NUM 2
105 #define CONFIG_SYS_MMC_ENV_DEV 0
106 #define CONFIG_SYS_MMC_ENV_PART 0
109 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
110 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
111 #define CONFIG_MXC_USB_FLAGS 0
112 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
114 #define CONFIG_IMX_THERMAL