1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2010-2011 Freescale Semiconductor, Inc.
8 * QorIQ RDB boards configuration file
13 #if defined(CONFIG_TARGET_P1020MBG)
14 #define CONFIG_BOARDNAME "P1020MBG-PC"
15 #define CONFIG_VSC7385_ENET
17 #define __SW_BOOT_MASK 0x03
18 #define __SW_BOOT_NOR 0xe4
19 #define __SW_BOOT_SD 0x54
20 #define CONFIG_SYS_L2_SIZE (256 << 10)
23 #if defined(CONFIG_TARGET_P1020UTM)
24 #define CONFIG_BOARDNAME "P1020UTM-PC"
25 #define __SW_BOOT_MASK 0x03
26 #define __SW_BOOT_NOR 0xe0
27 #define __SW_BOOT_SD 0x50
28 #define CONFIG_SYS_L2_SIZE (256 << 10)
31 #if defined(CONFIG_TARGET_P1020RDB_PC)
32 #define CONFIG_BOARDNAME "P1020RDB-PC"
33 #define CONFIG_NAND_FSL_ELBC
34 #define CONFIG_VSC7385_ENET
36 #define __SW_BOOT_MASK 0x03
37 #define __SW_BOOT_NOR 0x5c
38 #define __SW_BOOT_SPI 0x1c
39 #define __SW_BOOT_SD 0x9c
40 #define __SW_BOOT_NAND 0xec
41 #define __SW_BOOT_PCIE 0x6c
42 #define CONFIG_SYS_L2_SIZE (256 << 10)
46 * P1020RDB-PD board has user selectable switches for evaluating different
47 * frequency and boot options for the P1020 device. The table that
48 * follow describe the available options. The front six binary number was in
49 * accordance with SW3[1:6].
50 * 111101 533 533 267 667 NOR Core0 boot; Core1 hold-off
51 * 101101 667 667 333 667 NOR Core0 boot; Core1 hold-off
52 * 011001 800 800 400 667 NOR Core0 boot; Core1 hold-off
53 * 001001 800 800 400 667 SD/MMC Core0 boot; Core1 hold-off
54 * 001101 800 800 400 667 SPI Core0 boot; Core1 hold-off
55 * 010001 800 800 400 667 NAND Core0 boot; Core1 hold-off
56 * 011101 800 800 400 667 PCIe-2 Core0 boot; Core1 hold-off
58 #if defined(CONFIG_TARGET_P1020RDB_PD)
59 #define CONFIG_BOARDNAME "P1020RDB-PD"
60 #define CONFIG_NAND_FSL_ELBC
61 #define CONFIG_VSC7385_ENET
63 #define __SW_BOOT_MASK 0x03
64 #define __SW_BOOT_NOR 0x64
65 #define __SW_BOOT_SPI 0x34
66 #define __SW_BOOT_SD 0x24
67 #define __SW_BOOT_NAND 0x44
68 #define __SW_BOOT_PCIE 0x74
69 #define CONFIG_SYS_L2_SIZE (256 << 10)
71 * Dynamic MTD Partition support with mtdparts
75 #if defined(CONFIG_TARGET_P1021RDB)
76 #define CONFIG_BOARDNAME "P1021RDB-PC"
77 #define CONFIG_NAND_FSL_ELBC
78 #define CONFIG_VSC7385_ENET
79 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of
80 addresses in the LBC */
81 #define __SW_BOOT_MASK 0x03
82 #define __SW_BOOT_NOR 0x5c
83 #define __SW_BOOT_SPI 0x1c
84 #define __SW_BOOT_SD 0x9c
85 #define __SW_BOOT_NAND 0xec
86 #define __SW_BOOT_PCIE 0x6c
87 #define CONFIG_SYS_L2_SIZE (256 << 10)
89 * Dynamic MTD Partition support with mtdparts
93 #if defined(CONFIG_TARGET_P1024RDB)
94 #define CONFIG_BOARDNAME "P1024RDB"
95 #define CONFIG_NAND_FSL_ELBC
97 #define __SW_BOOT_MASK 0xf3
98 #define __SW_BOOT_NOR 0x00
99 #define __SW_BOOT_SPI 0x08
100 #define __SW_BOOT_SD 0x04
101 #define __SW_BOOT_NAND 0x0c
102 #define CONFIG_SYS_L2_SIZE (256 << 10)
105 #if defined(CONFIG_TARGET_P1025RDB)
106 #define CONFIG_BOARDNAME "P1025RDB"
107 #define CONFIG_NAND_FSL_ELBC
110 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of
111 addresses in the LBC */
112 #define __SW_BOOT_MASK 0xf3
113 #define __SW_BOOT_NOR 0x00
114 #define __SW_BOOT_SPI 0x08
115 #define __SW_BOOT_SD 0x04
116 #define __SW_BOOT_NAND 0x0c
117 #define CONFIG_SYS_L2_SIZE (256 << 10)
120 #if defined(CONFIG_TARGET_P2020RDB)
121 #define CONFIG_BOARDNAME "P2020RDB-PC"
122 #define CONFIG_NAND_FSL_ELBC
123 #define CONFIG_VSC7385_ENET
124 #define __SW_BOOT_MASK 0x03
125 #define __SW_BOOT_NOR 0xc8
126 #define __SW_BOOT_SPI 0x28
127 #define __SW_BOOT_SD 0x68 /* or 0x18 */
128 #define __SW_BOOT_NAND 0xe8
129 #define __SW_BOOT_PCIE 0xa8
130 #define CONFIG_SYS_L2_SIZE (512 << 10)
132 * Dynamic MTD Partition support with mtdparts
137 #define CONFIG_SPL_FLUSH_IMAGE
138 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
139 #define CONFIG_SPL_PAD_TO 0x20000
140 #define CONFIG_SPL_MAX_SIZE (128 * 1024)
141 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
142 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
143 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
144 #define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10)
145 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
146 #ifdef CONFIG_SPL_BUILD
147 #define CONFIG_SPL_COMMON_INIT_DDR
151 #ifdef CONFIG_SPIFLASH
152 #define CONFIG_SPL_SPI_FLASH_MINIMAL
153 #define CONFIG_SPL_FLUSH_IMAGE
154 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
155 #define CONFIG_SPL_PAD_TO 0x20000
156 #define CONFIG_SPL_MAX_SIZE (128 * 1024)
157 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
158 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
159 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
160 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10)
161 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
162 #ifdef CONFIG_SPL_BUILD
163 #define CONFIG_SPL_COMMON_INIT_DDR
167 #ifdef CONFIG_MTD_RAW_NAND
168 #ifdef CONFIG_TPL_BUILD
169 #define CONFIG_SPL_FLUSH_IMAGE
170 #define CONFIG_SPL_NAND_INIT
171 #define CONFIG_SPL_COMMON_INIT_DDR
172 #define CONFIG_SPL_MAX_SIZE (128 << 10)
173 #define CONFIG_TPL_TEXT_BASE 0xf8f81000
174 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
175 #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10)
176 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
177 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
178 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
179 #elif defined(CONFIG_SPL_BUILD)
180 #define CONFIG_SPL_INIT_MINIMAL
181 #define CONFIG_SPL_FLUSH_IMAGE
182 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
183 #define CONFIG_SPL_MAX_SIZE 4096
184 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
185 #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000
186 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000
187 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10)
188 #endif /* not CONFIG_TPL_BUILD */
190 #define CONFIG_SPL_PAD_TO 0x20000
191 #define CONFIG_TPL_PAD_TO 0x20000
192 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
195 #ifndef CONFIG_RESET_VECTOR_ADDRESS
196 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
199 #ifndef CONFIG_SYS_MONITOR_BASE
200 #ifdef CONFIG_TPL_BUILD
201 #define CONFIG_SYS_MONITOR_BASE CONFIG_TPL_TEXT_BASE
202 #elif defined(CONFIG_SPL_BUILD)
203 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
205 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
209 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
210 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
211 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
213 #define CONFIG_ENV_OVERWRITE
215 #define CONFIG_SYS_SATA_MAX_DEVICE 2
218 #if defined(CONFIG_TARGET_P2020RDB)
219 #define CONFIG_SYS_CLK_FREQ 100000000
221 #define CONFIG_SYS_CLK_FREQ 66666666
223 #define CONFIG_DDR_CLK_FREQ 66666666
225 #define CONFIG_HWCONFIG
227 * These can be toggled for performance analysis, otherwise use default.
229 #define CONFIG_L2_CACHE
232 #define CONFIG_ENABLE_36BIT_PHYS
234 #ifdef CONFIG_PHYS_64BIT
235 #define CONFIG_ADDR_MAP 1
236 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
239 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
240 #define CONFIG_SYS_MEMTEST_END 0x1fffffff
242 #define CONFIG_SYS_CCSRBAR 0xffe00000
243 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
245 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
247 #ifdef CONFIG_SPL_BUILD
248 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
252 #define CONFIG_SYS_DDR_RAW_TIMING
253 #define CONFIG_DDR_SPD
254 #define CONFIG_SYS_SPD_BUS_NUM 1
255 #define SPD_EEPROM_ADDRESS 0x52
257 #if (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD))
258 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G
259 #define CONFIG_CHIP_SELECTS_PER_CTRL 2
261 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_1G
262 #define CONFIG_CHIP_SELECTS_PER_CTRL 1
264 #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
265 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
266 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
268 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
270 /* Default settings for DDR3 */
271 #ifndef CONFIG_TARGET_P2020RDB
272 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
273 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
274 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
275 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f
276 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302
277 #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000
279 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
280 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
281 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
282 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
284 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
285 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608
286 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000
287 #define CONFIG_SYS_DDR_RCW_1 0x00000000
288 #define CONFIG_SYS_DDR_RCW_2 0x00000000
289 #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */
290 #define CONFIG_SYS_DDR_CONTROL_2 0x04401050
291 #define CONFIG_SYS_DDR_TIMING_4 0x00220001
292 #define CONFIG_SYS_DDR_TIMING_5 0x03402400
294 #define CONFIG_SYS_DDR_TIMING_3 0x00020000
295 #define CONFIG_SYS_DDR_TIMING_0 0x00330004
296 #define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846
297 #define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF
298 #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000
299 #define CONFIG_SYS_DDR_MODE_1 0x40461520
300 #define CONFIG_SYS_DDR_MODE_2 0x8000c000
301 #define CONFIG_SYS_DDR_INTERVAL 0x0C300000
304 #undef CONFIG_CLOCKS_IN_MHZ
309 * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable
310 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3)
311 * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1
312 * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 512K cacheable
314 * 0xff80_0000 0xff80_7fff NAND flash 32K non-cacheable CS1/0
315 * 0xff98_0000 0xff98_ffff PMC 64K non-cacheable CS2
316 * 0xffa0_0000 0xffaf_ffff CPLD 1M non-cacheable CS3
317 * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable CS2
318 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
319 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable
320 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
324 * Local Bus Definitions
326 #if (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD))
327 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */
328 #define CONFIG_SYS_FLASH_BASE 0xec000000
329 #elif defined(CONFIG_TARGET_P1020UTM)
330 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */
331 #define CONFIG_SYS_FLASH_BASE 0xee000000
333 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* 16M */
334 #define CONFIG_SYS_FLASH_BASE 0xef000000
337 #ifdef CONFIG_PHYS_64BIT
338 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
340 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
343 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
346 #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7
348 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
349 #define CONFIG_SYS_FLASH_QUIET_TEST
350 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
352 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
354 #undef CONFIG_SYS_FLASH_CHECKSUM
355 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
356 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
358 #define CONFIG_SYS_FLASH_EMPTY_INFO
361 #ifdef CONFIG_NAND_FSL_ELBC
362 #define CONFIG_SYS_NAND_BASE 0xff800000
363 #ifdef CONFIG_PHYS_64BIT
364 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
366 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
369 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
370 #define CONFIG_SYS_MAX_NAND_DEVICE 1
371 #if defined(CONFIG_TARGET_P1020RDB_PD)
372 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
374 #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024)
377 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
378 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
379 | BR_PS_8 /* Port Size = 8 bit */ \
380 | BR_MS_FCM /* MSEL = FCM */ \
382 #if defined(CONFIG_TARGET_P1020RDB_PD)
383 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \
384 | OR_FCM_PGS /* Large Page*/ \
392 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* small page */ \
400 #endif /* CONFIG_NAND_FSL_ELBC */
402 #define CONFIG_SYS_INIT_RAM_LOCK
403 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
404 #ifdef CONFIG_PHYS_64BIT
405 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
406 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
407 /* The assembler doesn't like typecast */
408 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
409 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
410 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
412 /* Initial L1 address */
413 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
414 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
415 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
417 /* Size of used area in RAM */
418 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
420 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
421 GENERATED_GBL_DATA_SIZE)
422 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
424 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
425 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */
427 #define CONFIG_SYS_CPLD_BASE 0xffa00000
428 #ifdef CONFIG_PHYS_64BIT
429 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffa00000ull
431 #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
433 /* CPLD config size: 1Mb */
434 #define CONFIG_CPLD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) | \
436 #define CONFIG_CPLD_OR_PRELIM (0xfff009f7)
438 #define CONFIG_SYS_PMC_BASE 0xff980000
439 #define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE
440 #define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \
442 #define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
443 OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \
446 #ifdef CONFIG_MTD_RAW_NAND
447 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
448 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
449 #define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
450 #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
452 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
453 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
454 #ifdef CONFIG_NAND_FSL_ELBC
455 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
456 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
459 #define CONFIG_SYS_BR3_PRELIM CONFIG_CPLD_BR_PRELIM /* CPLD Base Address */
460 #define CONFIG_SYS_OR3_PRELIM CONFIG_CPLD_OR_PRELIM /* CPLD Options */
463 #ifdef CONFIG_VSC7385_ENET
464 #define CONFIG_SYS_VSC7385_BASE 0xffb00000
466 #ifdef CONFIG_PHYS_64BIT
467 #define CONFIG_SYS_VSC7385_BASE_PHYS 0xfffb00000ull
469 #define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE
472 #define CONFIG_SYS_VSC7385_BR_PRELIM \
473 (BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE_PHYS) | BR_PS_8 | BR_V)
474 #define CONFIG_SYS_VSC7385_OR_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | \
475 OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | \
476 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
478 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_VSC7385_BR_PRELIM
479 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_VSC7385_OR_PRELIM
481 /* The size of the VSC7385 firmware image */
482 #define CONFIG_VSC7385_IMAGE_SIZE 8192
486 * Config the L2 Cache as L2 SRAM
488 #if defined(CONFIG_SPL_BUILD)
489 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
490 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
491 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
492 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
493 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
494 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
495 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024)
496 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024)
497 #if defined(CONFIG_TARGET_P2020RDB)
498 #define CONFIG_SPL_RELOC_MALLOC_SIZE (364 << 10)
500 #define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10)
502 #elif defined(CONFIG_MTD_RAW_NAND)
503 #ifdef CONFIG_TPL_BUILD
504 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
505 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
506 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
507 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
508 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
509 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
510 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
511 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
513 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
514 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
515 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
516 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000)
517 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
518 #endif /* CONFIG_TPL_BUILD */
522 /* Serial Port - controlled on board with jumper J8
526 #undef CONFIG_SERIAL_SOFTWARE_FIFO
527 #define CONFIG_SYS_NS16550_SERIAL
528 #define CONFIG_SYS_NS16550_REG_SIZE 1
529 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
530 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
531 #define CONFIG_NS16550_MIN_FUNCTIONS
534 #define CONFIG_SYS_BAUDRATE_TABLE \
535 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
537 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
538 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
541 #ifndef CONFIG_DM_I2C
542 #define CONFIG_SYS_I2C
543 #define CONFIG_SYS_FSL_I2C_SPEED 400000
544 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
545 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
546 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
547 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
548 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
549 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
551 #define CONFIG_I2C_SET_DEFAULT_BUS_NUM
552 #define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
555 #define CONFIG_SYS_I2C_FSL
556 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
557 #define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */
562 #undef CONFIG_ID_EEPROM
564 #define CONFIG_RTC_PT7C4338
565 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
566 #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18
568 /* enable read and write access to EEPROM */
569 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
570 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
571 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
573 #if defined(CONFIG_PCI)
576 * Memory space is mapped 1-1, but I/O space must start from 0.
579 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
580 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
581 #ifdef CONFIG_PHYS_64BIT
582 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
584 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
586 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
587 #ifdef CONFIG_PHYS_64BIT
588 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
590 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
593 /* controller 1, Slot 2, tgtid 1, Base address a000 */
594 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
595 #ifdef CONFIG_PHYS_64BIT
596 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
598 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
600 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
601 #ifdef CONFIG_PHYS_64BIT
602 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
604 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
607 #if !defined(CONFIG_DM_PCI)
608 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
609 #define CONFIG_PCI_INDIRECT_BRIDGE
610 #define CONFIG_SYS_PCIE2_NAME "PCIe SLOT"
611 #ifdef CONFIG_PHYS_64BIT
612 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
614 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
616 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
617 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
618 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
620 #define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT"
621 #ifdef CONFIG_PHYS_64BIT
622 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
624 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
626 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
627 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
628 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
631 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
632 #endif /* CONFIG_PCI */
634 #if defined(CONFIG_TSEC_ENET)
636 #define CONFIG_TSEC1_NAME "eTSEC1"
638 #define CONFIG_TSEC2_NAME "eTSEC2"
640 #define CONFIG_TSEC3_NAME "eTSEC3"
642 #define TSEC1_PHY_ADDR 2
643 #define TSEC2_PHY_ADDR 0
644 #define TSEC3_PHY_ADDR 1
646 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
647 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
648 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
650 #define TSEC1_PHYIDX 0
651 #define TSEC2_PHYIDX 0
652 #define TSEC3_PHYIDX 0
654 #define CONFIG_ETHPRIME "eTSEC1"
656 #define CONFIG_HAS_ETH0
657 #define CONFIG_HAS_ETH1
658 #define CONFIG_HAS_ETH2
659 #endif /* CONFIG_TSEC_ENET */
662 /* QE microcode/firmware address */
663 #define CONFIG_SYS_QE_FW_ADDR 0xefec0000
664 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
665 #endif /* CONFIG_QE */
667 #ifdef CONFIG_TARGET_P1025RDB
669 * QE UEC ethernet configuration
671 #define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120)
673 #undef CONFIG_UEC_ETH
674 #define CONFIG_PHY_MODE_NEED_CHANGE
676 #define CONFIG_UEC_ETH1 /* ETH1 */
677 #define CONFIG_HAS_ETH0
679 #ifdef CONFIG_UEC_ETH1
680 #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */
681 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK12 /* CLK12 for MII */
682 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 /* CLK9 for MII */
683 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
684 #define CONFIG_SYS_UEC1_PHY_ADDR 0x0 /* 0x0 for MII */
685 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
686 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
687 #endif /* CONFIG_UEC_ETH1 */
689 #define CONFIG_UEC_ETH5 /* ETH5 */
690 #define CONFIG_HAS_ETH1
692 #ifdef CONFIG_UEC_ETH5
693 #define CONFIG_SYS_UEC5_UCC_NUM 4 /* UCC5 */
694 #define CONFIG_SYS_UEC5_RX_CLK QE_CLK_NONE
695 #define CONFIG_SYS_UEC5_TX_CLK QE_CLK13 /* CLK 13 for RMII */
696 #define CONFIG_SYS_UEC5_ETH_TYPE FAST_ETH
697 #define CONFIG_SYS_UEC5_PHY_ADDR 0x3 /* 0x3 for RMII */
698 #define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
699 #define CONFIG_SYS_UEC5_INTERFACE_SPEED 100
700 #endif /* CONFIG_UEC_ETH5 */
701 #endif /* CONFIG_TARGET_P1025RDB */
706 #if defined(CONFIG_SDCARD)
707 #define CONFIG_FSL_FIXED_MMC_LOCATION
708 #define CONFIG_SYS_MMC_ENV_DEV 0
709 #elif defined(CONFIG_MTD_RAW_NAND)
710 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
711 #ifdef CONFIG_TPL_BUILD
712 #define SPL_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
714 #elif defined(CONFIG_SYS_RAMBOOT)
715 #define SPL_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
718 #define CONFIG_LOADS_ECHO /* echo on for serial download */
719 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
724 #define CONFIG_HAS_FSL_DR_USB
726 #if defined(CONFIG_HAS_FSL_DR_USB)
727 #ifdef CONFIG_USB_EHCI_HCD
728 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
729 #define CONFIG_USB_EHCI_FSL
733 #if defined(CONFIG_TARGET_P1020RDB_PD)
734 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
738 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
741 #undef CONFIG_WATCHDOG /* watchdog disabled */
744 * Miscellaneous configurable options
746 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
749 * For booting Linux, the board info and command line data
750 * have to be in the first 64 MB of memory, since this is
751 * the maximum mapped by the Linux kernel during initialization.
753 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/
754 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
756 #if defined(CONFIG_CMD_KGDB)
757 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
761 * Environment Configuration
763 #define CONFIG_HOSTNAME "unknown"
764 #define CONFIG_ROOTPATH "/opt/nfsroot"
765 #define CONFIG_BOOTFILE "uImage"
766 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
768 /* default location for tftp and bootm */
769 #define CONFIG_LOADADDR 1000000
772 #define __NOR_RST_CMD \
773 norboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NOR 1; \
774 i2c mw 18 3 __SW_BOOT_MASK 1; reset
777 #define __SPI_RST_CMD \
778 spiboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SPI 1; \
779 i2c mw 18 3 __SW_BOOT_MASK 1; reset
782 #define __SD_RST_CMD \
783 sdboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SD 1; \
784 i2c mw 18 3 __SW_BOOT_MASK 1; reset
786 #ifdef __SW_BOOT_NAND
787 #define __NAND_RST_CMD \
788 nandboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NAND 1; \
789 i2c mw 18 3 __SW_BOOT_MASK 1; reset
791 #ifdef __SW_BOOT_PCIE
792 #define __PCIE_RST_CMD \
793 pciboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_PCIE 1; \
794 i2c mw 18 3 __SW_BOOT_MASK 1; reset
797 #define CONFIG_EXTRA_ENV_SETTINGS \
799 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
800 "loadaddr=1000000\0" \
801 "bootfile=uImage\0" \
802 "tftpflash=tftpboot $loadaddr $uboot; " \
803 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
804 "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
805 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
806 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
807 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
808 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \
809 "consoledev=ttyS0\0" \
810 "ramdiskaddr=2000000\0" \
811 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
812 "fdtaddr=1e00000\0" \
814 "jffs2nor=mtdblock3\0" \
815 "norbootaddr=ef080000\0" \
816 "norfdtaddr=ef040000\0" \
817 "jffs2nand=mtdblock9\0" \
818 "nandbootaddr=100000\0" \
819 "nandfdtaddr=80000\0" \
820 "ramdisk_size=120000\0" \
821 "map_lowernorbank=i2c dev 1; i2c mw 18 1 02 1; i2c mw 18 3 fd 1\0" \
822 "map_uppernorbank=i2c dev 1; i2c mw 18 1 00 1; i2c mw 18 3 fd 1\0" \
823 __stringify(__NOR_RST_CMD)"\0" \
824 __stringify(__SPI_RST_CMD)"\0" \
825 __stringify(__SD_RST_CMD)"\0" \
826 __stringify(__NAND_RST_CMD)"\0" \
827 __stringify(__PCIE_RST_CMD)"\0"
829 #define CONFIG_NFSBOOTCOMMAND \
830 "setenv bootargs root=/dev/nfs rw " \
831 "nfsroot=$serverip:$rootpath " \
832 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
833 "console=$consoledev,$baudrate $othbootargs;" \
834 "tftp $loadaddr $bootfile;" \
835 "tftp $fdtaddr $fdtfile;" \
836 "bootm $loadaddr - $fdtaddr"
838 #define CONFIG_HDBOOT \
839 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
840 "console=$consoledev,$baudrate $othbootargs;" \
842 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
843 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
844 "bootm $loadaddr - $fdtaddr"
846 #define CONFIG_USB_FAT_BOOT \
847 "setenv bootargs root=/dev/ram rw " \
848 "console=$consoledev,$baudrate $othbootargs " \
849 "ramdisk_size=$ramdisk_size;" \
851 "fatload usb 0:2 $loadaddr $bootfile;" \
852 "fatload usb 0:2 $fdtaddr $fdtfile;" \
853 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
854 "bootm $loadaddr $ramdiskaddr $fdtaddr"
856 #define CONFIG_USB_EXT2_BOOT \
857 "setenv bootargs root=/dev/ram rw " \
858 "console=$consoledev,$baudrate $othbootargs " \
859 "ramdisk_size=$ramdisk_size;" \
861 "ext2load usb 0:4 $loadaddr $bootfile;" \
862 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
863 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
864 "bootm $loadaddr $ramdiskaddr $fdtaddr"
866 #define CONFIG_NORBOOT \
867 "setenv bootargs root=/dev/$jffs2nor rw " \
868 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \
869 "bootm $norbootaddr - $norfdtaddr"
871 #define CONFIG_RAMBOOTCOMMAND \
872 "setenv bootargs root=/dev/ram rw " \
873 "console=$consoledev,$baudrate $othbootargs " \
874 "ramdisk_size=$ramdisk_size;" \
875 "tftp $ramdiskaddr $ramdiskfile;" \
876 "tftp $loadaddr $bootfile;" \
877 "tftp $fdtaddr $fdtfile;" \
878 "bootm $loadaddr $ramdiskaddr $fdtaddr"
880 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
882 #endif /* __CONFIG_H */