include/configs/ls2080ardb.h

   1 /*
   2  * Copyright 2015 Freescale Semiconductor
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef __LS2_RDB_H
   8 #define __LS2_RDB_H
   9
  10 #include "ls2080a_common.h"
  11
  12 #undef CONFIG_CONS_INDEX
  13 #define CONFIG_CONS_INDEX       2
  14
  15 #define CONFIG_DISPLAY_BOARDINFO
  16
  17 #define I2C_MUX_CH_VOL_MONITOR          0xa
  18 #define I2C_VOL_MONITOR_ADDR            0x38
  19 #define CONFIG_VOL_MONITOR_IR36021_READ
  20 #define CONFIG_VOL_MONITOR_IR36021_SET
  21
  22 #define CONFIG_VID_FLS_ENV              "ls2080ardb_vdd_mv"
  23 #ifndef CONFIG_SPL_BUILD
  24 #define CONFIG_VID
  25 #endif
  26 /* step the IR regulator in 5mV increments */
  27 #define IR_VDD_STEP_DOWN                5
  28 #define IR_VDD_STEP_UP                  5
  29 /* The lowest and highest voltage allowed for LS2080ARDB */
  30 #define VDD_MV_MIN                      819
  31 #define VDD_MV_MAX                      1212
  32
  33 #ifndef __ASSEMBLY__
  34 unsigned long get_board_sys_clk(void);
  35 #endif
  36
  37 #define CONFIG_SYS_FSL_CLK
  38 #define CONFIG_SYS_CLK_FREQ             get_board_sys_clk()
  39 #define CONFIG_DDR_CLK_FREQ             133333333
  40 #define COUNTER_FREQUENCY_REAL          (CONFIG_SYS_CLK_FREQ/4)
  41
  42 #define CONFIG_DDR_SPD
  43 #define CONFIG_DDR_ECC
  44 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  45 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  46 #define SPD_EEPROM_ADDRESS1     0x51
  47 #define SPD_EEPROM_ADDRESS2     0x52
  48 #define SPD_EEPROM_ADDRESS3     0x53
  49 #define SPD_EEPROM_ADDRESS4     0x54
  50 #define SPD_EEPROM_ADDRESS5     0x55
  51 #define SPD_EEPROM_ADDRESS6     0x56    /* dummy address */
  52 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1
  53 #define CONFIG_SYS_SPD_BUS_NUM  0       /* SPD on I2C bus 0 */
  54 #define CONFIG_DIMM_SLOTS_PER_CTLR              2
  55 #define CONFIG_CHIP_SELECTS_PER_CTRL            4
  56 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
  57 #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR       1
  58 #endif
  59 #define CONFIG_FSL_DDR_BIST     /* enable built-in memory test */
  60
  61 /* SATA */
  62 #define CONFIG_LIBATA
  63 #define CONFIG_SCSI_AHCI
  64 #define CONFIG_SCSI_AHCI_PLAT
  65 #define CONFIG_CMD_SCSI
  66 #define CONFIG_CMD_FAT
  67 #define CONFIG_CMD_EXT2
  68 #define CONFIG_DOS_PARTITION
  69 #define CONFIG_BOARD_LATE_INIT
  70
  71 #define CONFIG_SYS_SATA1                        AHCI_BASE_ADDR1
  72 #define CONFIG_SYS_SATA2                        AHCI_BASE_ADDR2
  73
  74 #define CONFIG_SYS_SCSI_MAX_SCSI_ID             1
  75 #define CONFIG_SYS_SCSI_MAX_LUN                 1
  76 #define CONFIG_SYS_SCSI_MAX_DEVICE              (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
  77                                                 CONFIG_SYS_SCSI_MAX_LUN)
  78
  79 /* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */
  80
  81 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
  82 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128*1024*1024)
  83 #define CONFIG_SYS_NOR_AMASK_EARLY      IFC_AMASK(64*1024*1024)
  84
  85 #define CONFIG_SYS_NOR0_CSPR                                    \
  86         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS)             | \
  87         CSPR_PORT_SIZE_16                                       | \
  88         CSPR_MSEL_NOR                                           | \
  89         CSPR_V)
  90 #define CONFIG_SYS_NOR0_CSPR_EARLY                              \
  91         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY)       | \
  92         CSPR_PORT_SIZE_16                                       | \
  93         CSPR_MSEL_NOR                                           | \
  94         CSPR_V)
  95 #define CONFIG_SYS_NOR_CSOR     CSOR_NOR_ADM_SHIFT(12)
  96 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
  97                                 FTIM0_NOR_TEADC(0x5) | \
  98                                 FTIM0_NOR_TEAHC(0x5))
  99 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 100                                 FTIM1_NOR_TRAD_NOR(0x1a) |\
 101                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 102 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 103                                 FTIM2_NOR_TCH(0x4) | \
 104                                 FTIM2_NOR_TWPH(0x0E) | \
 105                                 FTIM2_NOR_TWP(0x1c))
 106 #define CONFIG_SYS_NOR_FTIM3    0x04000000
 107 #define CONFIG_SYS_IFC_CCR      0x01000000
 108
 109 #ifndef CONFIG_SYS_NO_FLASH
 110 #define CONFIG_FLASH_CFI_DRIVER
 111 #define CONFIG_SYS_FLASH_CFI
 112 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 113 #define CONFIG_SYS_FLASH_QUIET_TEST
 114 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 115
 116 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 117 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 118 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 119 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 120
 121 #define CONFIG_SYS_FLASH_EMPTY_INFO
 122 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE,\
 123                                          CONFIG_SYS_FLASH_BASE + 0x40000000}
 124 #endif
 125
 126 #define CONFIG_NAND_FSL_IFC
 127 #define CONFIG_SYS_NAND_MAX_ECCPOS      256
 128 #define CONFIG_SYS_NAND_MAX_OOBFREE     2
 129
 130
 131 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
 132 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 133                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 134                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 135                                 | CSPR_V)
 136 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64 * 1024)
 137
 138 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 139                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 140                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 141                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
 142                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
 143                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
 144                                 | CSOR_NAND_PB(128))    /* Pages Per Block 128*/
 145
 146 #define CONFIG_SYS_NAND_ONFI_DETECTION
 147
 148 /* ONFI NAND Flash mode0 Timing Params */
 149 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x0e) | \
 150                                         FTIM0_NAND_TWP(0x30)   | \
 151                                         FTIM0_NAND_TWCHT(0x0e) | \
 152                                         FTIM0_NAND_TWH(0x14))
 153 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x64) | \
 154                                         FTIM1_NAND_TWBE(0xab)  | \
 155                                         FTIM1_NAND_TRR(0x1c)   | \
 156                                         FTIM1_NAND_TRP(0x30))
 157 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x1e) | \
 158                                         FTIM2_NAND_TREH(0x14) | \
 159                                         FTIM2_NAND_TWHRE(0x3c))
 160 #define CONFIG_SYS_NAND_FTIM3           0x0
 161
 162 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 163 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 164 #define CONFIG_MTD_NAND_VERIFY_WRITE
 165 #define CONFIG_CMD_NAND
 166
 167 #define CONFIG_SYS_NAND_BLOCK_SIZE      (512 * 1024)
 168
 169 #define CONFIG_FSL_QIXIS        /* use common QIXIS code */
 170 #define QIXIS_LBMAP_SWITCH              0x06
 171 #define QIXIS_LBMAP_MASK                0x0f
 172 #define QIXIS_LBMAP_SHIFT               0
 173 #define QIXIS_LBMAP_DFLTBANK            0x00
 174 #define QIXIS_LBMAP_ALTBANK             0x04
 175 #define QIXIS_LBMAP_NAND                0x09
 176 #define QIXIS_RST_CTL_RESET             0x31
 177 #define QIXIS_RST_CTL_RESET_EN          0x30
 178 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 179 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 180 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 181 #define QIXIS_RCW_SRC_NAND              0x119
 182 #define QIXIS_RST_FORCE_MEM             0x01
 183
 184 #define CONFIG_SYS_CSPR3_EXT    (0x0)
 185 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
 186                                 | CSPR_PORT_SIZE_8 \
 187                                 | CSPR_MSEL_GPCM \
 188                                 | CSPR_V)
 189 #define CONFIG_SYS_CSPR3_FINAL  (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 190                                 | CSPR_PORT_SIZE_8 \
 191                                 | CSPR_MSEL_GPCM \
 192                                 | CSPR_V)
 193
 194 #define CONFIG_SYS_AMASK3       IFC_AMASK(64*1024)
 195 #define CONFIG_SYS_CSOR3        CSOR_GPCM_ADM_SHIFT(12)
 196 /* QIXIS Timing parameters for IFC CS3 */
 197 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 198                                         FTIM0_GPCM_TEADC(0x0e) | \
 199                                         FTIM0_GPCM_TEAHC(0x0e))
 200 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0xff) | \
 201                                         FTIM1_GPCM_TRAD(0x3f))
 202 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0xf) | \
 203                                         FTIM2_GPCM_TCH(0xf) | \
 204                                         FTIM2_GPCM_TWP(0x3E))
 205 #define CONFIG_SYS_CS3_FTIM3            0x0
 206
 207 #if defined(CONFIG_SPL) && defined(CONFIG_NAND)
 208 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 209 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR0_CSPR_EARLY
 210 #define CONFIG_SYS_CSPR2_FINAL          CONFIG_SYS_NOR0_CSPR
 211 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 212 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 213 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 214 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 215 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 216 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 217 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 218 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 219 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 220 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 221 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 222 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 223 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 224 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 225
 226 #define CONFIG_ENV_IS_IN_NAND
 227 #define CONFIG_ENV_OFFSET               (2048 * 1024)
 228 #define CONFIG_ENV_SECT_SIZE            0x20000
 229 #define CONFIG_ENV_SIZE                 0x2000
 230 #define CONFIG_SPL_PAD_TO               0x80000
 231 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (1024 * 1024)
 232 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (512 * 1024)
 233 #else
 234 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 235 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR_EARLY
 236 #define CONFIG_SYS_CSPR0_FINAL          CONFIG_SYS_NOR0_CSPR
 237 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 238 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 239 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 240 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 241 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 242 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 243 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 244 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 245 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 246 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 247 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 248 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 249 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 250 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 251
 252 #define CONFIG_ENV_IS_IN_FLASH
 253 #define CONFIG_ENV_ADDR                 (CONFIG_SYS_FLASH_BASE + 0x200000)
 254 #define CONFIG_ENV_SECT_SIZE            0x20000
 255 #define CONFIG_ENV_SIZE                 0x2000
 256 #endif
 257
 258 /* Debug Server firmware */
 259 #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
 260 #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL
 261
 262 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
 263
 264 /*
 265  * I2C
 266  */
 267 #define I2C_MUX_PCA_ADDR                0x75
 268 #define I2C_MUX_PCA_ADDR_PRI            0x75 /* Primary Mux*/
 269
 270 /* I2C bus multiplexer */
 271 #define I2C_MUX_CH_DEFAULT      0x8
 272
 273 /* SPI */
 274 #ifdef CONFIG_FSL_DSPI
 275 #define CONFIG_CMD_SF
 276 #define CONFIG_SPI_FLASH
 277 #define CONFIG_SPI_FLASH_BAR
 278 #endif
 279
 280 /*
 281  * RTC configuration
 282  */
 283 #define RTC
 284 #define CONFIG_RTC_DS3231               1
 285 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
 286 #define CONFIG_CMD_DATE
 287
 288 /* EEPROM */
 289 #define CONFIG_ID_EEPROM
 290 #define CONFIG_CMD_EEPROM
 291 #define CONFIG_SYS_I2C_EEPROM_NXID
 292 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 293 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 294 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 295 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 296 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
 297
 298 #define CONFIG_FSL_MEMAC
 299 #define CONFIG_PCI              /* Enable PCIE */
 300 #define CONFIG_PCIE_LAYERSCAPE  /* Use common FSL Layerscape PCIe code */
 301
 302 #ifdef CONFIG_PCI
 303 #define CONFIG_PCI_PNP
 304 #define CONFIG_PCI_SCAN_SHOW
 305 #define CONFIG_CMD_PCI
 306 #endif
 307
 308 /*  MMC  */
 309 #define CONFIG_MMC
 310 #ifdef CONFIG_MMC
 311 #define CONFIG_CMD_MMC
 312 #define CONFIG_FSL_ESDHC
 313 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
 314 #define CONFIG_GENERIC_MMC
 315 #define CONFIG_CMD_FAT
 316 #define CONFIG_DOS_PARTITION
 317 #endif
 318
 319 #define CONFIG_MISC_INIT_R
 320
 321 /*
 322  * USB
 323  */
 324 #define CONFIG_HAS_FSL_XHCI_USB
 325 #define CONFIG_USB_XHCI
 326 #define CONFIG_USB_XHCI_FSL
 327 #define CONFIG_USB_XHCI_DWC3
 328 #define CONFIG_USB_MAX_CONTROLLER_COUNT         2
 329 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS      2
 330 #define CONFIG_CMD_USB
 331 #define CONFIG_USB_STORAGE
 332 #define CONFIG_CMD_EXT2
 333
 334 /* Initial environment variables */
 335 #undef CONFIG_EXTRA_ENV_SETTINGS
 336 #define CONFIG_EXTRA_ENV_SETTINGS               \
 337         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 338         "loadaddr=0x80100000\0"                 \
 339         "kernel_addr=0x100000\0"                \
 340         "ramdisk_addr=0x800000\0"               \
 341         "ramdisk_size=0x2000000\0"              \
 342         "fdt_high=0xa0000000\0"                 \
 343         "initrd_high=0xffffffffffffffff\0"      \
 344         "kernel_start=0x581100000\0"            \
 345         "kernel_load=0xa0000000\0"              \
 346         "kernel_size=0x2800000\0"               \
 347         "mcinitcmd=fsl_mc start mc 0x580300000" \
 348         " 0x580800000 \0"
 349
 350 #undef CONFIG_BOOTARGS
 351 #define CONFIG_BOOTARGS         "console=ttyS1,115200 root=/dev/ram0 " \
 352                                 "earlycon=uart8250,mmio,0x21c0600 " \
 353                                 "ramdisk_size=0x2000000 default_hugepagesz=2m" \
 354                                 " hugepagesz=2m hugepages=256"
 355
 356 /* MAC/PHY configuration */
 357 #ifdef CONFIG_FSL_MC_ENET
 358 #define CONFIG_PHYLIB_10G
 359 #define CONFIG_PHY_AQUANTIA
 360 #define CONFIG_PHY_CORTINA
 361 #define CONFIG_PHYLIB
 362 #define CONFIG_SYS_CORTINA_FW_IN_NOR
 363 #define CONFIG_CORTINA_FW_ADDR          0x581000000
 364 #define CONFIG_CORTINA_FW_LENGTH        0x40000
 365
 366 #define CORTINA_PHY_ADDR1       0x10
 367 #define CORTINA_PHY_ADDR2       0x11
 368 #define CORTINA_PHY_ADDR3       0x12
 369 #define CORTINA_PHY_ADDR4       0x13
 370 #define AQ_PHY_ADDR1            0x00
 371 #define AQ_PHY_ADDR2            0x01
 372 #define AQ_PHY_ADDR3            0x02
 373 #define AQ_PHY_ADDR4            0x03
 374 #define AQR405_IRQ_MASK         0x36
 375
 376 #define CONFIG_MII
 377 #define CONFIG_ETHPRIME         "DPNI1"
 378 #define CONFIG_PHY_GIGE
 379 #define CONFIG_PHY_AQUANTIA
 380 #endif
 381
 382 #include <asm/fsl_secure_boot.h>
 383
 384 #endif /* __LS2_RDB_H */