include/configs/ls1046aqds.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2016 Freescale Semiconductor, Inc.
   4  */
   5
   6 #ifndef __LS1046AQDS_H__
   7 #define __LS1046AQDS_H__
   8
   9 #include "ls1046a_common.h"
  10
  11 #ifndef __ASSEMBLY__
  12 unsigned long get_board_sys_clk(void);
  13 unsigned long get_board_ddr_clk(void);
  14 #endif
  15
  16 #define CONFIG_SYS_CLK_FREQ             get_board_sys_clk()
  17 #define CONFIG_DDR_CLK_FREQ             get_board_ddr_clk()
  18
  19 #define CONFIG_SKIP_LOWLEVEL_INIT
  20
  21 #define CONFIG_LAYERSCAPE_NS_ACCESS
  22
  23 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  24 /* Physical Memory Map */
  25 #define CONFIG_CHIP_SELECTS_PER_CTRL    4
  26
  27 #define CONFIG_DDR_SPD
  28 #define SPD_EEPROM_ADDRESS              0x51
  29 #define CONFIG_SYS_SPD_BUS_NUM          0
  30
  31 #define CONFIG_DDR_ECC
  32 #ifdef CONFIG_DDR_ECC
  33 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  34 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  35 #endif
  36
  37 /* DSPI */
  38 #ifdef CONFIG_FSL_DSPI
  39 #define CONFIG_SPI_FLASH_STMICRO        /* cs0 */
  40 #define CONFIG_SPI_FLASH_SST            /* cs1 */
  41 #define CONFIG_SPI_FLASH_EON            /* cs2 */
  42 #endif
  43
  44 /* QSPI */
  45 #if defined(CONFIG_TFABOOT) ||  \
  46         defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
  47 #ifdef CONFIG_FSL_QSPI
  48 #define CONFIG_SPI_FLASH_SPANSION
  49 #define FSL_QSPI_FLASH_SIZE             (1 << 24)
  50 #define FSL_QSPI_FLASH_NUM              2
  51 #endif
  52 #endif
  53
  54 #ifdef CONFIG_SYS_DPAA_FMAN
  55 #define RGMII_PHY1_ADDR         0x1
  56 #define RGMII_PHY2_ADDR         0x2
  57 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
  58 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
  59 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
  60 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
  61 /* PHY address on QSGMII riser card on slot 2 */
  62 #define QSGMII_CARD_PORT1_PHY_ADDR_S2 0x8
  63 #define QSGMII_CARD_PORT2_PHY_ADDR_S2 0x9
  64 #define QSGMII_CARD_PORT3_PHY_ADDR_S2 0xA
  65 #define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB
  66 #endif
  67
  68 #ifdef CONFIG_RAMBOOT_PBL
  69 #define CONFIG_SYS_FSL_PBL_PBI \
  70         board/freescale/ls1046aqds/ls1046aqds_pbi.cfg
  71 #endif
  72
  73 #ifdef CONFIG_NAND_BOOT
  74 #define CONFIG_SYS_FSL_PBL_RCW \
  75         board/freescale/ls1046aqds/ls1046aqds_rcw_nand.cfg
  76 #endif
  77
  78 #ifdef CONFIG_SD_BOOT
  79 #ifdef CONFIG_SD_BOOT_QSPI
  80 #define CONFIG_SYS_FSL_PBL_RCW \
  81         board/freescale/ls1046aqds/ls1046aqds_rcw_sd_qspi.cfg
  82 #else
  83 #define CONFIG_SYS_FSL_PBL_RCW \
  84         board/freescale/ls1046aqds/ls1046aqds_rcw_sd_ifc.cfg
  85 #endif
  86 #endif
  87
  88 /* IFC */
  89 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  90 #define CONFIG_FSL_IFC
  91 /*
  92  * CONFIG_SYS_FLASH_BASE has the final address (core view)
  93  * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
  94  * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
  95  * CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting
  96  */
  97 #define CONFIG_SYS_FLASH_BASE                   0x60000000
  98 #define CONFIG_SYS_FLASH_BASE_PHYS              CONFIG_SYS_FLASH_BASE
  99 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY        0x00000000
 100
 101 #ifdef CONFIG_MTD_NOR_FLASH
 102 #define CONFIG_SYS_FLASH_QUIET_TEST
 103 #define CONFIG_FLASH_SHOW_PROGRESS      45      /* count down from 45/5: 9..1 */
 104 #endif
 105 #endif
 106
 107 /* LPUART */
 108 #ifdef CONFIG_LPUART
 109 #define CONFIG_LPUART_32B_REG
 110 #define CFG_UART_MUX_MASK       0x6
 111 #define CFG_UART_MUX_SHIFT      1
 112 #define CFG_LPUART_EN           0x2
 113 #endif
 114
 115 /* EEPROM */
 116 #define CONFIG_ID_EEPROM
 117 #define CONFIG_SYS_I2C_EEPROM_NXID
 118 #define CONFIG_SYS_EEPROM_BUS_NUM               0
 119 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x57
 120 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          1
 121 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       3
 122 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   5
 123
 124 /*
 125  * IFC Definitions
 126  */
 127 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 128 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
 129 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 130                                 CSPR_PORT_SIZE_16 | \
 131                                 CSPR_MSEL_NOR | \
 132                                 CSPR_V)
 133 #define CONFIG_SYS_NOR1_CSPR_EXT        (0x0)
 134 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
 135                                 + 0x8000000) | \
 136                                 CSPR_PORT_SIZE_16 | \
 137                                 CSPR_MSEL_NOR | \
 138                                 CSPR_V)
 139 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128 * 1024 * 1024)
 140
 141 #define CONFIG_SYS_NOR_CSOR             (CSOR_NOR_ADM_SHIFT(4) | \
 142                                         CSOR_NOR_TRHZ_80)
 143 #define CONFIG_SYS_NOR_FTIM0            (FTIM0_NOR_TACSE(0x4) | \
 144                                         FTIM0_NOR_TEADC(0x5) | \
 145                                         FTIM0_NOR_TAVDS(0x6) | \
 146                                         FTIM0_NOR_TEAHC(0x5))
 147 #define CONFIG_SYS_NOR_FTIM1            (FTIM1_NOR_TACO(0x35) | \
 148                                         FTIM1_NOR_TRAD_NOR(0x1a) | \
 149                                         FTIM1_NOR_TSEQRAD_NOR(0x13))
 150 #define CONFIG_SYS_NOR_FTIM2            (FTIM2_NOR_TCS(0x8) | \
 151                                         FTIM2_NOR_TCH(0x8) | \
 152                                         FTIM2_NOR_TWPH(0xe) | \
 153                                         FTIM2_NOR_TWP(0x1c))
 154 #define CONFIG_SYS_NOR_FTIM3            0
 155
 156 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 157 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 158 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 159 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 160
 161 #define CONFIG_SYS_FLASH_EMPTY_INFO
 162 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS, \
 163                                         CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
 164
 165 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 166 #define CONFIG_SYS_WRITE_SWAPPED_DATA
 167
 168 /*
 169  * NAND Flash Definitions
 170  */
 171 #define CONFIG_NAND_FSL_IFC
 172
 173 #define CONFIG_SYS_NAND_BASE            0x7e800000
 174 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 175
 176 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
 177
 178 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 179                                 | CSPR_PORT_SIZE_8      \
 180                                 | CSPR_MSEL_NAND        \
 181                                 | CSPR_V)
 182 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 183 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 184                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 185                                 | CSOR_NAND_ECC_MODE_8  /* 8-bit ECC */ \
 186                                 | CSOR_NAND_RAL_3       /* RAL = 3 Bytes */ \
 187                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
 188                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
 189                                 | CSOR_NAND_PB(64))     /* 64 Pages Per Block */
 190
 191 #define CONFIG_SYS_NAND_ONFI_DETECTION
 192
 193 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x7) | \
 194                                         FTIM0_NAND_TWP(0x18)   | \
 195                                         FTIM0_NAND_TWCHT(0x7) | \
 196                                         FTIM0_NAND_TWH(0xa))
 197 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 198                                         FTIM1_NAND_TWBE(0x39)  | \
 199                                         FTIM1_NAND_TRR(0xe)   | \
 200                                         FTIM1_NAND_TRP(0x18))
 201 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0xf) | \
 202                                         FTIM2_NAND_TREH(0xa) | \
 203                                         FTIM2_NAND_TWHRE(0x1e))
 204 #define CONFIG_SYS_NAND_FTIM3           0x0
 205
 206 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 207 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 208 #define CONFIG_MTD_NAND_VERIFY_WRITE
 209
 210 #define CONFIG_SYS_NAND_BLOCK_SIZE      (256 * 1024)
 211 #endif
 212
 213 #ifdef CONFIG_NAND_BOOT
 214 #define CONFIG_SPL_PAD_TO               0x40000         /* block aligned */
 215 #define CONFIG_SYS_NAND_U_BOOT_OFFS     CONFIG_SPL_PAD_TO
 216 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
 217 #endif
 218
 219 #if defined(CONFIG_TFABOOT) || \
 220         defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 221 #define CONFIG_QIXIS_I2C_ACCESS
 222 #define CONFIG_SYS_I2C_EARLY_INIT
 223 #endif
 224
 225 /*
 226  * QIXIS Definitions
 227  */
 228 #define CONFIG_FSL_QIXIS
 229
 230 #ifdef CONFIG_FSL_QIXIS
 231 #define QIXIS_BASE                      0x7fb00000
 232 #define QIXIS_BASE_PHYS                 QIXIS_BASE
 233 #define CONFIG_SYS_I2C_FPGA_ADDR        0x66
 234 #define QIXIS_LBMAP_SWITCH              6
 235 #define QIXIS_LBMAP_MASK                0x0f
 236 #define QIXIS_LBMAP_SHIFT               0
 237 #define QIXIS_LBMAP_DFLTBANK            0x00
 238 #define QIXIS_LBMAP_ALTBANK             0x04
 239 #define QIXIS_LBMAP_NAND                0x09
 240 #define QIXIS_LBMAP_SD                  0x00
 241 #define QIXIS_LBMAP_SD_QSPI             0xff
 242 #define QIXIS_LBMAP_QSPI                0xff
 243 #define QIXIS_RCW_SRC_NAND              0x110
 244 #define QIXIS_RCW_SRC_SD                0x040
 245 #define QIXIS_RCW_SRC_QSPI              0x045
 246 #define QIXIS_RST_CTL_RESET             0x41
 247 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 248 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 249 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 250
 251 #define CONFIG_SYS_FPGA_CSPR_EXT        (0x0)
 252 #define CONFIG_SYS_FPGA_CSPR            (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
 253                                         CSPR_PORT_SIZE_8 | \
 254                                         CSPR_MSEL_GPCM | \
 255                                         CSPR_V)
 256 #define CONFIG_SYS_FPGA_AMASK           IFC_AMASK(64 * 1024)
 257 #define CONFIG_SYS_FPGA_CSOR            (CSOR_NOR_ADM_SHIFT(4) | \
 258                                         CSOR_NOR_NOR_MODE_AVD_NOR | \
 259                                         CSOR_NOR_TRHZ_80)
 260
 261 /*
 262  * QIXIS Timing parameters for IFC GPCM
 263  */
 264 #define CONFIG_SYS_FPGA_FTIM0           (FTIM0_GPCM_TACSE(0xc) | \
 265                                         FTIM0_GPCM_TEADC(0x20) | \
 266                                         FTIM0_GPCM_TEAHC(0x10))
 267 #define CONFIG_SYS_FPGA_FTIM1           (FTIM1_GPCM_TACO(0x50) | \
 268                                         FTIM1_GPCM_TRAD(0x1f))
 269 #define CONFIG_SYS_FPGA_FTIM2           (FTIM2_GPCM_TCS(0x8) | \
 270                                         FTIM2_GPCM_TCH(0x8) | \
 271                                         FTIM2_GPCM_TWP(0xf0))
 272 #define CONFIG_SYS_FPGA_FTIM3           0x0
 273 #endif
 274
 275 #ifdef CONFIG_TFABOOT
 276 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 277 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 278 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 279 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 280 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 281 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 282 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 283 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 284 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 285 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 286 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 287 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 288 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 289 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 290 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 291 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 292 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 293 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 294 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 295 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 296 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 297 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 298 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 299 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 300 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 301 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 302 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
 303 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 304 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
 305 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
 306 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
 307 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
 308 #else
 309 #ifdef CONFIG_NAND_BOOT
 310 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 311 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 312 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 313 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 314 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 315 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 316 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 317 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 318 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 319 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 320 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 321 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 322 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 323 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 324 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 325 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 326 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 327 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
 328 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 329 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 330 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 331 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 332 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 333 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 334 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 335 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 336 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
 337 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 338 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
 339 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
 340 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
 341 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
 342 #else
 343 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 344 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 345 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 346 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 347 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 348 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 349 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 350 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 351 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 352 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 353 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 354 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 355 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 356 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 357 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 358 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 359 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 360 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 361 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 362 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 363 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 364 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 365 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 366 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 367 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 368 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 369 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
 370 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 371 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
 372 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
 373 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
 374 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
 375 #endif
 376 #endif
 377
 378 /*
 379  * I2C bus multiplexer
 380  */
 381 #define I2C_MUX_PCA_ADDR_PRI            0x77
 382 #define I2C_MUX_PCA_ADDR_SEC            0x76 /* Secondary multiplexer */
 383 #define I2C_RETIMER_ADDR                0x18
 384 #define I2C_MUX_CH_DEFAULT              0x8
 385 #define I2C_MUX_CH_CH7301               0xC
 386 #define I2C_MUX_CH5                     0xD
 387 #define I2C_MUX_CH6                     0xE
 388 #define I2C_MUX_CH7                     0xF
 389
 390 #define I2C_MUX_CH_VOL_MONITOR 0xa
 391
 392 /* Voltage monitor on channel 2*/
 393 #define I2C_VOL_MONITOR_ADDR           0x40
 394 #define I2C_VOL_MONITOR_BUS_V_OFFSET   0x2
 395 #define I2C_VOL_MONITOR_BUS_V_OVF      0x1
 396 #define I2C_VOL_MONITOR_BUS_V_SHIFT    3
 397
 398 #define CONFIG_VID_FLS_ENV              "ls1046aqds_vdd_mv"
 399 #ifndef CONFIG_SPL_BUILD
 400 #define CONFIG_VID
 401 #endif
 402 #define CONFIG_VOL_MONITOR_IR36021_SET
 403 #define CONFIG_VOL_MONITOR_INA220
 404 /* The lowest and highest voltage allowed for LS1046AQDS */
 405 #define VDD_MV_MIN                      819
 406 #define VDD_MV_MAX                      1212
 407
 408 /*
 409  * Miscellaneous configurable options
 410  */
 411
 412 #define CONFIG_SYS_MEMTEST_START        0x80000000
 413 #define CONFIG_SYS_MEMTEST_END          0x9fffffff
 414
 415 #define CONFIG_SYS_HZ                   1000
 416
 417 #define CONFIG_SYS_INIT_SP_OFFSET \
 418         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 419
 420 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 421
 422 /*
 423  * Environment
 424  */
 425 #define CONFIG_ENV_OVERWRITE
 426
 427 #ifdef CONFIG_TFABOOT
 428 #define CONFIG_SYS_MMC_ENV_DEV          0
 429 #else
 430 #ifdef CONFIG_NAND_BOOT
 431 #elif defined(CONFIG_SD_BOOT)
 432 #define CONFIG_SYS_MMC_ENV_DEV          0
 433 #endif
 434 #endif
 435
 436 #define CONFIG_CMDLINE_TAG
 437
 438 #undef CONFIG_BOOTCOMMAND
 439 #ifdef CONFIG_TFABOOT
 440 #define IFC_NAND_BOOTCOMMAND "run distro_bootcmd; run nand_bootcmd; "   \
 441                            "env exists secureboot && esbc_halt;;"
 442 #define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd"      \
 443                            "env exists secureboot && esbc_halt;;"
 444 #define IFC_NOR_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; "     \
 445                            "env exists secureboot && esbc_halt;;"
 446 #define SD_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; "   \
 447                            "env exists secureboot && esbc_halt;;"
 448 #else
 449 #if defined(CONFIG_QSPI_BOOT)
 450 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; "      \
 451                            "env exists secureboot && esbc_halt;;"
 452 #elif defined(CONFIG_NAND_BOOT)
 453 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run nand_bootcmd; "     \
 454                            "env exists secureboot && esbc_halt;;"
 455 #elif defined(CONFIG_SD_BOOT)
 456 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; "       \
 457                            "env exists secureboot && esbc_halt;;"
 458 #else
 459 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; "      \
 460                            "env exists secureboot && esbc_halt;;"
 461 #endif
 462 #endif
 463
 464 #include <asm/fsl_secure_boot.h>
 465
 466 #endif /* __LS1046AQDS_H__ */