include/configs/ls1046aqds.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2016 Freescale Semiconductor, Inc.
   4  */
   5
   6 #ifndef __LS1046AQDS_H__
   7 #define __LS1046AQDS_H__
   8
   9 #include "ls1046a_common.h"
  10
  11 #ifndef __ASSEMBLY__
  12 unsigned long get_board_sys_clk(void);
  13 unsigned long get_board_ddr_clk(void);
  14 #endif
  15
  16 #define CONFIG_SYS_CLK_FREQ             get_board_sys_clk()
  17 #define CONFIG_DDR_CLK_FREQ             get_board_ddr_clk()
  18
  19 #define CONFIG_SKIP_LOWLEVEL_INIT
  20
  21 #define CONFIG_LAYERSCAPE_NS_ACCESS
  22
  23 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  24 /* Physical Memory Map */
  25 #define CONFIG_CHIP_SELECTS_PER_CTRL    4
  26
  27 #define CONFIG_DDR_SPD
  28 #define SPD_EEPROM_ADDRESS              0x51
  29 #define CONFIG_SYS_SPD_BUS_NUM          0
  30
  31 #define CONFIG_DDR_ECC
  32 #ifdef CONFIG_DDR_ECC
  33 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  34 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  35 #endif
  36
  37 /* DSPI */
  38 #ifdef CONFIG_FSL_DSPI
  39 #define CONFIG_SPI_FLASH_STMICRO        /* cs0 */
  40 #define CONFIG_SPI_FLASH_SST            /* cs1 */
  41 #define CONFIG_SPI_FLASH_EON            /* cs2 */
  42 #endif
  43
  44 /* QSPI */
  45 #if defined(CONFIG_TFABOOT) ||  \
  46         defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
  47 #ifdef CONFIG_FSL_QSPI
  48 #define CONFIG_SPI_FLASH_SPANSION
  49 #define FSL_QSPI_FLASH_SIZE             (1 << 24)
  50 #define FSL_QSPI_FLASH_NUM              2
  51 #endif
  52 #endif
  53
  54 #ifdef CONFIG_SYS_DPAA_FMAN
  55 #define CONFIG_FMAN_ENET
  56 #define CONFIG_PHY_VITESSE
  57 #define CONFIG_PHY_REALTEK
  58 #define CONFIG_PHYLIB_10G
  59 #define RGMII_PHY1_ADDR         0x1
  60 #define RGMII_PHY2_ADDR         0x2
  61 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
  62 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
  63 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
  64 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
  65 /* PHY address on QSGMII riser card on slot 2 */
  66 #define QSGMII_CARD_PORT1_PHY_ADDR_S2 0x8
  67 #define QSGMII_CARD_PORT2_PHY_ADDR_S2 0x9
  68 #define QSGMII_CARD_PORT3_PHY_ADDR_S2 0xA
  69 #define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB
  70 #endif
  71
  72 #ifdef CONFIG_RAMBOOT_PBL
  73 #define CONFIG_SYS_FSL_PBL_PBI \
  74         board/freescale/ls1046aqds/ls1046aqds_pbi.cfg
  75 #endif
  76
  77 #ifdef CONFIG_NAND_BOOT
  78 #define CONFIG_SYS_FSL_PBL_RCW \
  79         board/freescale/ls1046aqds/ls1046aqds_rcw_nand.cfg
  80 #endif
  81
  82 #ifdef CONFIG_SD_BOOT
  83 #ifdef CONFIG_SD_BOOT_QSPI
  84 #define CONFIG_SYS_FSL_PBL_RCW \
  85         board/freescale/ls1046aqds/ls1046aqds_rcw_sd_qspi.cfg
  86 #else
  87 #define CONFIG_SYS_FSL_PBL_RCW \
  88         board/freescale/ls1046aqds/ls1046aqds_rcw_sd_ifc.cfg
  89 #endif
  90 #endif
  91
  92 /* IFC */
  93 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  94 #define CONFIG_FSL_IFC
  95 /*
  96  * CONFIG_SYS_FLASH_BASE has the final address (core view)
  97  * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
  98  * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
  99  * CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting
 100  */
 101 #define CONFIG_SYS_FLASH_BASE                   0x60000000
 102 #define CONFIG_SYS_FLASH_BASE_PHYS              CONFIG_SYS_FLASH_BASE
 103 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY        0x00000000
 104
 105 #ifdef CONFIG_MTD_NOR_FLASH
 106 #define CONFIG_SYS_FLASH_QUIET_TEST
 107 #define CONFIG_FLASH_SHOW_PROGRESS      45      /* count down from 45/5: 9..1 */
 108 #endif
 109 #endif
 110
 111 /* LPUART */
 112 #ifdef CONFIG_LPUART
 113 #define CONFIG_LPUART_32B_REG
 114 #define CFG_UART_MUX_MASK       0x6
 115 #define CFG_UART_MUX_SHIFT      1
 116 #define CFG_LPUART_EN           0x2
 117 #endif
 118
 119 /* EEPROM */
 120 #define CONFIG_ID_EEPROM
 121 #define CONFIG_SYS_I2C_EEPROM_NXID
 122 #define CONFIG_SYS_EEPROM_BUS_NUM               0
 123 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x57
 124 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          1
 125 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       3
 126 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   5
 127
 128 /*
 129  * IFC Definitions
 130  */
 131 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 132 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
 133 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 134                                 CSPR_PORT_SIZE_16 | \
 135                                 CSPR_MSEL_NOR | \
 136                                 CSPR_V)
 137 #define CONFIG_SYS_NOR1_CSPR_EXT        (0x0)
 138 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
 139                                 + 0x8000000) | \
 140                                 CSPR_PORT_SIZE_16 | \
 141                                 CSPR_MSEL_NOR | \
 142                                 CSPR_V)
 143 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128 * 1024 * 1024)
 144
 145 #define CONFIG_SYS_NOR_CSOR             (CSOR_NOR_ADM_SHIFT(4) | \
 146                                         CSOR_NOR_TRHZ_80)
 147 #define CONFIG_SYS_NOR_FTIM0            (FTIM0_NOR_TACSE(0x4) | \
 148                                         FTIM0_NOR_TEADC(0x5) | \
 149                                         FTIM0_NOR_TAVDS(0x6) | \
 150                                         FTIM0_NOR_TEAHC(0x5))
 151 #define CONFIG_SYS_NOR_FTIM1            (FTIM1_NOR_TACO(0x35) | \
 152                                         FTIM1_NOR_TRAD_NOR(0x1a) | \
 153                                         FTIM1_NOR_TSEQRAD_NOR(0x13))
 154 #define CONFIG_SYS_NOR_FTIM2            (FTIM2_NOR_TCS(0x8) | \
 155                                         FTIM2_NOR_TCH(0x8) | \
 156                                         FTIM2_NOR_TWPH(0xe) | \
 157                                         FTIM2_NOR_TWP(0x1c))
 158 #define CONFIG_SYS_NOR_FTIM3            0
 159
 160 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 161 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 162 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 163 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 164
 165 #define CONFIG_SYS_FLASH_EMPTY_INFO
 166 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS, \
 167                                         CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
 168
 169 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 170 #define CONFIG_SYS_WRITE_SWAPPED_DATA
 171
 172 /*
 173  * NAND Flash Definitions
 174  */
 175 #define CONFIG_NAND_FSL_IFC
 176
 177 #define CONFIG_SYS_NAND_BASE            0x7e800000
 178 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 179
 180 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
 181
 182 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 183                                 | CSPR_PORT_SIZE_8      \
 184                                 | CSPR_MSEL_NAND        \
 185                                 | CSPR_V)
 186 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 187 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 188                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 189                                 | CSOR_NAND_ECC_MODE_8  /* 8-bit ECC */ \
 190                                 | CSOR_NAND_RAL_3       /* RAL = 3 Bytes */ \
 191                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
 192                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
 193                                 | CSOR_NAND_PB(64))     /* 64 Pages Per Block */
 194
 195 #define CONFIG_SYS_NAND_ONFI_DETECTION
 196
 197 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x7) | \
 198                                         FTIM0_NAND_TWP(0x18)   | \
 199                                         FTIM0_NAND_TWCHT(0x7) | \
 200                                         FTIM0_NAND_TWH(0xa))
 201 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 202                                         FTIM1_NAND_TWBE(0x39)  | \
 203                                         FTIM1_NAND_TRR(0xe)   | \
 204                                         FTIM1_NAND_TRP(0x18))
 205 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0xf) | \
 206                                         FTIM2_NAND_TREH(0xa) | \
 207                                         FTIM2_NAND_TWHRE(0x1e))
 208 #define CONFIG_SYS_NAND_FTIM3           0x0
 209
 210 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 211 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 212 #define CONFIG_MTD_NAND_VERIFY_WRITE
 213
 214 #define CONFIG_SYS_NAND_BLOCK_SIZE      (256 * 1024)
 215 #endif
 216
 217 #ifdef CONFIG_NAND_BOOT
 218 #define CONFIG_SPL_PAD_TO               0x40000         /* block aligned */
 219 #define CONFIG_SYS_NAND_U_BOOT_OFFS     CONFIG_SPL_PAD_TO
 220 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
 221 #endif
 222
 223 #if defined(CONFIG_TFABOOT) || \
 224         defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 225 #define CONFIG_QIXIS_I2C_ACCESS
 226 #define CONFIG_SYS_I2C_EARLY_INIT
 227 #endif
 228
 229 /*
 230  * QIXIS Definitions
 231  */
 232 #define CONFIG_FSL_QIXIS
 233
 234 #ifdef CONFIG_FSL_QIXIS
 235 #define QIXIS_BASE                      0x7fb00000
 236 #define QIXIS_BASE_PHYS                 QIXIS_BASE
 237 #define CONFIG_SYS_I2C_FPGA_ADDR        0x66
 238 #define QIXIS_LBMAP_SWITCH              6
 239 #define QIXIS_LBMAP_MASK                0x0f
 240 #define QIXIS_LBMAP_SHIFT               0
 241 #define QIXIS_LBMAP_DFLTBANK            0x00
 242 #define QIXIS_LBMAP_ALTBANK             0x04
 243 #define QIXIS_LBMAP_NAND                0x09
 244 #define QIXIS_LBMAP_SD                  0x00
 245 #define QIXIS_LBMAP_SD_QSPI             0xff
 246 #define QIXIS_LBMAP_QSPI                0xff
 247 #define QIXIS_RCW_SRC_NAND              0x110
 248 #define QIXIS_RCW_SRC_SD                0x040
 249 #define QIXIS_RCW_SRC_QSPI              0x045
 250 #define QIXIS_RST_CTL_RESET             0x41
 251 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 252 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 253 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 254
 255 #define CONFIG_SYS_FPGA_CSPR_EXT        (0x0)
 256 #define CONFIG_SYS_FPGA_CSPR            (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
 257                                         CSPR_PORT_SIZE_8 | \
 258                                         CSPR_MSEL_GPCM | \
 259                                         CSPR_V)
 260 #define CONFIG_SYS_FPGA_AMASK           IFC_AMASK(64 * 1024)
 261 #define CONFIG_SYS_FPGA_CSOR            (CSOR_NOR_ADM_SHIFT(4) | \
 262                                         CSOR_NOR_NOR_MODE_AVD_NOR | \
 263                                         CSOR_NOR_TRHZ_80)
 264
 265 /*
 266  * QIXIS Timing parameters for IFC GPCM
 267  */
 268 #define CONFIG_SYS_FPGA_FTIM0           (FTIM0_GPCM_TACSE(0xc) | \
 269                                         FTIM0_GPCM_TEADC(0x20) | \
 270                                         FTIM0_GPCM_TEAHC(0x10))
 271 #define CONFIG_SYS_FPGA_FTIM1           (FTIM1_GPCM_TACO(0x50) | \
 272                                         FTIM1_GPCM_TRAD(0x1f))
 273 #define CONFIG_SYS_FPGA_FTIM2           (FTIM2_GPCM_TCS(0x8) | \
 274                                         FTIM2_GPCM_TCH(0x8) | \
 275                                         FTIM2_GPCM_TWP(0xf0))
 276 #define CONFIG_SYS_FPGA_FTIM3           0x0
 277 #endif
 278
 279 #ifdef CONFIG_TFABOOT
 280 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 281 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 282 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 283 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 284 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 285 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 286 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 287 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 288 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 289 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 290 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 291 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 292 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 293 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 294 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 295 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 296 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 297 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 298 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 299 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 300 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 301 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 302 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 303 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 304 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 305 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 306 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
 307 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 308 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
 309 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
 310 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
 311 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
 312 #else
 313 #ifdef CONFIG_NAND_BOOT
 314 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 315 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 316 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 317 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 318 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 319 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 320 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 321 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 322 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 323 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 324 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 325 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 326 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 327 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 328 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 329 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 330 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 331 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
 332 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 333 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 334 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 335 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 336 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 337 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 338 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 339 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 340 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
 341 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 342 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
 343 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
 344 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
 345 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
 346 #else
 347 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 348 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 349 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 350 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 351 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 352 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 353 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 354 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 355 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 356 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 357 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 358 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 359 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 360 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 361 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 362 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 363 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 364 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 365 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 366 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 367 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 368 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 369 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 370 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 371 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 372 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 373 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
 374 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 375 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
 376 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
 377 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
 378 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
 379 #endif
 380 #endif
 381
 382 /*
 383  * I2C bus multiplexer
 384  */
 385 #define I2C_MUX_PCA_ADDR_PRI            0x77
 386 #define I2C_MUX_PCA_ADDR_SEC            0x76 /* Secondary multiplexer */
 387 #define I2C_RETIMER_ADDR                0x18
 388 #define I2C_MUX_CH_DEFAULT              0x8
 389 #define I2C_MUX_CH_CH7301               0xC
 390 #define I2C_MUX_CH5                     0xD
 391 #define I2C_MUX_CH6                     0xE
 392 #define I2C_MUX_CH7                     0xF
 393
 394 #define I2C_MUX_CH_VOL_MONITOR 0xa
 395
 396 /* Voltage monitor on channel 2*/
 397 #define I2C_VOL_MONITOR_ADDR           0x40
 398 #define I2C_VOL_MONITOR_BUS_V_OFFSET   0x2
 399 #define I2C_VOL_MONITOR_BUS_V_OVF      0x1
 400 #define I2C_VOL_MONITOR_BUS_V_SHIFT    3
 401
 402 #define CONFIG_VID_FLS_ENV              "ls1046aqds_vdd_mv"
 403 #ifndef CONFIG_SPL_BUILD
 404 #define CONFIG_VID
 405 #endif
 406 #define CONFIG_VOL_MONITOR_IR36021_SET
 407 #define CONFIG_VOL_MONITOR_INA220
 408 /* The lowest and highest voltage allowed for LS1046AQDS */
 409 #define VDD_MV_MIN                      819
 410 #define VDD_MV_MAX                      1212
 411
 412 /*
 413  * Miscellaneous configurable options
 414  */
 415
 416 #define CONFIG_SYS_MEMTEST_START        0x80000000
 417 #define CONFIG_SYS_MEMTEST_END          0x9fffffff
 418
 419 #define CONFIG_SYS_HZ                   1000
 420
 421 #define CONFIG_SYS_INIT_SP_OFFSET \
 422         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 423
 424 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 425
 426 /*
 427  * Environment
 428  */
 429 #define CONFIG_ENV_OVERWRITE
 430
 431 #ifdef CONFIG_TFABOOT
 432 #define CONFIG_SYS_MMC_ENV_DEV          0
 433
 434 #define CONFIG_ENV_SIZE                 0x2000
 435 #define CONFIG_ENV_OFFSET               0x500000        /* 5MB */
 436 #define CONFIG_ENV_ADDR                 (CONFIG_SYS_FLASH_BASE + 0x500000)
 437 #define CONFIG_ENV_SECT_SIZE            0x20000
 438 #else
 439 #ifdef CONFIG_NAND_BOOT
 440 #define CONFIG_ENV_SIZE                 0x2000
 441 #define CONFIG_ENV_OFFSET               (12 * CONFIG_SYS_NAND_BLOCK_SIZE)
 442 #elif defined(CONFIG_SD_BOOT)
 443 #define CONFIG_ENV_OFFSET               (3 * 1024 * 1024)
 444 #define CONFIG_SYS_MMC_ENV_DEV          0
 445 #define CONFIG_ENV_SIZE                 0x2000
 446 #elif defined(CONFIG_QSPI_BOOT)
 447 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
 448 #define CONFIG_ENV_OFFSET               0x300000        /* 3MB */
 449 #define CONFIG_ENV_SECT_SIZE            0x10000
 450 #else
 451 #define CONFIG_ENV_ADDR                 (CONFIG_SYS_FLASH_BASE + 0x300000)
 452 #define CONFIG_ENV_SECT_SIZE            0x20000
 453 #define CONFIG_ENV_SIZE                 0x20000
 454 #endif
 455 #endif
 456
 457 #define CONFIG_CMDLINE_TAG
 458
 459 #undef CONFIG_BOOTCOMMAND
 460 #ifdef CONFIG_TFABOOT
 461 #define QSPI_NOR_BOOTCOMMAND            "sf probe && sf read $kernel_load "    \
 462                                         "e0000 f00000 && bootm $kernel_load"
 463 #define IFC_NOR_BOOTCOMMAND             "cp.b $kernel_start $kernel_load "     \
 464                                         "$kernel_size && bootm $kernel_load"
 465 #define SD_BOOTCOMMAND          "mmc info; mmc read $kernel_load"     \
 466                                         "$kernel_addr_sd $kernel_size_sd && bootm $kernel_load"
 467 #else
 468 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 469 #define CONFIG_BOOTCOMMAND              "sf probe && sf read $kernel_load "    \
 470                                         "e0000 f00000 && bootm $kernel_load"
 471 #else
 472 #define CONFIG_BOOTCOMMAND              "cp.b $kernel_start $kernel_load "     \
 473                                         "$kernel_size && bootm $kernel_load"
 474 #endif
 475 #endif
 476
 477 #include <asm/fsl_secure_boot.h>
 478
 479 #endif /* __LS1046AQDS_H__ */