include/configs/ls1043a_common.h

   1 /*
   2  * Copyright (C) 2015 Freescale Semiconductor
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef __LS1043A_COMMON_H
   8 #define __LS1043A_COMMON_H
   9
  10 #define CONFIG_REMAKE_ELF
  11 #define CONFIG_FSL_LAYERSCAPE
  12 #define CONFIG_FSL_LSCH2
  13 #define CONFIG_LS1043A
  14 #define CONFIG_SYS_FSL_CLK
  15 #define CONFIG_GICV2
  16
  17 #include <asm/arch/config.h>
  18 #ifdef CONFIG_SYS_FSL_SRDS_1
  19 #define CONFIG_SYS_HAS_SERDES
  20 #endif
  21
  22 /* Link Definitions */
  23 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
  24
  25 #define CONFIG_SUPPORT_RAW_INITRD
  26
  27 #define CONFIG_SKIP_LOWLEVEL_INIT
  28 #define CONFIG_BOARD_EARLY_INIT_F       1
  29
  30 /* Flat Device Tree Definitions */
  31 #define CONFIG_OF_LIBFDT
  32 #define CONFIG_OF_BOARD_SETUP
  33
  34 /* new uImage format support */
  35 #define CONFIG_FIT
  36 #define CONFIG_FIT_VERBOSE      /* enable fit_format_{error,warning}() */
  37
  38 #ifndef CONFIG_SYS_FSL_DDR4
  39 #define CONFIG_SYS_FSL_DDR3             /* Use DDR3 memory */
  40 #endif
  41
  42 #define CONFIG_VERY_BIG_RAM
  43 #define CONFIG_SYS_DDR_SDRAM_BASE       0x80000000
  44 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY       0
  45 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  46
  47 /* Generic Timer Definitions */
  48 #define COUNTER_FREQUENCY               25000000        /* 25MHz */
  49
  50 /* Size of malloc() pool */
  51 #define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + 1024 * 1024)
  52
  53 /* Serial Port */
  54 #define CONFIG_CONS_INDEX               1
  55 #define CONFIG_SYS_NS16550
  56 #define CONFIG_SYS_NS16550_SERIAL
  57 #define CONFIG_SYS_NS16550_REG_SIZE     1
  58 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0))
  59
  60 #define CONFIG_BAUDRATE                 115200
  61 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200 }
  62
  63 /* NAND SPL */
  64 #ifdef CONFIG_NAND_BOOT
  65 #define CONFIG_SPL_PBL_PAD
  66 #define CONFIG_SPL_FRAMEWORK
  67 #define CONFIG_SPL_LDSCRIPT             "arch/arm/cpu/armv8/u-boot-spl.lds"
  68 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  69 #define CONFIG_SPL_LIBCOMMON_SUPPORT
  70 #define CONFIG_SPL_LIBGENERIC_SUPPORT
  71 #define CONFIG_SPL_ENV_SUPPORT
  72 #define CONFIG_SPL_WATCHDOG_SUPPORT
  73 #define CONFIG_SPL_I2C_SUPPORT
  74 #define CONFIG_SPL_SERIAL_SUPPORT
  75 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
  76 #define CONFIG_SPL_NAND_SUPPORT
  77 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
  78 #define CONFIG_SPL_TEXT_BASE            0x10000000
  79 #define CONFIG_SPL_MAX_SIZE             0x1a000
  80 #define CONFIG_SPL_STACK                0x1001d000
  81 #define CONFIG_SYS_NAND_U_BOOT_DST      CONFIG_SYS_TEXT_BASE
  82 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_TEXT_BASE
  83 #define CONFIG_SYS_SPL_MALLOC_START     0x80200000
  84 #define CONFIG_SPL_BSS_START_ADDR       0x80100000
  85 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
  86 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000
  87 #define CONFIG_SYS_MONITOR_LEN          0xa0000
  88 #endif
  89
  90 /* IFC */
  91 #define CONFIG_FSL_IFC
  92 /*
  93  * CONFIG_SYS_FLASH_BASE has the final address (core view)
  94  * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
  95  * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
  96  * CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting
  97  */
  98 #define CONFIG_SYS_FLASH_BASE                   0x60000000
  99 #define CONFIG_SYS_FLASH_BASE_PHYS              CONFIG_SYS_FLASH_BASE
 100 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY        0x00000000
 101
 102 #ifndef CONFIG_SYS_NO_FLASH
 103 #define CONFIG_FLASH_CFI_DRIVER
 104 #define CONFIG_SYS_FLASH_CFI
 105 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 106 #define CONFIG_SYS_FLASH_QUIET_TEST
 107 #define CONFIG_FLASH_SHOW_PROGRESS      45      /* count down from 45/5: 9..1 */
 108 #endif
 109
 110 /* I2C */
 111 #define CONFIG_CMD_I2C
 112 #define CONFIG_SYS_I2C
 113 #define CONFIG_SYS_I2C_MXC
 114 #define CONFIG_SYS_I2C_MXC_I2C1
 115 #define CONFIG_SYS_I2C_MXC_I2C2
 116 #define CONFIG_SYS_I2C_MXC_I2C3
 117 #define CONFIG_SYS_I2C_MXC_I2C4
 118
 119 /* PCIe */
 120 #define CONFIG_PCI              /* Enable PCI/PCIE */
 121 #define CONFIG_PCIE1            /* PCIE controller 1 */
 122 #define CONFIG_PCIE2            /* PCIE controller 2 */
 123 #define CONFIG_PCIE3            /* PCIE controller 3 */
 124 #define CONFIG_PCIE_LAYERSCAPE  /* Use common FSL Layerscape PCIe code */
 125 #define FSL_PCIE_COMPAT "fsl,ls1043a-pcie"
 126
 127 #define CONFIG_SYS_PCI_64BIT
 128
 129 #define CONFIG_SYS_PCIE_CFG0_PHYS_OFF   0x00000000
 130 #define CONFIG_SYS_PCIE_CFG0_SIZE       0x00001000      /* 4k */
 131 #define CONFIG_SYS_PCIE_CFG1_PHYS_OFF   0x00001000
 132 #define CONFIG_SYS_PCIE_CFG1_SIZE       0x00001000      /* 4k */
 133
 134 #define CONFIG_SYS_PCIE_IO_BUS          0x00000000
 135 #define CONFIG_SYS_PCIE_IO_PHYS_OFF     0x00010000
 136 #define CONFIG_SYS_PCIE_IO_SIZE         0x00010000      /* 64k */
 137
 138 #define CONFIG_SYS_PCIE_MEM_BUS         0x40000000
 139 #define CONFIG_SYS_PCIE_MEM_PHYS_OFF    0x40000000
 140 #define CONFIG_SYS_PCIE_MEM_SIZE        0x40000000      /* 1G */
 141
 142 #ifdef CONFIG_PCI
 143 #define CONFIG_NET_MULTI
 144 #define CONFIG_PCI_PNP
 145 #define CONFIG_E1000
 146 #define CONFIG_PCI_SCAN_SHOW
 147 #define CONFIG_CMD_PCI
 148 #endif
 149
 150 /* Command line configuration */
 151 #define CONFIG_CMD_CACHE
 152 #define CONFIG_CMD_DHCP
 153 #define CONFIG_CMD_ENV
 154 #define CONFIG_CMD_PING
 155
 156 /*  MMC  */
 157 #define CONFIG_MMC
 158 #ifdef CONFIG_MMC
 159 #define CONFIG_CMD_MMC
 160 #define CONFIG_CMD_FAT
 161 #define CONFIG_FSL_ESDHC
 162 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
 163 #define CONFIG_GENERIC_MMC
 164 #define CONFIG_DOS_PARTITION
 165 #endif
 166
 167 /* FMan ucode */
 168 #define CONFIG_SYS_DPAA_FMAN
 169 #ifdef CONFIG_SYS_DPAA_FMAN
 170 #define CONFIG_SYS_FM_MURAM_SIZE        0x60000
 171
 172 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 173 /* FMan fireware Pre-load address */
 174 #define CONFIG_SYS_FMAN_FW_ADDR         0x60300000
 175 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 176 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 177 #endif
 178
 179 /* Miscellaneous configurable options */
 180 #define CONFIG_SYS_LOAD_ADDR    (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
 181 #define CONFIG_ARCH_EARLY_INIT_R
 182 #define CONFIG_BOARD_LATE_INIT
 183
 184 #define CONFIG_HWCONFIG
 185 #define HWCONFIG_BUFFER_SIZE            128
 186
 187 /* Initial environment variables */
 188 #define CONFIG_EXTRA_ENV_SETTINGS               \
 189         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 190         "loadaddr=0x80100000\0"                 \
 191         "kernel_addr=0x100000\0"                \
 192         "ramdisk_addr=0x800000\0"               \
 193         "ramdisk_size=0x2000000\0"              \
 194         "fdt_high=0xffffffffffffffff\0"         \
 195         "initrd_high=0xffffffffffffffff\0"      \
 196         "kernel_start=0x61200000\0"             \
 197         "kernel_load=0x807f0000\0"              \
 198         "kernel_size=0x1000000\0"               \
 199         "console=ttyAMA0,38400n8\0"
 200
 201 #define CONFIG_BOOTARGS                 "console=ttyS0,115200 root=/dev/ram0 " \
 202                                         "earlycon=uart8250,0x21c0500,115200"
 203 #define CONFIG_BOOTCOMMAND              "cp.b $kernel_start $kernel_load "     \
 204                                         "$kernel_size && bootm $kernel_load"
 205 #define CONFIG_BOOTDELAY                10
 206
 207 /* Monitor Command Prompt */
 208 #define CONFIG_SYS_CBSIZE               512     /* Console I/O Buffer Size */
 209 #define CONFIG_SYS_PROMPT               "=> "
 210 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + \
 211                                         sizeof(CONFIG_SYS_PROMPT) + 16)
 212 #define CONFIG_SYS_HUSH_PARSER
 213 #define CONFIG_SYS_PROMPT_HUSH_PS2      "> "
 214 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE /* Boot args buffer */
 215 #define CONFIG_SYS_LONGHELP
 216 #define CONFIG_CMDLINE_EDITING          1
 217 #define CONFIG_AUTO_COMPLETE
 218 #define CONFIG_SYS_MAXARGS              64      /* max command args */
 219
 220 #define CONFIG_SYS_BOOTM_LEN   (64 << 20)      /* Increase max gunzip size */
 221
 222 #endif /* __LS1043A_COMMON_H */