include/configs/ls1021atwr.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  * Copyright 2019 NXP
   5  */
   6
   7 #ifndef __CONFIG_H
   8 #define __CONFIG_H
   9
  10 #define CONFIG_ARMV7_PSCI_1_0
  11
  12 #define CONFIG_ARMV7_SECURE_BASE        OCRAM_BASE_S_ADDR
  13
  14 #define CONFIG_SYS_FSL_CLK
  15
  16 #define CONFIG_SKIP_LOWLEVEL_INIT
  17 #define CONFIG_DEEP_SLEEP
  18
  19 /*
  20  * Size of malloc() pool
  21  */
  22 #define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
  23
  24 #define CONFIG_SYS_INIT_RAM_ADDR        OCRAM_BASE_ADDR
  25 #define CONFIG_SYS_INIT_RAM_SIZE        OCRAM_SIZE
  26
  27 #define CONFIG_SYS_CLK_FREQ             100000000
  28 #define CONFIG_DDR_CLK_FREQ             100000000
  29
  30 #define DDR_SDRAM_CFG                   0x470c0008
  31 #define DDR_CS0_BNDS                    0x008000bf
  32 #define DDR_CS0_CONFIG                  0x80014302
  33 #define DDR_TIMING_CFG_0                0x50550004
  34 #define DDR_TIMING_CFG_1                0xbcb38c56
  35 #define DDR_TIMING_CFG_2                0x0040d120
  36 #define DDR_TIMING_CFG_3                0x010e1000
  37 #define DDR_TIMING_CFG_4                0x00000001
  38 #define DDR_TIMING_CFG_5                0x03401400
  39 #define DDR_SDRAM_CFG_2                 0x00401010
  40 #define DDR_SDRAM_MODE                  0x00061c60
  41 #define DDR_SDRAM_MODE_2                0x00180000
  42 #define DDR_SDRAM_INTERVAL              0x18600618
  43 #define DDR_DDR_WRLVL_CNTL              0x8655f605
  44 #define DDR_DDR_WRLVL_CNTL_2            0x05060607
  45 #define DDR_DDR_WRLVL_CNTL_3            0x05050505
  46 #define DDR_DDR_CDR1                    0x80040000
  47 #define DDR_DDR_CDR2                    0x00000001
  48 #define DDR_SDRAM_CLK_CNTL              0x02000000
  49 #define DDR_DDR_ZQ_CNTL                 0x89080600
  50 #define DDR_CS0_CONFIG_2                0
  51 #define DDR_SDRAM_CFG_MEM_EN            0x80000000
  52 #define SDRAM_CFG2_D_INIT               0x00000010
  53 #define DDR_CDR2_VREF_TRAIN_EN          0x00000080
  54 #define SDRAM_CFG2_FRC_SR               0x80000000
  55 #define SDRAM_CFG_BI                    0x00000001
  56
  57 #ifdef CONFIG_RAMBOOT_PBL
  58 #define CONFIG_SYS_FSL_PBL_PBI  board/freescale/ls1021atwr/ls102xa_pbi.cfg
  59 #endif
  60
  61 #ifdef CONFIG_SD_BOOT
  62 #ifdef CONFIG_SD_BOOT_QSPI
  63 #define CONFIG_SYS_FSL_PBL_RCW  \
  64         board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg
  65 #else
  66 #define CONFIG_SYS_FSL_PBL_RCW  \
  67         board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg
  68 #endif
  69
  70 #ifdef CONFIG_NXP_ESBC
  71 /*
  72  * HDR would be appended at end of image and copied to DDR along
  73  * with U-Boot image.
  74  */
  75 #define CONFIG_U_BOOT_HDR_SIZE                          (16 << 10)
  76 #endif /* ifdef CONFIG_NXP_ESBC */
  77
  78 #define CONFIG_SPL_MAX_SIZE             0x1a000
  79 #define CONFIG_SPL_STACK                0x1001d000
  80 #define CONFIG_SPL_PAD_TO               0x1c000
  81
  82 #define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SYS_TEXT_BASE + \
  83                 CONFIG_SYS_MONITOR_LEN)
  84 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
  85 #define CONFIG_SPL_BSS_START_ADDR       0x80100000
  86 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000
  87
  88 #ifdef CONFIG_U_BOOT_HDR_SIZE
  89 /*
  90  * HDR would be appended at end of image and copied to DDR along
  91  * with U-Boot image. Here u-boot max. size is 512K. So if binary
  92  * size increases then increase this size in case of secure boot as
  93  * it uses raw u-boot image instead of fit image.
  94  */
  95 #define CONFIG_SYS_MONITOR_LEN          (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
  96 #else
  97 #define CONFIG_SYS_MONITOR_LEN          0x100000
  98 #endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */
  99 #endif
 100
 101 #define PHYS_SDRAM                      0x80000000
 102 #define PHYS_SDRAM_SIZE                 (1u * 1024 * 1024 * 1024)
 103
 104 #define CONFIG_SYS_DDR_SDRAM_BASE      0x80000000UL
 105 #define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_SDRAM_BASE
 106
 107 #define CONFIG_CHIP_SELECTS_PER_CTRL    4
 108
 109 /*
 110  * IFC Definitions
 111  */
 112 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 113 #define CONFIG_FSL_IFC
 114 #define CONFIG_SYS_FLASH_BASE           0x60000000
 115 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 116
 117 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
 118 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 119                                 CSPR_PORT_SIZE_16 | \
 120                                 CSPR_MSEL_NOR | \
 121                                 CSPR_V)
 122 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128 * 1024 * 1024)
 123
 124 /* NOR Flash Timing Params */
 125 #define CONFIG_SYS_NOR_CSOR             (CSOR_NOR_ADM_SHIFT(4) | \
 126                                         CSOR_NOR_TRHZ_80)
 127 #define CONFIG_SYS_NOR_FTIM0            (FTIM0_NOR_TACSE(0x4) | \
 128                                         FTIM0_NOR_TEADC(0x5) | \
 129                                         FTIM0_NOR_TAVDS(0x0) | \
 130                                         FTIM0_NOR_TEAHC(0x5))
 131 #define CONFIG_SYS_NOR_FTIM1            (FTIM1_NOR_TACO(0x35) | \
 132                                         FTIM1_NOR_TRAD_NOR(0x1A) | \
 133                                         FTIM1_NOR_TSEQRAD_NOR(0x13))
 134 #define CONFIG_SYS_NOR_FTIM2            (FTIM2_NOR_TCS(0x4) | \
 135                                         FTIM2_NOR_TCH(0x4) | \
 136                                         FTIM2_NOR_TWP(0x1c) | \
 137                                         FTIM2_NOR_TWPH(0x0e))
 138 #define CONFIG_SYS_NOR_FTIM3            0
 139
 140 #define CONFIG_SYS_FLASH_QUIET_TEST
 141 #define CONFIG_FLASH_SHOW_PROGRESS      45      /* count down from 45/5: 9..1 */
 142
 143 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 144 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 145 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 146 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 147
 148 #define CONFIG_SYS_FLASH_EMPTY_INFO
 149 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE_PHYS }
 150
 151 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 152 #define CONFIG_SYS_WRITE_SWAPPED_DATA
 153 #endif
 154
 155 /* CPLD */
 156
 157 #define CONFIG_SYS_CPLD_BASE    0x7fb00000
 158 #define CPLD_BASE_PHYS          CONFIG_SYS_CPLD_BASE
 159
 160 #define CONFIG_SYS_FPGA_CSPR_EXT        (0x0)
 161 #define CONFIG_SYS_FPGA_CSPR            (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
 162                                         CSPR_PORT_SIZE_8 | \
 163                                         CSPR_MSEL_GPCM | \
 164                                         CSPR_V)
 165 #define CONFIG_SYS_FPGA_AMASK           IFC_AMASK(64 * 1024)
 166 #define CONFIG_SYS_FPGA_CSOR            (CSOR_NOR_ADM_SHIFT(4) | \
 167                                         CSOR_NOR_NOR_MODE_AVD_NOR | \
 168                                         CSOR_NOR_TRHZ_80)
 169
 170 /* CPLD Timing parameters for IFC GPCM */
 171 #define CONFIG_SYS_FPGA_FTIM0           (FTIM0_GPCM_TACSE(0xf) | \
 172                                         FTIM0_GPCM_TEADC(0xf) | \
 173                                         FTIM0_GPCM_TEAHC(0xf))
 174 #define CONFIG_SYS_FPGA_FTIM1           (FTIM1_GPCM_TACO(0xff) | \
 175                                         FTIM1_GPCM_TRAD(0x3f))
 176 #define CONFIG_SYS_FPGA_FTIM2           (FTIM2_GPCM_TCS(0xf) | \
 177                                         FTIM2_GPCM_TCH(0xf) | \
 178                                         FTIM2_GPCM_TWP(0xff))
 179 #define CONFIG_SYS_FPGA_FTIM3           0x0
 180 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 181 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 182 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 183 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 184 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 185 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 186 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 187 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 188 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 189 #define CONFIG_SYS_CSPR1                CONFIG_SYS_FPGA_CSPR
 190 #define CONFIG_SYS_AMASK1               CONFIG_SYS_FPGA_AMASK
 191 #define CONFIG_SYS_CSOR1                CONFIG_SYS_FPGA_CSOR
 192 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_FPGA_FTIM0
 193 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_FPGA_FTIM1
 194 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_FPGA_FTIM2
 195 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_FPGA_FTIM3
 196
 197 /*
 198  * Serial Port
 199  */
 200 #ifdef CONFIG_LPUART
 201 #define CONFIG_LPUART_32B_REG
 202 #else
 203 #define CONFIG_SYS_NS16550_SERIAL
 204 #ifndef CONFIG_DM_SERIAL
 205 #define CONFIG_SYS_NS16550_REG_SIZE     1
 206 #endif
 207 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
 208 #endif
 209
 210 /*
 211  * I2C
 212  */
 213 #ifndef CONFIG_DM_I2C
 214 #define CONFIG_SYS_I2C
 215 #else
 216 #define CONFIG_I2C_SET_DEFAULT_BUS_NUM
 217 #define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
 218 #endif
 219 #define CONFIG_SYS_I2C_MXC
 220 #define CONFIG_SYS_I2C_MXC_I2C1         /* enable I2C bus 1 */
 221 #define CONFIG_SYS_I2C_MXC_I2C2         /* enable I2C bus 2 */
 222 #define CONFIG_SYS_I2C_MXC_I2C3         /* enable I2C bus 3 */
 223
 224 /* EEPROM */
 225 #define CONFIG_ID_EEPROM
 226 #define CONFIG_SYS_I2C_EEPROM_NXID
 227 #define CONFIG_SYS_EEPROM_BUS_NUM               1
 228 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x53
 229 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          1
 230 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       3
 231 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   5
 232
 233 /*
 234  * MMC
 235  */
 236
 237 /* SPI */
 238 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 239 /* QSPI */
 240 #define QSPI0_AMBA_BASE                 0x40000000
 241 #define FSL_QSPI_FLASH_SIZE             (1 << 24)
 242 #define FSL_QSPI_FLASH_NUM              2
 243
 244 /* DSPI */
 245 #endif
 246
 247 /* DM SPI */
 248 #if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI)
 249 #define CONFIG_DM_SPI_FLASH
 250 #endif
 251
 252 /*
 253  * Video
 254  */
 255 #ifdef CONFIG_VIDEO_FSL_DCU_FB
 256 #define CONFIG_VIDEO_LOGO
 257 #define CONFIG_VIDEO_BMP_LOGO
 258
 259 #define CONFIG_FSL_DCU_SII9022A
 260 #define CONFIG_SYS_I2C_DVI_BUS_NUM      1
 261 #define CONFIG_SYS_I2C_DVI_ADDR         0x39
 262 #endif
 263
 264 /*
 265  * eTSEC
 266  */
 267
 268 #ifdef CONFIG_TSEC_ENET
 269 #define CONFIG_ETHPRIME                 "ethernet@2d10000"
 270 #endif
 271
 272 /* PCIe */
 273 #define CONFIG_PCIE1            /* PCIE controller 1 */
 274 #define CONFIG_PCIE2            /* PCIE controller 2 */
 275
 276 #ifdef CONFIG_PCI
 277 #define CONFIG_PCI_SCAN_SHOW
 278 #endif
 279
 280 #define CONFIG_CMDLINE_TAG
 281
 282 #define CONFIG_PEN_ADDR_BIG_ENDIAN
 283 #define CONFIG_LAYERSCAPE_NS_ACCESS
 284 #define CONFIG_SMP_PEN_ADDR             0x01ee0200
 285 #define COUNTER_FREQUENCY               12500000
 286
 287 #define CONFIG_HWCONFIG
 288 #define HWCONFIG_BUFFER_SIZE            256
 289
 290 #define CONFIG_FSL_DEVICE_DISABLE
 291
 292 #define BOOT_TARGET_DEVICES(func) \
 293         func(MMC, mmc, 0) \
 294         func(USB, usb, 0) \
 295         func(DHCP, dhcp, na)
 296 #include <config_distro_bootcmd.h>
 297
 298 #ifdef CONFIG_LPUART
 299 #define CONFIG_EXTRA_ENV_SETTINGS       \
 300         "bootargs=root=/dev/ram0 rw console=ttyLP0,115200 "     \
 301                 "cma=64M@0x0-0xb0000000\0" \
 302         "initrd_high=0xffffffff\0"      \
 303         "fdt_addr=0x64f00000\0"         \
 304         "kernel_addr=0x65000000\0"      \
 305         "scriptaddr=0x80000000\0"       \
 306         "scripthdraddr=0x80080000\0"    \
 307         "fdtheader_addr_r=0x80100000\0" \
 308         "kernelheader_addr_r=0x80200000\0"      \
 309         "kernel_addr_r=0x81000000\0"    \
 310         "fdt_addr_r=0x90000000\0"       \
 311         "ramdisk_addr_r=0xa0000000\0"   \
 312         "load_addr=0xa0000000\0"        \
 313         "kernel_size=0x2800000\0"       \
 314         "kernel_addr_sd=0x8000\0"       \
 315         "kernel_size_sd=0x14000\0"      \
 316         "othbootargs=cma=64M@0x0-0xb0000000\0"  \
 317         BOOTENV                         \
 318         "boot_scripts=ls1021atwr_boot.scr\0"    \
 319         "boot_script_hdr=hdr_ls1021atwr_bs.out\0"       \
 320                 "scan_dev_for_boot_part="       \
 321                         "part list ${devtype} ${devnum} devplist; "     \
 322                         "env exists devplist || setenv devplist 1; "    \
 323                         "for distro_bootpart in ${devplist}; do "       \
 324                         "if fstype ${devtype} "                         \
 325                                 "${devnum}:${distro_bootpart} "         \
 326                                 "bootfstype; then "                     \
 327                                 "run scan_dev_for_boot; "               \
 328                         "fi; "                  \
 329                 "done\0"                        \
 330         "scan_dev_for_boot="                              \
 331                 "echo Scanning ${devtype} "               \
 332                                 "${devnum}:${distro_bootpart}...; "  \
 333                 "for prefix in ${boot_prefixes}; do "     \
 334                         "run scan_dev_for_scripts; "      \
 335                 "done;"                                   \
 336                 "\0"                                      \
 337         "boot_a_script="                                  \
 338                 "load ${devtype} ${devnum}:${distro_bootpart} "  \
 339                         "${scriptaddr} ${prefix}${script}; "    \
 340                 "env exists secureboot && load ${devtype} "     \
 341                         "${devnum}:${distro_bootpart} "         \
 342                         "${scripthdraddr} ${prefix}${boot_script_hdr}; " \
 343                         "env exists secureboot "        \
 344                         "&& esbc_validate ${scripthdraddr};"    \
 345                 "source ${scriptaddr}\0"          \
 346         "installer=load mmc 0:2 $load_addr "    \
 347                 "/flex_installer_arm32.itb; "           \
 348                 "bootm $load_addr#ls1021atwr\0" \
 349         "qspi_bootcmd=echo Trying load from qspi..;"    \
 350                 "sf probe && sf read $load_addr "       \
 351                 "$kernel_addr $kernel_size && bootm $load_addr#$board\0"        \
 352         "nor_bootcmd=echo Trying load from nor..;"      \
 353                 "cp.b $kernel_addr $load_addr "         \
 354                 "$kernel_size && bootm $load_addr#$board\0"
 355 #else
 356 #define CONFIG_EXTRA_ENV_SETTINGS       \
 357         "bootargs=root=/dev/ram0 rw console=ttyS0,115200 "      \
 358                 "cma=64M@0x0-0xb0000000\0" \
 359         "initrd_high=0xffffffff\0"      \
 360         "fdt_addr=0x64f00000\0"         \
 361         "kernel_addr=0x61000000\0"      \
 362         "kernelheader_addr=0x60800000\0"        \
 363         "scriptaddr=0x80000000\0"       \
 364         "scripthdraddr=0x80080000\0"    \
 365         "fdtheader_addr_r=0x80100000\0" \
 366         "kernelheader_addr_r=0x80200000\0"      \
 367         "kernel_addr_r=0x81000000\0"    \
 368         "kernelheader_size=0x40000\0"   \
 369         "fdt_addr_r=0x90000000\0"       \
 370         "ramdisk_addr_r=0xa0000000\0"   \
 371         "load_addr=0xa0000000\0"        \
 372         "kernel_size=0x2800000\0"       \
 373         "kernel_addr_sd=0x8000\0"       \
 374         "kernel_size_sd=0x14000\0"      \
 375         "kernelhdr_addr_sd=0x4000\0"            \
 376         "kernelhdr_size_sd=0x10\0"              \
 377         "othbootargs=cma=64M@0x0-0xb0000000\0"  \
 378         BOOTENV                         \
 379         "boot_scripts=ls1021atwr_boot.scr\0"    \
 380         "boot_script_hdr=hdr_ls1021atwr_bs.out\0"       \
 381                 "scan_dev_for_boot_part="       \
 382                         "part list ${devtype} ${devnum} devplist; "     \
 383                         "env exists devplist || setenv devplist 1; "    \
 384                         "for distro_bootpart in ${devplist}; do "       \
 385                         "if fstype ${devtype} "                         \
 386                                 "${devnum}:${distro_bootpart} "         \
 387                                 "bootfstype; then "                     \
 388                                 "run scan_dev_for_boot; "               \
 389                         "fi; "                  \
 390                 "done\0"                        \
 391         "scan_dev_for_boot="                              \
 392                 "echo Scanning ${devtype} "               \
 393                                 "${devnum}:${distro_bootpart}...; "  \
 394                 "for prefix in ${boot_prefixes}; do "     \
 395                         "run scan_dev_for_scripts; "      \
 396                 "done;"                                   \
 397                 "\0"                                      \
 398         "boot_a_script="                                  \
 399                 "load ${devtype} ${devnum}:${distro_bootpart} "  \
 400                         "${scriptaddr} ${prefix}${script}; "    \
 401                 "env exists secureboot && load ${devtype} "     \
 402                         "${devnum}:${distro_bootpart} "         \
 403                         "${scripthdraddr} ${prefix}${boot_script_hdr} " \
 404                         "&& esbc_validate ${scripthdraddr};"    \
 405                 "source ${scriptaddr}\0"          \
 406         "qspi_bootcmd=echo Trying load from qspi..;"    \
 407                 "sf probe && sf read $load_addr "       \
 408                 "$kernel_addr $kernel_size; env exists secureboot "     \
 409                 "&& sf read $kernelheader_addr_r $kernelheader_addr "   \
 410                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
 411                 "bootm $load_addr#$board\0" \
 412         "nor_bootcmd=echo Trying load from nor..;"      \
 413                 "cp.b $kernel_addr $load_addr "         \
 414                 "$kernel_size; env exists secureboot "  \
 415                 "&& cp.b $kernelheader_addr $kernelheader_addr_r "      \
 416                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
 417                 "bootm $load_addr#$board\0"     \
 418         "sd_bootcmd=echo Trying load from SD ..;"       \
 419                 "mmcinfo && mmc read $load_addr "       \
 420                 "$kernel_addr_sd $kernel_size_sd && "   \
 421                 "env exists secureboot && mmc read $kernelheader_addr_r "               \
 422                 "$kernelhdr_addr_sd $kernelhdr_size_sd "                \
 423                 " && esbc_validate ${kernelheader_addr_r};"     \
 424                 "bootm $load_addr#$board\0"
 425 #endif
 426
 427 #undef CONFIG_BOOTCOMMAND
 428 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 429 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; "     \
 430                            "env exists secureboot && esbc_halt"
 431 #elif defined(CONFIG_SD_BOOT)
 432 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; "       \
 433                            "env exists secureboot && esbc_halt;"
 434 #else
 435 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd;"       \
 436                            "env exists secureboot && esbc_halt;"
 437 #endif
 438
 439 /*
 440  * Miscellaneous configurable options
 441  */
 442 #define CONFIG_SYS_BOOTMAPSZ            (256 << 20)
 443
 444 #define CONFIG_SYS_LOAD_ADDR            0x82000000
 445
 446 #define CONFIG_LS102XA_STREAM_ID
 447
 448 #define CONFIG_SYS_INIT_SP_OFFSET \
 449         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 450 #define CONFIG_SYS_INIT_SP_ADDR \
 451         (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
 452
 453 #ifdef CONFIG_SPL_BUILD
 454 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
 455 #undef CONFIG_DM_I2C
 456 #else
 457 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 458 #endif
 459
 460 #define CONFIG_SYS_QE_FW_ADDR     0x60940000
 461
 462 /*
 463  * Environment
 464  */
 465 #define CONFIG_ENV_OVERWRITE
 466
 467 #if defined(CONFIG_SD_BOOT)
 468 #define CONFIG_SYS_MMC_ENV_DEV          0
 469 #endif
 470
 471 #include <asm/fsl_secure_boot.h>
 472 #define CONFIG_SYS_BOOTM_LEN    (64 << 20) /* Increase max gunzip size */
 473
 474 #endif