include/configs/ls1021atwr.h

   1 /*
   2  * Copyright 2014 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef __CONFIG_H
   8 #define __CONFIG_H
   9
  10 #define CONFIG_LS102XA
  11
  12 #define CONFIG_ARMV7_PSCI_1_0
  13
  14 #define CONFIG_ARMV7_SECURE_BASE        OCRAM_BASE_S_ADDR
  15
  16 #define CONFIG_SYS_FSL_CLK
  17
  18 #define CONFIG_DISPLAY_CPUINFO
  19 #define CONFIG_DISPLAY_BOARDINFO
  20
  21 #define CONFIG_SKIP_LOWLEVEL_INIT
  22 #define CONFIG_BOARD_EARLY_INIT_F
  23 #define CONFIG_DEEP_SLEEP
  24 #ifdef CONFIG_DEEP_SLEEP
  25 #define CONFIG_SILENT_CONSOLE
  26 #endif
  27
  28 /*
  29  * Size of malloc() pool
  30  */
  31 #define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
  32
  33 #define CONFIG_SYS_INIT_RAM_ADDR        OCRAM_BASE_ADDR
  34 #define CONFIG_SYS_INIT_RAM_SIZE        OCRAM_SIZE
  35
  36 /*
  37  * USB
  38  */
  39
  40 /*
  41  * EHCI Support - disbaled by default as
  42  * there is no signal coming out of soc on
  43  * this board for this controller. However,
  44  * the silicon still has this controller,
  45  * and anyone can use this controller by
  46  * taking signals out on their board.
  47  */
  48
  49 /*#define CONFIG_HAS_FSL_DR_USB*/
  50
  51 #ifdef CONFIG_HAS_FSL_DR_USB
  52 #define CONFIG_USB_EHCI
  53 #define CONFIG_USB_EHCI_FSL
  54 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
  55 #endif
  56
  57 /* XHCI Support - enabled by default */
  58 #define CONFIG_HAS_FSL_XHCI_USB
  59
  60 #ifdef CONFIG_HAS_FSL_XHCI_USB
  61 #define CONFIG_USB_XHCI_FSL
  62 #define CONFIG_USB_MAX_CONTROLLER_COUNT        1
  63 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS     2
  64 #endif
  65
  66 /*
  67  * Generic Timer Definitions
  68  */
  69 #define GENERIC_TIMER_CLK               12500000
  70
  71 #define CONFIG_SYS_CLK_FREQ             100000000
  72 #define CONFIG_DDR_CLK_FREQ             100000000
  73
  74 #define DDR_SDRAM_CFG                   0x470c0008
  75 #define DDR_CS0_BNDS                    0x008000bf
  76 #define DDR_CS0_CONFIG                  0x80014302
  77 #define DDR_TIMING_CFG_0                0x50550004
  78 #define DDR_TIMING_CFG_1                0xbcb38c56
  79 #define DDR_TIMING_CFG_2                0x0040d120
  80 #define DDR_TIMING_CFG_3                0x010e1000
  81 #define DDR_TIMING_CFG_4                0x00000001
  82 #define DDR_TIMING_CFG_5                0x03401400
  83 #define DDR_SDRAM_CFG_2                 0x00401010
  84 #define DDR_SDRAM_MODE                  0x00061c60
  85 #define DDR_SDRAM_MODE_2                0x00180000
  86 #define DDR_SDRAM_INTERVAL              0x18600618
  87 #define DDR_DDR_WRLVL_CNTL              0x8655f605
  88 #define DDR_DDR_WRLVL_CNTL_2            0x05060607
  89 #define DDR_DDR_WRLVL_CNTL_3            0x05050505
  90 #define DDR_DDR_CDR1                    0x80040000
  91 #define DDR_DDR_CDR2                    0x00000001
  92 #define DDR_SDRAM_CLK_CNTL              0x02000000
  93 #define DDR_DDR_ZQ_CNTL                 0x89080600
  94 #define DDR_CS0_CONFIG_2                0
  95 #define DDR_SDRAM_CFG_MEM_EN            0x80000000
  96 #define SDRAM_CFG2_D_INIT               0x00000010
  97 #define DDR_CDR2_VREF_TRAIN_EN          0x00000080
  98 #define SDRAM_CFG2_FRC_SR               0x80000000
  99 #define SDRAM_CFG_BI                    0x00000001
 100
 101 #ifdef CONFIG_RAMBOOT_PBL
 102 #define CONFIG_SYS_FSL_PBL_PBI  board/freescale/ls1021atwr/ls102xa_pbi.cfg
 103 #endif
 104
 105 #ifdef CONFIG_SD_BOOT
 106 #ifdef CONFIG_SD_BOOT_QSPI
 107 #define CONFIG_SYS_FSL_PBL_RCW  \
 108         board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg
 109 #else
 110 #define CONFIG_SYS_FSL_PBL_RCW  \
 111         board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg
 112 #endif
 113 #define CONFIG_SPL_FRAMEWORK
 114 #define CONFIG_SPL_LDSCRIPT     "arch/$(ARCH)/cpu/u-boot-spl.lds"
 115 #define CONFIG_SPL_LIBCOMMON_SUPPORT
 116 #define CONFIG_SPL_LIBGENERIC_SUPPORT
 117 #define CONFIG_SPL_ENV_SUPPORT
 118 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
 119 #define CONFIG_SPL_I2C_SUPPORT
 120 #define CONFIG_SPL_WATCHDOG_SUPPORT
 121 #define CONFIG_SPL_SERIAL_SUPPORT
 122 #define CONFIG_SPL_MMC_SUPPORT
 123 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR         0xe8
 124
 125 #ifdef CONFIG_SECURE_BOOT
 126 #define CONFIG_U_BOOT_HDR_SIZE                          (16 << 10)
 127 /*
 128  * HDR would be appended at end of image and copied to DDR along
 129  * with U-Boot image.
 130  */
 131 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS              (0x400 + \
 132                 (CONFIG_U_BOOT_HDR_SIZE / 512)
 133 #else
 134 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS              0x400
 135 #endif /* ifdef CONFIG_SECURE_BOOT */
 136
 137 #define CONFIG_SPL_TEXT_BASE            0x10000000
 138 #define CONFIG_SPL_MAX_SIZE             0x1a000
 139 #define CONFIG_SPL_STACK                0x1001d000
 140 #define CONFIG_SPL_PAD_TO               0x1c000
 141 #define CONFIG_SYS_TEXT_BASE            0x82000000
 142
 143 #define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SYS_TEXT_BASE + \
 144                 CONFIG_SYS_MONITOR_LEN)
 145 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
 146 #define CONFIG_SPL_BSS_START_ADDR       0x80100000
 147 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000
 148
 149 #ifdef CONFIG_U_BOOT_HDR_SIZE
 150 /*
 151  * HDR would be appended at end of image and copied to DDR along
 152  * with U-Boot image. Here u-boot max. size is 512K. So if binary
 153  * size increases then increase this size in case of secure boot as
 154  * it uses raw u-boot image instead of fit image.
 155  */
 156 #define CONFIG_SYS_MONITOR_LEN          (0x80000 + CONFIG_U_BOOT_HDR_SIZE)
 157 #else
 158 #define CONFIG_SYS_MONITOR_LEN          0x80000
 159 #endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */
 160 #endif
 161
 162 #ifdef CONFIG_QSPI_BOOT
 163 #define CONFIG_SYS_TEXT_BASE            0x40010000
 164 #endif
 165
 166 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 167 #define CONFIG_SYS_NO_FLASH
 168 #endif
 169
 170 #ifndef CONFIG_SYS_TEXT_BASE
 171 #define CONFIG_SYS_TEXT_BASE            0x60100000
 172 #endif
 173
 174 #define CONFIG_NR_DRAM_BANKS            1
 175 #define PHYS_SDRAM                      0x80000000
 176 #define PHYS_SDRAM_SIZE                 (1u * 1024 * 1024 * 1024)
 177
 178 #define CONFIG_SYS_DDR_SDRAM_BASE      0x80000000UL
 179 #define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_SDRAM_BASE
 180
 181 #define CONFIG_SYS_HAS_SERDES
 182
 183 #define CONFIG_FSL_CAAM                 /* Enable CAAM */
 184
 185 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
 186         !defined(CONFIG_QSPI_BOOT)
 187 #define CONFIG_U_QE
 188 #endif
 189
 190 /*
 191  * IFC Definitions
 192  */
 193 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 194 #define CONFIG_FSL_IFC
 195 #define CONFIG_SYS_FLASH_BASE           0x60000000
 196 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 197
 198 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
 199 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 200                                 CSPR_PORT_SIZE_16 | \
 201                                 CSPR_MSEL_NOR | \
 202                                 CSPR_V)
 203 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128 * 1024 * 1024)
 204
 205 /* NOR Flash Timing Params */
 206 #define CONFIG_SYS_NOR_CSOR             (CSOR_NOR_ADM_SHIFT(4) | \
 207                                         CSOR_NOR_TRHZ_80)
 208 #define CONFIG_SYS_NOR_FTIM0            (FTIM0_NOR_TACSE(0x4) | \
 209                                         FTIM0_NOR_TEADC(0x5) | \
 210                                         FTIM0_NOR_TAVDS(0x0) | \
 211                                         FTIM0_NOR_TEAHC(0x5))
 212 #define CONFIG_SYS_NOR_FTIM1            (FTIM1_NOR_TACO(0x35) | \
 213                                         FTIM1_NOR_TRAD_NOR(0x1A) | \
 214                                         FTIM1_NOR_TSEQRAD_NOR(0x13))
 215 #define CONFIG_SYS_NOR_FTIM2            (FTIM2_NOR_TCS(0x4) | \
 216                                         FTIM2_NOR_TCH(0x4) | \
 217                                         FTIM2_NOR_TWP(0x1c) | \
 218                                         FTIM2_NOR_TWPH(0x0e))
 219 #define CONFIG_SYS_NOR_FTIM3            0
 220
 221 #define CONFIG_FLASH_CFI_DRIVER
 222 #define CONFIG_SYS_FLASH_CFI
 223 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 224 #define CONFIG_SYS_FLASH_QUIET_TEST
 225 #define CONFIG_FLASH_SHOW_PROGRESS      45      /* count down from 45/5: 9..1 */
 226
 227 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 228 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 229 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 230 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 231
 232 #define CONFIG_SYS_FLASH_EMPTY_INFO
 233 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE_PHYS }
 234
 235 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 236 #define CONFIG_SYS_WRITE_SWAPPED_DATA
 237 #endif
 238
 239 /* CPLD */
 240
 241 #define CONFIG_SYS_CPLD_BASE    0x7fb00000
 242 #define CPLD_BASE_PHYS          CONFIG_SYS_CPLD_BASE
 243
 244 #define CONFIG_SYS_FPGA_CSPR_EXT        (0x0)
 245 #define CONFIG_SYS_FPGA_CSPR            (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
 246                                         CSPR_PORT_SIZE_8 | \
 247                                         CSPR_MSEL_GPCM | \
 248                                         CSPR_V)
 249 #define CONFIG_SYS_FPGA_AMASK           IFC_AMASK(64 * 1024)
 250 #define CONFIG_SYS_FPGA_CSOR            (CSOR_NOR_ADM_SHIFT(4) | \
 251                                         CSOR_NOR_NOR_MODE_AVD_NOR | \
 252                                         CSOR_NOR_TRHZ_80)
 253
 254 /* CPLD Timing parameters for IFC GPCM */
 255 #define CONFIG_SYS_FPGA_FTIM0           (FTIM0_GPCM_TACSE(0xf) | \
 256                                         FTIM0_GPCM_TEADC(0xf) | \
 257                                         FTIM0_GPCM_TEAHC(0xf))
 258 #define CONFIG_SYS_FPGA_FTIM1           (FTIM1_GPCM_TACO(0xff) | \
 259                                         FTIM1_GPCM_TRAD(0x3f))
 260 #define CONFIG_SYS_FPGA_FTIM2           (FTIM2_GPCM_TCS(0xf) | \
 261                                         FTIM2_GPCM_TCH(0xf) | \
 262                                         FTIM2_GPCM_TWP(0xff))
 263 #define CONFIG_SYS_FPGA_FTIM3           0x0
 264 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 265 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 266 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 267 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 268 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 269 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 270 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 271 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 272 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 273 #define CONFIG_SYS_CSPR1                CONFIG_SYS_FPGA_CSPR
 274 #define CONFIG_SYS_AMASK1               CONFIG_SYS_FPGA_AMASK
 275 #define CONFIG_SYS_CSOR1                CONFIG_SYS_FPGA_CSOR
 276 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_FPGA_FTIM0
 277 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_FPGA_FTIM1
 278 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_FPGA_FTIM2
 279 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_FPGA_FTIM3
 280
 281 /*
 282  * Serial Port
 283  */
 284 #ifdef CONFIG_LPUART
 285 #define CONFIG_LPUART_32B_REG
 286 #else
 287 #define CONFIG_CONS_INDEX               1
 288 #define CONFIG_SYS_NS16550_SERIAL
 289 #ifndef CONFIG_DM_SERIAL
 290 #define CONFIG_SYS_NS16550_REG_SIZE     1
 291 #endif
 292 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
 293 #endif
 294
 295 #define CONFIG_BAUDRATE                 115200
 296
 297 /*
 298  * I2C
 299  */
 300 #define CONFIG_SYS_I2C
 301 #define CONFIG_SYS_I2C_MXC
 302 #define CONFIG_SYS_I2C_MXC_I2C1         /* enable I2C bus 1 */
 303 #define CONFIG_SYS_I2C_MXC_I2C2         /* enable I2C bus 2 */
 304 #define CONFIG_SYS_I2C_MXC_I2C3         /* enable I2C bus 3 */
 305
 306 /* EEPROM */
 307 #define CONFIG_ID_EEPROM
 308 #define CONFIG_SYS_I2C_EEPROM_NXID
 309 #define CONFIG_SYS_EEPROM_BUS_NUM               1
 310 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x53
 311 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          1
 312 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       3
 313 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   5
 314
 315 /*
 316  * MMC
 317  */
 318 #define CONFIG_MMC
 319 #define CONFIG_FSL_ESDHC
 320 #define CONFIG_GENERIC_MMC
 321
 322 #define CONFIG_DOS_PARTITION
 323
 324 /* SPI */
 325 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 326 /* QSPI */
 327 #define QSPI0_AMBA_BASE                 0x40000000
 328 #define FSL_QSPI_FLASH_SIZE             (1 << 24)
 329 #define FSL_QSPI_FLASH_NUM              2
 330
 331 /* DSPI */
 332 #endif
 333
 334 /* DM SPI */
 335 #if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI)
 336 #define CONFIG_DM_SPI_FLASH
 337 #endif
 338
 339 /*
 340  * Video
 341  */
 342 #define CONFIG_FSL_DCU_FB
 343
 344 #ifdef CONFIG_FSL_DCU_FB
 345 #define CONFIG_VIDEO
 346 #define CONFIG_CMD_BMP
 347 #define CONFIG_CFB_CONSOLE
 348 #define CONFIG_VGA_AS_SINGLE_DEVICE
 349 #define CONFIG_VIDEO_LOGO
 350 #define CONFIG_VIDEO_BMP_LOGO
 351 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
 352
 353 #define CONFIG_FSL_DCU_SII9022A
 354 #define CONFIG_SYS_I2C_DVI_BUS_NUM      1
 355 #define CONFIG_SYS_I2C_DVI_ADDR         0x39
 356 #endif
 357
 358 /*
 359  * eTSEC
 360  */
 361 #define CONFIG_TSEC_ENET
 362
 363 #ifdef CONFIG_TSEC_ENET
 364 #define CONFIG_MII
 365 #define CONFIG_MII_DEFAULT_TSEC         1
 366 #define CONFIG_TSEC1                    1
 367 #define CONFIG_TSEC1_NAME               "eTSEC1"
 368 #define CONFIG_TSEC2                    1
 369 #define CONFIG_TSEC2_NAME               "eTSEC2"
 370 #define CONFIG_TSEC3                    1
 371 #define CONFIG_TSEC3_NAME               "eTSEC3"
 372
 373 #define TSEC1_PHY_ADDR                  2
 374 #define TSEC2_PHY_ADDR                  0
 375 #define TSEC3_PHY_ADDR                  1
 376
 377 #define TSEC1_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 378 #define TSEC2_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 379 #define TSEC3_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 380
 381 #define TSEC1_PHYIDX                    0
 382 #define TSEC2_PHYIDX                    0
 383 #define TSEC3_PHYIDX                    0
 384
 385 #define CONFIG_ETHPRIME                 "eTSEC1"
 386
 387 #define CONFIG_PHY_GIGE
 388 #define CONFIG_PHYLIB
 389 #define CONFIG_PHY_ATHEROS
 390
 391 #define CONFIG_HAS_ETH0
 392 #define CONFIG_HAS_ETH1
 393 #define CONFIG_HAS_ETH2
 394 #endif
 395
 396 /* PCIe */
 397 #define CONFIG_PCI              /* Enable PCI/PCIE */
 398 #define CONFIG_PCIE1            /* PCIE controller 1 */
 399 #define CONFIG_PCIE2            /* PCIE controller 2 */
 400 #define CONFIG_PCIE_LAYERSCAPE  /* Use common FSL Layerscape PCIe code */
 401 #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"
 402
 403 #define CONFIG_SYS_PCI_64BIT
 404
 405 #define CONFIG_SYS_PCIE_CFG0_PHYS_OFF   0x00000000
 406 #define CONFIG_SYS_PCIE_CFG0_SIZE       0x00001000      /* 4k */
 407 #define CONFIG_SYS_PCIE_CFG1_PHYS_OFF   0x00001000
 408 #define CONFIG_SYS_PCIE_CFG1_SIZE       0x00001000      /* 4k */
 409
 410 #define CONFIG_SYS_PCIE_IO_BUS          0x00000000
 411 #define CONFIG_SYS_PCIE_IO_PHYS_OFF     0x00010000
 412 #define CONFIG_SYS_PCIE_IO_SIZE         0x00010000      /* 64k */
 413
 414 #define CONFIG_SYS_PCIE_MEM_BUS         0x08000000
 415 #define CONFIG_SYS_PCIE_MEM_PHYS_OFF    0x04000000
 416 #define CONFIG_SYS_PCIE_MEM_SIZE        0x08000000      /* 128M */
 417
 418 #ifdef CONFIG_PCI
 419 #define CONFIG_PCI_PNP
 420 #define CONFIG_PCI_SCAN_SHOW
 421 #define CONFIG_CMD_PCI
 422 #endif
 423
 424 #define CONFIG_CMDLINE_TAG
 425 #define CONFIG_CMDLINE_EDITING
 426
 427 #define CONFIG_ARMV7_NONSEC
 428 #define CONFIG_ARMV7_VIRT
 429 #define CONFIG_PEN_ADDR_BIG_ENDIAN
 430 #define CONFIG_LAYERSCAPE_NS_ACCESS
 431 #define CONFIG_SMP_PEN_ADDR             0x01ee0200
 432 #define CONFIG_TIMER_CLK_FREQ           12500000
 433
 434 #define CONFIG_HWCONFIG
 435 #define HWCONFIG_BUFFER_SIZE            256
 436
 437 #define CONFIG_FSL_DEVICE_DISABLE
 438
 439
 440 #ifdef CONFIG_LPUART
 441 #define CONFIG_EXTRA_ENV_SETTINGS       \
 442         "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
 443         "initrd_high=0xffffffff\0"      \
 444         "fdt_high=0xffffffff\0"
 445 #else
 446 #define CONFIG_EXTRA_ENV_SETTINGS       \
 447         "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
 448         "initrd_high=0xffffffff\0"      \
 449         "fdt_high=0xffffffff\0"
 450 #endif
 451
 452 /*
 453  * Miscellaneous configurable options
 454  */
 455 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 456 #define CONFIG_AUTO_COMPLETE
 457 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size */
 458 #define CONFIG_SYS_PBSIZE               \
 459                 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 460 #define CONFIG_SYS_MAXARGS              16      /* max number of command args */
 461 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
 462
 463 #define CONFIG_SYS_MEMTEST_START        0x80000000
 464 #define CONFIG_SYS_MEMTEST_END          0x9fffffff
 465
 466 #define CONFIG_SYS_LOAD_ADDR            0x82000000
 467
 468 #define CONFIG_LS102XA_STREAM_ID
 469
 470 /*
 471  * Stack sizes
 472  * The stack sizes are set up in start.S using the settings below
 473  */
 474 #define CONFIG_STACKSIZE                (30 * 1024)
 475
 476 #define CONFIG_SYS_INIT_SP_OFFSET \
 477         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 478 #define CONFIG_SYS_INIT_SP_ADDR \
 479         (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
 480
 481 #ifdef CONFIG_SPL_BUILD
 482 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
 483 #else
 484 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 485 #endif
 486
 487 #define CONFIG_SYS_QE_FW_ADDR     0x600c0000
 488
 489 /*
 490  * Environment
 491  */
 492 #define CONFIG_ENV_OVERWRITE
 493
 494 #if defined(CONFIG_SD_BOOT)
 495 #define CONFIG_ENV_OFFSET               0x100000
 496 #define CONFIG_ENV_IS_IN_MMC
 497 #define CONFIG_SYS_MMC_ENV_DEV          0
 498 #define CONFIG_ENV_SIZE                 0x20000
 499 #elif defined(CONFIG_QSPI_BOOT)
 500 #define CONFIG_ENV_IS_IN_SPI_FLASH
 501 #define CONFIG_ENV_SIZE                 0x2000
 502 #define CONFIG_ENV_OFFSET               0x100000
 503 #define CONFIG_ENV_SECT_SIZE            0x10000
 504 #else
 505 #define CONFIG_ENV_IS_IN_FLASH
 506 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 507 #define CONFIG_ENV_SIZE                 0x20000
 508 #define CONFIG_ENV_SECT_SIZE            0x20000 /* 128K (one sector) */
 509 #endif
 510
 511 #define CONFIG_MISC_INIT_R
 512
 513 /* Hash command with SHA acceleration supported in hardware */
 514 #ifdef CONFIG_FSL_CAAM
 515 #define CONFIG_CMD_HASH
 516 #define CONFIG_SHA_HW_ACCEL
 517 #endif
 518
 519 #include <asm/fsl_secure_boot.h>
 520 #define CONFIG_SYS_BOOTM_LEN    (64 << 20) /* Increase max gunzip size */
 521
 522 #endif