include/configs/ls1021atwr.h

   1 /*
   2  * Copyright 2014 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef __CONFIG_H
   8 #define __CONFIG_H
   9
  10 #define CONFIG_LS102XA
  11
  12 #define CONFIG_ARMV7_PSCI_1_0
  13
  14 #define CONFIG_ARMV7_SECURE_BASE        OCRAM_BASE_S_ADDR
  15
  16 #define CONFIG_SYS_FSL_CLK
  17
  18 #define CONFIG_SKIP_LOWLEVEL_INIT
  19 #define CONFIG_DEEP_SLEEP
  20
  21 /*
  22  * Size of malloc() pool
  23  */
  24 #define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
  25
  26 #define CONFIG_SYS_INIT_RAM_ADDR        OCRAM_BASE_ADDR
  27 #define CONFIG_SYS_INIT_RAM_SIZE        OCRAM_SIZE
  28
  29 /*
  30  * USB
  31  */
  32
  33 /*
  34  * EHCI Support - disbaled by default as
  35  * there is no signal coming out of soc on
  36  * this board for this controller. However,
  37  * the silicon still has this controller,
  38  * and anyone can use this controller by
  39  * taking signals out on their board.
  40  */
  41
  42 /*#define CONFIG_HAS_FSL_DR_USB*/
  43
  44 #ifdef CONFIG_HAS_FSL_DR_USB
  45 #define CONFIG_USB_EHCI
  46 #define CONFIG_USB_EHCI_FSL
  47 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
  48 #endif
  49
  50 /* XHCI Support - enabled by default */
  51 #define CONFIG_HAS_FSL_XHCI_USB
  52
  53 #ifdef CONFIG_HAS_FSL_XHCI_USB
  54 #define CONFIG_USB_XHCI_FSL
  55 #define CONFIG_USB_MAX_CONTROLLER_COUNT        1
  56 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS     2
  57 #endif
  58
  59 /*
  60  * Generic Timer Definitions
  61  */
  62 #define GENERIC_TIMER_CLK               12500000
  63
  64 #define CONFIG_SYS_CLK_FREQ             100000000
  65 #define CONFIG_DDR_CLK_FREQ             100000000
  66
  67 #define DDR_SDRAM_CFG                   0x470c0008
  68 #define DDR_CS0_BNDS                    0x008000bf
  69 #define DDR_CS0_CONFIG                  0x80014302
  70 #define DDR_TIMING_CFG_0                0x50550004
  71 #define DDR_TIMING_CFG_1                0xbcb38c56
  72 #define DDR_TIMING_CFG_2                0x0040d120
  73 #define DDR_TIMING_CFG_3                0x010e1000
  74 #define DDR_TIMING_CFG_4                0x00000001
  75 #define DDR_TIMING_CFG_5                0x03401400
  76 #define DDR_SDRAM_CFG_2                 0x00401010
  77 #define DDR_SDRAM_MODE                  0x00061c60
  78 #define DDR_SDRAM_MODE_2                0x00180000
  79 #define DDR_SDRAM_INTERVAL              0x18600618
  80 #define DDR_DDR_WRLVL_CNTL              0x8655f605
  81 #define DDR_DDR_WRLVL_CNTL_2            0x05060607
  82 #define DDR_DDR_WRLVL_CNTL_3            0x05050505
  83 #define DDR_DDR_CDR1                    0x80040000
  84 #define DDR_DDR_CDR2                    0x00000001
  85 #define DDR_SDRAM_CLK_CNTL              0x02000000
  86 #define DDR_DDR_ZQ_CNTL                 0x89080600
  87 #define DDR_CS0_CONFIG_2                0
  88 #define DDR_SDRAM_CFG_MEM_EN            0x80000000
  89 #define SDRAM_CFG2_D_INIT               0x00000010
  90 #define DDR_CDR2_VREF_TRAIN_EN          0x00000080
  91 #define SDRAM_CFG2_FRC_SR               0x80000000
  92 #define SDRAM_CFG_BI                    0x00000001
  93
  94 #ifdef CONFIG_RAMBOOT_PBL
  95 #define CONFIG_SYS_FSL_PBL_PBI  board/freescale/ls1021atwr/ls102xa_pbi.cfg
  96 #endif
  97
  98 #ifdef CONFIG_SD_BOOT
  99 #ifdef CONFIG_SD_BOOT_QSPI
 100 #define CONFIG_SYS_FSL_PBL_RCW  \
 101         board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg
 102 #else
 103 #define CONFIG_SYS_FSL_PBL_RCW  \
 104         board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg
 105 #endif
 106 #define CONFIG_SPL_FRAMEWORK
 107 #define CONFIG_SPL_LDSCRIPT     "arch/$(ARCH)/cpu/u-boot-spl.lds"
 108
 109 #ifdef CONFIG_SECURE_BOOT
 110 /*
 111  * HDR would be appended at end of image and copied to DDR along
 112  * with U-Boot image.
 113  */
 114 #define CONFIG_U_BOOT_HDR_SIZE                          (16 << 10)
 115 #endif /* ifdef CONFIG_SECURE_BOOT */
 116
 117 #define CONFIG_SPL_TEXT_BASE            0x10000000
 118 #define CONFIG_SPL_MAX_SIZE             0x1a000
 119 #define CONFIG_SPL_STACK                0x1001d000
 120 #define CONFIG_SPL_PAD_TO               0x1c000
 121 #define CONFIG_SYS_TEXT_BASE            0x82000000
 122
 123 #define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SYS_TEXT_BASE + \
 124                 CONFIG_SYS_MONITOR_LEN)
 125 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
 126 #define CONFIG_SPL_BSS_START_ADDR       0x80100000
 127 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000
 128
 129 #ifdef CONFIG_U_BOOT_HDR_SIZE
 130 /*
 131  * HDR would be appended at end of image and copied to DDR along
 132  * with U-Boot image. Here u-boot max. size is 512K. So if binary
 133  * size increases then increase this size in case of secure boot as
 134  * it uses raw u-boot image instead of fit image.
 135  */
 136 #define CONFIG_SYS_MONITOR_LEN          (0x80000 + CONFIG_U_BOOT_HDR_SIZE)
 137 #else
 138 #define CONFIG_SYS_MONITOR_LEN          0x80000
 139 #endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */
 140 #endif
 141
 142 #ifdef CONFIG_QSPI_BOOT
 143 #define CONFIG_SYS_TEXT_BASE            0x40010000
 144 #endif
 145
 146 #ifndef CONFIG_SYS_TEXT_BASE
 147 #define CONFIG_SYS_TEXT_BASE            0x60100000
 148 #endif
 149
 150 #define CONFIG_NR_DRAM_BANKS            1
 151 #define PHYS_SDRAM                      0x80000000
 152 #define PHYS_SDRAM_SIZE                 (1u * 1024 * 1024 * 1024)
 153
 154 #define CONFIG_SYS_DDR_SDRAM_BASE      0x80000000UL
 155 #define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_SDRAM_BASE
 156
 157 #define CONFIG_FSL_CAAM                 /* Enable CAAM */
 158
 159 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
 160         !defined(CONFIG_QSPI_BOOT)
 161 #define CONFIG_U_QE
 162 #endif
 163
 164 /*
 165  * IFC Definitions
 166  */
 167 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 168 #define CONFIG_FSL_IFC
 169 #define CONFIG_SYS_FLASH_BASE           0x60000000
 170 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 171
 172 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
 173 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 174                                 CSPR_PORT_SIZE_16 | \
 175                                 CSPR_MSEL_NOR | \
 176                                 CSPR_V)
 177 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128 * 1024 * 1024)
 178
 179 /* NOR Flash Timing Params */
 180 #define CONFIG_SYS_NOR_CSOR             (CSOR_NOR_ADM_SHIFT(4) | \
 181                                         CSOR_NOR_TRHZ_80)
 182 #define CONFIG_SYS_NOR_FTIM0            (FTIM0_NOR_TACSE(0x4) | \
 183                                         FTIM0_NOR_TEADC(0x5) | \
 184                                         FTIM0_NOR_TAVDS(0x0) | \
 185                                         FTIM0_NOR_TEAHC(0x5))
 186 #define CONFIG_SYS_NOR_FTIM1            (FTIM1_NOR_TACO(0x35) | \
 187                                         FTIM1_NOR_TRAD_NOR(0x1A) | \
 188                                         FTIM1_NOR_TSEQRAD_NOR(0x13))
 189 #define CONFIG_SYS_NOR_FTIM2            (FTIM2_NOR_TCS(0x4) | \
 190                                         FTIM2_NOR_TCH(0x4) | \
 191                                         FTIM2_NOR_TWP(0x1c) | \
 192                                         FTIM2_NOR_TWPH(0x0e))
 193 #define CONFIG_SYS_NOR_FTIM3            0
 194
 195 #define CONFIG_FLASH_CFI_DRIVER
 196 #define CONFIG_SYS_FLASH_CFI
 197 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 198 #define CONFIG_SYS_FLASH_QUIET_TEST
 199 #define CONFIG_FLASH_SHOW_PROGRESS      45      /* count down from 45/5: 9..1 */
 200
 201 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 202 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 203 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 204 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 205
 206 #define CONFIG_SYS_FLASH_EMPTY_INFO
 207 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE_PHYS }
 208
 209 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 210 #define CONFIG_SYS_WRITE_SWAPPED_DATA
 211 #endif
 212
 213 /* CPLD */
 214
 215 #define CONFIG_SYS_CPLD_BASE    0x7fb00000
 216 #define CPLD_BASE_PHYS          CONFIG_SYS_CPLD_BASE
 217
 218 #define CONFIG_SYS_FPGA_CSPR_EXT        (0x0)
 219 #define CONFIG_SYS_FPGA_CSPR            (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
 220                                         CSPR_PORT_SIZE_8 | \
 221                                         CSPR_MSEL_GPCM | \
 222                                         CSPR_V)
 223 #define CONFIG_SYS_FPGA_AMASK           IFC_AMASK(64 * 1024)
 224 #define CONFIG_SYS_FPGA_CSOR            (CSOR_NOR_ADM_SHIFT(4) | \
 225                                         CSOR_NOR_NOR_MODE_AVD_NOR | \
 226                                         CSOR_NOR_TRHZ_80)
 227
 228 /* CPLD Timing parameters for IFC GPCM */
 229 #define CONFIG_SYS_FPGA_FTIM0           (FTIM0_GPCM_TACSE(0xf) | \
 230                                         FTIM0_GPCM_TEADC(0xf) | \
 231                                         FTIM0_GPCM_TEAHC(0xf))
 232 #define CONFIG_SYS_FPGA_FTIM1           (FTIM1_GPCM_TACO(0xff) | \
 233                                         FTIM1_GPCM_TRAD(0x3f))
 234 #define CONFIG_SYS_FPGA_FTIM2           (FTIM2_GPCM_TCS(0xf) | \
 235                                         FTIM2_GPCM_TCH(0xf) | \
 236                                         FTIM2_GPCM_TWP(0xff))
 237 #define CONFIG_SYS_FPGA_FTIM3           0x0
 238 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 239 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 240 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 241 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 242 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 243 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 244 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 245 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 246 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 247 #define CONFIG_SYS_CSPR1                CONFIG_SYS_FPGA_CSPR
 248 #define CONFIG_SYS_AMASK1               CONFIG_SYS_FPGA_AMASK
 249 #define CONFIG_SYS_CSOR1                CONFIG_SYS_FPGA_CSOR
 250 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_FPGA_FTIM0
 251 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_FPGA_FTIM1
 252 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_FPGA_FTIM2
 253 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_FPGA_FTIM3
 254
 255 /*
 256  * Serial Port
 257  */
 258 #ifdef CONFIG_LPUART
 259 #define CONFIG_LPUART_32B_REG
 260 #else
 261 #define CONFIG_CONS_INDEX               1
 262 #define CONFIG_SYS_NS16550_SERIAL
 263 #ifndef CONFIG_DM_SERIAL
 264 #define CONFIG_SYS_NS16550_REG_SIZE     1
 265 #endif
 266 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
 267 #endif
 268
 269 #define CONFIG_BAUDRATE                 115200
 270
 271 /*
 272  * I2C
 273  */
 274 #define CONFIG_SYS_I2C
 275 #define CONFIG_SYS_I2C_MXC
 276 #define CONFIG_SYS_I2C_MXC_I2C1         /* enable I2C bus 1 */
 277 #define CONFIG_SYS_I2C_MXC_I2C2         /* enable I2C bus 2 */
 278 #define CONFIG_SYS_I2C_MXC_I2C3         /* enable I2C bus 3 */
 279
 280 /* EEPROM */
 281 #define CONFIG_ID_EEPROM
 282 #define CONFIG_SYS_I2C_EEPROM_NXID
 283 #define CONFIG_SYS_EEPROM_BUS_NUM               1
 284 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x53
 285 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          1
 286 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       3
 287 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   5
 288
 289 /*
 290  * MMC
 291  */
 292 #define CONFIG_FSL_ESDHC
 293
 294 /* SPI */
 295 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 296 /* QSPI */
 297 #define QSPI0_AMBA_BASE                 0x40000000
 298 #define FSL_QSPI_FLASH_SIZE             (1 << 24)
 299 #define FSL_QSPI_FLASH_NUM              2
 300
 301 /* DSPI */
 302 #endif
 303
 304 /* DM SPI */
 305 #if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI)
 306 #define CONFIG_DM_SPI_FLASH
 307 #endif
 308
 309 /*
 310  * Video
 311  */
 312 #define CONFIG_FSL_DCU_FB
 313
 314 #ifdef CONFIG_FSL_DCU_FB
 315 #define CONFIG_CMD_BMP
 316 #define CONFIG_VIDEO_LOGO
 317 #define CONFIG_VIDEO_BMP_LOGO
 318
 319 #define CONFIG_FSL_DCU_SII9022A
 320 #define CONFIG_SYS_I2C_DVI_BUS_NUM      1
 321 #define CONFIG_SYS_I2C_DVI_ADDR         0x39
 322 #endif
 323
 324 /*
 325  * eTSEC
 326  */
 327 #define CONFIG_TSEC_ENET
 328
 329 #ifdef CONFIG_TSEC_ENET
 330 #define CONFIG_MII
 331 #define CONFIG_MII_DEFAULT_TSEC         1
 332 #define CONFIG_TSEC1                    1
 333 #define CONFIG_TSEC1_NAME               "eTSEC1"
 334 #define CONFIG_TSEC2                    1
 335 #define CONFIG_TSEC2_NAME               "eTSEC2"
 336 #define CONFIG_TSEC3                    1
 337 #define CONFIG_TSEC3_NAME               "eTSEC3"
 338
 339 #define TSEC1_PHY_ADDR                  2
 340 #define TSEC2_PHY_ADDR                  0
 341 #define TSEC3_PHY_ADDR                  1
 342
 343 #define TSEC1_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 344 #define TSEC2_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 345 #define TSEC3_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 346
 347 #define TSEC1_PHYIDX                    0
 348 #define TSEC2_PHYIDX                    0
 349 #define TSEC3_PHYIDX                    0
 350
 351 #define CONFIG_ETHPRIME                 "eTSEC1"
 352
 353 #define CONFIG_PHY_GIGE
 354 #define CONFIG_PHYLIB
 355 #define CONFIG_PHY_ATHEROS
 356
 357 #define CONFIG_HAS_ETH0
 358 #define CONFIG_HAS_ETH1
 359 #define CONFIG_HAS_ETH2
 360 #endif
 361
 362 /* PCIe */
 363 #define CONFIG_PCIE1            /* PCIE controller 1 */
 364 #define CONFIG_PCIE2            /* PCIE controller 2 */
 365
 366 #ifdef CONFIG_PCI
 367 #define CONFIG_PCI_SCAN_SHOW
 368 #define CONFIG_CMD_PCI
 369 #endif
 370
 371 #define CONFIG_CMDLINE_TAG
 372 #define CONFIG_CMDLINE_EDITING
 373
 374 #define CONFIG_PEN_ADDR_BIG_ENDIAN
 375 #define CONFIG_LAYERSCAPE_NS_ACCESS
 376 #define CONFIG_SMP_PEN_ADDR             0x01ee0200
 377 #define CONFIG_TIMER_CLK_FREQ           12500000
 378
 379 #define CONFIG_HWCONFIG
 380 #define HWCONFIG_BUFFER_SIZE            256
 381
 382 #define CONFIG_FSL_DEVICE_DISABLE
 383
 384
 385 #ifdef CONFIG_LPUART
 386 #define CONFIG_EXTRA_ENV_SETTINGS       \
 387         "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
 388         "initrd_high=0xffffffff\0"      \
 389         "fdt_high=0xffffffff\0"
 390 #else
 391 #define CONFIG_EXTRA_ENV_SETTINGS       \
 392         "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
 393         "initrd_high=0xffffffff\0"      \
 394         "fdt_high=0xffffffff\0"
 395 #endif
 396
 397 /*
 398  * Miscellaneous configurable options
 399  */
 400 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 401 #define CONFIG_AUTO_COMPLETE
 402 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size */
 403 #define CONFIG_SYS_PBSIZE               \
 404                 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 405 #define CONFIG_SYS_MAXARGS              16      /* max number of command args */
 406 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
 407
 408 #define CONFIG_SYS_MEMTEST_START        0x80000000
 409 #define CONFIG_SYS_MEMTEST_END          0x9fffffff
 410
 411 #define CONFIG_SYS_LOAD_ADDR            0x82000000
 412
 413 #define CONFIG_LS102XA_STREAM_ID
 414
 415 /*
 416  * Stack sizes
 417  * The stack sizes are set up in start.S using the settings below
 418  */
 419 #define CONFIG_STACKSIZE                (30 * 1024)
 420
 421 #define CONFIG_SYS_INIT_SP_OFFSET \
 422         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 423 #define CONFIG_SYS_INIT_SP_ADDR \
 424         (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
 425
 426 #ifdef CONFIG_SPL_BUILD
 427 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
 428 #else
 429 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 430 #endif
 431
 432 #define CONFIG_SYS_QE_FW_ADDR     0x600c0000
 433
 434 /*
 435  * Environment
 436  */
 437 #define CONFIG_ENV_OVERWRITE
 438
 439 #if defined(CONFIG_SD_BOOT)
 440 #define CONFIG_ENV_OFFSET               0x100000
 441 #define CONFIG_ENV_IS_IN_MMC
 442 #define CONFIG_SYS_MMC_ENV_DEV          0
 443 #define CONFIG_ENV_SIZE                 0x20000
 444 #elif defined(CONFIG_QSPI_BOOT)
 445 #define CONFIG_ENV_IS_IN_SPI_FLASH
 446 #define CONFIG_ENV_SIZE                 0x2000
 447 #define CONFIG_ENV_OFFSET               0x100000
 448 #define CONFIG_ENV_SECT_SIZE            0x10000
 449 #else
 450 #define CONFIG_ENV_IS_IN_FLASH
 451 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 452 #define CONFIG_ENV_SIZE                 0x20000
 453 #define CONFIG_ENV_SECT_SIZE            0x20000 /* 128K (one sector) */
 454 #endif
 455
 456 #define CONFIG_MISC_INIT_R
 457
 458 /* Hash command with SHA acceleration supported in hardware */
 459 #ifdef CONFIG_FSL_CAAM
 460 #define CONFIG_CMD_HASH
 461 #define CONFIG_SHA_HW_ACCEL
 462 #endif
 463
 464 #include <asm/fsl_secure_boot.h>
 465 #define CONFIG_SYS_BOOTM_LEN    (64 << 20) /* Increase max gunzip size */
 466
 467 #endif