1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Configuration header file for K3 J721E EVM
5 * Copyright (C) 2018-2019 Texas Instruments Incorporated - http://www.ti.com/
6 * Lokesh Vutla <lokeshvutla@ti.com>
9 #ifndef __CONFIG_J721E_EVM_H
10 #define __CONFIG_J721E_EVM_H
12 #include <linux/sizes.h>
13 #include <config_distro_bootcmd.h>
14 #include <environment/ti/mmc.h>
15 #include <environment/ti/k3_rproc.h>
16 #include <environment/ti/ufs.h>
18 #define CONFIG_ENV_SIZE (128 << 10)
20 /* DDR Configuration */
21 #define CONFIG_SYS_SDRAM_BASE1 0x880000000
23 /* SPL Loader Configuration */
24 #ifdef CONFIG_TARGET_J721E_A72_EVM
25 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SPL_TEXT_BASE + \
26 CONFIG_SYS_K3_NON_SECURE_MSRAM_SIZE)
29 * Maximum size in memory allocated to the SPL BSS. Keep it as tight as
30 * possible (to allow the build to go through), as this directly affects
31 * our memory footprint. The less we use for BSS the more we have available
32 * for everything else.
34 #define CONFIG_SPL_BSS_MAX_SIZE 0xA000
36 * Link BSS to be within SPL in a dedicated region located near the top of
37 * the MCU SRAM, this way making it available also before relocation. Note
38 * that we are not using the actual top of the MCU SRAM as there is a memory
39 * location filled in by the boot ROM that we want to read out without any
40 * interference from the C context.
42 #define CONFIG_SPL_BSS_START_ADDR (CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX -\
43 CONFIG_SPL_BSS_MAX_SIZE)
44 /* Set the stack right below the SPL BSS section */
45 #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SPL_BSS_START_ADDR
46 /* Configure R5 SPL post-relocation malloc pool in DDR */
47 #define CONFIG_SYS_SPL_MALLOC_START 0x84000000
48 #define CONFIG_SYS_SPL_MALLOC_SIZE SZ_16M
51 #ifdef CONFIG_SYS_K3_SPL_ATF
52 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "tispl.bin"
55 #define CONFIG_SPL_MAX_SIZE CONFIG_SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE
57 #define CONFIG_SYS_BOOTM_LEN SZ_64M
58 #define CONFIG_CQSPI_REF_CLK 133333333
60 /* HyperFlash related configuration */
61 #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1
63 /* U-Boot general configuration */
64 #define EXTRA_ENV_J721E_BOARD_SETTINGS \
65 "default_device_tree=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
66 "findfdt=setenv fdtfile ${default_device_tree}\0" \
67 "loadaddr=0x80080000\0" \
68 "fdtaddr=0x82000000\0" \
69 "overlayaddr=0x83000000\0" \
71 "console=ttyS2,115200n8\0" \
72 "args_all=setenv optargs earlycon=ns16550a,mmio32,0x02800000\0" \
73 "run_kern=booti ${loadaddr} ${rd_spec} ${fdtaddr}\0"
75 /* U-Boot MMC-specific configuration */
76 #define EXTRA_ENV_J721E_BOARD_SETTINGS_MMC \
82 "init_mmc=run args_all args_mmc\0" \
83 "get_fdt_mmc=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \
85 "fdt address ${fdtaddr};" \
86 "fdt resize 0x100000;" \
87 "for overlay in $name_overlays;" \
89 "load mmc ${bootpart} ${overlayaddr} ${bootdir}/${overlay} && " \
90 "fdt apply ${overlayaddr};" \
92 "get_kern_mmc=load mmc ${bootpart} ${loadaddr} " \
93 "${bootdir}/${name_kern}\0"
98 #define DEFAULT_RPROCS "" \
99 "3 /lib/firmware/j7-main-r5f0_1-fw " \
100 "4 /lib/firmware/j7-main-r5f1_0-fw " \
101 "6 /lib/firmware/j7-c66_0-fw " \
102 "7 /lib/firmware/j7-c66_1-fw " \
103 "8 /lib/firmware/j7-c71_0-fw "
105 /* Incorporate settings into the U-Boot environment */
106 #define CONFIG_EXTRA_ENV_SETTINGS \
107 DEFAULT_MMC_TI_ARGS \
108 EXTRA_ENV_J721E_BOARD_SETTINGS \
109 EXTRA_ENV_J721E_BOARD_SETTINGS_MMC \
110 EXTRA_ENV_RPROC_SETTINGS \
113 /* Now for the remaining common defines */
114 #include <configs/ti_armv7_common.h>
116 #endif /* __CONFIG_J721E_EVM_H */