include/configs/hrcon.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * (C) Copyright 2014
   4  * Dirk Eibach,  Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
   5  *
   6  */
   7
   8 #ifndef __CONFIG_H
   9 #define __CONFIG_H
  10
  11 /*
  12  * High Level Configuration Options
  13  */
  14 #define CONFIG_E300             1 /* E300 family */
  15
  16 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC83xx_ESDHC_ADDR
  17
  18 /*
  19  * SERDES
  20  */
  21 #define CONFIG_FSL_SERDES
  22 #define CONFIG_FSL_SERDES1      0xe3000
  23
  24 /*
  25  * DDR Setup
  26  */
  27 #define CONFIG_SYS_SDRAM_BASE           0x00000000 /* DDR is system memory */
  28 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
  29 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
  30                                 | DDRCDR_PZ_LOZ \
  31                                 | DDRCDR_NZ_LOZ \
  32                                 | DDRCDR_ODT \
  33                                 | DDRCDR_Q_DRN)
  34                                 /* 0x7b880001 */
  35 /*
  36  * Manually set up DDR parameters
  37  * consist of one chip NT5TU64M16HG from NANYA
  38  */
  39
  40 #define CONFIG_SYS_DDR_SIZE             128 /* MB */
  41
  42 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
  43 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
  44                                 | CSCONFIG_ODT_RD_NEVER \
  45                                 | CSCONFIG_ODT_WR_ONLY_CURRENT \
  46                                 | CSCONFIG_BANK_BIT_3 \
  47                                 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
  48                                 /* 0x80010102 */
  49 #define CONFIG_SYS_DDR_TIMING_3 0
  50 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
  51                                 | (0 << TIMING_CFG0_WRT_SHIFT) \
  52                                 | (0 << TIMING_CFG0_RRT_SHIFT) \
  53                                 | (0 << TIMING_CFG0_WWT_SHIFT) \
  54                                 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
  55                                 | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
  56                                 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
  57                                 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
  58                                 /* 0x00260802 */
  59 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
  60                                 | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
  61                                 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
  62                                 | (7 << TIMING_CFG1_CASLAT_SHIFT) \
  63                                 | (9 << TIMING_CFG1_REFREC_SHIFT) \
  64                                 | (2 << TIMING_CFG1_WRREC_SHIFT) \
  65                                 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
  66                                 | (2 << TIMING_CFG1_WRTORD_SHIFT))
  67                                 /* 0x26279222 */
  68 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
  69                                 | (4 << TIMING_CFG2_CPO_SHIFT) \
  70                                 | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
  71                                 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
  72                                 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
  73                                 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
  74                                 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
  75                                 /* 0x021848c5 */
  76 #define CONFIG_SYS_DDR_INTERVAL ((0x0824 << SDRAM_INTERVAL_REFINT_SHIFT) \
  77                                 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
  78                                 /* 0x08240100 */
  79 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SREN \
  80                                 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
  81                                 | SDRAM_CFG_DBW_16)
  82                                 /* 0x43100000 */
  83
  84 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000 /* 1 posted refresh */
  85 #define CONFIG_SYS_DDR_MODE             ((0x0440 << SDRAM_MODE_ESD_SHIFT) \
  86                                 | (0x0242 << SDRAM_MODE_SD_SHIFT))
  87                                 /* ODT 150ohm CL=4, AL=0 on SDRAM */
  88 #define CONFIG_SYS_DDR_MODE2            0x00000000
  89
  90 /*
  91  * Memory test
  92  */
  93
  94 /*
  95  * The reserved memory
  96  */
  97 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  98
  99 #define CONFIG_SYS_MONITOR_LEN  (384 * 1024) /* Reserve 384 kB for Mon */
 100 #define CONFIG_SYS_MALLOC_LEN   (512 * 1024) /* Reserved for malloc */
 101
 102 /*
 103  * Initial RAM Base Address Setup
 104  */
 105 #define CONFIG_SYS_INIT_RAM_LOCK        1
 106 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
 107 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* Size of used area in RAM */
 108 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 109         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 110
 111 /*
 112  * FLASH on the Local Bus
 113  */
 114 #if 1
 115 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
 116 #define CONFIG_FLASH_CFI_LEGACY
 117 #define CONFIG_SYS_FLASH_LEGACY_512Kx16
 118 #endif
 119
 120 #define CONFIG_SYS_FLASH_BASE           0xFE000000 /* FLASH base address */
 121 #define CONFIG_SYS_FLASH_SIZE           8 /* FLASH size is up to 8M */
 122
 123
 124 #define CONFIG_SYS_MAX_FLASH_BANKS      1 /* number of banks */
 125 #define CONFIG_SYS_MAX_FLASH_SECT       135
 126
 127 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000 /* Flash Erase Timeout (ms) */
 128 #define CONFIG_SYS_FLASH_WRITE_TOUT     500 /* Flash Write Timeout (ms) */
 129
 130 #define CONFIG_SYS_FPGA_DONE(k)         0x0010
 131
 132 #define CONFIG_SYS_FPGA_COUNT           1
 133
 134 #define CONFIG_SYS_MCLINK_MAX           3
 135
 136 #define CONFIG_SYS_FPGA_PTR \
 137         { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, NULL, NULL, NULL }
 138
 139 /*
 140  * Serial Port
 141  */
 142 #define CONFIG_SYS_NS16550_SERIAL
 143 #define CONFIG_SYS_NS16550_REG_SIZE     1
 144 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 145
 146 #define CONFIG_SYS_BAUDRATE_TABLE  \
 147         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 148
 149 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
 150 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
 151
 152 /* Pass open firmware flat tree */
 153
 154 /* I2C */
 155 #define CONFIG_SYS_I2C
 156 #define CONFIG_SYS_I2C_FSL
 157 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 158 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 159 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 160
 161 #define CONFIG_PCA953X                  /* NXP PCA9554 */
 162 #define CONFIG_PCA9698                  /* NXP PCA9698 */
 163
 164 #define CONFIG_SYS_I2C_IHS
 165 #define CONFIG_SYS_I2C_IHS_CH0
 166 #define CONFIG_SYS_I2C_IHS_SPEED_0              50000
 167 #define CONFIG_SYS_I2C_IHS_SLAVE_0              0x7F
 168 #define CONFIG_SYS_I2C_IHS_CH1
 169 #define CONFIG_SYS_I2C_IHS_SPEED_1              50000
 170 #define CONFIG_SYS_I2C_IHS_SLAVE_1              0x7F
 171 #define CONFIG_SYS_I2C_IHS_CH2
 172 #define CONFIG_SYS_I2C_IHS_SPEED_2              50000
 173 #define CONFIG_SYS_I2C_IHS_SLAVE_2              0x7F
 174 #define CONFIG_SYS_I2C_IHS_CH3
 175 #define CONFIG_SYS_I2C_IHS_SPEED_3              50000
 176 #define CONFIG_SYS_I2C_IHS_SLAVE_3              0x7F
 177
 178 #ifdef CONFIG_HRCON_DH
 179 #define CONFIG_SYS_I2C_IHS_DUAL
 180 #define CONFIG_SYS_I2C_IHS_CH0_1
 181 #define CONFIG_SYS_I2C_IHS_SPEED_0_1            50000
 182 #define CONFIG_SYS_I2C_IHS_SLAVE_0_1            0x7F
 183 #define CONFIG_SYS_I2C_IHS_CH1_1
 184 #define CONFIG_SYS_I2C_IHS_SPEED_1_1            50000
 185 #define CONFIG_SYS_I2C_IHS_SLAVE_1_1            0x7F
 186 #define CONFIG_SYS_I2C_IHS_CH2_1
 187 #define CONFIG_SYS_I2C_IHS_SPEED_2_1            50000
 188 #define CONFIG_SYS_I2C_IHS_SLAVE_2_1            0x7F
 189 #define CONFIG_SYS_I2C_IHS_CH3_1
 190 #define CONFIG_SYS_I2C_IHS_SPEED_3_1            50000
 191 #define CONFIG_SYS_I2C_IHS_SLAVE_3_1            0x7F
 192 #endif
 193
 194 /*
 195  * Software (bit-bang) I2C driver configuration
 196  */
 197 #define CONFIG_SYS_I2C_SOFT
 198 #define CONFIG_SYS_I2C_SOFT_SPEED               50000
 199 #define CONFIG_SYS_I2C_SOFT_SLAVE               0x7F
 200 #define I2C_SOFT_DECLARATIONS2
 201 #define CONFIG_SYS_I2C_SOFT_SPEED_2             50000
 202 #define CONFIG_SYS_I2C_SOFT_SLAVE_2             0x7F
 203 #define I2C_SOFT_DECLARATIONS3
 204 #define CONFIG_SYS_I2C_SOFT_SPEED_3             50000
 205 #define CONFIG_SYS_I2C_SOFT_SLAVE_3             0x7F
 206 #define I2C_SOFT_DECLARATIONS4
 207 #define CONFIG_SYS_I2C_SOFT_SPEED_4             50000
 208 #define CONFIG_SYS_I2C_SOFT_SLAVE_4             0x7F
 209 #define I2C_SOFT_DECLARATIONS5
 210 #define CONFIG_SYS_I2C_SOFT_SPEED_5             50000
 211 #define CONFIG_SYS_I2C_SOFT_SLAVE_5             0x7F
 212 #define I2C_SOFT_DECLARATIONS6
 213 #define CONFIG_SYS_I2C_SOFT_SPEED_6             50000
 214 #define CONFIG_SYS_I2C_SOFT_SLAVE_6             0x7F
 215 #define I2C_SOFT_DECLARATIONS7
 216 #define CONFIG_SYS_I2C_SOFT_SPEED_7             50000
 217 #define CONFIG_SYS_I2C_SOFT_SLAVE_7             0x7F
 218 #define I2C_SOFT_DECLARATIONS8
 219 #define CONFIG_SYS_I2C_SOFT_SPEED_8             50000
 220 #define CONFIG_SYS_I2C_SOFT_SLAVE_8             0x7F
 221
 222 #ifdef CONFIG_HRCON_DH
 223 #define I2C_SOFT_DECLARATIONS9
 224 #define CONFIG_SYS_I2C_SOFT_SPEED_9             50000
 225 #define CONFIG_SYS_I2C_SOFT_SLAVE_9             0x7F
 226 #define I2C_SOFT_DECLARATIONS10
 227 #define CONFIG_SYS_I2C_SOFT_SPEED_10            50000
 228 #define CONFIG_SYS_I2C_SOFT_SLAVE_10            0x7F
 229 #define I2C_SOFT_DECLARATIONS11
 230 #define CONFIG_SYS_I2C_SOFT_SPEED_11            50000
 231 #define CONFIG_SYS_I2C_SOFT_SLAVE_11            0x7F
 232 #define I2C_SOFT_DECLARATIONS12
 233 #define CONFIG_SYS_I2C_SOFT_SPEED_12            50000
 234 #define CONFIG_SYS_I2C_SOFT_SLAVE_12            0x7F
 235 #endif
 236
 237 #ifdef CONFIG_HRCON_DH
 238 #define CONFIG_SYS_ICS8N3QV01_I2C               {13, 14, 15, 16, 17, 18, 19, 20}
 239 #define CONFIG_SYS_DP501_I2C                    {1, 3, 5, 7, 2, 4, 6, 8}
 240 #define CONFIG_HRCON_FANS                       { {10, 0x4c}, {11, 0x4c}, \
 241                                                   {12, 0x4c} }
 242 #else
 243 #define CONFIG_SYS_ICS8N3QV01_I2C               {9, 10, 11, 12}
 244 #define CONFIG_SYS_DP501_I2C                    {1, 2, 3, 4}
 245 #define CONFIG_HRCON_FANS                       { {6, 0x4c}, {7, 0x4c}, \
 246                                                   {8, 0x4c} }
 247 #endif
 248
 249 #ifndef __ASSEMBLY__
 250 void fpga_gpio_set(unsigned int bus, int pin);
 251 void fpga_gpio_clear(unsigned int bus, int pin);
 252 int fpga_gpio_get(unsigned int bus, int pin);
 253 void fpga_control_set(unsigned int bus, int pin);
 254 void fpga_control_clear(unsigned int bus, int pin);
 255 #endif
 256
 257 #define I2C_SDA_GPIO    ((I2C_ADAP_HWNR > 3) ? 0x0040 : 0x0200)
 258 #define I2C_SCL_GPIO    ((I2C_ADAP_HWNR > 3) ? 0x0020 : 0x0100)
 259 #define I2C_FPGA_IDX    (I2C_ADAP_HWNR % 4)
 260
 261 #ifdef CONFIG_HRCON_DH
 262 #define I2C_ACTIVE \
 263         do { \
 264                 if (I2C_ADAP_HWNR > 7) \
 265                         fpga_control_set(I2C_FPGA_IDX, 0x0004); \
 266                 else \
 267                         fpga_control_clear(I2C_FPGA_IDX, 0x0004); \
 268         } while (0)
 269 #else
 270 #define I2C_ACTIVE      { }
 271 #endif
 272 #define I2C_TRISTATE    { }
 273 #define I2C_READ \
 274         (fpga_gpio_get(I2C_FPGA_IDX, I2C_SDA_GPIO) ? 1 : 0)
 275 #define I2C_SDA(bit) \
 276         do { \
 277                 if (bit) \
 278                         fpga_gpio_set(I2C_FPGA_IDX, I2C_SDA_GPIO); \
 279                 else \
 280                         fpga_gpio_clear(I2C_FPGA_IDX, I2C_SDA_GPIO); \
 281         } while (0)
 282 #define I2C_SCL(bit) \
 283         do { \
 284                 if (bit) \
 285                         fpga_gpio_set(I2C_FPGA_IDX, I2C_SCL_GPIO); \
 286                 else \
 287                         fpga_gpio_clear(I2C_FPGA_IDX, I2C_SCL_GPIO); \
 288         } while (0)
 289 #define I2C_DELAY       udelay(25)      /* 1/4 I2C clock duration */
 290
 291 /*
 292  * Software (bit-bang) MII driver configuration
 293  */
 294 #define CONFIG_BITBANGMII_MULTI
 295
 296 /*
 297  * OSD Setup
 298  */
 299 #define CONFIG_SYS_OSD_SCREENS          1
 300 #define CONFIG_SYS_DP501_DIFFERENTIAL
 301 #define CONFIG_SYS_DP501_VCAPCTRL0      0x01 /* DDR mode 0, DE for H/VSYNC */
 302
 303 #ifdef CONFIG_HRCON_DH
 304 #define CONFIG_SYS_OSD_DH
 305 #endif
 306
 307 /*
 308  * General PCI
 309  * Addresses are mapped 1-1.
 310  */
 311 #define CONFIG_SYS_PCIE1_BASE           0xA0000000
 312 #define CONFIG_SYS_PCIE1_MEM_BASE       0xA0000000
 313 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xA0000000
 314 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000
 315 #define CONFIG_SYS_PCIE1_CFG_BASE       0xB0000000
 316 #define CONFIG_SYS_PCIE1_CFG_SIZE       0x01000000
 317 #define CONFIG_SYS_PCIE1_IO_BASE        0x00000000
 318 #define CONFIG_SYS_PCIE1_IO_PHYS        0xB1000000
 319 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00800000
 320
 321 /* enable PCIE clock */
 322 #define CONFIG_SYS_SCCR_PCIEXP1CM       1
 323
 324 #define CONFIG_PCI_INDIRECT_BRIDGE
 325 #define CONFIG_PCIE
 326
 327 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957   /* Freescale */
 328 #define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1
 329
 330 /*
 331  * TSEC
 332  */
 333 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 334 #define CONFIG_SYS_TSEC1        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
 335
 336 /*
 337  * TSEC ethernet configuration
 338  */
 339 #define CONFIG_TSEC1
 340 #define CONFIG_TSEC1_NAME       "eTSEC0"
 341 #define TSEC1_PHY_ADDR          1
 342 #define TSEC1_PHYIDX            0
 343 #define TSEC1_FLAGS             TSEC_GIGABIT
 344
 345 /* Options are: eTSEC[0-1] */
 346 #define CONFIG_ETHPRIME         "eTSEC0"
 347
 348 /*
 349  * Environment
 350  */
 351
 352 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 353 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 354
 355 /*
 356  * Command line configuration.
 357  */
 358
 359 /*
 360  * Miscellaneous configurable options
 361  */
 362 #define CONFIG_SYS_LOAD_ADDR            0x2000000 /* default load address */
 363 #define CONFIG_SYS_HZ           1000    /* decrementer freq: 1ms ticks */
 364
 365 #define CONFIG_SYS_CBSIZE       1024 /* Console I/O Buffer Size */
 366
 367 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 368
 369 /*
 370  * For booting Linux, the board info and command line data
 371  * have to be in the first 256 MB of memory, since this is
 372  * the maximum mapped by the Linux kernel during initialization.
 373  */
 374 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20) /* Initial Memory map for Linux */
 375
 376 /*
 377  * Environment Configuration
 378  */
 379
 380 #define CONFIG_ENV_OVERWRITE
 381
 382 #if defined(CONFIG_TSEC_ENET)
 383 #define CONFIG_HAS_ETH0
 384 #endif
 385
 386 #define CONFIG_LOADADDR 800000  /* default location for tftp and bootm */
 387
 388
 389 #define CONFIG_HOSTNAME         "hrcon"
 390 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 391 #define CONFIG_BOOTFILE         "uImage"
 392
 393 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 394         "netdev=eth0\0"                                                 \
 395         "consoledev=ttyS1\0"                                            \
 396         "u-boot=u-boot.bin\0"                                           \
 397         "kernel_addr=1000000\0"                                 \
 398         "fdt_addr=C00000\0"                                             \
 399         "fdtfile=hrcon.dtb\0"                           \
 400         "load=tftp ${loadaddr} ${u-boot}\0"                             \
 401         "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE)      \
 402                 " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
 403                 " +${filesize};cp.b ${fileaddr} "                       \
 404                 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0"   \
 405         "upd=run load update\0"                                         \
 406
 407 #define CONFIG_NFSBOOTCOMMAND                                           \
 408         "setenv bootargs root=/dev/nfs rw "                             \
 409         "nfsroot=$serverip:$rootpath "                                  \
 410         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 411         "console=$consoledev,$baudrate $othbootargs;"                   \
 412         "tftp ${kernel_addr} $bootfile;"                                \
 413         "tftp ${fdt_addr} $fdtfile;"                                    \
 414         "bootm ${kernel_addr} - ${fdt_addr}"
 415
 416 #define CONFIG_MMCBOOTCOMMAND                                           \
 417         "setenv bootargs root=/dev/mmcblk0p3 rw rootwait "              \
 418         "console=$consoledev,$baudrate $othbootargs;"                   \
 419         "ext2load mmc 0:2 ${kernel_addr} $bootfile;"                    \
 420         "ext2load mmc 0:2 ${fdt_addr} $fdtfile;"                        \
 421         "bootm ${kernel_addr} - ${fdt_addr}"
 422
 423 #define CONFIG_BOOTCOMMAND              CONFIG_MMCBOOTCOMMAND
 424
 425 #endif  /* __CONFIG_H */