include/configs/eb_cpu5282.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Configuation settings for the BuS EB+CPU5283 boards (aka EB+MCF-EV123)
   4  *
   5  * (C) Copyright 2005-2009 BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de>
   6  */
   7
   8 #ifndef _CONFIG_EB_CPU5282_H_
   9 #define _CONFIG_EB_CPU5282_H_
  10
  11 #undef CONFIG_SYS_HALT_BEFOR_RAM_JUMP
  12
  13 /*----------------------------------------------------------------------*
  14  * High Level Configuration Options (easy to change)                    *
  15  *----------------------------------------------------------------------*/
  16
  17 #define CONFIG_MCFUART
  18 #define CONFIG_SYS_UART_PORT            (0)
  19
  20 #undef  CONFIG_MONITOR_IS_IN_RAM                /* starts uboot direct */
  21
  22 #define CONFIG_BOOTCOMMAND "printenv"
  23
  24 /*----------------------------------------------------------------------*
  25  * Options                                                              *
  26  *----------------------------------------------------------------------*/
  27
  28 #define CONFIG_BOOT_RETRY_TIME  -1
  29 #define CONFIG_RESET_TO_RETRY
  30 #define CONFIG_SPLASH_SCREEN
  31
  32 #define CONFIG_HW_WATCHDOG
  33
  34 #define STATUS_LED_ACTIVE               0
  35
  36 /*----------------------------------------------------------------------*
  37  * Configuration for environment                                        *
  38  * Environment is in the second sector of the first 256k of flash       *
  39  *----------------------------------------------------------------------*/
  40
  41 /*
  42  * BOOTP options
  43  */
  44 #define CONFIG_BOOTP_BOOTFILESIZE
  45
  46 #define CONFIG_MCFTMR
  47
  48 #define CONFIG_SYS_CBSIZE       1024    /* Console I/O Buffer Size      */
  49 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
  50
  51 #define CONFIG_SYS_LOAD_ADDR            0x20000
  52
  53 /*#define CONFIG_SYS_DRAM_TEST          1 */
  54 #undef CONFIG_SYS_DRAM_TEST
  55
  56 /*----------------------------------------------------------------------*
  57  * Clock and PLL Configuration                                          *
  58  *----------------------------------------------------------------------*/
  59 #define CONFIG_SYS_CLK                  80000000      /* 8MHz * 8 */
  60
  61 /* PLL Configuration: Ext Clock * 8 (see table 9-4 of MCF user manual) */
  62
  63 #define CONFIG_SYS_MFD          0x02    /* PLL Multiplication Factor Devider */
  64 #define CONFIG_SYS_RFD          0x00    /* PLL Reduce Frecuency Devider */
  65
  66 /*----------------------------------------------------------------------*
  67  * Network                                                              *
  68  *----------------------------------------------------------------------*/
  69
  70 #ifdef CONFIG_MCFFEC
  71 #define CONFIG_MII_INIT                 1
  72 #define CONFIG_SYS_DISCOVER_PHY
  73 #define CONFIG_SYS_RX_ETH_BUFFER        8
  74 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  75 #define CONFIG_OVERWRITE_ETHADDR_ONCE
  76 #endif
  77
  78 /*-------------------------------------------------------------------------
  79  * Low Level Configuration Settings
  80  * (address mappings, register initial values, etc.)
  81  * You should know what you are doing if you make changes here.
  82  *-----------------------------------------------------------------------*/
  83
  84 #define CONFIG_SYS_MBAR                 0x40000000
  85
  86 /*-----------------------------------------------------------------------
  87  * Definitions for initial stack pointer and data area (in DPRAM)
  88  *-----------------------------------------------------------------------*/
  89
  90 #define CONFIG_SYS_INIT_RAM_ADDR        0x20000000
  91 #define CONFIG_SYS_INIT_RAM_SIZE        0x10000
  92 #define CONFIG_SYS_GBL_DATA_OFFSET      \
  93         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  94 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
  95
  96 /*-----------------------------------------------------------------------
  97  * Start addresses for the final memory configuration
  98  * (Set up by the startup code)
  99  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 100  */
 101 #define CONFIG_SYS_SDRAM_BASE0          0x00000000
 102 #define CONFIG_SYS_SDRAM_SIZE0          16      /* SDRAM size in MB */
 103
 104 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_SDRAM_BASE0
 105 #define CONFIG_SYS_SDRAM_SIZE           CONFIG_SYS_SDRAM_SIZE0
 106
 107 #define CONFIG_SYS_MONITOR_LEN          0x20000
 108 #define CONFIG_SYS_MALLOC_LEN           (4 * 1024 * 1024)
 109 #define CONFIG_SYS_BOOTPARAMS_LEN       64*1024
 110
 111 /*
 112  * For booting Linux, the board info and command line data
 113  * have to be in the first 8 MB of memory, since this is
 114  * the maximum mapped by the Linux kernel during initialization ??
 115  */
 116 #define CONFIG_SYS_BOOTMAPSZ    (8 << 20) /* Initial Memory map for Linux */
 117
 118 /*-----------------------------------------------------------------------
 119  * FLASH organization
 120  */
 121 #define CONFIG_FLASH_SHOW_PROGRESS      45
 122
 123 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_CS0_BASE
 124 #define CONFIG_SYS_INT_FLASH_BASE       0xF0000000
 125 #define CONFIG_SYS_INT_FLASH_ENABLE     0x21
 126
 127 #define CONFIG_SYS_MAX_FLASH_SECT       128
 128 #define CONFIG_SYS_MAX_FLASH_BANKS      1
 129 #define CONFIG_SYS_FLASH_ERASE_TOUT     10000000
 130
 131 #define CONFIG_SYS_FLASH_SIZE           16*1024*1024
 132 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
 133
 134 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
 135
 136 /*-----------------------------------------------------------------------
 137  * Cache Configuration
 138  */
 139 #define CONFIG_SYS_CACHELINE_SIZE       16
 140
 141 #define ICACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 142                                          CONFIG_SYS_INIT_RAM_SIZE - 8)
 143 #define DCACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 144                                          CONFIG_SYS_INIT_RAM_SIZE - 4)
 145 #define CONFIG_SYS_ICACHE_INV           (CF_CACR_CINV + CF_CACR_DCM)
 146 #define CONFIG_SYS_CACHE_ACR0           (CONFIG_SYS_SDRAM_BASE | \
 147                                          CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
 148                                          CF_ACR_EN | CF_ACR_SM_ALL)
 149 #define CONFIG_SYS_CACHE_ICACR          (CF_CACR_CENB | CF_CACR_DISD | \
 150                                          CF_CACR_CEIB | CF_CACR_DBWE | \
 151                                          CF_CACR_EUSP)
 152
 153 /*-----------------------------------------------------------------------
 154  * Memory bank definitions
 155  */
 156
 157 #define CONFIG_SYS_CS0_BASE             0xFF000000
 158 #define CONFIG_SYS_CS0_CTRL             0x00001980
 159 #define CONFIG_SYS_CS0_MASK             0x00FF0001
 160
 161 #define CONFIG_SYS_CS2_BASE             0xE0000000
 162 #define CONFIG_SYS_CS2_CTRL             0x00001980
 163 #define CONFIG_SYS_CS2_MASK             0x000F0001
 164
 165 #define CONFIG_SYS_CS3_BASE             0xE0100000
 166 #define CONFIG_SYS_CS3_CTRL             0x00001980
 167 #define CONFIG_SYS_CS3_MASK             0x000F0001
 168
 169 /*-----------------------------------------------------------------------
 170  * Port configuration
 171  */
 172 #define CONFIG_SYS_PACNT                0x0000000       /* Port A D[31:24] */
 173 #define CONFIG_SYS_PADDR                0x0000000
 174 #define CONFIG_SYS_PADAT                0x0000000
 175
 176 #define CONFIG_SYS_PBCNT                0x0000000       /* Port B D[23:16] */
 177 #define CONFIG_SYS_PBDDR                0x0000000
 178 #define CONFIG_SYS_PBDAT                0x0000000
 179
 180 #define CONFIG_SYS_PCCNT                0x0000000       /* Port C D[15:08] */
 181 #define CONFIG_SYS_PCDDR                0x0000000
 182 #define CONFIG_SYS_PCDAT                0x0000000
 183
 184 #define CONFIG_SYS_PDCNT                0x0000000       /* Port D D[07:00] */
 185 #define CONFIG_SYS_PCDDR                0x0000000
 186 #define CONFIG_SYS_PCDAT                0x0000000
 187
 188 #define CONFIG_SYS_PASPAR               0x0F0F
 189 #define CONFIG_SYS_PEHLPAR              0xC0
 190 #define CONFIG_SYS_PUAPAR               0x0F
 191 #define CONFIG_SYS_DDRUA                0x05
 192 #define CONFIG_SYS_PJPAR                0xFF
 193
 194 /*-----------------------------------------------------------------------
 195  * I2C
 196  */
 197
 198 #define CONFIG_SYS_I2C
 199 #define CONFIG_SYS_I2C_FSL
 200
 201 #define CONFIG_SYS_FSL_I2C_OFFSET       0x00000300
 202 #define CONFIG_SYS_IMMR                 CONFIG_SYS_MBAR
 203
 204 #define CONFIG_SYS_FSL_I2C_SPEED        100000
 205 #define CONFIG_SYS_FSL_I2C_SLAVE        0
 206
 207 #ifdef CONFIG_CMD_DATE
 208 #define CONFIG_RTC_DS1338
 209 #define CONFIG_I2C_RTC_ADDR             0x68
 210 #endif
 211
 212 /*-----------------------------------------------------------------------
 213  * VIDEO configuration
 214  */
 215
 216 #ifdef CONFIG_VIDEO
 217 #define CONFIG_VIDEO_VCXK                       1
 218
 219 #define CONFIG_SYS_VCXK_DEFAULT_LINEALIGN       2
 220 #define CONFIG_SYS_VCXK_DOUBLEBUFFERED          1
 221 #define CONFIG_SYS_VCXK_BASE                    CONFIG_SYS_CS2_BASE
 222
 223 #define CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT        MCFGPTB_GPTPORT
 224 #define CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR         MCFGPTB_GPTDDR
 225 #define CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN         0x0001
 226
 227 #define CONFIG_SYS_VCXK_ENABLE_PORT             MCFGPTB_GPTPORT
 228 #define CONFIG_SYS_VCXK_ENABLE_DDR              MCFGPTB_GPTDDR
 229 #define CONFIG_SYS_VCXK_ENABLE_PIN              0x0002
 230
 231 #define CONFIG_SYS_VCXK_REQUEST_PORT            MCFGPTB_GPTPORT
 232 #define CONFIG_SYS_VCXK_REQUEST_DDR             MCFGPTB_GPTDDR
 233 #define CONFIG_SYS_VCXK_REQUEST_PIN             0x0004
 234
 235 #define CONFIG_SYS_VCXK_INVERT_PORT             MCFGPIO_PORTE
 236 #define CONFIG_SYS_VCXK_INVERT_DDR              MCFGPIO_DDRE
 237 #define CONFIG_SYS_VCXK_INVERT_PIN              MCFGPIO_PORT2
 238
 239 #endif /* CONFIG_VIDEO */
 240 #endif  /* _CONFIG_M5282EVB_H */
 241 /*---------------------------------------------------------------------*/