include/configs/cm_t35.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * (C) Copyright 2011 CompuLab, Ltd.
   4  * Mike Rapoport <mike@compulab.co.il>
   5  * Igor Grinberg <grinberg@compulab.co.il>
   6  *
   7  * Based on omap3_beagle.h
   8  * (C) Copyright 2006-2008
   9  * Texas Instruments.
  10  * Richard Woodruff <r-woodruff2@ti.com>
  11  * Syed Mohammed Khasim <x0khasim@ti.com>
  12  *
  13  * Configuration settings for the CompuLab CM-T35 and CM-T3730 boards
  14  */
  15
  16 #ifndef __CONFIG_H
  17 #define __CONFIG_H
  18
  19 #define CONFIG_SYS_CACHELINE_SIZE       64
  20
  21 /*
  22  * High Level Configuration Options
  23  */
  24 #define CONFIG_CM_T3X   /* working with CM-T35 and CM-T3730 */
  25
  26 #include <asm/arch/cpu.h>               /* get chip and board defs */
  27 #include <asm/arch/omap.h>
  28
  29 /* Clock Defines */
  30 #define V_OSCK                  26000000        /* Clock output from T2 */
  31 #define V_SCLK                  (V_OSCK >> 1)
  32
  33 #define CONFIG_CMDLINE_TAG              /* enable passing of ATAGs */
  34 #define CONFIG_SETUP_MEMORY_TAGS
  35 #define CONFIG_INITRD_TAG
  36 #define CONFIG_REVISION_TAG
  37 #define CONFIG_SERIAL_TAG
  38
  39 /*
  40  * Size of malloc() pool
  41  */
  42                                         /* Sector */
  43 #define CONFIG_SYS_MALLOC_LEN   (CONFIG_ENV_SIZE + (128 << 10))
  44
  45 /*
  46  * Hardware drivers
  47  */
  48
  49 /*
  50  * NS16550 Configuration
  51  */
  52 #define V_NS16550_CLK                   48000000        /* 48MHz (APLL96/2) */
  53
  54 #define CONFIG_SYS_NS16550_SERIAL
  55 #define CONFIG_SYS_NS16550_REG_SIZE     (-4)
  56 #define CONFIG_SYS_NS16550_CLK          V_NS16550_CLK
  57
  58 /*
  59  * select serial console configuration
  60  */
  61 #define CONFIG_SYS_NS16550_COM3         OMAP34XX_UART3
  62
  63 /* allow to overwrite serial and ethaddr */
  64 #define CONFIG_ENV_OVERWRITE
  65 #define CONFIG_SYS_BAUDRATE_TABLE       {4800, 9600, 19200, 38400, 57600,\
  66                                         115200}
  67
  68 /* USB device configuration */
  69 #define CONFIG_USB_DEVICE
  70 #define CONFIG_USB_TTY
  71
  72 /* commands to include */
  73
  74 #define CONFIG_SYS_I2C
  75 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50
  76 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
  77 #define CONFIG_SYS_I2C_EEPROM_BUS       0
  78 #define CONFIG_I2C_MULTI_BUS
  79
  80 /*
  81  * TWL4030
  82  */
  83
  84 /*
  85  * Board NAND Info.
  86  */
  87 #define CONFIG_SYS_NAND_BASE            NAND_BASE       /* physical address */
  88                                                         /* to access nand at */
  89                                                         /* CS0 */
  90 #define CONFIG_SYS_MAX_NAND_DEVICE      1               /* Max number of NAND */
  91                                                         /* devices */
  92
  93 /* Environment information */
  94 #define CONFIG_EXTRA_ENV_SETTINGS \
  95         "loadaddr=0x82000000\0" \
  96         "usbtty=cdc_acm\0" \
  97         "console=ttyO2,115200n8\0" \
  98         "mpurate=500\0" \
  99         "vram=12M\0" \
 100         "dvimode=1024x768MR-16@60\0" \
 101         "defaultdisplay=dvi\0" \
 102         "mmcdev=0\0" \
 103         "mmcroot=/dev/mmcblk0p2 rw\0" \
 104         "mmcrootfstype=ext4 rootwait\0" \
 105         "nandroot=/dev/mtdblock4 rw\0" \
 106         "nandrootfstype=ubifs\0" \
 107         "mmcargs=setenv bootargs console=${console} " \
 108                 "mpurate=${mpurate} " \
 109                 "vram=${vram} " \
 110                 "omapfb.mode=dvi:${dvimode} " \
 111                 "omapdss.def_disp=${defaultdisplay} " \
 112                 "root=${mmcroot} " \
 113                 "rootfstype=${mmcrootfstype}\0" \
 114         "nandargs=setenv bootargs console=${console} " \
 115                 "mpurate=${mpurate} " \
 116                 "vram=${vram} " \
 117                 "omapfb.mode=dvi:${dvimode} " \
 118                 "omapdss.def_disp=${defaultdisplay} " \
 119                 "root=${nandroot} " \
 120                 "rootfstype=${nandrootfstype}\0" \
 121         "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
 122         "bootscript=echo Running bootscript from mmc ...; " \
 123                 "source ${loadaddr}\0" \
 124         "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
 125         "mmcboot=echo Booting from mmc ...; " \
 126                 "run mmcargs; " \
 127                 "bootm ${loadaddr}\0" \
 128         "nandboot=echo Booting from nand ...; " \
 129                 "run nandargs; " \
 130                 "nand read ${loadaddr} 2a0000 400000; " \
 131                 "bootm ${loadaddr}\0" \
 132
 133 #define CONFIG_BOOTCOMMAND \
 134         "mmc dev ${mmcdev}; if mmc rescan; then " \
 135                 "if run loadbootscript; then " \
 136                         "run bootscript; " \
 137                 "else " \
 138                         "if run loaduimage; then " \
 139                                 "run mmcboot; " \
 140                         "else run nandboot; " \
 141                         "fi; " \
 142                 "fi; " \
 143         "else run nandboot; fi"
 144
 145 /*
 146  * Miscellaneous configurable options
 147  */
 148 #define CONFIG_TIMESTAMP
 149 #define CONFIG_SYS_AUTOLOAD             "no"
 150
 151 #define CONFIG_SYS_MEMTEST_START        (OMAP34XX_SDRC_CS0)     /* memtest */
 152                                                                 /* works on */
 153 #define CONFIG_SYS_MEMTEST_END          (OMAP34XX_SDRC_CS0 + \
 154                                         0x01F00000) /* 31MB */
 155
 156 #define CONFIG_SYS_LOAD_ADDR            (OMAP34XX_SDRC_CS0)     /* default */
 157                                                         /* load address */
 158
 159 /*
 160  * OMAP3 has 12 GP timers, they can be driven by the system clock
 161  * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
 162  * This rate is divided by a local divisor.
 163  */
 164 #define CONFIG_SYS_TIMERBASE            (OMAP34XX_GPT2)
 165 #define CONFIG_SYS_PTV                  2       /* Divisor: 2^(PTV+1) => 8 */
 166
 167 /*-----------------------------------------------------------------------
 168  * Physical Memory Map
 169  */
 170 #define PHYS_SDRAM_1            OMAP34XX_SDRC_CS0
 171
 172 /*-----------------------------------------------------------------------
 173  * FLASH and environment organization
 174  */
 175
 176 /* **** PISMO SUPPORT *** */
 177 /* Monitor at start of flash */
 178 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_FLASH_BASE
 179 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 2 sectors */
 180
 181 /* additions for new relocation code, must be added to all boards */
 182 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
 183 #define CONFIG_SYS_INIT_RAM_ADDR        0x4020f800
 184 #define CONFIG_SYS_INIT_RAM_SIZE        0x800
 185 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_INIT_RAM_ADDR +     \
 186                                          CONFIG_SYS_INIT_RAM_SIZE -     \
 187                                          GENERATED_GBL_DATA_SIZE)
 188
 189 /* Status LED */
 190 #define GREEN_LED_GPIO                  186 /* CM-T35 Green LED is GPIO186 */
 191
 192 #define CONFIG_SPLASHIMAGE_GUARD
 193
 194 /* Display Configuration */
 195 #define LCD_BPP         LCD_COLOR16
 196
 197 #define CONFIG_SPLASH_SCREEN
 198 #define CONFIG_SPLASH_SOURCE
 199 #define CONFIG_BMP_16BPP
 200 #define CONFIG_SCF0403_LCD
 201
 202 /* Defines for SPL */
 203
 204 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION      1
 205 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
 206
 207 #define CONFIG_SPL_NAND_BASE
 208 #define CONFIG_SPL_NAND_DRIVERS
 209 #define CONFIG_SPL_NAND_ECC
 210
 211 /* NAND boot config */
 212 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
 213 #define CONFIG_SYS_NAND_PAGE_COUNT      64
 214 #define CONFIG_SYS_NAND_PAGE_SIZE       2048
 215 #define CONFIG_SYS_NAND_OOBSIZE         64
 216 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 217 #define CONFIG_SYS_NAND_BAD_BLOCK_POS   NAND_LARGE_BADBLOCK_POS
 218 /*
 219  * Use the ECC/OOB layout from omap_gpmc.h that matches your chip:
 220  * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT
 221  */
 222 #define CONFIG_SYS_NAND_ECCPOS          { 1, 2, 3, 4, 5, 6, 7, 8, 9, \
 223                                          10, 11, 12 }
 224 #define CONFIG_SYS_NAND_ECCSIZE         512
 225 #define CONFIG_SYS_NAND_ECCBYTES        3
 226 #define CONFIG_NAND_OMAP_ECCSCHEME      OMAP_ECC_HAM1_CODE_HW
 227
 228 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_TEXT_BASE
 229 #define CONFIG_SYS_NAND_U_BOOT_OFFS     0x80000
 230
 231 #define CONFIG_SPL_MAX_SIZE             (SRAM_SCRATCH_SPACE_ADDR - \
 232                                          CONFIG_SPL_TEXT_BASE)
 233
 234 /*
 235  * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the
 236  * older x-loader implementations. And move the BSS area so that it
 237  * doesn't overlap with TEXT_BASE.
 238  */
 239 #define CONFIG_SPL_BSS_START_ADDR       0x80100000
 240 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000         /* 512 KB */
 241
 242 #define CONFIG_SYS_SPL_MALLOC_START     0x80208000
 243 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
 244
 245 /* EEPROM */
 246 #define CONFIG_ENV_EEPROM_IS_ON_I2C
 247 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          1
 248 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       4
 249 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   5
 250 #define CONFIG_SYS_EEPROM_SIZE                  256
 251
 252 #endif /* __CONFIG_H */