3 * Congatec Conga-QEVAl board configuration file.
5 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
6 * Based on Freescale i.MX6Q Sabre Lite board configuration file.
7 * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
8 * Leo Sartre, <lsartre@adeneo-embedded.com>
10 * SPDX-License-Identifier: GPL-2.0+
13 #ifndef __CONFIG_CGTQMX6EVAL_H
14 #define __CONFIG_CGTQMX6EVAL_H
16 #include "mx6_common.h"
18 #define CONFIG_MACH_TYPE 4122
20 /* Size of malloc() pool */
21 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
23 #define CONFIG_BOARD_EARLY_INIT_F
24 #define CONFIG_MISC_INIT_R
26 #define CONFIG_MXC_UART
27 #define CONFIG_MXC_UART_BASE UART2_BASE
30 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
34 #define CONFIG_SPI_FLASH
35 #define CONFIG_SPI_FLASH_STMICRO
36 #define CONFIG_SPI_FLASH_SST
37 #define CONFIG_MXC_SPI
38 #define CONFIG_SF_DEFAULT_BUS 0
39 #define CONFIG_SF_DEFAULT_SPEED 20000000
40 #define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
42 /* Miscellaneous commands */
43 #define CONFIG_CMD_BMODE
46 #define CONFIG_IMX_THERMAL
49 #define CONFIG_CMD_I2C
50 #define CONFIG_SYS_I2C
51 #define CONFIG_SYS_I2C_MXC
52 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
53 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
54 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
55 #define CONFIG_SYS_I2C_SPEED 100000
59 #define CONFIG_POWER_I2C
60 #define CONFIG_POWER_PFUZE100
61 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
64 #define CONFIG_CMD_USB
65 #define CONFIG_CMD_FAT
66 #define CONFIG_USB_EHCI
67 #define CONFIG_USB_EHCI_MX6
68 #define CONFIG_USB_STORAGE
69 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
70 #define CONFIG_USB_HOST_ETHER
71 #define CONFIG_USB_ETHER_ASIX
72 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
73 #define CONFIG_MXC_USB_FLAGS 0
74 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 /* Enabled USB controller number */
75 #define CONFIG_USB_KEYBOARD
76 #define CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP
79 #define CONFIG_USBD_HS
80 #define CONFIG_USB_GADGET_DUALSPEED
82 #define CONFIG_USB_GADGET
83 #define CONFIG_CMD_USB_MASS_STORAGE
84 #define CONFIG_USB_FUNCTION_MASS_STORAGE
85 #define CONFIG_USB_GADGET_DOWNLOAD
86 #define CONFIG_USB_GADGET_VBUS_DRAW 2
88 #define CONFIG_G_DNL_VENDOR_NUM 0x0525
89 #define CONFIG_G_DNL_PRODUCT_NUM 0xa4a5
90 #define CONFIG_G_DNL_MANUFACTURER "Congatec"
92 #define CONFIG_USB_FUNCTION_FASTBOOT
93 #define CONFIG_CMD_FASTBOOT
94 #define CONFIG_ANDROID_BOOT_IMAGE
95 #define CONFIG_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR
96 #define CONFIG_FASTBOOT_BUF_SIZE 0x07000000
100 #define CONFIG_VIDEO_IPUV3
101 #define CONFIG_CFB_CONSOLE
102 #define CONFIG_VGA_AS_SINGLE_DEVICE
103 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
104 #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
105 #define CONFIG_VIDEO_BMP_RLE8
106 #define CONFIG_SPLASH_SCREEN
107 #define CONFIG_SPLASH_SCREEN_ALIGN
108 #define CONFIG_BMP_16BPP
109 #define CONFIG_VIDEO_LOGO
110 #define CONFIG_VIDEO_BMP_LOGO
112 #define CONFIG_IPUV3_CLK 198000000
114 #define CONFIG_IPUV3_CLK 264000000
116 #define CONFIG_IMX_HDMI
119 #define CONFIG_CMD_SATA
120 #define CONFIG_DWC_AHSATA
121 #define CONFIG_SYS_SATA_MAX_DEVICE 1
122 #define CONFIG_DWC_AHSATA_PORT_ID 0
123 #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
125 #define CONFIG_LIBATA
128 #define CONFIG_CMD_PING
129 #define CONFIG_CMD_DHCP
130 #define CONFIG_CMD_MII
131 #define CONFIG_FEC_MXC
133 #define IMX_FEC_BASE ENET_BASE_ADDR
134 #define CONFIG_FEC_XCV_TYPE RGMII
135 #define CONFIG_ETHPRIME "FEC"
136 #define CONFIG_FEC_MXC_PHYADDR 6
137 #define CONFIG_PHYLIB
138 #define CONFIG_PHY_ATHEROS
140 /* Command definition */
142 #define CONFIG_MXC_UART_BASE UART2_BASE
143 #define CONFIG_CONSOLE_DEV "ttymxc1"
144 #define CONFIG_MMCROOT "/dev/mmcblk0p2"
145 #define CONFIG_SYS_MMC_ENV_DEV 0
147 #define CONFIG_EXTRA_ENV_SETTINGS \
148 "script=boot.scr\0" \
150 "fdtfile=imx6q-qmx6.dtb\0" \
151 "fdt_addr_r=0x18000000\0" \
154 "console=" CONFIG_CONSOLE_DEV "\0" \
155 "bootm_size=0x10000000\0" \
156 "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
158 "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
159 "update_sd_firmware=" \
160 "if test ${ip_dyn} = yes; then " \
161 "setenv get_cmd dhcp; " \
163 "setenv get_cmd tftp; " \
165 "if mmc dev ${mmcdev}; then " \
166 "if ${get_cmd} ${update_sd_firmware_filename}; then " \
167 "setexpr fw_sz ${filesize} / 0x200; " \
168 "setexpr fw_sz ${fw_sz} + 1; " \
169 "mmc write ${loadaddr} 0x2 ${fw_sz}; " \
172 "mmcargs=setenv bootargs console=${console},${baudrate} " \
173 "root=${mmcroot}\0" \
175 "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
176 "bootscript=echo Running bootscript from mmc ...; " \
178 "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
179 "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile}\0" \
180 "mmcboot=echo Booting from mmc ...; " \
182 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
183 "if run loadfdt; then " \
184 "bootz ${loadaddr} - ${fdt_addr_r}; " \
186 "if test ${boot_fdt} = try; then " \
189 "echo WARN: Cannot load the DT; " \
195 "netargs=setenv bootargs console=${console},${baudrate} " \
197 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
198 "netboot=echo Booting from net ...; " \
200 "if test ${ip_dyn} = yes; then " \
201 "setenv get_cmd dhcp; " \
203 "setenv get_cmd tftp; " \
205 "${get_cmd} ${image}; " \
206 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
207 "if ${get_cmd} ${fdt_addr_r} ${fdtfile}; then " \
208 "bootz ${loadaddr} - ${fdt_addr_r}; " \
210 "if test ${boot_fdt} = try; then " \
213 "echo WARN: Cannot load the DT; " \
219 "spilock=sf probe && sf protect lock 0x3f0000 0x10000;"\
221 #define CONFIG_BOOTCOMMAND \
223 "mmc dev ${mmcdev};" \
224 "if mmc rescan; then " \
225 "if run loadbootscript; then " \
228 "if run loadimage; then " \
230 "else run netboot; " \
233 "else run netboot; fi"
235 #define CONFIG_SYS_MEMTEST_START 0x10000000
236 #define CONFIG_SYS_MEMTEST_END 0x10010000
237 #define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000
239 /* Physical Memory Map */
240 #define CONFIG_NR_DRAM_BANKS 1
241 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
242 #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
244 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
245 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
246 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
248 #define CONFIG_SYS_INIT_SP_OFFSET \
249 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
250 #define CONFIG_SYS_INIT_SP_ADDR \
251 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
253 /* Environment organization */
254 #if defined (CONFIG_ENV_IS_IN_MMC)
255 #define CONFIG_ENV_OFFSET (6 * 64 * 1024)
256 #define CONFIG_SYS_MMC_ENV_DEV 0
259 #define CONFIG_ENV_SIZE (8 * 1024)
261 #define CONFIG_ENV_IS_IN_SPI_FLASH
262 #if defined(CONFIG_ENV_IS_IN_SPI_FLASH)
263 #define CONFIG_ENV_OFFSET (768 * 1024)
264 #define CONFIG_ENV_SECT_SIZE (64 * 1024)
265 #define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
266 #define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
267 #define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
268 #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
271 #endif /* __CONFIG_CGTQMX6EVAL_H */