include/configs/adp-ag101p.h

   1 /*
   2  * Copyright (C) 2011 Andes Technology Corporation
   3  * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
   4  * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #ifndef __CONFIG_H
  10 #define __CONFIG_H
  11
  12 #include <asm/arch-ag101/ag101.h>
  13
  14 /*
  15  * CPU and Board Configuration Options
  16  */
  17 #define CONFIG_USE_INTERRUPT
  18
  19 #define CONFIG_SKIP_LOWLEVEL_INIT
  20
  21 #define CONFIG_ARCH_MAP_SYSMEM
  22
  23 #define CONFIG_BOOTP_SEND_HOSTNAME
  24 #define CONFIG_BOOTP_SERVERIP
  25
  26 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  27 #define CONFIG_MEM_REMAP
  28 #endif
  29
  30 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
  31 #ifdef CONFIG_OF_CONTROL
  32 #undef CONFIG_OF_SEPARATE
  33 #define CONFIG_OF_EMBED
  34 #endif
  35 #endif
  36
  37 /*
  38  * Timer
  39  */
  40 #define CONFIG_SYS_CLK_FREQ     39062500
  41 #define VERSION_CLOCK           CONFIG_SYS_CLK_FREQ
  42
  43 /*
  44  * Use Externel CLOCK or PCLK
  45  */
  46 #undef CONFIG_FTRTC010_EXTCLK
  47
  48 #ifndef CONFIG_FTRTC010_EXTCLK
  49 #define CONFIG_FTRTC010_PCLK
  50 #endif
  51
  52 #ifdef CONFIG_FTRTC010_EXTCLK
  53 #define TIMER_CLOCK     32768                   /* CONFIG_FTRTC010_EXTCLK */
  54 #else
  55 #define TIMER_CLOCK     CONFIG_SYS_HZ           /* CONFIG_FTRTC010_PCLK */
  56 #endif
  57
  58 #define TIMER_LOAD_VAL  0xffffffff
  59
  60 /*
  61  * Real Time Clock
  62  */
  63 #define CONFIG_RTC_FTRTC010
  64
  65 /*
  66  * Real Time Clock Divider
  67  * RTC_DIV_COUNT                        (OSC_CLK/OSC_5MHZ)
  68  */
  69 #define OSC_5MHZ                        (5*1000000)
  70 #define OSC_CLK                         (4*OSC_5MHZ)
  71 #define RTC_DIV_COUNT                   (0.5)   /* Why?? */
  72
  73 /*
  74  * Serial console configuration
  75  */
  76
  77 /* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */
  78 #define CONFIG_CONS_INDEX               1
  79 #define CONFIG_SYS_NS16550_SERIAL
  80 #define CONFIG_SYS_NS16550_COM1         CONFIG_FTUART010_02_BASE
  81 #ifndef CONFIG_DM_SERIAL
  82 #define CONFIG_SYS_NS16550_REG_SIZE     -4
  83 #endif
  84 #define CONFIG_SYS_NS16550_CLK          ((18432000 * 20) / 25)  /* AG101P */
  85
  86 /*
  87  * SD (MMC) controller
  88  */
  89 #define CONFIG_FTSDC010_NUMBER          1
  90 #define CONFIG_FTSDC010_SDIO
  91
  92 /*
  93  * Miscellaneous configurable options
  94  */
  95
  96 /*
  97  * Size of malloc() pool
  98  */
  99 /* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */
 100 #define CONFIG_SYS_MALLOC_LEN           (512 << 10)
 101
 102 /*
 103  * AHB Controller configuration
 104  */
 105 #define CONFIG_FTAHBC020S
 106
 107 #ifdef CONFIG_FTAHBC020S
 108 #include <faraday/ftahbc020s.h>
 109
 110 /* Address of PHYS_SDRAM_0 before memory remap is at 0x(100)00000 */
 111 #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE    0x100
 112
 113 /*
 114  * CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6: this define is used in lowlevel_init.S,
 115  * hence we cannot use FTAHBC020S_BSR_SIZE(2048) since it will use ffs() wrote
 116  * in C language.
 117  */
 118 #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6 \
 119         (FTAHBC020S_SLAVE_BSR_BASE(CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE) | \
 120                                         FTAHBC020S_SLAVE_BSR_SIZE(0xb))
 121 #endif
 122
 123 /*
 124  * Watchdog
 125  */
 126 #define CONFIG_FTWDT010_WATCHDOG
 127
 128 /*
 129  * PMU Power controller configuration
 130  */
 131 #define CONFIG_PMU
 132 #define CONFIG_FTPMU010_POWER
 133
 134 #ifdef CONFIG_FTPMU010_POWER
 135 #include <faraday/ftpmu010.h>
 136 #define CONFIG_SYS_FTPMU010_PDLLCR0_HCLKOUTDIS          0x0E
 137 #define CONFIG_SYS_FTPMU010_SDRAMHTC    (FTPMU010_SDRAMHTC_EBICTRL_DCSR  | \
 138                                          FTPMU010_SDRAMHTC_EBIDATA_DCSR  | \
 139                                          FTPMU010_SDRAMHTC_SDRAMCS_DCSR  | \
 140                                          FTPMU010_SDRAMHTC_SDRAMCTL_DCSR | \
 141                                          FTPMU010_SDRAMHTC_CKE_DCSR      | \
 142                                          FTPMU010_SDRAMHTC_DQM_DCSR      | \
 143                                          FTPMU010_SDRAMHTC_SDCLK_DCSR)
 144 #endif
 145
 146 /*
 147  * SDRAM controller configuration
 148  */
 149 #define CONFIG_FTSDMC021
 150
 151 #ifdef CONFIG_FTSDMC021
 152 #include <faraday/ftsdmc021.h>
 153
 154 #define CONFIG_SYS_FTSDMC021_TP1        (FTSDMC021_TP1_TRAS(2)  |       \
 155                                          FTSDMC021_TP1_TRP(1)   |       \
 156                                          FTSDMC021_TP1_TRCD(1)  |       \
 157                                          FTSDMC021_TP1_TRF(3)   |       \
 158                                          FTSDMC021_TP1_TWR(1)   |       \
 159                                          FTSDMC021_TP1_TCL(2))
 160
 161 #define CONFIG_SYS_FTSDMC021_TP2        (FTSDMC021_TP2_INI_PREC(4) |    \
 162                                          FTSDMC021_TP2_INI_REFT(8) |    \
 163                                          FTSDMC021_TP2_REF_INTV(0x180))
 164
 165 /*
 166  * CONFIG_SYS_FTSDMC021_CR1: this define is used in lowlevel_init.S,
 167  * hence we cannot use FTSDMC021_BANK_SIZE(64) since it will use ffs() wrote in
 168  * C language.
 169  */
 170 #define CONFIG_SYS_FTSDMC021_CR1        (FTSDMC021_CR1_DDW(2)    |      \
 171                                          FTSDMC021_CR1_DSZ(3)    |      \
 172                                          FTSDMC021_CR1_MBW(2)    |      \
 173                                          FTSDMC021_CR1_BNKSIZE(6))
 174
 175 #define CONFIG_SYS_FTSDMC021_CR2        (FTSDMC021_CR2_IPREC     |      \
 176                                          FTSDMC021_CR2_IREF      |      \
 177                                          FTSDMC021_CR2_ISMR)
 178
 179 #define CONFIG_SYS_FTSDMC021_BANK0_BASE CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE
 180 #define CONFIG_SYS_FTSDMC021_BANK0_BSR  (FTSDMC021_BANK_ENABLE   |      \
 181                                          CONFIG_SYS_FTSDMC021_BANK0_BASE)
 182
 183 #define CONFIG_SYS_FTSDMC021_BANK1_BASE \
 184         (CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE + (PHYS_SDRAM_0_SIZE >> 20))
 185 #define CONFIG_SYS_FTSDMC021_BANK1_BSR  (FTSDMC021_BANK_ENABLE   |      \
 186                                          CONFIG_SYS_FTSDMC021_BANK1_BASE)
 187 #endif
 188
 189 /*
 190  * Physical Memory Map
 191  */
 192 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
 193 #define PHYS_SDRAM_0    0x00000000  /* SDRAM Bank #1 */
 194 #else
 195 #ifdef CONFIG_MEM_REMAP
 196 #define PHYS_SDRAM_0    0x00000000      /* SDRAM Bank #1 */
 197 #else
 198 #define PHYS_SDRAM_0    0x80000000      /* SDRAM Bank #1 */
 199 #endif
 200 #endif
 201
 202 #define PHYS_SDRAM_1 \
 203         (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE)      /* SDRAM Bank #2 */
 204
 205 #define CONFIG_NR_DRAM_BANKS    2               /* we have 2 bank of DRAM */
 206
 207 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
 208 #define PHYS_SDRAM_0_SIZE       0x20000000      /* 512 MB */
 209 #define PHYS_SDRAM_1_SIZE       0x20000000      /* 512 MB */
 210 #else
 211 #ifdef CONFIG_MEM_REMAP
 212 #define PHYS_SDRAM_0_SIZE       0x20000000      /* 512 MB */
 213 #define PHYS_SDRAM_1_SIZE       0x20000000      /* 512 MB */
 214 #else
 215 #define PHYS_SDRAM_0_SIZE       0x08000000      /* 128 MB */
 216 #define PHYS_SDRAM_1_SIZE       0x08000000      /* 128 MB */
 217 #endif
 218 #endif
 219
 220 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_0
 221
 222 #ifdef CONFIG_MEM_REMAP
 223 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \
 224                                         GENERATED_GBL_DATA_SIZE)
 225 #else
 226 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
 227                                         GENERATED_GBL_DATA_SIZE)
 228 #endif /* CONFIG_MEM_REMAP */
 229
 230 /*
 231  * Load address and memory test area should agree with
 232  * arch/nds32/config.mk. Be careful not to overwrite U-Boot itself.
 233  */
 234 #define CONFIG_SYS_LOAD_ADDR            0x300000
 235
 236 /* memtest works on 63 MB in DRAM */
 237 #define CONFIG_SYS_MEMTEST_START        PHYS_SDRAM_0
 238 #define CONFIG_SYS_MEMTEST_END          (PHYS_SDRAM_0 + 0x03F00000)
 239
 240 /*
 241  * Static memory controller configuration
 242  */
 243 #define CONFIG_FTSMC020
 244
 245 #ifdef CONFIG_FTSMC020
 246 #include <faraday/ftsmc020.h>
 247
 248 #define CONFIG_SYS_FTSMC020_CONFIGS     {                       \
 249         { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, },      \
 250         { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, },      \
 251 }
 252
 253 #ifndef CONFIG_SKIP_LOWLEVEL_INIT       /* FLASH is on BANK 0 */
 254 #define FTSMC020_BANK0_LOWLV_CONFIG     (FTSMC020_BANK_ENABLE   |       \
 255                                          FTSMC020_BANK_SIZE_32M |       \
 256                                          FTSMC020_BANK_MBW_32)
 257
 258 #define FTSMC020_BANK0_LOWLV_TIMING     (FTSMC020_TPR_RBE       |       \
 259                                          FTSMC020_TPR_AST(1)    |       \
 260                                          FTSMC020_TPR_CTW(1)    |       \
 261                                          FTSMC020_TPR_ATI(1)    |       \
 262                                          FTSMC020_TPR_AT2(1)    |       \
 263                                          FTSMC020_TPR_WTC(1)    |       \
 264                                          FTSMC020_TPR_AHT(1)    |       \
 265                                          FTSMC020_TPR_TRNA(1))
 266 #endif
 267
 268 /*
 269  * FLASH on ADP_AG101P is connected to BANK0
 270  * Just disalbe the other BANK to avoid detection error.
 271  */
 272 #define FTSMC020_BANK0_CONFIG   (FTSMC020_BANK_ENABLE             |     \
 273                                  FTSMC020_BANK_BASE(PHYS_FLASH_1) |     \
 274                                  FTSMC020_BANK_SIZE_32M           |     \
 275                                  FTSMC020_BANK_MBW_32)
 276
 277 #define FTSMC020_BANK0_TIMING   (FTSMC020_TPR_AST(3)   |        \
 278                                  FTSMC020_TPR_CTW(3)   |        \
 279                                  FTSMC020_TPR_ATI(0xf) |        \
 280                                  FTSMC020_TPR_AT2(3)   |        \
 281                                  FTSMC020_TPR_WTC(3)   |        \
 282                                  FTSMC020_TPR_AHT(3)   |        \
 283                                  FTSMC020_TPR_TRNA(0xf))
 284
 285 #define FTSMC020_BANK1_CONFIG   (0x00)
 286 #define FTSMC020_BANK1_TIMING   (0x00)
 287 #endif /* CONFIG_FTSMC020 */
 288
 289 /*
 290  * FLASH and environment organization
 291  */
 292 /* use CFI framework */
 293 #define CONFIG_SYS_FLASH_CFI
 294 #define CONFIG_FLASH_CFI_DRIVER
 295
 296 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
 297 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 298 #define CONFIG_SYS_CFI_FLASH_STATUS_POLL
 299
 300 /* support JEDEC */
 301
 302 /* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */
 303 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
 304 #define PHYS_FLASH_1                    0x80000000      /* BANK 0 */
 305 #else
 306 #ifdef CONFIG_MEM_REMAP
 307 #define PHYS_FLASH_1                    0x80000000      /* BANK 0 */
 308 #else
 309 #define PHYS_FLASH_1                    0x00000000      /* BANK 0 */
 310 #endif
 311 #endif  /* CONFIG_MEM_REMAP */
 312
 313 #define CONFIG_SYS_FLASH_BASE           PHYS_FLASH_1
 314 #define CONFIG_SYS_FLASH_BANKS_LIST     { PHYS_FLASH_1, }
 315 #define CONFIG_SYS_MONITOR_BASE         PHYS_FLASH_1
 316
 317 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* TO for Flash Erase (ms) */
 318 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* TO for Flash Write (ms) */
 319
 320 /* max number of memory banks */
 321 /*
 322  * There are 4 banks supported for this Controller,
 323  * but we have only 1 bank connected to flash on board
 324  */
 325 #ifndef CONFIG_SYS_MAX_FLASH_BANKS_DETECT
 326 #define CONFIG_SYS_MAX_FLASH_BANKS      1
 327 #endif
 328 #define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000}
 329
 330 /* max number of sectors on one chip */
 331 #define CONFIG_FLASH_SECTOR_SIZE        (0x10000*2)
 332 #define CONFIG_ENV_SECT_SIZE            CONFIG_FLASH_SECTOR_SIZE
 333 #define CONFIG_SYS_MAX_FLASH_SECT       512
 334
 335 /* environments */
 336 #define CONFIG_ENV_ADDR                 (CONFIG_SYS_MONITOR_BASE + 0x140000)
 337 #define CONFIG_ENV_SIZE                 8192
 338 #define CONFIG_ENV_OVERWRITE
 339
 340 /*
 341  * For booting Linux, the board info and command line data
 342  * have to be in the first 16 MB of memory, since this is
 343  * the maximum mapped by the Linux kernel during initialization.
 344  */
 345
 346 /* Initial Memory map for Linux*/
 347 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)
 348 /* Increase max gunzip size */
 349 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)
 350
 351 #endif  /* __CONFIG_H */