include/configs/T208xRDB.h

   1 /*
   2  * Copyright 2014 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /*
   8  * T2080 RDB/PCIe board configuration file
   9  */
  10
  11 #ifndef __T2080RDB_H
  12 #define __T2080RDB_H
  13
  14 #define CONFIG_T2080RDB
  15 #define CONFIG_ICS307_REFCLK_HZ 25000000  /* ICS307 ref clk freq */
  16 #define CONFIG_USB_EHCI
  17 #define CONFIG_FSL_SATA_V2
  18
  19 /* High Level Configuration Options */
  20 #define CONFIG_SYS_BOOK3E_HV    /* Category E.HV supported */
  21 #define CONFIG_MP               /* support multiple processors */
  22 #define CONFIG_ENABLE_36BIT_PHYS
  23
  24 #ifdef CONFIG_PHYS_64BIT
  25 #define CONFIG_ADDR_MAP 1
  26 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
  27 #endif
  28
  29 #define CONFIG_SYS_FSL_CPC      /* Corenet Platform Cache */
  30 #define CONFIG_SYS_NUM_CPC      CONFIG_NUM_DDR_CONTROLLERS
  31 #define CONFIG_FSL_IFC          /* Enable IFC Support */
  32 #define CONFIG_FSL_CAAM         /* Enable SEC/CAAM */
  33 #define CONFIG_ENV_OVERWRITE
  34
  35 #ifdef CONFIG_RAMBOOT_PBL
  36 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xrdb/t2080_pbi.cfg
  37
  38 #define CONFIG_SPL_FLUSH_IMAGE
  39 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  40 #define CONFIG_SYS_TEXT_BASE            0x00201000
  41 #define CONFIG_SPL_TEXT_BASE            0xFFFD8000
  42 #define CONFIG_SPL_PAD_TO               0x40000
  43 #define CONFIG_SPL_MAX_SIZE             0x28000
  44 #define RESET_VECTOR_OFFSET             0x27FFC
  45 #define BOOT_PAGE_OFFSET                0x27000
  46 #ifdef CONFIG_SPL_BUILD
  47 #define CONFIG_SPL_SKIP_RELOCATE
  48 #define CONFIG_SPL_COMMON_INIT_DDR
  49 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  50 #define CONFIG_SYS_NO_FLASH
  51 #endif
  52
  53 #ifdef CONFIG_NAND
  54 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
  55 #define CONFIG_SYS_NAND_U_BOOT_DST      0x00200000
  56 #define CONFIG_SYS_NAND_U_BOOT_START    0x00200000
  57 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (256 << 10)
  58 #define CONFIG_SYS_LDSCRIPT  "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
  59 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_nand_rcw.cfg
  60 #define CONFIG_SPL_NAND_BOOT
  61 #endif
  62
  63 #ifdef CONFIG_SPIFLASH
  64 #define        CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  65 #define CONFIG_SPL_SPI_FLASH_MINIMAL
  66 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE       (768 << 10)
  67 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST                (0x00200000)
  68 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START      (0x00200000)
  69 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS       (256 << 10)
  70 #define CONFIG_SYS_LDSCRIPT    "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  71 #ifndef CONFIG_SPL_BUILD
  72 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  73 #endif
  74 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_spi_rcw.cfg
  75 #define CONFIG_SPL_SPI_BOOT
  76 #endif
  77
  78 #ifdef CONFIG_SDCARD
  79 #define        CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  80 #define CONFIG_SPL_MMC_MINIMAL
  81 #define CONFIG_SYS_MMC_U_BOOT_SIZE     (768 << 10)
  82 #define CONFIG_SYS_MMC_U_BOOT_DST      (0x00200000)
  83 #define CONFIG_SYS_MMC_U_BOOT_START    (0x00200000)
  84 #define CONFIG_SYS_MMC_U_BOOT_OFFS     (260 << 10)
  85 #define CONFIG_SYS_LDSCRIPT    "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  86 #ifndef CONFIG_SPL_BUILD
  87 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  88 #endif
  89 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_sd_rcw.cfg
  90 #define CONFIG_SPL_MMC_BOOT
  91 #endif
  92
  93 #endif /* CONFIG_RAMBOOT_PBL */
  94
  95 #define CONFIG_SRIO_PCIE_BOOT_MASTER
  96 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  97 /* Set 1M boot space */
  98 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  99 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
 100                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
 101 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
 102 #define CONFIG_SYS_NO_FLASH
 103 #endif
 104
 105 #ifndef CONFIG_SYS_TEXT_BASE
 106 #define CONFIG_SYS_TEXT_BASE    0xeff40000
 107 #endif
 108
 109 #ifndef CONFIG_RESET_VECTOR_ADDRESS
 110 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
 111 #endif
 112
 113 /*
 114  * These can be toggled for performance analysis, otherwise use default.
 115  */
 116 #define CONFIG_SYS_CACHE_STASHING
 117 #define CONFIG_BTB              /* toggle branch predition */
 118 #define CONFIG_DDR_ECC
 119 #ifdef CONFIG_DDR_ECC
 120 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 121 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 122 #endif
 123
 124 #define CONFIG_SYS_MEMTEST_START        0x00200000 /* memtest works on */
 125 #define CONFIG_SYS_MEMTEST_END          0x00400000
 126 #define CONFIG_SYS_ALT_MEMTEST
 127
 128 #ifndef CONFIG_SYS_NO_FLASH
 129 #define CONFIG_FLASH_CFI_DRIVER
 130 #define CONFIG_SYS_FLASH_CFI
 131 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 132 #endif
 133
 134 #if defined(CONFIG_SPIFLASH)
 135 #define CONFIG_SYS_EXTRA_ENV_RELOC
 136 #define CONFIG_ENV_IS_IN_SPI_FLASH
 137 #define CONFIG_ENV_SPI_BUS      0
 138 #define CONFIG_ENV_SPI_CS       0
 139 #define CONFIG_ENV_SPI_MAX_HZ   10000000
 140 #define CONFIG_ENV_SPI_MODE     0
 141 #define CONFIG_ENV_SIZE         0x2000     /* 8KB */
 142 #define CONFIG_ENV_OFFSET       0x100000   /* 1MB */
 143 #define CONFIG_ENV_SECT_SIZE    0x10000
 144 #elif defined(CONFIG_SDCARD)
 145 #define CONFIG_SYS_EXTRA_ENV_RELOC
 146 #define CONFIG_ENV_IS_IN_MMC
 147 #define CONFIG_SYS_MMC_ENV_DEV  0
 148 #define CONFIG_ENV_SIZE         0x2000
 149 #define CONFIG_ENV_OFFSET       (512 * 0x800)
 150 #elif defined(CONFIG_NAND)
 151 #define CONFIG_SYS_EXTRA_ENV_RELOC
 152 #define CONFIG_ENV_IS_IN_NAND
 153 #define CONFIG_ENV_SIZE         0x2000
 154 #define CONFIG_ENV_OFFSET       (2 * CONFIG_SYS_NAND_BLOCK_SIZE)
 155 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 156 #define CONFIG_ENV_IS_IN_REMOTE
 157 #define CONFIG_ENV_ADDR         0xffe20000
 158 #define CONFIG_ENV_SIZE         0x2000
 159 #elif defined(CONFIG_ENV_IS_NOWHERE)
 160 #define CONFIG_ENV_SIZE         0x2000
 161 #else
 162 #define CONFIG_ENV_IS_IN_FLASH
 163 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 164 #define CONFIG_ENV_SIZE         0x2000
 165 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 166 #endif
 167
 168 #ifndef __ASSEMBLY__
 169 unsigned long get_board_sys_clk(void);
 170 unsigned long get_board_ddr_clk(void);
 171 #endif
 172
 173 #define CONFIG_SYS_CLK_FREQ     66660000
 174 #define CONFIG_DDR_CLK_FREQ     133330000
 175
 176 /*
 177  * Config the L3 Cache as L3 SRAM
 178  */
 179 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
 180 #define CONFIG_SYS_L3_SIZE              (512 << 10)
 181 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
 182 #ifdef CONFIG_RAMBOOT_PBL
 183 #define CONFIG_ENV_ADDR                 (CONFIG_SPL_GD_ADDR + 4 * 1024)
 184 #endif
 185 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
 186 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (50 << 10)
 187 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
 188 #define CONFIG_SPL_RELOC_STACK_SIZE     (22 << 10)
 189
 190 #define CONFIG_SYS_DCSRBAR      0xf0000000
 191 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
 192
 193 /* EEPROM */
 194 #define CONFIG_ID_EEPROM
 195 #define CONFIG_SYS_I2C_EEPROM_NXID
 196 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 197 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50
 198 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  2
 199
 200 /*
 201  * DDR Setup
 202  */
 203 #define CONFIG_VERY_BIG_RAM
 204 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 205 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 206 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 207 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
 208 #define CONFIG_DDR_SPD
 209 #define CONFIG_SYS_FSL_DDR3
 210 #undef CONFIG_FSL_DDR_INTERACTIVE
 211 #define CONFIG_SYS_SPD_BUS_NUM  0
 212 #define CONFIG_SYS_SDRAM_SIZE   2048    /* for fixed parameter use */
 213 #define SPD_EEPROM_ADDRESS1     0x51
 214 #define SPD_EEPROM_ADDRESS2     0x52
 215 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1
 216 #define CTRL_INTLV_PREFERED     cacheline
 217
 218 /*
 219  * IFC Definitions
 220  */
 221 #define CONFIG_SYS_FLASH_BASE           0xe8000000
 222 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 223 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 224 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 225                                 CSPR_PORT_SIZE_16 | \
 226                                 CSPR_MSEL_NOR | \
 227                                 CSPR_V)
 228 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 229
 230 /* NOR Flash Timing Params */
 231 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 232
 233 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 234                                 FTIM0_NOR_TEADC(0x5) | \
 235                                 FTIM0_NOR_TEAHC(0x5))
 236 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 237                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 238                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 239 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 240                                 FTIM2_NOR_TCH(0x4) | \
 241                                 FTIM2_NOR_TWPH(0x0E) | \
 242                                 FTIM2_NOR_TWP(0x1c))
 243 #define CONFIG_SYS_NOR_FTIM3    0x0
 244
 245 #define CONFIG_SYS_FLASH_QUIET_TEST
 246 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 247
 248 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 249 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 250 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 251 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 252 #define CONFIG_SYS_FLASH_EMPTY_INFO
 253 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS }
 254
 255 /* CPLD on IFC */
 256 #define CONFIG_SYS_CPLD_BASE    0xffdf0000
 257 #define CONFIG_SYS_CPLD_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
 258 #define CONFIG_SYS_CSPR2_EXT    (0xf)
 259 #define CONFIG_SYS_CSPR2        (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
 260                                 | CSPR_PORT_SIZE_8 \
 261                                 | CSPR_MSEL_GPCM \
 262                                 | CSPR_V)
 263 #define CONFIG_SYS_AMASK2       IFC_AMASK(64*1024)
 264 #define CONFIG_SYS_CSOR2        0x0
 265
 266 /* CPLD Timing parameters for IFC CS2 */
 267 #define CONFIG_SYS_CS2_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 268                                         FTIM0_GPCM_TEADC(0x0e) | \
 269                                         FTIM0_GPCM_TEAHC(0x0e))
 270 #define CONFIG_SYS_CS2_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
 271                                         FTIM1_GPCM_TRAD(0x1f))
 272 #define CONFIG_SYS_CS2_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 273                                         FTIM2_GPCM_TCH(0x8) | \
 274                                         FTIM2_GPCM_TWP(0x1f))
 275 #define CONFIG_SYS_CS2_FTIM3            0x0
 276
 277 /* NAND Flash on IFC */
 278 #define CONFIG_NAND_FSL_IFC
 279 #define CONFIG_SYS_NAND_BASE            0xff800000
 280 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 281
 282 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 283 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 284                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 285                                 | CSPR_MSEL_NAND         /* MSEL = NAND */ \
 286                                 | CSPR_V)
 287 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 288
 289 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 290                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 291                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */     \
 292                                 | CSOR_NAND_RAL_3       /* RAL = 2Byes */   \
 293                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */\
 294                                 | CSOR_NAND_SPRZ_64     /* Spare size = 64 */\
 295                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 296
 297 #define CONFIG_SYS_NAND_ONFI_DETECTION
 298
 299 /* ONFI NAND Flash mode0 Timing Params */
 300 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 301                                         FTIM0_NAND_TWP(0x18)    | \
 302                                         FTIM0_NAND_TWCHT(0x07)  | \
 303                                         FTIM0_NAND_TWH(0x0a))
 304 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 305                                         FTIM1_NAND_TWBE(0x39)   | \
 306                                         FTIM1_NAND_TRR(0x0e)    | \
 307                                         FTIM1_NAND_TRP(0x18))
 308 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f)  | \
 309                                         FTIM2_NAND_TREH(0x0a)   | \
 310                                         FTIM2_NAND_TWHRE(0x1e))
 311 #define CONFIG_SYS_NAND_FTIM3           0x0
 312
 313 #define CONFIG_SYS_NAND_DDR_LAW         11
 314 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 315 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 316 #define CONFIG_CMD_NAND
 317 #define CONFIG_SYS_NAND_BLOCK_SIZE      (512 * 1024)
 318
 319 #if defined(CONFIG_NAND)
 320 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 321 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 322 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 323 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 324 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 325 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 326 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 327 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 328 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 329 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 330 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 331 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 332 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 333 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 334 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 335 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 336 #else
 337 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 338 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 339 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 340 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 341 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 342 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 343 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 344 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 345 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
 346 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 347 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 348 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 349 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 350 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 351 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 352 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 353 #endif
 354
 355 #if defined(CONFIG_RAMBOOT_PBL)
 356 #define CONFIG_SYS_RAMBOOT
 357 #endif
 358
 359 #ifdef CONFIG_SPL_BUILD
 360 #define CONFIG_SYS_MONITOR_BASE  CONFIG_SPL_TEXT_BASE
 361 #else
 362 #define CONFIG_SYS_MONITOR_BASE  CONFIG_SYS_TEXT_BASE /* start of monitor */
 363 #endif
 364
 365 #define CONFIG_BOARD_EARLY_INIT_R       /* call board_early_init_r function */
 366 #define CONFIG_MISC_INIT_R
 367 #define CONFIG_HWCONFIG
 368
 369 /* define to use L1 as initial stack */
 370 #define CONFIG_L1_INIT_RAM
 371 #define CONFIG_SYS_INIT_RAM_LOCK
 372 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000 /* Initial L1 address */
 373 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 374 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 375 /* The assembler doesn't like typecast */
 376 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 377                         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 378                         CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 379 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000
 380 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 381                                                 GENERATED_GBL_DATA_SIZE)
 382 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 383 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 384 #define CONFIG_SYS_MALLOC_LEN           (4 * 1024 * 1024)
 385
 386 /*
 387  * Serial Port
 388  */
 389 #define CONFIG_CONS_INDEX               1
 390 #define CONFIG_SYS_NS16550_SERIAL
 391 #define CONFIG_SYS_NS16550_REG_SIZE     1
 392 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 393 #define CONFIG_SYS_BAUDRATE_TABLE       \
 394         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 395 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 396 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 397 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 398 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 399
 400 /*
 401  * I2C
 402  */
 403 #define CONFIG_SYS_I2C
 404 #define CONFIG_SYS_I2C_FSL
 405 #define CONFIG_SYS_FSL_I2C_SLAVE   0x7F
 406 #define CONFIG_SYS_FSL_I2C2_SLAVE  0x7F
 407 #define CONFIG_SYS_FSL_I2C3_SLAVE  0x7F
 408 #define CONFIG_SYS_FSL_I2C4_SLAVE  0x7F
 409 #define CONFIG_SYS_FSL_I2C_OFFSET  0x118000
 410 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
 411 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
 412 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
 413 #define CONFIG_SYS_FSL_I2C_SPEED   100000
 414 #define CONFIG_SYS_FSL_I2C2_SPEED  100000
 415 #define CONFIG_SYS_FSL_I2C3_SPEED  100000
 416 #define CONFIG_SYS_FSL_I2C4_SPEED  100000
 417 #define I2C_MUX_PCA_ADDR_PRI    0x77 /* I2C bus multiplexer,primary */
 418 #define I2C_MUX_PCA_ADDR_SEC1   0x75 /* I2C bus multiplexer,secondary 1 */
 419 #define I2C_MUX_PCA_ADDR_SEC2   0x76 /* I2C bus multiplexer,secondary 2 */
 420 #define I2C_MUX_CH_DEFAULT      0x8
 421
 422 #define I2C_MUX_CH_VOL_MONITOR  0xa
 423
 424 #define CONFIG_VID_FLS_ENV              "t208xrdb_vdd_mv"
 425 #ifndef CONFIG_SPL_BUILD
 426 #define CONFIG_VID
 427 #endif
 428 #define CONFIG_VOL_MONITOR_IR36021_SET
 429 #define CONFIG_VOL_MONITOR_IR36021_READ
 430 /* The lowest and highest voltage allowed for T208xRDB */
 431 #define VDD_MV_MIN                      819
 432 #define VDD_MV_MAX                      1212
 433
 434 /*
 435  * RapidIO
 436  */
 437 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
 438 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
 439 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000 /* 256M */
 440 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
 441 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
 442 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000 /* 256M */
 443 /*
 444  * for slave u-boot IMAGE instored in master memory space,
 445  * PHYS must be aligned based on the SIZE
 446  */
 447 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 448 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 449 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
 450 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 451 /*
 452  * for slave UCODE and ENV instored in master memory space,
 453  * PHYS must be aligned based on the SIZE
 454  */
 455 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 456 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
 457 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE    0x40000 /* 256K */
 458
 459 /* slave core release by master*/
 460 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 461 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 462
 463 /*
 464  * SRIO_PCIE_BOOT - SLAVE
 465  */
 466 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 467 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 468 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 469                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 470 #endif
 471
 472 /*
 473  * eSPI - Enhanced SPI
 474  */
 475 #ifdef CONFIG_SPI_FLASH
 476 #define CONFIG_SPI_FLASH_BAR
 477 #define CONFIG_SF_DEFAULT_SPEED  10000000
 478 #define CONFIG_SF_DEFAULT_MODE    0
 479 #endif
 480
 481 /*
 482  * General PCI
 483  * Memory space is mapped 1-1, but I/O space must start from 0.
 484  */
 485 #define CONFIG_PCIE1            /* PCIE controller 1 */
 486 #define CONFIG_PCIE2            /* PCIE controller 2 */
 487 #define CONFIG_PCIE3            /* PCIE controller 3 */
 488 #define CONFIG_PCIE4            /* PCIE controller 4 */
 489 #define CONFIG_FSL_PCI_INIT     /* Use common FSL init code */
 490 #define CONFIG_SYS_PCI_64BIT    /* enable 64-bit PCI resources */
 491 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 492 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 493 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 494 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 495 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 496 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 497 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 498 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 499 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 500
 501 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 502 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 503 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 504 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 505 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000 /* 256M */
 506 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 507 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 508 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 509 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 510
 511 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 512 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xb0000000
 513 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 514 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc30000000ull
 515 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x10000000      /* 256M */
 516 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 517 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 518 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 519 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 520
 521 /* controller 4, Base address 203000 */
 522 #define CONFIG_SYS_PCIE4_MEM_VIRT       0xc0000000
 523 #define CONFIG_SYS_PCIE4_MEM_BUS        0xe0000000
 524 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc40000000ull
 525 #define CONFIG_SYS_PCIE4_MEM_SIZE       0x10000000      /* 256M */
 526 #define CONFIG_SYS_PCIE4_IO_BUS         0x00000000
 527 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 528 #define CONFIG_SYS_PCIE4_IO_SIZE        0x00010000      /* 64k */
 529
 530 #ifdef CONFIG_PCI
 531 #define CONFIG_PCI_INDIRECT_BRIDGE
 532 #define CONFIG_FSL_PCIE_RESET           /* need PCIe reset errata LSZ ADD */
 533 #define CONFIG_PCI_SCAN_SHOW    /* show pci devices on startup */
 534 #define CONFIG_DOS_PARTITION
 535 #endif
 536
 537 /* Qman/Bman */
 538 #ifndef CONFIG_NOBQFMAN
 539 #define CONFIG_SYS_DPAA_QBMAN           /* Support Q/Bman */
 540 #define CONFIG_SYS_BMAN_NUM_PORTALS     18
 541 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 542 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 543 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 544 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 545 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 546 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 547 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 548 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 549                                         CONFIG_SYS_BMAN_CENA_SIZE)
 550 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 551 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 552 #define CONFIG_SYS_QMAN_NUM_PORTALS     18
 553 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 554 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 555 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 556 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 557 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 558 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 559 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 560 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 561                                         CONFIG_SYS_QMAN_CENA_SIZE)
 562 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 563 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 564
 565 #define CONFIG_SYS_DPAA_FMAN
 566 #define CONFIG_SYS_DPAA_PME
 567 #define CONFIG_SYS_PMAN
 568 #define CONFIG_SYS_DPAA_DCE
 569 #define CONFIG_SYS_DPAA_RMAN            /* RMan */
 570 #define CONFIG_SYS_INTERLAKEN
 571
 572 /* Default address of microcode for the Linux Fman driver */
 573 #if defined(CONFIG_SPIFLASH)
 574 /*
 575  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 576  * env, so we got 0x110000.
 577  */
 578 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
 579 #define CONFIG_SYS_CORTINA_FW_IN_SPIFLASH
 580 #define CONFIG_SYS_FMAN_FW_ADDR         0x110000
 581 #define CONFIG_CORTINA_FW_ADDR          0x120000
 582
 583 #elif defined(CONFIG_SDCARD)
 584 /*
 585  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 586  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
 587  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
 588  */
 589 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 590 #define CONFIG_SYS_CORTINA_FW_IN_MMC
 591 #define CONFIG_SYS_FMAN_FW_ADDR         (512 * 0x820)
 592 #define CONFIG_CORTINA_FW_ADDR          (512 * 0x8a0)
 593
 594 #elif defined(CONFIG_NAND)
 595 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 596 #define CONFIG_SYS_CORTINA_FW_IN_NAND
 597 #define CONFIG_SYS_FMAN_FW_ADDR         (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
 598 #define CONFIG_CORTINA_FW_ADDR          (4 * CONFIG_SYS_NAND_BLOCK_SIZE)
 599 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 600 /*
 601  * Slave has no ucode locally, it can fetch this from remote. When implementing
 602  * in two corenet boards, slave's ucode could be stored in master's memory
 603  * space, the address can be mapped from slave TLB->slave LAW->
 604  * slave SRIO or PCIE outbound window->master inbound window->
 605  * master LAW->the ucode address in master's memory space.
 606  */
 607 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
 608 #define CONFIG_SYS_CORTINA_FW_IN_REMOTE
 609 #define CONFIG_SYS_FMAN_FW_ADDR         0xFFE00000
 610 #define CONFIG_CORTINA_FW_ADDR          0xFFE10000
 611 #else
 612 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 613 #define CONFIG_SYS_CORTINA_FW_IN_NOR
 614 #define CONFIG_SYS_FMAN_FW_ADDR         0xEFF00000
 615 #define CONFIG_CORTINA_FW_ADDR          0xEFE00000
 616 #endif
 617 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 618 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 619 #endif /* CONFIG_NOBQFMAN */
 620
 621 #ifdef CONFIG_SYS_DPAA_FMAN
 622 #define CONFIG_FMAN_ENET
 623 #define CONFIG_PHYLIB_10G
 624 #define CONFIG_PHY_AQUANTIA
 625 #define CONFIG_PHY_CORTINA
 626 #define CONFIG_PHY_REALTEK
 627 #define CONFIG_CORTINA_FW_LENGTH        0x40000
 628 #define RGMII_PHY1_ADDR         0x01  /* RealTek RTL8211E */
 629 #define RGMII_PHY2_ADDR         0x02
 630 #define CORTINA_PHY_ADDR1       0x0c  /* Cortina CS4315 */
 631 #define CORTINA_PHY_ADDR2       0x0d
 632 #define FM1_10GEC3_PHY_ADDR     0x00  /* Aquantia AQ1202 10G Base-T */
 633 #define FM1_10GEC4_PHY_ADDR     0x01
 634 #endif
 635
 636 #ifdef CONFIG_FMAN_ENET
 637 #define CONFIG_MII              /* MII PHY management */
 638 #define CONFIG_ETHPRIME         "FM1@DTSEC3"
 639 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
 640 #endif
 641
 642 /*
 643  * SATA
 644  */
 645 #ifdef CONFIG_FSL_SATA_V2
 646 #define CONFIG_LIBATA
 647 #define CONFIG_FSL_SATA
 648 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 649 #define CONFIG_SATA1
 650 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 651 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 652 #define CONFIG_SATA2
 653 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 654 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 655 #define CONFIG_LBA48
 656 #define CONFIG_CMD_SATA
 657 #define CONFIG_DOS_PARTITION
 658 #endif
 659
 660 /*
 661  * USB
 662  */
 663 #ifdef CONFIG_USB_EHCI
 664 #define CONFIG_USB_EHCI_FSL
 665 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 666 #define CONFIG_HAS_FSL_DR_USB
 667 #endif
 668
 669 /*
 670  * SDHC
 671  */
 672 #ifdef CONFIG_MMC
 673 #define CONFIG_FSL_ESDHC
 674 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 675 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 676 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
 677 #define CONFIG_GENERIC_MMC
 678 #define CONFIG_DOS_PARTITION
 679 #endif
 680
 681 /*
 682  * Dynamic MTD Partition support with mtdparts
 683  */
 684 #ifndef CONFIG_SYS_NO_FLASH
 685 #define CONFIG_MTD_DEVICE
 686 #define CONFIG_MTD_PARTITIONS
 687 #define CONFIG_CMD_MTDPARTS
 688 #define CONFIG_FLASH_CFI_MTD
 689 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \
 690                         "spi0=spife110000.1"
 691 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \
 692                         "128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot)," \
 693                         "5m(kernel),128k(dtb),96m(fs),-(user);spife110000.1:" \
 694                         "1m(uboot),5m(kernel),128k(dtb),-(user)"
 695 #endif
 696
 697 /*
 698  * Environment
 699  */
 700
 701 /*
 702  * Command line configuration.
 703  */
 704 #define CONFIG_CMD_ERRATA
 705 #define CONFIG_CMD_REGINFO
 706
 707 #ifdef CONFIG_PCI
 708 #define CONFIG_CMD_PCI
 709 #endif
 710
 711 /* Hash command with SHA acceleration supported in hardware */
 712 #ifdef CONFIG_FSL_CAAM
 713 #define CONFIG_CMD_HASH
 714 #define CONFIG_SHA_HW_ACCEL
 715 #endif
 716
 717 /*
 718  * Miscellaneous configurable options
 719  */
 720 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 721 #define CONFIG_CMDLINE_EDITING          /* Command-line editing */
 722 #define CONFIG_AUTO_COMPLETE            /* add autocompletion support */
 723 #define CONFIG_SYS_LOAD_ADDR    0x2000000 /* default load address */
 724 #ifdef CONFIG_CMD_KGDB
 725 #define CONFIG_SYS_CBSIZE       1024      /* Console I/O Buffer Size */
 726 #else
 727 #define CONFIG_SYS_CBSIZE       256       /* Console I/O Buffer Size */
 728 #endif
 729 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 730 #define CONFIG_SYS_MAXARGS      16      /* max number of command args */
 731 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
 732
 733 /*
 734  * For booting Linux, the board info and command line data
 735  * have to be in the first 64 MB of memory, since this is
 736  * the maximum mapped by the Linux kernel during initialization.
 737  */
 738 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 739 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 740
 741 #ifdef CONFIG_CMD_KGDB
 742 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 743 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 744 #endif
 745
 746 /*
 747  * Environment Configuration
 748  */
 749 #define CONFIG_ROOTPATH  "/opt/nfsroot"
 750 #define CONFIG_BOOTFILE  "uImage"
 751 #define CONFIG_UBOOTPATH "u-boot.bin"   /* U-Boot image on TFTP server */
 752
 753 /* default location for tftp and bootm */
 754 #define CONFIG_LOADADDR         1000000
 755 #define CONFIG_BAUDRATE         115200
 756 #define __USB_PHY_TYPE          utmi
 757
 758 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 759         "hwconfig=fsl_ddr:"                                     \
 760         "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","      \
 761         "bank_intlv=auto;"                                      \
 762         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 763         "netdev=eth0\0"                                         \
 764         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 765         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 766         "tftpflash=tftpboot $loadaddr $uboot && "               \
 767         "protect off $ubootaddr +$filesize && "                 \
 768         "erase $ubootaddr +$filesize && "                       \
 769         "cp.b $loadaddr $ubootaddr $filesize && "               \
 770         "protect on $ubootaddr +$filesize && "                  \
 771         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 772         "consoledev=ttyS0\0"                                    \
 773         "ramdiskaddr=2000000\0"                                 \
 774         "ramdiskfile=t2080rdb/ramdisk.uboot\0"                  \
 775         "fdtaddr=1e00000\0"                                     \
 776         "fdtfile=t2080rdb/t2080rdb.dtb\0"                       \
 777         "bdev=sda3\0"
 778
 779 /*
 780  * For emulation this causes u-boot to jump to the start of the
 781  * proof point app code automatically
 782  */
 783 #define CONFIG_PROOF_POINTS                             \
 784         "setenv bootargs root=/dev/$bdev rw "           \
 785         "console=$consoledev,$baudrate $othbootargs;"   \
 786         "cpu 1 release 0x29000000 - - -;"               \
 787         "cpu 2 release 0x29000000 - - -;"               \
 788         "cpu 3 release 0x29000000 - - -;"               \
 789         "cpu 4 release 0x29000000 - - -;"               \
 790         "cpu 5 release 0x29000000 - - -;"               \
 791         "cpu 6 release 0x29000000 - - -;"               \
 792         "cpu 7 release 0x29000000 - - -;"               \
 793         "go 0x29000000"
 794
 795 #define CONFIG_HVBOOT                           \
 796         "setenv bootargs config-addr=0x60000000; "      \
 797         "bootm 0x01000000 - 0x00f00000"
 798
 799 #define CONFIG_ALU                              \
 800         "setenv bootargs root=/dev/$bdev rw "           \
 801         "console=$consoledev,$baudrate $othbootargs;"   \
 802         "cpu 1 release 0x01000000 - - -;"               \
 803         "cpu 2 release 0x01000000 - - -;"               \
 804         "cpu 3 release 0x01000000 - - -;"               \
 805         "cpu 4 release 0x01000000 - - -;"               \
 806         "cpu 5 release 0x01000000 - - -;"               \
 807         "cpu 6 release 0x01000000 - - -;"               \
 808         "cpu 7 release 0x01000000 - - -;"               \
 809         "go 0x01000000"
 810
 811 #define CONFIG_LINUX                            \
 812         "setenv bootargs root=/dev/ram rw "             \
 813         "console=$consoledev,$baudrate $othbootargs;"   \
 814         "setenv ramdiskaddr 0x02000000;"                \
 815         "setenv fdtaddr 0x00c00000;"                    \
 816         "setenv loadaddr 0x1000000;"                    \
 817         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 818
 819 #define CONFIG_HDBOOT                                   \
 820         "setenv bootargs root=/dev/$bdev rw "           \
 821         "console=$consoledev,$baudrate $othbootargs;"   \
 822         "tftp $loadaddr $bootfile;"                     \
 823         "tftp $fdtaddr $fdtfile;"                       \
 824         "bootm $loadaddr - $fdtaddr"
 825
 826 #define CONFIG_NFSBOOTCOMMAND                   \
 827         "setenv bootargs root=/dev/nfs rw "     \
 828         "nfsroot=$serverip:$rootpath "          \
 829         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 830         "console=$consoledev,$baudrate $othbootargs;"   \
 831         "tftp $loadaddr $bootfile;"             \
 832         "tftp $fdtaddr $fdtfile;"               \
 833         "bootm $loadaddr - $fdtaddr"
 834
 835 #define CONFIG_RAMBOOTCOMMAND                           \
 836         "setenv bootargs root=/dev/ram rw "             \
 837         "console=$consoledev,$baudrate $othbootargs;"   \
 838         "tftp $ramdiskaddr $ramdiskfile;"               \
 839         "tftp $loadaddr $bootfile;"                     \
 840         "tftp $fdtaddr $fdtfile;"                       \
 841         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 842
 843 #define CONFIG_BOOTCOMMAND              CONFIG_LINUX
 844
 845 #include <asm/fsl_secure_boot.h>
 846
 847 #endif  /* __T2080RDB_H */