2 * Copyright 2013-2014 Freescale Semiconductor, Inc.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * T1040 QDS board configuration file
31 #ifdef CONFIG_RAMBOOT_PBL
32 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
33 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
34 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t1040qds/t1040_pbi.cfg
35 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t1040qds/t1040_rcw.cfg
38 /* High Level Configuration Options */
39 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
41 /* support deep sleep */
42 #define CONFIG_DEEP_SLEEP
44 #ifndef CONFIG_RESET_VECTOR_ADDRESS
45 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
48 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
49 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
50 #define CONFIG_PCI_INDIRECT_BRIDGE
51 #define CONFIG_PCIE1 /* PCIE controller 1 */
52 #define CONFIG_PCIE2 /* PCIE controller 2 */
53 #define CONFIG_PCIE3 /* PCIE controller 3 */
54 #define CONFIG_PCIE4 /* PCIE controller 4 */
56 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
57 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
59 #define CONFIG_ENV_OVERWRITE
61 #ifdef CONFIG_MTD_NOR_FLASH
62 #if defined(CONFIG_SPIFLASH)
63 #elif defined(CONFIG_SDCARD)
64 #define CONFIG_SYS_MMC_ENV_DEV 0
69 unsigned long get_board_sys_clk(void);
70 unsigned long get_board_ddr_clk(void);
73 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
74 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
77 * These can be toggled for performance analysis, otherwise use default.
79 #define CONFIG_SYS_CACHE_STASHING
80 #define CONFIG_BACKSIDE_L2_CACHE
81 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
82 #define CONFIG_BTB /* toggle branch predition */
83 #define CONFIG_DDR_ECC
85 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
86 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
89 #define CONFIG_ENABLE_36BIT_PHYS
91 #define CONFIG_ADDR_MAP
92 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
95 * Config the L3 Cache as L3 SRAM
97 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
99 #define CONFIG_SYS_DCSRBAR 0xf0000000
100 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
103 #define CONFIG_ID_EEPROM
104 #define CONFIG_SYS_I2C_EEPROM_NXID
105 #define CONFIG_SYS_EEPROM_BUS_NUM 0
106 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
107 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
108 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
109 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
114 #define CONFIG_VERY_BIG_RAM
115 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
116 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
118 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
119 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
121 #define CONFIG_DDR_SPD
123 #define CONFIG_SYS_SPD_BUS_NUM 0
124 #define SPD_EEPROM_ADDRESS 0x51
126 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
131 #define CONFIG_SYS_FLASH_BASE 0xe0000000
132 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
134 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
135 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
137 CSPR_PORT_SIZE_16 | \
140 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
141 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
142 CSPR_PORT_SIZE_16 | \
145 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
150 #define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000
152 /* NOR Flash Timing Params */
153 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
154 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
155 FTIM0_NOR_TEADC(0x5) | \
156 FTIM0_NOR_TEAHC(0x5))
157 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
158 FTIM1_NOR_TRAD_NOR(0x1A) |\
159 FTIM1_NOR_TSEQRAD_NOR(0x13))
160 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
161 FTIM2_NOR_TCH(0x4) | \
162 FTIM2_NOR_TWPH(0x0E) | \
164 #define CONFIG_SYS_NOR_FTIM3 0x0
166 #define CONFIG_SYS_FLASH_QUIET_TEST
167 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
169 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
170 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
171 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
172 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
174 #define CONFIG_SYS_FLASH_EMPTY_INFO
175 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
176 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
177 #define CONFIG_FSL_QIXIS /* use common QIXIS code */
178 #define QIXIS_BASE 0xffdf0000
179 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
180 #define QIXIS_LBMAP_SWITCH 0x06
181 #define QIXIS_LBMAP_MASK 0x0f
182 #define QIXIS_LBMAP_SHIFT 0
183 #define QIXIS_LBMAP_DFLTBANK 0x00
184 #define QIXIS_LBMAP_ALTBANK 0x04
185 #define QIXIS_RST_CTL_RESET 0x31
186 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
187 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
188 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
189 #define QIXIS_RST_FORCE_MEM 0x01
191 #define CONFIG_SYS_CSPR3_EXT (0xf)
192 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
196 #define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024)
197 #define CONFIG_SYS_CSOR3 0x0
198 /* QIXIS Timing parameters for IFC CS3 */
199 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
200 FTIM0_GPCM_TEADC(0x0e) | \
201 FTIM0_GPCM_TEAHC(0x0e))
202 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
203 FTIM1_GPCM_TRAD(0x3f))
204 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
205 FTIM2_GPCM_TCH(0x8) | \
206 FTIM2_GPCM_TWP(0x1f))
207 #define CONFIG_SYS_CS3_FTIM3 0x0
209 #define CONFIG_NAND_FSL_IFC
210 #define CONFIG_SYS_NAND_BASE 0xff800000
211 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
213 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
214 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
215 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
216 | CSPR_MSEL_NAND /* MSEL = NAND */ \
218 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
220 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
221 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
222 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
223 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
224 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
225 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
226 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
228 #define CONFIG_SYS_NAND_ONFI_DETECTION
230 /* ONFI NAND Flash mode0 Timing Params */
231 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
232 FTIM0_NAND_TWP(0x18) | \
233 FTIM0_NAND_TWCHT(0x07) | \
234 FTIM0_NAND_TWH(0x0a))
235 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
236 FTIM1_NAND_TWBE(0x39) | \
237 FTIM1_NAND_TRR(0x0e) | \
238 FTIM1_NAND_TRP(0x18))
239 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
240 FTIM2_NAND_TREH(0x0a) | \
241 FTIM2_NAND_TWHRE(0x1e))
242 #define CONFIG_SYS_NAND_FTIM3 0x0
244 #define CONFIG_SYS_NAND_DDR_LAW 11
245 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
246 #define CONFIG_SYS_MAX_NAND_DEVICE 1
248 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
250 #if defined(CONFIG_MTD_RAW_NAND)
251 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
252 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
253 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
254 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
255 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
256 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
257 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
258 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
259 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
260 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
261 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
262 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
263 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
264 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
265 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
266 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
267 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
268 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
269 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
270 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
271 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
272 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
273 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
274 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
276 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
277 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
278 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
279 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
280 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
281 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
282 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
283 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
284 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
285 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
286 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
287 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
288 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
289 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
290 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
291 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
292 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
293 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
294 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
295 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
296 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
297 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
298 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
299 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
302 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
304 #if defined(CONFIG_RAMBOOT_PBL)
305 #define CONFIG_SYS_RAMBOOT
308 #define CONFIG_HWCONFIG
310 /* define to use L1 as initial stack */
311 #define CONFIG_L1_INIT_RAM
312 #define CONFIG_SYS_INIT_RAM_LOCK
313 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
314 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
315 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
316 /* The assembler doesn't like typecast */
317 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
318 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
319 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
320 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
322 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
323 GENERATED_GBL_DATA_SIZE)
324 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
326 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
327 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
329 /* Serial Port - controlled on board with jumper J8
333 #define CONFIG_SYS_NS16550_SERIAL
334 #define CONFIG_SYS_NS16550_REG_SIZE 1
335 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
337 #define CONFIG_SYS_BAUDRATE_TABLE \
338 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
340 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
341 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
342 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
343 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
346 #define CONFIG_FSL_DIU_FB
347 #ifdef CONFIG_FSL_DIU_FB
348 #define CONFIG_FSL_DIU_CH7301
349 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000)
350 #define CONFIG_VIDEO_LOGO
351 #define CONFIG_VIDEO_BMP_LOGO
352 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
354 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
355 * disable empty flash sector detection, which is I/O-intensive.
357 #undef CONFIG_SYS_FLASH_EMPTY_INFO
362 #ifndef CONFIG_DM_I2C
363 #define CONFIG_SYS_I2C
364 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
365 #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */
366 #define CONFIG_SYS_FSL_I2C2_SPEED 50000
367 #define CONFIG_SYS_FSL_I2C3_SPEED 50000
368 #define CONFIG_SYS_FSL_I2C4_SPEED 50000
369 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
370 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
371 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
372 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
373 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
374 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
375 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
376 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
379 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
381 #define I2C_MUX_PCA_ADDR 0x77
382 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
384 /* I2C bus multiplexer */
385 #define I2C_MUX_CH_DEFAULT 0x8
386 #define I2C_MUX_CH_DIU 0xC
388 /* LDI/DVI Encoder for display */
389 #define CONFIG_SYS_I2C_LDI_ADDR 0x38
390 #define CONFIG_SYS_I2C_DVI_ADDR 0x75
391 #define CONFIG_SYS_I2C_DVI_BUS_NUM 0
397 #define CONFIG_RTC_DS3231 1
398 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
401 * eSPI - Enhanced SPI
406 * Memory space is mapped 1-1, but I/O space must start from 0.
410 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
412 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
413 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
414 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
415 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
416 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
417 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
418 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
419 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
422 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
424 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
425 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
426 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
427 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
428 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
429 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
430 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
431 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
434 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
436 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
437 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
438 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
439 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
440 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
441 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
442 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
443 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
446 /* controller 4, Base address 203000 */
448 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000
449 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
450 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull
451 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
452 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000
453 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
454 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
455 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
458 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
459 #endif /* CONFIG_PCI */
462 #define CONFIG_FSL_SATA_V2
463 #ifdef CONFIG_FSL_SATA_V2
464 #define CONFIG_SYS_SATA_MAX_DEVICE 2
466 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
467 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
469 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
470 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
478 #define CONFIG_HAS_FSL_DR_USB
480 #ifdef CONFIG_HAS_FSL_DR_USB
481 #ifdef CONFIG_USB_EHCI_HCD
482 #define CONFIG_USB_EHCI_FSL
483 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
488 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
489 #define CONFIG_FSL_ESDHC_ADAPTER_IDENT
493 #ifndef CONFIG_NOBQFMAN
494 #define CONFIG_SYS_BMAN_NUM_PORTALS 10
495 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
496 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
497 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
498 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
499 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
500 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
501 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
502 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
503 CONFIG_SYS_BMAN_CENA_SIZE)
504 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
505 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
506 #define CONFIG_SYS_QMAN_NUM_PORTALS 10
507 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
508 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
509 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
510 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
511 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
512 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
513 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
514 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
515 CONFIG_SYS_QMAN_CENA_SIZE)
516 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
517 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
519 #define CONFIG_SYS_DPAA_FMAN
520 #define CONFIG_SYS_DPAA_PME
522 /* Default address of microcode for the Linux Fman driver */
523 #if defined(CONFIG_SPIFLASH)
525 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
526 * env, so we got 0x110000.
528 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
529 #elif defined(CONFIG_SDCARD)
531 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
532 * about 825KB (1650 blocks), Env is stored after the image, and the env size is
533 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
535 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
536 #elif defined(CONFIG_MTD_RAW_NAND)
537 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
539 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
540 #define CONFIG_SYS_QE_FW_ADDR 0xEFF10000
542 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
543 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
544 #endif /* CONFIG_NOBQFMAN */
546 #ifdef CONFIG_SYS_DPAA_FMAN
547 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
548 #define SGMII_CARD_PORT2_PHY_ADDR 0x10
549 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
550 #define SGMII_CARD_PORT4_PHY_ADDR 0x11
553 #ifdef CONFIG_FMAN_ENET
554 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x01
555 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x02
557 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c
558 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d
559 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e
560 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f
562 #define CONFIG_ETHPRIME "FM1@DTSEC1"
565 /* Enable VSC9953 L2 Switch driver */
566 #define CONFIG_VSC9953
567 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x14
568 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x18
571 * Dynamic MTD Partition support with mtdparts
577 #define CONFIG_LOADS_ECHO /* echo on for serial download */
578 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
581 * Miscellaneous configurable options
583 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
586 * For booting Linux, the board info and command line data
587 * have to be in the first 64 MB of memory, since this is
588 * the maximum mapped by the Linux kernel during initialization.
590 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
591 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
593 #ifdef CONFIG_CMD_KGDB
594 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
598 * Environment Configuration
600 #define CONFIG_ROOTPATH "/opt/nfsroot"
601 #define CONFIG_BOOTFILE "uImage"
602 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
604 /* default location for tftp and bootm */
605 #define CONFIG_LOADADDR 1000000
607 #define __USB_PHY_TYPE utmi
609 #define CONFIG_EXTRA_ENV_SETTINGS \
610 "hwconfig=fsl_ddr:bank_intlv=auto;" \
611 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
613 "video-mode=fslfb:1024x768-32@60,monitor=dvi\0" \
614 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
615 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
616 "tftpflash=tftpboot $loadaddr $uboot && " \
617 "protect off $ubootaddr +$filesize && " \
618 "erase $ubootaddr +$filesize && " \
619 "cp.b $loadaddr $ubootaddr $filesize && " \
620 "protect on $ubootaddr +$filesize && " \
621 "cmp.b $loadaddr $ubootaddr $filesize\0" \
622 "consoledev=ttyS0\0" \
623 "ramdiskaddr=2000000\0" \
624 "ramdiskfile=t1040qds/ramdisk.uboot\0" \
625 "fdtaddr=1e00000\0" \
626 "fdtfile=t1040qds/t1040qds.dtb\0" \
629 #define CONFIG_LINUX \
630 "setenv bootargs root=/dev/ram rw " \
631 "console=$consoledev,$baudrate $othbootargs;" \
632 "setenv ramdiskaddr 0x02000000;" \
633 "setenv fdtaddr 0x00c00000;" \
634 "setenv loadaddr 0x1000000;" \
635 "bootm $loadaddr $ramdiskaddr $fdtaddr"
637 #define CONFIG_HDBOOT \
638 "setenv bootargs root=/dev/$bdev rw " \
639 "console=$consoledev,$baudrate $othbootargs;" \
640 "tftp $loadaddr $bootfile;" \
641 "tftp $fdtaddr $fdtfile;" \
642 "bootm $loadaddr - $fdtaddr"
644 #define CONFIG_NFSBOOTCOMMAND \
645 "setenv bootargs root=/dev/nfs rw " \
646 "nfsroot=$serverip:$rootpath " \
647 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
648 "console=$consoledev,$baudrate $othbootargs;" \
649 "tftp $loadaddr $bootfile;" \
650 "tftp $fdtaddr $fdtfile;" \
651 "bootm $loadaddr - $fdtaddr"
653 #define CONFIG_RAMBOOTCOMMAND \
654 "setenv bootargs root=/dev/ram rw " \
655 "console=$consoledev,$baudrate $othbootargs;" \
656 "tftp $ramdiskaddr $ramdiskfile;" \
657 "tftp $loadaddr $bootfile;" \
658 "tftp $fdtaddr $fdtfile;" \
659 "bootm $loadaddr $ramdiskaddr $fdtaddr"
661 #define CONFIG_BOOTCOMMAND CONFIG_LINUX
663 #include <asm/fsl_secure_boot.h>
665 #endif /* __CONFIG_H */