include/configs/MPC8323ERDB.h

   1 /*
   2  * Copyright (C) 2007 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms of the GNU General Public License version 2 as published
   6  * by the Free Software Foundation.
   7  */
   8
   9 #ifndef __CONFIG_H
  10 #define __CONFIG_H
  11
  12 /*
  13  * High Level Configuration Options
  14  */
  15 #define CONFIG_E300             1       /* E300 family */
  16
  17 /*
  18  * System IO Config
  19  */
  20 #define CONFIG_SYS_SICRL                0x00000000
  21
  22 /*
  23  * DDR Setup
  24  */
  25 #define CONFIG_SYS_SDRAM_BASE   0x00000000      /* DDR is system memory */
  26
  27 #undef CONFIG_SPD_EEPROM
  28 #if defined(CONFIG_SPD_EEPROM)
  29 /* Determine DDR configuration from I2C interface
  30  */
  31 #define SPD_EEPROM_ADDRESS      0x51    /* DDR SODIMM */
  32 #else
  33 /* Manually set up DDR parameters
  34  */
  35 #define CONFIG_SYS_DDR_SIZE     64      /* MB */
  36 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
  37                                 | CSCONFIG_ROW_BIT_13 \
  38                                 | CSCONFIG_COL_BIT_9)
  39                                 /* 0x80010101 */
  40 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
  41                                 | (0 << TIMING_CFG0_WRT_SHIFT) \
  42                                 | (0 << TIMING_CFG0_RRT_SHIFT) \
  43                                 | (0 << TIMING_CFG0_WWT_SHIFT) \
  44                                 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
  45                                 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
  46                                 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
  47                                 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
  48                                 /* 0x00220802 */
  49 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
  50                                 | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
  51                                 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
  52                                 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
  53                                 | (3 << TIMING_CFG1_REFREC_SHIFT) \
  54                                 | (2 << TIMING_CFG1_WRREC_SHIFT) \
  55                                 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
  56                                 | (2 << TIMING_CFG1_WRTORD_SHIFT))
  57                                 /* 0x26253222 */
  58 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
  59                                 | (31 << TIMING_CFG2_CPO_SHIFT) \
  60                                 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
  61                                 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
  62                                 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
  63                                 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
  64                                 | (7 << TIMING_CFG2_FOUR_ACT_SHIFT))
  65                                 /* 0x1f9048c7 */
  66 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
  67 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
  68                                 /* 0x02000000 */
  69 #define CONFIG_SYS_DDR_MODE     ((0x4448 << SDRAM_MODE_ESD_SHIFT) \
  70                                 | (0x0232 << SDRAM_MODE_SD_SHIFT))
  71                                 /* 0x44480232 */
  72 #define CONFIG_SYS_DDR_MODE2    0x8000c000
  73 #define CONFIG_SYS_DDR_INTERVAL ((800 << SDRAM_INTERVAL_REFINT_SHIFT) \
  74                                 | (100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
  75                                 /* 0x03200064 */
  76 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000003
  77 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SREN \
  78                                 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
  79                                 | SDRAM_CFG_32_BE)
  80                                 /* 0x43080000 */
  81 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000
  82 #endif
  83
  84 /*
  85  * Memory test
  86  */
  87 #undef CONFIG_SYS_DRAM_TEST             /* memory test, takes time */
  88 #define CONFIG_SYS_MEMTEST_START        0x00030000      /* memtest region */
  89 #define CONFIG_SYS_MEMTEST_END          0x03f00000
  90
  91 /*
  92  * The reserved memory
  93  */
  94 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
  95
  96 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
  97 #define CONFIG_SYS_RAMBOOT
  98 #else
  99 #undef  CONFIG_SYS_RAMBOOT
 100 #endif
 101
 102 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
 103 #define CONFIG_SYS_MONITOR_LEN  (512 * 1024)    /* Reserve 512 kB for Mon */
 104 #define CONFIG_SYS_MALLOC_LEN   (256 * 1024)    /* Reserved for malloc */
 105
 106 /*
 107  * Initial RAM Base Address Setup
 108  */
 109 #define CONFIG_SYS_INIT_RAM_LOCK        1
 110 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
 111 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* Size of used area in RAM */
 112 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 113                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 114
 115 /*
 116  * FLASH on the Local Bus
 117  */
 118 #define CONFIG_SYS_FLASH_BASE   0xFE000000      /* FLASH base address */
 119 #define CONFIG_SYS_FLASH_SIZE           16      /* FLASH size is 16M */
 120
 121
 122
 123 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 124 #define CONFIG_SYS_MAX_FLASH_SECT       128     /* sectors per device */
 125
 126 #undef CONFIG_SYS_FLASH_CHECKSUM
 127
 128 /*
 129  * Serial Port
 130  */
 131 #define CONFIG_SYS_NS16550_SERIAL
 132 #define CONFIG_SYS_NS16550_REG_SIZE     1
 133 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 134
 135 #define CONFIG_SYS_BAUDRATE_TABLE  \
 136                 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 137
 138 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 139 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 140
 141 /* I2C */
 142 #define CONFIG_SYS_I2C
 143 #define CONFIG_SYS_I2C_FSL
 144 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 145 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 146 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 147 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x51} }
 148
 149 /*
 150  * Config on-board EEPROM
 151  */
 152 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x50
 153 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          2
 154 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       6
 155 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10
 156
 157 /*
 158  * General PCI
 159  * Addresses are mapped 1-1.
 160  */
 161 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 162 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 163 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
 164 #define CONFIG_SYS_PCI1_MMIO_BASE       0x90000000
 165 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
 166 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
 167 #define CONFIG_SYS_PCI1_IO_BASE         0xd0000000
 168 #define CONFIG_SYS_PCI1_IO_PHYS         CONFIG_SYS_PCI1_IO_BASE
 169 #define CONFIG_SYS_PCI1_IO_SIZE         0x04000000      /* 64M */
 170
 171 #ifdef CONFIG_PCI
 172 #define CONFIG_PCI_INDIRECT_BRIDGE
 173 #define CONFIG_PCI_SKIP_HOST_BRIDGE
 174
 175 #undef CONFIG_EEPRO100
 176 #undef CONFIG_PCI_SCAN_SHOW     /* show pci devices on startup */
 177 #define CONFIG_SYS_PCI_SUBSYS_VENDORID  0x1957  /* Freescale */
 178
 179 #endif  /* CONFIG_PCI */
 180
 181 /*
 182  * QE UEC ethernet configuration
 183  */
 184 #define CONFIG_UEC_ETH
 185 #define CONFIG_ETHPRIME         "UEC0"
 186
 187 #define CONFIG_UEC_ETH1         /* ETH3 */
 188
 189 #ifdef CONFIG_UEC_ETH1
 190 #define CONFIG_SYS_UEC1_UCC_NUM 2       /* UCC3 */
 191 #define CONFIG_SYS_UEC1_RX_CLK          QE_CLK9
 192 #define CONFIG_SYS_UEC1_TX_CLK          QE_CLK10
 193 #define CONFIG_SYS_UEC1_ETH_TYPE        FAST_ETH
 194 #define CONFIG_SYS_UEC1_PHY_ADDR        4
 195 #define CONFIG_SYS_UEC1_INTERFACE_TYPE  PHY_INTERFACE_MODE_MII
 196 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
 197 #endif
 198
 199 #define CONFIG_UEC_ETH2         /* ETH4 */
 200
 201 #ifdef CONFIG_UEC_ETH2
 202 #define CONFIG_SYS_UEC2_UCC_NUM 1       /* UCC2 */
 203 #define CONFIG_SYS_UEC2_RX_CLK          QE_CLK16
 204 #define CONFIG_SYS_UEC2_TX_CLK          QE_CLK3
 205 #define CONFIG_SYS_UEC2_ETH_TYPE        FAST_ETH
 206 #define CONFIG_SYS_UEC2_PHY_ADDR        0
 207 #define CONFIG_SYS_UEC2_INTERFACE_TYPE  PHY_INTERFACE_MODE_MII
 208 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
 209 #endif
 210
 211 /*
 212  * Environment
 213  */
 214 #ifndef CONFIG_SYS_RAMBOOT
 215         #define CONFIG_ENV_ADDR         \
 216                         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 217         #define CONFIG_ENV_SECT_SIZE    0x20000
 218         #define CONFIG_ENV_SIZE         0x2000
 219 #else
 220         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 221         #define CONFIG_ENV_SIZE         0x2000
 222 #endif
 223
 224 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 225 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 226
 227 /*
 228  * BOOTP options
 229  */
 230 #define CONFIG_BOOTP_BOOTFILESIZE
 231
 232 /*
 233  * Command line configuration.
 234  */
 235
 236 #undef CONFIG_WATCHDOG          /* watchdog disabled */
 237
 238 /*
 239  * Miscellaneous configurable options
 240  */
 241 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 242
 243 /*
 244  * For booting Linux, the board info and command line data
 245  * have to be in the first 256 MB of memory, since this is
 246  * the maximum mapped by the Linux kernel during initialization.
 247  */
 248                                         /* Initial Memory map for Linux */
 249 #define CONFIG_SYS_BOOTMAPSZ            (256 << 20)
 250 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 251
 252 #if (CONFIG_CMD_KGDB)
 253 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 254 #endif
 255
 256 /*
 257  * Environment Configuration
 258  */
 259 #define CONFIG_ENV_OVERWRITE
 260
 261 #define CONFIG_HAS_ETH0         /* add support for "ethaddr" */
 262 #define CONFIG_HAS_ETH1         /* add support for "eth1addr" */
 263
 264 /* use mac_read_from_eeprom() to read ethaddr from I2C EEPROM
 265  * (see CONFIG_SYS_I2C_EEPROM) */
 266                                         /* MAC address offset in I2C EEPROM */
 267 #define CONFIG_SYS_I2C_MAC_OFFSET       0x7f00
 268
 269 #define CONFIG_NETDEV           "eth1"
 270
 271 #define CONFIG_HOSTNAME         "mpc8323erdb"
 272 #define CONFIG_ROOTPATH         "/nfsroot"
 273 #define CONFIG_BOOTFILE         "uImage"
 274                                 /* U-Boot image on TFTP server */
 275 #define CONFIG_UBOOTPATH        "u-boot.bin"
 276 #define CONFIG_FDTFILE          "mpc832x_rdb.dtb"
 277 #define CONFIG_RAMDISKFILE      "rootfs.ext2.gz.uboot"
 278
 279                                 /* default location for tftp and bootm */
 280 #define CONFIG_LOADADDR         800000
 281
 282 #define CONFIG_EXTRA_ENV_SETTINGS \
 283         "netdev=" CONFIG_NETDEV "\0"                                    \
 284         "uboot=" CONFIG_UBOOTPATH "\0"                                  \
 285         "tftpflash=tftp $loadaddr $uboot;"                              \
 286                 "protect off " __stringify(CONFIG_SYS_TEXT_BASE)        \
 287                         " +$filesize; " \
 288                 "erase " __stringify(CONFIG_SYS_TEXT_BASE)              \
 289                         " +$filesize; " \
 290                 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)     \
 291                         " $filesize; "  \
 292                 "protect on " __stringify(CONFIG_SYS_TEXT_BASE)         \
 293                         " +$filesize; " \
 294                 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)    \
 295                         " $filesize\0"  \
 296         "fdtaddr=780000\0"                                              \
 297         "fdtfile=" CONFIG_FDTFILE "\0"                                  \
 298         "ramdiskaddr=1000000\0"                                         \
 299         "ramdiskfile=" CONFIG_RAMDISKFILE "\0"                          \
 300         "console=ttyS0\0"                                               \
 301         "setbootargs=setenv bootargs "                                  \
 302                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"\
 303         "setipargs=setenv bootargs nfsroot=$serverip:$rootpath "        \
 304                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\
 305                                                                 "$netdev:off "\
 306                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
 307
 308 #define CONFIG_NFSBOOTCOMMAND                                           \
 309         "setenv rootdev /dev/nfs;"                                      \
 310         "run setbootargs;"                                              \
 311         "run setipargs;"                                                \
 312         "tftp $loadaddr $bootfile;"                                     \
 313         "tftp $fdtaddr $fdtfile;"                                       \
 314         "bootm $loadaddr - $fdtaddr"
 315
 316 #define CONFIG_RAMBOOTCOMMAND                                           \
 317         "setenv rootdev /dev/ram;"                                      \
 318         "run setbootargs;"                                              \
 319         "tftp $ramdiskaddr $ramdiskfile;"                               \
 320         "tftp $loadaddr $bootfile;"                                     \
 321         "tftp $fdtaddr $fdtfile;"                                       \
 322         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 323
 324 #endif  /* __CONFIG_H */