include/configs/M5272C3.h

   1 /*
   2  * Configuation settings for the Motorola MC5272C3 board.
   3  *
   4  * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 /*
  10  * board/config.h - configuration options, board specific
  11  */
  12
  13 #ifndef _M5272C3_H
  14 #define _M5272C3_H
  15
  16 /*
  17  * High Level Configuration Options
  18  * (easy to change)
  19  */
  20 #define CONFIG_MCFTMR
  21
  22 #define CONFIG_MCFUART
  23 #define CONFIG_SYS_UART_PORT            (0)
  24
  25 #undef CONFIG_WATCHDOG
  26 #define CONFIG_WATCHDOG_TIMEOUT 10000   /* timeout in milliseconds */
  27
  28 #undef CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */
  29
  30 /* Configuration for environment
  31  * Environment is embedded in u-boot in the second sector of the flash
  32  */
  33 #ifndef CONFIG_MONITOR_IS_IN_RAM
  34 #define CONFIG_ENV_OFFSET               0x4000
  35 #define CONFIG_ENV_SECT_SIZE    0x2000
  36 #else
  37 #define CONFIG_ENV_ADDR         0xffe04000
  38 #define CONFIG_ENV_SECT_SIZE    0x2000
  39 #endif
  40
  41 #define LDS_BOARD_TEXT \
  42         . = DEFINED(env_offset) ? env_offset : .; \
  43         env/embedded.o(.text);
  44
  45 /*
  46  * BOOTP options
  47  */
  48 #define CONFIG_BOOTP_BOOTFILESIZE
  49
  50 /*
  51  * Command line configuration.
  52  */
  53
  54 #define CONFIG_MCFFEC
  55 #ifdef CONFIG_MCFFEC
  56 #       define CONFIG_MII               1
  57 #       define CONFIG_MII_INIT          1
  58 #       define CONFIG_SYS_DISCOVER_PHY
  59 #       define CONFIG_SYS_RX_ETH_BUFFER 8
  60 #       define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  61
  62 #       define CONFIG_SYS_FEC0_PINMUX           0
  63 #       define CONFIG_SYS_FEC0_MIIBASE          CONFIG_SYS_FEC0_IOBASE
  64 #       define MCFFEC_TOUT_LOOP         50000
  65 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
  66 #       ifndef CONFIG_SYS_DISCOVER_PHY
  67 #               define FECDUPLEX        FULL
  68 #               define FECSPEED         _100BASET
  69 #       else
  70 #               ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  71 #                       define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  72 #               endif
  73 #       endif                   /* CONFIG_SYS_DISCOVER_PHY */
  74 #endif
  75
  76 #ifdef CONFIG_MCFFEC
  77 #       define CONFIG_IPADDR    192.162.1.2
  78 #       define CONFIG_NETMASK   255.255.255.0
  79 #       define CONFIG_SERVERIP  192.162.1.1
  80 #       define CONFIG_GATEWAYIP 192.162.1.1
  81 #endif                          /* CONFIG_MCFFEC */
  82
  83 #define CONFIG_HOSTNAME         M5272C3
  84 #define CONFIG_EXTRA_ENV_SETTINGS               \
  85         "netdev=eth0\0"                         \
  86         "loadaddr=10000\0"                      \
  87         "u-boot=u-boot.bin\0"                   \
  88         "load=tftp ${loadaddr) ${u-boot}\0"     \
  89         "upd=run load; run prog\0"              \
  90         "prog=prot off ffe00000 ffe3ffff;"      \
  91         "era ffe00000 ffe3ffff;"                \
  92         "cp.b ${loadaddr} ffe00000 ${filesize};"\
  93         "save\0"                                \
  94         ""
  95
  96 #define CONFIG_SYS_LOAD_ADDR            0x20000
  97 #define CONFIG_SYS_MEMTEST_START        0x400
  98 #define CONFIG_SYS_MEMTEST_END          0x380000
  99 #define CONFIG_SYS_CLK                  66000000
 100
 101 /*
 102  * Low Level Configuration Settings
 103  * (address mappings, register initial values, etc.)
 104  * You should know what you are doing if you make changes here.
 105  */
 106 #define CONFIG_SYS_MBAR         0x10000000      /* Register Base Addrs */
 107 #define CONFIG_SYS_SCR                  0x0003
 108 #define CONFIG_SYS_SPR                  0xffff
 109
 110 /*-----------------------------------------------------------------------
 111  * Definitions for initial stack pointer and data area (in DPRAM)
 112  */
 113 #define CONFIG_SYS_INIT_RAM_ADDR        0x20000000
 114 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000  /* Size of used area in internal SRAM    */
 115 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 116 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 117
 118 /*-----------------------------------------------------------------------
 119  * Start addresses for the final memory configuration
 120  * (Set up by the startup code)
 121  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 122  */
 123 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 124 #define CONFIG_SYS_SDRAM_SIZE           4       /* SDRAM size in MB */
 125 #define CONFIG_SYS_FLASH_BASE           0xffe00000
 126
 127 #ifdef  CONFIG_MONITOR_IS_IN_RAM
 128 #define CONFIG_SYS_MONITOR_BASE 0x20000
 129 #else
 130 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
 131 #endif
 132
 133 #define CONFIG_SYS_MONITOR_LEN          0x20000
 134 #define CONFIG_SYS_MALLOC_LEN           (256 << 10)
 135 #define CONFIG_SYS_BOOTPARAMS_LEN       64*1024
 136
 137 /*
 138  * For booting Linux, the board info and command line data
 139  * have to be in the first 8 MB of memory, since this is
 140  * the maximum mapped by the Linux kernel during initialization ??
 141  */
 142 #define CONFIG_SYS_BOOTMAPSZ            (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
 143
 144 /*
 145  * FLASH organization
 146  */
 147 #define CONFIG_SYS_FLASH_CFI
 148 #ifdef CONFIG_SYS_FLASH_CFI
 149 #       define CONFIG_FLASH_CFI_DRIVER  1
 150 #       define CONFIG_SYS_FLASH_SIZE            0x800000        /* Max size that the board might have */
 151 #       define CONFIG_SYS_FLASH_CFI_WIDTH       FLASH_CFI_16BIT
 152 #       define CONFIG_SYS_MAX_FLASH_BANKS       1       /* max number of memory banks */
 153 #       define CONFIG_SYS_MAX_FLASH_SECT        137     /* max number of sectors on one chip */
 154 #       define CONFIG_SYS_FLASH_PROTECTION      /* "Real" (hardware) sectors protection */
 155 #endif
 156
 157 /*-----------------------------------------------------------------------
 158  * Cache Configuration
 159  */
 160 #define CONFIG_SYS_CACHELINE_SIZE       16
 161
 162 #define ICACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 163                                          CONFIG_SYS_INIT_RAM_SIZE - 8)
 164 #define DCACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 165                                          CONFIG_SYS_INIT_RAM_SIZE - 4)
 166 #define CONFIG_SYS_ICACHE_INV           (CF_CACR_CINV | CF_CACR_INVI)
 167 #define CONFIG_SYS_CACHE_ACR0           (CONFIG_SYS_SDRAM_BASE | \
 168                                          CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
 169                                          CF_ACR_EN | CF_ACR_SM_ALL)
 170 #define CONFIG_SYS_CACHE_ICACR          (CF_CACR_CENB | CF_CACR_CINV | \
 171                                          CF_CACR_DISD | CF_CACR_INVI | \
 172                                          CF_CACR_CEIB | CF_CACR_DCM | \
 173                                          CF_CACR_EUSP)
 174
 175 /*-----------------------------------------------------------------------
 176  * Memory bank definitions
 177  */
 178 #define CONFIG_SYS_BR0_PRELIM           0xFFE00201
 179 #define CONFIG_SYS_OR0_PRELIM           0xFFE00014
 180 #define CONFIG_SYS_BR1_PRELIM           0
 181 #define CONFIG_SYS_OR1_PRELIM           0
 182 #define CONFIG_SYS_BR2_PRELIM           0x30000001
 183 #define CONFIG_SYS_OR2_PRELIM           0xFFF80000
 184 #define CONFIG_SYS_BR3_PRELIM           0
 185 #define CONFIG_SYS_OR3_PRELIM           0
 186 #define CONFIG_SYS_BR4_PRELIM           0
 187 #define CONFIG_SYS_OR4_PRELIM           0
 188 #define CONFIG_SYS_BR5_PRELIM           0
 189 #define CONFIG_SYS_OR5_PRELIM           0
 190 #define CONFIG_SYS_BR6_PRELIM           0
 191 #define CONFIG_SYS_OR6_PRELIM           0
 192 #define CONFIG_SYS_BR7_PRELIM           0x00000701
 193 #define CONFIG_SYS_OR7_PRELIM           0xFFC0007C
 194
 195 /*-----------------------------------------------------------------------
 196  * Port configuration
 197  */
 198 #define CONFIG_SYS_PACNT                0x00000000
 199 #define CONFIG_SYS_PADDR                0x0000
 200 #define CONFIG_SYS_PADAT                0x0000
 201 #define CONFIG_SYS_PBCNT                0x55554155      /* Ethernet/UART configuration */
 202 #define CONFIG_SYS_PBDDR                0x0000
 203 #define CONFIG_SYS_PBDAT                0x0000
 204 #define CONFIG_SYS_PDCNT                0x00000000
 205 #endif                          /* _M5272C3_H */