include/configs/B4860QDS.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2011-2012 Freescale Semiconductor, Inc.
   4  */
   5
   6 #ifndef __CONFIG_H
   7 #define __CONFIG_H
   8
   9 /*
  10  * B4860 QDS board configuration file
  11  */
  12 #ifdef CONFIG_RAMBOOT_PBL
  13 #define CONFIG_SYS_FSL_PBL_PBI  $(SRCTREE)/board/freescale/b4860qds/b4_pbi.cfg
  14 #define CONFIG_SYS_FSL_PBL_RCW  $(SRCTREE)/board/freescale/b4860qds/b4_rcw.cfg
  15 #ifndef CONFIG_NAND
  16 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
  17 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
  18 #else
  19 #define CONFIG_SPL_FLUSH_IMAGE
  20 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  21 #define CONFIG_SPL_TEXT_BASE            0xFFFD8000
  22 #define CONFIG_SPL_PAD_TO               0x40000
  23 #define CONFIG_SPL_MAX_SIZE             0x28000
  24 #define RESET_VECTOR_OFFSET             0x27FFC
  25 #define BOOT_PAGE_OFFSET                0x27000
  26 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
  27 #define CONFIG_SYS_NAND_U_BOOT_DST      0x00200000
  28 #define CONFIG_SYS_NAND_U_BOOT_START    0x00200000
  29 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (256 << 10)
  30 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
  31 #define CONFIG_SPL_NAND_BOOT
  32 #ifdef CONFIG_SPL_BUILD
  33 #define CONFIG_SPL_SKIP_RELOCATE
  34 #define CONFIG_SPL_COMMON_INIT_DDR
  35 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  36 #endif
  37 #endif
  38 #endif
  39
  40 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  41 /* Set 1M boot space */
  42 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  43 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  44                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  45 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  46 #endif
  47
  48 /* High Level Configuration Options */
  49 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  50
  51 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  52 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  53 #endif
  54
  55 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  56 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
  57 #define CONFIG_PCIE1                    /* PCIE controller 1 */
  58 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
  59 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
  60
  61 #ifndef CONFIG_ARCH_B4420
  62 #define CONFIG_SYS_SRIO
  63 #define CONFIG_SRIO1                    /* SRIO port 1 */
  64 #define CONFIG_SRIO2                    /* SRIO port 2 */
  65 #define CONFIG_SRIO_PCIE_BOOT_MASTER
  66 #endif
  67
  68 /* I2C bus multiplexer */
  69 #define I2C_MUX_PCA_ADDR                0x77
  70
  71 /* VSC Crossbar switches */
  72 #define CONFIG_VSC_CROSSBAR
  73 #define I2C_CH_DEFAULT                  0x8
  74 #define I2C_CH_VSC3316                  0xc
  75 #define I2C_CH_VSC3308                  0xd
  76
  77 #define VSC3316_TX_ADDRESS              0x70
  78 #define VSC3316_RX_ADDRESS              0x71
  79 #define VSC3308_TX_ADDRESS              0x02
  80 #define VSC3308_RX_ADDRESS              0x03
  81
  82 /* IDT clock synthesizers */
  83 #define CONFIG_IDT8T49N222A
  84 #define I2C_CH_IDT                     0x9
  85
  86 #define IDT_SERDES1_ADDRESS            0x6E
  87 #define IDT_SERDES2_ADDRESS            0x6C
  88
  89 /* Voltage monitor on channel 2*/
  90 #define I2C_MUX_CH_VOL_MONITOR          0xa
  91 #define I2C_VOL_MONITOR_ADDR            0x40
  92 #define I2C_VOL_MONITOR_BUS_V_OFFSET    0x2
  93 #define I2C_VOL_MONITOR_BUS_V_OVF       0x1
  94 #define I2C_VOL_MONITOR_BUS_V_SHIFT     3
  95
  96 #define CONFIG_ZM7300
  97 #define I2C_MUX_CH_DPM                  0xa
  98 #define I2C_DPM_ADDR                    0x28
  99
 100 #define CONFIG_ENV_OVERWRITE
 101
 102 #ifndef CONFIG_MTD_NOR_FLASH
 103 #else
 104 #define CONFIG_FLASH_CFI_DRIVER
 105 #define CONFIG_SYS_FLASH_CFI
 106 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 107 #endif
 108
 109 #if defined(CONFIG_SPIFLASH)
 110 #define CONFIG_SYS_EXTRA_ENV_RELOC
 111 #define CONFIG_ENV_SPI_BUS              0
 112 #define CONFIG_ENV_SPI_CS               0
 113 #define CONFIG_ENV_SPI_MAX_HZ           10000000
 114 #define CONFIG_ENV_SPI_MODE             0
 115 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
 116 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
 117 #define CONFIG_ENV_SECT_SIZE            0x10000
 118 #elif defined(CONFIG_SDCARD)
 119 #define CONFIG_SYS_EXTRA_ENV_RELOC
 120 #define CONFIG_SYS_MMC_ENV_DEV          0
 121 #define CONFIG_ENV_SIZE                 0x2000
 122 #define CONFIG_ENV_OFFSET               (512 * 1097)
 123 #elif defined(CONFIG_NAND)
 124 #define CONFIG_SYS_EXTRA_ENV_RELOC
 125 #define CONFIG_ENV_SIZE                 0x2000
 126 #define CONFIG_ENV_OFFSET               (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
 127 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 128 #define CONFIG_ENV_ADDR         0xffe20000
 129 #define CONFIG_ENV_SIZE         0x2000
 130 #elif defined(CONFIG_ENV_IS_NOWHERE)
 131 #define CONFIG_ENV_SIZE         0x2000
 132 #else
 133 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 134 #define CONFIG_ENV_SIZE         0x2000
 135 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 136 #endif
 137
 138 #ifndef __ASSEMBLY__
 139 unsigned long get_board_sys_clk(void);
 140 unsigned long get_board_ddr_clk(void);
 141 #endif
 142 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk() /* sysclk for MPC85xx */
 143 #define CONFIG_DDR_CLK_FREQ     get_board_ddr_clk()
 144
 145 /*
 146  * These can be toggled for performance analysis, otherwise use default.
 147  */
 148 #define CONFIG_SYS_CACHE_STASHING
 149 #define CONFIG_BTB                      /* toggle branch predition */
 150 #define CONFIG_DDR_ECC
 151 #ifdef CONFIG_DDR_ECC
 152 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 153 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 154 #endif
 155
 156 #define CONFIG_ENABLE_36BIT_PHYS
 157
 158 #ifdef CONFIG_PHYS_64BIT
 159 #define CONFIG_ADDR_MAP
 160 #define CONFIG_SYS_NUM_ADDR_MAP         64      /* number of TLB1 entries */
 161 #endif
 162
 163 #if 0
 164 #define CONFIG_POST CONFIG_SYS_POST_MEMORY      /* test POST memory test */
 165 #endif
 166 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
 167 #define CONFIG_SYS_MEMTEST_END          0x00400000
 168
 169 /*
 170  *  Config the L3 Cache as L3 SRAM
 171  */
 172 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
 173 #define CONFIG_SYS_L3_SIZE              256 << 10
 174 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
 175 #ifdef CONFIG_NAND
 176 #define CONFIG_ENV_ADDR                 (CONFIG_SPL_GD_ADDR + 4 * 1024)
 177 #endif
 178 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
 179 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (30 << 10)
 180 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
 181
 182 #ifdef CONFIG_PHYS_64BIT
 183 #define CONFIG_SYS_DCSRBAR              0xf0000000
 184 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
 185 #endif
 186
 187 /* EEPROM */
 188 #define CONFIG_ID_EEPROM
 189 #define CONFIG_SYS_I2C_EEPROM_NXID
 190 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 191 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 192 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 193 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 194 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
 195
 196 /*
 197  * DDR Setup
 198  */
 199 #define CONFIG_VERY_BIG_RAM
 200 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 201 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 202
 203 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 204 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
 205
 206 #define CONFIG_DDR_SPD
 207 #define CONFIG_SYS_DDR_RAW_TIMING
 208 #ifndef CONFIG_SPL_BUILD
 209 #define CONFIG_FSL_DDR_INTERACTIVE
 210 #endif
 211
 212 #define CONFIG_SYS_SPD_BUS_NUM  0
 213 #define SPD_EEPROM_ADDRESS1     0x51
 214 #define SPD_EEPROM_ADDRESS2     0x53
 215
 216 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1
 217 #define CONFIG_SYS_SDRAM_SIZE   2048    /* for fixed parameter use */
 218
 219 /*
 220  * IFC Definitions
 221  */
 222 #define CONFIG_SYS_FLASH_BASE   0xe0000000
 223 #ifdef CONFIG_PHYS_64BIT
 224 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 225 #else
 226 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 227 #endif
 228
 229 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 230 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
 231                                 + 0x8000000) | \
 232                                 CSPR_PORT_SIZE_16 | \
 233                                 CSPR_MSEL_NOR | \
 234                                 CSPR_V)
 235 #define CONFIG_SYS_NOR1_CSPR_EXT        (0xf)
 236 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 237                                 CSPR_PORT_SIZE_16 | \
 238                                 CSPR_MSEL_NOR | \
 239                                 CSPR_V)
 240 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128 * 1024 * 1024)
 241 /* NOR Flash Timing Params */
 242 #define CONFIG_SYS_NOR_CSOR     CSOR_NOR_ADM_SHIFT(4)
 243 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x01) | \
 244                                 FTIM0_NOR_TEADC(0x04) | \
 245                                 FTIM0_NOR_TEAHC(0x20))
 246 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 247                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 248                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 249 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x01) | \
 250                                 FTIM2_NOR_TCH(0x0E) | \
 251                                 FTIM2_NOR_TWPH(0x0E) | \
 252                                 FTIM2_NOR_TWP(0x1c))
 253 #define CONFIG_SYS_NOR_FTIM3    0x0
 254
 255 #define CONFIG_SYS_FLASH_QUIET_TEST
 256 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 257
 258 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 259 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 260 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 261 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 262
 263 #define CONFIG_SYS_FLASH_EMPTY_INFO
 264 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS \
 265                                         + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 266
 267 #define CONFIG_FSL_QIXIS        /* use common QIXIS code */
 268 #define CONFIG_FSL_QIXIS_V2
 269 #define QIXIS_BASE              0xffdf0000
 270 #ifdef CONFIG_PHYS_64BIT
 271 #define QIXIS_BASE_PHYS         (0xf00000000ull | QIXIS_BASE)
 272 #else
 273 #define QIXIS_BASE_PHYS         QIXIS_BASE
 274 #endif
 275 #define QIXIS_LBMAP_SWITCH              0x01
 276 #define QIXIS_LBMAP_MASK                0x0f
 277 #define QIXIS_LBMAP_SHIFT               0
 278 #define QIXIS_LBMAP_DFLTBANK            0x00
 279 #define QIXIS_LBMAP_ALTBANK             0x02
 280 #define QIXIS_RST_CTL_RESET             0x31
 281 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 282 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 283 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 284
 285 #define CONFIG_SYS_CSPR3_EXT    (0xf)
 286 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 287                                 | CSPR_PORT_SIZE_8 \
 288                                 | CSPR_MSEL_GPCM \
 289                                 | CSPR_V)
 290 #define CONFIG_SYS_AMASK3       IFC_AMASK(4 * 1024)
 291 #define CONFIG_SYS_CSOR3        0x0
 292 /* QIXIS Timing parameters for IFC CS3 */
 293 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 294                                         FTIM0_GPCM_TEADC(0x0e) | \
 295                                         FTIM0_GPCM_TEAHC(0x0e))
 296 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
 297                                         FTIM1_GPCM_TRAD(0x1f))
 298 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 299                                         FTIM2_GPCM_TCH(0x8) | \
 300                                         FTIM2_GPCM_TWP(0x1f))
 301 #define CONFIG_SYS_CS3_FTIM3            0x0
 302
 303 /* NAND Flash on IFC */
 304 #define CONFIG_NAND_FSL_IFC
 305 #define CONFIG_SYS_NAND_MAX_ECCPOS      256
 306 #define CONFIG_SYS_NAND_MAX_OOBFREE     2
 307 #define CONFIG_SYS_NAND_BASE            0xff800000
 308 #ifdef CONFIG_PHYS_64BIT
 309 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 310 #else
 311 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 312 #endif
 313
 314 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 315 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 316                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 317                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 318                                 | CSPR_V)
 319 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64 * 1024)
 320
 321 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 322                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 323                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 324                                 | CSOR_NAND_RAL_3       /* RAL = 2Byes */ \
 325                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 326                                 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
 327                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 328
 329 #define CONFIG_SYS_NAND_ONFI_DETECTION
 330
 331 /* ONFI NAND Flash mode0 Timing Params */
 332 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 333                                         FTIM0_NAND_TWP(0x18)   | \
 334                                         FTIM0_NAND_TWCHT(0x07) | \
 335                                         FTIM0_NAND_TWH(0x0a))
 336 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 337                                         FTIM1_NAND_TWBE(0x39)  | \
 338                                         FTIM1_NAND_TRR(0x0e)   | \
 339                                         FTIM1_NAND_TRP(0x18))
 340 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 341                                         FTIM2_NAND_TREH(0x0a) | \
 342                                         FTIM2_NAND_TWHRE(0x1e))
 343 #define CONFIG_SYS_NAND_FTIM3           0x0
 344
 345 #define CONFIG_SYS_NAND_DDR_LAW         11
 346
 347 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 348 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 349
 350 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 351
 352 #if defined(CONFIG_NAND)
 353 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 354 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 355 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 356 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 357 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 358 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 359 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 360 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 361 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 362 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR0_CSPR
 363 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 364 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 365 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 366 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 367 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 368 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 369 #else
 370 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 371 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 372 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 373 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 374 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 375 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 376 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 377 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 378 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 379 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 380 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 381 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 382 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 383 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 384 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 385 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 386 #endif
 387 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 388 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 389 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 390 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 391 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 392 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 393 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 394 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 395
 396 #ifdef CONFIG_SPL_BUILD
 397 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
 398 #else
 399 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 400 #endif
 401
 402 #if defined(CONFIG_RAMBOOT_PBL)
 403 #define CONFIG_SYS_RAMBOOT
 404 #endif
 405
 406 #define CONFIG_MISC_INIT_R
 407
 408 #define CONFIG_HWCONFIG
 409
 410 /* define to use L1 as initial stack */
 411 #define CONFIG_L1_INIT_RAM
 412 #define CONFIG_SYS_INIT_RAM_LOCK
 413 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
 414 #ifdef CONFIG_PHYS_64BIT
 415 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 416 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 417 /* The assembler doesn't like typecast */
 418 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 419         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 420           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 421 #else
 422 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   0xfe03c000 /* Initial L1 address */
 423 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 424 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 425 #endif
 426 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
 427
 428 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 429                                         GENERATED_GBL_DATA_SIZE)
 430 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 431
 432 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 433 #define CONFIG_SYS_MALLOC_LEN           (4 * 1024 * 1024)
 434
 435 /* Serial Port - controlled on board with jumper J8
 436  * open - index 2
 437  * shorted - index 1
 438  */
 439 #define CONFIG_SYS_NS16550_SERIAL
 440 #define CONFIG_SYS_NS16550_REG_SIZE     1
 441 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 442
 443 #define CONFIG_SYS_BAUDRATE_TABLE       \
 444         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 445
 446 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 447 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 448 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 449 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 450
 451 /* I2C */
 452 #define CONFIG_SYS_I2C
 453 #define CONFIG_SYS_I2C_FSL              /* Use FSL common I2C driver */
 454 #define CONFIG_SYS_FSL_I2C_SPEED        400000  /* I2C speed in Hz */
 455 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 456 #define CONFIG_SYS_FSL_I2C2_SPEED       400000  /* I2C speed in Hz */
 457 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 458 #define CONFIG_SYS_FSL_I2C_OFFSET       0x118000
 459 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x119000
 460
 461 /*
 462  * RTC configuration
 463  */
 464 #define RTC
 465 #define CONFIG_RTC_DS3231               1
 466 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
 467
 468 /*
 469  * RapidIO
 470  */
 471 #ifdef CONFIG_SYS_SRIO
 472 #ifdef CONFIG_SRIO1
 473 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
 474 #ifdef CONFIG_PHYS_64BIT
 475 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
 476 #else
 477 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xa0000000
 478 #endif
 479 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000      /* 256M */
 480 #endif
 481
 482 #ifdef CONFIG_SRIO2
 483 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
 484 #ifdef CONFIG_PHYS_64BIT
 485 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
 486 #else
 487 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xb0000000
 488 #endif
 489 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000      /* 256M */
 490 #endif
 491 #endif
 492
 493 /*
 494  * for slave u-boot IMAGE instored in master memory space,
 495  * PHYS must be aligned based on the SIZE
 496  */
 497 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 498 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 499 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000       /* 1M */
 500 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 501 /*
 502  * for slave UCODE and ENV instored in master memory space,
 503  * PHYS must be aligned based on the SIZE
 504  */
 505 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 506 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
 507 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000    /* 256K */
 508
 509 /* slave core release by master*/
 510 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 511 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 512
 513 /*
 514  * SRIO_PCIE_BOOT - SLAVE
 515  */
 516 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 517 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 518 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 519                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 520 #endif
 521
 522 /*
 523  * eSPI - Enhanced SPI
 524  */
 525 #define CONFIG_SF_DEFAULT_SPEED         10000000
 526 #define CONFIG_SF_DEFAULT_MODE          0
 527
 528 /*
 529  * MAPLE
 530  */
 531 #ifdef CONFIG_PHYS_64BIT
 532 #define CONFIG_SYS_MAPLE_MEM_PHYS      0xFA0000000ull
 533 #else
 534 #define CONFIG_SYS_MAPLE_MEM_PHYS      0xA0000000
 535 #endif
 536
 537 /*
 538  * General PCI
 539  * Memory space is mapped 1-1, but I/O space must start from 0.
 540  */
 541
 542 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 543 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 544 #ifdef CONFIG_PHYS_64BIT
 545 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 546 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 547 #else
 548 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
 549 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x80000000
 550 #endif
 551 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 552 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 553 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 554 #ifdef CONFIG_PHYS_64BIT
 555 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 556 #else
 557 #define CONFIG_SYS_PCIE1_IO_PHYS        0xf8000000
 558 #endif
 559 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 560
 561 /* Qman/Bman */
 562 #ifndef CONFIG_NOBQFMAN
 563 #define CONFIG_SYS_BMAN_NUM_PORTALS     25
 564 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 565 #ifdef CONFIG_PHYS_64BIT
 566 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 567 #else
 568 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
 569 #endif
 570 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 571 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 572 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 573 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 574 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 575 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 576                                         CONFIG_SYS_BMAN_CENA_SIZE)
 577 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 578 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 579 #define CONFIG_SYS_QMAN_NUM_PORTALS     25
 580 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 581 #ifdef CONFIG_PHYS_64BIT
 582 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 583 #else
 584 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
 585 #endif
 586 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 587 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 588 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 589 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 590 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 591 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 592                                         CONFIG_SYS_QMAN_CENA_SIZE)
 593 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 594 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 595
 596 #define CONFIG_SYS_DPAA_FMAN
 597
 598 #define CONFIG_SYS_DPAA_RMAN
 599
 600 /* Default address of microcode for the Linux Fman driver */
 601 #if defined(CONFIG_SPIFLASH)
 602 /*
 603  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 604  * env, so we got 0x110000.
 605  */
 606 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
 607 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
 608 #elif defined(CONFIG_SDCARD)
 609 /*
 610  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 611  * about 545KB (1089 blocks), Env is stored after the image, and the env size is
 612  * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130.
 613  */
 614 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 615 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1130)
 616 #elif defined(CONFIG_NAND)
 617 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 618 #define CONFIG_SYS_FMAN_FW_ADDR (13 * CONFIG_SYS_NAND_BLOCK_SIZE)
 619 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 620 /*
 621  * Slave has no ucode locally, it can fetch this from remote. When implementing
 622  * in two corenet boards, slave's ucode could be stored in master's memory
 623  * space, the address can be mapped from slave TLB->slave LAW->
 624  * slave SRIO or PCIE outbound window->master inbound window->
 625  * master LAW->the ucode address in master's memory space.
 626  */
 627 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
 628 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
 629 #else
 630 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 631 #define CONFIG_SYS_FMAN_FW_ADDR         0xEFF00000
 632 #endif
 633 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 634 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 635 #endif /* CONFIG_NOBQFMAN */
 636
 637 #ifdef CONFIG_SYS_DPAA_FMAN
 638 #define CONFIG_FMAN_ENET
 639 #define CONFIG_PHYLIB_10G
 640 #define CONFIG_PHY_VITESSE
 641 #define CONFIG_PHY_TERANETICS
 642 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
 643 #define SGMII_CARD_PORT2_PHY_ADDR 0x10
 644 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
 645 #define SGMII_CARD_PORT4_PHY_ADDR 0x11
 646 #endif
 647
 648 #ifdef CONFIG_PCI
 649 #define CONFIG_PCI_INDIRECT_BRIDGE
 650
 651 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 652 #endif  /* CONFIG_PCI */
 653
 654 #ifdef CONFIG_FMAN_ENET
 655 #define CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR 0x10
 656 #define CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR 0x11
 657
 658 /*B4860 QDS AMC2PEX-2S default PHY_ADDR */
 659 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0x7       /*SLOT 1*/
 660 #define CONFIG_SYS_FM1_10GEC2_PHY_ADDR 0x6       /*SLOT 2*/
 661
 662 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR    0x1c
 663 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR    0x1d
 664 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR    0x1e
 665 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR    0x1f
 666
 667 #define CONFIG_MII              /* MII PHY management */
 668 #define CONFIG_ETHPRIME         "FM1@DTSEC1"
 669 #endif
 670
 671 #define CONFIG_SYS_FSL_B4860QDS_XFI_ERR
 672
 673 /*
 674  * Environment
 675  */
 676 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 677 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 678
 679 /*
 680 * USB
 681 */
 682 #define CONFIG_HAS_FSL_DR_USB
 683
 684 #ifdef CONFIG_HAS_FSL_DR_USB
 685 #ifdef CONFIG_USB_EHCI_HCD
 686 #define CONFIG_USB_EHCI_FSL
 687 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 688 #endif
 689 #endif
 690
 691 /*
 692  * Miscellaneous configurable options
 693  */
 694 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 695
 696 /*
 697  * For booting Linux, the board info and command line data
 698  * have to be in the first 64 MB of memory, since this is
 699  * the maximum mapped by the Linux kernel during initialization.
 700  */
 701 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 702 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 703
 704 #ifdef CONFIG_CMD_KGDB
 705 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 706 #endif
 707
 708 /*
 709  * Environment Configuration
 710  */
 711 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 712 #define CONFIG_BOOTFILE         "uImage"
 713 #define CONFIG_UBOOTPATH        "u-boot.bin"    /* U-Boot image on TFTP server*/
 714
 715 /* default location for tftp and bootm */
 716 #define CONFIG_LOADADDR         1000000
 717
 718 #define __USB_PHY_TYPE  ulpi
 719
 720 #ifdef CONFIG_ARCH_B4860
 721 #define HWCONFIG        "hwconfig=fsl_ddr:ctlr_intlv=null,"     \
 722                         "bank_intlv=cs0_cs1;"   \
 723                         "en_cpc:cpc2;"
 724 #else
 725 #define HWCONFIG        "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=cs0_cs1;"
 726 #endif
 727
 728 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 729         HWCONFIG                                                \
 730         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 731         "netdev=eth0\0"                                         \
 732         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"                     \
 733         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"                     \
 734         "tftpflash=tftpboot $loadaddr $uboot && "               \
 735         "protect off $ubootaddr +$filesize && "                 \
 736         "erase $ubootaddr +$filesize && "                       \
 737         "cp.b $loadaddr $ubootaddr $filesize && "               \
 738         "protect on $ubootaddr +$filesize && "                  \
 739         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 740         "consoledev=ttyS0\0"                                    \
 741         "ramdiskaddr=2000000\0"                                 \
 742         "ramdiskfile=b4860qds/ramdisk.uboot\0"                  \
 743         "fdtaddr=1e00000\0"                                     \
 744         "fdtfile=b4860qds/b4860qds.dtb\0"                               \
 745         "bdev=sda3\0"
 746
 747 /* For emulation this causes u-boot to jump to the start of the proof point
 748    app code automatically */
 749 #define CONFIG_PROOF_POINTS                     \
 750  "setenv bootargs root=/dev/$bdev rw "          \
 751  "console=$consoledev,$baudrate $othbootargs;"  \
 752  "cpu 1 release 0x29000000 - - -;"              \
 753  "cpu 2 release 0x29000000 - - -;"              \
 754  "cpu 3 release 0x29000000 - - -;"              \
 755  "cpu 4 release 0x29000000 - - -;"              \
 756  "cpu 5 release 0x29000000 - - -;"              \
 757  "cpu 6 release 0x29000000 - - -;"              \
 758  "cpu 7 release 0x29000000 - - -;"              \
 759  "go 0x29000000"
 760
 761 #define CONFIG_HVBOOT   \
 762  "setenv bootargs config-addr=0x60000000; "     \
 763  "bootm 0x01000000 - 0x00f00000"
 764
 765 #define CONFIG_ALU                              \
 766  "setenv bootargs root=/dev/$bdev rw "          \
 767  "console=$consoledev,$baudrate $othbootargs;"  \
 768  "cpu 1 release 0x01000000 - - -;"              \
 769  "cpu 2 release 0x01000000 - - -;"              \
 770  "cpu 3 release 0x01000000 - - -;"              \
 771  "cpu 4 release 0x01000000 - - -;"              \
 772  "cpu 5 release 0x01000000 - - -;"              \
 773  "cpu 6 release 0x01000000 - - -;"              \
 774  "cpu 7 release 0x01000000 - - -;"              \
 775  "go 0x01000000"
 776
 777 #define CONFIG_LINUX                            \
 778  "setenv bootargs root=/dev/ram rw "            \
 779  "console=$consoledev,$baudrate $othbootargs;"  \
 780  "setenv ramdiskaddr 0x02000000;"               \
 781  "setenv fdtaddr 0x01e00000;"                   \
 782  "setenv loadaddr 0x1000000;"                   \
 783  "bootm $loadaddr $ramdiskaddr $fdtaddr"
 784
 785 #define CONFIG_HDBOOT                                   \
 786         "setenv bootargs root=/dev/$bdev rw "           \
 787         "console=$consoledev,$baudrate $othbootargs;"   \
 788         "tftp $loadaddr $bootfile;"                     \
 789         "tftp $fdtaddr $fdtfile;"                       \
 790         "bootm $loadaddr - $fdtaddr"
 791
 792 #define CONFIG_NFSBOOTCOMMAND                   \
 793         "setenv bootargs root=/dev/nfs rw "     \
 794         "nfsroot=$serverip:$rootpath "          \
 795         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 796         "console=$consoledev,$baudrate $othbootargs;"   \
 797         "tftp $loadaddr $bootfile;"             \
 798         "tftp $fdtaddr $fdtfile;"               \
 799         "bootm $loadaddr - $fdtaddr"
 800
 801 #define CONFIG_RAMBOOTCOMMAND                           \
 802         "setenv bootargs root=/dev/ram rw "             \
 803         "console=$consoledev,$baudrate $othbootargs;"   \
 804         "tftp $ramdiskaddr $ramdiskfile;"               \
 805         "tftp $loadaddr $bootfile;"                     \
 806         "tftp $fdtaddr $fdtfile;"                       \
 807         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 808
 809 #define CONFIG_BOOTCOMMAND              CONFIG_LINUX
 810
 811 #include <asm/fsl_secure_boot.h>
 812
 813 #endif  /* __CONFIG_H */