include/configs/B4860QDS.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2011-2012 Freescale Semiconductor, Inc.
   4  */
   5
   6 #ifndef __CONFIG_H
   7 #define __CONFIG_H
   8
   9 /*
  10  * B4860 QDS board configuration file
  11  */
  12 #ifdef CONFIG_RAMBOOT_PBL
  13 #define CONFIG_SYS_FSL_PBL_PBI  $(SRCTREE)/board/freescale/b4860qds/b4_pbi.cfg
  14 #define CONFIG_SYS_FSL_PBL_RCW  $(SRCTREE)/board/freescale/b4860qds/b4_rcw.cfg
  15 #ifndef CONFIG_NAND
  16 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
  17 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
  18 #else
  19 #define CONFIG_SPL_FLUSH_IMAGE
  20 #define CONFIG_SPL_PAD_TO               0x40000
  21 #define CONFIG_SPL_MAX_SIZE             0x28000
  22 #define RESET_VECTOR_OFFSET             0x27FFC
  23 #define BOOT_PAGE_OFFSET                0x27000
  24 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
  25 #define CONFIG_SYS_NAND_U_BOOT_DST      0x00200000
  26 #define CONFIG_SYS_NAND_U_BOOT_START    0x00200000
  27 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (256 << 10)
  28 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
  29 #ifdef CONFIG_SPL_BUILD
  30 #define CONFIG_SPL_SKIP_RELOCATE
  31 #define CONFIG_SPL_COMMON_INIT_DDR
  32 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  33 #endif
  34 #endif
  35 #endif
  36
  37 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  38 /* Set 1M boot space */
  39 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  40 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  41                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  42 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  43 #endif
  44
  45 /* High Level Configuration Options */
  46 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  47
  48 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  49 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  50 #endif
  51
  52 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  53 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
  54 #define CONFIG_PCIE1                    /* PCIE controller 1 */
  55 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
  56 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
  57
  58 #ifndef CONFIG_ARCH_B4420
  59 #define CONFIG_SYS_SRIO
  60 #define CONFIG_SRIO1                    /* SRIO port 1 */
  61 #define CONFIG_SRIO2                    /* SRIO port 2 */
  62 #define CONFIG_SRIO_PCIE_BOOT_MASTER
  63 #endif
  64
  65 /* I2C bus multiplexer */
  66 #define I2C_MUX_PCA_ADDR                0x77
  67
  68 /* VSC Crossbar switches */
  69 #define CONFIG_VSC_CROSSBAR
  70 #define I2C_CH_DEFAULT                  0x8
  71 #define I2C_CH_VSC3316                  0xc
  72 #define I2C_CH_VSC3308                  0xd
  73
  74 #define VSC3316_TX_ADDRESS              0x70
  75 #define VSC3316_RX_ADDRESS              0x71
  76 #define VSC3308_TX_ADDRESS              0x02
  77 #define VSC3308_RX_ADDRESS              0x03
  78
  79 /* IDT clock synthesizers */
  80 #define CONFIG_IDT8T49N222A
  81 #define I2C_CH_IDT                     0x9
  82
  83 #define IDT_SERDES1_ADDRESS            0x6E
  84 #define IDT_SERDES2_ADDRESS            0x6C
  85
  86 /* Voltage monitor on channel 2*/
  87 #define I2C_MUX_CH_VOL_MONITOR          0xa
  88 #define I2C_VOL_MONITOR_ADDR            0x40
  89 #define I2C_VOL_MONITOR_BUS_V_OFFSET    0x2
  90 #define I2C_VOL_MONITOR_BUS_V_OVF       0x1
  91 #define I2C_VOL_MONITOR_BUS_V_SHIFT     3
  92
  93 #define CONFIG_ZM7300
  94 #define I2C_MUX_CH_DPM                  0xa
  95 #define I2C_DPM_ADDR                    0x28
  96
  97 #define CONFIG_ENV_OVERWRITE
  98
  99 #if defined(CONFIG_SPIFLASH)
 100 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
 101 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
 102 #define CONFIG_ENV_SECT_SIZE            0x10000
 103 #elif defined(CONFIG_SDCARD)
 104 #define CONFIG_SYS_MMC_ENV_DEV          0
 105 #define CONFIG_ENV_SIZE                 0x2000
 106 #define CONFIG_ENV_OFFSET               (512 * 1097)
 107 #elif defined(CONFIG_NAND)
 108 #define CONFIG_ENV_SIZE                 0x2000
 109 #define CONFIG_ENV_OFFSET               (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
 110 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 111 #define CONFIG_ENV_ADDR         0xffe20000
 112 #define CONFIG_ENV_SIZE         0x2000
 113 #elif defined(CONFIG_ENV_IS_NOWHERE)
 114 #define CONFIG_ENV_SIZE         0x2000
 115 #else
 116 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 117 #define CONFIG_ENV_SIZE         0x2000
 118 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 119 #endif
 120
 121 #ifndef __ASSEMBLY__
 122 unsigned long get_board_sys_clk(void);
 123 unsigned long get_board_ddr_clk(void);
 124 #endif
 125 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk() /* sysclk for MPC85xx */
 126 #define CONFIG_DDR_CLK_FREQ     get_board_ddr_clk()
 127
 128 /*
 129  * These can be toggled for performance analysis, otherwise use default.
 130  */
 131 #define CONFIG_SYS_CACHE_STASHING
 132 #define CONFIG_BTB                      /* toggle branch predition */
 133 #define CONFIG_DDR_ECC
 134 #ifdef CONFIG_DDR_ECC
 135 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 136 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 137 #endif
 138
 139 #define CONFIG_ENABLE_36BIT_PHYS
 140
 141 #ifdef CONFIG_PHYS_64BIT
 142 #define CONFIG_ADDR_MAP
 143 #define CONFIG_SYS_NUM_ADDR_MAP         64      /* number of TLB1 entries */
 144 #endif
 145
 146 #if 0
 147 #define CONFIG_POST CONFIG_SYS_POST_MEMORY      /* test POST memory test */
 148 #endif
 149 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
 150 #define CONFIG_SYS_MEMTEST_END          0x00400000
 151
 152 /*
 153  *  Config the L3 Cache as L3 SRAM
 154  */
 155 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
 156 #define CONFIG_SYS_L3_SIZE              256 << 10
 157 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
 158 #ifdef CONFIG_NAND
 159 #define CONFIG_ENV_ADDR                 (CONFIG_SPL_GD_ADDR + 4 * 1024)
 160 #endif
 161 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
 162 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (30 << 10)
 163 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
 164
 165 #ifdef CONFIG_PHYS_64BIT
 166 #define CONFIG_SYS_DCSRBAR              0xf0000000
 167 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
 168 #endif
 169
 170 /* EEPROM */
 171 #define CONFIG_ID_EEPROM
 172 #define CONFIG_SYS_I2C_EEPROM_NXID
 173 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 174 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 175 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 176 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 177 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
 178
 179 /*
 180  * DDR Setup
 181  */
 182 #define CONFIG_VERY_BIG_RAM
 183 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 184 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 185
 186 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 187 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
 188
 189 #define CONFIG_DDR_SPD
 190 #define CONFIG_SYS_DDR_RAW_TIMING
 191
 192 #define CONFIG_SYS_SPD_BUS_NUM  0
 193 #define SPD_EEPROM_ADDRESS1     0x51
 194 #define SPD_EEPROM_ADDRESS2     0x53
 195
 196 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1
 197 #define CONFIG_SYS_SDRAM_SIZE   2048    /* for fixed parameter use */
 198
 199 /*
 200  * IFC Definitions
 201  */
 202 #define CONFIG_SYS_FLASH_BASE   0xe0000000
 203 #ifdef CONFIG_PHYS_64BIT
 204 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 205 #else
 206 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 207 #endif
 208
 209 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 210 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
 211                                 + 0x8000000) | \
 212                                 CSPR_PORT_SIZE_16 | \
 213                                 CSPR_MSEL_NOR | \
 214                                 CSPR_V)
 215 #define CONFIG_SYS_NOR1_CSPR_EXT        (0xf)
 216 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 217                                 CSPR_PORT_SIZE_16 | \
 218                                 CSPR_MSEL_NOR | \
 219                                 CSPR_V)
 220 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128 * 1024 * 1024)
 221 /* NOR Flash Timing Params */
 222 #define CONFIG_SYS_NOR_CSOR     CSOR_NOR_ADM_SHIFT(4)
 223 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x01) | \
 224                                 FTIM0_NOR_TEADC(0x04) | \
 225                                 FTIM0_NOR_TEAHC(0x20))
 226 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 227                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 228                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 229 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x01) | \
 230                                 FTIM2_NOR_TCH(0x0E) | \
 231                                 FTIM2_NOR_TWPH(0x0E) | \
 232                                 FTIM2_NOR_TWP(0x1c))
 233 #define CONFIG_SYS_NOR_FTIM3    0x0
 234
 235 #define CONFIG_SYS_FLASH_QUIET_TEST
 236 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 237
 238 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 239 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 240 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 241 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 242
 243 #define CONFIG_SYS_FLASH_EMPTY_INFO
 244 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS \
 245                                         + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 246
 247 #define CONFIG_FSL_QIXIS        /* use common QIXIS code */
 248 #define CONFIG_FSL_QIXIS_V2
 249 #define QIXIS_BASE              0xffdf0000
 250 #ifdef CONFIG_PHYS_64BIT
 251 #define QIXIS_BASE_PHYS         (0xf00000000ull | QIXIS_BASE)
 252 #else
 253 #define QIXIS_BASE_PHYS         QIXIS_BASE
 254 #endif
 255 #define QIXIS_LBMAP_SWITCH              0x01
 256 #define QIXIS_LBMAP_MASK                0x0f
 257 #define QIXIS_LBMAP_SHIFT               0
 258 #define QIXIS_LBMAP_DFLTBANK            0x00
 259 #define QIXIS_LBMAP_ALTBANK             0x02
 260 #define QIXIS_RST_CTL_RESET             0x31
 261 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 262 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 263 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 264
 265 #define CONFIG_SYS_CSPR3_EXT    (0xf)
 266 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 267                                 | CSPR_PORT_SIZE_8 \
 268                                 | CSPR_MSEL_GPCM \
 269                                 | CSPR_V)
 270 #define CONFIG_SYS_AMASK3       IFC_AMASK(64 * 1024)
 271 #define CONFIG_SYS_CSOR3        0x0
 272 /* QIXIS Timing parameters for IFC CS3 */
 273 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 274                                         FTIM0_GPCM_TEADC(0x0e) | \
 275                                         FTIM0_GPCM_TEAHC(0x0e))
 276 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
 277                                         FTIM1_GPCM_TRAD(0x1f))
 278 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 279                                         FTIM2_GPCM_TCH(0x8) | \
 280                                         FTIM2_GPCM_TWP(0x1f))
 281 #define CONFIG_SYS_CS3_FTIM3            0x0
 282
 283 /* NAND Flash on IFC */
 284 #define CONFIG_NAND_FSL_IFC
 285 #define CONFIG_SYS_NAND_MAX_ECCPOS      256
 286 #define CONFIG_SYS_NAND_MAX_OOBFREE     2
 287 #define CONFIG_SYS_NAND_BASE            0xff800000
 288 #ifdef CONFIG_PHYS_64BIT
 289 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 290 #else
 291 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 292 #endif
 293
 294 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 295 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 296                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 297                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 298                                 | CSPR_V)
 299 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64 * 1024)
 300
 301 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 302                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 303                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 304                                 | CSOR_NAND_RAL_3       /* RAL = 2Byes */ \
 305                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 306                                 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
 307                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 308
 309 #define CONFIG_SYS_NAND_ONFI_DETECTION
 310
 311 /* ONFI NAND Flash mode0 Timing Params */
 312 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 313                                         FTIM0_NAND_TWP(0x18)   | \
 314                                         FTIM0_NAND_TWCHT(0x07) | \
 315                                         FTIM0_NAND_TWH(0x0a))
 316 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 317                                         FTIM1_NAND_TWBE(0x39)  | \
 318                                         FTIM1_NAND_TRR(0x0e)   | \
 319                                         FTIM1_NAND_TRP(0x18))
 320 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 321                                         FTIM2_NAND_TREH(0x0a) | \
 322                                         FTIM2_NAND_TWHRE(0x1e))
 323 #define CONFIG_SYS_NAND_FTIM3           0x0
 324
 325 #define CONFIG_SYS_NAND_DDR_LAW         11
 326
 327 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 328 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 329
 330 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 331
 332 #if defined(CONFIG_NAND)
 333 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 334 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 335 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 336 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 337 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 338 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 339 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 340 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 341 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 342 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR0_CSPR
 343 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 344 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 345 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 346 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 347 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 348 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 349 #else
 350 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 351 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 352 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 353 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 354 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 355 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 356 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 357 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 358 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 359 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 360 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 361 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 362 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 363 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 364 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 365 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 366 #endif
 367 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 368 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 369 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 370 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 371 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 372 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 373 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 374 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 375
 376 #ifdef CONFIG_SPL_BUILD
 377 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
 378 #else
 379 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 380 #endif
 381
 382 #if defined(CONFIG_RAMBOOT_PBL)
 383 #define CONFIG_SYS_RAMBOOT
 384 #endif
 385
 386 #define CONFIG_HWCONFIG
 387
 388 /* define to use L1 as initial stack */
 389 #define CONFIG_L1_INIT_RAM
 390 #define CONFIG_SYS_INIT_RAM_LOCK
 391 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
 392 #ifdef CONFIG_PHYS_64BIT
 393 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 394 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 395 /* The assembler doesn't like typecast */
 396 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 397         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 398           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 399 #else
 400 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   0xfe03c000 /* Initial L1 address */
 401 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 402 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 403 #endif
 404 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
 405
 406 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 407                                         GENERATED_GBL_DATA_SIZE)
 408 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 409
 410 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 411 #define CONFIG_SYS_MALLOC_LEN           (4 * 1024 * 1024)
 412
 413 /* Serial Port - controlled on board with jumper J8
 414  * open - index 2
 415  * shorted - index 1
 416  */
 417 #define CONFIG_SYS_NS16550_SERIAL
 418 #define CONFIG_SYS_NS16550_REG_SIZE     1
 419 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 420
 421 #define CONFIG_SYS_BAUDRATE_TABLE       \
 422         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 423
 424 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 425 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 426 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 427 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 428
 429 /* I2C */
 430 #define CONFIG_SYS_I2C
 431 #define CONFIG_SYS_I2C_FSL              /* Use FSL common I2C driver */
 432 #define CONFIG_SYS_FSL_I2C_SPEED        400000  /* I2C speed in Hz */
 433 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 434 #define CONFIG_SYS_FSL_I2C2_SPEED       400000  /* I2C speed in Hz */
 435 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 436 #define CONFIG_SYS_FSL_I2C_OFFSET       0x118000
 437 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x119000
 438
 439 /*
 440  * RTC configuration
 441  */
 442 #define RTC
 443 #define CONFIG_RTC_DS3231               1
 444 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
 445
 446 /*
 447  * RapidIO
 448  */
 449 #ifdef CONFIG_SYS_SRIO
 450 #ifdef CONFIG_SRIO1
 451 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
 452 #ifdef CONFIG_PHYS_64BIT
 453 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
 454 #else
 455 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xa0000000
 456 #endif
 457 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000      /* 256M */
 458 #endif
 459
 460 #ifdef CONFIG_SRIO2
 461 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
 462 #ifdef CONFIG_PHYS_64BIT
 463 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
 464 #else
 465 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xb0000000
 466 #endif
 467 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000      /* 256M */
 468 #endif
 469 #endif
 470
 471 /*
 472  * for slave u-boot IMAGE instored in master memory space,
 473  * PHYS must be aligned based on the SIZE
 474  */
 475 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 476 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 477 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000       /* 1M */
 478 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 479 /*
 480  * for slave UCODE and ENV instored in master memory space,
 481  * PHYS must be aligned based on the SIZE
 482  */
 483 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 484 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
 485 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000    /* 256K */
 486
 487 /* slave core release by master*/
 488 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 489 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 490
 491 /*
 492  * SRIO_PCIE_BOOT - SLAVE
 493  */
 494 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 495 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 496 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 497                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 498 #endif
 499
 500 /*
 501  * eSPI - Enhanced SPI
 502  */
 503
 504 /*
 505  * MAPLE
 506  */
 507 #ifdef CONFIG_PHYS_64BIT
 508 #define CONFIG_SYS_MAPLE_MEM_PHYS      0xFA0000000ull
 509 #else
 510 #define CONFIG_SYS_MAPLE_MEM_PHYS      0xA0000000
 511 #endif
 512
 513 /*
 514  * General PCI
 515  * Memory space is mapped 1-1, but I/O space must start from 0.
 516  */
 517
 518 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 519 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 520 #ifdef CONFIG_PHYS_64BIT
 521 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 522 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 523 #else
 524 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
 525 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x80000000
 526 #endif
 527 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 528 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 529 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 530 #ifdef CONFIG_PHYS_64BIT
 531 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 532 #else
 533 #define CONFIG_SYS_PCIE1_IO_PHYS        0xf8000000
 534 #endif
 535 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 536
 537 /* Qman/Bman */
 538 #ifndef CONFIG_NOBQFMAN
 539 #define CONFIG_SYS_BMAN_NUM_PORTALS     25
 540 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 541 #ifdef CONFIG_PHYS_64BIT
 542 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 543 #else
 544 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
 545 #endif
 546 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 547 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 548 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 549 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 550 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 551 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 552                                         CONFIG_SYS_BMAN_CENA_SIZE)
 553 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 554 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 555 #define CONFIG_SYS_QMAN_NUM_PORTALS     25
 556 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 557 #ifdef CONFIG_PHYS_64BIT
 558 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 559 #else
 560 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
 561 #endif
 562 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 563 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 564 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 565 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 566 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 567 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 568                                         CONFIG_SYS_QMAN_CENA_SIZE)
 569 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 570 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 571
 572 #define CONFIG_SYS_DPAA_FMAN
 573
 574 #define CONFIG_SYS_DPAA_RMAN
 575
 576 /* Default address of microcode for the Linux Fman driver */
 577 #if defined(CONFIG_SPIFLASH)
 578 /*
 579  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 580  * env, so we got 0x110000.
 581  */
 582 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
 583 #elif defined(CONFIG_SDCARD)
 584 /*
 585  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 586  * about 545KB (1089 blocks), Env is stored after the image, and the env size is
 587  * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130.
 588  */
 589 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1130)
 590 #elif defined(CONFIG_NAND)
 591 #define CONFIG_SYS_FMAN_FW_ADDR (13 * CONFIG_SYS_NAND_BLOCK_SIZE)
 592 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 593 /*
 594  * Slave has no ucode locally, it can fetch this from remote. When implementing
 595  * in two corenet boards, slave's ucode could be stored in master's memory
 596  * space, the address can be mapped from slave TLB->slave LAW->
 597  * slave SRIO or PCIE outbound window->master inbound window->
 598  * master LAW->the ucode address in master's memory space.
 599  */
 600 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
 601 #else
 602 #define CONFIG_SYS_FMAN_FW_ADDR         0xEFF00000
 603 #endif
 604 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 605 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 606 #endif /* CONFIG_NOBQFMAN */
 607
 608 #ifdef CONFIG_SYS_DPAA_FMAN
 609 #define CONFIG_PHYLIB_10G
 610 #define CONFIG_PHY_VITESSE
 611 #define CONFIG_PHY_TERANETICS
 612 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
 613 #define SGMII_CARD_PORT2_PHY_ADDR 0x10
 614 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
 615 #define SGMII_CARD_PORT4_PHY_ADDR 0x11
 616 #endif
 617
 618 #ifdef CONFIG_PCI
 619 #define CONFIG_PCI_INDIRECT_BRIDGE
 620
 621 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 622 #endif  /* CONFIG_PCI */
 623
 624 #ifdef CONFIG_FMAN_ENET
 625 #define CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR 0x10
 626 #define CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR 0x11
 627
 628 /*B4860 QDS AMC2PEX-2S default PHY_ADDR */
 629 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0x7       /*SLOT 1*/
 630 #define CONFIG_SYS_FM1_10GEC2_PHY_ADDR 0x6       /*SLOT 2*/
 631
 632 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR    0x1c
 633 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR    0x1d
 634 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR    0x1e
 635 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR    0x1f
 636
 637 #define CONFIG_ETHPRIME         "FM1@DTSEC1"
 638 #endif
 639
 640 #define CONFIG_SYS_FSL_B4860QDS_XFI_ERR
 641
 642 /*
 643  * Environment
 644  */
 645 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 646 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 647
 648 /*
 649 * USB
 650 */
 651 #define CONFIG_HAS_FSL_DR_USB
 652
 653 #ifdef CONFIG_HAS_FSL_DR_USB
 654 #ifdef CONFIG_USB_EHCI_HCD
 655 #define CONFIG_USB_EHCI_FSL
 656 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 657 #endif
 658 #endif
 659
 660 /*
 661  * Miscellaneous configurable options
 662  */
 663 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 664
 665 /*
 666  * For booting Linux, the board info and command line data
 667  * have to be in the first 64 MB of memory, since this is
 668  * the maximum mapped by the Linux kernel during initialization.
 669  */
 670 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 671 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 672
 673 #ifdef CONFIG_CMD_KGDB
 674 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 675 #endif
 676
 677 /*
 678  * Environment Configuration
 679  */
 680 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 681 #define CONFIG_BOOTFILE         "uImage"
 682 #define CONFIG_UBOOTPATH        "u-boot.bin"    /* U-Boot image on TFTP server*/
 683
 684 /* default location for tftp and bootm */
 685 #define CONFIG_LOADADDR         1000000
 686
 687 #define __USB_PHY_TYPE  ulpi
 688
 689 #ifdef CONFIG_ARCH_B4860
 690 #define HWCONFIG        "hwconfig=fsl_ddr:ctlr_intlv=null,"     \
 691                         "bank_intlv=cs0_cs1;"   \
 692                         "en_cpc:cpc2;"
 693 #else
 694 #define HWCONFIG        "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=cs0_cs1;"
 695 #endif
 696
 697 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 698         HWCONFIG                                                \
 699         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 700         "netdev=eth0\0"                                         \
 701         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"                     \
 702         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"                     \
 703         "tftpflash=tftpboot $loadaddr $uboot && "               \
 704         "protect off $ubootaddr +$filesize && "                 \
 705         "erase $ubootaddr +$filesize && "                       \
 706         "cp.b $loadaddr $ubootaddr $filesize && "               \
 707         "protect on $ubootaddr +$filesize && "                  \
 708         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 709         "consoledev=ttyS0\0"                                    \
 710         "ramdiskaddr=2000000\0"                                 \
 711         "ramdiskfile=b4860qds/ramdisk.uboot\0"                  \
 712         "fdtaddr=1e00000\0"                                     \
 713         "fdtfile=b4860qds/b4860qds.dtb\0"                               \
 714         "bdev=sda3\0"
 715
 716 /* For emulation this causes u-boot to jump to the start of the proof point
 717    app code automatically */
 718 #define CONFIG_PROOF_POINTS                     \
 719  "setenv bootargs root=/dev/$bdev rw "          \
 720  "console=$consoledev,$baudrate $othbootargs;"  \
 721  "cpu 1 release 0x29000000 - - -;"              \
 722  "cpu 2 release 0x29000000 - - -;"              \
 723  "cpu 3 release 0x29000000 - - -;"              \
 724  "cpu 4 release 0x29000000 - - -;"              \
 725  "cpu 5 release 0x29000000 - - -;"              \
 726  "cpu 6 release 0x29000000 - - -;"              \
 727  "cpu 7 release 0x29000000 - - -;"              \
 728  "go 0x29000000"
 729
 730 #define CONFIG_HVBOOT   \
 731  "setenv bootargs config-addr=0x60000000; "     \
 732  "bootm 0x01000000 - 0x00f00000"
 733
 734 #define CONFIG_ALU                              \
 735  "setenv bootargs root=/dev/$bdev rw "          \
 736  "console=$consoledev,$baudrate $othbootargs;"  \
 737  "cpu 1 release 0x01000000 - - -;"              \
 738  "cpu 2 release 0x01000000 - - -;"              \
 739  "cpu 3 release 0x01000000 - - -;"              \
 740  "cpu 4 release 0x01000000 - - -;"              \
 741  "cpu 5 release 0x01000000 - - -;"              \
 742  "cpu 6 release 0x01000000 - - -;"              \
 743  "cpu 7 release 0x01000000 - - -;"              \
 744  "go 0x01000000"
 745
 746 #define CONFIG_LINUX                            \
 747  "setenv bootargs root=/dev/ram rw "            \
 748  "console=$consoledev,$baudrate $othbootargs;"  \
 749  "setenv ramdiskaddr 0x02000000;"               \
 750  "setenv fdtaddr 0x01e00000;"                   \
 751  "setenv loadaddr 0x1000000;"                   \
 752  "bootm $loadaddr $ramdiskaddr $fdtaddr"
 753
 754 #define CONFIG_HDBOOT                                   \
 755         "setenv bootargs root=/dev/$bdev rw "           \
 756         "console=$consoledev,$baudrate $othbootargs;"   \
 757         "tftp $loadaddr $bootfile;"                     \
 758         "tftp $fdtaddr $fdtfile;"                       \
 759         "bootm $loadaddr - $fdtaddr"
 760
 761 #define CONFIG_NFSBOOTCOMMAND                   \
 762         "setenv bootargs root=/dev/nfs rw "     \
 763         "nfsroot=$serverip:$rootpath "          \
 764         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 765         "console=$consoledev,$baudrate $othbootargs;"   \
 766         "tftp $loadaddr $bootfile;"             \
 767         "tftp $fdtaddr $fdtfile;"               \
 768         "bootm $loadaddr - $fdtaddr"
 769
 770 #define CONFIG_RAMBOOTCOMMAND                           \
 771         "setenv bootargs root=/dev/ram rw "             \
 772         "console=$consoledev,$baudrate $othbootargs;"   \
 773         "tftp $ramdiskaddr $ramdiskfile;"               \
 774         "tftp $loadaddr $bootfile;"                     \
 775         "tftp $fdtaddr $fdtfile;"                       \
 776         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 777
 778 #define CONFIG_BOOTCOMMAND              CONFIG_LINUX
 779
 780 #include <asm/fsl_secure_boot.h>
 781
 782 #endif  /* __CONFIG_H */