1 /*This file is subject to the terms and conditions of the GNU General Public
4 * Blackfin BF533/2.6 support : LG Soft India
5 * Updated : Ashutosh Singh / Jahid Khan : Rrap Software Pvt Ltd
6 * Updated : 1. SDRAM_KERNEL, SDRAM_DKENEL are added as initial cplb's
7 * shouldn't be victimized. cplbmgr.S search logic is corrected
8 * to findout the appropriate victim.
9 * 2. SDRAM_IGENERIC in dpdt_table is replaced with SDRAM_DGENERIC
14 #ifndef __ARCH_BFINNOMMU_CPLBTAB_H
15 #define __ARCH_BFINNOMMU_CPLBTAB_H
22 /* This table is configurable */
27 #define SDRAM_IGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID)
28 #define SDRAM_IKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
29 #define L1_IMEMORY (PAGE_SIZE_1MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
30 #define SDRAM_INON_CHBL (PAGE_SIZE_4MB | CPLB_USER_RD | CPLB_VALID)
32 /*Use the menuconfig cache policy here - CONFIG_BLKFIN_WT/CONFIG_BLKFIN_WB*/
34 #define ANOMALY_05000158 0x200
35 #ifdef CONFIG_BLKFIN_WB /*Write Back Policy */
36 #define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158)
37 #define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
38 #define SDRAM_DKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_USER_WR | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158)
39 #define L1_DMEMORY (PAGE_SIZE_4KB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158)
40 #define SDRAM_EBIU (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158)
42 #else /*Write Through */
43 #define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
44 #define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158)
45 #define SDRAM_DKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158)
46 #define L1_DMEMORY (PAGE_SIZE_4KB | CPLB_L1_CHBL | CPLB_L1_AOW | CPLB_WT | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
47 #define SDRAM_EBIU (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158)
51 .global _ipdt_table _ipdt_table:.byte4 0x00000000;
52 .byte4(SDRAM_IKERNEL); /*SDRAM_Page0 */
54 .byte4(SDRAM_IKERNEL); /*SDRAM_Page1 */
56 .byte4(SDRAM_IGENERIC); /*SDRAM_Page2 */
58 .byte4(SDRAM_IGENERIC); /*SDRAM_Page3 */
60 .byte4(SDRAM_IGENERIC); /*SDRAM_Page4 */
62 .byte4(SDRAM_IGENERIC); /*SDRAM_Page5 */
64 .byte4(SDRAM_IGENERIC); /*SDRAM_Page6 */
66 .byte4(SDRAM_IGENERIC); /*SDRAM_Page7 */
68 .byte4(SDRAM_IGENERIC); /*SDRAM_Page8 */
70 .byte4(SDRAM_IGENERIC); /*SDRAM_Page9 */
72 .byte4(SDRAM_IGENERIC); /*SDRAM_Page10 */
74 .byte4(SDRAM_IGENERIC); /*SDRAM_Page11 */
76 .byte4(SDRAM_IGENERIC); /*SDRAM_Page12 */
78 .byte4(SDRAM_IGENERIC); /*SDRAM_Page13 */
80 .byte4(SDRAM_IGENERIC); /*SDRAM_Page14 */
82 .byte4(SDRAM_IGENERIC); /*SDRAM_Page15 */
84 .byte4(SDRAM_EBIU); /* Async Memory Bank 2 (Secnd) */
86 .byte4 0xffffffff; /* end of section - termination */
89 * PAGE DESCRIPTOR TABLE
94 * Till here we are discussing about the static memory management model.
95 * However, the operating envoronments commonly define more CPLB
96 * descriptors to cover the entire addressable memory than will fit into
97 * the available on-chip 16 CPLB MMRs. When this happens, the below table
98 * will be used which will hold all the potentially required CPLB descriptors
100 * This is how Page descriptor Table is implemented in uClinux/Blackfin.
102 .global _dpdt_table _dpdt_table:.byte4 0x00000000;
103 .byte4(SDRAM_DKERNEL); /*SDRAM_Page0 */
105 .byte4(SDRAM_DKERNEL); /*SDRAM_Page1 */
107 .byte4(SDRAM_DGENERIC); /*SDRAM_Page2 */
109 .byte4(SDRAM_DGENERIC); /*SDRAM_Page3 */
111 .byte4(SDRAM_DGENERIC); /*SDRAM_Page4 */
113 .byte4(SDRAM_DGENERIC); /*SDRAM_Page5 */
115 .byte4(SDRAM_DGENERIC); /*SDRAM_Page6 */
117 .byte4(SDRAM_DGENERIC); /*SDRAM_Page7 */
119 .byte4(SDRAM_DGENERIC); /*SDRAM_Page8 */
121 .byte4(SDRAM_DGENERIC); /*SDRAM_Page9 */
123 .byte4(SDRAM_DGENERIC); /*SDRAM_Page10 */
125 .byte4(SDRAM_DGENERIC); /*SDRAM_Page11 */
127 .byte4(SDRAM_DGENERIC); /*SDRAM_Page12 */
129 .byte4(SDRAM_DGENERIC); /*SDRAM_Page13 */
131 .byte4(SDRAM_DGENERIC); /*SDRAM_Page14 */
133 .byte4(SDRAM_DGENERIC); /*SDRAM_Page15 */
135 .byte4(SDRAM_EBIU); /* Async Memory Bank 0 (Prim A) */
137 #if ((BFIN_CPU == ADSP_BF534) || (BFIN_CPU == ADSP_BF537))
155 #if ((BFIN_CPU == ADSP_BF534) || (BFIN_CPU == ADSP_BF537))
177 .byte4 0xffffffff; /*end of section - termination */
179 #ifdef CONFIG_CPLB_INFO
180 .global _ipdt_swapcount_table; /* swapin count first, then swapout count */
181 _ipdt_swapcount_table:
191 .byte4 0x00000000; /* 10 */
201 .byte4 0x00000000; /* 20 */
211 .byte4 0x00000000; /* 30 */
221 .byte4 0x00000000; /* 40 */
231 .byte4 0x00000000; /* 50 */
241 .byte4 0x00000000; /* 60 */
251 .byte4 0x00000000; /* 70 */
261 .byte4 0x00000000; /* 80 */
271 .byte4 0x00000000; /* 90 */
281 .byte4 0x00000000; /* 100 */
283 .global _dpdt_swapcount_table; /* swapin count first, then swapout count */
284 _dpdt_swapcount_table:
294 .byte4 0x00000000; /* 10 */
304 .byte4 0x00000000; /* 20 */
314 .byte4 0x00000000; /* 30 */
324 .byte4 0x00000000; /* 40 */
334 .byte4 0x00000000; /* 50 */
344 .byte4 0x00000000; /* 60 */
354 .byte4 0x00000000; /* 70 */
364 .byte4 0x00000000; /* 80 */
374 .byte4 0x00000000; /* 80 */
384 .byte4 0x00000000; /* 100 */
394 .byte4 0x00000000; /* 110 */
404 .byte4 0x00000000; /* 120 */
408 #endif /*__ARCH_BFINNOMMU_CPLBTAB_H*/